1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD$ 33 */ 34 35 /* 36 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 37 * the SK-984x series adapters, both single port and dual port. 38 * References: 39 * The XaQti XMAC II datasheet, http://www.xaqti.com 40 * The SysKonnect GEnesis manual, http://www.syskonnect.com 41 * 42 * Written by Bill Paul <wpaul@ee.columbia.edu> 43 * Department of Electrical Engineering 44 * Columbia University, New York City 45 */ 46 47 /* 48 * The SysKonnect gigabit ethernet adapters consist of two main 49 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 50 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 51 * components and a PHY while the GEnesis controller provides a PCI 52 * interface with DMA support. Each card may have between 512K and 53 * 2MB of SRAM on board depending on the configuration. 54 * 55 * The SysKonnect GEnesis controller can have either one or two XMAC 56 * chips connected to it, allowing single or dual port NIC configurations. 57 * SysKonnect has the distinction of being the only vendor on the market 58 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 59 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 60 * XMAC registers. This driver takes advantage of these features to allow 61 * both XMACs to operate as independent interfaces. 62 */ 63 64 #include "bpf.h" 65 66 #include <sys/param.h> 67 #include <sys/systm.h> 68 #include <sys/sockio.h> 69 #include <sys/mbuf.h> 70 #include <sys/malloc.h> 71 #include <sys/kernel.h> 72 #include <sys/socket.h> 73 #include <sys/queue.h> 74 75 #include <net/if.h> 76 #include <net/if_arp.h> 77 #include <net/ethernet.h> 78 #include <net/if_dl.h> 79 #include <net/if_media.h> 80 81 #if NBPF > 0 82 #include <net/bpf.h> 83 #endif 84 85 #include <vm/vm.h> /* for vtophys */ 86 #include <vm/pmap.h> /* for vtophys */ 87 #include <machine/clock.h> /* for DELAY */ 88 #include <machine/bus_pio.h> 89 #include <machine/bus_memio.h> 90 #include <machine/bus.h> 91 #include <machine/resource.h> 92 #include <sys/bus.h> 93 #include <sys/rman.h> 94 95 #include <pci/pcireg.h> 96 #include <pci/pcivar.h> 97 98 #define SK_USEIOSPACE 99 100 #include <pci/if_skreg.h> 101 #include <pci/xmaciireg.h> 102 103 #ifndef lint 104 static const char rcsid[] = 105 "$FreeBSD$"; 106 #endif 107 108 static struct sk_type sk_devs[] = { 109 { SK_VENDORID, SK_DEVICEID_GE, "SysKonnect Gigabit Ethernet" }, 110 { 0, 0, NULL } 111 }; 112 113 static unsigned long sk_count = 0; 114 static int sk_probe __P((device_t)); 115 static int sk_attach __P((device_t)); 116 static int sk_detach __P((device_t)); 117 static int sk_attach_xmac __P((struct sk_softc *, int)); 118 static void sk_intr __P((void *)); 119 static void sk_intr_xmac __P((struct sk_if_softc *)); 120 static void sk_rxeof __P((struct sk_if_softc *)); 121 static void sk_txeof __P((struct sk_if_softc *)); 122 static int sk_encap __P((struct sk_if_softc *, struct mbuf *, 123 u_int32_t *)); 124 static void sk_start __P((struct ifnet *)); 125 static int sk_ioctl __P((struct ifnet *, u_long, caddr_t)); 126 static void sk_init __P((void *)); 127 static void sk_init_xmac __P((struct sk_if_softc *)); 128 static void sk_stop __P((struct sk_if_softc *)); 129 static void sk_watchdog __P((struct ifnet *)); 130 static void sk_shutdown __P((device_t)); 131 static int sk_ifmedia_upd __P((struct ifnet *)); 132 static void sk_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 133 static void sk_reset __P((struct sk_softc *)); 134 static int sk_newbuf __P((struct sk_if_softc *, 135 struct sk_chain *, struct mbuf *)); 136 static int sk_alloc_jumbo_mem __P((struct sk_if_softc *)); 137 static void *sk_jalloc __P((struct sk_if_softc *)); 138 static void sk_jfree __P((caddr_t, u_int)); 139 static void sk_jref __P((caddr_t, u_int)); 140 static int sk_init_rx_ring __P((struct sk_if_softc *)); 141 static void sk_init_tx_ring __P((struct sk_if_softc *)); 142 #ifdef notdef 143 static u_int32_t sk_win_read_4 __P((struct sk_softc *, int)); 144 #endif 145 static u_int16_t sk_win_read_2 __P((struct sk_softc *, int)); 146 static u_int8_t sk_win_read_1 __P((struct sk_softc *, int)); 147 static void sk_win_write_4 __P((struct sk_softc *, int, u_int32_t)); 148 static void sk_win_write_2 __P((struct sk_softc *, int, u_int32_t)); 149 static void sk_win_write_1 __P((struct sk_softc *, int, u_int32_t)); 150 static u_int8_t sk_vpd_readbyte __P((struct sk_softc *, int)); 151 static void sk_vpd_read_res __P((struct sk_softc *, 152 struct vpd_res *, int)); 153 static void sk_vpd_read __P((struct sk_softc *)); 154 static u_int16_t sk_phy_readreg __P((struct sk_if_softc *, int)); 155 static void sk_phy_writereg __P((struct sk_if_softc *, int, u_int32_t)); 156 static u_int32_t sk_calchash __P((caddr_t)); 157 static void sk_setfilt __P((struct sk_if_softc *, caddr_t, int)); 158 static void sk_setmulti __P((struct sk_if_softc *)); 159 160 #ifdef SK_USEIOSPACE 161 #define SK_RES SYS_RES_IOPORT 162 #define SK_RID SK_PCI_LOIO 163 #else 164 #define SK_RES SYS_RES_MEMORY 165 #define SK_RID SK_PCI_LOMEM 166 #endif 167 168 static device_method_t sk_methods[] = { 169 /* Device interface */ 170 DEVMETHOD(device_probe, sk_probe), 171 DEVMETHOD(device_attach, sk_attach), 172 DEVMETHOD(device_detach, sk_detach), 173 DEVMETHOD(device_shutdown, sk_shutdown), 174 { 0, 0 } 175 }; 176 177 static driver_t sk_driver = { 178 "skc", 179 sk_methods, 180 sizeof(struct sk_softc) 181 }; 182 183 static devclass_t sk_devclass; 184 185 DRIVER_MODULE(sk, pci, sk_driver, sk_devclass, 0, 0); 186 187 #define SK_SETBIT(sc, reg, x) \ 188 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 189 190 #define SK_CLRBIT(sc, reg, x) \ 191 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 192 193 #define SK_WIN_SETBIT_4(sc, reg, x) \ 194 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x) 195 196 #define SK_WIN_CLRBIT_4(sc, reg, x) \ 197 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x) 198 199 #define SK_WIN_SETBIT_2(sc, reg, x) \ 200 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x) 201 202 #define SK_WIN_CLRBIT_2(sc, reg, x) \ 203 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x) 204 205 #ifdef notdef 206 static u_int32_t sk_win_read_4(sc, reg) 207 struct sk_softc *sc; 208 int reg; 209 { 210 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 211 return(CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg))); 212 } 213 #endif 214 215 static u_int16_t sk_win_read_2(sc, reg) 216 struct sk_softc *sc; 217 int reg; 218 { 219 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 220 return(CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg))); 221 } 222 223 static u_int8_t sk_win_read_1(sc, reg) 224 struct sk_softc *sc; 225 int reg; 226 { 227 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 228 return(CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg))); 229 } 230 231 static void sk_win_write_4(sc, reg, val) 232 struct sk_softc *sc; 233 int reg; 234 u_int32_t val; 235 { 236 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 237 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), val); 238 return; 239 } 240 241 static void sk_win_write_2(sc, reg, val) 242 struct sk_softc *sc; 243 int reg; 244 u_int32_t val; 245 { 246 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 247 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), (u_int32_t)val); 248 return; 249 } 250 251 static void sk_win_write_1(sc, reg, val) 252 struct sk_softc *sc; 253 int reg; 254 u_int32_t val; 255 { 256 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 257 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), val); 258 return; 259 } 260 261 /* 262 * The VPD EEPROM contains Vital Product Data, as suggested in 263 * the PCI 2.1 specification. The VPD data is separared into areas 264 * denoted by resource IDs. The SysKonnect VPD contains an ID string 265 * resource (the name of the adapter), a read-only area resource 266 * containing various key/data fields and a read/write area which 267 * can be used to store asset management information or log messages. 268 * We read the ID string and read-only into buffers attached to 269 * the controller softc structure for later use. At the moment, 270 * we only use the ID string during sk_attach(). 271 */ 272 static u_int8_t sk_vpd_readbyte(sc, addr) 273 struct sk_softc *sc; 274 int addr; 275 { 276 int i; 277 278 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 279 for (i = 0; i < SK_TIMEOUT; i++) { 280 DELAY(1); 281 if (sk_win_read_2(sc, 282 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 283 break; 284 } 285 286 if (i == SK_TIMEOUT) 287 return(0); 288 289 return(sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA))); 290 } 291 292 static void sk_vpd_read_res(sc, res, addr) 293 struct sk_softc *sc; 294 struct vpd_res *res; 295 int addr; 296 { 297 int i; 298 u_int8_t *ptr; 299 300 ptr = (u_int8_t *)res; 301 for (i = 0; i < sizeof(struct vpd_res); i++) 302 ptr[i] = sk_vpd_readbyte(sc, i + addr); 303 304 return; 305 } 306 307 static void sk_vpd_read(sc) 308 struct sk_softc *sc; 309 { 310 int pos = 0, i; 311 struct vpd_res res; 312 313 if (sc->sk_vpd_prodname != NULL) 314 free(sc->sk_vpd_prodname, M_DEVBUF); 315 if (sc->sk_vpd_readonly != NULL) 316 free(sc->sk_vpd_readonly, M_DEVBUF); 317 sc->sk_vpd_prodname = NULL; 318 sc->sk_vpd_readonly = NULL; 319 320 sk_vpd_read_res(sc, &res, pos); 321 322 if (res.vr_id != VPD_RES_ID) { 323 printf("skc%d: bad VPD resource id: expected %x got %x\n", 324 sc->sk_unit, VPD_RES_ID, res.vr_id); 325 return; 326 } 327 328 pos += sizeof(res); 329 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 330 for (i = 0; i < res.vr_len; i++) 331 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 332 sc->sk_vpd_prodname[i] = '\0'; 333 pos += i; 334 335 sk_vpd_read_res(sc, &res, pos); 336 337 if (res.vr_id != VPD_RES_READ) { 338 printf("skc%d: bad VPD resource id: expected %x got %x\n", 339 sc->sk_unit, VPD_RES_READ, res.vr_id); 340 return; 341 } 342 343 pos += sizeof(res); 344 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 345 for (i = 0; i < res.vr_len + 1; i++) 346 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 347 348 return; 349 } 350 351 static u_int16_t sk_phy_readreg(sc_if, reg) 352 struct sk_if_softc *sc_if; 353 int reg; 354 { 355 int i; 356 357 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg); 358 for (i = 0; i < SK_TIMEOUT; i++) { 359 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 360 break; 361 } 362 363 if (i == SK_TIMEOUT) { 364 printf("sk%d: phy failed to come ready\n", sc_if->sk_unit); 365 return(0); 366 } 367 368 return(SK_XM_READ_2(sc_if, XM_PHY_DATA)); 369 } 370 371 static void sk_phy_writereg(sc_if, reg, val) 372 struct sk_if_softc *sc_if; 373 int reg; 374 u_int32_t val; 375 { 376 int i; 377 378 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg); 379 for (i = 0; i < SK_TIMEOUT; i++) { 380 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 381 break; 382 } 383 384 if (i == SK_TIMEOUT) { 385 printf("sk%d: phy failed to come ready\n", sc_if->sk_unit); 386 return; 387 } 388 389 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 390 for (i = 0; i < SK_TIMEOUT; i++) { 391 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 392 break; 393 } 394 395 if (i == SK_TIMEOUT) 396 printf("sk%d: phy write timed out\n", sc_if->sk_unit); 397 398 return; 399 } 400 401 #define SK_POLY 0xEDB88320 402 #define SK_BITS 6 403 404 static u_int32_t sk_calchash(addr) 405 caddr_t addr; 406 { 407 u_int32_t idx, bit, data, crc; 408 409 /* Compute CRC for the address value. */ 410 crc = 0xFFFFFFFF; /* initial value */ 411 412 for (idx = 0; idx < 6; idx++) { 413 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 414 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? SK_POLY : 0); 415 } 416 417 return (~crc & ((1 << SK_BITS) - 1)); 418 } 419 420 static void sk_setfilt(sc_if, addr, slot) 421 struct sk_if_softc *sc_if; 422 caddr_t addr; 423 int slot; 424 { 425 int base; 426 427 base = XM_RXFILT_ENTRY(slot); 428 429 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 430 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 431 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 432 433 return; 434 } 435 436 static void sk_setmulti(sc_if) 437 struct sk_if_softc *sc_if; 438 { 439 struct ifnet *ifp; 440 u_int32_t hashes[2] = { 0, 0 }; 441 int h, i; 442 struct ifmultiaddr *ifma; 443 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 444 445 ifp = &sc_if->arpcom.ac_if; 446 447 /* First, zot all the existing filters. */ 448 for (i = 1; i < XM_RXFILT_MAX; i++) 449 sk_setfilt(sc_if, (caddr_t)&dummy, i); 450 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 451 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 452 453 /* Now program new ones. */ 454 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 455 hashes[0] = 0xFFFFFFFF; 456 hashes[1] = 0xFFFFFFFF; 457 } else { 458 i = 1; 459 /* First find the tail of the list. */ 460 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 461 ifma = ifma->ifma_link.le_next) { 462 if (ifma->ifma_link.le_next == NULL) 463 break; 464 } 465 /* Now traverse the list backwards. */ 466 for (; ifma != NULL && ifma != (void *)&ifp->if_multiaddrs; 467 ifma = (struct ifmultiaddr *)ifma->ifma_link.le_prev) { 468 if (ifma->ifma_addr->sa_family != AF_LINK) 469 continue; 470 /* 471 * Program the first XM_RXFILT_MAX multicast groups 472 * into the perfect filter. For all others, 473 * use the hash table. 474 */ 475 if (i < XM_RXFILT_MAX) { 476 sk_setfilt(sc_if, 477 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i); 478 i++; 479 continue; 480 } 481 482 h = sk_calchash( 483 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 484 if (h < 32) 485 hashes[0] |= (1 << h); 486 else 487 hashes[1] |= (1 << (h - 32)); 488 } 489 } 490 491 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 492 XM_MODE_RX_USE_PERFECT); 493 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 494 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 495 496 return; 497 } 498 499 static int sk_init_rx_ring(sc_if) 500 struct sk_if_softc *sc_if; 501 { 502 struct sk_chain_data *cd; 503 struct sk_ring_data *rd; 504 int i; 505 506 cd = &sc_if->sk_cdata; 507 rd = sc_if->sk_rdata; 508 509 bzero((char *)rd->sk_rx_ring, 510 sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 511 512 for (i = 0; i < SK_RX_RING_CNT; i++) { 513 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 514 if (sk_newbuf(sc_if, &cd->sk_rx_chain[i], NULL) == ENOBUFS) 515 return(ENOBUFS); 516 if (i == (SK_RX_RING_CNT - 1)) { 517 cd->sk_rx_chain[i].sk_next = 518 &cd->sk_rx_chain[0]; 519 rd->sk_rx_ring[i].sk_next = 520 vtophys(&rd->sk_rx_ring[0]); 521 } else { 522 cd->sk_rx_chain[i].sk_next = 523 &cd->sk_rx_chain[i + 1]; 524 rd->sk_rx_ring[i].sk_next = 525 vtophys(&rd->sk_rx_ring[i + 1]); 526 } 527 } 528 529 sc_if->sk_cdata.sk_rx_prod = 0; 530 sc_if->sk_cdata.sk_rx_cons = 0; 531 532 return(0); 533 } 534 535 static void sk_init_tx_ring(sc_if) 536 struct sk_if_softc *sc_if; 537 { 538 struct sk_chain_data *cd; 539 struct sk_ring_data *rd; 540 int i; 541 542 cd = &sc_if->sk_cdata; 543 rd = sc_if->sk_rdata; 544 545 bzero((char *)sc_if->sk_rdata->sk_tx_ring, 546 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 547 548 for (i = 0; i < SK_TX_RING_CNT; i++) { 549 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 550 if (i == (SK_TX_RING_CNT - 1)) { 551 cd->sk_tx_chain[i].sk_next = 552 &cd->sk_tx_chain[0]; 553 rd->sk_tx_ring[i].sk_next = 554 vtophys(&rd->sk_tx_ring[0]); 555 } else { 556 cd->sk_tx_chain[i].sk_next = 557 &cd->sk_tx_chain[i + 1]; 558 rd->sk_tx_ring[i].sk_next = 559 vtophys(&rd->sk_tx_ring[i + 1]); 560 } 561 } 562 563 sc_if->sk_cdata.sk_tx_prod = 0; 564 sc_if->sk_cdata.sk_tx_cons = 0; 565 sc_if->sk_cdata.sk_tx_cnt = 0; 566 567 return; 568 } 569 570 static int sk_newbuf(sc_if, c, m) 571 struct sk_if_softc *sc_if; 572 struct sk_chain *c; 573 struct mbuf *m; 574 { 575 struct mbuf *m_new = NULL; 576 struct sk_rx_desc *r; 577 578 if (m == NULL) { 579 caddr_t *buf = NULL; 580 581 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 582 if (m_new == NULL) { 583 printf("sk%d: no memory for rx list -- " 584 "packet dropped!\n", sc_if->sk_unit); 585 return(ENOBUFS); 586 } 587 588 /* Allocate the jumbo buffer */ 589 buf = sk_jalloc(sc_if); 590 if (buf == NULL) { 591 m_freem(m_new); 592 #ifdef SK_VERBOSE 593 printf("sk%d: jumbo allocation failed " 594 "-- packet dropped!\n", sc_if->sk_unit); 595 #endif 596 return(ENOBUFS); 597 } 598 599 /* Attach the buffer to the mbuf */ 600 m_new->m_data = m_new->m_ext.ext_buf = (void *)buf; 601 m_new->m_flags |= M_EXT; 602 m_new->m_ext.ext_size = m_new->m_pkthdr.len = 603 m_new->m_len = SK_MCLBYTES; 604 m_new->m_ext.ext_free = sk_jfree; 605 m_new->m_ext.ext_ref = sk_jref; 606 } else { 607 /* 608 * We're re-using a previously allocated mbuf; 609 * be sure to re-init pointers and lengths to 610 * default values. 611 */ 612 m_new = m; 613 m_new->m_len = m_new->m_pkthdr.len = SK_MCLBYTES; 614 m_new->m_data = m_new->m_ext.ext_buf; 615 } 616 617 /* 618 * Adjust alignment so packet payload begins on a 619 * longword boundary. Mandatory for Alpha, useful on 620 * x86 too. 621 */ 622 m_adj(m_new, ETHER_ALIGN); 623 624 r = c->sk_desc; 625 c->sk_mbuf = m_new; 626 r->sk_data_lo = vtophys(mtod(m_new, caddr_t)); 627 r->sk_ctl = m_new->m_len | SK_RXSTAT; 628 629 return(0); 630 } 631 632 /* 633 * Allocate jumbo buffer storage. The SysKonnect adapters support 634 * "jumbograms" (9K frames), although SysKonnect doesn't currently 635 * use them in their drivers. In order for us to use them, we need 636 * large 9K receive buffers, however standard mbuf clusters are only 637 * 2048 bytes in size. Consequently, we need to allocate and manage 638 * our own jumbo buffer pool. Fortunately, this does not require an 639 * excessive amount of additional code. 640 */ 641 static int sk_alloc_jumbo_mem(sc_if) 642 struct sk_if_softc *sc_if; 643 { 644 caddr_t ptr; 645 register int i; 646 struct sk_jpool_entry *entry; 647 648 /* Grab a big chunk o' storage. */ 649 sc_if->sk_cdata.sk_jumbo_buf = contigmalloc(SK_JMEM, M_DEVBUF, 650 M_NOWAIT, 0x100000, 0xffffffff, PAGE_SIZE, 0); 651 652 if (sc_if->sk_cdata.sk_jumbo_buf == NULL) { 653 printf("sk%d: no memory for jumbo buffers!\n", sc_if->sk_unit); 654 return(ENOBUFS); 655 } 656 657 SLIST_INIT(&sc_if->sk_jfree_listhead); 658 SLIST_INIT(&sc_if->sk_jinuse_listhead); 659 660 /* 661 * Now divide it up into 9K pieces and save the addresses 662 * in an array. Note that we play an evil trick here by using 663 * the first few bytes in the buffer to hold the the address 664 * of the softc structure for this interface. This is because 665 * sk_jfree() needs it, but it is called by the mbuf management 666 * code which will not pass it to us explicitly. 667 */ 668 ptr = sc_if->sk_cdata.sk_jumbo_buf; 669 for (i = 0; i < SK_JSLOTS; i++) { 670 u_int64_t **aptr; 671 aptr = (u_int64_t **)ptr; 672 aptr[0] = (u_int64_t *)sc_if; 673 ptr += sizeof(u_int64_t); 674 sc_if->sk_cdata.sk_jslots[i].sk_buf = ptr; 675 sc_if->sk_cdata.sk_jslots[i].sk_inuse = 0; 676 ptr += SK_MCLBYTES; 677 entry = malloc(sizeof(struct sk_jpool_entry), 678 M_DEVBUF, M_NOWAIT); 679 if (entry == NULL) { 680 free(sc_if->sk_cdata.sk_jumbo_buf, M_DEVBUF); 681 sc_if->sk_cdata.sk_jumbo_buf = NULL; 682 printf("sk%d: no memory for jumbo " 683 "buffer queue!\n", sc_if->sk_unit); 684 return(ENOBUFS); 685 } 686 entry->slot = i; 687 SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 688 entry, jpool_entries); 689 } 690 691 return(0); 692 } 693 694 /* 695 * Allocate a jumbo buffer. 696 */ 697 static void *sk_jalloc(sc_if) 698 struct sk_if_softc *sc_if; 699 { 700 struct sk_jpool_entry *entry; 701 702 entry = SLIST_FIRST(&sc_if->sk_jfree_listhead); 703 704 if (entry == NULL) { 705 #ifdef SK_VERBOSE 706 printf("sk%d: no free jumbo buffers\n", sc_if->sk_unit); 707 #endif 708 return(NULL); 709 } 710 711 SLIST_REMOVE_HEAD(&sc_if->sk_jfree_listhead, jpool_entries); 712 SLIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 713 sc_if->sk_cdata.sk_jslots[entry->slot].sk_inuse = 1; 714 return(sc_if->sk_cdata.sk_jslots[entry->slot].sk_buf); 715 } 716 717 /* 718 * Adjust usage count on a jumbo buffer. In general this doesn't 719 * get used much because our jumbo buffers don't get passed around 720 * a lot, but it's implemented for correctness. 721 */ 722 static void sk_jref(buf, size) 723 caddr_t buf; 724 u_int size; 725 { 726 struct sk_if_softc *sc_if; 727 u_int64_t **aptr; 728 register int i; 729 730 /* Extract the softc struct pointer. */ 731 aptr = (u_int64_t **)(buf - sizeof(u_int64_t)); 732 sc_if = (struct sk_if_softc *)(aptr[0]); 733 734 if (sc_if == NULL) 735 panic("sk_jref: can't find softc pointer!"); 736 737 if (size != SK_MCLBYTES) 738 panic("sk_jref: adjusting refcount of buf of wrong size!"); 739 740 /* calculate the slot this buffer belongs to */ 741 742 i = ((vm_offset_t)aptr 743 - (vm_offset_t)sc_if->sk_cdata.sk_jumbo_buf) / SK_JLEN; 744 745 if ((i < 0) || (i >= SK_JSLOTS)) 746 panic("sk_jref: asked to reference buffer " 747 "that we don't manage!"); 748 else if (sc_if->sk_cdata.sk_jslots[i].sk_inuse == 0) 749 panic("sk_jref: buffer already free!"); 750 else 751 sc_if->sk_cdata.sk_jslots[i].sk_inuse++; 752 753 return; 754 } 755 756 /* 757 * Release a jumbo buffer. 758 */ 759 static void sk_jfree(buf, size) 760 caddr_t buf; 761 u_int size; 762 { 763 struct sk_if_softc *sc_if; 764 u_int64_t **aptr; 765 int i; 766 struct sk_jpool_entry *entry; 767 768 /* Extract the softc struct pointer. */ 769 aptr = (u_int64_t **)(buf - sizeof(u_int64_t)); 770 sc_if = (struct sk_if_softc *)(aptr[0]); 771 772 if (sc_if == NULL) 773 panic("sk_jfree: can't find softc pointer!"); 774 775 if (size != SK_MCLBYTES) 776 panic("sk_jfree: freeing buffer of wrong size!"); 777 778 /* calculate the slot this buffer belongs to */ 779 780 i = ((vm_offset_t)aptr 781 - (vm_offset_t)sc_if->sk_cdata.sk_jumbo_buf) / SK_JLEN; 782 783 if ((i < 0) || (i >= SK_JSLOTS)) 784 panic("sk_jfree: asked to free buffer that we don't manage!"); 785 else if (sc_if->sk_cdata.sk_jslots[i].sk_inuse == 0) 786 panic("sk_jfree: buffer already free!"); 787 else { 788 sc_if->sk_cdata.sk_jslots[i].sk_inuse--; 789 if(sc_if->sk_cdata.sk_jslots[i].sk_inuse == 0) { 790 entry = SLIST_FIRST(&sc_if->sk_jinuse_listhead); 791 if (entry == NULL) 792 panic("sk_jfree: buffer not in use!"); 793 entry->slot = i; 794 SLIST_REMOVE_HEAD(&sc_if->sk_jinuse_listhead, 795 jpool_entries); 796 SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 797 entry, jpool_entries); 798 } 799 } 800 801 return; 802 } 803 804 /* 805 * Set media options. 806 */ 807 static int sk_ifmedia_upd(ifp) 808 struct ifnet *ifp; 809 { 810 struct sk_if_softc *sc_if; 811 struct ifmedia *ifm; 812 813 sc_if = ifp->if_softc; 814 ifm = &sc_if->ifmedia; 815 816 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 817 return(EINVAL); 818 819 switch(IFM_SUBTYPE(ifm->ifm_media)) { 820 case IFM_AUTO: 821 sk_phy_writereg(sc_if, XM_PHY_BMCR, 822 XM_BMCR_RENEGOTIATE|XM_BMCR_AUTONEGENBL); 823 break; 824 case IFM_1000_LX: 825 case IFM_1000_SX: 826 case IFM_1000_CX: 827 case IFM_1000_TX: 828 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 829 sk_phy_writereg(sc_if, XM_PHY_BMCR, XM_BMCR_DUPLEX); 830 else 831 sk_phy_writereg(sc_if, XM_PHY_BMCR, 0); 832 break; 833 default: 834 printf("sk%d: invalid media selected\n", sc_if->sk_unit); 835 return(EINVAL); 836 break; 837 } 838 839 return(0); 840 } 841 842 /* 843 * Report current media status. 844 */ 845 static void sk_ifmedia_sts(ifp, ifmr) 846 struct ifnet *ifp; 847 struct ifmediareq *ifmr; 848 { 849 struct sk_softc *sc; 850 struct sk_if_softc *sc_if; 851 u_int16_t bmsr, extsts; 852 853 sc_if = ifp->if_softc; 854 sc = sc_if->sk_softc; 855 856 ifmr->ifm_status = IFM_AVALID; 857 ifmr->ifm_active = IFM_ETHER; 858 859 bmsr = sk_phy_readreg(sc_if, XM_PHY_BMSR); 860 extsts = sk_phy_readreg(sc_if, XM_PHY_EXTSTS); 861 862 if (!(bmsr & XM_BMSR_LINKSTAT)) 863 return; 864 865 ifmr->ifm_status |= IFM_ACTIVE; 866 ifmr->ifm_active |= sc->sk_pmd;; 867 if (extsts & XM_EXTSTS_FULLDUPLEX) 868 ifmr->ifm_active |= IFM_FDX; 869 else 870 ifmr->ifm_active |= IFM_HDX; 871 872 return; 873 } 874 875 static int sk_ioctl(ifp, command, data) 876 struct ifnet *ifp; 877 u_long command; 878 caddr_t data; 879 { 880 struct sk_if_softc *sc_if = ifp->if_softc; 881 struct ifreq *ifr = (struct ifreq *) data; 882 int s, error = 0; 883 884 s = splimp(); 885 886 switch(command) { 887 case SIOCSIFADDR: 888 case SIOCGIFADDR: 889 error = ether_ioctl(ifp, command, data); 890 break; 891 case SIOCSIFMTU: 892 if (ifr->ifr_mtu > SK_JUMBO_MTU) 893 error = EINVAL; 894 else { 895 ifp->if_mtu = ifr->ifr_mtu; 896 sk_init(sc_if); 897 } 898 break; 899 case SIOCSIFFLAGS: 900 if (ifp->if_flags & IFF_UP) { 901 if (ifp->if_flags & IFF_RUNNING && 902 ifp->if_flags & IFF_PROMISC && 903 !(sc_if->sk_if_flags & IFF_PROMISC)) { 904 SK_XM_SETBIT_4(sc_if, XM_MODE, 905 XM_MODE_RX_PROMISC); 906 sk_setmulti(sc_if); 907 } else if (ifp->if_flags & IFF_RUNNING && 908 !(ifp->if_flags & IFF_PROMISC) && 909 sc_if->sk_if_flags & IFF_PROMISC) { 910 SK_XM_CLRBIT_4(sc_if, XM_MODE, 911 XM_MODE_RX_PROMISC); 912 sk_setmulti(sc_if); 913 } else 914 sk_init(sc_if); 915 } else { 916 if (ifp->if_flags & IFF_RUNNING) 917 sk_stop(sc_if); 918 } 919 sc_if->sk_if_flags = ifp->if_flags; 920 error = 0; 921 break; 922 case SIOCADDMULTI: 923 case SIOCDELMULTI: 924 sk_setmulti(sc_if); 925 error = 0; 926 break; 927 case SIOCGIFMEDIA: 928 case SIOCSIFMEDIA: 929 error = ifmedia_ioctl(ifp, ifr, &sc_if->ifmedia, command); 930 break; 931 default: 932 error = EINVAL; 933 break; 934 } 935 936 (void)splx(s); 937 938 return(error); 939 } 940 941 /* 942 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 943 * IDs against our list and return a device name if we find a match. 944 */ 945 static int sk_probe(dev) 946 device_t dev; 947 { 948 struct sk_type *t; 949 950 t = sk_devs; 951 952 while(t->sk_name != NULL) { 953 if ((pci_get_vendor(dev) == t->sk_vid) && 954 (pci_get_device(dev) == t->sk_did)) { 955 device_set_desc(dev, t->sk_name); 956 return(0); 957 } 958 t++; 959 } 960 961 return(ENXIO); 962 } 963 964 /* 965 * Force the GEnesis into reset, then bring it out of reset. 966 */ 967 static void sk_reset(sc) 968 struct sk_softc *sc; 969 { 970 CSR_WRITE_4(sc, SK_CSR, SK_CSR_SW_RESET); 971 CSR_WRITE_4(sc, SK_CSR, SK_CSR_MASTER_RESET); 972 DELAY(1000); 973 CSR_WRITE_4(sc, SK_CSR, SK_CSR_SW_UNRESET); 974 CSR_WRITE_4(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 975 976 /* Configure packet arbiter */ 977 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 978 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 979 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 980 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 981 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 982 983 /* Enable RAM interface */ 984 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 985 986 /* 987 * Configure interrupt moderation. The moderation timer 988 * defers interrupts specified in the interrupt moderation 989 * timer mask based on the timeout specified in the interrupt 990 * moderation timer init register. Each bit in the timer 991 * register represents 18.825ns, so to specify a timeout in 992 * microseconds, we have to multiply by 54. 993 */ 994 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(200)); 995 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 996 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 997 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 998 999 return; 1000 } 1001 1002 /* 1003 * Each XMAC chip is attached as a separate logical IP interface. 1004 * Single port cards will have only one logical interface of course. 1005 */ 1006 static int sk_attach_xmac(sc, port) 1007 struct sk_softc *sc; 1008 int port; 1009 { 1010 struct sk_if_softc *sc_if; 1011 struct ifnet *ifp; 1012 int i; 1013 1014 if (sc == NULL) 1015 return(EINVAL); 1016 1017 if (port != SK_PORT_A && port != SK_PORT_B) 1018 return(EINVAL); 1019 1020 sc_if = malloc(sizeof(struct sk_if_softc), M_DEVBUF, M_NOWAIT); 1021 if (sc_if == NULL) { 1022 printf("sk%d: no memory for interface softc!\n", sc->sk_unit); 1023 return(ENOMEM); 1024 } 1025 bzero((char *)sc_if, sizeof(struct sk_if_softc)); 1026 1027 sc_if->sk_unit = sk_count; 1028 sc_if->sk_port = port; 1029 sk_count++; 1030 sc_if->sk_softc = sc; 1031 sc->sk_if[port] = sc_if; 1032 if (port == SK_PORT_A) 1033 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1034 if (port == SK_PORT_B) 1035 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1036 1037 /* 1038 * Get station address for this interface. Note that 1039 * dual port cards actually come with three station 1040 * addresses: one for each port, plus an extra. The 1041 * extra one is used by the SysKonnect driver software 1042 * as a 'virtual' station address for when both ports 1043 * are operating in failover mode. Currently we don't 1044 * use this extra address. 1045 */ 1046 for (i = 0; i < ETHER_ADDR_LEN; i++) 1047 sc_if->arpcom.ac_enaddr[i] = 1048 sk_win_read_1(sc, SK_MAC0_0 + (port * 8) + i); 1049 1050 printf("sk%d: <XaQti Corp. XMAC II> at skc%d port %d\n", 1051 sc_if->sk_unit, sc->sk_unit, port); 1052 1053 printf("sk%d: Ethernet address: %6D\n", 1054 sc_if->sk_unit, sc_if->arpcom.ac_enaddr, ":"); 1055 1056 /* 1057 * Set up RAM buffer addresses. The NIC will have a certain 1058 * amount of SRAM on it, somewhere between 512K and 2MB. We 1059 * need to divide this up a) between the transmitter and 1060 * receiver and b) between the two XMACs, if this is a 1061 * dual port NIC. Our algotithm is to divide up the memory 1062 * evenly so that everyone gets a fair share. 1063 */ 1064 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1065 u_int32_t chunk, val; 1066 1067 chunk = sc->sk_ramsize / 2; 1068 val = sc->sk_rboff / sizeof(u_int64_t); 1069 sc_if->sk_rx_ramstart = val; 1070 val += (chunk / sizeof(u_int64_t)); 1071 sc_if->sk_rx_ramend = val - 1; 1072 sc_if->sk_tx_ramstart = val; 1073 val += (chunk / sizeof(u_int64_t)); 1074 sc_if->sk_tx_ramend = val - 1; 1075 } else { 1076 u_int32_t chunk, val; 1077 1078 chunk = sc->sk_ramsize / 4; 1079 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1080 sizeof(u_int64_t); 1081 sc_if->sk_rx_ramstart = val; 1082 val += (chunk / sizeof(u_int64_t)); 1083 sc_if->sk_rx_ramend = val - 1; 1084 sc_if->sk_tx_ramstart = val; 1085 val += (chunk / sizeof(u_int64_t)); 1086 sc_if->sk_tx_ramend = val - 1; 1087 } 1088 1089 /* Allocate the descriptor queues. */ 1090 sc_if->sk_rdata = contigmalloc(sizeof(struct sk_ring_data), M_DEVBUF, 1091 M_NOWAIT, 0x100000, 0xffffffff, PAGE_SIZE, 0); 1092 1093 if (sc_if->sk_rdata == NULL) { 1094 printf("sk%d: no memory for list buffers!\n", sc_if->sk_unit); 1095 free(sc_if, M_DEVBUF); 1096 sc->sk_if[port] = NULL; 1097 return(ENOMEM); 1098 } 1099 1100 bzero(sc_if->sk_rdata, sizeof(struct sk_ring_data)); 1101 1102 /* Try to allocate memory for jumbo buffers. */ 1103 if (sk_alloc_jumbo_mem(sc_if)) { 1104 printf("sk%d: jumbo buffer allocation failed\n", 1105 sc_if->sk_unit); 1106 free(sc_if->sk_rdata, M_DEVBUF); 1107 free(sc_if, M_DEVBUF); 1108 sc->sk_if[port] = NULL; 1109 return(ENOMEM); 1110 } 1111 1112 ifp = &sc_if->arpcom.ac_if; 1113 ifp->if_softc = sc_if; 1114 ifp->if_unit = sc_if->sk_unit; 1115 ifp->if_name = "sk"; 1116 ifp->if_mtu = ETHERMTU; 1117 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1118 ifp->if_ioctl = sk_ioctl; 1119 ifp->if_output = ether_output; 1120 ifp->if_start = sk_start; 1121 ifp->if_watchdog = sk_watchdog; 1122 ifp->if_init = sk_init; 1123 ifp->if_baudrate = 1000000000; 1124 ifp->if_snd.ifq_maxlen = SK_TX_RING_CNT - 1; 1125 1126 /* 1127 * Do ifmedia setup. 1128 */ 1129 ifmedia_init(&sc_if->ifmedia, 0, sk_ifmedia_upd, sk_ifmedia_sts); 1130 ifmedia_add(&sc_if->ifmedia, IFM_ETHER|sc->sk_pmd, 0, NULL); 1131 ifmedia_add(&sc_if->ifmedia, IFM_ETHER|sc->sk_pmd|IFM_FDX, 0, NULL); 1132 ifmedia_add(&sc_if->ifmedia, IFM_ETHER|sc->sk_pmd|IFM_HDX, 0, NULL); 1133 ifmedia_add(&sc_if->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 1134 ifmedia_set(&sc_if->ifmedia, IFM_ETHER|IFM_AUTO); 1135 1136 /* 1137 * Call MI attach routines. 1138 */ 1139 if_attach(ifp); 1140 ether_ifattach(ifp); 1141 1142 #if NBPF > 0 1143 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 1144 #endif 1145 1146 return(0); 1147 } 1148 1149 /* 1150 * Attach the interface. Allocate softc structures, do ifmedia 1151 * setup and ethernet/BPF attach. 1152 */ 1153 static int sk_attach(dev) 1154 device_t dev; 1155 { 1156 int s; 1157 u_int32_t command; 1158 struct sk_softc *sc; 1159 int unit, error = 0, rid; 1160 1161 s = splimp(); 1162 1163 sc = device_get_softc(dev); 1164 unit = device_get_unit(dev); 1165 bzero(sc, sizeof(struct sk_softc)); 1166 1167 /* 1168 * Handle power management nonsense. 1169 */ 1170 command = pci_read_config(dev, SK_PCI_CAPID, 4) & 0x000000FF; 1171 if (command == 0x01) { 1172 1173 command = pci_read_config(dev, SK_PCI_PWRMGMTCTRL, 4); 1174 if (command & SK_PSTATE_MASK) { 1175 u_int32_t iobase, membase, irq; 1176 1177 /* Save important PCI config data. */ 1178 iobase = pci_read_config(dev, SK_PCI_LOIO, 4); 1179 membase = pci_read_config(dev, SK_PCI_LOMEM, 4); 1180 irq = pci_read_config(dev, SK_PCI_INTLINE, 4); 1181 1182 /* Reset the power state. */ 1183 printf("skc%d: chip is in D%d power mode " 1184 "-- setting to D0\n", unit, command & SK_PSTATE_MASK); 1185 command &= 0xFFFFFFFC; 1186 pci_write_config(dev, SK_PCI_PWRMGMTCTRL, command, 4); 1187 1188 /* Restore PCI config data. */ 1189 pci_write_config(dev, SK_PCI_LOIO, iobase, 4); 1190 pci_write_config(dev, SK_PCI_LOMEM, membase, 4); 1191 pci_write_config(dev, SK_PCI_INTLINE, irq, 4); 1192 } 1193 } 1194 1195 /* 1196 * Map control/status registers. 1197 */ 1198 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 1199 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1200 pci_write_config(dev, PCI_COMMAND_STATUS_REG, command, 4); 1201 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 1202 1203 #ifdef SK_USEIOSPACE 1204 if (!(command & PCIM_CMD_PORTEN)) { 1205 printf("skc%d: failed to enable I/O ports!\n", unit); 1206 error = ENXIO; 1207 goto fail; 1208 } 1209 #else 1210 if (!(command & PCIM_CMD_MEMEN)) { 1211 printf("skc%d: failed to enable memory mapping!\n", unit); 1212 error = ENXIO; 1213 goto fail; 1214 } 1215 #endif 1216 1217 rid = SK_RID; 1218 sc->sk_res = bus_alloc_resource(dev, SK_RES, &rid, 1219 0, ~0, 1, RF_ACTIVE); 1220 1221 if (sc->sk_res == NULL) { 1222 printf("sk%d: couldn't map ports/memory\n", unit); 1223 error = ENXIO; 1224 goto fail; 1225 } 1226 1227 sc->sk_btag = rman_get_bustag(sc->sk_res); 1228 sc->sk_bhandle = rman_get_bushandle(sc->sk_res); 1229 1230 /* Allocate interrupt */ 1231 rid = 0; 1232 sc->sk_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1233 RF_SHAREABLE | RF_ACTIVE); 1234 1235 if (sc->sk_irq == NULL) { 1236 printf("skc%d: couldn't map interrupt\n", unit); 1237 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res); 1238 error = ENXIO; 1239 goto fail; 1240 } 1241 1242 error = bus_setup_intr(dev, sc->sk_irq, INTR_TYPE_NET, 1243 sk_intr, sc, &sc->sk_intrhand); 1244 1245 if (error) { 1246 printf("skc%d: couldn't set up irq\n", unit); 1247 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res); 1248 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_res); 1249 goto fail; 1250 } 1251 1252 /* Reset the adapter. */ 1253 sk_reset(sc); 1254 1255 sc->sk_unit = unit; 1256 1257 /* Read and save vital product data from EEPROM. */ 1258 sk_vpd_read(sc); 1259 1260 /* Read and save RAM size and RAMbuffer offset */ 1261 switch(sk_win_read_1(sc, SK_EPROM0)) { 1262 case SK_RAMSIZE_512K_64: 1263 sc->sk_ramsize = 0x80000; 1264 sc->sk_rboff = SK_RBOFF_0; 1265 break; 1266 case SK_RAMSIZE_1024K_64: 1267 sc->sk_ramsize = 0x100000; 1268 sc->sk_rboff = SK_RBOFF_80000; 1269 break; 1270 case SK_RAMSIZE_1024K_128: 1271 sc->sk_ramsize = 0x100000; 1272 sc->sk_rboff = SK_RBOFF_0; 1273 break; 1274 case SK_RAMSIZE_2048K_128: 1275 sc->sk_ramsize = 0x200000; 1276 sc->sk_rboff = SK_RBOFF_0; 1277 break; 1278 default: 1279 printf("skc%d: unknown ram size: %d\n", 1280 sc->sk_unit, sk_win_read_1(sc, SK_EPROM0)); 1281 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand); 1282 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq); 1283 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res); 1284 error = ENXIO; 1285 goto fail; 1286 break; 1287 } 1288 1289 /* Read and save physical media type */ 1290 switch(sk_win_read_1(sc, SK_PMDTYPE)) { 1291 case SK_PMD_1000BASESX: 1292 sc->sk_pmd = IFM_1000_SX; 1293 break; 1294 case SK_PMD_1000BASELX: 1295 sc->sk_pmd = IFM_1000_LX; 1296 break; 1297 case SK_PMD_1000BASECX: 1298 sc->sk_pmd = IFM_1000_CX; 1299 break; 1300 case SK_PMD_1000BASETX: 1301 sc->sk_pmd = IFM_1000_TX; 1302 break; 1303 default: 1304 printf("skc%d: unknown media type: 0x%x\n", 1305 sc->sk_unit, sk_win_read_1(sc, SK_PMDTYPE)); 1306 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand); 1307 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq); 1308 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res); 1309 error = ENXIO; 1310 goto fail; 1311 } 1312 1313 /* Announce the product name. */ 1314 printf("skc%d: %s\n", sc->sk_unit, sc->sk_vpd_prodname); 1315 1316 sk_attach_xmac(sc, SK_PORT_A); 1317 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) 1318 sk_attach_xmac(sc, SK_PORT_B); 1319 1320 /* Turn on the 'driver is loaded' LED. */ 1321 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1322 1323 fail: 1324 splx(s); 1325 return(error); 1326 } 1327 1328 static int sk_detach(dev) 1329 device_t dev; 1330 { 1331 struct sk_softc *sc; 1332 struct sk_if_softc *sc_if0 = NULL, *sc_if1 = NULL; 1333 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 1334 int s; 1335 1336 s = splimp(); 1337 1338 sc = device_get_softc(dev); 1339 sc_if0 = sc->sk_if[SK_PORT_A]; 1340 ifp0 = &sc_if0->arpcom.ac_if; 1341 sk_stop(sc_if0); 1342 if_detach(ifp0); 1343 free(sc_if0->sk_cdata.sk_jumbo_buf, M_DEVBUF); 1344 ifmedia_removeall(&sc_if0->ifmedia); 1345 if (sc->sk_if[SK_PORT_B] != NULL) { 1346 sc_if1 = sc->sk_if[SK_PORT_B]; 1347 ifp1 = &sc_if1->arpcom.ac_if; 1348 sk_stop(sc_if1); 1349 if_detach(ifp1); 1350 free(sc_if1->sk_cdata.sk_jumbo_buf, M_DEVBUF); 1351 ifmedia_removeall(&sc_if1->ifmedia); 1352 } 1353 1354 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand); 1355 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq); 1356 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res); 1357 1358 splx(s); 1359 1360 return(0); 1361 } 1362 1363 static int sk_encap(sc_if, m_head, txidx) 1364 struct sk_if_softc *sc_if; 1365 struct mbuf *m_head; 1366 u_int32_t *txidx; 1367 { 1368 struct sk_tx_desc *f = NULL; 1369 struct mbuf *m; 1370 u_int32_t frag, cur, cnt = 0; 1371 1372 m = m_head; 1373 cur = frag = *txidx; 1374 1375 /* 1376 * Start packing the mbufs in this chain into 1377 * the fragment pointers. Stop when we run out 1378 * of fragments or hit the end of the mbuf chain. 1379 */ 1380 for (m = m_head; m != NULL; m = m->m_next) { 1381 if (m->m_len != 0) { 1382 if ((SK_TX_RING_CNT - 1383 (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) 1384 return(ENOBUFS); 1385 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1386 f->sk_data_lo = vtophys(mtod(m, vm_offset_t)); 1387 f->sk_ctl = m->m_len | SK_OPCODE_DEFAULT; 1388 if (cnt == 0) 1389 f->sk_ctl |= SK_TXCTL_FIRSTFRAG; 1390 else 1391 f->sk_ctl |= SK_TXCTL_OWN; 1392 cur = frag; 1393 SK_INC(frag, SK_TX_RING_CNT); 1394 cnt++; 1395 } 1396 } 1397 1398 if (m != NULL) 1399 return(ENOBUFS); 1400 1401 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1402 SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR; 1403 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1404 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= SK_TXCTL_OWN; 1405 sc_if->sk_cdata.sk_tx_cnt += cnt; 1406 1407 *txidx = frag; 1408 1409 return(0); 1410 } 1411 1412 static void sk_start(ifp) 1413 struct ifnet *ifp; 1414 { 1415 struct sk_softc *sc; 1416 struct sk_if_softc *sc_if; 1417 struct mbuf *m_head = NULL; 1418 u_int32_t idx; 1419 1420 sc_if = ifp->if_softc; 1421 sc = sc_if->sk_softc; 1422 1423 idx = sc_if->sk_cdata.sk_tx_prod; 1424 1425 while(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1426 IF_DEQUEUE(&ifp->if_snd, m_head); 1427 if (m_head == NULL) 1428 break; 1429 1430 /* 1431 * Pack the data into the transmit ring. If we 1432 * don't have room, set the OACTIVE flag and wait 1433 * for the NIC to drain the ring. 1434 */ 1435 if (sk_encap(sc_if, m_head, &idx)) { 1436 IF_PREPEND(&ifp->if_snd, m_head); 1437 ifp->if_flags |= IFF_OACTIVE; 1438 break; 1439 } 1440 1441 /* 1442 * If there's a BPF listener, bounce a copy of this frame 1443 * to him. 1444 */ 1445 #if NBPF > 0 1446 if (ifp->if_bpf) 1447 bpf_mtap(ifp, m_head); 1448 #endif 1449 } 1450 1451 /* Transmit */ 1452 sc_if->sk_cdata.sk_tx_prod = idx; 1453 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1454 1455 /* Set a timeout in case the chip goes out to lunch. */ 1456 ifp->if_timer = 5; 1457 1458 return; 1459 } 1460 1461 1462 static void sk_watchdog(ifp) 1463 struct ifnet *ifp; 1464 { 1465 struct sk_if_softc *sc_if; 1466 1467 sc_if = ifp->if_softc; 1468 1469 printf("sk%d: watchdog timeout\n", sc_if->sk_unit); 1470 sk_init(sc_if); 1471 1472 return; 1473 } 1474 1475 static void sk_shutdown(dev) 1476 device_t dev; 1477 { 1478 struct sk_softc *sc; 1479 1480 sc = device_get_softc(dev); 1481 1482 /* Turn off the 'driver is loaded' LED. */ 1483 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1484 1485 /* 1486 * Reset the GEnesis controller. Doing this should also 1487 * assert the resets on the attached XMAC(s). 1488 */ 1489 sk_reset(sc); 1490 1491 return; 1492 } 1493 1494 static void sk_rxeof(sc_if) 1495 struct sk_if_softc *sc_if; 1496 { 1497 struct ether_header *eh; 1498 struct mbuf *m; 1499 struct ifnet *ifp; 1500 struct sk_chain *cur_rx; 1501 int total_len = 0; 1502 int i; 1503 u_int32_t rxstat; 1504 1505 ifp = &sc_if->arpcom.ac_if; 1506 i = sc_if->sk_cdata.sk_rx_prod; 1507 cur_rx = &sc_if->sk_cdata.sk_rx_chain[i]; 1508 1509 while(!(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl & SK_RXCTL_OWN)) { 1510 1511 cur_rx = &sc_if->sk_cdata.sk_rx_chain[i]; 1512 rxstat = sc_if->sk_rdata->sk_rx_ring[i].sk_xmac_rxstat; 1513 m = cur_rx->sk_mbuf; 1514 cur_rx->sk_mbuf = NULL; 1515 total_len = SK_RXBYTES(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl); 1516 SK_INC(i, SK_RX_RING_CNT); 1517 1518 if (rxstat & XM_RXSTAT_ERRFRAME) { 1519 ifp->if_ierrors++; 1520 sk_newbuf(sc_if, cur_rx, m); 1521 continue; 1522 } 1523 1524 /* 1525 * Try to allocate a new jumbo buffer. If that 1526 * fails, copy the packet to mbufs and put the 1527 * jumbo buffer back in the ring so it can be 1528 * re-used. If allocating mbufs fails, then we 1529 * have to drop the packet. 1530 */ 1531 if (sk_newbuf(sc_if, cur_rx, NULL) == ENOBUFS) { 1532 struct mbuf *m0; 1533 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1534 total_len + ETHER_ALIGN, 0, ifp, NULL); 1535 sk_newbuf(sc_if, cur_rx, m); 1536 if (m0 == NULL) { 1537 printf("sk%d: no receive buffers " 1538 "available -- packet dropped!\n", 1539 sc_if->sk_unit); 1540 ifp->if_ierrors++; 1541 continue; 1542 } 1543 m_adj(m0, ETHER_ALIGN); 1544 m = m0; 1545 } else { 1546 m->m_pkthdr.rcvif = ifp; 1547 m->m_pkthdr.len = m->m_len = total_len; 1548 } 1549 1550 ifp->if_ipackets++; 1551 eh = mtod(m, struct ether_header *); 1552 1553 #if NBPF > 0 1554 if (ifp->if_bpf) { 1555 bpf_mtap(ifp, m); 1556 if (ifp->if_flags & IFF_PROMISC && 1557 (bcmp(eh->ether_dhost, sc_if->arpcom.ac_enaddr, 1558 ETHER_ADDR_LEN) && !(eh->ether_dhost[0] & 1))) { 1559 m_freem(m); 1560 continue; 1561 } 1562 } 1563 #endif 1564 /* Remove header from mbuf and pass it on. */ 1565 m_adj(m, sizeof(struct ether_header)); 1566 ether_input(ifp, eh, m); 1567 } 1568 1569 sc_if->sk_cdata.sk_rx_prod = i; 1570 1571 return; 1572 } 1573 1574 static void sk_txeof(sc_if) 1575 struct sk_if_softc *sc_if; 1576 { 1577 struct sk_tx_desc *cur_tx = NULL; 1578 struct ifnet *ifp; 1579 u_int32_t idx; 1580 1581 ifp = &sc_if->arpcom.ac_if; 1582 1583 /* 1584 * Go through our tx ring and free mbufs for those 1585 * frames that have been sent. 1586 */ 1587 idx = sc_if->sk_cdata.sk_tx_cons; 1588 while(idx != sc_if->sk_cdata.sk_tx_prod) { 1589 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 1590 if (cur_tx->sk_ctl & SK_TXCTL_OWN) 1591 break; 1592 if (cur_tx->sk_ctl & SK_TXCTL_LASTFRAG) 1593 ifp->if_opackets++; 1594 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 1595 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 1596 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 1597 } 1598 sc_if->sk_cdata.sk_tx_cnt--; 1599 SK_INC(idx, SK_TX_RING_CNT); 1600 ifp->if_timer = 0; 1601 } 1602 1603 sc_if->sk_cdata.sk_tx_cons = idx; 1604 1605 if (cur_tx != NULL) 1606 ifp->if_flags &= ~IFF_OACTIVE; 1607 1608 return; 1609 } 1610 1611 static void sk_intr_xmac(sc_if) 1612 struct sk_if_softc *sc_if; 1613 { 1614 struct sk_softc *sc; 1615 u_int16_t status; 1616 u_int16_t bmsr; 1617 1618 sc = sc_if->sk_softc; 1619 status = SK_XM_READ_2(sc_if, XM_ISR); 1620 1621 if (status & XM_ISR_LINKEVENT) { 1622 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_LINKEVENT); 1623 if (sc_if->sk_link == 1) { 1624 printf("sk%d: gigabit link down\n", sc_if->sk_unit); 1625 sc_if->sk_link = 0; 1626 } 1627 } 1628 1629 if (status & XM_ISR_AUTONEG_DONE) { 1630 bmsr = sk_phy_readreg(sc_if, XM_PHY_BMSR); 1631 if (bmsr & XM_BMSR_LINKSTAT) { 1632 sc_if->sk_link = 1; 1633 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_LINKEVENT); 1634 printf("sk%d: gigabit link up\n", sc_if->sk_unit); 1635 } 1636 } 1637 1638 if (status & XM_IMR_TX_UNDERRUN) 1639 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 1640 1641 if (status & XM_IMR_RX_OVERRUN) 1642 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 1643 1644 return; 1645 } 1646 1647 static void sk_intr(xsc) 1648 void *xsc; 1649 { 1650 struct sk_softc *sc = xsc; 1651 struct sk_if_softc *sc_if0 = NULL, *sc_if1 = NULL; 1652 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 1653 u_int32_t status; 1654 1655 sc_if0 = sc->sk_if[SK_PORT_A]; 1656 sc_if1 = sc->sk_if[SK_PORT_B]; 1657 1658 if (sc_if0 != NULL) 1659 ifp0 = &sc_if0->arpcom.ac_if; 1660 if (sc_if1 != NULL) 1661 ifp1 = &sc_if0->arpcom.ac_if; 1662 1663 for (;;) { 1664 status = CSR_READ_4(sc, SK_ISSR); 1665 if (!(status & sc->sk_intrmask)) 1666 break; 1667 1668 /* Handle receive interrupts first. */ 1669 if (status & SK_ISR_RX1_EOF) { 1670 sk_rxeof(sc_if0); 1671 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 1672 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 1673 } 1674 if (status & SK_ISR_RX2_EOF) { 1675 sk_rxeof(sc_if1); 1676 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 1677 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 1678 } 1679 1680 /* Then transmit interrupts. */ 1681 if (status & SK_ISR_TX1_S_EOF) { 1682 sk_txeof(sc_if0); 1683 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 1684 SK_TXBMU_CLR_IRQ_EOF); 1685 } 1686 if (status & SK_ISR_TX2_S_EOF) { 1687 sk_txeof(sc_if1); 1688 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 1689 SK_TXBMU_CLR_IRQ_EOF); 1690 } 1691 1692 /* Then MAC interrupts. */ 1693 if (status & SK_ISR_MAC1) 1694 sk_intr_xmac(sc_if0); 1695 1696 if (status & SK_ISR_MAC2) 1697 sk_intr_xmac(sc_if1); 1698 } 1699 1700 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 1701 1702 return; 1703 } 1704 1705 static void sk_init_xmac(sc_if) 1706 struct sk_if_softc *sc_if; 1707 { 1708 struct sk_softc *sc; 1709 struct ifnet *ifp; 1710 1711 sc = sc_if->sk_softc; 1712 ifp = &sc_if->arpcom.ac_if; 1713 1714 /* Unreset the XMAC. */ 1715 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 1716 DELAY(1000); 1717 1718 /* Save the XMAC II revision */ 1719 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 1720 1721 /* Set station address */ 1722 SK_XM_WRITE_2(sc_if, XM_PAR0, 1723 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[0])); 1724 SK_XM_WRITE_2(sc_if, XM_PAR1, 1725 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[2])); 1726 SK_XM_WRITE_2(sc_if, XM_PAR2, 1727 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[4])); 1728 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 1729 1730 if (ifp->if_flags & IFF_PROMISC) { 1731 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 1732 } else { 1733 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 1734 } 1735 1736 if (ifp->if_flags & IFF_BROADCAST) { 1737 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 1738 } else { 1739 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 1740 } 1741 1742 /* We don't need the FCS appended to the packet. */ 1743 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 1744 1745 /* We want short frames padded to 60 bytes. */ 1746 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 1747 1748 /* 1749 * Enable the reception of all error frames. This is is 1750 * a necessary evil due to the design of the XMAC. The 1751 * XMAC's receive FIFO is only 8K in size, however jumbo 1752 * frames can be up to 9000 bytes in length. When bad 1753 * frame filtering is enabled, the XMAC's RX FIFO operates 1754 * in 'store and forward' mode. For this to work, the 1755 * entire frame has to fit into the FIFO, but that means 1756 * that jumbo frames larger than 8192 bytes will be 1757 * truncated. Disabling all bad frame filtering causes 1758 * the RX FIFO to operate in streaming mode, in which 1759 * case the XMAC will start transfering frames out of the 1760 * RX FIFO as soon as the FIFO threshold is reached. 1761 */ 1762 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 1763 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 1764 XM_MODE_RX_INRANGELEN); 1765 1766 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 1767 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 1768 else 1769 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 1770 1771 /* 1772 * Bump up the transmit threshold. This helps hold off transmit 1773 * underruns when we're blasting traffic from both ports at once. 1774 */ 1775 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 1776 1777 /* Set multicast filter */ 1778 sk_setmulti(sc_if); 1779 1780 /* Clear and enable interrupts */ 1781 SK_XM_READ_2(sc_if, XM_ISR); 1782 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 1783 1784 sc_if->sk_link = 0; 1785 1786 /* Configure MAC arbiter */ 1787 switch(sc_if->sk_xmac_rev) { 1788 case XM_XMAC_REV_B2: 1789 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 1790 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 1791 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 1792 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 1793 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 1794 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 1795 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 1796 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 1797 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 1798 break; 1799 case XM_XMAC_REV_C1: 1800 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 1801 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 1802 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 1803 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 1804 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 1805 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 1806 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 1807 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 1808 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 1809 break; 1810 default: 1811 break; 1812 } 1813 sk_win_write_2(sc, SK_MACARB_CTL, 1814 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 1815 1816 return; 1817 } 1818 1819 /* 1820 * Note that to properly initialize any part of the GEnesis chip, 1821 * you first have to take it out of reset mode. 1822 */ 1823 static void sk_init(xsc) 1824 void *xsc; 1825 { 1826 struct sk_if_softc *sc_if = xsc; 1827 struct sk_softc *sc; 1828 struct ifnet *ifp; 1829 int s; 1830 1831 s = splimp(); 1832 1833 ifp = &sc_if->arpcom.ac_if; 1834 sc = sc_if->sk_softc; 1835 1836 /* Cancel pending I/O and free all RX/TX buffers. */ 1837 sk_stop(sc_if); 1838 1839 /* Configure LINK_SYNC LED */ 1840 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 1841 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_ON); 1842 1843 /* Configure RX LED */ 1844 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_START); 1845 1846 /* Configure TX LED */ 1847 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_TXLEDCTL_COUNTER_START); 1848 1849 /* Configure I2C registers */ 1850 1851 /* Configure XMAC(s) */ 1852 sk_init_xmac(sc_if); 1853 1854 /* Configure MAC FIFOs */ 1855 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 1856 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 1857 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 1858 1859 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 1860 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 1861 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 1862 1863 /* Configure transmit arbiter(s) */ 1864 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 1865 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 1866 1867 /* Configure RAMbuffers */ 1868 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 1869 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 1870 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 1871 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 1872 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 1873 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 1874 1875 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 1876 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 1877 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 1878 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 1879 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 1880 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 1881 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 1882 1883 /* Configure BMUs */ 1884 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 1885 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 1886 vtophys(&sc_if->sk_rdata->sk_rx_ring[0])); 1887 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 1888 1889 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 1890 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 1891 vtophys(&sc_if->sk_rdata->sk_tx_ring[0])); 1892 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 1893 1894 /* Init descriptors */ 1895 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 1896 printf("sk%d: initialization failed: no " 1897 "memory for rx buffers\n", sc_if->sk_unit); 1898 sk_stop(sc_if); 1899 (void)splx(s); 1900 return; 1901 } 1902 sk_init_tx_ring(sc_if); 1903 1904 /* Configure interrupt handling */ 1905 CSR_READ_4(sc, SK_ISSR); 1906 if (sc_if->sk_port == SK_PORT_A) 1907 sc->sk_intrmask |= SK_INTRS1; 1908 else 1909 sc->sk_intrmask |= SK_INTRS2; 1910 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 1911 1912 /* Start BMUs. */ 1913 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 1914 1915 /* Enable XMACs TX and RX state machines */ 1916 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 1917 1918 ifp->if_flags |= IFF_RUNNING; 1919 ifp->if_flags &= ~IFF_OACTIVE; 1920 1921 splx(s); 1922 1923 return; 1924 } 1925 1926 static void sk_stop(sc_if) 1927 struct sk_if_softc *sc_if; 1928 { 1929 int i; 1930 struct sk_softc *sc; 1931 struct ifnet *ifp; 1932 1933 sc = sc_if->sk_softc; 1934 ifp = &sc_if->arpcom.ac_if; 1935 1936 /* Turn off various components of this interface. */ 1937 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_RESET); 1938 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 1939 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 1940 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 1941 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 1942 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 1943 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 1944 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 1945 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 1946 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 1947 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 1948 1949 /* Disable interrupts */ 1950 if (sc_if->sk_port == SK_PORT_A) 1951 sc->sk_intrmask &= ~SK_INTRS1; 1952 else 1953 sc->sk_intrmask &= ~SK_INTRS2; 1954 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 1955 1956 /* Free RX and TX mbufs still in the queues. */ 1957 for (i = 0; i < SK_RX_RING_CNT; i++) { 1958 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 1959 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 1960 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 1961 } 1962 } 1963 1964 for (i = 0; i < SK_TX_RING_CNT; i++) { 1965 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 1966 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 1967 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 1968 } 1969 } 1970 1971 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1972 1973 return; 1974 } 1975