1 /* $OpenBSD: if_sk.c,v 2.33 2003/08/12 05:23:06 nate Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999, 2000 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 /*- 35 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 36 * 37 * Permission to use, copy, modify, and distribute this software for any 38 * purpose with or without fee is hereby granted, provided that the above 39 * copyright notice and this permission notice appear in all copies. 40 * 41 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 42 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 43 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 44 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 45 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 46 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 47 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 48 */ 49 50 #include <sys/cdefs.h> 51 __FBSDID("$FreeBSD$"); 52 53 /* 54 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 55 * the SK-984x series adapters, both single port and dual port. 56 * References: 57 * The XaQti XMAC II datasheet, 58 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 59 * The SysKonnect GEnesis manual, http://www.syskonnect.com 60 * 61 * Note: XaQti has been aquired by Vitesse, and Vitesse does not have the 62 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 63 * convenience to others until Vitesse corrects this problem: 64 * 65 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 66 * 67 * Written by Bill Paul <wpaul@ee.columbia.edu> 68 * Department of Electrical Engineering 69 * Columbia University, New York City 70 */ 71 /* 72 * The SysKonnect gigabit ethernet adapters consist of two main 73 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 74 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 75 * components and a PHY while the GEnesis controller provides a PCI 76 * interface with DMA support. Each card may have between 512K and 77 * 2MB of SRAM on board depending on the configuration. 78 * 79 * The SysKonnect GEnesis controller can have either one or two XMAC 80 * chips connected to it, allowing single or dual port NIC configurations. 81 * SysKonnect has the distinction of being the only vendor on the market 82 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 83 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 84 * XMAC registers. This driver takes advantage of these features to allow 85 * both XMACs to operate as independent interfaces. 86 */ 87 88 #include <sys/param.h> 89 #include <sys/systm.h> 90 #include <sys/bus.h> 91 #include <sys/endian.h> 92 #include <sys/mbuf.h> 93 #include <sys/malloc.h> 94 #include <sys/kernel.h> 95 #include <sys/module.h> 96 #include <sys/socket.h> 97 #include <sys/sockio.h> 98 #include <sys/queue.h> 99 #include <sys/sysctl.h> 100 101 #include <net/bpf.h> 102 #include <net/ethernet.h> 103 #include <net/if.h> 104 #include <net/if_arp.h> 105 #include <net/if_dl.h> 106 #include <net/if_media.h> 107 #include <net/if_types.h> 108 #include <net/if_vlan_var.h> 109 110 #include <netinet/in.h> 111 #include <netinet/in_systm.h> 112 #include <netinet/ip.h> 113 114 #include <machine/bus.h> 115 #include <machine/in_cksum.h> 116 #include <machine/resource.h> 117 #include <sys/rman.h> 118 119 #include <dev/mii/mii.h> 120 #include <dev/mii/miivar.h> 121 #include <dev/mii/brgphyreg.h> 122 123 #include <dev/pci/pcireg.h> 124 #include <dev/pci/pcivar.h> 125 126 #if 0 127 #define SK_USEIOSPACE 128 #endif 129 130 #include <dev/sk/if_skreg.h> 131 #include <dev/sk/xmaciireg.h> 132 #include <dev/sk/yukonreg.h> 133 134 MODULE_DEPEND(sk, pci, 1, 1, 1); 135 MODULE_DEPEND(sk, ether, 1, 1, 1); 136 MODULE_DEPEND(sk, miibus, 1, 1, 1); 137 138 /* "device miibus" required. See GENERIC if you get errors here. */ 139 #include "miibus_if.h" 140 141 #ifndef lint 142 static const char rcsid[] = 143 "$FreeBSD$"; 144 #endif 145 146 static struct sk_type sk_devs[] = { 147 { 148 VENDORID_SK, 149 DEVICEID_SK_V1, 150 "SysKonnect Gigabit Ethernet (V1.0)" 151 }, 152 { 153 VENDORID_SK, 154 DEVICEID_SK_V2, 155 "SysKonnect Gigabit Ethernet (V2.0)" 156 }, 157 { 158 VENDORID_MARVELL, 159 DEVICEID_SK_V2, 160 "Marvell Gigabit Ethernet" 161 }, 162 #ifdef not_yet 163 { 164 VENDORID_MARVELL, 165 DEVICEID_MRVL_4360, 166 "Marvell 88E8052 Gigabit Ethernet Controller" 167 }, 168 { 169 VENDORID_MARVELL, 170 DEVICEID_MRVL_4361, 171 "Marvell 88E8050 Gigabit Ethernet Controller" 172 }, 173 { 174 VENDORID_MARVELL, 175 DEVICEID_MRVL_4362, 176 "Marvell 88E8053 Gigabit Ethernet Controller" 177 }, 178 #endif 179 { 180 VENDORID_MARVELL, 181 DEVICEID_BELKIN_5005, 182 "Belkin F5D5005 Gigabit Ethernet" 183 }, 184 { 185 VENDORID_3COM, 186 DEVICEID_3COM_3C940, 187 "3Com 3C940 Gigabit Ethernet" 188 }, 189 { 190 VENDORID_LINKSYS, 191 DEVICEID_LINKSYS_EG1032, 192 "Linksys EG1032 Gigabit Ethernet" 193 }, 194 { 195 VENDORID_DLINK, 196 DEVICEID_DLINK_DGE530T, 197 "D-Link DGE-530T Gigabit Ethernet" 198 }, 199 { 0, 0, NULL } 200 }; 201 202 static int skc_probe(device_t); 203 static int skc_attach(device_t); 204 static int skc_detach(device_t); 205 static void skc_shutdown(device_t); 206 static int skc_suspend(device_t); 207 static int skc_resume(device_t); 208 static int sk_detach(device_t); 209 static int sk_probe(device_t); 210 static int sk_attach(device_t); 211 static void sk_tick(void *); 212 static void sk_yukon_tick(void *); 213 static void sk_intr(void *); 214 static void sk_intr_xmac(struct sk_if_softc *); 215 static void sk_intr_bcom(struct sk_if_softc *); 216 static void sk_intr_yukon(struct sk_if_softc *); 217 static __inline void sk_rxcksum(struct ifnet *, struct mbuf *, u_int32_t); 218 static __inline int sk_rxvalid(struct sk_softc *, u_int32_t, u_int32_t); 219 static void sk_rxeof(struct sk_if_softc *); 220 static void sk_jumbo_rxeof(struct sk_if_softc *); 221 static void sk_txeof(struct sk_if_softc *); 222 static void sk_txcksum(struct ifnet *, struct mbuf *, struct sk_tx_desc *); 223 static int sk_encap(struct sk_if_softc *, struct mbuf **); 224 static void sk_start(struct ifnet *); 225 static void sk_start_locked(struct ifnet *); 226 static int sk_ioctl(struct ifnet *, u_long, caddr_t); 227 static void sk_init(void *); 228 static void sk_init_locked(struct sk_if_softc *); 229 static void sk_init_xmac(struct sk_if_softc *); 230 static void sk_init_yukon(struct sk_if_softc *); 231 static void sk_stop(struct sk_if_softc *); 232 static void sk_watchdog(struct ifnet *); 233 static int sk_ifmedia_upd(struct ifnet *); 234 static void sk_ifmedia_sts(struct ifnet *, struct ifmediareq *); 235 static void sk_reset(struct sk_softc *); 236 static __inline void sk_discard_rxbuf(struct sk_if_softc *, int); 237 static __inline void sk_discard_jumbo_rxbuf(struct sk_if_softc *, int); 238 static int sk_newbuf(struct sk_if_softc *, int); 239 static int sk_jumbo_newbuf(struct sk_if_softc *, int); 240 static void sk_dmamap_cb(void *, bus_dma_segment_t *, int, int); 241 static int sk_dma_alloc(struct sk_if_softc *); 242 static void sk_dma_free(struct sk_if_softc *); 243 static void *sk_jalloc(struct sk_if_softc *); 244 static void sk_jfree(void *, void *); 245 static int sk_init_rx_ring(struct sk_if_softc *); 246 static int sk_init_jumbo_rx_ring(struct sk_if_softc *); 247 static void sk_init_tx_ring(struct sk_if_softc *); 248 static u_int32_t sk_win_read_4(struct sk_softc *, int); 249 static u_int16_t sk_win_read_2(struct sk_softc *, int); 250 static u_int8_t sk_win_read_1(struct sk_softc *, int); 251 static void sk_win_write_4(struct sk_softc *, int, u_int32_t); 252 static void sk_win_write_2(struct sk_softc *, int, u_int32_t); 253 static void sk_win_write_1(struct sk_softc *, int, u_int32_t); 254 static u_int8_t sk_vpd_readbyte(struct sk_softc *, int); 255 static void sk_vpd_read_res(struct sk_softc *, struct vpd_res *, int); 256 static void sk_vpd_read(struct sk_softc *); 257 258 static int sk_miibus_readreg(device_t, int, int); 259 static int sk_miibus_writereg(device_t, int, int, int); 260 static void sk_miibus_statchg(device_t); 261 262 static int sk_xmac_miibus_readreg(struct sk_if_softc *, int, int); 263 static int sk_xmac_miibus_writereg(struct sk_if_softc *, int, int, 264 int); 265 static void sk_xmac_miibus_statchg(struct sk_if_softc *); 266 267 static int sk_marv_miibus_readreg(struct sk_if_softc *, int, int); 268 static int sk_marv_miibus_writereg(struct sk_if_softc *, int, int, 269 int); 270 static void sk_marv_miibus_statchg(struct sk_if_softc *); 271 272 static uint32_t sk_xmchash(const uint8_t *); 273 static uint32_t sk_gmchash(const uint8_t *); 274 static void sk_setfilt(struct sk_if_softc *, u_int16_t *, int); 275 static void sk_setmulti(struct sk_if_softc *); 276 static void sk_setpromisc(struct sk_if_softc *); 277 278 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high); 279 static int sysctl_hw_sk_int_mod(SYSCTL_HANDLER_ARGS); 280 281 #ifdef SK_USEIOSPACE 282 #define SK_RES SYS_RES_IOPORT 283 #define SK_RID SK_PCI_LOIO 284 #else 285 #define SK_RES SYS_RES_MEMORY 286 #define SK_RID SK_PCI_LOMEM 287 #endif 288 289 /* 290 * It seems that SK-NET GENESIS supports very simple checksum offload 291 * capability for Tx and I believe it can generate 0 checksum value for 292 * UDP packets in Tx as the hardware can't differenciate UDP packets from 293 * TCP packets. 0 chcecksum value for UDP packet is an invalid one as it 294 * means sender didn't perforam checksum computation. For the safety I 295 * disabled UDP checksum offload capability at the moment. Alternatively 296 * we can intrduce a LINK0/LINK1 flag as hme(4) did in its Tx checksum 297 * offload routine. 298 */ 299 #define SK_CSUM_FEATURES (CSUM_TCP) 300 301 /* 302 * Note that we have newbus methods for both the GEnesis controller 303 * itself and the XMAC(s). The XMACs are children of the GEnesis, and 304 * the miibus code is a child of the XMACs. We need to do it this way 305 * so that the miibus drivers can access the PHY registers on the 306 * right PHY. It's not quite what I had in mind, but it's the only 307 * design that achieves the desired effect. 308 */ 309 static device_method_t skc_methods[] = { 310 /* Device interface */ 311 DEVMETHOD(device_probe, skc_probe), 312 DEVMETHOD(device_attach, skc_attach), 313 DEVMETHOD(device_detach, skc_detach), 314 DEVMETHOD(device_suspend, skc_suspend), 315 DEVMETHOD(device_resume, skc_resume), 316 DEVMETHOD(device_shutdown, skc_shutdown), 317 318 /* bus interface */ 319 DEVMETHOD(bus_print_child, bus_generic_print_child), 320 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 321 322 { 0, 0 } 323 }; 324 325 static driver_t skc_driver = { 326 "skc", 327 skc_methods, 328 sizeof(struct sk_softc) 329 }; 330 331 static devclass_t skc_devclass; 332 333 static device_method_t sk_methods[] = { 334 /* Device interface */ 335 DEVMETHOD(device_probe, sk_probe), 336 DEVMETHOD(device_attach, sk_attach), 337 DEVMETHOD(device_detach, sk_detach), 338 DEVMETHOD(device_shutdown, bus_generic_shutdown), 339 340 /* bus interface */ 341 DEVMETHOD(bus_print_child, bus_generic_print_child), 342 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 343 344 /* MII interface */ 345 DEVMETHOD(miibus_readreg, sk_miibus_readreg), 346 DEVMETHOD(miibus_writereg, sk_miibus_writereg), 347 DEVMETHOD(miibus_statchg, sk_miibus_statchg), 348 349 { 0, 0 } 350 }; 351 352 static driver_t sk_driver = { 353 "sk", 354 sk_methods, 355 sizeof(struct sk_if_softc) 356 }; 357 358 static devclass_t sk_devclass; 359 360 DRIVER_MODULE(skc, pci, skc_driver, skc_devclass, 0, 0); 361 DRIVER_MODULE(sk, skc, sk_driver, sk_devclass, 0, 0); 362 DRIVER_MODULE(miibus, sk, miibus_driver, miibus_devclass, 0, 0); 363 364 #define SK_SETBIT(sc, reg, x) \ 365 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 366 367 #define SK_CLRBIT(sc, reg, x) \ 368 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 369 370 #define SK_WIN_SETBIT_4(sc, reg, x) \ 371 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x) 372 373 #define SK_WIN_CLRBIT_4(sc, reg, x) \ 374 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x) 375 376 #define SK_WIN_SETBIT_2(sc, reg, x) \ 377 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x) 378 379 #define SK_WIN_CLRBIT_2(sc, reg, x) \ 380 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x) 381 382 static u_int32_t 383 sk_win_read_4(sc, reg) 384 struct sk_softc *sc; 385 int reg; 386 { 387 #ifdef SK_USEIOSPACE 388 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 389 return(CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg))); 390 #else 391 return(CSR_READ_4(sc, reg)); 392 #endif 393 } 394 395 static u_int16_t 396 sk_win_read_2(sc, reg) 397 struct sk_softc *sc; 398 int reg; 399 { 400 #ifdef SK_USEIOSPACE 401 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 402 return(CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg))); 403 #else 404 return(CSR_READ_2(sc, reg)); 405 #endif 406 } 407 408 static u_int8_t 409 sk_win_read_1(sc, reg) 410 struct sk_softc *sc; 411 int reg; 412 { 413 #ifdef SK_USEIOSPACE 414 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 415 return(CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg))); 416 #else 417 return(CSR_READ_1(sc, reg)); 418 #endif 419 } 420 421 static void 422 sk_win_write_4(sc, reg, val) 423 struct sk_softc *sc; 424 int reg; 425 u_int32_t val; 426 { 427 #ifdef SK_USEIOSPACE 428 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 429 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), val); 430 #else 431 CSR_WRITE_4(sc, reg, val); 432 #endif 433 return; 434 } 435 436 static void 437 sk_win_write_2(sc, reg, val) 438 struct sk_softc *sc; 439 int reg; 440 u_int32_t val; 441 { 442 #ifdef SK_USEIOSPACE 443 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 444 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), val); 445 #else 446 CSR_WRITE_2(sc, reg, val); 447 #endif 448 return; 449 } 450 451 static void 452 sk_win_write_1(sc, reg, val) 453 struct sk_softc *sc; 454 int reg; 455 u_int32_t val; 456 { 457 #ifdef SK_USEIOSPACE 458 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 459 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), val); 460 #else 461 CSR_WRITE_1(sc, reg, val); 462 #endif 463 return; 464 } 465 466 /* 467 * The VPD EEPROM contains Vital Product Data, as suggested in 468 * the PCI 2.1 specification. The VPD data is separared into areas 469 * denoted by resource IDs. The SysKonnect VPD contains an ID string 470 * resource (the name of the adapter), a read-only area resource 471 * containing various key/data fields and a read/write area which 472 * can be used to store asset management information or log messages. 473 * We read the ID string and read-only into buffers attached to 474 * the controller softc structure for later use. At the moment, 475 * we only use the ID string during skc_attach(). 476 */ 477 static u_int8_t 478 sk_vpd_readbyte(sc, addr) 479 struct sk_softc *sc; 480 int addr; 481 { 482 int i; 483 484 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 485 for (i = 0; i < SK_TIMEOUT; i++) { 486 /* ASUS LOM takes a very long time to read VPD. */ 487 DELAY(100); 488 if (sk_win_read_2(sc, 489 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 490 break; 491 } 492 493 if (i == SK_TIMEOUT) 494 return(0); 495 496 return(sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA))); 497 } 498 499 static void 500 sk_vpd_read_res(sc, res, addr) 501 struct sk_softc *sc; 502 struct vpd_res *res; 503 int addr; 504 { 505 int i; 506 u_int8_t *ptr; 507 508 ptr = (u_int8_t *)res; 509 for (i = 0; i < sizeof(struct vpd_res); i++) 510 ptr[i] = sk_vpd_readbyte(sc, i + addr); 511 512 return; 513 } 514 515 static void 516 sk_vpd_read(sc) 517 struct sk_softc *sc; 518 { 519 int pos = 0, i; 520 struct vpd_res res; 521 522 /* Check VPD capability */ 523 if (sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_CAPID)) != PCIY_VPD) 524 return; 525 if (sc->sk_vpd_prodname != NULL) 526 free(sc->sk_vpd_prodname, M_DEVBUF); 527 if (sc->sk_vpd_readonly != NULL) 528 free(sc->sk_vpd_readonly, M_DEVBUF); 529 sc->sk_vpd_prodname = NULL; 530 sc->sk_vpd_readonly = NULL; 531 sc->sk_vpd_readonly_len = 0; 532 533 sk_vpd_read_res(sc, &res, pos); 534 535 /* 536 * Bail out quietly if the eeprom appears to be missing or empty. 537 */ 538 if (res.vr_id == 0xff && res.vr_len == 0xff && res.vr_pad == 0xff) 539 return; 540 541 if (res.vr_id != VPD_RES_ID) { 542 device_printf(sc->sk_dev, "bad VPD resource id: expected %x " 543 "got %x\n", VPD_RES_ID, res.vr_id); 544 return; 545 } 546 547 pos += sizeof(res); 548 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 549 if (sc->sk_vpd_prodname != NULL) { 550 for (i = 0; i < res.vr_len; i++) 551 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 552 sc->sk_vpd_prodname[i] = '\0'; 553 } 554 pos += res.vr_len; 555 556 sk_vpd_read_res(sc, &res, pos); 557 558 if (res.vr_id != VPD_RES_READ) { 559 device_printf(sc->sk_dev, "bad VPD resource id: expected %x " 560 "got %x\n", VPD_RES_READ, res.vr_id); 561 return; 562 } 563 564 pos += sizeof(res); 565 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 566 for (i = 0; i < res.vr_len; i++) 567 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 568 sc->sk_vpd_readonly_len = res.vr_len; 569 570 return; 571 } 572 573 static int 574 sk_miibus_readreg(dev, phy, reg) 575 device_t dev; 576 int phy, reg; 577 { 578 struct sk_if_softc *sc_if; 579 int v; 580 581 sc_if = device_get_softc(dev); 582 583 SK_IF_MII_LOCK(sc_if); 584 switch(sc_if->sk_softc->sk_type) { 585 case SK_GENESIS: 586 v = sk_xmac_miibus_readreg(sc_if, phy, reg); 587 break; 588 case SK_YUKON: 589 case SK_YUKON_LITE: 590 case SK_YUKON_LP: 591 case SK_YUKON_EC: 592 v = sk_marv_miibus_readreg(sc_if, phy, reg); 593 break; 594 default: 595 v = 0; 596 break; 597 } 598 SK_IF_MII_UNLOCK(sc_if); 599 600 return (v); 601 } 602 603 static int 604 sk_miibus_writereg(dev, phy, reg, val) 605 device_t dev; 606 int phy, reg, val; 607 { 608 struct sk_if_softc *sc_if; 609 int v; 610 611 sc_if = device_get_softc(dev); 612 613 SK_IF_MII_LOCK(sc_if); 614 switch(sc_if->sk_softc->sk_type) { 615 case SK_GENESIS: 616 v = sk_xmac_miibus_writereg(sc_if, phy, reg, val); 617 break; 618 case SK_YUKON: 619 case SK_YUKON_LITE: 620 case SK_YUKON_LP: 621 case SK_YUKON_EC: 622 v = sk_marv_miibus_writereg(sc_if, phy, reg, val); 623 break; 624 default: 625 v = 0; 626 break; 627 } 628 SK_IF_MII_UNLOCK(sc_if); 629 630 return (v); 631 } 632 633 static void 634 sk_miibus_statchg(dev) 635 device_t dev; 636 { 637 struct sk_if_softc *sc_if; 638 639 sc_if = device_get_softc(dev); 640 641 SK_IF_MII_LOCK(sc_if); 642 switch(sc_if->sk_softc->sk_type) { 643 case SK_GENESIS: 644 sk_xmac_miibus_statchg(sc_if); 645 break; 646 case SK_YUKON: 647 case SK_YUKON_LITE: 648 case SK_YUKON_LP: 649 case SK_YUKON_EC: 650 sk_marv_miibus_statchg(sc_if); 651 break; 652 } 653 SK_IF_MII_UNLOCK(sc_if); 654 655 return; 656 } 657 658 static int 659 sk_xmac_miibus_readreg(sc_if, phy, reg) 660 struct sk_if_softc *sc_if; 661 int phy, reg; 662 { 663 int i; 664 665 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 666 return(0); 667 668 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 669 SK_XM_READ_2(sc_if, XM_PHY_DATA); 670 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 671 for (i = 0; i < SK_TIMEOUT; i++) { 672 DELAY(1); 673 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 674 XM_MMUCMD_PHYDATARDY) 675 break; 676 } 677 678 if (i == SK_TIMEOUT) { 679 if_printf(sc_if->sk_ifp, "phy failed to come ready\n"); 680 return(0); 681 } 682 } 683 DELAY(1); 684 i = SK_XM_READ_2(sc_if, XM_PHY_DATA); 685 686 return(i); 687 } 688 689 static int 690 sk_xmac_miibus_writereg(sc_if, phy, reg, val) 691 struct sk_if_softc *sc_if; 692 int phy, reg, val; 693 { 694 int i; 695 696 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 697 for (i = 0; i < SK_TIMEOUT; i++) { 698 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 699 break; 700 } 701 702 if (i == SK_TIMEOUT) { 703 if_printf(sc_if->sk_ifp, "phy failed to come ready\n"); 704 return (ETIMEDOUT); 705 } 706 707 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 708 for (i = 0; i < SK_TIMEOUT; i++) { 709 DELAY(1); 710 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 711 break; 712 } 713 if (i == SK_TIMEOUT) 714 if_printf(sc_if->sk_ifp, "phy write timed out\n"); 715 716 return(0); 717 } 718 719 static void 720 sk_xmac_miibus_statchg(sc_if) 721 struct sk_if_softc *sc_if; 722 { 723 struct mii_data *mii; 724 725 mii = device_get_softc(sc_if->sk_miibus); 726 727 /* 728 * If this is a GMII PHY, manually set the XMAC's 729 * duplex mode accordingly. 730 */ 731 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 732 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 733 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 734 } else { 735 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 736 } 737 } 738 } 739 740 static int 741 sk_marv_miibus_readreg(sc_if, phy, reg) 742 struct sk_if_softc *sc_if; 743 int phy, reg; 744 { 745 u_int16_t val; 746 int i; 747 748 if (phy != 0 || 749 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 750 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 751 return(0); 752 } 753 754 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 755 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 756 757 for (i = 0; i < SK_TIMEOUT; i++) { 758 DELAY(1); 759 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 760 if (val & YU_SMICR_READ_VALID) 761 break; 762 } 763 764 if (i == SK_TIMEOUT) { 765 if_printf(sc_if->sk_ifp, "phy failed to come ready\n"); 766 return(0); 767 } 768 769 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 770 771 return(val); 772 } 773 774 static int 775 sk_marv_miibus_writereg(sc_if, phy, reg, val) 776 struct sk_if_softc *sc_if; 777 int phy, reg, val; 778 { 779 int i; 780 781 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 782 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 783 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 784 785 for (i = 0; i < SK_TIMEOUT; i++) { 786 DELAY(1); 787 if (SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY) 788 break; 789 } 790 if (i == SK_TIMEOUT) { 791 if_printf(sc_if->sk_ifp, "phy write timeout\n"); 792 return (0); 793 } 794 795 return(0); 796 } 797 798 static void 799 sk_marv_miibus_statchg(sc_if) 800 struct sk_if_softc *sc_if; 801 { 802 return; 803 } 804 805 #define HASH_BITS 6 806 807 static u_int32_t 808 sk_xmchash(addr) 809 const uint8_t *addr; 810 { 811 uint32_t crc; 812 813 /* Compute CRC for the address value. */ 814 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 815 816 return (~crc & ((1 << HASH_BITS) - 1)); 817 } 818 819 /* gmchash is just a big endian crc */ 820 static u_int32_t 821 sk_gmchash(addr) 822 const uint8_t *addr; 823 { 824 uint32_t crc; 825 826 /* Compute CRC for the address value. */ 827 crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 828 829 return (crc & ((1 << HASH_BITS) - 1)); 830 } 831 832 static void 833 sk_setfilt(sc_if, addr, slot) 834 struct sk_if_softc *sc_if; 835 u_int16_t *addr; 836 int slot; 837 { 838 int base; 839 840 base = XM_RXFILT_ENTRY(slot); 841 842 SK_XM_WRITE_2(sc_if, base, addr[0]); 843 SK_XM_WRITE_2(sc_if, base + 2, addr[1]); 844 SK_XM_WRITE_2(sc_if, base + 4, addr[2]); 845 846 return; 847 } 848 849 static void 850 sk_setmulti(sc_if) 851 struct sk_if_softc *sc_if; 852 { 853 struct sk_softc *sc = sc_if->sk_softc; 854 struct ifnet *ifp = sc_if->sk_ifp; 855 u_int32_t hashes[2] = { 0, 0 }; 856 int h = 0, i; 857 struct ifmultiaddr *ifma; 858 u_int16_t dummy[] = { 0, 0, 0 }; 859 u_int16_t maddr[(ETHER_ADDR_LEN+1)/2]; 860 861 SK_IF_LOCK_ASSERT(sc_if); 862 863 /* First, zot all the existing filters. */ 864 switch(sc->sk_type) { 865 case SK_GENESIS: 866 for (i = 1; i < XM_RXFILT_MAX; i++) 867 sk_setfilt(sc_if, dummy, i); 868 869 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 870 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 871 break; 872 case SK_YUKON: 873 case SK_YUKON_LITE: 874 case SK_YUKON_LP: 875 case SK_YUKON_EC: 876 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 877 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 878 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 879 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 880 break; 881 } 882 883 /* Now program new ones. */ 884 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 885 hashes[0] = 0xFFFFFFFF; 886 hashes[1] = 0xFFFFFFFF; 887 } else { 888 i = 1; 889 IF_ADDR_LOCK(ifp); 890 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, ifma_link) { 891 if (ifma->ifma_addr->sa_family != AF_LINK) 892 continue; 893 /* 894 * Program the first XM_RXFILT_MAX multicast groups 895 * into the perfect filter. For all others, 896 * use the hash table. 897 */ 898 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) { 899 bcopy(LLADDR( 900 (struct sockaddr_dl *)ifma->ifma_addr), 901 maddr, ETHER_ADDR_LEN); 902 sk_setfilt(sc_if, maddr, i); 903 i++; 904 continue; 905 } 906 907 switch(sc->sk_type) { 908 case SK_GENESIS: 909 bcopy(LLADDR( 910 (struct sockaddr_dl *)ifma->ifma_addr), 911 maddr, ETHER_ADDR_LEN); 912 h = sk_xmchash((const uint8_t *)maddr); 913 break; 914 case SK_YUKON: 915 case SK_YUKON_LITE: 916 case SK_YUKON_LP: 917 case SK_YUKON_EC: 918 bcopy(LLADDR( 919 (struct sockaddr_dl *)ifma->ifma_addr), 920 maddr, ETHER_ADDR_LEN); 921 h = sk_gmchash((const uint8_t *)maddr); 922 break; 923 } 924 if (h < 32) 925 hashes[0] |= (1 << h); 926 else 927 hashes[1] |= (1 << (h - 32)); 928 } 929 IF_ADDR_UNLOCK(ifp); 930 } 931 932 switch(sc->sk_type) { 933 case SK_GENESIS: 934 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 935 XM_MODE_RX_USE_PERFECT); 936 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 937 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 938 break; 939 case SK_YUKON: 940 case SK_YUKON_LITE: 941 case SK_YUKON_LP: 942 case SK_YUKON_EC: 943 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 944 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 945 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 946 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 947 break; 948 } 949 950 return; 951 } 952 953 static void 954 sk_setpromisc(sc_if) 955 struct sk_if_softc *sc_if; 956 { 957 struct sk_softc *sc = sc_if->sk_softc; 958 struct ifnet *ifp = sc_if->sk_ifp; 959 960 SK_IF_LOCK_ASSERT(sc_if); 961 962 switch(sc->sk_type) { 963 case SK_GENESIS: 964 if (ifp->if_flags & IFF_PROMISC) { 965 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 966 } else { 967 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 968 } 969 break; 970 case SK_YUKON: 971 case SK_YUKON_LITE: 972 case SK_YUKON_LP: 973 case SK_YUKON_EC: 974 if (ifp->if_flags & IFF_PROMISC) { 975 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 976 YU_RCR_UFLEN | YU_RCR_MUFLEN); 977 } else { 978 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 979 YU_RCR_UFLEN | YU_RCR_MUFLEN); 980 } 981 break; 982 } 983 984 return; 985 } 986 987 static int 988 sk_init_rx_ring(sc_if) 989 struct sk_if_softc *sc_if; 990 { 991 struct sk_ring_data *rd; 992 bus_addr_t addr; 993 u_int32_t csum_start; 994 int i; 995 996 sc_if->sk_cdata.sk_rx_cons = 0; 997 998 csum_start = (ETHER_HDR_LEN + sizeof(struct ip)) << 16 | 999 ETHER_HDR_LEN; 1000 rd = &sc_if->sk_rdata; 1001 bzero(rd->sk_rx_ring, sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 1002 for (i = 0; i < SK_RX_RING_CNT; i++) { 1003 if (sk_newbuf(sc_if, i) != 0) 1004 return (ENOBUFS); 1005 if (i == (SK_RX_RING_CNT - 1)) 1006 addr = SK_RX_RING_ADDR(sc_if, 0); 1007 else 1008 addr = SK_RX_RING_ADDR(sc_if, i + 1); 1009 rd->sk_rx_ring[i].sk_next = htole32(SK_ADDR_LO(addr)); 1010 rd->sk_rx_ring[i].sk_csum_start = htole32(csum_start); 1011 } 1012 1013 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag, 1014 sc_if->sk_cdata.sk_rx_ring_map, 1015 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1016 1017 return(0); 1018 } 1019 1020 static int 1021 sk_init_jumbo_rx_ring(sc_if) 1022 struct sk_if_softc *sc_if; 1023 { 1024 struct sk_ring_data *rd; 1025 bus_addr_t addr; 1026 u_int32_t csum_start; 1027 int i; 1028 1029 sc_if->sk_cdata.sk_jumbo_rx_cons = 0; 1030 1031 csum_start = ((ETHER_HDR_LEN + sizeof(struct ip)) << 16) | 1032 ETHER_HDR_LEN; 1033 rd = &sc_if->sk_rdata; 1034 bzero(rd->sk_jumbo_rx_ring, 1035 sizeof(struct sk_rx_desc) * SK_JUMBO_RX_RING_CNT); 1036 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) { 1037 if (sk_jumbo_newbuf(sc_if, i) != 0) 1038 return (ENOBUFS); 1039 if (i == (SK_JUMBO_RX_RING_CNT - 1)) 1040 addr = SK_JUMBO_RX_RING_ADDR(sc_if, 0); 1041 else 1042 addr = SK_JUMBO_RX_RING_ADDR(sc_if, i + 1); 1043 rd->sk_jumbo_rx_ring[i].sk_next = htole32(SK_ADDR_LO(addr)); 1044 rd->sk_jumbo_rx_ring[i].sk_csum_start = htole32(csum_start); 1045 } 1046 1047 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 1048 sc_if->sk_cdata.sk_jumbo_rx_ring_map, 1049 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1050 1051 return (0); 1052 } 1053 1054 static void 1055 sk_init_tx_ring(sc_if) 1056 struct sk_if_softc *sc_if; 1057 { 1058 struct sk_ring_data *rd; 1059 struct sk_txdesc *txd; 1060 bus_addr_t addr; 1061 int i; 1062 1063 STAILQ_INIT(&sc_if->sk_cdata.sk_txfreeq); 1064 STAILQ_INIT(&sc_if->sk_cdata.sk_txbusyq); 1065 1066 sc_if->sk_cdata.sk_tx_prod = 0; 1067 sc_if->sk_cdata.sk_tx_cons = 0; 1068 sc_if->sk_cdata.sk_tx_cnt = 0; 1069 1070 rd = &sc_if->sk_rdata; 1071 bzero(rd->sk_tx_ring, sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 1072 for (i = 0; i < SK_TX_RING_CNT; i++) { 1073 if (i == (SK_TX_RING_CNT - 1)) 1074 addr = SK_TX_RING_ADDR(sc_if, 0); 1075 else 1076 addr = SK_TX_RING_ADDR(sc_if, i + 1); 1077 rd->sk_tx_ring[i].sk_next = htole32(SK_ADDR_LO(addr)); 1078 txd = &sc_if->sk_cdata.sk_txdesc[i]; 1079 STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txfreeq, txd, tx_q); 1080 } 1081 1082 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag, 1083 sc_if->sk_cdata.sk_tx_ring_map, 1084 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1085 } 1086 1087 static __inline void 1088 sk_discard_rxbuf(sc_if, idx) 1089 struct sk_if_softc *sc_if; 1090 int idx; 1091 { 1092 struct sk_rx_desc *r; 1093 struct sk_rxdesc *rxd; 1094 struct mbuf *m; 1095 1096 1097 r = &sc_if->sk_rdata.sk_rx_ring[idx]; 1098 rxd = &sc_if->sk_cdata.sk_rxdesc[idx]; 1099 m = rxd->rx_m; 1100 r->sk_ctl = htole32(m->m_len | SK_RXSTAT | SK_OPCODE_CSUM); 1101 } 1102 1103 static __inline void 1104 sk_discard_jumbo_rxbuf(sc_if, idx) 1105 struct sk_if_softc *sc_if; 1106 int idx; 1107 { 1108 struct sk_rx_desc *r; 1109 struct sk_rxdesc *rxd; 1110 struct mbuf *m; 1111 1112 r = &sc_if->sk_rdata.sk_jumbo_rx_ring[idx]; 1113 rxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[idx]; 1114 m = rxd->rx_m; 1115 r->sk_ctl = htole32(m->m_len | SK_RXSTAT | SK_OPCODE_CSUM); 1116 } 1117 1118 static int 1119 sk_newbuf(sc_if, idx) 1120 struct sk_if_softc *sc_if; 1121 int idx; 1122 { 1123 struct sk_rx_desc *r; 1124 struct sk_rxdesc *rxd; 1125 struct mbuf *m; 1126 bus_dma_segment_t segs[1]; 1127 bus_dmamap_t map; 1128 int nsegs; 1129 1130 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1131 if (m == NULL) 1132 return (ENOBUFS); 1133 m->m_len = m->m_pkthdr.len = MCLBYTES; 1134 m_adj(m, ETHER_ALIGN); 1135 1136 if (bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_rx_tag, 1137 sc_if->sk_cdata.sk_rx_sparemap, m, segs, &nsegs, 0) != 0) { 1138 m_freem(m); 1139 return (ENOBUFS); 1140 } 1141 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1142 1143 rxd = &sc_if->sk_cdata.sk_rxdesc[idx]; 1144 if (rxd->rx_m != NULL) { 1145 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap, 1146 BUS_DMASYNC_POSTREAD); 1147 bus_dmamap_unload(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap); 1148 } 1149 map = rxd->rx_dmamap; 1150 rxd->rx_dmamap = sc_if->sk_cdata.sk_rx_sparemap; 1151 sc_if->sk_cdata.sk_rx_sparemap = map; 1152 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap, 1153 BUS_DMASYNC_PREREAD); 1154 rxd->rx_m = m; 1155 r = &sc_if->sk_rdata.sk_rx_ring[idx]; 1156 r->sk_data_lo = htole32(SK_ADDR_LO(segs[0].ds_addr)); 1157 r->sk_data_hi = htole32(SK_ADDR_HI(segs[0].ds_addr)); 1158 r->sk_ctl = htole32(segs[0].ds_len | SK_RXSTAT | SK_OPCODE_CSUM); 1159 1160 return (0); 1161 } 1162 1163 static int 1164 sk_jumbo_newbuf(sc_if, idx) 1165 struct sk_if_softc *sc_if; 1166 int idx; 1167 { 1168 struct sk_rx_desc *r; 1169 struct sk_rxdesc *rxd; 1170 struct mbuf *m; 1171 bus_dma_segment_t segs[1]; 1172 bus_dmamap_t map; 1173 int nsegs; 1174 void *buf; 1175 1176 MGETHDR(m, M_DONTWAIT, MT_DATA); 1177 if (m == NULL) 1178 return (ENOBUFS); 1179 buf = sk_jalloc(sc_if); 1180 if (buf == NULL) { 1181 m_freem(m); 1182 return (ENOBUFS); 1183 } 1184 /* Attach the buffer to the mbuf */ 1185 MEXTADD(m, buf, SK_JLEN, sk_jfree, (struct sk_if_softc *)sc_if, 0, 1186 EXT_NET_DRV); 1187 if ((m->m_flags & M_EXT) == 0) { 1188 m_freem(m); 1189 return (ENOBUFS); 1190 } 1191 m->m_pkthdr.len = m->m_len = SK_JLEN; 1192 /* 1193 * Adjust alignment so packet payload begins on a 1194 * longword boundary. Mandatory for Alpha, useful on 1195 * x86 too. 1196 */ 1197 m_adj(m, ETHER_ALIGN); 1198 1199 if (bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_jumbo_rx_tag, 1200 sc_if->sk_cdata.sk_jumbo_rx_sparemap, m, segs, &nsegs, 0) != 0) { 1201 m_freem(m); 1202 return (ENOBUFS); 1203 } 1204 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1205 1206 rxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[idx]; 1207 if (rxd->rx_m != NULL) { 1208 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag, rxd->rx_dmamap, 1209 BUS_DMASYNC_POSTREAD); 1210 bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_tag, 1211 rxd->rx_dmamap); 1212 } 1213 map = rxd->rx_dmamap; 1214 rxd->rx_dmamap = sc_if->sk_cdata.sk_jumbo_rx_sparemap; 1215 sc_if->sk_cdata.sk_jumbo_rx_sparemap = map; 1216 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag, rxd->rx_dmamap, 1217 BUS_DMASYNC_PREREAD); 1218 rxd->rx_m = m; 1219 r = &sc_if->sk_rdata.sk_jumbo_rx_ring[idx]; 1220 r->sk_data_lo = htole32(SK_ADDR_LO(segs[0].ds_addr)); 1221 r->sk_data_hi = htole32(SK_ADDR_HI(segs[0].ds_addr)); 1222 r->sk_ctl = htole32(segs[0].ds_len | SK_RXSTAT | SK_OPCODE_CSUM); 1223 1224 return (0); 1225 } 1226 1227 /* 1228 * Set media options. 1229 */ 1230 static int 1231 sk_ifmedia_upd(ifp) 1232 struct ifnet *ifp; 1233 { 1234 struct sk_if_softc *sc_if = ifp->if_softc; 1235 struct mii_data *mii; 1236 1237 mii = device_get_softc(sc_if->sk_miibus); 1238 sk_init(sc_if); 1239 mii_mediachg(mii); 1240 1241 return(0); 1242 } 1243 1244 /* 1245 * Report current media status. 1246 */ 1247 static void 1248 sk_ifmedia_sts(ifp, ifmr) 1249 struct ifnet *ifp; 1250 struct ifmediareq *ifmr; 1251 { 1252 struct sk_if_softc *sc_if; 1253 struct mii_data *mii; 1254 1255 sc_if = ifp->if_softc; 1256 mii = device_get_softc(sc_if->sk_miibus); 1257 1258 mii_pollstat(mii); 1259 ifmr->ifm_active = mii->mii_media_active; 1260 ifmr->ifm_status = mii->mii_media_status; 1261 1262 return; 1263 } 1264 1265 static int 1266 sk_ioctl(ifp, command, data) 1267 struct ifnet *ifp; 1268 u_long command; 1269 caddr_t data; 1270 { 1271 struct sk_if_softc *sc_if = ifp->if_softc; 1272 struct ifreq *ifr = (struct ifreq *) data; 1273 int error, mask; 1274 struct mii_data *mii; 1275 1276 error = 0; 1277 switch(command) { 1278 case SIOCSIFMTU: 1279 SK_IF_LOCK(sc_if); 1280 if (ifr->ifr_mtu > SK_JUMBO_MTU) 1281 error = EINVAL; 1282 else { 1283 ifp->if_mtu = ifr->ifr_mtu; 1284 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1285 sk_init_locked(sc_if); 1286 } 1287 SK_IF_UNLOCK(sc_if); 1288 break; 1289 case SIOCSIFFLAGS: 1290 SK_IF_LOCK(sc_if); 1291 if (ifp->if_flags & IFF_UP) { 1292 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1293 if ((ifp->if_flags ^ sc_if->sk_if_flags) 1294 & IFF_PROMISC) { 1295 sk_setpromisc(sc_if); 1296 sk_setmulti(sc_if); 1297 } 1298 } else 1299 sk_init_locked(sc_if); 1300 } else { 1301 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1302 sk_stop(sc_if); 1303 } 1304 sc_if->sk_if_flags = ifp->if_flags; 1305 SK_IF_UNLOCK(sc_if); 1306 break; 1307 case SIOCADDMULTI: 1308 case SIOCDELMULTI: 1309 SK_IF_LOCK(sc_if); 1310 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1311 sk_setmulti(sc_if); 1312 SK_IF_UNLOCK(sc_if); 1313 break; 1314 case SIOCGIFMEDIA: 1315 case SIOCSIFMEDIA: 1316 mii = device_get_softc(sc_if->sk_miibus); 1317 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1318 break; 1319 case SIOCSIFCAP: 1320 SK_IF_LOCK(sc_if); 1321 if (sc_if->sk_softc->sk_type == SK_GENESIS) { 1322 SK_IF_UNLOCK(sc_if); 1323 break; 1324 } 1325 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1326 if (mask & IFCAP_HWCSUM) { 1327 ifp->if_capenable ^= IFCAP_HWCSUM; 1328 if (IFCAP_HWCSUM & ifp->if_capenable && 1329 IFCAP_HWCSUM & ifp->if_capabilities) 1330 ifp->if_hwassist = SK_CSUM_FEATURES; 1331 else 1332 ifp->if_hwassist = 0; 1333 } 1334 SK_IF_UNLOCK(sc_if); 1335 break; 1336 default: 1337 error = ether_ioctl(ifp, command, data); 1338 break; 1339 } 1340 1341 return (error); 1342 } 1343 1344 /* 1345 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 1346 * IDs against our list and return a device name if we find a match. 1347 */ 1348 static int 1349 skc_probe(dev) 1350 device_t dev; 1351 { 1352 struct sk_type *t = sk_devs; 1353 1354 while(t->sk_name != NULL) { 1355 if ((pci_get_vendor(dev) == t->sk_vid) && 1356 (pci_get_device(dev) == t->sk_did)) { 1357 /* 1358 * Only attach to rev. 2 of the Linksys EG1032 adapter. 1359 * Rev. 3 is supported by re(4). 1360 */ 1361 if ((t->sk_vid == VENDORID_LINKSYS) && 1362 (t->sk_did == DEVICEID_LINKSYS_EG1032) && 1363 (pci_get_subdevice(dev) != 1364 SUBDEVICEID_LINKSYS_EG1032_REV2)) { 1365 t++; 1366 continue; 1367 } 1368 device_set_desc(dev, t->sk_name); 1369 return (BUS_PROBE_DEFAULT); 1370 } 1371 t++; 1372 } 1373 1374 return(ENXIO); 1375 } 1376 1377 /* 1378 * Force the GEnesis into reset, then bring it out of reset. 1379 */ 1380 static void 1381 sk_reset(sc) 1382 struct sk_softc *sc; 1383 { 1384 1385 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 1386 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 1387 if (SK_YUKON_FAMILY(sc->sk_type)) 1388 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 1389 1390 DELAY(1000); 1391 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 1392 DELAY(2); 1393 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1394 if (SK_YUKON_FAMILY(sc->sk_type)) 1395 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 1396 1397 if (sc->sk_type == SK_GENESIS) { 1398 /* Configure packet arbiter */ 1399 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1400 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1401 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1402 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1403 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1404 } 1405 1406 /* Enable RAM interface */ 1407 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1408 1409 /* 1410 * Configure interrupt moderation. The moderation timer 1411 * defers interrupts specified in the interrupt moderation 1412 * timer mask based on the timeout specified in the interrupt 1413 * moderation timer init register. Each bit in the timer 1414 * register represents one tick, so to specify a timeout in 1415 * microseconds, we have to multiply by the correct number of 1416 * ticks-per-microsecond. 1417 */ 1418 switch (sc->sk_type) { 1419 case SK_GENESIS: 1420 sc->sk_int_ticks = SK_IMTIMER_TICKS_GENESIS; 1421 break; 1422 case SK_YUKON_EC: 1423 sc->sk_int_ticks = SK_IMTIMER_TICKS_YUKON_EC; 1424 break; 1425 default: 1426 sc->sk_int_ticks = SK_IMTIMER_TICKS_YUKON; 1427 break; 1428 } 1429 if (bootverbose) 1430 device_printf(sc->sk_dev, "interrupt moderation is %d us\n", 1431 sc->sk_int_mod); 1432 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod, 1433 sc->sk_int_ticks)); 1434 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 1435 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 1436 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1437 1438 return; 1439 } 1440 1441 static int 1442 sk_probe(dev) 1443 device_t dev; 1444 { 1445 struct sk_softc *sc; 1446 1447 sc = device_get_softc(device_get_parent(dev)); 1448 1449 /* 1450 * Not much to do here. We always know there will be 1451 * at least one XMAC present, and if there are two, 1452 * skc_attach() will create a second device instance 1453 * for us. 1454 */ 1455 switch (sc->sk_type) { 1456 case SK_GENESIS: 1457 device_set_desc(dev, "XaQti Corp. XMAC II"); 1458 break; 1459 case SK_YUKON: 1460 case SK_YUKON_LITE: 1461 case SK_YUKON_LP: 1462 case SK_YUKON_EC: 1463 device_set_desc(dev, "Marvell Semiconductor, Inc. Yukon"); 1464 break; 1465 } 1466 1467 return (BUS_PROBE_DEFAULT); 1468 } 1469 1470 /* 1471 * Each XMAC chip is attached as a separate logical IP interface. 1472 * Single port cards will have only one logical interface of course. 1473 */ 1474 static int 1475 sk_attach(dev) 1476 device_t dev; 1477 { 1478 struct sk_softc *sc; 1479 struct sk_if_softc *sc_if; 1480 struct ifnet *ifp; 1481 int i, port, error; 1482 u_char eaddr[6]; 1483 1484 if (dev == NULL) 1485 return(EINVAL); 1486 1487 error = 0; 1488 sc_if = device_get_softc(dev); 1489 sc = device_get_softc(device_get_parent(dev)); 1490 port = *(int *)device_get_ivars(dev); 1491 1492 sc_if->sk_if_dev = dev; 1493 sc_if->sk_port = port; 1494 sc_if->sk_softc = sc; 1495 sc->sk_if[port] = sc_if; 1496 if (port == SK_PORT_A) 1497 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1498 if (port == SK_PORT_B) 1499 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1500 1501 callout_init_mtx(&sc_if->sk_tick_ch, &sc_if->sk_softc->sk_mtx, 0); 1502 1503 if (sk_dma_alloc(sc_if) != 0) { 1504 error = ENOMEM; 1505 goto fail; 1506 } 1507 1508 ifp = sc_if->sk_ifp = if_alloc(IFT_ETHER); 1509 if (ifp == NULL) { 1510 device_printf(sc_if->sk_if_dev, "can not if_alloc()\n"); 1511 error = ENOSPC; 1512 goto fail; 1513 } 1514 ifp->if_softc = sc_if; 1515 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1516 ifp->if_mtu = ETHERMTU; 1517 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1518 /* 1519 * SK_GENESIS has a bug in checksum offload - From linux. 1520 */ 1521 if (sc_if->sk_softc->sk_type != SK_GENESIS) { 1522 ifp->if_capabilities = IFCAP_HWCSUM; 1523 ifp->if_hwassist = SK_CSUM_FEATURES; 1524 } else { 1525 ifp->if_capabilities = 0; 1526 ifp->if_hwassist = 0; 1527 } 1528 ifp->if_capenable = ifp->if_capabilities; 1529 ifp->if_ioctl = sk_ioctl; 1530 ifp->if_start = sk_start; 1531 ifp->if_watchdog = sk_watchdog; 1532 ifp->if_init = sk_init; 1533 IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1); 1534 ifp->if_snd.ifq_drv_maxlen = SK_TX_RING_CNT - 1; 1535 IFQ_SET_READY(&ifp->if_snd); 1536 1537 /* 1538 * Get station address for this interface. Note that 1539 * dual port cards actually come with three station 1540 * addresses: one for each port, plus an extra. The 1541 * extra one is used by the SysKonnect driver software 1542 * as a 'virtual' station address for when both ports 1543 * are operating in failover mode. Currently we don't 1544 * use this extra address. 1545 */ 1546 SK_IF_LOCK(sc_if); 1547 for (i = 0; i < ETHER_ADDR_LEN; i++) 1548 eaddr[i] = 1549 sk_win_read_1(sc, SK_MAC0_0 + (port * 8) + i); 1550 1551 /* 1552 * Set up RAM buffer addresses. The NIC will have a certain 1553 * amount of SRAM on it, somewhere between 512K and 2MB. We 1554 * need to divide this up a) between the transmitter and 1555 * receiver and b) between the two XMACs, if this is a 1556 * dual port NIC. Our algotithm is to divide up the memory 1557 * evenly so that everyone gets a fair share. 1558 * 1559 * Just to be contrary, Yukon2 appears to have separate memory 1560 * for each MAC. 1561 */ 1562 if (SK_IS_YUKON2(sc) || 1563 sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1564 u_int32_t chunk, val; 1565 1566 chunk = sc->sk_ramsize / 2; 1567 val = sc->sk_rboff / sizeof(u_int64_t); 1568 sc_if->sk_rx_ramstart = val; 1569 val += (chunk / sizeof(u_int64_t)); 1570 sc_if->sk_rx_ramend = val - 1; 1571 sc_if->sk_tx_ramstart = val; 1572 val += (chunk / sizeof(u_int64_t)); 1573 sc_if->sk_tx_ramend = val - 1; 1574 } else { 1575 u_int32_t chunk, val; 1576 1577 chunk = sc->sk_ramsize / 4; 1578 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1579 sizeof(u_int64_t); 1580 sc_if->sk_rx_ramstart = val; 1581 val += (chunk / sizeof(u_int64_t)); 1582 sc_if->sk_rx_ramend = val - 1; 1583 sc_if->sk_tx_ramstart = val; 1584 val += (chunk / sizeof(u_int64_t)); 1585 sc_if->sk_tx_ramend = val - 1; 1586 } 1587 1588 /* Read and save PHY type and set PHY address */ 1589 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1590 if (!SK_YUKON_FAMILY(sc->sk_type)) { 1591 switch(sc_if->sk_phytype) { 1592 case SK_PHYTYPE_XMAC: 1593 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1594 break; 1595 case SK_PHYTYPE_BCOM: 1596 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1597 break; 1598 default: 1599 device_printf(sc->sk_dev, "unsupported PHY type: %d\n", 1600 sc_if->sk_phytype); 1601 error = ENODEV; 1602 SK_IF_UNLOCK(sc_if); 1603 goto fail; 1604 } 1605 } else { 1606 if (sc_if->sk_phytype < SK_PHYTYPE_MARV_COPPER && 1607 sc->sk_pmd != 'S') { 1608 /* not initialized, punt */ 1609 sc_if->sk_phytype = SK_PHYTYPE_MARV_COPPER; 1610 sc->sk_coppertype = 1; 1611 } 1612 1613 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1614 1615 if (!(sc->sk_coppertype)) 1616 sc_if->sk_phytype = SK_PHYTYPE_MARV_FIBER; 1617 } 1618 1619 /* 1620 * Call MI attach routine. Can't hold locks when calling into ether_*. 1621 */ 1622 SK_IF_UNLOCK(sc_if); 1623 ether_ifattach(ifp, eaddr); 1624 SK_IF_LOCK(sc_if); 1625 1626 /* 1627 * The hardware should be ready for VLAN_MTU by default: 1628 * XMAC II has 0x8100 in VLAN Tag Level 1 register initially; 1629 * YU_SMR_MFL_VLAN is set by this driver in Yukon. 1630 * 1631 */ 1632 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1633 ifp->if_capenable |= IFCAP_VLAN_MTU; 1634 /* 1635 * Tell the upper layer(s) we support long frames. 1636 * Must appear after the call to ether_ifattach() because 1637 * ether_ifattach() sets ifi_hdrlen to the default value. 1638 */ 1639 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1640 1641 /* 1642 * Do miibus setup. 1643 */ 1644 switch (sc->sk_type) { 1645 case SK_GENESIS: 1646 sk_init_xmac(sc_if); 1647 break; 1648 case SK_YUKON: 1649 case SK_YUKON_LITE: 1650 case SK_YUKON_LP: 1651 case SK_YUKON_EC: 1652 sk_init_yukon(sc_if); 1653 break; 1654 } 1655 1656 SK_IF_UNLOCK(sc_if); 1657 if (mii_phy_probe(dev, &sc_if->sk_miibus, 1658 sk_ifmedia_upd, sk_ifmedia_sts)) { 1659 device_printf(sc_if->sk_if_dev, "no PHY found!\n"); 1660 ether_ifdetach(ifp); 1661 error = ENXIO; 1662 goto fail; 1663 } 1664 1665 fail: 1666 if (error) { 1667 /* Access should be ok even though lock has been dropped */ 1668 sc->sk_if[port] = NULL; 1669 sk_detach(dev); 1670 } 1671 1672 return(error); 1673 } 1674 1675 /* 1676 * Attach the interface. Allocate softc structures, do ifmedia 1677 * setup and ethernet/BPF attach. 1678 */ 1679 static int 1680 skc_attach(dev) 1681 device_t dev; 1682 { 1683 struct sk_softc *sc; 1684 int error = 0, rid, *port, sk_macs; 1685 uint8_t skrs; 1686 char *pname, *revstr; 1687 1688 sc = device_get_softc(dev); 1689 sc->sk_dev = dev; 1690 1691 mtx_init(&sc->sk_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1692 MTX_DEF); 1693 mtx_init(&sc->sk_mii_mtx, "sk_mii_mutex", NULL, MTX_DEF); 1694 /* 1695 * Map control/status registers. 1696 */ 1697 pci_enable_busmaster(dev); 1698 1699 rid = SK_RID; 1700 sc->sk_res = bus_alloc_resource_any(dev, SK_RES, &rid, RF_ACTIVE); 1701 1702 if (sc->sk_res == NULL) { 1703 device_printf(dev, "couldn't map ports/memory\n"); 1704 error = ENXIO; 1705 goto fail; 1706 } 1707 1708 sc->sk_btag = rman_get_bustag(sc->sk_res); 1709 sc->sk_bhandle = rman_get_bushandle(sc->sk_res); 1710 1711 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1712 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4) & 0xf; 1713 1714 /* Bail out if chip is not recognized. */ 1715 if (sc->sk_type != SK_GENESIS && !SK_YUKON_FAMILY(sc->sk_type)) { 1716 device_printf(dev, "unknown device: chipver=%02x, rev=%x\n", 1717 sc->sk_type, sc->sk_rev); 1718 error = ENXIO; 1719 goto fail; 1720 } 1721 1722 /* Allocate interrupt */ 1723 rid = 0; 1724 sc->sk_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1725 RF_SHAREABLE | RF_ACTIVE); 1726 1727 if (sc->sk_irq == NULL) { 1728 device_printf(dev, "couldn't map interrupt\n"); 1729 error = ENXIO; 1730 goto fail; 1731 } 1732 1733 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 1734 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 1735 OID_AUTO, "int_mod", CTLTYPE_INT|CTLFLAG_RW, 1736 &sc->sk_int_mod, 0, sysctl_hw_sk_int_mod, "I", 1737 "SK interrupt moderation"); 1738 1739 /* Pull in device tunables. */ 1740 sc->sk_int_mod = SK_IM_DEFAULT; 1741 error = resource_int_value(device_get_name(dev), device_get_unit(dev), 1742 "int_mod", &sc->sk_int_mod); 1743 if (error == 0) { 1744 if (sc->sk_int_mod < SK_IM_MIN || 1745 sc->sk_int_mod > SK_IM_MAX) { 1746 device_printf(dev, "int_mod value out of range; " 1747 "using default: %d\n", SK_IM_DEFAULT); 1748 sc->sk_int_mod = SK_IM_DEFAULT; 1749 } 1750 } 1751 1752 /* Reset the adapter. */ 1753 sk_reset(sc); 1754 1755 /* Read and save vital product data from EEPROM. */ 1756 sk_vpd_read(sc); 1757 1758 skrs = sk_win_read_1(sc, SK_EPROM0); 1759 if (sc->sk_type == SK_GENESIS) { 1760 /* Read and save RAM size and RAMbuffer offset */ 1761 switch(skrs) { 1762 case SK_RAMSIZE_512K_64: 1763 sc->sk_ramsize = 0x80000; 1764 sc->sk_rboff = SK_RBOFF_0; 1765 break; 1766 case SK_RAMSIZE_1024K_64: 1767 sc->sk_ramsize = 0x100000; 1768 sc->sk_rboff = SK_RBOFF_80000; 1769 break; 1770 case SK_RAMSIZE_1024K_128: 1771 sc->sk_ramsize = 0x100000; 1772 sc->sk_rboff = SK_RBOFF_0; 1773 break; 1774 case SK_RAMSIZE_2048K_128: 1775 sc->sk_ramsize = 0x200000; 1776 sc->sk_rboff = SK_RBOFF_0; 1777 break; 1778 default: 1779 device_printf(dev, "unknown ram size: %d\n", skrs); 1780 error = ENXIO; 1781 goto fail; 1782 } 1783 } else { /* SK_YUKON_FAMILY */ 1784 if (skrs == 0x00) 1785 sc->sk_ramsize = 0x20000; 1786 else 1787 sc->sk_ramsize = skrs * (1<<12); 1788 sc->sk_rboff = SK_RBOFF_0; 1789 } 1790 1791 /* Read and save physical media type */ 1792 sc->sk_pmd = sk_win_read_1(sc, SK_PMDTYPE); 1793 1794 if (sc->sk_pmd == 'T' || sc->sk_pmd == '1') 1795 sc->sk_coppertype = 1; 1796 else 1797 sc->sk_coppertype = 0; 1798 1799 /* Determine whether to name it with VPD PN or just make it up. 1800 * Marvell Yukon VPD PN seems to freqently be bogus. */ 1801 switch (pci_get_device(dev)) { 1802 case DEVICEID_SK_V1: 1803 case DEVICEID_BELKIN_5005: 1804 case DEVICEID_3COM_3C940: 1805 case DEVICEID_LINKSYS_EG1032: 1806 case DEVICEID_DLINK_DGE530T: 1807 /* Stay with VPD PN. */ 1808 pname = sc->sk_vpd_prodname; 1809 break; 1810 case DEVICEID_SK_V2: 1811 case DEVICEID_MRVL_4360: 1812 case DEVICEID_MRVL_4361: 1813 case DEVICEID_MRVL_4362: 1814 /* YUKON VPD PN might bear no resemblance to reality. */ 1815 switch (sc->sk_type) { 1816 case SK_GENESIS: 1817 /* Stay with VPD PN. */ 1818 pname = sc->sk_vpd_prodname; 1819 break; 1820 case SK_YUKON: 1821 pname = "Marvell Yukon Gigabit Ethernet"; 1822 break; 1823 case SK_YUKON_LITE: 1824 pname = "Marvell Yukon Lite Gigabit Ethernet"; 1825 break; 1826 case SK_YUKON_LP: 1827 pname = "Marvell Yukon LP Gigabit Ethernet"; 1828 break; 1829 case SK_YUKON_EC: 1830 pname = "Marvell Yukon-2 EC Gigabit Ethernet"; 1831 break; 1832 default: 1833 pname = "Marvell Yukon (Unknown) Gigabit Ethernet"; 1834 break; 1835 } 1836 1837 /* Yukon Lite Rev. A0 needs special test. */ 1838 if (sc->sk_type == SK_YUKON || sc->sk_type == SK_YUKON_LP) { 1839 u_int32_t far; 1840 u_int8_t testbyte; 1841 1842 /* Save flash address register before testing. */ 1843 far = sk_win_read_4(sc, SK_EP_ADDR); 1844 1845 sk_win_write_1(sc, SK_EP_ADDR+0x03, 0xff); 1846 testbyte = sk_win_read_1(sc, SK_EP_ADDR+0x03); 1847 1848 if (testbyte != 0x00) { 1849 /* Yukon Lite Rev. A0 detected. */ 1850 sc->sk_type = SK_YUKON_LITE; 1851 sc->sk_rev = SK_YUKON_LITE_REV_A0; 1852 /* Restore flash address register. */ 1853 sk_win_write_4(sc, SK_EP_ADDR, far); 1854 } 1855 } 1856 break; 1857 default: 1858 device_printf(dev, "unknown device: vendor=%04x, device=%04x, " 1859 "chipver=%02x, rev=%x\n", 1860 pci_get_vendor(dev), pci_get_device(dev), 1861 sc->sk_type, sc->sk_rev); 1862 error = ENXIO; 1863 goto fail; 1864 } 1865 1866 if (sc->sk_type == SK_YUKON_LITE) { 1867 switch (sc->sk_rev) { 1868 case SK_YUKON_LITE_REV_A0: 1869 revstr = "A0"; 1870 break; 1871 case SK_YUKON_LITE_REV_A1: 1872 revstr = "A1"; 1873 break; 1874 case SK_YUKON_LITE_REV_A3: 1875 revstr = "A3"; 1876 break; 1877 default: 1878 revstr = ""; 1879 break; 1880 } 1881 } else if (sc->sk_type == SK_YUKON_EC) { 1882 switch (sc->sk_rev) { 1883 case SK_YUKON_EC_REV_A1: 1884 revstr = "A1"; 1885 break; 1886 case SK_YUKON_EC_REV_A2: 1887 revstr = "A2"; 1888 break; 1889 case SK_YUKON_EC_REV_A3: 1890 revstr = "A3"; 1891 break; 1892 default: 1893 revstr = ""; 1894 break; 1895 } 1896 } else { 1897 revstr = ""; 1898 } 1899 1900 /* Announce the product name and more VPD data if there. */ 1901 device_printf(dev, "%s rev. %s(0x%x)\n", 1902 pname != NULL ? pname : "<unknown>", revstr, sc->sk_rev); 1903 1904 if (bootverbose) { 1905 if (sc->sk_vpd_readonly != NULL && 1906 sc->sk_vpd_readonly_len != 0) { 1907 char buf[256]; 1908 char *dp = sc->sk_vpd_readonly; 1909 uint16_t l, len = sc->sk_vpd_readonly_len; 1910 1911 while (len >= 3) { 1912 if ((*dp == 'P' && *(dp+1) == 'N') || 1913 (*dp == 'E' && *(dp+1) == 'C') || 1914 (*dp == 'M' && *(dp+1) == 'N') || 1915 (*dp == 'S' && *(dp+1) == 'N')) { 1916 l = 0; 1917 while (l < *(dp+2)) { 1918 buf[l] = *(dp+3+l); 1919 ++l; 1920 } 1921 buf[l] = '\0'; 1922 device_printf(dev, "%c%c: %s\n", 1923 *dp, *(dp+1), buf); 1924 len -= (3 + l); 1925 dp += (3 + l); 1926 } else { 1927 len -= (3 + *(dp+2)); 1928 dp += (3 + *(dp+2)); 1929 } 1930 } 1931 } 1932 device_printf(dev, "chip ver = 0x%02x\n", sc->sk_type); 1933 device_printf(dev, "chip rev = 0x%02x\n", sc->sk_rev); 1934 device_printf(dev, "SK_EPROM0 = 0x%02x\n", skrs); 1935 device_printf(dev, "SRAM size = 0x%06x\n", sc->sk_ramsize); 1936 } 1937 1938 sc->sk_devs[SK_PORT_A] = device_add_child(dev, "sk", -1); 1939 if (sc->sk_devs[SK_PORT_A] == NULL) { 1940 device_printf(dev, "failed to add child for PORT_A\n"); 1941 error = ENXIO; 1942 goto fail; 1943 } 1944 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT); 1945 if (port == NULL) { 1946 device_printf(dev, "failed to allocate memory for " 1947 "ivars of PORT_A\n"); 1948 error = ENXIO; 1949 goto fail; 1950 } 1951 *port = SK_PORT_A; 1952 device_set_ivars(sc->sk_devs[SK_PORT_A], port); 1953 1954 sk_macs = 1; 1955 1956 if (SK_IS_YUKON2(sc)) { 1957 u_int8_t hw; 1958 1959 hw = sk_win_read_1(sc, SK_Y2_HWRES); 1960 if ((hw & SK_Y2_HWRES_LINK_MASK) == SK_Y2_HWRES_LINK_DUAL) { 1961 if ((sk_win_read_1(sc, SK_Y2_CLKGATE) & 1962 SK_Y2_CLKGATE_LINK2_INACTIVE) == 0) 1963 sk_macs++; 1964 } 1965 } else { 1966 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) 1967 sk_macs++; 1968 } 1969 1970 if (sk_macs > 1) { 1971 sc->sk_devs[SK_PORT_B] = device_add_child(dev, "sk", -1); 1972 if (sc->sk_devs[SK_PORT_B] == NULL) { 1973 device_printf(dev, "failed to add child for PORT_B\n"); 1974 error = ENXIO; 1975 goto fail; 1976 } 1977 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT); 1978 if (port == NULL) { 1979 device_printf(dev, "failed to allocate memory for " 1980 "ivars of PORT_B\n"); 1981 error = ENXIO; 1982 goto fail; 1983 } 1984 *port = SK_PORT_B; 1985 device_set_ivars(sc->sk_devs[SK_PORT_B], port); 1986 } 1987 1988 /* Turn on the 'driver is loaded' LED. */ 1989 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1990 1991 error = bus_generic_attach(dev); 1992 if (error) { 1993 device_printf(dev, "failed to attach port(s)\n"); 1994 goto fail; 1995 } 1996 1997 /* Hook interrupt last to avoid having to lock softc */ 1998 error = bus_setup_intr(dev, sc->sk_irq, INTR_TYPE_NET|INTR_MPSAFE, 1999 sk_intr, sc, &sc->sk_intrhand); 2000 2001 if (error) { 2002 device_printf(dev, "couldn't set up irq\n"); 2003 goto fail; 2004 } 2005 2006 fail: 2007 if (error) 2008 skc_detach(dev); 2009 2010 return(error); 2011 } 2012 2013 /* 2014 * Shutdown hardware and free up resources. This can be called any 2015 * time after the mutex has been initialized. It is called in both 2016 * the error case in attach and the normal detach case so it needs 2017 * to be careful about only freeing resources that have actually been 2018 * allocated. 2019 */ 2020 static int 2021 sk_detach(dev) 2022 device_t dev; 2023 { 2024 struct sk_if_softc *sc_if; 2025 struct ifnet *ifp; 2026 2027 sc_if = device_get_softc(dev); 2028 KASSERT(mtx_initialized(&sc_if->sk_softc->sk_mtx), 2029 ("sk mutex not initialized in sk_detach")); 2030 SK_IF_LOCK(sc_if); 2031 2032 ifp = sc_if->sk_ifp; 2033 /* These should only be active if attach_xmac succeeded */ 2034 if (device_is_attached(dev)) { 2035 sk_stop(sc_if); 2036 /* Can't hold locks while calling detach */ 2037 SK_IF_UNLOCK(sc_if); 2038 callout_drain(&sc_if->sk_tick_ch); 2039 ether_ifdetach(ifp); 2040 SK_IF_LOCK(sc_if); 2041 } 2042 if (ifp) 2043 if_free(ifp); 2044 /* 2045 * We're generally called from skc_detach() which is using 2046 * device_delete_child() to get to here. It's already trashed 2047 * miibus for us, so don't do it here or we'll panic. 2048 */ 2049 /* 2050 if (sc_if->sk_miibus != NULL) 2051 device_delete_child(dev, sc_if->sk_miibus); 2052 */ 2053 bus_generic_detach(dev); 2054 sk_dma_free(sc_if); 2055 SK_IF_UNLOCK(sc_if); 2056 2057 return(0); 2058 } 2059 2060 static int 2061 skc_detach(dev) 2062 device_t dev; 2063 { 2064 struct sk_softc *sc; 2065 2066 sc = device_get_softc(dev); 2067 KASSERT(mtx_initialized(&sc->sk_mtx), ("sk mutex not initialized")); 2068 2069 if (device_is_alive(dev)) { 2070 if (sc->sk_devs[SK_PORT_A] != NULL) { 2071 free(device_get_ivars(sc->sk_devs[SK_PORT_A]), M_DEVBUF); 2072 device_delete_child(dev, sc->sk_devs[SK_PORT_A]); 2073 } 2074 if (sc->sk_devs[SK_PORT_B] != NULL) { 2075 free(device_get_ivars(sc->sk_devs[SK_PORT_B]), M_DEVBUF); 2076 device_delete_child(dev, sc->sk_devs[SK_PORT_B]); 2077 } 2078 bus_generic_detach(dev); 2079 } 2080 2081 if (sc->sk_vpd_prodname != NULL) 2082 free(sc->sk_vpd_prodname, M_DEVBUF); 2083 if (sc->sk_vpd_readonly != NULL) 2084 free(sc->sk_vpd_readonly, M_DEVBUF); 2085 2086 if (sc->sk_intrhand) 2087 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand); 2088 if (sc->sk_irq) 2089 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq); 2090 if (sc->sk_res) 2091 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res); 2092 2093 mtx_destroy(&sc->sk_mii_mtx); 2094 mtx_destroy(&sc->sk_mtx); 2095 2096 return(0); 2097 } 2098 2099 struct sk_dmamap_arg { 2100 bus_addr_t sk_busaddr; 2101 }; 2102 2103 static void 2104 sk_dmamap_cb(arg, segs, nseg, error) 2105 void *arg; 2106 bus_dma_segment_t *segs; 2107 int nseg; 2108 int error; 2109 { 2110 struct sk_dmamap_arg *ctx; 2111 2112 if (error != 0) 2113 return; 2114 2115 ctx = arg; 2116 ctx->sk_busaddr = segs[0].ds_addr; 2117 } 2118 2119 /* 2120 * Allocate jumbo buffer storage. The SysKonnect adapters support 2121 * "jumbograms" (9K frames), although SysKonnect doesn't currently 2122 * use them in their drivers. In order for us to use them, we need 2123 * large 9K receive buffers, however standard mbuf clusters are only 2124 * 2048 bytes in size. Consequently, we need to allocate and manage 2125 * our own jumbo buffer pool. Fortunately, this does not require an 2126 * excessive amount of additional code. 2127 */ 2128 static int 2129 sk_dma_alloc(sc_if) 2130 struct sk_if_softc *sc_if; 2131 { 2132 struct sk_dmamap_arg ctx; 2133 struct sk_txdesc *txd; 2134 struct sk_rxdesc *rxd; 2135 struct sk_rxdesc *jrxd; 2136 u_int8_t *ptr; 2137 struct sk_jpool_entry *entry; 2138 int error, i; 2139 2140 mtx_init(&sc_if->sk_jlist_mtx, "sk_jlist_mtx", NULL, MTX_DEF); 2141 SLIST_INIT(&sc_if->sk_jfree_listhead); 2142 SLIST_INIT(&sc_if->sk_jinuse_listhead); 2143 2144 /* create parent tag */ 2145 /* 2146 * XXX 2147 * This driver should use BUS_SPACE_MAXADDR for lowaddr argument 2148 * in bus_dma_tag_create(9) as the NIC would support DAC mode. 2149 * However bz@ reported that it does not work on amd64 with > 4GB 2150 * RAM. Until we have more clues of the breakage, disable DAC mode 2151 * by limiting DMA address to be in 32bit address space. 2152 */ 2153 error = bus_dma_tag_create(NULL, /* parent */ 2154 1, 0, /* algnmnt, boundary */ 2155 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 2156 BUS_SPACE_MAXADDR, /* highaddr */ 2157 NULL, NULL, /* filter, filterarg */ 2158 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 2159 0, /* nsegments */ 2160 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 2161 0, /* flags */ 2162 NULL, NULL, /* lockfunc, lockarg */ 2163 &sc_if->sk_cdata.sk_parent_tag); 2164 if (error != 0) { 2165 device_printf(sc_if->sk_if_dev, 2166 "failed to create parent DMA tag\n"); 2167 goto fail; 2168 } 2169 /* create tag for Tx ring */ 2170 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */ 2171 SK_RING_ALIGN, 0, /* algnmnt, boundary */ 2172 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 2173 BUS_SPACE_MAXADDR, /* highaddr */ 2174 NULL, NULL, /* filter, filterarg */ 2175 SK_TX_RING_SZ, /* maxsize */ 2176 1, /* nsegments */ 2177 SK_TX_RING_SZ, /* maxsegsize */ 2178 0, /* flags */ 2179 NULL, NULL, /* lockfunc, lockarg */ 2180 &sc_if->sk_cdata.sk_tx_ring_tag); 2181 if (error != 0) { 2182 device_printf(sc_if->sk_if_dev, 2183 "failed to allocate Tx ring DMA tag\n"); 2184 goto fail; 2185 } 2186 2187 /* create tag for Rx ring */ 2188 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */ 2189 SK_RING_ALIGN, 0, /* algnmnt, boundary */ 2190 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 2191 BUS_SPACE_MAXADDR, /* highaddr */ 2192 NULL, NULL, /* filter, filterarg */ 2193 SK_RX_RING_SZ, /* maxsize */ 2194 1, /* nsegments */ 2195 SK_RX_RING_SZ, /* maxsegsize */ 2196 0, /* flags */ 2197 NULL, NULL, /* lockfunc, lockarg */ 2198 &sc_if->sk_cdata.sk_rx_ring_tag); 2199 if (error != 0) { 2200 device_printf(sc_if->sk_if_dev, 2201 "failed to allocate Rx ring DMA tag\n"); 2202 goto fail; 2203 } 2204 2205 /* create tag for jumbo Rx ring */ 2206 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */ 2207 SK_RING_ALIGN, 0, /* algnmnt, boundary */ 2208 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 2209 BUS_SPACE_MAXADDR, /* highaddr */ 2210 NULL, NULL, /* filter, filterarg */ 2211 SK_JUMBO_RX_RING_SZ, /* maxsize */ 2212 1, /* nsegments */ 2213 SK_JUMBO_RX_RING_SZ, /* maxsegsize */ 2214 0, /* flags */ 2215 NULL, NULL, /* lockfunc, lockarg */ 2216 &sc_if->sk_cdata.sk_jumbo_rx_ring_tag); 2217 if (error != 0) { 2218 device_printf(sc_if->sk_if_dev, 2219 "failed to allocate jumbo Rx ring DMA tag\n"); 2220 goto fail; 2221 } 2222 2223 /* create tag for jumbo buffer blocks */ 2224 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */ 2225 PAGE_SIZE, 0, /* algnmnt, boundary */ 2226 BUS_SPACE_MAXADDR, /* lowaddr */ 2227 BUS_SPACE_MAXADDR, /* highaddr */ 2228 NULL, NULL, /* filter, filterarg */ 2229 SK_JMEM, /* maxsize */ 2230 1, /* nsegments */ 2231 SK_JMEM, /* maxsegsize */ 2232 0, /* flags */ 2233 NULL, NULL, /* lockfunc, lockarg */ 2234 &sc_if->sk_cdata.sk_jumbo_tag); 2235 if (error != 0) { 2236 device_printf(sc_if->sk_if_dev, 2237 "failed to allocate jumbo Rx buffer block DMA tag\n"); 2238 goto fail; 2239 } 2240 2241 /* create tag for Tx buffers */ 2242 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */ 2243 1, 0, /* algnmnt, boundary */ 2244 BUS_SPACE_MAXADDR, /* lowaddr */ 2245 BUS_SPACE_MAXADDR, /* highaddr */ 2246 NULL, NULL, /* filter, filterarg */ 2247 MCLBYTES * SK_MAXTXSEGS, /* maxsize */ 2248 SK_MAXTXSEGS, /* nsegments */ 2249 MCLBYTES, /* maxsegsize */ 2250 0, /* flags */ 2251 NULL, NULL, /* lockfunc, lockarg */ 2252 &sc_if->sk_cdata.sk_tx_tag); 2253 if (error != 0) { 2254 device_printf(sc_if->sk_if_dev, 2255 "failed to allocate Tx DMA tag\n"); 2256 goto fail; 2257 } 2258 2259 /* create tag for Rx buffers */ 2260 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */ 2261 1, 0, /* algnmnt, boundary */ 2262 BUS_SPACE_MAXADDR, /* lowaddr */ 2263 BUS_SPACE_MAXADDR, /* highaddr */ 2264 NULL, NULL, /* filter, filterarg */ 2265 MCLBYTES, /* maxsize */ 2266 1, /* nsegments */ 2267 MCLBYTES, /* maxsegsize */ 2268 0, /* flags */ 2269 NULL, NULL, /* lockfunc, lockarg */ 2270 &sc_if->sk_cdata.sk_rx_tag); 2271 if (error != 0) { 2272 device_printf(sc_if->sk_if_dev, 2273 "failed to allocate Rx DMA tag\n"); 2274 goto fail; 2275 } 2276 2277 /* create tag for jumbo Rx buffers */ 2278 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */ 2279 PAGE_SIZE, 0, /* algnmnt, boundary */ 2280 BUS_SPACE_MAXADDR, /* lowaddr */ 2281 BUS_SPACE_MAXADDR, /* highaddr */ 2282 NULL, NULL, /* filter, filterarg */ 2283 MCLBYTES * SK_MAXRXSEGS, /* maxsize */ 2284 SK_MAXRXSEGS, /* nsegments */ 2285 SK_JLEN, /* maxsegsize */ 2286 0, /* flags */ 2287 NULL, NULL, /* lockfunc, lockarg */ 2288 &sc_if->sk_cdata.sk_jumbo_rx_tag); 2289 if (error != 0) { 2290 device_printf(sc_if->sk_if_dev, 2291 "failed to allocate jumbo Rx DMA tag\n"); 2292 goto fail; 2293 } 2294 2295 /* allocate DMA'able memory and load the DMA map for Tx ring */ 2296 error = bus_dmamem_alloc(sc_if->sk_cdata.sk_tx_ring_tag, 2297 (void **)&sc_if->sk_rdata.sk_tx_ring, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 2298 &sc_if->sk_cdata.sk_tx_ring_map); 2299 if (error != 0) { 2300 device_printf(sc_if->sk_if_dev, 2301 "failed to allocate DMA'able memory for Tx ring\n"); 2302 goto fail; 2303 } 2304 2305 ctx.sk_busaddr = 0; 2306 error = bus_dmamap_load(sc_if->sk_cdata.sk_tx_ring_tag, 2307 sc_if->sk_cdata.sk_tx_ring_map, sc_if->sk_rdata.sk_tx_ring, 2308 SK_TX_RING_SZ, sk_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 2309 if (error != 0) { 2310 device_printf(sc_if->sk_if_dev, 2311 "failed to load DMA'able memory for Tx ring\n"); 2312 goto fail; 2313 } 2314 sc_if->sk_rdata.sk_tx_ring_paddr = ctx.sk_busaddr; 2315 2316 /* allocate DMA'able memory and load the DMA map for Rx ring */ 2317 error = bus_dmamem_alloc(sc_if->sk_cdata.sk_rx_ring_tag, 2318 (void **)&sc_if->sk_rdata.sk_rx_ring, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 2319 &sc_if->sk_cdata.sk_rx_ring_map); 2320 if (error != 0) { 2321 device_printf(sc_if->sk_if_dev, 2322 "failed to allocate DMA'able memory for Rx ring\n"); 2323 goto fail; 2324 } 2325 2326 ctx.sk_busaddr = 0; 2327 error = bus_dmamap_load(sc_if->sk_cdata.sk_rx_ring_tag, 2328 sc_if->sk_cdata.sk_rx_ring_map, sc_if->sk_rdata.sk_rx_ring, 2329 SK_RX_RING_SZ, sk_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 2330 if (error != 0) { 2331 device_printf(sc_if->sk_if_dev, 2332 "failed to load DMA'able memory for Rx ring\n"); 2333 goto fail; 2334 } 2335 sc_if->sk_rdata.sk_rx_ring_paddr = ctx.sk_busaddr; 2336 2337 /* allocate DMA'able memory and load the DMA map for jumbo Rx ring */ 2338 error = bus_dmamem_alloc(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 2339 (void **)&sc_if->sk_rdata.sk_jumbo_rx_ring, 2340 BUS_DMA_NOWAIT|BUS_DMA_ZERO, &sc_if->sk_cdata.sk_jumbo_rx_ring_map); 2341 if (error != 0) { 2342 device_printf(sc_if->sk_if_dev, 2343 "failed to allocate DMA'able memory for jumbo Rx ring\n"); 2344 goto fail; 2345 } 2346 2347 ctx.sk_busaddr = 0; 2348 error = bus_dmamap_load(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 2349 sc_if->sk_cdata.sk_jumbo_rx_ring_map, 2350 sc_if->sk_rdata.sk_jumbo_rx_ring, SK_JUMBO_RX_RING_SZ, sk_dmamap_cb, 2351 &ctx, BUS_DMA_NOWAIT); 2352 if (error != 0) { 2353 device_printf(sc_if->sk_if_dev, 2354 "failed to load DMA'able memory for jumbo Rx ring\n"); 2355 goto fail; 2356 } 2357 sc_if->sk_rdata.sk_jumbo_rx_ring_paddr = ctx.sk_busaddr; 2358 2359 /* create DMA maps for Tx buffers */ 2360 for (i = 0; i < SK_TX_RING_CNT; i++) { 2361 txd = &sc_if->sk_cdata.sk_txdesc[i]; 2362 txd->tx_m = NULL; 2363 txd->tx_dmamap = 0; 2364 error = bus_dmamap_create(sc_if->sk_cdata.sk_tx_tag, 0, 2365 &txd->tx_dmamap); 2366 if (error != 0) { 2367 device_printf(sc_if->sk_if_dev, 2368 "failed to create Tx dmamap\n"); 2369 goto fail; 2370 } 2371 } 2372 /* create DMA maps for Rx buffers */ 2373 if ((error = bus_dmamap_create(sc_if->sk_cdata.sk_rx_tag, 0, 2374 &sc_if->sk_cdata.sk_rx_sparemap)) != 0) { 2375 device_printf(sc_if->sk_if_dev, 2376 "failed to create spare Rx dmamap\n"); 2377 goto fail; 2378 } 2379 for (i = 0; i < SK_RX_RING_CNT; i++) { 2380 rxd = &sc_if->sk_cdata.sk_rxdesc[i]; 2381 rxd->rx_m = NULL; 2382 rxd->rx_dmamap = 0; 2383 error = bus_dmamap_create(sc_if->sk_cdata.sk_rx_tag, 0, 2384 &rxd->rx_dmamap); 2385 if (error != 0) { 2386 device_printf(sc_if->sk_if_dev, 2387 "failed to create Rx dmamap\n"); 2388 goto fail; 2389 } 2390 } 2391 /* create DMA maps for jumbo Rx buffers */ 2392 if ((error = bus_dmamap_create(sc_if->sk_cdata.sk_jumbo_rx_tag, 0, 2393 &sc_if->sk_cdata.sk_jumbo_rx_sparemap)) != 0) { 2394 device_printf(sc_if->sk_if_dev, 2395 "failed to create spare jumbo Rx dmamap\n"); 2396 goto fail; 2397 } 2398 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) { 2399 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i]; 2400 jrxd->rx_m = NULL; 2401 jrxd->rx_dmamap = 0; 2402 error = bus_dmamap_create(sc_if->sk_cdata.sk_jumbo_rx_tag, 0, 2403 &jrxd->rx_dmamap); 2404 if (error != 0) { 2405 device_printf(sc_if->sk_if_dev, 2406 "failed to create jumbo Rx dmamap\n"); 2407 goto fail; 2408 } 2409 } 2410 2411 /* allocate DMA'able memory and load the DMA map for jumbo buf */ 2412 error = bus_dmamem_alloc(sc_if->sk_cdata.sk_jumbo_tag, 2413 (void **)&sc_if->sk_rdata.sk_jumbo_buf, 2414 BUS_DMA_NOWAIT|BUS_DMA_ZERO, &sc_if->sk_cdata.sk_jumbo_map); 2415 if (error != 0) { 2416 device_printf(sc_if->sk_if_dev, 2417 "failed to allocate DMA'able memory for jumbo buf\n"); 2418 goto fail; 2419 } 2420 2421 ctx.sk_busaddr = 0; 2422 error = bus_dmamap_load(sc_if->sk_cdata.sk_jumbo_tag, 2423 sc_if->sk_cdata.sk_jumbo_map, 2424 sc_if->sk_rdata.sk_jumbo_buf, SK_JMEM, sk_dmamap_cb, 2425 &ctx, BUS_DMA_NOWAIT); 2426 if (error != 0) { 2427 device_printf(sc_if->sk_if_dev, 2428 "failed to load DMA'able memory for jumbobuf\n"); 2429 goto fail; 2430 } 2431 sc_if->sk_rdata.sk_jumbo_buf_paddr = ctx.sk_busaddr; 2432 2433 /* 2434 * Now divide it up into 9K pieces and save the addresses 2435 * in an array. 2436 */ 2437 ptr = sc_if->sk_rdata.sk_jumbo_buf; 2438 for (i = 0; i < SK_JSLOTS; i++) { 2439 sc_if->sk_cdata.sk_jslots[i] = ptr; 2440 ptr += SK_JLEN; 2441 entry = malloc(sizeof(struct sk_jpool_entry), 2442 M_DEVBUF, M_NOWAIT); 2443 if (entry == NULL) { 2444 device_printf(sc_if->sk_if_dev, 2445 "no memory for jumbo buffers!\n"); 2446 error = ENOMEM; 2447 goto fail; 2448 } 2449 entry->slot = i; 2450 SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, entry, 2451 jpool_entries); 2452 } 2453 2454 fail: 2455 return (error); 2456 } 2457 2458 static void 2459 sk_dma_free(sc_if) 2460 struct sk_if_softc *sc_if; 2461 { 2462 struct sk_txdesc *txd; 2463 struct sk_rxdesc *rxd; 2464 struct sk_rxdesc *jrxd; 2465 struct sk_jpool_entry *entry; 2466 int i; 2467 2468 SK_JLIST_LOCK(sc_if); 2469 while ((entry = SLIST_FIRST(&sc_if->sk_jinuse_listhead))) { 2470 device_printf(sc_if->sk_if_dev, 2471 "asked to free buffer that is in use!\n"); 2472 SLIST_REMOVE_HEAD(&sc_if->sk_jinuse_listhead, jpool_entries); 2473 SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, entry, 2474 jpool_entries); 2475 } 2476 2477 while (!SLIST_EMPTY(&sc_if->sk_jfree_listhead)) { 2478 entry = SLIST_FIRST(&sc_if->sk_jfree_listhead); 2479 SLIST_REMOVE_HEAD(&sc_if->sk_jfree_listhead, jpool_entries); 2480 free(entry, M_DEVBUF); 2481 } 2482 SK_JLIST_UNLOCK(sc_if); 2483 2484 /* destroy jumbo buffer block */ 2485 if (sc_if->sk_cdata.sk_jumbo_map) 2486 bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_tag, 2487 sc_if->sk_cdata.sk_jumbo_map); 2488 2489 if (sc_if->sk_rdata.sk_jumbo_buf) { 2490 bus_dmamem_free(sc_if->sk_cdata.sk_jumbo_tag, 2491 sc_if->sk_rdata.sk_jumbo_buf, 2492 sc_if->sk_cdata.sk_jumbo_map); 2493 sc_if->sk_rdata.sk_jumbo_buf = NULL; 2494 sc_if->sk_cdata.sk_jumbo_map = 0; 2495 } 2496 2497 /* Tx ring */ 2498 if (sc_if->sk_cdata.sk_tx_ring_tag) { 2499 if (sc_if->sk_cdata.sk_tx_ring_map) 2500 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_ring_tag, 2501 sc_if->sk_cdata.sk_tx_ring_map); 2502 if (sc_if->sk_cdata.sk_tx_ring_map && 2503 sc_if->sk_rdata.sk_tx_ring) 2504 bus_dmamem_free(sc_if->sk_cdata.sk_tx_ring_tag, 2505 sc_if->sk_rdata.sk_tx_ring, 2506 sc_if->sk_cdata.sk_tx_ring_map); 2507 sc_if->sk_rdata.sk_tx_ring = NULL; 2508 sc_if->sk_cdata.sk_tx_ring_map = 0; 2509 bus_dma_tag_destroy(sc_if->sk_cdata.sk_tx_ring_tag); 2510 sc_if->sk_cdata.sk_tx_ring_tag = NULL; 2511 } 2512 /* Rx ring */ 2513 if (sc_if->sk_cdata.sk_rx_ring_tag) { 2514 if (sc_if->sk_cdata.sk_rx_ring_map) 2515 bus_dmamap_unload(sc_if->sk_cdata.sk_rx_ring_tag, 2516 sc_if->sk_cdata.sk_rx_ring_map); 2517 if (sc_if->sk_cdata.sk_rx_ring_map && 2518 sc_if->sk_rdata.sk_rx_ring) 2519 bus_dmamem_free(sc_if->sk_cdata.sk_rx_ring_tag, 2520 sc_if->sk_rdata.sk_rx_ring, 2521 sc_if->sk_cdata.sk_rx_ring_map); 2522 sc_if->sk_rdata.sk_rx_ring = NULL; 2523 sc_if->sk_cdata.sk_rx_ring_map = 0; 2524 bus_dma_tag_destroy(sc_if->sk_cdata.sk_rx_ring_tag); 2525 sc_if->sk_cdata.sk_rx_ring_tag = NULL; 2526 } 2527 /* jumbo Rx ring */ 2528 if (sc_if->sk_cdata.sk_jumbo_rx_ring_tag) { 2529 if (sc_if->sk_cdata.sk_jumbo_rx_ring_map) 2530 bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 2531 sc_if->sk_cdata.sk_jumbo_rx_ring_map); 2532 if (sc_if->sk_cdata.sk_jumbo_rx_ring_map && 2533 sc_if->sk_rdata.sk_jumbo_rx_ring) 2534 bus_dmamem_free(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 2535 sc_if->sk_rdata.sk_jumbo_rx_ring, 2536 sc_if->sk_cdata.sk_jumbo_rx_ring_map); 2537 sc_if->sk_rdata.sk_jumbo_rx_ring = NULL; 2538 sc_if->sk_cdata.sk_jumbo_rx_ring_map = 0; 2539 bus_dma_tag_destroy(sc_if->sk_cdata.sk_jumbo_rx_ring_tag); 2540 sc_if->sk_cdata.sk_jumbo_rx_ring_tag = NULL; 2541 } 2542 /* Tx buffers */ 2543 if (sc_if->sk_cdata.sk_tx_tag) { 2544 for (i = 0; i < SK_TX_RING_CNT; i++) { 2545 txd = &sc_if->sk_cdata.sk_txdesc[i]; 2546 if (txd->tx_dmamap) { 2547 bus_dmamap_destroy(sc_if->sk_cdata.sk_tx_tag, 2548 txd->tx_dmamap); 2549 txd->tx_dmamap = 0; 2550 } 2551 } 2552 bus_dma_tag_destroy(sc_if->sk_cdata.sk_tx_tag); 2553 sc_if->sk_cdata.sk_tx_tag = NULL; 2554 } 2555 /* Rx buffers */ 2556 if (sc_if->sk_cdata.sk_rx_tag) { 2557 for (i = 0; i < SK_RX_RING_CNT; i++) { 2558 rxd = &sc_if->sk_cdata.sk_rxdesc[i]; 2559 if (rxd->rx_dmamap) { 2560 bus_dmamap_destroy(sc_if->sk_cdata.sk_rx_tag, 2561 rxd->rx_dmamap); 2562 rxd->rx_dmamap = 0; 2563 } 2564 } 2565 if (sc_if->sk_cdata.sk_rx_sparemap) { 2566 bus_dmamap_destroy(sc_if->sk_cdata.sk_rx_tag, 2567 sc_if->sk_cdata.sk_rx_sparemap); 2568 sc_if->sk_cdata.sk_rx_sparemap = 0; 2569 } 2570 bus_dma_tag_destroy(sc_if->sk_cdata.sk_rx_tag); 2571 sc_if->sk_cdata.sk_rx_tag = NULL; 2572 } 2573 /* jumbo Rx buffers */ 2574 if (sc_if->sk_cdata.sk_jumbo_rx_tag) { 2575 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) { 2576 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i]; 2577 if (jrxd->rx_dmamap) { 2578 bus_dmamap_destroy( 2579 sc_if->sk_cdata.sk_jumbo_rx_tag, 2580 jrxd->rx_dmamap); 2581 jrxd->rx_dmamap = 0; 2582 } 2583 } 2584 if (sc_if->sk_cdata.sk_jumbo_rx_sparemap) { 2585 bus_dmamap_destroy(sc_if->sk_cdata.sk_jumbo_rx_tag, 2586 sc_if->sk_cdata.sk_jumbo_rx_sparemap); 2587 sc_if->sk_cdata.sk_jumbo_rx_sparemap = 0; 2588 } 2589 bus_dma_tag_destroy(sc_if->sk_cdata.sk_jumbo_rx_tag); 2590 sc_if->sk_cdata.sk_jumbo_rx_tag = NULL; 2591 } 2592 2593 if (sc_if->sk_cdata.sk_parent_tag) { 2594 bus_dma_tag_destroy(sc_if->sk_cdata.sk_parent_tag); 2595 sc_if->sk_cdata.sk_parent_tag = NULL; 2596 } 2597 mtx_destroy(&sc_if->sk_jlist_mtx); 2598 } 2599 2600 /* 2601 * Allocate a jumbo buffer. 2602 */ 2603 static void * 2604 sk_jalloc(sc_if) 2605 struct sk_if_softc *sc_if; 2606 { 2607 struct sk_jpool_entry *entry; 2608 2609 SK_JLIST_LOCK(sc_if); 2610 2611 entry = SLIST_FIRST(&sc_if->sk_jfree_listhead); 2612 2613 if (entry == NULL) { 2614 SK_JLIST_UNLOCK(sc_if); 2615 return (NULL); 2616 } 2617 2618 SLIST_REMOVE_HEAD(&sc_if->sk_jfree_listhead, jpool_entries); 2619 SLIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 2620 2621 SK_JLIST_UNLOCK(sc_if); 2622 2623 return (sc_if->sk_cdata.sk_jslots[entry->slot]); 2624 } 2625 2626 /* 2627 * Release a jumbo buffer. 2628 */ 2629 static void 2630 sk_jfree(buf, args) 2631 void *buf; 2632 void *args; 2633 { 2634 struct sk_if_softc *sc_if; 2635 struct sk_jpool_entry *entry; 2636 int i; 2637 2638 /* Extract the softc struct pointer. */ 2639 sc_if = (struct sk_if_softc *)args; 2640 KASSERT(sc_if != NULL, ("%s: can't find softc pointer!", __func__)); 2641 2642 SK_JLIST_LOCK(sc_if); 2643 /* calculate the slot this buffer belongs to */ 2644 i = ((vm_offset_t)buf 2645 - (vm_offset_t)sc_if->sk_rdata.sk_jumbo_buf) / SK_JLEN; 2646 KASSERT(i >= 0 && i < SK_JSLOTS, 2647 ("%s: asked to free buffer that we don't manage!", __func__)); 2648 2649 entry = SLIST_FIRST(&sc_if->sk_jinuse_listhead); 2650 KASSERT(entry != NULL, ("%s: buffer not in use!", __func__)); 2651 entry->slot = i; 2652 SLIST_REMOVE_HEAD(&sc_if->sk_jinuse_listhead, jpool_entries); 2653 SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, entry, jpool_entries); 2654 if (SLIST_EMPTY(&sc_if->sk_jinuse_listhead)) 2655 wakeup(sc_if); 2656 2657 SK_JLIST_UNLOCK(sc_if); 2658 } 2659 2660 static void 2661 sk_txcksum(ifp, m, f) 2662 struct ifnet *ifp; 2663 struct mbuf *m; 2664 struct sk_tx_desc *f; 2665 { 2666 struct ip *ip; 2667 u_int16_t offset; 2668 u_int8_t *p; 2669 2670 offset = sizeof(struct ip) + ETHER_HDR_LEN; 2671 for(; m && m->m_len == 0; m = m->m_next) 2672 ; 2673 if (m == NULL || m->m_len < ETHER_HDR_LEN) { 2674 if_printf(ifp, "%s: m_len < ETHER_HDR_LEN\n", __func__); 2675 /* checksum may be corrupted */ 2676 goto sendit; 2677 } 2678 if (m->m_len < ETHER_HDR_LEN + sizeof(u_int32_t)) { 2679 if (m->m_len != ETHER_HDR_LEN) { 2680 if_printf(ifp, "%s: m_len != ETHER_HDR_LEN\n", 2681 __func__); 2682 /* checksum may be corrupted */ 2683 goto sendit; 2684 } 2685 for(m = m->m_next; m && m->m_len == 0; m = m->m_next) 2686 ; 2687 if (m == NULL) { 2688 offset = sizeof(struct ip) + ETHER_HDR_LEN; 2689 /* checksum may be corrupted */ 2690 goto sendit; 2691 } 2692 ip = mtod(m, struct ip *); 2693 } else { 2694 p = mtod(m, u_int8_t *); 2695 p += ETHER_HDR_LEN; 2696 ip = (struct ip *)p; 2697 } 2698 offset = (ip->ip_hl << 2) + ETHER_HDR_LEN; 2699 2700 sendit: 2701 f->sk_csum_startval = 0; 2702 f->sk_csum_start = htole32(((offset + m->m_pkthdr.csum_data) & 0xffff) | 2703 (offset << 16)); 2704 } 2705 2706 static int 2707 sk_encap(sc_if, m_head) 2708 struct sk_if_softc *sc_if; 2709 struct mbuf **m_head; 2710 { 2711 struct sk_txdesc *txd; 2712 struct sk_tx_desc *f = NULL; 2713 struct mbuf *m, *n; 2714 bus_dma_segment_t txsegs[SK_MAXTXSEGS]; 2715 u_int32_t cflags, frag, si, sk_ctl; 2716 int error, i, nseg; 2717 2718 SK_IF_LOCK_ASSERT(sc_if); 2719 2720 if ((txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txfreeq)) == NULL) 2721 return (ENOBUFS); 2722 2723 m = *m_head; 2724 error = bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_tx_tag, 2725 txd->tx_dmamap, m, txsegs, &nseg, 0); 2726 if (error == EFBIG) { 2727 n = m_defrag(m, M_DONTWAIT); 2728 if (n == NULL) { 2729 m_freem(m); 2730 m = NULL; 2731 return (ENOMEM); 2732 } 2733 m = n; 2734 error = bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_tx_tag, 2735 txd->tx_dmamap, m, txsegs, &nseg, 0); 2736 if (error != 0) { 2737 m_freem(m); 2738 m = NULL; 2739 return (error); 2740 } 2741 } else if (error != 0) 2742 return (error); 2743 if (nseg == 0) { 2744 m_freem(m); 2745 m = NULL; 2746 return (EIO); 2747 } 2748 if (sc_if->sk_cdata.sk_tx_cnt + nseg >= SK_TX_RING_CNT) { 2749 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap); 2750 return (ENOBUFS); 2751 } 2752 2753 if ((m->m_pkthdr.csum_flags & sc_if->sk_ifp->if_hwassist) != 0) 2754 cflags = SK_OPCODE_CSUM; 2755 else 2756 cflags = SK_OPCODE_DEFAULT; 2757 si = frag = sc_if->sk_cdata.sk_tx_prod; 2758 for (i = 0; i < nseg; i++) { 2759 f = &sc_if->sk_rdata.sk_tx_ring[frag]; 2760 f->sk_data_lo = htole32(SK_ADDR_LO(txsegs[i].ds_addr)); 2761 f->sk_data_hi = htole32(SK_ADDR_HI(txsegs[i].ds_addr)); 2762 sk_ctl = txsegs[i].ds_len | cflags; 2763 if (i == 0) { 2764 if (cflags == SK_OPCODE_CSUM) 2765 sk_txcksum(sc_if->sk_ifp, m, f); 2766 sk_ctl |= SK_TXCTL_FIRSTFRAG; 2767 } else 2768 sk_ctl |= SK_TXCTL_OWN; 2769 f->sk_ctl = htole32(sk_ctl); 2770 sc_if->sk_cdata.sk_tx_cnt++; 2771 SK_INC(frag, SK_TX_RING_CNT); 2772 } 2773 sc_if->sk_cdata.sk_tx_prod = frag; 2774 2775 /* set EOF on the last desciptor */ 2776 frag = (frag + SK_TX_RING_CNT - 1) % SK_TX_RING_CNT; 2777 f = &sc_if->sk_rdata.sk_tx_ring[frag]; 2778 f->sk_ctl |= htole32(SK_TXCTL_LASTFRAG | SK_TXCTL_EOF_INTR); 2779 2780 /* turn the first descriptor ownership to NIC */ 2781 f = &sc_if->sk_rdata.sk_tx_ring[si]; 2782 f->sk_ctl |= htole32(SK_TXCTL_OWN); 2783 2784 STAILQ_REMOVE_HEAD(&sc_if->sk_cdata.sk_txfreeq, tx_q); 2785 STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txbusyq, txd, tx_q); 2786 txd->tx_m = m; 2787 2788 /* sync descriptors */ 2789 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap, 2790 BUS_DMASYNC_PREWRITE); 2791 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag, 2792 sc_if->sk_cdata.sk_tx_ring_map, 2793 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2794 2795 return (0); 2796 } 2797 2798 static void 2799 sk_start(ifp) 2800 struct ifnet *ifp; 2801 { 2802 struct sk_if_softc *sc_if; 2803 2804 sc_if = ifp->if_softc; 2805 2806 SK_IF_LOCK(sc_if); 2807 sk_start_locked(ifp); 2808 SK_IF_UNLOCK(sc_if); 2809 2810 return; 2811 } 2812 2813 static void 2814 sk_start_locked(ifp) 2815 struct ifnet *ifp; 2816 { 2817 struct sk_softc *sc; 2818 struct sk_if_softc *sc_if; 2819 struct mbuf *m_head; 2820 int enq; 2821 2822 sc_if = ifp->if_softc; 2823 sc = sc_if->sk_softc; 2824 2825 SK_IF_LOCK_ASSERT(sc_if); 2826 2827 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2828 sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 1; ) { 2829 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2830 if (m_head == NULL) 2831 break; 2832 2833 /* 2834 * Pack the data into the transmit ring. If we 2835 * don't have room, set the OACTIVE flag and wait 2836 * for the NIC to drain the ring. 2837 */ 2838 if (sk_encap(sc_if, &m_head)) { 2839 if (m_head == NULL) 2840 break; 2841 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2842 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2843 break; 2844 } 2845 2846 enq++; 2847 /* 2848 * If there's a BPF listener, bounce a copy of this frame 2849 * to him. 2850 */ 2851 BPF_MTAP(ifp, m_head); 2852 } 2853 2854 if (enq > 0) { 2855 /* Transmit */ 2856 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 2857 2858 /* Set a timeout in case the chip goes out to lunch. */ 2859 ifp->if_timer = 5; 2860 } 2861 } 2862 2863 2864 static void 2865 sk_watchdog(ifp) 2866 struct ifnet *ifp; 2867 { 2868 struct sk_if_softc *sc_if; 2869 2870 sc_if = ifp->if_softc; 2871 2872 SK_IF_LOCK(sc_if); 2873 /* 2874 * Reclaim first as there is a possibility of loosing Tx completion 2875 * interrupt. 2876 */ 2877 sk_txeof(sc_if); 2878 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 2879 if_printf(sc_if->sk_ifp, "watchdog timeout\n"); 2880 ifp->if_oerrors++; 2881 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2882 sk_init_locked(sc_if); 2883 } 2884 SK_IF_UNLOCK(sc_if); 2885 2886 return; 2887 } 2888 2889 static void 2890 skc_shutdown(dev) 2891 device_t dev; 2892 { 2893 struct sk_softc *sc; 2894 2895 sc = device_get_softc(dev); 2896 SK_LOCK(sc); 2897 2898 /* Turn off the 'driver is loaded' LED. */ 2899 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 2900 2901 /* 2902 * Reset the GEnesis controller. Doing this should also 2903 * assert the resets on the attached XMAC(s). 2904 */ 2905 sk_reset(sc); 2906 SK_UNLOCK(sc); 2907 2908 return; 2909 } 2910 2911 static int 2912 skc_suspend(dev) 2913 device_t dev; 2914 { 2915 struct sk_softc *sc; 2916 struct sk_if_softc *sc_if0, *sc_if1; 2917 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2918 2919 sc = device_get_softc(dev); 2920 2921 SK_LOCK(sc); 2922 2923 sc_if0 = sc->sk_if[SK_PORT_A]; 2924 sc_if1 = sc->sk_if[SK_PORT_B]; 2925 if (sc_if0 != NULL) 2926 ifp0 = sc_if0->sk_ifp; 2927 if (sc_if1 != NULL) 2928 ifp1 = sc_if1->sk_ifp; 2929 if (ifp0 != NULL) 2930 sk_stop(sc_if0); 2931 if (ifp1 != NULL) 2932 sk_stop(sc_if1); 2933 sc->sk_suspended = 1; 2934 2935 SK_UNLOCK(sc); 2936 2937 return (0); 2938 } 2939 2940 static int 2941 skc_resume(dev) 2942 device_t dev; 2943 { 2944 struct sk_softc *sc; 2945 struct sk_if_softc *sc_if0, *sc_if1; 2946 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2947 2948 sc = device_get_softc(dev); 2949 2950 SK_LOCK(sc); 2951 2952 sc_if0 = sc->sk_if[SK_PORT_A]; 2953 sc_if1 = sc->sk_if[SK_PORT_B]; 2954 if (sc_if0 != NULL) 2955 ifp0 = sc_if0->sk_ifp; 2956 if (sc_if1 != NULL) 2957 ifp1 = sc_if1->sk_ifp; 2958 if (ifp0 != NULL && ifp0->if_flags & IFF_UP) 2959 sk_init_locked(sc_if0); 2960 if (ifp1 != NULL && ifp1->if_flags & IFF_UP) 2961 sk_init_locked(sc_if1); 2962 sc->sk_suspended = 0; 2963 2964 SK_UNLOCK(sc); 2965 2966 return (0); 2967 } 2968 2969 /* 2970 * According to the data sheet from SK-NET GENESIS the hardware can compute 2971 * two Rx checksums at the same time(Each checksum start position is 2972 * programmed in Rx descriptors). However it seems that TCP/UDP checksum 2973 * does not work at least on my Yukon hardware. I tried every possible ways 2974 * to get correct checksum value but couldn't get correct one. So TCP/UDP 2975 * checksum offload was disabled at the moment and only IP checksum offload 2976 * was enabled. 2977 * As nomral IP header size is 20 bytes I can't expect it would give an 2978 * increase in throughput. However it seems it doesn't hurt performance in 2979 * my testing. If there is a more detailed information for checksum secret 2980 * of the hardware in question please contact yongari@FreeBSD.org to add 2981 * TCP/UDP checksum offload support. 2982 */ 2983 static __inline void 2984 sk_rxcksum(ifp, m, csum) 2985 struct ifnet *ifp; 2986 struct mbuf *m; 2987 u_int32_t csum; 2988 { 2989 struct ether_header *eh; 2990 struct ip *ip; 2991 int32_t hlen, len, pktlen; 2992 u_int16_t csum1, csum2, ipcsum; 2993 2994 pktlen = m->m_pkthdr.len; 2995 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip)) 2996 return; 2997 eh = mtod(m, struct ether_header *); 2998 if (eh->ether_type != htons(ETHERTYPE_IP)) 2999 return; 3000 ip = (struct ip *)(eh + 1); 3001 if (ip->ip_v != IPVERSION) 3002 return; 3003 hlen = ip->ip_hl << 2; 3004 pktlen -= sizeof(struct ether_header); 3005 if (hlen < sizeof(struct ip)) 3006 return; 3007 if (ntohs(ip->ip_len) < hlen) 3008 return; 3009 if (ntohs(ip->ip_len) != pktlen) 3010 return; 3011 3012 csum1 = htons(csum & 0xffff); 3013 csum2 = htons((csum >> 16) & 0xffff); 3014 ipcsum = in_addword(csum1, ~csum2 & 0xffff); 3015 /* checksum fixup for IP options */ 3016 len = hlen - sizeof(struct ip); 3017 if (len > 0) { 3018 /* 3019 * If the second checksum value is correct we can compute IP 3020 * checksum with simple math. Unfortunately the second checksum 3021 * value is wrong so we can't verify the checksum from the 3022 * value(It seems there is some magic here to get correct 3023 * value). If the second checksum value is correct it also 3024 * means we can get TCP/UDP checksum) here. However, it still 3025 * needs pseudo header checksum calculation due to hardware 3026 * limitations. 3027 */ 3028 return; 3029 } 3030 m->m_pkthdr.csum_flags = CSUM_IP_CHECKED; 3031 if (ipcsum == 0xffff) 3032 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 3033 } 3034 3035 static __inline int 3036 sk_rxvalid(sc, stat, len) 3037 struct sk_softc *sc; 3038 u_int32_t stat, len; 3039 { 3040 3041 if (sc->sk_type == SK_GENESIS) { 3042 if ((stat & XM_RXSTAT_ERRFRAME) == XM_RXSTAT_ERRFRAME || 3043 XM_RXSTAT_BYTES(stat) != len) 3044 return (0); 3045 } else { 3046 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR | 3047 YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | 3048 YU_RXSTAT_JABBER)) != 0 || 3049 (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK || 3050 YU_RXSTAT_BYTES(stat) != len) 3051 return (0); 3052 } 3053 3054 return (1); 3055 } 3056 3057 static void 3058 sk_rxeof(sc_if) 3059 struct sk_if_softc *sc_if; 3060 { 3061 struct sk_softc *sc; 3062 struct mbuf *m; 3063 struct ifnet *ifp; 3064 struct sk_rx_desc *cur_rx; 3065 struct sk_rxdesc *rxd; 3066 int cons, prog; 3067 u_int32_t csum, rxstat, sk_ctl; 3068 3069 sc = sc_if->sk_softc; 3070 ifp = sc_if->sk_ifp; 3071 3072 SK_IF_LOCK_ASSERT(sc_if); 3073 3074 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag, 3075 sc_if->sk_cdata.sk_rx_ring_map, BUS_DMASYNC_POSTREAD); 3076 3077 prog = 0; 3078 for (cons = sc_if->sk_cdata.sk_rx_cons; prog < SK_RX_RING_CNT; 3079 prog++, SK_INC(cons, SK_RX_RING_CNT)) { 3080 cur_rx = &sc_if->sk_rdata.sk_rx_ring[cons]; 3081 sk_ctl = le32toh(cur_rx->sk_ctl); 3082 if ((sk_ctl & SK_RXCTL_OWN) != 0) 3083 break; 3084 rxd = &sc_if->sk_cdata.sk_rxdesc[cons]; 3085 rxstat = le32toh(cur_rx->sk_xmac_rxstat); 3086 3087 if ((sk_ctl & (SK_RXCTL_STATUS_VALID | SK_RXCTL_FIRSTFRAG | 3088 SK_RXCTL_LASTFRAG)) != (SK_RXCTL_STATUS_VALID | 3089 SK_RXCTL_FIRSTFRAG | SK_RXCTL_LASTFRAG) || 3090 SK_RXBYTES(sk_ctl) < SK_MIN_FRAMELEN || 3091 SK_RXBYTES(sk_ctl) > SK_MAX_FRAMELEN || 3092 sk_rxvalid(sc, rxstat, SK_RXBYTES(sk_ctl)) == 0) { 3093 ifp->if_ierrors++; 3094 sk_discard_rxbuf(sc_if, cons); 3095 continue; 3096 } 3097 3098 m = rxd->rx_m; 3099 csum = le32toh(cur_rx->sk_csum); 3100 if (sk_newbuf(sc_if, cons) != 0) { 3101 ifp->if_iqdrops++; 3102 /* reuse old buffer */ 3103 sk_discard_rxbuf(sc_if, cons); 3104 continue; 3105 } 3106 m->m_pkthdr.rcvif = ifp; 3107 m->m_pkthdr.len = m->m_len = SK_RXBYTES(sk_ctl); 3108 ifp->if_ipackets++; 3109 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 3110 sk_rxcksum(ifp, m, csum); 3111 SK_IF_UNLOCK(sc_if); 3112 (*ifp->if_input)(ifp, m); 3113 SK_IF_LOCK(sc_if); 3114 } 3115 3116 if (prog > 0) { 3117 sc_if->sk_cdata.sk_rx_cons = cons; 3118 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag, 3119 sc_if->sk_cdata.sk_rx_ring_map, 3120 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3121 } 3122 } 3123 3124 static void 3125 sk_jumbo_rxeof(sc_if) 3126 struct sk_if_softc *sc_if; 3127 { 3128 struct sk_softc *sc; 3129 struct mbuf *m; 3130 struct ifnet *ifp; 3131 struct sk_rx_desc *cur_rx; 3132 struct sk_rxdesc *jrxd; 3133 int cons, prog; 3134 u_int32_t csum, rxstat, sk_ctl; 3135 3136 sc = sc_if->sk_softc; 3137 ifp = sc_if->sk_ifp; 3138 3139 SK_IF_LOCK_ASSERT(sc_if); 3140 3141 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 3142 sc_if->sk_cdata.sk_jumbo_rx_ring_map, BUS_DMASYNC_POSTREAD); 3143 3144 prog = 0; 3145 for (cons = sc_if->sk_cdata.sk_jumbo_rx_cons; 3146 prog < SK_JUMBO_RX_RING_CNT; 3147 prog++, SK_INC(cons, SK_JUMBO_RX_RING_CNT)) { 3148 cur_rx = &sc_if->sk_rdata.sk_jumbo_rx_ring[cons]; 3149 sk_ctl = le32toh(cur_rx->sk_ctl); 3150 if ((sk_ctl & SK_RXCTL_OWN) != 0) 3151 break; 3152 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[cons]; 3153 rxstat = le32toh(cur_rx->sk_xmac_rxstat); 3154 3155 if ((sk_ctl & (SK_RXCTL_STATUS_VALID | SK_RXCTL_FIRSTFRAG | 3156 SK_RXCTL_LASTFRAG)) != (SK_RXCTL_STATUS_VALID | 3157 SK_RXCTL_FIRSTFRAG | SK_RXCTL_LASTFRAG) || 3158 SK_RXBYTES(sk_ctl) < SK_MIN_FRAMELEN || 3159 SK_RXBYTES(sk_ctl) > SK_JUMBO_FRAMELEN || 3160 sk_rxvalid(sc, rxstat, SK_RXBYTES(sk_ctl)) == 0) { 3161 ifp->if_ierrors++; 3162 sk_discard_jumbo_rxbuf(sc_if, cons); 3163 continue; 3164 } 3165 3166 m = jrxd->rx_m; 3167 csum = le32toh(cur_rx->sk_csum); 3168 if (sk_jumbo_newbuf(sc_if, cons) != 0) { 3169 ifp->if_iqdrops++; 3170 /* reuse old buffer */ 3171 sk_discard_jumbo_rxbuf(sc_if, cons); 3172 continue; 3173 } 3174 m->m_pkthdr.rcvif = ifp; 3175 m->m_pkthdr.len = m->m_len = SK_RXBYTES(sk_ctl); 3176 ifp->if_ipackets++; 3177 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 3178 sk_rxcksum(ifp, m, csum); 3179 SK_IF_UNLOCK(sc_if); 3180 (*ifp->if_input)(ifp, m); 3181 SK_IF_LOCK(sc_if); 3182 } 3183 3184 if (prog > 0) { 3185 sc_if->sk_cdata.sk_jumbo_rx_cons = cons; 3186 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 3187 sc_if->sk_cdata.sk_jumbo_rx_ring_map, 3188 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3189 } 3190 } 3191 3192 static void 3193 sk_txeof(sc_if) 3194 struct sk_if_softc *sc_if; 3195 { 3196 struct sk_softc *sc; 3197 struct sk_txdesc *txd; 3198 struct sk_tx_desc *cur_tx; 3199 struct ifnet *ifp; 3200 u_int32_t idx, sk_ctl; 3201 3202 sc = sc_if->sk_softc; 3203 ifp = sc_if->sk_ifp; 3204 3205 txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txbusyq); 3206 if (txd == NULL) 3207 return; 3208 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag, 3209 sc_if->sk_cdata.sk_tx_ring_map, BUS_DMASYNC_POSTREAD); 3210 /* 3211 * Go through our tx ring and free mbufs for those 3212 * frames that have been sent. 3213 */ 3214 for (idx = sc_if->sk_cdata.sk_tx_cons;; SK_INC(idx, SK_TX_RING_CNT)) { 3215 if (sc_if->sk_cdata.sk_tx_cnt <= 0) 3216 break; 3217 cur_tx = &sc_if->sk_rdata.sk_tx_ring[idx]; 3218 sk_ctl = le32toh(cur_tx->sk_ctl); 3219 if (sk_ctl & SK_TXCTL_OWN) 3220 break; 3221 sc_if->sk_cdata.sk_tx_cnt--; 3222 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3223 if ((sk_ctl & SK_TXCTL_LASTFRAG) == 0) 3224 continue; 3225 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap, 3226 BUS_DMASYNC_POSTWRITE); 3227 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap); 3228 3229 ifp->if_opackets++; 3230 m_freem(txd->tx_m); 3231 txd->tx_m = NULL; 3232 STAILQ_REMOVE_HEAD(&sc_if->sk_cdata.sk_txbusyq, tx_q); 3233 STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txfreeq, txd, tx_q); 3234 txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txbusyq); 3235 } 3236 sc_if->sk_cdata.sk_tx_cons = idx; 3237 ifp->if_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0; 3238 3239 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag, 3240 sc_if->sk_cdata.sk_tx_ring_map, 3241 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3242 } 3243 3244 static void 3245 sk_tick(xsc_if) 3246 void *xsc_if; 3247 { 3248 struct sk_if_softc *sc_if; 3249 struct mii_data *mii; 3250 struct ifnet *ifp; 3251 int i; 3252 3253 sc_if = xsc_if; 3254 ifp = sc_if->sk_ifp; 3255 mii = device_get_softc(sc_if->sk_miibus); 3256 3257 if (!(ifp->if_flags & IFF_UP)) 3258 return; 3259 3260 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 3261 sk_intr_bcom(sc_if); 3262 return; 3263 } 3264 3265 /* 3266 * According to SysKonnect, the correct way to verify that 3267 * the link has come back up is to poll bit 0 of the GPIO 3268 * register three times. This pin has the signal from the 3269 * link_sync pin connected to it; if we read the same link 3270 * state 3 times in a row, we know the link is up. 3271 */ 3272 for (i = 0; i < 3; i++) { 3273 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 3274 break; 3275 } 3276 3277 if (i != 3) { 3278 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 3279 return; 3280 } 3281 3282 /* Turn the GP0 interrupt back on. */ 3283 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 3284 SK_XM_READ_2(sc_if, XM_ISR); 3285 mii_tick(mii); 3286 callout_stop(&sc_if->sk_tick_ch); 3287 } 3288 3289 static void 3290 sk_yukon_tick(xsc_if) 3291 void *xsc_if; 3292 { 3293 struct sk_if_softc *sc_if; 3294 struct mii_data *mii; 3295 3296 sc_if = xsc_if; 3297 mii = device_get_softc(sc_if->sk_miibus); 3298 3299 mii_tick(mii); 3300 callout_reset(&sc_if->sk_tick_ch, hz, sk_yukon_tick, sc_if); 3301 } 3302 3303 static void 3304 sk_intr_bcom(sc_if) 3305 struct sk_if_softc *sc_if; 3306 { 3307 struct mii_data *mii; 3308 struct ifnet *ifp; 3309 int status; 3310 mii = device_get_softc(sc_if->sk_miibus); 3311 ifp = sc_if->sk_ifp; 3312 3313 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 3314 3315 /* 3316 * Read the PHY interrupt register to make sure 3317 * we clear any pending interrupts. 3318 */ 3319 status = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 3320 3321 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3322 sk_init_xmac(sc_if); 3323 return; 3324 } 3325 3326 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 3327 int lstat; 3328 lstat = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 3329 BRGPHY_MII_AUXSTS); 3330 3331 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 3332 mii_mediachg(mii); 3333 /* Turn off the link LED. */ 3334 SK_IF_WRITE_1(sc_if, 0, 3335 SK_LINKLED1_CTL, SK_LINKLED_OFF); 3336 sc_if->sk_link = 0; 3337 } else if (status & BRGPHY_ISR_LNK_CHG) { 3338 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 3339 BRGPHY_MII_IMR, 0xFF00); 3340 mii_tick(mii); 3341 sc_if->sk_link = 1; 3342 /* Turn on the link LED. */ 3343 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 3344 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 3345 SK_LINKLED_BLINK_OFF); 3346 } else { 3347 mii_tick(mii); 3348 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 3349 } 3350 } 3351 3352 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 3353 3354 return; 3355 } 3356 3357 static void 3358 sk_intr_xmac(sc_if) 3359 struct sk_if_softc *sc_if; 3360 { 3361 struct sk_softc *sc; 3362 u_int16_t status; 3363 3364 sc = sc_if->sk_softc; 3365 status = SK_XM_READ_2(sc_if, XM_ISR); 3366 3367 /* 3368 * Link has gone down. Start MII tick timeout to 3369 * watch for link resync. 3370 */ 3371 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 3372 if (status & XM_ISR_GP0_SET) { 3373 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 3374 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 3375 } 3376 3377 if (status & XM_ISR_AUTONEG_DONE) { 3378 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 3379 } 3380 } 3381 3382 if (status & XM_IMR_TX_UNDERRUN) 3383 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 3384 3385 if (status & XM_IMR_RX_OVERRUN) 3386 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 3387 3388 status = SK_XM_READ_2(sc_if, XM_ISR); 3389 3390 return; 3391 } 3392 3393 static void 3394 sk_intr_yukon(sc_if) 3395 struct sk_if_softc *sc_if; 3396 { 3397 u_int8_t status; 3398 3399 status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR); 3400 /* RX overrun */ 3401 if ((status & SK_GMAC_INT_RX_OVER) != 0) { 3402 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 3403 SK_RFCTL_RX_FIFO_OVER); 3404 } 3405 /* TX underrun */ 3406 if ((status & SK_GMAC_INT_TX_UNDER) != 0) { 3407 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 3408 SK_TFCTL_TX_FIFO_UNDER); 3409 } 3410 } 3411 3412 static void 3413 sk_intr(xsc) 3414 void *xsc; 3415 { 3416 struct sk_softc *sc = xsc; 3417 struct sk_if_softc *sc_if0, *sc_if1; 3418 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 3419 u_int32_t status; 3420 3421 SK_LOCK(sc); 3422 3423 status = CSR_READ_4(sc, SK_ISSR); 3424 if (status == 0 || status == 0xffffffff || sc->sk_suspended) 3425 goto done_locked; 3426 3427 sc_if0 = sc->sk_if[SK_PORT_A]; 3428 sc_if1 = sc->sk_if[SK_PORT_B]; 3429 3430 if (sc_if0 != NULL) 3431 ifp0 = sc_if0->sk_ifp; 3432 if (sc_if1 != NULL) 3433 ifp1 = sc_if1->sk_ifp; 3434 3435 for (; (status &= sc->sk_intrmask) != 0;) { 3436 /* Handle receive interrupts first. */ 3437 if (status & SK_ISR_RX1_EOF) { 3438 if (ifp0->if_mtu > SK_MAX_FRAMELEN) 3439 sk_jumbo_rxeof(sc_if0); 3440 else 3441 sk_rxeof(sc_if0); 3442 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 3443 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 3444 } 3445 if (status & SK_ISR_RX2_EOF) { 3446 if (ifp1->if_mtu > SK_MAX_FRAMELEN) 3447 sk_jumbo_rxeof(sc_if1); 3448 else 3449 sk_rxeof(sc_if1); 3450 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 3451 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 3452 } 3453 3454 /* Then transmit interrupts. */ 3455 if (status & SK_ISR_TX1_S_EOF) { 3456 sk_txeof(sc_if0); 3457 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, SK_TXBMU_CLR_IRQ_EOF); 3458 } 3459 if (status & SK_ISR_TX2_S_EOF) { 3460 sk_txeof(sc_if1); 3461 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, SK_TXBMU_CLR_IRQ_EOF); 3462 } 3463 3464 /* Then MAC interrupts. */ 3465 if (status & SK_ISR_MAC1 && 3466 ifp0->if_drv_flags & IFF_DRV_RUNNING) { 3467 if (sc->sk_type == SK_GENESIS) 3468 sk_intr_xmac(sc_if0); 3469 else 3470 sk_intr_yukon(sc_if0); 3471 } 3472 3473 if (status & SK_ISR_MAC2 && 3474 ifp1->if_drv_flags & IFF_DRV_RUNNING) { 3475 if (sc->sk_type == SK_GENESIS) 3476 sk_intr_xmac(sc_if1); 3477 else 3478 sk_intr_yukon(sc_if1); 3479 } 3480 3481 if (status & SK_ISR_EXTERNAL_REG) { 3482 if (ifp0 != NULL && 3483 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 3484 sk_intr_bcom(sc_if0); 3485 if (ifp1 != NULL && 3486 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 3487 sk_intr_bcom(sc_if1); 3488 } 3489 status = CSR_READ_4(sc, SK_ISSR); 3490 } 3491 3492 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 3493 3494 if (ifp0 != NULL && !IFQ_DRV_IS_EMPTY(&ifp0->if_snd)) 3495 sk_start_locked(ifp0); 3496 if (ifp1 != NULL && !IFQ_DRV_IS_EMPTY(&ifp1->if_snd)) 3497 sk_start_locked(ifp1); 3498 3499 done_locked: 3500 SK_UNLOCK(sc); 3501 } 3502 3503 static void 3504 sk_init_xmac(sc_if) 3505 struct sk_if_softc *sc_if; 3506 { 3507 struct sk_softc *sc; 3508 struct ifnet *ifp; 3509 u_int16_t eaddr[(ETHER_ADDR_LEN+1)/2]; 3510 struct sk_bcom_hack bhack[] = { 3511 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 3512 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 3513 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 3514 { 0, 0 } }; 3515 3516 SK_IF_LOCK_ASSERT(sc_if); 3517 3518 sc = sc_if->sk_softc; 3519 ifp = sc_if->sk_ifp; 3520 3521 /* Unreset the XMAC. */ 3522 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 3523 DELAY(1000); 3524 3525 /* Reset the XMAC's internal state. */ 3526 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 3527 3528 /* Save the XMAC II revision */ 3529 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 3530 3531 /* 3532 * Perform additional initialization for external PHYs, 3533 * namely for the 1000baseTX cards that use the XMAC's 3534 * GMII mode. 3535 */ 3536 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 3537 int i = 0; 3538 u_int32_t val; 3539 3540 /* Take PHY out of reset. */ 3541 val = sk_win_read_4(sc, SK_GPIO); 3542 if (sc_if->sk_port == SK_PORT_A) 3543 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 3544 else 3545 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 3546 sk_win_write_4(sc, SK_GPIO, val); 3547 3548 /* Enable GMII mode on the XMAC. */ 3549 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 3550 3551 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 3552 BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET); 3553 DELAY(10000); 3554 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 3555 BRGPHY_MII_IMR, 0xFFF0); 3556 3557 /* 3558 * Early versions of the BCM5400 apparently have 3559 * a bug that requires them to have their reserved 3560 * registers initialized to some magic values. I don't 3561 * know what the numbers do, I'm just the messenger. 3562 */ 3563 if (sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 0x03) 3564 == 0x6041) { 3565 while(bhack[i].reg) { 3566 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 3567 bhack[i].reg, bhack[i].val); 3568 i++; 3569 } 3570 } 3571 } 3572 3573 /* Set station address */ 3574 bcopy(IF_LLADDR(sc_if->sk_ifp), eaddr, ETHER_ADDR_LEN); 3575 SK_XM_WRITE_2(sc_if, XM_PAR0, eaddr[0]); 3576 SK_XM_WRITE_2(sc_if, XM_PAR1, eaddr[1]); 3577 SK_XM_WRITE_2(sc_if, XM_PAR2, eaddr[2]); 3578 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 3579 3580 if (ifp->if_flags & IFF_BROADCAST) { 3581 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 3582 } else { 3583 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 3584 } 3585 3586 /* We don't need the FCS appended to the packet. */ 3587 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 3588 3589 /* We want short frames padded to 60 bytes. */ 3590 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 3591 3592 /* 3593 * Enable the reception of all error frames. This is is 3594 * a necessary evil due to the design of the XMAC. The 3595 * XMAC's receive FIFO is only 8K in size, however jumbo 3596 * frames can be up to 9000 bytes in length. When bad 3597 * frame filtering is enabled, the XMAC's RX FIFO operates 3598 * in 'store and forward' mode. For this to work, the 3599 * entire frame has to fit into the FIFO, but that means 3600 * that jumbo frames larger than 8192 bytes will be 3601 * truncated. Disabling all bad frame filtering causes 3602 * the RX FIFO to operate in streaming mode, in which 3603 * case the XMAC will start transfering frames out of the 3604 * RX FIFO as soon as the FIFO threshold is reached. 3605 */ 3606 if (ifp->if_mtu > SK_MAX_FRAMELEN) { 3607 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 3608 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 3609 XM_MODE_RX_INRANGELEN); 3610 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 3611 } else 3612 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 3613 3614 /* 3615 * Bump up the transmit threshold. This helps hold off transmit 3616 * underruns when we're blasting traffic from both ports at once. 3617 */ 3618 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 3619 3620 /* Set promiscuous mode */ 3621 sk_setpromisc(sc_if); 3622 3623 /* Set multicast filter */ 3624 sk_setmulti(sc_if); 3625 3626 /* Clear and enable interrupts */ 3627 SK_XM_READ_2(sc_if, XM_ISR); 3628 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 3629 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 3630 else 3631 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 3632 3633 /* Configure MAC arbiter */ 3634 switch(sc_if->sk_xmac_rev) { 3635 case XM_XMAC_REV_B2: 3636 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 3637 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 3638 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 3639 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 3640 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 3641 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 3642 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 3643 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 3644 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 3645 break; 3646 case XM_XMAC_REV_C1: 3647 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 3648 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 3649 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 3650 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 3651 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 3652 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 3653 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 3654 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 3655 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 3656 break; 3657 default: 3658 break; 3659 } 3660 sk_win_write_2(sc, SK_MACARB_CTL, 3661 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 3662 3663 sc_if->sk_link = 1; 3664 3665 return; 3666 } 3667 3668 static void 3669 sk_init_yukon(sc_if) 3670 struct sk_if_softc *sc_if; 3671 { 3672 u_int32_t phy, v; 3673 u_int16_t reg; 3674 struct sk_softc *sc; 3675 struct ifnet *ifp; 3676 int i; 3677 3678 SK_IF_LOCK_ASSERT(sc_if); 3679 3680 sc = sc_if->sk_softc; 3681 ifp = sc_if->sk_ifp; 3682 3683 if (sc->sk_type == SK_YUKON_LITE && 3684 sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 3685 /* 3686 * Workaround code for COMA mode, set PHY reset. 3687 * Otherwise it will not correctly take chip out of 3688 * powerdown (coma) 3689 */ 3690 v = sk_win_read_4(sc, SK_GPIO); 3691 v |= SK_GPIO_DIR9 | SK_GPIO_DAT9; 3692 sk_win_write_4(sc, SK_GPIO, v); 3693 } 3694 3695 /* GMAC and GPHY Reset */ 3696 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 3697 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 3698 DELAY(1000); 3699 3700 if (sc->sk_type == SK_YUKON_LITE && 3701 sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 3702 /* 3703 * Workaround code for COMA mode, clear PHY reset 3704 */ 3705 v = sk_win_read_4(sc, SK_GPIO); 3706 v |= SK_GPIO_DIR9; 3707 v &= ~SK_GPIO_DAT9; 3708 sk_win_write_4(sc, SK_GPIO, v); 3709 } 3710 3711 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 3712 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 3713 3714 if (sc->sk_coppertype) 3715 phy |= SK_GPHY_COPPER; 3716 else 3717 phy |= SK_GPHY_FIBER; 3718 3719 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 3720 DELAY(1000); 3721 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 3722 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 3723 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 3724 3725 /* unused read of the interrupt source register */ 3726 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 3727 3728 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 3729 3730 /* MIB Counter Clear Mode set */ 3731 reg |= YU_PAR_MIB_CLR; 3732 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 3733 3734 /* MIB Counter Clear Mode clear */ 3735 reg &= ~YU_PAR_MIB_CLR; 3736 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 3737 3738 /* receive control reg */ 3739 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR); 3740 3741 /* transmit parameter register */ 3742 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 3743 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 3744 3745 /* serial mode register */ 3746 reg = YU_SMR_DATA_BLIND(0x1c) | YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e); 3747 if (ifp->if_mtu > SK_MAX_FRAMELEN) 3748 reg |= YU_SMR_MFL_JUMBO; 3749 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg); 3750 3751 /* Setup Yukon's address */ 3752 for (i = 0; i < 3; i++) { 3753 /* Write Source Address 1 (unicast filter) */ 3754 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 3755 IF_LLADDR(sc_if->sk_ifp)[i * 2] | 3756 IF_LLADDR(sc_if->sk_ifp)[i * 2 + 1] << 8); 3757 } 3758 3759 for (i = 0; i < 3; i++) { 3760 reg = sk_win_read_2(sc_if->sk_softc, 3761 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 3762 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 3763 } 3764 3765 /* Set promiscuous mode */ 3766 sk_setpromisc(sc_if); 3767 3768 /* Set multicast filter */ 3769 sk_setmulti(sc_if); 3770 3771 /* enable interrupt mask for counter overflows */ 3772 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 3773 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 3774 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 3775 3776 /* Configure RX MAC FIFO Flush Mask */ 3777 v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR | 3778 YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT | 3779 YU_RXSTAT_JABBER; 3780 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v); 3781 3782 /* Disable RX MAC FIFO Flush for YUKON-Lite Rev. A0 only */ 3783 if (sc->sk_type == SK_YUKON_LITE && sc->sk_rev == SK_YUKON_LITE_REV_A0) 3784 v = SK_TFCTL_OPERATION_ON; 3785 else 3786 v = SK_TFCTL_OPERATION_ON | SK_RFCTL_FIFO_FLUSH_ON; 3787 /* Configure RX MAC FIFO */ 3788 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 3789 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, v); 3790 3791 /* Increase flush threshould to 64 bytes */ 3792 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD, 3793 SK_RFCTL_FIFO_THRESHOLD + 1); 3794 3795 /* Configure TX MAC FIFO */ 3796 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 3797 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 3798 } 3799 3800 /* 3801 * Note that to properly initialize any part of the GEnesis chip, 3802 * you first have to take it out of reset mode. 3803 */ 3804 static void 3805 sk_init(xsc) 3806 void *xsc; 3807 { 3808 struct sk_if_softc *sc_if = xsc; 3809 3810 SK_IF_LOCK(sc_if); 3811 sk_init_locked(sc_if); 3812 SK_IF_UNLOCK(sc_if); 3813 3814 return; 3815 } 3816 3817 static void 3818 sk_init_locked(sc_if) 3819 struct sk_if_softc *sc_if; 3820 { 3821 struct sk_softc *sc; 3822 struct ifnet *ifp; 3823 struct mii_data *mii; 3824 u_int16_t reg; 3825 u_int32_t imr; 3826 int error; 3827 3828 SK_IF_LOCK_ASSERT(sc_if); 3829 3830 ifp = sc_if->sk_ifp; 3831 sc = sc_if->sk_softc; 3832 mii = device_get_softc(sc_if->sk_miibus); 3833 3834 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3835 return; 3836 3837 /* Cancel pending I/O and free all RX/TX buffers. */ 3838 sk_stop(sc_if); 3839 3840 if (sc->sk_type == SK_GENESIS) { 3841 /* Configure LINK_SYNC LED */ 3842 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 3843 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 3844 SK_LINKLED_LINKSYNC_ON); 3845 3846 /* Configure RX LED */ 3847 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 3848 SK_RXLEDCTL_COUNTER_START); 3849 3850 /* Configure TX LED */ 3851 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 3852 SK_TXLEDCTL_COUNTER_START); 3853 } 3854 3855 /* 3856 * Configure descriptor poll timer 3857 * 3858 * SK-NET GENESIS data sheet says that possibility of losing Start 3859 * transmit command due to CPU/cache related interim storage problems 3860 * under certain conditions. The document recommends a polling 3861 * mechanism to send a Start transmit command to initiate transfer 3862 * of ready descriptors regulary. To cope with this issue sk(4) now 3863 * enables descriptor poll timer to initiate descriptor processing 3864 * periodically as defined by SK_DPT_TIMER_MAX. However sk(4) still 3865 * issue SK_TXBMU_TX_START to Tx BMU to get fast execution of Tx 3866 * command instead of waiting for next descriptor polling time. 3867 * The same rule may apply to Rx side too but it seems that is not 3868 * needed at the moment. 3869 * Since sk(4) uses descriptor polling as a last resort there is no 3870 * need to set smaller polling time than maximum allowable one. 3871 */ 3872 SK_IF_WRITE_4(sc_if, 0, SK_DPT_INIT, SK_DPT_TIMER_MAX); 3873 3874 /* Configure I2C registers */ 3875 3876 /* Configure XMAC(s) */ 3877 switch (sc->sk_type) { 3878 case SK_GENESIS: 3879 sk_init_xmac(sc_if); 3880 break; 3881 case SK_YUKON: 3882 case SK_YUKON_LITE: 3883 case SK_YUKON_LP: 3884 case SK_YUKON_EC: 3885 sk_init_yukon(sc_if); 3886 break; 3887 } 3888 mii_mediachg(mii); 3889 3890 if (sc->sk_type == SK_GENESIS) { 3891 /* Configure MAC FIFOs */ 3892 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 3893 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 3894 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 3895 3896 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 3897 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 3898 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 3899 } 3900 3901 /* Configure transmit arbiter(s) */ 3902 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 3903 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 3904 3905 /* Configure RAMbuffers */ 3906 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 3907 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 3908 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 3909 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 3910 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 3911 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 3912 3913 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 3914 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 3915 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 3916 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 3917 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 3918 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 3919 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 3920 3921 /* Configure BMUs */ 3922 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 3923 if (ifp->if_mtu > SK_MAX_FRAMELEN) { 3924 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 3925 SK_ADDR_LO(SK_JUMBO_RX_RING_ADDR(sc_if, 0))); 3926 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 3927 SK_ADDR_HI(SK_JUMBO_RX_RING_ADDR(sc_if, 0))); 3928 } else { 3929 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 3930 SK_ADDR_LO(SK_RX_RING_ADDR(sc_if, 0))); 3931 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 3932 SK_ADDR_HI(SK_RX_RING_ADDR(sc_if, 0))); 3933 } 3934 3935 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 3936 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 3937 SK_ADDR_LO(SK_TX_RING_ADDR(sc_if, 0))); 3938 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 3939 SK_ADDR_HI(SK_TX_RING_ADDR(sc_if, 0))); 3940 3941 /* Init descriptors */ 3942 if (ifp->if_mtu > SK_MAX_FRAMELEN) 3943 error = sk_init_jumbo_rx_ring(sc_if); 3944 else 3945 error = sk_init_rx_ring(sc_if); 3946 if (error != 0) { 3947 device_printf(sc_if->sk_if_dev, 3948 "initialization failed: no memory for rx buffers\n"); 3949 sk_stop(sc_if); 3950 return; 3951 } 3952 sk_init_tx_ring(sc_if); 3953 3954 /* Set interrupt moderation if changed via sysctl. */ 3955 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 3956 if (imr != SK_IM_USECS(sc->sk_int_mod, sc->sk_int_ticks)) { 3957 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod, 3958 sc->sk_int_ticks)); 3959 if (bootverbose) 3960 device_printf(sc_if->sk_if_dev, 3961 "interrupt moderation is %d us.\n", 3962 sc->sk_int_mod); 3963 } 3964 3965 /* Configure interrupt handling */ 3966 CSR_READ_4(sc, SK_ISSR); 3967 if (sc_if->sk_port == SK_PORT_A) 3968 sc->sk_intrmask |= SK_INTRS1; 3969 else 3970 sc->sk_intrmask |= SK_INTRS2; 3971 3972 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 3973 3974 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 3975 3976 /* Start BMUs. */ 3977 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 3978 3979 switch(sc->sk_type) { 3980 case SK_GENESIS: 3981 /* Enable XMACs TX and RX state machines */ 3982 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 3983 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 3984 break; 3985 case SK_YUKON: 3986 case SK_YUKON_LITE: 3987 case SK_YUKON_LP: 3988 case SK_YUKON_EC: 3989 reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 3990 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 3991 #if 0 3992 /* XXX disable 100Mbps and full duplex mode? */ 3993 reg &= ~(YU_GPCR_SPEED | YU_GPCR_DPLX_DIS); 3994 #endif 3995 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 3996 } 3997 3998 /* Activate descriptor polling timer */ 3999 SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_START); 4000 /* start transfer of Tx descriptors */ 4001 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 4002 4003 ifp->if_drv_flags |= IFF_DRV_RUNNING; 4004 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 4005 4006 switch (sc->sk_type) { 4007 case SK_YUKON: 4008 case SK_YUKON_LITE: 4009 case SK_YUKON_LP: 4010 case SK_YUKON_EC: 4011 callout_reset(&sc_if->sk_tick_ch, hz, sk_yukon_tick, sc_if); 4012 break; 4013 } 4014 4015 return; 4016 } 4017 4018 static void 4019 sk_stop(sc_if) 4020 struct sk_if_softc *sc_if; 4021 { 4022 int i; 4023 struct sk_softc *sc; 4024 struct sk_txdesc *txd; 4025 struct sk_rxdesc *rxd; 4026 struct sk_rxdesc *jrxd; 4027 struct ifnet *ifp; 4028 u_int32_t val; 4029 4030 SK_IF_LOCK_ASSERT(sc_if); 4031 sc = sc_if->sk_softc; 4032 ifp = sc_if->sk_ifp; 4033 4034 callout_stop(&sc_if->sk_tick_ch); 4035 4036 /* stop Tx descriptor polling timer */ 4037 SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP); 4038 /* stop transfer of Tx descriptors */ 4039 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_STOP); 4040 for (i = 0; i < SK_TIMEOUT; i++) { 4041 val = CSR_READ_4(sc, sc_if->sk_tx_bmu); 4042 if ((val & SK_TXBMU_TX_STOP) == 0) 4043 break; 4044 DELAY(1); 4045 } 4046 if (i == SK_TIMEOUT) 4047 device_printf(sc_if->sk_if_dev, 4048 "can not stop transfer of Tx descriptor\n"); 4049 /* stop transfer of Rx descriptors */ 4050 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_STOP); 4051 for (i = 0; i < SK_TIMEOUT; i++) { 4052 val = SK_IF_READ_4(sc_if, 0, SK_RXQ1_BMU_CSR); 4053 if ((val & SK_RXBMU_RX_STOP) == 0) 4054 break; 4055 DELAY(1); 4056 } 4057 if (i == SK_TIMEOUT) 4058 device_printf(sc_if->sk_if_dev, 4059 "can not stop transfer of Rx descriptor\n"); 4060 4061 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 4062 /* Put PHY back into reset. */ 4063 val = sk_win_read_4(sc, SK_GPIO); 4064 if (sc_if->sk_port == SK_PORT_A) { 4065 val |= SK_GPIO_DIR0; 4066 val &= ~SK_GPIO_DAT0; 4067 } else { 4068 val |= SK_GPIO_DIR2; 4069 val &= ~SK_GPIO_DAT2; 4070 } 4071 sk_win_write_4(sc, SK_GPIO, val); 4072 } 4073 4074 /* Turn off various components of this interface. */ 4075 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 4076 switch (sc->sk_type) { 4077 case SK_GENESIS: 4078 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_RESET); 4079 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 4080 break; 4081 case SK_YUKON: 4082 case SK_YUKON_LITE: 4083 case SK_YUKON_LP: 4084 case SK_YUKON_EC: 4085 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 4086 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 4087 break; 4088 } 4089 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 4090 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 4091 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 4092 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 4093 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 4094 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 4095 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 4096 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 4097 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 4098 4099 /* Disable interrupts */ 4100 if (sc_if->sk_port == SK_PORT_A) 4101 sc->sk_intrmask &= ~SK_INTRS1; 4102 else 4103 sc->sk_intrmask &= ~SK_INTRS2; 4104 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 4105 4106 SK_XM_READ_2(sc_if, XM_ISR); 4107 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 4108 4109 /* Free RX and TX mbufs still in the queues. */ 4110 for (i = 0; i < SK_RX_RING_CNT; i++) { 4111 rxd = &sc_if->sk_cdata.sk_rxdesc[i]; 4112 if (rxd->rx_m != NULL) { 4113 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag, 4114 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 4115 bus_dmamap_unload(sc_if->sk_cdata.sk_rx_tag, 4116 rxd->rx_dmamap); 4117 m_freem(rxd->rx_m); 4118 rxd->rx_m = NULL; 4119 } 4120 } 4121 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) { 4122 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i]; 4123 if (jrxd->rx_m != NULL) { 4124 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag, 4125 jrxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 4126 bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_tag, 4127 jrxd->rx_dmamap); 4128 m_freem(jrxd->rx_m); 4129 jrxd->rx_m = NULL; 4130 } 4131 } 4132 for (i = 0; i < SK_TX_RING_CNT; i++) { 4133 txd = &sc_if->sk_cdata.sk_txdesc[i]; 4134 if (txd->tx_m != NULL) { 4135 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag, 4136 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 4137 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag, 4138 txd->tx_dmamap); 4139 m_freem(txd->tx_m); 4140 txd->tx_m = NULL; 4141 } 4142 } 4143 4144 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING|IFF_DRV_OACTIVE); 4145 4146 return; 4147 } 4148 4149 static int 4150 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 4151 { 4152 int error, value; 4153 4154 if (!arg1) 4155 return (EINVAL); 4156 value = *(int *)arg1; 4157 error = sysctl_handle_int(oidp, &value, 0, req); 4158 if (error || !req->newptr) 4159 return (error); 4160 if (value < low || value > high) 4161 return (EINVAL); 4162 *(int *)arg1 = value; 4163 return (0); 4164 } 4165 4166 static int 4167 sysctl_hw_sk_int_mod(SYSCTL_HANDLER_ARGS) 4168 { 4169 return (sysctl_int_range(oidp, arg1, arg2, req, SK_IM_MIN, SK_IM_MAX)); 4170 } 4171