1 /* $OpenBSD: if_sk.c,v 2.33 2003/08/12 05:23:06 nate Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999, 2000 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 /*- 35 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 36 * 37 * Permission to use, copy, modify, and distribute this software for any 38 * purpose with or without fee is hereby granted, provided that the above 39 * copyright notice and this permission notice appear in all copies. 40 * 41 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 42 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 43 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 44 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 45 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 46 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 47 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 48 */ 49 50 #include <sys/cdefs.h> 51 __FBSDID("$FreeBSD$"); 52 53 /* 54 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 55 * the SK-984x series adapters, both single port and dual port. 56 * References: 57 * The XaQti XMAC II datasheet, 58 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 59 * The SysKonnect GEnesis manual, http://www.syskonnect.com 60 * 61 * Note: XaQti has been aquired by Vitesse, and Vitesse does not have the 62 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 63 * convenience to others until Vitesse corrects this problem: 64 * 65 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 66 * 67 * Written by Bill Paul <wpaul@ee.columbia.edu> 68 * Department of Electrical Engineering 69 * Columbia University, New York City 70 */ 71 /* 72 * The SysKonnect gigabit ethernet adapters consist of two main 73 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 74 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 75 * components and a PHY while the GEnesis controller provides a PCI 76 * interface with DMA support. Each card may have between 512K and 77 * 2MB of SRAM on board depending on the configuration. 78 * 79 * The SysKonnect GEnesis controller can have either one or two XMAC 80 * chips connected to it, allowing single or dual port NIC configurations. 81 * SysKonnect has the distinction of being the only vendor on the market 82 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 83 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 84 * XMAC registers. This driver takes advantage of these features to allow 85 * both XMACs to operate as independent interfaces. 86 */ 87 88 #include <sys/param.h> 89 #include <sys/systm.h> 90 #include <sys/bus.h> 91 #include <sys/endian.h> 92 #include <sys/mbuf.h> 93 #include <sys/malloc.h> 94 #include <sys/kernel.h> 95 #include <sys/module.h> 96 #include <sys/socket.h> 97 #include <sys/sockio.h> 98 #include <sys/queue.h> 99 #include <sys/sysctl.h> 100 101 #include <net/bpf.h> 102 #include <net/ethernet.h> 103 #include <net/if.h> 104 #include <net/if_arp.h> 105 #include <net/if_dl.h> 106 #include <net/if_media.h> 107 #include <net/if_types.h> 108 #include <net/if_vlan_var.h> 109 110 #include <netinet/in.h> 111 #include <netinet/in_systm.h> 112 #include <netinet/ip.h> 113 114 #include <machine/bus.h> 115 #include <machine/in_cksum.h> 116 #include <machine/resource.h> 117 #include <sys/rman.h> 118 119 #include <dev/mii/mii.h> 120 #include <dev/mii/miivar.h> 121 #include <dev/mii/brgphyreg.h> 122 123 #include <dev/pci/pcireg.h> 124 #include <dev/pci/pcivar.h> 125 126 #if 0 127 #define SK_USEIOSPACE 128 #endif 129 130 #include <dev/sk/if_skreg.h> 131 #include <dev/sk/xmaciireg.h> 132 #include <dev/sk/yukonreg.h> 133 134 MODULE_DEPEND(sk, pci, 1, 1, 1); 135 MODULE_DEPEND(sk, ether, 1, 1, 1); 136 MODULE_DEPEND(sk, miibus, 1, 1, 1); 137 138 /* "device miibus" required. See GENERIC if you get errors here. */ 139 #include "miibus_if.h" 140 141 #ifndef lint 142 static const char rcsid[] = 143 "$FreeBSD$"; 144 #endif 145 146 static struct sk_type sk_devs[] = { 147 { 148 VENDORID_SK, 149 DEVICEID_SK_V1, 150 "SysKonnect Gigabit Ethernet (V1.0)" 151 }, 152 { 153 VENDORID_SK, 154 DEVICEID_SK_V2, 155 "SysKonnect Gigabit Ethernet (V2.0)" 156 }, 157 { 158 VENDORID_MARVELL, 159 DEVICEID_SK_V2, 160 "Marvell Gigabit Ethernet" 161 }, 162 #ifdef not_yet 163 { 164 VENDORID_MARVELL, 165 DEVICEID_MRVL_4360, 166 "Marvell 88E8052 Gigabit Ethernet Controller" 167 }, 168 { 169 VENDORID_MARVELL, 170 DEVICEID_MRVL_4361, 171 "Marvell 88E8050 Gigabit Ethernet Controller" 172 }, 173 { 174 VENDORID_MARVELL, 175 DEVICEID_MRVL_4362, 176 "Marvell 88E8053 Gigabit Ethernet Controller" 177 }, 178 #endif 179 { 180 VENDORID_MARVELL, 181 DEVICEID_BELKIN_5005, 182 "Belkin F5D5005 Gigabit Ethernet" 183 }, 184 { 185 VENDORID_3COM, 186 DEVICEID_3COM_3C940, 187 "3Com 3C940 Gigabit Ethernet" 188 }, 189 { 190 VENDORID_LINKSYS, 191 DEVICEID_LINKSYS_EG1032, 192 "Linksys EG1032 Gigabit Ethernet" 193 }, 194 { 195 VENDORID_DLINK, 196 DEVICEID_DLINK_DGE530T, 197 "D-Link DGE-530T Gigabit Ethernet" 198 }, 199 { 0, 0, NULL } 200 }; 201 202 static int skc_probe(device_t); 203 static int skc_attach(device_t); 204 static int skc_detach(device_t); 205 static void skc_shutdown(device_t); 206 static int skc_suspend(device_t); 207 static int skc_resume(device_t); 208 static int sk_detach(device_t); 209 static int sk_probe(device_t); 210 static int sk_attach(device_t); 211 static void sk_tick(void *); 212 static void sk_yukon_tick(void *); 213 static void sk_intr(void *); 214 static void sk_intr_xmac(struct sk_if_softc *); 215 static void sk_intr_bcom(struct sk_if_softc *); 216 static void sk_intr_yukon(struct sk_if_softc *); 217 static __inline void sk_rxcksum(struct ifnet *, struct mbuf *, u_int32_t); 218 static __inline int sk_rxvalid(struct sk_softc *, u_int32_t, u_int32_t); 219 static void sk_rxeof(struct sk_if_softc *); 220 static void sk_jumbo_rxeof(struct sk_if_softc *); 221 static void sk_txeof(struct sk_if_softc *); 222 static void sk_txcksum(struct ifnet *, struct mbuf *, struct sk_tx_desc *); 223 static int sk_encap(struct sk_if_softc *, struct mbuf **); 224 static void sk_start(struct ifnet *); 225 static void sk_start_locked(struct ifnet *); 226 static int sk_ioctl(struct ifnet *, u_long, caddr_t); 227 static void sk_init(void *); 228 static void sk_init_locked(struct sk_if_softc *); 229 static void sk_init_xmac(struct sk_if_softc *); 230 static void sk_init_yukon(struct sk_if_softc *); 231 static void sk_stop(struct sk_if_softc *); 232 static void sk_watchdog(struct ifnet *); 233 static int sk_ifmedia_upd(struct ifnet *); 234 static void sk_ifmedia_sts(struct ifnet *, struct ifmediareq *); 235 static void sk_reset(struct sk_softc *); 236 static __inline void sk_discard_rxbuf(struct sk_if_softc *, int); 237 static __inline void sk_discard_jumbo_rxbuf(struct sk_if_softc *, int); 238 static int sk_newbuf(struct sk_if_softc *, int); 239 static int sk_jumbo_newbuf(struct sk_if_softc *, int); 240 static void sk_dmamap_cb(void *, bus_dma_segment_t *, int, int); 241 static int sk_dma_alloc(struct sk_if_softc *); 242 static void sk_dma_free(struct sk_if_softc *); 243 static void *sk_jalloc(struct sk_if_softc *); 244 static void sk_jfree(void *, void *); 245 static int sk_init_rx_ring(struct sk_if_softc *); 246 static int sk_init_jumbo_rx_ring(struct sk_if_softc *); 247 static void sk_init_tx_ring(struct sk_if_softc *); 248 static u_int32_t sk_win_read_4(struct sk_softc *, int); 249 static u_int16_t sk_win_read_2(struct sk_softc *, int); 250 static u_int8_t sk_win_read_1(struct sk_softc *, int); 251 static void sk_win_write_4(struct sk_softc *, int, u_int32_t); 252 static void sk_win_write_2(struct sk_softc *, int, u_int32_t); 253 static void sk_win_write_1(struct sk_softc *, int, u_int32_t); 254 static u_int8_t sk_vpd_readbyte(struct sk_softc *, int); 255 static void sk_vpd_read_res(struct sk_softc *, struct vpd_res *, int); 256 static void sk_vpd_read(struct sk_softc *); 257 258 static int sk_miibus_readreg(device_t, int, int); 259 static int sk_miibus_writereg(device_t, int, int, int); 260 static void sk_miibus_statchg(device_t); 261 262 static int sk_xmac_miibus_readreg(struct sk_if_softc *, int, int); 263 static int sk_xmac_miibus_writereg(struct sk_if_softc *, int, int, 264 int); 265 static void sk_xmac_miibus_statchg(struct sk_if_softc *); 266 267 static int sk_marv_miibus_readreg(struct sk_if_softc *, int, int); 268 static int sk_marv_miibus_writereg(struct sk_if_softc *, int, int, 269 int); 270 static void sk_marv_miibus_statchg(struct sk_if_softc *); 271 272 static uint32_t sk_xmchash(const uint8_t *); 273 static uint32_t sk_gmchash(const uint8_t *); 274 static void sk_setfilt(struct sk_if_softc *, u_int16_t *, int); 275 static void sk_setmulti(struct sk_if_softc *); 276 static void sk_setpromisc(struct sk_if_softc *); 277 278 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high); 279 static int sysctl_hw_sk_int_mod(SYSCTL_HANDLER_ARGS); 280 281 /* 282 * It seems that SK-NET GENESIS supports very simple checksum offload 283 * capability for Tx and I believe it can generate 0 checksum value for 284 * UDP packets in Tx as the hardware can't differenciate UDP packets from 285 * TCP packets. 0 chcecksum value for UDP packet is an invalid one as it 286 * means sender didn't perforam checksum computation. For the safety I 287 * disabled UDP checksum offload capability at the moment. Alternatively 288 * we can intrduce a LINK0/LINK1 flag as hme(4) did in its Tx checksum 289 * offload routine. 290 */ 291 #define SK_CSUM_FEATURES (CSUM_TCP) 292 293 /* 294 * Note that we have newbus methods for both the GEnesis controller 295 * itself and the XMAC(s). The XMACs are children of the GEnesis, and 296 * the miibus code is a child of the XMACs. We need to do it this way 297 * so that the miibus drivers can access the PHY registers on the 298 * right PHY. It's not quite what I had in mind, but it's the only 299 * design that achieves the desired effect. 300 */ 301 static device_method_t skc_methods[] = { 302 /* Device interface */ 303 DEVMETHOD(device_probe, skc_probe), 304 DEVMETHOD(device_attach, skc_attach), 305 DEVMETHOD(device_detach, skc_detach), 306 DEVMETHOD(device_suspend, skc_suspend), 307 DEVMETHOD(device_resume, skc_resume), 308 DEVMETHOD(device_shutdown, skc_shutdown), 309 310 /* bus interface */ 311 DEVMETHOD(bus_print_child, bus_generic_print_child), 312 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 313 314 { 0, 0 } 315 }; 316 317 static driver_t skc_driver = { 318 "skc", 319 skc_methods, 320 sizeof(struct sk_softc) 321 }; 322 323 static devclass_t skc_devclass; 324 325 static device_method_t sk_methods[] = { 326 /* Device interface */ 327 DEVMETHOD(device_probe, sk_probe), 328 DEVMETHOD(device_attach, sk_attach), 329 DEVMETHOD(device_detach, sk_detach), 330 DEVMETHOD(device_shutdown, bus_generic_shutdown), 331 332 /* bus interface */ 333 DEVMETHOD(bus_print_child, bus_generic_print_child), 334 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 335 336 /* MII interface */ 337 DEVMETHOD(miibus_readreg, sk_miibus_readreg), 338 DEVMETHOD(miibus_writereg, sk_miibus_writereg), 339 DEVMETHOD(miibus_statchg, sk_miibus_statchg), 340 341 { 0, 0 } 342 }; 343 344 static driver_t sk_driver = { 345 "sk", 346 sk_methods, 347 sizeof(struct sk_if_softc) 348 }; 349 350 static devclass_t sk_devclass; 351 352 DRIVER_MODULE(skc, pci, skc_driver, skc_devclass, 0, 0); 353 DRIVER_MODULE(sk, skc, sk_driver, sk_devclass, 0, 0); 354 DRIVER_MODULE(miibus, sk, miibus_driver, miibus_devclass, 0, 0); 355 356 static struct resource_spec sk_res_spec_io[] = { 357 { SYS_RES_IOPORT, PCIR_BAR(1), RF_ACTIVE }, 358 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 359 { -1, 0, 0 } 360 }; 361 362 static struct resource_spec sk_res_spec_mem[] = { 363 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 364 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 365 { -1, 0, 0 } 366 }; 367 368 #define SK_SETBIT(sc, reg, x) \ 369 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 370 371 #define SK_CLRBIT(sc, reg, x) \ 372 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 373 374 #define SK_WIN_SETBIT_4(sc, reg, x) \ 375 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x) 376 377 #define SK_WIN_CLRBIT_4(sc, reg, x) \ 378 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x) 379 380 #define SK_WIN_SETBIT_2(sc, reg, x) \ 381 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x) 382 383 #define SK_WIN_CLRBIT_2(sc, reg, x) \ 384 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x) 385 386 static u_int32_t 387 sk_win_read_4(sc, reg) 388 struct sk_softc *sc; 389 int reg; 390 { 391 #ifdef SK_USEIOSPACE 392 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 393 return(CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg))); 394 #else 395 return(CSR_READ_4(sc, reg)); 396 #endif 397 } 398 399 static u_int16_t 400 sk_win_read_2(sc, reg) 401 struct sk_softc *sc; 402 int reg; 403 { 404 #ifdef SK_USEIOSPACE 405 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 406 return(CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg))); 407 #else 408 return(CSR_READ_2(sc, reg)); 409 #endif 410 } 411 412 static u_int8_t 413 sk_win_read_1(sc, reg) 414 struct sk_softc *sc; 415 int reg; 416 { 417 #ifdef SK_USEIOSPACE 418 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 419 return(CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg))); 420 #else 421 return(CSR_READ_1(sc, reg)); 422 #endif 423 } 424 425 static void 426 sk_win_write_4(sc, reg, val) 427 struct sk_softc *sc; 428 int reg; 429 u_int32_t val; 430 { 431 #ifdef SK_USEIOSPACE 432 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 433 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), val); 434 #else 435 CSR_WRITE_4(sc, reg, val); 436 #endif 437 return; 438 } 439 440 static void 441 sk_win_write_2(sc, reg, val) 442 struct sk_softc *sc; 443 int reg; 444 u_int32_t val; 445 { 446 #ifdef SK_USEIOSPACE 447 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 448 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), val); 449 #else 450 CSR_WRITE_2(sc, reg, val); 451 #endif 452 return; 453 } 454 455 static void 456 sk_win_write_1(sc, reg, val) 457 struct sk_softc *sc; 458 int reg; 459 u_int32_t val; 460 { 461 #ifdef SK_USEIOSPACE 462 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 463 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), val); 464 #else 465 CSR_WRITE_1(sc, reg, val); 466 #endif 467 return; 468 } 469 470 /* 471 * The VPD EEPROM contains Vital Product Data, as suggested in 472 * the PCI 2.1 specification. The VPD data is separared into areas 473 * denoted by resource IDs. The SysKonnect VPD contains an ID string 474 * resource (the name of the adapter), a read-only area resource 475 * containing various key/data fields and a read/write area which 476 * can be used to store asset management information or log messages. 477 * We read the ID string and read-only into buffers attached to 478 * the controller softc structure for later use. At the moment, 479 * we only use the ID string during skc_attach(). 480 */ 481 static u_int8_t 482 sk_vpd_readbyte(sc, addr) 483 struct sk_softc *sc; 484 int addr; 485 { 486 int i; 487 488 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 489 for (i = 0; i < SK_TIMEOUT; i++) { 490 /* ASUS LOM takes a very long time to read VPD. */ 491 DELAY(100); 492 if (sk_win_read_2(sc, 493 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 494 break; 495 } 496 497 if (i == SK_TIMEOUT) 498 return(0); 499 500 return(sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA))); 501 } 502 503 static void 504 sk_vpd_read_res(sc, res, addr) 505 struct sk_softc *sc; 506 struct vpd_res *res; 507 int addr; 508 { 509 int i; 510 u_int8_t *ptr; 511 512 ptr = (u_int8_t *)res; 513 for (i = 0; i < sizeof(struct vpd_res); i++) 514 ptr[i] = sk_vpd_readbyte(sc, i + addr); 515 516 return; 517 } 518 519 static void 520 sk_vpd_read(sc) 521 struct sk_softc *sc; 522 { 523 int pos = 0, i; 524 struct vpd_res res; 525 526 /* Check VPD capability */ 527 if (sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_CAPID)) != PCIY_VPD) 528 return; 529 if (sc->sk_vpd_prodname != NULL) 530 free(sc->sk_vpd_prodname, M_DEVBUF); 531 if (sc->sk_vpd_readonly != NULL) 532 free(sc->sk_vpd_readonly, M_DEVBUF); 533 sc->sk_vpd_prodname = NULL; 534 sc->sk_vpd_readonly = NULL; 535 sc->sk_vpd_readonly_len = 0; 536 537 sk_vpd_read_res(sc, &res, pos); 538 539 /* 540 * Bail out quietly if the eeprom appears to be missing or empty. 541 */ 542 if (res.vr_id == 0xff && res.vr_len == 0xff && res.vr_pad == 0xff) 543 return; 544 545 if (res.vr_id != VPD_RES_ID) { 546 device_printf(sc->sk_dev, "bad VPD resource id: expected %x " 547 "got %x\n", VPD_RES_ID, res.vr_id); 548 return; 549 } 550 551 pos += sizeof(res); 552 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 553 if (sc->sk_vpd_prodname != NULL) { 554 for (i = 0; i < res.vr_len; i++) 555 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 556 sc->sk_vpd_prodname[i] = '\0'; 557 } 558 pos += res.vr_len; 559 560 sk_vpd_read_res(sc, &res, pos); 561 562 if (res.vr_id != VPD_RES_READ) { 563 device_printf(sc->sk_dev, "bad VPD resource id: expected %x " 564 "got %x\n", VPD_RES_READ, res.vr_id); 565 return; 566 } 567 568 pos += sizeof(res); 569 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 570 for (i = 0; i < res.vr_len; i++) 571 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 572 sc->sk_vpd_readonly_len = res.vr_len; 573 574 return; 575 } 576 577 static int 578 sk_miibus_readreg(dev, phy, reg) 579 device_t dev; 580 int phy, reg; 581 { 582 struct sk_if_softc *sc_if; 583 int v; 584 585 sc_if = device_get_softc(dev); 586 587 SK_IF_MII_LOCK(sc_if); 588 switch(sc_if->sk_softc->sk_type) { 589 case SK_GENESIS: 590 v = sk_xmac_miibus_readreg(sc_if, phy, reg); 591 break; 592 case SK_YUKON: 593 case SK_YUKON_LITE: 594 case SK_YUKON_LP: 595 case SK_YUKON_EC: 596 v = sk_marv_miibus_readreg(sc_if, phy, reg); 597 break; 598 default: 599 v = 0; 600 break; 601 } 602 SK_IF_MII_UNLOCK(sc_if); 603 604 return (v); 605 } 606 607 static int 608 sk_miibus_writereg(dev, phy, reg, val) 609 device_t dev; 610 int phy, reg, val; 611 { 612 struct sk_if_softc *sc_if; 613 int v; 614 615 sc_if = device_get_softc(dev); 616 617 SK_IF_MII_LOCK(sc_if); 618 switch(sc_if->sk_softc->sk_type) { 619 case SK_GENESIS: 620 v = sk_xmac_miibus_writereg(sc_if, phy, reg, val); 621 break; 622 case SK_YUKON: 623 case SK_YUKON_LITE: 624 case SK_YUKON_LP: 625 case SK_YUKON_EC: 626 v = sk_marv_miibus_writereg(sc_if, phy, reg, val); 627 break; 628 default: 629 v = 0; 630 break; 631 } 632 SK_IF_MII_UNLOCK(sc_if); 633 634 return (v); 635 } 636 637 static void 638 sk_miibus_statchg(dev) 639 device_t dev; 640 { 641 struct sk_if_softc *sc_if; 642 643 sc_if = device_get_softc(dev); 644 645 SK_IF_MII_LOCK(sc_if); 646 switch(sc_if->sk_softc->sk_type) { 647 case SK_GENESIS: 648 sk_xmac_miibus_statchg(sc_if); 649 break; 650 case SK_YUKON: 651 case SK_YUKON_LITE: 652 case SK_YUKON_LP: 653 case SK_YUKON_EC: 654 sk_marv_miibus_statchg(sc_if); 655 break; 656 } 657 SK_IF_MII_UNLOCK(sc_if); 658 659 return; 660 } 661 662 static int 663 sk_xmac_miibus_readreg(sc_if, phy, reg) 664 struct sk_if_softc *sc_if; 665 int phy, reg; 666 { 667 int i; 668 669 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 670 return(0); 671 672 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 673 SK_XM_READ_2(sc_if, XM_PHY_DATA); 674 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 675 for (i = 0; i < SK_TIMEOUT; i++) { 676 DELAY(1); 677 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 678 XM_MMUCMD_PHYDATARDY) 679 break; 680 } 681 682 if (i == SK_TIMEOUT) { 683 if_printf(sc_if->sk_ifp, "phy failed to come ready\n"); 684 return(0); 685 } 686 } 687 DELAY(1); 688 i = SK_XM_READ_2(sc_if, XM_PHY_DATA); 689 690 return(i); 691 } 692 693 static int 694 sk_xmac_miibus_writereg(sc_if, phy, reg, val) 695 struct sk_if_softc *sc_if; 696 int phy, reg, val; 697 { 698 int i; 699 700 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 701 for (i = 0; i < SK_TIMEOUT; i++) { 702 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 703 break; 704 } 705 706 if (i == SK_TIMEOUT) { 707 if_printf(sc_if->sk_ifp, "phy failed to come ready\n"); 708 return (ETIMEDOUT); 709 } 710 711 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 712 for (i = 0; i < SK_TIMEOUT; i++) { 713 DELAY(1); 714 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 715 break; 716 } 717 if (i == SK_TIMEOUT) 718 if_printf(sc_if->sk_ifp, "phy write timed out\n"); 719 720 return(0); 721 } 722 723 static void 724 sk_xmac_miibus_statchg(sc_if) 725 struct sk_if_softc *sc_if; 726 { 727 struct mii_data *mii; 728 729 mii = device_get_softc(sc_if->sk_miibus); 730 731 /* 732 * If this is a GMII PHY, manually set the XMAC's 733 * duplex mode accordingly. 734 */ 735 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 736 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 737 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 738 } else { 739 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 740 } 741 } 742 } 743 744 static int 745 sk_marv_miibus_readreg(sc_if, phy, reg) 746 struct sk_if_softc *sc_if; 747 int phy, reg; 748 { 749 u_int16_t val; 750 int i; 751 752 if (phy != 0 || 753 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 754 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 755 return(0); 756 } 757 758 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 759 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 760 761 for (i = 0; i < SK_TIMEOUT; i++) { 762 DELAY(1); 763 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 764 if (val & YU_SMICR_READ_VALID) 765 break; 766 } 767 768 if (i == SK_TIMEOUT) { 769 if_printf(sc_if->sk_ifp, "phy failed to come ready\n"); 770 return(0); 771 } 772 773 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 774 775 return(val); 776 } 777 778 static int 779 sk_marv_miibus_writereg(sc_if, phy, reg, val) 780 struct sk_if_softc *sc_if; 781 int phy, reg, val; 782 { 783 int i; 784 785 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 786 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 787 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 788 789 for (i = 0; i < SK_TIMEOUT; i++) { 790 DELAY(1); 791 if (SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY) 792 break; 793 } 794 if (i == SK_TIMEOUT) { 795 if_printf(sc_if->sk_ifp, "phy write timeout\n"); 796 return (0); 797 } 798 799 return(0); 800 } 801 802 static void 803 sk_marv_miibus_statchg(sc_if) 804 struct sk_if_softc *sc_if; 805 { 806 return; 807 } 808 809 #define HASH_BITS 6 810 811 static u_int32_t 812 sk_xmchash(addr) 813 const uint8_t *addr; 814 { 815 uint32_t crc; 816 817 /* Compute CRC for the address value. */ 818 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 819 820 return (~crc & ((1 << HASH_BITS) - 1)); 821 } 822 823 /* gmchash is just a big endian crc */ 824 static u_int32_t 825 sk_gmchash(addr) 826 const uint8_t *addr; 827 { 828 uint32_t crc; 829 830 /* Compute CRC for the address value. */ 831 crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 832 833 return (crc & ((1 << HASH_BITS) - 1)); 834 } 835 836 static void 837 sk_setfilt(sc_if, addr, slot) 838 struct sk_if_softc *sc_if; 839 u_int16_t *addr; 840 int slot; 841 { 842 int base; 843 844 base = XM_RXFILT_ENTRY(slot); 845 846 SK_XM_WRITE_2(sc_if, base, addr[0]); 847 SK_XM_WRITE_2(sc_if, base + 2, addr[1]); 848 SK_XM_WRITE_2(sc_if, base + 4, addr[2]); 849 850 return; 851 } 852 853 static void 854 sk_setmulti(sc_if) 855 struct sk_if_softc *sc_if; 856 { 857 struct sk_softc *sc = sc_if->sk_softc; 858 struct ifnet *ifp = sc_if->sk_ifp; 859 u_int32_t hashes[2] = { 0, 0 }; 860 int h = 0, i; 861 struct ifmultiaddr *ifma; 862 u_int16_t dummy[] = { 0, 0, 0 }; 863 u_int16_t maddr[(ETHER_ADDR_LEN+1)/2]; 864 865 SK_IF_LOCK_ASSERT(sc_if); 866 867 /* First, zot all the existing filters. */ 868 switch(sc->sk_type) { 869 case SK_GENESIS: 870 for (i = 1; i < XM_RXFILT_MAX; i++) 871 sk_setfilt(sc_if, dummy, i); 872 873 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 874 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 875 break; 876 case SK_YUKON: 877 case SK_YUKON_LITE: 878 case SK_YUKON_LP: 879 case SK_YUKON_EC: 880 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 881 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 882 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 883 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 884 break; 885 } 886 887 /* Now program new ones. */ 888 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 889 hashes[0] = 0xFFFFFFFF; 890 hashes[1] = 0xFFFFFFFF; 891 } else { 892 i = 1; 893 IF_ADDR_LOCK(ifp); 894 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, ifma_link) { 895 if (ifma->ifma_addr->sa_family != AF_LINK) 896 continue; 897 /* 898 * Program the first XM_RXFILT_MAX multicast groups 899 * into the perfect filter. For all others, 900 * use the hash table. 901 */ 902 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) { 903 bcopy(LLADDR( 904 (struct sockaddr_dl *)ifma->ifma_addr), 905 maddr, ETHER_ADDR_LEN); 906 sk_setfilt(sc_if, maddr, i); 907 i++; 908 continue; 909 } 910 911 switch(sc->sk_type) { 912 case SK_GENESIS: 913 bcopy(LLADDR( 914 (struct sockaddr_dl *)ifma->ifma_addr), 915 maddr, ETHER_ADDR_LEN); 916 h = sk_xmchash((const uint8_t *)maddr); 917 break; 918 case SK_YUKON: 919 case SK_YUKON_LITE: 920 case SK_YUKON_LP: 921 case SK_YUKON_EC: 922 bcopy(LLADDR( 923 (struct sockaddr_dl *)ifma->ifma_addr), 924 maddr, ETHER_ADDR_LEN); 925 h = sk_gmchash((const uint8_t *)maddr); 926 break; 927 } 928 if (h < 32) 929 hashes[0] |= (1 << h); 930 else 931 hashes[1] |= (1 << (h - 32)); 932 } 933 IF_ADDR_UNLOCK(ifp); 934 } 935 936 switch(sc->sk_type) { 937 case SK_GENESIS: 938 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 939 XM_MODE_RX_USE_PERFECT); 940 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 941 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 942 break; 943 case SK_YUKON: 944 case SK_YUKON_LITE: 945 case SK_YUKON_LP: 946 case SK_YUKON_EC: 947 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 948 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 949 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 950 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 951 break; 952 } 953 954 return; 955 } 956 957 static void 958 sk_setpromisc(sc_if) 959 struct sk_if_softc *sc_if; 960 { 961 struct sk_softc *sc = sc_if->sk_softc; 962 struct ifnet *ifp = sc_if->sk_ifp; 963 964 SK_IF_LOCK_ASSERT(sc_if); 965 966 switch(sc->sk_type) { 967 case SK_GENESIS: 968 if (ifp->if_flags & IFF_PROMISC) { 969 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 970 } else { 971 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 972 } 973 break; 974 case SK_YUKON: 975 case SK_YUKON_LITE: 976 case SK_YUKON_LP: 977 case SK_YUKON_EC: 978 if (ifp->if_flags & IFF_PROMISC) { 979 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 980 YU_RCR_UFLEN | YU_RCR_MUFLEN); 981 } else { 982 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 983 YU_RCR_UFLEN | YU_RCR_MUFLEN); 984 } 985 break; 986 } 987 988 return; 989 } 990 991 static int 992 sk_init_rx_ring(sc_if) 993 struct sk_if_softc *sc_if; 994 { 995 struct sk_ring_data *rd; 996 bus_addr_t addr; 997 u_int32_t csum_start; 998 int i; 999 1000 sc_if->sk_cdata.sk_rx_cons = 0; 1001 1002 csum_start = (ETHER_HDR_LEN + sizeof(struct ip)) << 16 | 1003 ETHER_HDR_LEN; 1004 rd = &sc_if->sk_rdata; 1005 bzero(rd->sk_rx_ring, sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 1006 for (i = 0; i < SK_RX_RING_CNT; i++) { 1007 if (sk_newbuf(sc_if, i) != 0) 1008 return (ENOBUFS); 1009 if (i == (SK_RX_RING_CNT - 1)) 1010 addr = SK_RX_RING_ADDR(sc_if, 0); 1011 else 1012 addr = SK_RX_RING_ADDR(sc_if, i + 1); 1013 rd->sk_rx_ring[i].sk_next = htole32(SK_ADDR_LO(addr)); 1014 rd->sk_rx_ring[i].sk_csum_start = htole32(csum_start); 1015 } 1016 1017 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag, 1018 sc_if->sk_cdata.sk_rx_ring_map, 1019 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1020 1021 return(0); 1022 } 1023 1024 static int 1025 sk_init_jumbo_rx_ring(sc_if) 1026 struct sk_if_softc *sc_if; 1027 { 1028 struct sk_ring_data *rd; 1029 bus_addr_t addr; 1030 u_int32_t csum_start; 1031 int i; 1032 1033 sc_if->sk_cdata.sk_jumbo_rx_cons = 0; 1034 1035 csum_start = ((ETHER_HDR_LEN + sizeof(struct ip)) << 16) | 1036 ETHER_HDR_LEN; 1037 rd = &sc_if->sk_rdata; 1038 bzero(rd->sk_jumbo_rx_ring, 1039 sizeof(struct sk_rx_desc) * SK_JUMBO_RX_RING_CNT); 1040 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) { 1041 if (sk_jumbo_newbuf(sc_if, i) != 0) 1042 return (ENOBUFS); 1043 if (i == (SK_JUMBO_RX_RING_CNT - 1)) 1044 addr = SK_JUMBO_RX_RING_ADDR(sc_if, 0); 1045 else 1046 addr = SK_JUMBO_RX_RING_ADDR(sc_if, i + 1); 1047 rd->sk_jumbo_rx_ring[i].sk_next = htole32(SK_ADDR_LO(addr)); 1048 rd->sk_jumbo_rx_ring[i].sk_csum_start = htole32(csum_start); 1049 } 1050 1051 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 1052 sc_if->sk_cdata.sk_jumbo_rx_ring_map, 1053 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1054 1055 return (0); 1056 } 1057 1058 static void 1059 sk_init_tx_ring(sc_if) 1060 struct sk_if_softc *sc_if; 1061 { 1062 struct sk_ring_data *rd; 1063 struct sk_txdesc *txd; 1064 bus_addr_t addr; 1065 int i; 1066 1067 STAILQ_INIT(&sc_if->sk_cdata.sk_txfreeq); 1068 STAILQ_INIT(&sc_if->sk_cdata.sk_txbusyq); 1069 1070 sc_if->sk_cdata.sk_tx_prod = 0; 1071 sc_if->sk_cdata.sk_tx_cons = 0; 1072 sc_if->sk_cdata.sk_tx_cnt = 0; 1073 1074 rd = &sc_if->sk_rdata; 1075 bzero(rd->sk_tx_ring, sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 1076 for (i = 0; i < SK_TX_RING_CNT; i++) { 1077 if (i == (SK_TX_RING_CNT - 1)) 1078 addr = SK_TX_RING_ADDR(sc_if, 0); 1079 else 1080 addr = SK_TX_RING_ADDR(sc_if, i + 1); 1081 rd->sk_tx_ring[i].sk_next = htole32(SK_ADDR_LO(addr)); 1082 txd = &sc_if->sk_cdata.sk_txdesc[i]; 1083 STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txfreeq, txd, tx_q); 1084 } 1085 1086 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag, 1087 sc_if->sk_cdata.sk_tx_ring_map, 1088 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1089 } 1090 1091 static __inline void 1092 sk_discard_rxbuf(sc_if, idx) 1093 struct sk_if_softc *sc_if; 1094 int idx; 1095 { 1096 struct sk_rx_desc *r; 1097 struct sk_rxdesc *rxd; 1098 struct mbuf *m; 1099 1100 1101 r = &sc_if->sk_rdata.sk_rx_ring[idx]; 1102 rxd = &sc_if->sk_cdata.sk_rxdesc[idx]; 1103 m = rxd->rx_m; 1104 r->sk_ctl = htole32(m->m_len | SK_RXSTAT | SK_OPCODE_CSUM); 1105 } 1106 1107 static __inline void 1108 sk_discard_jumbo_rxbuf(sc_if, idx) 1109 struct sk_if_softc *sc_if; 1110 int idx; 1111 { 1112 struct sk_rx_desc *r; 1113 struct sk_rxdesc *rxd; 1114 struct mbuf *m; 1115 1116 r = &sc_if->sk_rdata.sk_jumbo_rx_ring[idx]; 1117 rxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[idx]; 1118 m = rxd->rx_m; 1119 r->sk_ctl = htole32(m->m_len | SK_RXSTAT | SK_OPCODE_CSUM); 1120 } 1121 1122 static int 1123 sk_newbuf(sc_if, idx) 1124 struct sk_if_softc *sc_if; 1125 int idx; 1126 { 1127 struct sk_rx_desc *r; 1128 struct sk_rxdesc *rxd; 1129 struct mbuf *m; 1130 bus_dma_segment_t segs[1]; 1131 bus_dmamap_t map; 1132 int nsegs; 1133 1134 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1135 if (m == NULL) 1136 return (ENOBUFS); 1137 m->m_len = m->m_pkthdr.len = MCLBYTES; 1138 m_adj(m, ETHER_ALIGN); 1139 1140 if (bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_rx_tag, 1141 sc_if->sk_cdata.sk_rx_sparemap, m, segs, &nsegs, 0) != 0) { 1142 m_freem(m); 1143 return (ENOBUFS); 1144 } 1145 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1146 1147 rxd = &sc_if->sk_cdata.sk_rxdesc[idx]; 1148 if (rxd->rx_m != NULL) { 1149 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap, 1150 BUS_DMASYNC_POSTREAD); 1151 bus_dmamap_unload(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap); 1152 } 1153 map = rxd->rx_dmamap; 1154 rxd->rx_dmamap = sc_if->sk_cdata.sk_rx_sparemap; 1155 sc_if->sk_cdata.sk_rx_sparemap = map; 1156 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap, 1157 BUS_DMASYNC_PREREAD); 1158 rxd->rx_m = m; 1159 r = &sc_if->sk_rdata.sk_rx_ring[idx]; 1160 r->sk_data_lo = htole32(SK_ADDR_LO(segs[0].ds_addr)); 1161 r->sk_data_hi = htole32(SK_ADDR_HI(segs[0].ds_addr)); 1162 r->sk_ctl = htole32(segs[0].ds_len | SK_RXSTAT | SK_OPCODE_CSUM); 1163 1164 return (0); 1165 } 1166 1167 static int 1168 sk_jumbo_newbuf(sc_if, idx) 1169 struct sk_if_softc *sc_if; 1170 int idx; 1171 { 1172 struct sk_rx_desc *r; 1173 struct sk_rxdesc *rxd; 1174 struct mbuf *m; 1175 bus_dma_segment_t segs[1]; 1176 bus_dmamap_t map; 1177 int nsegs; 1178 void *buf; 1179 1180 MGETHDR(m, M_DONTWAIT, MT_DATA); 1181 if (m == NULL) 1182 return (ENOBUFS); 1183 buf = sk_jalloc(sc_if); 1184 if (buf == NULL) { 1185 m_freem(m); 1186 return (ENOBUFS); 1187 } 1188 /* Attach the buffer to the mbuf */ 1189 MEXTADD(m, buf, SK_JLEN, sk_jfree, (struct sk_if_softc *)sc_if, 0, 1190 EXT_NET_DRV); 1191 if ((m->m_flags & M_EXT) == 0) { 1192 m_freem(m); 1193 return (ENOBUFS); 1194 } 1195 m->m_pkthdr.len = m->m_len = SK_JLEN; 1196 /* 1197 * Adjust alignment so packet payload begins on a 1198 * longword boundary. Mandatory for Alpha, useful on 1199 * x86 too. 1200 */ 1201 m_adj(m, ETHER_ALIGN); 1202 1203 if (bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_jumbo_rx_tag, 1204 sc_if->sk_cdata.sk_jumbo_rx_sparemap, m, segs, &nsegs, 0) != 0) { 1205 m_freem(m); 1206 return (ENOBUFS); 1207 } 1208 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1209 1210 rxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[idx]; 1211 if (rxd->rx_m != NULL) { 1212 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag, rxd->rx_dmamap, 1213 BUS_DMASYNC_POSTREAD); 1214 bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_tag, 1215 rxd->rx_dmamap); 1216 } 1217 map = rxd->rx_dmamap; 1218 rxd->rx_dmamap = sc_if->sk_cdata.sk_jumbo_rx_sparemap; 1219 sc_if->sk_cdata.sk_jumbo_rx_sparemap = map; 1220 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag, rxd->rx_dmamap, 1221 BUS_DMASYNC_PREREAD); 1222 rxd->rx_m = m; 1223 r = &sc_if->sk_rdata.sk_jumbo_rx_ring[idx]; 1224 r->sk_data_lo = htole32(SK_ADDR_LO(segs[0].ds_addr)); 1225 r->sk_data_hi = htole32(SK_ADDR_HI(segs[0].ds_addr)); 1226 r->sk_ctl = htole32(segs[0].ds_len | SK_RXSTAT | SK_OPCODE_CSUM); 1227 1228 return (0); 1229 } 1230 1231 /* 1232 * Set media options. 1233 */ 1234 static int 1235 sk_ifmedia_upd(ifp) 1236 struct ifnet *ifp; 1237 { 1238 struct sk_if_softc *sc_if = ifp->if_softc; 1239 struct mii_data *mii; 1240 1241 mii = device_get_softc(sc_if->sk_miibus); 1242 sk_init(sc_if); 1243 mii_mediachg(mii); 1244 1245 return(0); 1246 } 1247 1248 /* 1249 * Report current media status. 1250 */ 1251 static void 1252 sk_ifmedia_sts(ifp, ifmr) 1253 struct ifnet *ifp; 1254 struct ifmediareq *ifmr; 1255 { 1256 struct sk_if_softc *sc_if; 1257 struct mii_data *mii; 1258 1259 sc_if = ifp->if_softc; 1260 mii = device_get_softc(sc_if->sk_miibus); 1261 1262 mii_pollstat(mii); 1263 ifmr->ifm_active = mii->mii_media_active; 1264 ifmr->ifm_status = mii->mii_media_status; 1265 1266 return; 1267 } 1268 1269 static int 1270 sk_ioctl(ifp, command, data) 1271 struct ifnet *ifp; 1272 u_long command; 1273 caddr_t data; 1274 { 1275 struct sk_if_softc *sc_if = ifp->if_softc; 1276 struct ifreq *ifr = (struct ifreq *) data; 1277 int error, mask; 1278 struct mii_data *mii; 1279 1280 error = 0; 1281 switch(command) { 1282 case SIOCSIFMTU: 1283 SK_IF_LOCK(sc_if); 1284 if (ifr->ifr_mtu > SK_JUMBO_MTU) 1285 error = EINVAL; 1286 else { 1287 ifp->if_mtu = ifr->ifr_mtu; 1288 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1289 sk_init_locked(sc_if); 1290 } 1291 SK_IF_UNLOCK(sc_if); 1292 break; 1293 case SIOCSIFFLAGS: 1294 SK_IF_LOCK(sc_if); 1295 if (ifp->if_flags & IFF_UP) { 1296 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1297 if ((ifp->if_flags ^ sc_if->sk_if_flags) 1298 & IFF_PROMISC) { 1299 sk_setpromisc(sc_if); 1300 sk_setmulti(sc_if); 1301 } 1302 } else 1303 sk_init_locked(sc_if); 1304 } else { 1305 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1306 sk_stop(sc_if); 1307 } 1308 sc_if->sk_if_flags = ifp->if_flags; 1309 SK_IF_UNLOCK(sc_if); 1310 break; 1311 case SIOCADDMULTI: 1312 case SIOCDELMULTI: 1313 SK_IF_LOCK(sc_if); 1314 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1315 sk_setmulti(sc_if); 1316 SK_IF_UNLOCK(sc_if); 1317 break; 1318 case SIOCGIFMEDIA: 1319 case SIOCSIFMEDIA: 1320 mii = device_get_softc(sc_if->sk_miibus); 1321 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1322 break; 1323 case SIOCSIFCAP: 1324 SK_IF_LOCK(sc_if); 1325 if (sc_if->sk_softc->sk_type == SK_GENESIS) { 1326 SK_IF_UNLOCK(sc_if); 1327 break; 1328 } 1329 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1330 if (mask & IFCAP_HWCSUM) { 1331 ifp->if_capenable ^= IFCAP_HWCSUM; 1332 if (IFCAP_HWCSUM & ifp->if_capenable && 1333 IFCAP_HWCSUM & ifp->if_capabilities) 1334 ifp->if_hwassist = SK_CSUM_FEATURES; 1335 else 1336 ifp->if_hwassist = 0; 1337 } 1338 SK_IF_UNLOCK(sc_if); 1339 break; 1340 default: 1341 error = ether_ioctl(ifp, command, data); 1342 break; 1343 } 1344 1345 return (error); 1346 } 1347 1348 /* 1349 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 1350 * IDs against our list and return a device name if we find a match. 1351 */ 1352 static int 1353 skc_probe(dev) 1354 device_t dev; 1355 { 1356 struct sk_type *t = sk_devs; 1357 1358 while(t->sk_name != NULL) { 1359 if ((pci_get_vendor(dev) == t->sk_vid) && 1360 (pci_get_device(dev) == t->sk_did)) { 1361 /* 1362 * Only attach to rev. 2 of the Linksys EG1032 adapter. 1363 * Rev. 3 is supported by re(4). 1364 */ 1365 if ((t->sk_vid == VENDORID_LINKSYS) && 1366 (t->sk_did == DEVICEID_LINKSYS_EG1032) && 1367 (pci_get_subdevice(dev) != 1368 SUBDEVICEID_LINKSYS_EG1032_REV2)) { 1369 t++; 1370 continue; 1371 } 1372 device_set_desc(dev, t->sk_name); 1373 return (BUS_PROBE_DEFAULT); 1374 } 1375 t++; 1376 } 1377 1378 return(ENXIO); 1379 } 1380 1381 /* 1382 * Force the GEnesis into reset, then bring it out of reset. 1383 */ 1384 static void 1385 sk_reset(sc) 1386 struct sk_softc *sc; 1387 { 1388 1389 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 1390 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 1391 if (SK_YUKON_FAMILY(sc->sk_type)) 1392 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 1393 1394 DELAY(1000); 1395 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 1396 DELAY(2); 1397 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1398 if (SK_YUKON_FAMILY(sc->sk_type)) 1399 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 1400 1401 if (sc->sk_type == SK_GENESIS) { 1402 /* Configure packet arbiter */ 1403 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1404 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1405 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1406 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1407 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1408 } 1409 1410 /* Enable RAM interface */ 1411 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1412 1413 /* 1414 * Configure interrupt moderation. The moderation timer 1415 * defers interrupts specified in the interrupt moderation 1416 * timer mask based on the timeout specified in the interrupt 1417 * moderation timer init register. Each bit in the timer 1418 * register represents one tick, so to specify a timeout in 1419 * microseconds, we have to multiply by the correct number of 1420 * ticks-per-microsecond. 1421 */ 1422 switch (sc->sk_type) { 1423 case SK_GENESIS: 1424 sc->sk_int_ticks = SK_IMTIMER_TICKS_GENESIS; 1425 break; 1426 case SK_YUKON_EC: 1427 sc->sk_int_ticks = SK_IMTIMER_TICKS_YUKON_EC; 1428 break; 1429 default: 1430 sc->sk_int_ticks = SK_IMTIMER_TICKS_YUKON; 1431 break; 1432 } 1433 if (bootverbose) 1434 device_printf(sc->sk_dev, "interrupt moderation is %d us\n", 1435 sc->sk_int_mod); 1436 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod, 1437 sc->sk_int_ticks)); 1438 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 1439 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 1440 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1441 1442 return; 1443 } 1444 1445 static int 1446 sk_probe(dev) 1447 device_t dev; 1448 { 1449 struct sk_softc *sc; 1450 1451 sc = device_get_softc(device_get_parent(dev)); 1452 1453 /* 1454 * Not much to do here. We always know there will be 1455 * at least one XMAC present, and if there are two, 1456 * skc_attach() will create a second device instance 1457 * for us. 1458 */ 1459 switch (sc->sk_type) { 1460 case SK_GENESIS: 1461 device_set_desc(dev, "XaQti Corp. XMAC II"); 1462 break; 1463 case SK_YUKON: 1464 case SK_YUKON_LITE: 1465 case SK_YUKON_LP: 1466 case SK_YUKON_EC: 1467 device_set_desc(dev, "Marvell Semiconductor, Inc. Yukon"); 1468 break; 1469 } 1470 1471 return (BUS_PROBE_DEFAULT); 1472 } 1473 1474 /* 1475 * Each XMAC chip is attached as a separate logical IP interface. 1476 * Single port cards will have only one logical interface of course. 1477 */ 1478 static int 1479 sk_attach(dev) 1480 device_t dev; 1481 { 1482 struct sk_softc *sc; 1483 struct sk_if_softc *sc_if; 1484 struct ifnet *ifp; 1485 int i, port, error; 1486 u_char eaddr[6]; 1487 1488 if (dev == NULL) 1489 return(EINVAL); 1490 1491 error = 0; 1492 sc_if = device_get_softc(dev); 1493 sc = device_get_softc(device_get_parent(dev)); 1494 port = *(int *)device_get_ivars(dev); 1495 1496 sc_if->sk_if_dev = dev; 1497 sc_if->sk_port = port; 1498 sc_if->sk_softc = sc; 1499 sc->sk_if[port] = sc_if; 1500 if (port == SK_PORT_A) 1501 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1502 if (port == SK_PORT_B) 1503 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1504 1505 callout_init_mtx(&sc_if->sk_tick_ch, &sc_if->sk_softc->sk_mtx, 0); 1506 1507 if (sk_dma_alloc(sc_if) != 0) { 1508 error = ENOMEM; 1509 goto fail; 1510 } 1511 1512 ifp = sc_if->sk_ifp = if_alloc(IFT_ETHER); 1513 if (ifp == NULL) { 1514 device_printf(sc_if->sk_if_dev, "can not if_alloc()\n"); 1515 error = ENOSPC; 1516 goto fail; 1517 } 1518 ifp->if_softc = sc_if; 1519 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1520 ifp->if_mtu = ETHERMTU; 1521 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1522 /* 1523 * SK_GENESIS has a bug in checksum offload - From linux. 1524 */ 1525 if (sc_if->sk_softc->sk_type != SK_GENESIS) { 1526 ifp->if_capabilities = IFCAP_HWCSUM; 1527 ifp->if_hwassist = SK_CSUM_FEATURES; 1528 } else { 1529 ifp->if_capabilities = 0; 1530 ifp->if_hwassist = 0; 1531 } 1532 ifp->if_capenable = ifp->if_capabilities; 1533 ifp->if_ioctl = sk_ioctl; 1534 ifp->if_start = sk_start; 1535 ifp->if_watchdog = sk_watchdog; 1536 ifp->if_init = sk_init; 1537 IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1); 1538 ifp->if_snd.ifq_drv_maxlen = SK_TX_RING_CNT - 1; 1539 IFQ_SET_READY(&ifp->if_snd); 1540 1541 /* 1542 * Get station address for this interface. Note that 1543 * dual port cards actually come with three station 1544 * addresses: one for each port, plus an extra. The 1545 * extra one is used by the SysKonnect driver software 1546 * as a 'virtual' station address for when both ports 1547 * are operating in failover mode. Currently we don't 1548 * use this extra address. 1549 */ 1550 SK_IF_LOCK(sc_if); 1551 for (i = 0; i < ETHER_ADDR_LEN; i++) 1552 eaddr[i] = 1553 sk_win_read_1(sc, SK_MAC0_0 + (port * 8) + i); 1554 1555 /* 1556 * Set up RAM buffer addresses. The NIC will have a certain 1557 * amount of SRAM on it, somewhere between 512K and 2MB. We 1558 * need to divide this up a) between the transmitter and 1559 * receiver and b) between the two XMACs, if this is a 1560 * dual port NIC. Our algotithm is to divide up the memory 1561 * evenly so that everyone gets a fair share. 1562 * 1563 * Just to be contrary, Yukon2 appears to have separate memory 1564 * for each MAC. 1565 */ 1566 if (SK_IS_YUKON2(sc) || 1567 sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1568 u_int32_t chunk, val; 1569 1570 chunk = sc->sk_ramsize / 2; 1571 val = sc->sk_rboff / sizeof(u_int64_t); 1572 sc_if->sk_rx_ramstart = val; 1573 val += (chunk / sizeof(u_int64_t)); 1574 sc_if->sk_rx_ramend = val - 1; 1575 sc_if->sk_tx_ramstart = val; 1576 val += (chunk / sizeof(u_int64_t)); 1577 sc_if->sk_tx_ramend = val - 1; 1578 } else { 1579 u_int32_t chunk, val; 1580 1581 chunk = sc->sk_ramsize / 4; 1582 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1583 sizeof(u_int64_t); 1584 sc_if->sk_rx_ramstart = val; 1585 val += (chunk / sizeof(u_int64_t)); 1586 sc_if->sk_rx_ramend = val - 1; 1587 sc_if->sk_tx_ramstart = val; 1588 val += (chunk / sizeof(u_int64_t)); 1589 sc_if->sk_tx_ramend = val - 1; 1590 } 1591 1592 /* Read and save PHY type and set PHY address */ 1593 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1594 if (!SK_YUKON_FAMILY(sc->sk_type)) { 1595 switch(sc_if->sk_phytype) { 1596 case SK_PHYTYPE_XMAC: 1597 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1598 break; 1599 case SK_PHYTYPE_BCOM: 1600 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1601 break; 1602 default: 1603 device_printf(sc->sk_dev, "unsupported PHY type: %d\n", 1604 sc_if->sk_phytype); 1605 error = ENODEV; 1606 SK_IF_UNLOCK(sc_if); 1607 goto fail; 1608 } 1609 } else { 1610 if (sc_if->sk_phytype < SK_PHYTYPE_MARV_COPPER && 1611 sc->sk_pmd != 'S') { 1612 /* not initialized, punt */ 1613 sc_if->sk_phytype = SK_PHYTYPE_MARV_COPPER; 1614 sc->sk_coppertype = 1; 1615 } 1616 1617 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1618 1619 if (!(sc->sk_coppertype)) 1620 sc_if->sk_phytype = SK_PHYTYPE_MARV_FIBER; 1621 } 1622 1623 /* 1624 * Call MI attach routine. Can't hold locks when calling into ether_*. 1625 */ 1626 SK_IF_UNLOCK(sc_if); 1627 ether_ifattach(ifp, eaddr); 1628 SK_IF_LOCK(sc_if); 1629 1630 /* 1631 * The hardware should be ready for VLAN_MTU by default: 1632 * XMAC II has 0x8100 in VLAN Tag Level 1 register initially; 1633 * YU_SMR_MFL_VLAN is set by this driver in Yukon. 1634 * 1635 */ 1636 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1637 ifp->if_capenable |= IFCAP_VLAN_MTU; 1638 /* 1639 * Tell the upper layer(s) we support long frames. 1640 * Must appear after the call to ether_ifattach() because 1641 * ether_ifattach() sets ifi_hdrlen to the default value. 1642 */ 1643 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1644 1645 /* 1646 * Do miibus setup. 1647 */ 1648 switch (sc->sk_type) { 1649 case SK_GENESIS: 1650 sk_init_xmac(sc_if); 1651 break; 1652 case SK_YUKON: 1653 case SK_YUKON_LITE: 1654 case SK_YUKON_LP: 1655 case SK_YUKON_EC: 1656 sk_init_yukon(sc_if); 1657 break; 1658 } 1659 1660 SK_IF_UNLOCK(sc_if); 1661 if (mii_phy_probe(dev, &sc_if->sk_miibus, 1662 sk_ifmedia_upd, sk_ifmedia_sts)) { 1663 device_printf(sc_if->sk_if_dev, "no PHY found!\n"); 1664 ether_ifdetach(ifp); 1665 error = ENXIO; 1666 goto fail; 1667 } 1668 1669 fail: 1670 if (error) { 1671 /* Access should be ok even though lock has been dropped */ 1672 sc->sk_if[port] = NULL; 1673 sk_detach(dev); 1674 } 1675 1676 return(error); 1677 } 1678 1679 /* 1680 * Attach the interface. Allocate softc structures, do ifmedia 1681 * setup and ethernet/BPF attach. 1682 */ 1683 static int 1684 skc_attach(dev) 1685 device_t dev; 1686 { 1687 struct sk_softc *sc; 1688 int error = 0, *port, sk_macs; 1689 uint8_t skrs; 1690 char *pname, *revstr; 1691 1692 sc = device_get_softc(dev); 1693 sc->sk_dev = dev; 1694 1695 mtx_init(&sc->sk_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1696 MTX_DEF); 1697 mtx_init(&sc->sk_mii_mtx, "sk_mii_mutex", NULL, MTX_DEF); 1698 /* 1699 * Map control/status registers. 1700 */ 1701 pci_enable_busmaster(dev); 1702 1703 /* Allocate resources */ 1704 #ifdef SK_USEIOSPACE 1705 sc->sk_res_spec = sk_res_spec_io; 1706 #else 1707 sc->sk_res_spec = sk_res_spec_mem; 1708 #endif 1709 error = bus_alloc_resources(dev, sc->sk_res_spec, sc->sk_res); 1710 if (error) { 1711 if (sc->sk_res_spec == sk_res_spec_mem) 1712 sc->sk_res_spec = sk_res_spec_io; 1713 else 1714 sc->sk_res_spec = sk_res_spec_mem; 1715 error = bus_alloc_resources(dev, sc->sk_res_spec, sc->sk_res); 1716 if (error) { 1717 device_printf(dev, "couldn't allocate %s resources\n", 1718 sc->sk_res_spec == sk_res_spec_mem ? "memory" : 1719 "I/O"); 1720 goto fail; 1721 } 1722 } 1723 1724 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1725 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4) & 0xf; 1726 1727 /* Bail out if chip is not recognized. */ 1728 if (sc->sk_type != SK_GENESIS && !SK_YUKON_FAMILY(sc->sk_type)) { 1729 device_printf(dev, "unknown device: chipver=%02x, rev=%x\n", 1730 sc->sk_type, sc->sk_rev); 1731 error = ENXIO; 1732 goto fail; 1733 } 1734 1735 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 1736 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 1737 OID_AUTO, "int_mod", CTLTYPE_INT|CTLFLAG_RW, 1738 &sc->sk_int_mod, 0, sysctl_hw_sk_int_mod, "I", 1739 "SK interrupt moderation"); 1740 1741 /* Pull in device tunables. */ 1742 sc->sk_int_mod = SK_IM_DEFAULT; 1743 error = resource_int_value(device_get_name(dev), device_get_unit(dev), 1744 "int_mod", &sc->sk_int_mod); 1745 if (error == 0) { 1746 if (sc->sk_int_mod < SK_IM_MIN || 1747 sc->sk_int_mod > SK_IM_MAX) { 1748 device_printf(dev, "int_mod value out of range; " 1749 "using default: %d\n", SK_IM_DEFAULT); 1750 sc->sk_int_mod = SK_IM_DEFAULT; 1751 } 1752 } 1753 1754 /* Reset the adapter. */ 1755 sk_reset(sc); 1756 1757 /* Read and save vital product data from EEPROM. */ 1758 sk_vpd_read(sc); 1759 1760 skrs = sk_win_read_1(sc, SK_EPROM0); 1761 if (sc->sk_type == SK_GENESIS) { 1762 /* Read and save RAM size and RAMbuffer offset */ 1763 switch(skrs) { 1764 case SK_RAMSIZE_512K_64: 1765 sc->sk_ramsize = 0x80000; 1766 sc->sk_rboff = SK_RBOFF_0; 1767 break; 1768 case SK_RAMSIZE_1024K_64: 1769 sc->sk_ramsize = 0x100000; 1770 sc->sk_rboff = SK_RBOFF_80000; 1771 break; 1772 case SK_RAMSIZE_1024K_128: 1773 sc->sk_ramsize = 0x100000; 1774 sc->sk_rboff = SK_RBOFF_0; 1775 break; 1776 case SK_RAMSIZE_2048K_128: 1777 sc->sk_ramsize = 0x200000; 1778 sc->sk_rboff = SK_RBOFF_0; 1779 break; 1780 default: 1781 device_printf(dev, "unknown ram size: %d\n", skrs); 1782 error = ENXIO; 1783 goto fail; 1784 } 1785 } else { /* SK_YUKON_FAMILY */ 1786 if (skrs == 0x00) 1787 sc->sk_ramsize = 0x20000; 1788 else 1789 sc->sk_ramsize = skrs * (1<<12); 1790 sc->sk_rboff = SK_RBOFF_0; 1791 } 1792 1793 /* Read and save physical media type */ 1794 sc->sk_pmd = sk_win_read_1(sc, SK_PMDTYPE); 1795 1796 if (sc->sk_pmd == 'T' || sc->sk_pmd == '1') 1797 sc->sk_coppertype = 1; 1798 else 1799 sc->sk_coppertype = 0; 1800 1801 /* Determine whether to name it with VPD PN or just make it up. 1802 * Marvell Yukon VPD PN seems to freqently be bogus. */ 1803 switch (pci_get_device(dev)) { 1804 case DEVICEID_SK_V1: 1805 case DEVICEID_BELKIN_5005: 1806 case DEVICEID_3COM_3C940: 1807 case DEVICEID_LINKSYS_EG1032: 1808 case DEVICEID_DLINK_DGE530T: 1809 /* Stay with VPD PN. */ 1810 pname = sc->sk_vpd_prodname; 1811 break; 1812 case DEVICEID_SK_V2: 1813 case DEVICEID_MRVL_4360: 1814 case DEVICEID_MRVL_4361: 1815 case DEVICEID_MRVL_4362: 1816 /* YUKON VPD PN might bear no resemblance to reality. */ 1817 switch (sc->sk_type) { 1818 case SK_GENESIS: 1819 /* Stay with VPD PN. */ 1820 pname = sc->sk_vpd_prodname; 1821 break; 1822 case SK_YUKON: 1823 pname = "Marvell Yukon Gigabit Ethernet"; 1824 break; 1825 case SK_YUKON_LITE: 1826 pname = "Marvell Yukon Lite Gigabit Ethernet"; 1827 break; 1828 case SK_YUKON_LP: 1829 pname = "Marvell Yukon LP Gigabit Ethernet"; 1830 break; 1831 case SK_YUKON_EC: 1832 pname = "Marvell Yukon-2 EC Gigabit Ethernet"; 1833 break; 1834 default: 1835 pname = "Marvell Yukon (Unknown) Gigabit Ethernet"; 1836 break; 1837 } 1838 1839 /* Yukon Lite Rev. A0 needs special test. */ 1840 if (sc->sk_type == SK_YUKON || sc->sk_type == SK_YUKON_LP) { 1841 u_int32_t far; 1842 u_int8_t testbyte; 1843 1844 /* Save flash address register before testing. */ 1845 far = sk_win_read_4(sc, SK_EP_ADDR); 1846 1847 sk_win_write_1(sc, SK_EP_ADDR+0x03, 0xff); 1848 testbyte = sk_win_read_1(sc, SK_EP_ADDR+0x03); 1849 1850 if (testbyte != 0x00) { 1851 /* Yukon Lite Rev. A0 detected. */ 1852 sc->sk_type = SK_YUKON_LITE; 1853 sc->sk_rev = SK_YUKON_LITE_REV_A0; 1854 /* Restore flash address register. */ 1855 sk_win_write_4(sc, SK_EP_ADDR, far); 1856 } 1857 } 1858 break; 1859 default: 1860 device_printf(dev, "unknown device: vendor=%04x, device=%04x, " 1861 "chipver=%02x, rev=%x\n", 1862 pci_get_vendor(dev), pci_get_device(dev), 1863 sc->sk_type, sc->sk_rev); 1864 error = ENXIO; 1865 goto fail; 1866 } 1867 1868 if (sc->sk_type == SK_YUKON_LITE) { 1869 switch (sc->sk_rev) { 1870 case SK_YUKON_LITE_REV_A0: 1871 revstr = "A0"; 1872 break; 1873 case SK_YUKON_LITE_REV_A1: 1874 revstr = "A1"; 1875 break; 1876 case SK_YUKON_LITE_REV_A3: 1877 revstr = "A3"; 1878 break; 1879 default: 1880 revstr = ""; 1881 break; 1882 } 1883 } else if (sc->sk_type == SK_YUKON_EC) { 1884 switch (sc->sk_rev) { 1885 case SK_YUKON_EC_REV_A1: 1886 revstr = "A1"; 1887 break; 1888 case SK_YUKON_EC_REV_A2: 1889 revstr = "A2"; 1890 break; 1891 case SK_YUKON_EC_REV_A3: 1892 revstr = "A3"; 1893 break; 1894 default: 1895 revstr = ""; 1896 break; 1897 } 1898 } else { 1899 revstr = ""; 1900 } 1901 1902 /* Announce the product name and more VPD data if there. */ 1903 device_printf(dev, "%s rev. %s(0x%x)\n", 1904 pname != NULL ? pname : "<unknown>", revstr, sc->sk_rev); 1905 1906 if (bootverbose) { 1907 if (sc->sk_vpd_readonly != NULL && 1908 sc->sk_vpd_readonly_len != 0) { 1909 char buf[256]; 1910 char *dp = sc->sk_vpd_readonly; 1911 uint16_t l, len = sc->sk_vpd_readonly_len; 1912 1913 while (len >= 3) { 1914 if ((*dp == 'P' && *(dp+1) == 'N') || 1915 (*dp == 'E' && *(dp+1) == 'C') || 1916 (*dp == 'M' && *(dp+1) == 'N') || 1917 (*dp == 'S' && *(dp+1) == 'N')) { 1918 l = 0; 1919 while (l < *(dp+2)) { 1920 buf[l] = *(dp+3+l); 1921 ++l; 1922 } 1923 buf[l] = '\0'; 1924 device_printf(dev, "%c%c: %s\n", 1925 *dp, *(dp+1), buf); 1926 len -= (3 + l); 1927 dp += (3 + l); 1928 } else { 1929 len -= (3 + *(dp+2)); 1930 dp += (3 + *(dp+2)); 1931 } 1932 } 1933 } 1934 device_printf(dev, "chip ver = 0x%02x\n", sc->sk_type); 1935 device_printf(dev, "chip rev = 0x%02x\n", sc->sk_rev); 1936 device_printf(dev, "SK_EPROM0 = 0x%02x\n", skrs); 1937 device_printf(dev, "SRAM size = 0x%06x\n", sc->sk_ramsize); 1938 } 1939 1940 sc->sk_devs[SK_PORT_A] = device_add_child(dev, "sk", -1); 1941 if (sc->sk_devs[SK_PORT_A] == NULL) { 1942 device_printf(dev, "failed to add child for PORT_A\n"); 1943 error = ENXIO; 1944 goto fail; 1945 } 1946 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT); 1947 if (port == NULL) { 1948 device_printf(dev, "failed to allocate memory for " 1949 "ivars of PORT_A\n"); 1950 error = ENXIO; 1951 goto fail; 1952 } 1953 *port = SK_PORT_A; 1954 device_set_ivars(sc->sk_devs[SK_PORT_A], port); 1955 1956 sk_macs = 1; 1957 1958 if (SK_IS_YUKON2(sc)) { 1959 u_int8_t hw; 1960 1961 hw = sk_win_read_1(sc, SK_Y2_HWRES); 1962 if ((hw & SK_Y2_HWRES_LINK_MASK) == SK_Y2_HWRES_LINK_DUAL) { 1963 if ((sk_win_read_1(sc, SK_Y2_CLKGATE) & 1964 SK_Y2_CLKGATE_LINK2_INACTIVE) == 0) 1965 sk_macs++; 1966 } 1967 } else { 1968 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) 1969 sk_macs++; 1970 } 1971 1972 if (sk_macs > 1) { 1973 sc->sk_devs[SK_PORT_B] = device_add_child(dev, "sk", -1); 1974 if (sc->sk_devs[SK_PORT_B] == NULL) { 1975 device_printf(dev, "failed to add child for PORT_B\n"); 1976 error = ENXIO; 1977 goto fail; 1978 } 1979 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT); 1980 if (port == NULL) { 1981 device_printf(dev, "failed to allocate memory for " 1982 "ivars of PORT_B\n"); 1983 error = ENXIO; 1984 goto fail; 1985 } 1986 *port = SK_PORT_B; 1987 device_set_ivars(sc->sk_devs[SK_PORT_B], port); 1988 } 1989 1990 /* Turn on the 'driver is loaded' LED. */ 1991 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1992 1993 error = bus_generic_attach(dev); 1994 if (error) { 1995 device_printf(dev, "failed to attach port(s)\n"); 1996 goto fail; 1997 } 1998 1999 /* Hook interrupt last to avoid having to lock softc */ 2000 error = bus_setup_intr(dev, sc->sk_res[1], INTR_TYPE_NET|INTR_MPSAFE, 2001 sk_intr, sc, &sc->sk_intrhand); 2002 2003 if (error) { 2004 device_printf(dev, "couldn't set up irq\n"); 2005 goto fail; 2006 } 2007 2008 fail: 2009 if (error) 2010 skc_detach(dev); 2011 2012 return(error); 2013 } 2014 2015 /* 2016 * Shutdown hardware and free up resources. This can be called any 2017 * time after the mutex has been initialized. It is called in both 2018 * the error case in attach and the normal detach case so it needs 2019 * to be careful about only freeing resources that have actually been 2020 * allocated. 2021 */ 2022 static int 2023 sk_detach(dev) 2024 device_t dev; 2025 { 2026 struct sk_if_softc *sc_if; 2027 struct ifnet *ifp; 2028 2029 sc_if = device_get_softc(dev); 2030 KASSERT(mtx_initialized(&sc_if->sk_softc->sk_mtx), 2031 ("sk mutex not initialized in sk_detach")); 2032 SK_IF_LOCK(sc_if); 2033 2034 ifp = sc_if->sk_ifp; 2035 /* These should only be active if attach_xmac succeeded */ 2036 if (device_is_attached(dev)) { 2037 sk_stop(sc_if); 2038 /* Can't hold locks while calling detach */ 2039 SK_IF_UNLOCK(sc_if); 2040 callout_drain(&sc_if->sk_tick_ch); 2041 ether_ifdetach(ifp); 2042 SK_IF_LOCK(sc_if); 2043 } 2044 if (ifp) 2045 if_free(ifp); 2046 /* 2047 * We're generally called from skc_detach() which is using 2048 * device_delete_child() to get to here. It's already trashed 2049 * miibus for us, so don't do it here or we'll panic. 2050 */ 2051 /* 2052 if (sc_if->sk_miibus != NULL) 2053 device_delete_child(dev, sc_if->sk_miibus); 2054 */ 2055 bus_generic_detach(dev); 2056 sk_dma_free(sc_if); 2057 SK_IF_UNLOCK(sc_if); 2058 2059 return(0); 2060 } 2061 2062 static int 2063 skc_detach(dev) 2064 device_t dev; 2065 { 2066 struct sk_softc *sc; 2067 2068 sc = device_get_softc(dev); 2069 KASSERT(mtx_initialized(&sc->sk_mtx), ("sk mutex not initialized")); 2070 2071 if (device_is_alive(dev)) { 2072 if (sc->sk_devs[SK_PORT_A] != NULL) { 2073 free(device_get_ivars(sc->sk_devs[SK_PORT_A]), M_DEVBUF); 2074 device_delete_child(dev, sc->sk_devs[SK_PORT_A]); 2075 } 2076 if (sc->sk_devs[SK_PORT_B] != NULL) { 2077 free(device_get_ivars(sc->sk_devs[SK_PORT_B]), M_DEVBUF); 2078 device_delete_child(dev, sc->sk_devs[SK_PORT_B]); 2079 } 2080 bus_generic_detach(dev); 2081 } 2082 2083 if (sc->sk_vpd_prodname != NULL) 2084 free(sc->sk_vpd_prodname, M_DEVBUF); 2085 if (sc->sk_vpd_readonly != NULL) 2086 free(sc->sk_vpd_readonly, M_DEVBUF); 2087 2088 if (sc->sk_intrhand) 2089 bus_teardown_intr(dev, sc->sk_res[1], sc->sk_intrhand); 2090 bus_release_resources(dev, sc->sk_res_spec, sc->sk_res); 2091 2092 mtx_destroy(&sc->sk_mii_mtx); 2093 mtx_destroy(&sc->sk_mtx); 2094 2095 return(0); 2096 } 2097 2098 struct sk_dmamap_arg { 2099 bus_addr_t sk_busaddr; 2100 }; 2101 2102 static void 2103 sk_dmamap_cb(arg, segs, nseg, error) 2104 void *arg; 2105 bus_dma_segment_t *segs; 2106 int nseg; 2107 int error; 2108 { 2109 struct sk_dmamap_arg *ctx; 2110 2111 if (error != 0) 2112 return; 2113 2114 ctx = arg; 2115 ctx->sk_busaddr = segs[0].ds_addr; 2116 } 2117 2118 /* 2119 * Allocate jumbo buffer storage. The SysKonnect adapters support 2120 * "jumbograms" (9K frames), although SysKonnect doesn't currently 2121 * use them in their drivers. In order for us to use them, we need 2122 * large 9K receive buffers, however standard mbuf clusters are only 2123 * 2048 bytes in size. Consequently, we need to allocate and manage 2124 * our own jumbo buffer pool. Fortunately, this does not require an 2125 * excessive amount of additional code. 2126 */ 2127 static int 2128 sk_dma_alloc(sc_if) 2129 struct sk_if_softc *sc_if; 2130 { 2131 struct sk_dmamap_arg ctx; 2132 struct sk_txdesc *txd; 2133 struct sk_rxdesc *rxd; 2134 struct sk_rxdesc *jrxd; 2135 u_int8_t *ptr; 2136 struct sk_jpool_entry *entry; 2137 int error, i; 2138 2139 mtx_init(&sc_if->sk_jlist_mtx, "sk_jlist_mtx", NULL, MTX_DEF); 2140 SLIST_INIT(&sc_if->sk_jfree_listhead); 2141 SLIST_INIT(&sc_if->sk_jinuse_listhead); 2142 2143 /* create parent tag */ 2144 /* 2145 * XXX 2146 * This driver should use BUS_SPACE_MAXADDR for lowaddr argument 2147 * in bus_dma_tag_create(9) as the NIC would support DAC mode. 2148 * However bz@ reported that it does not work on amd64 with > 4GB 2149 * RAM. Until we have more clues of the breakage, disable DAC mode 2150 * by limiting DMA address to be in 32bit address space. 2151 */ 2152 error = bus_dma_tag_create(NULL, /* parent */ 2153 1, 0, /* algnmnt, boundary */ 2154 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 2155 BUS_SPACE_MAXADDR, /* highaddr */ 2156 NULL, NULL, /* filter, filterarg */ 2157 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 2158 0, /* nsegments */ 2159 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 2160 0, /* flags */ 2161 NULL, NULL, /* lockfunc, lockarg */ 2162 &sc_if->sk_cdata.sk_parent_tag); 2163 if (error != 0) { 2164 device_printf(sc_if->sk_if_dev, 2165 "failed to create parent DMA tag\n"); 2166 goto fail; 2167 } 2168 /* create tag for Tx ring */ 2169 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */ 2170 SK_RING_ALIGN, 0, /* algnmnt, boundary */ 2171 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 2172 BUS_SPACE_MAXADDR, /* highaddr */ 2173 NULL, NULL, /* filter, filterarg */ 2174 SK_TX_RING_SZ, /* maxsize */ 2175 1, /* nsegments */ 2176 SK_TX_RING_SZ, /* maxsegsize */ 2177 0, /* flags */ 2178 NULL, NULL, /* lockfunc, lockarg */ 2179 &sc_if->sk_cdata.sk_tx_ring_tag); 2180 if (error != 0) { 2181 device_printf(sc_if->sk_if_dev, 2182 "failed to allocate Tx ring DMA tag\n"); 2183 goto fail; 2184 } 2185 2186 /* create tag for Rx ring */ 2187 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */ 2188 SK_RING_ALIGN, 0, /* algnmnt, boundary */ 2189 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 2190 BUS_SPACE_MAXADDR, /* highaddr */ 2191 NULL, NULL, /* filter, filterarg */ 2192 SK_RX_RING_SZ, /* maxsize */ 2193 1, /* nsegments */ 2194 SK_RX_RING_SZ, /* maxsegsize */ 2195 0, /* flags */ 2196 NULL, NULL, /* lockfunc, lockarg */ 2197 &sc_if->sk_cdata.sk_rx_ring_tag); 2198 if (error != 0) { 2199 device_printf(sc_if->sk_if_dev, 2200 "failed to allocate Rx ring DMA tag\n"); 2201 goto fail; 2202 } 2203 2204 /* create tag for jumbo Rx ring */ 2205 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */ 2206 SK_RING_ALIGN, 0, /* algnmnt, boundary */ 2207 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 2208 BUS_SPACE_MAXADDR, /* highaddr */ 2209 NULL, NULL, /* filter, filterarg */ 2210 SK_JUMBO_RX_RING_SZ, /* maxsize */ 2211 1, /* nsegments */ 2212 SK_JUMBO_RX_RING_SZ, /* maxsegsize */ 2213 0, /* flags */ 2214 NULL, NULL, /* lockfunc, lockarg */ 2215 &sc_if->sk_cdata.sk_jumbo_rx_ring_tag); 2216 if (error != 0) { 2217 device_printf(sc_if->sk_if_dev, 2218 "failed to allocate jumbo Rx ring DMA tag\n"); 2219 goto fail; 2220 } 2221 2222 /* create tag for jumbo buffer blocks */ 2223 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */ 2224 PAGE_SIZE, 0, /* algnmnt, boundary */ 2225 BUS_SPACE_MAXADDR, /* lowaddr */ 2226 BUS_SPACE_MAXADDR, /* highaddr */ 2227 NULL, NULL, /* filter, filterarg */ 2228 SK_JMEM, /* maxsize */ 2229 1, /* nsegments */ 2230 SK_JMEM, /* maxsegsize */ 2231 0, /* flags */ 2232 NULL, NULL, /* lockfunc, lockarg */ 2233 &sc_if->sk_cdata.sk_jumbo_tag); 2234 if (error != 0) { 2235 device_printf(sc_if->sk_if_dev, 2236 "failed to allocate jumbo Rx buffer block DMA tag\n"); 2237 goto fail; 2238 } 2239 2240 /* create tag for Tx buffers */ 2241 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */ 2242 1, 0, /* algnmnt, boundary */ 2243 BUS_SPACE_MAXADDR, /* lowaddr */ 2244 BUS_SPACE_MAXADDR, /* highaddr */ 2245 NULL, NULL, /* filter, filterarg */ 2246 MCLBYTES * SK_MAXTXSEGS, /* maxsize */ 2247 SK_MAXTXSEGS, /* nsegments */ 2248 MCLBYTES, /* maxsegsize */ 2249 0, /* flags */ 2250 NULL, NULL, /* lockfunc, lockarg */ 2251 &sc_if->sk_cdata.sk_tx_tag); 2252 if (error != 0) { 2253 device_printf(sc_if->sk_if_dev, 2254 "failed to allocate Tx DMA tag\n"); 2255 goto fail; 2256 } 2257 2258 /* create tag for Rx buffers */ 2259 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */ 2260 1, 0, /* algnmnt, boundary */ 2261 BUS_SPACE_MAXADDR, /* lowaddr */ 2262 BUS_SPACE_MAXADDR, /* highaddr */ 2263 NULL, NULL, /* filter, filterarg */ 2264 MCLBYTES, /* maxsize */ 2265 1, /* nsegments */ 2266 MCLBYTES, /* maxsegsize */ 2267 0, /* flags */ 2268 NULL, NULL, /* lockfunc, lockarg */ 2269 &sc_if->sk_cdata.sk_rx_tag); 2270 if (error != 0) { 2271 device_printf(sc_if->sk_if_dev, 2272 "failed to allocate Rx DMA tag\n"); 2273 goto fail; 2274 } 2275 2276 /* create tag for jumbo Rx buffers */ 2277 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */ 2278 PAGE_SIZE, 0, /* algnmnt, boundary */ 2279 BUS_SPACE_MAXADDR, /* lowaddr */ 2280 BUS_SPACE_MAXADDR, /* highaddr */ 2281 NULL, NULL, /* filter, filterarg */ 2282 MCLBYTES * SK_MAXRXSEGS, /* maxsize */ 2283 SK_MAXRXSEGS, /* nsegments */ 2284 SK_JLEN, /* maxsegsize */ 2285 0, /* flags */ 2286 NULL, NULL, /* lockfunc, lockarg */ 2287 &sc_if->sk_cdata.sk_jumbo_rx_tag); 2288 if (error != 0) { 2289 device_printf(sc_if->sk_if_dev, 2290 "failed to allocate jumbo Rx DMA tag\n"); 2291 goto fail; 2292 } 2293 2294 /* allocate DMA'able memory and load the DMA map for Tx ring */ 2295 error = bus_dmamem_alloc(sc_if->sk_cdata.sk_tx_ring_tag, 2296 (void **)&sc_if->sk_rdata.sk_tx_ring, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 2297 &sc_if->sk_cdata.sk_tx_ring_map); 2298 if (error != 0) { 2299 device_printf(sc_if->sk_if_dev, 2300 "failed to allocate DMA'able memory for Tx ring\n"); 2301 goto fail; 2302 } 2303 2304 ctx.sk_busaddr = 0; 2305 error = bus_dmamap_load(sc_if->sk_cdata.sk_tx_ring_tag, 2306 sc_if->sk_cdata.sk_tx_ring_map, sc_if->sk_rdata.sk_tx_ring, 2307 SK_TX_RING_SZ, sk_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 2308 if (error != 0) { 2309 device_printf(sc_if->sk_if_dev, 2310 "failed to load DMA'able memory for Tx ring\n"); 2311 goto fail; 2312 } 2313 sc_if->sk_rdata.sk_tx_ring_paddr = ctx.sk_busaddr; 2314 2315 /* allocate DMA'able memory and load the DMA map for Rx ring */ 2316 error = bus_dmamem_alloc(sc_if->sk_cdata.sk_rx_ring_tag, 2317 (void **)&sc_if->sk_rdata.sk_rx_ring, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 2318 &sc_if->sk_cdata.sk_rx_ring_map); 2319 if (error != 0) { 2320 device_printf(sc_if->sk_if_dev, 2321 "failed to allocate DMA'able memory for Rx ring\n"); 2322 goto fail; 2323 } 2324 2325 ctx.sk_busaddr = 0; 2326 error = bus_dmamap_load(sc_if->sk_cdata.sk_rx_ring_tag, 2327 sc_if->sk_cdata.sk_rx_ring_map, sc_if->sk_rdata.sk_rx_ring, 2328 SK_RX_RING_SZ, sk_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 2329 if (error != 0) { 2330 device_printf(sc_if->sk_if_dev, 2331 "failed to load DMA'able memory for Rx ring\n"); 2332 goto fail; 2333 } 2334 sc_if->sk_rdata.sk_rx_ring_paddr = ctx.sk_busaddr; 2335 2336 /* allocate DMA'able memory and load the DMA map for jumbo Rx ring */ 2337 error = bus_dmamem_alloc(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 2338 (void **)&sc_if->sk_rdata.sk_jumbo_rx_ring, 2339 BUS_DMA_NOWAIT|BUS_DMA_ZERO, &sc_if->sk_cdata.sk_jumbo_rx_ring_map); 2340 if (error != 0) { 2341 device_printf(sc_if->sk_if_dev, 2342 "failed to allocate DMA'able memory for jumbo Rx ring\n"); 2343 goto fail; 2344 } 2345 2346 ctx.sk_busaddr = 0; 2347 error = bus_dmamap_load(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 2348 sc_if->sk_cdata.sk_jumbo_rx_ring_map, 2349 sc_if->sk_rdata.sk_jumbo_rx_ring, SK_JUMBO_RX_RING_SZ, sk_dmamap_cb, 2350 &ctx, BUS_DMA_NOWAIT); 2351 if (error != 0) { 2352 device_printf(sc_if->sk_if_dev, 2353 "failed to load DMA'able memory for jumbo Rx ring\n"); 2354 goto fail; 2355 } 2356 sc_if->sk_rdata.sk_jumbo_rx_ring_paddr = ctx.sk_busaddr; 2357 2358 /* create DMA maps for Tx buffers */ 2359 for (i = 0; i < SK_TX_RING_CNT; i++) { 2360 txd = &sc_if->sk_cdata.sk_txdesc[i]; 2361 txd->tx_m = NULL; 2362 txd->tx_dmamap = 0; 2363 error = bus_dmamap_create(sc_if->sk_cdata.sk_tx_tag, 0, 2364 &txd->tx_dmamap); 2365 if (error != 0) { 2366 device_printf(sc_if->sk_if_dev, 2367 "failed to create Tx dmamap\n"); 2368 goto fail; 2369 } 2370 } 2371 /* create DMA maps for Rx buffers */ 2372 if ((error = bus_dmamap_create(sc_if->sk_cdata.sk_rx_tag, 0, 2373 &sc_if->sk_cdata.sk_rx_sparemap)) != 0) { 2374 device_printf(sc_if->sk_if_dev, 2375 "failed to create spare Rx dmamap\n"); 2376 goto fail; 2377 } 2378 for (i = 0; i < SK_RX_RING_CNT; i++) { 2379 rxd = &sc_if->sk_cdata.sk_rxdesc[i]; 2380 rxd->rx_m = NULL; 2381 rxd->rx_dmamap = 0; 2382 error = bus_dmamap_create(sc_if->sk_cdata.sk_rx_tag, 0, 2383 &rxd->rx_dmamap); 2384 if (error != 0) { 2385 device_printf(sc_if->sk_if_dev, 2386 "failed to create Rx dmamap\n"); 2387 goto fail; 2388 } 2389 } 2390 /* create DMA maps for jumbo Rx buffers */ 2391 if ((error = bus_dmamap_create(sc_if->sk_cdata.sk_jumbo_rx_tag, 0, 2392 &sc_if->sk_cdata.sk_jumbo_rx_sparemap)) != 0) { 2393 device_printf(sc_if->sk_if_dev, 2394 "failed to create spare jumbo Rx dmamap\n"); 2395 goto fail; 2396 } 2397 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) { 2398 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i]; 2399 jrxd->rx_m = NULL; 2400 jrxd->rx_dmamap = 0; 2401 error = bus_dmamap_create(sc_if->sk_cdata.sk_jumbo_rx_tag, 0, 2402 &jrxd->rx_dmamap); 2403 if (error != 0) { 2404 device_printf(sc_if->sk_if_dev, 2405 "failed to create jumbo Rx dmamap\n"); 2406 goto fail; 2407 } 2408 } 2409 2410 /* allocate DMA'able memory and load the DMA map for jumbo buf */ 2411 error = bus_dmamem_alloc(sc_if->sk_cdata.sk_jumbo_tag, 2412 (void **)&sc_if->sk_rdata.sk_jumbo_buf, 2413 BUS_DMA_NOWAIT|BUS_DMA_ZERO, &sc_if->sk_cdata.sk_jumbo_map); 2414 if (error != 0) { 2415 device_printf(sc_if->sk_if_dev, 2416 "failed to allocate DMA'able memory for jumbo buf\n"); 2417 goto fail; 2418 } 2419 2420 ctx.sk_busaddr = 0; 2421 error = bus_dmamap_load(sc_if->sk_cdata.sk_jumbo_tag, 2422 sc_if->sk_cdata.sk_jumbo_map, 2423 sc_if->sk_rdata.sk_jumbo_buf, SK_JMEM, sk_dmamap_cb, 2424 &ctx, BUS_DMA_NOWAIT); 2425 if (error != 0) { 2426 device_printf(sc_if->sk_if_dev, 2427 "failed to load DMA'able memory for jumbobuf\n"); 2428 goto fail; 2429 } 2430 sc_if->sk_rdata.sk_jumbo_buf_paddr = ctx.sk_busaddr; 2431 2432 /* 2433 * Now divide it up into 9K pieces and save the addresses 2434 * in an array. 2435 */ 2436 ptr = sc_if->sk_rdata.sk_jumbo_buf; 2437 for (i = 0; i < SK_JSLOTS; i++) { 2438 sc_if->sk_cdata.sk_jslots[i] = ptr; 2439 ptr += SK_JLEN; 2440 entry = malloc(sizeof(struct sk_jpool_entry), 2441 M_DEVBUF, M_NOWAIT); 2442 if (entry == NULL) { 2443 device_printf(sc_if->sk_if_dev, 2444 "no memory for jumbo buffers!\n"); 2445 error = ENOMEM; 2446 goto fail; 2447 } 2448 entry->slot = i; 2449 SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, entry, 2450 jpool_entries); 2451 } 2452 2453 fail: 2454 return (error); 2455 } 2456 2457 static void 2458 sk_dma_free(sc_if) 2459 struct sk_if_softc *sc_if; 2460 { 2461 struct sk_txdesc *txd; 2462 struct sk_rxdesc *rxd; 2463 struct sk_rxdesc *jrxd; 2464 struct sk_jpool_entry *entry; 2465 int i; 2466 2467 SK_JLIST_LOCK(sc_if); 2468 while ((entry = SLIST_FIRST(&sc_if->sk_jinuse_listhead))) { 2469 device_printf(sc_if->sk_if_dev, 2470 "asked to free buffer that is in use!\n"); 2471 SLIST_REMOVE_HEAD(&sc_if->sk_jinuse_listhead, jpool_entries); 2472 SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, entry, 2473 jpool_entries); 2474 } 2475 2476 while (!SLIST_EMPTY(&sc_if->sk_jfree_listhead)) { 2477 entry = SLIST_FIRST(&sc_if->sk_jfree_listhead); 2478 SLIST_REMOVE_HEAD(&sc_if->sk_jfree_listhead, jpool_entries); 2479 free(entry, M_DEVBUF); 2480 } 2481 SK_JLIST_UNLOCK(sc_if); 2482 2483 /* destroy jumbo buffer block */ 2484 if (sc_if->sk_cdata.sk_jumbo_map) 2485 bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_tag, 2486 sc_if->sk_cdata.sk_jumbo_map); 2487 2488 if (sc_if->sk_rdata.sk_jumbo_buf) { 2489 bus_dmamem_free(sc_if->sk_cdata.sk_jumbo_tag, 2490 sc_if->sk_rdata.sk_jumbo_buf, 2491 sc_if->sk_cdata.sk_jumbo_map); 2492 sc_if->sk_rdata.sk_jumbo_buf = NULL; 2493 sc_if->sk_cdata.sk_jumbo_map = 0; 2494 } 2495 2496 /* Tx ring */ 2497 if (sc_if->sk_cdata.sk_tx_ring_tag) { 2498 if (sc_if->sk_cdata.sk_tx_ring_map) 2499 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_ring_tag, 2500 sc_if->sk_cdata.sk_tx_ring_map); 2501 if (sc_if->sk_cdata.sk_tx_ring_map && 2502 sc_if->sk_rdata.sk_tx_ring) 2503 bus_dmamem_free(sc_if->sk_cdata.sk_tx_ring_tag, 2504 sc_if->sk_rdata.sk_tx_ring, 2505 sc_if->sk_cdata.sk_tx_ring_map); 2506 sc_if->sk_rdata.sk_tx_ring = NULL; 2507 sc_if->sk_cdata.sk_tx_ring_map = 0; 2508 bus_dma_tag_destroy(sc_if->sk_cdata.sk_tx_ring_tag); 2509 sc_if->sk_cdata.sk_tx_ring_tag = NULL; 2510 } 2511 /* Rx ring */ 2512 if (sc_if->sk_cdata.sk_rx_ring_tag) { 2513 if (sc_if->sk_cdata.sk_rx_ring_map) 2514 bus_dmamap_unload(sc_if->sk_cdata.sk_rx_ring_tag, 2515 sc_if->sk_cdata.sk_rx_ring_map); 2516 if (sc_if->sk_cdata.sk_rx_ring_map && 2517 sc_if->sk_rdata.sk_rx_ring) 2518 bus_dmamem_free(sc_if->sk_cdata.sk_rx_ring_tag, 2519 sc_if->sk_rdata.sk_rx_ring, 2520 sc_if->sk_cdata.sk_rx_ring_map); 2521 sc_if->sk_rdata.sk_rx_ring = NULL; 2522 sc_if->sk_cdata.sk_rx_ring_map = 0; 2523 bus_dma_tag_destroy(sc_if->sk_cdata.sk_rx_ring_tag); 2524 sc_if->sk_cdata.sk_rx_ring_tag = NULL; 2525 } 2526 /* jumbo Rx ring */ 2527 if (sc_if->sk_cdata.sk_jumbo_rx_ring_tag) { 2528 if (sc_if->sk_cdata.sk_jumbo_rx_ring_map) 2529 bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 2530 sc_if->sk_cdata.sk_jumbo_rx_ring_map); 2531 if (sc_if->sk_cdata.sk_jumbo_rx_ring_map && 2532 sc_if->sk_rdata.sk_jumbo_rx_ring) 2533 bus_dmamem_free(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 2534 sc_if->sk_rdata.sk_jumbo_rx_ring, 2535 sc_if->sk_cdata.sk_jumbo_rx_ring_map); 2536 sc_if->sk_rdata.sk_jumbo_rx_ring = NULL; 2537 sc_if->sk_cdata.sk_jumbo_rx_ring_map = 0; 2538 bus_dma_tag_destroy(sc_if->sk_cdata.sk_jumbo_rx_ring_tag); 2539 sc_if->sk_cdata.sk_jumbo_rx_ring_tag = NULL; 2540 } 2541 /* Tx buffers */ 2542 if (sc_if->sk_cdata.sk_tx_tag) { 2543 for (i = 0; i < SK_TX_RING_CNT; i++) { 2544 txd = &sc_if->sk_cdata.sk_txdesc[i]; 2545 if (txd->tx_dmamap) { 2546 bus_dmamap_destroy(sc_if->sk_cdata.sk_tx_tag, 2547 txd->tx_dmamap); 2548 txd->tx_dmamap = 0; 2549 } 2550 } 2551 bus_dma_tag_destroy(sc_if->sk_cdata.sk_tx_tag); 2552 sc_if->sk_cdata.sk_tx_tag = NULL; 2553 } 2554 /* Rx buffers */ 2555 if (sc_if->sk_cdata.sk_rx_tag) { 2556 for (i = 0; i < SK_RX_RING_CNT; i++) { 2557 rxd = &sc_if->sk_cdata.sk_rxdesc[i]; 2558 if (rxd->rx_dmamap) { 2559 bus_dmamap_destroy(sc_if->sk_cdata.sk_rx_tag, 2560 rxd->rx_dmamap); 2561 rxd->rx_dmamap = 0; 2562 } 2563 } 2564 if (sc_if->sk_cdata.sk_rx_sparemap) { 2565 bus_dmamap_destroy(sc_if->sk_cdata.sk_rx_tag, 2566 sc_if->sk_cdata.sk_rx_sparemap); 2567 sc_if->sk_cdata.sk_rx_sparemap = 0; 2568 } 2569 bus_dma_tag_destroy(sc_if->sk_cdata.sk_rx_tag); 2570 sc_if->sk_cdata.sk_rx_tag = NULL; 2571 } 2572 /* jumbo Rx buffers */ 2573 if (sc_if->sk_cdata.sk_jumbo_rx_tag) { 2574 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) { 2575 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i]; 2576 if (jrxd->rx_dmamap) { 2577 bus_dmamap_destroy( 2578 sc_if->sk_cdata.sk_jumbo_rx_tag, 2579 jrxd->rx_dmamap); 2580 jrxd->rx_dmamap = 0; 2581 } 2582 } 2583 if (sc_if->sk_cdata.sk_jumbo_rx_sparemap) { 2584 bus_dmamap_destroy(sc_if->sk_cdata.sk_jumbo_rx_tag, 2585 sc_if->sk_cdata.sk_jumbo_rx_sparemap); 2586 sc_if->sk_cdata.sk_jumbo_rx_sparemap = 0; 2587 } 2588 bus_dma_tag_destroy(sc_if->sk_cdata.sk_jumbo_rx_tag); 2589 sc_if->sk_cdata.sk_jumbo_rx_tag = NULL; 2590 } 2591 2592 if (sc_if->sk_cdata.sk_parent_tag) { 2593 bus_dma_tag_destroy(sc_if->sk_cdata.sk_parent_tag); 2594 sc_if->sk_cdata.sk_parent_tag = NULL; 2595 } 2596 mtx_destroy(&sc_if->sk_jlist_mtx); 2597 } 2598 2599 /* 2600 * Allocate a jumbo buffer. 2601 */ 2602 static void * 2603 sk_jalloc(sc_if) 2604 struct sk_if_softc *sc_if; 2605 { 2606 struct sk_jpool_entry *entry; 2607 2608 SK_JLIST_LOCK(sc_if); 2609 2610 entry = SLIST_FIRST(&sc_if->sk_jfree_listhead); 2611 2612 if (entry == NULL) { 2613 SK_JLIST_UNLOCK(sc_if); 2614 return (NULL); 2615 } 2616 2617 SLIST_REMOVE_HEAD(&sc_if->sk_jfree_listhead, jpool_entries); 2618 SLIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 2619 2620 SK_JLIST_UNLOCK(sc_if); 2621 2622 return (sc_if->sk_cdata.sk_jslots[entry->slot]); 2623 } 2624 2625 /* 2626 * Release a jumbo buffer. 2627 */ 2628 static void 2629 sk_jfree(buf, args) 2630 void *buf; 2631 void *args; 2632 { 2633 struct sk_if_softc *sc_if; 2634 struct sk_jpool_entry *entry; 2635 int i; 2636 2637 /* Extract the softc struct pointer. */ 2638 sc_if = (struct sk_if_softc *)args; 2639 KASSERT(sc_if != NULL, ("%s: can't find softc pointer!", __func__)); 2640 2641 SK_JLIST_LOCK(sc_if); 2642 /* calculate the slot this buffer belongs to */ 2643 i = ((vm_offset_t)buf 2644 - (vm_offset_t)sc_if->sk_rdata.sk_jumbo_buf) / SK_JLEN; 2645 KASSERT(i >= 0 && i < SK_JSLOTS, 2646 ("%s: asked to free buffer that we don't manage!", __func__)); 2647 2648 entry = SLIST_FIRST(&sc_if->sk_jinuse_listhead); 2649 KASSERT(entry != NULL, ("%s: buffer not in use!", __func__)); 2650 entry->slot = i; 2651 SLIST_REMOVE_HEAD(&sc_if->sk_jinuse_listhead, jpool_entries); 2652 SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, entry, jpool_entries); 2653 if (SLIST_EMPTY(&sc_if->sk_jinuse_listhead)) 2654 wakeup(sc_if); 2655 2656 SK_JLIST_UNLOCK(sc_if); 2657 } 2658 2659 static void 2660 sk_txcksum(ifp, m, f) 2661 struct ifnet *ifp; 2662 struct mbuf *m; 2663 struct sk_tx_desc *f; 2664 { 2665 struct ip *ip; 2666 u_int16_t offset; 2667 u_int8_t *p; 2668 2669 offset = sizeof(struct ip) + ETHER_HDR_LEN; 2670 for(; m && m->m_len == 0; m = m->m_next) 2671 ; 2672 if (m == NULL || m->m_len < ETHER_HDR_LEN) { 2673 if_printf(ifp, "%s: m_len < ETHER_HDR_LEN\n", __func__); 2674 /* checksum may be corrupted */ 2675 goto sendit; 2676 } 2677 if (m->m_len < ETHER_HDR_LEN + sizeof(u_int32_t)) { 2678 if (m->m_len != ETHER_HDR_LEN) { 2679 if_printf(ifp, "%s: m_len != ETHER_HDR_LEN\n", 2680 __func__); 2681 /* checksum may be corrupted */ 2682 goto sendit; 2683 } 2684 for(m = m->m_next; m && m->m_len == 0; m = m->m_next) 2685 ; 2686 if (m == NULL) { 2687 offset = sizeof(struct ip) + ETHER_HDR_LEN; 2688 /* checksum may be corrupted */ 2689 goto sendit; 2690 } 2691 ip = mtod(m, struct ip *); 2692 } else { 2693 p = mtod(m, u_int8_t *); 2694 p += ETHER_HDR_LEN; 2695 ip = (struct ip *)p; 2696 } 2697 offset = (ip->ip_hl << 2) + ETHER_HDR_LEN; 2698 2699 sendit: 2700 f->sk_csum_startval = 0; 2701 f->sk_csum_start = htole32(((offset + m->m_pkthdr.csum_data) & 0xffff) | 2702 (offset << 16)); 2703 } 2704 2705 static int 2706 sk_encap(sc_if, m_head) 2707 struct sk_if_softc *sc_if; 2708 struct mbuf **m_head; 2709 { 2710 struct sk_txdesc *txd; 2711 struct sk_tx_desc *f = NULL; 2712 struct mbuf *m, *n; 2713 bus_dma_segment_t txsegs[SK_MAXTXSEGS]; 2714 u_int32_t cflags, frag, si, sk_ctl; 2715 int error, i, nseg; 2716 2717 SK_IF_LOCK_ASSERT(sc_if); 2718 2719 if ((txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txfreeq)) == NULL) 2720 return (ENOBUFS); 2721 2722 m = *m_head; 2723 error = bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_tx_tag, 2724 txd->tx_dmamap, m, txsegs, &nseg, 0); 2725 if (error == EFBIG) { 2726 n = m_defrag(m, M_DONTWAIT); 2727 if (n == NULL) { 2728 m_freem(m); 2729 m = NULL; 2730 return (ENOMEM); 2731 } 2732 m = n; 2733 error = bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_tx_tag, 2734 txd->tx_dmamap, m, txsegs, &nseg, 0); 2735 if (error != 0) { 2736 m_freem(m); 2737 m = NULL; 2738 return (error); 2739 } 2740 } else if (error != 0) 2741 return (error); 2742 if (nseg == 0) { 2743 m_freem(m); 2744 m = NULL; 2745 return (EIO); 2746 } 2747 if (sc_if->sk_cdata.sk_tx_cnt + nseg >= SK_TX_RING_CNT) { 2748 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap); 2749 return (ENOBUFS); 2750 } 2751 2752 if ((m->m_pkthdr.csum_flags & sc_if->sk_ifp->if_hwassist) != 0) 2753 cflags = SK_OPCODE_CSUM; 2754 else 2755 cflags = SK_OPCODE_DEFAULT; 2756 si = frag = sc_if->sk_cdata.sk_tx_prod; 2757 for (i = 0; i < nseg; i++) { 2758 f = &sc_if->sk_rdata.sk_tx_ring[frag]; 2759 f->sk_data_lo = htole32(SK_ADDR_LO(txsegs[i].ds_addr)); 2760 f->sk_data_hi = htole32(SK_ADDR_HI(txsegs[i].ds_addr)); 2761 sk_ctl = txsegs[i].ds_len | cflags; 2762 if (i == 0) { 2763 if (cflags == SK_OPCODE_CSUM) 2764 sk_txcksum(sc_if->sk_ifp, m, f); 2765 sk_ctl |= SK_TXCTL_FIRSTFRAG; 2766 } else 2767 sk_ctl |= SK_TXCTL_OWN; 2768 f->sk_ctl = htole32(sk_ctl); 2769 sc_if->sk_cdata.sk_tx_cnt++; 2770 SK_INC(frag, SK_TX_RING_CNT); 2771 } 2772 sc_if->sk_cdata.sk_tx_prod = frag; 2773 2774 /* set EOF on the last desciptor */ 2775 frag = (frag + SK_TX_RING_CNT - 1) % SK_TX_RING_CNT; 2776 f = &sc_if->sk_rdata.sk_tx_ring[frag]; 2777 f->sk_ctl |= htole32(SK_TXCTL_LASTFRAG | SK_TXCTL_EOF_INTR); 2778 2779 /* turn the first descriptor ownership to NIC */ 2780 f = &sc_if->sk_rdata.sk_tx_ring[si]; 2781 f->sk_ctl |= htole32(SK_TXCTL_OWN); 2782 2783 STAILQ_REMOVE_HEAD(&sc_if->sk_cdata.sk_txfreeq, tx_q); 2784 STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txbusyq, txd, tx_q); 2785 txd->tx_m = m; 2786 2787 /* sync descriptors */ 2788 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap, 2789 BUS_DMASYNC_PREWRITE); 2790 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag, 2791 sc_if->sk_cdata.sk_tx_ring_map, 2792 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2793 2794 return (0); 2795 } 2796 2797 static void 2798 sk_start(ifp) 2799 struct ifnet *ifp; 2800 { 2801 struct sk_if_softc *sc_if; 2802 2803 sc_if = ifp->if_softc; 2804 2805 SK_IF_LOCK(sc_if); 2806 sk_start_locked(ifp); 2807 SK_IF_UNLOCK(sc_if); 2808 2809 return; 2810 } 2811 2812 static void 2813 sk_start_locked(ifp) 2814 struct ifnet *ifp; 2815 { 2816 struct sk_softc *sc; 2817 struct sk_if_softc *sc_if; 2818 struct mbuf *m_head; 2819 int enq; 2820 2821 sc_if = ifp->if_softc; 2822 sc = sc_if->sk_softc; 2823 2824 SK_IF_LOCK_ASSERT(sc_if); 2825 2826 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2827 sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 1; ) { 2828 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2829 if (m_head == NULL) 2830 break; 2831 2832 /* 2833 * Pack the data into the transmit ring. If we 2834 * don't have room, set the OACTIVE flag and wait 2835 * for the NIC to drain the ring. 2836 */ 2837 if (sk_encap(sc_if, &m_head)) { 2838 if (m_head == NULL) 2839 break; 2840 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2841 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2842 break; 2843 } 2844 2845 enq++; 2846 /* 2847 * If there's a BPF listener, bounce a copy of this frame 2848 * to him. 2849 */ 2850 BPF_MTAP(ifp, m_head); 2851 } 2852 2853 if (enq > 0) { 2854 /* Transmit */ 2855 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 2856 2857 /* Set a timeout in case the chip goes out to lunch. */ 2858 ifp->if_timer = 5; 2859 } 2860 } 2861 2862 2863 static void 2864 sk_watchdog(ifp) 2865 struct ifnet *ifp; 2866 { 2867 struct sk_if_softc *sc_if; 2868 2869 sc_if = ifp->if_softc; 2870 2871 SK_IF_LOCK(sc_if); 2872 /* 2873 * Reclaim first as there is a possibility of losing Tx completion 2874 * interrupts. 2875 */ 2876 sk_txeof(sc_if); 2877 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 2878 if_printf(sc_if->sk_ifp, "watchdog timeout\n"); 2879 ifp->if_oerrors++; 2880 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2881 sk_init_locked(sc_if); 2882 } 2883 SK_IF_UNLOCK(sc_if); 2884 2885 return; 2886 } 2887 2888 static void 2889 skc_shutdown(dev) 2890 device_t dev; 2891 { 2892 struct sk_softc *sc; 2893 2894 sc = device_get_softc(dev); 2895 SK_LOCK(sc); 2896 2897 /* Turn off the 'driver is loaded' LED. */ 2898 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 2899 2900 /* 2901 * Reset the GEnesis controller. Doing this should also 2902 * assert the resets on the attached XMAC(s). 2903 */ 2904 sk_reset(sc); 2905 SK_UNLOCK(sc); 2906 2907 return; 2908 } 2909 2910 static int 2911 skc_suspend(dev) 2912 device_t dev; 2913 { 2914 struct sk_softc *sc; 2915 struct sk_if_softc *sc_if0, *sc_if1; 2916 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2917 2918 sc = device_get_softc(dev); 2919 2920 SK_LOCK(sc); 2921 2922 sc_if0 = sc->sk_if[SK_PORT_A]; 2923 sc_if1 = sc->sk_if[SK_PORT_B]; 2924 if (sc_if0 != NULL) 2925 ifp0 = sc_if0->sk_ifp; 2926 if (sc_if1 != NULL) 2927 ifp1 = sc_if1->sk_ifp; 2928 if (ifp0 != NULL) 2929 sk_stop(sc_if0); 2930 if (ifp1 != NULL) 2931 sk_stop(sc_if1); 2932 sc->sk_suspended = 1; 2933 2934 SK_UNLOCK(sc); 2935 2936 return (0); 2937 } 2938 2939 static int 2940 skc_resume(dev) 2941 device_t dev; 2942 { 2943 struct sk_softc *sc; 2944 struct sk_if_softc *sc_if0, *sc_if1; 2945 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2946 2947 sc = device_get_softc(dev); 2948 2949 SK_LOCK(sc); 2950 2951 sc_if0 = sc->sk_if[SK_PORT_A]; 2952 sc_if1 = sc->sk_if[SK_PORT_B]; 2953 if (sc_if0 != NULL) 2954 ifp0 = sc_if0->sk_ifp; 2955 if (sc_if1 != NULL) 2956 ifp1 = sc_if1->sk_ifp; 2957 if (ifp0 != NULL && ifp0->if_flags & IFF_UP) 2958 sk_init_locked(sc_if0); 2959 if (ifp1 != NULL && ifp1->if_flags & IFF_UP) 2960 sk_init_locked(sc_if1); 2961 sc->sk_suspended = 0; 2962 2963 SK_UNLOCK(sc); 2964 2965 return (0); 2966 } 2967 2968 /* 2969 * According to the data sheet from SK-NET GENESIS the hardware can compute 2970 * two Rx checksums at the same time(Each checksum start position is 2971 * programmed in Rx descriptors). However it seems that TCP/UDP checksum 2972 * does not work at least on my Yukon hardware. I tried every possible ways 2973 * to get correct checksum value but couldn't get correct one. So TCP/UDP 2974 * checksum offload was disabled at the moment and only IP checksum offload 2975 * was enabled. 2976 * As nomral IP header size is 20 bytes I can't expect it would give an 2977 * increase in throughput. However it seems it doesn't hurt performance in 2978 * my testing. If there is a more detailed information for checksum secret 2979 * of the hardware in question please contact yongari@FreeBSD.org to add 2980 * TCP/UDP checksum offload support. 2981 */ 2982 static __inline void 2983 sk_rxcksum(ifp, m, csum) 2984 struct ifnet *ifp; 2985 struct mbuf *m; 2986 u_int32_t csum; 2987 { 2988 struct ether_header *eh; 2989 struct ip *ip; 2990 int32_t hlen, len, pktlen; 2991 u_int16_t csum1, csum2, ipcsum; 2992 2993 pktlen = m->m_pkthdr.len; 2994 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip)) 2995 return; 2996 eh = mtod(m, struct ether_header *); 2997 if (eh->ether_type != htons(ETHERTYPE_IP)) 2998 return; 2999 ip = (struct ip *)(eh + 1); 3000 if (ip->ip_v != IPVERSION) 3001 return; 3002 hlen = ip->ip_hl << 2; 3003 pktlen -= sizeof(struct ether_header); 3004 if (hlen < sizeof(struct ip)) 3005 return; 3006 if (ntohs(ip->ip_len) < hlen) 3007 return; 3008 if (ntohs(ip->ip_len) != pktlen) 3009 return; 3010 3011 csum1 = htons(csum & 0xffff); 3012 csum2 = htons((csum >> 16) & 0xffff); 3013 ipcsum = in_addword(csum1, ~csum2 & 0xffff); 3014 /* checksum fixup for IP options */ 3015 len = hlen - sizeof(struct ip); 3016 if (len > 0) { 3017 /* 3018 * If the second checksum value is correct we can compute IP 3019 * checksum with simple math. Unfortunately the second checksum 3020 * value is wrong so we can't verify the checksum from the 3021 * value(It seems there is some magic here to get correct 3022 * value). If the second checksum value is correct it also 3023 * means we can get TCP/UDP checksum) here. However, it still 3024 * needs pseudo header checksum calculation due to hardware 3025 * limitations. 3026 */ 3027 return; 3028 } 3029 m->m_pkthdr.csum_flags = CSUM_IP_CHECKED; 3030 if (ipcsum == 0xffff) 3031 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 3032 } 3033 3034 static __inline int 3035 sk_rxvalid(sc, stat, len) 3036 struct sk_softc *sc; 3037 u_int32_t stat, len; 3038 { 3039 3040 if (sc->sk_type == SK_GENESIS) { 3041 if ((stat & XM_RXSTAT_ERRFRAME) == XM_RXSTAT_ERRFRAME || 3042 XM_RXSTAT_BYTES(stat) != len) 3043 return (0); 3044 } else { 3045 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR | 3046 YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | 3047 YU_RXSTAT_JABBER)) != 0 || 3048 (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK || 3049 YU_RXSTAT_BYTES(stat) != len) 3050 return (0); 3051 } 3052 3053 return (1); 3054 } 3055 3056 static void 3057 sk_rxeof(sc_if) 3058 struct sk_if_softc *sc_if; 3059 { 3060 struct sk_softc *sc; 3061 struct mbuf *m; 3062 struct ifnet *ifp; 3063 struct sk_rx_desc *cur_rx; 3064 struct sk_rxdesc *rxd; 3065 int cons, prog; 3066 u_int32_t csum, rxstat, sk_ctl; 3067 3068 sc = sc_if->sk_softc; 3069 ifp = sc_if->sk_ifp; 3070 3071 SK_IF_LOCK_ASSERT(sc_if); 3072 3073 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag, 3074 sc_if->sk_cdata.sk_rx_ring_map, BUS_DMASYNC_POSTREAD); 3075 3076 prog = 0; 3077 for (cons = sc_if->sk_cdata.sk_rx_cons; prog < SK_RX_RING_CNT; 3078 prog++, SK_INC(cons, SK_RX_RING_CNT)) { 3079 cur_rx = &sc_if->sk_rdata.sk_rx_ring[cons]; 3080 sk_ctl = le32toh(cur_rx->sk_ctl); 3081 if ((sk_ctl & SK_RXCTL_OWN) != 0) 3082 break; 3083 rxd = &sc_if->sk_cdata.sk_rxdesc[cons]; 3084 rxstat = le32toh(cur_rx->sk_xmac_rxstat); 3085 3086 if ((sk_ctl & (SK_RXCTL_STATUS_VALID | SK_RXCTL_FIRSTFRAG | 3087 SK_RXCTL_LASTFRAG)) != (SK_RXCTL_STATUS_VALID | 3088 SK_RXCTL_FIRSTFRAG | SK_RXCTL_LASTFRAG) || 3089 SK_RXBYTES(sk_ctl) < SK_MIN_FRAMELEN || 3090 SK_RXBYTES(sk_ctl) > SK_MAX_FRAMELEN || 3091 sk_rxvalid(sc, rxstat, SK_RXBYTES(sk_ctl)) == 0) { 3092 ifp->if_ierrors++; 3093 sk_discard_rxbuf(sc_if, cons); 3094 continue; 3095 } 3096 3097 m = rxd->rx_m; 3098 csum = le32toh(cur_rx->sk_csum); 3099 if (sk_newbuf(sc_if, cons) != 0) { 3100 ifp->if_iqdrops++; 3101 /* reuse old buffer */ 3102 sk_discard_rxbuf(sc_if, cons); 3103 continue; 3104 } 3105 m->m_pkthdr.rcvif = ifp; 3106 m->m_pkthdr.len = m->m_len = SK_RXBYTES(sk_ctl); 3107 ifp->if_ipackets++; 3108 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 3109 sk_rxcksum(ifp, m, csum); 3110 SK_IF_UNLOCK(sc_if); 3111 (*ifp->if_input)(ifp, m); 3112 SK_IF_LOCK(sc_if); 3113 } 3114 3115 if (prog > 0) { 3116 sc_if->sk_cdata.sk_rx_cons = cons; 3117 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag, 3118 sc_if->sk_cdata.sk_rx_ring_map, 3119 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3120 } 3121 } 3122 3123 static void 3124 sk_jumbo_rxeof(sc_if) 3125 struct sk_if_softc *sc_if; 3126 { 3127 struct sk_softc *sc; 3128 struct mbuf *m; 3129 struct ifnet *ifp; 3130 struct sk_rx_desc *cur_rx; 3131 struct sk_rxdesc *jrxd; 3132 int cons, prog; 3133 u_int32_t csum, rxstat, sk_ctl; 3134 3135 sc = sc_if->sk_softc; 3136 ifp = sc_if->sk_ifp; 3137 3138 SK_IF_LOCK_ASSERT(sc_if); 3139 3140 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 3141 sc_if->sk_cdata.sk_jumbo_rx_ring_map, BUS_DMASYNC_POSTREAD); 3142 3143 prog = 0; 3144 for (cons = sc_if->sk_cdata.sk_jumbo_rx_cons; 3145 prog < SK_JUMBO_RX_RING_CNT; 3146 prog++, SK_INC(cons, SK_JUMBO_RX_RING_CNT)) { 3147 cur_rx = &sc_if->sk_rdata.sk_jumbo_rx_ring[cons]; 3148 sk_ctl = le32toh(cur_rx->sk_ctl); 3149 if ((sk_ctl & SK_RXCTL_OWN) != 0) 3150 break; 3151 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[cons]; 3152 rxstat = le32toh(cur_rx->sk_xmac_rxstat); 3153 3154 if ((sk_ctl & (SK_RXCTL_STATUS_VALID | SK_RXCTL_FIRSTFRAG | 3155 SK_RXCTL_LASTFRAG)) != (SK_RXCTL_STATUS_VALID | 3156 SK_RXCTL_FIRSTFRAG | SK_RXCTL_LASTFRAG) || 3157 SK_RXBYTES(sk_ctl) < SK_MIN_FRAMELEN || 3158 SK_RXBYTES(sk_ctl) > SK_JUMBO_FRAMELEN || 3159 sk_rxvalid(sc, rxstat, SK_RXBYTES(sk_ctl)) == 0) { 3160 ifp->if_ierrors++; 3161 sk_discard_jumbo_rxbuf(sc_if, cons); 3162 continue; 3163 } 3164 3165 m = jrxd->rx_m; 3166 csum = le32toh(cur_rx->sk_csum); 3167 if (sk_jumbo_newbuf(sc_if, cons) != 0) { 3168 ifp->if_iqdrops++; 3169 /* reuse old buffer */ 3170 sk_discard_jumbo_rxbuf(sc_if, cons); 3171 continue; 3172 } 3173 m->m_pkthdr.rcvif = ifp; 3174 m->m_pkthdr.len = m->m_len = SK_RXBYTES(sk_ctl); 3175 ifp->if_ipackets++; 3176 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 3177 sk_rxcksum(ifp, m, csum); 3178 SK_IF_UNLOCK(sc_if); 3179 (*ifp->if_input)(ifp, m); 3180 SK_IF_LOCK(sc_if); 3181 } 3182 3183 if (prog > 0) { 3184 sc_if->sk_cdata.sk_jumbo_rx_cons = cons; 3185 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 3186 sc_if->sk_cdata.sk_jumbo_rx_ring_map, 3187 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3188 } 3189 } 3190 3191 static void 3192 sk_txeof(sc_if) 3193 struct sk_if_softc *sc_if; 3194 { 3195 struct sk_softc *sc; 3196 struct sk_txdesc *txd; 3197 struct sk_tx_desc *cur_tx; 3198 struct ifnet *ifp; 3199 u_int32_t idx, sk_ctl; 3200 3201 sc = sc_if->sk_softc; 3202 ifp = sc_if->sk_ifp; 3203 3204 txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txbusyq); 3205 if (txd == NULL) 3206 return; 3207 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag, 3208 sc_if->sk_cdata.sk_tx_ring_map, BUS_DMASYNC_POSTREAD); 3209 /* 3210 * Go through our tx ring and free mbufs for those 3211 * frames that have been sent. 3212 */ 3213 for (idx = sc_if->sk_cdata.sk_tx_cons;; SK_INC(idx, SK_TX_RING_CNT)) { 3214 if (sc_if->sk_cdata.sk_tx_cnt <= 0) 3215 break; 3216 cur_tx = &sc_if->sk_rdata.sk_tx_ring[idx]; 3217 sk_ctl = le32toh(cur_tx->sk_ctl); 3218 if (sk_ctl & SK_TXCTL_OWN) 3219 break; 3220 sc_if->sk_cdata.sk_tx_cnt--; 3221 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3222 if ((sk_ctl & SK_TXCTL_LASTFRAG) == 0) 3223 continue; 3224 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap, 3225 BUS_DMASYNC_POSTWRITE); 3226 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap); 3227 3228 ifp->if_opackets++; 3229 m_freem(txd->tx_m); 3230 txd->tx_m = NULL; 3231 STAILQ_REMOVE_HEAD(&sc_if->sk_cdata.sk_txbusyq, tx_q); 3232 STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txfreeq, txd, tx_q); 3233 txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txbusyq); 3234 } 3235 sc_if->sk_cdata.sk_tx_cons = idx; 3236 ifp->if_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0; 3237 3238 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag, 3239 sc_if->sk_cdata.sk_tx_ring_map, 3240 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3241 } 3242 3243 static void 3244 sk_tick(xsc_if) 3245 void *xsc_if; 3246 { 3247 struct sk_if_softc *sc_if; 3248 struct mii_data *mii; 3249 struct ifnet *ifp; 3250 int i; 3251 3252 sc_if = xsc_if; 3253 ifp = sc_if->sk_ifp; 3254 mii = device_get_softc(sc_if->sk_miibus); 3255 3256 if (!(ifp->if_flags & IFF_UP)) 3257 return; 3258 3259 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 3260 sk_intr_bcom(sc_if); 3261 return; 3262 } 3263 3264 /* 3265 * According to SysKonnect, the correct way to verify that 3266 * the link has come back up is to poll bit 0 of the GPIO 3267 * register three times. This pin has the signal from the 3268 * link_sync pin connected to it; if we read the same link 3269 * state 3 times in a row, we know the link is up. 3270 */ 3271 for (i = 0; i < 3; i++) { 3272 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 3273 break; 3274 } 3275 3276 if (i != 3) { 3277 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 3278 return; 3279 } 3280 3281 /* Turn the GP0 interrupt back on. */ 3282 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 3283 SK_XM_READ_2(sc_if, XM_ISR); 3284 mii_tick(mii); 3285 callout_stop(&sc_if->sk_tick_ch); 3286 } 3287 3288 static void 3289 sk_yukon_tick(xsc_if) 3290 void *xsc_if; 3291 { 3292 struct sk_if_softc *sc_if; 3293 struct mii_data *mii; 3294 3295 sc_if = xsc_if; 3296 mii = device_get_softc(sc_if->sk_miibus); 3297 3298 mii_tick(mii); 3299 callout_reset(&sc_if->sk_tick_ch, hz, sk_yukon_tick, sc_if); 3300 } 3301 3302 static void 3303 sk_intr_bcom(sc_if) 3304 struct sk_if_softc *sc_if; 3305 { 3306 struct mii_data *mii; 3307 struct ifnet *ifp; 3308 int status; 3309 mii = device_get_softc(sc_if->sk_miibus); 3310 ifp = sc_if->sk_ifp; 3311 3312 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 3313 3314 /* 3315 * Read the PHY interrupt register to make sure 3316 * we clear any pending interrupts. 3317 */ 3318 status = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 3319 3320 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3321 sk_init_xmac(sc_if); 3322 return; 3323 } 3324 3325 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 3326 int lstat; 3327 lstat = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 3328 BRGPHY_MII_AUXSTS); 3329 3330 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 3331 mii_mediachg(mii); 3332 /* Turn off the link LED. */ 3333 SK_IF_WRITE_1(sc_if, 0, 3334 SK_LINKLED1_CTL, SK_LINKLED_OFF); 3335 sc_if->sk_link = 0; 3336 } else if (status & BRGPHY_ISR_LNK_CHG) { 3337 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 3338 BRGPHY_MII_IMR, 0xFF00); 3339 mii_tick(mii); 3340 sc_if->sk_link = 1; 3341 /* Turn on the link LED. */ 3342 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 3343 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 3344 SK_LINKLED_BLINK_OFF); 3345 } else { 3346 mii_tick(mii); 3347 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 3348 } 3349 } 3350 3351 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 3352 3353 return; 3354 } 3355 3356 static void 3357 sk_intr_xmac(sc_if) 3358 struct sk_if_softc *sc_if; 3359 { 3360 struct sk_softc *sc; 3361 u_int16_t status; 3362 3363 sc = sc_if->sk_softc; 3364 status = SK_XM_READ_2(sc_if, XM_ISR); 3365 3366 /* 3367 * Link has gone down. Start MII tick timeout to 3368 * watch for link resync. 3369 */ 3370 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 3371 if (status & XM_ISR_GP0_SET) { 3372 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 3373 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 3374 } 3375 3376 if (status & XM_ISR_AUTONEG_DONE) { 3377 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 3378 } 3379 } 3380 3381 if (status & XM_IMR_TX_UNDERRUN) 3382 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 3383 3384 if (status & XM_IMR_RX_OVERRUN) 3385 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 3386 3387 status = SK_XM_READ_2(sc_if, XM_ISR); 3388 3389 return; 3390 } 3391 3392 static void 3393 sk_intr_yukon(sc_if) 3394 struct sk_if_softc *sc_if; 3395 { 3396 u_int8_t status; 3397 3398 status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR); 3399 /* RX overrun */ 3400 if ((status & SK_GMAC_INT_RX_OVER) != 0) { 3401 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 3402 SK_RFCTL_RX_FIFO_OVER); 3403 } 3404 /* TX underrun */ 3405 if ((status & SK_GMAC_INT_TX_UNDER) != 0) { 3406 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 3407 SK_TFCTL_TX_FIFO_UNDER); 3408 } 3409 } 3410 3411 static void 3412 sk_intr(xsc) 3413 void *xsc; 3414 { 3415 struct sk_softc *sc = xsc; 3416 struct sk_if_softc *sc_if0, *sc_if1; 3417 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 3418 u_int32_t status; 3419 3420 SK_LOCK(sc); 3421 3422 status = CSR_READ_4(sc, SK_ISSR); 3423 if (status == 0 || status == 0xffffffff || sc->sk_suspended) 3424 goto done_locked; 3425 3426 sc_if0 = sc->sk_if[SK_PORT_A]; 3427 sc_if1 = sc->sk_if[SK_PORT_B]; 3428 3429 if (sc_if0 != NULL) 3430 ifp0 = sc_if0->sk_ifp; 3431 if (sc_if1 != NULL) 3432 ifp1 = sc_if1->sk_ifp; 3433 3434 for (; (status &= sc->sk_intrmask) != 0;) { 3435 /* Handle receive interrupts first. */ 3436 if (status & SK_ISR_RX1_EOF) { 3437 if (ifp0->if_mtu > SK_MAX_FRAMELEN) 3438 sk_jumbo_rxeof(sc_if0); 3439 else 3440 sk_rxeof(sc_if0); 3441 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 3442 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 3443 } 3444 if (status & SK_ISR_RX2_EOF) { 3445 if (ifp1->if_mtu > SK_MAX_FRAMELEN) 3446 sk_jumbo_rxeof(sc_if1); 3447 else 3448 sk_rxeof(sc_if1); 3449 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 3450 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 3451 } 3452 3453 /* Then transmit interrupts. */ 3454 if (status & SK_ISR_TX1_S_EOF) { 3455 sk_txeof(sc_if0); 3456 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, SK_TXBMU_CLR_IRQ_EOF); 3457 } 3458 if (status & SK_ISR_TX2_S_EOF) { 3459 sk_txeof(sc_if1); 3460 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, SK_TXBMU_CLR_IRQ_EOF); 3461 } 3462 3463 /* Then MAC interrupts. */ 3464 if (status & SK_ISR_MAC1 && 3465 ifp0->if_drv_flags & IFF_DRV_RUNNING) { 3466 if (sc->sk_type == SK_GENESIS) 3467 sk_intr_xmac(sc_if0); 3468 else 3469 sk_intr_yukon(sc_if0); 3470 } 3471 3472 if (status & SK_ISR_MAC2 && 3473 ifp1->if_drv_flags & IFF_DRV_RUNNING) { 3474 if (sc->sk_type == SK_GENESIS) 3475 sk_intr_xmac(sc_if1); 3476 else 3477 sk_intr_yukon(sc_if1); 3478 } 3479 3480 if (status & SK_ISR_EXTERNAL_REG) { 3481 if (ifp0 != NULL && 3482 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 3483 sk_intr_bcom(sc_if0); 3484 if (ifp1 != NULL && 3485 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 3486 sk_intr_bcom(sc_if1); 3487 } 3488 status = CSR_READ_4(sc, SK_ISSR); 3489 } 3490 3491 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 3492 3493 if (ifp0 != NULL && !IFQ_DRV_IS_EMPTY(&ifp0->if_snd)) 3494 sk_start_locked(ifp0); 3495 if (ifp1 != NULL && !IFQ_DRV_IS_EMPTY(&ifp1->if_snd)) 3496 sk_start_locked(ifp1); 3497 3498 done_locked: 3499 SK_UNLOCK(sc); 3500 } 3501 3502 static void 3503 sk_init_xmac(sc_if) 3504 struct sk_if_softc *sc_if; 3505 { 3506 struct sk_softc *sc; 3507 struct ifnet *ifp; 3508 u_int16_t eaddr[(ETHER_ADDR_LEN+1)/2]; 3509 struct sk_bcom_hack bhack[] = { 3510 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 3511 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 3512 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 3513 { 0, 0 } }; 3514 3515 SK_IF_LOCK_ASSERT(sc_if); 3516 3517 sc = sc_if->sk_softc; 3518 ifp = sc_if->sk_ifp; 3519 3520 /* Unreset the XMAC. */ 3521 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 3522 DELAY(1000); 3523 3524 /* Reset the XMAC's internal state. */ 3525 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 3526 3527 /* Save the XMAC II revision */ 3528 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 3529 3530 /* 3531 * Perform additional initialization for external PHYs, 3532 * namely for the 1000baseTX cards that use the XMAC's 3533 * GMII mode. 3534 */ 3535 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 3536 int i = 0; 3537 u_int32_t val; 3538 3539 /* Take PHY out of reset. */ 3540 val = sk_win_read_4(sc, SK_GPIO); 3541 if (sc_if->sk_port == SK_PORT_A) 3542 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 3543 else 3544 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 3545 sk_win_write_4(sc, SK_GPIO, val); 3546 3547 /* Enable GMII mode on the XMAC. */ 3548 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 3549 3550 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 3551 BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET); 3552 DELAY(10000); 3553 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 3554 BRGPHY_MII_IMR, 0xFFF0); 3555 3556 /* 3557 * Early versions of the BCM5400 apparently have 3558 * a bug that requires them to have their reserved 3559 * registers initialized to some magic values. I don't 3560 * know what the numbers do, I'm just the messenger. 3561 */ 3562 if (sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 0x03) 3563 == 0x6041) { 3564 while(bhack[i].reg) { 3565 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 3566 bhack[i].reg, bhack[i].val); 3567 i++; 3568 } 3569 } 3570 } 3571 3572 /* Set station address */ 3573 bcopy(IF_LLADDR(sc_if->sk_ifp), eaddr, ETHER_ADDR_LEN); 3574 SK_XM_WRITE_2(sc_if, XM_PAR0, eaddr[0]); 3575 SK_XM_WRITE_2(sc_if, XM_PAR1, eaddr[1]); 3576 SK_XM_WRITE_2(sc_if, XM_PAR2, eaddr[2]); 3577 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 3578 3579 if (ifp->if_flags & IFF_BROADCAST) { 3580 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 3581 } else { 3582 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 3583 } 3584 3585 /* We don't need the FCS appended to the packet. */ 3586 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 3587 3588 /* We want short frames padded to 60 bytes. */ 3589 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 3590 3591 /* 3592 * Enable the reception of all error frames. This is is 3593 * a necessary evil due to the design of the XMAC. The 3594 * XMAC's receive FIFO is only 8K in size, however jumbo 3595 * frames can be up to 9000 bytes in length. When bad 3596 * frame filtering is enabled, the XMAC's RX FIFO operates 3597 * in 'store and forward' mode. For this to work, the 3598 * entire frame has to fit into the FIFO, but that means 3599 * that jumbo frames larger than 8192 bytes will be 3600 * truncated. Disabling all bad frame filtering causes 3601 * the RX FIFO to operate in streaming mode, in which 3602 * case the XMAC will start transfering frames out of the 3603 * RX FIFO as soon as the FIFO threshold is reached. 3604 */ 3605 if (ifp->if_mtu > SK_MAX_FRAMELEN) { 3606 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 3607 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 3608 XM_MODE_RX_INRANGELEN); 3609 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 3610 } else 3611 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 3612 3613 /* 3614 * Bump up the transmit threshold. This helps hold off transmit 3615 * underruns when we're blasting traffic from both ports at once. 3616 */ 3617 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 3618 3619 /* Set promiscuous mode */ 3620 sk_setpromisc(sc_if); 3621 3622 /* Set multicast filter */ 3623 sk_setmulti(sc_if); 3624 3625 /* Clear and enable interrupts */ 3626 SK_XM_READ_2(sc_if, XM_ISR); 3627 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 3628 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 3629 else 3630 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 3631 3632 /* Configure MAC arbiter */ 3633 switch(sc_if->sk_xmac_rev) { 3634 case XM_XMAC_REV_B2: 3635 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 3636 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 3637 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 3638 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 3639 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 3640 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 3641 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 3642 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 3643 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 3644 break; 3645 case XM_XMAC_REV_C1: 3646 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 3647 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 3648 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 3649 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 3650 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 3651 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 3652 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 3653 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 3654 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 3655 break; 3656 default: 3657 break; 3658 } 3659 sk_win_write_2(sc, SK_MACARB_CTL, 3660 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 3661 3662 sc_if->sk_link = 1; 3663 3664 return; 3665 } 3666 3667 static void 3668 sk_init_yukon(sc_if) 3669 struct sk_if_softc *sc_if; 3670 { 3671 u_int32_t phy, v; 3672 u_int16_t reg; 3673 struct sk_softc *sc; 3674 struct ifnet *ifp; 3675 int i; 3676 3677 SK_IF_LOCK_ASSERT(sc_if); 3678 3679 sc = sc_if->sk_softc; 3680 ifp = sc_if->sk_ifp; 3681 3682 if (sc->sk_type == SK_YUKON_LITE && 3683 sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 3684 /* 3685 * Workaround code for COMA mode, set PHY reset. 3686 * Otherwise it will not correctly take chip out of 3687 * powerdown (coma) 3688 */ 3689 v = sk_win_read_4(sc, SK_GPIO); 3690 v |= SK_GPIO_DIR9 | SK_GPIO_DAT9; 3691 sk_win_write_4(sc, SK_GPIO, v); 3692 } 3693 3694 /* GMAC and GPHY Reset */ 3695 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 3696 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 3697 DELAY(1000); 3698 3699 if (sc->sk_type == SK_YUKON_LITE && 3700 sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 3701 /* 3702 * Workaround code for COMA mode, clear PHY reset 3703 */ 3704 v = sk_win_read_4(sc, SK_GPIO); 3705 v |= SK_GPIO_DIR9; 3706 v &= ~SK_GPIO_DAT9; 3707 sk_win_write_4(sc, SK_GPIO, v); 3708 } 3709 3710 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 3711 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 3712 3713 if (sc->sk_coppertype) 3714 phy |= SK_GPHY_COPPER; 3715 else 3716 phy |= SK_GPHY_FIBER; 3717 3718 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 3719 DELAY(1000); 3720 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 3721 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 3722 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 3723 3724 /* unused read of the interrupt source register */ 3725 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 3726 3727 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 3728 3729 /* MIB Counter Clear Mode set */ 3730 reg |= YU_PAR_MIB_CLR; 3731 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 3732 3733 /* MIB Counter Clear Mode clear */ 3734 reg &= ~YU_PAR_MIB_CLR; 3735 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 3736 3737 /* receive control reg */ 3738 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR); 3739 3740 /* transmit parameter register */ 3741 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 3742 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 3743 3744 /* serial mode register */ 3745 reg = YU_SMR_DATA_BLIND(0x1c) | YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e); 3746 if (ifp->if_mtu > SK_MAX_FRAMELEN) 3747 reg |= YU_SMR_MFL_JUMBO; 3748 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg); 3749 3750 /* Setup Yukon's address */ 3751 for (i = 0; i < 3; i++) { 3752 /* Write Source Address 1 (unicast filter) */ 3753 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 3754 IF_LLADDR(sc_if->sk_ifp)[i * 2] | 3755 IF_LLADDR(sc_if->sk_ifp)[i * 2 + 1] << 8); 3756 } 3757 3758 for (i = 0; i < 3; i++) { 3759 reg = sk_win_read_2(sc_if->sk_softc, 3760 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 3761 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 3762 } 3763 3764 /* Set promiscuous mode */ 3765 sk_setpromisc(sc_if); 3766 3767 /* Set multicast filter */ 3768 sk_setmulti(sc_if); 3769 3770 /* enable interrupt mask for counter overflows */ 3771 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 3772 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 3773 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 3774 3775 /* Configure RX MAC FIFO Flush Mask */ 3776 v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR | 3777 YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT | 3778 YU_RXSTAT_JABBER; 3779 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v); 3780 3781 /* Disable RX MAC FIFO Flush for YUKON-Lite Rev. A0 only */ 3782 if (sc->sk_type == SK_YUKON_LITE && sc->sk_rev == SK_YUKON_LITE_REV_A0) 3783 v = SK_TFCTL_OPERATION_ON; 3784 else 3785 v = SK_TFCTL_OPERATION_ON | SK_RFCTL_FIFO_FLUSH_ON; 3786 /* Configure RX MAC FIFO */ 3787 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 3788 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, v); 3789 3790 /* Increase flush threshould to 64 bytes */ 3791 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD, 3792 SK_RFCTL_FIFO_THRESHOLD + 1); 3793 3794 /* Configure TX MAC FIFO */ 3795 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 3796 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 3797 } 3798 3799 /* 3800 * Note that to properly initialize any part of the GEnesis chip, 3801 * you first have to take it out of reset mode. 3802 */ 3803 static void 3804 sk_init(xsc) 3805 void *xsc; 3806 { 3807 struct sk_if_softc *sc_if = xsc; 3808 3809 SK_IF_LOCK(sc_if); 3810 sk_init_locked(sc_if); 3811 SK_IF_UNLOCK(sc_if); 3812 3813 return; 3814 } 3815 3816 static void 3817 sk_init_locked(sc_if) 3818 struct sk_if_softc *sc_if; 3819 { 3820 struct sk_softc *sc; 3821 struct ifnet *ifp; 3822 struct mii_data *mii; 3823 u_int16_t reg; 3824 u_int32_t imr; 3825 int error; 3826 3827 SK_IF_LOCK_ASSERT(sc_if); 3828 3829 ifp = sc_if->sk_ifp; 3830 sc = sc_if->sk_softc; 3831 mii = device_get_softc(sc_if->sk_miibus); 3832 3833 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3834 return; 3835 3836 /* Cancel pending I/O and free all RX/TX buffers. */ 3837 sk_stop(sc_if); 3838 3839 if (sc->sk_type == SK_GENESIS) { 3840 /* Configure LINK_SYNC LED */ 3841 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 3842 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 3843 SK_LINKLED_LINKSYNC_ON); 3844 3845 /* Configure RX LED */ 3846 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 3847 SK_RXLEDCTL_COUNTER_START); 3848 3849 /* Configure TX LED */ 3850 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 3851 SK_TXLEDCTL_COUNTER_START); 3852 } 3853 3854 /* 3855 * Configure descriptor poll timer 3856 * 3857 * SK-NET GENESIS data sheet says that possibility of losing Start 3858 * transmit command due to CPU/cache related interim storage problems 3859 * under certain conditions. The document recommends a polling 3860 * mechanism to send a Start transmit command to initiate transfer 3861 * of ready descriptors regulary. To cope with this issue sk(4) now 3862 * enables descriptor poll timer to initiate descriptor processing 3863 * periodically as defined by SK_DPT_TIMER_MAX. However sk(4) still 3864 * issue SK_TXBMU_TX_START to Tx BMU to get fast execution of Tx 3865 * command instead of waiting for next descriptor polling time. 3866 * The same rule may apply to Rx side too but it seems that is not 3867 * needed at the moment. 3868 * Since sk(4) uses descriptor polling as a last resort there is no 3869 * need to set smaller polling time than maximum allowable one. 3870 */ 3871 SK_IF_WRITE_4(sc_if, 0, SK_DPT_INIT, SK_DPT_TIMER_MAX); 3872 3873 /* Configure I2C registers */ 3874 3875 /* Configure XMAC(s) */ 3876 switch (sc->sk_type) { 3877 case SK_GENESIS: 3878 sk_init_xmac(sc_if); 3879 break; 3880 case SK_YUKON: 3881 case SK_YUKON_LITE: 3882 case SK_YUKON_LP: 3883 case SK_YUKON_EC: 3884 sk_init_yukon(sc_if); 3885 break; 3886 } 3887 mii_mediachg(mii); 3888 3889 if (sc->sk_type == SK_GENESIS) { 3890 /* Configure MAC FIFOs */ 3891 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 3892 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 3893 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 3894 3895 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 3896 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 3897 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 3898 } 3899 3900 /* Configure transmit arbiter(s) */ 3901 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 3902 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 3903 3904 /* Configure RAMbuffers */ 3905 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 3906 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 3907 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 3908 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 3909 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 3910 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 3911 3912 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 3913 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 3914 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 3915 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 3916 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 3917 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 3918 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 3919 3920 /* Configure BMUs */ 3921 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 3922 if (ifp->if_mtu > SK_MAX_FRAMELEN) { 3923 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 3924 SK_ADDR_LO(SK_JUMBO_RX_RING_ADDR(sc_if, 0))); 3925 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 3926 SK_ADDR_HI(SK_JUMBO_RX_RING_ADDR(sc_if, 0))); 3927 } else { 3928 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 3929 SK_ADDR_LO(SK_RX_RING_ADDR(sc_if, 0))); 3930 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 3931 SK_ADDR_HI(SK_RX_RING_ADDR(sc_if, 0))); 3932 } 3933 3934 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 3935 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 3936 SK_ADDR_LO(SK_TX_RING_ADDR(sc_if, 0))); 3937 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 3938 SK_ADDR_HI(SK_TX_RING_ADDR(sc_if, 0))); 3939 3940 /* Init descriptors */ 3941 if (ifp->if_mtu > SK_MAX_FRAMELEN) 3942 error = sk_init_jumbo_rx_ring(sc_if); 3943 else 3944 error = sk_init_rx_ring(sc_if); 3945 if (error != 0) { 3946 device_printf(sc_if->sk_if_dev, 3947 "initialization failed: no memory for rx buffers\n"); 3948 sk_stop(sc_if); 3949 return; 3950 } 3951 sk_init_tx_ring(sc_if); 3952 3953 /* Set interrupt moderation if changed via sysctl. */ 3954 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 3955 if (imr != SK_IM_USECS(sc->sk_int_mod, sc->sk_int_ticks)) { 3956 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod, 3957 sc->sk_int_ticks)); 3958 if (bootverbose) 3959 device_printf(sc_if->sk_if_dev, 3960 "interrupt moderation is %d us.\n", 3961 sc->sk_int_mod); 3962 } 3963 3964 /* Configure interrupt handling */ 3965 CSR_READ_4(sc, SK_ISSR); 3966 if (sc_if->sk_port == SK_PORT_A) 3967 sc->sk_intrmask |= SK_INTRS1; 3968 else 3969 sc->sk_intrmask |= SK_INTRS2; 3970 3971 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 3972 3973 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 3974 3975 /* Start BMUs. */ 3976 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 3977 3978 switch(sc->sk_type) { 3979 case SK_GENESIS: 3980 /* Enable XMACs TX and RX state machines */ 3981 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 3982 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 3983 break; 3984 case SK_YUKON: 3985 case SK_YUKON_LITE: 3986 case SK_YUKON_LP: 3987 case SK_YUKON_EC: 3988 reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 3989 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 3990 #if 0 3991 /* XXX disable 100Mbps and full duplex mode? */ 3992 reg &= ~(YU_GPCR_SPEED | YU_GPCR_DPLX_DIS); 3993 #endif 3994 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 3995 } 3996 3997 /* Activate descriptor polling timer */ 3998 SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_START); 3999 /* start transfer of Tx descriptors */ 4000 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 4001 4002 ifp->if_drv_flags |= IFF_DRV_RUNNING; 4003 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 4004 4005 switch (sc->sk_type) { 4006 case SK_YUKON: 4007 case SK_YUKON_LITE: 4008 case SK_YUKON_LP: 4009 case SK_YUKON_EC: 4010 callout_reset(&sc_if->sk_tick_ch, hz, sk_yukon_tick, sc_if); 4011 break; 4012 } 4013 4014 return; 4015 } 4016 4017 static void 4018 sk_stop(sc_if) 4019 struct sk_if_softc *sc_if; 4020 { 4021 int i; 4022 struct sk_softc *sc; 4023 struct sk_txdesc *txd; 4024 struct sk_rxdesc *rxd; 4025 struct sk_rxdesc *jrxd; 4026 struct ifnet *ifp; 4027 u_int32_t val; 4028 4029 SK_IF_LOCK_ASSERT(sc_if); 4030 sc = sc_if->sk_softc; 4031 ifp = sc_if->sk_ifp; 4032 4033 callout_stop(&sc_if->sk_tick_ch); 4034 4035 /* stop Tx descriptor polling timer */ 4036 SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP); 4037 /* stop transfer of Tx descriptors */ 4038 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_STOP); 4039 for (i = 0; i < SK_TIMEOUT; i++) { 4040 val = CSR_READ_4(sc, sc_if->sk_tx_bmu); 4041 if ((val & SK_TXBMU_TX_STOP) == 0) 4042 break; 4043 DELAY(1); 4044 } 4045 if (i == SK_TIMEOUT) 4046 device_printf(sc_if->sk_if_dev, 4047 "can not stop transfer of Tx descriptor\n"); 4048 /* stop transfer of Rx descriptors */ 4049 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_STOP); 4050 for (i = 0; i < SK_TIMEOUT; i++) { 4051 val = SK_IF_READ_4(sc_if, 0, SK_RXQ1_BMU_CSR); 4052 if ((val & SK_RXBMU_RX_STOP) == 0) 4053 break; 4054 DELAY(1); 4055 } 4056 if (i == SK_TIMEOUT) 4057 device_printf(sc_if->sk_if_dev, 4058 "can not stop transfer of Rx descriptor\n"); 4059 4060 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 4061 /* Put PHY back into reset. */ 4062 val = sk_win_read_4(sc, SK_GPIO); 4063 if (sc_if->sk_port == SK_PORT_A) { 4064 val |= SK_GPIO_DIR0; 4065 val &= ~SK_GPIO_DAT0; 4066 } else { 4067 val |= SK_GPIO_DIR2; 4068 val &= ~SK_GPIO_DAT2; 4069 } 4070 sk_win_write_4(sc, SK_GPIO, val); 4071 } 4072 4073 /* Turn off various components of this interface. */ 4074 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 4075 switch (sc->sk_type) { 4076 case SK_GENESIS: 4077 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_RESET); 4078 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 4079 break; 4080 case SK_YUKON: 4081 case SK_YUKON_LITE: 4082 case SK_YUKON_LP: 4083 case SK_YUKON_EC: 4084 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 4085 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 4086 break; 4087 } 4088 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 4089 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 4090 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 4091 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 4092 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 4093 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 4094 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 4095 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 4096 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 4097 4098 /* Disable interrupts */ 4099 if (sc_if->sk_port == SK_PORT_A) 4100 sc->sk_intrmask &= ~SK_INTRS1; 4101 else 4102 sc->sk_intrmask &= ~SK_INTRS2; 4103 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 4104 4105 SK_XM_READ_2(sc_if, XM_ISR); 4106 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 4107 4108 /* Free RX and TX mbufs still in the queues. */ 4109 for (i = 0; i < SK_RX_RING_CNT; i++) { 4110 rxd = &sc_if->sk_cdata.sk_rxdesc[i]; 4111 if (rxd->rx_m != NULL) { 4112 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag, 4113 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 4114 bus_dmamap_unload(sc_if->sk_cdata.sk_rx_tag, 4115 rxd->rx_dmamap); 4116 m_freem(rxd->rx_m); 4117 rxd->rx_m = NULL; 4118 } 4119 } 4120 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) { 4121 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i]; 4122 if (jrxd->rx_m != NULL) { 4123 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag, 4124 jrxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 4125 bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_tag, 4126 jrxd->rx_dmamap); 4127 m_freem(jrxd->rx_m); 4128 jrxd->rx_m = NULL; 4129 } 4130 } 4131 for (i = 0; i < SK_TX_RING_CNT; i++) { 4132 txd = &sc_if->sk_cdata.sk_txdesc[i]; 4133 if (txd->tx_m != NULL) { 4134 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag, 4135 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 4136 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag, 4137 txd->tx_dmamap); 4138 m_freem(txd->tx_m); 4139 txd->tx_m = NULL; 4140 } 4141 } 4142 4143 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING|IFF_DRV_OACTIVE); 4144 4145 return; 4146 } 4147 4148 static int 4149 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 4150 { 4151 int error, value; 4152 4153 if (!arg1) 4154 return (EINVAL); 4155 value = *(int *)arg1; 4156 error = sysctl_handle_int(oidp, &value, 0, req); 4157 if (error || !req->newptr) 4158 return (error); 4159 if (value < low || value > high) 4160 return (EINVAL); 4161 *(int *)arg1 = value; 4162 return (0); 4163 } 4164 4165 static int 4166 sysctl_hw_sk_int_mod(SYSCTL_HANDLER_ARGS) 4167 { 4168 return (sysctl_int_range(oidp, arg1, arg2, req, SK_IM_MIN, SK_IM_MAX)); 4169 } 4170