1 /* 2 * Copyright (c) 1997, 1998, 1999, 2000 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD$ 33 */ 34 35 /* 36 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 37 * the SK-984x series adapters, both single port and dual port. 38 * References: 39 * The XaQti XMAC II datasheet, 40 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 41 * The SysKonnect GEnesis manual, http://www.syskonnect.com 42 * 43 * Note: XaQti has been aquired by Vitesse, and Vitesse does not have the 44 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 45 * convenience to others until Vitesse corrects this problem: 46 * 47 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 48 * 49 * Written by Bill Paul <wpaul@ee.columbia.edu> 50 * Department of Electrical Engineering 51 * Columbia University, New York City 52 */ 53 54 /* 55 * The SysKonnect gigabit ethernet adapters consist of two main 56 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 57 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 58 * components and a PHY while the GEnesis controller provides a PCI 59 * interface with DMA support. Each card may have between 512K and 60 * 2MB of SRAM on board depending on the configuration. 61 * 62 * The SysKonnect GEnesis controller can have either one or two XMAC 63 * chips connected to it, allowing single or dual port NIC configurations. 64 * SysKonnect has the distinction of being the only vendor on the market 65 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 66 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 67 * XMAC registers. This driver takes advantage of these features to allow 68 * both XMACs to operate as independent interfaces. 69 */ 70 71 #include <sys/param.h> 72 #include <sys/systm.h> 73 #include <sys/sockio.h> 74 #include <sys/mbuf.h> 75 #include <sys/malloc.h> 76 #include <sys/kernel.h> 77 #include <sys/socket.h> 78 #include <sys/queue.h> 79 80 #include <net/if.h> 81 #include <net/if_arp.h> 82 #include <net/ethernet.h> 83 #include <net/if_dl.h> 84 #include <net/if_media.h> 85 86 #include <net/bpf.h> 87 88 #include <vm/vm.h> /* for vtophys */ 89 #include <vm/pmap.h> /* for vtophys */ 90 #include <machine/bus_pio.h> 91 #include <machine/bus_memio.h> 92 #include <machine/bus.h> 93 #include <machine/resource.h> 94 #include <sys/bus.h> 95 #include <sys/rman.h> 96 97 #include <dev/mii/mii.h> 98 #include <dev/mii/miivar.h> 99 #include <dev/mii/brgphyreg.h> 100 101 #include <pci/pcireg.h> 102 #include <pci/pcivar.h> 103 104 #define SK_USEIOSPACE 105 106 #include <pci/if_skreg.h> 107 #include <pci/xmaciireg.h> 108 109 MODULE_DEPEND(sk, miibus, 1, 1, 1); 110 111 /* "controller miibus0" required. See GENERIC if you get errors here. */ 112 #include "miibus_if.h" 113 114 #ifndef lint 115 static const char rcsid[] = 116 "$FreeBSD$"; 117 #endif 118 119 static struct sk_type sk_devs[] = { 120 { SK_VENDORID, SK_DEVICEID_GE, "SysKonnect Gigabit Ethernet" }, 121 { 0, 0, NULL } 122 }; 123 124 static int sk_probe (device_t); 125 static int sk_attach (device_t); 126 static int sk_detach (device_t); 127 static int sk_detach_xmac (device_t); 128 static int sk_probe_xmac (device_t); 129 static int sk_attach_xmac (device_t); 130 static void sk_tick (void *); 131 static void sk_intr (void *); 132 static void sk_intr_xmac (struct sk_if_softc *); 133 static void sk_intr_bcom (struct sk_if_softc *); 134 static void sk_rxeof (struct sk_if_softc *); 135 static void sk_txeof (struct sk_if_softc *); 136 static int sk_encap (struct sk_if_softc *, struct mbuf *, 137 u_int32_t *); 138 static void sk_start (struct ifnet *); 139 static int sk_ioctl (struct ifnet *, u_long, caddr_t); 140 static void sk_init (void *); 141 static void sk_init_xmac (struct sk_if_softc *); 142 static void sk_stop (struct sk_if_softc *); 143 static void sk_watchdog (struct ifnet *); 144 static void sk_shutdown (device_t); 145 static int sk_ifmedia_upd (struct ifnet *); 146 static void sk_ifmedia_sts (struct ifnet *, struct ifmediareq *); 147 static void sk_reset (struct sk_softc *); 148 static int sk_newbuf (struct sk_if_softc *, 149 struct sk_chain *, struct mbuf *); 150 static int sk_alloc_jumbo_mem (struct sk_if_softc *); 151 static void *sk_jalloc (struct sk_if_softc *); 152 static void sk_jfree (void *, void *); 153 static int sk_init_rx_ring (struct sk_if_softc *); 154 static void sk_init_tx_ring (struct sk_if_softc *); 155 static u_int32_t sk_win_read_4 (struct sk_softc *, int); 156 static u_int16_t sk_win_read_2 (struct sk_softc *, int); 157 static u_int8_t sk_win_read_1 (struct sk_softc *, int); 158 static void sk_win_write_4 (struct sk_softc *, int, u_int32_t); 159 static void sk_win_write_2 (struct sk_softc *, int, u_int32_t); 160 static void sk_win_write_1 (struct sk_softc *, int, u_int32_t); 161 static u_int8_t sk_vpd_readbyte (struct sk_softc *, int); 162 static void sk_vpd_read_res (struct sk_softc *, struct vpd_res *, int); 163 static void sk_vpd_read (struct sk_softc *); 164 165 static int sk_miibus_readreg (device_t, int, int); 166 static int sk_miibus_writereg (device_t, int, int, int); 167 static void sk_miibus_statchg (device_t); 168 169 static u_int32_t sk_calchash (caddr_t); 170 static void sk_setfilt (struct sk_if_softc *, caddr_t, int); 171 static void sk_setmulti (struct sk_if_softc *); 172 173 #ifdef SK_USEIOSPACE 174 #define SK_RES SYS_RES_IOPORT 175 #define SK_RID SK_PCI_LOIO 176 #else 177 #define SK_RES SYS_RES_MEMORY 178 #define SK_RID SK_PCI_LOMEM 179 #endif 180 181 /* 182 * Note that we have newbus methods for both the GEnesis controller 183 * itself and the XMAC(s). The XMACs are children of the GEnesis, and 184 * the miibus code is a child of the XMACs. We need to do it this way 185 * so that the miibus drivers can access the PHY registers on the 186 * right PHY. It's not quite what I had in mind, but it's the only 187 * design that achieves the desired effect. 188 */ 189 static device_method_t skc_methods[] = { 190 /* Device interface */ 191 DEVMETHOD(device_probe, sk_probe), 192 DEVMETHOD(device_attach, sk_attach), 193 DEVMETHOD(device_detach, sk_detach), 194 DEVMETHOD(device_shutdown, sk_shutdown), 195 196 /* bus interface */ 197 DEVMETHOD(bus_print_child, bus_generic_print_child), 198 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 199 200 { 0, 0 } 201 }; 202 203 static driver_t skc_driver = { 204 "skc", 205 skc_methods, 206 sizeof(struct sk_softc) 207 }; 208 209 static devclass_t skc_devclass; 210 211 static device_method_t sk_methods[] = { 212 /* Device interface */ 213 DEVMETHOD(device_probe, sk_probe_xmac), 214 DEVMETHOD(device_attach, sk_attach_xmac), 215 DEVMETHOD(device_detach, sk_detach_xmac), 216 DEVMETHOD(device_shutdown, bus_generic_shutdown), 217 218 /* bus interface */ 219 DEVMETHOD(bus_print_child, bus_generic_print_child), 220 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 221 222 /* MII interface */ 223 DEVMETHOD(miibus_readreg, sk_miibus_readreg), 224 DEVMETHOD(miibus_writereg, sk_miibus_writereg), 225 DEVMETHOD(miibus_statchg, sk_miibus_statchg), 226 227 { 0, 0 } 228 }; 229 230 static driver_t sk_driver = { 231 "sk", 232 sk_methods, 233 sizeof(struct sk_if_softc) 234 }; 235 236 static devclass_t sk_devclass; 237 238 DRIVER_MODULE(if_sk, pci, skc_driver, skc_devclass, 0, 0); 239 DRIVER_MODULE(sk, skc, sk_driver, sk_devclass, 0, 0); 240 DRIVER_MODULE(miibus, sk, miibus_driver, miibus_devclass, 0, 0); 241 242 #define SK_SETBIT(sc, reg, x) \ 243 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 244 245 #define SK_CLRBIT(sc, reg, x) \ 246 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 247 248 #define SK_WIN_SETBIT_4(sc, reg, x) \ 249 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x) 250 251 #define SK_WIN_CLRBIT_4(sc, reg, x) \ 252 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x) 253 254 #define SK_WIN_SETBIT_2(sc, reg, x) \ 255 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x) 256 257 #define SK_WIN_CLRBIT_2(sc, reg, x) \ 258 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x) 259 260 static u_int32_t 261 sk_win_read_4(sc, reg) 262 struct sk_softc *sc; 263 int reg; 264 { 265 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 266 return(CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg))); 267 } 268 269 static u_int16_t 270 sk_win_read_2(sc, reg) 271 struct sk_softc *sc; 272 int reg; 273 { 274 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 275 return(CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg))); 276 } 277 278 static u_int8_t 279 sk_win_read_1(sc, reg) 280 struct sk_softc *sc; 281 int reg; 282 { 283 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 284 return(CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg))); 285 } 286 287 static void 288 sk_win_write_4(sc, reg, val) 289 struct sk_softc *sc; 290 int reg; 291 u_int32_t val; 292 { 293 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 294 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), val); 295 return; 296 } 297 298 static void 299 sk_win_write_2(sc, reg, val) 300 struct sk_softc *sc; 301 int reg; 302 u_int32_t val; 303 { 304 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 305 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), (u_int32_t)val); 306 return; 307 } 308 309 static void 310 sk_win_write_1(sc, reg, val) 311 struct sk_softc *sc; 312 int reg; 313 u_int32_t val; 314 { 315 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 316 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), val); 317 return; 318 } 319 320 /* 321 * The VPD EEPROM contains Vital Product Data, as suggested in 322 * the PCI 2.1 specification. The VPD data is separared into areas 323 * denoted by resource IDs. The SysKonnect VPD contains an ID string 324 * resource (the name of the adapter), a read-only area resource 325 * containing various key/data fields and a read/write area which 326 * can be used to store asset management information or log messages. 327 * We read the ID string and read-only into buffers attached to 328 * the controller softc structure for later use. At the moment, 329 * we only use the ID string during sk_attach(). 330 */ 331 static u_int8_t 332 sk_vpd_readbyte(sc, addr) 333 struct sk_softc *sc; 334 int addr; 335 { 336 int i; 337 338 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 339 for (i = 0; i < SK_TIMEOUT; i++) { 340 DELAY(1); 341 if (sk_win_read_2(sc, 342 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 343 break; 344 } 345 346 if (i == SK_TIMEOUT) 347 return(0); 348 349 return(sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA))); 350 } 351 352 static void 353 sk_vpd_read_res(sc, res, addr) 354 struct sk_softc *sc; 355 struct vpd_res *res; 356 int addr; 357 { 358 int i; 359 u_int8_t *ptr; 360 361 ptr = (u_int8_t *)res; 362 for (i = 0; i < sizeof(struct vpd_res); i++) 363 ptr[i] = sk_vpd_readbyte(sc, i + addr); 364 365 return; 366 } 367 368 static void 369 sk_vpd_read(sc) 370 struct sk_softc *sc; 371 { 372 int pos = 0, i; 373 struct vpd_res res; 374 375 if (sc->sk_vpd_prodname != NULL) 376 free(sc->sk_vpd_prodname, M_DEVBUF); 377 if (sc->sk_vpd_readonly != NULL) 378 free(sc->sk_vpd_readonly, M_DEVBUF); 379 sc->sk_vpd_prodname = NULL; 380 sc->sk_vpd_readonly = NULL; 381 382 sk_vpd_read_res(sc, &res, pos); 383 384 if (res.vr_id != VPD_RES_ID) { 385 printf("skc%d: bad VPD resource id: expected %x got %x\n", 386 sc->sk_unit, VPD_RES_ID, res.vr_id); 387 return; 388 } 389 390 pos += sizeof(res); 391 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 392 for (i = 0; i < res.vr_len; i++) 393 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 394 sc->sk_vpd_prodname[i] = '\0'; 395 pos += i; 396 397 sk_vpd_read_res(sc, &res, pos); 398 399 if (res.vr_id != VPD_RES_READ) { 400 printf("skc%d: bad VPD resource id: expected %x got %x\n", 401 sc->sk_unit, VPD_RES_READ, res.vr_id); 402 return; 403 } 404 405 pos += sizeof(res); 406 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 407 for (i = 0; i < res.vr_len + 1; i++) 408 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 409 410 return; 411 } 412 413 static int 414 sk_miibus_readreg(dev, phy, reg) 415 device_t dev; 416 int phy, reg; 417 { 418 struct sk_if_softc *sc_if; 419 int i; 420 421 sc_if = device_get_softc(dev); 422 423 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 424 return(0); 425 426 SK_IF_LOCK(sc_if); 427 428 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 429 SK_XM_READ_2(sc_if, XM_PHY_DATA); 430 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 431 for (i = 0; i < SK_TIMEOUT; i++) { 432 DELAY(1); 433 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 434 XM_MMUCMD_PHYDATARDY) 435 break; 436 } 437 438 if (i == SK_TIMEOUT) { 439 printf("sk%d: phy failed to come ready\n", 440 sc_if->sk_unit); 441 return(0); 442 } 443 } 444 DELAY(1); 445 i = SK_XM_READ_2(sc_if, XM_PHY_DATA); 446 SK_IF_UNLOCK(sc_if); 447 return(i); 448 } 449 450 static int 451 sk_miibus_writereg(dev, phy, reg, val) 452 device_t dev; 453 int phy, reg, val; 454 { 455 struct sk_if_softc *sc_if; 456 int i; 457 458 sc_if = device_get_softc(dev); 459 SK_IF_LOCK(sc_if); 460 461 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 462 for (i = 0; i < SK_TIMEOUT; i++) { 463 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 464 break; 465 } 466 467 if (i == SK_TIMEOUT) { 468 printf("sk%d: phy failed to come ready\n", sc_if->sk_unit); 469 return(ETIMEDOUT); 470 } 471 472 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 473 for (i = 0; i < SK_TIMEOUT; i++) { 474 DELAY(1); 475 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 476 break; 477 } 478 479 SK_IF_UNLOCK(sc_if); 480 481 if (i == SK_TIMEOUT) 482 printf("sk%d: phy write timed out\n", sc_if->sk_unit); 483 484 return(0); 485 } 486 487 static void 488 sk_miibus_statchg(dev) 489 device_t dev; 490 { 491 struct sk_if_softc *sc_if; 492 struct mii_data *mii; 493 494 sc_if = device_get_softc(dev); 495 mii = device_get_softc(sc_if->sk_miibus); 496 SK_IF_LOCK(sc_if); 497 /* 498 * If this is a GMII PHY, manually set the XMAC's 499 * duplex mode accordingly. 500 */ 501 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 502 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 503 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 504 } else { 505 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 506 } 507 } 508 SK_IF_UNLOCK(sc_if); 509 510 return; 511 } 512 513 #define SK_POLY 0xEDB88320 514 #define SK_BITS 6 515 516 static u_int32_t 517 sk_calchash(addr) 518 caddr_t addr; 519 { 520 u_int32_t idx, bit, data, crc; 521 522 /* Compute CRC for the address value. */ 523 crc = 0xFFFFFFFF; /* initial value */ 524 525 for (idx = 0; idx < 6; idx++) { 526 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 527 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? SK_POLY : 0); 528 } 529 530 return (~crc & ((1 << SK_BITS) - 1)); 531 } 532 533 static void 534 sk_setfilt(sc_if, addr, slot) 535 struct sk_if_softc *sc_if; 536 caddr_t addr; 537 int slot; 538 { 539 int base; 540 541 base = XM_RXFILT_ENTRY(slot); 542 543 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 544 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 545 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 546 547 return; 548 } 549 550 static void 551 sk_setmulti(sc_if) 552 struct sk_if_softc *sc_if; 553 { 554 struct ifnet *ifp; 555 u_int32_t hashes[2] = { 0, 0 }; 556 int h, i; 557 struct ifmultiaddr *ifma; 558 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 559 560 ifp = &sc_if->arpcom.ac_if; 561 562 /* First, zot all the existing filters. */ 563 for (i = 1; i < XM_RXFILT_MAX; i++) 564 sk_setfilt(sc_if, (caddr_t)&dummy, i); 565 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 566 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 567 568 /* Now program new ones. */ 569 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 570 hashes[0] = 0xFFFFFFFF; 571 hashes[1] = 0xFFFFFFFF; 572 } else { 573 i = 1; 574 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, ifma_link) { 575 if (ifma->ifma_addr->sa_family != AF_LINK) 576 continue; 577 /* 578 * Program the first XM_RXFILT_MAX multicast groups 579 * into the perfect filter. For all others, 580 * use the hash table. 581 */ 582 if (i < XM_RXFILT_MAX) { 583 sk_setfilt(sc_if, 584 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i); 585 i++; 586 continue; 587 } 588 589 h = sk_calchash( 590 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 591 if (h < 32) 592 hashes[0] |= (1 << h); 593 else 594 hashes[1] |= (1 << (h - 32)); 595 } 596 } 597 598 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 599 XM_MODE_RX_USE_PERFECT); 600 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 601 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 602 603 return; 604 } 605 606 static int 607 sk_init_rx_ring(sc_if) 608 struct sk_if_softc *sc_if; 609 { 610 struct sk_chain_data *cd; 611 struct sk_ring_data *rd; 612 int i; 613 614 cd = &sc_if->sk_cdata; 615 rd = sc_if->sk_rdata; 616 617 bzero((char *)rd->sk_rx_ring, 618 sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 619 620 for (i = 0; i < SK_RX_RING_CNT; i++) { 621 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 622 if (sk_newbuf(sc_if, &cd->sk_rx_chain[i], NULL) == ENOBUFS) 623 return(ENOBUFS); 624 if (i == (SK_RX_RING_CNT - 1)) { 625 cd->sk_rx_chain[i].sk_next = 626 &cd->sk_rx_chain[0]; 627 rd->sk_rx_ring[i].sk_next = 628 vtophys(&rd->sk_rx_ring[0]); 629 } else { 630 cd->sk_rx_chain[i].sk_next = 631 &cd->sk_rx_chain[i + 1]; 632 rd->sk_rx_ring[i].sk_next = 633 vtophys(&rd->sk_rx_ring[i + 1]); 634 } 635 } 636 637 sc_if->sk_cdata.sk_rx_prod = 0; 638 sc_if->sk_cdata.sk_rx_cons = 0; 639 640 return(0); 641 } 642 643 static void 644 sk_init_tx_ring(sc_if) 645 struct sk_if_softc *sc_if; 646 { 647 struct sk_chain_data *cd; 648 struct sk_ring_data *rd; 649 int i; 650 651 cd = &sc_if->sk_cdata; 652 rd = sc_if->sk_rdata; 653 654 bzero((char *)sc_if->sk_rdata->sk_tx_ring, 655 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 656 657 for (i = 0; i < SK_TX_RING_CNT; i++) { 658 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 659 if (i == (SK_TX_RING_CNT - 1)) { 660 cd->sk_tx_chain[i].sk_next = 661 &cd->sk_tx_chain[0]; 662 rd->sk_tx_ring[i].sk_next = 663 vtophys(&rd->sk_tx_ring[0]); 664 } else { 665 cd->sk_tx_chain[i].sk_next = 666 &cd->sk_tx_chain[i + 1]; 667 rd->sk_tx_ring[i].sk_next = 668 vtophys(&rd->sk_tx_ring[i + 1]); 669 } 670 } 671 672 sc_if->sk_cdata.sk_tx_prod = 0; 673 sc_if->sk_cdata.sk_tx_cons = 0; 674 sc_if->sk_cdata.sk_tx_cnt = 0; 675 676 return; 677 } 678 679 static int 680 sk_newbuf(sc_if, c, m) 681 struct sk_if_softc *sc_if; 682 struct sk_chain *c; 683 struct mbuf *m; 684 { 685 struct mbuf *m_new = NULL; 686 struct sk_rx_desc *r; 687 688 if (m == NULL) { 689 caddr_t *buf = NULL; 690 691 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 692 if (m_new == NULL) 693 return(ENOBUFS); 694 695 /* Allocate the jumbo buffer */ 696 buf = sk_jalloc(sc_if); 697 if (buf == NULL) { 698 m_freem(m_new); 699 #ifdef SK_VERBOSE 700 printf("sk%d: jumbo allocation failed " 701 "-- packet dropped!\n", sc_if->sk_unit); 702 #endif 703 return(ENOBUFS); 704 } 705 706 /* Attach the buffer to the mbuf */ 707 MEXTADD(m_new, buf, SK_JLEN, sk_jfree, 708 (struct sk_if_softc *)sc_if, 0, EXT_NET_DRV); 709 m_new->m_data = (void *)buf; 710 m_new->m_pkthdr.len = m_new->m_len = SK_JLEN; 711 } else { 712 /* 713 * We're re-using a previously allocated mbuf; 714 * be sure to re-init pointers and lengths to 715 * default values. 716 */ 717 m_new = m; 718 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 719 m_new->m_data = m_new->m_ext.ext_buf; 720 } 721 722 /* 723 * Adjust alignment so packet payload begins on a 724 * longword boundary. Mandatory for Alpha, useful on 725 * x86 too. 726 */ 727 m_adj(m_new, ETHER_ALIGN); 728 729 r = c->sk_desc; 730 c->sk_mbuf = m_new; 731 r->sk_data_lo = vtophys(mtod(m_new, caddr_t)); 732 r->sk_ctl = m_new->m_len | SK_RXSTAT; 733 734 return(0); 735 } 736 737 /* 738 * Allocate jumbo buffer storage. The SysKonnect adapters support 739 * "jumbograms" (9K frames), although SysKonnect doesn't currently 740 * use them in their drivers. In order for us to use them, we need 741 * large 9K receive buffers, however standard mbuf clusters are only 742 * 2048 bytes in size. Consequently, we need to allocate and manage 743 * our own jumbo buffer pool. Fortunately, this does not require an 744 * excessive amount of additional code. 745 */ 746 static int 747 sk_alloc_jumbo_mem(sc_if) 748 struct sk_if_softc *sc_if; 749 { 750 caddr_t ptr; 751 register int i; 752 struct sk_jpool_entry *entry; 753 754 /* Grab a big chunk o' storage. */ 755 sc_if->sk_cdata.sk_jumbo_buf = contigmalloc(SK_JMEM, M_DEVBUF, 756 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 757 758 if (sc_if->sk_cdata.sk_jumbo_buf == NULL) { 759 printf("sk%d: no memory for jumbo buffers!\n", sc_if->sk_unit); 760 return(ENOBUFS); 761 } 762 763 SLIST_INIT(&sc_if->sk_jfree_listhead); 764 SLIST_INIT(&sc_if->sk_jinuse_listhead); 765 766 /* 767 * Now divide it up into 9K pieces and save the addresses 768 * in an array. 769 */ 770 ptr = sc_if->sk_cdata.sk_jumbo_buf; 771 for (i = 0; i < SK_JSLOTS; i++) { 772 sc_if->sk_cdata.sk_jslots[i] = ptr; 773 ptr += SK_JLEN; 774 entry = malloc(sizeof(struct sk_jpool_entry), 775 M_DEVBUF, M_NOWAIT); 776 if (entry == NULL) { 777 free(sc_if->sk_cdata.sk_jumbo_buf, M_DEVBUF); 778 sc_if->sk_cdata.sk_jumbo_buf = NULL; 779 printf("sk%d: no memory for jumbo " 780 "buffer queue!\n", sc_if->sk_unit); 781 return(ENOBUFS); 782 } 783 entry->slot = i; 784 SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 785 entry, jpool_entries); 786 } 787 788 return(0); 789 } 790 791 /* 792 * Allocate a jumbo buffer. 793 */ 794 static void * 795 sk_jalloc(sc_if) 796 struct sk_if_softc *sc_if; 797 { 798 struct sk_jpool_entry *entry; 799 800 entry = SLIST_FIRST(&sc_if->sk_jfree_listhead); 801 802 if (entry == NULL) { 803 #ifdef SK_VERBOSE 804 printf("sk%d: no free jumbo buffers\n", sc_if->sk_unit); 805 #endif 806 return(NULL); 807 } 808 809 SLIST_REMOVE_HEAD(&sc_if->sk_jfree_listhead, jpool_entries); 810 SLIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 811 return(sc_if->sk_cdata.sk_jslots[entry->slot]); 812 } 813 814 /* 815 * Release a jumbo buffer. 816 */ 817 static void 818 sk_jfree(buf, args) 819 void *buf; 820 void *args; 821 { 822 struct sk_if_softc *sc_if; 823 int i; 824 struct sk_jpool_entry *entry; 825 826 /* Extract the softc struct pointer. */ 827 sc_if = (struct sk_if_softc *)args; 828 829 if (sc_if == NULL) 830 panic("sk_jfree: didn't get softc pointer!"); 831 832 /* calculate the slot this buffer belongs to */ 833 i = ((vm_offset_t)buf 834 - (vm_offset_t)sc_if->sk_cdata.sk_jumbo_buf) / SK_JLEN; 835 836 if ((i < 0) || (i >= SK_JSLOTS)) 837 panic("sk_jfree: asked to free buffer that we don't manage!"); 838 839 entry = SLIST_FIRST(&sc_if->sk_jinuse_listhead); 840 if (entry == NULL) 841 panic("sk_jfree: buffer not in use!"); 842 entry->slot = i; 843 SLIST_REMOVE_HEAD(&sc_if->sk_jinuse_listhead, jpool_entries); 844 SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, entry, jpool_entries); 845 846 return; 847 } 848 849 /* 850 * Set media options. 851 */ 852 static int 853 sk_ifmedia_upd(ifp) 854 struct ifnet *ifp; 855 { 856 struct sk_if_softc *sc_if; 857 struct mii_data *mii; 858 859 sc_if = ifp->if_softc; 860 mii = device_get_softc(sc_if->sk_miibus); 861 sk_init(sc_if); 862 mii_mediachg(mii); 863 864 return(0); 865 } 866 867 /* 868 * Report current media status. 869 */ 870 static void 871 sk_ifmedia_sts(ifp, ifmr) 872 struct ifnet *ifp; 873 struct ifmediareq *ifmr; 874 { 875 struct sk_if_softc *sc_if; 876 struct mii_data *mii; 877 878 sc_if = ifp->if_softc; 879 mii = device_get_softc(sc_if->sk_miibus); 880 881 mii_pollstat(mii); 882 ifmr->ifm_active = mii->mii_media_active; 883 ifmr->ifm_status = mii->mii_media_status; 884 885 return; 886 } 887 888 static int 889 sk_ioctl(ifp, command, data) 890 struct ifnet *ifp; 891 u_long command; 892 caddr_t data; 893 { 894 struct sk_if_softc *sc_if = ifp->if_softc; 895 struct ifreq *ifr = (struct ifreq *) data; 896 int error = 0; 897 struct mii_data *mii; 898 899 SK_IF_LOCK(sc_if); 900 901 switch(command) { 902 case SIOCSIFADDR: 903 case SIOCGIFADDR: 904 error = ether_ioctl(ifp, command, data); 905 break; 906 case SIOCSIFMTU: 907 if (ifr->ifr_mtu > SK_JUMBO_MTU) 908 error = EINVAL; 909 else { 910 ifp->if_mtu = ifr->ifr_mtu; 911 sk_init(sc_if); 912 } 913 break; 914 case SIOCSIFFLAGS: 915 if (ifp->if_flags & IFF_UP) { 916 if (ifp->if_flags & IFF_RUNNING && 917 ifp->if_flags & IFF_PROMISC && 918 !(sc_if->sk_if_flags & IFF_PROMISC)) { 919 SK_XM_SETBIT_4(sc_if, XM_MODE, 920 XM_MODE_RX_PROMISC); 921 sk_setmulti(sc_if); 922 } else if (ifp->if_flags & IFF_RUNNING && 923 !(ifp->if_flags & IFF_PROMISC) && 924 sc_if->sk_if_flags & IFF_PROMISC) { 925 SK_XM_CLRBIT_4(sc_if, XM_MODE, 926 XM_MODE_RX_PROMISC); 927 sk_setmulti(sc_if); 928 } else 929 sk_init(sc_if); 930 } else { 931 if (ifp->if_flags & IFF_RUNNING) 932 sk_stop(sc_if); 933 } 934 sc_if->sk_if_flags = ifp->if_flags; 935 error = 0; 936 break; 937 case SIOCADDMULTI: 938 case SIOCDELMULTI: 939 sk_setmulti(sc_if); 940 error = 0; 941 break; 942 case SIOCGIFMEDIA: 943 case SIOCSIFMEDIA: 944 mii = device_get_softc(sc_if->sk_miibus); 945 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 946 break; 947 default: 948 error = EINVAL; 949 break; 950 } 951 952 SK_IF_UNLOCK(sc_if); 953 954 return(error); 955 } 956 957 /* 958 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 959 * IDs against our list and return a device name if we find a match. 960 */ 961 static int 962 sk_probe(dev) 963 device_t dev; 964 { 965 struct sk_type *t; 966 967 t = sk_devs; 968 969 while(t->sk_name != NULL) { 970 if ((pci_get_vendor(dev) == t->sk_vid) && 971 (pci_get_device(dev) == t->sk_did)) { 972 device_set_desc(dev, t->sk_name); 973 return(0); 974 } 975 t++; 976 } 977 978 return(ENXIO); 979 } 980 981 /* 982 * Force the GEnesis into reset, then bring it out of reset. 983 */ 984 static void 985 sk_reset(sc) 986 struct sk_softc *sc; 987 { 988 CSR_WRITE_4(sc, SK_CSR, SK_CSR_SW_RESET); 989 CSR_WRITE_4(sc, SK_CSR, SK_CSR_MASTER_RESET); 990 DELAY(1000); 991 CSR_WRITE_4(sc, SK_CSR, SK_CSR_SW_UNRESET); 992 CSR_WRITE_4(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 993 994 /* Configure packet arbiter */ 995 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 996 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 997 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 998 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 999 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1000 1001 /* Enable RAM interface */ 1002 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1003 1004 /* 1005 * Configure interrupt moderation. The moderation timer 1006 * defers interrupts specified in the interrupt moderation 1007 * timer mask based on the timeout specified in the interrupt 1008 * moderation timer init register. Each bit in the timer 1009 * register represents 18.825ns, so to specify a timeout in 1010 * microseconds, we have to multiply by 54. 1011 */ 1012 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(200)); 1013 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 1014 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 1015 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1016 1017 return; 1018 } 1019 1020 static int 1021 sk_probe_xmac(dev) 1022 device_t dev; 1023 { 1024 /* 1025 * Not much to do here. We always know there will be 1026 * at least one XMAC present, and if there are two, 1027 * sk_attach() will create a second device instance 1028 * for us. 1029 */ 1030 device_set_desc(dev, "XaQti Corp. XMAC II"); 1031 1032 return(0); 1033 } 1034 1035 /* 1036 * Each XMAC chip is attached as a separate logical IP interface. 1037 * Single port cards will have only one logical interface of course. 1038 */ 1039 static int 1040 sk_attach_xmac(dev) 1041 device_t dev; 1042 { 1043 struct sk_softc *sc; 1044 struct sk_if_softc *sc_if; 1045 struct ifnet *ifp; 1046 int i, port; 1047 1048 if (dev == NULL) 1049 return(EINVAL); 1050 1051 sc_if = device_get_softc(dev); 1052 sc = device_get_softc(device_get_parent(dev)); 1053 SK_LOCK(sc); 1054 port = *(int *)device_get_ivars(dev); 1055 free(device_get_ivars(dev), M_DEVBUF); 1056 device_set_ivars(dev, NULL); 1057 sc_if->sk_dev = dev; 1058 1059 bzero((char *)sc_if, sizeof(struct sk_if_softc)); 1060 1061 sc_if->sk_dev = dev; 1062 sc_if->sk_unit = device_get_unit(dev); 1063 sc_if->sk_port = port; 1064 sc_if->sk_softc = sc; 1065 sc->sk_if[port] = sc_if; 1066 if (port == SK_PORT_A) 1067 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1068 if (port == SK_PORT_B) 1069 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1070 1071 /* 1072 * Get station address for this interface. Note that 1073 * dual port cards actually come with three station 1074 * addresses: one for each port, plus an extra. The 1075 * extra one is used by the SysKonnect driver software 1076 * as a 'virtual' station address for when both ports 1077 * are operating in failover mode. Currently we don't 1078 * use this extra address. 1079 */ 1080 for (i = 0; i < ETHER_ADDR_LEN; i++) 1081 sc_if->arpcom.ac_enaddr[i] = 1082 sk_win_read_1(sc, SK_MAC0_0 + (port * 8) + i); 1083 1084 printf("sk%d: Ethernet address: %6D\n", 1085 sc_if->sk_unit, sc_if->arpcom.ac_enaddr, ":"); 1086 1087 /* 1088 * Set up RAM buffer addresses. The NIC will have a certain 1089 * amount of SRAM on it, somewhere between 512K and 2MB. We 1090 * need to divide this up a) between the transmitter and 1091 * receiver and b) between the two XMACs, if this is a 1092 * dual port NIC. Our algotithm is to divide up the memory 1093 * evenly so that everyone gets a fair share. 1094 */ 1095 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1096 u_int32_t chunk, val; 1097 1098 chunk = sc->sk_ramsize / 2; 1099 val = sc->sk_rboff / sizeof(u_int64_t); 1100 sc_if->sk_rx_ramstart = val; 1101 val += (chunk / sizeof(u_int64_t)); 1102 sc_if->sk_rx_ramend = val - 1; 1103 sc_if->sk_tx_ramstart = val; 1104 val += (chunk / sizeof(u_int64_t)); 1105 sc_if->sk_tx_ramend = val - 1; 1106 } else { 1107 u_int32_t chunk, val; 1108 1109 chunk = sc->sk_ramsize / 4; 1110 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1111 sizeof(u_int64_t); 1112 sc_if->sk_rx_ramstart = val; 1113 val += (chunk / sizeof(u_int64_t)); 1114 sc_if->sk_rx_ramend = val - 1; 1115 sc_if->sk_tx_ramstart = val; 1116 val += (chunk / sizeof(u_int64_t)); 1117 sc_if->sk_tx_ramend = val - 1; 1118 } 1119 1120 /* Read and save PHY type and set PHY address */ 1121 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1122 switch(sc_if->sk_phytype) { 1123 case SK_PHYTYPE_XMAC: 1124 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1125 break; 1126 case SK_PHYTYPE_BCOM: 1127 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1128 break; 1129 default: 1130 printf("skc%d: unsupported PHY type: %d\n", 1131 sc->sk_unit, sc_if->sk_phytype); 1132 SK_UNLOCK(sc); 1133 return(ENODEV); 1134 } 1135 1136 /* Allocate the descriptor queues. */ 1137 sc_if->sk_rdata = contigmalloc(sizeof(struct sk_ring_data), M_DEVBUF, 1138 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1139 1140 if (sc_if->sk_rdata == NULL) { 1141 printf("sk%d: no memory for list buffers!\n", sc_if->sk_unit); 1142 sc->sk_if[port] = NULL; 1143 SK_UNLOCK(sc); 1144 return(ENOMEM); 1145 } 1146 1147 bzero(sc_if->sk_rdata, sizeof(struct sk_ring_data)); 1148 1149 /* Try to allocate memory for jumbo buffers. */ 1150 if (sk_alloc_jumbo_mem(sc_if)) { 1151 printf("sk%d: jumbo buffer allocation failed\n", 1152 sc_if->sk_unit); 1153 contigfree(sc_if->sk_rdata, 1154 sizeof(struct sk_ring_data), M_DEVBUF); 1155 sc->sk_if[port] = NULL; 1156 SK_UNLOCK(sc); 1157 return(ENOMEM); 1158 } 1159 1160 ifp = &sc_if->arpcom.ac_if; 1161 ifp->if_softc = sc_if; 1162 ifp->if_unit = sc_if->sk_unit; 1163 ifp->if_name = "sk"; 1164 ifp->if_mtu = ETHERMTU; 1165 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1166 ifp->if_ioctl = sk_ioctl; 1167 ifp->if_output = ether_output; 1168 ifp->if_start = sk_start; 1169 ifp->if_watchdog = sk_watchdog; 1170 ifp->if_init = sk_init; 1171 ifp->if_baudrate = 1000000000; 1172 ifp->if_snd.ifq_maxlen = SK_TX_RING_CNT - 1; 1173 1174 /* 1175 * Call MI attach routine. 1176 */ 1177 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 1178 callout_handle_init(&sc_if->sk_tick_ch); 1179 1180 /* 1181 * Do miibus setup. 1182 */ 1183 sk_init_xmac(sc_if); 1184 if (mii_phy_probe(dev, &sc_if->sk_miibus, 1185 sk_ifmedia_upd, sk_ifmedia_sts)) { 1186 printf("skc%d: no PHY found!\n", sc_if->sk_unit); 1187 contigfree(sc_if->sk_rdata, 1188 sizeof(struct sk_ring_data), M_DEVBUF); 1189 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 1190 SK_UNLOCK(sc); 1191 return(ENXIO); 1192 } 1193 1194 SK_UNLOCK(sc); 1195 1196 return(0); 1197 } 1198 1199 /* 1200 * Attach the interface. Allocate softc structures, do ifmedia 1201 * setup and ethernet/BPF attach. 1202 */ 1203 static int 1204 sk_attach(dev) 1205 device_t dev; 1206 { 1207 u_int32_t command; 1208 struct sk_softc *sc; 1209 int unit, error = 0, rid, *port; 1210 1211 sc = device_get_softc(dev); 1212 unit = device_get_unit(dev); 1213 bzero(sc, sizeof(struct sk_softc)); 1214 1215 mtx_init(&sc->sk_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1216 MTX_DEF | MTX_RECURSE); 1217 SK_LOCK(sc); 1218 1219 /* 1220 * Handle power management nonsense. 1221 */ 1222 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1223 u_int32_t iobase, membase, irq; 1224 1225 /* Save important PCI config data. */ 1226 iobase = pci_read_config(dev, SK_PCI_LOIO, 4); 1227 membase = pci_read_config(dev, SK_PCI_LOMEM, 4); 1228 irq = pci_read_config(dev, SK_PCI_INTLINE, 4); 1229 1230 /* Reset the power state. */ 1231 printf("skc%d: chip is in D%d power mode " 1232 "-- setting to D0\n", unit, 1233 pci_get_powerstate(dev)); 1234 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1235 1236 /* Restore PCI config data. */ 1237 pci_write_config(dev, SK_PCI_LOIO, iobase, 4); 1238 pci_write_config(dev, SK_PCI_LOMEM, membase, 4); 1239 pci_write_config(dev, SK_PCI_INTLINE, irq, 4); 1240 } 1241 1242 /* 1243 * Map control/status registers. 1244 */ 1245 pci_enable_busmaster(dev); 1246 pci_enable_io(dev, SYS_RES_IOPORT); 1247 pci_enable_io(dev, SYS_RES_MEMORY); 1248 command = pci_read_config(dev, PCIR_COMMAND, 4); 1249 1250 #ifdef SK_USEIOSPACE 1251 if (!(command & PCIM_CMD_PORTEN)) { 1252 printf("skc%d: failed to enable I/O ports!\n", unit); 1253 error = ENXIO; 1254 goto fail; 1255 } 1256 #else 1257 if (!(command & PCIM_CMD_MEMEN)) { 1258 printf("skc%d: failed to enable memory mapping!\n", unit); 1259 error = ENXIO; 1260 goto fail; 1261 } 1262 #endif 1263 1264 rid = SK_RID; 1265 sc->sk_res = bus_alloc_resource(dev, SK_RES, &rid, 1266 0, ~0, 1, RF_ACTIVE); 1267 1268 if (sc->sk_res == NULL) { 1269 printf("sk%d: couldn't map ports/memory\n", unit); 1270 error = ENXIO; 1271 goto fail; 1272 } 1273 1274 sc->sk_btag = rman_get_bustag(sc->sk_res); 1275 sc->sk_bhandle = rman_get_bushandle(sc->sk_res); 1276 1277 /* Allocate interrupt */ 1278 rid = 0; 1279 sc->sk_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1280 RF_SHAREABLE | RF_ACTIVE); 1281 1282 if (sc->sk_irq == NULL) { 1283 printf("skc%d: couldn't map interrupt\n", unit); 1284 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res); 1285 error = ENXIO; 1286 goto fail; 1287 } 1288 1289 error = bus_setup_intr(dev, sc->sk_irq, INTR_TYPE_NET, 1290 sk_intr, sc, &sc->sk_intrhand); 1291 1292 if (error) { 1293 printf("skc%d: couldn't set up irq\n", unit); 1294 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res); 1295 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq); 1296 goto fail; 1297 } 1298 1299 /* Reset the adapter. */ 1300 sk_reset(sc); 1301 1302 sc->sk_unit = unit; 1303 1304 /* Read and save vital product data from EEPROM. */ 1305 sk_vpd_read(sc); 1306 1307 /* Read and save RAM size and RAMbuffer offset */ 1308 switch(sk_win_read_1(sc, SK_EPROM0)) { 1309 case SK_RAMSIZE_512K_64: 1310 sc->sk_ramsize = 0x80000; 1311 sc->sk_rboff = SK_RBOFF_0; 1312 break; 1313 case SK_RAMSIZE_1024K_64: 1314 sc->sk_ramsize = 0x100000; 1315 sc->sk_rboff = SK_RBOFF_80000; 1316 break; 1317 case SK_RAMSIZE_1024K_128: 1318 sc->sk_ramsize = 0x100000; 1319 sc->sk_rboff = SK_RBOFF_0; 1320 break; 1321 case SK_RAMSIZE_2048K_128: 1322 sc->sk_ramsize = 0x200000; 1323 sc->sk_rboff = SK_RBOFF_0; 1324 break; 1325 default: 1326 printf("skc%d: unknown ram size: %d\n", 1327 sc->sk_unit, sk_win_read_1(sc, SK_EPROM0)); 1328 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand); 1329 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq); 1330 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res); 1331 error = ENXIO; 1332 goto fail; 1333 break; 1334 } 1335 1336 /* Read and save physical media type */ 1337 switch(sk_win_read_1(sc, SK_PMDTYPE)) { 1338 case SK_PMD_1000BASESX: 1339 sc->sk_pmd = IFM_1000_SX; 1340 break; 1341 case SK_PMD_1000BASELX: 1342 sc->sk_pmd = IFM_1000_LX; 1343 break; 1344 case SK_PMD_1000BASECX: 1345 sc->sk_pmd = IFM_1000_CX; 1346 break; 1347 case SK_PMD_1000BASETX: 1348 sc->sk_pmd = IFM_1000_T; 1349 break; 1350 default: 1351 printf("skc%d: unknown media type: 0x%x\n", 1352 sc->sk_unit, sk_win_read_1(sc, SK_PMDTYPE)); 1353 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand); 1354 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq); 1355 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res); 1356 error = ENXIO; 1357 goto fail; 1358 } 1359 1360 /* Announce the product name. */ 1361 printf("skc%d: %s\n", sc->sk_unit, sc->sk_vpd_prodname); 1362 sc->sk_devs[SK_PORT_A] = device_add_child(dev, "sk", -1); 1363 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT); 1364 *port = SK_PORT_A; 1365 device_set_ivars(sc->sk_devs[SK_PORT_A], port); 1366 1367 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1368 sc->sk_devs[SK_PORT_B] = device_add_child(dev, "sk", -1); 1369 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT); 1370 *port = SK_PORT_B; 1371 device_set_ivars(sc->sk_devs[SK_PORT_B], port); 1372 } 1373 1374 /* Turn on the 'driver is loaded' LED. */ 1375 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1376 1377 bus_generic_attach(dev); 1378 SK_UNLOCK(sc); 1379 return(0); 1380 1381 fail: 1382 SK_UNLOCK(sc); 1383 mtx_destroy(&sc->sk_mtx); 1384 return(error); 1385 } 1386 1387 static int 1388 sk_detach_xmac(dev) 1389 device_t dev; 1390 { 1391 struct sk_softc *sc; 1392 struct sk_if_softc *sc_if; 1393 struct ifnet *ifp; 1394 1395 sc = device_get_softc(device_get_parent(dev)); 1396 sc_if = device_get_softc(dev); 1397 SK_IF_LOCK(sc_if); 1398 1399 ifp = &sc_if->arpcom.ac_if; 1400 sk_stop(sc_if); 1401 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 1402 bus_generic_detach(dev); 1403 if (sc_if->sk_miibus != NULL) 1404 device_delete_child(dev, sc_if->sk_miibus); 1405 contigfree(sc_if->sk_cdata.sk_jumbo_buf, SK_JMEM, M_DEVBUF); 1406 contigfree(sc_if->sk_rdata, sizeof(struct sk_ring_data), M_DEVBUF); 1407 SK_IF_UNLOCK(sc_if); 1408 1409 return(0); 1410 } 1411 1412 static int 1413 sk_detach(dev) 1414 device_t dev; 1415 { 1416 struct sk_softc *sc; 1417 1418 sc = device_get_softc(dev); 1419 SK_LOCK(sc); 1420 1421 bus_generic_detach(dev); 1422 if (sc->sk_devs[SK_PORT_A] != NULL) 1423 device_delete_child(dev, sc->sk_devs[SK_PORT_A]); 1424 if (sc->sk_devs[SK_PORT_B] != NULL) 1425 device_delete_child(dev, sc->sk_devs[SK_PORT_B]); 1426 1427 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand); 1428 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq); 1429 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res); 1430 1431 SK_UNLOCK(sc); 1432 mtx_destroy(&sc->sk_mtx); 1433 1434 return(0); 1435 } 1436 1437 static int 1438 sk_encap(sc_if, m_head, txidx) 1439 struct sk_if_softc *sc_if; 1440 struct mbuf *m_head; 1441 u_int32_t *txidx; 1442 { 1443 struct sk_tx_desc *f = NULL; 1444 struct mbuf *m; 1445 u_int32_t frag, cur, cnt = 0; 1446 1447 m = m_head; 1448 cur = frag = *txidx; 1449 1450 /* 1451 * Start packing the mbufs in this chain into 1452 * the fragment pointers. Stop when we run out 1453 * of fragments or hit the end of the mbuf chain. 1454 */ 1455 for (m = m_head; m != NULL; m = m->m_next) { 1456 if (m->m_len != 0) { 1457 if ((SK_TX_RING_CNT - 1458 (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) 1459 return(ENOBUFS); 1460 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1461 f->sk_data_lo = vtophys(mtod(m, vm_offset_t)); 1462 f->sk_ctl = m->m_len | SK_OPCODE_DEFAULT; 1463 if (cnt == 0) 1464 f->sk_ctl |= SK_TXCTL_FIRSTFRAG; 1465 else 1466 f->sk_ctl |= SK_TXCTL_OWN; 1467 cur = frag; 1468 SK_INC(frag, SK_TX_RING_CNT); 1469 cnt++; 1470 } 1471 } 1472 1473 if (m != NULL) 1474 return(ENOBUFS); 1475 1476 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1477 SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR; 1478 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1479 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= SK_TXCTL_OWN; 1480 sc_if->sk_cdata.sk_tx_cnt += cnt; 1481 1482 *txidx = frag; 1483 1484 return(0); 1485 } 1486 1487 static void 1488 sk_start(ifp) 1489 struct ifnet *ifp; 1490 { 1491 struct sk_softc *sc; 1492 struct sk_if_softc *sc_if; 1493 struct mbuf *m_head = NULL; 1494 u_int32_t idx; 1495 1496 sc_if = ifp->if_softc; 1497 sc = sc_if->sk_softc; 1498 1499 SK_IF_LOCK(sc_if); 1500 1501 idx = sc_if->sk_cdata.sk_tx_prod; 1502 1503 while(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1504 IF_DEQUEUE(&ifp->if_snd, m_head); 1505 if (m_head == NULL) 1506 break; 1507 1508 /* 1509 * Pack the data into the transmit ring. If we 1510 * don't have room, set the OACTIVE flag and wait 1511 * for the NIC to drain the ring. 1512 */ 1513 if (sk_encap(sc_if, m_head, &idx)) { 1514 IF_PREPEND(&ifp->if_snd, m_head); 1515 ifp->if_flags |= IFF_OACTIVE; 1516 break; 1517 } 1518 1519 /* 1520 * If there's a BPF listener, bounce a copy of this frame 1521 * to him. 1522 */ 1523 if (ifp->if_bpf) 1524 bpf_mtap(ifp, m_head); 1525 } 1526 1527 /* Transmit */ 1528 sc_if->sk_cdata.sk_tx_prod = idx; 1529 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1530 1531 /* Set a timeout in case the chip goes out to lunch. */ 1532 ifp->if_timer = 5; 1533 SK_IF_UNLOCK(sc_if); 1534 1535 return; 1536 } 1537 1538 1539 static void 1540 sk_watchdog(ifp) 1541 struct ifnet *ifp; 1542 { 1543 struct sk_if_softc *sc_if; 1544 1545 sc_if = ifp->if_softc; 1546 1547 printf("sk%d: watchdog timeout\n", sc_if->sk_unit); 1548 sk_init(sc_if); 1549 1550 return; 1551 } 1552 1553 static void 1554 sk_shutdown(dev) 1555 device_t dev; 1556 { 1557 struct sk_softc *sc; 1558 1559 sc = device_get_softc(dev); 1560 SK_LOCK(sc); 1561 1562 /* Turn off the 'driver is loaded' LED. */ 1563 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1564 1565 /* 1566 * Reset the GEnesis controller. Doing this should also 1567 * assert the resets on the attached XMAC(s). 1568 */ 1569 sk_reset(sc); 1570 SK_UNLOCK(sc); 1571 1572 return; 1573 } 1574 1575 static void 1576 sk_rxeof(sc_if) 1577 struct sk_if_softc *sc_if; 1578 { 1579 struct ether_header *eh; 1580 struct mbuf *m; 1581 struct ifnet *ifp; 1582 struct sk_chain *cur_rx; 1583 int total_len = 0; 1584 int i; 1585 u_int32_t rxstat; 1586 1587 ifp = &sc_if->arpcom.ac_if; 1588 i = sc_if->sk_cdata.sk_rx_prod; 1589 cur_rx = &sc_if->sk_cdata.sk_rx_chain[i]; 1590 1591 while(!(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl & SK_RXCTL_OWN)) { 1592 1593 cur_rx = &sc_if->sk_cdata.sk_rx_chain[i]; 1594 rxstat = sc_if->sk_rdata->sk_rx_ring[i].sk_xmac_rxstat; 1595 m = cur_rx->sk_mbuf; 1596 cur_rx->sk_mbuf = NULL; 1597 total_len = SK_RXBYTES(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl); 1598 SK_INC(i, SK_RX_RING_CNT); 1599 1600 if (rxstat & XM_RXSTAT_ERRFRAME) { 1601 ifp->if_ierrors++; 1602 sk_newbuf(sc_if, cur_rx, m); 1603 continue; 1604 } 1605 1606 /* 1607 * Try to allocate a new jumbo buffer. If that 1608 * fails, copy the packet to mbufs and put the 1609 * jumbo buffer back in the ring so it can be 1610 * re-used. If allocating mbufs fails, then we 1611 * have to drop the packet. 1612 */ 1613 if (sk_newbuf(sc_if, cur_rx, NULL) == ENOBUFS) { 1614 struct mbuf *m0; 1615 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, 1616 ifp, NULL); 1617 sk_newbuf(sc_if, cur_rx, m); 1618 if (m0 == NULL) { 1619 printf("sk%d: no receive buffers " 1620 "available -- packet dropped!\n", 1621 sc_if->sk_unit); 1622 ifp->if_ierrors++; 1623 continue; 1624 } 1625 m = m0; 1626 } else { 1627 m->m_pkthdr.rcvif = ifp; 1628 m->m_pkthdr.len = m->m_len = total_len; 1629 } 1630 1631 ifp->if_ipackets++; 1632 eh = mtod(m, struct ether_header *); 1633 1634 /* Remove header from mbuf and pass it on. */ 1635 m_adj(m, sizeof(struct ether_header)); 1636 ether_input(ifp, eh, m); 1637 } 1638 1639 sc_if->sk_cdata.sk_rx_prod = i; 1640 1641 return; 1642 } 1643 1644 static void 1645 sk_txeof(sc_if) 1646 struct sk_if_softc *sc_if; 1647 { 1648 struct sk_tx_desc *cur_tx = NULL; 1649 struct ifnet *ifp; 1650 u_int32_t idx; 1651 1652 ifp = &sc_if->arpcom.ac_if; 1653 1654 /* 1655 * Go through our tx ring and free mbufs for those 1656 * frames that have been sent. 1657 */ 1658 idx = sc_if->sk_cdata.sk_tx_cons; 1659 while(idx != sc_if->sk_cdata.sk_tx_prod) { 1660 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 1661 if (cur_tx->sk_ctl & SK_TXCTL_OWN) 1662 break; 1663 if (cur_tx->sk_ctl & SK_TXCTL_LASTFRAG) 1664 ifp->if_opackets++; 1665 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 1666 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 1667 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 1668 } 1669 sc_if->sk_cdata.sk_tx_cnt--; 1670 SK_INC(idx, SK_TX_RING_CNT); 1671 ifp->if_timer = 0; 1672 } 1673 1674 sc_if->sk_cdata.sk_tx_cons = idx; 1675 1676 if (cur_tx != NULL) 1677 ifp->if_flags &= ~IFF_OACTIVE; 1678 1679 return; 1680 } 1681 1682 static void 1683 sk_tick(xsc_if) 1684 void *xsc_if; 1685 { 1686 struct sk_if_softc *sc_if; 1687 struct mii_data *mii; 1688 struct ifnet *ifp; 1689 int i; 1690 1691 sc_if = xsc_if; 1692 SK_IF_LOCK(sc_if); 1693 ifp = &sc_if->arpcom.ac_if; 1694 mii = device_get_softc(sc_if->sk_miibus); 1695 1696 if (!(ifp->if_flags & IFF_UP)) { 1697 SK_IF_UNLOCK(sc_if); 1698 return; 1699 } 1700 1701 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 1702 sk_intr_bcom(sc_if); 1703 SK_IF_UNLOCK(sc_if); 1704 return; 1705 } 1706 1707 /* 1708 * According to SysKonnect, the correct way to verify that 1709 * the link has come back up is to poll bit 0 of the GPIO 1710 * register three times. This pin has the signal from the 1711 * link_sync pin connected to it; if we read the same link 1712 * state 3 times in a row, we know the link is up. 1713 */ 1714 for (i = 0; i < 3; i++) { 1715 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 1716 break; 1717 } 1718 1719 if (i != 3) { 1720 sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz); 1721 SK_IF_UNLOCK(sc_if); 1722 return; 1723 } 1724 1725 /* Turn the GP0 interrupt back on. */ 1726 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 1727 SK_XM_READ_2(sc_if, XM_ISR); 1728 mii_tick(mii); 1729 untimeout(sk_tick, sc_if, sc_if->sk_tick_ch); 1730 1731 SK_IF_UNLOCK(sc_if); 1732 return; 1733 } 1734 1735 static void 1736 sk_intr_bcom(sc_if) 1737 struct sk_if_softc *sc_if; 1738 { 1739 struct sk_softc *sc; 1740 struct mii_data *mii; 1741 struct ifnet *ifp; 1742 int status; 1743 1744 sc = sc_if->sk_softc; 1745 mii = device_get_softc(sc_if->sk_miibus); 1746 ifp = &sc_if->arpcom.ac_if; 1747 1748 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 1749 1750 /* 1751 * Read the PHY interrupt register to make sure 1752 * we clear any pending interrupts. 1753 */ 1754 status = sk_miibus_readreg(sc_if->sk_dev, 1755 SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 1756 1757 if (!(ifp->if_flags & IFF_RUNNING)) { 1758 sk_init_xmac(sc_if); 1759 return; 1760 } 1761 1762 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 1763 int lstat; 1764 lstat = sk_miibus_readreg(sc_if->sk_dev, 1765 SK_PHYADDR_BCOM, BRGPHY_MII_AUXSTS); 1766 1767 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 1768 mii_mediachg(mii); 1769 /* Turn off the link LED. */ 1770 SK_IF_WRITE_1(sc_if, 0, 1771 SK_LINKLED1_CTL, SK_LINKLED_OFF); 1772 sc_if->sk_link = 0; 1773 } else if (status & BRGPHY_ISR_LNK_CHG) { 1774 sk_miibus_writereg(sc_if->sk_dev, SK_PHYADDR_BCOM, 1775 BRGPHY_MII_IMR, 0xFF00); 1776 mii_tick(mii); 1777 sc_if->sk_link = 1; 1778 /* Turn on the link LED. */ 1779 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 1780 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 1781 SK_LINKLED_BLINK_OFF); 1782 } else { 1783 mii_tick(mii); 1784 sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz); 1785 } 1786 } 1787 1788 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 1789 1790 return; 1791 } 1792 1793 static void 1794 sk_intr_xmac(sc_if) 1795 struct sk_if_softc *sc_if; 1796 { 1797 struct sk_softc *sc; 1798 u_int16_t status; 1799 struct mii_data *mii; 1800 1801 sc = sc_if->sk_softc; 1802 mii = device_get_softc(sc_if->sk_miibus); 1803 status = SK_XM_READ_2(sc_if, XM_ISR); 1804 1805 /* 1806 * Link has gone down. Start MII tick timeout to 1807 * watch for link resync. 1808 */ 1809 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 1810 if (status & XM_ISR_GP0_SET) { 1811 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 1812 sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz); 1813 } 1814 1815 if (status & XM_ISR_AUTONEG_DONE) { 1816 sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz); 1817 } 1818 } 1819 1820 if (status & XM_IMR_TX_UNDERRUN) 1821 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 1822 1823 if (status & XM_IMR_RX_OVERRUN) 1824 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 1825 1826 status = SK_XM_READ_2(sc_if, XM_ISR); 1827 1828 return; 1829 } 1830 1831 static void 1832 sk_intr(xsc) 1833 void *xsc; 1834 { 1835 struct sk_softc *sc = xsc; 1836 struct sk_if_softc *sc_if0 = NULL, *sc_if1 = NULL; 1837 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 1838 u_int32_t status; 1839 1840 SK_LOCK(sc); 1841 1842 sc_if0 = sc->sk_if[SK_PORT_A]; 1843 sc_if1 = sc->sk_if[SK_PORT_B]; 1844 1845 if (sc_if0 != NULL) 1846 ifp0 = &sc_if0->arpcom.ac_if; 1847 if (sc_if1 != NULL) 1848 ifp1 = &sc_if1->arpcom.ac_if; 1849 1850 for (;;) { 1851 status = CSR_READ_4(sc, SK_ISSR); 1852 if (!(status & sc->sk_intrmask)) 1853 break; 1854 1855 /* Handle receive interrupts first. */ 1856 if (status & SK_ISR_RX1_EOF) { 1857 sk_rxeof(sc_if0); 1858 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 1859 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 1860 } 1861 if (status & SK_ISR_RX2_EOF) { 1862 sk_rxeof(sc_if1); 1863 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 1864 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 1865 } 1866 1867 /* Then transmit interrupts. */ 1868 if (status & SK_ISR_TX1_S_EOF) { 1869 sk_txeof(sc_if0); 1870 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 1871 SK_TXBMU_CLR_IRQ_EOF); 1872 } 1873 if (status & SK_ISR_TX2_S_EOF) { 1874 sk_txeof(sc_if1); 1875 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 1876 SK_TXBMU_CLR_IRQ_EOF); 1877 } 1878 1879 /* Then MAC interrupts. */ 1880 if (status & SK_ISR_MAC1 && 1881 ifp0->if_flags & IFF_RUNNING) 1882 sk_intr_xmac(sc_if0); 1883 1884 if (status & SK_ISR_MAC2 && 1885 ifp1->if_flags & IFF_RUNNING) 1886 sk_intr_xmac(sc_if1); 1887 1888 if (status & SK_ISR_EXTERNAL_REG) { 1889 if (ifp0 != NULL) 1890 sk_intr_bcom(sc_if0); 1891 if (ifp1 != NULL) 1892 sk_intr_bcom(sc_if1); 1893 } 1894 } 1895 1896 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 1897 1898 if (ifp0 != NULL && ifp0->if_snd.ifq_head != NULL) 1899 sk_start(ifp0); 1900 if (ifp1 != NULL && ifp1->if_snd.ifq_head != NULL) 1901 sk_start(ifp1); 1902 1903 SK_UNLOCK(sc); 1904 1905 return; 1906 } 1907 1908 static void 1909 sk_init_xmac(sc_if) 1910 struct sk_if_softc *sc_if; 1911 { 1912 struct sk_softc *sc; 1913 struct ifnet *ifp; 1914 struct sk_bcom_hack bhack[] = { 1915 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 1916 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 1917 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 1918 { 0, 0 } }; 1919 1920 sc = sc_if->sk_softc; 1921 ifp = &sc_if->arpcom.ac_if; 1922 1923 /* Unreset the XMAC. */ 1924 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 1925 DELAY(1000); 1926 1927 /* Reset the XMAC's internal state. */ 1928 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 1929 1930 /* Save the XMAC II revision */ 1931 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 1932 1933 /* 1934 * Perform additional initialization for external PHYs, 1935 * namely for the 1000baseTX cards that use the XMAC's 1936 * GMII mode. 1937 */ 1938 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 1939 int i = 0; 1940 u_int32_t val; 1941 1942 /* Take PHY out of reset. */ 1943 val = sk_win_read_4(sc, SK_GPIO); 1944 if (sc_if->sk_port == SK_PORT_A) 1945 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 1946 else 1947 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 1948 sk_win_write_4(sc, SK_GPIO, val); 1949 1950 /* Enable GMII mode on the XMAC. */ 1951 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 1952 1953 sk_miibus_writereg(sc_if->sk_dev, SK_PHYADDR_BCOM, 1954 BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET); 1955 DELAY(10000); 1956 sk_miibus_writereg(sc_if->sk_dev, SK_PHYADDR_BCOM, 1957 BRGPHY_MII_IMR, 0xFFF0); 1958 1959 /* 1960 * Early versions of the BCM5400 apparently have 1961 * a bug that requires them to have their reserved 1962 * registers initialized to some magic values. I don't 1963 * know what the numbers do, I'm just the messenger. 1964 */ 1965 if (sk_miibus_readreg(sc_if->sk_dev, 1966 SK_PHYADDR_BCOM, 0x03) == 0x6041) { 1967 while(bhack[i].reg) { 1968 sk_miibus_writereg(sc_if->sk_dev, 1969 SK_PHYADDR_BCOM, bhack[i].reg, 1970 bhack[i].val); 1971 i++; 1972 } 1973 } 1974 } 1975 1976 /* Set station address */ 1977 SK_XM_WRITE_2(sc_if, XM_PAR0, 1978 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[0])); 1979 SK_XM_WRITE_2(sc_if, XM_PAR1, 1980 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[2])); 1981 SK_XM_WRITE_2(sc_if, XM_PAR2, 1982 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[4])); 1983 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 1984 1985 if (ifp->if_flags & IFF_PROMISC) { 1986 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 1987 } else { 1988 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 1989 } 1990 1991 if (ifp->if_flags & IFF_BROADCAST) { 1992 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 1993 } else { 1994 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 1995 } 1996 1997 /* We don't need the FCS appended to the packet. */ 1998 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 1999 2000 /* We want short frames padded to 60 bytes. */ 2001 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 2002 2003 /* 2004 * Enable the reception of all error frames. This is is 2005 * a necessary evil due to the design of the XMAC. The 2006 * XMAC's receive FIFO is only 8K in size, however jumbo 2007 * frames can be up to 9000 bytes in length. When bad 2008 * frame filtering is enabled, the XMAC's RX FIFO operates 2009 * in 'store and forward' mode. For this to work, the 2010 * entire frame has to fit into the FIFO, but that means 2011 * that jumbo frames larger than 8192 bytes will be 2012 * truncated. Disabling all bad frame filtering causes 2013 * the RX FIFO to operate in streaming mode, in which 2014 * case the XMAC will start transfering frames out of the 2015 * RX FIFO as soon as the FIFO threshold is reached. 2016 */ 2017 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 2018 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 2019 XM_MODE_RX_INRANGELEN); 2020 2021 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2022 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2023 else 2024 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2025 2026 /* 2027 * Bump up the transmit threshold. This helps hold off transmit 2028 * underruns when we're blasting traffic from both ports at once. 2029 */ 2030 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2031 2032 /* Set multicast filter */ 2033 sk_setmulti(sc_if); 2034 2035 /* Clear and enable interrupts */ 2036 SK_XM_READ_2(sc_if, XM_ISR); 2037 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2038 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2039 else 2040 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2041 2042 /* Configure MAC arbiter */ 2043 switch(sc_if->sk_xmac_rev) { 2044 case XM_XMAC_REV_B2: 2045 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2046 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2047 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2048 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2049 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2050 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2051 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2052 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2053 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2054 break; 2055 case XM_XMAC_REV_C1: 2056 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2057 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2058 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2059 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2060 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2061 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2062 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2063 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2064 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2065 break; 2066 default: 2067 break; 2068 } 2069 sk_win_write_2(sc, SK_MACARB_CTL, 2070 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 2071 2072 sc_if->sk_link = 1; 2073 2074 return; 2075 } 2076 2077 /* 2078 * Note that to properly initialize any part of the GEnesis chip, 2079 * you first have to take it out of reset mode. 2080 */ 2081 static void 2082 sk_init(xsc) 2083 void *xsc; 2084 { 2085 struct sk_if_softc *sc_if = xsc; 2086 struct sk_softc *sc; 2087 struct ifnet *ifp; 2088 struct mii_data *mii; 2089 2090 SK_IF_LOCK(sc_if); 2091 2092 ifp = &sc_if->arpcom.ac_if; 2093 sc = sc_if->sk_softc; 2094 mii = device_get_softc(sc_if->sk_miibus); 2095 2096 /* Cancel pending I/O and free all RX/TX buffers. */ 2097 sk_stop(sc_if); 2098 2099 /* Configure LINK_SYNC LED */ 2100 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2101 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_ON); 2102 2103 /* Configure RX LED */ 2104 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_START); 2105 2106 /* Configure TX LED */ 2107 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_TXLEDCTL_COUNTER_START); 2108 2109 /* Configure I2C registers */ 2110 2111 /* Configure XMAC(s) */ 2112 sk_init_xmac(sc_if); 2113 mii_mediachg(mii); 2114 2115 /* Configure MAC FIFOs */ 2116 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2117 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2118 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2119 2120 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2121 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2122 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2123 2124 /* Configure transmit arbiter(s) */ 2125 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2126 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2127 2128 /* Configure RAMbuffers */ 2129 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2130 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2131 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2132 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2133 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2134 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2135 2136 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2137 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2138 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2139 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2140 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2141 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2142 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2143 2144 /* Configure BMUs */ 2145 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2146 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2147 vtophys(&sc_if->sk_rdata->sk_rx_ring[0])); 2148 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2149 2150 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2151 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2152 vtophys(&sc_if->sk_rdata->sk_tx_ring[0])); 2153 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2154 2155 /* Init descriptors */ 2156 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2157 printf("sk%d: initialization failed: no " 2158 "memory for rx buffers\n", sc_if->sk_unit); 2159 sk_stop(sc_if); 2160 SK_IF_UNLOCK(sc_if); 2161 return; 2162 } 2163 sk_init_tx_ring(sc_if); 2164 2165 /* Configure interrupt handling */ 2166 CSR_READ_4(sc, SK_ISSR); 2167 if (sc_if->sk_port == SK_PORT_A) 2168 sc->sk_intrmask |= SK_INTRS1; 2169 else 2170 sc->sk_intrmask |= SK_INTRS2; 2171 2172 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2173 2174 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2175 2176 /* Start BMUs. */ 2177 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2178 2179 /* Enable XMACs TX and RX state machines */ 2180 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2181 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2182 2183 ifp->if_flags |= IFF_RUNNING; 2184 ifp->if_flags &= ~IFF_OACTIVE; 2185 2186 SK_IF_UNLOCK(sc_if); 2187 2188 return; 2189 } 2190 2191 static void 2192 sk_stop(sc_if) 2193 struct sk_if_softc *sc_if; 2194 { 2195 int i; 2196 struct sk_softc *sc; 2197 struct ifnet *ifp; 2198 2199 SK_IF_LOCK(sc_if); 2200 sc = sc_if->sk_softc; 2201 ifp = &sc_if->arpcom.ac_if; 2202 2203 untimeout(sk_tick, sc_if, sc_if->sk_tick_ch); 2204 2205 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2206 u_int32_t val; 2207 2208 /* Put PHY back into reset. */ 2209 val = sk_win_read_4(sc, SK_GPIO); 2210 if (sc_if->sk_port == SK_PORT_A) { 2211 val |= SK_GPIO_DIR0; 2212 val &= ~SK_GPIO_DAT0; 2213 } else { 2214 val |= SK_GPIO_DIR2; 2215 val &= ~SK_GPIO_DAT2; 2216 } 2217 sk_win_write_4(sc, SK_GPIO, val); 2218 } 2219 2220 /* Turn off various components of this interface. */ 2221 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2222 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_RESET); 2223 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2224 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2225 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2226 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2227 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2228 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2229 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2230 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2231 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2232 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2233 2234 /* Disable interrupts */ 2235 if (sc_if->sk_port == SK_PORT_A) 2236 sc->sk_intrmask &= ~SK_INTRS1; 2237 else 2238 sc->sk_intrmask &= ~SK_INTRS2; 2239 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2240 2241 SK_XM_READ_2(sc_if, XM_ISR); 2242 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2243 2244 /* Free RX and TX mbufs still in the queues. */ 2245 for (i = 0; i < SK_RX_RING_CNT; i++) { 2246 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2247 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2248 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2249 } 2250 } 2251 2252 for (i = 0; i < SK_TX_RING_CNT; i++) { 2253 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2254 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2255 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2256 } 2257 } 2258 2259 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2260 SK_IF_UNLOCK(sc_if); 2261 return; 2262 } 2263