1 /* $OpenBSD: if_sk.c,v 2.33 2003/08/12 05:23:06 nate Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999, 2000 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 /*- 35 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 36 * 37 * Permission to use, copy, modify, and distribute this software for any 38 * purpose with or without fee is hereby granted, provided that the above 39 * copyright notice and this permission notice appear in all copies. 40 * 41 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 42 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 43 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 44 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 45 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 46 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 47 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 48 */ 49 50 #include <sys/cdefs.h> 51 __FBSDID("$FreeBSD$"); 52 53 /* 54 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 55 * the SK-984x series adapters, both single port and dual port. 56 * References: 57 * The XaQti XMAC II datasheet, 58 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 59 * The SysKonnect GEnesis manual, http://www.syskonnect.com 60 * 61 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the 62 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 63 * convenience to others until Vitesse corrects this problem: 64 * 65 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 66 * 67 * Written by Bill Paul <wpaul@ee.columbia.edu> 68 * Department of Electrical Engineering 69 * Columbia University, New York City 70 */ 71 /* 72 * The SysKonnect gigabit ethernet adapters consist of two main 73 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 74 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 75 * components and a PHY while the GEnesis controller provides a PCI 76 * interface with DMA support. Each card may have between 512K and 77 * 2MB of SRAM on board depending on the configuration. 78 * 79 * The SysKonnect GEnesis controller can have either one or two XMAC 80 * chips connected to it, allowing single or dual port NIC configurations. 81 * SysKonnect has the distinction of being the only vendor on the market 82 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 83 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 84 * XMAC registers. This driver takes advantage of these features to allow 85 * both XMACs to operate as independent interfaces. 86 */ 87 88 #include <sys/param.h> 89 #include <sys/systm.h> 90 #include <sys/bus.h> 91 #include <sys/endian.h> 92 #include <sys/mbuf.h> 93 #include <sys/malloc.h> 94 #include <sys/kernel.h> 95 #include <sys/module.h> 96 #include <sys/socket.h> 97 #include <sys/sockio.h> 98 #include <sys/queue.h> 99 #include <sys/sysctl.h> 100 101 #include <net/bpf.h> 102 #include <net/ethernet.h> 103 #include <net/if.h> 104 #include <net/if_var.h> 105 #include <net/if_arp.h> 106 #include <net/if_dl.h> 107 #include <net/if_media.h> 108 #include <net/if_types.h> 109 #include <net/if_vlan_var.h> 110 111 #include <netinet/in.h> 112 #include <netinet/in_systm.h> 113 #include <netinet/ip.h> 114 115 #include <machine/bus.h> 116 #include <machine/in_cksum.h> 117 #include <machine/resource.h> 118 #include <sys/rman.h> 119 120 #include <dev/mii/mii.h> 121 #include <dev/mii/miivar.h> 122 #include <dev/mii/brgphyreg.h> 123 124 #include <dev/pci/pcireg.h> 125 #include <dev/pci/pcivar.h> 126 127 #if 0 128 #define SK_USEIOSPACE 129 #endif 130 131 #include <dev/sk/if_skreg.h> 132 #include <dev/sk/xmaciireg.h> 133 #include <dev/sk/yukonreg.h> 134 135 MODULE_DEPEND(sk, pci, 1, 1, 1); 136 MODULE_DEPEND(sk, ether, 1, 1, 1); 137 MODULE_DEPEND(sk, miibus, 1, 1, 1); 138 139 /* "device miibus" required. See GENERIC if you get errors here. */ 140 #include "miibus_if.h" 141 142 static const struct sk_type sk_devs[] = { 143 { 144 VENDORID_SK, 145 DEVICEID_SK_V1, 146 "SysKonnect Gigabit Ethernet (V1.0)" 147 }, 148 { 149 VENDORID_SK, 150 DEVICEID_SK_V2, 151 "SysKonnect Gigabit Ethernet (V2.0)" 152 }, 153 { 154 VENDORID_MARVELL, 155 DEVICEID_SK_V2, 156 "Marvell Gigabit Ethernet" 157 }, 158 { 159 VENDORID_MARVELL, 160 DEVICEID_BELKIN_5005, 161 "Belkin F5D5005 Gigabit Ethernet" 162 }, 163 { 164 VENDORID_3COM, 165 DEVICEID_3COM_3C940, 166 "3Com 3C940 Gigabit Ethernet" 167 }, 168 { 169 VENDORID_LINKSYS, 170 DEVICEID_LINKSYS_EG1032, 171 "Linksys EG1032 Gigabit Ethernet" 172 }, 173 { 174 VENDORID_DLINK, 175 DEVICEID_DLINK_DGE530T_A1, 176 "D-Link DGE-530T Gigabit Ethernet" 177 }, 178 { 179 VENDORID_DLINK, 180 DEVICEID_DLINK_DGE530T_B1, 181 "D-Link DGE-530T Gigabit Ethernet" 182 }, 183 { 0, 0, NULL } 184 }; 185 186 static int skc_probe(device_t); 187 static int skc_attach(device_t); 188 static int skc_detach(device_t); 189 static int skc_shutdown(device_t); 190 static int skc_suspend(device_t); 191 static int skc_resume(device_t); 192 static bus_dma_tag_t skc_get_dma_tag(device_t, device_t); 193 static int sk_detach(device_t); 194 static int sk_probe(device_t); 195 static int sk_attach(device_t); 196 static void sk_tick(void *); 197 static void sk_yukon_tick(void *); 198 static void sk_intr(void *); 199 static void sk_intr_xmac(struct sk_if_softc *); 200 static void sk_intr_bcom(struct sk_if_softc *); 201 static void sk_intr_yukon(struct sk_if_softc *); 202 static __inline void sk_rxcksum(struct ifnet *, struct mbuf *, u_int32_t); 203 static __inline int sk_rxvalid(struct sk_softc *, u_int32_t, u_int32_t); 204 static void sk_rxeof(struct sk_if_softc *); 205 static void sk_jumbo_rxeof(struct sk_if_softc *); 206 static void sk_txeof(struct sk_if_softc *); 207 static void sk_txcksum(struct ifnet *, struct mbuf *, struct sk_tx_desc *); 208 static int sk_encap(struct sk_if_softc *, struct mbuf **); 209 static void sk_start(struct ifnet *); 210 static void sk_start_locked(struct ifnet *); 211 static int sk_ioctl(struct ifnet *, u_long, caddr_t); 212 static void sk_init(void *); 213 static void sk_init_locked(struct sk_if_softc *); 214 static void sk_init_xmac(struct sk_if_softc *); 215 static void sk_init_yukon(struct sk_if_softc *); 216 static void sk_stop(struct sk_if_softc *); 217 static void sk_watchdog(void *); 218 static int sk_ifmedia_upd(struct ifnet *); 219 static void sk_ifmedia_sts(struct ifnet *, struct ifmediareq *); 220 static void sk_reset(struct sk_softc *); 221 static __inline void sk_discard_rxbuf(struct sk_if_softc *, int); 222 static __inline void sk_discard_jumbo_rxbuf(struct sk_if_softc *, int); 223 static int sk_newbuf(struct sk_if_softc *, int); 224 static int sk_jumbo_newbuf(struct sk_if_softc *, int); 225 static void sk_dmamap_cb(void *, bus_dma_segment_t *, int, int); 226 static int sk_dma_alloc(struct sk_if_softc *); 227 static int sk_dma_jumbo_alloc(struct sk_if_softc *); 228 static void sk_dma_free(struct sk_if_softc *); 229 static void sk_dma_jumbo_free(struct sk_if_softc *); 230 static int sk_init_rx_ring(struct sk_if_softc *); 231 static int sk_init_jumbo_rx_ring(struct sk_if_softc *); 232 static void sk_init_tx_ring(struct sk_if_softc *); 233 static u_int32_t sk_win_read_4(struct sk_softc *, int); 234 static u_int16_t sk_win_read_2(struct sk_softc *, int); 235 static u_int8_t sk_win_read_1(struct sk_softc *, int); 236 static void sk_win_write_4(struct sk_softc *, int, u_int32_t); 237 static void sk_win_write_2(struct sk_softc *, int, u_int32_t); 238 static void sk_win_write_1(struct sk_softc *, int, u_int32_t); 239 240 static int sk_miibus_readreg(device_t, int, int); 241 static int sk_miibus_writereg(device_t, int, int, int); 242 static void sk_miibus_statchg(device_t); 243 244 static int sk_xmac_miibus_readreg(struct sk_if_softc *, int, int); 245 static int sk_xmac_miibus_writereg(struct sk_if_softc *, int, int, 246 int); 247 static void sk_xmac_miibus_statchg(struct sk_if_softc *); 248 249 static int sk_marv_miibus_readreg(struct sk_if_softc *, int, int); 250 static int sk_marv_miibus_writereg(struct sk_if_softc *, int, int, 251 int); 252 static void sk_marv_miibus_statchg(struct sk_if_softc *); 253 254 static uint32_t sk_xmchash(const uint8_t *); 255 static void sk_setfilt(struct sk_if_softc *, u_int16_t *, int); 256 static void sk_rxfilter(struct sk_if_softc *); 257 static void sk_rxfilter_genesis(struct sk_if_softc *); 258 static void sk_rxfilter_yukon(struct sk_if_softc *); 259 260 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high); 261 static int sysctl_hw_sk_int_mod(SYSCTL_HANDLER_ARGS); 262 263 /* Tunables. */ 264 static int jumbo_disable = 0; 265 TUNABLE_INT("hw.skc.jumbo_disable", &jumbo_disable); 266 267 /* 268 * It seems that SK-NET GENESIS supports very simple checksum offload 269 * capability for Tx and I believe it can generate 0 checksum value for 270 * UDP packets in Tx as the hardware can't differenciate UDP packets from 271 * TCP packets. 0 chcecksum value for UDP packet is an invalid one as it 272 * means sender didn't perforam checksum computation. For the safety I 273 * disabled UDP checksum offload capability at the moment. Alternatively 274 * we can intrduce a LINK0/LINK1 flag as hme(4) did in its Tx checksum 275 * offload routine. 276 */ 277 #define SK_CSUM_FEATURES (CSUM_TCP) 278 279 /* 280 * Note that we have newbus methods for both the GEnesis controller 281 * itself and the XMAC(s). The XMACs are children of the GEnesis, and 282 * the miibus code is a child of the XMACs. We need to do it this way 283 * so that the miibus drivers can access the PHY registers on the 284 * right PHY. It's not quite what I had in mind, but it's the only 285 * design that achieves the desired effect. 286 */ 287 static device_method_t skc_methods[] = { 288 /* Device interface */ 289 DEVMETHOD(device_probe, skc_probe), 290 DEVMETHOD(device_attach, skc_attach), 291 DEVMETHOD(device_detach, skc_detach), 292 DEVMETHOD(device_suspend, skc_suspend), 293 DEVMETHOD(device_resume, skc_resume), 294 DEVMETHOD(device_shutdown, skc_shutdown), 295 296 DEVMETHOD(bus_get_dma_tag, skc_get_dma_tag), 297 298 DEVMETHOD_END 299 }; 300 301 static driver_t skc_driver = { 302 "skc", 303 skc_methods, 304 sizeof(struct sk_softc) 305 }; 306 307 static devclass_t skc_devclass; 308 309 static device_method_t sk_methods[] = { 310 /* Device interface */ 311 DEVMETHOD(device_probe, sk_probe), 312 DEVMETHOD(device_attach, sk_attach), 313 DEVMETHOD(device_detach, sk_detach), 314 DEVMETHOD(device_shutdown, bus_generic_shutdown), 315 316 /* MII interface */ 317 DEVMETHOD(miibus_readreg, sk_miibus_readreg), 318 DEVMETHOD(miibus_writereg, sk_miibus_writereg), 319 DEVMETHOD(miibus_statchg, sk_miibus_statchg), 320 321 DEVMETHOD_END 322 }; 323 324 static driver_t sk_driver = { 325 "sk", 326 sk_methods, 327 sizeof(struct sk_if_softc) 328 }; 329 330 static devclass_t sk_devclass; 331 332 DRIVER_MODULE(skc, pci, skc_driver, skc_devclass, NULL, NULL); 333 DRIVER_MODULE(sk, skc, sk_driver, sk_devclass, NULL, NULL); 334 DRIVER_MODULE(miibus, sk, miibus_driver, miibus_devclass, NULL, NULL); 335 336 static struct resource_spec sk_res_spec_io[] = { 337 { SYS_RES_IOPORT, PCIR_BAR(1), RF_ACTIVE }, 338 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 339 { -1, 0, 0 } 340 }; 341 342 static struct resource_spec sk_res_spec_mem[] = { 343 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 344 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 345 { -1, 0, 0 } 346 }; 347 348 #define SK_SETBIT(sc, reg, x) \ 349 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 350 351 #define SK_CLRBIT(sc, reg, x) \ 352 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 353 354 #define SK_WIN_SETBIT_4(sc, reg, x) \ 355 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x) 356 357 #define SK_WIN_CLRBIT_4(sc, reg, x) \ 358 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x) 359 360 #define SK_WIN_SETBIT_2(sc, reg, x) \ 361 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x) 362 363 #define SK_WIN_CLRBIT_2(sc, reg, x) \ 364 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x) 365 366 static u_int32_t 367 sk_win_read_4(sc, reg) 368 struct sk_softc *sc; 369 int reg; 370 { 371 #ifdef SK_USEIOSPACE 372 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 373 return(CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg))); 374 #else 375 return(CSR_READ_4(sc, reg)); 376 #endif 377 } 378 379 static u_int16_t 380 sk_win_read_2(sc, reg) 381 struct sk_softc *sc; 382 int reg; 383 { 384 #ifdef SK_USEIOSPACE 385 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 386 return(CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg))); 387 #else 388 return(CSR_READ_2(sc, reg)); 389 #endif 390 } 391 392 static u_int8_t 393 sk_win_read_1(sc, reg) 394 struct sk_softc *sc; 395 int reg; 396 { 397 #ifdef SK_USEIOSPACE 398 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 399 return(CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg))); 400 #else 401 return(CSR_READ_1(sc, reg)); 402 #endif 403 } 404 405 static void 406 sk_win_write_4(sc, reg, val) 407 struct sk_softc *sc; 408 int reg; 409 u_int32_t val; 410 { 411 #ifdef SK_USEIOSPACE 412 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 413 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), val); 414 #else 415 CSR_WRITE_4(sc, reg, val); 416 #endif 417 return; 418 } 419 420 static void 421 sk_win_write_2(sc, reg, val) 422 struct sk_softc *sc; 423 int reg; 424 u_int32_t val; 425 { 426 #ifdef SK_USEIOSPACE 427 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 428 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), val); 429 #else 430 CSR_WRITE_2(sc, reg, val); 431 #endif 432 return; 433 } 434 435 static void 436 sk_win_write_1(sc, reg, val) 437 struct sk_softc *sc; 438 int reg; 439 u_int32_t val; 440 { 441 #ifdef SK_USEIOSPACE 442 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 443 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), val); 444 #else 445 CSR_WRITE_1(sc, reg, val); 446 #endif 447 return; 448 } 449 450 static int 451 sk_miibus_readreg(dev, phy, reg) 452 device_t dev; 453 int phy, reg; 454 { 455 struct sk_if_softc *sc_if; 456 int v; 457 458 sc_if = device_get_softc(dev); 459 460 SK_IF_MII_LOCK(sc_if); 461 switch(sc_if->sk_softc->sk_type) { 462 case SK_GENESIS: 463 v = sk_xmac_miibus_readreg(sc_if, phy, reg); 464 break; 465 case SK_YUKON: 466 case SK_YUKON_LITE: 467 case SK_YUKON_LP: 468 v = sk_marv_miibus_readreg(sc_if, phy, reg); 469 break; 470 default: 471 v = 0; 472 break; 473 } 474 SK_IF_MII_UNLOCK(sc_if); 475 476 return (v); 477 } 478 479 static int 480 sk_miibus_writereg(dev, phy, reg, val) 481 device_t dev; 482 int phy, reg, val; 483 { 484 struct sk_if_softc *sc_if; 485 int v; 486 487 sc_if = device_get_softc(dev); 488 489 SK_IF_MII_LOCK(sc_if); 490 switch(sc_if->sk_softc->sk_type) { 491 case SK_GENESIS: 492 v = sk_xmac_miibus_writereg(sc_if, phy, reg, val); 493 break; 494 case SK_YUKON: 495 case SK_YUKON_LITE: 496 case SK_YUKON_LP: 497 v = sk_marv_miibus_writereg(sc_if, phy, reg, val); 498 break; 499 default: 500 v = 0; 501 break; 502 } 503 SK_IF_MII_UNLOCK(sc_if); 504 505 return (v); 506 } 507 508 static void 509 sk_miibus_statchg(dev) 510 device_t dev; 511 { 512 struct sk_if_softc *sc_if; 513 514 sc_if = device_get_softc(dev); 515 516 SK_IF_MII_LOCK(sc_if); 517 switch(sc_if->sk_softc->sk_type) { 518 case SK_GENESIS: 519 sk_xmac_miibus_statchg(sc_if); 520 break; 521 case SK_YUKON: 522 case SK_YUKON_LITE: 523 case SK_YUKON_LP: 524 sk_marv_miibus_statchg(sc_if); 525 break; 526 } 527 SK_IF_MII_UNLOCK(sc_if); 528 529 return; 530 } 531 532 static int 533 sk_xmac_miibus_readreg(sc_if, phy, reg) 534 struct sk_if_softc *sc_if; 535 int phy, reg; 536 { 537 int i; 538 539 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 540 SK_XM_READ_2(sc_if, XM_PHY_DATA); 541 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 542 for (i = 0; i < SK_TIMEOUT; i++) { 543 DELAY(1); 544 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 545 XM_MMUCMD_PHYDATARDY) 546 break; 547 } 548 549 if (i == SK_TIMEOUT) { 550 if_printf(sc_if->sk_ifp, "phy failed to come ready\n"); 551 return(0); 552 } 553 } 554 DELAY(1); 555 i = SK_XM_READ_2(sc_if, XM_PHY_DATA); 556 557 return(i); 558 } 559 560 static int 561 sk_xmac_miibus_writereg(sc_if, phy, reg, val) 562 struct sk_if_softc *sc_if; 563 int phy, reg, val; 564 { 565 int i; 566 567 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 568 for (i = 0; i < SK_TIMEOUT; i++) { 569 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 570 break; 571 } 572 573 if (i == SK_TIMEOUT) { 574 if_printf(sc_if->sk_ifp, "phy failed to come ready\n"); 575 return (ETIMEDOUT); 576 } 577 578 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 579 for (i = 0; i < SK_TIMEOUT; i++) { 580 DELAY(1); 581 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 582 break; 583 } 584 if (i == SK_TIMEOUT) 585 if_printf(sc_if->sk_ifp, "phy write timed out\n"); 586 587 return(0); 588 } 589 590 static void 591 sk_xmac_miibus_statchg(sc_if) 592 struct sk_if_softc *sc_if; 593 { 594 struct mii_data *mii; 595 596 mii = device_get_softc(sc_if->sk_miibus); 597 598 /* 599 * If this is a GMII PHY, manually set the XMAC's 600 * duplex mode accordingly. 601 */ 602 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 603 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 604 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 605 } else { 606 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 607 } 608 } 609 } 610 611 static int 612 sk_marv_miibus_readreg(sc_if, phy, reg) 613 struct sk_if_softc *sc_if; 614 int phy, reg; 615 { 616 u_int16_t val; 617 int i; 618 619 if (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 620 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER) { 621 return(0); 622 } 623 624 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 625 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 626 627 for (i = 0; i < SK_TIMEOUT; i++) { 628 DELAY(1); 629 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 630 if (val & YU_SMICR_READ_VALID) 631 break; 632 } 633 634 if (i == SK_TIMEOUT) { 635 if_printf(sc_if->sk_ifp, "phy failed to come ready\n"); 636 return(0); 637 } 638 639 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 640 641 return(val); 642 } 643 644 static int 645 sk_marv_miibus_writereg(sc_if, phy, reg, val) 646 struct sk_if_softc *sc_if; 647 int phy, reg, val; 648 { 649 int i; 650 651 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 652 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 653 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 654 655 for (i = 0; i < SK_TIMEOUT; i++) { 656 DELAY(1); 657 if ((SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY) == 0) 658 break; 659 } 660 if (i == SK_TIMEOUT) 661 if_printf(sc_if->sk_ifp, "phy write timeout\n"); 662 663 return(0); 664 } 665 666 static void 667 sk_marv_miibus_statchg(sc_if) 668 struct sk_if_softc *sc_if; 669 { 670 return; 671 } 672 673 #define HASH_BITS 6 674 675 static u_int32_t 676 sk_xmchash(addr) 677 const uint8_t *addr; 678 { 679 uint32_t crc; 680 681 /* Compute CRC for the address value. */ 682 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 683 684 return (~crc & ((1 << HASH_BITS) - 1)); 685 } 686 687 static void 688 sk_setfilt(sc_if, addr, slot) 689 struct sk_if_softc *sc_if; 690 u_int16_t *addr; 691 int slot; 692 { 693 int base; 694 695 base = XM_RXFILT_ENTRY(slot); 696 697 SK_XM_WRITE_2(sc_if, base, addr[0]); 698 SK_XM_WRITE_2(sc_if, base + 2, addr[1]); 699 SK_XM_WRITE_2(sc_if, base + 4, addr[2]); 700 701 return; 702 } 703 704 static void 705 sk_rxfilter(sc_if) 706 struct sk_if_softc *sc_if; 707 { 708 struct sk_softc *sc; 709 710 SK_IF_LOCK_ASSERT(sc_if); 711 712 sc = sc_if->sk_softc; 713 if (sc->sk_type == SK_GENESIS) 714 sk_rxfilter_genesis(sc_if); 715 else 716 sk_rxfilter_yukon(sc_if); 717 } 718 719 static void 720 sk_rxfilter_genesis(sc_if) 721 struct sk_if_softc *sc_if; 722 { 723 struct ifnet *ifp = sc_if->sk_ifp; 724 u_int32_t hashes[2] = { 0, 0 }, mode; 725 int h = 0, i; 726 struct ifmultiaddr *ifma; 727 u_int16_t dummy[] = { 0, 0, 0 }; 728 u_int16_t maddr[(ETHER_ADDR_LEN+1)/2]; 729 730 SK_IF_LOCK_ASSERT(sc_if); 731 732 mode = SK_XM_READ_4(sc_if, XM_MODE); 733 mode &= ~(XM_MODE_RX_PROMISC | XM_MODE_RX_USE_HASH | 734 XM_MODE_RX_USE_PERFECT); 735 /* First, zot all the existing perfect filters. */ 736 for (i = 1; i < XM_RXFILT_MAX; i++) 737 sk_setfilt(sc_if, dummy, i); 738 739 /* Now program new ones. */ 740 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 741 if (ifp->if_flags & IFF_ALLMULTI) 742 mode |= XM_MODE_RX_USE_HASH; 743 if (ifp->if_flags & IFF_PROMISC) 744 mode |= XM_MODE_RX_PROMISC; 745 hashes[0] = 0xFFFFFFFF; 746 hashes[1] = 0xFFFFFFFF; 747 } else { 748 i = 1; 749 if_maddr_rlock(ifp); 750 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, 751 ifma_link) { 752 if (ifma->ifma_addr->sa_family != AF_LINK) 753 continue; 754 /* 755 * Program the first XM_RXFILT_MAX multicast groups 756 * into the perfect filter. 757 */ 758 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 759 maddr, ETHER_ADDR_LEN); 760 if (i < XM_RXFILT_MAX) { 761 sk_setfilt(sc_if, maddr, i); 762 mode |= XM_MODE_RX_USE_PERFECT; 763 i++; 764 continue; 765 } 766 h = sk_xmchash((const uint8_t *)maddr); 767 if (h < 32) 768 hashes[0] |= (1 << h); 769 else 770 hashes[1] |= (1 << (h - 32)); 771 mode |= XM_MODE_RX_USE_HASH; 772 } 773 if_maddr_runlock(ifp); 774 } 775 776 SK_XM_WRITE_4(sc_if, XM_MODE, mode); 777 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 778 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 779 } 780 781 static void 782 sk_rxfilter_yukon(sc_if) 783 struct sk_if_softc *sc_if; 784 { 785 struct ifnet *ifp; 786 u_int32_t crc, hashes[2] = { 0, 0 }, mode; 787 struct ifmultiaddr *ifma; 788 789 SK_IF_LOCK_ASSERT(sc_if); 790 791 ifp = sc_if->sk_ifp; 792 mode = SK_YU_READ_2(sc_if, YUKON_RCR); 793 if (ifp->if_flags & IFF_PROMISC) 794 mode &= ~(YU_RCR_UFLEN | YU_RCR_MUFLEN); 795 else if (ifp->if_flags & IFF_ALLMULTI) { 796 mode |= YU_RCR_UFLEN | YU_RCR_MUFLEN; 797 hashes[0] = 0xFFFFFFFF; 798 hashes[1] = 0xFFFFFFFF; 799 } else { 800 mode |= YU_RCR_UFLEN; 801 if_maddr_rlock(ifp); 802 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 803 if (ifma->ifma_addr->sa_family != AF_LINK) 804 continue; 805 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 806 ifma->ifma_addr), ETHER_ADDR_LEN); 807 /* Just want the 6 least significant bits. */ 808 crc &= 0x3f; 809 /* Set the corresponding bit in the hash table. */ 810 hashes[crc >> 5] |= 1 << (crc & 0x1f); 811 } 812 if_maddr_runlock(ifp); 813 if (hashes[0] != 0 || hashes[1] != 0) 814 mode |= YU_RCR_MUFLEN; 815 } 816 817 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 818 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 819 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 820 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 821 SK_YU_WRITE_2(sc_if, YUKON_RCR, mode); 822 } 823 824 static int 825 sk_init_rx_ring(sc_if) 826 struct sk_if_softc *sc_if; 827 { 828 struct sk_ring_data *rd; 829 bus_addr_t addr; 830 u_int32_t csum_start; 831 int i; 832 833 sc_if->sk_cdata.sk_rx_cons = 0; 834 835 csum_start = (ETHER_HDR_LEN + sizeof(struct ip)) << 16 | 836 ETHER_HDR_LEN; 837 rd = &sc_if->sk_rdata; 838 bzero(rd->sk_rx_ring, sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 839 for (i = 0; i < SK_RX_RING_CNT; i++) { 840 if (sk_newbuf(sc_if, i) != 0) 841 return (ENOBUFS); 842 if (i == (SK_RX_RING_CNT - 1)) 843 addr = SK_RX_RING_ADDR(sc_if, 0); 844 else 845 addr = SK_RX_RING_ADDR(sc_if, i + 1); 846 rd->sk_rx_ring[i].sk_next = htole32(SK_ADDR_LO(addr)); 847 rd->sk_rx_ring[i].sk_csum_start = htole32(csum_start); 848 } 849 850 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag, 851 sc_if->sk_cdata.sk_rx_ring_map, 852 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 853 854 return(0); 855 } 856 857 static int 858 sk_init_jumbo_rx_ring(sc_if) 859 struct sk_if_softc *sc_if; 860 { 861 struct sk_ring_data *rd; 862 bus_addr_t addr; 863 u_int32_t csum_start; 864 int i; 865 866 sc_if->sk_cdata.sk_jumbo_rx_cons = 0; 867 868 csum_start = ((ETHER_HDR_LEN + sizeof(struct ip)) << 16) | 869 ETHER_HDR_LEN; 870 rd = &sc_if->sk_rdata; 871 bzero(rd->sk_jumbo_rx_ring, 872 sizeof(struct sk_rx_desc) * SK_JUMBO_RX_RING_CNT); 873 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) { 874 if (sk_jumbo_newbuf(sc_if, i) != 0) 875 return (ENOBUFS); 876 if (i == (SK_JUMBO_RX_RING_CNT - 1)) 877 addr = SK_JUMBO_RX_RING_ADDR(sc_if, 0); 878 else 879 addr = SK_JUMBO_RX_RING_ADDR(sc_if, i + 1); 880 rd->sk_jumbo_rx_ring[i].sk_next = htole32(SK_ADDR_LO(addr)); 881 rd->sk_jumbo_rx_ring[i].sk_csum_start = htole32(csum_start); 882 } 883 884 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 885 sc_if->sk_cdata.sk_jumbo_rx_ring_map, 886 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 887 888 return (0); 889 } 890 891 static void 892 sk_init_tx_ring(sc_if) 893 struct sk_if_softc *sc_if; 894 { 895 struct sk_ring_data *rd; 896 struct sk_txdesc *txd; 897 bus_addr_t addr; 898 int i; 899 900 STAILQ_INIT(&sc_if->sk_cdata.sk_txfreeq); 901 STAILQ_INIT(&sc_if->sk_cdata.sk_txbusyq); 902 903 sc_if->sk_cdata.sk_tx_prod = 0; 904 sc_if->sk_cdata.sk_tx_cons = 0; 905 sc_if->sk_cdata.sk_tx_cnt = 0; 906 907 rd = &sc_if->sk_rdata; 908 bzero(rd->sk_tx_ring, sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 909 for (i = 0; i < SK_TX_RING_CNT; i++) { 910 if (i == (SK_TX_RING_CNT - 1)) 911 addr = SK_TX_RING_ADDR(sc_if, 0); 912 else 913 addr = SK_TX_RING_ADDR(sc_if, i + 1); 914 rd->sk_tx_ring[i].sk_next = htole32(SK_ADDR_LO(addr)); 915 txd = &sc_if->sk_cdata.sk_txdesc[i]; 916 STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txfreeq, txd, tx_q); 917 } 918 919 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag, 920 sc_if->sk_cdata.sk_tx_ring_map, 921 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 922 } 923 924 static __inline void 925 sk_discard_rxbuf(sc_if, idx) 926 struct sk_if_softc *sc_if; 927 int idx; 928 { 929 struct sk_rx_desc *r; 930 struct sk_rxdesc *rxd; 931 struct mbuf *m; 932 933 934 r = &sc_if->sk_rdata.sk_rx_ring[idx]; 935 rxd = &sc_if->sk_cdata.sk_rxdesc[idx]; 936 m = rxd->rx_m; 937 r->sk_ctl = htole32(m->m_len | SK_RXSTAT | SK_OPCODE_CSUM); 938 } 939 940 static __inline void 941 sk_discard_jumbo_rxbuf(sc_if, idx) 942 struct sk_if_softc *sc_if; 943 int idx; 944 { 945 struct sk_rx_desc *r; 946 struct sk_rxdesc *rxd; 947 struct mbuf *m; 948 949 r = &sc_if->sk_rdata.sk_jumbo_rx_ring[idx]; 950 rxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[idx]; 951 m = rxd->rx_m; 952 r->sk_ctl = htole32(m->m_len | SK_RXSTAT | SK_OPCODE_CSUM); 953 } 954 955 static int 956 sk_newbuf(sc_if, idx) 957 struct sk_if_softc *sc_if; 958 int idx; 959 { 960 struct sk_rx_desc *r; 961 struct sk_rxdesc *rxd; 962 struct mbuf *m; 963 bus_dma_segment_t segs[1]; 964 bus_dmamap_t map; 965 int nsegs; 966 967 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 968 if (m == NULL) 969 return (ENOBUFS); 970 m->m_len = m->m_pkthdr.len = MCLBYTES; 971 m_adj(m, ETHER_ALIGN); 972 973 if (bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_rx_tag, 974 sc_if->sk_cdata.sk_rx_sparemap, m, segs, &nsegs, 0) != 0) { 975 m_freem(m); 976 return (ENOBUFS); 977 } 978 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 979 980 rxd = &sc_if->sk_cdata.sk_rxdesc[idx]; 981 if (rxd->rx_m != NULL) { 982 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap, 983 BUS_DMASYNC_POSTREAD); 984 bus_dmamap_unload(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap); 985 } 986 map = rxd->rx_dmamap; 987 rxd->rx_dmamap = sc_if->sk_cdata.sk_rx_sparemap; 988 sc_if->sk_cdata.sk_rx_sparemap = map; 989 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap, 990 BUS_DMASYNC_PREREAD); 991 rxd->rx_m = m; 992 r = &sc_if->sk_rdata.sk_rx_ring[idx]; 993 r->sk_data_lo = htole32(SK_ADDR_LO(segs[0].ds_addr)); 994 r->sk_data_hi = htole32(SK_ADDR_HI(segs[0].ds_addr)); 995 r->sk_ctl = htole32(segs[0].ds_len | SK_RXSTAT | SK_OPCODE_CSUM); 996 997 return (0); 998 } 999 1000 static int 1001 sk_jumbo_newbuf(sc_if, idx) 1002 struct sk_if_softc *sc_if; 1003 int idx; 1004 { 1005 struct sk_rx_desc *r; 1006 struct sk_rxdesc *rxd; 1007 struct mbuf *m; 1008 bus_dma_segment_t segs[1]; 1009 bus_dmamap_t map; 1010 int nsegs; 1011 1012 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 1013 if (m == NULL) 1014 return (ENOBUFS); 1015 if ((m->m_flags & M_EXT) == 0) { 1016 m_freem(m); 1017 return (ENOBUFS); 1018 } 1019 m->m_pkthdr.len = m->m_len = MJUM9BYTES; 1020 /* 1021 * Adjust alignment so packet payload begins on a 1022 * longword boundary. Mandatory for Alpha, useful on 1023 * x86 too. 1024 */ 1025 m_adj(m, ETHER_ALIGN); 1026 1027 if (bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_jumbo_rx_tag, 1028 sc_if->sk_cdata.sk_jumbo_rx_sparemap, m, segs, &nsegs, 0) != 0) { 1029 m_freem(m); 1030 return (ENOBUFS); 1031 } 1032 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1033 1034 rxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[idx]; 1035 if (rxd->rx_m != NULL) { 1036 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag, rxd->rx_dmamap, 1037 BUS_DMASYNC_POSTREAD); 1038 bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_tag, 1039 rxd->rx_dmamap); 1040 } 1041 map = rxd->rx_dmamap; 1042 rxd->rx_dmamap = sc_if->sk_cdata.sk_jumbo_rx_sparemap; 1043 sc_if->sk_cdata.sk_jumbo_rx_sparemap = map; 1044 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag, rxd->rx_dmamap, 1045 BUS_DMASYNC_PREREAD); 1046 rxd->rx_m = m; 1047 r = &sc_if->sk_rdata.sk_jumbo_rx_ring[idx]; 1048 r->sk_data_lo = htole32(SK_ADDR_LO(segs[0].ds_addr)); 1049 r->sk_data_hi = htole32(SK_ADDR_HI(segs[0].ds_addr)); 1050 r->sk_ctl = htole32(segs[0].ds_len | SK_RXSTAT | SK_OPCODE_CSUM); 1051 1052 return (0); 1053 } 1054 1055 /* 1056 * Set media options. 1057 */ 1058 static int 1059 sk_ifmedia_upd(ifp) 1060 struct ifnet *ifp; 1061 { 1062 struct sk_if_softc *sc_if = ifp->if_softc; 1063 struct mii_data *mii; 1064 1065 mii = device_get_softc(sc_if->sk_miibus); 1066 sk_init(sc_if); 1067 mii_mediachg(mii); 1068 1069 return(0); 1070 } 1071 1072 /* 1073 * Report current media status. 1074 */ 1075 static void 1076 sk_ifmedia_sts(ifp, ifmr) 1077 struct ifnet *ifp; 1078 struct ifmediareq *ifmr; 1079 { 1080 struct sk_if_softc *sc_if; 1081 struct mii_data *mii; 1082 1083 sc_if = ifp->if_softc; 1084 mii = device_get_softc(sc_if->sk_miibus); 1085 1086 mii_pollstat(mii); 1087 ifmr->ifm_active = mii->mii_media_active; 1088 ifmr->ifm_status = mii->mii_media_status; 1089 1090 return; 1091 } 1092 1093 static int 1094 sk_ioctl(ifp, command, data) 1095 struct ifnet *ifp; 1096 u_long command; 1097 caddr_t data; 1098 { 1099 struct sk_if_softc *sc_if = ifp->if_softc; 1100 struct ifreq *ifr = (struct ifreq *) data; 1101 int error, mask; 1102 struct mii_data *mii; 1103 1104 error = 0; 1105 switch(command) { 1106 case SIOCSIFMTU: 1107 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > SK_JUMBO_MTU) 1108 error = EINVAL; 1109 else if (ifp->if_mtu != ifr->ifr_mtu) { 1110 if (sc_if->sk_jumbo_disable != 0 && 1111 ifr->ifr_mtu > SK_MAX_FRAMELEN) 1112 error = EINVAL; 1113 else { 1114 SK_IF_LOCK(sc_if); 1115 ifp->if_mtu = ifr->ifr_mtu; 1116 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1117 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1118 sk_init_locked(sc_if); 1119 } 1120 SK_IF_UNLOCK(sc_if); 1121 } 1122 } 1123 break; 1124 case SIOCSIFFLAGS: 1125 SK_IF_LOCK(sc_if); 1126 if (ifp->if_flags & IFF_UP) { 1127 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1128 if ((ifp->if_flags ^ sc_if->sk_if_flags) 1129 & (IFF_PROMISC | IFF_ALLMULTI)) 1130 sk_rxfilter(sc_if); 1131 } else 1132 sk_init_locked(sc_if); 1133 } else { 1134 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1135 sk_stop(sc_if); 1136 } 1137 sc_if->sk_if_flags = ifp->if_flags; 1138 SK_IF_UNLOCK(sc_if); 1139 break; 1140 case SIOCADDMULTI: 1141 case SIOCDELMULTI: 1142 SK_IF_LOCK(sc_if); 1143 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1144 sk_rxfilter(sc_if); 1145 SK_IF_UNLOCK(sc_if); 1146 break; 1147 case SIOCGIFMEDIA: 1148 case SIOCSIFMEDIA: 1149 mii = device_get_softc(sc_if->sk_miibus); 1150 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1151 break; 1152 case SIOCSIFCAP: 1153 SK_IF_LOCK(sc_if); 1154 if (sc_if->sk_softc->sk_type == SK_GENESIS) { 1155 SK_IF_UNLOCK(sc_if); 1156 break; 1157 } 1158 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1159 if ((mask & IFCAP_TXCSUM) != 0 && 1160 (IFCAP_TXCSUM & ifp->if_capabilities) != 0) { 1161 ifp->if_capenable ^= IFCAP_TXCSUM; 1162 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 1163 ifp->if_hwassist |= SK_CSUM_FEATURES; 1164 else 1165 ifp->if_hwassist &= ~SK_CSUM_FEATURES; 1166 } 1167 if ((mask & IFCAP_RXCSUM) != 0 && 1168 (IFCAP_RXCSUM & ifp->if_capabilities) != 0) 1169 ifp->if_capenable ^= IFCAP_RXCSUM; 1170 SK_IF_UNLOCK(sc_if); 1171 break; 1172 default: 1173 error = ether_ioctl(ifp, command, data); 1174 break; 1175 } 1176 1177 return (error); 1178 } 1179 1180 /* 1181 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 1182 * IDs against our list and return a device name if we find a match. 1183 */ 1184 static int 1185 skc_probe(dev) 1186 device_t dev; 1187 { 1188 const struct sk_type *t = sk_devs; 1189 1190 while(t->sk_name != NULL) { 1191 if ((pci_get_vendor(dev) == t->sk_vid) && 1192 (pci_get_device(dev) == t->sk_did)) { 1193 /* 1194 * Only attach to rev. 2 of the Linksys EG1032 adapter. 1195 * Rev. 3 is supported by re(4). 1196 */ 1197 if ((t->sk_vid == VENDORID_LINKSYS) && 1198 (t->sk_did == DEVICEID_LINKSYS_EG1032) && 1199 (pci_get_subdevice(dev) != 1200 SUBDEVICEID_LINKSYS_EG1032_REV2)) { 1201 t++; 1202 continue; 1203 } 1204 device_set_desc(dev, t->sk_name); 1205 return (BUS_PROBE_DEFAULT); 1206 } 1207 t++; 1208 } 1209 1210 return(ENXIO); 1211 } 1212 1213 /* 1214 * Force the GEnesis into reset, then bring it out of reset. 1215 */ 1216 static void 1217 sk_reset(sc) 1218 struct sk_softc *sc; 1219 { 1220 1221 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 1222 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 1223 if (SK_YUKON_FAMILY(sc->sk_type)) 1224 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 1225 1226 DELAY(1000); 1227 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 1228 DELAY(2); 1229 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1230 if (SK_YUKON_FAMILY(sc->sk_type)) 1231 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 1232 1233 if (sc->sk_type == SK_GENESIS) { 1234 /* Configure packet arbiter */ 1235 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1236 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1237 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1238 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1239 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1240 } 1241 1242 /* Enable RAM interface */ 1243 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1244 1245 /* 1246 * Configure interrupt moderation. The moderation timer 1247 * defers interrupts specified in the interrupt moderation 1248 * timer mask based on the timeout specified in the interrupt 1249 * moderation timer init register. Each bit in the timer 1250 * register represents one tick, so to specify a timeout in 1251 * microseconds, we have to multiply by the correct number of 1252 * ticks-per-microsecond. 1253 */ 1254 switch (sc->sk_type) { 1255 case SK_GENESIS: 1256 sc->sk_int_ticks = SK_IMTIMER_TICKS_GENESIS; 1257 break; 1258 default: 1259 sc->sk_int_ticks = SK_IMTIMER_TICKS_YUKON; 1260 break; 1261 } 1262 if (bootverbose) 1263 device_printf(sc->sk_dev, "interrupt moderation is %d us\n", 1264 sc->sk_int_mod); 1265 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod, 1266 sc->sk_int_ticks)); 1267 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 1268 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 1269 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1270 1271 return; 1272 } 1273 1274 static int 1275 sk_probe(dev) 1276 device_t dev; 1277 { 1278 struct sk_softc *sc; 1279 1280 sc = device_get_softc(device_get_parent(dev)); 1281 1282 /* 1283 * Not much to do here. We always know there will be 1284 * at least one XMAC present, and if there are two, 1285 * skc_attach() will create a second device instance 1286 * for us. 1287 */ 1288 switch (sc->sk_type) { 1289 case SK_GENESIS: 1290 device_set_desc(dev, "XaQti Corp. XMAC II"); 1291 break; 1292 case SK_YUKON: 1293 case SK_YUKON_LITE: 1294 case SK_YUKON_LP: 1295 device_set_desc(dev, "Marvell Semiconductor, Inc. Yukon"); 1296 break; 1297 } 1298 1299 return (BUS_PROBE_DEFAULT); 1300 } 1301 1302 /* 1303 * Each XMAC chip is attached as a separate logical IP interface. 1304 * Single port cards will have only one logical interface of course. 1305 */ 1306 static int 1307 sk_attach(dev) 1308 device_t dev; 1309 { 1310 struct sk_softc *sc; 1311 struct sk_if_softc *sc_if; 1312 struct ifnet *ifp; 1313 u_int32_t r; 1314 int error, i, phy, port; 1315 u_char eaddr[6]; 1316 u_char inv_mac[] = {0, 0, 0, 0, 0, 0}; 1317 1318 if (dev == NULL) 1319 return(EINVAL); 1320 1321 error = 0; 1322 sc_if = device_get_softc(dev); 1323 sc = device_get_softc(device_get_parent(dev)); 1324 port = *(int *)device_get_ivars(dev); 1325 1326 sc_if->sk_if_dev = dev; 1327 sc_if->sk_port = port; 1328 sc_if->sk_softc = sc; 1329 sc->sk_if[port] = sc_if; 1330 if (port == SK_PORT_A) 1331 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1332 if (port == SK_PORT_B) 1333 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1334 1335 callout_init_mtx(&sc_if->sk_tick_ch, &sc_if->sk_softc->sk_mtx, 0); 1336 callout_init_mtx(&sc_if->sk_watchdog_ch, &sc_if->sk_softc->sk_mtx, 0); 1337 1338 if (sk_dma_alloc(sc_if) != 0) { 1339 error = ENOMEM; 1340 goto fail; 1341 } 1342 sk_dma_jumbo_alloc(sc_if); 1343 1344 ifp = sc_if->sk_ifp = if_alloc(IFT_ETHER); 1345 if (ifp == NULL) { 1346 device_printf(sc_if->sk_if_dev, "can not if_alloc()\n"); 1347 error = ENOSPC; 1348 goto fail; 1349 } 1350 ifp->if_softc = sc_if; 1351 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1352 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1353 /* 1354 * SK_GENESIS has a bug in checksum offload - From linux. 1355 */ 1356 if (sc_if->sk_softc->sk_type != SK_GENESIS) { 1357 ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_RXCSUM; 1358 ifp->if_hwassist = 0; 1359 } else { 1360 ifp->if_capabilities = 0; 1361 ifp->if_hwassist = 0; 1362 } 1363 ifp->if_capenable = ifp->if_capabilities; 1364 /* 1365 * Some revision of Yukon controller generates corrupted 1366 * frame when TX checksum offloading is enabled. The 1367 * frame has a valid checksum value so payload might be 1368 * modified during TX checksum calculation. Disable TX 1369 * checksum offloading but give users chance to enable it 1370 * when they know their controller works without problems 1371 * with TX checksum offloading. 1372 */ 1373 ifp->if_capenable &= ~IFCAP_TXCSUM; 1374 ifp->if_ioctl = sk_ioctl; 1375 ifp->if_start = sk_start; 1376 ifp->if_init = sk_init; 1377 IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1); 1378 ifp->if_snd.ifq_drv_maxlen = SK_TX_RING_CNT - 1; 1379 IFQ_SET_READY(&ifp->if_snd); 1380 1381 /* 1382 * Get station address for this interface. Note that 1383 * dual port cards actually come with three station 1384 * addresses: one for each port, plus an extra. The 1385 * extra one is used by the SysKonnect driver software 1386 * as a 'virtual' station address for when both ports 1387 * are operating in failover mode. Currently we don't 1388 * use this extra address. 1389 */ 1390 SK_IF_LOCK(sc_if); 1391 for (i = 0; i < ETHER_ADDR_LEN; i++) 1392 eaddr[i] = 1393 sk_win_read_1(sc, SK_MAC0_0 + (port * 8) + i); 1394 1395 /* Verify whether the station address is invalid or not. */ 1396 if (bcmp(eaddr, inv_mac, sizeof(inv_mac)) == 0) { 1397 device_printf(sc_if->sk_if_dev, 1398 "Generating random ethernet address\n"); 1399 r = arc4random(); 1400 /* 1401 * Set OUI to convenient locally assigned address. 'b' 1402 * is 0x62, which has the locally assigned bit set, and 1403 * the broadcast/multicast bit clear. 1404 */ 1405 eaddr[0] = 'b'; 1406 eaddr[1] = 's'; 1407 eaddr[2] = 'd'; 1408 eaddr[3] = (r >> 16) & 0xff; 1409 eaddr[4] = (r >> 8) & 0xff; 1410 eaddr[5] = (r >> 0) & 0xff; 1411 } 1412 /* 1413 * Set up RAM buffer addresses. The NIC will have a certain 1414 * amount of SRAM on it, somewhere between 512K and 2MB. We 1415 * need to divide this up a) between the transmitter and 1416 * receiver and b) between the two XMACs, if this is a 1417 * dual port NIC. Our algotithm is to divide up the memory 1418 * evenly so that everyone gets a fair share. 1419 * 1420 * Just to be contrary, Yukon2 appears to have separate memory 1421 * for each MAC. 1422 */ 1423 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1424 u_int32_t chunk, val; 1425 1426 chunk = sc->sk_ramsize / 2; 1427 val = sc->sk_rboff / sizeof(u_int64_t); 1428 sc_if->sk_rx_ramstart = val; 1429 val += (chunk / sizeof(u_int64_t)); 1430 sc_if->sk_rx_ramend = val - 1; 1431 sc_if->sk_tx_ramstart = val; 1432 val += (chunk / sizeof(u_int64_t)); 1433 sc_if->sk_tx_ramend = val - 1; 1434 } else { 1435 u_int32_t chunk, val; 1436 1437 chunk = sc->sk_ramsize / 4; 1438 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1439 sizeof(u_int64_t); 1440 sc_if->sk_rx_ramstart = val; 1441 val += (chunk / sizeof(u_int64_t)); 1442 sc_if->sk_rx_ramend = val - 1; 1443 sc_if->sk_tx_ramstart = val; 1444 val += (chunk / sizeof(u_int64_t)); 1445 sc_if->sk_tx_ramend = val - 1; 1446 } 1447 1448 /* Read and save PHY type and set PHY address */ 1449 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1450 if (!SK_YUKON_FAMILY(sc->sk_type)) { 1451 switch(sc_if->sk_phytype) { 1452 case SK_PHYTYPE_XMAC: 1453 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1454 break; 1455 case SK_PHYTYPE_BCOM: 1456 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1457 break; 1458 default: 1459 device_printf(sc->sk_dev, "unsupported PHY type: %d\n", 1460 sc_if->sk_phytype); 1461 error = ENODEV; 1462 SK_IF_UNLOCK(sc_if); 1463 goto fail; 1464 } 1465 } else { 1466 if (sc_if->sk_phytype < SK_PHYTYPE_MARV_COPPER && 1467 sc->sk_pmd != 'S') { 1468 /* not initialized, punt */ 1469 sc_if->sk_phytype = SK_PHYTYPE_MARV_COPPER; 1470 sc->sk_coppertype = 1; 1471 } 1472 1473 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1474 1475 if (!(sc->sk_coppertype)) 1476 sc_if->sk_phytype = SK_PHYTYPE_MARV_FIBER; 1477 } 1478 1479 /* 1480 * Call MI attach routine. Can't hold locks when calling into ether_*. 1481 */ 1482 SK_IF_UNLOCK(sc_if); 1483 ether_ifattach(ifp, eaddr); 1484 SK_IF_LOCK(sc_if); 1485 1486 /* 1487 * The hardware should be ready for VLAN_MTU by default: 1488 * XMAC II has 0x8100 in VLAN Tag Level 1 register initially; 1489 * YU_SMR_MFL_VLAN is set by this driver in Yukon. 1490 * 1491 */ 1492 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1493 ifp->if_capenable |= IFCAP_VLAN_MTU; 1494 /* 1495 * Tell the upper layer(s) we support long frames. 1496 * Must appear after the call to ether_ifattach() because 1497 * ether_ifattach() sets ifi_hdrlen to the default value. 1498 */ 1499 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1500 1501 /* 1502 * Do miibus setup. 1503 */ 1504 phy = MII_PHY_ANY; 1505 switch (sc->sk_type) { 1506 case SK_GENESIS: 1507 sk_init_xmac(sc_if); 1508 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 1509 phy = 0; 1510 break; 1511 case SK_YUKON: 1512 case SK_YUKON_LITE: 1513 case SK_YUKON_LP: 1514 sk_init_yukon(sc_if); 1515 phy = 0; 1516 break; 1517 } 1518 1519 SK_IF_UNLOCK(sc_if); 1520 error = mii_attach(dev, &sc_if->sk_miibus, ifp, sk_ifmedia_upd, 1521 sk_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0); 1522 if (error != 0) { 1523 device_printf(sc_if->sk_if_dev, "attaching PHYs failed\n"); 1524 ether_ifdetach(ifp); 1525 goto fail; 1526 } 1527 1528 fail: 1529 if (error) { 1530 /* Access should be ok even though lock has been dropped */ 1531 sc->sk_if[port] = NULL; 1532 sk_detach(dev); 1533 } 1534 1535 return(error); 1536 } 1537 1538 /* 1539 * Attach the interface. Allocate softc structures, do ifmedia 1540 * setup and ethernet/BPF attach. 1541 */ 1542 static int 1543 skc_attach(dev) 1544 device_t dev; 1545 { 1546 struct sk_softc *sc; 1547 int error = 0, *port; 1548 uint8_t skrs; 1549 const char *pname = NULL; 1550 char *revstr; 1551 1552 sc = device_get_softc(dev); 1553 sc->sk_dev = dev; 1554 1555 mtx_init(&sc->sk_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1556 MTX_DEF); 1557 mtx_init(&sc->sk_mii_mtx, "sk_mii_mutex", NULL, MTX_DEF); 1558 /* 1559 * Map control/status registers. 1560 */ 1561 pci_enable_busmaster(dev); 1562 1563 /* Allocate resources */ 1564 #ifdef SK_USEIOSPACE 1565 sc->sk_res_spec = sk_res_spec_io; 1566 #else 1567 sc->sk_res_spec = sk_res_spec_mem; 1568 #endif 1569 error = bus_alloc_resources(dev, sc->sk_res_spec, sc->sk_res); 1570 if (error) { 1571 if (sc->sk_res_spec == sk_res_spec_mem) 1572 sc->sk_res_spec = sk_res_spec_io; 1573 else 1574 sc->sk_res_spec = sk_res_spec_mem; 1575 error = bus_alloc_resources(dev, sc->sk_res_spec, sc->sk_res); 1576 if (error) { 1577 device_printf(dev, "couldn't allocate %s resources\n", 1578 sc->sk_res_spec == sk_res_spec_mem ? "memory" : 1579 "I/O"); 1580 goto fail; 1581 } 1582 } 1583 1584 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1585 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4) & 0xf; 1586 1587 /* Bail out if chip is not recognized. */ 1588 if (sc->sk_type != SK_GENESIS && !SK_YUKON_FAMILY(sc->sk_type)) { 1589 device_printf(dev, "unknown device: chipver=%02x, rev=%x\n", 1590 sc->sk_type, sc->sk_rev); 1591 error = ENXIO; 1592 goto fail; 1593 } 1594 1595 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 1596 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 1597 OID_AUTO, "int_mod", CTLTYPE_INT|CTLFLAG_RW, 1598 &sc->sk_int_mod, 0, sysctl_hw_sk_int_mod, "I", 1599 "SK interrupt moderation"); 1600 1601 /* Pull in device tunables. */ 1602 sc->sk_int_mod = SK_IM_DEFAULT; 1603 error = resource_int_value(device_get_name(dev), device_get_unit(dev), 1604 "int_mod", &sc->sk_int_mod); 1605 if (error == 0) { 1606 if (sc->sk_int_mod < SK_IM_MIN || 1607 sc->sk_int_mod > SK_IM_MAX) { 1608 device_printf(dev, "int_mod value out of range; " 1609 "using default: %d\n", SK_IM_DEFAULT); 1610 sc->sk_int_mod = SK_IM_DEFAULT; 1611 } 1612 } 1613 1614 /* Reset the adapter. */ 1615 sk_reset(sc); 1616 1617 skrs = sk_win_read_1(sc, SK_EPROM0); 1618 if (sc->sk_type == SK_GENESIS) { 1619 /* Read and save RAM size and RAMbuffer offset */ 1620 switch(skrs) { 1621 case SK_RAMSIZE_512K_64: 1622 sc->sk_ramsize = 0x80000; 1623 sc->sk_rboff = SK_RBOFF_0; 1624 break; 1625 case SK_RAMSIZE_1024K_64: 1626 sc->sk_ramsize = 0x100000; 1627 sc->sk_rboff = SK_RBOFF_80000; 1628 break; 1629 case SK_RAMSIZE_1024K_128: 1630 sc->sk_ramsize = 0x100000; 1631 sc->sk_rboff = SK_RBOFF_0; 1632 break; 1633 case SK_RAMSIZE_2048K_128: 1634 sc->sk_ramsize = 0x200000; 1635 sc->sk_rboff = SK_RBOFF_0; 1636 break; 1637 default: 1638 device_printf(dev, "unknown ram size: %d\n", skrs); 1639 error = ENXIO; 1640 goto fail; 1641 } 1642 } else { /* SK_YUKON_FAMILY */ 1643 if (skrs == 0x00) 1644 sc->sk_ramsize = 0x20000; 1645 else 1646 sc->sk_ramsize = skrs * (1<<12); 1647 sc->sk_rboff = SK_RBOFF_0; 1648 } 1649 1650 /* Read and save physical media type */ 1651 sc->sk_pmd = sk_win_read_1(sc, SK_PMDTYPE); 1652 1653 if (sc->sk_pmd == 'T' || sc->sk_pmd == '1') 1654 sc->sk_coppertype = 1; 1655 else 1656 sc->sk_coppertype = 0; 1657 1658 /* Determine whether to name it with VPD PN or just make it up. 1659 * Marvell Yukon VPD PN seems to freqently be bogus. */ 1660 switch (pci_get_device(dev)) { 1661 case DEVICEID_SK_V1: 1662 case DEVICEID_BELKIN_5005: 1663 case DEVICEID_3COM_3C940: 1664 case DEVICEID_LINKSYS_EG1032: 1665 case DEVICEID_DLINK_DGE530T_A1: 1666 case DEVICEID_DLINK_DGE530T_B1: 1667 /* Stay with VPD PN. */ 1668 (void) pci_get_vpd_ident(dev, &pname); 1669 break; 1670 case DEVICEID_SK_V2: 1671 /* YUKON VPD PN might bear no resemblance to reality. */ 1672 switch (sc->sk_type) { 1673 case SK_GENESIS: 1674 /* Stay with VPD PN. */ 1675 (void) pci_get_vpd_ident(dev, &pname); 1676 break; 1677 case SK_YUKON: 1678 pname = "Marvell Yukon Gigabit Ethernet"; 1679 break; 1680 case SK_YUKON_LITE: 1681 pname = "Marvell Yukon Lite Gigabit Ethernet"; 1682 break; 1683 case SK_YUKON_LP: 1684 pname = "Marvell Yukon LP Gigabit Ethernet"; 1685 break; 1686 default: 1687 pname = "Marvell Yukon (Unknown) Gigabit Ethernet"; 1688 break; 1689 } 1690 1691 /* Yukon Lite Rev. A0 needs special test. */ 1692 if (sc->sk_type == SK_YUKON || sc->sk_type == SK_YUKON_LP) { 1693 u_int32_t far; 1694 u_int8_t testbyte; 1695 1696 /* Save flash address register before testing. */ 1697 far = sk_win_read_4(sc, SK_EP_ADDR); 1698 1699 sk_win_write_1(sc, SK_EP_ADDR+0x03, 0xff); 1700 testbyte = sk_win_read_1(sc, SK_EP_ADDR+0x03); 1701 1702 if (testbyte != 0x00) { 1703 /* Yukon Lite Rev. A0 detected. */ 1704 sc->sk_type = SK_YUKON_LITE; 1705 sc->sk_rev = SK_YUKON_LITE_REV_A0; 1706 /* Restore flash address register. */ 1707 sk_win_write_4(sc, SK_EP_ADDR, far); 1708 } 1709 } 1710 break; 1711 default: 1712 device_printf(dev, "unknown device: vendor=%04x, device=%04x, " 1713 "chipver=%02x, rev=%x\n", 1714 pci_get_vendor(dev), pci_get_device(dev), 1715 sc->sk_type, sc->sk_rev); 1716 error = ENXIO; 1717 goto fail; 1718 } 1719 1720 if (sc->sk_type == SK_YUKON_LITE) { 1721 switch (sc->sk_rev) { 1722 case SK_YUKON_LITE_REV_A0: 1723 revstr = "A0"; 1724 break; 1725 case SK_YUKON_LITE_REV_A1: 1726 revstr = "A1"; 1727 break; 1728 case SK_YUKON_LITE_REV_A3: 1729 revstr = "A3"; 1730 break; 1731 default: 1732 revstr = ""; 1733 break; 1734 } 1735 } else { 1736 revstr = ""; 1737 } 1738 1739 /* Announce the product name and more VPD data if there. */ 1740 if (pname != NULL) 1741 device_printf(dev, "%s rev. %s(0x%x)\n", 1742 pname, revstr, sc->sk_rev); 1743 1744 if (bootverbose) { 1745 device_printf(dev, "chip ver = 0x%02x\n", sc->sk_type); 1746 device_printf(dev, "chip rev = 0x%02x\n", sc->sk_rev); 1747 device_printf(dev, "SK_EPROM0 = 0x%02x\n", skrs); 1748 device_printf(dev, "SRAM size = 0x%06x\n", sc->sk_ramsize); 1749 } 1750 1751 sc->sk_devs[SK_PORT_A] = device_add_child(dev, "sk", -1); 1752 if (sc->sk_devs[SK_PORT_A] == NULL) { 1753 device_printf(dev, "failed to add child for PORT_A\n"); 1754 error = ENXIO; 1755 goto fail; 1756 } 1757 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT); 1758 if (port == NULL) { 1759 device_printf(dev, "failed to allocate memory for " 1760 "ivars of PORT_A\n"); 1761 error = ENXIO; 1762 goto fail; 1763 } 1764 *port = SK_PORT_A; 1765 device_set_ivars(sc->sk_devs[SK_PORT_A], port); 1766 1767 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1768 sc->sk_devs[SK_PORT_B] = device_add_child(dev, "sk", -1); 1769 if (sc->sk_devs[SK_PORT_B] == NULL) { 1770 device_printf(dev, "failed to add child for PORT_B\n"); 1771 error = ENXIO; 1772 goto fail; 1773 } 1774 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT); 1775 if (port == NULL) { 1776 device_printf(dev, "failed to allocate memory for " 1777 "ivars of PORT_B\n"); 1778 error = ENXIO; 1779 goto fail; 1780 } 1781 *port = SK_PORT_B; 1782 device_set_ivars(sc->sk_devs[SK_PORT_B], port); 1783 } 1784 1785 /* Turn on the 'driver is loaded' LED. */ 1786 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1787 1788 error = bus_generic_attach(dev); 1789 if (error) { 1790 device_printf(dev, "failed to attach port(s)\n"); 1791 goto fail; 1792 } 1793 1794 /* Hook interrupt last to avoid having to lock softc */ 1795 error = bus_setup_intr(dev, sc->sk_res[1], INTR_TYPE_NET|INTR_MPSAFE, 1796 NULL, sk_intr, sc, &sc->sk_intrhand); 1797 1798 if (error) { 1799 device_printf(dev, "couldn't set up irq\n"); 1800 goto fail; 1801 } 1802 1803 fail: 1804 if (error) 1805 skc_detach(dev); 1806 1807 return(error); 1808 } 1809 1810 /* 1811 * Shutdown hardware and free up resources. This can be called any 1812 * time after the mutex has been initialized. It is called in both 1813 * the error case in attach and the normal detach case so it needs 1814 * to be careful about only freeing resources that have actually been 1815 * allocated. 1816 */ 1817 static int 1818 sk_detach(dev) 1819 device_t dev; 1820 { 1821 struct sk_if_softc *sc_if; 1822 struct ifnet *ifp; 1823 1824 sc_if = device_get_softc(dev); 1825 KASSERT(mtx_initialized(&sc_if->sk_softc->sk_mtx), 1826 ("sk mutex not initialized in sk_detach")); 1827 SK_IF_LOCK(sc_if); 1828 1829 ifp = sc_if->sk_ifp; 1830 /* These should only be active if attach_xmac succeeded */ 1831 if (device_is_attached(dev)) { 1832 sk_stop(sc_if); 1833 /* Can't hold locks while calling detach */ 1834 SK_IF_UNLOCK(sc_if); 1835 callout_drain(&sc_if->sk_tick_ch); 1836 callout_drain(&sc_if->sk_watchdog_ch); 1837 ether_ifdetach(ifp); 1838 SK_IF_LOCK(sc_if); 1839 } 1840 if (ifp) 1841 if_free(ifp); 1842 /* 1843 * We're generally called from skc_detach() which is using 1844 * device_delete_child() to get to here. It's already trashed 1845 * miibus for us, so don't do it here or we'll panic. 1846 */ 1847 /* 1848 if (sc_if->sk_miibus != NULL) 1849 device_delete_child(dev, sc_if->sk_miibus); 1850 */ 1851 bus_generic_detach(dev); 1852 sk_dma_jumbo_free(sc_if); 1853 sk_dma_free(sc_if); 1854 SK_IF_UNLOCK(sc_if); 1855 1856 return(0); 1857 } 1858 1859 static int 1860 skc_detach(dev) 1861 device_t dev; 1862 { 1863 struct sk_softc *sc; 1864 1865 sc = device_get_softc(dev); 1866 KASSERT(mtx_initialized(&sc->sk_mtx), ("sk mutex not initialized")); 1867 1868 if (device_is_alive(dev)) { 1869 if (sc->sk_devs[SK_PORT_A] != NULL) { 1870 free(device_get_ivars(sc->sk_devs[SK_PORT_A]), M_DEVBUF); 1871 device_delete_child(dev, sc->sk_devs[SK_PORT_A]); 1872 } 1873 if (sc->sk_devs[SK_PORT_B] != NULL) { 1874 free(device_get_ivars(sc->sk_devs[SK_PORT_B]), M_DEVBUF); 1875 device_delete_child(dev, sc->sk_devs[SK_PORT_B]); 1876 } 1877 bus_generic_detach(dev); 1878 } 1879 1880 if (sc->sk_intrhand) 1881 bus_teardown_intr(dev, sc->sk_res[1], sc->sk_intrhand); 1882 bus_release_resources(dev, sc->sk_res_spec, sc->sk_res); 1883 1884 mtx_destroy(&sc->sk_mii_mtx); 1885 mtx_destroy(&sc->sk_mtx); 1886 1887 return(0); 1888 } 1889 1890 static bus_dma_tag_t 1891 skc_get_dma_tag(device_t bus, device_t child __unused) 1892 { 1893 1894 return (bus_get_dma_tag(bus)); 1895 } 1896 1897 struct sk_dmamap_arg { 1898 bus_addr_t sk_busaddr; 1899 }; 1900 1901 static void 1902 sk_dmamap_cb(arg, segs, nseg, error) 1903 void *arg; 1904 bus_dma_segment_t *segs; 1905 int nseg; 1906 int error; 1907 { 1908 struct sk_dmamap_arg *ctx; 1909 1910 if (error != 0) 1911 return; 1912 1913 ctx = arg; 1914 ctx->sk_busaddr = segs[0].ds_addr; 1915 } 1916 1917 /* 1918 * Allocate jumbo buffer storage. The SysKonnect adapters support 1919 * "jumbograms" (9K frames), although SysKonnect doesn't currently 1920 * use them in their drivers. In order for us to use them, we need 1921 * large 9K receive buffers, however standard mbuf clusters are only 1922 * 2048 bytes in size. Consequently, we need to allocate and manage 1923 * our own jumbo buffer pool. Fortunately, this does not require an 1924 * excessive amount of additional code. 1925 */ 1926 static int 1927 sk_dma_alloc(sc_if) 1928 struct sk_if_softc *sc_if; 1929 { 1930 struct sk_dmamap_arg ctx; 1931 struct sk_txdesc *txd; 1932 struct sk_rxdesc *rxd; 1933 int error, i; 1934 1935 /* create parent tag */ 1936 /* 1937 * XXX 1938 * This driver should use BUS_SPACE_MAXADDR for lowaddr argument 1939 * in bus_dma_tag_create(9) as the NIC would support DAC mode. 1940 * However bz@ reported that it does not work on amd64 with > 4GB 1941 * RAM. Until we have more clues of the breakage, disable DAC mode 1942 * by limiting DMA address to be in 32bit address space. 1943 */ 1944 error = bus_dma_tag_create( 1945 bus_get_dma_tag(sc_if->sk_if_dev),/* parent */ 1946 1, 0, /* algnmnt, boundary */ 1947 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1948 BUS_SPACE_MAXADDR, /* highaddr */ 1949 NULL, NULL, /* filter, filterarg */ 1950 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1951 0, /* nsegments */ 1952 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1953 0, /* flags */ 1954 NULL, NULL, /* lockfunc, lockarg */ 1955 &sc_if->sk_cdata.sk_parent_tag); 1956 if (error != 0) { 1957 device_printf(sc_if->sk_if_dev, 1958 "failed to create parent DMA tag\n"); 1959 goto fail; 1960 } 1961 1962 /* create tag for Tx ring */ 1963 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */ 1964 SK_RING_ALIGN, 0, /* algnmnt, boundary */ 1965 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1966 BUS_SPACE_MAXADDR, /* highaddr */ 1967 NULL, NULL, /* filter, filterarg */ 1968 SK_TX_RING_SZ, /* maxsize */ 1969 1, /* nsegments */ 1970 SK_TX_RING_SZ, /* maxsegsize */ 1971 0, /* flags */ 1972 NULL, NULL, /* lockfunc, lockarg */ 1973 &sc_if->sk_cdata.sk_tx_ring_tag); 1974 if (error != 0) { 1975 device_printf(sc_if->sk_if_dev, 1976 "failed to allocate Tx ring DMA tag\n"); 1977 goto fail; 1978 } 1979 1980 /* create tag for Rx ring */ 1981 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */ 1982 SK_RING_ALIGN, 0, /* algnmnt, boundary */ 1983 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1984 BUS_SPACE_MAXADDR, /* highaddr */ 1985 NULL, NULL, /* filter, filterarg */ 1986 SK_RX_RING_SZ, /* maxsize */ 1987 1, /* nsegments */ 1988 SK_RX_RING_SZ, /* maxsegsize */ 1989 0, /* flags */ 1990 NULL, NULL, /* lockfunc, lockarg */ 1991 &sc_if->sk_cdata.sk_rx_ring_tag); 1992 if (error != 0) { 1993 device_printf(sc_if->sk_if_dev, 1994 "failed to allocate Rx ring DMA tag\n"); 1995 goto fail; 1996 } 1997 1998 /* create tag for Tx buffers */ 1999 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */ 2000 1, 0, /* algnmnt, boundary */ 2001 BUS_SPACE_MAXADDR, /* lowaddr */ 2002 BUS_SPACE_MAXADDR, /* highaddr */ 2003 NULL, NULL, /* filter, filterarg */ 2004 MCLBYTES * SK_MAXTXSEGS, /* maxsize */ 2005 SK_MAXTXSEGS, /* nsegments */ 2006 MCLBYTES, /* maxsegsize */ 2007 0, /* flags */ 2008 NULL, NULL, /* lockfunc, lockarg */ 2009 &sc_if->sk_cdata.sk_tx_tag); 2010 if (error != 0) { 2011 device_printf(sc_if->sk_if_dev, 2012 "failed to allocate Tx DMA tag\n"); 2013 goto fail; 2014 } 2015 2016 /* create tag for Rx buffers */ 2017 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */ 2018 1, 0, /* algnmnt, boundary */ 2019 BUS_SPACE_MAXADDR, /* lowaddr */ 2020 BUS_SPACE_MAXADDR, /* highaddr */ 2021 NULL, NULL, /* filter, filterarg */ 2022 MCLBYTES, /* maxsize */ 2023 1, /* nsegments */ 2024 MCLBYTES, /* maxsegsize */ 2025 0, /* flags */ 2026 NULL, NULL, /* lockfunc, lockarg */ 2027 &sc_if->sk_cdata.sk_rx_tag); 2028 if (error != 0) { 2029 device_printf(sc_if->sk_if_dev, 2030 "failed to allocate Rx DMA tag\n"); 2031 goto fail; 2032 } 2033 2034 /* allocate DMA'able memory and load the DMA map for Tx ring */ 2035 error = bus_dmamem_alloc(sc_if->sk_cdata.sk_tx_ring_tag, 2036 (void **)&sc_if->sk_rdata.sk_tx_ring, BUS_DMA_NOWAIT | 2037 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->sk_cdata.sk_tx_ring_map); 2038 if (error != 0) { 2039 device_printf(sc_if->sk_if_dev, 2040 "failed to allocate DMA'able memory for Tx ring\n"); 2041 goto fail; 2042 } 2043 2044 ctx.sk_busaddr = 0; 2045 error = bus_dmamap_load(sc_if->sk_cdata.sk_tx_ring_tag, 2046 sc_if->sk_cdata.sk_tx_ring_map, sc_if->sk_rdata.sk_tx_ring, 2047 SK_TX_RING_SZ, sk_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 2048 if (error != 0) { 2049 device_printf(sc_if->sk_if_dev, 2050 "failed to load DMA'able memory for Tx ring\n"); 2051 goto fail; 2052 } 2053 sc_if->sk_rdata.sk_tx_ring_paddr = ctx.sk_busaddr; 2054 2055 /* allocate DMA'able memory and load the DMA map for Rx ring */ 2056 error = bus_dmamem_alloc(sc_if->sk_cdata.sk_rx_ring_tag, 2057 (void **)&sc_if->sk_rdata.sk_rx_ring, BUS_DMA_NOWAIT | 2058 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->sk_cdata.sk_rx_ring_map); 2059 if (error != 0) { 2060 device_printf(sc_if->sk_if_dev, 2061 "failed to allocate DMA'able memory for Rx ring\n"); 2062 goto fail; 2063 } 2064 2065 ctx.sk_busaddr = 0; 2066 error = bus_dmamap_load(sc_if->sk_cdata.sk_rx_ring_tag, 2067 sc_if->sk_cdata.sk_rx_ring_map, sc_if->sk_rdata.sk_rx_ring, 2068 SK_RX_RING_SZ, sk_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 2069 if (error != 0) { 2070 device_printf(sc_if->sk_if_dev, 2071 "failed to load DMA'able memory for Rx ring\n"); 2072 goto fail; 2073 } 2074 sc_if->sk_rdata.sk_rx_ring_paddr = ctx.sk_busaddr; 2075 2076 /* create DMA maps for Tx buffers */ 2077 for (i = 0; i < SK_TX_RING_CNT; i++) { 2078 txd = &sc_if->sk_cdata.sk_txdesc[i]; 2079 txd->tx_m = NULL; 2080 txd->tx_dmamap = NULL; 2081 error = bus_dmamap_create(sc_if->sk_cdata.sk_tx_tag, 0, 2082 &txd->tx_dmamap); 2083 if (error != 0) { 2084 device_printf(sc_if->sk_if_dev, 2085 "failed to create Tx dmamap\n"); 2086 goto fail; 2087 } 2088 } 2089 2090 /* create DMA maps for Rx buffers */ 2091 if ((error = bus_dmamap_create(sc_if->sk_cdata.sk_rx_tag, 0, 2092 &sc_if->sk_cdata.sk_rx_sparemap)) != 0) { 2093 device_printf(sc_if->sk_if_dev, 2094 "failed to create spare Rx dmamap\n"); 2095 goto fail; 2096 } 2097 for (i = 0; i < SK_RX_RING_CNT; i++) { 2098 rxd = &sc_if->sk_cdata.sk_rxdesc[i]; 2099 rxd->rx_m = NULL; 2100 rxd->rx_dmamap = NULL; 2101 error = bus_dmamap_create(sc_if->sk_cdata.sk_rx_tag, 0, 2102 &rxd->rx_dmamap); 2103 if (error != 0) { 2104 device_printf(sc_if->sk_if_dev, 2105 "failed to create Rx dmamap\n"); 2106 goto fail; 2107 } 2108 } 2109 2110 fail: 2111 return (error); 2112 } 2113 2114 static int 2115 sk_dma_jumbo_alloc(sc_if) 2116 struct sk_if_softc *sc_if; 2117 { 2118 struct sk_dmamap_arg ctx; 2119 struct sk_rxdesc *jrxd; 2120 int error, i; 2121 2122 if (jumbo_disable != 0) { 2123 device_printf(sc_if->sk_if_dev, "disabling jumbo frame support\n"); 2124 sc_if->sk_jumbo_disable = 1; 2125 return (0); 2126 } 2127 /* create tag for jumbo Rx ring */ 2128 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */ 2129 SK_RING_ALIGN, 0, /* algnmnt, boundary */ 2130 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 2131 BUS_SPACE_MAXADDR, /* highaddr */ 2132 NULL, NULL, /* filter, filterarg */ 2133 SK_JUMBO_RX_RING_SZ, /* maxsize */ 2134 1, /* nsegments */ 2135 SK_JUMBO_RX_RING_SZ, /* maxsegsize */ 2136 0, /* flags */ 2137 NULL, NULL, /* lockfunc, lockarg */ 2138 &sc_if->sk_cdata.sk_jumbo_rx_ring_tag); 2139 if (error != 0) { 2140 device_printf(sc_if->sk_if_dev, 2141 "failed to allocate jumbo Rx ring DMA tag\n"); 2142 goto jumbo_fail; 2143 } 2144 2145 /* create tag for jumbo Rx buffers */ 2146 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */ 2147 1, 0, /* algnmnt, boundary */ 2148 BUS_SPACE_MAXADDR, /* lowaddr */ 2149 BUS_SPACE_MAXADDR, /* highaddr */ 2150 NULL, NULL, /* filter, filterarg */ 2151 MJUM9BYTES, /* maxsize */ 2152 1, /* nsegments */ 2153 MJUM9BYTES, /* maxsegsize */ 2154 0, /* flags */ 2155 NULL, NULL, /* lockfunc, lockarg */ 2156 &sc_if->sk_cdata.sk_jumbo_rx_tag); 2157 if (error != 0) { 2158 device_printf(sc_if->sk_if_dev, 2159 "failed to allocate jumbo Rx DMA tag\n"); 2160 goto jumbo_fail; 2161 } 2162 2163 /* allocate DMA'able memory and load the DMA map for jumbo Rx ring */ 2164 error = bus_dmamem_alloc(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 2165 (void **)&sc_if->sk_rdata.sk_jumbo_rx_ring, BUS_DMA_NOWAIT | 2166 BUS_DMA_COHERENT | BUS_DMA_ZERO, 2167 &sc_if->sk_cdata.sk_jumbo_rx_ring_map); 2168 if (error != 0) { 2169 device_printf(sc_if->sk_if_dev, 2170 "failed to allocate DMA'able memory for jumbo Rx ring\n"); 2171 goto jumbo_fail; 2172 } 2173 2174 ctx.sk_busaddr = 0; 2175 error = bus_dmamap_load(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 2176 sc_if->sk_cdata.sk_jumbo_rx_ring_map, 2177 sc_if->sk_rdata.sk_jumbo_rx_ring, SK_JUMBO_RX_RING_SZ, sk_dmamap_cb, 2178 &ctx, BUS_DMA_NOWAIT); 2179 if (error != 0) { 2180 device_printf(sc_if->sk_if_dev, 2181 "failed to load DMA'able memory for jumbo Rx ring\n"); 2182 goto jumbo_fail; 2183 } 2184 sc_if->sk_rdata.sk_jumbo_rx_ring_paddr = ctx.sk_busaddr; 2185 2186 /* create DMA maps for jumbo Rx buffers */ 2187 if ((error = bus_dmamap_create(sc_if->sk_cdata.sk_jumbo_rx_tag, 0, 2188 &sc_if->sk_cdata.sk_jumbo_rx_sparemap)) != 0) { 2189 device_printf(sc_if->sk_if_dev, 2190 "failed to create spare jumbo Rx dmamap\n"); 2191 goto jumbo_fail; 2192 } 2193 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) { 2194 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i]; 2195 jrxd->rx_m = NULL; 2196 jrxd->rx_dmamap = NULL; 2197 error = bus_dmamap_create(sc_if->sk_cdata.sk_jumbo_rx_tag, 0, 2198 &jrxd->rx_dmamap); 2199 if (error != 0) { 2200 device_printf(sc_if->sk_if_dev, 2201 "failed to create jumbo Rx dmamap\n"); 2202 goto jumbo_fail; 2203 } 2204 } 2205 2206 return (0); 2207 2208 jumbo_fail: 2209 sk_dma_jumbo_free(sc_if); 2210 device_printf(sc_if->sk_if_dev, "disabling jumbo frame support due to " 2211 "resource shortage\n"); 2212 sc_if->sk_jumbo_disable = 1; 2213 return (0); 2214 } 2215 2216 static void 2217 sk_dma_free(sc_if) 2218 struct sk_if_softc *sc_if; 2219 { 2220 struct sk_txdesc *txd; 2221 struct sk_rxdesc *rxd; 2222 int i; 2223 2224 /* Tx ring */ 2225 if (sc_if->sk_cdata.sk_tx_ring_tag) { 2226 if (sc_if->sk_rdata.sk_tx_ring_paddr) 2227 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_ring_tag, 2228 sc_if->sk_cdata.sk_tx_ring_map); 2229 if (sc_if->sk_rdata.sk_tx_ring) 2230 bus_dmamem_free(sc_if->sk_cdata.sk_tx_ring_tag, 2231 sc_if->sk_rdata.sk_tx_ring, 2232 sc_if->sk_cdata.sk_tx_ring_map); 2233 sc_if->sk_rdata.sk_tx_ring = NULL; 2234 sc_if->sk_rdata.sk_tx_ring_paddr = 0; 2235 bus_dma_tag_destroy(sc_if->sk_cdata.sk_tx_ring_tag); 2236 sc_if->sk_cdata.sk_tx_ring_tag = NULL; 2237 } 2238 /* Rx ring */ 2239 if (sc_if->sk_cdata.sk_rx_ring_tag) { 2240 if (sc_if->sk_rdata.sk_rx_ring_paddr) 2241 bus_dmamap_unload(sc_if->sk_cdata.sk_rx_ring_tag, 2242 sc_if->sk_cdata.sk_rx_ring_map); 2243 if (sc_if->sk_rdata.sk_rx_ring) 2244 bus_dmamem_free(sc_if->sk_cdata.sk_rx_ring_tag, 2245 sc_if->sk_rdata.sk_rx_ring, 2246 sc_if->sk_cdata.sk_rx_ring_map); 2247 sc_if->sk_rdata.sk_rx_ring = NULL; 2248 sc_if->sk_rdata.sk_rx_ring_paddr = 0; 2249 bus_dma_tag_destroy(sc_if->sk_cdata.sk_rx_ring_tag); 2250 sc_if->sk_cdata.sk_rx_ring_tag = NULL; 2251 } 2252 /* Tx buffers */ 2253 if (sc_if->sk_cdata.sk_tx_tag) { 2254 for (i = 0; i < SK_TX_RING_CNT; i++) { 2255 txd = &sc_if->sk_cdata.sk_txdesc[i]; 2256 if (txd->tx_dmamap) { 2257 bus_dmamap_destroy(sc_if->sk_cdata.sk_tx_tag, 2258 txd->tx_dmamap); 2259 txd->tx_dmamap = NULL; 2260 } 2261 } 2262 bus_dma_tag_destroy(sc_if->sk_cdata.sk_tx_tag); 2263 sc_if->sk_cdata.sk_tx_tag = NULL; 2264 } 2265 /* Rx buffers */ 2266 if (sc_if->sk_cdata.sk_rx_tag) { 2267 for (i = 0; i < SK_RX_RING_CNT; i++) { 2268 rxd = &sc_if->sk_cdata.sk_rxdesc[i]; 2269 if (rxd->rx_dmamap) { 2270 bus_dmamap_destroy(sc_if->sk_cdata.sk_rx_tag, 2271 rxd->rx_dmamap); 2272 rxd->rx_dmamap = NULL; 2273 } 2274 } 2275 if (sc_if->sk_cdata.sk_rx_sparemap) { 2276 bus_dmamap_destroy(sc_if->sk_cdata.sk_rx_tag, 2277 sc_if->sk_cdata.sk_rx_sparemap); 2278 sc_if->sk_cdata.sk_rx_sparemap = NULL; 2279 } 2280 bus_dma_tag_destroy(sc_if->sk_cdata.sk_rx_tag); 2281 sc_if->sk_cdata.sk_rx_tag = NULL; 2282 } 2283 2284 if (sc_if->sk_cdata.sk_parent_tag) { 2285 bus_dma_tag_destroy(sc_if->sk_cdata.sk_parent_tag); 2286 sc_if->sk_cdata.sk_parent_tag = NULL; 2287 } 2288 } 2289 2290 static void 2291 sk_dma_jumbo_free(sc_if) 2292 struct sk_if_softc *sc_if; 2293 { 2294 struct sk_rxdesc *jrxd; 2295 int i; 2296 2297 /* jumbo Rx ring */ 2298 if (sc_if->sk_cdata.sk_jumbo_rx_ring_tag) { 2299 if (sc_if->sk_rdata.sk_jumbo_rx_ring_paddr) 2300 bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 2301 sc_if->sk_cdata.sk_jumbo_rx_ring_map); 2302 if (sc_if->sk_rdata.sk_jumbo_rx_ring) 2303 bus_dmamem_free(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 2304 sc_if->sk_rdata.sk_jumbo_rx_ring, 2305 sc_if->sk_cdata.sk_jumbo_rx_ring_map); 2306 sc_if->sk_rdata.sk_jumbo_rx_ring = NULL; 2307 sc_if->sk_rdata.sk_jumbo_rx_ring_paddr = 0; 2308 bus_dma_tag_destroy(sc_if->sk_cdata.sk_jumbo_rx_ring_tag); 2309 sc_if->sk_cdata.sk_jumbo_rx_ring_tag = NULL; 2310 } 2311 2312 /* jumbo Rx buffers */ 2313 if (sc_if->sk_cdata.sk_jumbo_rx_tag) { 2314 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) { 2315 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i]; 2316 if (jrxd->rx_dmamap) { 2317 bus_dmamap_destroy( 2318 sc_if->sk_cdata.sk_jumbo_rx_tag, 2319 jrxd->rx_dmamap); 2320 jrxd->rx_dmamap = NULL; 2321 } 2322 } 2323 if (sc_if->sk_cdata.sk_jumbo_rx_sparemap) { 2324 bus_dmamap_destroy(sc_if->sk_cdata.sk_jumbo_rx_tag, 2325 sc_if->sk_cdata.sk_jumbo_rx_sparemap); 2326 sc_if->sk_cdata.sk_jumbo_rx_sparemap = NULL; 2327 } 2328 bus_dma_tag_destroy(sc_if->sk_cdata.sk_jumbo_rx_tag); 2329 sc_if->sk_cdata.sk_jumbo_rx_tag = NULL; 2330 } 2331 } 2332 2333 static void 2334 sk_txcksum(ifp, m, f) 2335 struct ifnet *ifp; 2336 struct mbuf *m; 2337 struct sk_tx_desc *f; 2338 { 2339 struct ip *ip; 2340 u_int16_t offset; 2341 u_int8_t *p; 2342 2343 offset = sizeof(struct ip) + ETHER_HDR_LEN; 2344 for(; m && m->m_len == 0; m = m->m_next) 2345 ; 2346 if (m == NULL || m->m_len < ETHER_HDR_LEN) { 2347 if_printf(ifp, "%s: m_len < ETHER_HDR_LEN\n", __func__); 2348 /* checksum may be corrupted */ 2349 goto sendit; 2350 } 2351 if (m->m_len < ETHER_HDR_LEN + sizeof(u_int32_t)) { 2352 if (m->m_len != ETHER_HDR_LEN) { 2353 if_printf(ifp, "%s: m_len != ETHER_HDR_LEN\n", 2354 __func__); 2355 /* checksum may be corrupted */ 2356 goto sendit; 2357 } 2358 for(m = m->m_next; m && m->m_len == 0; m = m->m_next) 2359 ; 2360 if (m == NULL) { 2361 offset = sizeof(struct ip) + ETHER_HDR_LEN; 2362 /* checksum may be corrupted */ 2363 goto sendit; 2364 } 2365 ip = mtod(m, struct ip *); 2366 } else { 2367 p = mtod(m, u_int8_t *); 2368 p += ETHER_HDR_LEN; 2369 ip = (struct ip *)p; 2370 } 2371 offset = (ip->ip_hl << 2) + ETHER_HDR_LEN; 2372 2373 sendit: 2374 f->sk_csum_startval = 0; 2375 f->sk_csum_start = htole32(((offset + m->m_pkthdr.csum_data) & 0xffff) | 2376 (offset << 16)); 2377 } 2378 2379 static int 2380 sk_encap(sc_if, m_head) 2381 struct sk_if_softc *sc_if; 2382 struct mbuf **m_head; 2383 { 2384 struct sk_txdesc *txd; 2385 struct sk_tx_desc *f = NULL; 2386 struct mbuf *m; 2387 bus_dma_segment_t txsegs[SK_MAXTXSEGS]; 2388 u_int32_t cflags, frag, si, sk_ctl; 2389 int error, i, nseg; 2390 2391 SK_IF_LOCK_ASSERT(sc_if); 2392 2393 if ((txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txfreeq)) == NULL) 2394 return (ENOBUFS); 2395 2396 error = bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_tx_tag, 2397 txd->tx_dmamap, *m_head, txsegs, &nseg, 0); 2398 if (error == EFBIG) { 2399 m = m_defrag(*m_head, M_NOWAIT); 2400 if (m == NULL) { 2401 m_freem(*m_head); 2402 *m_head = NULL; 2403 return (ENOMEM); 2404 } 2405 *m_head = m; 2406 error = bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_tx_tag, 2407 txd->tx_dmamap, *m_head, txsegs, &nseg, 0); 2408 if (error != 0) { 2409 m_freem(*m_head); 2410 *m_head = NULL; 2411 return (error); 2412 } 2413 } else if (error != 0) 2414 return (error); 2415 if (nseg == 0) { 2416 m_freem(*m_head); 2417 *m_head = NULL; 2418 return (EIO); 2419 } 2420 if (sc_if->sk_cdata.sk_tx_cnt + nseg >= SK_TX_RING_CNT) { 2421 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap); 2422 return (ENOBUFS); 2423 } 2424 2425 m = *m_head; 2426 if ((m->m_pkthdr.csum_flags & sc_if->sk_ifp->if_hwassist) != 0) 2427 cflags = SK_OPCODE_CSUM; 2428 else 2429 cflags = SK_OPCODE_DEFAULT; 2430 si = frag = sc_if->sk_cdata.sk_tx_prod; 2431 for (i = 0; i < nseg; i++) { 2432 f = &sc_if->sk_rdata.sk_tx_ring[frag]; 2433 f->sk_data_lo = htole32(SK_ADDR_LO(txsegs[i].ds_addr)); 2434 f->sk_data_hi = htole32(SK_ADDR_HI(txsegs[i].ds_addr)); 2435 sk_ctl = txsegs[i].ds_len | cflags; 2436 if (i == 0) { 2437 if (cflags == SK_OPCODE_CSUM) 2438 sk_txcksum(sc_if->sk_ifp, m, f); 2439 sk_ctl |= SK_TXCTL_FIRSTFRAG; 2440 } else 2441 sk_ctl |= SK_TXCTL_OWN; 2442 f->sk_ctl = htole32(sk_ctl); 2443 sc_if->sk_cdata.sk_tx_cnt++; 2444 SK_INC(frag, SK_TX_RING_CNT); 2445 } 2446 sc_if->sk_cdata.sk_tx_prod = frag; 2447 2448 /* set EOF on the last desciptor */ 2449 frag = (frag + SK_TX_RING_CNT - 1) % SK_TX_RING_CNT; 2450 f = &sc_if->sk_rdata.sk_tx_ring[frag]; 2451 f->sk_ctl |= htole32(SK_TXCTL_LASTFRAG | SK_TXCTL_EOF_INTR); 2452 2453 /* turn the first descriptor ownership to NIC */ 2454 f = &sc_if->sk_rdata.sk_tx_ring[si]; 2455 f->sk_ctl |= htole32(SK_TXCTL_OWN); 2456 2457 STAILQ_REMOVE_HEAD(&sc_if->sk_cdata.sk_txfreeq, tx_q); 2458 STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txbusyq, txd, tx_q); 2459 txd->tx_m = m; 2460 2461 /* sync descriptors */ 2462 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap, 2463 BUS_DMASYNC_PREWRITE); 2464 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag, 2465 sc_if->sk_cdata.sk_tx_ring_map, 2466 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2467 2468 return (0); 2469 } 2470 2471 static void 2472 sk_start(ifp) 2473 struct ifnet *ifp; 2474 { 2475 struct sk_if_softc *sc_if; 2476 2477 sc_if = ifp->if_softc; 2478 2479 SK_IF_LOCK(sc_if); 2480 sk_start_locked(ifp); 2481 SK_IF_UNLOCK(sc_if); 2482 2483 return; 2484 } 2485 2486 static void 2487 sk_start_locked(ifp) 2488 struct ifnet *ifp; 2489 { 2490 struct sk_softc *sc; 2491 struct sk_if_softc *sc_if; 2492 struct mbuf *m_head; 2493 int enq; 2494 2495 sc_if = ifp->if_softc; 2496 sc = sc_if->sk_softc; 2497 2498 SK_IF_LOCK_ASSERT(sc_if); 2499 2500 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2501 sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 1; ) { 2502 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2503 if (m_head == NULL) 2504 break; 2505 2506 /* 2507 * Pack the data into the transmit ring. If we 2508 * don't have room, set the OACTIVE flag and wait 2509 * for the NIC to drain the ring. 2510 */ 2511 if (sk_encap(sc_if, &m_head)) { 2512 if (m_head == NULL) 2513 break; 2514 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2515 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2516 break; 2517 } 2518 2519 enq++; 2520 /* 2521 * If there's a BPF listener, bounce a copy of this frame 2522 * to him. 2523 */ 2524 BPF_MTAP(ifp, m_head); 2525 } 2526 2527 if (enq > 0) { 2528 /* Transmit */ 2529 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 2530 2531 /* Set a timeout in case the chip goes out to lunch. */ 2532 sc_if->sk_watchdog_timer = 5; 2533 } 2534 } 2535 2536 2537 static void 2538 sk_watchdog(arg) 2539 void *arg; 2540 { 2541 struct sk_if_softc *sc_if; 2542 struct ifnet *ifp; 2543 2544 ifp = arg; 2545 sc_if = ifp->if_softc; 2546 2547 SK_IF_LOCK_ASSERT(sc_if); 2548 2549 if (sc_if->sk_watchdog_timer == 0 || --sc_if->sk_watchdog_timer) 2550 goto done; 2551 2552 /* 2553 * Reclaim first as there is a possibility of losing Tx completion 2554 * interrupts. 2555 */ 2556 sk_txeof(sc_if); 2557 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 2558 if_printf(sc_if->sk_ifp, "watchdog timeout\n"); 2559 ifp->if_oerrors++; 2560 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2561 sk_init_locked(sc_if); 2562 } 2563 2564 done: 2565 callout_reset(&sc_if->sk_watchdog_ch, hz, sk_watchdog, ifp); 2566 2567 return; 2568 } 2569 2570 static int 2571 skc_shutdown(dev) 2572 device_t dev; 2573 { 2574 struct sk_softc *sc; 2575 2576 sc = device_get_softc(dev); 2577 SK_LOCK(sc); 2578 2579 /* Turn off the 'driver is loaded' LED. */ 2580 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 2581 2582 /* 2583 * Reset the GEnesis controller. Doing this should also 2584 * assert the resets on the attached XMAC(s). 2585 */ 2586 sk_reset(sc); 2587 SK_UNLOCK(sc); 2588 2589 return (0); 2590 } 2591 2592 static int 2593 skc_suspend(dev) 2594 device_t dev; 2595 { 2596 struct sk_softc *sc; 2597 struct sk_if_softc *sc_if0, *sc_if1; 2598 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2599 2600 sc = device_get_softc(dev); 2601 2602 SK_LOCK(sc); 2603 2604 sc_if0 = sc->sk_if[SK_PORT_A]; 2605 sc_if1 = sc->sk_if[SK_PORT_B]; 2606 if (sc_if0 != NULL) 2607 ifp0 = sc_if0->sk_ifp; 2608 if (sc_if1 != NULL) 2609 ifp1 = sc_if1->sk_ifp; 2610 if (ifp0 != NULL) 2611 sk_stop(sc_if0); 2612 if (ifp1 != NULL) 2613 sk_stop(sc_if1); 2614 sc->sk_suspended = 1; 2615 2616 SK_UNLOCK(sc); 2617 2618 return (0); 2619 } 2620 2621 static int 2622 skc_resume(dev) 2623 device_t dev; 2624 { 2625 struct sk_softc *sc; 2626 struct sk_if_softc *sc_if0, *sc_if1; 2627 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2628 2629 sc = device_get_softc(dev); 2630 2631 SK_LOCK(sc); 2632 2633 sc_if0 = sc->sk_if[SK_PORT_A]; 2634 sc_if1 = sc->sk_if[SK_PORT_B]; 2635 if (sc_if0 != NULL) 2636 ifp0 = sc_if0->sk_ifp; 2637 if (sc_if1 != NULL) 2638 ifp1 = sc_if1->sk_ifp; 2639 if (ifp0 != NULL && ifp0->if_flags & IFF_UP) 2640 sk_init_locked(sc_if0); 2641 if (ifp1 != NULL && ifp1->if_flags & IFF_UP) 2642 sk_init_locked(sc_if1); 2643 sc->sk_suspended = 0; 2644 2645 SK_UNLOCK(sc); 2646 2647 return (0); 2648 } 2649 2650 /* 2651 * According to the data sheet from SK-NET GENESIS the hardware can compute 2652 * two Rx checksums at the same time(Each checksum start position is 2653 * programmed in Rx descriptors). However it seems that TCP/UDP checksum 2654 * does not work at least on my Yukon hardware. I tried every possible ways 2655 * to get correct checksum value but couldn't get correct one. So TCP/UDP 2656 * checksum offload was disabled at the moment and only IP checksum offload 2657 * was enabled. 2658 * As nomral IP header size is 20 bytes I can't expect it would give an 2659 * increase in throughput. However it seems it doesn't hurt performance in 2660 * my testing. If there is a more detailed information for checksum secret 2661 * of the hardware in question please contact yongari@FreeBSD.org to add 2662 * TCP/UDP checksum offload support. 2663 */ 2664 static __inline void 2665 sk_rxcksum(ifp, m, csum) 2666 struct ifnet *ifp; 2667 struct mbuf *m; 2668 u_int32_t csum; 2669 { 2670 struct ether_header *eh; 2671 struct ip *ip; 2672 int32_t hlen, len, pktlen; 2673 u_int16_t csum1, csum2, ipcsum; 2674 2675 pktlen = m->m_pkthdr.len; 2676 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip)) 2677 return; 2678 eh = mtod(m, struct ether_header *); 2679 if (eh->ether_type != htons(ETHERTYPE_IP)) 2680 return; 2681 ip = (struct ip *)(eh + 1); 2682 if (ip->ip_v != IPVERSION) 2683 return; 2684 hlen = ip->ip_hl << 2; 2685 pktlen -= sizeof(struct ether_header); 2686 if (hlen < sizeof(struct ip)) 2687 return; 2688 if (ntohs(ip->ip_len) < hlen) 2689 return; 2690 if (ntohs(ip->ip_len) != pktlen) 2691 return; 2692 2693 csum1 = htons(csum & 0xffff); 2694 csum2 = htons((csum >> 16) & 0xffff); 2695 ipcsum = in_addword(csum1, ~csum2 & 0xffff); 2696 /* checksum fixup for IP options */ 2697 len = hlen - sizeof(struct ip); 2698 if (len > 0) { 2699 /* 2700 * If the second checksum value is correct we can compute IP 2701 * checksum with simple math. Unfortunately the second checksum 2702 * value is wrong so we can't verify the checksum from the 2703 * value(It seems there is some magic here to get correct 2704 * value). If the second checksum value is correct it also 2705 * means we can get TCP/UDP checksum) here. However, it still 2706 * needs pseudo header checksum calculation due to hardware 2707 * limitations. 2708 */ 2709 return; 2710 } 2711 m->m_pkthdr.csum_flags = CSUM_IP_CHECKED; 2712 if (ipcsum == 0xffff) 2713 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2714 } 2715 2716 static __inline int 2717 sk_rxvalid(sc, stat, len) 2718 struct sk_softc *sc; 2719 u_int32_t stat, len; 2720 { 2721 2722 if (sc->sk_type == SK_GENESIS) { 2723 if ((stat & XM_RXSTAT_ERRFRAME) == XM_RXSTAT_ERRFRAME || 2724 XM_RXSTAT_BYTES(stat) != len) 2725 return (0); 2726 } else { 2727 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR | 2728 YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | 2729 YU_RXSTAT_JABBER)) != 0 || 2730 (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK || 2731 YU_RXSTAT_BYTES(stat) != len) 2732 return (0); 2733 } 2734 2735 return (1); 2736 } 2737 2738 static void 2739 sk_rxeof(sc_if) 2740 struct sk_if_softc *sc_if; 2741 { 2742 struct sk_softc *sc; 2743 struct mbuf *m; 2744 struct ifnet *ifp; 2745 struct sk_rx_desc *cur_rx; 2746 struct sk_rxdesc *rxd; 2747 int cons, prog; 2748 u_int32_t csum, rxstat, sk_ctl; 2749 2750 sc = sc_if->sk_softc; 2751 ifp = sc_if->sk_ifp; 2752 2753 SK_IF_LOCK_ASSERT(sc_if); 2754 2755 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag, 2756 sc_if->sk_cdata.sk_rx_ring_map, BUS_DMASYNC_POSTREAD); 2757 2758 prog = 0; 2759 for (cons = sc_if->sk_cdata.sk_rx_cons; prog < SK_RX_RING_CNT; 2760 prog++, SK_INC(cons, SK_RX_RING_CNT)) { 2761 cur_rx = &sc_if->sk_rdata.sk_rx_ring[cons]; 2762 sk_ctl = le32toh(cur_rx->sk_ctl); 2763 if ((sk_ctl & SK_RXCTL_OWN) != 0) 2764 break; 2765 rxd = &sc_if->sk_cdata.sk_rxdesc[cons]; 2766 rxstat = le32toh(cur_rx->sk_xmac_rxstat); 2767 2768 if ((sk_ctl & (SK_RXCTL_STATUS_VALID | SK_RXCTL_FIRSTFRAG | 2769 SK_RXCTL_LASTFRAG)) != (SK_RXCTL_STATUS_VALID | 2770 SK_RXCTL_FIRSTFRAG | SK_RXCTL_LASTFRAG) || 2771 SK_RXBYTES(sk_ctl) < SK_MIN_FRAMELEN || 2772 SK_RXBYTES(sk_ctl) > SK_MAX_FRAMELEN || 2773 sk_rxvalid(sc, rxstat, SK_RXBYTES(sk_ctl)) == 0) { 2774 ifp->if_ierrors++; 2775 sk_discard_rxbuf(sc_if, cons); 2776 continue; 2777 } 2778 2779 m = rxd->rx_m; 2780 csum = le32toh(cur_rx->sk_csum); 2781 if (sk_newbuf(sc_if, cons) != 0) { 2782 ifp->if_iqdrops++; 2783 /* reuse old buffer */ 2784 sk_discard_rxbuf(sc_if, cons); 2785 continue; 2786 } 2787 m->m_pkthdr.rcvif = ifp; 2788 m->m_pkthdr.len = m->m_len = SK_RXBYTES(sk_ctl); 2789 ifp->if_ipackets++; 2790 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 2791 sk_rxcksum(ifp, m, csum); 2792 SK_IF_UNLOCK(sc_if); 2793 (*ifp->if_input)(ifp, m); 2794 SK_IF_LOCK(sc_if); 2795 } 2796 2797 if (prog > 0) { 2798 sc_if->sk_cdata.sk_rx_cons = cons; 2799 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag, 2800 sc_if->sk_cdata.sk_rx_ring_map, 2801 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2802 } 2803 } 2804 2805 static void 2806 sk_jumbo_rxeof(sc_if) 2807 struct sk_if_softc *sc_if; 2808 { 2809 struct sk_softc *sc; 2810 struct mbuf *m; 2811 struct ifnet *ifp; 2812 struct sk_rx_desc *cur_rx; 2813 struct sk_rxdesc *jrxd; 2814 int cons, prog; 2815 u_int32_t csum, rxstat, sk_ctl; 2816 2817 sc = sc_if->sk_softc; 2818 ifp = sc_if->sk_ifp; 2819 2820 SK_IF_LOCK_ASSERT(sc_if); 2821 2822 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 2823 sc_if->sk_cdata.sk_jumbo_rx_ring_map, BUS_DMASYNC_POSTREAD); 2824 2825 prog = 0; 2826 for (cons = sc_if->sk_cdata.sk_jumbo_rx_cons; 2827 prog < SK_JUMBO_RX_RING_CNT; 2828 prog++, SK_INC(cons, SK_JUMBO_RX_RING_CNT)) { 2829 cur_rx = &sc_if->sk_rdata.sk_jumbo_rx_ring[cons]; 2830 sk_ctl = le32toh(cur_rx->sk_ctl); 2831 if ((sk_ctl & SK_RXCTL_OWN) != 0) 2832 break; 2833 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[cons]; 2834 rxstat = le32toh(cur_rx->sk_xmac_rxstat); 2835 2836 if ((sk_ctl & (SK_RXCTL_STATUS_VALID | SK_RXCTL_FIRSTFRAG | 2837 SK_RXCTL_LASTFRAG)) != (SK_RXCTL_STATUS_VALID | 2838 SK_RXCTL_FIRSTFRAG | SK_RXCTL_LASTFRAG) || 2839 SK_RXBYTES(sk_ctl) < SK_MIN_FRAMELEN || 2840 SK_RXBYTES(sk_ctl) > SK_JUMBO_FRAMELEN || 2841 sk_rxvalid(sc, rxstat, SK_RXBYTES(sk_ctl)) == 0) { 2842 ifp->if_ierrors++; 2843 sk_discard_jumbo_rxbuf(sc_if, cons); 2844 continue; 2845 } 2846 2847 m = jrxd->rx_m; 2848 csum = le32toh(cur_rx->sk_csum); 2849 if (sk_jumbo_newbuf(sc_if, cons) != 0) { 2850 ifp->if_iqdrops++; 2851 /* reuse old buffer */ 2852 sk_discard_jumbo_rxbuf(sc_if, cons); 2853 continue; 2854 } 2855 m->m_pkthdr.rcvif = ifp; 2856 m->m_pkthdr.len = m->m_len = SK_RXBYTES(sk_ctl); 2857 ifp->if_ipackets++; 2858 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 2859 sk_rxcksum(ifp, m, csum); 2860 SK_IF_UNLOCK(sc_if); 2861 (*ifp->if_input)(ifp, m); 2862 SK_IF_LOCK(sc_if); 2863 } 2864 2865 if (prog > 0) { 2866 sc_if->sk_cdata.sk_jumbo_rx_cons = cons; 2867 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 2868 sc_if->sk_cdata.sk_jumbo_rx_ring_map, 2869 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2870 } 2871 } 2872 2873 static void 2874 sk_txeof(sc_if) 2875 struct sk_if_softc *sc_if; 2876 { 2877 struct sk_txdesc *txd; 2878 struct sk_tx_desc *cur_tx; 2879 struct ifnet *ifp; 2880 u_int32_t idx, sk_ctl; 2881 2882 ifp = sc_if->sk_ifp; 2883 2884 txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txbusyq); 2885 if (txd == NULL) 2886 return; 2887 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag, 2888 sc_if->sk_cdata.sk_tx_ring_map, BUS_DMASYNC_POSTREAD); 2889 /* 2890 * Go through our tx ring and free mbufs for those 2891 * frames that have been sent. 2892 */ 2893 for (idx = sc_if->sk_cdata.sk_tx_cons;; SK_INC(idx, SK_TX_RING_CNT)) { 2894 if (sc_if->sk_cdata.sk_tx_cnt <= 0) 2895 break; 2896 cur_tx = &sc_if->sk_rdata.sk_tx_ring[idx]; 2897 sk_ctl = le32toh(cur_tx->sk_ctl); 2898 if (sk_ctl & SK_TXCTL_OWN) 2899 break; 2900 sc_if->sk_cdata.sk_tx_cnt--; 2901 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2902 if ((sk_ctl & SK_TXCTL_LASTFRAG) == 0) 2903 continue; 2904 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap, 2905 BUS_DMASYNC_POSTWRITE); 2906 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap); 2907 2908 ifp->if_opackets++; 2909 m_freem(txd->tx_m); 2910 txd->tx_m = NULL; 2911 STAILQ_REMOVE_HEAD(&sc_if->sk_cdata.sk_txbusyq, tx_q); 2912 STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txfreeq, txd, tx_q); 2913 txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txbusyq); 2914 } 2915 sc_if->sk_cdata.sk_tx_cons = idx; 2916 sc_if->sk_watchdog_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0; 2917 2918 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag, 2919 sc_if->sk_cdata.sk_tx_ring_map, 2920 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2921 } 2922 2923 static void 2924 sk_tick(xsc_if) 2925 void *xsc_if; 2926 { 2927 struct sk_if_softc *sc_if; 2928 struct mii_data *mii; 2929 struct ifnet *ifp; 2930 int i; 2931 2932 sc_if = xsc_if; 2933 ifp = sc_if->sk_ifp; 2934 mii = device_get_softc(sc_if->sk_miibus); 2935 2936 if (!(ifp->if_flags & IFF_UP)) 2937 return; 2938 2939 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2940 sk_intr_bcom(sc_if); 2941 return; 2942 } 2943 2944 /* 2945 * According to SysKonnect, the correct way to verify that 2946 * the link has come back up is to poll bit 0 of the GPIO 2947 * register three times. This pin has the signal from the 2948 * link_sync pin connected to it; if we read the same link 2949 * state 3 times in a row, we know the link is up. 2950 */ 2951 for (i = 0; i < 3; i++) { 2952 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 2953 break; 2954 } 2955 2956 if (i != 3) { 2957 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2958 return; 2959 } 2960 2961 /* Turn the GP0 interrupt back on. */ 2962 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2963 SK_XM_READ_2(sc_if, XM_ISR); 2964 mii_tick(mii); 2965 callout_stop(&sc_if->sk_tick_ch); 2966 } 2967 2968 static void 2969 sk_yukon_tick(xsc_if) 2970 void *xsc_if; 2971 { 2972 struct sk_if_softc *sc_if; 2973 struct mii_data *mii; 2974 2975 sc_if = xsc_if; 2976 mii = device_get_softc(sc_if->sk_miibus); 2977 2978 mii_tick(mii); 2979 callout_reset(&sc_if->sk_tick_ch, hz, sk_yukon_tick, sc_if); 2980 } 2981 2982 static void 2983 sk_intr_bcom(sc_if) 2984 struct sk_if_softc *sc_if; 2985 { 2986 struct mii_data *mii; 2987 struct ifnet *ifp; 2988 int status; 2989 mii = device_get_softc(sc_if->sk_miibus); 2990 ifp = sc_if->sk_ifp; 2991 2992 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2993 2994 /* 2995 * Read the PHY interrupt register to make sure 2996 * we clear any pending interrupts. 2997 */ 2998 status = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 2999 3000 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3001 sk_init_xmac(sc_if); 3002 return; 3003 } 3004 3005 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 3006 int lstat; 3007 lstat = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 3008 BRGPHY_MII_AUXSTS); 3009 3010 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 3011 mii_mediachg(mii); 3012 /* Turn off the link LED. */ 3013 SK_IF_WRITE_1(sc_if, 0, 3014 SK_LINKLED1_CTL, SK_LINKLED_OFF); 3015 sc_if->sk_link = 0; 3016 } else if (status & BRGPHY_ISR_LNK_CHG) { 3017 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 3018 BRGPHY_MII_IMR, 0xFF00); 3019 mii_tick(mii); 3020 sc_if->sk_link = 1; 3021 /* Turn on the link LED. */ 3022 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 3023 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 3024 SK_LINKLED_BLINK_OFF); 3025 } else { 3026 mii_tick(mii); 3027 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 3028 } 3029 } 3030 3031 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 3032 3033 return; 3034 } 3035 3036 static void 3037 sk_intr_xmac(sc_if) 3038 struct sk_if_softc *sc_if; 3039 { 3040 struct sk_softc *sc; 3041 u_int16_t status; 3042 3043 sc = sc_if->sk_softc; 3044 status = SK_XM_READ_2(sc_if, XM_ISR); 3045 3046 /* 3047 * Link has gone down. Start MII tick timeout to 3048 * watch for link resync. 3049 */ 3050 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 3051 if (status & XM_ISR_GP0_SET) { 3052 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 3053 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 3054 } 3055 3056 if (status & XM_ISR_AUTONEG_DONE) { 3057 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 3058 } 3059 } 3060 3061 if (status & XM_IMR_TX_UNDERRUN) 3062 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 3063 3064 if (status & XM_IMR_RX_OVERRUN) 3065 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 3066 3067 status = SK_XM_READ_2(sc_if, XM_ISR); 3068 3069 return; 3070 } 3071 3072 static void 3073 sk_intr_yukon(sc_if) 3074 struct sk_if_softc *sc_if; 3075 { 3076 u_int8_t status; 3077 3078 status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR); 3079 /* RX overrun */ 3080 if ((status & SK_GMAC_INT_RX_OVER) != 0) { 3081 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 3082 SK_RFCTL_RX_FIFO_OVER); 3083 } 3084 /* TX underrun */ 3085 if ((status & SK_GMAC_INT_TX_UNDER) != 0) { 3086 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 3087 SK_TFCTL_TX_FIFO_UNDER); 3088 } 3089 } 3090 3091 static void 3092 sk_intr(xsc) 3093 void *xsc; 3094 { 3095 struct sk_softc *sc = xsc; 3096 struct sk_if_softc *sc_if0, *sc_if1; 3097 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 3098 u_int32_t status; 3099 3100 SK_LOCK(sc); 3101 3102 status = CSR_READ_4(sc, SK_ISSR); 3103 if (status == 0 || status == 0xffffffff || sc->sk_suspended) 3104 goto done_locked; 3105 3106 sc_if0 = sc->sk_if[SK_PORT_A]; 3107 sc_if1 = sc->sk_if[SK_PORT_B]; 3108 3109 if (sc_if0 != NULL) 3110 ifp0 = sc_if0->sk_ifp; 3111 if (sc_if1 != NULL) 3112 ifp1 = sc_if1->sk_ifp; 3113 3114 for (; (status &= sc->sk_intrmask) != 0;) { 3115 /* Handle receive interrupts first. */ 3116 if (status & SK_ISR_RX1_EOF) { 3117 if (ifp0->if_mtu > SK_MAX_FRAMELEN) 3118 sk_jumbo_rxeof(sc_if0); 3119 else 3120 sk_rxeof(sc_if0); 3121 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 3122 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 3123 } 3124 if (status & SK_ISR_RX2_EOF) { 3125 if (ifp1->if_mtu > SK_MAX_FRAMELEN) 3126 sk_jumbo_rxeof(sc_if1); 3127 else 3128 sk_rxeof(sc_if1); 3129 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 3130 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 3131 } 3132 3133 /* Then transmit interrupts. */ 3134 if (status & SK_ISR_TX1_S_EOF) { 3135 sk_txeof(sc_if0); 3136 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, SK_TXBMU_CLR_IRQ_EOF); 3137 } 3138 if (status & SK_ISR_TX2_S_EOF) { 3139 sk_txeof(sc_if1); 3140 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, SK_TXBMU_CLR_IRQ_EOF); 3141 } 3142 3143 /* Then MAC interrupts. */ 3144 if (status & SK_ISR_MAC1 && 3145 ifp0->if_drv_flags & IFF_DRV_RUNNING) { 3146 if (sc->sk_type == SK_GENESIS) 3147 sk_intr_xmac(sc_if0); 3148 else 3149 sk_intr_yukon(sc_if0); 3150 } 3151 3152 if (status & SK_ISR_MAC2 && 3153 ifp1->if_drv_flags & IFF_DRV_RUNNING) { 3154 if (sc->sk_type == SK_GENESIS) 3155 sk_intr_xmac(sc_if1); 3156 else 3157 sk_intr_yukon(sc_if1); 3158 } 3159 3160 if (status & SK_ISR_EXTERNAL_REG) { 3161 if (ifp0 != NULL && 3162 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 3163 sk_intr_bcom(sc_if0); 3164 if (ifp1 != NULL && 3165 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 3166 sk_intr_bcom(sc_if1); 3167 } 3168 status = CSR_READ_4(sc, SK_ISSR); 3169 } 3170 3171 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 3172 3173 if (ifp0 != NULL && !IFQ_DRV_IS_EMPTY(&ifp0->if_snd)) 3174 sk_start_locked(ifp0); 3175 if (ifp1 != NULL && !IFQ_DRV_IS_EMPTY(&ifp1->if_snd)) 3176 sk_start_locked(ifp1); 3177 3178 done_locked: 3179 SK_UNLOCK(sc); 3180 } 3181 3182 static void 3183 sk_init_xmac(sc_if) 3184 struct sk_if_softc *sc_if; 3185 { 3186 struct sk_softc *sc; 3187 struct ifnet *ifp; 3188 u_int16_t eaddr[(ETHER_ADDR_LEN+1)/2]; 3189 static const struct sk_bcom_hack bhack[] = { 3190 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 3191 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 3192 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 3193 { 0, 0 } }; 3194 3195 SK_IF_LOCK_ASSERT(sc_if); 3196 3197 sc = sc_if->sk_softc; 3198 ifp = sc_if->sk_ifp; 3199 3200 /* Unreset the XMAC. */ 3201 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 3202 DELAY(1000); 3203 3204 /* Reset the XMAC's internal state. */ 3205 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 3206 3207 /* Save the XMAC II revision */ 3208 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 3209 3210 /* 3211 * Perform additional initialization for external PHYs, 3212 * namely for the 1000baseTX cards that use the XMAC's 3213 * GMII mode. 3214 */ 3215 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 3216 int i = 0; 3217 u_int32_t val; 3218 3219 /* Take PHY out of reset. */ 3220 val = sk_win_read_4(sc, SK_GPIO); 3221 if (sc_if->sk_port == SK_PORT_A) 3222 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 3223 else 3224 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 3225 sk_win_write_4(sc, SK_GPIO, val); 3226 3227 /* Enable GMII mode on the XMAC. */ 3228 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 3229 3230 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 3231 BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET); 3232 DELAY(10000); 3233 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 3234 BRGPHY_MII_IMR, 0xFFF0); 3235 3236 /* 3237 * Early versions of the BCM5400 apparently have 3238 * a bug that requires them to have their reserved 3239 * registers initialized to some magic values. I don't 3240 * know what the numbers do, I'm just the messenger. 3241 */ 3242 if (sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 0x03) 3243 == 0x6041) { 3244 while(bhack[i].reg) { 3245 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 3246 bhack[i].reg, bhack[i].val); 3247 i++; 3248 } 3249 } 3250 } 3251 3252 /* Set station address */ 3253 bcopy(IF_LLADDR(sc_if->sk_ifp), eaddr, ETHER_ADDR_LEN); 3254 SK_XM_WRITE_2(sc_if, XM_PAR0, eaddr[0]); 3255 SK_XM_WRITE_2(sc_if, XM_PAR1, eaddr[1]); 3256 SK_XM_WRITE_2(sc_if, XM_PAR2, eaddr[2]); 3257 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 3258 3259 if (ifp->if_flags & IFF_BROADCAST) { 3260 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 3261 } else { 3262 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 3263 } 3264 3265 /* We don't need the FCS appended to the packet. */ 3266 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 3267 3268 /* We want short frames padded to 60 bytes. */ 3269 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 3270 3271 /* 3272 * Enable the reception of all error frames. This is is 3273 * a necessary evil due to the design of the XMAC. The 3274 * XMAC's receive FIFO is only 8K in size, however jumbo 3275 * frames can be up to 9000 bytes in length. When bad 3276 * frame filtering is enabled, the XMAC's RX FIFO operates 3277 * in 'store and forward' mode. For this to work, the 3278 * entire frame has to fit into the FIFO, but that means 3279 * that jumbo frames larger than 8192 bytes will be 3280 * truncated. Disabling all bad frame filtering causes 3281 * the RX FIFO to operate in streaming mode, in which 3282 * case the XMAC will start transfering frames out of the 3283 * RX FIFO as soon as the FIFO threshold is reached. 3284 */ 3285 if (ifp->if_mtu > SK_MAX_FRAMELEN) { 3286 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 3287 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 3288 XM_MODE_RX_INRANGELEN); 3289 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 3290 } else 3291 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 3292 3293 /* 3294 * Bump up the transmit threshold. This helps hold off transmit 3295 * underruns when we're blasting traffic from both ports at once. 3296 */ 3297 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 3298 3299 /* Set Rx filter */ 3300 sk_rxfilter_genesis(sc_if); 3301 3302 /* Clear and enable interrupts */ 3303 SK_XM_READ_2(sc_if, XM_ISR); 3304 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 3305 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 3306 else 3307 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 3308 3309 /* Configure MAC arbiter */ 3310 switch(sc_if->sk_xmac_rev) { 3311 case XM_XMAC_REV_B2: 3312 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 3313 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 3314 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 3315 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 3316 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 3317 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 3318 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 3319 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 3320 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 3321 break; 3322 case XM_XMAC_REV_C1: 3323 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 3324 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 3325 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 3326 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 3327 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 3328 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 3329 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 3330 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 3331 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 3332 break; 3333 default: 3334 break; 3335 } 3336 sk_win_write_2(sc, SK_MACARB_CTL, 3337 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 3338 3339 sc_if->sk_link = 1; 3340 3341 return; 3342 } 3343 3344 static void 3345 sk_init_yukon(sc_if) 3346 struct sk_if_softc *sc_if; 3347 { 3348 u_int32_t phy, v; 3349 u_int16_t reg; 3350 struct sk_softc *sc; 3351 struct ifnet *ifp; 3352 u_int8_t *eaddr; 3353 int i; 3354 3355 SK_IF_LOCK_ASSERT(sc_if); 3356 3357 sc = sc_if->sk_softc; 3358 ifp = sc_if->sk_ifp; 3359 3360 if (sc->sk_type == SK_YUKON_LITE && 3361 sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 3362 /* 3363 * Workaround code for COMA mode, set PHY reset. 3364 * Otherwise it will not correctly take chip out of 3365 * powerdown (coma) 3366 */ 3367 v = sk_win_read_4(sc, SK_GPIO); 3368 v |= SK_GPIO_DIR9 | SK_GPIO_DAT9; 3369 sk_win_write_4(sc, SK_GPIO, v); 3370 } 3371 3372 /* GMAC and GPHY Reset */ 3373 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 3374 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 3375 DELAY(1000); 3376 3377 if (sc->sk_type == SK_YUKON_LITE && 3378 sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 3379 /* 3380 * Workaround code for COMA mode, clear PHY reset 3381 */ 3382 v = sk_win_read_4(sc, SK_GPIO); 3383 v |= SK_GPIO_DIR9; 3384 v &= ~SK_GPIO_DAT9; 3385 sk_win_write_4(sc, SK_GPIO, v); 3386 } 3387 3388 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 3389 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 3390 3391 if (sc->sk_coppertype) 3392 phy |= SK_GPHY_COPPER; 3393 else 3394 phy |= SK_GPHY_FIBER; 3395 3396 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 3397 DELAY(1000); 3398 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 3399 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 3400 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 3401 3402 /* unused read of the interrupt source register */ 3403 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 3404 3405 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 3406 3407 /* MIB Counter Clear Mode set */ 3408 reg |= YU_PAR_MIB_CLR; 3409 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 3410 3411 /* MIB Counter Clear Mode clear */ 3412 reg &= ~YU_PAR_MIB_CLR; 3413 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 3414 3415 /* receive control reg */ 3416 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR); 3417 3418 /* transmit parameter register */ 3419 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 3420 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 3421 3422 /* serial mode register */ 3423 reg = YU_SMR_DATA_BLIND(0x1c) | YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e); 3424 if (ifp->if_mtu > SK_MAX_FRAMELEN) 3425 reg |= YU_SMR_MFL_JUMBO; 3426 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg); 3427 3428 /* Setup Yukon's station address */ 3429 eaddr = IF_LLADDR(sc_if->sk_ifp); 3430 for (i = 0; i < 3; i++) 3431 SK_YU_WRITE_2(sc_if, SK_MAC0_0 + i * 4, 3432 eaddr[i * 2] | eaddr[i * 2 + 1] << 8); 3433 /* Set GMAC source address of flow control. */ 3434 for (i = 0; i < 3; i++) 3435 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 3436 eaddr[i * 2] | eaddr[i * 2 + 1] << 8); 3437 /* Set GMAC virtual address. */ 3438 for (i = 0; i < 3; i++) 3439 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, 3440 eaddr[i * 2] | eaddr[i * 2 + 1] << 8); 3441 3442 /* Set Rx filter */ 3443 sk_rxfilter_yukon(sc_if); 3444 3445 /* enable interrupt mask for counter overflows */ 3446 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 3447 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 3448 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 3449 3450 /* Configure RX MAC FIFO Flush Mask */ 3451 v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR | 3452 YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT | 3453 YU_RXSTAT_JABBER; 3454 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v); 3455 3456 /* Disable RX MAC FIFO Flush for YUKON-Lite Rev. A0 only */ 3457 if (sc->sk_type == SK_YUKON_LITE && sc->sk_rev == SK_YUKON_LITE_REV_A0) 3458 v = SK_TFCTL_OPERATION_ON; 3459 else 3460 v = SK_TFCTL_OPERATION_ON | SK_RFCTL_FIFO_FLUSH_ON; 3461 /* Configure RX MAC FIFO */ 3462 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 3463 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, v); 3464 3465 /* Increase flush threshould to 64 bytes */ 3466 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD, 3467 SK_RFCTL_FIFO_THRESHOLD + 1); 3468 3469 /* Configure TX MAC FIFO */ 3470 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 3471 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 3472 } 3473 3474 /* 3475 * Note that to properly initialize any part of the GEnesis chip, 3476 * you first have to take it out of reset mode. 3477 */ 3478 static void 3479 sk_init(xsc) 3480 void *xsc; 3481 { 3482 struct sk_if_softc *sc_if = xsc; 3483 3484 SK_IF_LOCK(sc_if); 3485 sk_init_locked(sc_if); 3486 SK_IF_UNLOCK(sc_if); 3487 3488 return; 3489 } 3490 3491 static void 3492 sk_init_locked(sc_if) 3493 struct sk_if_softc *sc_if; 3494 { 3495 struct sk_softc *sc; 3496 struct ifnet *ifp; 3497 struct mii_data *mii; 3498 u_int16_t reg; 3499 u_int32_t imr; 3500 int error; 3501 3502 SK_IF_LOCK_ASSERT(sc_if); 3503 3504 ifp = sc_if->sk_ifp; 3505 sc = sc_if->sk_softc; 3506 mii = device_get_softc(sc_if->sk_miibus); 3507 3508 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3509 return; 3510 3511 /* Cancel pending I/O and free all RX/TX buffers. */ 3512 sk_stop(sc_if); 3513 3514 if (sc->sk_type == SK_GENESIS) { 3515 /* Configure LINK_SYNC LED */ 3516 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 3517 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 3518 SK_LINKLED_LINKSYNC_ON); 3519 3520 /* Configure RX LED */ 3521 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 3522 SK_RXLEDCTL_COUNTER_START); 3523 3524 /* Configure TX LED */ 3525 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 3526 SK_TXLEDCTL_COUNTER_START); 3527 } 3528 3529 /* 3530 * Configure descriptor poll timer 3531 * 3532 * SK-NET GENESIS data sheet says that possibility of losing Start 3533 * transmit command due to CPU/cache related interim storage problems 3534 * under certain conditions. The document recommends a polling 3535 * mechanism to send a Start transmit command to initiate transfer 3536 * of ready descriptors regulary. To cope with this issue sk(4) now 3537 * enables descriptor poll timer to initiate descriptor processing 3538 * periodically as defined by SK_DPT_TIMER_MAX. However sk(4) still 3539 * issue SK_TXBMU_TX_START to Tx BMU to get fast execution of Tx 3540 * command instead of waiting for next descriptor polling time. 3541 * The same rule may apply to Rx side too but it seems that is not 3542 * needed at the moment. 3543 * Since sk(4) uses descriptor polling as a last resort there is no 3544 * need to set smaller polling time than maximum allowable one. 3545 */ 3546 SK_IF_WRITE_4(sc_if, 0, SK_DPT_INIT, SK_DPT_TIMER_MAX); 3547 3548 /* Configure I2C registers */ 3549 3550 /* Configure XMAC(s) */ 3551 switch (sc->sk_type) { 3552 case SK_GENESIS: 3553 sk_init_xmac(sc_if); 3554 break; 3555 case SK_YUKON: 3556 case SK_YUKON_LITE: 3557 case SK_YUKON_LP: 3558 sk_init_yukon(sc_if); 3559 break; 3560 } 3561 mii_mediachg(mii); 3562 3563 if (sc->sk_type == SK_GENESIS) { 3564 /* Configure MAC FIFOs */ 3565 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 3566 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 3567 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 3568 3569 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 3570 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 3571 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 3572 } 3573 3574 /* Configure transmit arbiter(s) */ 3575 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 3576 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 3577 3578 /* Configure RAMbuffers */ 3579 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 3580 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 3581 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 3582 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 3583 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 3584 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 3585 3586 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 3587 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 3588 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 3589 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 3590 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 3591 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 3592 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 3593 3594 /* Configure BMUs */ 3595 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 3596 if (ifp->if_mtu > SK_MAX_FRAMELEN) { 3597 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 3598 SK_ADDR_LO(SK_JUMBO_RX_RING_ADDR(sc_if, 0))); 3599 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 3600 SK_ADDR_HI(SK_JUMBO_RX_RING_ADDR(sc_if, 0))); 3601 } else { 3602 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 3603 SK_ADDR_LO(SK_RX_RING_ADDR(sc_if, 0))); 3604 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 3605 SK_ADDR_HI(SK_RX_RING_ADDR(sc_if, 0))); 3606 } 3607 3608 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 3609 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 3610 SK_ADDR_LO(SK_TX_RING_ADDR(sc_if, 0))); 3611 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 3612 SK_ADDR_HI(SK_TX_RING_ADDR(sc_if, 0))); 3613 3614 /* Init descriptors */ 3615 if (ifp->if_mtu > SK_MAX_FRAMELEN) 3616 error = sk_init_jumbo_rx_ring(sc_if); 3617 else 3618 error = sk_init_rx_ring(sc_if); 3619 if (error != 0) { 3620 device_printf(sc_if->sk_if_dev, 3621 "initialization failed: no memory for rx buffers\n"); 3622 sk_stop(sc_if); 3623 return; 3624 } 3625 sk_init_tx_ring(sc_if); 3626 3627 /* Set interrupt moderation if changed via sysctl. */ 3628 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 3629 if (imr != SK_IM_USECS(sc->sk_int_mod, sc->sk_int_ticks)) { 3630 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod, 3631 sc->sk_int_ticks)); 3632 if (bootverbose) 3633 device_printf(sc_if->sk_if_dev, 3634 "interrupt moderation is %d us.\n", 3635 sc->sk_int_mod); 3636 } 3637 3638 /* Configure interrupt handling */ 3639 CSR_READ_4(sc, SK_ISSR); 3640 if (sc_if->sk_port == SK_PORT_A) 3641 sc->sk_intrmask |= SK_INTRS1; 3642 else 3643 sc->sk_intrmask |= SK_INTRS2; 3644 3645 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 3646 3647 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 3648 3649 /* Start BMUs. */ 3650 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 3651 3652 switch(sc->sk_type) { 3653 case SK_GENESIS: 3654 /* Enable XMACs TX and RX state machines */ 3655 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 3656 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 3657 break; 3658 case SK_YUKON: 3659 case SK_YUKON_LITE: 3660 case SK_YUKON_LP: 3661 reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 3662 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 3663 #if 0 3664 /* XXX disable 100Mbps and full duplex mode? */ 3665 reg &= ~(YU_GPCR_SPEED | YU_GPCR_DPLX_DIS); 3666 #endif 3667 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 3668 } 3669 3670 /* Activate descriptor polling timer */ 3671 SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_START); 3672 /* start transfer of Tx descriptors */ 3673 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 3674 3675 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3676 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3677 3678 switch (sc->sk_type) { 3679 case SK_YUKON: 3680 case SK_YUKON_LITE: 3681 case SK_YUKON_LP: 3682 callout_reset(&sc_if->sk_tick_ch, hz, sk_yukon_tick, sc_if); 3683 break; 3684 } 3685 3686 callout_reset(&sc_if->sk_watchdog_ch, hz, sk_watchdog, ifp); 3687 3688 return; 3689 } 3690 3691 static void 3692 sk_stop(sc_if) 3693 struct sk_if_softc *sc_if; 3694 { 3695 int i; 3696 struct sk_softc *sc; 3697 struct sk_txdesc *txd; 3698 struct sk_rxdesc *rxd; 3699 struct sk_rxdesc *jrxd; 3700 struct ifnet *ifp; 3701 u_int32_t val; 3702 3703 SK_IF_LOCK_ASSERT(sc_if); 3704 sc = sc_if->sk_softc; 3705 ifp = sc_if->sk_ifp; 3706 3707 callout_stop(&sc_if->sk_tick_ch); 3708 callout_stop(&sc_if->sk_watchdog_ch); 3709 3710 /* stop Tx descriptor polling timer */ 3711 SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP); 3712 /* stop transfer of Tx descriptors */ 3713 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_STOP); 3714 for (i = 0; i < SK_TIMEOUT; i++) { 3715 val = CSR_READ_4(sc, sc_if->sk_tx_bmu); 3716 if ((val & SK_TXBMU_TX_STOP) == 0) 3717 break; 3718 DELAY(1); 3719 } 3720 if (i == SK_TIMEOUT) 3721 device_printf(sc_if->sk_if_dev, 3722 "can not stop transfer of Tx descriptor\n"); 3723 /* stop transfer of Rx descriptors */ 3724 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_STOP); 3725 for (i = 0; i < SK_TIMEOUT; i++) { 3726 val = SK_IF_READ_4(sc_if, 0, SK_RXQ1_BMU_CSR); 3727 if ((val & SK_RXBMU_RX_STOP) == 0) 3728 break; 3729 DELAY(1); 3730 } 3731 if (i == SK_TIMEOUT) 3732 device_printf(sc_if->sk_if_dev, 3733 "can not stop transfer of Rx descriptor\n"); 3734 3735 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 3736 /* Put PHY back into reset. */ 3737 val = sk_win_read_4(sc, SK_GPIO); 3738 if (sc_if->sk_port == SK_PORT_A) { 3739 val |= SK_GPIO_DIR0; 3740 val &= ~SK_GPIO_DAT0; 3741 } else { 3742 val |= SK_GPIO_DIR2; 3743 val &= ~SK_GPIO_DAT2; 3744 } 3745 sk_win_write_4(sc, SK_GPIO, val); 3746 } 3747 3748 /* Turn off various components of this interface. */ 3749 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 3750 switch (sc->sk_type) { 3751 case SK_GENESIS: 3752 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_RESET); 3753 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 3754 break; 3755 case SK_YUKON: 3756 case SK_YUKON_LITE: 3757 case SK_YUKON_LP: 3758 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 3759 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 3760 break; 3761 } 3762 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 3763 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 3764 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 3765 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 3766 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 3767 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 3768 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 3769 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 3770 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 3771 3772 /* Disable interrupts */ 3773 if (sc_if->sk_port == SK_PORT_A) 3774 sc->sk_intrmask &= ~SK_INTRS1; 3775 else 3776 sc->sk_intrmask &= ~SK_INTRS2; 3777 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 3778 3779 SK_XM_READ_2(sc_if, XM_ISR); 3780 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 3781 3782 /* Free RX and TX mbufs still in the queues. */ 3783 for (i = 0; i < SK_RX_RING_CNT; i++) { 3784 rxd = &sc_if->sk_cdata.sk_rxdesc[i]; 3785 if (rxd->rx_m != NULL) { 3786 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag, 3787 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3788 bus_dmamap_unload(sc_if->sk_cdata.sk_rx_tag, 3789 rxd->rx_dmamap); 3790 m_freem(rxd->rx_m); 3791 rxd->rx_m = NULL; 3792 } 3793 } 3794 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) { 3795 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i]; 3796 if (jrxd->rx_m != NULL) { 3797 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag, 3798 jrxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3799 bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_tag, 3800 jrxd->rx_dmamap); 3801 m_freem(jrxd->rx_m); 3802 jrxd->rx_m = NULL; 3803 } 3804 } 3805 for (i = 0; i < SK_TX_RING_CNT; i++) { 3806 txd = &sc_if->sk_cdata.sk_txdesc[i]; 3807 if (txd->tx_m != NULL) { 3808 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag, 3809 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 3810 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag, 3811 txd->tx_dmamap); 3812 m_freem(txd->tx_m); 3813 txd->tx_m = NULL; 3814 } 3815 } 3816 3817 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING|IFF_DRV_OACTIVE); 3818 3819 return; 3820 } 3821 3822 static int 3823 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3824 { 3825 int error, value; 3826 3827 if (!arg1) 3828 return (EINVAL); 3829 value = *(int *)arg1; 3830 error = sysctl_handle_int(oidp, &value, 0, req); 3831 if (error || !req->newptr) 3832 return (error); 3833 if (value < low || value > high) 3834 return (EINVAL); 3835 *(int *)arg1 = value; 3836 return (0); 3837 } 3838 3839 static int 3840 sysctl_hw_sk_int_mod(SYSCTL_HANDLER_ARGS) 3841 { 3842 return (sysctl_int_range(oidp, arg1, arg2, req, SK_IM_MIN, SK_IM_MAX)); 3843 } 3844