1 /* $OpenBSD: if_sk.c,v 2.33 2003/08/12 05:23:06 nate Exp $ */ 2 3 /*- 4 * SPDX-License-Identifier: BSD-4-Clause 5 * 6 * Copyright (c) 1997, 1998, 1999, 2000 7 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Bill Paul. 20 * 4. Neither the name of the author nor the names of any co-contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 34 * THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 /*- 37 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 38 * 39 * Permission to use, copy, modify, and distribute this software for any 40 * purpose with or without fee is hereby granted, provided that the above 41 * copyright notice and this permission notice appear in all copies. 42 * 43 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 44 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 45 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 46 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 47 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 48 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 49 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 50 */ 51 52 #include <sys/cdefs.h> 53 /* 54 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 55 * the SK-984x series adapters, both single port and dual port. 56 * References: 57 * The XaQti XMAC II datasheet, 58 * https://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 59 * The SysKonnect GEnesis manual, http://www.syskonnect.com 60 * 61 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the 62 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 63 * convenience to others until Vitesse corrects this problem: 64 * 65 * https://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 66 * 67 * Written by Bill Paul <wpaul@ee.columbia.edu> 68 * Department of Electrical Engineering 69 * Columbia University, New York City 70 */ 71 /* 72 * The SysKonnect gigabit ethernet adapters consist of two main 73 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 74 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 75 * components and a PHY while the GEnesis controller provides a PCI 76 * interface with DMA support. Each card may have between 512K and 77 * 2MB of SRAM on board depending on the configuration. 78 * 79 * The SysKonnect GEnesis controller can have either one or two XMAC 80 * chips connected to it, allowing single or dual port NIC configurations. 81 * SysKonnect has the distinction of being the only vendor on the market 82 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 83 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 84 * XMAC registers. This driver takes advantage of these features to allow 85 * both XMACs to operate as independent interfaces. 86 */ 87 88 #include <sys/param.h> 89 #include <sys/systm.h> 90 #include <sys/bus.h> 91 #include <sys/endian.h> 92 #include <sys/mbuf.h> 93 #include <sys/malloc.h> 94 #include <sys/kernel.h> 95 #include <sys/module.h> 96 #include <sys/socket.h> 97 #include <sys/sockio.h> 98 #include <sys/queue.h> 99 #include <sys/sysctl.h> 100 101 #include <net/bpf.h> 102 #include <net/ethernet.h> 103 #include <net/if.h> 104 #include <net/if_var.h> 105 #include <net/if_arp.h> 106 #include <net/if_dl.h> 107 #include <net/if_media.h> 108 #include <net/if_types.h> 109 #include <net/if_vlan_var.h> 110 111 #include <netinet/in.h> 112 #include <netinet/in_systm.h> 113 #include <netinet/ip.h> 114 115 #include <machine/bus.h> 116 #include <machine/in_cksum.h> 117 #include <machine/resource.h> 118 #include <sys/rman.h> 119 120 #include <dev/mii/mii.h> 121 #include <dev/mii/miivar.h> 122 #include <dev/mii/brgphyreg.h> 123 124 #include <dev/pci/pcireg.h> 125 #include <dev/pci/pcivar.h> 126 127 #if 0 128 #define SK_USEIOSPACE 129 #endif 130 131 #include <dev/sk/if_skreg.h> 132 #include <dev/sk/xmaciireg.h> 133 #include <dev/sk/yukonreg.h> 134 135 MODULE_DEPEND(sk, pci, 1, 1, 1); 136 MODULE_DEPEND(sk, ether, 1, 1, 1); 137 MODULE_DEPEND(sk, miibus, 1, 1, 1); 138 139 /* "device miibus" required. See GENERIC if you get errors here. */ 140 #include "miibus_if.h" 141 142 static const struct sk_type sk_devs[] = { 143 { 144 VENDORID_SK, 145 DEVICEID_SK_V1, 146 "SysKonnect Gigabit Ethernet (V1.0)" 147 }, 148 { 149 VENDORID_SK, 150 DEVICEID_SK_V2, 151 "SysKonnect Gigabit Ethernet (V2.0)" 152 }, 153 { 154 VENDORID_MARVELL, 155 DEVICEID_SK_V2, 156 "Marvell Gigabit Ethernet" 157 }, 158 { 159 VENDORID_MARVELL, 160 DEVICEID_BELKIN_5005, 161 "Belkin F5D5005 Gigabit Ethernet" 162 }, 163 { 164 VENDORID_3COM, 165 DEVICEID_3COM_3C940, 166 "3Com 3C940 Gigabit Ethernet" 167 }, 168 { 169 VENDORID_LINKSYS, 170 DEVICEID_LINKSYS_EG1032, 171 "Linksys EG1032 Gigabit Ethernet" 172 }, 173 { 174 VENDORID_DLINK, 175 DEVICEID_DLINK_DGE530T_A1, 176 "D-Link DGE-530T Gigabit Ethernet" 177 }, 178 { 179 VENDORID_DLINK, 180 DEVICEID_DLINK_DGE530T_B1, 181 "D-Link DGE-530T Gigabit Ethernet" 182 }, 183 { 0, 0, NULL } 184 }; 185 186 static int skc_probe(device_t); 187 static int skc_attach(device_t); 188 static int skc_detach(device_t); 189 static int skc_shutdown(device_t); 190 static int skc_suspend(device_t); 191 static int skc_resume(device_t); 192 static bus_dma_tag_t skc_get_dma_tag(device_t, device_t); 193 static int sk_detach(device_t); 194 static int sk_probe(device_t); 195 static int sk_attach(device_t); 196 static void sk_tick(void *); 197 static void sk_yukon_tick(void *); 198 static void sk_intr(void *); 199 static void sk_intr_xmac(struct sk_if_softc *); 200 static void sk_intr_bcom(struct sk_if_softc *); 201 static void sk_intr_yukon(struct sk_if_softc *); 202 static __inline void sk_rxcksum(if_t, struct mbuf *, u_int32_t); 203 static __inline int sk_rxvalid(struct sk_softc *, u_int32_t, u_int32_t); 204 static void sk_rxeof(struct sk_if_softc *); 205 static void sk_jumbo_rxeof(struct sk_if_softc *); 206 static void sk_txeof(struct sk_if_softc *); 207 static void sk_txcksum(if_t, struct mbuf *, struct sk_tx_desc *); 208 static int sk_encap(struct sk_if_softc *, struct mbuf **); 209 static void sk_start(if_t); 210 static void sk_start_locked(if_t); 211 static int sk_ioctl(if_t, u_long, caddr_t); 212 static void sk_init(void *); 213 static void sk_init_locked(struct sk_if_softc *); 214 static void sk_init_xmac(struct sk_if_softc *); 215 static void sk_init_yukon(struct sk_if_softc *); 216 static void sk_stop(struct sk_if_softc *); 217 static void sk_watchdog(void *); 218 static int sk_ifmedia_upd(if_t); 219 static void sk_ifmedia_sts(if_t, struct ifmediareq *); 220 static void sk_reset(struct sk_softc *); 221 static __inline void sk_discard_rxbuf(struct sk_if_softc *, int); 222 static __inline void sk_discard_jumbo_rxbuf(struct sk_if_softc *, int); 223 static int sk_newbuf(struct sk_if_softc *, int); 224 static int sk_jumbo_newbuf(struct sk_if_softc *, int); 225 static void sk_dmamap_cb(void *, bus_dma_segment_t *, int, int); 226 static int sk_dma_alloc(struct sk_if_softc *); 227 static int sk_dma_jumbo_alloc(struct sk_if_softc *); 228 static void sk_dma_free(struct sk_if_softc *); 229 static void sk_dma_jumbo_free(struct sk_if_softc *); 230 static int sk_init_rx_ring(struct sk_if_softc *); 231 static int sk_init_jumbo_rx_ring(struct sk_if_softc *); 232 static void sk_init_tx_ring(struct sk_if_softc *); 233 static u_int32_t sk_win_read_4(struct sk_softc *, int); 234 static u_int16_t sk_win_read_2(struct sk_softc *, int); 235 static u_int8_t sk_win_read_1(struct sk_softc *, int); 236 static void sk_win_write_4(struct sk_softc *, int, u_int32_t); 237 static void sk_win_write_2(struct sk_softc *, int, u_int32_t); 238 static void sk_win_write_1(struct sk_softc *, int, u_int32_t); 239 240 static int sk_miibus_readreg(device_t, int, int); 241 static int sk_miibus_writereg(device_t, int, int, int); 242 static void sk_miibus_statchg(device_t); 243 244 static int sk_xmac_miibus_readreg(struct sk_if_softc *, int, int); 245 static int sk_xmac_miibus_writereg(struct sk_if_softc *, int, int, 246 int); 247 static void sk_xmac_miibus_statchg(struct sk_if_softc *); 248 249 static int sk_marv_miibus_readreg(struct sk_if_softc *, int, int); 250 static int sk_marv_miibus_writereg(struct sk_if_softc *, int, int, 251 int); 252 static void sk_marv_miibus_statchg(struct sk_if_softc *); 253 254 static uint32_t sk_xmchash(const uint8_t *); 255 static void sk_setfilt(struct sk_if_softc *, u_int16_t *, int); 256 static void sk_rxfilter(struct sk_if_softc *); 257 static void sk_rxfilter_genesis(struct sk_if_softc *); 258 static void sk_rxfilter_yukon(struct sk_if_softc *); 259 260 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high); 261 static int sysctl_hw_sk_int_mod(SYSCTL_HANDLER_ARGS); 262 263 /* Tunables. */ 264 static int jumbo_disable = 0; 265 TUNABLE_INT("hw.skc.jumbo_disable", &jumbo_disable); 266 267 /* 268 * It seems that SK-NET GENESIS supports very simple checksum offload 269 * capability for Tx and I believe it can generate 0 checksum value for 270 * UDP packets in Tx as the hardware can't differenciate UDP packets from 271 * TCP packets. 0 chcecksum value for UDP packet is an invalid one as it 272 * means sender didn't perforam checksum computation. For the safety I 273 * disabled UDP checksum offload capability at the moment. 274 */ 275 #define SK_CSUM_FEATURES (CSUM_TCP) 276 277 /* 278 * Note that we have newbus methods for both the GEnesis controller 279 * itself and the XMAC(s). The XMACs are children of the GEnesis, and 280 * the miibus code is a child of the XMACs. We need to do it this way 281 * so that the miibus drivers can access the PHY registers on the 282 * right PHY. It's not quite what I had in mind, but it's the only 283 * design that achieves the desired effect. 284 */ 285 static device_method_t skc_methods[] = { 286 /* Device interface */ 287 DEVMETHOD(device_probe, skc_probe), 288 DEVMETHOD(device_attach, skc_attach), 289 DEVMETHOD(device_detach, skc_detach), 290 DEVMETHOD(device_suspend, skc_suspend), 291 DEVMETHOD(device_resume, skc_resume), 292 DEVMETHOD(device_shutdown, skc_shutdown), 293 294 DEVMETHOD(bus_get_dma_tag, skc_get_dma_tag), 295 296 DEVMETHOD_END 297 }; 298 299 static driver_t skc_driver = { 300 "skc", 301 skc_methods, 302 sizeof(struct sk_softc) 303 }; 304 305 static device_method_t sk_methods[] = { 306 /* Device interface */ 307 DEVMETHOD(device_probe, sk_probe), 308 DEVMETHOD(device_attach, sk_attach), 309 DEVMETHOD(device_detach, sk_detach), 310 DEVMETHOD(device_shutdown, bus_generic_shutdown), 311 312 /* MII interface */ 313 DEVMETHOD(miibus_readreg, sk_miibus_readreg), 314 DEVMETHOD(miibus_writereg, sk_miibus_writereg), 315 DEVMETHOD(miibus_statchg, sk_miibus_statchg), 316 317 DEVMETHOD_END 318 }; 319 320 static driver_t sk_driver = { 321 "sk", 322 sk_methods, 323 sizeof(struct sk_if_softc) 324 }; 325 326 DRIVER_MODULE(skc, pci, skc_driver, NULL, NULL); 327 DRIVER_MODULE(sk, skc, sk_driver, NULL, NULL); 328 DRIVER_MODULE(miibus, sk, miibus_driver, NULL, NULL); 329 330 static struct resource_spec sk_res_spec_io[] = { 331 { SYS_RES_IOPORT, PCIR_BAR(1), RF_ACTIVE }, 332 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 333 { -1, 0, 0 } 334 }; 335 336 static struct resource_spec sk_res_spec_mem[] = { 337 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 338 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 339 { -1, 0, 0 } 340 }; 341 342 #define SK_SETBIT(sc, reg, x) \ 343 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 344 345 #define SK_CLRBIT(sc, reg, x) \ 346 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 347 348 #define SK_WIN_SETBIT_4(sc, reg, x) \ 349 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x) 350 351 #define SK_WIN_CLRBIT_4(sc, reg, x) \ 352 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x) 353 354 #define SK_WIN_SETBIT_2(sc, reg, x) \ 355 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x) 356 357 #define SK_WIN_CLRBIT_2(sc, reg, x) \ 358 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x) 359 360 static u_int32_t 361 sk_win_read_4(struct sk_softc *sc, int reg) 362 { 363 #ifdef SK_USEIOSPACE 364 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 365 return(CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg))); 366 #else 367 return(CSR_READ_4(sc, reg)); 368 #endif 369 } 370 371 static u_int16_t 372 sk_win_read_2(struct sk_softc *sc, int reg) 373 { 374 #ifdef SK_USEIOSPACE 375 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 376 return(CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg))); 377 #else 378 return(CSR_READ_2(sc, reg)); 379 #endif 380 } 381 382 static u_int8_t 383 sk_win_read_1(struct sk_softc *sc, int reg) 384 { 385 #ifdef SK_USEIOSPACE 386 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 387 return(CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg))); 388 #else 389 return(CSR_READ_1(sc, reg)); 390 #endif 391 } 392 393 static void 394 sk_win_write_4(struct sk_softc *sc, int reg, u_int32_t val) 395 { 396 #ifdef SK_USEIOSPACE 397 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 398 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), val); 399 #else 400 CSR_WRITE_4(sc, reg, val); 401 #endif 402 return; 403 } 404 405 static void 406 sk_win_write_2(struct sk_softc *sc, int reg, u_int32_t val) 407 { 408 #ifdef SK_USEIOSPACE 409 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 410 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), val); 411 #else 412 CSR_WRITE_2(sc, reg, val); 413 #endif 414 return; 415 } 416 417 static void 418 sk_win_write_1(struct sk_softc *sc, int reg, u_int32_t val) 419 { 420 #ifdef SK_USEIOSPACE 421 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 422 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), val); 423 #else 424 CSR_WRITE_1(sc, reg, val); 425 #endif 426 return; 427 } 428 429 static int 430 sk_miibus_readreg(device_t dev, int phy, int reg) 431 { 432 struct sk_if_softc *sc_if; 433 int v; 434 435 sc_if = device_get_softc(dev); 436 437 SK_IF_MII_LOCK(sc_if); 438 switch(sc_if->sk_softc->sk_type) { 439 case SK_GENESIS: 440 v = sk_xmac_miibus_readreg(sc_if, phy, reg); 441 break; 442 case SK_YUKON: 443 case SK_YUKON_LITE: 444 case SK_YUKON_LP: 445 v = sk_marv_miibus_readreg(sc_if, phy, reg); 446 break; 447 default: 448 v = 0; 449 break; 450 } 451 SK_IF_MII_UNLOCK(sc_if); 452 453 return (v); 454 } 455 456 static int 457 sk_miibus_writereg(device_t dev, int phy, int reg, int val) 458 { 459 struct sk_if_softc *sc_if; 460 int v; 461 462 sc_if = device_get_softc(dev); 463 464 SK_IF_MII_LOCK(sc_if); 465 switch(sc_if->sk_softc->sk_type) { 466 case SK_GENESIS: 467 v = sk_xmac_miibus_writereg(sc_if, phy, reg, val); 468 break; 469 case SK_YUKON: 470 case SK_YUKON_LITE: 471 case SK_YUKON_LP: 472 v = sk_marv_miibus_writereg(sc_if, phy, reg, val); 473 break; 474 default: 475 v = 0; 476 break; 477 } 478 SK_IF_MII_UNLOCK(sc_if); 479 480 return (v); 481 } 482 483 static void 484 sk_miibus_statchg(device_t dev) 485 { 486 struct sk_if_softc *sc_if; 487 488 sc_if = device_get_softc(dev); 489 490 SK_IF_MII_LOCK(sc_if); 491 switch(sc_if->sk_softc->sk_type) { 492 case SK_GENESIS: 493 sk_xmac_miibus_statchg(sc_if); 494 break; 495 case SK_YUKON: 496 case SK_YUKON_LITE: 497 case SK_YUKON_LP: 498 sk_marv_miibus_statchg(sc_if); 499 break; 500 } 501 SK_IF_MII_UNLOCK(sc_if); 502 503 return; 504 } 505 506 static int 507 sk_xmac_miibus_readreg(struct sk_if_softc *sc_if, int phy, int reg) 508 { 509 int i; 510 511 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 512 SK_XM_READ_2(sc_if, XM_PHY_DATA); 513 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 514 for (i = 0; i < SK_TIMEOUT; i++) { 515 DELAY(1); 516 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 517 XM_MMUCMD_PHYDATARDY) 518 break; 519 } 520 521 if (i == SK_TIMEOUT) { 522 if_printf(sc_if->sk_ifp, "phy failed to come ready\n"); 523 return(0); 524 } 525 } 526 DELAY(1); 527 i = SK_XM_READ_2(sc_if, XM_PHY_DATA); 528 529 return(i); 530 } 531 532 static int 533 sk_xmac_miibus_writereg(struct sk_if_softc *sc_if, int phy, int reg, int val) 534 { 535 int i; 536 537 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 538 for (i = 0; i < SK_TIMEOUT; i++) { 539 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 540 break; 541 } 542 543 if (i == SK_TIMEOUT) { 544 if_printf(sc_if->sk_ifp, "phy failed to come ready\n"); 545 return (ETIMEDOUT); 546 } 547 548 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 549 for (i = 0; i < SK_TIMEOUT; i++) { 550 DELAY(1); 551 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 552 break; 553 } 554 if (i == SK_TIMEOUT) 555 if_printf(sc_if->sk_ifp, "phy write timed out\n"); 556 557 return(0); 558 } 559 560 static void 561 sk_xmac_miibus_statchg(struct sk_if_softc *sc_if) 562 { 563 struct mii_data *mii; 564 565 mii = device_get_softc(sc_if->sk_miibus); 566 567 /* 568 * If this is a GMII PHY, manually set the XMAC's 569 * duplex mode accordingly. 570 */ 571 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 572 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 573 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 574 } else { 575 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 576 } 577 } 578 } 579 580 static int 581 sk_marv_miibus_readreg(struct sk_if_softc *sc_if, int phy, int reg) 582 { 583 u_int16_t val; 584 int i; 585 586 if (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 587 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER) { 588 return(0); 589 } 590 591 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 592 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 593 594 for (i = 0; i < SK_TIMEOUT; i++) { 595 DELAY(1); 596 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 597 if (val & YU_SMICR_READ_VALID) 598 break; 599 } 600 601 if (i == SK_TIMEOUT) { 602 if_printf(sc_if->sk_ifp, "phy failed to come ready\n"); 603 return(0); 604 } 605 606 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 607 608 return(val); 609 } 610 611 static int 612 sk_marv_miibus_writereg(struct sk_if_softc *sc_if, int phy, int reg, int val) 613 { 614 int i; 615 616 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 617 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 618 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 619 620 for (i = 0; i < SK_TIMEOUT; i++) { 621 DELAY(1); 622 if ((SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY) == 0) 623 break; 624 } 625 if (i == SK_TIMEOUT) 626 if_printf(sc_if->sk_ifp, "phy write timeout\n"); 627 628 return(0); 629 } 630 631 static void 632 sk_marv_miibus_statchg(struct sk_if_softc *sc_if) 633 { 634 return; 635 } 636 637 #define HASH_BITS 6 638 639 static u_int32_t 640 sk_xmchash(const uint8_t *addr) 641 { 642 uint32_t crc; 643 644 /* Compute CRC for the address value. */ 645 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 646 647 return (~crc & ((1 << HASH_BITS) - 1)); 648 } 649 650 static void 651 sk_setfilt(struct sk_if_softc *sc_if, u_int16_t *addr, int slot) 652 { 653 int base; 654 655 base = XM_RXFILT_ENTRY(slot); 656 657 SK_XM_WRITE_2(sc_if, base, addr[0]); 658 SK_XM_WRITE_2(sc_if, base + 2, addr[1]); 659 SK_XM_WRITE_2(sc_if, base + 4, addr[2]); 660 661 return; 662 } 663 664 static void 665 sk_rxfilter(struct sk_if_softc *sc_if) 666 { 667 struct sk_softc *sc; 668 669 SK_IF_LOCK_ASSERT(sc_if); 670 671 sc = sc_if->sk_softc; 672 if (sc->sk_type == SK_GENESIS) 673 sk_rxfilter_genesis(sc_if); 674 else 675 sk_rxfilter_yukon(sc_if); 676 } 677 678 struct sk_add_maddr_genesis_ctx { 679 struct sk_if_softc *sc_if; 680 uint32_t hashes[2]; 681 uint32_t mode; 682 }; 683 684 static u_int 685 sk_add_maddr_genesis(void *arg, struct sockaddr_dl *sdl, u_int cnt) 686 { 687 struct sk_add_maddr_genesis_ctx *ctx = arg; 688 int h; 689 690 /* 691 * Program the first XM_RXFILT_MAX multicast groups 692 * into the perfect filter. 693 */ 694 if (cnt + 1 < XM_RXFILT_MAX) { 695 sk_setfilt(ctx->sc_if, (uint16_t *)LLADDR(sdl), cnt + 1); 696 ctx->mode |= XM_MODE_RX_USE_PERFECT; 697 return (1); 698 } 699 h = sk_xmchash((const uint8_t *)LLADDR(sdl)); 700 if (h < 32) 701 ctx->hashes[0] |= (1 << h); 702 else 703 ctx->hashes[1] |= (1 << (h - 32)); 704 ctx->mode |= XM_MODE_RX_USE_HASH; 705 706 return (1); 707 } 708 709 static void 710 sk_rxfilter_genesis(struct sk_if_softc *sc_if) 711 { 712 if_t ifp = sc_if->sk_ifp; 713 struct sk_add_maddr_genesis_ctx ctx = { sc_if, { 0, 0 } }; 714 int i; 715 u_int16_t dummy[] = { 0, 0, 0 }; 716 717 SK_IF_LOCK_ASSERT(sc_if); 718 719 ctx.mode = SK_XM_READ_4(sc_if, XM_MODE); 720 ctx.mode &= ~(XM_MODE_RX_PROMISC | XM_MODE_RX_USE_HASH | 721 XM_MODE_RX_USE_PERFECT); 722 /* First, zot all the existing perfect filters. */ 723 for (i = 1; i < XM_RXFILT_MAX; i++) 724 sk_setfilt(sc_if, dummy, i); 725 726 /* Now program new ones. */ 727 if (if_getflags(ifp) & IFF_ALLMULTI || if_getflags(ifp) & IFF_PROMISC) { 728 if (if_getflags(ifp) & IFF_ALLMULTI) 729 ctx.mode |= XM_MODE_RX_USE_HASH; 730 if (if_getflags(ifp) & IFF_PROMISC) 731 ctx.mode |= XM_MODE_RX_PROMISC; 732 ctx.hashes[0] = 0xFFFFFFFF; 733 ctx.hashes[1] = 0xFFFFFFFF; 734 } else 735 /* XXX want to maintain reverse semantics */ 736 if_foreach_llmaddr(ifp, sk_add_maddr_genesis, &ctx); 737 738 SK_XM_WRITE_4(sc_if, XM_MODE, ctx.mode); 739 SK_XM_WRITE_4(sc_if, XM_MAR0, ctx.hashes[0]); 740 SK_XM_WRITE_4(sc_if, XM_MAR2, ctx.hashes[1]); 741 } 742 743 static u_int 744 sk_hash_maddr_yukon(void *arg, struct sockaddr_dl *sdl, u_int cnt) 745 { 746 uint32_t crc, *hashes = arg; 747 748 crc = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN); 749 /* Just want the 6 least significant bits. */ 750 crc &= 0x3f; 751 /* Set the corresponding bit in the hash table. */ 752 hashes[crc >> 5] |= 1 << (crc & 0x1f); 753 754 return (1); 755 } 756 757 static void 758 sk_rxfilter_yukon(struct sk_if_softc *sc_if) 759 { 760 if_t ifp; 761 uint32_t hashes[2] = { 0, 0 }, mode; 762 763 SK_IF_LOCK_ASSERT(sc_if); 764 765 ifp = sc_if->sk_ifp; 766 mode = SK_YU_READ_2(sc_if, YUKON_RCR); 767 if (if_getflags(ifp) & IFF_PROMISC) 768 mode &= ~(YU_RCR_UFLEN | YU_RCR_MUFLEN); 769 else if (if_getflags(ifp) & IFF_ALLMULTI) { 770 mode |= YU_RCR_UFLEN | YU_RCR_MUFLEN; 771 hashes[0] = 0xFFFFFFFF; 772 hashes[1] = 0xFFFFFFFF; 773 } else { 774 mode |= YU_RCR_UFLEN; 775 if_foreach_llmaddr(ifp, sk_hash_maddr_yukon, hashes); 776 if (hashes[0] != 0 || hashes[1] != 0) 777 mode |= YU_RCR_MUFLEN; 778 } 779 780 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 781 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 782 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 783 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 784 SK_YU_WRITE_2(sc_if, YUKON_RCR, mode); 785 } 786 787 static int 788 sk_init_rx_ring(struct sk_if_softc *sc_if) 789 { 790 struct sk_ring_data *rd; 791 bus_addr_t addr; 792 u_int32_t csum_start; 793 int i; 794 795 sc_if->sk_cdata.sk_rx_cons = 0; 796 797 csum_start = (ETHER_HDR_LEN + sizeof(struct ip)) << 16 | 798 ETHER_HDR_LEN; 799 rd = &sc_if->sk_rdata; 800 bzero(rd->sk_rx_ring, sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 801 for (i = 0; i < SK_RX_RING_CNT; i++) { 802 if (sk_newbuf(sc_if, i) != 0) 803 return (ENOBUFS); 804 if (i == (SK_RX_RING_CNT - 1)) 805 addr = SK_RX_RING_ADDR(sc_if, 0); 806 else 807 addr = SK_RX_RING_ADDR(sc_if, i + 1); 808 rd->sk_rx_ring[i].sk_next = htole32(SK_ADDR_LO(addr)); 809 rd->sk_rx_ring[i].sk_csum_start = htole32(csum_start); 810 } 811 812 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag, 813 sc_if->sk_cdata.sk_rx_ring_map, 814 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 815 816 return(0); 817 } 818 819 static int 820 sk_init_jumbo_rx_ring(struct sk_if_softc *sc_if) 821 { 822 struct sk_ring_data *rd; 823 bus_addr_t addr; 824 u_int32_t csum_start; 825 int i; 826 827 sc_if->sk_cdata.sk_jumbo_rx_cons = 0; 828 829 csum_start = ((ETHER_HDR_LEN + sizeof(struct ip)) << 16) | 830 ETHER_HDR_LEN; 831 rd = &sc_if->sk_rdata; 832 bzero(rd->sk_jumbo_rx_ring, 833 sizeof(struct sk_rx_desc) * SK_JUMBO_RX_RING_CNT); 834 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) { 835 if (sk_jumbo_newbuf(sc_if, i) != 0) 836 return (ENOBUFS); 837 if (i == (SK_JUMBO_RX_RING_CNT - 1)) 838 addr = SK_JUMBO_RX_RING_ADDR(sc_if, 0); 839 else 840 addr = SK_JUMBO_RX_RING_ADDR(sc_if, i + 1); 841 rd->sk_jumbo_rx_ring[i].sk_next = htole32(SK_ADDR_LO(addr)); 842 rd->sk_jumbo_rx_ring[i].sk_csum_start = htole32(csum_start); 843 } 844 845 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 846 sc_if->sk_cdata.sk_jumbo_rx_ring_map, 847 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 848 849 return (0); 850 } 851 852 static void 853 sk_init_tx_ring(struct sk_if_softc *sc_if) 854 { 855 struct sk_ring_data *rd; 856 struct sk_txdesc *txd; 857 bus_addr_t addr; 858 int i; 859 860 STAILQ_INIT(&sc_if->sk_cdata.sk_txfreeq); 861 STAILQ_INIT(&sc_if->sk_cdata.sk_txbusyq); 862 863 sc_if->sk_cdata.sk_tx_prod = 0; 864 sc_if->sk_cdata.sk_tx_cons = 0; 865 sc_if->sk_cdata.sk_tx_cnt = 0; 866 867 rd = &sc_if->sk_rdata; 868 bzero(rd->sk_tx_ring, sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 869 for (i = 0; i < SK_TX_RING_CNT; i++) { 870 if (i == (SK_TX_RING_CNT - 1)) 871 addr = SK_TX_RING_ADDR(sc_if, 0); 872 else 873 addr = SK_TX_RING_ADDR(sc_if, i + 1); 874 rd->sk_tx_ring[i].sk_next = htole32(SK_ADDR_LO(addr)); 875 txd = &sc_if->sk_cdata.sk_txdesc[i]; 876 STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txfreeq, txd, tx_q); 877 } 878 879 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag, 880 sc_if->sk_cdata.sk_tx_ring_map, 881 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 882 } 883 884 static __inline void 885 sk_discard_rxbuf(struct sk_if_softc *sc_if, int idx) 886 { 887 struct sk_rx_desc *r; 888 struct sk_rxdesc *rxd; 889 struct mbuf *m; 890 891 r = &sc_if->sk_rdata.sk_rx_ring[idx]; 892 rxd = &sc_if->sk_cdata.sk_rxdesc[idx]; 893 m = rxd->rx_m; 894 r->sk_ctl = htole32(m->m_len | SK_RXSTAT | SK_OPCODE_CSUM); 895 } 896 897 static __inline void 898 sk_discard_jumbo_rxbuf(struct sk_if_softc *sc_if, int idx) 899 { 900 struct sk_rx_desc *r; 901 struct sk_rxdesc *rxd; 902 struct mbuf *m; 903 904 r = &sc_if->sk_rdata.sk_jumbo_rx_ring[idx]; 905 rxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[idx]; 906 m = rxd->rx_m; 907 r->sk_ctl = htole32(m->m_len | SK_RXSTAT | SK_OPCODE_CSUM); 908 } 909 910 static int 911 sk_newbuf(struct sk_if_softc *sc_if, int idx) 912 { 913 struct sk_rx_desc *r; 914 struct sk_rxdesc *rxd; 915 struct mbuf *m; 916 bus_dma_segment_t segs[1]; 917 bus_dmamap_t map; 918 int nsegs; 919 920 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 921 if (m == NULL) 922 return (ENOBUFS); 923 m->m_len = m->m_pkthdr.len = MCLBYTES; 924 m_adj(m, ETHER_ALIGN); 925 926 if (bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_rx_tag, 927 sc_if->sk_cdata.sk_rx_sparemap, m, segs, &nsegs, 0) != 0) { 928 m_freem(m); 929 return (ENOBUFS); 930 } 931 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 932 933 rxd = &sc_if->sk_cdata.sk_rxdesc[idx]; 934 if (rxd->rx_m != NULL) { 935 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap, 936 BUS_DMASYNC_POSTREAD); 937 bus_dmamap_unload(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap); 938 } 939 map = rxd->rx_dmamap; 940 rxd->rx_dmamap = sc_if->sk_cdata.sk_rx_sparemap; 941 sc_if->sk_cdata.sk_rx_sparemap = map; 942 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap, 943 BUS_DMASYNC_PREREAD); 944 rxd->rx_m = m; 945 r = &sc_if->sk_rdata.sk_rx_ring[idx]; 946 r->sk_data_lo = htole32(SK_ADDR_LO(segs[0].ds_addr)); 947 r->sk_data_hi = htole32(SK_ADDR_HI(segs[0].ds_addr)); 948 r->sk_ctl = htole32(segs[0].ds_len | SK_RXSTAT | SK_OPCODE_CSUM); 949 950 return (0); 951 } 952 953 static int 954 sk_jumbo_newbuf(struct sk_if_softc *sc_if, int idx) 955 { 956 struct sk_rx_desc *r; 957 struct sk_rxdesc *rxd; 958 struct mbuf *m; 959 bus_dma_segment_t segs[1]; 960 bus_dmamap_t map; 961 int nsegs; 962 963 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 964 if (m == NULL) 965 return (ENOBUFS); 966 m->m_pkthdr.len = m->m_len = MJUM9BYTES; 967 /* 968 * Adjust alignment so packet payload begins on a 969 * longword boundary. Mandatory for Alpha, useful on 970 * x86 too. 971 */ 972 m_adj(m, ETHER_ALIGN); 973 974 if (bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_jumbo_rx_tag, 975 sc_if->sk_cdata.sk_jumbo_rx_sparemap, m, segs, &nsegs, 0) != 0) { 976 m_freem(m); 977 return (ENOBUFS); 978 } 979 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 980 981 rxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[idx]; 982 if (rxd->rx_m != NULL) { 983 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag, rxd->rx_dmamap, 984 BUS_DMASYNC_POSTREAD); 985 bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_tag, 986 rxd->rx_dmamap); 987 } 988 map = rxd->rx_dmamap; 989 rxd->rx_dmamap = sc_if->sk_cdata.sk_jumbo_rx_sparemap; 990 sc_if->sk_cdata.sk_jumbo_rx_sparemap = map; 991 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag, rxd->rx_dmamap, 992 BUS_DMASYNC_PREREAD); 993 rxd->rx_m = m; 994 r = &sc_if->sk_rdata.sk_jumbo_rx_ring[idx]; 995 r->sk_data_lo = htole32(SK_ADDR_LO(segs[0].ds_addr)); 996 r->sk_data_hi = htole32(SK_ADDR_HI(segs[0].ds_addr)); 997 r->sk_ctl = htole32(segs[0].ds_len | SK_RXSTAT | SK_OPCODE_CSUM); 998 999 return (0); 1000 } 1001 1002 /* 1003 * Set media options. 1004 */ 1005 static int 1006 sk_ifmedia_upd(if_t ifp) 1007 { 1008 struct sk_if_softc *sc_if = if_getsoftc(ifp); 1009 struct mii_data *mii; 1010 1011 mii = device_get_softc(sc_if->sk_miibus); 1012 sk_init(sc_if); 1013 mii_mediachg(mii); 1014 1015 return(0); 1016 } 1017 1018 /* 1019 * Report current media status. 1020 */ 1021 static void 1022 sk_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr) 1023 { 1024 struct sk_if_softc *sc_if; 1025 struct mii_data *mii; 1026 1027 sc_if = if_getsoftc(ifp); 1028 mii = device_get_softc(sc_if->sk_miibus); 1029 1030 mii_pollstat(mii); 1031 ifmr->ifm_active = mii->mii_media_active; 1032 ifmr->ifm_status = mii->mii_media_status; 1033 1034 return; 1035 } 1036 1037 static int 1038 sk_ioctl(if_t ifp, u_long command, caddr_t data) 1039 { 1040 struct sk_if_softc *sc_if = if_getsoftc(ifp); 1041 struct ifreq *ifr = (struct ifreq *) data; 1042 int error, mask; 1043 struct mii_data *mii; 1044 1045 error = 0; 1046 switch(command) { 1047 case SIOCSIFMTU: 1048 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > SK_JUMBO_MTU) 1049 error = EINVAL; 1050 else if (if_getmtu(ifp) != ifr->ifr_mtu) { 1051 if (sc_if->sk_jumbo_disable != 0 && 1052 ifr->ifr_mtu > SK_MAX_FRAMELEN) 1053 error = EINVAL; 1054 else { 1055 SK_IF_LOCK(sc_if); 1056 if_setmtu(ifp, ifr->ifr_mtu); 1057 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 1058 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1059 sk_init_locked(sc_if); 1060 } 1061 SK_IF_UNLOCK(sc_if); 1062 } 1063 } 1064 break; 1065 case SIOCSIFFLAGS: 1066 SK_IF_LOCK(sc_if); 1067 if (if_getflags(ifp) & IFF_UP) { 1068 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 1069 if ((if_getflags(ifp) ^ sc_if->sk_if_flags) 1070 & (IFF_PROMISC | IFF_ALLMULTI)) 1071 sk_rxfilter(sc_if); 1072 } else 1073 sk_init_locked(sc_if); 1074 } else { 1075 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 1076 sk_stop(sc_if); 1077 } 1078 sc_if->sk_if_flags = if_getflags(ifp); 1079 SK_IF_UNLOCK(sc_if); 1080 break; 1081 case SIOCADDMULTI: 1082 case SIOCDELMULTI: 1083 SK_IF_LOCK(sc_if); 1084 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 1085 sk_rxfilter(sc_if); 1086 SK_IF_UNLOCK(sc_if); 1087 break; 1088 case SIOCGIFMEDIA: 1089 case SIOCSIFMEDIA: 1090 mii = device_get_softc(sc_if->sk_miibus); 1091 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1092 break; 1093 case SIOCSIFCAP: 1094 SK_IF_LOCK(sc_if); 1095 if (sc_if->sk_softc->sk_type == SK_GENESIS) { 1096 SK_IF_UNLOCK(sc_if); 1097 break; 1098 } 1099 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 1100 if ((mask & IFCAP_TXCSUM) != 0 && 1101 (IFCAP_TXCSUM & if_getcapabilities(ifp)) != 0) { 1102 if_togglecapenable(ifp, IFCAP_TXCSUM); 1103 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0) 1104 if_sethwassistbits(ifp, SK_CSUM_FEATURES, 0); 1105 else 1106 if_sethwassistbits(ifp, 0, SK_CSUM_FEATURES); 1107 } 1108 if ((mask & IFCAP_RXCSUM) != 0 && 1109 (IFCAP_RXCSUM & if_getcapabilities(ifp)) != 0) 1110 if_togglecapenable(ifp, IFCAP_RXCSUM); 1111 SK_IF_UNLOCK(sc_if); 1112 break; 1113 default: 1114 error = ether_ioctl(ifp, command, data); 1115 break; 1116 } 1117 1118 return (error); 1119 } 1120 1121 /* 1122 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 1123 * IDs against our list and return a device name if we find a match. 1124 */ 1125 static int 1126 skc_probe(device_t dev) 1127 { 1128 const struct sk_type *t = sk_devs; 1129 1130 while(t->sk_name != NULL) { 1131 if ((pci_get_vendor(dev) == t->sk_vid) && 1132 (pci_get_device(dev) == t->sk_did)) { 1133 /* 1134 * Only attach to rev. 2 of the Linksys EG1032 adapter. 1135 * Rev. 3 is supported by re(4). 1136 */ 1137 if ((t->sk_vid == VENDORID_LINKSYS) && 1138 (t->sk_did == DEVICEID_LINKSYS_EG1032) && 1139 (pci_get_subdevice(dev) != 1140 SUBDEVICEID_LINKSYS_EG1032_REV2)) { 1141 t++; 1142 continue; 1143 } 1144 device_set_desc(dev, t->sk_name); 1145 return (BUS_PROBE_DEFAULT); 1146 } 1147 t++; 1148 } 1149 1150 return(ENXIO); 1151 } 1152 1153 /* 1154 * Force the GEnesis into reset, then bring it out of reset. 1155 */ 1156 static void 1157 sk_reset(struct sk_softc *sc) 1158 { 1159 1160 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 1161 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 1162 if (SK_YUKON_FAMILY(sc->sk_type)) 1163 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 1164 1165 DELAY(1000); 1166 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 1167 DELAY(2); 1168 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1169 if (SK_YUKON_FAMILY(sc->sk_type)) 1170 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 1171 1172 if (sc->sk_type == SK_GENESIS) { 1173 /* Configure packet arbiter */ 1174 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1175 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1176 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1177 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1178 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1179 } 1180 1181 /* Enable RAM interface */ 1182 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1183 1184 /* 1185 * Configure interrupt moderation. The moderation timer 1186 * defers interrupts specified in the interrupt moderation 1187 * timer mask based on the timeout specified in the interrupt 1188 * moderation timer init register. Each bit in the timer 1189 * register represents one tick, so to specify a timeout in 1190 * microseconds, we have to multiply by the correct number of 1191 * ticks-per-microsecond. 1192 */ 1193 switch (sc->sk_type) { 1194 case SK_GENESIS: 1195 sc->sk_int_ticks = SK_IMTIMER_TICKS_GENESIS; 1196 break; 1197 default: 1198 sc->sk_int_ticks = SK_IMTIMER_TICKS_YUKON; 1199 break; 1200 } 1201 if (bootverbose) 1202 device_printf(sc->sk_dev, "interrupt moderation is %d us\n", 1203 sc->sk_int_mod); 1204 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod, 1205 sc->sk_int_ticks)); 1206 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 1207 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 1208 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1209 1210 return; 1211 } 1212 1213 static int 1214 sk_probe(device_t dev) 1215 { 1216 struct sk_softc *sc; 1217 1218 sc = device_get_softc(device_get_parent(dev)); 1219 1220 /* 1221 * Not much to do here. We always know there will be 1222 * at least one XMAC present, and if there are two, 1223 * skc_attach() will create a second device instance 1224 * for us. 1225 */ 1226 switch (sc->sk_type) { 1227 case SK_GENESIS: 1228 device_set_desc(dev, "XaQti Corp. XMAC II"); 1229 break; 1230 case SK_YUKON: 1231 case SK_YUKON_LITE: 1232 case SK_YUKON_LP: 1233 device_set_desc(dev, "Marvell Semiconductor, Inc. Yukon"); 1234 break; 1235 } 1236 1237 return (BUS_PROBE_DEFAULT); 1238 } 1239 1240 /* 1241 * Each XMAC chip is attached as a separate logical IP interface. 1242 * Single port cards will have only one logical interface of course. 1243 */ 1244 static int 1245 sk_attach(device_t dev) 1246 { 1247 struct sk_softc *sc; 1248 struct sk_if_softc *sc_if; 1249 if_t ifp; 1250 u_int32_t r; 1251 int error, i, phy, port; 1252 u_char eaddr[6]; 1253 u_char inv_mac[] = {0, 0, 0, 0, 0, 0}; 1254 1255 if (dev == NULL) 1256 return(EINVAL); 1257 1258 error = 0; 1259 sc_if = device_get_softc(dev); 1260 sc = device_get_softc(device_get_parent(dev)); 1261 port = *(int *)device_get_ivars(dev); 1262 1263 sc_if->sk_if_dev = dev; 1264 sc_if->sk_port = port; 1265 sc_if->sk_softc = sc; 1266 sc->sk_if[port] = sc_if; 1267 if (port == SK_PORT_A) 1268 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1269 if (port == SK_PORT_B) 1270 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1271 1272 callout_init_mtx(&sc_if->sk_tick_ch, &sc_if->sk_softc->sk_mtx, 0); 1273 callout_init_mtx(&sc_if->sk_watchdog_ch, &sc_if->sk_softc->sk_mtx, 0); 1274 1275 if (sk_dma_alloc(sc_if) != 0) { 1276 error = ENOMEM; 1277 goto fail; 1278 } 1279 sk_dma_jumbo_alloc(sc_if); 1280 1281 ifp = sc_if->sk_ifp = if_alloc(IFT_ETHER); 1282 if_setsoftc(ifp, sc_if); 1283 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1284 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 1285 /* 1286 * SK_GENESIS has a bug in checksum offload - From linux. 1287 */ 1288 if (sc_if->sk_softc->sk_type != SK_GENESIS) { 1289 if_setcapabilities(ifp, IFCAP_TXCSUM | IFCAP_RXCSUM); 1290 if_sethwassist(ifp, 0); 1291 } else { 1292 if_setcapabilities(ifp, 0); 1293 if_sethwassist(ifp, 0); 1294 } 1295 if_setcapenable(ifp, if_getcapabilities(ifp)); 1296 /* 1297 * Some revision of Yukon controller generates corrupted 1298 * frame when TX checksum offloading is enabled. The 1299 * frame has a valid checksum value so payload might be 1300 * modified during TX checksum calculation. Disable TX 1301 * checksum offloading but give users chance to enable it 1302 * when they know their controller works without problems 1303 * with TX checksum offloading. 1304 */ 1305 if_setcapenablebit(ifp, 0, IFCAP_TXCSUM); 1306 if_setioctlfn(ifp, sk_ioctl); 1307 if_setstartfn(ifp, sk_start); 1308 if_setinitfn(ifp, sk_init); 1309 if_setsendqlen(ifp, SK_TX_RING_CNT - 1); 1310 if_setsendqready(ifp); 1311 1312 /* 1313 * Get station address for this interface. Note that 1314 * dual port cards actually come with three station 1315 * addresses: one for each port, plus an extra. The 1316 * extra one is used by the SysKonnect driver software 1317 * as a 'virtual' station address for when both ports 1318 * are operating in failover mode. Currently we don't 1319 * use this extra address. 1320 */ 1321 SK_IF_LOCK(sc_if); 1322 for (i = 0; i < ETHER_ADDR_LEN; i++) 1323 eaddr[i] = 1324 sk_win_read_1(sc, SK_MAC0_0 + (port * 8) + i); 1325 1326 /* Verify whether the station address is invalid or not. */ 1327 if (bcmp(eaddr, inv_mac, sizeof(inv_mac)) == 0) { 1328 device_printf(sc_if->sk_if_dev, 1329 "Generating random ethernet address\n"); 1330 r = arc4random(); 1331 /* 1332 * Set OUI to convenient locally assigned address. 'b' 1333 * is 0x62, which has the locally assigned bit set, and 1334 * the broadcast/multicast bit clear. 1335 */ 1336 eaddr[0] = 'b'; 1337 eaddr[1] = 's'; 1338 eaddr[2] = 'd'; 1339 eaddr[3] = (r >> 16) & 0xff; 1340 eaddr[4] = (r >> 8) & 0xff; 1341 eaddr[5] = (r >> 0) & 0xff; 1342 } 1343 /* 1344 * Set up RAM buffer addresses. The NIC will have a certain 1345 * amount of SRAM on it, somewhere between 512K and 2MB. We 1346 * need to divide this up a) between the transmitter and 1347 * receiver and b) between the two XMACs, if this is a 1348 * dual port NIC. Our algotithm is to divide up the memory 1349 * evenly so that everyone gets a fair share. 1350 * 1351 * Just to be contrary, Yukon2 appears to have separate memory 1352 * for each MAC. 1353 */ 1354 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1355 u_int32_t chunk, val; 1356 1357 chunk = sc->sk_ramsize / 2; 1358 val = sc->sk_rboff / sizeof(u_int64_t); 1359 sc_if->sk_rx_ramstart = val; 1360 val += (chunk / sizeof(u_int64_t)); 1361 sc_if->sk_rx_ramend = val - 1; 1362 sc_if->sk_tx_ramstart = val; 1363 val += (chunk / sizeof(u_int64_t)); 1364 sc_if->sk_tx_ramend = val - 1; 1365 } else { 1366 u_int32_t chunk, val; 1367 1368 chunk = sc->sk_ramsize / 4; 1369 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1370 sizeof(u_int64_t); 1371 sc_if->sk_rx_ramstart = val; 1372 val += (chunk / sizeof(u_int64_t)); 1373 sc_if->sk_rx_ramend = val - 1; 1374 sc_if->sk_tx_ramstart = val; 1375 val += (chunk / sizeof(u_int64_t)); 1376 sc_if->sk_tx_ramend = val - 1; 1377 } 1378 1379 /* Read and save PHY type and set PHY address */ 1380 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1381 if (!SK_YUKON_FAMILY(sc->sk_type)) { 1382 switch(sc_if->sk_phytype) { 1383 case SK_PHYTYPE_XMAC: 1384 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1385 break; 1386 case SK_PHYTYPE_BCOM: 1387 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1388 break; 1389 default: 1390 device_printf(sc->sk_dev, "unsupported PHY type: %d\n", 1391 sc_if->sk_phytype); 1392 error = ENODEV; 1393 SK_IF_UNLOCK(sc_if); 1394 goto fail; 1395 } 1396 } else { 1397 if (sc_if->sk_phytype < SK_PHYTYPE_MARV_COPPER && 1398 sc->sk_pmd != 'S') { 1399 /* not initialized, punt */ 1400 sc_if->sk_phytype = SK_PHYTYPE_MARV_COPPER; 1401 sc->sk_coppertype = 1; 1402 } 1403 1404 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1405 1406 if (!(sc->sk_coppertype)) 1407 sc_if->sk_phytype = SK_PHYTYPE_MARV_FIBER; 1408 } 1409 1410 /* 1411 * Call MI attach routine. Can't hold locks when calling into ether_*. 1412 */ 1413 SK_IF_UNLOCK(sc_if); 1414 ether_ifattach(ifp, eaddr); 1415 SK_IF_LOCK(sc_if); 1416 1417 /* 1418 * The hardware should be ready for VLAN_MTU by default: 1419 * XMAC II has 0x8100 in VLAN Tag Level 1 register initially; 1420 * YU_SMR_MFL_VLAN is set by this driver in Yukon. 1421 * 1422 */ 1423 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU, 0); 1424 if_setcapenablebit(ifp, IFCAP_VLAN_MTU, 0); 1425 /* 1426 * Tell the upper layer(s) we support long frames. 1427 * Must appear after the call to ether_ifattach() because 1428 * ether_ifattach() sets ifi_hdrlen to the default value. 1429 */ 1430 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 1431 1432 /* 1433 * Do miibus setup. 1434 */ 1435 phy = MII_PHY_ANY; 1436 switch (sc->sk_type) { 1437 case SK_GENESIS: 1438 sk_init_xmac(sc_if); 1439 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 1440 phy = 0; 1441 break; 1442 case SK_YUKON: 1443 case SK_YUKON_LITE: 1444 case SK_YUKON_LP: 1445 sk_init_yukon(sc_if); 1446 phy = 0; 1447 break; 1448 } 1449 1450 SK_IF_UNLOCK(sc_if); 1451 error = mii_attach(dev, &sc_if->sk_miibus, ifp, sk_ifmedia_upd, 1452 sk_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0); 1453 if (error != 0) { 1454 device_printf(sc_if->sk_if_dev, "attaching PHYs failed\n"); 1455 ether_ifdetach(ifp); 1456 goto fail; 1457 } 1458 1459 fail: 1460 if (error) { 1461 /* Access should be ok even though lock has been dropped */ 1462 sc->sk_if[port] = NULL; 1463 sk_detach(dev); 1464 } 1465 1466 return(error); 1467 } 1468 1469 /* 1470 * Attach the interface. Allocate softc structures, do ifmedia 1471 * setup and ethernet/BPF attach. 1472 */ 1473 static int 1474 skc_attach(device_t dev) 1475 { 1476 struct sk_softc *sc; 1477 int error = 0, *port; 1478 uint8_t skrs; 1479 const char *pname = NULL; 1480 char *revstr; 1481 1482 sc = device_get_softc(dev); 1483 sc->sk_dev = dev; 1484 1485 mtx_init(&sc->sk_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1486 MTX_DEF); 1487 mtx_init(&sc->sk_mii_mtx, "sk_mii_mutex", NULL, MTX_DEF); 1488 /* 1489 * Map control/status registers. 1490 */ 1491 pci_enable_busmaster(dev); 1492 1493 /* Allocate resources */ 1494 #ifdef SK_USEIOSPACE 1495 sc->sk_res_spec = sk_res_spec_io; 1496 #else 1497 sc->sk_res_spec = sk_res_spec_mem; 1498 #endif 1499 error = bus_alloc_resources(dev, sc->sk_res_spec, sc->sk_res); 1500 if (error) { 1501 if (sc->sk_res_spec == sk_res_spec_mem) 1502 sc->sk_res_spec = sk_res_spec_io; 1503 else 1504 sc->sk_res_spec = sk_res_spec_mem; 1505 error = bus_alloc_resources(dev, sc->sk_res_spec, sc->sk_res); 1506 if (error) { 1507 device_printf(dev, "couldn't allocate %s resources\n", 1508 sc->sk_res_spec == sk_res_spec_mem ? "memory" : 1509 "I/O"); 1510 goto fail; 1511 } 1512 } 1513 1514 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1515 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4) & 0xf; 1516 1517 /* Bail out if chip is not recognized. */ 1518 if (sc->sk_type != SK_GENESIS && !SK_YUKON_FAMILY(sc->sk_type)) { 1519 device_printf(dev, "unknown device: chipver=%02x, rev=%x\n", 1520 sc->sk_type, sc->sk_rev); 1521 error = ENXIO; 1522 goto fail; 1523 } 1524 1525 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 1526 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 1527 OID_AUTO, "int_mod", 1528 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 1529 &sc->sk_int_mod, 0, sysctl_hw_sk_int_mod, "I", 1530 "SK interrupt moderation"); 1531 1532 /* Pull in device tunables. */ 1533 sc->sk_int_mod = SK_IM_DEFAULT; 1534 error = resource_int_value(device_get_name(dev), device_get_unit(dev), 1535 "int_mod", &sc->sk_int_mod); 1536 if (error == 0) { 1537 if (sc->sk_int_mod < SK_IM_MIN || 1538 sc->sk_int_mod > SK_IM_MAX) { 1539 device_printf(dev, "int_mod value out of range; " 1540 "using default: %d\n", SK_IM_DEFAULT); 1541 sc->sk_int_mod = SK_IM_DEFAULT; 1542 } 1543 } 1544 1545 /* Reset the adapter. */ 1546 sk_reset(sc); 1547 1548 skrs = sk_win_read_1(sc, SK_EPROM0); 1549 if (sc->sk_type == SK_GENESIS) { 1550 /* Read and save RAM size and RAMbuffer offset */ 1551 switch(skrs) { 1552 case SK_RAMSIZE_512K_64: 1553 sc->sk_ramsize = 0x80000; 1554 sc->sk_rboff = SK_RBOFF_0; 1555 break; 1556 case SK_RAMSIZE_1024K_64: 1557 sc->sk_ramsize = 0x100000; 1558 sc->sk_rboff = SK_RBOFF_80000; 1559 break; 1560 case SK_RAMSIZE_1024K_128: 1561 sc->sk_ramsize = 0x100000; 1562 sc->sk_rboff = SK_RBOFF_0; 1563 break; 1564 case SK_RAMSIZE_2048K_128: 1565 sc->sk_ramsize = 0x200000; 1566 sc->sk_rboff = SK_RBOFF_0; 1567 break; 1568 default: 1569 device_printf(dev, "unknown ram size: %d\n", skrs); 1570 error = ENXIO; 1571 goto fail; 1572 } 1573 } else { /* SK_YUKON_FAMILY */ 1574 if (skrs == 0x00) 1575 sc->sk_ramsize = 0x20000; 1576 else 1577 sc->sk_ramsize = skrs * (1<<12); 1578 sc->sk_rboff = SK_RBOFF_0; 1579 } 1580 1581 /* Read and save physical media type */ 1582 sc->sk_pmd = sk_win_read_1(sc, SK_PMDTYPE); 1583 1584 if (sc->sk_pmd == 'T' || sc->sk_pmd == '1') 1585 sc->sk_coppertype = 1; 1586 else 1587 sc->sk_coppertype = 0; 1588 1589 /* Determine whether to name it with VPD PN or just make it up. 1590 * Marvell Yukon VPD PN seems to freqently be bogus. */ 1591 switch (pci_get_device(dev)) { 1592 case DEVICEID_SK_V1: 1593 case DEVICEID_BELKIN_5005: 1594 case DEVICEID_3COM_3C940: 1595 case DEVICEID_LINKSYS_EG1032: 1596 case DEVICEID_DLINK_DGE530T_A1: 1597 case DEVICEID_DLINK_DGE530T_B1: 1598 /* Stay with VPD PN. */ 1599 (void) pci_get_vpd_ident(dev, &pname); 1600 break; 1601 case DEVICEID_SK_V2: 1602 /* YUKON VPD PN might bear no resemblance to reality. */ 1603 switch (sc->sk_type) { 1604 case SK_GENESIS: 1605 /* Stay with VPD PN. */ 1606 (void) pci_get_vpd_ident(dev, &pname); 1607 break; 1608 case SK_YUKON: 1609 pname = "Marvell Yukon Gigabit Ethernet"; 1610 break; 1611 case SK_YUKON_LITE: 1612 pname = "Marvell Yukon Lite Gigabit Ethernet"; 1613 break; 1614 case SK_YUKON_LP: 1615 pname = "Marvell Yukon LP Gigabit Ethernet"; 1616 break; 1617 default: 1618 pname = "Marvell Yukon (Unknown) Gigabit Ethernet"; 1619 break; 1620 } 1621 1622 /* Yukon Lite Rev. A0 needs special test. */ 1623 if (sc->sk_type == SK_YUKON || sc->sk_type == SK_YUKON_LP) { 1624 u_int32_t far; 1625 u_int8_t testbyte; 1626 1627 /* Save flash address register before testing. */ 1628 far = sk_win_read_4(sc, SK_EP_ADDR); 1629 1630 sk_win_write_1(sc, SK_EP_ADDR+0x03, 0xff); 1631 testbyte = sk_win_read_1(sc, SK_EP_ADDR+0x03); 1632 1633 if (testbyte != 0x00) { 1634 /* Yukon Lite Rev. A0 detected. */ 1635 sc->sk_type = SK_YUKON_LITE; 1636 sc->sk_rev = SK_YUKON_LITE_REV_A0; 1637 /* Restore flash address register. */ 1638 sk_win_write_4(sc, SK_EP_ADDR, far); 1639 } 1640 } 1641 break; 1642 default: 1643 device_printf(dev, "unknown device: vendor=%04x, device=%04x, " 1644 "chipver=%02x, rev=%x\n", 1645 pci_get_vendor(dev), pci_get_device(dev), 1646 sc->sk_type, sc->sk_rev); 1647 error = ENXIO; 1648 goto fail; 1649 } 1650 1651 if (sc->sk_type == SK_YUKON_LITE) { 1652 switch (sc->sk_rev) { 1653 case SK_YUKON_LITE_REV_A0: 1654 revstr = "A0"; 1655 break; 1656 case SK_YUKON_LITE_REV_A1: 1657 revstr = "A1"; 1658 break; 1659 case SK_YUKON_LITE_REV_A3: 1660 revstr = "A3"; 1661 break; 1662 default: 1663 revstr = ""; 1664 break; 1665 } 1666 } else { 1667 revstr = ""; 1668 } 1669 1670 /* Announce the product name and more VPD data if there. */ 1671 if (pname != NULL) 1672 device_printf(dev, "%s rev. %s(0x%x)\n", 1673 pname, revstr, sc->sk_rev); 1674 1675 if (bootverbose) { 1676 device_printf(dev, "chip ver = 0x%02x\n", sc->sk_type); 1677 device_printf(dev, "chip rev = 0x%02x\n", sc->sk_rev); 1678 device_printf(dev, "SK_EPROM0 = 0x%02x\n", skrs); 1679 device_printf(dev, "SRAM size = 0x%06x\n", sc->sk_ramsize); 1680 } 1681 1682 sc->sk_devs[SK_PORT_A] = device_add_child(dev, "sk", DEVICE_UNIT_ANY); 1683 if (sc->sk_devs[SK_PORT_A] == NULL) { 1684 device_printf(dev, "failed to add child for PORT_A\n"); 1685 error = ENXIO; 1686 goto fail; 1687 } 1688 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT); 1689 if (port == NULL) { 1690 device_printf(dev, "failed to allocate memory for " 1691 "ivars of PORT_A\n"); 1692 error = ENXIO; 1693 goto fail; 1694 } 1695 *port = SK_PORT_A; 1696 device_set_ivars(sc->sk_devs[SK_PORT_A], port); 1697 1698 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1699 sc->sk_devs[SK_PORT_B] = device_add_child(dev, "sk", DEVICE_UNIT_ANY); 1700 if (sc->sk_devs[SK_PORT_B] == NULL) { 1701 device_printf(dev, "failed to add child for PORT_B\n"); 1702 error = ENXIO; 1703 goto fail; 1704 } 1705 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT); 1706 if (port == NULL) { 1707 device_printf(dev, "failed to allocate memory for " 1708 "ivars of PORT_B\n"); 1709 error = ENXIO; 1710 goto fail; 1711 } 1712 *port = SK_PORT_B; 1713 device_set_ivars(sc->sk_devs[SK_PORT_B], port); 1714 } 1715 1716 /* Turn on the 'driver is loaded' LED. */ 1717 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1718 1719 error = bus_generic_attach(dev); 1720 if (error) { 1721 device_printf(dev, "failed to attach port(s)\n"); 1722 goto fail; 1723 } 1724 1725 /* Hook interrupt last to avoid having to lock softc */ 1726 error = bus_setup_intr(dev, sc->sk_res[1], INTR_TYPE_NET|INTR_MPSAFE, 1727 NULL, sk_intr, sc, &sc->sk_intrhand); 1728 1729 if (error) { 1730 device_printf(dev, "couldn't set up irq\n"); 1731 goto fail; 1732 } 1733 1734 fail: 1735 if (error) 1736 skc_detach(dev); 1737 1738 return(error); 1739 } 1740 1741 /* 1742 * Shutdown hardware and free up resources. This can be called any 1743 * time after the mutex has been initialized. It is called in both 1744 * the error case in attach and the normal detach case so it needs 1745 * to be careful about only freeing resources that have actually been 1746 * allocated. 1747 */ 1748 static int 1749 sk_detach(device_t dev) 1750 { 1751 struct sk_if_softc *sc_if; 1752 if_t ifp; 1753 1754 sc_if = device_get_softc(dev); 1755 KASSERT(mtx_initialized(&sc_if->sk_softc->sk_mtx), 1756 ("sk mutex not initialized in sk_detach")); 1757 SK_IF_LOCK(sc_if); 1758 1759 ifp = sc_if->sk_ifp; 1760 /* These should only be active if attach_xmac succeeded */ 1761 if (device_is_attached(dev)) { 1762 sk_stop(sc_if); 1763 /* Can't hold locks while calling detach */ 1764 SK_IF_UNLOCK(sc_if); 1765 callout_drain(&sc_if->sk_tick_ch); 1766 callout_drain(&sc_if->sk_watchdog_ch); 1767 ether_ifdetach(ifp); 1768 SK_IF_LOCK(sc_if); 1769 } 1770 /* 1771 * We're generally called from skc_detach() which is using 1772 * device_delete_child() to get to here. It's already trashed 1773 * miibus for us, so don't do it here or we'll panic. 1774 */ 1775 /* 1776 if (sc_if->sk_miibus != NULL) 1777 device_delete_child(dev, sc_if->sk_miibus); 1778 */ 1779 bus_generic_detach(dev); 1780 sk_dma_jumbo_free(sc_if); 1781 sk_dma_free(sc_if); 1782 SK_IF_UNLOCK(sc_if); 1783 if (ifp) 1784 if_free(ifp); 1785 1786 return(0); 1787 } 1788 1789 static int 1790 skc_detach(device_t dev) 1791 { 1792 struct sk_softc *sc; 1793 1794 sc = device_get_softc(dev); 1795 KASSERT(mtx_initialized(&sc->sk_mtx), ("sk mutex not initialized")); 1796 1797 if (device_is_alive(dev)) { 1798 if (sc->sk_devs[SK_PORT_A] != NULL) { 1799 free(device_get_ivars(sc->sk_devs[SK_PORT_A]), M_DEVBUF); 1800 device_delete_child(dev, sc->sk_devs[SK_PORT_A]); 1801 } 1802 if (sc->sk_devs[SK_PORT_B] != NULL) { 1803 free(device_get_ivars(sc->sk_devs[SK_PORT_B]), M_DEVBUF); 1804 device_delete_child(dev, sc->sk_devs[SK_PORT_B]); 1805 } 1806 bus_generic_detach(dev); 1807 } 1808 1809 if (sc->sk_intrhand) 1810 bus_teardown_intr(dev, sc->sk_res[1], sc->sk_intrhand); 1811 bus_release_resources(dev, sc->sk_res_spec, sc->sk_res); 1812 1813 mtx_destroy(&sc->sk_mii_mtx); 1814 mtx_destroy(&sc->sk_mtx); 1815 1816 return(0); 1817 } 1818 1819 static bus_dma_tag_t 1820 skc_get_dma_tag(device_t bus, device_t child __unused) 1821 { 1822 1823 return (bus_get_dma_tag(bus)); 1824 } 1825 1826 struct sk_dmamap_arg { 1827 bus_addr_t sk_busaddr; 1828 }; 1829 1830 static void 1831 sk_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1832 { 1833 struct sk_dmamap_arg *ctx; 1834 1835 if (error != 0) 1836 return; 1837 1838 ctx = arg; 1839 ctx->sk_busaddr = segs[0].ds_addr; 1840 } 1841 1842 /* 1843 * Allocate jumbo buffer storage. The SysKonnect adapters support 1844 * "jumbograms" (9K frames), although SysKonnect doesn't currently 1845 * use them in their drivers. In order for us to use them, we need 1846 * large 9K receive buffers, however standard mbuf clusters are only 1847 * 2048 bytes in size. Consequently, we need to allocate and manage 1848 * our own jumbo buffer pool. Fortunately, this does not require an 1849 * excessive amount of additional code. 1850 */ 1851 static int 1852 sk_dma_alloc(struct sk_if_softc *sc_if) 1853 { 1854 struct sk_dmamap_arg ctx; 1855 struct sk_txdesc *txd; 1856 struct sk_rxdesc *rxd; 1857 int error, i; 1858 1859 /* create parent tag */ 1860 /* 1861 * XXX 1862 * This driver should use BUS_SPACE_MAXADDR for lowaddr argument 1863 * in bus_dma_tag_create(9) as the NIC would support DAC mode. 1864 * However bz@ reported that it does not work on amd64 with > 4GB 1865 * RAM. Until we have more clues of the breakage, disable DAC mode 1866 * by limiting DMA address to be in 32bit address space. 1867 */ 1868 error = bus_dma_tag_create( 1869 bus_get_dma_tag(sc_if->sk_if_dev),/* parent */ 1870 1, 0, /* algnmnt, boundary */ 1871 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1872 BUS_SPACE_MAXADDR, /* highaddr */ 1873 NULL, NULL, /* filter, filterarg */ 1874 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1875 0, /* nsegments */ 1876 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1877 0, /* flags */ 1878 NULL, NULL, /* lockfunc, lockarg */ 1879 &sc_if->sk_cdata.sk_parent_tag); 1880 if (error != 0) { 1881 device_printf(sc_if->sk_if_dev, 1882 "failed to create parent DMA tag\n"); 1883 goto fail; 1884 } 1885 1886 /* create tag for Tx ring */ 1887 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */ 1888 SK_RING_ALIGN, 0, /* algnmnt, boundary */ 1889 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1890 BUS_SPACE_MAXADDR, /* highaddr */ 1891 NULL, NULL, /* filter, filterarg */ 1892 SK_TX_RING_SZ, /* maxsize */ 1893 1, /* nsegments */ 1894 SK_TX_RING_SZ, /* maxsegsize */ 1895 0, /* flags */ 1896 NULL, NULL, /* lockfunc, lockarg */ 1897 &sc_if->sk_cdata.sk_tx_ring_tag); 1898 if (error != 0) { 1899 device_printf(sc_if->sk_if_dev, 1900 "failed to allocate Tx ring DMA tag\n"); 1901 goto fail; 1902 } 1903 1904 /* create tag for Rx ring */ 1905 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */ 1906 SK_RING_ALIGN, 0, /* algnmnt, boundary */ 1907 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1908 BUS_SPACE_MAXADDR, /* highaddr */ 1909 NULL, NULL, /* filter, filterarg */ 1910 SK_RX_RING_SZ, /* maxsize */ 1911 1, /* nsegments */ 1912 SK_RX_RING_SZ, /* maxsegsize */ 1913 0, /* flags */ 1914 NULL, NULL, /* lockfunc, lockarg */ 1915 &sc_if->sk_cdata.sk_rx_ring_tag); 1916 if (error != 0) { 1917 device_printf(sc_if->sk_if_dev, 1918 "failed to allocate Rx ring DMA tag\n"); 1919 goto fail; 1920 } 1921 1922 /* create tag for Tx buffers */ 1923 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */ 1924 1, 0, /* algnmnt, boundary */ 1925 BUS_SPACE_MAXADDR, /* lowaddr */ 1926 BUS_SPACE_MAXADDR, /* highaddr */ 1927 NULL, NULL, /* filter, filterarg */ 1928 MCLBYTES * SK_MAXTXSEGS, /* maxsize */ 1929 SK_MAXTXSEGS, /* nsegments */ 1930 MCLBYTES, /* maxsegsize */ 1931 0, /* flags */ 1932 NULL, NULL, /* lockfunc, lockarg */ 1933 &sc_if->sk_cdata.sk_tx_tag); 1934 if (error != 0) { 1935 device_printf(sc_if->sk_if_dev, 1936 "failed to allocate Tx DMA tag\n"); 1937 goto fail; 1938 } 1939 1940 /* create tag for Rx buffers */ 1941 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */ 1942 1, 0, /* algnmnt, boundary */ 1943 BUS_SPACE_MAXADDR, /* lowaddr */ 1944 BUS_SPACE_MAXADDR, /* highaddr */ 1945 NULL, NULL, /* filter, filterarg */ 1946 MCLBYTES, /* maxsize */ 1947 1, /* nsegments */ 1948 MCLBYTES, /* maxsegsize */ 1949 0, /* flags */ 1950 NULL, NULL, /* lockfunc, lockarg */ 1951 &sc_if->sk_cdata.sk_rx_tag); 1952 if (error != 0) { 1953 device_printf(sc_if->sk_if_dev, 1954 "failed to allocate Rx DMA tag\n"); 1955 goto fail; 1956 } 1957 1958 /* allocate DMA'able memory and load the DMA map for Tx ring */ 1959 error = bus_dmamem_alloc(sc_if->sk_cdata.sk_tx_ring_tag, 1960 (void **)&sc_if->sk_rdata.sk_tx_ring, BUS_DMA_NOWAIT | 1961 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->sk_cdata.sk_tx_ring_map); 1962 if (error != 0) { 1963 device_printf(sc_if->sk_if_dev, 1964 "failed to allocate DMA'able memory for Tx ring\n"); 1965 goto fail; 1966 } 1967 1968 ctx.sk_busaddr = 0; 1969 error = bus_dmamap_load(sc_if->sk_cdata.sk_tx_ring_tag, 1970 sc_if->sk_cdata.sk_tx_ring_map, sc_if->sk_rdata.sk_tx_ring, 1971 SK_TX_RING_SZ, sk_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 1972 if (error != 0) { 1973 device_printf(sc_if->sk_if_dev, 1974 "failed to load DMA'able memory for Tx ring\n"); 1975 goto fail; 1976 } 1977 sc_if->sk_rdata.sk_tx_ring_paddr = ctx.sk_busaddr; 1978 1979 /* allocate DMA'able memory and load the DMA map for Rx ring */ 1980 error = bus_dmamem_alloc(sc_if->sk_cdata.sk_rx_ring_tag, 1981 (void **)&sc_if->sk_rdata.sk_rx_ring, BUS_DMA_NOWAIT | 1982 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->sk_cdata.sk_rx_ring_map); 1983 if (error != 0) { 1984 device_printf(sc_if->sk_if_dev, 1985 "failed to allocate DMA'able memory for Rx ring\n"); 1986 goto fail; 1987 } 1988 1989 ctx.sk_busaddr = 0; 1990 error = bus_dmamap_load(sc_if->sk_cdata.sk_rx_ring_tag, 1991 sc_if->sk_cdata.sk_rx_ring_map, sc_if->sk_rdata.sk_rx_ring, 1992 SK_RX_RING_SZ, sk_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 1993 if (error != 0) { 1994 device_printf(sc_if->sk_if_dev, 1995 "failed to load DMA'able memory for Rx ring\n"); 1996 goto fail; 1997 } 1998 sc_if->sk_rdata.sk_rx_ring_paddr = ctx.sk_busaddr; 1999 2000 /* create DMA maps for Tx buffers */ 2001 for (i = 0; i < SK_TX_RING_CNT; i++) { 2002 txd = &sc_if->sk_cdata.sk_txdesc[i]; 2003 txd->tx_m = NULL; 2004 txd->tx_dmamap = NULL; 2005 error = bus_dmamap_create(sc_if->sk_cdata.sk_tx_tag, 0, 2006 &txd->tx_dmamap); 2007 if (error != 0) { 2008 device_printf(sc_if->sk_if_dev, 2009 "failed to create Tx dmamap\n"); 2010 goto fail; 2011 } 2012 } 2013 2014 /* create DMA maps for Rx buffers */ 2015 if ((error = bus_dmamap_create(sc_if->sk_cdata.sk_rx_tag, 0, 2016 &sc_if->sk_cdata.sk_rx_sparemap)) != 0) { 2017 device_printf(sc_if->sk_if_dev, 2018 "failed to create spare Rx dmamap\n"); 2019 goto fail; 2020 } 2021 for (i = 0; i < SK_RX_RING_CNT; i++) { 2022 rxd = &sc_if->sk_cdata.sk_rxdesc[i]; 2023 rxd->rx_m = NULL; 2024 rxd->rx_dmamap = NULL; 2025 error = bus_dmamap_create(sc_if->sk_cdata.sk_rx_tag, 0, 2026 &rxd->rx_dmamap); 2027 if (error != 0) { 2028 device_printf(sc_if->sk_if_dev, 2029 "failed to create Rx dmamap\n"); 2030 goto fail; 2031 } 2032 } 2033 2034 fail: 2035 return (error); 2036 } 2037 2038 static int 2039 sk_dma_jumbo_alloc(struct sk_if_softc *sc_if) 2040 { 2041 struct sk_dmamap_arg ctx; 2042 struct sk_rxdesc *jrxd; 2043 int error, i; 2044 2045 if (jumbo_disable != 0) { 2046 device_printf(sc_if->sk_if_dev, "disabling jumbo frame support\n"); 2047 sc_if->sk_jumbo_disable = 1; 2048 return (0); 2049 } 2050 /* create tag for jumbo Rx ring */ 2051 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */ 2052 SK_RING_ALIGN, 0, /* algnmnt, boundary */ 2053 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 2054 BUS_SPACE_MAXADDR, /* highaddr */ 2055 NULL, NULL, /* filter, filterarg */ 2056 SK_JUMBO_RX_RING_SZ, /* maxsize */ 2057 1, /* nsegments */ 2058 SK_JUMBO_RX_RING_SZ, /* maxsegsize */ 2059 0, /* flags */ 2060 NULL, NULL, /* lockfunc, lockarg */ 2061 &sc_if->sk_cdata.sk_jumbo_rx_ring_tag); 2062 if (error != 0) { 2063 device_printf(sc_if->sk_if_dev, 2064 "failed to allocate jumbo Rx ring DMA tag\n"); 2065 goto jumbo_fail; 2066 } 2067 2068 /* create tag for jumbo Rx buffers */ 2069 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */ 2070 1, 0, /* algnmnt, boundary */ 2071 BUS_SPACE_MAXADDR, /* lowaddr */ 2072 BUS_SPACE_MAXADDR, /* highaddr */ 2073 NULL, NULL, /* filter, filterarg */ 2074 MJUM9BYTES, /* maxsize */ 2075 1, /* nsegments */ 2076 MJUM9BYTES, /* maxsegsize */ 2077 0, /* flags */ 2078 NULL, NULL, /* lockfunc, lockarg */ 2079 &sc_if->sk_cdata.sk_jumbo_rx_tag); 2080 if (error != 0) { 2081 device_printf(sc_if->sk_if_dev, 2082 "failed to allocate jumbo Rx DMA tag\n"); 2083 goto jumbo_fail; 2084 } 2085 2086 /* allocate DMA'able memory and load the DMA map for jumbo Rx ring */ 2087 error = bus_dmamem_alloc(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 2088 (void **)&sc_if->sk_rdata.sk_jumbo_rx_ring, BUS_DMA_NOWAIT | 2089 BUS_DMA_COHERENT | BUS_DMA_ZERO, 2090 &sc_if->sk_cdata.sk_jumbo_rx_ring_map); 2091 if (error != 0) { 2092 device_printf(sc_if->sk_if_dev, 2093 "failed to allocate DMA'able memory for jumbo Rx ring\n"); 2094 goto jumbo_fail; 2095 } 2096 2097 ctx.sk_busaddr = 0; 2098 error = bus_dmamap_load(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 2099 sc_if->sk_cdata.sk_jumbo_rx_ring_map, 2100 sc_if->sk_rdata.sk_jumbo_rx_ring, SK_JUMBO_RX_RING_SZ, sk_dmamap_cb, 2101 &ctx, BUS_DMA_NOWAIT); 2102 if (error != 0) { 2103 device_printf(sc_if->sk_if_dev, 2104 "failed to load DMA'able memory for jumbo Rx ring\n"); 2105 goto jumbo_fail; 2106 } 2107 sc_if->sk_rdata.sk_jumbo_rx_ring_paddr = ctx.sk_busaddr; 2108 2109 /* create DMA maps for jumbo Rx buffers */ 2110 if ((error = bus_dmamap_create(sc_if->sk_cdata.sk_jumbo_rx_tag, 0, 2111 &sc_if->sk_cdata.sk_jumbo_rx_sparemap)) != 0) { 2112 device_printf(sc_if->sk_if_dev, 2113 "failed to create spare jumbo Rx dmamap\n"); 2114 goto jumbo_fail; 2115 } 2116 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) { 2117 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i]; 2118 jrxd->rx_m = NULL; 2119 jrxd->rx_dmamap = NULL; 2120 error = bus_dmamap_create(sc_if->sk_cdata.sk_jumbo_rx_tag, 0, 2121 &jrxd->rx_dmamap); 2122 if (error != 0) { 2123 device_printf(sc_if->sk_if_dev, 2124 "failed to create jumbo Rx dmamap\n"); 2125 goto jumbo_fail; 2126 } 2127 } 2128 2129 return (0); 2130 2131 jumbo_fail: 2132 sk_dma_jumbo_free(sc_if); 2133 device_printf(sc_if->sk_if_dev, "disabling jumbo frame support due to " 2134 "resource shortage\n"); 2135 sc_if->sk_jumbo_disable = 1; 2136 return (0); 2137 } 2138 2139 static void 2140 sk_dma_free(struct sk_if_softc *sc_if) 2141 { 2142 struct sk_txdesc *txd; 2143 struct sk_rxdesc *rxd; 2144 int i; 2145 2146 /* Tx ring */ 2147 if (sc_if->sk_cdata.sk_tx_ring_tag) { 2148 if (sc_if->sk_rdata.sk_tx_ring_paddr) 2149 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_ring_tag, 2150 sc_if->sk_cdata.sk_tx_ring_map); 2151 if (sc_if->sk_rdata.sk_tx_ring) 2152 bus_dmamem_free(sc_if->sk_cdata.sk_tx_ring_tag, 2153 sc_if->sk_rdata.sk_tx_ring, 2154 sc_if->sk_cdata.sk_tx_ring_map); 2155 sc_if->sk_rdata.sk_tx_ring = NULL; 2156 sc_if->sk_rdata.sk_tx_ring_paddr = 0; 2157 bus_dma_tag_destroy(sc_if->sk_cdata.sk_tx_ring_tag); 2158 sc_if->sk_cdata.sk_tx_ring_tag = NULL; 2159 } 2160 /* Rx ring */ 2161 if (sc_if->sk_cdata.sk_rx_ring_tag) { 2162 if (sc_if->sk_rdata.sk_rx_ring_paddr) 2163 bus_dmamap_unload(sc_if->sk_cdata.sk_rx_ring_tag, 2164 sc_if->sk_cdata.sk_rx_ring_map); 2165 if (sc_if->sk_rdata.sk_rx_ring) 2166 bus_dmamem_free(sc_if->sk_cdata.sk_rx_ring_tag, 2167 sc_if->sk_rdata.sk_rx_ring, 2168 sc_if->sk_cdata.sk_rx_ring_map); 2169 sc_if->sk_rdata.sk_rx_ring = NULL; 2170 sc_if->sk_rdata.sk_rx_ring_paddr = 0; 2171 bus_dma_tag_destroy(sc_if->sk_cdata.sk_rx_ring_tag); 2172 sc_if->sk_cdata.sk_rx_ring_tag = NULL; 2173 } 2174 /* Tx buffers */ 2175 if (sc_if->sk_cdata.sk_tx_tag) { 2176 for (i = 0; i < SK_TX_RING_CNT; i++) { 2177 txd = &sc_if->sk_cdata.sk_txdesc[i]; 2178 if (txd->tx_dmamap) { 2179 bus_dmamap_destroy(sc_if->sk_cdata.sk_tx_tag, 2180 txd->tx_dmamap); 2181 txd->tx_dmamap = NULL; 2182 } 2183 } 2184 bus_dma_tag_destroy(sc_if->sk_cdata.sk_tx_tag); 2185 sc_if->sk_cdata.sk_tx_tag = NULL; 2186 } 2187 /* Rx buffers */ 2188 if (sc_if->sk_cdata.sk_rx_tag) { 2189 for (i = 0; i < SK_RX_RING_CNT; i++) { 2190 rxd = &sc_if->sk_cdata.sk_rxdesc[i]; 2191 if (rxd->rx_dmamap) { 2192 bus_dmamap_destroy(sc_if->sk_cdata.sk_rx_tag, 2193 rxd->rx_dmamap); 2194 rxd->rx_dmamap = NULL; 2195 } 2196 } 2197 if (sc_if->sk_cdata.sk_rx_sparemap) { 2198 bus_dmamap_destroy(sc_if->sk_cdata.sk_rx_tag, 2199 sc_if->sk_cdata.sk_rx_sparemap); 2200 sc_if->sk_cdata.sk_rx_sparemap = NULL; 2201 } 2202 bus_dma_tag_destroy(sc_if->sk_cdata.sk_rx_tag); 2203 sc_if->sk_cdata.sk_rx_tag = NULL; 2204 } 2205 2206 if (sc_if->sk_cdata.sk_parent_tag) { 2207 bus_dma_tag_destroy(sc_if->sk_cdata.sk_parent_tag); 2208 sc_if->sk_cdata.sk_parent_tag = NULL; 2209 } 2210 } 2211 2212 static void 2213 sk_dma_jumbo_free(struct sk_if_softc *sc_if) 2214 { 2215 struct sk_rxdesc *jrxd; 2216 int i; 2217 2218 /* jumbo Rx ring */ 2219 if (sc_if->sk_cdata.sk_jumbo_rx_ring_tag) { 2220 if (sc_if->sk_rdata.sk_jumbo_rx_ring_paddr) 2221 bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 2222 sc_if->sk_cdata.sk_jumbo_rx_ring_map); 2223 if (sc_if->sk_rdata.sk_jumbo_rx_ring) 2224 bus_dmamem_free(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 2225 sc_if->sk_rdata.sk_jumbo_rx_ring, 2226 sc_if->sk_cdata.sk_jumbo_rx_ring_map); 2227 sc_if->sk_rdata.sk_jumbo_rx_ring = NULL; 2228 sc_if->sk_rdata.sk_jumbo_rx_ring_paddr = 0; 2229 bus_dma_tag_destroy(sc_if->sk_cdata.sk_jumbo_rx_ring_tag); 2230 sc_if->sk_cdata.sk_jumbo_rx_ring_tag = NULL; 2231 } 2232 2233 /* jumbo Rx buffers */ 2234 if (sc_if->sk_cdata.sk_jumbo_rx_tag) { 2235 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) { 2236 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i]; 2237 if (jrxd->rx_dmamap) { 2238 bus_dmamap_destroy( 2239 sc_if->sk_cdata.sk_jumbo_rx_tag, 2240 jrxd->rx_dmamap); 2241 jrxd->rx_dmamap = NULL; 2242 } 2243 } 2244 if (sc_if->sk_cdata.sk_jumbo_rx_sparemap) { 2245 bus_dmamap_destroy(sc_if->sk_cdata.sk_jumbo_rx_tag, 2246 sc_if->sk_cdata.sk_jumbo_rx_sparemap); 2247 sc_if->sk_cdata.sk_jumbo_rx_sparemap = NULL; 2248 } 2249 bus_dma_tag_destroy(sc_if->sk_cdata.sk_jumbo_rx_tag); 2250 sc_if->sk_cdata.sk_jumbo_rx_tag = NULL; 2251 } 2252 } 2253 2254 static void 2255 sk_txcksum(if_t ifp, struct mbuf *m, struct sk_tx_desc *f) 2256 { 2257 struct ip *ip; 2258 u_int16_t offset; 2259 u_int8_t *p; 2260 2261 offset = sizeof(struct ip) + ETHER_HDR_LEN; 2262 for(; m && m->m_len == 0; m = m->m_next) 2263 ; 2264 if (m == NULL || m->m_len < ETHER_HDR_LEN) { 2265 if_printf(ifp, "%s: m_len < ETHER_HDR_LEN\n", __func__); 2266 /* checksum may be corrupted */ 2267 goto sendit; 2268 } 2269 if (m->m_len < ETHER_HDR_LEN + sizeof(u_int32_t)) { 2270 if (m->m_len != ETHER_HDR_LEN) { 2271 if_printf(ifp, "%s: m_len != ETHER_HDR_LEN\n", 2272 __func__); 2273 /* checksum may be corrupted */ 2274 goto sendit; 2275 } 2276 for(m = m->m_next; m && m->m_len == 0; m = m->m_next) 2277 ; 2278 if (m == NULL) { 2279 offset = sizeof(struct ip) + ETHER_HDR_LEN; 2280 /* checksum may be corrupted */ 2281 goto sendit; 2282 } 2283 ip = mtod(m, struct ip *); 2284 } else { 2285 p = mtod(m, u_int8_t *); 2286 p += ETHER_HDR_LEN; 2287 ip = (struct ip *)p; 2288 } 2289 offset = (ip->ip_hl << 2) + ETHER_HDR_LEN; 2290 2291 sendit: 2292 f->sk_csum_startval = 0; 2293 f->sk_csum_start = htole32(((offset + m->m_pkthdr.csum_data) & 0xffff) | 2294 (offset << 16)); 2295 } 2296 2297 static int 2298 sk_encap(struct sk_if_softc *sc_if, struct mbuf **m_head) 2299 { 2300 struct sk_txdesc *txd; 2301 struct sk_tx_desc *f = NULL; 2302 struct mbuf *m; 2303 bus_dma_segment_t txsegs[SK_MAXTXSEGS]; 2304 u_int32_t cflags, frag, si, sk_ctl; 2305 int error, i, nseg; 2306 2307 SK_IF_LOCK_ASSERT(sc_if); 2308 2309 if ((txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txfreeq)) == NULL) 2310 return (ENOBUFS); 2311 2312 error = bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_tx_tag, 2313 txd->tx_dmamap, *m_head, txsegs, &nseg, 0); 2314 if (error == EFBIG) { 2315 m = m_defrag(*m_head, M_NOWAIT); 2316 if (m == NULL) { 2317 m_freem(*m_head); 2318 *m_head = NULL; 2319 return (ENOMEM); 2320 } 2321 *m_head = m; 2322 error = bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_tx_tag, 2323 txd->tx_dmamap, *m_head, txsegs, &nseg, 0); 2324 if (error != 0) { 2325 m_freem(*m_head); 2326 *m_head = NULL; 2327 return (error); 2328 } 2329 } else if (error != 0) 2330 return (error); 2331 if (nseg == 0) { 2332 m_freem(*m_head); 2333 *m_head = NULL; 2334 return (EIO); 2335 } 2336 if (sc_if->sk_cdata.sk_tx_cnt + nseg >= SK_TX_RING_CNT) { 2337 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap); 2338 return (ENOBUFS); 2339 } 2340 2341 m = *m_head; 2342 if ((m->m_pkthdr.csum_flags & if_gethwassist(sc_if->sk_ifp)) != 0) 2343 cflags = SK_OPCODE_CSUM; 2344 else 2345 cflags = SK_OPCODE_DEFAULT; 2346 si = frag = sc_if->sk_cdata.sk_tx_prod; 2347 for (i = 0; i < nseg; i++) { 2348 f = &sc_if->sk_rdata.sk_tx_ring[frag]; 2349 f->sk_data_lo = htole32(SK_ADDR_LO(txsegs[i].ds_addr)); 2350 f->sk_data_hi = htole32(SK_ADDR_HI(txsegs[i].ds_addr)); 2351 sk_ctl = txsegs[i].ds_len | cflags; 2352 if (i == 0) { 2353 if (cflags == SK_OPCODE_CSUM) 2354 sk_txcksum(sc_if->sk_ifp, m, f); 2355 sk_ctl |= SK_TXCTL_FIRSTFRAG; 2356 } else 2357 sk_ctl |= SK_TXCTL_OWN; 2358 f->sk_ctl = htole32(sk_ctl); 2359 sc_if->sk_cdata.sk_tx_cnt++; 2360 SK_INC(frag, SK_TX_RING_CNT); 2361 } 2362 sc_if->sk_cdata.sk_tx_prod = frag; 2363 2364 /* set EOF on the last descriptor */ 2365 frag = (frag + SK_TX_RING_CNT - 1) % SK_TX_RING_CNT; 2366 f = &sc_if->sk_rdata.sk_tx_ring[frag]; 2367 f->sk_ctl |= htole32(SK_TXCTL_LASTFRAG | SK_TXCTL_EOF_INTR); 2368 2369 /* turn the first descriptor ownership to NIC */ 2370 f = &sc_if->sk_rdata.sk_tx_ring[si]; 2371 f->sk_ctl |= htole32(SK_TXCTL_OWN); 2372 2373 STAILQ_REMOVE_HEAD(&sc_if->sk_cdata.sk_txfreeq, tx_q); 2374 STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txbusyq, txd, tx_q); 2375 txd->tx_m = m; 2376 2377 /* sync descriptors */ 2378 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap, 2379 BUS_DMASYNC_PREWRITE); 2380 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag, 2381 sc_if->sk_cdata.sk_tx_ring_map, 2382 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2383 2384 return (0); 2385 } 2386 2387 static void 2388 sk_start(if_t ifp) 2389 { 2390 struct sk_if_softc *sc_if; 2391 2392 sc_if = if_getsoftc(ifp); 2393 2394 SK_IF_LOCK(sc_if); 2395 sk_start_locked(ifp); 2396 SK_IF_UNLOCK(sc_if); 2397 2398 return; 2399 } 2400 2401 static void 2402 sk_start_locked(if_t ifp) 2403 { 2404 struct sk_softc *sc; 2405 struct sk_if_softc *sc_if; 2406 struct mbuf *m_head; 2407 int enq; 2408 2409 sc_if = if_getsoftc(ifp); 2410 sc = sc_if->sk_softc; 2411 2412 SK_IF_LOCK_ASSERT(sc_if); 2413 2414 for (enq = 0; !if_sendq_empty(ifp) && 2415 sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 1; ) { 2416 m_head = if_dequeue(ifp); 2417 if (m_head == NULL) 2418 break; 2419 2420 /* 2421 * Pack the data into the transmit ring. If we 2422 * don't have room, set the OACTIVE flag and wait 2423 * for the NIC to drain the ring. 2424 */ 2425 if (sk_encap(sc_if, &m_head)) { 2426 if (m_head == NULL) 2427 break; 2428 if_sendq_prepend(ifp, m_head); 2429 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 2430 break; 2431 } 2432 2433 enq++; 2434 /* 2435 * If there's a BPF listener, bounce a copy of this frame 2436 * to him. 2437 */ 2438 BPF_MTAP(ifp, m_head); 2439 } 2440 2441 if (enq > 0) { 2442 /* Transmit */ 2443 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 2444 2445 /* Set a timeout in case the chip goes out to lunch. */ 2446 sc_if->sk_watchdog_timer = 5; 2447 } 2448 } 2449 2450 static void 2451 sk_watchdog(void *arg) 2452 { 2453 struct sk_if_softc *sc_if; 2454 if_t ifp; 2455 2456 ifp = arg; 2457 sc_if = if_getsoftc(ifp); 2458 2459 SK_IF_LOCK_ASSERT(sc_if); 2460 2461 if (sc_if->sk_watchdog_timer == 0 || --sc_if->sk_watchdog_timer) 2462 goto done; 2463 2464 /* 2465 * Reclaim first as there is a possibility of losing Tx completion 2466 * interrupts. 2467 */ 2468 sk_txeof(sc_if); 2469 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 2470 if_printf(sc_if->sk_ifp, "watchdog timeout\n"); 2471 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2472 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2473 sk_init_locked(sc_if); 2474 } 2475 2476 done: 2477 callout_reset(&sc_if->sk_watchdog_ch, hz, sk_watchdog, ifp); 2478 2479 return; 2480 } 2481 2482 static int 2483 skc_shutdown(device_t dev) 2484 { 2485 struct sk_softc *sc; 2486 2487 sc = device_get_softc(dev); 2488 SK_LOCK(sc); 2489 2490 /* Turn off the 'driver is loaded' LED. */ 2491 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 2492 2493 /* 2494 * Reset the GEnesis controller. Doing this should also 2495 * assert the resets on the attached XMAC(s). 2496 */ 2497 sk_reset(sc); 2498 SK_UNLOCK(sc); 2499 2500 return (0); 2501 } 2502 2503 static int 2504 skc_suspend(device_t dev) 2505 { 2506 struct sk_softc *sc; 2507 struct sk_if_softc *sc_if0, *sc_if1; 2508 if_t ifp0 = NULL, ifp1 = NULL; 2509 2510 sc = device_get_softc(dev); 2511 2512 SK_LOCK(sc); 2513 2514 sc_if0 = sc->sk_if[SK_PORT_A]; 2515 sc_if1 = sc->sk_if[SK_PORT_B]; 2516 if (sc_if0 != NULL) 2517 ifp0 = sc_if0->sk_ifp; 2518 if (sc_if1 != NULL) 2519 ifp1 = sc_if1->sk_ifp; 2520 if (ifp0 != NULL) 2521 sk_stop(sc_if0); 2522 if (ifp1 != NULL) 2523 sk_stop(sc_if1); 2524 sc->sk_suspended = 1; 2525 2526 SK_UNLOCK(sc); 2527 2528 return (0); 2529 } 2530 2531 static int 2532 skc_resume(device_t dev) 2533 { 2534 struct sk_softc *sc; 2535 struct sk_if_softc *sc_if0, *sc_if1; 2536 if_t ifp0 = NULL, ifp1 = NULL; 2537 2538 sc = device_get_softc(dev); 2539 2540 SK_LOCK(sc); 2541 2542 sc_if0 = sc->sk_if[SK_PORT_A]; 2543 sc_if1 = sc->sk_if[SK_PORT_B]; 2544 if (sc_if0 != NULL) 2545 ifp0 = sc_if0->sk_ifp; 2546 if (sc_if1 != NULL) 2547 ifp1 = sc_if1->sk_ifp; 2548 if (ifp0 != NULL && if_getflags(ifp0) & IFF_UP) 2549 sk_init_locked(sc_if0); 2550 if (ifp1 != NULL && if_getflags(ifp1) & IFF_UP) 2551 sk_init_locked(sc_if1); 2552 sc->sk_suspended = 0; 2553 2554 SK_UNLOCK(sc); 2555 2556 return (0); 2557 } 2558 2559 /* 2560 * According to the data sheet from SK-NET GENESIS the hardware can compute 2561 * two Rx checksums at the same time(Each checksum start position is 2562 * programmed in Rx descriptors). However it seems that TCP/UDP checksum 2563 * does not work at least on my Yukon hardware. I tried every possible ways 2564 * to get correct checksum value but couldn't get correct one. So TCP/UDP 2565 * checksum offload was disabled at the moment and only IP checksum offload 2566 * was enabled. 2567 * As normal IP header size is 20 bytes I can't expect it would give an 2568 * increase in throughput. However it seems it doesn't hurt performance in 2569 * my testing. If there is a more detailed information for checksum secret 2570 * of the hardware in question please contact yongari@FreeBSD.org to add 2571 * TCP/UDP checksum offload support. 2572 */ 2573 static __inline void 2574 sk_rxcksum(if_t ifp, struct mbuf *m, u_int32_t csum) 2575 { 2576 struct ether_header *eh; 2577 struct ip *ip; 2578 int32_t hlen, len, pktlen; 2579 u_int16_t csum1, csum2, ipcsum; 2580 2581 pktlen = m->m_pkthdr.len; 2582 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip)) 2583 return; 2584 eh = mtod(m, struct ether_header *); 2585 if (eh->ether_type != htons(ETHERTYPE_IP)) 2586 return; 2587 ip = (struct ip *)(eh + 1); 2588 if (ip->ip_v != IPVERSION) 2589 return; 2590 hlen = ip->ip_hl << 2; 2591 pktlen -= sizeof(struct ether_header); 2592 if (hlen < sizeof(struct ip)) 2593 return; 2594 if (ntohs(ip->ip_len) < hlen) 2595 return; 2596 if (ntohs(ip->ip_len) != pktlen) 2597 return; 2598 2599 csum1 = htons(csum & 0xffff); 2600 csum2 = htons((csum >> 16) & 0xffff); 2601 ipcsum = in_addword(csum1, ~csum2 & 0xffff); 2602 /* checksum fixup for IP options */ 2603 len = hlen - sizeof(struct ip); 2604 if (len > 0) { 2605 /* 2606 * If the second checksum value is correct we can compute IP 2607 * checksum with simple math. Unfortunately the second checksum 2608 * value is wrong so we can't verify the checksum from the 2609 * value(It seems there is some magic here to get correct 2610 * value). If the second checksum value is correct it also 2611 * means we can get TCP/UDP checksum) here. However, it still 2612 * needs pseudo header checksum calculation due to hardware 2613 * limitations. 2614 */ 2615 return; 2616 } 2617 m->m_pkthdr.csum_flags = CSUM_IP_CHECKED; 2618 if (ipcsum == 0xffff) 2619 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2620 } 2621 2622 static __inline int 2623 sk_rxvalid(struct sk_softc *sc, u_int32_t stat, u_int32_t len) 2624 { 2625 2626 if (sc->sk_type == SK_GENESIS) { 2627 if ((stat & XM_RXSTAT_ERRFRAME) == XM_RXSTAT_ERRFRAME || 2628 XM_RXSTAT_BYTES(stat) != len) 2629 return (0); 2630 } else { 2631 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR | 2632 YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | 2633 YU_RXSTAT_JABBER)) != 0 || 2634 (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK || 2635 YU_RXSTAT_BYTES(stat) != len) 2636 return (0); 2637 } 2638 2639 return (1); 2640 } 2641 2642 static void 2643 sk_rxeof(struct sk_if_softc *sc_if) 2644 { 2645 struct sk_softc *sc; 2646 struct mbuf *m; 2647 if_t ifp; 2648 struct sk_rx_desc *cur_rx; 2649 struct sk_rxdesc *rxd; 2650 int cons, prog; 2651 u_int32_t csum, rxstat, sk_ctl; 2652 2653 sc = sc_if->sk_softc; 2654 ifp = sc_if->sk_ifp; 2655 2656 SK_IF_LOCK_ASSERT(sc_if); 2657 2658 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag, 2659 sc_if->sk_cdata.sk_rx_ring_map, BUS_DMASYNC_POSTREAD); 2660 2661 prog = 0; 2662 for (cons = sc_if->sk_cdata.sk_rx_cons; prog < SK_RX_RING_CNT; 2663 prog++, SK_INC(cons, SK_RX_RING_CNT)) { 2664 cur_rx = &sc_if->sk_rdata.sk_rx_ring[cons]; 2665 sk_ctl = le32toh(cur_rx->sk_ctl); 2666 if ((sk_ctl & SK_RXCTL_OWN) != 0) 2667 break; 2668 rxd = &sc_if->sk_cdata.sk_rxdesc[cons]; 2669 rxstat = le32toh(cur_rx->sk_xmac_rxstat); 2670 2671 if ((sk_ctl & (SK_RXCTL_STATUS_VALID | SK_RXCTL_FIRSTFRAG | 2672 SK_RXCTL_LASTFRAG)) != (SK_RXCTL_STATUS_VALID | 2673 SK_RXCTL_FIRSTFRAG | SK_RXCTL_LASTFRAG) || 2674 SK_RXBYTES(sk_ctl) < SK_MIN_FRAMELEN || 2675 SK_RXBYTES(sk_ctl) > SK_MAX_FRAMELEN || 2676 sk_rxvalid(sc, rxstat, SK_RXBYTES(sk_ctl)) == 0) { 2677 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2678 sk_discard_rxbuf(sc_if, cons); 2679 continue; 2680 } 2681 2682 m = rxd->rx_m; 2683 csum = le32toh(cur_rx->sk_csum); 2684 if (sk_newbuf(sc_if, cons) != 0) { 2685 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2686 /* reuse old buffer */ 2687 sk_discard_rxbuf(sc_if, cons); 2688 continue; 2689 } 2690 m->m_pkthdr.rcvif = ifp; 2691 m->m_pkthdr.len = m->m_len = SK_RXBYTES(sk_ctl); 2692 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 2693 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) 2694 sk_rxcksum(ifp, m, csum); 2695 SK_IF_UNLOCK(sc_if); 2696 if_input(ifp, m); 2697 SK_IF_LOCK(sc_if); 2698 } 2699 2700 if (prog > 0) { 2701 sc_if->sk_cdata.sk_rx_cons = cons; 2702 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag, 2703 sc_if->sk_cdata.sk_rx_ring_map, 2704 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2705 } 2706 } 2707 2708 static void 2709 sk_jumbo_rxeof(struct sk_if_softc *sc_if) 2710 { 2711 struct sk_softc *sc; 2712 struct mbuf *m; 2713 if_t ifp; 2714 struct sk_rx_desc *cur_rx; 2715 struct sk_rxdesc *jrxd; 2716 int cons, prog; 2717 u_int32_t csum, rxstat, sk_ctl; 2718 2719 sc = sc_if->sk_softc; 2720 ifp = sc_if->sk_ifp; 2721 2722 SK_IF_LOCK_ASSERT(sc_if); 2723 2724 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 2725 sc_if->sk_cdata.sk_jumbo_rx_ring_map, BUS_DMASYNC_POSTREAD); 2726 2727 prog = 0; 2728 for (cons = sc_if->sk_cdata.sk_jumbo_rx_cons; 2729 prog < SK_JUMBO_RX_RING_CNT; 2730 prog++, SK_INC(cons, SK_JUMBO_RX_RING_CNT)) { 2731 cur_rx = &sc_if->sk_rdata.sk_jumbo_rx_ring[cons]; 2732 sk_ctl = le32toh(cur_rx->sk_ctl); 2733 if ((sk_ctl & SK_RXCTL_OWN) != 0) 2734 break; 2735 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[cons]; 2736 rxstat = le32toh(cur_rx->sk_xmac_rxstat); 2737 2738 if ((sk_ctl & (SK_RXCTL_STATUS_VALID | SK_RXCTL_FIRSTFRAG | 2739 SK_RXCTL_LASTFRAG)) != (SK_RXCTL_STATUS_VALID | 2740 SK_RXCTL_FIRSTFRAG | SK_RXCTL_LASTFRAG) || 2741 SK_RXBYTES(sk_ctl) < SK_MIN_FRAMELEN || 2742 SK_RXBYTES(sk_ctl) > SK_JUMBO_FRAMELEN || 2743 sk_rxvalid(sc, rxstat, SK_RXBYTES(sk_ctl)) == 0) { 2744 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2745 sk_discard_jumbo_rxbuf(sc_if, cons); 2746 continue; 2747 } 2748 2749 m = jrxd->rx_m; 2750 csum = le32toh(cur_rx->sk_csum); 2751 if (sk_jumbo_newbuf(sc_if, cons) != 0) { 2752 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2753 /* reuse old buffer */ 2754 sk_discard_jumbo_rxbuf(sc_if, cons); 2755 continue; 2756 } 2757 m->m_pkthdr.rcvif = ifp; 2758 m->m_pkthdr.len = m->m_len = SK_RXBYTES(sk_ctl); 2759 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 2760 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) 2761 sk_rxcksum(ifp, m, csum); 2762 SK_IF_UNLOCK(sc_if); 2763 if_input(ifp, m); 2764 SK_IF_LOCK(sc_if); 2765 } 2766 2767 if (prog > 0) { 2768 sc_if->sk_cdata.sk_jumbo_rx_cons = cons; 2769 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 2770 sc_if->sk_cdata.sk_jumbo_rx_ring_map, 2771 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2772 } 2773 } 2774 2775 static void 2776 sk_txeof(struct sk_if_softc *sc_if) 2777 { 2778 struct sk_txdesc *txd; 2779 struct sk_tx_desc *cur_tx; 2780 if_t ifp; 2781 u_int32_t idx, sk_ctl; 2782 2783 ifp = sc_if->sk_ifp; 2784 2785 txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txbusyq); 2786 if (txd == NULL) 2787 return; 2788 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag, 2789 sc_if->sk_cdata.sk_tx_ring_map, BUS_DMASYNC_POSTREAD); 2790 /* 2791 * Go through our tx ring and free mbufs for those 2792 * frames that have been sent. 2793 */ 2794 for (idx = sc_if->sk_cdata.sk_tx_cons;; SK_INC(idx, SK_TX_RING_CNT)) { 2795 if (sc_if->sk_cdata.sk_tx_cnt <= 0) 2796 break; 2797 cur_tx = &sc_if->sk_rdata.sk_tx_ring[idx]; 2798 sk_ctl = le32toh(cur_tx->sk_ctl); 2799 if (sk_ctl & SK_TXCTL_OWN) 2800 break; 2801 sc_if->sk_cdata.sk_tx_cnt--; 2802 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 2803 if ((sk_ctl & SK_TXCTL_LASTFRAG) == 0) 2804 continue; 2805 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap, 2806 BUS_DMASYNC_POSTWRITE); 2807 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap); 2808 2809 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 2810 m_freem(txd->tx_m); 2811 txd->tx_m = NULL; 2812 STAILQ_REMOVE_HEAD(&sc_if->sk_cdata.sk_txbusyq, tx_q); 2813 STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txfreeq, txd, tx_q); 2814 txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txbusyq); 2815 } 2816 sc_if->sk_cdata.sk_tx_cons = idx; 2817 sc_if->sk_watchdog_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0; 2818 2819 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag, 2820 sc_if->sk_cdata.sk_tx_ring_map, 2821 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2822 } 2823 2824 static void 2825 sk_tick(void *xsc_if) 2826 { 2827 struct sk_if_softc *sc_if; 2828 struct mii_data *mii; 2829 if_t ifp; 2830 int i; 2831 2832 sc_if = xsc_if; 2833 ifp = sc_if->sk_ifp; 2834 mii = device_get_softc(sc_if->sk_miibus); 2835 2836 if (!(if_getflags(ifp) & IFF_UP)) 2837 return; 2838 2839 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2840 sk_intr_bcom(sc_if); 2841 return; 2842 } 2843 2844 /* 2845 * According to SysKonnect, the correct way to verify that 2846 * the link has come back up is to poll bit 0 of the GPIO 2847 * register three times. This pin has the signal from the 2848 * link_sync pin connected to it; if we read the same link 2849 * state 3 times in a row, we know the link is up. 2850 */ 2851 for (i = 0; i < 3; i++) { 2852 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 2853 break; 2854 } 2855 2856 if (i != 3) { 2857 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2858 return; 2859 } 2860 2861 /* Turn the GP0 interrupt back on. */ 2862 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2863 SK_XM_READ_2(sc_if, XM_ISR); 2864 mii_tick(mii); 2865 callout_stop(&sc_if->sk_tick_ch); 2866 } 2867 2868 static void 2869 sk_yukon_tick(void *xsc_if) 2870 { 2871 struct sk_if_softc *sc_if; 2872 struct mii_data *mii; 2873 2874 sc_if = xsc_if; 2875 mii = device_get_softc(sc_if->sk_miibus); 2876 2877 mii_tick(mii); 2878 callout_reset(&sc_if->sk_tick_ch, hz, sk_yukon_tick, sc_if); 2879 } 2880 2881 static void 2882 sk_intr_bcom(struct sk_if_softc *sc_if) 2883 { 2884 struct mii_data *mii; 2885 if_t ifp; 2886 int status; 2887 mii = device_get_softc(sc_if->sk_miibus); 2888 ifp = sc_if->sk_ifp; 2889 2890 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2891 2892 /* 2893 * Read the PHY interrupt register to make sure 2894 * we clear any pending interrupts. 2895 */ 2896 status = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 2897 2898 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) { 2899 sk_init_xmac(sc_if); 2900 return; 2901 } 2902 2903 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 2904 int lstat; 2905 lstat = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 2906 BRGPHY_MII_AUXSTS); 2907 2908 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 2909 mii_mediachg(mii); 2910 /* Turn off the link LED. */ 2911 SK_IF_WRITE_1(sc_if, 0, 2912 SK_LINKLED1_CTL, SK_LINKLED_OFF); 2913 sc_if->sk_link = 0; 2914 } else if (status & BRGPHY_ISR_LNK_CHG) { 2915 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 2916 BRGPHY_MII_IMR, 0xFF00); 2917 mii_tick(mii); 2918 sc_if->sk_link = 1; 2919 /* Turn on the link LED. */ 2920 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2921 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 2922 SK_LINKLED_BLINK_OFF); 2923 } else { 2924 mii_tick(mii); 2925 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2926 } 2927 } 2928 2929 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2930 2931 return; 2932 } 2933 2934 static void 2935 sk_intr_xmac(struct sk_if_softc *sc_if) 2936 { 2937 u_int16_t status; 2938 2939 status = SK_XM_READ_2(sc_if, XM_ISR); 2940 2941 /* 2942 * Link has gone down. Start MII tick timeout to 2943 * watch for link resync. 2944 */ 2945 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 2946 if (status & XM_ISR_GP0_SET) { 2947 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2948 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2949 } 2950 2951 if (status & XM_ISR_AUTONEG_DONE) { 2952 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2953 } 2954 } 2955 2956 if (status & XM_IMR_TX_UNDERRUN) 2957 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 2958 2959 if (status & XM_IMR_RX_OVERRUN) 2960 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 2961 2962 status = SK_XM_READ_2(sc_if, XM_ISR); 2963 2964 return; 2965 } 2966 2967 static void 2968 sk_intr_yukon(struct sk_if_softc *sc_if) 2969 { 2970 u_int8_t status; 2971 2972 status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR); 2973 /* RX overrun */ 2974 if ((status & SK_GMAC_INT_RX_OVER) != 0) { 2975 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 2976 SK_RFCTL_RX_FIFO_OVER); 2977 } 2978 /* TX underrun */ 2979 if ((status & SK_GMAC_INT_TX_UNDER) != 0) { 2980 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 2981 SK_TFCTL_TX_FIFO_UNDER); 2982 } 2983 } 2984 2985 static void 2986 sk_intr(void *xsc) 2987 { 2988 struct sk_softc *sc = xsc; 2989 struct sk_if_softc *sc_if0, *sc_if1; 2990 if_t ifp0 = NULL, ifp1 = NULL; 2991 u_int32_t status; 2992 2993 SK_LOCK(sc); 2994 2995 status = CSR_READ_4(sc, SK_ISSR); 2996 if (status == 0 || status == 0xffffffff || sc->sk_suspended) 2997 goto done_locked; 2998 2999 sc_if0 = sc->sk_if[SK_PORT_A]; 3000 sc_if1 = sc->sk_if[SK_PORT_B]; 3001 3002 if (sc_if0 != NULL) 3003 ifp0 = sc_if0->sk_ifp; 3004 if (sc_if1 != NULL) 3005 ifp1 = sc_if1->sk_ifp; 3006 3007 for (; (status &= sc->sk_intrmask) != 0;) { 3008 /* Handle receive interrupts first. */ 3009 if (status & SK_ISR_RX1_EOF) { 3010 if (if_getmtu(ifp0) > SK_MAX_FRAMELEN) 3011 sk_jumbo_rxeof(sc_if0); 3012 else 3013 sk_rxeof(sc_if0); 3014 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 3015 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 3016 } 3017 if (status & SK_ISR_RX2_EOF) { 3018 if (if_getflags(ifp1) > SK_MAX_FRAMELEN) 3019 sk_jumbo_rxeof(sc_if1); 3020 else 3021 sk_rxeof(sc_if1); 3022 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 3023 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 3024 } 3025 3026 /* Then transmit interrupts. */ 3027 if (status & SK_ISR_TX1_S_EOF) { 3028 sk_txeof(sc_if0); 3029 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, SK_TXBMU_CLR_IRQ_EOF); 3030 } 3031 if (status & SK_ISR_TX2_S_EOF) { 3032 sk_txeof(sc_if1); 3033 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, SK_TXBMU_CLR_IRQ_EOF); 3034 } 3035 3036 /* Then MAC interrupts. */ 3037 if (status & SK_ISR_MAC1 && 3038 if_getdrvflags(ifp0) & IFF_DRV_RUNNING) { 3039 if (sc->sk_type == SK_GENESIS) 3040 sk_intr_xmac(sc_if0); 3041 else 3042 sk_intr_yukon(sc_if0); 3043 } 3044 3045 if (status & SK_ISR_MAC2 && 3046 if_getdrvflags(ifp1) & IFF_DRV_RUNNING) { 3047 if (sc->sk_type == SK_GENESIS) 3048 sk_intr_xmac(sc_if1); 3049 else 3050 sk_intr_yukon(sc_if1); 3051 } 3052 3053 if (status & SK_ISR_EXTERNAL_REG) { 3054 if (ifp0 != NULL && 3055 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 3056 sk_intr_bcom(sc_if0); 3057 if (ifp1 != NULL && 3058 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 3059 sk_intr_bcom(sc_if1); 3060 } 3061 status = CSR_READ_4(sc, SK_ISSR); 3062 } 3063 3064 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 3065 3066 if (ifp0 != NULL && !if_sendq_empty(ifp0)) 3067 sk_start_locked(ifp0); 3068 if (ifp1 != NULL && !if_sendq_empty(ifp1)) 3069 sk_start_locked(ifp1); 3070 3071 done_locked: 3072 SK_UNLOCK(sc); 3073 } 3074 3075 static void 3076 sk_init_xmac(struct sk_if_softc *sc_if) 3077 { 3078 struct sk_softc *sc; 3079 if_t ifp; 3080 u_int16_t eaddr[(ETHER_ADDR_LEN+1)/2]; 3081 static const struct sk_bcom_hack bhack[] = { 3082 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 3083 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 3084 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 3085 { 0, 0 } }; 3086 3087 SK_IF_LOCK_ASSERT(sc_if); 3088 3089 sc = sc_if->sk_softc; 3090 ifp = sc_if->sk_ifp; 3091 3092 /* Unreset the XMAC. */ 3093 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 3094 DELAY(1000); 3095 3096 /* Reset the XMAC's internal state. */ 3097 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 3098 3099 /* Save the XMAC II revision */ 3100 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 3101 3102 /* 3103 * Perform additional initialization for external PHYs, 3104 * namely for the 1000baseTX cards that use the XMAC's 3105 * GMII mode. 3106 */ 3107 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 3108 int i = 0; 3109 u_int32_t val; 3110 3111 /* Take PHY out of reset. */ 3112 val = sk_win_read_4(sc, SK_GPIO); 3113 if (sc_if->sk_port == SK_PORT_A) 3114 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 3115 else 3116 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 3117 sk_win_write_4(sc, SK_GPIO, val); 3118 3119 /* Enable GMII mode on the XMAC. */ 3120 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 3121 3122 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 3123 BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET); 3124 DELAY(10000); 3125 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 3126 BRGPHY_MII_IMR, 0xFFF0); 3127 3128 /* 3129 * Early versions of the BCM5400 apparently have 3130 * a bug that requires them to have their reserved 3131 * registers initialized to some magic values. I don't 3132 * know what the numbers do, I'm just the messenger. 3133 */ 3134 if (sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 0x03) 3135 == 0x6041) { 3136 while(bhack[i].reg) { 3137 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 3138 bhack[i].reg, bhack[i].val); 3139 i++; 3140 } 3141 } 3142 } 3143 3144 /* Set station address */ 3145 bcopy(if_getlladdr(sc_if->sk_ifp), eaddr, ETHER_ADDR_LEN); 3146 SK_XM_WRITE_2(sc_if, XM_PAR0, eaddr[0]); 3147 SK_XM_WRITE_2(sc_if, XM_PAR1, eaddr[1]); 3148 SK_XM_WRITE_2(sc_if, XM_PAR2, eaddr[2]); 3149 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 3150 3151 if (if_getflags(ifp) & IFF_BROADCAST) { 3152 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 3153 } else { 3154 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 3155 } 3156 3157 /* We don't need the FCS appended to the packet. */ 3158 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 3159 3160 /* We want short frames padded to 60 bytes. */ 3161 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 3162 3163 /* 3164 * Enable the reception of all error frames. This is is 3165 * a necessary evil due to the design of the XMAC. The 3166 * XMAC's receive FIFO is only 8K in size, however jumbo 3167 * frames can be up to 9000 bytes in length. When bad 3168 * frame filtering is enabled, the XMAC's RX FIFO operates 3169 * in 'store and forward' mode. For this to work, the 3170 * entire frame has to fit into the FIFO, but that means 3171 * that jumbo frames larger than 8192 bytes will be 3172 * truncated. Disabling all bad frame filtering causes 3173 * the RX FIFO to operate in streaming mode, in which 3174 * case the XMAC will start transferring frames out of the 3175 * RX FIFO as soon as the FIFO threshold is reached. 3176 */ 3177 if (if_getmtu(ifp) > SK_MAX_FRAMELEN) { 3178 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 3179 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 3180 XM_MODE_RX_INRANGELEN); 3181 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 3182 } else 3183 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 3184 3185 /* 3186 * Bump up the transmit threshold. This helps hold off transmit 3187 * underruns when we're blasting traffic from both ports at once. 3188 */ 3189 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 3190 3191 /* Set Rx filter */ 3192 sk_rxfilter_genesis(sc_if); 3193 3194 /* Clear and enable interrupts */ 3195 SK_XM_READ_2(sc_if, XM_ISR); 3196 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 3197 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 3198 else 3199 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 3200 3201 /* Configure MAC arbiter */ 3202 switch(sc_if->sk_xmac_rev) { 3203 case XM_XMAC_REV_B2: 3204 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 3205 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 3206 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 3207 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 3208 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 3209 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 3210 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 3211 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 3212 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 3213 break; 3214 case XM_XMAC_REV_C1: 3215 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 3216 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 3217 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 3218 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 3219 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 3220 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 3221 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 3222 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 3223 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 3224 break; 3225 default: 3226 break; 3227 } 3228 sk_win_write_2(sc, SK_MACARB_CTL, 3229 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 3230 3231 sc_if->sk_link = 1; 3232 3233 return; 3234 } 3235 3236 static void 3237 sk_init_yukon(struct sk_if_softc *sc_if) 3238 { 3239 u_int32_t phy, v; 3240 u_int16_t reg; 3241 struct sk_softc *sc; 3242 if_t ifp; 3243 u_int8_t *eaddr; 3244 int i; 3245 3246 SK_IF_LOCK_ASSERT(sc_if); 3247 3248 sc = sc_if->sk_softc; 3249 ifp = sc_if->sk_ifp; 3250 3251 if (sc->sk_type == SK_YUKON_LITE && 3252 sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 3253 /* 3254 * Workaround code for COMA mode, set PHY reset. 3255 * Otherwise it will not correctly take chip out of 3256 * powerdown (coma) 3257 */ 3258 v = sk_win_read_4(sc, SK_GPIO); 3259 v |= SK_GPIO_DIR9 | SK_GPIO_DAT9; 3260 sk_win_write_4(sc, SK_GPIO, v); 3261 } 3262 3263 /* GMAC and GPHY Reset */ 3264 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 3265 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 3266 DELAY(1000); 3267 3268 if (sc->sk_type == SK_YUKON_LITE && 3269 sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 3270 /* 3271 * Workaround code for COMA mode, clear PHY reset 3272 */ 3273 v = sk_win_read_4(sc, SK_GPIO); 3274 v |= SK_GPIO_DIR9; 3275 v &= ~SK_GPIO_DAT9; 3276 sk_win_write_4(sc, SK_GPIO, v); 3277 } 3278 3279 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 3280 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 3281 3282 if (sc->sk_coppertype) 3283 phy |= SK_GPHY_COPPER; 3284 else 3285 phy |= SK_GPHY_FIBER; 3286 3287 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 3288 DELAY(1000); 3289 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 3290 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 3291 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 3292 3293 /* unused read of the interrupt source register */ 3294 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 3295 3296 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 3297 3298 /* MIB Counter Clear Mode set */ 3299 reg |= YU_PAR_MIB_CLR; 3300 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 3301 3302 /* MIB Counter Clear Mode clear */ 3303 reg &= ~YU_PAR_MIB_CLR; 3304 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 3305 3306 /* receive control reg */ 3307 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR); 3308 3309 /* transmit parameter register */ 3310 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 3311 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 3312 3313 /* serial mode register */ 3314 reg = YU_SMR_DATA_BLIND(0x1c) | YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e); 3315 if (if_getmtu(ifp) > SK_MAX_FRAMELEN) 3316 reg |= YU_SMR_MFL_JUMBO; 3317 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg); 3318 3319 /* Setup Yukon's station address */ 3320 eaddr = if_getlladdr(sc_if->sk_ifp); 3321 for (i = 0; i < 3; i++) 3322 SK_YU_WRITE_2(sc_if, SK_MAC0_0 + i * 4, 3323 eaddr[i * 2] | eaddr[i * 2 + 1] << 8); 3324 /* Set GMAC source address of flow control. */ 3325 for (i = 0; i < 3; i++) 3326 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 3327 eaddr[i * 2] | eaddr[i * 2 + 1] << 8); 3328 /* Set GMAC virtual address. */ 3329 for (i = 0; i < 3; i++) 3330 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, 3331 eaddr[i * 2] | eaddr[i * 2 + 1] << 8); 3332 3333 /* Set Rx filter */ 3334 sk_rxfilter_yukon(sc_if); 3335 3336 /* enable interrupt mask for counter overflows */ 3337 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 3338 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 3339 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 3340 3341 /* Configure RX MAC FIFO Flush Mask */ 3342 v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR | 3343 YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT | 3344 YU_RXSTAT_JABBER; 3345 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v); 3346 3347 /* Disable RX MAC FIFO Flush for YUKON-Lite Rev. A0 only */ 3348 if (sc->sk_type == SK_YUKON_LITE && sc->sk_rev == SK_YUKON_LITE_REV_A0) 3349 v = SK_TFCTL_OPERATION_ON; 3350 else 3351 v = SK_TFCTL_OPERATION_ON | SK_RFCTL_FIFO_FLUSH_ON; 3352 /* Configure RX MAC FIFO */ 3353 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 3354 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, v); 3355 3356 /* Increase flush threshould to 64 bytes */ 3357 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD, 3358 SK_RFCTL_FIFO_THRESHOLD + 1); 3359 3360 /* Configure TX MAC FIFO */ 3361 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 3362 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 3363 } 3364 3365 /* 3366 * Note that to properly initialize any part of the GEnesis chip, 3367 * you first have to take it out of reset mode. 3368 */ 3369 static void 3370 sk_init(void *xsc) 3371 { 3372 struct sk_if_softc *sc_if = xsc; 3373 3374 SK_IF_LOCK(sc_if); 3375 sk_init_locked(sc_if); 3376 SK_IF_UNLOCK(sc_if); 3377 3378 return; 3379 } 3380 3381 static void 3382 sk_init_locked(struct sk_if_softc *sc_if) 3383 { 3384 struct sk_softc *sc; 3385 if_t ifp; 3386 struct mii_data *mii; 3387 u_int16_t reg; 3388 u_int32_t imr; 3389 int error; 3390 3391 SK_IF_LOCK_ASSERT(sc_if); 3392 3393 ifp = sc_if->sk_ifp; 3394 sc = sc_if->sk_softc; 3395 mii = device_get_softc(sc_if->sk_miibus); 3396 3397 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 3398 return; 3399 3400 /* Cancel pending I/O and free all RX/TX buffers. */ 3401 sk_stop(sc_if); 3402 3403 if (sc->sk_type == SK_GENESIS) { 3404 /* Configure LINK_SYNC LED */ 3405 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 3406 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 3407 SK_LINKLED_LINKSYNC_ON); 3408 3409 /* Configure RX LED */ 3410 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 3411 SK_RXLEDCTL_COUNTER_START); 3412 3413 /* Configure TX LED */ 3414 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 3415 SK_TXLEDCTL_COUNTER_START); 3416 } 3417 3418 /* 3419 * Configure descriptor poll timer 3420 * 3421 * SK-NET GENESIS data sheet says that possibility of losing Start 3422 * transmit command due to CPU/cache related interim storage problems 3423 * under certain conditions. The document recommends a polling 3424 * mechanism to send a Start transmit command to initiate transfer 3425 * of ready descriptors regulary. To cope with this issue sk(4) now 3426 * enables descriptor poll timer to initiate descriptor processing 3427 * periodically as defined by SK_DPT_TIMER_MAX. However sk(4) still 3428 * issue SK_TXBMU_TX_START to Tx BMU to get fast execution of Tx 3429 * command instead of waiting for next descriptor polling time. 3430 * The same rule may apply to Rx side too but it seems that is not 3431 * needed at the moment. 3432 * Since sk(4) uses descriptor polling as a last resort there is no 3433 * need to set smaller polling time than maximum allowable one. 3434 */ 3435 SK_IF_WRITE_4(sc_if, 0, SK_DPT_INIT, SK_DPT_TIMER_MAX); 3436 3437 /* Configure I2C registers */ 3438 3439 /* Configure XMAC(s) */ 3440 switch (sc->sk_type) { 3441 case SK_GENESIS: 3442 sk_init_xmac(sc_if); 3443 break; 3444 case SK_YUKON: 3445 case SK_YUKON_LITE: 3446 case SK_YUKON_LP: 3447 sk_init_yukon(sc_if); 3448 break; 3449 } 3450 mii_mediachg(mii); 3451 3452 if (sc->sk_type == SK_GENESIS) { 3453 /* Configure MAC FIFOs */ 3454 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 3455 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 3456 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 3457 3458 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 3459 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 3460 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 3461 } 3462 3463 /* Configure transmit arbiter(s) */ 3464 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 3465 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 3466 3467 /* Configure RAMbuffers */ 3468 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 3469 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 3470 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 3471 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 3472 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 3473 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 3474 3475 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 3476 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 3477 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 3478 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 3479 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 3480 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 3481 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 3482 3483 /* Configure BMUs */ 3484 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 3485 if (if_getmtu(ifp) > SK_MAX_FRAMELEN) { 3486 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 3487 SK_ADDR_LO(SK_JUMBO_RX_RING_ADDR(sc_if, 0))); 3488 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 3489 SK_ADDR_HI(SK_JUMBO_RX_RING_ADDR(sc_if, 0))); 3490 } else { 3491 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 3492 SK_ADDR_LO(SK_RX_RING_ADDR(sc_if, 0))); 3493 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 3494 SK_ADDR_HI(SK_RX_RING_ADDR(sc_if, 0))); 3495 } 3496 3497 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 3498 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 3499 SK_ADDR_LO(SK_TX_RING_ADDR(sc_if, 0))); 3500 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 3501 SK_ADDR_HI(SK_TX_RING_ADDR(sc_if, 0))); 3502 3503 /* Init descriptors */ 3504 if (if_getmtu(ifp) > SK_MAX_FRAMELEN) 3505 error = sk_init_jumbo_rx_ring(sc_if); 3506 else 3507 error = sk_init_rx_ring(sc_if); 3508 if (error != 0) { 3509 device_printf(sc_if->sk_if_dev, 3510 "initialization failed: no memory for rx buffers\n"); 3511 sk_stop(sc_if); 3512 return; 3513 } 3514 sk_init_tx_ring(sc_if); 3515 3516 /* Set interrupt moderation if changed via sysctl. */ 3517 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 3518 if (imr != SK_IM_USECS(sc->sk_int_mod, sc->sk_int_ticks)) { 3519 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod, 3520 sc->sk_int_ticks)); 3521 if (bootverbose) 3522 device_printf(sc_if->sk_if_dev, 3523 "interrupt moderation is %d us.\n", 3524 sc->sk_int_mod); 3525 } 3526 3527 /* Configure interrupt handling */ 3528 CSR_READ_4(sc, SK_ISSR); 3529 if (sc_if->sk_port == SK_PORT_A) 3530 sc->sk_intrmask |= SK_INTRS1; 3531 else 3532 sc->sk_intrmask |= SK_INTRS2; 3533 3534 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 3535 3536 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 3537 3538 /* Start BMUs. */ 3539 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 3540 3541 switch(sc->sk_type) { 3542 case SK_GENESIS: 3543 /* Enable XMACs TX and RX state machines */ 3544 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 3545 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 3546 break; 3547 case SK_YUKON: 3548 case SK_YUKON_LITE: 3549 case SK_YUKON_LP: 3550 reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 3551 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 3552 #if 0 3553 /* XXX disable 100Mbps and full duplex mode? */ 3554 reg &= ~(YU_GPCR_SPEED | YU_GPCR_DPLX_DIS); 3555 #endif 3556 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 3557 } 3558 3559 /* Activate descriptor polling timer */ 3560 SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_START); 3561 /* start transfer of Tx descriptors */ 3562 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 3563 3564 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 3565 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 3566 3567 switch (sc->sk_type) { 3568 case SK_YUKON: 3569 case SK_YUKON_LITE: 3570 case SK_YUKON_LP: 3571 callout_reset(&sc_if->sk_tick_ch, hz, sk_yukon_tick, sc_if); 3572 break; 3573 } 3574 3575 callout_reset(&sc_if->sk_watchdog_ch, hz, sk_watchdog, ifp); 3576 3577 return; 3578 } 3579 3580 static void 3581 sk_stop(struct sk_if_softc *sc_if) 3582 { 3583 int i; 3584 struct sk_softc *sc; 3585 struct sk_txdesc *txd; 3586 struct sk_rxdesc *rxd; 3587 struct sk_rxdesc *jrxd; 3588 if_t ifp; 3589 u_int32_t val; 3590 3591 SK_IF_LOCK_ASSERT(sc_if); 3592 sc = sc_if->sk_softc; 3593 ifp = sc_if->sk_ifp; 3594 3595 callout_stop(&sc_if->sk_tick_ch); 3596 callout_stop(&sc_if->sk_watchdog_ch); 3597 3598 /* stop Tx descriptor polling timer */ 3599 SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP); 3600 /* stop transfer of Tx descriptors */ 3601 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_STOP); 3602 for (i = 0; i < SK_TIMEOUT; i++) { 3603 val = CSR_READ_4(sc, sc_if->sk_tx_bmu); 3604 if ((val & SK_TXBMU_TX_STOP) == 0) 3605 break; 3606 DELAY(1); 3607 } 3608 if (i == SK_TIMEOUT) 3609 device_printf(sc_if->sk_if_dev, 3610 "can not stop transfer of Tx descriptor\n"); 3611 /* stop transfer of Rx descriptors */ 3612 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_STOP); 3613 for (i = 0; i < SK_TIMEOUT; i++) { 3614 val = SK_IF_READ_4(sc_if, 0, SK_RXQ1_BMU_CSR); 3615 if ((val & SK_RXBMU_RX_STOP) == 0) 3616 break; 3617 DELAY(1); 3618 } 3619 if (i == SK_TIMEOUT) 3620 device_printf(sc_if->sk_if_dev, 3621 "can not stop transfer of Rx descriptor\n"); 3622 3623 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 3624 /* Put PHY back into reset. */ 3625 val = sk_win_read_4(sc, SK_GPIO); 3626 if (sc_if->sk_port == SK_PORT_A) { 3627 val |= SK_GPIO_DIR0; 3628 val &= ~SK_GPIO_DAT0; 3629 } else { 3630 val |= SK_GPIO_DIR2; 3631 val &= ~SK_GPIO_DAT2; 3632 } 3633 sk_win_write_4(sc, SK_GPIO, val); 3634 } 3635 3636 /* Turn off various components of this interface. */ 3637 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 3638 switch (sc->sk_type) { 3639 case SK_GENESIS: 3640 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_RESET); 3641 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 3642 break; 3643 case SK_YUKON: 3644 case SK_YUKON_LITE: 3645 case SK_YUKON_LP: 3646 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 3647 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 3648 break; 3649 } 3650 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 3651 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 3652 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 3653 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 3654 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 3655 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 3656 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 3657 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 3658 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 3659 3660 /* Disable interrupts */ 3661 if (sc_if->sk_port == SK_PORT_A) 3662 sc->sk_intrmask &= ~SK_INTRS1; 3663 else 3664 sc->sk_intrmask &= ~SK_INTRS2; 3665 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 3666 3667 SK_XM_READ_2(sc_if, XM_ISR); 3668 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 3669 3670 /* Free RX and TX mbufs still in the queues. */ 3671 for (i = 0; i < SK_RX_RING_CNT; i++) { 3672 rxd = &sc_if->sk_cdata.sk_rxdesc[i]; 3673 if (rxd->rx_m != NULL) { 3674 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag, 3675 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3676 bus_dmamap_unload(sc_if->sk_cdata.sk_rx_tag, 3677 rxd->rx_dmamap); 3678 m_freem(rxd->rx_m); 3679 rxd->rx_m = NULL; 3680 } 3681 } 3682 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) { 3683 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i]; 3684 if (jrxd->rx_m != NULL) { 3685 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag, 3686 jrxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3687 bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_tag, 3688 jrxd->rx_dmamap); 3689 m_freem(jrxd->rx_m); 3690 jrxd->rx_m = NULL; 3691 } 3692 } 3693 for (i = 0; i < SK_TX_RING_CNT; i++) { 3694 txd = &sc_if->sk_cdata.sk_txdesc[i]; 3695 if (txd->tx_m != NULL) { 3696 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag, 3697 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 3698 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag, 3699 txd->tx_dmamap); 3700 m_freem(txd->tx_m); 3701 txd->tx_m = NULL; 3702 } 3703 } 3704 3705 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING|IFF_DRV_OACTIVE)); 3706 3707 return; 3708 } 3709 3710 static int 3711 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3712 { 3713 int error, value; 3714 3715 if (!arg1) 3716 return (EINVAL); 3717 value = *(int *)arg1; 3718 error = sysctl_handle_int(oidp, &value, 0, req); 3719 if (error || !req->newptr) 3720 return (error); 3721 if (value < low || value > high) 3722 return (EINVAL); 3723 *(int *)arg1 = value; 3724 return (0); 3725 } 3726 3727 static int 3728 sysctl_hw_sk_int_mod(SYSCTL_HANDLER_ARGS) 3729 { 3730 return (sysctl_int_range(oidp, arg1, arg2, req, SK_IM_MIN, SK_IM_MAX)); 3731 } 3732