1 /* $OpenBSD: if_sk.c,v 2.33 2003/08/12 05:23:06 nate Exp $ */ 2 3 /*- 4 * SPDX-License-Identifier: BSD-4-Clause 5 * 6 * Copyright (c) 1997, 1998, 1999, 2000 7 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Bill Paul. 20 * 4. Neither the name of the author nor the names of any co-contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 34 * THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 /*- 37 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 38 * 39 * Permission to use, copy, modify, and distribute this software for any 40 * purpose with or without fee is hereby granted, provided that the above 41 * copyright notice and this permission notice appear in all copies. 42 * 43 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 44 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 45 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 46 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 47 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 48 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 49 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 50 */ 51 52 #include <sys/cdefs.h> 53 __FBSDID("$FreeBSD$"); 54 55 /* 56 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 57 * the SK-984x series adapters, both single port and dual port. 58 * References: 59 * The XaQti XMAC II datasheet, 60 * https://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 61 * The SysKonnect GEnesis manual, http://www.syskonnect.com 62 * 63 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the 64 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 65 * convenience to others until Vitesse corrects this problem: 66 * 67 * https://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 68 * 69 * Written by Bill Paul <wpaul@ee.columbia.edu> 70 * Department of Electrical Engineering 71 * Columbia University, New York City 72 */ 73 /* 74 * The SysKonnect gigabit ethernet adapters consist of two main 75 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 76 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 77 * components and a PHY while the GEnesis controller provides a PCI 78 * interface with DMA support. Each card may have between 512K and 79 * 2MB of SRAM on board depending on the configuration. 80 * 81 * The SysKonnect GEnesis controller can have either one or two XMAC 82 * chips connected to it, allowing single or dual port NIC configurations. 83 * SysKonnect has the distinction of being the only vendor on the market 84 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 85 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 86 * XMAC registers. This driver takes advantage of these features to allow 87 * both XMACs to operate as independent interfaces. 88 */ 89 90 #include <sys/param.h> 91 #include <sys/systm.h> 92 #include <sys/bus.h> 93 #include <sys/endian.h> 94 #include <sys/mbuf.h> 95 #include <sys/malloc.h> 96 #include <sys/kernel.h> 97 #include <sys/module.h> 98 #include <sys/socket.h> 99 #include <sys/sockio.h> 100 #include <sys/queue.h> 101 #include <sys/sysctl.h> 102 103 #include <net/bpf.h> 104 #include <net/ethernet.h> 105 #include <net/if.h> 106 #include <net/if_var.h> 107 #include <net/if_arp.h> 108 #include <net/if_dl.h> 109 #include <net/if_media.h> 110 #include <net/if_types.h> 111 #include <net/if_vlan_var.h> 112 113 #include <netinet/in.h> 114 #include <netinet/in_systm.h> 115 #include <netinet/ip.h> 116 117 #include <machine/bus.h> 118 #include <machine/in_cksum.h> 119 #include <machine/resource.h> 120 #include <sys/rman.h> 121 122 #include <dev/mii/mii.h> 123 #include <dev/mii/miivar.h> 124 #include <dev/mii/brgphyreg.h> 125 126 #include <dev/pci/pcireg.h> 127 #include <dev/pci/pcivar.h> 128 129 #if 0 130 #define SK_USEIOSPACE 131 #endif 132 133 #include <dev/sk/if_skreg.h> 134 #include <dev/sk/xmaciireg.h> 135 #include <dev/sk/yukonreg.h> 136 137 MODULE_DEPEND(sk, pci, 1, 1, 1); 138 MODULE_DEPEND(sk, ether, 1, 1, 1); 139 MODULE_DEPEND(sk, miibus, 1, 1, 1); 140 141 /* "device miibus" required. See GENERIC if you get errors here. */ 142 #include "miibus_if.h" 143 144 static const struct sk_type sk_devs[] = { 145 { 146 VENDORID_SK, 147 DEVICEID_SK_V1, 148 "SysKonnect Gigabit Ethernet (V1.0)" 149 }, 150 { 151 VENDORID_SK, 152 DEVICEID_SK_V2, 153 "SysKonnect Gigabit Ethernet (V2.0)" 154 }, 155 { 156 VENDORID_MARVELL, 157 DEVICEID_SK_V2, 158 "Marvell Gigabit Ethernet" 159 }, 160 { 161 VENDORID_MARVELL, 162 DEVICEID_BELKIN_5005, 163 "Belkin F5D5005 Gigabit Ethernet" 164 }, 165 { 166 VENDORID_3COM, 167 DEVICEID_3COM_3C940, 168 "3Com 3C940 Gigabit Ethernet" 169 }, 170 { 171 VENDORID_LINKSYS, 172 DEVICEID_LINKSYS_EG1032, 173 "Linksys EG1032 Gigabit Ethernet" 174 }, 175 { 176 VENDORID_DLINK, 177 DEVICEID_DLINK_DGE530T_A1, 178 "D-Link DGE-530T Gigabit Ethernet" 179 }, 180 { 181 VENDORID_DLINK, 182 DEVICEID_DLINK_DGE530T_B1, 183 "D-Link DGE-530T Gigabit Ethernet" 184 }, 185 { 0, 0, NULL } 186 }; 187 188 static int skc_probe(device_t); 189 static int skc_attach(device_t); 190 static int skc_detach(device_t); 191 static int skc_shutdown(device_t); 192 static int skc_suspend(device_t); 193 static int skc_resume(device_t); 194 static bus_dma_tag_t skc_get_dma_tag(device_t, device_t); 195 static int sk_detach(device_t); 196 static int sk_probe(device_t); 197 static int sk_attach(device_t); 198 static void sk_tick(void *); 199 static void sk_yukon_tick(void *); 200 static void sk_intr(void *); 201 static void sk_intr_xmac(struct sk_if_softc *); 202 static void sk_intr_bcom(struct sk_if_softc *); 203 static void sk_intr_yukon(struct sk_if_softc *); 204 static __inline void sk_rxcksum(if_t, struct mbuf *, u_int32_t); 205 static __inline int sk_rxvalid(struct sk_softc *, u_int32_t, u_int32_t); 206 static void sk_rxeof(struct sk_if_softc *); 207 static void sk_jumbo_rxeof(struct sk_if_softc *); 208 static void sk_txeof(struct sk_if_softc *); 209 static void sk_txcksum(if_t, struct mbuf *, struct sk_tx_desc *); 210 static int sk_encap(struct sk_if_softc *, struct mbuf **); 211 static void sk_start(if_t); 212 static void sk_start_locked(if_t); 213 static int sk_ioctl(if_t, u_long, caddr_t); 214 static void sk_init(void *); 215 static void sk_init_locked(struct sk_if_softc *); 216 static void sk_init_xmac(struct sk_if_softc *); 217 static void sk_init_yukon(struct sk_if_softc *); 218 static void sk_stop(struct sk_if_softc *); 219 static void sk_watchdog(void *); 220 static int sk_ifmedia_upd(if_t); 221 static void sk_ifmedia_sts(if_t, struct ifmediareq *); 222 static void sk_reset(struct sk_softc *); 223 static __inline void sk_discard_rxbuf(struct sk_if_softc *, int); 224 static __inline void sk_discard_jumbo_rxbuf(struct sk_if_softc *, int); 225 static int sk_newbuf(struct sk_if_softc *, int); 226 static int sk_jumbo_newbuf(struct sk_if_softc *, int); 227 static void sk_dmamap_cb(void *, bus_dma_segment_t *, int, int); 228 static int sk_dma_alloc(struct sk_if_softc *); 229 static int sk_dma_jumbo_alloc(struct sk_if_softc *); 230 static void sk_dma_free(struct sk_if_softc *); 231 static void sk_dma_jumbo_free(struct sk_if_softc *); 232 static int sk_init_rx_ring(struct sk_if_softc *); 233 static int sk_init_jumbo_rx_ring(struct sk_if_softc *); 234 static void sk_init_tx_ring(struct sk_if_softc *); 235 static u_int32_t sk_win_read_4(struct sk_softc *, int); 236 static u_int16_t sk_win_read_2(struct sk_softc *, int); 237 static u_int8_t sk_win_read_1(struct sk_softc *, int); 238 static void sk_win_write_4(struct sk_softc *, int, u_int32_t); 239 static void sk_win_write_2(struct sk_softc *, int, u_int32_t); 240 static void sk_win_write_1(struct sk_softc *, int, u_int32_t); 241 242 static int sk_miibus_readreg(device_t, int, int); 243 static int sk_miibus_writereg(device_t, int, int, int); 244 static void sk_miibus_statchg(device_t); 245 246 static int sk_xmac_miibus_readreg(struct sk_if_softc *, int, int); 247 static int sk_xmac_miibus_writereg(struct sk_if_softc *, int, int, 248 int); 249 static void sk_xmac_miibus_statchg(struct sk_if_softc *); 250 251 static int sk_marv_miibus_readreg(struct sk_if_softc *, int, int); 252 static int sk_marv_miibus_writereg(struct sk_if_softc *, int, int, 253 int); 254 static void sk_marv_miibus_statchg(struct sk_if_softc *); 255 256 static uint32_t sk_xmchash(const uint8_t *); 257 static void sk_setfilt(struct sk_if_softc *, u_int16_t *, int); 258 static void sk_rxfilter(struct sk_if_softc *); 259 static void sk_rxfilter_genesis(struct sk_if_softc *); 260 static void sk_rxfilter_yukon(struct sk_if_softc *); 261 262 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high); 263 static int sysctl_hw_sk_int_mod(SYSCTL_HANDLER_ARGS); 264 265 /* Tunables. */ 266 static int jumbo_disable = 0; 267 TUNABLE_INT("hw.skc.jumbo_disable", &jumbo_disable); 268 269 /* 270 * It seems that SK-NET GENESIS supports very simple checksum offload 271 * capability for Tx and I believe it can generate 0 checksum value for 272 * UDP packets in Tx as the hardware can't differenciate UDP packets from 273 * TCP packets. 0 chcecksum value for UDP packet is an invalid one as it 274 * means sender didn't perforam checksum computation. For the safety I 275 * disabled UDP checksum offload capability at the moment. 276 */ 277 #define SK_CSUM_FEATURES (CSUM_TCP) 278 279 /* 280 * Note that we have newbus methods for both the GEnesis controller 281 * itself and the XMAC(s). The XMACs are children of the GEnesis, and 282 * the miibus code is a child of the XMACs. We need to do it this way 283 * so that the miibus drivers can access the PHY registers on the 284 * right PHY. It's not quite what I had in mind, but it's the only 285 * design that achieves the desired effect. 286 */ 287 static device_method_t skc_methods[] = { 288 /* Device interface */ 289 DEVMETHOD(device_probe, skc_probe), 290 DEVMETHOD(device_attach, skc_attach), 291 DEVMETHOD(device_detach, skc_detach), 292 DEVMETHOD(device_suspend, skc_suspend), 293 DEVMETHOD(device_resume, skc_resume), 294 DEVMETHOD(device_shutdown, skc_shutdown), 295 296 DEVMETHOD(bus_get_dma_tag, skc_get_dma_tag), 297 298 DEVMETHOD_END 299 }; 300 301 static driver_t skc_driver = { 302 "skc", 303 skc_methods, 304 sizeof(struct sk_softc) 305 }; 306 307 static device_method_t sk_methods[] = { 308 /* Device interface */ 309 DEVMETHOD(device_probe, sk_probe), 310 DEVMETHOD(device_attach, sk_attach), 311 DEVMETHOD(device_detach, sk_detach), 312 DEVMETHOD(device_shutdown, bus_generic_shutdown), 313 314 /* MII interface */ 315 DEVMETHOD(miibus_readreg, sk_miibus_readreg), 316 DEVMETHOD(miibus_writereg, sk_miibus_writereg), 317 DEVMETHOD(miibus_statchg, sk_miibus_statchg), 318 319 DEVMETHOD_END 320 }; 321 322 static driver_t sk_driver = { 323 "sk", 324 sk_methods, 325 sizeof(struct sk_if_softc) 326 }; 327 328 DRIVER_MODULE(skc, pci, skc_driver, NULL, NULL); 329 DRIVER_MODULE(sk, skc, sk_driver, NULL, NULL); 330 DRIVER_MODULE(miibus, sk, miibus_driver, NULL, NULL); 331 332 static struct resource_spec sk_res_spec_io[] = { 333 { SYS_RES_IOPORT, PCIR_BAR(1), RF_ACTIVE }, 334 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 335 { -1, 0, 0 } 336 }; 337 338 static struct resource_spec sk_res_spec_mem[] = { 339 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 340 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 341 { -1, 0, 0 } 342 }; 343 344 #define SK_SETBIT(sc, reg, x) \ 345 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 346 347 #define SK_CLRBIT(sc, reg, x) \ 348 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 349 350 #define SK_WIN_SETBIT_4(sc, reg, x) \ 351 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x) 352 353 #define SK_WIN_CLRBIT_4(sc, reg, x) \ 354 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x) 355 356 #define SK_WIN_SETBIT_2(sc, reg, x) \ 357 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x) 358 359 #define SK_WIN_CLRBIT_2(sc, reg, x) \ 360 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x) 361 362 static u_int32_t 363 sk_win_read_4(struct sk_softc *sc, int reg) 364 { 365 #ifdef SK_USEIOSPACE 366 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 367 return(CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg))); 368 #else 369 return(CSR_READ_4(sc, reg)); 370 #endif 371 } 372 373 static u_int16_t 374 sk_win_read_2(struct sk_softc *sc, int reg) 375 { 376 #ifdef SK_USEIOSPACE 377 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 378 return(CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg))); 379 #else 380 return(CSR_READ_2(sc, reg)); 381 #endif 382 } 383 384 static u_int8_t 385 sk_win_read_1(struct sk_softc *sc, int reg) 386 { 387 #ifdef SK_USEIOSPACE 388 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 389 return(CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg))); 390 #else 391 return(CSR_READ_1(sc, reg)); 392 #endif 393 } 394 395 static void 396 sk_win_write_4(struct sk_softc *sc, int reg, u_int32_t val) 397 { 398 #ifdef SK_USEIOSPACE 399 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 400 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), val); 401 #else 402 CSR_WRITE_4(sc, reg, val); 403 #endif 404 return; 405 } 406 407 static void 408 sk_win_write_2(struct sk_softc *sc, int reg, u_int32_t val) 409 { 410 #ifdef SK_USEIOSPACE 411 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 412 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), val); 413 #else 414 CSR_WRITE_2(sc, reg, val); 415 #endif 416 return; 417 } 418 419 static void 420 sk_win_write_1(struct sk_softc *sc, int reg, u_int32_t val) 421 { 422 #ifdef SK_USEIOSPACE 423 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 424 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), val); 425 #else 426 CSR_WRITE_1(sc, reg, val); 427 #endif 428 return; 429 } 430 431 static int 432 sk_miibus_readreg(device_t dev, int phy, int reg) 433 { 434 struct sk_if_softc *sc_if; 435 int v; 436 437 sc_if = device_get_softc(dev); 438 439 SK_IF_MII_LOCK(sc_if); 440 switch(sc_if->sk_softc->sk_type) { 441 case SK_GENESIS: 442 v = sk_xmac_miibus_readreg(sc_if, phy, reg); 443 break; 444 case SK_YUKON: 445 case SK_YUKON_LITE: 446 case SK_YUKON_LP: 447 v = sk_marv_miibus_readreg(sc_if, phy, reg); 448 break; 449 default: 450 v = 0; 451 break; 452 } 453 SK_IF_MII_UNLOCK(sc_if); 454 455 return (v); 456 } 457 458 static int 459 sk_miibus_writereg(device_t dev, int phy, int reg, int val) 460 { 461 struct sk_if_softc *sc_if; 462 int v; 463 464 sc_if = device_get_softc(dev); 465 466 SK_IF_MII_LOCK(sc_if); 467 switch(sc_if->sk_softc->sk_type) { 468 case SK_GENESIS: 469 v = sk_xmac_miibus_writereg(sc_if, phy, reg, val); 470 break; 471 case SK_YUKON: 472 case SK_YUKON_LITE: 473 case SK_YUKON_LP: 474 v = sk_marv_miibus_writereg(sc_if, phy, reg, val); 475 break; 476 default: 477 v = 0; 478 break; 479 } 480 SK_IF_MII_UNLOCK(sc_if); 481 482 return (v); 483 } 484 485 static void 486 sk_miibus_statchg(device_t dev) 487 { 488 struct sk_if_softc *sc_if; 489 490 sc_if = device_get_softc(dev); 491 492 SK_IF_MII_LOCK(sc_if); 493 switch(sc_if->sk_softc->sk_type) { 494 case SK_GENESIS: 495 sk_xmac_miibus_statchg(sc_if); 496 break; 497 case SK_YUKON: 498 case SK_YUKON_LITE: 499 case SK_YUKON_LP: 500 sk_marv_miibus_statchg(sc_if); 501 break; 502 } 503 SK_IF_MII_UNLOCK(sc_if); 504 505 return; 506 } 507 508 static int 509 sk_xmac_miibus_readreg(struct sk_if_softc *sc_if, int phy, int reg) 510 { 511 int i; 512 513 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 514 SK_XM_READ_2(sc_if, XM_PHY_DATA); 515 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 516 for (i = 0; i < SK_TIMEOUT; i++) { 517 DELAY(1); 518 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 519 XM_MMUCMD_PHYDATARDY) 520 break; 521 } 522 523 if (i == SK_TIMEOUT) { 524 if_printf(sc_if->sk_ifp, "phy failed to come ready\n"); 525 return(0); 526 } 527 } 528 DELAY(1); 529 i = SK_XM_READ_2(sc_if, XM_PHY_DATA); 530 531 return(i); 532 } 533 534 static int 535 sk_xmac_miibus_writereg(struct sk_if_softc *sc_if, int phy, int reg, int val) 536 { 537 int i; 538 539 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 540 for (i = 0; i < SK_TIMEOUT; i++) { 541 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 542 break; 543 } 544 545 if (i == SK_TIMEOUT) { 546 if_printf(sc_if->sk_ifp, "phy failed to come ready\n"); 547 return (ETIMEDOUT); 548 } 549 550 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 551 for (i = 0; i < SK_TIMEOUT; i++) { 552 DELAY(1); 553 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 554 break; 555 } 556 if (i == SK_TIMEOUT) 557 if_printf(sc_if->sk_ifp, "phy write timed out\n"); 558 559 return(0); 560 } 561 562 static void 563 sk_xmac_miibus_statchg(struct sk_if_softc *sc_if) 564 { 565 struct mii_data *mii; 566 567 mii = device_get_softc(sc_if->sk_miibus); 568 569 /* 570 * If this is a GMII PHY, manually set the XMAC's 571 * duplex mode accordingly. 572 */ 573 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 574 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 575 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 576 } else { 577 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 578 } 579 } 580 } 581 582 static int 583 sk_marv_miibus_readreg(struct sk_if_softc *sc_if, int phy, int reg) 584 { 585 u_int16_t val; 586 int i; 587 588 if (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 589 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER) { 590 return(0); 591 } 592 593 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 594 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 595 596 for (i = 0; i < SK_TIMEOUT; i++) { 597 DELAY(1); 598 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 599 if (val & YU_SMICR_READ_VALID) 600 break; 601 } 602 603 if (i == SK_TIMEOUT) { 604 if_printf(sc_if->sk_ifp, "phy failed to come ready\n"); 605 return(0); 606 } 607 608 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 609 610 return(val); 611 } 612 613 static int 614 sk_marv_miibus_writereg(struct sk_if_softc *sc_if, int phy, int reg, int val) 615 { 616 int i; 617 618 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 619 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 620 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 621 622 for (i = 0; i < SK_TIMEOUT; i++) { 623 DELAY(1); 624 if ((SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY) == 0) 625 break; 626 } 627 if (i == SK_TIMEOUT) 628 if_printf(sc_if->sk_ifp, "phy write timeout\n"); 629 630 return(0); 631 } 632 633 static void 634 sk_marv_miibus_statchg(struct sk_if_softc *sc_if) 635 { 636 return; 637 } 638 639 #define HASH_BITS 6 640 641 static u_int32_t 642 sk_xmchash(const uint8_t *addr) 643 { 644 uint32_t crc; 645 646 /* Compute CRC for the address value. */ 647 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 648 649 return (~crc & ((1 << HASH_BITS) - 1)); 650 } 651 652 static void 653 sk_setfilt(struct sk_if_softc *sc_if, u_int16_t *addr, int slot) 654 { 655 int base; 656 657 base = XM_RXFILT_ENTRY(slot); 658 659 SK_XM_WRITE_2(sc_if, base, addr[0]); 660 SK_XM_WRITE_2(sc_if, base + 2, addr[1]); 661 SK_XM_WRITE_2(sc_if, base + 4, addr[2]); 662 663 return; 664 } 665 666 static void 667 sk_rxfilter(struct sk_if_softc *sc_if) 668 { 669 struct sk_softc *sc; 670 671 SK_IF_LOCK_ASSERT(sc_if); 672 673 sc = sc_if->sk_softc; 674 if (sc->sk_type == SK_GENESIS) 675 sk_rxfilter_genesis(sc_if); 676 else 677 sk_rxfilter_yukon(sc_if); 678 } 679 680 struct sk_add_maddr_genesis_ctx { 681 struct sk_if_softc *sc_if; 682 uint32_t hashes[2]; 683 uint32_t mode; 684 }; 685 686 static u_int 687 sk_add_maddr_genesis(void *arg, struct sockaddr_dl *sdl, u_int cnt) 688 { 689 struct sk_add_maddr_genesis_ctx *ctx = arg; 690 int h; 691 692 /* 693 * Program the first XM_RXFILT_MAX multicast groups 694 * into the perfect filter. 695 */ 696 if (cnt + 1 < XM_RXFILT_MAX) { 697 sk_setfilt(ctx->sc_if, (uint16_t *)LLADDR(sdl), cnt + 1); 698 ctx->mode |= XM_MODE_RX_USE_PERFECT; 699 return (1); 700 } 701 h = sk_xmchash((const uint8_t *)LLADDR(sdl)); 702 if (h < 32) 703 ctx->hashes[0] |= (1 << h); 704 else 705 ctx->hashes[1] |= (1 << (h - 32)); 706 ctx->mode |= XM_MODE_RX_USE_HASH; 707 708 return (1); 709 } 710 711 static void 712 sk_rxfilter_genesis(struct sk_if_softc *sc_if) 713 { 714 if_t ifp = sc_if->sk_ifp; 715 struct sk_add_maddr_genesis_ctx ctx = { sc_if, { 0, 0 } }; 716 int i; 717 u_int16_t dummy[] = { 0, 0, 0 }; 718 719 SK_IF_LOCK_ASSERT(sc_if); 720 721 ctx.mode = SK_XM_READ_4(sc_if, XM_MODE); 722 ctx.mode &= ~(XM_MODE_RX_PROMISC | XM_MODE_RX_USE_HASH | 723 XM_MODE_RX_USE_PERFECT); 724 /* First, zot all the existing perfect filters. */ 725 for (i = 1; i < XM_RXFILT_MAX; i++) 726 sk_setfilt(sc_if, dummy, i); 727 728 /* Now program new ones. */ 729 if (if_getflags(ifp) & IFF_ALLMULTI || if_getflags(ifp) & IFF_PROMISC) { 730 if (if_getflags(ifp) & IFF_ALLMULTI) 731 ctx.mode |= XM_MODE_RX_USE_HASH; 732 if (if_getflags(ifp) & IFF_PROMISC) 733 ctx.mode |= XM_MODE_RX_PROMISC; 734 ctx.hashes[0] = 0xFFFFFFFF; 735 ctx.hashes[1] = 0xFFFFFFFF; 736 } else 737 /* XXX want to maintain reverse semantics */ 738 if_foreach_llmaddr(ifp, sk_add_maddr_genesis, &ctx); 739 740 SK_XM_WRITE_4(sc_if, XM_MODE, ctx.mode); 741 SK_XM_WRITE_4(sc_if, XM_MAR0, ctx.hashes[0]); 742 SK_XM_WRITE_4(sc_if, XM_MAR2, ctx.hashes[1]); 743 } 744 745 static u_int 746 sk_hash_maddr_yukon(void *arg, struct sockaddr_dl *sdl, u_int cnt) 747 { 748 uint32_t crc, *hashes = arg; 749 750 crc = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN); 751 /* Just want the 6 least significant bits. */ 752 crc &= 0x3f; 753 /* Set the corresponding bit in the hash table. */ 754 hashes[crc >> 5] |= 1 << (crc & 0x1f); 755 756 return (1); 757 } 758 759 static void 760 sk_rxfilter_yukon(struct sk_if_softc *sc_if) 761 { 762 if_t ifp; 763 uint32_t hashes[2] = { 0, 0 }, mode; 764 765 SK_IF_LOCK_ASSERT(sc_if); 766 767 ifp = sc_if->sk_ifp; 768 mode = SK_YU_READ_2(sc_if, YUKON_RCR); 769 if (if_getflags(ifp) & IFF_PROMISC) 770 mode &= ~(YU_RCR_UFLEN | YU_RCR_MUFLEN); 771 else if (if_getflags(ifp) & IFF_ALLMULTI) { 772 mode |= YU_RCR_UFLEN | YU_RCR_MUFLEN; 773 hashes[0] = 0xFFFFFFFF; 774 hashes[1] = 0xFFFFFFFF; 775 } else { 776 mode |= YU_RCR_UFLEN; 777 if_foreach_llmaddr(ifp, sk_hash_maddr_yukon, hashes); 778 if (hashes[0] != 0 || hashes[1] != 0) 779 mode |= YU_RCR_MUFLEN; 780 } 781 782 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 783 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 784 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 785 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 786 SK_YU_WRITE_2(sc_if, YUKON_RCR, mode); 787 } 788 789 static int 790 sk_init_rx_ring(struct sk_if_softc *sc_if) 791 { 792 struct sk_ring_data *rd; 793 bus_addr_t addr; 794 u_int32_t csum_start; 795 int i; 796 797 sc_if->sk_cdata.sk_rx_cons = 0; 798 799 csum_start = (ETHER_HDR_LEN + sizeof(struct ip)) << 16 | 800 ETHER_HDR_LEN; 801 rd = &sc_if->sk_rdata; 802 bzero(rd->sk_rx_ring, sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 803 for (i = 0; i < SK_RX_RING_CNT; i++) { 804 if (sk_newbuf(sc_if, i) != 0) 805 return (ENOBUFS); 806 if (i == (SK_RX_RING_CNT - 1)) 807 addr = SK_RX_RING_ADDR(sc_if, 0); 808 else 809 addr = SK_RX_RING_ADDR(sc_if, i + 1); 810 rd->sk_rx_ring[i].sk_next = htole32(SK_ADDR_LO(addr)); 811 rd->sk_rx_ring[i].sk_csum_start = htole32(csum_start); 812 } 813 814 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag, 815 sc_if->sk_cdata.sk_rx_ring_map, 816 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 817 818 return(0); 819 } 820 821 static int 822 sk_init_jumbo_rx_ring(struct sk_if_softc *sc_if) 823 { 824 struct sk_ring_data *rd; 825 bus_addr_t addr; 826 u_int32_t csum_start; 827 int i; 828 829 sc_if->sk_cdata.sk_jumbo_rx_cons = 0; 830 831 csum_start = ((ETHER_HDR_LEN + sizeof(struct ip)) << 16) | 832 ETHER_HDR_LEN; 833 rd = &sc_if->sk_rdata; 834 bzero(rd->sk_jumbo_rx_ring, 835 sizeof(struct sk_rx_desc) * SK_JUMBO_RX_RING_CNT); 836 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) { 837 if (sk_jumbo_newbuf(sc_if, i) != 0) 838 return (ENOBUFS); 839 if (i == (SK_JUMBO_RX_RING_CNT - 1)) 840 addr = SK_JUMBO_RX_RING_ADDR(sc_if, 0); 841 else 842 addr = SK_JUMBO_RX_RING_ADDR(sc_if, i + 1); 843 rd->sk_jumbo_rx_ring[i].sk_next = htole32(SK_ADDR_LO(addr)); 844 rd->sk_jumbo_rx_ring[i].sk_csum_start = htole32(csum_start); 845 } 846 847 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 848 sc_if->sk_cdata.sk_jumbo_rx_ring_map, 849 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 850 851 return (0); 852 } 853 854 static void 855 sk_init_tx_ring(struct sk_if_softc *sc_if) 856 { 857 struct sk_ring_data *rd; 858 struct sk_txdesc *txd; 859 bus_addr_t addr; 860 int i; 861 862 STAILQ_INIT(&sc_if->sk_cdata.sk_txfreeq); 863 STAILQ_INIT(&sc_if->sk_cdata.sk_txbusyq); 864 865 sc_if->sk_cdata.sk_tx_prod = 0; 866 sc_if->sk_cdata.sk_tx_cons = 0; 867 sc_if->sk_cdata.sk_tx_cnt = 0; 868 869 rd = &sc_if->sk_rdata; 870 bzero(rd->sk_tx_ring, sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 871 for (i = 0; i < SK_TX_RING_CNT; i++) { 872 if (i == (SK_TX_RING_CNT - 1)) 873 addr = SK_TX_RING_ADDR(sc_if, 0); 874 else 875 addr = SK_TX_RING_ADDR(sc_if, i + 1); 876 rd->sk_tx_ring[i].sk_next = htole32(SK_ADDR_LO(addr)); 877 txd = &sc_if->sk_cdata.sk_txdesc[i]; 878 STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txfreeq, txd, tx_q); 879 } 880 881 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag, 882 sc_if->sk_cdata.sk_tx_ring_map, 883 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 884 } 885 886 static __inline void 887 sk_discard_rxbuf(struct sk_if_softc *sc_if, int idx) 888 { 889 struct sk_rx_desc *r; 890 struct sk_rxdesc *rxd; 891 struct mbuf *m; 892 893 r = &sc_if->sk_rdata.sk_rx_ring[idx]; 894 rxd = &sc_if->sk_cdata.sk_rxdesc[idx]; 895 m = rxd->rx_m; 896 r->sk_ctl = htole32(m->m_len | SK_RXSTAT | SK_OPCODE_CSUM); 897 } 898 899 static __inline void 900 sk_discard_jumbo_rxbuf(struct sk_if_softc *sc_if, int idx) 901 { 902 struct sk_rx_desc *r; 903 struct sk_rxdesc *rxd; 904 struct mbuf *m; 905 906 r = &sc_if->sk_rdata.sk_jumbo_rx_ring[idx]; 907 rxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[idx]; 908 m = rxd->rx_m; 909 r->sk_ctl = htole32(m->m_len | SK_RXSTAT | SK_OPCODE_CSUM); 910 } 911 912 static int 913 sk_newbuf(struct sk_if_softc *sc_if, int idx) 914 { 915 struct sk_rx_desc *r; 916 struct sk_rxdesc *rxd; 917 struct mbuf *m; 918 bus_dma_segment_t segs[1]; 919 bus_dmamap_t map; 920 int nsegs; 921 922 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 923 if (m == NULL) 924 return (ENOBUFS); 925 m->m_len = m->m_pkthdr.len = MCLBYTES; 926 m_adj(m, ETHER_ALIGN); 927 928 if (bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_rx_tag, 929 sc_if->sk_cdata.sk_rx_sparemap, m, segs, &nsegs, 0) != 0) { 930 m_freem(m); 931 return (ENOBUFS); 932 } 933 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 934 935 rxd = &sc_if->sk_cdata.sk_rxdesc[idx]; 936 if (rxd->rx_m != NULL) { 937 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap, 938 BUS_DMASYNC_POSTREAD); 939 bus_dmamap_unload(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap); 940 } 941 map = rxd->rx_dmamap; 942 rxd->rx_dmamap = sc_if->sk_cdata.sk_rx_sparemap; 943 sc_if->sk_cdata.sk_rx_sparemap = map; 944 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap, 945 BUS_DMASYNC_PREREAD); 946 rxd->rx_m = m; 947 r = &sc_if->sk_rdata.sk_rx_ring[idx]; 948 r->sk_data_lo = htole32(SK_ADDR_LO(segs[0].ds_addr)); 949 r->sk_data_hi = htole32(SK_ADDR_HI(segs[0].ds_addr)); 950 r->sk_ctl = htole32(segs[0].ds_len | SK_RXSTAT | SK_OPCODE_CSUM); 951 952 return (0); 953 } 954 955 static int 956 sk_jumbo_newbuf(struct sk_if_softc *sc_if, int idx) 957 { 958 struct sk_rx_desc *r; 959 struct sk_rxdesc *rxd; 960 struct mbuf *m; 961 bus_dma_segment_t segs[1]; 962 bus_dmamap_t map; 963 int nsegs; 964 965 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 966 if (m == NULL) 967 return (ENOBUFS); 968 m->m_pkthdr.len = m->m_len = MJUM9BYTES; 969 /* 970 * Adjust alignment so packet payload begins on a 971 * longword boundary. Mandatory for Alpha, useful on 972 * x86 too. 973 */ 974 m_adj(m, ETHER_ALIGN); 975 976 if (bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_jumbo_rx_tag, 977 sc_if->sk_cdata.sk_jumbo_rx_sparemap, m, segs, &nsegs, 0) != 0) { 978 m_freem(m); 979 return (ENOBUFS); 980 } 981 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 982 983 rxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[idx]; 984 if (rxd->rx_m != NULL) { 985 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag, rxd->rx_dmamap, 986 BUS_DMASYNC_POSTREAD); 987 bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_tag, 988 rxd->rx_dmamap); 989 } 990 map = rxd->rx_dmamap; 991 rxd->rx_dmamap = sc_if->sk_cdata.sk_jumbo_rx_sparemap; 992 sc_if->sk_cdata.sk_jumbo_rx_sparemap = map; 993 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag, rxd->rx_dmamap, 994 BUS_DMASYNC_PREREAD); 995 rxd->rx_m = m; 996 r = &sc_if->sk_rdata.sk_jumbo_rx_ring[idx]; 997 r->sk_data_lo = htole32(SK_ADDR_LO(segs[0].ds_addr)); 998 r->sk_data_hi = htole32(SK_ADDR_HI(segs[0].ds_addr)); 999 r->sk_ctl = htole32(segs[0].ds_len | SK_RXSTAT | SK_OPCODE_CSUM); 1000 1001 return (0); 1002 } 1003 1004 /* 1005 * Set media options. 1006 */ 1007 static int 1008 sk_ifmedia_upd(if_t ifp) 1009 { 1010 struct sk_if_softc *sc_if = if_getsoftc(ifp); 1011 struct mii_data *mii; 1012 1013 mii = device_get_softc(sc_if->sk_miibus); 1014 sk_init(sc_if); 1015 mii_mediachg(mii); 1016 1017 return(0); 1018 } 1019 1020 /* 1021 * Report current media status. 1022 */ 1023 static void 1024 sk_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr) 1025 { 1026 struct sk_if_softc *sc_if; 1027 struct mii_data *mii; 1028 1029 sc_if = if_getsoftc(ifp); 1030 mii = device_get_softc(sc_if->sk_miibus); 1031 1032 mii_pollstat(mii); 1033 ifmr->ifm_active = mii->mii_media_active; 1034 ifmr->ifm_status = mii->mii_media_status; 1035 1036 return; 1037 } 1038 1039 static int 1040 sk_ioctl(if_t ifp, u_long command, caddr_t data) 1041 { 1042 struct sk_if_softc *sc_if = if_getsoftc(ifp); 1043 struct ifreq *ifr = (struct ifreq *) data; 1044 int error, mask; 1045 struct mii_data *mii; 1046 1047 error = 0; 1048 switch(command) { 1049 case SIOCSIFMTU: 1050 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > SK_JUMBO_MTU) 1051 error = EINVAL; 1052 else if (if_getmtu(ifp) != ifr->ifr_mtu) { 1053 if (sc_if->sk_jumbo_disable != 0 && 1054 ifr->ifr_mtu > SK_MAX_FRAMELEN) 1055 error = EINVAL; 1056 else { 1057 SK_IF_LOCK(sc_if); 1058 if_setmtu(ifp, ifr->ifr_mtu); 1059 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 1060 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1061 sk_init_locked(sc_if); 1062 } 1063 SK_IF_UNLOCK(sc_if); 1064 } 1065 } 1066 break; 1067 case SIOCSIFFLAGS: 1068 SK_IF_LOCK(sc_if); 1069 if (if_getflags(ifp) & IFF_UP) { 1070 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 1071 if ((if_getflags(ifp) ^ sc_if->sk_if_flags) 1072 & (IFF_PROMISC | IFF_ALLMULTI)) 1073 sk_rxfilter(sc_if); 1074 } else 1075 sk_init_locked(sc_if); 1076 } else { 1077 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 1078 sk_stop(sc_if); 1079 } 1080 sc_if->sk_if_flags = if_getflags(ifp); 1081 SK_IF_UNLOCK(sc_if); 1082 break; 1083 case SIOCADDMULTI: 1084 case SIOCDELMULTI: 1085 SK_IF_LOCK(sc_if); 1086 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 1087 sk_rxfilter(sc_if); 1088 SK_IF_UNLOCK(sc_if); 1089 break; 1090 case SIOCGIFMEDIA: 1091 case SIOCSIFMEDIA: 1092 mii = device_get_softc(sc_if->sk_miibus); 1093 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1094 break; 1095 case SIOCSIFCAP: 1096 SK_IF_LOCK(sc_if); 1097 if (sc_if->sk_softc->sk_type == SK_GENESIS) { 1098 SK_IF_UNLOCK(sc_if); 1099 break; 1100 } 1101 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 1102 if ((mask & IFCAP_TXCSUM) != 0 && 1103 (IFCAP_TXCSUM & if_getcapabilities(ifp)) != 0) { 1104 if_togglecapenable(ifp, IFCAP_TXCSUM); 1105 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0) 1106 if_sethwassistbits(ifp, SK_CSUM_FEATURES, 0); 1107 else 1108 if_sethwassistbits(ifp, 0, SK_CSUM_FEATURES); 1109 } 1110 if ((mask & IFCAP_RXCSUM) != 0 && 1111 (IFCAP_RXCSUM & if_getcapabilities(ifp)) != 0) 1112 if_togglecapenable(ifp, IFCAP_RXCSUM); 1113 SK_IF_UNLOCK(sc_if); 1114 break; 1115 default: 1116 error = ether_ioctl(ifp, command, data); 1117 break; 1118 } 1119 1120 return (error); 1121 } 1122 1123 /* 1124 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 1125 * IDs against our list and return a device name if we find a match. 1126 */ 1127 static int 1128 skc_probe(device_t dev) 1129 { 1130 const struct sk_type *t = sk_devs; 1131 1132 while(t->sk_name != NULL) { 1133 if ((pci_get_vendor(dev) == t->sk_vid) && 1134 (pci_get_device(dev) == t->sk_did)) { 1135 /* 1136 * Only attach to rev. 2 of the Linksys EG1032 adapter. 1137 * Rev. 3 is supported by re(4). 1138 */ 1139 if ((t->sk_vid == VENDORID_LINKSYS) && 1140 (t->sk_did == DEVICEID_LINKSYS_EG1032) && 1141 (pci_get_subdevice(dev) != 1142 SUBDEVICEID_LINKSYS_EG1032_REV2)) { 1143 t++; 1144 continue; 1145 } 1146 device_set_desc(dev, t->sk_name); 1147 return (BUS_PROBE_DEFAULT); 1148 } 1149 t++; 1150 } 1151 1152 return(ENXIO); 1153 } 1154 1155 /* 1156 * Force the GEnesis into reset, then bring it out of reset. 1157 */ 1158 static void 1159 sk_reset(struct sk_softc *sc) 1160 { 1161 1162 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 1163 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 1164 if (SK_YUKON_FAMILY(sc->sk_type)) 1165 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 1166 1167 DELAY(1000); 1168 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 1169 DELAY(2); 1170 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1171 if (SK_YUKON_FAMILY(sc->sk_type)) 1172 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 1173 1174 if (sc->sk_type == SK_GENESIS) { 1175 /* Configure packet arbiter */ 1176 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1177 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1178 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1179 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1180 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1181 } 1182 1183 /* Enable RAM interface */ 1184 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1185 1186 /* 1187 * Configure interrupt moderation. The moderation timer 1188 * defers interrupts specified in the interrupt moderation 1189 * timer mask based on the timeout specified in the interrupt 1190 * moderation timer init register. Each bit in the timer 1191 * register represents one tick, so to specify a timeout in 1192 * microseconds, we have to multiply by the correct number of 1193 * ticks-per-microsecond. 1194 */ 1195 switch (sc->sk_type) { 1196 case SK_GENESIS: 1197 sc->sk_int_ticks = SK_IMTIMER_TICKS_GENESIS; 1198 break; 1199 default: 1200 sc->sk_int_ticks = SK_IMTIMER_TICKS_YUKON; 1201 break; 1202 } 1203 if (bootverbose) 1204 device_printf(sc->sk_dev, "interrupt moderation is %d us\n", 1205 sc->sk_int_mod); 1206 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod, 1207 sc->sk_int_ticks)); 1208 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 1209 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 1210 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1211 1212 return; 1213 } 1214 1215 static int 1216 sk_probe(device_t dev) 1217 { 1218 struct sk_softc *sc; 1219 1220 sc = device_get_softc(device_get_parent(dev)); 1221 1222 /* 1223 * Not much to do here. We always know there will be 1224 * at least one XMAC present, and if there are two, 1225 * skc_attach() will create a second device instance 1226 * for us. 1227 */ 1228 switch (sc->sk_type) { 1229 case SK_GENESIS: 1230 device_set_desc(dev, "XaQti Corp. XMAC II"); 1231 break; 1232 case SK_YUKON: 1233 case SK_YUKON_LITE: 1234 case SK_YUKON_LP: 1235 device_set_desc(dev, "Marvell Semiconductor, Inc. Yukon"); 1236 break; 1237 } 1238 1239 return (BUS_PROBE_DEFAULT); 1240 } 1241 1242 /* 1243 * Each XMAC chip is attached as a separate logical IP interface. 1244 * Single port cards will have only one logical interface of course. 1245 */ 1246 static int 1247 sk_attach(device_t dev) 1248 { 1249 struct sk_softc *sc; 1250 struct sk_if_softc *sc_if; 1251 if_t ifp; 1252 u_int32_t r; 1253 int error, i, phy, port; 1254 u_char eaddr[6]; 1255 u_char inv_mac[] = {0, 0, 0, 0, 0, 0}; 1256 1257 if (dev == NULL) 1258 return(EINVAL); 1259 1260 error = 0; 1261 sc_if = device_get_softc(dev); 1262 sc = device_get_softc(device_get_parent(dev)); 1263 port = *(int *)device_get_ivars(dev); 1264 1265 sc_if->sk_if_dev = dev; 1266 sc_if->sk_port = port; 1267 sc_if->sk_softc = sc; 1268 sc->sk_if[port] = sc_if; 1269 if (port == SK_PORT_A) 1270 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1271 if (port == SK_PORT_B) 1272 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1273 1274 callout_init_mtx(&sc_if->sk_tick_ch, &sc_if->sk_softc->sk_mtx, 0); 1275 callout_init_mtx(&sc_if->sk_watchdog_ch, &sc_if->sk_softc->sk_mtx, 0); 1276 1277 if (sk_dma_alloc(sc_if) != 0) { 1278 error = ENOMEM; 1279 goto fail; 1280 } 1281 sk_dma_jumbo_alloc(sc_if); 1282 1283 ifp = sc_if->sk_ifp = if_alloc(IFT_ETHER); 1284 if (ifp == NULL) { 1285 device_printf(sc_if->sk_if_dev, "can not if_alloc()\n"); 1286 error = ENOSPC; 1287 goto fail; 1288 } 1289 if_setsoftc(ifp, sc_if); 1290 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1291 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 1292 /* 1293 * SK_GENESIS has a bug in checksum offload - From linux. 1294 */ 1295 if (sc_if->sk_softc->sk_type != SK_GENESIS) { 1296 if_setcapabilities(ifp, IFCAP_TXCSUM | IFCAP_RXCSUM); 1297 if_sethwassist(ifp, 0); 1298 } else { 1299 if_setcapabilities(ifp, 0); 1300 if_sethwassist(ifp, 0); 1301 } 1302 if_setcapenable(ifp, if_getcapabilities(ifp)); 1303 /* 1304 * Some revision of Yukon controller generates corrupted 1305 * frame when TX checksum offloading is enabled. The 1306 * frame has a valid checksum value so payload might be 1307 * modified during TX checksum calculation. Disable TX 1308 * checksum offloading but give users chance to enable it 1309 * when they know their controller works without problems 1310 * with TX checksum offloading. 1311 */ 1312 if_setcapenablebit(ifp, 0, IFCAP_TXCSUM); 1313 if_setioctlfn(ifp, sk_ioctl); 1314 if_setstartfn(ifp, sk_start); 1315 if_setinitfn(ifp, sk_init); 1316 if_setsendqlen(ifp, SK_TX_RING_CNT - 1); 1317 if_setsendqready(ifp); 1318 1319 /* 1320 * Get station address for this interface. Note that 1321 * dual port cards actually come with three station 1322 * addresses: one for each port, plus an extra. The 1323 * extra one is used by the SysKonnect driver software 1324 * as a 'virtual' station address for when both ports 1325 * are operating in failover mode. Currently we don't 1326 * use this extra address. 1327 */ 1328 SK_IF_LOCK(sc_if); 1329 for (i = 0; i < ETHER_ADDR_LEN; i++) 1330 eaddr[i] = 1331 sk_win_read_1(sc, SK_MAC0_0 + (port * 8) + i); 1332 1333 /* Verify whether the station address is invalid or not. */ 1334 if (bcmp(eaddr, inv_mac, sizeof(inv_mac)) == 0) { 1335 device_printf(sc_if->sk_if_dev, 1336 "Generating random ethernet address\n"); 1337 r = arc4random(); 1338 /* 1339 * Set OUI to convenient locally assigned address. 'b' 1340 * is 0x62, which has the locally assigned bit set, and 1341 * the broadcast/multicast bit clear. 1342 */ 1343 eaddr[0] = 'b'; 1344 eaddr[1] = 's'; 1345 eaddr[2] = 'd'; 1346 eaddr[3] = (r >> 16) & 0xff; 1347 eaddr[4] = (r >> 8) & 0xff; 1348 eaddr[5] = (r >> 0) & 0xff; 1349 } 1350 /* 1351 * Set up RAM buffer addresses. The NIC will have a certain 1352 * amount of SRAM on it, somewhere between 512K and 2MB. We 1353 * need to divide this up a) between the transmitter and 1354 * receiver and b) between the two XMACs, if this is a 1355 * dual port NIC. Our algotithm is to divide up the memory 1356 * evenly so that everyone gets a fair share. 1357 * 1358 * Just to be contrary, Yukon2 appears to have separate memory 1359 * for each MAC. 1360 */ 1361 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1362 u_int32_t chunk, val; 1363 1364 chunk = sc->sk_ramsize / 2; 1365 val = sc->sk_rboff / sizeof(u_int64_t); 1366 sc_if->sk_rx_ramstart = val; 1367 val += (chunk / sizeof(u_int64_t)); 1368 sc_if->sk_rx_ramend = val - 1; 1369 sc_if->sk_tx_ramstart = val; 1370 val += (chunk / sizeof(u_int64_t)); 1371 sc_if->sk_tx_ramend = val - 1; 1372 } else { 1373 u_int32_t chunk, val; 1374 1375 chunk = sc->sk_ramsize / 4; 1376 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1377 sizeof(u_int64_t); 1378 sc_if->sk_rx_ramstart = val; 1379 val += (chunk / sizeof(u_int64_t)); 1380 sc_if->sk_rx_ramend = val - 1; 1381 sc_if->sk_tx_ramstart = val; 1382 val += (chunk / sizeof(u_int64_t)); 1383 sc_if->sk_tx_ramend = val - 1; 1384 } 1385 1386 /* Read and save PHY type and set PHY address */ 1387 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1388 if (!SK_YUKON_FAMILY(sc->sk_type)) { 1389 switch(sc_if->sk_phytype) { 1390 case SK_PHYTYPE_XMAC: 1391 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1392 break; 1393 case SK_PHYTYPE_BCOM: 1394 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1395 break; 1396 default: 1397 device_printf(sc->sk_dev, "unsupported PHY type: %d\n", 1398 sc_if->sk_phytype); 1399 error = ENODEV; 1400 SK_IF_UNLOCK(sc_if); 1401 goto fail; 1402 } 1403 } else { 1404 if (sc_if->sk_phytype < SK_PHYTYPE_MARV_COPPER && 1405 sc->sk_pmd != 'S') { 1406 /* not initialized, punt */ 1407 sc_if->sk_phytype = SK_PHYTYPE_MARV_COPPER; 1408 sc->sk_coppertype = 1; 1409 } 1410 1411 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1412 1413 if (!(sc->sk_coppertype)) 1414 sc_if->sk_phytype = SK_PHYTYPE_MARV_FIBER; 1415 } 1416 1417 /* 1418 * Call MI attach routine. Can't hold locks when calling into ether_*. 1419 */ 1420 SK_IF_UNLOCK(sc_if); 1421 ether_ifattach(ifp, eaddr); 1422 SK_IF_LOCK(sc_if); 1423 1424 /* 1425 * The hardware should be ready for VLAN_MTU by default: 1426 * XMAC II has 0x8100 in VLAN Tag Level 1 register initially; 1427 * YU_SMR_MFL_VLAN is set by this driver in Yukon. 1428 * 1429 */ 1430 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU, 0); 1431 if_setcapenablebit(ifp, IFCAP_VLAN_MTU, 0); 1432 /* 1433 * Tell the upper layer(s) we support long frames. 1434 * Must appear after the call to ether_ifattach() because 1435 * ether_ifattach() sets ifi_hdrlen to the default value. 1436 */ 1437 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 1438 1439 /* 1440 * Do miibus setup. 1441 */ 1442 phy = MII_PHY_ANY; 1443 switch (sc->sk_type) { 1444 case SK_GENESIS: 1445 sk_init_xmac(sc_if); 1446 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 1447 phy = 0; 1448 break; 1449 case SK_YUKON: 1450 case SK_YUKON_LITE: 1451 case SK_YUKON_LP: 1452 sk_init_yukon(sc_if); 1453 phy = 0; 1454 break; 1455 } 1456 1457 SK_IF_UNLOCK(sc_if); 1458 error = mii_attach(dev, &sc_if->sk_miibus, ifp, sk_ifmedia_upd, 1459 sk_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0); 1460 if (error != 0) { 1461 device_printf(sc_if->sk_if_dev, "attaching PHYs failed\n"); 1462 ether_ifdetach(ifp); 1463 goto fail; 1464 } 1465 1466 fail: 1467 if (error) { 1468 /* Access should be ok even though lock has been dropped */ 1469 sc->sk_if[port] = NULL; 1470 sk_detach(dev); 1471 } 1472 1473 return(error); 1474 } 1475 1476 /* 1477 * Attach the interface. Allocate softc structures, do ifmedia 1478 * setup and ethernet/BPF attach. 1479 */ 1480 static int 1481 skc_attach(device_t dev) 1482 { 1483 struct sk_softc *sc; 1484 int error = 0, *port; 1485 uint8_t skrs; 1486 const char *pname = NULL; 1487 char *revstr; 1488 1489 sc = device_get_softc(dev); 1490 sc->sk_dev = dev; 1491 1492 mtx_init(&sc->sk_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1493 MTX_DEF); 1494 mtx_init(&sc->sk_mii_mtx, "sk_mii_mutex", NULL, MTX_DEF); 1495 /* 1496 * Map control/status registers. 1497 */ 1498 pci_enable_busmaster(dev); 1499 1500 /* Allocate resources */ 1501 #ifdef SK_USEIOSPACE 1502 sc->sk_res_spec = sk_res_spec_io; 1503 #else 1504 sc->sk_res_spec = sk_res_spec_mem; 1505 #endif 1506 error = bus_alloc_resources(dev, sc->sk_res_spec, sc->sk_res); 1507 if (error) { 1508 if (sc->sk_res_spec == sk_res_spec_mem) 1509 sc->sk_res_spec = sk_res_spec_io; 1510 else 1511 sc->sk_res_spec = sk_res_spec_mem; 1512 error = bus_alloc_resources(dev, sc->sk_res_spec, sc->sk_res); 1513 if (error) { 1514 device_printf(dev, "couldn't allocate %s resources\n", 1515 sc->sk_res_spec == sk_res_spec_mem ? "memory" : 1516 "I/O"); 1517 goto fail; 1518 } 1519 } 1520 1521 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1522 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4) & 0xf; 1523 1524 /* Bail out if chip is not recognized. */ 1525 if (sc->sk_type != SK_GENESIS && !SK_YUKON_FAMILY(sc->sk_type)) { 1526 device_printf(dev, "unknown device: chipver=%02x, rev=%x\n", 1527 sc->sk_type, sc->sk_rev); 1528 error = ENXIO; 1529 goto fail; 1530 } 1531 1532 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 1533 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 1534 OID_AUTO, "int_mod", 1535 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 1536 &sc->sk_int_mod, 0, sysctl_hw_sk_int_mod, "I", 1537 "SK interrupt moderation"); 1538 1539 /* Pull in device tunables. */ 1540 sc->sk_int_mod = SK_IM_DEFAULT; 1541 error = resource_int_value(device_get_name(dev), device_get_unit(dev), 1542 "int_mod", &sc->sk_int_mod); 1543 if (error == 0) { 1544 if (sc->sk_int_mod < SK_IM_MIN || 1545 sc->sk_int_mod > SK_IM_MAX) { 1546 device_printf(dev, "int_mod value out of range; " 1547 "using default: %d\n", SK_IM_DEFAULT); 1548 sc->sk_int_mod = SK_IM_DEFAULT; 1549 } 1550 } 1551 1552 /* Reset the adapter. */ 1553 sk_reset(sc); 1554 1555 skrs = sk_win_read_1(sc, SK_EPROM0); 1556 if (sc->sk_type == SK_GENESIS) { 1557 /* Read and save RAM size and RAMbuffer offset */ 1558 switch(skrs) { 1559 case SK_RAMSIZE_512K_64: 1560 sc->sk_ramsize = 0x80000; 1561 sc->sk_rboff = SK_RBOFF_0; 1562 break; 1563 case SK_RAMSIZE_1024K_64: 1564 sc->sk_ramsize = 0x100000; 1565 sc->sk_rboff = SK_RBOFF_80000; 1566 break; 1567 case SK_RAMSIZE_1024K_128: 1568 sc->sk_ramsize = 0x100000; 1569 sc->sk_rboff = SK_RBOFF_0; 1570 break; 1571 case SK_RAMSIZE_2048K_128: 1572 sc->sk_ramsize = 0x200000; 1573 sc->sk_rboff = SK_RBOFF_0; 1574 break; 1575 default: 1576 device_printf(dev, "unknown ram size: %d\n", skrs); 1577 error = ENXIO; 1578 goto fail; 1579 } 1580 } else { /* SK_YUKON_FAMILY */ 1581 if (skrs == 0x00) 1582 sc->sk_ramsize = 0x20000; 1583 else 1584 sc->sk_ramsize = skrs * (1<<12); 1585 sc->sk_rboff = SK_RBOFF_0; 1586 } 1587 1588 /* Read and save physical media type */ 1589 sc->sk_pmd = sk_win_read_1(sc, SK_PMDTYPE); 1590 1591 if (sc->sk_pmd == 'T' || sc->sk_pmd == '1') 1592 sc->sk_coppertype = 1; 1593 else 1594 sc->sk_coppertype = 0; 1595 1596 /* Determine whether to name it with VPD PN or just make it up. 1597 * Marvell Yukon VPD PN seems to freqently be bogus. */ 1598 switch (pci_get_device(dev)) { 1599 case DEVICEID_SK_V1: 1600 case DEVICEID_BELKIN_5005: 1601 case DEVICEID_3COM_3C940: 1602 case DEVICEID_LINKSYS_EG1032: 1603 case DEVICEID_DLINK_DGE530T_A1: 1604 case DEVICEID_DLINK_DGE530T_B1: 1605 /* Stay with VPD PN. */ 1606 (void) pci_get_vpd_ident(dev, &pname); 1607 break; 1608 case DEVICEID_SK_V2: 1609 /* YUKON VPD PN might bear no resemblance to reality. */ 1610 switch (sc->sk_type) { 1611 case SK_GENESIS: 1612 /* Stay with VPD PN. */ 1613 (void) pci_get_vpd_ident(dev, &pname); 1614 break; 1615 case SK_YUKON: 1616 pname = "Marvell Yukon Gigabit Ethernet"; 1617 break; 1618 case SK_YUKON_LITE: 1619 pname = "Marvell Yukon Lite Gigabit Ethernet"; 1620 break; 1621 case SK_YUKON_LP: 1622 pname = "Marvell Yukon LP Gigabit Ethernet"; 1623 break; 1624 default: 1625 pname = "Marvell Yukon (Unknown) Gigabit Ethernet"; 1626 break; 1627 } 1628 1629 /* Yukon Lite Rev. A0 needs special test. */ 1630 if (sc->sk_type == SK_YUKON || sc->sk_type == SK_YUKON_LP) { 1631 u_int32_t far; 1632 u_int8_t testbyte; 1633 1634 /* Save flash address register before testing. */ 1635 far = sk_win_read_4(sc, SK_EP_ADDR); 1636 1637 sk_win_write_1(sc, SK_EP_ADDR+0x03, 0xff); 1638 testbyte = sk_win_read_1(sc, SK_EP_ADDR+0x03); 1639 1640 if (testbyte != 0x00) { 1641 /* Yukon Lite Rev. A0 detected. */ 1642 sc->sk_type = SK_YUKON_LITE; 1643 sc->sk_rev = SK_YUKON_LITE_REV_A0; 1644 /* Restore flash address register. */ 1645 sk_win_write_4(sc, SK_EP_ADDR, far); 1646 } 1647 } 1648 break; 1649 default: 1650 device_printf(dev, "unknown device: vendor=%04x, device=%04x, " 1651 "chipver=%02x, rev=%x\n", 1652 pci_get_vendor(dev), pci_get_device(dev), 1653 sc->sk_type, sc->sk_rev); 1654 error = ENXIO; 1655 goto fail; 1656 } 1657 1658 if (sc->sk_type == SK_YUKON_LITE) { 1659 switch (sc->sk_rev) { 1660 case SK_YUKON_LITE_REV_A0: 1661 revstr = "A0"; 1662 break; 1663 case SK_YUKON_LITE_REV_A1: 1664 revstr = "A1"; 1665 break; 1666 case SK_YUKON_LITE_REV_A3: 1667 revstr = "A3"; 1668 break; 1669 default: 1670 revstr = ""; 1671 break; 1672 } 1673 } else { 1674 revstr = ""; 1675 } 1676 1677 /* Announce the product name and more VPD data if there. */ 1678 if (pname != NULL) 1679 device_printf(dev, "%s rev. %s(0x%x)\n", 1680 pname, revstr, sc->sk_rev); 1681 1682 if (bootverbose) { 1683 device_printf(dev, "chip ver = 0x%02x\n", sc->sk_type); 1684 device_printf(dev, "chip rev = 0x%02x\n", sc->sk_rev); 1685 device_printf(dev, "SK_EPROM0 = 0x%02x\n", skrs); 1686 device_printf(dev, "SRAM size = 0x%06x\n", sc->sk_ramsize); 1687 } 1688 1689 sc->sk_devs[SK_PORT_A] = device_add_child(dev, "sk", -1); 1690 if (sc->sk_devs[SK_PORT_A] == NULL) { 1691 device_printf(dev, "failed to add child for PORT_A\n"); 1692 error = ENXIO; 1693 goto fail; 1694 } 1695 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT); 1696 if (port == NULL) { 1697 device_printf(dev, "failed to allocate memory for " 1698 "ivars of PORT_A\n"); 1699 error = ENXIO; 1700 goto fail; 1701 } 1702 *port = SK_PORT_A; 1703 device_set_ivars(sc->sk_devs[SK_PORT_A], port); 1704 1705 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1706 sc->sk_devs[SK_PORT_B] = device_add_child(dev, "sk", -1); 1707 if (sc->sk_devs[SK_PORT_B] == NULL) { 1708 device_printf(dev, "failed to add child for PORT_B\n"); 1709 error = ENXIO; 1710 goto fail; 1711 } 1712 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT); 1713 if (port == NULL) { 1714 device_printf(dev, "failed to allocate memory for " 1715 "ivars of PORT_B\n"); 1716 error = ENXIO; 1717 goto fail; 1718 } 1719 *port = SK_PORT_B; 1720 device_set_ivars(sc->sk_devs[SK_PORT_B], port); 1721 } 1722 1723 /* Turn on the 'driver is loaded' LED. */ 1724 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1725 1726 error = bus_generic_attach(dev); 1727 if (error) { 1728 device_printf(dev, "failed to attach port(s)\n"); 1729 goto fail; 1730 } 1731 1732 /* Hook interrupt last to avoid having to lock softc */ 1733 error = bus_setup_intr(dev, sc->sk_res[1], INTR_TYPE_NET|INTR_MPSAFE, 1734 NULL, sk_intr, sc, &sc->sk_intrhand); 1735 1736 if (error) { 1737 device_printf(dev, "couldn't set up irq\n"); 1738 goto fail; 1739 } 1740 1741 fail: 1742 if (error) 1743 skc_detach(dev); 1744 1745 return(error); 1746 } 1747 1748 /* 1749 * Shutdown hardware and free up resources. This can be called any 1750 * time after the mutex has been initialized. It is called in both 1751 * the error case in attach and the normal detach case so it needs 1752 * to be careful about only freeing resources that have actually been 1753 * allocated. 1754 */ 1755 static int 1756 sk_detach(device_t dev) 1757 { 1758 struct sk_if_softc *sc_if; 1759 if_t ifp; 1760 1761 sc_if = device_get_softc(dev); 1762 KASSERT(mtx_initialized(&sc_if->sk_softc->sk_mtx), 1763 ("sk mutex not initialized in sk_detach")); 1764 SK_IF_LOCK(sc_if); 1765 1766 ifp = sc_if->sk_ifp; 1767 /* These should only be active if attach_xmac succeeded */ 1768 if (device_is_attached(dev)) { 1769 sk_stop(sc_if); 1770 /* Can't hold locks while calling detach */ 1771 SK_IF_UNLOCK(sc_if); 1772 callout_drain(&sc_if->sk_tick_ch); 1773 callout_drain(&sc_if->sk_watchdog_ch); 1774 ether_ifdetach(ifp); 1775 SK_IF_LOCK(sc_if); 1776 } 1777 /* 1778 * We're generally called from skc_detach() which is using 1779 * device_delete_child() to get to here. It's already trashed 1780 * miibus for us, so don't do it here or we'll panic. 1781 */ 1782 /* 1783 if (sc_if->sk_miibus != NULL) 1784 device_delete_child(dev, sc_if->sk_miibus); 1785 */ 1786 bus_generic_detach(dev); 1787 sk_dma_jumbo_free(sc_if); 1788 sk_dma_free(sc_if); 1789 SK_IF_UNLOCK(sc_if); 1790 if (ifp) 1791 if_free(ifp); 1792 1793 return(0); 1794 } 1795 1796 static int 1797 skc_detach(device_t dev) 1798 { 1799 struct sk_softc *sc; 1800 1801 sc = device_get_softc(dev); 1802 KASSERT(mtx_initialized(&sc->sk_mtx), ("sk mutex not initialized")); 1803 1804 if (device_is_alive(dev)) { 1805 if (sc->sk_devs[SK_PORT_A] != NULL) { 1806 free(device_get_ivars(sc->sk_devs[SK_PORT_A]), M_DEVBUF); 1807 device_delete_child(dev, sc->sk_devs[SK_PORT_A]); 1808 } 1809 if (sc->sk_devs[SK_PORT_B] != NULL) { 1810 free(device_get_ivars(sc->sk_devs[SK_PORT_B]), M_DEVBUF); 1811 device_delete_child(dev, sc->sk_devs[SK_PORT_B]); 1812 } 1813 bus_generic_detach(dev); 1814 } 1815 1816 if (sc->sk_intrhand) 1817 bus_teardown_intr(dev, sc->sk_res[1], sc->sk_intrhand); 1818 bus_release_resources(dev, sc->sk_res_spec, sc->sk_res); 1819 1820 mtx_destroy(&sc->sk_mii_mtx); 1821 mtx_destroy(&sc->sk_mtx); 1822 1823 return(0); 1824 } 1825 1826 static bus_dma_tag_t 1827 skc_get_dma_tag(device_t bus, device_t child __unused) 1828 { 1829 1830 return (bus_get_dma_tag(bus)); 1831 } 1832 1833 struct sk_dmamap_arg { 1834 bus_addr_t sk_busaddr; 1835 }; 1836 1837 static void 1838 sk_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1839 { 1840 struct sk_dmamap_arg *ctx; 1841 1842 if (error != 0) 1843 return; 1844 1845 ctx = arg; 1846 ctx->sk_busaddr = segs[0].ds_addr; 1847 } 1848 1849 /* 1850 * Allocate jumbo buffer storage. The SysKonnect adapters support 1851 * "jumbograms" (9K frames), although SysKonnect doesn't currently 1852 * use them in their drivers. In order for us to use them, we need 1853 * large 9K receive buffers, however standard mbuf clusters are only 1854 * 2048 bytes in size. Consequently, we need to allocate and manage 1855 * our own jumbo buffer pool. Fortunately, this does not require an 1856 * excessive amount of additional code. 1857 */ 1858 static int 1859 sk_dma_alloc(struct sk_if_softc *sc_if) 1860 { 1861 struct sk_dmamap_arg ctx; 1862 struct sk_txdesc *txd; 1863 struct sk_rxdesc *rxd; 1864 int error, i; 1865 1866 /* create parent tag */ 1867 /* 1868 * XXX 1869 * This driver should use BUS_SPACE_MAXADDR for lowaddr argument 1870 * in bus_dma_tag_create(9) as the NIC would support DAC mode. 1871 * However bz@ reported that it does not work on amd64 with > 4GB 1872 * RAM. Until we have more clues of the breakage, disable DAC mode 1873 * by limiting DMA address to be in 32bit address space. 1874 */ 1875 error = bus_dma_tag_create( 1876 bus_get_dma_tag(sc_if->sk_if_dev),/* parent */ 1877 1, 0, /* algnmnt, boundary */ 1878 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1879 BUS_SPACE_MAXADDR, /* highaddr */ 1880 NULL, NULL, /* filter, filterarg */ 1881 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1882 0, /* nsegments */ 1883 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1884 0, /* flags */ 1885 NULL, NULL, /* lockfunc, lockarg */ 1886 &sc_if->sk_cdata.sk_parent_tag); 1887 if (error != 0) { 1888 device_printf(sc_if->sk_if_dev, 1889 "failed to create parent DMA tag\n"); 1890 goto fail; 1891 } 1892 1893 /* create tag for Tx ring */ 1894 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */ 1895 SK_RING_ALIGN, 0, /* algnmnt, boundary */ 1896 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1897 BUS_SPACE_MAXADDR, /* highaddr */ 1898 NULL, NULL, /* filter, filterarg */ 1899 SK_TX_RING_SZ, /* maxsize */ 1900 1, /* nsegments */ 1901 SK_TX_RING_SZ, /* maxsegsize */ 1902 0, /* flags */ 1903 NULL, NULL, /* lockfunc, lockarg */ 1904 &sc_if->sk_cdata.sk_tx_ring_tag); 1905 if (error != 0) { 1906 device_printf(sc_if->sk_if_dev, 1907 "failed to allocate Tx ring DMA tag\n"); 1908 goto fail; 1909 } 1910 1911 /* create tag for Rx ring */ 1912 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */ 1913 SK_RING_ALIGN, 0, /* algnmnt, boundary */ 1914 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1915 BUS_SPACE_MAXADDR, /* highaddr */ 1916 NULL, NULL, /* filter, filterarg */ 1917 SK_RX_RING_SZ, /* maxsize */ 1918 1, /* nsegments */ 1919 SK_RX_RING_SZ, /* maxsegsize */ 1920 0, /* flags */ 1921 NULL, NULL, /* lockfunc, lockarg */ 1922 &sc_if->sk_cdata.sk_rx_ring_tag); 1923 if (error != 0) { 1924 device_printf(sc_if->sk_if_dev, 1925 "failed to allocate Rx ring DMA tag\n"); 1926 goto fail; 1927 } 1928 1929 /* create tag for Tx buffers */ 1930 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */ 1931 1, 0, /* algnmnt, boundary */ 1932 BUS_SPACE_MAXADDR, /* lowaddr */ 1933 BUS_SPACE_MAXADDR, /* highaddr */ 1934 NULL, NULL, /* filter, filterarg */ 1935 MCLBYTES * SK_MAXTXSEGS, /* maxsize */ 1936 SK_MAXTXSEGS, /* nsegments */ 1937 MCLBYTES, /* maxsegsize */ 1938 0, /* flags */ 1939 NULL, NULL, /* lockfunc, lockarg */ 1940 &sc_if->sk_cdata.sk_tx_tag); 1941 if (error != 0) { 1942 device_printf(sc_if->sk_if_dev, 1943 "failed to allocate Tx DMA tag\n"); 1944 goto fail; 1945 } 1946 1947 /* create tag for Rx buffers */ 1948 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */ 1949 1, 0, /* algnmnt, boundary */ 1950 BUS_SPACE_MAXADDR, /* lowaddr */ 1951 BUS_SPACE_MAXADDR, /* highaddr */ 1952 NULL, NULL, /* filter, filterarg */ 1953 MCLBYTES, /* maxsize */ 1954 1, /* nsegments */ 1955 MCLBYTES, /* maxsegsize */ 1956 0, /* flags */ 1957 NULL, NULL, /* lockfunc, lockarg */ 1958 &sc_if->sk_cdata.sk_rx_tag); 1959 if (error != 0) { 1960 device_printf(sc_if->sk_if_dev, 1961 "failed to allocate Rx DMA tag\n"); 1962 goto fail; 1963 } 1964 1965 /* allocate DMA'able memory and load the DMA map for Tx ring */ 1966 error = bus_dmamem_alloc(sc_if->sk_cdata.sk_tx_ring_tag, 1967 (void **)&sc_if->sk_rdata.sk_tx_ring, BUS_DMA_NOWAIT | 1968 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->sk_cdata.sk_tx_ring_map); 1969 if (error != 0) { 1970 device_printf(sc_if->sk_if_dev, 1971 "failed to allocate DMA'able memory for Tx ring\n"); 1972 goto fail; 1973 } 1974 1975 ctx.sk_busaddr = 0; 1976 error = bus_dmamap_load(sc_if->sk_cdata.sk_tx_ring_tag, 1977 sc_if->sk_cdata.sk_tx_ring_map, sc_if->sk_rdata.sk_tx_ring, 1978 SK_TX_RING_SZ, sk_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 1979 if (error != 0) { 1980 device_printf(sc_if->sk_if_dev, 1981 "failed to load DMA'able memory for Tx ring\n"); 1982 goto fail; 1983 } 1984 sc_if->sk_rdata.sk_tx_ring_paddr = ctx.sk_busaddr; 1985 1986 /* allocate DMA'able memory and load the DMA map for Rx ring */ 1987 error = bus_dmamem_alloc(sc_if->sk_cdata.sk_rx_ring_tag, 1988 (void **)&sc_if->sk_rdata.sk_rx_ring, BUS_DMA_NOWAIT | 1989 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->sk_cdata.sk_rx_ring_map); 1990 if (error != 0) { 1991 device_printf(sc_if->sk_if_dev, 1992 "failed to allocate DMA'able memory for Rx ring\n"); 1993 goto fail; 1994 } 1995 1996 ctx.sk_busaddr = 0; 1997 error = bus_dmamap_load(sc_if->sk_cdata.sk_rx_ring_tag, 1998 sc_if->sk_cdata.sk_rx_ring_map, sc_if->sk_rdata.sk_rx_ring, 1999 SK_RX_RING_SZ, sk_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 2000 if (error != 0) { 2001 device_printf(sc_if->sk_if_dev, 2002 "failed to load DMA'able memory for Rx ring\n"); 2003 goto fail; 2004 } 2005 sc_if->sk_rdata.sk_rx_ring_paddr = ctx.sk_busaddr; 2006 2007 /* create DMA maps for Tx buffers */ 2008 for (i = 0; i < SK_TX_RING_CNT; i++) { 2009 txd = &sc_if->sk_cdata.sk_txdesc[i]; 2010 txd->tx_m = NULL; 2011 txd->tx_dmamap = NULL; 2012 error = bus_dmamap_create(sc_if->sk_cdata.sk_tx_tag, 0, 2013 &txd->tx_dmamap); 2014 if (error != 0) { 2015 device_printf(sc_if->sk_if_dev, 2016 "failed to create Tx dmamap\n"); 2017 goto fail; 2018 } 2019 } 2020 2021 /* create DMA maps for Rx buffers */ 2022 if ((error = bus_dmamap_create(sc_if->sk_cdata.sk_rx_tag, 0, 2023 &sc_if->sk_cdata.sk_rx_sparemap)) != 0) { 2024 device_printf(sc_if->sk_if_dev, 2025 "failed to create spare Rx dmamap\n"); 2026 goto fail; 2027 } 2028 for (i = 0; i < SK_RX_RING_CNT; i++) { 2029 rxd = &sc_if->sk_cdata.sk_rxdesc[i]; 2030 rxd->rx_m = NULL; 2031 rxd->rx_dmamap = NULL; 2032 error = bus_dmamap_create(sc_if->sk_cdata.sk_rx_tag, 0, 2033 &rxd->rx_dmamap); 2034 if (error != 0) { 2035 device_printf(sc_if->sk_if_dev, 2036 "failed to create Rx dmamap\n"); 2037 goto fail; 2038 } 2039 } 2040 2041 fail: 2042 return (error); 2043 } 2044 2045 static int 2046 sk_dma_jumbo_alloc(struct sk_if_softc *sc_if) 2047 { 2048 struct sk_dmamap_arg ctx; 2049 struct sk_rxdesc *jrxd; 2050 int error, i; 2051 2052 if (jumbo_disable != 0) { 2053 device_printf(sc_if->sk_if_dev, "disabling jumbo frame support\n"); 2054 sc_if->sk_jumbo_disable = 1; 2055 return (0); 2056 } 2057 /* create tag for jumbo Rx ring */ 2058 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */ 2059 SK_RING_ALIGN, 0, /* algnmnt, boundary */ 2060 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 2061 BUS_SPACE_MAXADDR, /* highaddr */ 2062 NULL, NULL, /* filter, filterarg */ 2063 SK_JUMBO_RX_RING_SZ, /* maxsize */ 2064 1, /* nsegments */ 2065 SK_JUMBO_RX_RING_SZ, /* maxsegsize */ 2066 0, /* flags */ 2067 NULL, NULL, /* lockfunc, lockarg */ 2068 &sc_if->sk_cdata.sk_jumbo_rx_ring_tag); 2069 if (error != 0) { 2070 device_printf(sc_if->sk_if_dev, 2071 "failed to allocate jumbo Rx ring DMA tag\n"); 2072 goto jumbo_fail; 2073 } 2074 2075 /* create tag for jumbo Rx buffers */ 2076 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */ 2077 1, 0, /* algnmnt, boundary */ 2078 BUS_SPACE_MAXADDR, /* lowaddr */ 2079 BUS_SPACE_MAXADDR, /* highaddr */ 2080 NULL, NULL, /* filter, filterarg */ 2081 MJUM9BYTES, /* maxsize */ 2082 1, /* nsegments */ 2083 MJUM9BYTES, /* maxsegsize */ 2084 0, /* flags */ 2085 NULL, NULL, /* lockfunc, lockarg */ 2086 &sc_if->sk_cdata.sk_jumbo_rx_tag); 2087 if (error != 0) { 2088 device_printf(sc_if->sk_if_dev, 2089 "failed to allocate jumbo Rx DMA tag\n"); 2090 goto jumbo_fail; 2091 } 2092 2093 /* allocate DMA'able memory and load the DMA map for jumbo Rx ring */ 2094 error = bus_dmamem_alloc(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 2095 (void **)&sc_if->sk_rdata.sk_jumbo_rx_ring, BUS_DMA_NOWAIT | 2096 BUS_DMA_COHERENT | BUS_DMA_ZERO, 2097 &sc_if->sk_cdata.sk_jumbo_rx_ring_map); 2098 if (error != 0) { 2099 device_printf(sc_if->sk_if_dev, 2100 "failed to allocate DMA'able memory for jumbo Rx ring\n"); 2101 goto jumbo_fail; 2102 } 2103 2104 ctx.sk_busaddr = 0; 2105 error = bus_dmamap_load(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 2106 sc_if->sk_cdata.sk_jumbo_rx_ring_map, 2107 sc_if->sk_rdata.sk_jumbo_rx_ring, SK_JUMBO_RX_RING_SZ, sk_dmamap_cb, 2108 &ctx, BUS_DMA_NOWAIT); 2109 if (error != 0) { 2110 device_printf(sc_if->sk_if_dev, 2111 "failed to load DMA'able memory for jumbo Rx ring\n"); 2112 goto jumbo_fail; 2113 } 2114 sc_if->sk_rdata.sk_jumbo_rx_ring_paddr = ctx.sk_busaddr; 2115 2116 /* create DMA maps for jumbo Rx buffers */ 2117 if ((error = bus_dmamap_create(sc_if->sk_cdata.sk_jumbo_rx_tag, 0, 2118 &sc_if->sk_cdata.sk_jumbo_rx_sparemap)) != 0) { 2119 device_printf(sc_if->sk_if_dev, 2120 "failed to create spare jumbo Rx dmamap\n"); 2121 goto jumbo_fail; 2122 } 2123 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) { 2124 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i]; 2125 jrxd->rx_m = NULL; 2126 jrxd->rx_dmamap = NULL; 2127 error = bus_dmamap_create(sc_if->sk_cdata.sk_jumbo_rx_tag, 0, 2128 &jrxd->rx_dmamap); 2129 if (error != 0) { 2130 device_printf(sc_if->sk_if_dev, 2131 "failed to create jumbo Rx dmamap\n"); 2132 goto jumbo_fail; 2133 } 2134 } 2135 2136 return (0); 2137 2138 jumbo_fail: 2139 sk_dma_jumbo_free(sc_if); 2140 device_printf(sc_if->sk_if_dev, "disabling jumbo frame support due to " 2141 "resource shortage\n"); 2142 sc_if->sk_jumbo_disable = 1; 2143 return (0); 2144 } 2145 2146 static void 2147 sk_dma_free(struct sk_if_softc *sc_if) 2148 { 2149 struct sk_txdesc *txd; 2150 struct sk_rxdesc *rxd; 2151 int i; 2152 2153 /* Tx ring */ 2154 if (sc_if->sk_cdata.sk_tx_ring_tag) { 2155 if (sc_if->sk_rdata.sk_tx_ring_paddr) 2156 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_ring_tag, 2157 sc_if->sk_cdata.sk_tx_ring_map); 2158 if (sc_if->sk_rdata.sk_tx_ring) 2159 bus_dmamem_free(sc_if->sk_cdata.sk_tx_ring_tag, 2160 sc_if->sk_rdata.sk_tx_ring, 2161 sc_if->sk_cdata.sk_tx_ring_map); 2162 sc_if->sk_rdata.sk_tx_ring = NULL; 2163 sc_if->sk_rdata.sk_tx_ring_paddr = 0; 2164 bus_dma_tag_destroy(sc_if->sk_cdata.sk_tx_ring_tag); 2165 sc_if->sk_cdata.sk_tx_ring_tag = NULL; 2166 } 2167 /* Rx ring */ 2168 if (sc_if->sk_cdata.sk_rx_ring_tag) { 2169 if (sc_if->sk_rdata.sk_rx_ring_paddr) 2170 bus_dmamap_unload(sc_if->sk_cdata.sk_rx_ring_tag, 2171 sc_if->sk_cdata.sk_rx_ring_map); 2172 if (sc_if->sk_rdata.sk_rx_ring) 2173 bus_dmamem_free(sc_if->sk_cdata.sk_rx_ring_tag, 2174 sc_if->sk_rdata.sk_rx_ring, 2175 sc_if->sk_cdata.sk_rx_ring_map); 2176 sc_if->sk_rdata.sk_rx_ring = NULL; 2177 sc_if->sk_rdata.sk_rx_ring_paddr = 0; 2178 bus_dma_tag_destroy(sc_if->sk_cdata.sk_rx_ring_tag); 2179 sc_if->sk_cdata.sk_rx_ring_tag = NULL; 2180 } 2181 /* Tx buffers */ 2182 if (sc_if->sk_cdata.sk_tx_tag) { 2183 for (i = 0; i < SK_TX_RING_CNT; i++) { 2184 txd = &sc_if->sk_cdata.sk_txdesc[i]; 2185 if (txd->tx_dmamap) { 2186 bus_dmamap_destroy(sc_if->sk_cdata.sk_tx_tag, 2187 txd->tx_dmamap); 2188 txd->tx_dmamap = NULL; 2189 } 2190 } 2191 bus_dma_tag_destroy(sc_if->sk_cdata.sk_tx_tag); 2192 sc_if->sk_cdata.sk_tx_tag = NULL; 2193 } 2194 /* Rx buffers */ 2195 if (sc_if->sk_cdata.sk_rx_tag) { 2196 for (i = 0; i < SK_RX_RING_CNT; i++) { 2197 rxd = &sc_if->sk_cdata.sk_rxdesc[i]; 2198 if (rxd->rx_dmamap) { 2199 bus_dmamap_destroy(sc_if->sk_cdata.sk_rx_tag, 2200 rxd->rx_dmamap); 2201 rxd->rx_dmamap = NULL; 2202 } 2203 } 2204 if (sc_if->sk_cdata.sk_rx_sparemap) { 2205 bus_dmamap_destroy(sc_if->sk_cdata.sk_rx_tag, 2206 sc_if->sk_cdata.sk_rx_sparemap); 2207 sc_if->sk_cdata.sk_rx_sparemap = NULL; 2208 } 2209 bus_dma_tag_destroy(sc_if->sk_cdata.sk_rx_tag); 2210 sc_if->sk_cdata.sk_rx_tag = NULL; 2211 } 2212 2213 if (sc_if->sk_cdata.sk_parent_tag) { 2214 bus_dma_tag_destroy(sc_if->sk_cdata.sk_parent_tag); 2215 sc_if->sk_cdata.sk_parent_tag = NULL; 2216 } 2217 } 2218 2219 static void 2220 sk_dma_jumbo_free(struct sk_if_softc *sc_if) 2221 { 2222 struct sk_rxdesc *jrxd; 2223 int i; 2224 2225 /* jumbo Rx ring */ 2226 if (sc_if->sk_cdata.sk_jumbo_rx_ring_tag) { 2227 if (sc_if->sk_rdata.sk_jumbo_rx_ring_paddr) 2228 bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 2229 sc_if->sk_cdata.sk_jumbo_rx_ring_map); 2230 if (sc_if->sk_rdata.sk_jumbo_rx_ring) 2231 bus_dmamem_free(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 2232 sc_if->sk_rdata.sk_jumbo_rx_ring, 2233 sc_if->sk_cdata.sk_jumbo_rx_ring_map); 2234 sc_if->sk_rdata.sk_jumbo_rx_ring = NULL; 2235 sc_if->sk_rdata.sk_jumbo_rx_ring_paddr = 0; 2236 bus_dma_tag_destroy(sc_if->sk_cdata.sk_jumbo_rx_ring_tag); 2237 sc_if->sk_cdata.sk_jumbo_rx_ring_tag = NULL; 2238 } 2239 2240 /* jumbo Rx buffers */ 2241 if (sc_if->sk_cdata.sk_jumbo_rx_tag) { 2242 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) { 2243 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i]; 2244 if (jrxd->rx_dmamap) { 2245 bus_dmamap_destroy( 2246 sc_if->sk_cdata.sk_jumbo_rx_tag, 2247 jrxd->rx_dmamap); 2248 jrxd->rx_dmamap = NULL; 2249 } 2250 } 2251 if (sc_if->sk_cdata.sk_jumbo_rx_sparemap) { 2252 bus_dmamap_destroy(sc_if->sk_cdata.sk_jumbo_rx_tag, 2253 sc_if->sk_cdata.sk_jumbo_rx_sparemap); 2254 sc_if->sk_cdata.sk_jumbo_rx_sparemap = NULL; 2255 } 2256 bus_dma_tag_destroy(sc_if->sk_cdata.sk_jumbo_rx_tag); 2257 sc_if->sk_cdata.sk_jumbo_rx_tag = NULL; 2258 } 2259 } 2260 2261 static void 2262 sk_txcksum(if_t ifp, struct mbuf *m, struct sk_tx_desc *f) 2263 { 2264 struct ip *ip; 2265 u_int16_t offset; 2266 u_int8_t *p; 2267 2268 offset = sizeof(struct ip) + ETHER_HDR_LEN; 2269 for(; m && m->m_len == 0; m = m->m_next) 2270 ; 2271 if (m == NULL || m->m_len < ETHER_HDR_LEN) { 2272 if_printf(ifp, "%s: m_len < ETHER_HDR_LEN\n", __func__); 2273 /* checksum may be corrupted */ 2274 goto sendit; 2275 } 2276 if (m->m_len < ETHER_HDR_LEN + sizeof(u_int32_t)) { 2277 if (m->m_len != ETHER_HDR_LEN) { 2278 if_printf(ifp, "%s: m_len != ETHER_HDR_LEN\n", 2279 __func__); 2280 /* checksum may be corrupted */ 2281 goto sendit; 2282 } 2283 for(m = m->m_next; m && m->m_len == 0; m = m->m_next) 2284 ; 2285 if (m == NULL) { 2286 offset = sizeof(struct ip) + ETHER_HDR_LEN; 2287 /* checksum may be corrupted */ 2288 goto sendit; 2289 } 2290 ip = mtod(m, struct ip *); 2291 } else { 2292 p = mtod(m, u_int8_t *); 2293 p += ETHER_HDR_LEN; 2294 ip = (struct ip *)p; 2295 } 2296 offset = (ip->ip_hl << 2) + ETHER_HDR_LEN; 2297 2298 sendit: 2299 f->sk_csum_startval = 0; 2300 f->sk_csum_start = htole32(((offset + m->m_pkthdr.csum_data) & 0xffff) | 2301 (offset << 16)); 2302 } 2303 2304 static int 2305 sk_encap(struct sk_if_softc *sc_if, struct mbuf **m_head) 2306 { 2307 struct sk_txdesc *txd; 2308 struct sk_tx_desc *f = NULL; 2309 struct mbuf *m; 2310 bus_dma_segment_t txsegs[SK_MAXTXSEGS]; 2311 u_int32_t cflags, frag, si, sk_ctl; 2312 int error, i, nseg; 2313 2314 SK_IF_LOCK_ASSERT(sc_if); 2315 2316 if ((txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txfreeq)) == NULL) 2317 return (ENOBUFS); 2318 2319 error = bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_tx_tag, 2320 txd->tx_dmamap, *m_head, txsegs, &nseg, 0); 2321 if (error == EFBIG) { 2322 m = m_defrag(*m_head, M_NOWAIT); 2323 if (m == NULL) { 2324 m_freem(*m_head); 2325 *m_head = NULL; 2326 return (ENOMEM); 2327 } 2328 *m_head = m; 2329 error = bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_tx_tag, 2330 txd->tx_dmamap, *m_head, txsegs, &nseg, 0); 2331 if (error != 0) { 2332 m_freem(*m_head); 2333 *m_head = NULL; 2334 return (error); 2335 } 2336 } else if (error != 0) 2337 return (error); 2338 if (nseg == 0) { 2339 m_freem(*m_head); 2340 *m_head = NULL; 2341 return (EIO); 2342 } 2343 if (sc_if->sk_cdata.sk_tx_cnt + nseg >= SK_TX_RING_CNT) { 2344 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap); 2345 return (ENOBUFS); 2346 } 2347 2348 m = *m_head; 2349 if ((m->m_pkthdr.csum_flags & if_gethwassist(sc_if->sk_ifp)) != 0) 2350 cflags = SK_OPCODE_CSUM; 2351 else 2352 cflags = SK_OPCODE_DEFAULT; 2353 si = frag = sc_if->sk_cdata.sk_tx_prod; 2354 for (i = 0; i < nseg; i++) { 2355 f = &sc_if->sk_rdata.sk_tx_ring[frag]; 2356 f->sk_data_lo = htole32(SK_ADDR_LO(txsegs[i].ds_addr)); 2357 f->sk_data_hi = htole32(SK_ADDR_HI(txsegs[i].ds_addr)); 2358 sk_ctl = txsegs[i].ds_len | cflags; 2359 if (i == 0) { 2360 if (cflags == SK_OPCODE_CSUM) 2361 sk_txcksum(sc_if->sk_ifp, m, f); 2362 sk_ctl |= SK_TXCTL_FIRSTFRAG; 2363 } else 2364 sk_ctl |= SK_TXCTL_OWN; 2365 f->sk_ctl = htole32(sk_ctl); 2366 sc_if->sk_cdata.sk_tx_cnt++; 2367 SK_INC(frag, SK_TX_RING_CNT); 2368 } 2369 sc_if->sk_cdata.sk_tx_prod = frag; 2370 2371 /* set EOF on the last descriptor */ 2372 frag = (frag + SK_TX_RING_CNT - 1) % SK_TX_RING_CNT; 2373 f = &sc_if->sk_rdata.sk_tx_ring[frag]; 2374 f->sk_ctl |= htole32(SK_TXCTL_LASTFRAG | SK_TXCTL_EOF_INTR); 2375 2376 /* turn the first descriptor ownership to NIC */ 2377 f = &sc_if->sk_rdata.sk_tx_ring[si]; 2378 f->sk_ctl |= htole32(SK_TXCTL_OWN); 2379 2380 STAILQ_REMOVE_HEAD(&sc_if->sk_cdata.sk_txfreeq, tx_q); 2381 STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txbusyq, txd, tx_q); 2382 txd->tx_m = m; 2383 2384 /* sync descriptors */ 2385 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap, 2386 BUS_DMASYNC_PREWRITE); 2387 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag, 2388 sc_if->sk_cdata.sk_tx_ring_map, 2389 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2390 2391 return (0); 2392 } 2393 2394 static void 2395 sk_start(if_t ifp) 2396 { 2397 struct sk_if_softc *sc_if; 2398 2399 sc_if = if_getsoftc(ifp); 2400 2401 SK_IF_LOCK(sc_if); 2402 sk_start_locked(ifp); 2403 SK_IF_UNLOCK(sc_if); 2404 2405 return; 2406 } 2407 2408 static void 2409 sk_start_locked(if_t ifp) 2410 { 2411 struct sk_softc *sc; 2412 struct sk_if_softc *sc_if; 2413 struct mbuf *m_head; 2414 int enq; 2415 2416 sc_if = if_getsoftc(ifp); 2417 sc = sc_if->sk_softc; 2418 2419 SK_IF_LOCK_ASSERT(sc_if); 2420 2421 for (enq = 0; !if_sendq_empty(ifp) && 2422 sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 1; ) { 2423 m_head = if_dequeue(ifp); 2424 if (m_head == NULL) 2425 break; 2426 2427 /* 2428 * Pack the data into the transmit ring. If we 2429 * don't have room, set the OACTIVE flag and wait 2430 * for the NIC to drain the ring. 2431 */ 2432 if (sk_encap(sc_if, &m_head)) { 2433 if (m_head == NULL) 2434 break; 2435 if_sendq_prepend(ifp, m_head); 2436 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 2437 break; 2438 } 2439 2440 enq++; 2441 /* 2442 * If there's a BPF listener, bounce a copy of this frame 2443 * to him. 2444 */ 2445 BPF_MTAP(ifp, m_head); 2446 } 2447 2448 if (enq > 0) { 2449 /* Transmit */ 2450 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 2451 2452 /* Set a timeout in case the chip goes out to lunch. */ 2453 sc_if->sk_watchdog_timer = 5; 2454 } 2455 } 2456 2457 static void 2458 sk_watchdog(void *arg) 2459 { 2460 struct sk_if_softc *sc_if; 2461 if_t ifp; 2462 2463 ifp = arg; 2464 sc_if = if_getsoftc(ifp); 2465 2466 SK_IF_LOCK_ASSERT(sc_if); 2467 2468 if (sc_if->sk_watchdog_timer == 0 || --sc_if->sk_watchdog_timer) 2469 goto done; 2470 2471 /* 2472 * Reclaim first as there is a possibility of losing Tx completion 2473 * interrupts. 2474 */ 2475 sk_txeof(sc_if); 2476 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 2477 if_printf(sc_if->sk_ifp, "watchdog timeout\n"); 2478 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2479 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2480 sk_init_locked(sc_if); 2481 } 2482 2483 done: 2484 callout_reset(&sc_if->sk_watchdog_ch, hz, sk_watchdog, ifp); 2485 2486 return; 2487 } 2488 2489 static int 2490 skc_shutdown(device_t dev) 2491 { 2492 struct sk_softc *sc; 2493 2494 sc = device_get_softc(dev); 2495 SK_LOCK(sc); 2496 2497 /* Turn off the 'driver is loaded' LED. */ 2498 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 2499 2500 /* 2501 * Reset the GEnesis controller. Doing this should also 2502 * assert the resets on the attached XMAC(s). 2503 */ 2504 sk_reset(sc); 2505 SK_UNLOCK(sc); 2506 2507 return (0); 2508 } 2509 2510 static int 2511 skc_suspend(device_t dev) 2512 { 2513 struct sk_softc *sc; 2514 struct sk_if_softc *sc_if0, *sc_if1; 2515 if_t ifp0 = NULL, ifp1 = NULL; 2516 2517 sc = device_get_softc(dev); 2518 2519 SK_LOCK(sc); 2520 2521 sc_if0 = sc->sk_if[SK_PORT_A]; 2522 sc_if1 = sc->sk_if[SK_PORT_B]; 2523 if (sc_if0 != NULL) 2524 ifp0 = sc_if0->sk_ifp; 2525 if (sc_if1 != NULL) 2526 ifp1 = sc_if1->sk_ifp; 2527 if (ifp0 != NULL) 2528 sk_stop(sc_if0); 2529 if (ifp1 != NULL) 2530 sk_stop(sc_if1); 2531 sc->sk_suspended = 1; 2532 2533 SK_UNLOCK(sc); 2534 2535 return (0); 2536 } 2537 2538 static int 2539 skc_resume(device_t dev) 2540 { 2541 struct sk_softc *sc; 2542 struct sk_if_softc *sc_if0, *sc_if1; 2543 if_t ifp0 = NULL, ifp1 = NULL; 2544 2545 sc = device_get_softc(dev); 2546 2547 SK_LOCK(sc); 2548 2549 sc_if0 = sc->sk_if[SK_PORT_A]; 2550 sc_if1 = sc->sk_if[SK_PORT_B]; 2551 if (sc_if0 != NULL) 2552 ifp0 = sc_if0->sk_ifp; 2553 if (sc_if1 != NULL) 2554 ifp1 = sc_if1->sk_ifp; 2555 if (ifp0 != NULL && if_getflags(ifp0) & IFF_UP) 2556 sk_init_locked(sc_if0); 2557 if (ifp1 != NULL && if_getflags(ifp1) & IFF_UP) 2558 sk_init_locked(sc_if1); 2559 sc->sk_suspended = 0; 2560 2561 SK_UNLOCK(sc); 2562 2563 return (0); 2564 } 2565 2566 /* 2567 * According to the data sheet from SK-NET GENESIS the hardware can compute 2568 * two Rx checksums at the same time(Each checksum start position is 2569 * programmed in Rx descriptors). However it seems that TCP/UDP checksum 2570 * does not work at least on my Yukon hardware. I tried every possible ways 2571 * to get correct checksum value but couldn't get correct one. So TCP/UDP 2572 * checksum offload was disabled at the moment and only IP checksum offload 2573 * was enabled. 2574 * As normal IP header size is 20 bytes I can't expect it would give an 2575 * increase in throughput. However it seems it doesn't hurt performance in 2576 * my testing. If there is a more detailed information for checksum secret 2577 * of the hardware in question please contact yongari@FreeBSD.org to add 2578 * TCP/UDP checksum offload support. 2579 */ 2580 static __inline void 2581 sk_rxcksum(if_t ifp, struct mbuf *m, u_int32_t csum) 2582 { 2583 struct ether_header *eh; 2584 struct ip *ip; 2585 int32_t hlen, len, pktlen; 2586 u_int16_t csum1, csum2, ipcsum; 2587 2588 pktlen = m->m_pkthdr.len; 2589 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip)) 2590 return; 2591 eh = mtod(m, struct ether_header *); 2592 if (eh->ether_type != htons(ETHERTYPE_IP)) 2593 return; 2594 ip = (struct ip *)(eh + 1); 2595 if (ip->ip_v != IPVERSION) 2596 return; 2597 hlen = ip->ip_hl << 2; 2598 pktlen -= sizeof(struct ether_header); 2599 if (hlen < sizeof(struct ip)) 2600 return; 2601 if (ntohs(ip->ip_len) < hlen) 2602 return; 2603 if (ntohs(ip->ip_len) != pktlen) 2604 return; 2605 2606 csum1 = htons(csum & 0xffff); 2607 csum2 = htons((csum >> 16) & 0xffff); 2608 ipcsum = in_addword(csum1, ~csum2 & 0xffff); 2609 /* checksum fixup for IP options */ 2610 len = hlen - sizeof(struct ip); 2611 if (len > 0) { 2612 /* 2613 * If the second checksum value is correct we can compute IP 2614 * checksum with simple math. Unfortunately the second checksum 2615 * value is wrong so we can't verify the checksum from the 2616 * value(It seems there is some magic here to get correct 2617 * value). If the second checksum value is correct it also 2618 * means we can get TCP/UDP checksum) here. However, it still 2619 * needs pseudo header checksum calculation due to hardware 2620 * limitations. 2621 */ 2622 return; 2623 } 2624 m->m_pkthdr.csum_flags = CSUM_IP_CHECKED; 2625 if (ipcsum == 0xffff) 2626 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2627 } 2628 2629 static __inline int 2630 sk_rxvalid(struct sk_softc *sc, u_int32_t stat, u_int32_t len) 2631 { 2632 2633 if (sc->sk_type == SK_GENESIS) { 2634 if ((stat & XM_RXSTAT_ERRFRAME) == XM_RXSTAT_ERRFRAME || 2635 XM_RXSTAT_BYTES(stat) != len) 2636 return (0); 2637 } else { 2638 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR | 2639 YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | 2640 YU_RXSTAT_JABBER)) != 0 || 2641 (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK || 2642 YU_RXSTAT_BYTES(stat) != len) 2643 return (0); 2644 } 2645 2646 return (1); 2647 } 2648 2649 static void 2650 sk_rxeof(struct sk_if_softc *sc_if) 2651 { 2652 struct sk_softc *sc; 2653 struct mbuf *m; 2654 if_t ifp; 2655 struct sk_rx_desc *cur_rx; 2656 struct sk_rxdesc *rxd; 2657 int cons, prog; 2658 u_int32_t csum, rxstat, sk_ctl; 2659 2660 sc = sc_if->sk_softc; 2661 ifp = sc_if->sk_ifp; 2662 2663 SK_IF_LOCK_ASSERT(sc_if); 2664 2665 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag, 2666 sc_if->sk_cdata.sk_rx_ring_map, BUS_DMASYNC_POSTREAD); 2667 2668 prog = 0; 2669 for (cons = sc_if->sk_cdata.sk_rx_cons; prog < SK_RX_RING_CNT; 2670 prog++, SK_INC(cons, SK_RX_RING_CNT)) { 2671 cur_rx = &sc_if->sk_rdata.sk_rx_ring[cons]; 2672 sk_ctl = le32toh(cur_rx->sk_ctl); 2673 if ((sk_ctl & SK_RXCTL_OWN) != 0) 2674 break; 2675 rxd = &sc_if->sk_cdata.sk_rxdesc[cons]; 2676 rxstat = le32toh(cur_rx->sk_xmac_rxstat); 2677 2678 if ((sk_ctl & (SK_RXCTL_STATUS_VALID | SK_RXCTL_FIRSTFRAG | 2679 SK_RXCTL_LASTFRAG)) != (SK_RXCTL_STATUS_VALID | 2680 SK_RXCTL_FIRSTFRAG | SK_RXCTL_LASTFRAG) || 2681 SK_RXBYTES(sk_ctl) < SK_MIN_FRAMELEN || 2682 SK_RXBYTES(sk_ctl) > SK_MAX_FRAMELEN || 2683 sk_rxvalid(sc, rxstat, SK_RXBYTES(sk_ctl)) == 0) { 2684 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2685 sk_discard_rxbuf(sc_if, cons); 2686 continue; 2687 } 2688 2689 m = rxd->rx_m; 2690 csum = le32toh(cur_rx->sk_csum); 2691 if (sk_newbuf(sc_if, cons) != 0) { 2692 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2693 /* reuse old buffer */ 2694 sk_discard_rxbuf(sc_if, cons); 2695 continue; 2696 } 2697 m->m_pkthdr.rcvif = ifp; 2698 m->m_pkthdr.len = m->m_len = SK_RXBYTES(sk_ctl); 2699 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 2700 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) 2701 sk_rxcksum(ifp, m, csum); 2702 SK_IF_UNLOCK(sc_if); 2703 if_input(ifp, m); 2704 SK_IF_LOCK(sc_if); 2705 } 2706 2707 if (prog > 0) { 2708 sc_if->sk_cdata.sk_rx_cons = cons; 2709 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag, 2710 sc_if->sk_cdata.sk_rx_ring_map, 2711 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2712 } 2713 } 2714 2715 static void 2716 sk_jumbo_rxeof(struct sk_if_softc *sc_if) 2717 { 2718 struct sk_softc *sc; 2719 struct mbuf *m; 2720 if_t ifp; 2721 struct sk_rx_desc *cur_rx; 2722 struct sk_rxdesc *jrxd; 2723 int cons, prog; 2724 u_int32_t csum, rxstat, sk_ctl; 2725 2726 sc = sc_if->sk_softc; 2727 ifp = sc_if->sk_ifp; 2728 2729 SK_IF_LOCK_ASSERT(sc_if); 2730 2731 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 2732 sc_if->sk_cdata.sk_jumbo_rx_ring_map, BUS_DMASYNC_POSTREAD); 2733 2734 prog = 0; 2735 for (cons = sc_if->sk_cdata.sk_jumbo_rx_cons; 2736 prog < SK_JUMBO_RX_RING_CNT; 2737 prog++, SK_INC(cons, SK_JUMBO_RX_RING_CNT)) { 2738 cur_rx = &sc_if->sk_rdata.sk_jumbo_rx_ring[cons]; 2739 sk_ctl = le32toh(cur_rx->sk_ctl); 2740 if ((sk_ctl & SK_RXCTL_OWN) != 0) 2741 break; 2742 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[cons]; 2743 rxstat = le32toh(cur_rx->sk_xmac_rxstat); 2744 2745 if ((sk_ctl & (SK_RXCTL_STATUS_VALID | SK_RXCTL_FIRSTFRAG | 2746 SK_RXCTL_LASTFRAG)) != (SK_RXCTL_STATUS_VALID | 2747 SK_RXCTL_FIRSTFRAG | SK_RXCTL_LASTFRAG) || 2748 SK_RXBYTES(sk_ctl) < SK_MIN_FRAMELEN || 2749 SK_RXBYTES(sk_ctl) > SK_JUMBO_FRAMELEN || 2750 sk_rxvalid(sc, rxstat, SK_RXBYTES(sk_ctl)) == 0) { 2751 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2752 sk_discard_jumbo_rxbuf(sc_if, cons); 2753 continue; 2754 } 2755 2756 m = jrxd->rx_m; 2757 csum = le32toh(cur_rx->sk_csum); 2758 if (sk_jumbo_newbuf(sc_if, cons) != 0) { 2759 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2760 /* reuse old buffer */ 2761 sk_discard_jumbo_rxbuf(sc_if, cons); 2762 continue; 2763 } 2764 m->m_pkthdr.rcvif = ifp; 2765 m->m_pkthdr.len = m->m_len = SK_RXBYTES(sk_ctl); 2766 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 2767 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) 2768 sk_rxcksum(ifp, m, csum); 2769 SK_IF_UNLOCK(sc_if); 2770 if_input(ifp, m); 2771 SK_IF_LOCK(sc_if); 2772 } 2773 2774 if (prog > 0) { 2775 sc_if->sk_cdata.sk_jumbo_rx_cons = cons; 2776 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 2777 sc_if->sk_cdata.sk_jumbo_rx_ring_map, 2778 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2779 } 2780 } 2781 2782 static void 2783 sk_txeof(struct sk_if_softc *sc_if) 2784 { 2785 struct sk_txdesc *txd; 2786 struct sk_tx_desc *cur_tx; 2787 if_t ifp; 2788 u_int32_t idx, sk_ctl; 2789 2790 ifp = sc_if->sk_ifp; 2791 2792 txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txbusyq); 2793 if (txd == NULL) 2794 return; 2795 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag, 2796 sc_if->sk_cdata.sk_tx_ring_map, BUS_DMASYNC_POSTREAD); 2797 /* 2798 * Go through our tx ring and free mbufs for those 2799 * frames that have been sent. 2800 */ 2801 for (idx = sc_if->sk_cdata.sk_tx_cons;; SK_INC(idx, SK_TX_RING_CNT)) { 2802 if (sc_if->sk_cdata.sk_tx_cnt <= 0) 2803 break; 2804 cur_tx = &sc_if->sk_rdata.sk_tx_ring[idx]; 2805 sk_ctl = le32toh(cur_tx->sk_ctl); 2806 if (sk_ctl & SK_TXCTL_OWN) 2807 break; 2808 sc_if->sk_cdata.sk_tx_cnt--; 2809 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 2810 if ((sk_ctl & SK_TXCTL_LASTFRAG) == 0) 2811 continue; 2812 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap, 2813 BUS_DMASYNC_POSTWRITE); 2814 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap); 2815 2816 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 2817 m_freem(txd->tx_m); 2818 txd->tx_m = NULL; 2819 STAILQ_REMOVE_HEAD(&sc_if->sk_cdata.sk_txbusyq, tx_q); 2820 STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txfreeq, txd, tx_q); 2821 txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txbusyq); 2822 } 2823 sc_if->sk_cdata.sk_tx_cons = idx; 2824 sc_if->sk_watchdog_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0; 2825 2826 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag, 2827 sc_if->sk_cdata.sk_tx_ring_map, 2828 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2829 } 2830 2831 static void 2832 sk_tick(void *xsc_if) 2833 { 2834 struct sk_if_softc *sc_if; 2835 struct mii_data *mii; 2836 if_t ifp; 2837 int i; 2838 2839 sc_if = xsc_if; 2840 ifp = sc_if->sk_ifp; 2841 mii = device_get_softc(sc_if->sk_miibus); 2842 2843 if (!(if_getflags(ifp) & IFF_UP)) 2844 return; 2845 2846 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2847 sk_intr_bcom(sc_if); 2848 return; 2849 } 2850 2851 /* 2852 * According to SysKonnect, the correct way to verify that 2853 * the link has come back up is to poll bit 0 of the GPIO 2854 * register three times. This pin has the signal from the 2855 * link_sync pin connected to it; if we read the same link 2856 * state 3 times in a row, we know the link is up. 2857 */ 2858 for (i = 0; i < 3; i++) { 2859 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 2860 break; 2861 } 2862 2863 if (i != 3) { 2864 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2865 return; 2866 } 2867 2868 /* Turn the GP0 interrupt back on. */ 2869 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2870 SK_XM_READ_2(sc_if, XM_ISR); 2871 mii_tick(mii); 2872 callout_stop(&sc_if->sk_tick_ch); 2873 } 2874 2875 static void 2876 sk_yukon_tick(void *xsc_if) 2877 { 2878 struct sk_if_softc *sc_if; 2879 struct mii_data *mii; 2880 2881 sc_if = xsc_if; 2882 mii = device_get_softc(sc_if->sk_miibus); 2883 2884 mii_tick(mii); 2885 callout_reset(&sc_if->sk_tick_ch, hz, sk_yukon_tick, sc_if); 2886 } 2887 2888 static void 2889 sk_intr_bcom(struct sk_if_softc *sc_if) 2890 { 2891 struct mii_data *mii; 2892 if_t ifp; 2893 int status; 2894 mii = device_get_softc(sc_if->sk_miibus); 2895 ifp = sc_if->sk_ifp; 2896 2897 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2898 2899 /* 2900 * Read the PHY interrupt register to make sure 2901 * we clear any pending interrupts. 2902 */ 2903 status = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 2904 2905 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) { 2906 sk_init_xmac(sc_if); 2907 return; 2908 } 2909 2910 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 2911 int lstat; 2912 lstat = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 2913 BRGPHY_MII_AUXSTS); 2914 2915 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 2916 mii_mediachg(mii); 2917 /* Turn off the link LED. */ 2918 SK_IF_WRITE_1(sc_if, 0, 2919 SK_LINKLED1_CTL, SK_LINKLED_OFF); 2920 sc_if->sk_link = 0; 2921 } else if (status & BRGPHY_ISR_LNK_CHG) { 2922 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 2923 BRGPHY_MII_IMR, 0xFF00); 2924 mii_tick(mii); 2925 sc_if->sk_link = 1; 2926 /* Turn on the link LED. */ 2927 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2928 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 2929 SK_LINKLED_BLINK_OFF); 2930 } else { 2931 mii_tick(mii); 2932 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2933 } 2934 } 2935 2936 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2937 2938 return; 2939 } 2940 2941 static void 2942 sk_intr_xmac(struct sk_if_softc *sc_if) 2943 { 2944 u_int16_t status; 2945 2946 status = SK_XM_READ_2(sc_if, XM_ISR); 2947 2948 /* 2949 * Link has gone down. Start MII tick timeout to 2950 * watch for link resync. 2951 */ 2952 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 2953 if (status & XM_ISR_GP0_SET) { 2954 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2955 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2956 } 2957 2958 if (status & XM_ISR_AUTONEG_DONE) { 2959 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2960 } 2961 } 2962 2963 if (status & XM_IMR_TX_UNDERRUN) 2964 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 2965 2966 if (status & XM_IMR_RX_OVERRUN) 2967 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 2968 2969 status = SK_XM_READ_2(sc_if, XM_ISR); 2970 2971 return; 2972 } 2973 2974 static void 2975 sk_intr_yukon(struct sk_if_softc *sc_if) 2976 { 2977 u_int8_t status; 2978 2979 status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR); 2980 /* RX overrun */ 2981 if ((status & SK_GMAC_INT_RX_OVER) != 0) { 2982 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 2983 SK_RFCTL_RX_FIFO_OVER); 2984 } 2985 /* TX underrun */ 2986 if ((status & SK_GMAC_INT_TX_UNDER) != 0) { 2987 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 2988 SK_TFCTL_TX_FIFO_UNDER); 2989 } 2990 } 2991 2992 static void 2993 sk_intr(void *xsc) 2994 { 2995 struct sk_softc *sc = xsc; 2996 struct sk_if_softc *sc_if0, *sc_if1; 2997 if_t ifp0 = NULL, ifp1 = NULL; 2998 u_int32_t status; 2999 3000 SK_LOCK(sc); 3001 3002 status = CSR_READ_4(sc, SK_ISSR); 3003 if (status == 0 || status == 0xffffffff || sc->sk_suspended) 3004 goto done_locked; 3005 3006 sc_if0 = sc->sk_if[SK_PORT_A]; 3007 sc_if1 = sc->sk_if[SK_PORT_B]; 3008 3009 if (sc_if0 != NULL) 3010 ifp0 = sc_if0->sk_ifp; 3011 if (sc_if1 != NULL) 3012 ifp1 = sc_if1->sk_ifp; 3013 3014 for (; (status &= sc->sk_intrmask) != 0;) { 3015 /* Handle receive interrupts first. */ 3016 if (status & SK_ISR_RX1_EOF) { 3017 if (if_getmtu(ifp0) > SK_MAX_FRAMELEN) 3018 sk_jumbo_rxeof(sc_if0); 3019 else 3020 sk_rxeof(sc_if0); 3021 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 3022 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 3023 } 3024 if (status & SK_ISR_RX2_EOF) { 3025 if (if_getflags(ifp1) > SK_MAX_FRAMELEN) 3026 sk_jumbo_rxeof(sc_if1); 3027 else 3028 sk_rxeof(sc_if1); 3029 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 3030 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 3031 } 3032 3033 /* Then transmit interrupts. */ 3034 if (status & SK_ISR_TX1_S_EOF) { 3035 sk_txeof(sc_if0); 3036 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, SK_TXBMU_CLR_IRQ_EOF); 3037 } 3038 if (status & SK_ISR_TX2_S_EOF) { 3039 sk_txeof(sc_if1); 3040 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, SK_TXBMU_CLR_IRQ_EOF); 3041 } 3042 3043 /* Then MAC interrupts. */ 3044 if (status & SK_ISR_MAC1 && 3045 if_getdrvflags(ifp0) & IFF_DRV_RUNNING) { 3046 if (sc->sk_type == SK_GENESIS) 3047 sk_intr_xmac(sc_if0); 3048 else 3049 sk_intr_yukon(sc_if0); 3050 } 3051 3052 if (status & SK_ISR_MAC2 && 3053 if_getdrvflags(ifp1) & IFF_DRV_RUNNING) { 3054 if (sc->sk_type == SK_GENESIS) 3055 sk_intr_xmac(sc_if1); 3056 else 3057 sk_intr_yukon(sc_if1); 3058 } 3059 3060 if (status & SK_ISR_EXTERNAL_REG) { 3061 if (ifp0 != NULL && 3062 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 3063 sk_intr_bcom(sc_if0); 3064 if (ifp1 != NULL && 3065 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 3066 sk_intr_bcom(sc_if1); 3067 } 3068 status = CSR_READ_4(sc, SK_ISSR); 3069 } 3070 3071 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 3072 3073 if (ifp0 != NULL && !if_sendq_empty(ifp0)) 3074 sk_start_locked(ifp0); 3075 if (ifp1 != NULL && !if_sendq_empty(ifp1)) 3076 sk_start_locked(ifp1); 3077 3078 done_locked: 3079 SK_UNLOCK(sc); 3080 } 3081 3082 static void 3083 sk_init_xmac(struct sk_if_softc *sc_if) 3084 { 3085 struct sk_softc *sc; 3086 if_t ifp; 3087 u_int16_t eaddr[(ETHER_ADDR_LEN+1)/2]; 3088 static const struct sk_bcom_hack bhack[] = { 3089 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 3090 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 3091 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 3092 { 0, 0 } }; 3093 3094 SK_IF_LOCK_ASSERT(sc_if); 3095 3096 sc = sc_if->sk_softc; 3097 ifp = sc_if->sk_ifp; 3098 3099 /* Unreset the XMAC. */ 3100 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 3101 DELAY(1000); 3102 3103 /* Reset the XMAC's internal state. */ 3104 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 3105 3106 /* Save the XMAC II revision */ 3107 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 3108 3109 /* 3110 * Perform additional initialization for external PHYs, 3111 * namely for the 1000baseTX cards that use the XMAC's 3112 * GMII mode. 3113 */ 3114 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 3115 int i = 0; 3116 u_int32_t val; 3117 3118 /* Take PHY out of reset. */ 3119 val = sk_win_read_4(sc, SK_GPIO); 3120 if (sc_if->sk_port == SK_PORT_A) 3121 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 3122 else 3123 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 3124 sk_win_write_4(sc, SK_GPIO, val); 3125 3126 /* Enable GMII mode on the XMAC. */ 3127 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 3128 3129 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 3130 BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET); 3131 DELAY(10000); 3132 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 3133 BRGPHY_MII_IMR, 0xFFF0); 3134 3135 /* 3136 * Early versions of the BCM5400 apparently have 3137 * a bug that requires them to have their reserved 3138 * registers initialized to some magic values. I don't 3139 * know what the numbers do, I'm just the messenger. 3140 */ 3141 if (sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 0x03) 3142 == 0x6041) { 3143 while(bhack[i].reg) { 3144 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 3145 bhack[i].reg, bhack[i].val); 3146 i++; 3147 } 3148 } 3149 } 3150 3151 /* Set station address */ 3152 bcopy(if_getlladdr(sc_if->sk_ifp), eaddr, ETHER_ADDR_LEN); 3153 SK_XM_WRITE_2(sc_if, XM_PAR0, eaddr[0]); 3154 SK_XM_WRITE_2(sc_if, XM_PAR1, eaddr[1]); 3155 SK_XM_WRITE_2(sc_if, XM_PAR2, eaddr[2]); 3156 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 3157 3158 if (if_getflags(ifp) & IFF_BROADCAST) { 3159 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 3160 } else { 3161 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 3162 } 3163 3164 /* We don't need the FCS appended to the packet. */ 3165 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 3166 3167 /* We want short frames padded to 60 bytes. */ 3168 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 3169 3170 /* 3171 * Enable the reception of all error frames. This is is 3172 * a necessary evil due to the design of the XMAC. The 3173 * XMAC's receive FIFO is only 8K in size, however jumbo 3174 * frames can be up to 9000 bytes in length. When bad 3175 * frame filtering is enabled, the XMAC's RX FIFO operates 3176 * in 'store and forward' mode. For this to work, the 3177 * entire frame has to fit into the FIFO, but that means 3178 * that jumbo frames larger than 8192 bytes will be 3179 * truncated. Disabling all bad frame filtering causes 3180 * the RX FIFO to operate in streaming mode, in which 3181 * case the XMAC will start transferring frames out of the 3182 * RX FIFO as soon as the FIFO threshold is reached. 3183 */ 3184 if (if_getmtu(ifp) > SK_MAX_FRAMELEN) { 3185 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 3186 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 3187 XM_MODE_RX_INRANGELEN); 3188 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 3189 } else 3190 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 3191 3192 /* 3193 * Bump up the transmit threshold. This helps hold off transmit 3194 * underruns when we're blasting traffic from both ports at once. 3195 */ 3196 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 3197 3198 /* Set Rx filter */ 3199 sk_rxfilter_genesis(sc_if); 3200 3201 /* Clear and enable interrupts */ 3202 SK_XM_READ_2(sc_if, XM_ISR); 3203 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 3204 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 3205 else 3206 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 3207 3208 /* Configure MAC arbiter */ 3209 switch(sc_if->sk_xmac_rev) { 3210 case XM_XMAC_REV_B2: 3211 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 3212 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 3213 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 3214 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 3215 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 3216 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 3217 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 3218 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 3219 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 3220 break; 3221 case XM_XMAC_REV_C1: 3222 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 3223 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 3224 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 3225 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 3226 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 3227 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 3228 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 3229 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 3230 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 3231 break; 3232 default: 3233 break; 3234 } 3235 sk_win_write_2(sc, SK_MACARB_CTL, 3236 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 3237 3238 sc_if->sk_link = 1; 3239 3240 return; 3241 } 3242 3243 static void 3244 sk_init_yukon(struct sk_if_softc *sc_if) 3245 { 3246 u_int32_t phy, v; 3247 u_int16_t reg; 3248 struct sk_softc *sc; 3249 if_t ifp; 3250 u_int8_t *eaddr; 3251 int i; 3252 3253 SK_IF_LOCK_ASSERT(sc_if); 3254 3255 sc = sc_if->sk_softc; 3256 ifp = sc_if->sk_ifp; 3257 3258 if (sc->sk_type == SK_YUKON_LITE && 3259 sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 3260 /* 3261 * Workaround code for COMA mode, set PHY reset. 3262 * Otherwise it will not correctly take chip out of 3263 * powerdown (coma) 3264 */ 3265 v = sk_win_read_4(sc, SK_GPIO); 3266 v |= SK_GPIO_DIR9 | SK_GPIO_DAT9; 3267 sk_win_write_4(sc, SK_GPIO, v); 3268 } 3269 3270 /* GMAC and GPHY Reset */ 3271 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 3272 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 3273 DELAY(1000); 3274 3275 if (sc->sk_type == SK_YUKON_LITE && 3276 sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 3277 /* 3278 * Workaround code for COMA mode, clear PHY reset 3279 */ 3280 v = sk_win_read_4(sc, SK_GPIO); 3281 v |= SK_GPIO_DIR9; 3282 v &= ~SK_GPIO_DAT9; 3283 sk_win_write_4(sc, SK_GPIO, v); 3284 } 3285 3286 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 3287 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 3288 3289 if (sc->sk_coppertype) 3290 phy |= SK_GPHY_COPPER; 3291 else 3292 phy |= SK_GPHY_FIBER; 3293 3294 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 3295 DELAY(1000); 3296 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 3297 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 3298 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 3299 3300 /* unused read of the interrupt source register */ 3301 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 3302 3303 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 3304 3305 /* MIB Counter Clear Mode set */ 3306 reg |= YU_PAR_MIB_CLR; 3307 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 3308 3309 /* MIB Counter Clear Mode clear */ 3310 reg &= ~YU_PAR_MIB_CLR; 3311 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 3312 3313 /* receive control reg */ 3314 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR); 3315 3316 /* transmit parameter register */ 3317 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 3318 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 3319 3320 /* serial mode register */ 3321 reg = YU_SMR_DATA_BLIND(0x1c) | YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e); 3322 if (if_getmtu(ifp) > SK_MAX_FRAMELEN) 3323 reg |= YU_SMR_MFL_JUMBO; 3324 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg); 3325 3326 /* Setup Yukon's station address */ 3327 eaddr = if_getlladdr(sc_if->sk_ifp); 3328 for (i = 0; i < 3; i++) 3329 SK_YU_WRITE_2(sc_if, SK_MAC0_0 + i * 4, 3330 eaddr[i * 2] | eaddr[i * 2 + 1] << 8); 3331 /* Set GMAC source address of flow control. */ 3332 for (i = 0; i < 3; i++) 3333 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 3334 eaddr[i * 2] | eaddr[i * 2 + 1] << 8); 3335 /* Set GMAC virtual address. */ 3336 for (i = 0; i < 3; i++) 3337 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, 3338 eaddr[i * 2] | eaddr[i * 2 + 1] << 8); 3339 3340 /* Set Rx filter */ 3341 sk_rxfilter_yukon(sc_if); 3342 3343 /* enable interrupt mask for counter overflows */ 3344 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 3345 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 3346 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 3347 3348 /* Configure RX MAC FIFO Flush Mask */ 3349 v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR | 3350 YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT | 3351 YU_RXSTAT_JABBER; 3352 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v); 3353 3354 /* Disable RX MAC FIFO Flush for YUKON-Lite Rev. A0 only */ 3355 if (sc->sk_type == SK_YUKON_LITE && sc->sk_rev == SK_YUKON_LITE_REV_A0) 3356 v = SK_TFCTL_OPERATION_ON; 3357 else 3358 v = SK_TFCTL_OPERATION_ON | SK_RFCTL_FIFO_FLUSH_ON; 3359 /* Configure RX MAC FIFO */ 3360 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 3361 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, v); 3362 3363 /* Increase flush threshould to 64 bytes */ 3364 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD, 3365 SK_RFCTL_FIFO_THRESHOLD + 1); 3366 3367 /* Configure TX MAC FIFO */ 3368 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 3369 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 3370 } 3371 3372 /* 3373 * Note that to properly initialize any part of the GEnesis chip, 3374 * you first have to take it out of reset mode. 3375 */ 3376 static void 3377 sk_init(void *xsc) 3378 { 3379 struct sk_if_softc *sc_if = xsc; 3380 3381 SK_IF_LOCK(sc_if); 3382 sk_init_locked(sc_if); 3383 SK_IF_UNLOCK(sc_if); 3384 3385 return; 3386 } 3387 3388 static void 3389 sk_init_locked(struct sk_if_softc *sc_if) 3390 { 3391 struct sk_softc *sc; 3392 if_t ifp; 3393 struct mii_data *mii; 3394 u_int16_t reg; 3395 u_int32_t imr; 3396 int error; 3397 3398 SK_IF_LOCK_ASSERT(sc_if); 3399 3400 ifp = sc_if->sk_ifp; 3401 sc = sc_if->sk_softc; 3402 mii = device_get_softc(sc_if->sk_miibus); 3403 3404 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 3405 return; 3406 3407 /* Cancel pending I/O and free all RX/TX buffers. */ 3408 sk_stop(sc_if); 3409 3410 if (sc->sk_type == SK_GENESIS) { 3411 /* Configure LINK_SYNC LED */ 3412 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 3413 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 3414 SK_LINKLED_LINKSYNC_ON); 3415 3416 /* Configure RX LED */ 3417 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 3418 SK_RXLEDCTL_COUNTER_START); 3419 3420 /* Configure TX LED */ 3421 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 3422 SK_TXLEDCTL_COUNTER_START); 3423 } 3424 3425 /* 3426 * Configure descriptor poll timer 3427 * 3428 * SK-NET GENESIS data sheet says that possibility of losing Start 3429 * transmit command due to CPU/cache related interim storage problems 3430 * under certain conditions. The document recommends a polling 3431 * mechanism to send a Start transmit command to initiate transfer 3432 * of ready descriptors regulary. To cope with this issue sk(4) now 3433 * enables descriptor poll timer to initiate descriptor processing 3434 * periodically as defined by SK_DPT_TIMER_MAX. However sk(4) still 3435 * issue SK_TXBMU_TX_START to Tx BMU to get fast execution of Tx 3436 * command instead of waiting for next descriptor polling time. 3437 * The same rule may apply to Rx side too but it seems that is not 3438 * needed at the moment. 3439 * Since sk(4) uses descriptor polling as a last resort there is no 3440 * need to set smaller polling time than maximum allowable one. 3441 */ 3442 SK_IF_WRITE_4(sc_if, 0, SK_DPT_INIT, SK_DPT_TIMER_MAX); 3443 3444 /* Configure I2C registers */ 3445 3446 /* Configure XMAC(s) */ 3447 switch (sc->sk_type) { 3448 case SK_GENESIS: 3449 sk_init_xmac(sc_if); 3450 break; 3451 case SK_YUKON: 3452 case SK_YUKON_LITE: 3453 case SK_YUKON_LP: 3454 sk_init_yukon(sc_if); 3455 break; 3456 } 3457 mii_mediachg(mii); 3458 3459 if (sc->sk_type == SK_GENESIS) { 3460 /* Configure MAC FIFOs */ 3461 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 3462 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 3463 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 3464 3465 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 3466 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 3467 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 3468 } 3469 3470 /* Configure transmit arbiter(s) */ 3471 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 3472 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 3473 3474 /* Configure RAMbuffers */ 3475 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 3476 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 3477 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 3478 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 3479 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 3480 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 3481 3482 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 3483 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 3484 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 3485 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 3486 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 3487 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 3488 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 3489 3490 /* Configure BMUs */ 3491 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 3492 if (if_getmtu(ifp) > SK_MAX_FRAMELEN) { 3493 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 3494 SK_ADDR_LO(SK_JUMBO_RX_RING_ADDR(sc_if, 0))); 3495 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 3496 SK_ADDR_HI(SK_JUMBO_RX_RING_ADDR(sc_if, 0))); 3497 } else { 3498 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 3499 SK_ADDR_LO(SK_RX_RING_ADDR(sc_if, 0))); 3500 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 3501 SK_ADDR_HI(SK_RX_RING_ADDR(sc_if, 0))); 3502 } 3503 3504 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 3505 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 3506 SK_ADDR_LO(SK_TX_RING_ADDR(sc_if, 0))); 3507 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 3508 SK_ADDR_HI(SK_TX_RING_ADDR(sc_if, 0))); 3509 3510 /* Init descriptors */ 3511 if (if_getmtu(ifp) > SK_MAX_FRAMELEN) 3512 error = sk_init_jumbo_rx_ring(sc_if); 3513 else 3514 error = sk_init_rx_ring(sc_if); 3515 if (error != 0) { 3516 device_printf(sc_if->sk_if_dev, 3517 "initialization failed: no memory for rx buffers\n"); 3518 sk_stop(sc_if); 3519 return; 3520 } 3521 sk_init_tx_ring(sc_if); 3522 3523 /* Set interrupt moderation if changed via sysctl. */ 3524 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 3525 if (imr != SK_IM_USECS(sc->sk_int_mod, sc->sk_int_ticks)) { 3526 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod, 3527 sc->sk_int_ticks)); 3528 if (bootverbose) 3529 device_printf(sc_if->sk_if_dev, 3530 "interrupt moderation is %d us.\n", 3531 sc->sk_int_mod); 3532 } 3533 3534 /* Configure interrupt handling */ 3535 CSR_READ_4(sc, SK_ISSR); 3536 if (sc_if->sk_port == SK_PORT_A) 3537 sc->sk_intrmask |= SK_INTRS1; 3538 else 3539 sc->sk_intrmask |= SK_INTRS2; 3540 3541 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 3542 3543 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 3544 3545 /* Start BMUs. */ 3546 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 3547 3548 switch(sc->sk_type) { 3549 case SK_GENESIS: 3550 /* Enable XMACs TX and RX state machines */ 3551 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 3552 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 3553 break; 3554 case SK_YUKON: 3555 case SK_YUKON_LITE: 3556 case SK_YUKON_LP: 3557 reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 3558 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 3559 #if 0 3560 /* XXX disable 100Mbps and full duplex mode? */ 3561 reg &= ~(YU_GPCR_SPEED | YU_GPCR_DPLX_DIS); 3562 #endif 3563 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 3564 } 3565 3566 /* Activate descriptor polling timer */ 3567 SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_START); 3568 /* start transfer of Tx descriptors */ 3569 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 3570 3571 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 3572 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 3573 3574 switch (sc->sk_type) { 3575 case SK_YUKON: 3576 case SK_YUKON_LITE: 3577 case SK_YUKON_LP: 3578 callout_reset(&sc_if->sk_tick_ch, hz, sk_yukon_tick, sc_if); 3579 break; 3580 } 3581 3582 callout_reset(&sc_if->sk_watchdog_ch, hz, sk_watchdog, ifp); 3583 3584 return; 3585 } 3586 3587 static void 3588 sk_stop(struct sk_if_softc *sc_if) 3589 { 3590 int i; 3591 struct sk_softc *sc; 3592 struct sk_txdesc *txd; 3593 struct sk_rxdesc *rxd; 3594 struct sk_rxdesc *jrxd; 3595 if_t ifp; 3596 u_int32_t val; 3597 3598 SK_IF_LOCK_ASSERT(sc_if); 3599 sc = sc_if->sk_softc; 3600 ifp = sc_if->sk_ifp; 3601 3602 callout_stop(&sc_if->sk_tick_ch); 3603 callout_stop(&sc_if->sk_watchdog_ch); 3604 3605 /* stop Tx descriptor polling timer */ 3606 SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP); 3607 /* stop transfer of Tx descriptors */ 3608 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_STOP); 3609 for (i = 0; i < SK_TIMEOUT; i++) { 3610 val = CSR_READ_4(sc, sc_if->sk_tx_bmu); 3611 if ((val & SK_TXBMU_TX_STOP) == 0) 3612 break; 3613 DELAY(1); 3614 } 3615 if (i == SK_TIMEOUT) 3616 device_printf(sc_if->sk_if_dev, 3617 "can not stop transfer of Tx descriptor\n"); 3618 /* stop transfer of Rx descriptors */ 3619 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_STOP); 3620 for (i = 0; i < SK_TIMEOUT; i++) { 3621 val = SK_IF_READ_4(sc_if, 0, SK_RXQ1_BMU_CSR); 3622 if ((val & SK_RXBMU_RX_STOP) == 0) 3623 break; 3624 DELAY(1); 3625 } 3626 if (i == SK_TIMEOUT) 3627 device_printf(sc_if->sk_if_dev, 3628 "can not stop transfer of Rx descriptor\n"); 3629 3630 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 3631 /* Put PHY back into reset. */ 3632 val = sk_win_read_4(sc, SK_GPIO); 3633 if (sc_if->sk_port == SK_PORT_A) { 3634 val |= SK_GPIO_DIR0; 3635 val &= ~SK_GPIO_DAT0; 3636 } else { 3637 val |= SK_GPIO_DIR2; 3638 val &= ~SK_GPIO_DAT2; 3639 } 3640 sk_win_write_4(sc, SK_GPIO, val); 3641 } 3642 3643 /* Turn off various components of this interface. */ 3644 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 3645 switch (sc->sk_type) { 3646 case SK_GENESIS: 3647 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_RESET); 3648 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 3649 break; 3650 case SK_YUKON: 3651 case SK_YUKON_LITE: 3652 case SK_YUKON_LP: 3653 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 3654 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 3655 break; 3656 } 3657 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 3658 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 3659 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 3660 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 3661 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 3662 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 3663 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 3664 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 3665 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 3666 3667 /* Disable interrupts */ 3668 if (sc_if->sk_port == SK_PORT_A) 3669 sc->sk_intrmask &= ~SK_INTRS1; 3670 else 3671 sc->sk_intrmask &= ~SK_INTRS2; 3672 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 3673 3674 SK_XM_READ_2(sc_if, XM_ISR); 3675 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 3676 3677 /* Free RX and TX mbufs still in the queues. */ 3678 for (i = 0; i < SK_RX_RING_CNT; i++) { 3679 rxd = &sc_if->sk_cdata.sk_rxdesc[i]; 3680 if (rxd->rx_m != NULL) { 3681 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag, 3682 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3683 bus_dmamap_unload(sc_if->sk_cdata.sk_rx_tag, 3684 rxd->rx_dmamap); 3685 m_freem(rxd->rx_m); 3686 rxd->rx_m = NULL; 3687 } 3688 } 3689 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) { 3690 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i]; 3691 if (jrxd->rx_m != NULL) { 3692 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag, 3693 jrxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3694 bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_tag, 3695 jrxd->rx_dmamap); 3696 m_freem(jrxd->rx_m); 3697 jrxd->rx_m = NULL; 3698 } 3699 } 3700 for (i = 0; i < SK_TX_RING_CNT; i++) { 3701 txd = &sc_if->sk_cdata.sk_txdesc[i]; 3702 if (txd->tx_m != NULL) { 3703 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag, 3704 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 3705 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag, 3706 txd->tx_dmamap); 3707 m_freem(txd->tx_m); 3708 txd->tx_m = NULL; 3709 } 3710 } 3711 3712 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING|IFF_DRV_OACTIVE)); 3713 3714 return; 3715 } 3716 3717 static int 3718 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3719 { 3720 int error, value; 3721 3722 if (!arg1) 3723 return (EINVAL); 3724 value = *(int *)arg1; 3725 error = sysctl_handle_int(oidp, &value, 0, req); 3726 if (error || !req->newptr) 3727 return (error); 3728 if (value < low || value > high) 3729 return (EINVAL); 3730 *(int *)arg1 = value; 3731 return (0); 3732 } 3733 3734 static int 3735 sysctl_hw_sk_int_mod(SYSCTL_HANDLER_ARGS) 3736 { 3737 return (sysctl_int_range(oidp, arg1, arg2, req, SK_IM_MIN, SK_IM_MAX)); 3738 } 3739