1 /* $OpenBSD: if_sk.c,v 2.33 2003/08/12 05:23:06 nate Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998, 1999, 2000 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 /* 35 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 36 * 37 * Permission to use, copy, modify, and distribute this software for any 38 * purpose with or without fee is hereby granted, provided that the above 39 * copyright notice and this permission notice appear in all copies. 40 * 41 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 42 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 43 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 44 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 45 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 46 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 47 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 48 */ 49 50 #include <sys/cdefs.h> 51 __FBSDID("$FreeBSD$"); 52 53 /* 54 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 55 * the SK-984x series adapters, both single port and dual port. 56 * References: 57 * The XaQti XMAC II datasheet, 58 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 59 * The SysKonnect GEnesis manual, http://www.syskonnect.com 60 * 61 * Note: XaQti has been aquired by Vitesse, and Vitesse does not have the 62 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 63 * convenience to others until Vitesse corrects this problem: 64 * 65 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 66 * 67 * Written by Bill Paul <wpaul@ee.columbia.edu> 68 * Department of Electrical Engineering 69 * Columbia University, New York City 70 */ 71 /* 72 * The SysKonnect gigabit ethernet adapters consist of two main 73 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 74 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 75 * components and a PHY while the GEnesis controller provides a PCI 76 * interface with DMA support. Each card may have between 512K and 77 * 2MB of SRAM on board depending on the configuration. 78 * 79 * The SysKonnect GEnesis controller can have either one or two XMAC 80 * chips connected to it, allowing single or dual port NIC configurations. 81 * SysKonnect has the distinction of being the only vendor on the market 82 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 83 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 84 * XMAC registers. This driver takes advantage of these features to allow 85 * both XMACs to operate as independent interfaces. 86 */ 87 88 #include <sys/param.h> 89 #include <sys/systm.h> 90 #include <sys/sockio.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/module.h> 95 #include <sys/socket.h> 96 #include <sys/queue.h> 97 98 #include <net/if.h> 99 #include <net/if_arp.h> 100 #include <net/ethernet.h> 101 #include <net/if_dl.h> 102 #include <net/if_media.h> 103 104 #include <net/bpf.h> 105 106 #include <vm/vm.h> /* for vtophys */ 107 #include <vm/pmap.h> /* for vtophys */ 108 #include <machine/bus_pio.h> 109 #include <machine/bus_memio.h> 110 #include <machine/bus.h> 111 #include <machine/resource.h> 112 #include <sys/bus.h> 113 #include <sys/rman.h> 114 115 #include <dev/mii/mii.h> 116 #include <dev/mii/miivar.h> 117 #include <dev/mii/brgphyreg.h> 118 119 #include <dev/pci/pcireg.h> 120 #include <dev/pci/pcivar.h> 121 122 #if 0 123 #define SK_USEIOSPACE 124 #endif 125 126 #include <pci/if_skreg.h> 127 #include <pci/xmaciireg.h> 128 #include <pci/yukonreg.h> 129 130 MODULE_DEPEND(sk, pci, 1, 1, 1); 131 MODULE_DEPEND(sk, ether, 1, 1, 1); 132 MODULE_DEPEND(sk, miibus, 1, 1, 1); 133 134 /* "controller miibus0" required. See GENERIC if you get errors here. */ 135 #include "miibus_if.h" 136 137 #ifndef lint 138 static const char rcsid[] = 139 "$FreeBSD$"; 140 #endif 141 142 static struct sk_type sk_devs[] = { 143 { 144 VENDORID_SK, 145 DEVICEID_SK_V1, 146 "SysKonnect Gigabit Ethernet (V1.0)" 147 }, 148 { 149 VENDORID_SK, 150 DEVICEID_SK_V2, 151 "SysKonnect Gigabit Ethernet (V2.0)" 152 }, 153 { 154 VENDORID_MARVELL, 155 DEVICEID_SK_V2, 156 "Marvell Gigabit Ethernet" 157 }, 158 { 159 VENDORID_MARVELL, 160 DEVICEID_BELKIN_5005, 161 "Belkin F5D5005 Gigabit Ethernet" 162 }, 163 { 164 VENDORID_3COM, 165 DEVICEID_3COM_3C940, 166 "3Com 3C940 Gigabit Ethernet" 167 }, 168 { 169 VENDORID_LINKSYS, 170 DEVICEID_LINKSYS_EG1032, 171 "Linksys EG1032 Gigabit Ethernet" 172 }, 173 { 174 VENDORID_DLINK, 175 DEVICEID_DLINK_DGE530T, 176 "D-Link DGE-530T Gigabit Ethernet" 177 }, 178 { 0, 0, NULL } 179 }; 180 181 static int skc_probe (device_t); 182 static int skc_attach (device_t); 183 static int skc_detach (device_t); 184 static void skc_shutdown (device_t); 185 static int sk_detach (device_t); 186 static int sk_probe (device_t); 187 static int sk_attach (device_t); 188 static void sk_tick (void *); 189 static void sk_intr (void *); 190 static void sk_intr_xmac (struct sk_if_softc *); 191 static void sk_intr_bcom (struct sk_if_softc *); 192 static void sk_intr_yukon (struct sk_if_softc *); 193 static void sk_rxeof (struct sk_if_softc *); 194 static void sk_txeof (struct sk_if_softc *); 195 static int sk_encap (struct sk_if_softc *, struct mbuf *, 196 u_int32_t *); 197 static void sk_start (struct ifnet *); 198 static int sk_ioctl (struct ifnet *, u_long, caddr_t); 199 static void sk_init (void *); 200 static void sk_init_xmac (struct sk_if_softc *); 201 static void sk_init_yukon (struct sk_if_softc *); 202 static void sk_stop (struct sk_if_softc *); 203 static void sk_watchdog (struct ifnet *); 204 static int sk_ifmedia_upd (struct ifnet *); 205 static void sk_ifmedia_sts (struct ifnet *, struct ifmediareq *); 206 static void sk_reset (struct sk_softc *); 207 static int sk_newbuf (struct sk_if_softc *, 208 struct sk_chain *, struct mbuf *); 209 static int sk_alloc_jumbo_mem (struct sk_if_softc *); 210 static void *sk_jalloc (struct sk_if_softc *); 211 static void sk_jfree (void *, void *); 212 static int sk_init_rx_ring (struct sk_if_softc *); 213 static void sk_init_tx_ring (struct sk_if_softc *); 214 static u_int32_t sk_win_read_4 (struct sk_softc *, int); 215 static u_int16_t sk_win_read_2 (struct sk_softc *, int); 216 static u_int8_t sk_win_read_1 (struct sk_softc *, int); 217 static void sk_win_write_4 (struct sk_softc *, int, u_int32_t); 218 static void sk_win_write_2 (struct sk_softc *, int, u_int32_t); 219 static void sk_win_write_1 (struct sk_softc *, int, u_int32_t); 220 static u_int8_t sk_vpd_readbyte (struct sk_softc *, int); 221 static void sk_vpd_read_res (struct sk_softc *, struct vpd_res *, int); 222 static void sk_vpd_read (struct sk_softc *); 223 224 static int sk_miibus_readreg (device_t, int, int); 225 static int sk_miibus_writereg (device_t, int, int, int); 226 static void sk_miibus_statchg (device_t); 227 228 static int sk_xmac_miibus_readreg (struct sk_if_softc *, int, int); 229 static int sk_xmac_miibus_writereg (struct sk_if_softc *, int, int, 230 int); 231 static void sk_xmac_miibus_statchg (struct sk_if_softc *); 232 233 static int sk_marv_miibus_readreg (struct sk_if_softc *, int, int); 234 static int sk_marv_miibus_writereg (struct sk_if_softc *, int, int, 235 int); 236 static void sk_marv_miibus_statchg (struct sk_if_softc *); 237 238 static uint32_t sk_xmchash (const uint8_t *); 239 static uint32_t sk_gmchash (const uint8_t *); 240 static void sk_setfilt (struct sk_if_softc *, caddr_t, int); 241 static void sk_setmulti (struct sk_if_softc *); 242 static void sk_setpromisc (struct sk_if_softc *); 243 244 #ifdef SK_USEIOSPACE 245 #define SK_RES SYS_RES_IOPORT 246 #define SK_RID SK_PCI_LOIO 247 #else 248 #define SK_RES SYS_RES_MEMORY 249 #define SK_RID SK_PCI_LOMEM 250 #endif 251 252 /* 253 * Note that we have newbus methods for both the GEnesis controller 254 * itself and the XMAC(s). The XMACs are children of the GEnesis, and 255 * the miibus code is a child of the XMACs. We need to do it this way 256 * so that the miibus drivers can access the PHY registers on the 257 * right PHY. It's not quite what I had in mind, but it's the only 258 * design that achieves the desired effect. 259 */ 260 static device_method_t skc_methods[] = { 261 /* Device interface */ 262 DEVMETHOD(device_probe, skc_probe), 263 DEVMETHOD(device_attach, skc_attach), 264 DEVMETHOD(device_detach, skc_detach), 265 DEVMETHOD(device_shutdown, skc_shutdown), 266 267 /* bus interface */ 268 DEVMETHOD(bus_print_child, bus_generic_print_child), 269 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 270 271 { 0, 0 } 272 }; 273 274 static driver_t skc_driver = { 275 "skc", 276 skc_methods, 277 sizeof(struct sk_softc) 278 }; 279 280 static devclass_t skc_devclass; 281 282 static device_method_t sk_methods[] = { 283 /* Device interface */ 284 DEVMETHOD(device_probe, sk_probe), 285 DEVMETHOD(device_attach, sk_attach), 286 DEVMETHOD(device_detach, sk_detach), 287 DEVMETHOD(device_shutdown, bus_generic_shutdown), 288 289 /* bus interface */ 290 DEVMETHOD(bus_print_child, bus_generic_print_child), 291 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 292 293 /* MII interface */ 294 DEVMETHOD(miibus_readreg, sk_miibus_readreg), 295 DEVMETHOD(miibus_writereg, sk_miibus_writereg), 296 DEVMETHOD(miibus_statchg, sk_miibus_statchg), 297 298 { 0, 0 } 299 }; 300 301 static driver_t sk_driver = { 302 "sk", 303 sk_methods, 304 sizeof(struct sk_if_softc) 305 }; 306 307 static devclass_t sk_devclass; 308 309 DRIVER_MODULE(sk, pci, skc_driver, skc_devclass, 0, 0); 310 DRIVER_MODULE(sk, skc, sk_driver, sk_devclass, 0, 0); 311 DRIVER_MODULE(miibus, sk, miibus_driver, miibus_devclass, 0, 0); 312 313 #define SK_SETBIT(sc, reg, x) \ 314 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 315 316 #define SK_CLRBIT(sc, reg, x) \ 317 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 318 319 #define SK_WIN_SETBIT_4(sc, reg, x) \ 320 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x) 321 322 #define SK_WIN_CLRBIT_4(sc, reg, x) \ 323 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x) 324 325 #define SK_WIN_SETBIT_2(sc, reg, x) \ 326 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x) 327 328 #define SK_WIN_CLRBIT_2(sc, reg, x) \ 329 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x) 330 331 static u_int32_t 332 sk_win_read_4(sc, reg) 333 struct sk_softc *sc; 334 int reg; 335 { 336 #ifdef SK_USEIOSPACE 337 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 338 return(CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg))); 339 #else 340 return(CSR_READ_4(sc, reg)); 341 #endif 342 } 343 344 static u_int16_t 345 sk_win_read_2(sc, reg) 346 struct sk_softc *sc; 347 int reg; 348 { 349 #ifdef SK_USEIOSPACE 350 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 351 return(CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg))); 352 #else 353 return(CSR_READ_2(sc, reg)); 354 #endif 355 } 356 357 static u_int8_t 358 sk_win_read_1(sc, reg) 359 struct sk_softc *sc; 360 int reg; 361 { 362 #ifdef SK_USEIOSPACE 363 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 364 return(CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg))); 365 #else 366 return(CSR_READ_1(sc, reg)); 367 #endif 368 } 369 370 static void 371 sk_win_write_4(sc, reg, val) 372 struct sk_softc *sc; 373 int reg; 374 u_int32_t val; 375 { 376 #ifdef SK_USEIOSPACE 377 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 378 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), val); 379 #else 380 CSR_WRITE_4(sc, reg, val); 381 #endif 382 return; 383 } 384 385 static void 386 sk_win_write_2(sc, reg, val) 387 struct sk_softc *sc; 388 int reg; 389 u_int32_t val; 390 { 391 #ifdef SK_USEIOSPACE 392 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 393 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), val); 394 #else 395 CSR_WRITE_2(sc, reg, val); 396 #endif 397 return; 398 } 399 400 static void 401 sk_win_write_1(sc, reg, val) 402 struct sk_softc *sc; 403 int reg; 404 u_int32_t val; 405 { 406 #ifdef SK_USEIOSPACE 407 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 408 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), val); 409 #else 410 CSR_WRITE_1(sc, reg, val); 411 #endif 412 return; 413 } 414 415 /* 416 * The VPD EEPROM contains Vital Product Data, as suggested in 417 * the PCI 2.1 specification. The VPD data is separared into areas 418 * denoted by resource IDs. The SysKonnect VPD contains an ID string 419 * resource (the name of the adapter), a read-only area resource 420 * containing various key/data fields and a read/write area which 421 * can be used to store asset management information or log messages. 422 * We read the ID string and read-only into buffers attached to 423 * the controller softc structure for later use. At the moment, 424 * we only use the ID string during skc_attach(). 425 */ 426 static u_int8_t 427 sk_vpd_readbyte(sc, addr) 428 struct sk_softc *sc; 429 int addr; 430 { 431 int i; 432 433 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 434 for (i = 0; i < SK_TIMEOUT; i++) { 435 DELAY(1); 436 if (sk_win_read_2(sc, 437 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 438 break; 439 } 440 441 if (i == SK_TIMEOUT) 442 return(0); 443 444 return(sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA))); 445 } 446 447 static void 448 sk_vpd_read_res(sc, res, addr) 449 struct sk_softc *sc; 450 struct vpd_res *res; 451 int addr; 452 { 453 int i; 454 u_int8_t *ptr; 455 456 ptr = (u_int8_t *)res; 457 for (i = 0; i < sizeof(struct vpd_res); i++) 458 ptr[i] = sk_vpd_readbyte(sc, i + addr); 459 460 return; 461 } 462 463 static void 464 sk_vpd_read(sc) 465 struct sk_softc *sc; 466 { 467 int pos = 0, i; 468 struct vpd_res res; 469 470 if (sc->sk_vpd_prodname != NULL) 471 free(sc->sk_vpd_prodname, M_DEVBUF); 472 if (sc->sk_vpd_readonly != NULL) 473 free(sc->sk_vpd_readonly, M_DEVBUF); 474 sc->sk_vpd_prodname = NULL; 475 sc->sk_vpd_readonly = NULL; 476 sc->sk_vpd_readonly_len = 0; 477 478 sk_vpd_read_res(sc, &res, pos); 479 480 /* 481 * Bail out quietly if the eeprom appears to be missing or empty. 482 */ 483 if (res.vr_id == 0xff && res.vr_len == 0xff && res.vr_pad == 0xff) 484 return; 485 486 if (res.vr_id != VPD_RES_ID) { 487 printf("skc%d: bad VPD resource id: expected %x got %x\n", 488 sc->sk_unit, VPD_RES_ID, res.vr_id); 489 return; 490 } 491 492 pos += sizeof(res); 493 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 494 for (i = 0; i < res.vr_len; i++) 495 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 496 sc->sk_vpd_prodname[i] = '\0'; 497 pos += i; 498 499 sk_vpd_read_res(sc, &res, pos); 500 501 if (res.vr_id != VPD_RES_READ) { 502 printf("skc%d: bad VPD resource id: expected %x got %x\n", 503 sc->sk_unit, VPD_RES_READ, res.vr_id); 504 return; 505 } 506 507 pos += sizeof(res); 508 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 509 for (i = 0; i < res.vr_len; i++) 510 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 511 sc->sk_vpd_readonly_len = res.vr_len; 512 513 return; 514 } 515 516 static int 517 sk_miibus_readreg(dev, phy, reg) 518 device_t dev; 519 int phy, reg; 520 { 521 struct sk_if_softc *sc_if; 522 523 sc_if = device_get_softc(dev); 524 525 switch(sc_if->sk_softc->sk_type) { 526 case SK_GENESIS: 527 return(sk_xmac_miibus_readreg(sc_if, phy, reg)); 528 case SK_YUKON: 529 return(sk_marv_miibus_readreg(sc_if, phy, reg)); 530 } 531 532 return(0); 533 } 534 535 static int 536 sk_miibus_writereg(dev, phy, reg, val) 537 device_t dev; 538 int phy, reg, val; 539 { 540 struct sk_if_softc *sc_if; 541 542 sc_if = device_get_softc(dev); 543 544 switch(sc_if->sk_softc->sk_type) { 545 case SK_GENESIS: 546 return(sk_xmac_miibus_writereg(sc_if, phy, reg, val)); 547 case SK_YUKON: 548 return(sk_marv_miibus_writereg(sc_if, phy, reg, val)); 549 } 550 551 return(0); 552 } 553 554 static void 555 sk_miibus_statchg(dev) 556 device_t dev; 557 { 558 struct sk_if_softc *sc_if; 559 560 sc_if = device_get_softc(dev); 561 562 switch(sc_if->sk_softc->sk_type) { 563 case SK_GENESIS: 564 sk_xmac_miibus_statchg(sc_if); 565 break; 566 case SK_YUKON: 567 sk_marv_miibus_statchg(sc_if); 568 break; 569 } 570 571 return; 572 } 573 574 static int 575 sk_xmac_miibus_readreg(sc_if, phy, reg) 576 struct sk_if_softc *sc_if; 577 int phy, reg; 578 { 579 int i; 580 581 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 582 return(0); 583 584 SK_IF_LOCK(sc_if); 585 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 586 SK_XM_READ_2(sc_if, XM_PHY_DATA); 587 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 588 for (i = 0; i < SK_TIMEOUT; i++) { 589 DELAY(1); 590 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 591 XM_MMUCMD_PHYDATARDY) 592 break; 593 } 594 595 if (i == SK_TIMEOUT) { 596 printf("sk%d: phy failed to come ready\n", 597 sc_if->sk_unit); 598 SK_IF_UNLOCK(sc_if); 599 return(0); 600 } 601 } 602 DELAY(1); 603 i = SK_XM_READ_2(sc_if, XM_PHY_DATA); 604 SK_IF_UNLOCK(sc_if); 605 return(i); 606 } 607 608 static int 609 sk_xmac_miibus_writereg(sc_if, phy, reg, val) 610 struct sk_if_softc *sc_if; 611 int phy, reg, val; 612 { 613 int i; 614 615 SK_IF_LOCK(sc_if); 616 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 617 for (i = 0; i < SK_TIMEOUT; i++) { 618 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 619 break; 620 } 621 622 if (i == SK_TIMEOUT) { 623 printf("sk%d: phy failed to come ready\n", sc_if->sk_unit); 624 SK_IF_UNLOCK(sc_if); 625 return(ETIMEDOUT); 626 } 627 628 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 629 for (i = 0; i < SK_TIMEOUT; i++) { 630 DELAY(1); 631 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 632 break; 633 } 634 SK_IF_UNLOCK(sc_if); 635 if (i == SK_TIMEOUT) 636 printf("sk%d: phy write timed out\n", sc_if->sk_unit); 637 638 return(0); 639 } 640 641 static void 642 sk_xmac_miibus_statchg(sc_if) 643 struct sk_if_softc *sc_if; 644 { 645 struct mii_data *mii; 646 647 mii = device_get_softc(sc_if->sk_miibus); 648 649 SK_IF_LOCK(sc_if); 650 /* 651 * If this is a GMII PHY, manually set the XMAC's 652 * duplex mode accordingly. 653 */ 654 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 655 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 656 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 657 } else { 658 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 659 } 660 } 661 SK_IF_UNLOCK(sc_if); 662 663 return; 664 } 665 666 static int 667 sk_marv_miibus_readreg(sc_if, phy, reg) 668 struct sk_if_softc *sc_if; 669 int phy, reg; 670 { 671 u_int16_t val; 672 int i; 673 674 if (phy != 0 || 675 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 676 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 677 return(0); 678 } 679 680 SK_IF_LOCK(sc_if); 681 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 682 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 683 684 for (i = 0; i < SK_TIMEOUT; i++) { 685 DELAY(1); 686 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 687 if (val & YU_SMICR_READ_VALID) 688 break; 689 } 690 691 if (i == SK_TIMEOUT) { 692 printf("sk%d: phy failed to come ready\n", 693 sc_if->sk_unit); 694 SK_IF_UNLOCK(sc_if); 695 return(0); 696 } 697 698 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 699 SK_IF_UNLOCK(sc_if); 700 701 return(val); 702 } 703 704 static int 705 sk_marv_miibus_writereg(sc_if, phy, reg, val) 706 struct sk_if_softc *sc_if; 707 int phy, reg, val; 708 { 709 int i; 710 711 SK_IF_LOCK(sc_if); 712 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 713 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 714 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 715 716 for (i = 0; i < SK_TIMEOUT; i++) { 717 DELAY(1); 718 if (SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY) 719 break; 720 } 721 SK_IF_UNLOCK(sc_if); 722 723 return(0); 724 } 725 726 static void 727 sk_marv_miibus_statchg(sc_if) 728 struct sk_if_softc *sc_if; 729 { 730 return; 731 } 732 733 #define HASH_BITS 6 734 735 static u_int32_t 736 sk_xmchash(addr) 737 const uint8_t *addr; 738 { 739 uint32_t crc; 740 741 /* Compute CRC for the address value. */ 742 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 743 744 return (~crc & ((1 << HASH_BITS) - 1)); 745 } 746 747 /* gmchash is just a big endian crc */ 748 static u_int32_t 749 sk_gmchash(addr) 750 const uint8_t *addr; 751 { 752 uint32_t crc; 753 754 /* Compute CRC for the address value. */ 755 crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 756 757 return (crc & ((1 << HASH_BITS) - 1)); 758 } 759 760 static void 761 sk_setfilt(sc_if, addr, slot) 762 struct sk_if_softc *sc_if; 763 caddr_t addr; 764 int slot; 765 { 766 int base; 767 768 base = XM_RXFILT_ENTRY(slot); 769 770 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 771 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 772 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 773 774 return; 775 } 776 777 static void 778 sk_setmulti(sc_if) 779 struct sk_if_softc *sc_if; 780 { 781 struct sk_softc *sc = sc_if->sk_softc; 782 struct ifnet *ifp = &sc_if->arpcom.ac_if; 783 u_int32_t hashes[2] = { 0, 0 }; 784 int h = 0, i; 785 struct ifmultiaddr *ifma; 786 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 787 788 789 /* First, zot all the existing filters. */ 790 switch(sc->sk_type) { 791 case SK_GENESIS: 792 for (i = 1; i < XM_RXFILT_MAX; i++) 793 sk_setfilt(sc_if, (caddr_t)&dummy, i); 794 795 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 796 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 797 break; 798 case SK_YUKON: 799 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 800 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 801 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 802 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 803 break; 804 } 805 806 /* Now program new ones. */ 807 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 808 hashes[0] = 0xFFFFFFFF; 809 hashes[1] = 0xFFFFFFFF; 810 } else { 811 i = 1; 812 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, ifma_link) { 813 if (ifma->ifma_addr->sa_family != AF_LINK) 814 continue; 815 /* 816 * Program the first XM_RXFILT_MAX multicast groups 817 * into the perfect filter. For all others, 818 * use the hash table. 819 */ 820 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) { 821 sk_setfilt(sc_if, 822 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i); 823 i++; 824 continue; 825 } 826 827 switch(sc->sk_type) { 828 case SK_GENESIS: 829 h = sk_xmchash( 830 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 831 break; 832 case SK_YUKON: 833 h = sk_gmchash( 834 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 835 break; 836 } 837 if (h < 32) 838 hashes[0] |= (1 << h); 839 else 840 hashes[1] |= (1 << (h - 32)); 841 } 842 } 843 844 switch(sc->sk_type) { 845 case SK_GENESIS: 846 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 847 XM_MODE_RX_USE_PERFECT); 848 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 849 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 850 break; 851 case SK_YUKON: 852 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 853 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 854 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 855 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 856 break; 857 } 858 859 return; 860 } 861 862 static void 863 sk_setpromisc(sc_if) 864 struct sk_if_softc *sc_if; 865 { 866 struct sk_softc *sc = sc_if->sk_softc; 867 struct ifnet *ifp = &sc_if->arpcom.ac_if; 868 869 switch(sc->sk_type) { 870 case SK_GENESIS: 871 if (ifp->if_flags & IFF_PROMISC) { 872 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 873 } else { 874 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 875 } 876 break; 877 case SK_YUKON: 878 if (ifp->if_flags & IFF_PROMISC) { 879 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 880 YU_RCR_UFLEN | YU_RCR_MUFLEN); 881 } else { 882 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 883 YU_RCR_UFLEN | YU_RCR_MUFLEN); 884 } 885 break; 886 } 887 888 return; 889 } 890 891 static int 892 sk_init_rx_ring(sc_if) 893 struct sk_if_softc *sc_if; 894 { 895 struct sk_chain_data *cd = &sc_if->sk_cdata; 896 struct sk_ring_data *rd = sc_if->sk_rdata; 897 int i; 898 899 bzero((char *)rd->sk_rx_ring, 900 sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 901 902 for (i = 0; i < SK_RX_RING_CNT; i++) { 903 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 904 if (sk_newbuf(sc_if, &cd->sk_rx_chain[i], NULL) == ENOBUFS) 905 return(ENOBUFS); 906 if (i == (SK_RX_RING_CNT - 1)) { 907 cd->sk_rx_chain[i].sk_next = 908 &cd->sk_rx_chain[0]; 909 rd->sk_rx_ring[i].sk_next = 910 vtophys(&rd->sk_rx_ring[0]); 911 } else { 912 cd->sk_rx_chain[i].sk_next = 913 &cd->sk_rx_chain[i + 1]; 914 rd->sk_rx_ring[i].sk_next = 915 vtophys(&rd->sk_rx_ring[i + 1]); 916 } 917 } 918 919 sc_if->sk_cdata.sk_rx_prod = 0; 920 sc_if->sk_cdata.sk_rx_cons = 0; 921 922 return(0); 923 } 924 925 static void 926 sk_init_tx_ring(sc_if) 927 struct sk_if_softc *sc_if; 928 { 929 struct sk_chain_data *cd = &sc_if->sk_cdata; 930 struct sk_ring_data *rd = sc_if->sk_rdata; 931 int i; 932 933 bzero((char *)sc_if->sk_rdata->sk_tx_ring, 934 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 935 936 for (i = 0; i < SK_TX_RING_CNT; i++) { 937 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 938 if (i == (SK_TX_RING_CNT - 1)) { 939 cd->sk_tx_chain[i].sk_next = 940 &cd->sk_tx_chain[0]; 941 rd->sk_tx_ring[i].sk_next = 942 vtophys(&rd->sk_tx_ring[0]); 943 } else { 944 cd->sk_tx_chain[i].sk_next = 945 &cd->sk_tx_chain[i + 1]; 946 rd->sk_tx_ring[i].sk_next = 947 vtophys(&rd->sk_tx_ring[i + 1]); 948 } 949 } 950 951 sc_if->sk_cdata.sk_tx_prod = 0; 952 sc_if->sk_cdata.sk_tx_cons = 0; 953 sc_if->sk_cdata.sk_tx_cnt = 0; 954 955 return; 956 } 957 958 static int 959 sk_newbuf(sc_if, c, m) 960 struct sk_if_softc *sc_if; 961 struct sk_chain *c; 962 struct mbuf *m; 963 { 964 struct mbuf *m_new = NULL; 965 struct sk_rx_desc *r; 966 967 if (m == NULL) { 968 caddr_t *buf = NULL; 969 970 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 971 if (m_new == NULL) 972 return(ENOBUFS); 973 974 /* Allocate the jumbo buffer */ 975 buf = sk_jalloc(sc_if); 976 if (buf == NULL) { 977 m_freem(m_new); 978 #ifdef SK_VERBOSE 979 printf("sk%d: jumbo allocation failed " 980 "-- packet dropped!\n", sc_if->sk_unit); 981 #endif 982 return(ENOBUFS); 983 } 984 985 /* Attach the buffer to the mbuf */ 986 MEXTADD(m_new, buf, SK_JLEN, sk_jfree, 987 (struct sk_if_softc *)sc_if, 0, EXT_NET_DRV); 988 m_new->m_data = (void *)buf; 989 m_new->m_pkthdr.len = m_new->m_len = SK_JLEN; 990 } else { 991 /* 992 * We're re-using a previously allocated mbuf; 993 * be sure to re-init pointers and lengths to 994 * default values. 995 */ 996 m_new = m; 997 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 998 m_new->m_data = m_new->m_ext.ext_buf; 999 } 1000 1001 /* 1002 * Adjust alignment so packet payload begins on a 1003 * longword boundary. Mandatory for Alpha, useful on 1004 * x86 too. 1005 */ 1006 m_adj(m_new, ETHER_ALIGN); 1007 1008 r = c->sk_desc; 1009 c->sk_mbuf = m_new; 1010 r->sk_data_lo = vtophys(mtod(m_new, caddr_t)); 1011 r->sk_ctl = m_new->m_len | SK_RXSTAT; 1012 1013 return(0); 1014 } 1015 1016 /* 1017 * Allocate jumbo buffer storage. The SysKonnect adapters support 1018 * "jumbograms" (9K frames), although SysKonnect doesn't currently 1019 * use them in their drivers. In order for us to use them, we need 1020 * large 9K receive buffers, however standard mbuf clusters are only 1021 * 2048 bytes in size. Consequently, we need to allocate and manage 1022 * our own jumbo buffer pool. Fortunately, this does not require an 1023 * excessive amount of additional code. 1024 */ 1025 static int 1026 sk_alloc_jumbo_mem(sc_if) 1027 struct sk_if_softc *sc_if; 1028 { 1029 caddr_t ptr; 1030 register int i; 1031 struct sk_jpool_entry *entry; 1032 1033 /* Grab a big chunk o' storage. */ 1034 sc_if->sk_cdata.sk_jumbo_buf = contigmalloc(SK_JMEM, M_DEVBUF, 1035 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1036 1037 if (sc_if->sk_cdata.sk_jumbo_buf == NULL) { 1038 printf("sk%d: no memory for jumbo buffers!\n", sc_if->sk_unit); 1039 return(ENOBUFS); 1040 } 1041 1042 SLIST_INIT(&sc_if->sk_jfree_listhead); 1043 SLIST_INIT(&sc_if->sk_jinuse_listhead); 1044 1045 /* 1046 * Now divide it up into 9K pieces and save the addresses 1047 * in an array. 1048 */ 1049 ptr = sc_if->sk_cdata.sk_jumbo_buf; 1050 for (i = 0; i < SK_JSLOTS; i++) { 1051 sc_if->sk_cdata.sk_jslots[i] = ptr; 1052 ptr += SK_JLEN; 1053 entry = malloc(sizeof(struct sk_jpool_entry), 1054 M_DEVBUF, M_NOWAIT); 1055 if (entry == NULL) { 1056 free(sc_if->sk_cdata.sk_jumbo_buf, M_DEVBUF); 1057 sc_if->sk_cdata.sk_jumbo_buf = NULL; 1058 printf("sk%d: no memory for jumbo " 1059 "buffer queue!\n", sc_if->sk_unit); 1060 return(ENOBUFS); 1061 } 1062 entry->slot = i; 1063 SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 1064 entry, jpool_entries); 1065 } 1066 1067 return(0); 1068 } 1069 1070 /* 1071 * Allocate a jumbo buffer. 1072 */ 1073 static void * 1074 sk_jalloc(sc_if) 1075 struct sk_if_softc *sc_if; 1076 { 1077 struct sk_jpool_entry *entry; 1078 1079 entry = SLIST_FIRST(&sc_if->sk_jfree_listhead); 1080 1081 if (entry == NULL) { 1082 #ifdef SK_VERBOSE 1083 printf("sk%d: no free jumbo buffers\n", sc_if->sk_unit); 1084 #endif 1085 return(NULL); 1086 } 1087 1088 SLIST_REMOVE_HEAD(&sc_if->sk_jfree_listhead, jpool_entries); 1089 SLIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 1090 return(sc_if->sk_cdata.sk_jslots[entry->slot]); 1091 } 1092 1093 /* 1094 * Release a jumbo buffer. 1095 */ 1096 static void 1097 sk_jfree(buf, args) 1098 void *buf; 1099 void *args; 1100 { 1101 struct sk_if_softc *sc_if; 1102 int i; 1103 struct sk_jpool_entry *entry; 1104 1105 /* Extract the softc struct pointer. */ 1106 sc_if = (struct sk_if_softc *)args; 1107 1108 if (sc_if == NULL) 1109 panic("sk_jfree: didn't get softc pointer!"); 1110 1111 /* calculate the slot this buffer belongs to */ 1112 i = ((vm_offset_t)buf 1113 - (vm_offset_t)sc_if->sk_cdata.sk_jumbo_buf) / SK_JLEN; 1114 1115 if ((i < 0) || (i >= SK_JSLOTS)) 1116 panic("sk_jfree: asked to free buffer that we don't manage!"); 1117 1118 entry = SLIST_FIRST(&sc_if->sk_jinuse_listhead); 1119 if (entry == NULL) 1120 panic("sk_jfree: buffer not in use!"); 1121 entry->slot = i; 1122 SLIST_REMOVE_HEAD(&sc_if->sk_jinuse_listhead, jpool_entries); 1123 SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, entry, jpool_entries); 1124 1125 return; 1126 } 1127 1128 /* 1129 * Set media options. 1130 */ 1131 static int 1132 sk_ifmedia_upd(ifp) 1133 struct ifnet *ifp; 1134 { 1135 struct sk_if_softc *sc_if = ifp->if_softc; 1136 struct mii_data *mii; 1137 1138 mii = device_get_softc(sc_if->sk_miibus); 1139 sk_init(sc_if); 1140 mii_mediachg(mii); 1141 1142 return(0); 1143 } 1144 1145 /* 1146 * Report current media status. 1147 */ 1148 static void 1149 sk_ifmedia_sts(ifp, ifmr) 1150 struct ifnet *ifp; 1151 struct ifmediareq *ifmr; 1152 { 1153 struct sk_if_softc *sc_if; 1154 struct mii_data *mii; 1155 1156 sc_if = ifp->if_softc; 1157 mii = device_get_softc(sc_if->sk_miibus); 1158 1159 mii_pollstat(mii); 1160 ifmr->ifm_active = mii->mii_media_active; 1161 ifmr->ifm_status = mii->mii_media_status; 1162 1163 return; 1164 } 1165 1166 static int 1167 sk_ioctl(ifp, command, data) 1168 struct ifnet *ifp; 1169 u_long command; 1170 caddr_t data; 1171 { 1172 struct sk_if_softc *sc_if = ifp->if_softc; 1173 struct ifreq *ifr = (struct ifreq *) data; 1174 int error = 0; 1175 struct mii_data *mii; 1176 1177 SK_IF_LOCK(sc_if); 1178 1179 switch(command) { 1180 case SIOCSIFMTU: 1181 if (ifr->ifr_mtu > SK_JUMBO_MTU) 1182 error = EINVAL; 1183 else { 1184 ifp->if_mtu = ifr->ifr_mtu; 1185 sk_init(sc_if); 1186 } 1187 break; 1188 case SIOCSIFFLAGS: 1189 if (ifp->if_flags & IFF_UP) { 1190 if (ifp->if_flags & IFF_RUNNING) { 1191 if ((ifp->if_flags ^ sc_if->sk_if_flags) 1192 & IFF_PROMISC) { 1193 sk_setpromisc(sc_if); 1194 sk_setmulti(sc_if); 1195 } 1196 } else 1197 sk_init(sc_if); 1198 } else { 1199 if (ifp->if_flags & IFF_RUNNING) 1200 sk_stop(sc_if); 1201 } 1202 sc_if->sk_if_flags = ifp->if_flags; 1203 error = 0; 1204 break; 1205 case SIOCADDMULTI: 1206 case SIOCDELMULTI: 1207 sk_setmulti(sc_if); 1208 error = 0; 1209 break; 1210 case SIOCGIFMEDIA: 1211 case SIOCSIFMEDIA: 1212 mii = device_get_softc(sc_if->sk_miibus); 1213 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1214 break; 1215 default: 1216 error = ether_ioctl(ifp, command, data); 1217 break; 1218 } 1219 1220 SK_IF_UNLOCK(sc_if); 1221 1222 return(error); 1223 } 1224 1225 /* 1226 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 1227 * IDs against our list and return a device name if we find a match. 1228 */ 1229 static int 1230 skc_probe(dev) 1231 device_t dev; 1232 { 1233 struct sk_softc *sc; 1234 struct sk_type *t = sk_devs; 1235 1236 sc = device_get_softc(dev); 1237 1238 while(t->sk_name != NULL) { 1239 if ((pci_get_vendor(dev) == t->sk_vid) && 1240 (pci_get_device(dev) == t->sk_did)) { 1241 device_set_desc(dev, t->sk_name); 1242 return(0); 1243 } 1244 t++; 1245 } 1246 1247 return(ENXIO); 1248 } 1249 1250 /* 1251 * Force the GEnesis into reset, then bring it out of reset. 1252 */ 1253 static void 1254 sk_reset(sc) 1255 struct sk_softc *sc; 1256 { 1257 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 1258 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 1259 if (sc->sk_type == SK_YUKON) 1260 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 1261 1262 DELAY(1000); 1263 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 1264 DELAY(2); 1265 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1266 if (sc->sk_type == SK_YUKON) 1267 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 1268 1269 if (sc->sk_type == SK_GENESIS) { 1270 /* Configure packet arbiter */ 1271 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1272 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1273 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1274 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1275 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1276 } 1277 1278 /* Enable RAM interface */ 1279 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1280 1281 /* 1282 * Configure interrupt moderation. The moderation timer 1283 * defers interrupts specified in the interrupt moderation 1284 * timer mask based on the timeout specified in the interrupt 1285 * moderation timer init register. Each bit in the timer 1286 * register represents 18.825ns, so to specify a timeout in 1287 * microseconds, we have to multiply by 54. 1288 */ 1289 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(200)); 1290 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 1291 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 1292 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1293 1294 return; 1295 } 1296 1297 static int 1298 sk_probe(dev) 1299 device_t dev; 1300 { 1301 struct sk_softc *sc; 1302 1303 sc = device_get_softc(device_get_parent(dev)); 1304 1305 /* 1306 * Not much to do here. We always know there will be 1307 * at least one XMAC present, and if there are two, 1308 * skc_attach() will create a second device instance 1309 * for us. 1310 */ 1311 switch (sc->sk_type) { 1312 case SK_GENESIS: 1313 device_set_desc(dev, "XaQti Corp. XMAC II"); 1314 break; 1315 case SK_YUKON: 1316 device_set_desc(dev, "Marvell Semiconductor, Inc. Yukon"); 1317 break; 1318 } 1319 1320 return(0); 1321 } 1322 1323 /* 1324 * Each XMAC chip is attached as a separate logical IP interface. 1325 * Single port cards will have only one logical interface of course. 1326 */ 1327 static int 1328 sk_attach(dev) 1329 device_t dev; 1330 { 1331 struct sk_softc *sc; 1332 struct sk_if_softc *sc_if; 1333 struct ifnet *ifp; 1334 int i, port, error; 1335 1336 if (dev == NULL) 1337 return(EINVAL); 1338 1339 error = 0; 1340 sc_if = device_get_softc(dev); 1341 sc = device_get_softc(device_get_parent(dev)); 1342 port = *(int *)device_get_ivars(dev); 1343 free(device_get_ivars(dev), M_DEVBUF); 1344 device_set_ivars(dev, NULL); 1345 1346 sc_if->sk_dev = dev; 1347 sc_if->sk_unit = device_get_unit(dev); 1348 sc_if->sk_port = port; 1349 sc_if->sk_softc = sc; 1350 sc->sk_if[port] = sc_if; 1351 if (port == SK_PORT_A) 1352 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1353 if (port == SK_PORT_B) 1354 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1355 1356 /* Allocate the descriptor queues. */ 1357 sc_if->sk_rdata = contigmalloc(sizeof(struct sk_ring_data), M_DEVBUF, 1358 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1359 1360 if (sc_if->sk_rdata == NULL) { 1361 printf("sk%d: no memory for list buffers!\n", sc_if->sk_unit); 1362 error = ENOMEM; 1363 goto fail; 1364 } 1365 1366 bzero(sc_if->sk_rdata, sizeof(struct sk_ring_data)); 1367 1368 /* Try to allocate memory for jumbo buffers. */ 1369 if (sk_alloc_jumbo_mem(sc_if)) { 1370 printf("sk%d: jumbo buffer allocation failed\n", 1371 sc_if->sk_unit); 1372 error = ENOMEM; 1373 goto fail; 1374 } 1375 1376 ifp = &sc_if->arpcom.ac_if; 1377 ifp->if_softc = sc_if; 1378 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1379 ifp->if_mtu = ETHERMTU; 1380 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1381 ifp->if_ioctl = sk_ioctl; 1382 ifp->if_start = sk_start; 1383 ifp->if_watchdog = sk_watchdog; 1384 ifp->if_init = sk_init; 1385 ifp->if_baudrate = 1000000000; 1386 ifp->if_snd.ifq_maxlen = SK_TX_RING_CNT - 1; 1387 1388 callout_handle_init(&sc_if->sk_tick_ch); 1389 1390 /* 1391 * Get station address for this interface. Note that 1392 * dual port cards actually come with three station 1393 * addresses: one for each port, plus an extra. The 1394 * extra one is used by the SysKonnect driver software 1395 * as a 'virtual' station address for when both ports 1396 * are operating in failover mode. Currently we don't 1397 * use this extra address. 1398 */ 1399 SK_LOCK(sc); 1400 for (i = 0; i < ETHER_ADDR_LEN; i++) 1401 sc_if->arpcom.ac_enaddr[i] = 1402 sk_win_read_1(sc, SK_MAC0_0 + (port * 8) + i); 1403 1404 /* 1405 * Set up RAM buffer addresses. The NIC will have a certain 1406 * amount of SRAM on it, somewhere between 512K and 2MB. We 1407 * need to divide this up a) between the transmitter and 1408 * receiver and b) between the two XMACs, if this is a 1409 * dual port NIC. Our algotithm is to divide up the memory 1410 * evenly so that everyone gets a fair share. 1411 */ 1412 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1413 u_int32_t chunk, val; 1414 1415 chunk = sc->sk_ramsize / 2; 1416 val = sc->sk_rboff / sizeof(u_int64_t); 1417 sc_if->sk_rx_ramstart = val; 1418 val += (chunk / sizeof(u_int64_t)); 1419 sc_if->sk_rx_ramend = val - 1; 1420 sc_if->sk_tx_ramstart = val; 1421 val += (chunk / sizeof(u_int64_t)); 1422 sc_if->sk_tx_ramend = val - 1; 1423 } else { 1424 u_int32_t chunk, val; 1425 1426 chunk = sc->sk_ramsize / 4; 1427 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1428 sizeof(u_int64_t); 1429 sc_if->sk_rx_ramstart = val; 1430 val += (chunk / sizeof(u_int64_t)); 1431 sc_if->sk_rx_ramend = val - 1; 1432 sc_if->sk_tx_ramstart = val; 1433 val += (chunk / sizeof(u_int64_t)); 1434 sc_if->sk_tx_ramend = val - 1; 1435 } 1436 1437 /* Read and save PHY type and set PHY address */ 1438 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1439 switch(sc_if->sk_phytype) { 1440 case SK_PHYTYPE_XMAC: 1441 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1442 break; 1443 case SK_PHYTYPE_BCOM: 1444 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1445 break; 1446 case SK_PHYTYPE_MARV_COPPER: 1447 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1448 break; 1449 default: 1450 printf("skc%d: unsupported PHY type: %d\n", 1451 sc->sk_unit, sc_if->sk_phytype); 1452 error = ENODEV; 1453 SK_UNLOCK(sc); 1454 goto fail; 1455 } 1456 1457 1458 /* 1459 * Call MI attach routine. Can't hold locks when calling into ether_*. 1460 */ 1461 SK_UNLOCK(sc); 1462 ether_ifattach(ifp, sc_if->arpcom.ac_enaddr); 1463 SK_LOCK(sc); 1464 1465 /* 1466 * Do miibus setup. 1467 */ 1468 switch (sc->sk_type) { 1469 case SK_GENESIS: 1470 sk_init_xmac(sc_if); 1471 break; 1472 case SK_YUKON: 1473 sk_init_yukon(sc_if); 1474 break; 1475 } 1476 1477 SK_UNLOCK(sc); 1478 if (mii_phy_probe(dev, &sc_if->sk_miibus, 1479 sk_ifmedia_upd, sk_ifmedia_sts)) { 1480 printf("skc%d: no PHY found!\n", sc_if->sk_unit); 1481 ether_ifdetach(ifp); 1482 error = ENXIO; 1483 goto fail; 1484 } 1485 1486 fail: 1487 if (error) { 1488 /* Access should be ok even though lock has been dropped */ 1489 sc->sk_if[port] = NULL; 1490 sk_detach(dev); 1491 } 1492 1493 return(error); 1494 } 1495 1496 /* 1497 * Attach the interface. Allocate softc structures, do ifmedia 1498 * setup and ethernet/BPF attach. 1499 */ 1500 static int 1501 skc_attach(dev) 1502 device_t dev; 1503 { 1504 struct sk_softc *sc; 1505 int unit, error = 0, rid, *port; 1506 1507 sc = device_get_softc(dev); 1508 unit = device_get_unit(dev); 1509 1510 mtx_init(&sc->sk_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1511 MTX_DEF | MTX_RECURSE); 1512 /* 1513 * Map control/status registers. 1514 */ 1515 pci_enable_busmaster(dev); 1516 1517 rid = SK_RID; 1518 sc->sk_res = bus_alloc_resource_any(dev, SK_RES, &rid, RF_ACTIVE); 1519 1520 if (sc->sk_res == NULL) { 1521 printf("sk%d: couldn't map ports/memory\n", unit); 1522 error = ENXIO; 1523 goto fail; 1524 } 1525 1526 sc->sk_btag = rman_get_bustag(sc->sk_res); 1527 sc->sk_bhandle = rman_get_bushandle(sc->sk_res); 1528 1529 /* Allocate interrupt */ 1530 rid = 0; 1531 sc->sk_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1532 RF_SHAREABLE | RF_ACTIVE); 1533 1534 if (sc->sk_irq == NULL) { 1535 printf("skc%d: couldn't map interrupt\n", unit); 1536 error = ENXIO; 1537 goto fail; 1538 } 1539 1540 /* Set adapter type */ 1541 switch (pci_get_device(dev)) { 1542 case DEVICEID_SK_V1: 1543 sc->sk_type = SK_GENESIS; 1544 break; 1545 case DEVICEID_SK_V2: 1546 case DEVICEID_BELKIN_5005: 1547 case DEVICEID_3COM_3C940: 1548 case DEVICEID_LINKSYS_EG1032: 1549 case DEVICEID_DLINK_DGE530T: 1550 sc->sk_type = SK_YUKON; 1551 break; 1552 default: 1553 printf("skc%d: unknown device!\n", unit); 1554 error = ENXIO; 1555 goto fail; 1556 } 1557 1558 /* Reset the adapter. */ 1559 sk_reset(sc); 1560 1561 sc->sk_unit = unit; 1562 1563 /* Read and save vital product data from EEPROM. */ 1564 sk_vpd_read(sc); 1565 1566 if (sc->sk_type == SK_GENESIS) { 1567 /* Read and save RAM size and RAMbuffer offset */ 1568 switch(sk_win_read_1(sc, SK_EPROM0)) { 1569 case SK_RAMSIZE_512K_64: 1570 sc->sk_ramsize = 0x80000; 1571 sc->sk_rboff = SK_RBOFF_0; 1572 break; 1573 case SK_RAMSIZE_1024K_64: 1574 sc->sk_ramsize = 0x100000; 1575 sc->sk_rboff = SK_RBOFF_80000; 1576 break; 1577 case SK_RAMSIZE_1024K_128: 1578 sc->sk_ramsize = 0x100000; 1579 sc->sk_rboff = SK_RBOFF_0; 1580 break; 1581 case SK_RAMSIZE_2048K_128: 1582 sc->sk_ramsize = 0x200000; 1583 sc->sk_rboff = SK_RBOFF_0; 1584 break; 1585 default: 1586 printf("skc%d: unknown ram size: %d\n", 1587 sc->sk_unit, sk_win_read_1(sc, SK_EPROM0)); 1588 error = ENXIO; 1589 goto fail; 1590 } 1591 } else { 1592 sc->sk_ramsize = 0x20000; 1593 sc->sk_rboff = SK_RBOFF_0; 1594 } 1595 1596 /* Read and save physical media type */ 1597 switch(sk_win_read_1(sc, SK_PMDTYPE)) { 1598 case SK_PMD_1000BASESX: 1599 sc->sk_pmd = IFM_1000_SX; 1600 break; 1601 case SK_PMD_1000BASELX: 1602 sc->sk_pmd = IFM_1000_LX; 1603 break; 1604 case SK_PMD_1000BASECX: 1605 sc->sk_pmd = IFM_1000_CX; 1606 break; 1607 case SK_PMD_1000BASETX: 1608 sc->sk_pmd = IFM_1000_T; 1609 break; 1610 default: 1611 printf("skc%d: unknown media type: 0x%x\n", 1612 sc->sk_unit, sk_win_read_1(sc, SK_PMDTYPE)); 1613 error = ENXIO; 1614 goto fail; 1615 } 1616 1617 /* Announce the product name and more VPD data if there. */ 1618 if (sc->sk_vpd_prodname != NULL) 1619 printf("skc%d: %s\n", sc->sk_unit, sc->sk_vpd_prodname); 1620 if (sc->sk_vpd_readonly != NULL && sc->sk_vpd_readonly_len != 0) { 1621 char buf[256]; 1622 char *dp = sc->sk_vpd_readonly; 1623 uint16_t l, len = sc->sk_vpd_readonly_len; 1624 1625 while (len >= 3) { 1626 if ( (*dp == 'P' && *(dp+1) == 'N') || 1627 (*dp == 'E' && *(dp+1) == 'C') || 1628 (*dp == 'M' && *(dp+1) == 'N') || 1629 (*dp == 'S' && *(dp+1) == 'N') ) { 1630 1631 l = 0; 1632 while(l < *(dp+2)) { 1633 buf[l] = *(dp+3+l); 1634 ++l; 1635 } 1636 buf[l] = '\0'; 1637 printf("skc%d: %c%c: %s\n", 1638 sc->sk_unit, *dp, *(dp+1), buf); 1639 len -= (3 + l); 1640 dp += (3 + l); 1641 } else { 1642 len -= (3 + *(dp+2)); 1643 dp += (3 + *(dp+2)); 1644 } 1645 } 1646 } 1647 sc->sk_devs[SK_PORT_A] = device_add_child(dev, "sk", -1); 1648 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT); 1649 *port = SK_PORT_A; 1650 device_set_ivars(sc->sk_devs[SK_PORT_A], port); 1651 1652 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1653 sc->sk_devs[SK_PORT_B] = device_add_child(dev, "sk", -1); 1654 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT); 1655 *port = SK_PORT_B; 1656 device_set_ivars(sc->sk_devs[SK_PORT_B], port); 1657 } 1658 1659 /* Turn on the 'driver is loaded' LED. */ 1660 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1661 1662 bus_generic_attach(dev); 1663 1664 /* Hook interrupt last to avoid having to lock softc */ 1665 error = bus_setup_intr(dev, sc->sk_irq, INTR_TYPE_NET|INTR_MPSAFE, 1666 sk_intr, sc, &sc->sk_intrhand); 1667 1668 if (error) { 1669 printf("skc%d: couldn't set up irq\n", unit); 1670 goto fail; 1671 } 1672 1673 fail: 1674 if (error) 1675 skc_detach(dev); 1676 1677 return(error); 1678 } 1679 1680 /* 1681 * Shutdown hardware and free up resources. This can be called any 1682 * time after the mutex has been initialized. It is called in both 1683 * the error case in attach and the normal detach case so it needs 1684 * to be careful about only freeing resources that have actually been 1685 * allocated. 1686 */ 1687 static int 1688 sk_detach(dev) 1689 device_t dev; 1690 { 1691 struct sk_if_softc *sc_if; 1692 struct ifnet *ifp; 1693 1694 sc_if = device_get_softc(dev); 1695 KASSERT(mtx_initialized(&sc_if->sk_softc->sk_mtx), 1696 ("sk mutex not initialized in sk_detach")); 1697 SK_IF_LOCK(sc_if); 1698 1699 ifp = &sc_if->arpcom.ac_if; 1700 /* These should only be active if attach_xmac succeeded */ 1701 if (device_is_attached(dev)) { 1702 sk_stop(sc_if); 1703 /* Can't hold locks while calling detach */ 1704 SK_IF_UNLOCK(sc_if); 1705 ether_ifdetach(ifp); 1706 SK_IF_LOCK(sc_if); 1707 } 1708 /* 1709 * We're generally called from skc_detach() which is using 1710 * device_delete_child() to get to here. It's already trashed 1711 * miibus for us, so don't do it here or we'll panic. 1712 */ 1713 /* 1714 if (sc_if->sk_miibus != NULL) 1715 device_delete_child(dev, sc_if->sk_miibus); 1716 */ 1717 bus_generic_detach(dev); 1718 if (sc_if->sk_cdata.sk_jumbo_buf != NULL) 1719 contigfree(sc_if->sk_cdata.sk_jumbo_buf, SK_JMEM, M_DEVBUF); 1720 if (sc_if->sk_rdata != NULL) { 1721 contigfree(sc_if->sk_rdata, sizeof(struct sk_ring_data), 1722 M_DEVBUF); 1723 } 1724 SK_IF_UNLOCK(sc_if); 1725 1726 return(0); 1727 } 1728 1729 static int 1730 skc_detach(dev) 1731 device_t dev; 1732 { 1733 struct sk_softc *sc; 1734 1735 sc = device_get_softc(dev); 1736 KASSERT(mtx_initialized(&sc->sk_mtx), ("sk mutex not initialized")); 1737 1738 if (device_is_alive(dev)) { 1739 if (sc->sk_devs[SK_PORT_A] != NULL) 1740 device_delete_child(dev, sc->sk_devs[SK_PORT_A]); 1741 if (sc->sk_devs[SK_PORT_B] != NULL) 1742 device_delete_child(dev, sc->sk_devs[SK_PORT_B]); 1743 bus_generic_detach(dev); 1744 } 1745 1746 if (sc->sk_intrhand) 1747 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand); 1748 if (sc->sk_irq) 1749 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq); 1750 if (sc->sk_res) 1751 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res); 1752 1753 mtx_destroy(&sc->sk_mtx); 1754 1755 return(0); 1756 } 1757 1758 static int 1759 sk_encap(sc_if, m_head, txidx) 1760 struct sk_if_softc *sc_if; 1761 struct mbuf *m_head; 1762 u_int32_t *txidx; 1763 { 1764 struct sk_tx_desc *f = NULL; 1765 struct mbuf *m; 1766 u_int32_t frag, cur, cnt = 0; 1767 1768 m = m_head; 1769 cur = frag = *txidx; 1770 1771 /* 1772 * Start packing the mbufs in this chain into 1773 * the fragment pointers. Stop when we run out 1774 * of fragments or hit the end of the mbuf chain. 1775 */ 1776 for (m = m_head; m != NULL; m = m->m_next) { 1777 if (m->m_len != 0) { 1778 if ((SK_TX_RING_CNT - 1779 (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) 1780 return(ENOBUFS); 1781 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1782 f->sk_data_lo = vtophys(mtod(m, vm_offset_t)); 1783 f->sk_ctl = m->m_len | SK_OPCODE_DEFAULT; 1784 if (cnt == 0) 1785 f->sk_ctl |= SK_TXCTL_FIRSTFRAG; 1786 else 1787 f->sk_ctl |= SK_TXCTL_OWN; 1788 cur = frag; 1789 SK_INC(frag, SK_TX_RING_CNT); 1790 cnt++; 1791 } 1792 } 1793 1794 if (m != NULL) 1795 return(ENOBUFS); 1796 1797 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1798 SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR; 1799 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1800 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= SK_TXCTL_OWN; 1801 sc_if->sk_cdata.sk_tx_cnt += cnt; 1802 1803 *txidx = frag; 1804 1805 return(0); 1806 } 1807 1808 static void 1809 sk_start(ifp) 1810 struct ifnet *ifp; 1811 { 1812 struct sk_softc *sc; 1813 struct sk_if_softc *sc_if; 1814 struct mbuf *m_head = NULL; 1815 u_int32_t idx; 1816 1817 sc_if = ifp->if_softc; 1818 sc = sc_if->sk_softc; 1819 1820 SK_IF_LOCK(sc_if); 1821 1822 idx = sc_if->sk_cdata.sk_tx_prod; 1823 1824 while(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1825 IF_DEQUEUE(&ifp->if_snd, m_head); 1826 if (m_head == NULL) 1827 break; 1828 1829 /* 1830 * Pack the data into the transmit ring. If we 1831 * don't have room, set the OACTIVE flag and wait 1832 * for the NIC to drain the ring. 1833 */ 1834 if (sk_encap(sc_if, m_head, &idx)) { 1835 IF_PREPEND(&ifp->if_snd, m_head); 1836 ifp->if_flags |= IFF_OACTIVE; 1837 break; 1838 } 1839 1840 /* 1841 * If there's a BPF listener, bounce a copy of this frame 1842 * to him. 1843 */ 1844 BPF_MTAP(ifp, m_head); 1845 } 1846 1847 /* Transmit */ 1848 sc_if->sk_cdata.sk_tx_prod = idx; 1849 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1850 1851 /* Set a timeout in case the chip goes out to lunch. */ 1852 ifp->if_timer = 5; 1853 SK_IF_UNLOCK(sc_if); 1854 1855 return; 1856 } 1857 1858 1859 static void 1860 sk_watchdog(ifp) 1861 struct ifnet *ifp; 1862 { 1863 struct sk_if_softc *sc_if; 1864 1865 sc_if = ifp->if_softc; 1866 1867 printf("sk%d: watchdog timeout\n", sc_if->sk_unit); 1868 sk_init(sc_if); 1869 1870 return; 1871 } 1872 1873 static void 1874 skc_shutdown(dev) 1875 device_t dev; 1876 { 1877 struct sk_softc *sc; 1878 1879 sc = device_get_softc(dev); 1880 SK_LOCK(sc); 1881 1882 /* Turn off the 'driver is loaded' LED. */ 1883 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1884 1885 /* 1886 * Reset the GEnesis controller. Doing this should also 1887 * assert the resets on the attached XMAC(s). 1888 */ 1889 sk_reset(sc); 1890 SK_UNLOCK(sc); 1891 1892 return; 1893 } 1894 1895 static void 1896 sk_rxeof(sc_if) 1897 struct sk_if_softc *sc_if; 1898 { 1899 struct sk_softc *sc; 1900 struct mbuf *m; 1901 struct ifnet *ifp; 1902 struct sk_chain *cur_rx; 1903 int total_len = 0; 1904 int i; 1905 u_int32_t rxstat; 1906 1907 sc = sc_if->sk_softc; 1908 ifp = &sc_if->arpcom.ac_if; 1909 i = sc_if->sk_cdata.sk_rx_prod; 1910 cur_rx = &sc_if->sk_cdata.sk_rx_chain[i]; 1911 1912 SK_LOCK_ASSERT(sc); 1913 1914 while(!(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl & SK_RXCTL_OWN)) { 1915 1916 cur_rx = &sc_if->sk_cdata.sk_rx_chain[i]; 1917 rxstat = sc_if->sk_rdata->sk_rx_ring[i].sk_xmac_rxstat; 1918 m = cur_rx->sk_mbuf; 1919 cur_rx->sk_mbuf = NULL; 1920 total_len = SK_RXBYTES(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl); 1921 SK_INC(i, SK_RX_RING_CNT); 1922 1923 if (rxstat & XM_RXSTAT_ERRFRAME) { 1924 ifp->if_ierrors++; 1925 sk_newbuf(sc_if, cur_rx, m); 1926 continue; 1927 } 1928 1929 /* 1930 * Try to allocate a new jumbo buffer. If that 1931 * fails, copy the packet to mbufs and put the 1932 * jumbo buffer back in the ring so it can be 1933 * re-used. If allocating mbufs fails, then we 1934 * have to drop the packet. 1935 */ 1936 if (sk_newbuf(sc_if, cur_rx, NULL) == ENOBUFS) { 1937 struct mbuf *m0; 1938 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, 1939 ifp, NULL); 1940 sk_newbuf(sc_if, cur_rx, m); 1941 if (m0 == NULL) { 1942 printf("sk%d: no receive buffers " 1943 "available -- packet dropped!\n", 1944 sc_if->sk_unit); 1945 ifp->if_ierrors++; 1946 continue; 1947 } 1948 m = m0; 1949 } else { 1950 m->m_pkthdr.rcvif = ifp; 1951 m->m_pkthdr.len = m->m_len = total_len; 1952 } 1953 1954 ifp->if_ipackets++; 1955 SK_UNLOCK(sc); 1956 (*ifp->if_input)(ifp, m); 1957 SK_LOCK(sc); 1958 } 1959 1960 sc_if->sk_cdata.sk_rx_prod = i; 1961 1962 return; 1963 } 1964 1965 static void 1966 sk_txeof(sc_if) 1967 struct sk_if_softc *sc_if; 1968 { 1969 struct sk_tx_desc *cur_tx = NULL; 1970 struct ifnet *ifp; 1971 u_int32_t idx; 1972 1973 ifp = &sc_if->arpcom.ac_if; 1974 1975 /* 1976 * Go through our tx ring and free mbufs for those 1977 * frames that have been sent. 1978 */ 1979 idx = sc_if->sk_cdata.sk_tx_cons; 1980 while(idx != sc_if->sk_cdata.sk_tx_prod) { 1981 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 1982 if (cur_tx->sk_ctl & SK_TXCTL_OWN) 1983 break; 1984 if (cur_tx->sk_ctl & SK_TXCTL_LASTFRAG) 1985 ifp->if_opackets++; 1986 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 1987 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 1988 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 1989 } 1990 sc_if->sk_cdata.sk_tx_cnt--; 1991 SK_INC(idx, SK_TX_RING_CNT); 1992 ifp->if_timer = 0; 1993 } 1994 1995 sc_if->sk_cdata.sk_tx_cons = idx; 1996 1997 if (cur_tx != NULL) 1998 ifp->if_flags &= ~IFF_OACTIVE; 1999 2000 return; 2001 } 2002 2003 static void 2004 sk_tick(xsc_if) 2005 void *xsc_if; 2006 { 2007 struct sk_if_softc *sc_if; 2008 struct mii_data *mii; 2009 struct ifnet *ifp; 2010 int i; 2011 2012 sc_if = xsc_if; 2013 SK_IF_LOCK(sc_if); 2014 ifp = &sc_if->arpcom.ac_if; 2015 mii = device_get_softc(sc_if->sk_miibus); 2016 2017 if (!(ifp->if_flags & IFF_UP)) { 2018 SK_IF_UNLOCK(sc_if); 2019 return; 2020 } 2021 2022 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2023 sk_intr_bcom(sc_if); 2024 SK_IF_UNLOCK(sc_if); 2025 return; 2026 } 2027 2028 /* 2029 * According to SysKonnect, the correct way to verify that 2030 * the link has come back up is to poll bit 0 of the GPIO 2031 * register three times. This pin has the signal from the 2032 * link_sync pin connected to it; if we read the same link 2033 * state 3 times in a row, we know the link is up. 2034 */ 2035 for (i = 0; i < 3; i++) { 2036 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 2037 break; 2038 } 2039 2040 if (i != 3) { 2041 sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz); 2042 SK_IF_UNLOCK(sc_if); 2043 return; 2044 } 2045 2046 /* Turn the GP0 interrupt back on. */ 2047 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2048 SK_XM_READ_2(sc_if, XM_ISR); 2049 mii_tick(mii); 2050 untimeout(sk_tick, sc_if, sc_if->sk_tick_ch); 2051 2052 SK_IF_UNLOCK(sc_if); 2053 return; 2054 } 2055 2056 static void 2057 sk_intr_bcom(sc_if) 2058 struct sk_if_softc *sc_if; 2059 { 2060 struct mii_data *mii; 2061 struct ifnet *ifp; 2062 int status; 2063 mii = device_get_softc(sc_if->sk_miibus); 2064 ifp = &sc_if->arpcom.ac_if; 2065 2066 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2067 2068 /* 2069 * Read the PHY interrupt register to make sure 2070 * we clear any pending interrupts. 2071 */ 2072 status = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 2073 2074 if (!(ifp->if_flags & IFF_RUNNING)) { 2075 sk_init_xmac(sc_if); 2076 return; 2077 } 2078 2079 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 2080 int lstat; 2081 lstat = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 2082 BRGPHY_MII_AUXSTS); 2083 2084 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 2085 mii_mediachg(mii); 2086 /* Turn off the link LED. */ 2087 SK_IF_WRITE_1(sc_if, 0, 2088 SK_LINKLED1_CTL, SK_LINKLED_OFF); 2089 sc_if->sk_link = 0; 2090 } else if (status & BRGPHY_ISR_LNK_CHG) { 2091 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 2092 BRGPHY_MII_IMR, 0xFF00); 2093 mii_tick(mii); 2094 sc_if->sk_link = 1; 2095 /* Turn on the link LED. */ 2096 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2097 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 2098 SK_LINKLED_BLINK_OFF); 2099 } else { 2100 mii_tick(mii); 2101 sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz); 2102 } 2103 } 2104 2105 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2106 2107 return; 2108 } 2109 2110 static void 2111 sk_intr_xmac(sc_if) 2112 struct sk_if_softc *sc_if; 2113 { 2114 struct sk_softc *sc; 2115 u_int16_t status; 2116 2117 sc = sc_if->sk_softc; 2118 status = SK_XM_READ_2(sc_if, XM_ISR); 2119 2120 /* 2121 * Link has gone down. Start MII tick timeout to 2122 * watch for link resync. 2123 */ 2124 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 2125 if (status & XM_ISR_GP0_SET) { 2126 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2127 sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz); 2128 } 2129 2130 if (status & XM_ISR_AUTONEG_DONE) { 2131 sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz); 2132 } 2133 } 2134 2135 if (status & XM_IMR_TX_UNDERRUN) 2136 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 2137 2138 if (status & XM_IMR_RX_OVERRUN) 2139 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 2140 2141 status = SK_XM_READ_2(sc_if, XM_ISR); 2142 2143 return; 2144 } 2145 2146 static void 2147 sk_intr_yukon(sc_if) 2148 struct sk_if_softc *sc_if; 2149 { 2150 int status; 2151 2152 status = SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2153 2154 return; 2155 } 2156 2157 static void 2158 sk_intr(xsc) 2159 void *xsc; 2160 { 2161 struct sk_softc *sc = xsc; 2162 struct sk_if_softc *sc_if0 = NULL, *sc_if1 = NULL; 2163 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2164 u_int32_t status; 2165 2166 SK_LOCK(sc); 2167 2168 sc_if0 = sc->sk_if[SK_PORT_A]; 2169 sc_if1 = sc->sk_if[SK_PORT_B]; 2170 2171 if (sc_if0 != NULL) 2172 ifp0 = &sc_if0->arpcom.ac_if; 2173 if (sc_if1 != NULL) 2174 ifp1 = &sc_if1->arpcom.ac_if; 2175 2176 for (;;) { 2177 status = CSR_READ_4(sc, SK_ISSR); 2178 if (!(status & sc->sk_intrmask)) 2179 break; 2180 2181 /* Handle receive interrupts first. */ 2182 if (status & SK_ISR_RX1_EOF) { 2183 sk_rxeof(sc_if0); 2184 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 2185 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2186 } 2187 if (status & SK_ISR_RX2_EOF) { 2188 sk_rxeof(sc_if1); 2189 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 2190 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2191 } 2192 2193 /* Then transmit interrupts. */ 2194 if (status & SK_ISR_TX1_S_EOF) { 2195 sk_txeof(sc_if0); 2196 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 2197 SK_TXBMU_CLR_IRQ_EOF); 2198 } 2199 if (status & SK_ISR_TX2_S_EOF) { 2200 sk_txeof(sc_if1); 2201 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 2202 SK_TXBMU_CLR_IRQ_EOF); 2203 } 2204 2205 /* Then MAC interrupts. */ 2206 if (status & SK_ISR_MAC1 && ifp0->if_flags & IFF_RUNNING) { 2207 if (sc->sk_type == SK_GENESIS) 2208 sk_intr_xmac(sc_if0); 2209 else 2210 sk_intr_yukon(sc_if0); 2211 } 2212 2213 if (status & SK_ISR_MAC2 && ifp1->if_flags & IFF_RUNNING) { 2214 if (sc->sk_type == SK_GENESIS) 2215 sk_intr_xmac(sc_if1); 2216 else 2217 sk_intr_yukon(sc_if1); 2218 } 2219 2220 if (status & SK_ISR_EXTERNAL_REG) { 2221 if (ifp0 != NULL && 2222 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 2223 sk_intr_bcom(sc_if0); 2224 if (ifp1 != NULL && 2225 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 2226 sk_intr_bcom(sc_if1); 2227 } 2228 } 2229 2230 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2231 2232 if (ifp0 != NULL && ifp0->if_snd.ifq_head != NULL) 2233 sk_start(ifp0); 2234 if (ifp1 != NULL && ifp1->if_snd.ifq_head != NULL) 2235 sk_start(ifp1); 2236 2237 SK_UNLOCK(sc); 2238 2239 return; 2240 } 2241 2242 static void 2243 sk_init_xmac(sc_if) 2244 struct sk_if_softc *sc_if; 2245 { 2246 struct sk_softc *sc; 2247 struct ifnet *ifp; 2248 struct sk_bcom_hack bhack[] = { 2249 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 2250 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 2251 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 2252 { 0, 0 } }; 2253 2254 sc = sc_if->sk_softc; 2255 ifp = &sc_if->arpcom.ac_if; 2256 2257 /* Unreset the XMAC. */ 2258 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 2259 DELAY(1000); 2260 2261 /* Reset the XMAC's internal state. */ 2262 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2263 2264 /* Save the XMAC II revision */ 2265 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 2266 2267 /* 2268 * Perform additional initialization for external PHYs, 2269 * namely for the 1000baseTX cards that use the XMAC's 2270 * GMII mode. 2271 */ 2272 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2273 int i = 0; 2274 u_int32_t val; 2275 2276 /* Take PHY out of reset. */ 2277 val = sk_win_read_4(sc, SK_GPIO); 2278 if (sc_if->sk_port == SK_PORT_A) 2279 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 2280 else 2281 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 2282 sk_win_write_4(sc, SK_GPIO, val); 2283 2284 /* Enable GMII mode on the XMAC. */ 2285 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 2286 2287 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 2288 BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET); 2289 DELAY(10000); 2290 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 2291 BRGPHY_MII_IMR, 0xFFF0); 2292 2293 /* 2294 * Early versions of the BCM5400 apparently have 2295 * a bug that requires them to have their reserved 2296 * registers initialized to some magic values. I don't 2297 * know what the numbers do, I'm just the messenger. 2298 */ 2299 if (sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 0x03) 2300 == 0x6041) { 2301 while(bhack[i].reg) { 2302 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 2303 bhack[i].reg, bhack[i].val); 2304 i++; 2305 } 2306 } 2307 } 2308 2309 /* Set station address */ 2310 SK_XM_WRITE_2(sc_if, XM_PAR0, 2311 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[0])); 2312 SK_XM_WRITE_2(sc_if, XM_PAR1, 2313 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[2])); 2314 SK_XM_WRITE_2(sc_if, XM_PAR2, 2315 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[4])); 2316 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 2317 2318 if (ifp->if_flags & IFF_BROADCAST) { 2319 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2320 } else { 2321 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2322 } 2323 2324 /* We don't need the FCS appended to the packet. */ 2325 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 2326 2327 /* We want short frames padded to 60 bytes. */ 2328 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 2329 2330 /* 2331 * Enable the reception of all error frames. This is is 2332 * a necessary evil due to the design of the XMAC. The 2333 * XMAC's receive FIFO is only 8K in size, however jumbo 2334 * frames can be up to 9000 bytes in length. When bad 2335 * frame filtering is enabled, the XMAC's RX FIFO operates 2336 * in 'store and forward' mode. For this to work, the 2337 * entire frame has to fit into the FIFO, but that means 2338 * that jumbo frames larger than 8192 bytes will be 2339 * truncated. Disabling all bad frame filtering causes 2340 * the RX FIFO to operate in streaming mode, in which 2341 * case the XMAC will start transfering frames out of the 2342 * RX FIFO as soon as the FIFO threshold is reached. 2343 */ 2344 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 2345 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 2346 XM_MODE_RX_INRANGELEN); 2347 2348 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2349 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2350 else 2351 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2352 2353 /* 2354 * Bump up the transmit threshold. This helps hold off transmit 2355 * underruns when we're blasting traffic from both ports at once. 2356 */ 2357 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2358 2359 /* Set promiscuous mode */ 2360 sk_setpromisc(sc_if); 2361 2362 /* Set multicast filter */ 2363 sk_setmulti(sc_if); 2364 2365 /* Clear and enable interrupts */ 2366 SK_XM_READ_2(sc_if, XM_ISR); 2367 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2368 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2369 else 2370 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2371 2372 /* Configure MAC arbiter */ 2373 switch(sc_if->sk_xmac_rev) { 2374 case XM_XMAC_REV_B2: 2375 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2376 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2377 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2378 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2379 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2380 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2381 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2382 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2383 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2384 break; 2385 case XM_XMAC_REV_C1: 2386 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2387 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2388 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2389 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2390 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2391 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2392 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2393 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2394 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2395 break; 2396 default: 2397 break; 2398 } 2399 sk_win_write_2(sc, SK_MACARB_CTL, 2400 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 2401 2402 sc_if->sk_link = 1; 2403 2404 return; 2405 } 2406 2407 static void 2408 sk_init_yukon(sc_if) 2409 struct sk_if_softc *sc_if; 2410 { 2411 u_int32_t phy; 2412 u_int16_t reg; 2413 int i; 2414 2415 /* GMAC and GPHY Reset */ 2416 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 2417 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2418 DELAY(1000); 2419 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR); 2420 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2421 DELAY(1000); 2422 2423 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 2424 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 2425 2426 switch(sc_if->sk_softc->sk_pmd) { 2427 case IFM_1000_SX: 2428 case IFM_1000_LX: 2429 phy |= SK_GPHY_FIBER; 2430 break; 2431 2432 case IFM_1000_CX: 2433 case IFM_1000_T: 2434 phy |= SK_GPHY_COPPER; 2435 break; 2436 } 2437 2438 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 2439 DELAY(1000); 2440 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 2441 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 2442 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 2443 2444 /* unused read of the interrupt source register */ 2445 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2446 2447 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2448 2449 /* MIB Counter Clear Mode set */ 2450 reg |= YU_PAR_MIB_CLR; 2451 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2452 2453 /* MIB Counter Clear Mode clear */ 2454 reg &= ~YU_PAR_MIB_CLR; 2455 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2456 2457 /* receive control reg */ 2458 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR); 2459 2460 /* transmit parameter register */ 2461 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2462 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 2463 2464 /* serial mode register */ 2465 SK_YU_WRITE_2(sc_if, YUKON_SMR, YU_SMR_DATA_BLIND(0x1c) | 2466 YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e)); 2467 2468 /* Setup Yukon's address */ 2469 for (i = 0; i < 3; i++) { 2470 /* Write Source Address 1 (unicast filter) */ 2471 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2472 sc_if->arpcom.ac_enaddr[i * 2] | 2473 sc_if->arpcom.ac_enaddr[i * 2 + 1] << 8); 2474 } 2475 2476 for (i = 0; i < 3; i++) { 2477 reg = sk_win_read_2(sc_if->sk_softc, 2478 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2479 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2480 } 2481 2482 /* Set promiscuous mode */ 2483 sk_setpromisc(sc_if); 2484 2485 /* Set multicast filter */ 2486 sk_setmulti(sc_if); 2487 2488 /* enable interrupt mask for counter overflows */ 2489 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2490 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2491 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2492 2493 /* Configure RX MAC FIFO */ 2494 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2495 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON); 2496 2497 /* Configure TX MAC FIFO */ 2498 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2499 SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2500 } 2501 2502 /* 2503 * Note that to properly initialize any part of the GEnesis chip, 2504 * you first have to take it out of reset mode. 2505 */ 2506 static void 2507 sk_init(xsc) 2508 void *xsc; 2509 { 2510 struct sk_if_softc *sc_if = xsc; 2511 struct sk_softc *sc; 2512 struct ifnet *ifp; 2513 struct mii_data *mii; 2514 u_int16_t reg; 2515 2516 SK_IF_LOCK(sc_if); 2517 2518 ifp = &sc_if->arpcom.ac_if; 2519 sc = sc_if->sk_softc; 2520 mii = device_get_softc(sc_if->sk_miibus); 2521 2522 /* Cancel pending I/O and free all RX/TX buffers. */ 2523 sk_stop(sc_if); 2524 2525 if (sc->sk_type == SK_GENESIS) { 2526 /* Configure LINK_SYNC LED */ 2527 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2528 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2529 SK_LINKLED_LINKSYNC_ON); 2530 2531 /* Configure RX LED */ 2532 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 2533 SK_RXLEDCTL_COUNTER_START); 2534 2535 /* Configure TX LED */ 2536 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 2537 SK_TXLEDCTL_COUNTER_START); 2538 } 2539 2540 /* Configure I2C registers */ 2541 2542 /* Configure XMAC(s) */ 2543 switch (sc->sk_type) { 2544 case SK_GENESIS: 2545 sk_init_xmac(sc_if); 2546 break; 2547 case SK_YUKON: 2548 sk_init_yukon(sc_if); 2549 break; 2550 } 2551 mii_mediachg(mii); 2552 2553 if (sc->sk_type == SK_GENESIS) { 2554 /* Configure MAC FIFOs */ 2555 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2556 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2557 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2558 2559 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2560 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2561 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2562 } 2563 2564 /* Configure transmit arbiter(s) */ 2565 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2566 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2567 2568 /* Configure RAMbuffers */ 2569 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2570 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2571 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2572 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2573 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2574 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2575 2576 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2577 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2578 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2579 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2580 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2581 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2582 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2583 2584 /* Configure BMUs */ 2585 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2586 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2587 vtophys(&sc_if->sk_rdata->sk_rx_ring[0])); 2588 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2589 2590 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2591 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2592 vtophys(&sc_if->sk_rdata->sk_tx_ring[0])); 2593 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2594 2595 /* Init descriptors */ 2596 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2597 printf("sk%d: initialization failed: no " 2598 "memory for rx buffers\n", sc_if->sk_unit); 2599 sk_stop(sc_if); 2600 SK_IF_UNLOCK(sc_if); 2601 return; 2602 } 2603 sk_init_tx_ring(sc_if); 2604 2605 /* Configure interrupt handling */ 2606 CSR_READ_4(sc, SK_ISSR); 2607 if (sc_if->sk_port == SK_PORT_A) 2608 sc->sk_intrmask |= SK_INTRS1; 2609 else 2610 sc->sk_intrmask |= SK_INTRS2; 2611 2612 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2613 2614 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2615 2616 /* Start BMUs. */ 2617 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2618 2619 switch(sc->sk_type) { 2620 case SK_GENESIS: 2621 /* Enable XMACs TX and RX state machines */ 2622 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2623 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2624 break; 2625 case SK_YUKON: 2626 reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 2627 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 2628 reg &= ~(YU_GPCR_SPEED_EN | YU_GPCR_DPLX_EN); 2629 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 2630 } 2631 2632 ifp->if_flags |= IFF_RUNNING; 2633 ifp->if_flags &= ~IFF_OACTIVE; 2634 2635 SK_IF_UNLOCK(sc_if); 2636 2637 return; 2638 } 2639 2640 static void 2641 sk_stop(sc_if) 2642 struct sk_if_softc *sc_if; 2643 { 2644 int i; 2645 struct sk_softc *sc; 2646 struct ifnet *ifp; 2647 2648 SK_IF_LOCK(sc_if); 2649 sc = sc_if->sk_softc; 2650 ifp = &sc_if->arpcom.ac_if; 2651 2652 untimeout(sk_tick, sc_if, sc_if->sk_tick_ch); 2653 2654 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2655 u_int32_t val; 2656 2657 /* Put PHY back into reset. */ 2658 val = sk_win_read_4(sc, SK_GPIO); 2659 if (sc_if->sk_port == SK_PORT_A) { 2660 val |= SK_GPIO_DIR0; 2661 val &= ~SK_GPIO_DAT0; 2662 } else { 2663 val |= SK_GPIO_DIR2; 2664 val &= ~SK_GPIO_DAT2; 2665 } 2666 sk_win_write_4(sc, SK_GPIO, val); 2667 } 2668 2669 /* Turn off various components of this interface. */ 2670 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2671 switch (sc->sk_type) { 2672 case SK_GENESIS: 2673 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_RESET); 2674 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2675 break; 2676 case SK_YUKON: 2677 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2678 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2679 break; 2680 } 2681 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2682 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2683 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2684 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2685 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2686 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2687 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2688 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2689 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2690 2691 /* Disable interrupts */ 2692 if (sc_if->sk_port == SK_PORT_A) 2693 sc->sk_intrmask &= ~SK_INTRS1; 2694 else 2695 sc->sk_intrmask &= ~SK_INTRS2; 2696 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2697 2698 SK_XM_READ_2(sc_if, XM_ISR); 2699 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2700 2701 /* Free RX and TX mbufs still in the queues. */ 2702 for (i = 0; i < SK_RX_RING_CNT; i++) { 2703 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2704 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2705 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2706 } 2707 } 2708 2709 for (i = 0; i < SK_TX_RING_CNT; i++) { 2710 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2711 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2712 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2713 } 2714 } 2715 2716 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2717 SK_IF_UNLOCK(sc_if); 2718 return; 2719 } 2720