1 /* 2 * Copyright (c) 1997, 1998, 1999, 2000 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD$ 33 */ 34 35 /* 36 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 37 * the SK-984x series adapters, both single port and dual port. 38 * References: 39 * The XaQti XMAC II datasheet, 40 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 41 * The SysKonnect GEnesis manual, http://www.syskonnect.com 42 * 43 * Note: XaQti has been aquired by Vitesse, and Vitesse does not have the 44 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 45 * convenience to others until Vitesse corrects this problem: 46 * 47 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 48 * 49 * Written by Bill Paul <wpaul@ee.columbia.edu> 50 * Department of Electrical Engineering 51 * Columbia University, New York City 52 */ 53 54 /* 55 * The SysKonnect gigabit ethernet adapters consist of two main 56 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 57 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 58 * components and a PHY while the GEnesis controller provides a PCI 59 * interface with DMA support. Each card may have between 512K and 60 * 2MB of SRAM on board depending on the configuration. 61 * 62 * The SysKonnect GEnesis controller can have either one or two XMAC 63 * chips connected to it, allowing single or dual port NIC configurations. 64 * SysKonnect has the distinction of being the only vendor on the market 65 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 66 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 67 * XMAC registers. This driver takes advantage of these features to allow 68 * both XMACs to operate as independent interfaces. 69 */ 70 71 #include <sys/param.h> 72 #include <sys/systm.h> 73 #include <sys/sockio.h> 74 #include <sys/mbuf.h> 75 #include <sys/malloc.h> 76 #include <sys/kernel.h> 77 #include <sys/socket.h> 78 #include <sys/queue.h> 79 80 #include <net/if.h> 81 #include <net/if_arp.h> 82 #include <net/ethernet.h> 83 #include <net/if_dl.h> 84 #include <net/if_media.h> 85 86 #include <net/bpf.h> 87 88 #include <vm/vm.h> /* for vtophys */ 89 #include <vm/pmap.h> /* for vtophys */ 90 #include <machine/bus_pio.h> 91 #include <machine/bus_memio.h> 92 #include <machine/bus.h> 93 #include <machine/resource.h> 94 #include <sys/bus.h> 95 #include <sys/rman.h> 96 97 #include <dev/mii/mii.h> 98 #include <dev/mii/miivar.h> 99 #include <dev/mii/brgphyreg.h> 100 101 #include <pci/pcireg.h> 102 #include <pci/pcivar.h> 103 104 #define SK_USEIOSPACE 105 106 #include <pci/if_skreg.h> 107 #include <pci/xmaciireg.h> 108 109 MODULE_DEPEND(sk, miibus, 1, 1, 1); 110 111 /* "controller miibus0" required. See GENERIC if you get errors here. */ 112 #include "miibus_if.h" 113 114 #ifndef lint 115 static const char rcsid[] = 116 "$FreeBSD$"; 117 #endif 118 119 static struct sk_type sk_devs[] = { 120 { SK_VENDORID, SK_DEVICEID_GE, "SysKonnect Gigabit Ethernet" }, 121 { 0, 0, NULL } 122 }; 123 124 static int sk_probe __P((device_t)); 125 static int sk_attach __P((device_t)); 126 static int sk_detach __P((device_t)); 127 static int sk_detach_xmac __P((device_t)); 128 static int sk_probe_xmac __P((device_t)); 129 static int sk_attach_xmac __P((device_t)); 130 static void sk_tick __P((void *)); 131 static void sk_intr __P((void *)); 132 static void sk_intr_xmac __P((struct sk_if_softc *)); 133 static void sk_intr_bcom __P((struct sk_if_softc *)); 134 static void sk_rxeof __P((struct sk_if_softc *)); 135 static void sk_txeof __P((struct sk_if_softc *)); 136 static int sk_encap __P((struct sk_if_softc *, struct mbuf *, 137 u_int32_t *)); 138 static void sk_start __P((struct ifnet *)); 139 static int sk_ioctl __P((struct ifnet *, u_long, caddr_t)); 140 static void sk_init __P((void *)); 141 static void sk_init_xmac __P((struct sk_if_softc *)); 142 static void sk_stop __P((struct sk_if_softc *)); 143 static void sk_watchdog __P((struct ifnet *)); 144 static void sk_shutdown __P((device_t)); 145 static int sk_ifmedia_upd __P((struct ifnet *)); 146 static void sk_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 147 static void sk_reset __P((struct sk_softc *)); 148 static int sk_newbuf __P((struct sk_if_softc *, 149 struct sk_chain *, struct mbuf *)); 150 static int sk_alloc_jumbo_mem __P((struct sk_if_softc *)); 151 static void *sk_jalloc __P((struct sk_if_softc *)); 152 static void sk_jfree __P((caddr_t, void *)); 153 static int sk_init_rx_ring __P((struct sk_if_softc *)); 154 static void sk_init_tx_ring __P((struct sk_if_softc *)); 155 static u_int32_t sk_win_read_4 __P((struct sk_softc *, int)); 156 static u_int16_t sk_win_read_2 __P((struct sk_softc *, int)); 157 static u_int8_t sk_win_read_1 __P((struct sk_softc *, int)); 158 static void sk_win_write_4 __P((struct sk_softc *, int, u_int32_t)); 159 static void sk_win_write_2 __P((struct sk_softc *, int, u_int32_t)); 160 static void sk_win_write_1 __P((struct sk_softc *, int, u_int32_t)); 161 static u_int8_t sk_vpd_readbyte __P((struct sk_softc *, int)); 162 static void sk_vpd_read_res __P((struct sk_softc *, 163 struct vpd_res *, int)); 164 static void sk_vpd_read __P((struct sk_softc *)); 165 166 static int sk_miibus_readreg __P((device_t, int, int)); 167 static int sk_miibus_writereg __P((device_t, int, int, int)); 168 static void sk_miibus_statchg __P((device_t)); 169 170 static u_int32_t sk_calchash __P((caddr_t)); 171 static void sk_setfilt __P((struct sk_if_softc *, caddr_t, int)); 172 static void sk_setmulti __P((struct sk_if_softc *)); 173 174 #ifdef SK_USEIOSPACE 175 #define SK_RES SYS_RES_IOPORT 176 #define SK_RID SK_PCI_LOIO 177 #else 178 #define SK_RES SYS_RES_MEMORY 179 #define SK_RID SK_PCI_LOMEM 180 #endif 181 182 /* 183 * Note that we have newbus methods for both the GEnesis controller 184 * itself and the XMAC(s). The XMACs are children of the GEnesis, and 185 * the miibus code is a child of the XMACs. We need to do it this way 186 * so that the miibus drivers can access the PHY registers on the 187 * right PHY. It's not quite what I had in mind, but it's the only 188 * design that achieves the desired effect. 189 */ 190 static device_method_t skc_methods[] = { 191 /* Device interface */ 192 DEVMETHOD(device_probe, sk_probe), 193 DEVMETHOD(device_attach, sk_attach), 194 DEVMETHOD(device_detach, sk_detach), 195 DEVMETHOD(device_shutdown, sk_shutdown), 196 197 /* bus interface */ 198 DEVMETHOD(bus_print_child, bus_generic_print_child), 199 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 200 201 { 0, 0 } 202 }; 203 204 static driver_t skc_driver = { 205 "skc", 206 skc_methods, 207 sizeof(struct sk_softc) 208 }; 209 210 static devclass_t skc_devclass; 211 212 static device_method_t sk_methods[] = { 213 /* Device interface */ 214 DEVMETHOD(device_probe, sk_probe_xmac), 215 DEVMETHOD(device_attach, sk_attach_xmac), 216 DEVMETHOD(device_detach, sk_detach_xmac), 217 DEVMETHOD(device_shutdown, bus_generic_shutdown), 218 219 /* bus interface */ 220 DEVMETHOD(bus_print_child, bus_generic_print_child), 221 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 222 223 /* MII interface */ 224 DEVMETHOD(miibus_readreg, sk_miibus_readreg), 225 DEVMETHOD(miibus_writereg, sk_miibus_writereg), 226 DEVMETHOD(miibus_statchg, sk_miibus_statchg), 227 228 { 0, 0 } 229 }; 230 231 static driver_t sk_driver = { 232 "sk", 233 sk_methods, 234 sizeof(struct sk_if_softc) 235 }; 236 237 static devclass_t sk_devclass; 238 239 DRIVER_MODULE(if_sk, pci, skc_driver, skc_devclass, 0, 0); 240 DRIVER_MODULE(sk, skc, sk_driver, sk_devclass, 0, 0); 241 DRIVER_MODULE(miibus, sk, miibus_driver, miibus_devclass, 0, 0); 242 243 #define SK_SETBIT(sc, reg, x) \ 244 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 245 246 #define SK_CLRBIT(sc, reg, x) \ 247 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 248 249 #define SK_WIN_SETBIT_4(sc, reg, x) \ 250 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x) 251 252 #define SK_WIN_CLRBIT_4(sc, reg, x) \ 253 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x) 254 255 #define SK_WIN_SETBIT_2(sc, reg, x) \ 256 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x) 257 258 #define SK_WIN_CLRBIT_2(sc, reg, x) \ 259 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x) 260 261 static u_int32_t sk_win_read_4(sc, reg) 262 struct sk_softc *sc; 263 int reg; 264 { 265 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 266 return(CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg))); 267 } 268 269 static u_int16_t sk_win_read_2(sc, reg) 270 struct sk_softc *sc; 271 int reg; 272 { 273 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 274 return(CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg))); 275 } 276 277 static u_int8_t sk_win_read_1(sc, reg) 278 struct sk_softc *sc; 279 int reg; 280 { 281 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 282 return(CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg))); 283 } 284 285 static void sk_win_write_4(sc, reg, val) 286 struct sk_softc *sc; 287 int reg; 288 u_int32_t val; 289 { 290 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 291 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), val); 292 return; 293 } 294 295 static void sk_win_write_2(sc, reg, val) 296 struct sk_softc *sc; 297 int reg; 298 u_int32_t val; 299 { 300 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 301 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), (u_int32_t)val); 302 return; 303 } 304 305 static void sk_win_write_1(sc, reg, val) 306 struct sk_softc *sc; 307 int reg; 308 u_int32_t val; 309 { 310 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 311 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), val); 312 return; 313 } 314 315 /* 316 * The VPD EEPROM contains Vital Product Data, as suggested in 317 * the PCI 2.1 specification. The VPD data is separared into areas 318 * denoted by resource IDs. The SysKonnect VPD contains an ID string 319 * resource (the name of the adapter), a read-only area resource 320 * containing various key/data fields and a read/write area which 321 * can be used to store asset management information or log messages. 322 * We read the ID string and read-only into buffers attached to 323 * the controller softc structure for later use. At the moment, 324 * we only use the ID string during sk_attach(). 325 */ 326 static u_int8_t sk_vpd_readbyte(sc, addr) 327 struct sk_softc *sc; 328 int addr; 329 { 330 int i; 331 332 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 333 for (i = 0; i < SK_TIMEOUT; i++) { 334 DELAY(1); 335 if (sk_win_read_2(sc, 336 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 337 break; 338 } 339 340 if (i == SK_TIMEOUT) 341 return(0); 342 343 return(sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA))); 344 } 345 346 static void sk_vpd_read_res(sc, res, addr) 347 struct sk_softc *sc; 348 struct vpd_res *res; 349 int addr; 350 { 351 int i; 352 u_int8_t *ptr; 353 354 ptr = (u_int8_t *)res; 355 for (i = 0; i < sizeof(struct vpd_res); i++) 356 ptr[i] = sk_vpd_readbyte(sc, i + addr); 357 358 return; 359 } 360 361 static void sk_vpd_read(sc) 362 struct sk_softc *sc; 363 { 364 int pos = 0, i; 365 struct vpd_res res; 366 367 if (sc->sk_vpd_prodname != NULL) 368 free(sc->sk_vpd_prodname, M_DEVBUF); 369 if (sc->sk_vpd_readonly != NULL) 370 free(sc->sk_vpd_readonly, M_DEVBUF); 371 sc->sk_vpd_prodname = NULL; 372 sc->sk_vpd_readonly = NULL; 373 374 sk_vpd_read_res(sc, &res, pos); 375 376 if (res.vr_id != VPD_RES_ID) { 377 printf("skc%d: bad VPD resource id: expected %x got %x\n", 378 sc->sk_unit, VPD_RES_ID, res.vr_id); 379 return; 380 } 381 382 pos += sizeof(res); 383 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 384 for (i = 0; i < res.vr_len; i++) 385 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 386 sc->sk_vpd_prodname[i] = '\0'; 387 pos += i; 388 389 sk_vpd_read_res(sc, &res, pos); 390 391 if (res.vr_id != VPD_RES_READ) { 392 printf("skc%d: bad VPD resource id: expected %x got %x\n", 393 sc->sk_unit, VPD_RES_READ, res.vr_id); 394 return; 395 } 396 397 pos += sizeof(res); 398 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 399 for (i = 0; i < res.vr_len + 1; i++) 400 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 401 402 return; 403 } 404 405 static int sk_miibus_readreg(dev, phy, reg) 406 device_t dev; 407 int phy, reg; 408 { 409 struct sk_if_softc *sc_if; 410 int i; 411 412 sc_if = device_get_softc(dev); 413 414 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 415 return(0); 416 417 SK_IF_LOCK(sc_if); 418 419 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 420 SK_XM_READ_2(sc_if, XM_PHY_DATA); 421 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 422 for (i = 0; i < SK_TIMEOUT; i++) { 423 DELAY(1); 424 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 425 XM_MMUCMD_PHYDATARDY) 426 break; 427 } 428 429 if (i == SK_TIMEOUT) { 430 printf("sk%d: phy failed to come ready\n", 431 sc_if->sk_unit); 432 return(0); 433 } 434 } 435 DELAY(1); 436 i = SK_XM_READ_2(sc_if, XM_PHY_DATA); 437 SK_IF_UNLOCK(sc_if); 438 return(i); 439 } 440 441 static int sk_miibus_writereg(dev, phy, reg, val) 442 device_t dev; 443 int phy, reg, val; 444 { 445 struct sk_if_softc *sc_if; 446 int i; 447 448 sc_if = device_get_softc(dev); 449 SK_IF_LOCK(sc_if); 450 451 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 452 for (i = 0; i < SK_TIMEOUT; i++) { 453 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 454 break; 455 } 456 457 if (i == SK_TIMEOUT) { 458 printf("sk%d: phy failed to come ready\n", sc_if->sk_unit); 459 return(ETIMEDOUT); 460 } 461 462 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 463 for (i = 0; i < SK_TIMEOUT; i++) { 464 DELAY(1); 465 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 466 break; 467 } 468 469 SK_IF_UNLOCK(sc_if); 470 471 if (i == SK_TIMEOUT) 472 printf("sk%d: phy write timed out\n", sc_if->sk_unit); 473 474 return(0); 475 } 476 477 static void sk_miibus_statchg(dev) 478 device_t dev; 479 { 480 struct sk_if_softc *sc_if; 481 struct mii_data *mii; 482 483 sc_if = device_get_softc(dev); 484 mii = device_get_softc(sc_if->sk_miibus); 485 SK_IF_LOCK(sc_if); 486 /* 487 * If this is a GMII PHY, manually set the XMAC's 488 * duplex mode accordingly. 489 */ 490 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 491 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 492 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 493 } else { 494 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 495 } 496 } 497 SK_IF_UNLOCK(sc_if); 498 499 return; 500 } 501 502 #define SK_POLY 0xEDB88320 503 #define SK_BITS 6 504 505 static u_int32_t sk_calchash(addr) 506 caddr_t addr; 507 { 508 u_int32_t idx, bit, data, crc; 509 510 /* Compute CRC for the address value. */ 511 crc = 0xFFFFFFFF; /* initial value */ 512 513 for (idx = 0; idx < 6; idx++) { 514 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 515 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? SK_POLY : 0); 516 } 517 518 return (~crc & ((1 << SK_BITS) - 1)); 519 } 520 521 static void sk_setfilt(sc_if, addr, slot) 522 struct sk_if_softc *sc_if; 523 caddr_t addr; 524 int slot; 525 { 526 int base; 527 528 base = XM_RXFILT_ENTRY(slot); 529 530 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 531 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 532 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 533 534 return; 535 } 536 537 static void sk_setmulti(sc_if) 538 struct sk_if_softc *sc_if; 539 { 540 struct ifnet *ifp; 541 u_int32_t hashes[2] = { 0, 0 }; 542 int h, i; 543 struct ifmultiaddr *ifma; 544 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 545 546 ifp = &sc_if->arpcom.ac_if; 547 548 /* First, zot all the existing filters. */ 549 for (i = 1; i < XM_RXFILT_MAX; i++) 550 sk_setfilt(sc_if, (caddr_t)&dummy, i); 551 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 552 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 553 554 /* Now program new ones. */ 555 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 556 hashes[0] = 0xFFFFFFFF; 557 hashes[1] = 0xFFFFFFFF; 558 } else { 559 i = 1; 560 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, ifma_link) { 561 if (ifma->ifma_addr->sa_family != AF_LINK) 562 continue; 563 /* 564 * Program the first XM_RXFILT_MAX multicast groups 565 * into the perfect filter. For all others, 566 * use the hash table. 567 */ 568 if (i < XM_RXFILT_MAX) { 569 sk_setfilt(sc_if, 570 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i); 571 i++; 572 continue; 573 } 574 575 h = sk_calchash( 576 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 577 if (h < 32) 578 hashes[0] |= (1 << h); 579 else 580 hashes[1] |= (1 << (h - 32)); 581 } 582 } 583 584 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 585 XM_MODE_RX_USE_PERFECT); 586 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 587 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 588 589 return; 590 } 591 592 static int sk_init_rx_ring(sc_if) 593 struct sk_if_softc *sc_if; 594 { 595 struct sk_chain_data *cd; 596 struct sk_ring_data *rd; 597 int i; 598 599 cd = &sc_if->sk_cdata; 600 rd = sc_if->sk_rdata; 601 602 bzero((char *)rd->sk_rx_ring, 603 sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 604 605 for (i = 0; i < SK_RX_RING_CNT; i++) { 606 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 607 if (sk_newbuf(sc_if, &cd->sk_rx_chain[i], NULL) == ENOBUFS) 608 return(ENOBUFS); 609 if (i == (SK_RX_RING_CNT - 1)) { 610 cd->sk_rx_chain[i].sk_next = 611 &cd->sk_rx_chain[0]; 612 rd->sk_rx_ring[i].sk_next = 613 vtophys(&rd->sk_rx_ring[0]); 614 } else { 615 cd->sk_rx_chain[i].sk_next = 616 &cd->sk_rx_chain[i + 1]; 617 rd->sk_rx_ring[i].sk_next = 618 vtophys(&rd->sk_rx_ring[i + 1]); 619 } 620 } 621 622 sc_if->sk_cdata.sk_rx_prod = 0; 623 sc_if->sk_cdata.sk_rx_cons = 0; 624 625 return(0); 626 } 627 628 static void sk_init_tx_ring(sc_if) 629 struct sk_if_softc *sc_if; 630 { 631 struct sk_chain_data *cd; 632 struct sk_ring_data *rd; 633 int i; 634 635 cd = &sc_if->sk_cdata; 636 rd = sc_if->sk_rdata; 637 638 bzero((char *)sc_if->sk_rdata->sk_tx_ring, 639 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 640 641 for (i = 0; i < SK_TX_RING_CNT; i++) { 642 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 643 if (i == (SK_TX_RING_CNT - 1)) { 644 cd->sk_tx_chain[i].sk_next = 645 &cd->sk_tx_chain[0]; 646 rd->sk_tx_ring[i].sk_next = 647 vtophys(&rd->sk_tx_ring[0]); 648 } else { 649 cd->sk_tx_chain[i].sk_next = 650 &cd->sk_tx_chain[i + 1]; 651 rd->sk_tx_ring[i].sk_next = 652 vtophys(&rd->sk_tx_ring[i + 1]); 653 } 654 } 655 656 sc_if->sk_cdata.sk_tx_prod = 0; 657 sc_if->sk_cdata.sk_tx_cons = 0; 658 sc_if->sk_cdata.sk_tx_cnt = 0; 659 660 return; 661 } 662 663 static int sk_newbuf(sc_if, c, m) 664 struct sk_if_softc *sc_if; 665 struct sk_chain *c; 666 struct mbuf *m; 667 { 668 struct mbuf *m_new = NULL; 669 struct sk_rx_desc *r; 670 671 if (m == NULL) { 672 caddr_t *buf = NULL; 673 674 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 675 if (m_new == NULL) { 676 printf("sk%d: no memory for rx list -- " 677 "packet dropped!\n", sc_if->sk_unit); 678 return(ENOBUFS); 679 } 680 681 /* Allocate the jumbo buffer */ 682 buf = sk_jalloc(sc_if); 683 if (buf == NULL) { 684 m_freem(m_new); 685 #ifdef SK_VERBOSE 686 printf("sk%d: jumbo allocation failed " 687 "-- packet dropped!\n", sc_if->sk_unit); 688 #endif 689 return(ENOBUFS); 690 } 691 692 /* Attach the buffer to the mbuf */ 693 MEXTADD(m_new, buf, SK_JLEN, sk_jfree, 694 (struct sk_if_softc *)sc_if, 0, EXT_NET_DRV); 695 m_new->m_data = (void *)buf; 696 m_new->m_pkthdr.len = m_new->m_len = SK_JLEN; 697 } else { 698 /* 699 * We're re-using a previously allocated mbuf; 700 * be sure to re-init pointers and lengths to 701 * default values. 702 */ 703 m_new = m; 704 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 705 m_new->m_data = m_new->m_ext.ext_buf; 706 } 707 708 /* 709 * Adjust alignment so packet payload begins on a 710 * longword boundary. Mandatory for Alpha, useful on 711 * x86 too. 712 */ 713 m_adj(m_new, ETHER_ALIGN); 714 715 r = c->sk_desc; 716 c->sk_mbuf = m_new; 717 r->sk_data_lo = vtophys(mtod(m_new, caddr_t)); 718 r->sk_ctl = m_new->m_len | SK_RXSTAT; 719 720 return(0); 721 } 722 723 /* 724 * Allocate jumbo buffer storage. The SysKonnect adapters support 725 * "jumbograms" (9K frames), although SysKonnect doesn't currently 726 * use them in their drivers. In order for us to use them, we need 727 * large 9K receive buffers, however standard mbuf clusters are only 728 * 2048 bytes in size. Consequently, we need to allocate and manage 729 * our own jumbo buffer pool. Fortunately, this does not require an 730 * excessive amount of additional code. 731 */ 732 static int sk_alloc_jumbo_mem(sc_if) 733 struct sk_if_softc *sc_if; 734 { 735 caddr_t ptr; 736 register int i; 737 struct sk_jpool_entry *entry; 738 739 /* Grab a big chunk o' storage. */ 740 sc_if->sk_cdata.sk_jumbo_buf = contigmalloc(SK_JMEM, M_DEVBUF, 741 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 742 743 if (sc_if->sk_cdata.sk_jumbo_buf == NULL) { 744 printf("sk%d: no memory for jumbo buffers!\n", sc_if->sk_unit); 745 return(ENOBUFS); 746 } 747 748 SLIST_INIT(&sc_if->sk_jfree_listhead); 749 SLIST_INIT(&sc_if->sk_jinuse_listhead); 750 751 /* 752 * Now divide it up into 9K pieces and save the addresses 753 * in an array. 754 */ 755 ptr = sc_if->sk_cdata.sk_jumbo_buf; 756 for (i = 0; i < SK_JSLOTS; i++) { 757 sc_if->sk_cdata.sk_jslots[i] = ptr; 758 ptr += SK_JLEN; 759 entry = malloc(sizeof(struct sk_jpool_entry), 760 M_DEVBUF, M_NOWAIT); 761 if (entry == NULL) { 762 free(sc_if->sk_cdata.sk_jumbo_buf, M_DEVBUF); 763 sc_if->sk_cdata.sk_jumbo_buf = NULL; 764 printf("sk%d: no memory for jumbo " 765 "buffer queue!\n", sc_if->sk_unit); 766 return(ENOBUFS); 767 } 768 entry->slot = i; 769 SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 770 entry, jpool_entries); 771 } 772 773 return(0); 774 } 775 776 /* 777 * Allocate a jumbo buffer. 778 */ 779 static void *sk_jalloc(sc_if) 780 struct sk_if_softc *sc_if; 781 { 782 struct sk_jpool_entry *entry; 783 784 entry = SLIST_FIRST(&sc_if->sk_jfree_listhead); 785 786 if (entry == NULL) { 787 #ifdef SK_VERBOSE 788 printf("sk%d: no free jumbo buffers\n", sc_if->sk_unit); 789 #endif 790 return(NULL); 791 } 792 793 SLIST_REMOVE_HEAD(&sc_if->sk_jfree_listhead, jpool_entries); 794 SLIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 795 return(sc_if->sk_cdata.sk_jslots[entry->slot]); 796 } 797 798 /* 799 * Release a jumbo buffer. 800 */ 801 static void sk_jfree(buf, args) 802 caddr_t buf; 803 void *args; 804 { 805 struct sk_if_softc *sc_if; 806 int i; 807 struct sk_jpool_entry *entry; 808 809 /* Extract the softc struct pointer. */ 810 sc_if = (struct sk_if_softc *)args; 811 812 if (sc_if == NULL) 813 panic("sk_jfree: didn't get softc pointer!"); 814 815 /* calculate the slot this buffer belongs to */ 816 i = ((vm_offset_t)buf 817 - (vm_offset_t)sc_if->sk_cdata.sk_jumbo_buf) / SK_JLEN; 818 819 if ((i < 0) || (i >= SK_JSLOTS)) 820 panic("sk_jfree: asked to free buffer that we don't manage!"); 821 822 entry = SLIST_FIRST(&sc_if->sk_jinuse_listhead); 823 if (entry == NULL) 824 panic("sk_jfree: buffer not in use!"); 825 entry->slot = i; 826 SLIST_REMOVE_HEAD(&sc_if->sk_jinuse_listhead, jpool_entries); 827 SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, entry, jpool_entries); 828 829 return; 830 } 831 832 /* 833 * Set media options. 834 */ 835 static int sk_ifmedia_upd(ifp) 836 struct ifnet *ifp; 837 { 838 struct sk_if_softc *sc_if; 839 struct mii_data *mii; 840 841 sc_if = ifp->if_softc; 842 mii = device_get_softc(sc_if->sk_miibus); 843 sk_init(sc_if); 844 mii_mediachg(mii); 845 846 return(0); 847 } 848 849 /* 850 * Report current media status. 851 */ 852 static void sk_ifmedia_sts(ifp, ifmr) 853 struct ifnet *ifp; 854 struct ifmediareq *ifmr; 855 { 856 struct sk_if_softc *sc_if; 857 struct mii_data *mii; 858 859 sc_if = ifp->if_softc; 860 mii = device_get_softc(sc_if->sk_miibus); 861 862 mii_pollstat(mii); 863 ifmr->ifm_active = mii->mii_media_active; 864 ifmr->ifm_status = mii->mii_media_status; 865 866 return; 867 } 868 869 static int sk_ioctl(ifp, command, data) 870 struct ifnet *ifp; 871 u_long command; 872 caddr_t data; 873 { 874 struct sk_if_softc *sc_if = ifp->if_softc; 875 struct ifreq *ifr = (struct ifreq *) data; 876 int error = 0; 877 struct mii_data *mii; 878 879 SK_IF_LOCK(sc_if); 880 881 switch(command) { 882 case SIOCSIFADDR: 883 case SIOCGIFADDR: 884 error = ether_ioctl(ifp, command, data); 885 break; 886 case SIOCSIFMTU: 887 if (ifr->ifr_mtu > SK_JUMBO_MTU) 888 error = EINVAL; 889 else { 890 ifp->if_mtu = ifr->ifr_mtu; 891 sk_init(sc_if); 892 } 893 break; 894 case SIOCSIFFLAGS: 895 if (ifp->if_flags & IFF_UP) { 896 if (ifp->if_flags & IFF_RUNNING && 897 ifp->if_flags & IFF_PROMISC && 898 !(sc_if->sk_if_flags & IFF_PROMISC)) { 899 SK_XM_SETBIT_4(sc_if, XM_MODE, 900 XM_MODE_RX_PROMISC); 901 sk_setmulti(sc_if); 902 } else if (ifp->if_flags & IFF_RUNNING && 903 !(ifp->if_flags & IFF_PROMISC) && 904 sc_if->sk_if_flags & IFF_PROMISC) { 905 SK_XM_CLRBIT_4(sc_if, XM_MODE, 906 XM_MODE_RX_PROMISC); 907 sk_setmulti(sc_if); 908 } else 909 sk_init(sc_if); 910 } else { 911 if (ifp->if_flags & IFF_RUNNING) 912 sk_stop(sc_if); 913 } 914 sc_if->sk_if_flags = ifp->if_flags; 915 error = 0; 916 break; 917 case SIOCADDMULTI: 918 case SIOCDELMULTI: 919 sk_setmulti(sc_if); 920 error = 0; 921 break; 922 case SIOCGIFMEDIA: 923 case SIOCSIFMEDIA: 924 mii = device_get_softc(sc_if->sk_miibus); 925 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 926 break; 927 default: 928 error = EINVAL; 929 break; 930 } 931 932 SK_IF_UNLOCK(sc_if); 933 934 return(error); 935 } 936 937 /* 938 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 939 * IDs against our list and return a device name if we find a match. 940 */ 941 static int sk_probe(dev) 942 device_t dev; 943 { 944 struct sk_type *t; 945 946 t = sk_devs; 947 948 while(t->sk_name != NULL) { 949 if ((pci_get_vendor(dev) == t->sk_vid) && 950 (pci_get_device(dev) == t->sk_did)) { 951 device_set_desc(dev, t->sk_name); 952 return(0); 953 } 954 t++; 955 } 956 957 return(ENXIO); 958 } 959 960 /* 961 * Force the GEnesis into reset, then bring it out of reset. 962 */ 963 static void sk_reset(sc) 964 struct sk_softc *sc; 965 { 966 CSR_WRITE_4(sc, SK_CSR, SK_CSR_SW_RESET); 967 CSR_WRITE_4(sc, SK_CSR, SK_CSR_MASTER_RESET); 968 DELAY(1000); 969 CSR_WRITE_4(sc, SK_CSR, SK_CSR_SW_UNRESET); 970 CSR_WRITE_4(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 971 972 /* Configure packet arbiter */ 973 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 974 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 975 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 976 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 977 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 978 979 /* Enable RAM interface */ 980 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 981 982 /* 983 * Configure interrupt moderation. The moderation timer 984 * defers interrupts specified in the interrupt moderation 985 * timer mask based on the timeout specified in the interrupt 986 * moderation timer init register. Each bit in the timer 987 * register represents 18.825ns, so to specify a timeout in 988 * microseconds, we have to multiply by 54. 989 */ 990 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(200)); 991 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 992 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 993 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 994 995 return; 996 } 997 998 static int sk_probe_xmac(dev) 999 device_t dev; 1000 { 1001 /* 1002 * Not much to do here. We always know there will be 1003 * at least one XMAC present, and if there are two, 1004 * sk_attach() will create a second device instance 1005 * for us. 1006 */ 1007 device_set_desc(dev, "XaQti Corp. XMAC II"); 1008 1009 return(0); 1010 } 1011 1012 /* 1013 * Each XMAC chip is attached as a separate logical IP interface. 1014 * Single port cards will have only one logical interface of course. 1015 */ 1016 static int sk_attach_xmac(dev) 1017 device_t dev; 1018 { 1019 struct sk_softc *sc; 1020 struct sk_if_softc *sc_if; 1021 struct ifnet *ifp; 1022 int i, port; 1023 1024 if (dev == NULL) 1025 return(EINVAL); 1026 1027 sc_if = device_get_softc(dev); 1028 sc = device_get_softc(device_get_parent(dev)); 1029 SK_LOCK(sc); 1030 port = *(int *)device_get_ivars(dev); 1031 free(device_get_ivars(dev), M_DEVBUF); 1032 device_set_ivars(dev, NULL); 1033 sc_if->sk_dev = dev; 1034 1035 bzero((char *)sc_if, sizeof(struct sk_if_softc)); 1036 1037 sc_if->sk_dev = dev; 1038 sc_if->sk_unit = device_get_unit(dev); 1039 sc_if->sk_port = port; 1040 sc_if->sk_softc = sc; 1041 sc->sk_if[port] = sc_if; 1042 if (port == SK_PORT_A) 1043 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1044 if (port == SK_PORT_B) 1045 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1046 1047 /* 1048 * Get station address for this interface. Note that 1049 * dual port cards actually come with three station 1050 * addresses: one for each port, plus an extra. The 1051 * extra one is used by the SysKonnect driver software 1052 * as a 'virtual' station address for when both ports 1053 * are operating in failover mode. Currently we don't 1054 * use this extra address. 1055 */ 1056 for (i = 0; i < ETHER_ADDR_LEN; i++) 1057 sc_if->arpcom.ac_enaddr[i] = 1058 sk_win_read_1(sc, SK_MAC0_0 + (port * 8) + i); 1059 1060 printf("sk%d: Ethernet address: %6D\n", 1061 sc_if->sk_unit, sc_if->arpcom.ac_enaddr, ":"); 1062 1063 /* 1064 * Set up RAM buffer addresses. The NIC will have a certain 1065 * amount of SRAM on it, somewhere between 512K and 2MB. We 1066 * need to divide this up a) between the transmitter and 1067 * receiver and b) between the two XMACs, if this is a 1068 * dual port NIC. Our algotithm is to divide up the memory 1069 * evenly so that everyone gets a fair share. 1070 */ 1071 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1072 u_int32_t chunk, val; 1073 1074 chunk = sc->sk_ramsize / 2; 1075 val = sc->sk_rboff / sizeof(u_int64_t); 1076 sc_if->sk_rx_ramstart = val; 1077 val += (chunk / sizeof(u_int64_t)); 1078 sc_if->sk_rx_ramend = val - 1; 1079 sc_if->sk_tx_ramstart = val; 1080 val += (chunk / sizeof(u_int64_t)); 1081 sc_if->sk_tx_ramend = val - 1; 1082 } else { 1083 u_int32_t chunk, val; 1084 1085 chunk = sc->sk_ramsize / 4; 1086 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1087 sizeof(u_int64_t); 1088 sc_if->sk_rx_ramstart = val; 1089 val += (chunk / sizeof(u_int64_t)); 1090 sc_if->sk_rx_ramend = val - 1; 1091 sc_if->sk_tx_ramstart = val; 1092 val += (chunk / sizeof(u_int64_t)); 1093 sc_if->sk_tx_ramend = val - 1; 1094 } 1095 1096 /* Read and save PHY type and set PHY address */ 1097 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1098 switch(sc_if->sk_phytype) { 1099 case SK_PHYTYPE_XMAC: 1100 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1101 break; 1102 case SK_PHYTYPE_BCOM: 1103 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1104 break; 1105 default: 1106 printf("skc%d: unsupported PHY type: %d\n", 1107 sc->sk_unit, sc_if->sk_phytype); 1108 SK_UNLOCK(sc); 1109 return(ENODEV); 1110 } 1111 1112 /* Allocate the descriptor queues. */ 1113 sc_if->sk_rdata = contigmalloc(sizeof(struct sk_ring_data), M_DEVBUF, 1114 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1115 1116 if (sc_if->sk_rdata == NULL) { 1117 printf("sk%d: no memory for list buffers!\n", sc_if->sk_unit); 1118 sc->sk_if[port] = NULL; 1119 SK_UNLOCK(sc); 1120 return(ENOMEM); 1121 } 1122 1123 bzero(sc_if->sk_rdata, sizeof(struct sk_ring_data)); 1124 1125 /* Try to allocate memory for jumbo buffers. */ 1126 if (sk_alloc_jumbo_mem(sc_if)) { 1127 printf("sk%d: jumbo buffer allocation failed\n", 1128 sc_if->sk_unit); 1129 contigfree(sc_if->sk_rdata, 1130 sizeof(struct sk_ring_data), M_DEVBUF); 1131 sc->sk_if[port] = NULL; 1132 SK_UNLOCK(sc); 1133 return(ENOMEM); 1134 } 1135 1136 ifp = &sc_if->arpcom.ac_if; 1137 ifp->if_softc = sc_if; 1138 ifp->if_unit = sc_if->sk_unit; 1139 ifp->if_name = "sk"; 1140 ifp->if_mtu = ETHERMTU; 1141 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1142 ifp->if_ioctl = sk_ioctl; 1143 ifp->if_output = ether_output; 1144 ifp->if_start = sk_start; 1145 ifp->if_watchdog = sk_watchdog; 1146 ifp->if_init = sk_init; 1147 ifp->if_baudrate = 1000000000; 1148 ifp->if_snd.ifq_maxlen = SK_TX_RING_CNT - 1; 1149 1150 /* 1151 * Call MI attach routine. 1152 */ 1153 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 1154 callout_handle_init(&sc_if->sk_tick_ch); 1155 1156 /* 1157 * Do miibus setup. 1158 */ 1159 sk_init_xmac(sc_if); 1160 if (mii_phy_probe(dev, &sc_if->sk_miibus, 1161 sk_ifmedia_upd, sk_ifmedia_sts)) { 1162 printf("skc%d: no PHY found!\n", sc_if->sk_unit); 1163 contigfree(sc_if->sk_rdata, 1164 sizeof(struct sk_ring_data), M_DEVBUF); 1165 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 1166 SK_UNLOCK(sc); 1167 return(ENXIO); 1168 } 1169 1170 SK_UNLOCK(sc); 1171 1172 return(0); 1173 } 1174 1175 /* 1176 * Attach the interface. Allocate softc structures, do ifmedia 1177 * setup and ethernet/BPF attach. 1178 */ 1179 static int sk_attach(dev) 1180 device_t dev; 1181 { 1182 u_int32_t command; 1183 struct sk_softc *sc; 1184 int unit, error = 0, rid, *port; 1185 1186 sc = device_get_softc(dev); 1187 unit = device_get_unit(dev); 1188 bzero(sc, sizeof(struct sk_softc)); 1189 1190 mtx_init(&sc->sk_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE); 1191 SK_LOCK(sc); 1192 1193 /* 1194 * Handle power management nonsense. 1195 */ 1196 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1197 u_int32_t iobase, membase, irq; 1198 1199 /* Save important PCI config data. */ 1200 iobase = pci_read_config(dev, SK_PCI_LOIO, 4); 1201 membase = pci_read_config(dev, SK_PCI_LOMEM, 4); 1202 irq = pci_read_config(dev, SK_PCI_INTLINE, 4); 1203 1204 /* Reset the power state. */ 1205 printf("skc%d: chip is in D%d power mode " 1206 "-- setting to D0\n", unit, 1207 pci_get_powerstate(dev)); 1208 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1209 1210 /* Restore PCI config data. */ 1211 pci_write_config(dev, SK_PCI_LOIO, iobase, 4); 1212 pci_write_config(dev, SK_PCI_LOMEM, membase, 4); 1213 pci_write_config(dev, SK_PCI_INTLINE, irq, 4); 1214 } 1215 1216 /* 1217 * Map control/status registers. 1218 */ 1219 pci_enable_busmaster(dev); 1220 pci_enable_io(dev, PCIM_CMD_PORTEN); 1221 pci_enable_io(dev, PCIM_CMD_MEMEN); 1222 command = pci_read_config(dev, PCIR_COMMAND, 4); 1223 1224 #ifdef SK_USEIOSPACE 1225 if (!(command & PCIM_CMD_PORTEN)) { 1226 printf("skc%d: failed to enable I/O ports!\n", unit); 1227 error = ENXIO; 1228 goto fail; 1229 } 1230 #else 1231 if (!(command & PCIM_CMD_MEMEN)) { 1232 printf("skc%d: failed to enable memory mapping!\n", unit); 1233 error = ENXIO; 1234 goto fail; 1235 } 1236 #endif 1237 1238 rid = SK_RID; 1239 sc->sk_res = bus_alloc_resource(dev, SK_RES, &rid, 1240 0, ~0, 1, RF_ACTIVE); 1241 1242 if (sc->sk_res == NULL) { 1243 printf("sk%d: couldn't map ports/memory\n", unit); 1244 error = ENXIO; 1245 goto fail; 1246 } 1247 1248 sc->sk_btag = rman_get_bustag(sc->sk_res); 1249 sc->sk_bhandle = rman_get_bushandle(sc->sk_res); 1250 1251 /* Allocate interrupt */ 1252 rid = 0; 1253 sc->sk_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1254 RF_SHAREABLE | RF_ACTIVE); 1255 1256 if (sc->sk_irq == NULL) { 1257 printf("skc%d: couldn't map interrupt\n", unit); 1258 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res); 1259 error = ENXIO; 1260 goto fail; 1261 } 1262 1263 error = bus_setup_intr(dev, sc->sk_irq, INTR_TYPE_NET, 1264 sk_intr, sc, &sc->sk_intrhand); 1265 1266 if (error) { 1267 printf("skc%d: couldn't set up irq\n", unit); 1268 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res); 1269 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq); 1270 goto fail; 1271 } 1272 1273 /* Reset the adapter. */ 1274 sk_reset(sc); 1275 1276 sc->sk_unit = unit; 1277 1278 /* Read and save vital product data from EEPROM. */ 1279 sk_vpd_read(sc); 1280 1281 /* Read and save RAM size and RAMbuffer offset */ 1282 switch(sk_win_read_1(sc, SK_EPROM0)) { 1283 case SK_RAMSIZE_512K_64: 1284 sc->sk_ramsize = 0x80000; 1285 sc->sk_rboff = SK_RBOFF_0; 1286 break; 1287 case SK_RAMSIZE_1024K_64: 1288 sc->sk_ramsize = 0x100000; 1289 sc->sk_rboff = SK_RBOFF_80000; 1290 break; 1291 case SK_RAMSIZE_1024K_128: 1292 sc->sk_ramsize = 0x100000; 1293 sc->sk_rboff = SK_RBOFF_0; 1294 break; 1295 case SK_RAMSIZE_2048K_128: 1296 sc->sk_ramsize = 0x200000; 1297 sc->sk_rboff = SK_RBOFF_0; 1298 break; 1299 default: 1300 printf("skc%d: unknown ram size: %d\n", 1301 sc->sk_unit, sk_win_read_1(sc, SK_EPROM0)); 1302 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand); 1303 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq); 1304 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res); 1305 error = ENXIO; 1306 goto fail; 1307 break; 1308 } 1309 1310 /* Read and save physical media type */ 1311 switch(sk_win_read_1(sc, SK_PMDTYPE)) { 1312 case SK_PMD_1000BASESX: 1313 sc->sk_pmd = IFM_1000_SX; 1314 break; 1315 case SK_PMD_1000BASELX: 1316 sc->sk_pmd = IFM_1000_LX; 1317 break; 1318 case SK_PMD_1000BASECX: 1319 sc->sk_pmd = IFM_1000_CX; 1320 break; 1321 case SK_PMD_1000BASETX: 1322 sc->sk_pmd = IFM_1000_TX; 1323 break; 1324 default: 1325 printf("skc%d: unknown media type: 0x%x\n", 1326 sc->sk_unit, sk_win_read_1(sc, SK_PMDTYPE)); 1327 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand); 1328 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq); 1329 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res); 1330 error = ENXIO; 1331 goto fail; 1332 } 1333 1334 /* Announce the product name. */ 1335 printf("skc%d: %s\n", sc->sk_unit, sc->sk_vpd_prodname); 1336 sc->sk_devs[SK_PORT_A] = device_add_child(dev, "sk", -1); 1337 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT); 1338 *port = SK_PORT_A; 1339 device_set_ivars(sc->sk_devs[SK_PORT_A], port); 1340 1341 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1342 sc->sk_devs[SK_PORT_B] = device_add_child(dev, "sk", -1); 1343 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT); 1344 *port = SK_PORT_B; 1345 device_set_ivars(sc->sk_devs[SK_PORT_B], port); 1346 } 1347 1348 /* Turn on the 'driver is loaded' LED. */ 1349 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1350 1351 bus_generic_attach(dev); 1352 SK_UNLOCK(sc); 1353 return(0); 1354 1355 fail: 1356 SK_UNLOCK(sc); 1357 mtx_destroy(&sc->sk_mtx); 1358 return(error); 1359 } 1360 1361 static int sk_detach_xmac(dev) 1362 device_t dev; 1363 { 1364 struct sk_softc *sc; 1365 struct sk_if_softc *sc_if; 1366 struct ifnet *ifp; 1367 1368 sc = device_get_softc(device_get_parent(dev)); 1369 sc_if = device_get_softc(dev); 1370 SK_IF_LOCK(sc_if); 1371 1372 ifp = &sc_if->arpcom.ac_if; 1373 sk_stop(sc_if); 1374 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 1375 bus_generic_detach(dev); 1376 if (sc_if->sk_miibus != NULL) 1377 device_delete_child(dev, sc_if->sk_miibus); 1378 contigfree(sc_if->sk_cdata.sk_jumbo_buf, SK_JMEM, M_DEVBUF); 1379 contigfree(sc_if->sk_rdata, sizeof(struct sk_ring_data), M_DEVBUF); 1380 SK_IF_UNLOCK(sc_if); 1381 1382 return(0); 1383 } 1384 1385 static int sk_detach(dev) 1386 device_t dev; 1387 { 1388 struct sk_softc *sc; 1389 1390 sc = device_get_softc(dev); 1391 SK_LOCK(sc); 1392 1393 bus_generic_detach(dev); 1394 if (sc->sk_devs[SK_PORT_A] != NULL) 1395 device_delete_child(dev, sc->sk_devs[SK_PORT_A]); 1396 if (sc->sk_devs[SK_PORT_B] != NULL) 1397 device_delete_child(dev, sc->sk_devs[SK_PORT_B]); 1398 1399 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand); 1400 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq); 1401 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res); 1402 1403 SK_UNLOCK(sc); 1404 mtx_destroy(&sc->sk_mtx); 1405 1406 return(0); 1407 } 1408 1409 static int sk_encap(sc_if, m_head, txidx) 1410 struct sk_if_softc *sc_if; 1411 struct mbuf *m_head; 1412 u_int32_t *txidx; 1413 { 1414 struct sk_tx_desc *f = NULL; 1415 struct mbuf *m; 1416 u_int32_t frag, cur, cnt = 0; 1417 1418 m = m_head; 1419 cur = frag = *txidx; 1420 1421 /* 1422 * Start packing the mbufs in this chain into 1423 * the fragment pointers. Stop when we run out 1424 * of fragments or hit the end of the mbuf chain. 1425 */ 1426 for (m = m_head; m != NULL; m = m->m_next) { 1427 if (m->m_len != 0) { 1428 if ((SK_TX_RING_CNT - 1429 (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) 1430 return(ENOBUFS); 1431 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1432 f->sk_data_lo = vtophys(mtod(m, vm_offset_t)); 1433 f->sk_ctl = m->m_len | SK_OPCODE_DEFAULT; 1434 if (cnt == 0) 1435 f->sk_ctl |= SK_TXCTL_FIRSTFRAG; 1436 else 1437 f->sk_ctl |= SK_TXCTL_OWN; 1438 cur = frag; 1439 SK_INC(frag, SK_TX_RING_CNT); 1440 cnt++; 1441 } 1442 } 1443 1444 if (m != NULL) 1445 return(ENOBUFS); 1446 1447 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1448 SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR; 1449 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1450 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= SK_TXCTL_OWN; 1451 sc_if->sk_cdata.sk_tx_cnt += cnt; 1452 1453 *txidx = frag; 1454 1455 return(0); 1456 } 1457 1458 static void sk_start(ifp) 1459 struct ifnet *ifp; 1460 { 1461 struct sk_softc *sc; 1462 struct sk_if_softc *sc_if; 1463 struct mbuf *m_head = NULL; 1464 u_int32_t idx; 1465 1466 sc_if = ifp->if_softc; 1467 sc = sc_if->sk_softc; 1468 1469 SK_IF_LOCK(sc_if); 1470 1471 idx = sc_if->sk_cdata.sk_tx_prod; 1472 1473 while(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1474 IF_DEQUEUE(&ifp->if_snd, m_head); 1475 if (m_head == NULL) 1476 break; 1477 1478 /* 1479 * Pack the data into the transmit ring. If we 1480 * don't have room, set the OACTIVE flag and wait 1481 * for the NIC to drain the ring. 1482 */ 1483 if (sk_encap(sc_if, m_head, &idx)) { 1484 IF_PREPEND(&ifp->if_snd, m_head); 1485 ifp->if_flags |= IFF_OACTIVE; 1486 break; 1487 } 1488 1489 /* 1490 * If there's a BPF listener, bounce a copy of this frame 1491 * to him. 1492 */ 1493 if (ifp->if_bpf) 1494 bpf_mtap(ifp, m_head); 1495 } 1496 1497 /* Transmit */ 1498 sc_if->sk_cdata.sk_tx_prod = idx; 1499 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1500 1501 /* Set a timeout in case the chip goes out to lunch. */ 1502 ifp->if_timer = 5; 1503 SK_IF_UNLOCK(sc_if); 1504 1505 return; 1506 } 1507 1508 1509 static void sk_watchdog(ifp) 1510 struct ifnet *ifp; 1511 { 1512 struct sk_if_softc *sc_if; 1513 1514 sc_if = ifp->if_softc; 1515 1516 printf("sk%d: watchdog timeout\n", sc_if->sk_unit); 1517 sk_init(sc_if); 1518 1519 return; 1520 } 1521 1522 static void sk_shutdown(dev) 1523 device_t dev; 1524 { 1525 struct sk_softc *sc; 1526 1527 sc = device_get_softc(dev); 1528 SK_LOCK(sc); 1529 1530 /* Turn off the 'driver is loaded' LED. */ 1531 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1532 1533 /* 1534 * Reset the GEnesis controller. Doing this should also 1535 * assert the resets on the attached XMAC(s). 1536 */ 1537 sk_reset(sc); 1538 SK_UNLOCK(sc); 1539 1540 return; 1541 } 1542 1543 static void sk_rxeof(sc_if) 1544 struct sk_if_softc *sc_if; 1545 { 1546 struct ether_header *eh; 1547 struct mbuf *m; 1548 struct ifnet *ifp; 1549 struct sk_chain *cur_rx; 1550 int total_len = 0; 1551 int i; 1552 u_int32_t rxstat; 1553 1554 ifp = &sc_if->arpcom.ac_if; 1555 i = sc_if->sk_cdata.sk_rx_prod; 1556 cur_rx = &sc_if->sk_cdata.sk_rx_chain[i]; 1557 1558 while(!(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl & SK_RXCTL_OWN)) { 1559 1560 cur_rx = &sc_if->sk_cdata.sk_rx_chain[i]; 1561 rxstat = sc_if->sk_rdata->sk_rx_ring[i].sk_xmac_rxstat; 1562 m = cur_rx->sk_mbuf; 1563 cur_rx->sk_mbuf = NULL; 1564 total_len = SK_RXBYTES(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl); 1565 SK_INC(i, SK_RX_RING_CNT); 1566 1567 if (rxstat & XM_RXSTAT_ERRFRAME) { 1568 ifp->if_ierrors++; 1569 sk_newbuf(sc_if, cur_rx, m); 1570 continue; 1571 } 1572 1573 /* 1574 * Try to allocate a new jumbo buffer. If that 1575 * fails, copy the packet to mbufs and put the 1576 * jumbo buffer back in the ring so it can be 1577 * re-used. If allocating mbufs fails, then we 1578 * have to drop the packet. 1579 */ 1580 if (sk_newbuf(sc_if, cur_rx, NULL) == ENOBUFS) { 1581 struct mbuf *m0; 1582 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, 1583 ifp, NULL); 1584 sk_newbuf(sc_if, cur_rx, m); 1585 if (m0 == NULL) { 1586 printf("sk%d: no receive buffers " 1587 "available -- packet dropped!\n", 1588 sc_if->sk_unit); 1589 ifp->if_ierrors++; 1590 continue; 1591 } 1592 m = m0; 1593 } else { 1594 m->m_pkthdr.rcvif = ifp; 1595 m->m_pkthdr.len = m->m_len = total_len; 1596 } 1597 1598 ifp->if_ipackets++; 1599 eh = mtod(m, struct ether_header *); 1600 1601 /* Remove header from mbuf and pass it on. */ 1602 m_adj(m, sizeof(struct ether_header)); 1603 ether_input(ifp, eh, m); 1604 } 1605 1606 sc_if->sk_cdata.sk_rx_prod = i; 1607 1608 return; 1609 } 1610 1611 static void sk_txeof(sc_if) 1612 struct sk_if_softc *sc_if; 1613 { 1614 struct sk_tx_desc *cur_tx = NULL; 1615 struct ifnet *ifp; 1616 u_int32_t idx; 1617 1618 ifp = &sc_if->arpcom.ac_if; 1619 1620 /* 1621 * Go through our tx ring and free mbufs for those 1622 * frames that have been sent. 1623 */ 1624 idx = sc_if->sk_cdata.sk_tx_cons; 1625 while(idx != sc_if->sk_cdata.sk_tx_prod) { 1626 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 1627 if (cur_tx->sk_ctl & SK_TXCTL_OWN) 1628 break; 1629 if (cur_tx->sk_ctl & SK_TXCTL_LASTFRAG) 1630 ifp->if_opackets++; 1631 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 1632 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 1633 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 1634 } 1635 sc_if->sk_cdata.sk_tx_cnt--; 1636 SK_INC(idx, SK_TX_RING_CNT); 1637 ifp->if_timer = 0; 1638 } 1639 1640 sc_if->sk_cdata.sk_tx_cons = idx; 1641 1642 if (cur_tx != NULL) 1643 ifp->if_flags &= ~IFF_OACTIVE; 1644 1645 return; 1646 } 1647 1648 static void sk_tick(xsc_if) 1649 void *xsc_if; 1650 { 1651 struct sk_if_softc *sc_if; 1652 struct mii_data *mii; 1653 struct ifnet *ifp; 1654 int i; 1655 1656 sc_if = xsc_if; 1657 SK_IF_LOCK(sc_if); 1658 ifp = &sc_if->arpcom.ac_if; 1659 mii = device_get_softc(sc_if->sk_miibus); 1660 1661 if (!(ifp->if_flags & IFF_UP)) { 1662 SK_IF_UNLOCK(sc_if); 1663 return; 1664 } 1665 1666 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 1667 sk_intr_bcom(sc_if); 1668 SK_IF_UNLOCK(sc_if); 1669 return; 1670 } 1671 1672 /* 1673 * According to SysKonnect, the correct way to verify that 1674 * the link has come back up is to poll bit 0 of the GPIO 1675 * register three times. This pin has the signal from the 1676 * link_sync pin connected to it; if we read the same link 1677 * state 3 times in a row, we know the link is up. 1678 */ 1679 for (i = 0; i < 3; i++) { 1680 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 1681 break; 1682 } 1683 1684 if (i != 3) { 1685 sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz); 1686 SK_IF_UNLOCK(sc_if); 1687 return; 1688 } 1689 1690 /* Turn the GP0 interrupt back on. */ 1691 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 1692 SK_XM_READ_2(sc_if, XM_ISR); 1693 mii_tick(mii); 1694 mii_pollstat(mii); 1695 untimeout(sk_tick, sc_if, sc_if->sk_tick_ch); 1696 1697 SK_IF_UNLOCK(sc_if); 1698 return; 1699 } 1700 1701 static void sk_intr_bcom(sc_if) 1702 struct sk_if_softc *sc_if; 1703 { 1704 struct sk_softc *sc; 1705 struct mii_data *mii; 1706 struct ifnet *ifp; 1707 int status; 1708 1709 sc = sc_if->sk_softc; 1710 mii = device_get_softc(sc_if->sk_miibus); 1711 ifp = &sc_if->arpcom.ac_if; 1712 1713 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 1714 1715 /* 1716 * Read the PHY interrupt register to make sure 1717 * we clear any pending interrupts. 1718 */ 1719 status = sk_miibus_readreg(sc_if->sk_dev, 1720 SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 1721 1722 if (!(ifp->if_flags & IFF_RUNNING)) { 1723 sk_init_xmac(sc_if); 1724 return; 1725 } 1726 1727 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 1728 int lstat; 1729 lstat = sk_miibus_readreg(sc_if->sk_dev, 1730 SK_PHYADDR_BCOM, BRGPHY_MII_AUXSTS); 1731 1732 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 1733 mii_mediachg(mii); 1734 /* Turn off the link LED. */ 1735 SK_IF_WRITE_1(sc_if, 0, 1736 SK_LINKLED1_CTL, SK_LINKLED_OFF); 1737 sc_if->sk_link = 0; 1738 } else if (status & BRGPHY_ISR_LNK_CHG) { 1739 sk_miibus_writereg(sc_if->sk_dev, SK_PHYADDR_BCOM, 1740 BRGPHY_MII_IMR, 0xFF00); 1741 mii_tick(mii); 1742 sc_if->sk_link = 1; 1743 /* Turn on the link LED. */ 1744 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 1745 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 1746 SK_LINKLED_BLINK_OFF); 1747 mii_pollstat(mii); 1748 } else { 1749 mii_tick(mii); 1750 sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz); 1751 } 1752 } 1753 1754 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 1755 1756 return; 1757 } 1758 1759 static void sk_intr_xmac(sc_if) 1760 struct sk_if_softc *sc_if; 1761 { 1762 struct sk_softc *sc; 1763 u_int16_t status; 1764 struct mii_data *mii; 1765 1766 sc = sc_if->sk_softc; 1767 mii = device_get_softc(sc_if->sk_miibus); 1768 status = SK_XM_READ_2(sc_if, XM_ISR); 1769 1770 /* 1771 * Link has gone down. Start MII tick timeout to 1772 * watch for link resync. 1773 */ 1774 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 1775 if (status & XM_ISR_GP0_SET) { 1776 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 1777 sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz); 1778 } 1779 1780 if (status & XM_ISR_AUTONEG_DONE) { 1781 sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz); 1782 } 1783 } 1784 1785 if (status & XM_IMR_TX_UNDERRUN) 1786 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 1787 1788 if (status & XM_IMR_RX_OVERRUN) 1789 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 1790 1791 status = SK_XM_READ_2(sc_if, XM_ISR); 1792 1793 return; 1794 } 1795 1796 static void sk_intr(xsc) 1797 void *xsc; 1798 { 1799 struct sk_softc *sc = xsc; 1800 struct sk_if_softc *sc_if0 = NULL, *sc_if1 = NULL; 1801 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 1802 u_int32_t status; 1803 1804 SK_LOCK(sc); 1805 1806 sc_if0 = sc->sk_if[SK_PORT_A]; 1807 sc_if1 = sc->sk_if[SK_PORT_B]; 1808 1809 if (sc_if0 != NULL) 1810 ifp0 = &sc_if0->arpcom.ac_if; 1811 if (sc_if1 != NULL) 1812 ifp1 = &sc_if1->arpcom.ac_if; 1813 1814 for (;;) { 1815 status = CSR_READ_4(sc, SK_ISSR); 1816 if (!(status & sc->sk_intrmask)) 1817 break; 1818 1819 /* Handle receive interrupts first. */ 1820 if (status & SK_ISR_RX1_EOF) { 1821 sk_rxeof(sc_if0); 1822 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 1823 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 1824 } 1825 if (status & SK_ISR_RX2_EOF) { 1826 sk_rxeof(sc_if1); 1827 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 1828 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 1829 } 1830 1831 /* Then transmit interrupts. */ 1832 if (status & SK_ISR_TX1_S_EOF) { 1833 sk_txeof(sc_if0); 1834 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 1835 SK_TXBMU_CLR_IRQ_EOF); 1836 } 1837 if (status & SK_ISR_TX2_S_EOF) { 1838 sk_txeof(sc_if1); 1839 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 1840 SK_TXBMU_CLR_IRQ_EOF); 1841 } 1842 1843 /* Then MAC interrupts. */ 1844 if (status & SK_ISR_MAC1 && 1845 ifp0->if_flags & IFF_RUNNING) 1846 sk_intr_xmac(sc_if0); 1847 1848 if (status & SK_ISR_MAC2 && 1849 ifp1->if_flags & IFF_RUNNING) 1850 sk_intr_xmac(sc_if1); 1851 1852 if (status & SK_ISR_EXTERNAL_REG) { 1853 if (ifp0 != NULL) 1854 sk_intr_bcom(sc_if0); 1855 if (ifp1 != NULL) 1856 sk_intr_bcom(sc_if1); 1857 } 1858 } 1859 1860 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 1861 1862 if (ifp0 != NULL && ifp0->if_snd.ifq_head != NULL) 1863 sk_start(ifp0); 1864 if (ifp1 != NULL && ifp1->if_snd.ifq_head != NULL) 1865 sk_start(ifp1); 1866 1867 SK_UNLOCK(sc); 1868 1869 return; 1870 } 1871 1872 static void sk_init_xmac(sc_if) 1873 struct sk_if_softc *sc_if; 1874 { 1875 struct sk_softc *sc; 1876 struct ifnet *ifp; 1877 struct sk_bcom_hack bhack[] = { 1878 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 1879 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 1880 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 1881 { 0, 0 } }; 1882 1883 sc = sc_if->sk_softc; 1884 ifp = &sc_if->arpcom.ac_if; 1885 1886 /* Unreset the XMAC. */ 1887 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 1888 DELAY(1000); 1889 1890 /* Reset the XMAC's internal state. */ 1891 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 1892 1893 /* Save the XMAC II revision */ 1894 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 1895 1896 /* 1897 * Perform additional initialization for external PHYs, 1898 * namely for the 1000baseTX cards that use the XMAC's 1899 * GMII mode. 1900 */ 1901 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 1902 int i = 0; 1903 u_int32_t val; 1904 1905 /* Take PHY out of reset. */ 1906 val = sk_win_read_4(sc, SK_GPIO); 1907 if (sc_if->sk_port == SK_PORT_A) 1908 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 1909 else 1910 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 1911 sk_win_write_4(sc, SK_GPIO, val); 1912 1913 /* Enable GMII mode on the XMAC. */ 1914 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 1915 1916 sk_miibus_writereg(sc_if->sk_dev, SK_PHYADDR_BCOM, 1917 BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET); 1918 DELAY(10000); 1919 sk_miibus_writereg(sc_if->sk_dev, SK_PHYADDR_BCOM, 1920 BRGPHY_MII_IMR, 0xFFF0); 1921 1922 /* 1923 * Early versions of the BCM5400 apparently have 1924 * a bug that requires them to have their reserved 1925 * registers initialized to some magic values. I don't 1926 * know what the numbers do, I'm just the messenger. 1927 */ 1928 if (sk_miibus_readreg(sc_if->sk_dev, 1929 SK_PHYADDR_BCOM, 0x03) == 0x6041) { 1930 while(bhack[i].reg) { 1931 sk_miibus_writereg(sc_if->sk_dev, 1932 SK_PHYADDR_BCOM, bhack[i].reg, 1933 bhack[i].val); 1934 i++; 1935 } 1936 } 1937 } 1938 1939 /* Set station address */ 1940 SK_XM_WRITE_2(sc_if, XM_PAR0, 1941 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[0])); 1942 SK_XM_WRITE_2(sc_if, XM_PAR1, 1943 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[2])); 1944 SK_XM_WRITE_2(sc_if, XM_PAR2, 1945 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[4])); 1946 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 1947 1948 if (ifp->if_flags & IFF_PROMISC) { 1949 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 1950 } else { 1951 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 1952 } 1953 1954 if (ifp->if_flags & IFF_BROADCAST) { 1955 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 1956 } else { 1957 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 1958 } 1959 1960 /* We don't need the FCS appended to the packet. */ 1961 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 1962 1963 /* We want short frames padded to 60 bytes. */ 1964 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 1965 1966 /* 1967 * Enable the reception of all error frames. This is is 1968 * a necessary evil due to the design of the XMAC. The 1969 * XMAC's receive FIFO is only 8K in size, however jumbo 1970 * frames can be up to 9000 bytes in length. When bad 1971 * frame filtering is enabled, the XMAC's RX FIFO operates 1972 * in 'store and forward' mode. For this to work, the 1973 * entire frame has to fit into the FIFO, but that means 1974 * that jumbo frames larger than 8192 bytes will be 1975 * truncated. Disabling all bad frame filtering causes 1976 * the RX FIFO to operate in streaming mode, in which 1977 * case the XMAC will start transfering frames out of the 1978 * RX FIFO as soon as the FIFO threshold is reached. 1979 */ 1980 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 1981 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 1982 XM_MODE_RX_INRANGELEN); 1983 1984 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 1985 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 1986 else 1987 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 1988 1989 /* 1990 * Bump up the transmit threshold. This helps hold off transmit 1991 * underruns when we're blasting traffic from both ports at once. 1992 */ 1993 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 1994 1995 /* Set multicast filter */ 1996 sk_setmulti(sc_if); 1997 1998 /* Clear and enable interrupts */ 1999 SK_XM_READ_2(sc_if, XM_ISR); 2000 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2001 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2002 else 2003 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2004 2005 /* Configure MAC arbiter */ 2006 switch(sc_if->sk_xmac_rev) { 2007 case XM_XMAC_REV_B2: 2008 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2009 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2010 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2011 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2012 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2013 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2014 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2015 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2016 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2017 break; 2018 case XM_XMAC_REV_C1: 2019 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2020 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2021 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2022 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2023 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2024 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2025 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2026 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2027 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2028 break; 2029 default: 2030 break; 2031 } 2032 sk_win_write_2(sc, SK_MACARB_CTL, 2033 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 2034 2035 sc_if->sk_link = 1; 2036 2037 return; 2038 } 2039 2040 /* 2041 * Note that to properly initialize any part of the GEnesis chip, 2042 * you first have to take it out of reset mode. 2043 */ 2044 static void sk_init(xsc) 2045 void *xsc; 2046 { 2047 struct sk_if_softc *sc_if = xsc; 2048 struct sk_softc *sc; 2049 struct ifnet *ifp; 2050 struct mii_data *mii; 2051 2052 SK_IF_LOCK(sc_if); 2053 2054 ifp = &sc_if->arpcom.ac_if; 2055 sc = sc_if->sk_softc; 2056 mii = device_get_softc(sc_if->sk_miibus); 2057 2058 /* Cancel pending I/O and free all RX/TX buffers. */ 2059 sk_stop(sc_if); 2060 2061 /* Configure LINK_SYNC LED */ 2062 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2063 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_ON); 2064 2065 /* Configure RX LED */ 2066 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_START); 2067 2068 /* Configure TX LED */ 2069 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_TXLEDCTL_COUNTER_START); 2070 2071 /* Configure I2C registers */ 2072 2073 /* Configure XMAC(s) */ 2074 sk_init_xmac(sc_if); 2075 mii_mediachg(mii); 2076 2077 /* Configure MAC FIFOs */ 2078 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2079 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2080 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2081 2082 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2083 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2084 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2085 2086 /* Configure transmit arbiter(s) */ 2087 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2088 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2089 2090 /* Configure RAMbuffers */ 2091 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2092 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2093 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2094 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2095 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2096 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2097 2098 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2099 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2100 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2101 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2102 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2103 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2104 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2105 2106 /* Configure BMUs */ 2107 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2108 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2109 vtophys(&sc_if->sk_rdata->sk_rx_ring[0])); 2110 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2111 2112 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2113 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2114 vtophys(&sc_if->sk_rdata->sk_tx_ring[0])); 2115 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2116 2117 /* Init descriptors */ 2118 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2119 printf("sk%d: initialization failed: no " 2120 "memory for rx buffers\n", sc_if->sk_unit); 2121 sk_stop(sc_if); 2122 SK_IF_UNLOCK(sc_if); 2123 return; 2124 } 2125 sk_init_tx_ring(sc_if); 2126 2127 /* Configure interrupt handling */ 2128 CSR_READ_4(sc, SK_ISSR); 2129 if (sc_if->sk_port == SK_PORT_A) 2130 sc->sk_intrmask |= SK_INTRS1; 2131 else 2132 sc->sk_intrmask |= SK_INTRS2; 2133 2134 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2135 2136 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2137 2138 /* Start BMUs. */ 2139 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2140 2141 /* Enable XMACs TX and RX state machines */ 2142 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2143 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2144 2145 ifp->if_flags |= IFF_RUNNING; 2146 ifp->if_flags &= ~IFF_OACTIVE; 2147 2148 SK_IF_UNLOCK(sc_if); 2149 2150 return; 2151 } 2152 2153 static void sk_stop(sc_if) 2154 struct sk_if_softc *sc_if; 2155 { 2156 int i; 2157 struct sk_softc *sc; 2158 struct ifnet *ifp; 2159 2160 SK_IF_LOCK(sc_if); 2161 sc = sc_if->sk_softc; 2162 ifp = &sc_if->arpcom.ac_if; 2163 2164 untimeout(sk_tick, sc_if, sc_if->sk_tick_ch); 2165 2166 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2167 u_int32_t val; 2168 2169 /* Put PHY back into reset. */ 2170 val = sk_win_read_4(sc, SK_GPIO); 2171 if (sc_if->sk_port == SK_PORT_A) { 2172 val |= SK_GPIO_DIR0; 2173 val &= ~SK_GPIO_DAT0; 2174 } else { 2175 val |= SK_GPIO_DIR2; 2176 val &= ~SK_GPIO_DAT2; 2177 } 2178 sk_win_write_4(sc, SK_GPIO, val); 2179 } 2180 2181 /* Turn off various components of this interface. */ 2182 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2183 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_RESET); 2184 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2185 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2186 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2187 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2188 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2189 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2190 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2191 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2192 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2193 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2194 2195 /* Disable interrupts */ 2196 if (sc_if->sk_port == SK_PORT_A) 2197 sc->sk_intrmask &= ~SK_INTRS1; 2198 else 2199 sc->sk_intrmask &= ~SK_INTRS2; 2200 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2201 2202 SK_XM_READ_2(sc_if, XM_ISR); 2203 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2204 2205 /* Free RX and TX mbufs still in the queues. */ 2206 for (i = 0; i < SK_RX_RING_CNT; i++) { 2207 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2208 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2209 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2210 } 2211 } 2212 2213 for (i = 0; i < SK_TX_RING_CNT; i++) { 2214 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2215 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2216 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2217 } 2218 } 2219 2220 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2221 SK_IF_UNLOCK(sc_if); 2222 return; 2223 } 2224