xref: /freebsd/sys/dev/sk/if_sk.c (revision 5022f21bd974c740b9052f149fb31745dc602965)
1 /*	$OpenBSD: if_sk.c,v 2.33 2003/08/12 05:23:06 nate Exp $	*/
2 
3 /*-
4  * Copyright (c) 1997, 1998, 1999, 2000
5  *	Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  * 3. All advertising materials mentioning features or use of this software
16  *    must display the following acknowledgement:
17  *	This product includes software developed by Bill Paul.
18  * 4. Neither the name of the author nor the names of any co-contributors
19  *    may be used to endorse or promote products derived from this software
20  *    without specific prior written permission.
21  *
22  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32  * THE POSSIBILITY OF SUCH DAMAGE.
33  */
34 /*-
35  * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu>
36  *
37  * Permission to use, copy, modify, and distribute this software for any
38  * purpose with or without fee is hereby granted, provided that the above
39  * copyright notice and this permission notice appear in all copies.
40  *
41  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
42  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
43  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
44  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
45  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
46  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
47  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
48  */
49 
50 #include <sys/cdefs.h>
51 __FBSDID("$FreeBSD$");
52 
53 /*
54  * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports
55  * the SK-984x series adapters, both single port and dual port.
56  * References:
57  * 	The XaQti XMAC II datasheet,
58  *  http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
59  *	The SysKonnect GEnesis manual, http://www.syskonnect.com
60  *
61  * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the
62  * XMAC II datasheet online. I have put my copy at people.freebsd.org as a
63  * convenience to others until Vitesse corrects this problem:
64  *
65  * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
66  *
67  * Written by Bill Paul <wpaul@ee.columbia.edu>
68  * Department of Electrical Engineering
69  * Columbia University, New York City
70  */
71 /*
72  * The SysKonnect gigabit ethernet adapters consist of two main
73  * components: the SysKonnect GEnesis controller chip and the XaQti Corp.
74  * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC
75  * components and a PHY while the GEnesis controller provides a PCI
76  * interface with DMA support. Each card may have between 512K and
77  * 2MB of SRAM on board depending on the configuration.
78  *
79  * The SysKonnect GEnesis controller can have either one or two XMAC
80  * chips connected to it, allowing single or dual port NIC configurations.
81  * SysKonnect has the distinction of being the only vendor on the market
82  * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs,
83  * dual DMA queues, packet/MAC/transmit arbiters and direct access to the
84  * XMAC registers. This driver takes advantage of these features to allow
85  * both XMACs to operate as independent interfaces.
86  */
87 
88 #include <sys/param.h>
89 #include <sys/systm.h>
90 #include <sys/bus.h>
91 #include <sys/endian.h>
92 #include <sys/mbuf.h>
93 #include <sys/malloc.h>
94 #include <sys/kernel.h>
95 #include <sys/module.h>
96 #include <sys/socket.h>
97 #include <sys/sockio.h>
98 #include <sys/queue.h>
99 #include <sys/sysctl.h>
100 
101 #include <net/bpf.h>
102 #include <net/ethernet.h>
103 #include <net/if.h>
104 #include <net/if_arp.h>
105 #include <net/if_dl.h>
106 #include <net/if_media.h>
107 #include <net/if_types.h>
108 #include <net/if_vlan_var.h>
109 
110 #include <netinet/in.h>
111 #include <netinet/in_systm.h>
112 #include <netinet/ip.h>
113 
114 #include <machine/bus.h>
115 #include <machine/in_cksum.h>
116 #include <machine/resource.h>
117 #include <sys/rman.h>
118 
119 #include <dev/mii/mii.h>
120 #include <dev/mii/miivar.h>
121 #include <dev/mii/brgphyreg.h>
122 
123 #include <dev/pci/pcireg.h>
124 #include <dev/pci/pcivar.h>
125 
126 #if 0
127 #define SK_USEIOSPACE
128 #endif
129 
130 #include <dev/sk/if_skreg.h>
131 #include <dev/sk/xmaciireg.h>
132 #include <dev/sk/yukonreg.h>
133 
134 MODULE_DEPEND(sk, pci, 1, 1, 1);
135 MODULE_DEPEND(sk, ether, 1, 1, 1);
136 MODULE_DEPEND(sk, miibus, 1, 1, 1);
137 
138 /* "device miibus" required.  See GENERIC if you get errors here. */
139 #include "miibus_if.h"
140 
141 #ifndef lint
142 static const char rcsid[] =
143   "$FreeBSD$";
144 #endif
145 
146 static struct sk_type sk_devs[] = {
147 	{
148 		VENDORID_SK,
149 		DEVICEID_SK_V1,
150 		"SysKonnect Gigabit Ethernet (V1.0)"
151 	},
152 	{
153 		VENDORID_SK,
154 		DEVICEID_SK_V2,
155 		"SysKonnect Gigabit Ethernet (V2.0)"
156 	},
157 	{
158 		VENDORID_MARVELL,
159 		DEVICEID_SK_V2,
160 		"Marvell Gigabit Ethernet"
161 	},
162 	{
163 		VENDORID_MARVELL,
164 		DEVICEID_BELKIN_5005,
165 		"Belkin F5D5005 Gigabit Ethernet"
166 	},
167 	{
168 		VENDORID_3COM,
169 		DEVICEID_3COM_3C940,
170 		"3Com 3C940 Gigabit Ethernet"
171 	},
172 	{
173 		VENDORID_LINKSYS,
174 		DEVICEID_LINKSYS_EG1032,
175 		"Linksys EG1032 Gigabit Ethernet"
176 	},
177 	{
178 		VENDORID_DLINK,
179 		DEVICEID_DLINK_DGE530T_A1,
180 		"D-Link DGE-530T Gigabit Ethernet"
181 	},
182 	{
183 		VENDORID_DLINK,
184 		DEVICEID_DLINK_DGE530T_B1,
185 		"D-Link DGE-530T Gigabit Ethernet"
186 	},
187 	{ 0, 0, NULL }
188 };
189 
190 static int skc_probe(device_t);
191 static int skc_attach(device_t);
192 static int skc_detach(device_t);
193 static int skc_shutdown(device_t);
194 static int skc_suspend(device_t);
195 static int skc_resume(device_t);
196 static int sk_detach(device_t);
197 static int sk_probe(device_t);
198 static int sk_attach(device_t);
199 static void sk_tick(void *);
200 static void sk_yukon_tick(void *);
201 static void sk_intr(void *);
202 static void sk_intr_xmac(struct sk_if_softc *);
203 static void sk_intr_bcom(struct sk_if_softc *);
204 static void sk_intr_yukon(struct sk_if_softc *);
205 static __inline void sk_rxcksum(struct ifnet *, struct mbuf *, u_int32_t);
206 static __inline int sk_rxvalid(struct sk_softc *, u_int32_t, u_int32_t);
207 static void sk_rxeof(struct sk_if_softc *);
208 static void sk_jumbo_rxeof(struct sk_if_softc *);
209 static void sk_txeof(struct sk_if_softc *);
210 static void sk_txcksum(struct ifnet *, struct mbuf *, struct sk_tx_desc *);
211 static int sk_encap(struct sk_if_softc *, struct mbuf **);
212 static void sk_start(struct ifnet *);
213 static void sk_start_locked(struct ifnet *);
214 static int sk_ioctl(struct ifnet *, u_long, caddr_t);
215 static void sk_init(void *);
216 static void sk_init_locked(struct sk_if_softc *);
217 static void sk_init_xmac(struct sk_if_softc *);
218 static void sk_init_yukon(struct sk_if_softc *);
219 static void sk_stop(struct sk_if_softc *);
220 static void sk_watchdog(void *);
221 static int sk_ifmedia_upd(struct ifnet *);
222 static void sk_ifmedia_sts(struct ifnet *, struct ifmediareq *);
223 static void sk_reset(struct sk_softc *);
224 static __inline void sk_discard_rxbuf(struct sk_if_softc *, int);
225 static __inline void sk_discard_jumbo_rxbuf(struct sk_if_softc *, int);
226 static int sk_newbuf(struct sk_if_softc *, int);
227 static int sk_jumbo_newbuf(struct sk_if_softc *, int);
228 static void sk_dmamap_cb(void *, bus_dma_segment_t *, int, int);
229 static int sk_dma_alloc(struct sk_if_softc *);
230 static int sk_dma_jumbo_alloc(struct sk_if_softc *);
231 static void sk_dma_free(struct sk_if_softc *);
232 static void sk_dma_jumbo_free(struct sk_if_softc *);
233 static int sk_init_rx_ring(struct sk_if_softc *);
234 static int sk_init_jumbo_rx_ring(struct sk_if_softc *);
235 static void sk_init_tx_ring(struct sk_if_softc *);
236 static u_int32_t sk_win_read_4(struct sk_softc *, int);
237 static u_int16_t sk_win_read_2(struct sk_softc *, int);
238 static u_int8_t sk_win_read_1(struct sk_softc *, int);
239 static void sk_win_write_4(struct sk_softc *, int, u_int32_t);
240 static void sk_win_write_2(struct sk_softc *, int, u_int32_t);
241 static void sk_win_write_1(struct sk_softc *, int, u_int32_t);
242 
243 static int sk_miibus_readreg(device_t, int, int);
244 static int sk_miibus_writereg(device_t, int, int, int);
245 static void sk_miibus_statchg(device_t);
246 
247 static int sk_xmac_miibus_readreg(struct sk_if_softc *, int, int);
248 static int sk_xmac_miibus_writereg(struct sk_if_softc *, int, int,
249 						int);
250 static void sk_xmac_miibus_statchg(struct sk_if_softc *);
251 
252 static int sk_marv_miibus_readreg(struct sk_if_softc *, int, int);
253 static int sk_marv_miibus_writereg(struct sk_if_softc *, int, int,
254 						int);
255 static void sk_marv_miibus_statchg(struct sk_if_softc *);
256 
257 static uint32_t sk_xmchash(const uint8_t *);
258 static void sk_setfilt(struct sk_if_softc *, u_int16_t *, int);
259 static void sk_rxfilter(struct sk_if_softc *);
260 static void sk_rxfilter_genesis(struct sk_if_softc *);
261 static void sk_rxfilter_yukon(struct sk_if_softc *);
262 
263 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high);
264 static int sysctl_hw_sk_int_mod(SYSCTL_HANDLER_ARGS);
265 
266 /* Tunables. */
267 static int jumbo_disable = 0;
268 TUNABLE_INT("hw.skc.jumbo_disable", &jumbo_disable);
269 
270 /*
271  * It seems that SK-NET GENESIS supports very simple checksum offload
272  * capability for Tx and I believe it can generate 0 checksum value for
273  * UDP packets in Tx as the hardware can't differenciate UDP packets from
274  * TCP packets. 0 chcecksum value for UDP packet is an invalid one as it
275  * means sender didn't perforam checksum computation. For the safety I
276  * disabled UDP checksum offload capability at the moment. Alternatively
277  * we can intrduce a LINK0/LINK1 flag as hme(4) did in its Tx checksum
278  * offload routine.
279  */
280 #define SK_CSUM_FEATURES	(CSUM_TCP)
281 
282 /*
283  * Note that we have newbus methods for both the GEnesis controller
284  * itself and the XMAC(s). The XMACs are children of the GEnesis, and
285  * the miibus code is a child of the XMACs. We need to do it this way
286  * so that the miibus drivers can access the PHY registers on the
287  * right PHY. It's not quite what I had in mind, but it's the only
288  * design that achieves the desired effect.
289  */
290 static device_method_t skc_methods[] = {
291 	/* Device interface */
292 	DEVMETHOD(device_probe,		skc_probe),
293 	DEVMETHOD(device_attach,	skc_attach),
294 	DEVMETHOD(device_detach,	skc_detach),
295 	DEVMETHOD(device_suspend,	skc_suspend),
296 	DEVMETHOD(device_resume,	skc_resume),
297 	DEVMETHOD(device_shutdown,	skc_shutdown),
298 
299 	/* bus interface */
300 	DEVMETHOD(bus_print_child,	bus_generic_print_child),
301 	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
302 
303 	{ 0, 0 }
304 };
305 
306 static driver_t skc_driver = {
307 	"skc",
308 	skc_methods,
309 	sizeof(struct sk_softc)
310 };
311 
312 static devclass_t skc_devclass;
313 
314 static device_method_t sk_methods[] = {
315 	/* Device interface */
316 	DEVMETHOD(device_probe,		sk_probe),
317 	DEVMETHOD(device_attach,	sk_attach),
318 	DEVMETHOD(device_detach,	sk_detach),
319 	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
320 
321 	/* bus interface */
322 	DEVMETHOD(bus_print_child,	bus_generic_print_child),
323 	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
324 
325 	/* MII interface */
326 	DEVMETHOD(miibus_readreg,	sk_miibus_readreg),
327 	DEVMETHOD(miibus_writereg,	sk_miibus_writereg),
328 	DEVMETHOD(miibus_statchg,	sk_miibus_statchg),
329 
330 	{ 0, 0 }
331 };
332 
333 static driver_t sk_driver = {
334 	"sk",
335 	sk_methods,
336 	sizeof(struct sk_if_softc)
337 };
338 
339 static devclass_t sk_devclass;
340 
341 DRIVER_MODULE(skc, pci, skc_driver, skc_devclass, 0, 0);
342 DRIVER_MODULE(sk, skc, sk_driver, sk_devclass, 0, 0);
343 DRIVER_MODULE(miibus, sk, miibus_driver, miibus_devclass, 0, 0);
344 
345 static struct resource_spec sk_res_spec_io[] = {
346 	{ SYS_RES_IOPORT,	PCIR_BAR(1),	RF_ACTIVE },
347 	{ SYS_RES_IRQ,		0,		RF_ACTIVE | RF_SHAREABLE },
348 	{ -1,			0,		0 }
349 };
350 
351 static struct resource_spec sk_res_spec_mem[] = {
352 	{ SYS_RES_MEMORY,	PCIR_BAR(0),	RF_ACTIVE },
353 	{ SYS_RES_IRQ,		0,		RF_ACTIVE | RF_SHAREABLE },
354 	{ -1,			0,		0 }
355 };
356 
357 #define SK_SETBIT(sc, reg, x)		\
358 	CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x)
359 
360 #define SK_CLRBIT(sc, reg, x)		\
361 	CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x)
362 
363 #define SK_WIN_SETBIT_4(sc, reg, x)	\
364 	sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x)
365 
366 #define SK_WIN_CLRBIT_4(sc, reg, x)	\
367 	sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x)
368 
369 #define SK_WIN_SETBIT_2(sc, reg, x)	\
370 	sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x)
371 
372 #define SK_WIN_CLRBIT_2(sc, reg, x)	\
373 	sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x)
374 
375 static u_int32_t
376 sk_win_read_4(sc, reg)
377 	struct sk_softc		*sc;
378 	int			reg;
379 {
380 #ifdef SK_USEIOSPACE
381 	CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
382 	return(CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)));
383 #else
384 	return(CSR_READ_4(sc, reg));
385 #endif
386 }
387 
388 static u_int16_t
389 sk_win_read_2(sc, reg)
390 	struct sk_softc		*sc;
391 	int			reg;
392 {
393 #ifdef SK_USEIOSPACE
394 	CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
395 	return(CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)));
396 #else
397 	return(CSR_READ_2(sc, reg));
398 #endif
399 }
400 
401 static u_int8_t
402 sk_win_read_1(sc, reg)
403 	struct sk_softc		*sc;
404 	int			reg;
405 {
406 #ifdef SK_USEIOSPACE
407 	CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
408 	return(CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)));
409 #else
410 	return(CSR_READ_1(sc, reg));
411 #endif
412 }
413 
414 static void
415 sk_win_write_4(sc, reg, val)
416 	struct sk_softc		*sc;
417 	int			reg;
418 	u_int32_t		val;
419 {
420 #ifdef SK_USEIOSPACE
421 	CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
422 	CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), val);
423 #else
424 	CSR_WRITE_4(sc, reg, val);
425 #endif
426 	return;
427 }
428 
429 static void
430 sk_win_write_2(sc, reg, val)
431 	struct sk_softc		*sc;
432 	int			reg;
433 	u_int32_t		val;
434 {
435 #ifdef SK_USEIOSPACE
436 	CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
437 	CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), val);
438 #else
439 	CSR_WRITE_2(sc, reg, val);
440 #endif
441 	return;
442 }
443 
444 static void
445 sk_win_write_1(sc, reg, val)
446 	struct sk_softc		*sc;
447 	int			reg;
448 	u_int32_t		val;
449 {
450 #ifdef SK_USEIOSPACE
451 	CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
452 	CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), val);
453 #else
454 	CSR_WRITE_1(sc, reg, val);
455 #endif
456 	return;
457 }
458 
459 static int
460 sk_miibus_readreg(dev, phy, reg)
461 	device_t		dev;
462 	int			phy, reg;
463 {
464 	struct sk_if_softc	*sc_if;
465 	int			v;
466 
467 	sc_if = device_get_softc(dev);
468 
469 	SK_IF_MII_LOCK(sc_if);
470 	switch(sc_if->sk_softc->sk_type) {
471 	case SK_GENESIS:
472 		v = sk_xmac_miibus_readreg(sc_if, phy, reg);
473 		break;
474 	case SK_YUKON:
475 	case SK_YUKON_LITE:
476 	case SK_YUKON_LP:
477 		v = sk_marv_miibus_readreg(sc_if, phy, reg);
478 		break;
479 	default:
480 		v = 0;
481 		break;
482 	}
483 	SK_IF_MII_UNLOCK(sc_if);
484 
485 	return (v);
486 }
487 
488 static int
489 sk_miibus_writereg(dev, phy, reg, val)
490 	device_t		dev;
491 	int			phy, reg, val;
492 {
493 	struct sk_if_softc	*sc_if;
494 	int			v;
495 
496 	sc_if = device_get_softc(dev);
497 
498 	SK_IF_MII_LOCK(sc_if);
499 	switch(sc_if->sk_softc->sk_type) {
500 	case SK_GENESIS:
501 		v = sk_xmac_miibus_writereg(sc_if, phy, reg, val);
502 		break;
503 	case SK_YUKON:
504 	case SK_YUKON_LITE:
505 	case SK_YUKON_LP:
506 		v = sk_marv_miibus_writereg(sc_if, phy, reg, val);
507 		break;
508 	default:
509 		v = 0;
510 		break;
511 	}
512 	SK_IF_MII_UNLOCK(sc_if);
513 
514 	return (v);
515 }
516 
517 static void
518 sk_miibus_statchg(dev)
519 	device_t		dev;
520 {
521 	struct sk_if_softc	*sc_if;
522 
523 	sc_if = device_get_softc(dev);
524 
525 	SK_IF_MII_LOCK(sc_if);
526 	switch(sc_if->sk_softc->sk_type) {
527 	case SK_GENESIS:
528 		sk_xmac_miibus_statchg(sc_if);
529 		break;
530 	case SK_YUKON:
531 	case SK_YUKON_LITE:
532 	case SK_YUKON_LP:
533 		sk_marv_miibus_statchg(sc_if);
534 		break;
535 	}
536 	SK_IF_MII_UNLOCK(sc_if);
537 
538 	return;
539 }
540 
541 static int
542 sk_xmac_miibus_readreg(sc_if, phy, reg)
543 	struct sk_if_softc	*sc_if;
544 	int			phy, reg;
545 {
546 	int			i;
547 
548 	if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0)
549 		return(0);
550 
551 	SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
552 	SK_XM_READ_2(sc_if, XM_PHY_DATA);
553 	if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
554 		for (i = 0; i < SK_TIMEOUT; i++) {
555 			DELAY(1);
556 			if (SK_XM_READ_2(sc_if, XM_MMUCMD) &
557 			    XM_MMUCMD_PHYDATARDY)
558 				break;
559 		}
560 
561 		if (i == SK_TIMEOUT) {
562 			if_printf(sc_if->sk_ifp, "phy failed to come ready\n");
563 			return(0);
564 		}
565 	}
566 	DELAY(1);
567 	i = SK_XM_READ_2(sc_if, XM_PHY_DATA);
568 
569 	return(i);
570 }
571 
572 static int
573 sk_xmac_miibus_writereg(sc_if, phy, reg, val)
574 	struct sk_if_softc	*sc_if;
575 	int			phy, reg, val;
576 {
577 	int			i;
578 
579 	SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
580 	for (i = 0; i < SK_TIMEOUT; i++) {
581 		if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY))
582 			break;
583 	}
584 
585 	if (i == SK_TIMEOUT) {
586 		if_printf(sc_if->sk_ifp, "phy failed to come ready\n");
587 		return (ETIMEDOUT);
588 	}
589 
590 	SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val);
591 	for (i = 0; i < SK_TIMEOUT; i++) {
592 		DELAY(1);
593 		if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY))
594 			break;
595 	}
596 	if (i == SK_TIMEOUT)
597 		if_printf(sc_if->sk_ifp, "phy write timed out\n");
598 
599 	return(0);
600 }
601 
602 static void
603 sk_xmac_miibus_statchg(sc_if)
604 	struct sk_if_softc	*sc_if;
605 {
606 	struct mii_data		*mii;
607 
608 	mii = device_get_softc(sc_if->sk_miibus);
609 
610 	/*
611 	 * If this is a GMII PHY, manually set the XMAC's
612 	 * duplex mode accordingly.
613 	 */
614 	if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
615 		if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
616 			SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
617 		} else {
618 			SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
619 		}
620 	}
621 }
622 
623 static int
624 sk_marv_miibus_readreg(sc_if, phy, reg)
625 	struct sk_if_softc	*sc_if;
626 	int			phy, reg;
627 {
628 	u_int16_t		val;
629 	int			i;
630 
631 	if (phy != 0 ||
632 	    (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER &&
633 	     sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) {
634 		return(0);
635 	}
636 
637         SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
638 		      YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ);
639 
640 	for (i = 0; i < SK_TIMEOUT; i++) {
641 		DELAY(1);
642 		val = SK_YU_READ_2(sc_if, YUKON_SMICR);
643 		if (val & YU_SMICR_READ_VALID)
644 			break;
645 	}
646 
647 	if (i == SK_TIMEOUT) {
648 		if_printf(sc_if->sk_ifp, "phy failed to come ready\n");
649 		return(0);
650 	}
651 
652 	val = SK_YU_READ_2(sc_if, YUKON_SMIDR);
653 
654 	return(val);
655 }
656 
657 static int
658 sk_marv_miibus_writereg(sc_if, phy, reg, val)
659 	struct sk_if_softc	*sc_if;
660 	int			phy, reg, val;
661 {
662 	int			i;
663 
664 	SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val);
665 	SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
666 		      YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE);
667 
668 	for (i = 0; i < SK_TIMEOUT; i++) {
669 		DELAY(1);
670 		if ((SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY) == 0)
671 			break;
672 	}
673 	if (i == SK_TIMEOUT)
674 		if_printf(sc_if->sk_ifp, "phy write timeout\n");
675 
676 	return(0);
677 }
678 
679 static void
680 sk_marv_miibus_statchg(sc_if)
681 	struct sk_if_softc	*sc_if;
682 {
683 	return;
684 }
685 
686 #define HASH_BITS		6
687 
688 static u_int32_t
689 sk_xmchash(addr)
690 	const uint8_t *addr;
691 {
692 	uint32_t crc;
693 
694 	/* Compute CRC for the address value. */
695 	crc = ether_crc32_le(addr, ETHER_ADDR_LEN);
696 
697 	return (~crc & ((1 << HASH_BITS) - 1));
698 }
699 
700 static void
701 sk_setfilt(sc_if, addr, slot)
702 	struct sk_if_softc	*sc_if;
703 	u_int16_t		*addr;
704 	int			slot;
705 {
706 	int			base;
707 
708 	base = XM_RXFILT_ENTRY(slot);
709 
710 	SK_XM_WRITE_2(sc_if, base, addr[0]);
711 	SK_XM_WRITE_2(sc_if, base + 2, addr[1]);
712 	SK_XM_WRITE_2(sc_if, base + 4, addr[2]);
713 
714 	return;
715 }
716 
717 static void
718 sk_rxfilter(sc_if)
719 	struct sk_if_softc	*sc_if;
720 {
721 	struct sk_softc		*sc;
722 
723 	SK_IF_LOCK_ASSERT(sc_if);
724 
725 	sc = sc_if->sk_softc;
726 	if (sc->sk_type == SK_GENESIS)
727 		sk_rxfilter_genesis(sc_if);
728 	else
729 		sk_rxfilter_yukon(sc_if);
730 }
731 
732 static void
733 sk_rxfilter_genesis(sc_if)
734 	struct sk_if_softc	*sc_if;
735 {
736 	struct ifnet		*ifp = sc_if->sk_ifp;
737 	u_int32_t		hashes[2] = { 0, 0 }, mode;
738 	int			h = 0, i;
739 	struct ifmultiaddr	*ifma;
740 	u_int16_t		dummy[] = { 0, 0, 0 };
741 	u_int16_t		maddr[(ETHER_ADDR_LEN+1)/2];
742 
743 	SK_IF_LOCK_ASSERT(sc_if);
744 
745 	mode = SK_XM_READ_4(sc_if, XM_MODE);
746 	mode &= ~(XM_MODE_RX_PROMISC | XM_MODE_RX_USE_HASH |
747 	    XM_MODE_RX_USE_PERFECT);
748 	/* First, zot all the existing perfect filters. */
749 	for (i = 1; i < XM_RXFILT_MAX; i++)
750 		sk_setfilt(sc_if, dummy, i);
751 
752 	/* Now program new ones. */
753 	if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
754 		if (ifp->if_flags & IFF_ALLMULTI)
755 			mode |= XM_MODE_RX_USE_HASH;
756 		if (ifp->if_flags & IFF_PROMISC)
757 			mode |= XM_MODE_RX_PROMISC;
758 		hashes[0] = 0xFFFFFFFF;
759 		hashes[1] = 0xFFFFFFFF;
760 	} else {
761 		i = 1;
762 		if_maddr_rlock(ifp);
763 		TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead,
764 		    ifma_link) {
765 			if (ifma->ifma_addr->sa_family != AF_LINK)
766 				continue;
767 			/*
768 			 * Program the first XM_RXFILT_MAX multicast groups
769 			 * into the perfect filter.
770 			 */
771 			bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
772 			    maddr, ETHER_ADDR_LEN);
773 			if (i < XM_RXFILT_MAX) {
774 				sk_setfilt(sc_if, maddr, i);
775 				mode |= XM_MODE_RX_USE_PERFECT;
776 				i++;
777 				continue;
778 			}
779 			h = sk_xmchash((const uint8_t *)maddr);
780 			if (h < 32)
781 				hashes[0] |= (1 << h);
782 			else
783 				hashes[1] |= (1 << (h - 32));
784 			mode |= XM_MODE_RX_USE_HASH;
785 		}
786 		if_maddr_runlock(ifp);
787 	}
788 
789 	SK_XM_WRITE_4(sc_if, XM_MODE, mode);
790 	SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]);
791 	SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]);
792 }
793 
794 static void
795 sk_rxfilter_yukon(sc_if)
796 	struct sk_if_softc	*sc_if;
797 {
798 	struct ifnet		*ifp;
799 	u_int32_t		crc, hashes[2] = { 0, 0 }, mode;
800 	struct ifmultiaddr	*ifma;
801 
802 	SK_IF_LOCK_ASSERT(sc_if);
803 
804 	ifp = sc_if->sk_ifp;
805 	mode = SK_YU_READ_2(sc_if, YUKON_RCR);
806 	if (ifp->if_flags & IFF_PROMISC)
807 		mode &= ~(YU_RCR_UFLEN | YU_RCR_MUFLEN);
808 	else if (ifp->if_flags & IFF_ALLMULTI) {
809 		mode |= YU_RCR_UFLEN | YU_RCR_MUFLEN;
810 		hashes[0] = 0xFFFFFFFF;
811 		hashes[1] = 0xFFFFFFFF;
812 	} else {
813 		mode |= YU_RCR_UFLEN;
814 		if_maddr_rlock(ifp);
815 		TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
816 			if (ifma->ifma_addr->sa_family != AF_LINK)
817 				continue;
818 			crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
819 			    ifma->ifma_addr), ETHER_ADDR_LEN);
820 			/* Just want the 6 least significant bits. */
821 			crc &= 0x3f;
822 			/* Set the corresponding bit in the hash table. */
823 			hashes[crc >> 5] |= 1 << (crc & 0x1f);
824 		}
825 		if_maddr_runlock(ifp);
826 		if (hashes[0] != 0 || hashes[1] != 0)
827 			mode |= YU_RCR_MUFLEN;
828 	}
829 
830 	SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff);
831 	SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff);
832 	SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff);
833 	SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff);
834 	SK_YU_WRITE_2(sc_if, YUKON_RCR, mode);
835 }
836 
837 static int
838 sk_init_rx_ring(sc_if)
839 	struct sk_if_softc	*sc_if;
840 {
841 	struct sk_ring_data	*rd;
842 	bus_addr_t		addr;
843 	u_int32_t		csum_start;
844 	int			i;
845 
846 	sc_if->sk_cdata.sk_rx_cons = 0;
847 
848 	csum_start = (ETHER_HDR_LEN + sizeof(struct ip))  << 16 |
849 	    ETHER_HDR_LEN;
850 	rd = &sc_if->sk_rdata;
851 	bzero(rd->sk_rx_ring, sizeof(struct sk_rx_desc) * SK_RX_RING_CNT);
852 	for (i = 0; i < SK_RX_RING_CNT; i++) {
853 		if (sk_newbuf(sc_if, i) != 0)
854 			return (ENOBUFS);
855 		if (i == (SK_RX_RING_CNT - 1))
856 			addr = SK_RX_RING_ADDR(sc_if, 0);
857 		else
858 			addr = SK_RX_RING_ADDR(sc_if, i + 1);
859 		rd->sk_rx_ring[i].sk_next = htole32(SK_ADDR_LO(addr));
860 		rd->sk_rx_ring[i].sk_csum_start = htole32(csum_start);
861 	}
862 
863 	bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag,
864 	    sc_if->sk_cdata.sk_rx_ring_map,
865 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
866 
867 	return(0);
868 }
869 
870 static int
871 sk_init_jumbo_rx_ring(sc_if)
872 	struct sk_if_softc	*sc_if;
873 {
874 	struct sk_ring_data	*rd;
875 	bus_addr_t		addr;
876 	u_int32_t		csum_start;
877 	int			i;
878 
879 	sc_if->sk_cdata.sk_jumbo_rx_cons = 0;
880 
881 	csum_start = ((ETHER_HDR_LEN + sizeof(struct ip)) << 16) |
882 	    ETHER_HDR_LEN;
883 	rd = &sc_if->sk_rdata;
884 	bzero(rd->sk_jumbo_rx_ring,
885 	    sizeof(struct sk_rx_desc) * SK_JUMBO_RX_RING_CNT);
886 	for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) {
887 		if (sk_jumbo_newbuf(sc_if, i) != 0)
888 			return (ENOBUFS);
889 		if (i == (SK_JUMBO_RX_RING_CNT - 1))
890 			addr = SK_JUMBO_RX_RING_ADDR(sc_if, 0);
891 		else
892 			addr = SK_JUMBO_RX_RING_ADDR(sc_if, i + 1);
893 		rd->sk_jumbo_rx_ring[i].sk_next = htole32(SK_ADDR_LO(addr));
894 		rd->sk_jumbo_rx_ring[i].sk_csum_start = htole32(csum_start);
895 	}
896 
897 	bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
898 	    sc_if->sk_cdata.sk_jumbo_rx_ring_map,
899 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
900 
901 	return (0);
902 }
903 
904 static void
905 sk_init_tx_ring(sc_if)
906 	struct sk_if_softc	*sc_if;
907 {
908 	struct sk_ring_data	*rd;
909 	struct sk_txdesc	*txd;
910 	bus_addr_t		addr;
911 	int			i;
912 
913 	STAILQ_INIT(&sc_if->sk_cdata.sk_txfreeq);
914 	STAILQ_INIT(&sc_if->sk_cdata.sk_txbusyq);
915 
916 	sc_if->sk_cdata.sk_tx_prod = 0;
917 	sc_if->sk_cdata.sk_tx_cons = 0;
918 	sc_if->sk_cdata.sk_tx_cnt = 0;
919 
920 	rd = &sc_if->sk_rdata;
921 	bzero(rd->sk_tx_ring, sizeof(struct sk_tx_desc) * SK_TX_RING_CNT);
922 	for (i = 0; i < SK_TX_RING_CNT; i++) {
923 		if (i == (SK_TX_RING_CNT - 1))
924 			addr = SK_TX_RING_ADDR(sc_if, 0);
925 		else
926 			addr = SK_TX_RING_ADDR(sc_if, i + 1);
927 		rd->sk_tx_ring[i].sk_next = htole32(SK_ADDR_LO(addr));
928 		txd = &sc_if->sk_cdata.sk_txdesc[i];
929 		STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txfreeq, txd, tx_q);
930 	}
931 
932 	bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag,
933 	    sc_if->sk_cdata.sk_tx_ring_map,
934 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
935 }
936 
937 static __inline void
938 sk_discard_rxbuf(sc_if, idx)
939 	struct sk_if_softc	*sc_if;
940 	int			idx;
941 {
942 	struct sk_rx_desc	*r;
943 	struct sk_rxdesc	*rxd;
944 	struct mbuf		*m;
945 
946 
947 	r = &sc_if->sk_rdata.sk_rx_ring[idx];
948 	rxd = &sc_if->sk_cdata.sk_rxdesc[idx];
949 	m = rxd->rx_m;
950 	r->sk_ctl = htole32(m->m_len | SK_RXSTAT | SK_OPCODE_CSUM);
951 }
952 
953 static __inline void
954 sk_discard_jumbo_rxbuf(sc_if, idx)
955 	struct sk_if_softc	*sc_if;
956 	int			idx;
957 {
958 	struct sk_rx_desc	*r;
959 	struct sk_rxdesc	*rxd;
960 	struct mbuf		*m;
961 
962 	r = &sc_if->sk_rdata.sk_jumbo_rx_ring[idx];
963 	rxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[idx];
964 	m = rxd->rx_m;
965 	r->sk_ctl = htole32(m->m_len | SK_RXSTAT | SK_OPCODE_CSUM);
966 }
967 
968 static int
969 sk_newbuf(sc_if, idx)
970 	struct sk_if_softc	*sc_if;
971 	int 			idx;
972 {
973 	struct sk_rx_desc	*r;
974 	struct sk_rxdesc	*rxd;
975 	struct mbuf		*m;
976 	bus_dma_segment_t	segs[1];
977 	bus_dmamap_t		map;
978 	int			nsegs;
979 
980 	m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
981 	if (m == NULL)
982 		return (ENOBUFS);
983 	m->m_len = m->m_pkthdr.len = MCLBYTES;
984 	m_adj(m, ETHER_ALIGN);
985 
986 	if (bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_rx_tag,
987 	    sc_if->sk_cdata.sk_rx_sparemap, m, segs, &nsegs, 0) != 0) {
988 		m_freem(m);
989 		return (ENOBUFS);
990 	}
991 	KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
992 
993 	rxd = &sc_if->sk_cdata.sk_rxdesc[idx];
994 	if (rxd->rx_m != NULL) {
995 		bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap,
996 		    BUS_DMASYNC_POSTREAD);
997 		bus_dmamap_unload(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap);
998 	}
999 	map = rxd->rx_dmamap;
1000 	rxd->rx_dmamap = sc_if->sk_cdata.sk_rx_sparemap;
1001 	sc_if->sk_cdata.sk_rx_sparemap = map;
1002 	bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap,
1003 	    BUS_DMASYNC_PREREAD);
1004 	rxd->rx_m = m;
1005 	r = &sc_if->sk_rdata.sk_rx_ring[idx];
1006 	r->sk_data_lo = htole32(SK_ADDR_LO(segs[0].ds_addr));
1007 	r->sk_data_hi = htole32(SK_ADDR_HI(segs[0].ds_addr));
1008 	r->sk_ctl = htole32(segs[0].ds_len | SK_RXSTAT | SK_OPCODE_CSUM);
1009 
1010 	return (0);
1011 }
1012 
1013 static int
1014 sk_jumbo_newbuf(sc_if, idx)
1015 	struct sk_if_softc	*sc_if;
1016 	int			idx;
1017 {
1018 	struct sk_rx_desc	*r;
1019 	struct sk_rxdesc	*rxd;
1020 	struct mbuf		*m;
1021 	bus_dma_segment_t	segs[1];
1022 	bus_dmamap_t		map;
1023 	int			nsegs;
1024 
1025 	m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES);
1026 	if (m == NULL)
1027 		return (ENOBUFS);
1028 	if ((m->m_flags & M_EXT) == 0) {
1029 		m_freem(m);
1030 		return (ENOBUFS);
1031 	}
1032 	m->m_pkthdr.len = m->m_len = MJUM9BYTES;
1033 	/*
1034 	 * Adjust alignment so packet payload begins on a
1035 	 * longword boundary. Mandatory for Alpha, useful on
1036 	 * x86 too.
1037 	 */
1038 	m_adj(m, ETHER_ALIGN);
1039 
1040 	if (bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_jumbo_rx_tag,
1041 	    sc_if->sk_cdata.sk_jumbo_rx_sparemap, m, segs, &nsegs, 0) != 0) {
1042 		m_freem(m);
1043 		return (ENOBUFS);
1044 	}
1045 	KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1046 
1047 	rxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[idx];
1048 	if (rxd->rx_m != NULL) {
1049 		bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag, rxd->rx_dmamap,
1050 		    BUS_DMASYNC_POSTREAD);
1051 		bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_tag,
1052 		    rxd->rx_dmamap);
1053 	}
1054 	map = rxd->rx_dmamap;
1055 	rxd->rx_dmamap = sc_if->sk_cdata.sk_jumbo_rx_sparemap;
1056 	sc_if->sk_cdata.sk_jumbo_rx_sparemap = map;
1057 	bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag, rxd->rx_dmamap,
1058 	    BUS_DMASYNC_PREREAD);
1059 	rxd->rx_m = m;
1060 	r = &sc_if->sk_rdata.sk_jumbo_rx_ring[idx];
1061 	r->sk_data_lo = htole32(SK_ADDR_LO(segs[0].ds_addr));
1062 	r->sk_data_hi = htole32(SK_ADDR_HI(segs[0].ds_addr));
1063 	r->sk_ctl = htole32(segs[0].ds_len | SK_RXSTAT | SK_OPCODE_CSUM);
1064 
1065 	return (0);
1066 }
1067 
1068 /*
1069  * Set media options.
1070  */
1071 static int
1072 sk_ifmedia_upd(ifp)
1073 	struct ifnet		*ifp;
1074 {
1075 	struct sk_if_softc	*sc_if = ifp->if_softc;
1076 	struct mii_data		*mii;
1077 
1078 	mii = device_get_softc(sc_if->sk_miibus);
1079 	sk_init(sc_if);
1080 	mii_mediachg(mii);
1081 
1082 	return(0);
1083 }
1084 
1085 /*
1086  * Report current media status.
1087  */
1088 static void
1089 sk_ifmedia_sts(ifp, ifmr)
1090 	struct ifnet		*ifp;
1091 	struct ifmediareq	*ifmr;
1092 {
1093 	struct sk_if_softc	*sc_if;
1094 	struct mii_data		*mii;
1095 
1096 	sc_if = ifp->if_softc;
1097 	mii = device_get_softc(sc_if->sk_miibus);
1098 
1099 	mii_pollstat(mii);
1100 	ifmr->ifm_active = mii->mii_media_active;
1101 	ifmr->ifm_status = mii->mii_media_status;
1102 
1103 	return;
1104 }
1105 
1106 static int
1107 sk_ioctl(ifp, command, data)
1108 	struct ifnet		*ifp;
1109 	u_long			command;
1110 	caddr_t			data;
1111 {
1112 	struct sk_if_softc	*sc_if = ifp->if_softc;
1113 	struct ifreq		*ifr = (struct ifreq *) data;
1114 	int			error, mask;
1115 	struct mii_data		*mii;
1116 
1117 	error = 0;
1118 	switch(command) {
1119 	case SIOCSIFMTU:
1120 		if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > SK_JUMBO_MTU)
1121 			error = EINVAL;
1122 		else if (ifp->if_mtu != ifr->ifr_mtu) {
1123 			if (sc_if->sk_jumbo_disable != 0 &&
1124 			    ifr->ifr_mtu > SK_MAX_FRAMELEN)
1125 				error = EINVAL;
1126 			else {
1127 				SK_IF_LOCK(sc_if);
1128 				ifp->if_mtu = ifr->ifr_mtu;
1129 				if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1130 					ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1131 					sk_init_locked(sc_if);
1132 				}
1133 				SK_IF_UNLOCK(sc_if);
1134 			}
1135 		}
1136 		break;
1137 	case SIOCSIFFLAGS:
1138 		SK_IF_LOCK(sc_if);
1139 		if (ifp->if_flags & IFF_UP) {
1140 			if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1141 				if ((ifp->if_flags ^ sc_if->sk_if_flags)
1142 				    & (IFF_PROMISC | IFF_ALLMULTI))
1143 					sk_rxfilter(sc_if);
1144 			} else
1145 				sk_init_locked(sc_if);
1146 		} else {
1147 			if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1148 				sk_stop(sc_if);
1149 		}
1150 		sc_if->sk_if_flags = ifp->if_flags;
1151 		SK_IF_UNLOCK(sc_if);
1152 		break;
1153 	case SIOCADDMULTI:
1154 	case SIOCDELMULTI:
1155 		SK_IF_LOCK(sc_if);
1156 		if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1157 			sk_rxfilter(sc_if);
1158 		SK_IF_UNLOCK(sc_if);
1159 		break;
1160 	case SIOCGIFMEDIA:
1161 	case SIOCSIFMEDIA:
1162 		mii = device_get_softc(sc_if->sk_miibus);
1163 		error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1164 		break;
1165 	case SIOCSIFCAP:
1166 		SK_IF_LOCK(sc_if);
1167 		if (sc_if->sk_softc->sk_type == SK_GENESIS) {
1168 			SK_IF_UNLOCK(sc_if);
1169 			break;
1170 		}
1171 		mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1172 		if (mask & IFCAP_HWCSUM) {
1173 			ifp->if_capenable ^= IFCAP_HWCSUM;
1174 			if (IFCAP_HWCSUM & ifp->if_capenable &&
1175 			    IFCAP_HWCSUM & ifp->if_capabilities)
1176 				ifp->if_hwassist = SK_CSUM_FEATURES;
1177 			else
1178 				ifp->if_hwassist = 0;
1179 		}
1180 		SK_IF_UNLOCK(sc_if);
1181 		break;
1182 	default:
1183 		error = ether_ioctl(ifp, command, data);
1184 		break;
1185 	}
1186 
1187 	return (error);
1188 }
1189 
1190 /*
1191  * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device
1192  * IDs against our list and return a device name if we find a match.
1193  */
1194 static int
1195 skc_probe(dev)
1196 	device_t		dev;
1197 {
1198 	struct sk_type		*t = sk_devs;
1199 
1200 	while(t->sk_name != NULL) {
1201 		if ((pci_get_vendor(dev) == t->sk_vid) &&
1202 		    (pci_get_device(dev) == t->sk_did)) {
1203 			/*
1204 			 * Only attach to rev. 2 of the Linksys EG1032 adapter.
1205 			 * Rev. 3 is supported by re(4).
1206 			 */
1207 			if ((t->sk_vid == VENDORID_LINKSYS) &&
1208 				(t->sk_did == DEVICEID_LINKSYS_EG1032) &&
1209 				(pci_get_subdevice(dev) !=
1210 				 SUBDEVICEID_LINKSYS_EG1032_REV2)) {
1211 				t++;
1212 				continue;
1213 			}
1214 			device_set_desc(dev, t->sk_name);
1215 			return (BUS_PROBE_DEFAULT);
1216 		}
1217 		t++;
1218 	}
1219 
1220 	return(ENXIO);
1221 }
1222 
1223 /*
1224  * Force the GEnesis into reset, then bring it out of reset.
1225  */
1226 static void
1227 sk_reset(sc)
1228 	struct sk_softc		*sc;
1229 {
1230 
1231 	CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET);
1232 	CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET);
1233 	if (SK_YUKON_FAMILY(sc->sk_type))
1234 		CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET);
1235 
1236 	DELAY(1000);
1237 	CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET);
1238 	DELAY(2);
1239 	CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET);
1240 	if (SK_YUKON_FAMILY(sc->sk_type))
1241 		CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR);
1242 
1243 	if (sc->sk_type == SK_GENESIS) {
1244 		/* Configure packet arbiter */
1245 		sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET);
1246 		sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT);
1247 		sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT);
1248 		sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT);
1249 		sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT);
1250 	}
1251 
1252 	/* Enable RAM interface */
1253 	sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET);
1254 
1255 	/*
1256          * Configure interrupt moderation. The moderation timer
1257 	 * defers interrupts specified in the interrupt moderation
1258 	 * timer mask based on the timeout specified in the interrupt
1259 	 * moderation timer init register. Each bit in the timer
1260 	 * register represents one tick, so to specify a timeout in
1261 	 * microseconds, we have to multiply by the correct number of
1262 	 * ticks-per-microsecond.
1263 	 */
1264 	switch (sc->sk_type) {
1265 	case SK_GENESIS:
1266 		sc->sk_int_ticks = SK_IMTIMER_TICKS_GENESIS;
1267 		break;
1268 	default:
1269 		sc->sk_int_ticks = SK_IMTIMER_TICKS_YUKON;
1270 		break;
1271 	}
1272 	if (bootverbose)
1273 		device_printf(sc->sk_dev, "interrupt moderation is %d us\n",
1274 		    sc->sk_int_mod);
1275 	sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod,
1276 	    sc->sk_int_ticks));
1277 	sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF|
1278 	    SK_ISR_RX1_EOF|SK_ISR_RX2_EOF);
1279 	sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START);
1280 
1281 	return;
1282 }
1283 
1284 static int
1285 sk_probe(dev)
1286 	device_t		dev;
1287 {
1288 	struct sk_softc		*sc;
1289 
1290 	sc = device_get_softc(device_get_parent(dev));
1291 
1292 	/*
1293 	 * Not much to do here. We always know there will be
1294 	 * at least one XMAC present, and if there are two,
1295 	 * skc_attach() will create a second device instance
1296 	 * for us.
1297 	 */
1298 	switch (sc->sk_type) {
1299 	case SK_GENESIS:
1300 		device_set_desc(dev, "XaQti Corp. XMAC II");
1301 		break;
1302 	case SK_YUKON:
1303 	case SK_YUKON_LITE:
1304 	case SK_YUKON_LP:
1305 		device_set_desc(dev, "Marvell Semiconductor, Inc. Yukon");
1306 		break;
1307 	}
1308 
1309 	return (BUS_PROBE_DEFAULT);
1310 }
1311 
1312 /*
1313  * Each XMAC chip is attached as a separate logical IP interface.
1314  * Single port cards will have only one logical interface of course.
1315  */
1316 static int
1317 sk_attach(dev)
1318 	device_t		dev;
1319 {
1320 	struct sk_softc		*sc;
1321 	struct sk_if_softc	*sc_if;
1322 	struct ifnet		*ifp;
1323 	int			i, port, error;
1324 	u_char			eaddr[6];
1325 
1326 	if (dev == NULL)
1327 		return(EINVAL);
1328 
1329 	error = 0;
1330 	sc_if = device_get_softc(dev);
1331 	sc = device_get_softc(device_get_parent(dev));
1332 	port = *(int *)device_get_ivars(dev);
1333 
1334 	sc_if->sk_if_dev = dev;
1335 	sc_if->sk_port = port;
1336 	sc_if->sk_softc = sc;
1337 	sc->sk_if[port] = sc_if;
1338 	if (port == SK_PORT_A)
1339 		sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0;
1340 	if (port == SK_PORT_B)
1341 		sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1;
1342 
1343 	callout_init_mtx(&sc_if->sk_tick_ch, &sc_if->sk_softc->sk_mtx, 0);
1344 	callout_init_mtx(&sc_if->sk_watchdog_ch, &sc_if->sk_softc->sk_mtx, 0);
1345 
1346 	if (sk_dma_alloc(sc_if) != 0) {
1347 		error = ENOMEM;
1348 		goto fail;
1349 	}
1350 	sk_dma_jumbo_alloc(sc_if);
1351 
1352 	ifp = sc_if->sk_ifp = if_alloc(IFT_ETHER);
1353 	if (ifp == NULL) {
1354 		device_printf(sc_if->sk_if_dev, "can not if_alloc()\n");
1355 		error = ENOSPC;
1356 		goto fail;
1357 	}
1358 	ifp->if_softc = sc_if;
1359 	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1360 	ifp->if_mtu = ETHERMTU;
1361 	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1362 	/*
1363 	 * SK_GENESIS has a bug in checksum offload - From linux.
1364 	 */
1365 	if (sc_if->sk_softc->sk_type != SK_GENESIS) {
1366 		ifp->if_capabilities = IFCAP_HWCSUM;
1367 		ifp->if_hwassist = SK_CSUM_FEATURES;
1368 	} else {
1369 		ifp->if_capabilities = 0;
1370 		ifp->if_hwassist = 0;
1371 	}
1372 	ifp->if_capenable = ifp->if_capabilities;
1373 	ifp->if_ioctl = sk_ioctl;
1374 	ifp->if_start = sk_start;
1375 	ifp->if_init = sk_init;
1376 	IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1);
1377 	ifp->if_snd.ifq_drv_maxlen = SK_TX_RING_CNT - 1;
1378 	IFQ_SET_READY(&ifp->if_snd);
1379 
1380 	/*
1381 	 * Get station address for this interface. Note that
1382 	 * dual port cards actually come with three station
1383 	 * addresses: one for each port, plus an extra. The
1384 	 * extra one is used by the SysKonnect driver software
1385 	 * as a 'virtual' station address for when both ports
1386 	 * are operating in failover mode. Currently we don't
1387 	 * use this extra address.
1388 	 */
1389 	SK_IF_LOCK(sc_if);
1390 	for (i = 0; i < ETHER_ADDR_LEN; i++)
1391 		eaddr[i] =
1392 		    sk_win_read_1(sc, SK_MAC0_0 + (port * 8) + i);
1393 
1394 	/*
1395 	 * Set up RAM buffer addresses. The NIC will have a certain
1396 	 * amount of SRAM on it, somewhere between 512K and 2MB. We
1397 	 * need to divide this up a) between the transmitter and
1398  	 * receiver and b) between the two XMACs, if this is a
1399 	 * dual port NIC. Our algotithm is to divide up the memory
1400 	 * evenly so that everyone gets a fair share.
1401 	 *
1402 	 * Just to be contrary, Yukon2 appears to have separate memory
1403 	 * for each MAC.
1404 	 */
1405 	if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) {
1406 		u_int32_t		chunk, val;
1407 
1408 		chunk = sc->sk_ramsize / 2;
1409 		val = sc->sk_rboff / sizeof(u_int64_t);
1410 		sc_if->sk_rx_ramstart = val;
1411 		val += (chunk / sizeof(u_int64_t));
1412 		sc_if->sk_rx_ramend = val - 1;
1413 		sc_if->sk_tx_ramstart = val;
1414 		val += (chunk / sizeof(u_int64_t));
1415 		sc_if->sk_tx_ramend = val - 1;
1416 	} else {
1417 		u_int32_t		chunk, val;
1418 
1419 		chunk = sc->sk_ramsize / 4;
1420 		val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) /
1421 		    sizeof(u_int64_t);
1422 		sc_if->sk_rx_ramstart = val;
1423 		val += (chunk / sizeof(u_int64_t));
1424 		sc_if->sk_rx_ramend = val - 1;
1425 		sc_if->sk_tx_ramstart = val;
1426 		val += (chunk / sizeof(u_int64_t));
1427 		sc_if->sk_tx_ramend = val - 1;
1428 	}
1429 
1430 	/* Read and save PHY type and set PHY address */
1431 	sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF;
1432 	if (!SK_YUKON_FAMILY(sc->sk_type)) {
1433 		switch(sc_if->sk_phytype) {
1434 		case SK_PHYTYPE_XMAC:
1435 			sc_if->sk_phyaddr = SK_PHYADDR_XMAC;
1436 			break;
1437 		case SK_PHYTYPE_BCOM:
1438 			sc_if->sk_phyaddr = SK_PHYADDR_BCOM;
1439 			break;
1440 		default:
1441 			device_printf(sc->sk_dev, "unsupported PHY type: %d\n",
1442 			    sc_if->sk_phytype);
1443 			error = ENODEV;
1444 			SK_IF_UNLOCK(sc_if);
1445 			goto fail;
1446 		}
1447 	} else {
1448 		if (sc_if->sk_phytype < SK_PHYTYPE_MARV_COPPER &&
1449 		    sc->sk_pmd != 'S') {
1450 			/* not initialized, punt */
1451 			sc_if->sk_phytype = SK_PHYTYPE_MARV_COPPER;
1452 			sc->sk_coppertype = 1;
1453 		}
1454 
1455 		sc_if->sk_phyaddr = SK_PHYADDR_MARV;
1456 
1457 		if (!(sc->sk_coppertype))
1458 			sc_if->sk_phytype = SK_PHYTYPE_MARV_FIBER;
1459 	}
1460 
1461 	/*
1462 	 * Call MI attach routine.  Can't hold locks when calling into ether_*.
1463 	 */
1464 	SK_IF_UNLOCK(sc_if);
1465 	ether_ifattach(ifp, eaddr);
1466 	SK_IF_LOCK(sc_if);
1467 
1468 	/*
1469 	 * The hardware should be ready for VLAN_MTU by default:
1470 	 * XMAC II has 0x8100 in VLAN Tag Level 1 register initially;
1471 	 * YU_SMR_MFL_VLAN is set by this driver in Yukon.
1472 	 *
1473 	 */
1474         ifp->if_capabilities |= IFCAP_VLAN_MTU;
1475         ifp->if_capenable |= IFCAP_VLAN_MTU;
1476 	/*
1477 	 * Tell the upper layer(s) we support long frames.
1478 	 * Must appear after the call to ether_ifattach() because
1479 	 * ether_ifattach() sets ifi_hdrlen to the default value.
1480 	 */
1481         ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1482 
1483 	/*
1484 	 * Do miibus setup.
1485 	 */
1486 	switch (sc->sk_type) {
1487 	case SK_GENESIS:
1488 		sk_init_xmac(sc_if);
1489 		break;
1490 	case SK_YUKON:
1491 	case SK_YUKON_LITE:
1492 	case SK_YUKON_LP:
1493 		sk_init_yukon(sc_if);
1494 		break;
1495 	}
1496 
1497 	SK_IF_UNLOCK(sc_if);
1498 	if (mii_phy_probe(dev, &sc_if->sk_miibus,
1499 	    sk_ifmedia_upd, sk_ifmedia_sts)) {
1500 		device_printf(sc_if->sk_if_dev, "no PHY found!\n");
1501 		ether_ifdetach(ifp);
1502 		error = ENXIO;
1503 		goto fail;
1504 	}
1505 
1506 fail:
1507 	if (error) {
1508 		/* Access should be ok even though lock has been dropped */
1509 		sc->sk_if[port] = NULL;
1510 		sk_detach(dev);
1511 	}
1512 
1513 	return(error);
1514 }
1515 
1516 /*
1517  * Attach the interface. Allocate softc structures, do ifmedia
1518  * setup and ethernet/BPF attach.
1519  */
1520 static int
1521 skc_attach(dev)
1522 	device_t		dev;
1523 {
1524 	struct sk_softc		*sc;
1525 	int			error = 0, *port;
1526 	uint8_t			skrs;
1527 	const char		*pname = NULL;
1528 	char			*revstr;
1529 
1530 	sc = device_get_softc(dev);
1531 	sc->sk_dev = dev;
1532 
1533 	mtx_init(&sc->sk_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1534 	    MTX_DEF);
1535 	mtx_init(&sc->sk_mii_mtx, "sk_mii_mutex", NULL, MTX_DEF);
1536 	/*
1537 	 * Map control/status registers.
1538 	 */
1539 	pci_enable_busmaster(dev);
1540 
1541 	/* Allocate resources */
1542 #ifdef SK_USEIOSPACE
1543 	sc->sk_res_spec = sk_res_spec_io;
1544 #else
1545 	sc->sk_res_spec = sk_res_spec_mem;
1546 #endif
1547 	error = bus_alloc_resources(dev, sc->sk_res_spec, sc->sk_res);
1548 	if (error) {
1549 		if (sc->sk_res_spec == sk_res_spec_mem)
1550 			sc->sk_res_spec = sk_res_spec_io;
1551 		else
1552 			sc->sk_res_spec = sk_res_spec_mem;
1553 		error = bus_alloc_resources(dev, sc->sk_res_spec, sc->sk_res);
1554 		if (error) {
1555 			device_printf(dev, "couldn't allocate %s resources\n",
1556 			    sc->sk_res_spec == sk_res_spec_mem ? "memory" :
1557 			    "I/O");
1558 			goto fail;
1559 		}
1560 	}
1561 
1562 	sc->sk_type = sk_win_read_1(sc, SK_CHIPVER);
1563 	sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4) & 0xf;
1564 
1565 	/* Bail out if chip is not recognized. */
1566 	if (sc->sk_type != SK_GENESIS && !SK_YUKON_FAMILY(sc->sk_type)) {
1567 		device_printf(dev, "unknown device: chipver=%02x, rev=%x\n",
1568 		    sc->sk_type, sc->sk_rev);
1569 		error = ENXIO;
1570 		goto fail;
1571 	}
1572 
1573 	SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
1574 		SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
1575 		OID_AUTO, "int_mod", CTLTYPE_INT|CTLFLAG_RW,
1576 		&sc->sk_int_mod, 0, sysctl_hw_sk_int_mod, "I",
1577 		"SK interrupt moderation");
1578 
1579 	/* Pull in device tunables. */
1580 	sc->sk_int_mod = SK_IM_DEFAULT;
1581 	error = resource_int_value(device_get_name(dev), device_get_unit(dev),
1582 		"int_mod", &sc->sk_int_mod);
1583 	if (error == 0) {
1584 		if (sc->sk_int_mod < SK_IM_MIN ||
1585 		    sc->sk_int_mod > SK_IM_MAX) {
1586 			device_printf(dev, "int_mod value out of range; "
1587 			    "using default: %d\n", SK_IM_DEFAULT);
1588 			sc->sk_int_mod = SK_IM_DEFAULT;
1589 		}
1590 	}
1591 
1592 	/* Reset the adapter. */
1593 	sk_reset(sc);
1594 
1595 	skrs = sk_win_read_1(sc, SK_EPROM0);
1596 	if (sc->sk_type == SK_GENESIS) {
1597 		/* Read and save RAM size and RAMbuffer offset */
1598 		switch(skrs) {
1599 		case SK_RAMSIZE_512K_64:
1600 			sc->sk_ramsize = 0x80000;
1601 			sc->sk_rboff = SK_RBOFF_0;
1602 			break;
1603 		case SK_RAMSIZE_1024K_64:
1604 			sc->sk_ramsize = 0x100000;
1605 			sc->sk_rboff = SK_RBOFF_80000;
1606 			break;
1607 		case SK_RAMSIZE_1024K_128:
1608 			sc->sk_ramsize = 0x100000;
1609 			sc->sk_rboff = SK_RBOFF_0;
1610 			break;
1611 		case SK_RAMSIZE_2048K_128:
1612 			sc->sk_ramsize = 0x200000;
1613 			sc->sk_rboff = SK_RBOFF_0;
1614 			break;
1615 		default:
1616 			device_printf(dev, "unknown ram size: %d\n", skrs);
1617 			error = ENXIO;
1618 			goto fail;
1619 		}
1620 	} else { /* SK_YUKON_FAMILY */
1621 		if (skrs == 0x00)
1622 			sc->sk_ramsize = 0x20000;
1623 		else
1624 			sc->sk_ramsize = skrs * (1<<12);
1625 		sc->sk_rboff = SK_RBOFF_0;
1626 	}
1627 
1628 	/* Read and save physical media type */
1629 	 sc->sk_pmd = sk_win_read_1(sc, SK_PMDTYPE);
1630 
1631 	 if (sc->sk_pmd == 'T' || sc->sk_pmd == '1')
1632 		 sc->sk_coppertype = 1;
1633 	 else
1634 		 sc->sk_coppertype = 0;
1635 
1636 	/* Determine whether to name it with VPD PN or just make it up.
1637 	 * Marvell Yukon VPD PN seems to freqently be bogus. */
1638 	switch (pci_get_device(dev)) {
1639 	case DEVICEID_SK_V1:
1640 	case DEVICEID_BELKIN_5005:
1641 	case DEVICEID_3COM_3C940:
1642 	case DEVICEID_LINKSYS_EG1032:
1643 	case DEVICEID_DLINK_DGE530T_A1:
1644 	case DEVICEID_DLINK_DGE530T_B1:
1645 		/* Stay with VPD PN. */
1646 		(void) pci_get_vpd_ident(dev, &pname);
1647 		break;
1648 	case DEVICEID_SK_V2:
1649 		/* YUKON VPD PN might bear no resemblance to reality. */
1650 		switch (sc->sk_type) {
1651 		case SK_GENESIS:
1652 			/* Stay with VPD PN. */
1653 			(void) pci_get_vpd_ident(dev, &pname);
1654 			break;
1655 		case SK_YUKON:
1656 			pname = "Marvell Yukon Gigabit Ethernet";
1657 			break;
1658 		case SK_YUKON_LITE:
1659 			pname = "Marvell Yukon Lite Gigabit Ethernet";
1660 			break;
1661 		case SK_YUKON_LP:
1662 			pname = "Marvell Yukon LP Gigabit Ethernet";
1663 			break;
1664 		default:
1665 			pname = "Marvell Yukon (Unknown) Gigabit Ethernet";
1666 			break;
1667 		}
1668 
1669 		/* Yukon Lite Rev. A0 needs special test. */
1670 		if (sc->sk_type == SK_YUKON || sc->sk_type == SK_YUKON_LP) {
1671 			u_int32_t far;
1672 			u_int8_t testbyte;
1673 
1674 			/* Save flash address register before testing. */
1675 			far = sk_win_read_4(sc, SK_EP_ADDR);
1676 
1677 			sk_win_write_1(sc, SK_EP_ADDR+0x03, 0xff);
1678 			testbyte = sk_win_read_1(sc, SK_EP_ADDR+0x03);
1679 
1680 			if (testbyte != 0x00) {
1681 				/* Yukon Lite Rev. A0 detected. */
1682 				sc->sk_type = SK_YUKON_LITE;
1683 				sc->sk_rev = SK_YUKON_LITE_REV_A0;
1684 				/* Restore flash address register. */
1685 				sk_win_write_4(sc, SK_EP_ADDR, far);
1686 			}
1687 		}
1688 		break;
1689 	default:
1690 		device_printf(dev, "unknown device: vendor=%04x, device=%04x, "
1691 			"chipver=%02x, rev=%x\n",
1692 			pci_get_vendor(dev), pci_get_device(dev),
1693 			sc->sk_type, sc->sk_rev);
1694 		error = ENXIO;
1695 		goto fail;
1696 	}
1697 
1698 	if (sc->sk_type == SK_YUKON_LITE) {
1699 		switch (sc->sk_rev) {
1700 		case SK_YUKON_LITE_REV_A0:
1701 			revstr = "A0";
1702 			break;
1703 		case SK_YUKON_LITE_REV_A1:
1704 			revstr = "A1";
1705 			break;
1706 		case SK_YUKON_LITE_REV_A3:
1707 			revstr = "A3";
1708 			break;
1709 		default:
1710 			revstr = "";
1711 			break;
1712 		}
1713 	} else {
1714 		revstr = "";
1715 	}
1716 
1717 	/* Announce the product name and more VPD data if there. */
1718 	if (pname != NULL)
1719 		device_printf(dev, "%s rev. %s(0x%x)\n",
1720 			pname, revstr, sc->sk_rev);
1721 
1722 	if (bootverbose) {
1723 		device_printf(dev, "chip ver  = 0x%02x\n", sc->sk_type);
1724 		device_printf(dev, "chip rev  = 0x%02x\n", sc->sk_rev);
1725 		device_printf(dev, "SK_EPROM0 = 0x%02x\n", skrs);
1726 		device_printf(dev, "SRAM size = 0x%06x\n", sc->sk_ramsize);
1727 	}
1728 
1729 	sc->sk_devs[SK_PORT_A] = device_add_child(dev, "sk", -1);
1730 	if (sc->sk_devs[SK_PORT_A] == NULL) {
1731 		device_printf(dev, "failed to add child for PORT_A\n");
1732 		error = ENXIO;
1733 		goto fail;
1734 	}
1735 	port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT);
1736 	if (port == NULL) {
1737 		device_printf(dev, "failed to allocate memory for "
1738 		    "ivars of PORT_A\n");
1739 		error = ENXIO;
1740 		goto fail;
1741 	}
1742 	*port = SK_PORT_A;
1743 	device_set_ivars(sc->sk_devs[SK_PORT_A], port);
1744 
1745 	if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) {
1746 		sc->sk_devs[SK_PORT_B] = device_add_child(dev, "sk", -1);
1747 		if (sc->sk_devs[SK_PORT_B] == NULL) {
1748 			device_printf(dev, "failed to add child for PORT_B\n");
1749 			error = ENXIO;
1750 			goto fail;
1751 		}
1752 		port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT);
1753 		if (port == NULL) {
1754 			device_printf(dev, "failed to allocate memory for "
1755 			    "ivars of PORT_B\n");
1756 			error = ENXIO;
1757 			goto fail;
1758 		}
1759 		*port = SK_PORT_B;
1760 		device_set_ivars(sc->sk_devs[SK_PORT_B], port);
1761 	}
1762 
1763 	/* Turn on the 'driver is loaded' LED. */
1764 	CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON);
1765 
1766 	error = bus_generic_attach(dev);
1767 	if (error) {
1768 		device_printf(dev, "failed to attach port(s)\n");
1769 		goto fail;
1770 	}
1771 
1772 	/* Hook interrupt last to avoid having to lock softc */
1773 	error = bus_setup_intr(dev, sc->sk_res[1], INTR_TYPE_NET|INTR_MPSAFE,
1774 	    NULL, sk_intr, sc, &sc->sk_intrhand);
1775 
1776 	if (error) {
1777 		device_printf(dev, "couldn't set up irq\n");
1778 		goto fail;
1779 	}
1780 
1781 fail:
1782 	if (error)
1783 		skc_detach(dev);
1784 
1785 	return(error);
1786 }
1787 
1788 /*
1789  * Shutdown hardware and free up resources. This can be called any
1790  * time after the mutex has been initialized. It is called in both
1791  * the error case in attach and the normal detach case so it needs
1792  * to be careful about only freeing resources that have actually been
1793  * allocated.
1794  */
1795 static int
1796 sk_detach(dev)
1797 	device_t		dev;
1798 {
1799 	struct sk_if_softc	*sc_if;
1800 	struct ifnet		*ifp;
1801 
1802 	sc_if = device_get_softc(dev);
1803 	KASSERT(mtx_initialized(&sc_if->sk_softc->sk_mtx),
1804 	    ("sk mutex not initialized in sk_detach"));
1805 	SK_IF_LOCK(sc_if);
1806 
1807 	ifp = sc_if->sk_ifp;
1808 	/* These should only be active if attach_xmac succeeded */
1809 	if (device_is_attached(dev)) {
1810 		sk_stop(sc_if);
1811 		/* Can't hold locks while calling detach */
1812 		SK_IF_UNLOCK(sc_if);
1813 		callout_drain(&sc_if->sk_tick_ch);
1814 		callout_drain(&sc_if->sk_watchdog_ch);
1815 		ether_ifdetach(ifp);
1816 		SK_IF_LOCK(sc_if);
1817 	}
1818 	if (ifp)
1819 		if_free(ifp);
1820 	/*
1821 	 * We're generally called from skc_detach() which is using
1822 	 * device_delete_child() to get to here. It's already trashed
1823 	 * miibus for us, so don't do it here or we'll panic.
1824 	 */
1825 	/*
1826 	if (sc_if->sk_miibus != NULL)
1827 		device_delete_child(dev, sc_if->sk_miibus);
1828 	*/
1829 	bus_generic_detach(dev);
1830 	sk_dma_jumbo_free(sc_if);
1831 	sk_dma_free(sc_if);
1832 	SK_IF_UNLOCK(sc_if);
1833 
1834 	return(0);
1835 }
1836 
1837 static int
1838 skc_detach(dev)
1839 	device_t		dev;
1840 {
1841 	struct sk_softc		*sc;
1842 
1843 	sc = device_get_softc(dev);
1844 	KASSERT(mtx_initialized(&sc->sk_mtx), ("sk mutex not initialized"));
1845 
1846 	if (device_is_alive(dev)) {
1847 		if (sc->sk_devs[SK_PORT_A] != NULL) {
1848 			free(device_get_ivars(sc->sk_devs[SK_PORT_A]), M_DEVBUF);
1849 			device_delete_child(dev, sc->sk_devs[SK_PORT_A]);
1850 		}
1851 		if (sc->sk_devs[SK_PORT_B] != NULL) {
1852 			free(device_get_ivars(sc->sk_devs[SK_PORT_B]), M_DEVBUF);
1853 			device_delete_child(dev, sc->sk_devs[SK_PORT_B]);
1854 		}
1855 		bus_generic_detach(dev);
1856 	}
1857 
1858 	if (sc->sk_intrhand)
1859 		bus_teardown_intr(dev, sc->sk_res[1], sc->sk_intrhand);
1860 	bus_release_resources(dev, sc->sk_res_spec, sc->sk_res);
1861 
1862 	mtx_destroy(&sc->sk_mii_mtx);
1863 	mtx_destroy(&sc->sk_mtx);
1864 
1865 	return(0);
1866 }
1867 
1868 struct sk_dmamap_arg {
1869 	bus_addr_t	sk_busaddr;
1870 };
1871 
1872 static void
1873 sk_dmamap_cb(arg, segs, nseg, error)
1874 	void			*arg;
1875 	bus_dma_segment_t	*segs;
1876 	int			nseg;
1877 	int			error;
1878 {
1879 	struct sk_dmamap_arg	*ctx;
1880 
1881 	if (error != 0)
1882 		return;
1883 
1884 	ctx = arg;
1885 	ctx->sk_busaddr = segs[0].ds_addr;
1886 }
1887 
1888 /*
1889  * Allocate jumbo buffer storage. The SysKonnect adapters support
1890  * "jumbograms" (9K frames), although SysKonnect doesn't currently
1891  * use them in their drivers. In order for us to use them, we need
1892  * large 9K receive buffers, however standard mbuf clusters are only
1893  * 2048 bytes in size. Consequently, we need to allocate and manage
1894  * our own jumbo buffer pool. Fortunately, this does not require an
1895  * excessive amount of additional code.
1896  */
1897 static int
1898 sk_dma_alloc(sc_if)
1899 	struct sk_if_softc	*sc_if;
1900 {
1901 	struct sk_dmamap_arg	ctx;
1902 	struct sk_txdesc	*txd;
1903 	struct sk_rxdesc	*rxd;
1904 	int			error, i;
1905 
1906 	/* create parent tag */
1907 	/*
1908 	 * XXX
1909 	 * This driver should use BUS_SPACE_MAXADDR for lowaddr argument
1910 	 * in bus_dma_tag_create(9) as the NIC would support DAC mode.
1911 	 * However bz@ reported that it does not work on amd64 with > 4GB
1912 	 * RAM. Until we have more clues of the breakage, disable DAC mode
1913 	 * by limiting DMA address to be in 32bit address space.
1914 	 */
1915 	error = bus_dma_tag_create(
1916 		    bus_get_dma_tag(sc_if->sk_if_dev),/* parent */
1917 		    1, 0,			/* algnmnt, boundary */
1918 		    BUS_SPACE_MAXADDR_32BIT,	/* lowaddr */
1919 		    BUS_SPACE_MAXADDR,		/* highaddr */
1920 		    NULL, NULL,			/* filter, filterarg */
1921 		    BUS_SPACE_MAXSIZE_32BIT,	/* maxsize */
1922 		    0,				/* nsegments */
1923 		    BUS_SPACE_MAXSIZE_32BIT,	/* maxsegsize */
1924 		    0,				/* flags */
1925 		    NULL, NULL,			/* lockfunc, lockarg */
1926 		    &sc_if->sk_cdata.sk_parent_tag);
1927 	if (error != 0) {
1928 		device_printf(sc_if->sk_if_dev,
1929 		    "failed to create parent DMA tag\n");
1930 		goto fail;
1931 	}
1932 
1933 	/* create tag for Tx ring */
1934 	error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
1935 		    SK_RING_ALIGN, 0,		/* algnmnt, boundary */
1936 		    BUS_SPACE_MAXADDR_32BIT,	/* lowaddr */
1937 		    BUS_SPACE_MAXADDR,		/* highaddr */
1938 		    NULL, NULL,			/* filter, filterarg */
1939 		    SK_TX_RING_SZ,		/* maxsize */
1940 		    1,				/* nsegments */
1941 		    SK_TX_RING_SZ,		/* maxsegsize */
1942 		    0,				/* flags */
1943 		    NULL, NULL,			/* lockfunc, lockarg */
1944 		    &sc_if->sk_cdata.sk_tx_ring_tag);
1945 	if (error != 0) {
1946 		device_printf(sc_if->sk_if_dev,
1947 		    "failed to allocate Tx ring DMA tag\n");
1948 		goto fail;
1949 	}
1950 
1951 	/* create tag for Rx ring */
1952 	error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
1953 		    SK_RING_ALIGN, 0,		/* algnmnt, boundary */
1954 		    BUS_SPACE_MAXADDR_32BIT,	/* lowaddr */
1955 		    BUS_SPACE_MAXADDR,		/* highaddr */
1956 		    NULL, NULL,			/* filter, filterarg */
1957 		    SK_RX_RING_SZ,		/* maxsize */
1958 		    1,				/* nsegments */
1959 		    SK_RX_RING_SZ,		/* maxsegsize */
1960 		    0,				/* flags */
1961 		    NULL, NULL,			/* lockfunc, lockarg */
1962 		    &sc_if->sk_cdata.sk_rx_ring_tag);
1963 	if (error != 0) {
1964 		device_printf(sc_if->sk_if_dev,
1965 		    "failed to allocate Rx ring DMA tag\n");
1966 		goto fail;
1967 	}
1968 
1969 	/* create tag for Tx buffers */
1970 	error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
1971 		    1, 0,			/* algnmnt, boundary */
1972 		    BUS_SPACE_MAXADDR,		/* lowaddr */
1973 		    BUS_SPACE_MAXADDR,		/* highaddr */
1974 		    NULL, NULL,			/* filter, filterarg */
1975 		    MCLBYTES * SK_MAXTXSEGS,	/* maxsize */
1976 		    SK_MAXTXSEGS,		/* nsegments */
1977 		    MCLBYTES,			/* maxsegsize */
1978 		    0,				/* flags */
1979 		    NULL, NULL,			/* lockfunc, lockarg */
1980 		    &sc_if->sk_cdata.sk_tx_tag);
1981 	if (error != 0) {
1982 		device_printf(sc_if->sk_if_dev,
1983 		    "failed to allocate Tx DMA tag\n");
1984 		goto fail;
1985 	}
1986 
1987 	/* create tag for Rx buffers */
1988 	error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
1989 		    1, 0,			/* algnmnt, boundary */
1990 		    BUS_SPACE_MAXADDR,		/* lowaddr */
1991 		    BUS_SPACE_MAXADDR,		/* highaddr */
1992 		    NULL, NULL,			/* filter, filterarg */
1993 		    MCLBYTES,			/* maxsize */
1994 		    1,				/* nsegments */
1995 		    MCLBYTES,			/* maxsegsize */
1996 		    0,				/* flags */
1997 		    NULL, NULL,			/* lockfunc, lockarg */
1998 		    &sc_if->sk_cdata.sk_rx_tag);
1999 	if (error != 0) {
2000 		device_printf(sc_if->sk_if_dev,
2001 		    "failed to allocate Rx DMA tag\n");
2002 		goto fail;
2003 	}
2004 
2005 	/* allocate DMA'able memory and load the DMA map for Tx ring */
2006 	error = bus_dmamem_alloc(sc_if->sk_cdata.sk_tx_ring_tag,
2007 	    (void **)&sc_if->sk_rdata.sk_tx_ring, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
2008 	    &sc_if->sk_cdata.sk_tx_ring_map);
2009 	if (error != 0) {
2010 		device_printf(sc_if->sk_if_dev,
2011 		    "failed to allocate DMA'able memory for Tx ring\n");
2012 		goto fail;
2013 	}
2014 
2015 	ctx.sk_busaddr = 0;
2016 	error = bus_dmamap_load(sc_if->sk_cdata.sk_tx_ring_tag,
2017 	    sc_if->sk_cdata.sk_tx_ring_map, sc_if->sk_rdata.sk_tx_ring,
2018 	    SK_TX_RING_SZ, sk_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
2019 	if (error != 0) {
2020 		device_printf(sc_if->sk_if_dev,
2021 		    "failed to load DMA'able memory for Tx ring\n");
2022 		goto fail;
2023 	}
2024 	sc_if->sk_rdata.sk_tx_ring_paddr = ctx.sk_busaddr;
2025 
2026 	/* allocate DMA'able memory and load the DMA map for Rx ring */
2027 	error = bus_dmamem_alloc(sc_if->sk_cdata.sk_rx_ring_tag,
2028 	    (void **)&sc_if->sk_rdata.sk_rx_ring, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
2029 	    &sc_if->sk_cdata.sk_rx_ring_map);
2030 	if (error != 0) {
2031 		device_printf(sc_if->sk_if_dev,
2032 		    "failed to allocate DMA'able memory for Rx ring\n");
2033 		goto fail;
2034 	}
2035 
2036 	ctx.sk_busaddr = 0;
2037 	error = bus_dmamap_load(sc_if->sk_cdata.sk_rx_ring_tag,
2038 	    sc_if->sk_cdata.sk_rx_ring_map, sc_if->sk_rdata.sk_rx_ring,
2039 	    SK_RX_RING_SZ, sk_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
2040 	if (error != 0) {
2041 		device_printf(sc_if->sk_if_dev,
2042 		    "failed to load DMA'able memory for Rx ring\n");
2043 		goto fail;
2044 	}
2045 	sc_if->sk_rdata.sk_rx_ring_paddr = ctx.sk_busaddr;
2046 
2047 	/* create DMA maps for Tx buffers */
2048 	for (i = 0; i < SK_TX_RING_CNT; i++) {
2049 		txd = &sc_if->sk_cdata.sk_txdesc[i];
2050 		txd->tx_m = NULL;
2051 		txd->tx_dmamap = NULL;
2052 		error = bus_dmamap_create(sc_if->sk_cdata.sk_tx_tag, 0,
2053 		    &txd->tx_dmamap);
2054 		if (error != 0) {
2055 			device_printf(sc_if->sk_if_dev,
2056 			    "failed to create Tx dmamap\n");
2057 			goto fail;
2058 		}
2059 	}
2060 
2061 	/* create DMA maps for Rx buffers */
2062 	if ((error = bus_dmamap_create(sc_if->sk_cdata.sk_rx_tag, 0,
2063 	    &sc_if->sk_cdata.sk_rx_sparemap)) != 0) {
2064 		device_printf(sc_if->sk_if_dev,
2065 		    "failed to create spare Rx dmamap\n");
2066 		goto fail;
2067 	}
2068 	for (i = 0; i < SK_RX_RING_CNT; i++) {
2069 		rxd = &sc_if->sk_cdata.sk_rxdesc[i];
2070 		rxd->rx_m = NULL;
2071 		rxd->rx_dmamap = NULL;
2072 		error = bus_dmamap_create(sc_if->sk_cdata.sk_rx_tag, 0,
2073 		    &rxd->rx_dmamap);
2074 		if (error != 0) {
2075 			device_printf(sc_if->sk_if_dev,
2076 			    "failed to create Rx dmamap\n");
2077 			goto fail;
2078 		}
2079 	}
2080 
2081 fail:
2082 	return (error);
2083 }
2084 
2085 static int
2086 sk_dma_jumbo_alloc(sc_if)
2087 	struct sk_if_softc	*sc_if;
2088 {
2089 	struct sk_dmamap_arg	ctx;
2090 	struct sk_rxdesc	*jrxd;
2091 	int			error, i;
2092 
2093 	if (jumbo_disable != 0) {
2094 		device_printf(sc_if->sk_if_dev, "disabling jumbo frame support\n");
2095 		sc_if->sk_jumbo_disable = 1;
2096 		return (0);
2097 	}
2098 	/* create tag for jumbo Rx ring */
2099 	error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
2100 		    SK_RING_ALIGN, 0,		/* algnmnt, boundary */
2101 		    BUS_SPACE_MAXADDR_32BIT,	/* lowaddr */
2102 		    BUS_SPACE_MAXADDR,		/* highaddr */
2103 		    NULL, NULL,			/* filter, filterarg */
2104 		    SK_JUMBO_RX_RING_SZ,	/* maxsize */
2105 		    1,				/* nsegments */
2106 		    SK_JUMBO_RX_RING_SZ,	/* maxsegsize */
2107 		    0,				/* flags */
2108 		    NULL, NULL,			/* lockfunc, lockarg */
2109 		    &sc_if->sk_cdata.sk_jumbo_rx_ring_tag);
2110 	if (error != 0) {
2111 		device_printf(sc_if->sk_if_dev,
2112 		    "failed to allocate jumbo Rx ring DMA tag\n");
2113 		goto jumbo_fail;
2114 	}
2115 
2116 	/* create tag for jumbo Rx buffers */
2117 	error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
2118 		    1, 0,			/* algnmnt, boundary */
2119 		    BUS_SPACE_MAXADDR,		/* lowaddr */
2120 		    BUS_SPACE_MAXADDR,		/* highaddr */
2121 		    NULL, NULL,			/* filter, filterarg */
2122 		    MJUM9BYTES,			/* maxsize */
2123 		    1,				/* nsegments */
2124 		    MJUM9BYTES,			/* maxsegsize */
2125 		    0,				/* flags */
2126 		    NULL, NULL,			/* lockfunc, lockarg */
2127 		    &sc_if->sk_cdata.sk_jumbo_rx_tag);
2128 	if (error != 0) {
2129 		device_printf(sc_if->sk_if_dev,
2130 		    "failed to allocate jumbo Rx DMA tag\n");
2131 		goto jumbo_fail;
2132 	}
2133 
2134 	/* allocate DMA'able memory and load the DMA map for jumbo Rx ring */
2135 	error = bus_dmamem_alloc(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2136 	    (void **)&sc_if->sk_rdata.sk_jumbo_rx_ring,
2137 	    BUS_DMA_NOWAIT|BUS_DMA_ZERO, &sc_if->sk_cdata.sk_jumbo_rx_ring_map);
2138 	if (error != 0) {
2139 		device_printf(sc_if->sk_if_dev,
2140 		    "failed to allocate DMA'able memory for jumbo Rx ring\n");
2141 		goto jumbo_fail;
2142 	}
2143 
2144 	ctx.sk_busaddr = 0;
2145 	error = bus_dmamap_load(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2146 	    sc_if->sk_cdata.sk_jumbo_rx_ring_map,
2147 	    sc_if->sk_rdata.sk_jumbo_rx_ring, SK_JUMBO_RX_RING_SZ, sk_dmamap_cb,
2148 	    &ctx, BUS_DMA_NOWAIT);
2149 	if (error != 0) {
2150 		device_printf(sc_if->sk_if_dev,
2151 		    "failed to load DMA'able memory for jumbo Rx ring\n");
2152 		goto jumbo_fail;
2153 	}
2154 	sc_if->sk_rdata.sk_jumbo_rx_ring_paddr = ctx.sk_busaddr;
2155 
2156 	/* create DMA maps for jumbo Rx buffers */
2157 	if ((error = bus_dmamap_create(sc_if->sk_cdata.sk_jumbo_rx_tag, 0,
2158 	    &sc_if->sk_cdata.sk_jumbo_rx_sparemap)) != 0) {
2159 		device_printf(sc_if->sk_if_dev,
2160 		    "failed to create spare jumbo Rx dmamap\n");
2161 		goto jumbo_fail;
2162 	}
2163 	for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) {
2164 		jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i];
2165 		jrxd->rx_m = NULL;
2166 		jrxd->rx_dmamap = NULL;
2167 		error = bus_dmamap_create(sc_if->sk_cdata.sk_jumbo_rx_tag, 0,
2168 		    &jrxd->rx_dmamap);
2169 		if (error != 0) {
2170 			device_printf(sc_if->sk_if_dev,
2171 			    "failed to create jumbo Rx dmamap\n");
2172 			goto jumbo_fail;
2173 		}
2174 	}
2175 
2176 	return (0);
2177 
2178 jumbo_fail:
2179 	sk_dma_jumbo_free(sc_if);
2180 	device_printf(sc_if->sk_if_dev, "disabling jumbo frame support due to "
2181 	    "resource shortage\n");
2182 	sc_if->sk_jumbo_disable = 1;
2183 	return (0);
2184 }
2185 
2186 static void
2187 sk_dma_free(sc_if)
2188 	struct sk_if_softc	*sc_if;
2189 {
2190 	struct sk_txdesc	*txd;
2191 	struct sk_rxdesc	*rxd;
2192 	int			i;
2193 
2194 	/* Tx ring */
2195 	if (sc_if->sk_cdata.sk_tx_ring_tag) {
2196 		if (sc_if->sk_cdata.sk_tx_ring_map)
2197 			bus_dmamap_unload(sc_if->sk_cdata.sk_tx_ring_tag,
2198 			    sc_if->sk_cdata.sk_tx_ring_map);
2199 		if (sc_if->sk_cdata.sk_tx_ring_map &&
2200 		    sc_if->sk_rdata.sk_tx_ring)
2201 			bus_dmamem_free(sc_if->sk_cdata.sk_tx_ring_tag,
2202 			    sc_if->sk_rdata.sk_tx_ring,
2203 			    sc_if->sk_cdata.sk_tx_ring_map);
2204 		sc_if->sk_rdata.sk_tx_ring = NULL;
2205 		sc_if->sk_cdata.sk_tx_ring_map = NULL;
2206 		bus_dma_tag_destroy(sc_if->sk_cdata.sk_tx_ring_tag);
2207 		sc_if->sk_cdata.sk_tx_ring_tag = NULL;
2208 	}
2209 	/* Rx ring */
2210 	if (sc_if->sk_cdata.sk_rx_ring_tag) {
2211 		if (sc_if->sk_cdata.sk_rx_ring_map)
2212 			bus_dmamap_unload(sc_if->sk_cdata.sk_rx_ring_tag,
2213 			    sc_if->sk_cdata.sk_rx_ring_map);
2214 		if (sc_if->sk_cdata.sk_rx_ring_map &&
2215 		    sc_if->sk_rdata.sk_rx_ring)
2216 			bus_dmamem_free(sc_if->sk_cdata.sk_rx_ring_tag,
2217 			    sc_if->sk_rdata.sk_rx_ring,
2218 			    sc_if->sk_cdata.sk_rx_ring_map);
2219 		sc_if->sk_rdata.sk_rx_ring = NULL;
2220 		sc_if->sk_cdata.sk_rx_ring_map = NULL;
2221 		bus_dma_tag_destroy(sc_if->sk_cdata.sk_rx_ring_tag);
2222 		sc_if->sk_cdata.sk_rx_ring_tag = NULL;
2223 	}
2224 	/* Tx buffers */
2225 	if (sc_if->sk_cdata.sk_tx_tag) {
2226 		for (i = 0; i < SK_TX_RING_CNT; i++) {
2227 			txd = &sc_if->sk_cdata.sk_txdesc[i];
2228 			if (txd->tx_dmamap) {
2229 				bus_dmamap_destroy(sc_if->sk_cdata.sk_tx_tag,
2230 				    txd->tx_dmamap);
2231 				txd->tx_dmamap = NULL;
2232 			}
2233 		}
2234 		bus_dma_tag_destroy(sc_if->sk_cdata.sk_tx_tag);
2235 		sc_if->sk_cdata.sk_tx_tag = NULL;
2236 	}
2237 	/* Rx buffers */
2238 	if (sc_if->sk_cdata.sk_rx_tag) {
2239 		for (i = 0; i < SK_RX_RING_CNT; i++) {
2240 			rxd = &sc_if->sk_cdata.sk_rxdesc[i];
2241 			if (rxd->rx_dmamap) {
2242 				bus_dmamap_destroy(sc_if->sk_cdata.sk_rx_tag,
2243 				    rxd->rx_dmamap);
2244 				rxd->rx_dmamap = NULL;
2245 			}
2246 		}
2247 		if (sc_if->sk_cdata.sk_rx_sparemap) {
2248 			bus_dmamap_destroy(sc_if->sk_cdata.sk_rx_tag,
2249 			    sc_if->sk_cdata.sk_rx_sparemap);
2250 			sc_if->sk_cdata.sk_rx_sparemap = NULL;
2251 		}
2252 		bus_dma_tag_destroy(sc_if->sk_cdata.sk_rx_tag);
2253 		sc_if->sk_cdata.sk_rx_tag = NULL;
2254 	}
2255 
2256 	if (sc_if->sk_cdata.sk_parent_tag) {
2257 		bus_dma_tag_destroy(sc_if->sk_cdata.sk_parent_tag);
2258 		sc_if->sk_cdata.sk_parent_tag = NULL;
2259 	}
2260 }
2261 
2262 static void
2263 sk_dma_jumbo_free(sc_if)
2264 	struct sk_if_softc	*sc_if;
2265 {
2266 	struct sk_rxdesc	*jrxd;
2267 	int			i;
2268 
2269 	/* jumbo Rx ring */
2270 	if (sc_if->sk_cdata.sk_jumbo_rx_ring_tag) {
2271 		if (sc_if->sk_cdata.sk_jumbo_rx_ring_map)
2272 			bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2273 			    sc_if->sk_cdata.sk_jumbo_rx_ring_map);
2274 		if (sc_if->sk_cdata.sk_jumbo_rx_ring_map &&
2275 		    sc_if->sk_rdata.sk_jumbo_rx_ring)
2276 			bus_dmamem_free(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2277 			    sc_if->sk_rdata.sk_jumbo_rx_ring,
2278 			    sc_if->sk_cdata.sk_jumbo_rx_ring_map);
2279 		sc_if->sk_rdata.sk_jumbo_rx_ring = NULL;
2280 		sc_if->sk_cdata.sk_jumbo_rx_ring_map = NULL;
2281 		bus_dma_tag_destroy(sc_if->sk_cdata.sk_jumbo_rx_ring_tag);
2282 		sc_if->sk_cdata.sk_jumbo_rx_ring_tag = NULL;
2283 	}
2284 
2285 	/* jumbo Rx buffers */
2286 	if (sc_if->sk_cdata.sk_jumbo_rx_tag) {
2287 		for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) {
2288 			jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i];
2289 			if (jrxd->rx_dmamap) {
2290 				bus_dmamap_destroy(
2291 				    sc_if->sk_cdata.sk_jumbo_rx_tag,
2292 				    jrxd->rx_dmamap);
2293 				jrxd->rx_dmamap = NULL;
2294 			}
2295 		}
2296 		if (sc_if->sk_cdata.sk_jumbo_rx_sparemap) {
2297 			bus_dmamap_destroy(sc_if->sk_cdata.sk_jumbo_rx_tag,
2298 			    sc_if->sk_cdata.sk_jumbo_rx_sparemap);
2299 			sc_if->sk_cdata.sk_jumbo_rx_sparemap = NULL;
2300 		}
2301 		bus_dma_tag_destroy(sc_if->sk_cdata.sk_jumbo_rx_tag);
2302 		sc_if->sk_cdata.sk_jumbo_rx_tag = NULL;
2303 	}
2304 }
2305 
2306 static void
2307 sk_txcksum(ifp, m, f)
2308 	struct ifnet		*ifp;
2309 	struct mbuf		*m;
2310 	struct sk_tx_desc	*f;
2311 {
2312 	struct ip		*ip;
2313 	u_int16_t		offset;
2314 	u_int8_t 		*p;
2315 
2316 	offset = sizeof(struct ip) + ETHER_HDR_LEN;
2317 	for(; m && m->m_len == 0; m = m->m_next)
2318 		;
2319 	if (m == NULL || m->m_len < ETHER_HDR_LEN) {
2320 		if_printf(ifp, "%s: m_len < ETHER_HDR_LEN\n", __func__);
2321 		/* checksum may be corrupted */
2322 		goto sendit;
2323 	}
2324 	if (m->m_len < ETHER_HDR_LEN + sizeof(u_int32_t)) {
2325 		if (m->m_len != ETHER_HDR_LEN) {
2326 			if_printf(ifp, "%s: m_len != ETHER_HDR_LEN\n",
2327 			    __func__);
2328 			/* checksum may be corrupted */
2329 			goto sendit;
2330 		}
2331 		for(m = m->m_next; m && m->m_len == 0; m = m->m_next)
2332 			;
2333 		if (m == NULL) {
2334 			offset = sizeof(struct ip) + ETHER_HDR_LEN;
2335 			/* checksum may be corrupted */
2336 			goto sendit;
2337 		}
2338 		ip = mtod(m, struct ip *);
2339 	} else {
2340 		p = mtod(m, u_int8_t *);
2341 		p += ETHER_HDR_LEN;
2342 		ip = (struct ip *)p;
2343 	}
2344 	offset = (ip->ip_hl << 2) + ETHER_HDR_LEN;
2345 
2346 sendit:
2347 	f->sk_csum_startval = 0;
2348 	f->sk_csum_start = htole32(((offset + m->m_pkthdr.csum_data) & 0xffff) |
2349 	    (offset << 16));
2350 }
2351 
2352 static int
2353 sk_encap(sc_if, m_head)
2354         struct sk_if_softc	*sc_if;
2355         struct mbuf		**m_head;
2356 {
2357 	struct sk_txdesc	*txd;
2358 	struct sk_tx_desc	*f = NULL;
2359 	struct mbuf		*m;
2360 	bus_dma_segment_t	txsegs[SK_MAXTXSEGS];
2361 	u_int32_t		cflags, frag, si, sk_ctl;
2362 	int			error, i, nseg;
2363 
2364 	SK_IF_LOCK_ASSERT(sc_if);
2365 
2366 	if ((txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txfreeq)) == NULL)
2367 		return (ENOBUFS);
2368 
2369 	error = bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_tx_tag,
2370 	    txd->tx_dmamap, *m_head, txsegs, &nseg, 0);
2371 	if (error == EFBIG) {
2372 		m = m_defrag(*m_head, M_DONTWAIT);
2373 		if (m == NULL) {
2374 			m_freem(*m_head);
2375 			*m_head = NULL;
2376 			return (ENOMEM);
2377 		}
2378 		*m_head = m;
2379 		error = bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_tx_tag,
2380 		    txd->tx_dmamap, *m_head, txsegs, &nseg, 0);
2381 		if (error != 0) {
2382 			m_freem(*m_head);
2383 			*m_head = NULL;
2384 			return (error);
2385 		}
2386 	} else if (error != 0)
2387 		return (error);
2388 	if (nseg == 0) {
2389 		m_freem(*m_head);
2390 		*m_head = NULL;
2391 		return (EIO);
2392 	}
2393 	if (sc_if->sk_cdata.sk_tx_cnt + nseg >= SK_TX_RING_CNT) {
2394 		bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap);
2395 		return (ENOBUFS);
2396 	}
2397 
2398 	m = *m_head;
2399 	if ((m->m_pkthdr.csum_flags & sc_if->sk_ifp->if_hwassist) != 0)
2400 		cflags = SK_OPCODE_CSUM;
2401 	else
2402 		cflags = SK_OPCODE_DEFAULT;
2403 	si = frag = sc_if->sk_cdata.sk_tx_prod;
2404 	for (i = 0; i < nseg; i++) {
2405 		f = &sc_if->sk_rdata.sk_tx_ring[frag];
2406 		f->sk_data_lo = htole32(SK_ADDR_LO(txsegs[i].ds_addr));
2407 		f->sk_data_hi = htole32(SK_ADDR_HI(txsegs[i].ds_addr));
2408 		sk_ctl = txsegs[i].ds_len | cflags;
2409 		if (i == 0) {
2410 			if (cflags == SK_OPCODE_CSUM)
2411 				sk_txcksum(sc_if->sk_ifp, m, f);
2412 			sk_ctl |= SK_TXCTL_FIRSTFRAG;
2413 		} else
2414 			sk_ctl |= SK_TXCTL_OWN;
2415 		f->sk_ctl = htole32(sk_ctl);
2416 		sc_if->sk_cdata.sk_tx_cnt++;
2417 		SK_INC(frag, SK_TX_RING_CNT);
2418 	}
2419 	sc_if->sk_cdata.sk_tx_prod = frag;
2420 
2421 	/* set EOF on the last desciptor */
2422 	frag = (frag + SK_TX_RING_CNT - 1) % SK_TX_RING_CNT;
2423 	f = &sc_if->sk_rdata.sk_tx_ring[frag];
2424 	f->sk_ctl |= htole32(SK_TXCTL_LASTFRAG | SK_TXCTL_EOF_INTR);
2425 
2426 	/* turn the first descriptor ownership to NIC */
2427 	f = &sc_if->sk_rdata.sk_tx_ring[si];
2428 	f->sk_ctl |= htole32(SK_TXCTL_OWN);
2429 
2430 	STAILQ_REMOVE_HEAD(&sc_if->sk_cdata.sk_txfreeq, tx_q);
2431 	STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txbusyq, txd, tx_q);
2432 	txd->tx_m = m;
2433 
2434 	/* sync descriptors */
2435 	bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap,
2436 	    BUS_DMASYNC_PREWRITE);
2437 	bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag,
2438 	    sc_if->sk_cdata.sk_tx_ring_map,
2439 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2440 
2441 	return (0);
2442 }
2443 
2444 static void
2445 sk_start(ifp)
2446 	struct ifnet		*ifp;
2447 {
2448 	struct sk_if_softc *sc_if;
2449 
2450 	sc_if = ifp->if_softc;
2451 
2452 	SK_IF_LOCK(sc_if);
2453 	sk_start_locked(ifp);
2454 	SK_IF_UNLOCK(sc_if);
2455 
2456 	return;
2457 }
2458 
2459 static void
2460 sk_start_locked(ifp)
2461 	struct ifnet		*ifp;
2462 {
2463         struct sk_softc		*sc;
2464         struct sk_if_softc	*sc_if;
2465         struct mbuf		*m_head;
2466 	int			enq;
2467 
2468 	sc_if = ifp->if_softc;
2469 	sc = sc_if->sk_softc;
2470 
2471 	SK_IF_LOCK_ASSERT(sc_if);
2472 
2473 	for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
2474 	    sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 1; ) {
2475 		IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2476 		if (m_head == NULL)
2477 			break;
2478 
2479 		/*
2480 		 * Pack the data into the transmit ring. If we
2481 		 * don't have room, set the OACTIVE flag and wait
2482 		 * for the NIC to drain the ring.
2483 		 */
2484 		if (sk_encap(sc_if, &m_head)) {
2485 			if (m_head == NULL)
2486 				break;
2487 			IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
2488 			ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2489 			break;
2490 		}
2491 
2492 		enq++;
2493 		/*
2494 		 * If there's a BPF listener, bounce a copy of this frame
2495 		 * to him.
2496 		 */
2497 		BPF_MTAP(ifp, m_head);
2498 	}
2499 
2500 	if (enq > 0) {
2501 		/* Transmit */
2502 		CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START);
2503 
2504 		/* Set a timeout in case the chip goes out to lunch. */
2505 		sc_if->sk_watchdog_timer = 5;
2506 	}
2507 }
2508 
2509 
2510 static void
2511 sk_watchdog(arg)
2512 	void			*arg;
2513 {
2514 	struct sk_if_softc	*sc_if;
2515 	struct ifnet		*ifp;
2516 
2517 	ifp = arg;
2518 	sc_if = ifp->if_softc;
2519 
2520 	SK_IF_LOCK_ASSERT(sc_if);
2521 
2522 	if (sc_if->sk_watchdog_timer == 0 || --sc_if->sk_watchdog_timer)
2523 		goto done;
2524 
2525 	/*
2526 	 * Reclaim first as there is a possibility of losing Tx completion
2527 	 * interrupts.
2528 	 */
2529 	sk_txeof(sc_if);
2530 	if (sc_if->sk_cdata.sk_tx_cnt != 0) {
2531 		if_printf(sc_if->sk_ifp, "watchdog timeout\n");
2532 		ifp->if_oerrors++;
2533 		ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2534 		sk_init_locked(sc_if);
2535 	}
2536 
2537 done:
2538 	callout_reset(&sc_if->sk_watchdog_ch, hz, sk_watchdog, ifp);
2539 
2540 	return;
2541 }
2542 
2543 static int
2544 skc_shutdown(dev)
2545 	device_t		dev;
2546 {
2547 	struct sk_softc		*sc;
2548 
2549 	sc = device_get_softc(dev);
2550 	SK_LOCK(sc);
2551 
2552 	/* Turn off the 'driver is loaded' LED. */
2553 	CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF);
2554 
2555 	/*
2556 	 * Reset the GEnesis controller. Doing this should also
2557 	 * assert the resets on the attached XMAC(s).
2558 	 */
2559 	sk_reset(sc);
2560 	SK_UNLOCK(sc);
2561 
2562 	return (0);
2563 }
2564 
2565 static int
2566 skc_suspend(dev)
2567 	device_t		dev;
2568 {
2569 	struct sk_softc		*sc;
2570 	struct sk_if_softc	*sc_if0, *sc_if1;
2571 	struct ifnet		*ifp0 = NULL, *ifp1 = NULL;
2572 
2573 	sc = device_get_softc(dev);
2574 
2575 	SK_LOCK(sc);
2576 
2577 	sc_if0 = sc->sk_if[SK_PORT_A];
2578 	sc_if1 = sc->sk_if[SK_PORT_B];
2579 	if (sc_if0 != NULL)
2580 		ifp0 = sc_if0->sk_ifp;
2581 	if (sc_if1 != NULL)
2582 		ifp1 = sc_if1->sk_ifp;
2583 	if (ifp0 != NULL)
2584 		sk_stop(sc_if0);
2585 	if (ifp1 != NULL)
2586 		sk_stop(sc_if1);
2587 	sc->sk_suspended = 1;
2588 
2589 	SK_UNLOCK(sc);
2590 
2591 	return (0);
2592 }
2593 
2594 static int
2595 skc_resume(dev)
2596 	device_t		dev;
2597 {
2598 	struct sk_softc		*sc;
2599 	struct sk_if_softc	*sc_if0, *sc_if1;
2600 	struct ifnet		*ifp0 = NULL, *ifp1 = NULL;
2601 
2602 	sc = device_get_softc(dev);
2603 
2604 	SK_LOCK(sc);
2605 
2606 	sc_if0 = sc->sk_if[SK_PORT_A];
2607 	sc_if1 = sc->sk_if[SK_PORT_B];
2608 	if (sc_if0 != NULL)
2609 		ifp0 = sc_if0->sk_ifp;
2610 	if (sc_if1 != NULL)
2611 		ifp1 = sc_if1->sk_ifp;
2612 	if (ifp0 != NULL && ifp0->if_flags & IFF_UP)
2613 		sk_init_locked(sc_if0);
2614 	if (ifp1 != NULL && ifp1->if_flags & IFF_UP)
2615 		sk_init_locked(sc_if1);
2616 	sc->sk_suspended = 0;
2617 
2618 	SK_UNLOCK(sc);
2619 
2620 	return (0);
2621 }
2622 
2623 /*
2624  * According to the data sheet from SK-NET GENESIS the hardware can compute
2625  * two Rx checksums at the same time(Each checksum start position is
2626  * programmed in Rx descriptors). However it seems that TCP/UDP checksum
2627  * does not work at least on my Yukon hardware. I tried every possible ways
2628  * to get correct checksum value but couldn't get correct one. So TCP/UDP
2629  * checksum offload was disabled at the moment and only IP checksum offload
2630  * was enabled.
2631  * As nomral IP header size is 20 bytes I can't expect it would give an
2632  * increase in throughput. However it seems it doesn't hurt performance in
2633  * my testing. If there is a more detailed information for checksum secret
2634  * of the hardware in question please contact yongari@FreeBSD.org to add
2635  * TCP/UDP checksum offload support.
2636  */
2637 static __inline void
2638 sk_rxcksum(ifp, m, csum)
2639 	struct ifnet		*ifp;
2640 	struct mbuf		*m;
2641 	u_int32_t		csum;
2642 {
2643 	struct ether_header	*eh;
2644 	struct ip		*ip;
2645 	int32_t			hlen, len, pktlen;
2646 	u_int16_t		csum1, csum2, ipcsum;
2647 
2648 	pktlen = m->m_pkthdr.len;
2649 	if (pktlen < sizeof(struct ether_header) + sizeof(struct ip))
2650 		return;
2651 	eh = mtod(m, struct ether_header *);
2652 	if (eh->ether_type != htons(ETHERTYPE_IP))
2653 		return;
2654 	ip = (struct ip *)(eh + 1);
2655 	if (ip->ip_v != IPVERSION)
2656 		return;
2657 	hlen = ip->ip_hl << 2;
2658 	pktlen -= sizeof(struct ether_header);
2659 	if (hlen < sizeof(struct ip))
2660 		return;
2661 	if (ntohs(ip->ip_len) < hlen)
2662 		return;
2663 	if (ntohs(ip->ip_len) != pktlen)
2664 		return;
2665 
2666 	csum1 = htons(csum & 0xffff);
2667 	csum2 = htons((csum >> 16) & 0xffff);
2668 	ipcsum = in_addword(csum1, ~csum2 & 0xffff);
2669 	/* checksum fixup for IP options */
2670 	len = hlen - sizeof(struct ip);
2671 	if (len > 0) {
2672 		/*
2673 		 * If the second checksum value is correct we can compute IP
2674 		 * checksum with simple math. Unfortunately the second checksum
2675 		 * value is wrong so we can't verify the checksum from the
2676 		 * value(It seems there is some magic here to get correct
2677 		 * value). If the second checksum value is correct it also
2678 		 * means we can get TCP/UDP checksum) here. However, it still
2679 		 * needs pseudo header checksum calculation due to hardware
2680 		 * limitations.
2681 		 */
2682 		return;
2683 	}
2684 	m->m_pkthdr.csum_flags = CSUM_IP_CHECKED;
2685 	if (ipcsum == 0xffff)
2686 		m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2687 }
2688 
2689 static __inline int
2690 sk_rxvalid(sc, stat, len)
2691 	struct sk_softc		*sc;
2692 	u_int32_t		stat, len;
2693 {
2694 
2695 	if (sc->sk_type == SK_GENESIS) {
2696 		if ((stat & XM_RXSTAT_ERRFRAME) == XM_RXSTAT_ERRFRAME ||
2697 		    XM_RXSTAT_BYTES(stat) != len)
2698 			return (0);
2699 	} else {
2700 		if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR |
2701 		    YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC |
2702 		    YU_RXSTAT_JABBER)) != 0 ||
2703 		    (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK ||
2704 		    YU_RXSTAT_BYTES(stat) != len)
2705 			return (0);
2706 	}
2707 
2708 	return (1);
2709 }
2710 
2711 static void
2712 sk_rxeof(sc_if)
2713 	struct sk_if_softc	*sc_if;
2714 {
2715 	struct sk_softc		*sc;
2716 	struct mbuf		*m;
2717 	struct ifnet		*ifp;
2718 	struct sk_rx_desc	*cur_rx;
2719 	struct sk_rxdesc	*rxd;
2720 	int			cons, prog;
2721 	u_int32_t		csum, rxstat, sk_ctl;
2722 
2723 	sc = sc_if->sk_softc;
2724 	ifp = sc_if->sk_ifp;
2725 
2726 	SK_IF_LOCK_ASSERT(sc_if);
2727 
2728 	bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag,
2729 	    sc_if->sk_cdata.sk_rx_ring_map, BUS_DMASYNC_POSTREAD);
2730 
2731 	prog = 0;
2732 	for (cons = sc_if->sk_cdata.sk_rx_cons; prog < SK_RX_RING_CNT;
2733 	    prog++, SK_INC(cons, SK_RX_RING_CNT)) {
2734 		cur_rx = &sc_if->sk_rdata.sk_rx_ring[cons];
2735 		sk_ctl = le32toh(cur_rx->sk_ctl);
2736 		if ((sk_ctl & SK_RXCTL_OWN) != 0)
2737 			break;
2738 		rxd = &sc_if->sk_cdata.sk_rxdesc[cons];
2739 		rxstat = le32toh(cur_rx->sk_xmac_rxstat);
2740 
2741 		if ((sk_ctl & (SK_RXCTL_STATUS_VALID | SK_RXCTL_FIRSTFRAG |
2742 		    SK_RXCTL_LASTFRAG)) != (SK_RXCTL_STATUS_VALID |
2743 		    SK_RXCTL_FIRSTFRAG | SK_RXCTL_LASTFRAG) ||
2744 		    SK_RXBYTES(sk_ctl) < SK_MIN_FRAMELEN ||
2745 		    SK_RXBYTES(sk_ctl) > SK_MAX_FRAMELEN ||
2746 		    sk_rxvalid(sc, rxstat, SK_RXBYTES(sk_ctl)) == 0) {
2747 			ifp->if_ierrors++;
2748 			sk_discard_rxbuf(sc_if, cons);
2749 			continue;
2750 		}
2751 
2752 		m = rxd->rx_m;
2753 		csum = le32toh(cur_rx->sk_csum);
2754 		if (sk_newbuf(sc_if, cons) != 0) {
2755 			ifp->if_iqdrops++;
2756 			/* reuse old buffer */
2757 			sk_discard_rxbuf(sc_if, cons);
2758 			continue;
2759 		}
2760 		m->m_pkthdr.rcvif = ifp;
2761 		m->m_pkthdr.len = m->m_len = SK_RXBYTES(sk_ctl);
2762 		ifp->if_ipackets++;
2763 		if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
2764 			sk_rxcksum(ifp, m, csum);
2765 		SK_IF_UNLOCK(sc_if);
2766 		(*ifp->if_input)(ifp, m);
2767 		SK_IF_LOCK(sc_if);
2768 	}
2769 
2770 	if (prog > 0) {
2771 		sc_if->sk_cdata.sk_rx_cons = cons;
2772 		bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag,
2773 		    sc_if->sk_cdata.sk_rx_ring_map,
2774 		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2775 	}
2776 }
2777 
2778 static void
2779 sk_jumbo_rxeof(sc_if)
2780 	struct sk_if_softc	*sc_if;
2781 {
2782 	struct sk_softc		*sc;
2783 	struct mbuf		*m;
2784 	struct ifnet		*ifp;
2785 	struct sk_rx_desc	*cur_rx;
2786 	struct sk_rxdesc	*jrxd;
2787 	int			cons, prog;
2788 	u_int32_t		csum, rxstat, sk_ctl;
2789 
2790 	sc = sc_if->sk_softc;
2791 	ifp = sc_if->sk_ifp;
2792 
2793 	SK_IF_LOCK_ASSERT(sc_if);
2794 
2795 	bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2796 	    sc_if->sk_cdata.sk_jumbo_rx_ring_map, BUS_DMASYNC_POSTREAD);
2797 
2798 	prog = 0;
2799 	for (cons = sc_if->sk_cdata.sk_jumbo_rx_cons;
2800 	    prog < SK_JUMBO_RX_RING_CNT;
2801 	    prog++, SK_INC(cons, SK_JUMBO_RX_RING_CNT)) {
2802 		cur_rx = &sc_if->sk_rdata.sk_jumbo_rx_ring[cons];
2803 		sk_ctl = le32toh(cur_rx->sk_ctl);
2804 		if ((sk_ctl & SK_RXCTL_OWN) != 0)
2805 			break;
2806 		jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[cons];
2807 		rxstat = le32toh(cur_rx->sk_xmac_rxstat);
2808 
2809 		if ((sk_ctl & (SK_RXCTL_STATUS_VALID | SK_RXCTL_FIRSTFRAG |
2810 		    SK_RXCTL_LASTFRAG)) != (SK_RXCTL_STATUS_VALID |
2811 		    SK_RXCTL_FIRSTFRAG | SK_RXCTL_LASTFRAG) ||
2812 		    SK_RXBYTES(sk_ctl) < SK_MIN_FRAMELEN ||
2813 		    SK_RXBYTES(sk_ctl) > SK_JUMBO_FRAMELEN ||
2814 		    sk_rxvalid(sc, rxstat, SK_RXBYTES(sk_ctl)) == 0) {
2815 			ifp->if_ierrors++;
2816 			sk_discard_jumbo_rxbuf(sc_if, cons);
2817 			continue;
2818 		}
2819 
2820 		m = jrxd->rx_m;
2821 		csum = le32toh(cur_rx->sk_csum);
2822 		if (sk_jumbo_newbuf(sc_if, cons) != 0) {
2823 			ifp->if_iqdrops++;
2824 			/* reuse old buffer */
2825 			sk_discard_jumbo_rxbuf(sc_if, cons);
2826 			continue;
2827 		}
2828 		m->m_pkthdr.rcvif = ifp;
2829 		m->m_pkthdr.len = m->m_len = SK_RXBYTES(sk_ctl);
2830 		ifp->if_ipackets++;
2831 		if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
2832 			sk_rxcksum(ifp, m, csum);
2833 		SK_IF_UNLOCK(sc_if);
2834 		(*ifp->if_input)(ifp, m);
2835 		SK_IF_LOCK(sc_if);
2836 	}
2837 
2838 	if (prog > 0) {
2839 		sc_if->sk_cdata.sk_jumbo_rx_cons = cons;
2840 		bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2841 		    sc_if->sk_cdata.sk_jumbo_rx_ring_map,
2842 		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2843 	}
2844 }
2845 
2846 static void
2847 sk_txeof(sc_if)
2848 	struct sk_if_softc	*sc_if;
2849 {
2850 	struct sk_softc		*sc;
2851 	struct sk_txdesc	*txd;
2852 	struct sk_tx_desc	*cur_tx;
2853 	struct ifnet		*ifp;
2854 	u_int32_t		idx, sk_ctl;
2855 
2856 	sc = sc_if->sk_softc;
2857 	ifp = sc_if->sk_ifp;
2858 
2859 	txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txbusyq);
2860 	if (txd == NULL)
2861 		return;
2862 	bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag,
2863 	    sc_if->sk_cdata.sk_tx_ring_map, BUS_DMASYNC_POSTREAD);
2864 	/*
2865 	 * Go through our tx ring and free mbufs for those
2866 	 * frames that have been sent.
2867 	 */
2868 	for (idx = sc_if->sk_cdata.sk_tx_cons;; SK_INC(idx, SK_TX_RING_CNT)) {
2869 		if (sc_if->sk_cdata.sk_tx_cnt <= 0)
2870 			break;
2871 		cur_tx = &sc_if->sk_rdata.sk_tx_ring[idx];
2872 		sk_ctl = le32toh(cur_tx->sk_ctl);
2873 		if (sk_ctl & SK_TXCTL_OWN)
2874 			break;
2875 		sc_if->sk_cdata.sk_tx_cnt--;
2876 		ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2877 		if ((sk_ctl & SK_TXCTL_LASTFRAG) == 0)
2878 			continue;
2879 		bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap,
2880 		    BUS_DMASYNC_POSTWRITE);
2881 		bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap);
2882 
2883 		ifp->if_opackets++;
2884 		m_freem(txd->tx_m);
2885 		txd->tx_m = NULL;
2886 		STAILQ_REMOVE_HEAD(&sc_if->sk_cdata.sk_txbusyq, tx_q);
2887 		STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txfreeq, txd, tx_q);
2888 		txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txbusyq);
2889 	}
2890 	sc_if->sk_cdata.sk_tx_cons = idx;
2891 	sc_if->sk_watchdog_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0;
2892 
2893 	bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag,
2894 	    sc_if->sk_cdata.sk_tx_ring_map,
2895 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2896 }
2897 
2898 static void
2899 sk_tick(xsc_if)
2900 	void			*xsc_if;
2901 {
2902 	struct sk_if_softc	*sc_if;
2903 	struct mii_data		*mii;
2904 	struct ifnet		*ifp;
2905 	int			i;
2906 
2907 	sc_if = xsc_if;
2908 	ifp = sc_if->sk_ifp;
2909 	mii = device_get_softc(sc_if->sk_miibus);
2910 
2911 	if (!(ifp->if_flags & IFF_UP))
2912 		return;
2913 
2914 	if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
2915 		sk_intr_bcom(sc_if);
2916 		return;
2917 	}
2918 
2919 	/*
2920 	 * According to SysKonnect, the correct way to verify that
2921 	 * the link has come back up is to poll bit 0 of the GPIO
2922 	 * register three times. This pin has the signal from the
2923 	 * link_sync pin connected to it; if we read the same link
2924 	 * state 3 times in a row, we know the link is up.
2925 	 */
2926 	for (i = 0; i < 3; i++) {
2927 		if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET)
2928 			break;
2929 	}
2930 
2931 	if (i != 3) {
2932 		callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
2933 		return;
2934 	}
2935 
2936 	/* Turn the GP0 interrupt back on. */
2937 	SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
2938 	SK_XM_READ_2(sc_if, XM_ISR);
2939 	mii_tick(mii);
2940 	callout_stop(&sc_if->sk_tick_ch);
2941 }
2942 
2943 static void
2944 sk_yukon_tick(xsc_if)
2945 	void			*xsc_if;
2946 {
2947 	struct sk_if_softc	*sc_if;
2948 	struct mii_data		*mii;
2949 
2950 	sc_if = xsc_if;
2951 	mii = device_get_softc(sc_if->sk_miibus);
2952 
2953 	mii_tick(mii);
2954 	callout_reset(&sc_if->sk_tick_ch, hz, sk_yukon_tick, sc_if);
2955 }
2956 
2957 static void
2958 sk_intr_bcom(sc_if)
2959 	struct sk_if_softc	*sc_if;
2960 {
2961 	struct mii_data		*mii;
2962 	struct ifnet		*ifp;
2963 	int			status;
2964 	mii = device_get_softc(sc_if->sk_miibus);
2965 	ifp = sc_if->sk_ifp;
2966 
2967 	SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
2968 
2969 	/*
2970 	 * Read the PHY interrupt register to make sure
2971 	 * we clear any pending interrupts.
2972 	 */
2973 	status = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, BRGPHY_MII_ISR);
2974 
2975 	if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
2976 		sk_init_xmac(sc_if);
2977 		return;
2978 	}
2979 
2980 	if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) {
2981 		int			lstat;
2982 		lstat = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM,
2983 		    BRGPHY_MII_AUXSTS);
2984 
2985 		if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) {
2986 			mii_mediachg(mii);
2987 			/* Turn off the link LED. */
2988 			SK_IF_WRITE_1(sc_if, 0,
2989 			    SK_LINKLED1_CTL, SK_LINKLED_OFF);
2990 			sc_if->sk_link = 0;
2991 		} else if (status & BRGPHY_ISR_LNK_CHG) {
2992 			sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
2993 	    		    BRGPHY_MII_IMR, 0xFF00);
2994 			mii_tick(mii);
2995 			sc_if->sk_link = 1;
2996 			/* Turn on the link LED. */
2997 			SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
2998 			    SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF|
2999 			    SK_LINKLED_BLINK_OFF);
3000 		} else {
3001 			mii_tick(mii);
3002 			callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
3003 		}
3004 	}
3005 
3006 	SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
3007 
3008 	return;
3009 }
3010 
3011 static void
3012 sk_intr_xmac(sc_if)
3013 	struct sk_if_softc	*sc_if;
3014 {
3015 	struct sk_softc		*sc;
3016 	u_int16_t		status;
3017 
3018 	sc = sc_if->sk_softc;
3019 	status = SK_XM_READ_2(sc_if, XM_ISR);
3020 
3021 	/*
3022 	 * Link has gone down. Start MII tick timeout to
3023 	 * watch for link resync.
3024 	 */
3025 	if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) {
3026 		if (status & XM_ISR_GP0_SET) {
3027 			SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
3028 			callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
3029 		}
3030 
3031 		if (status & XM_ISR_AUTONEG_DONE) {
3032 			callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
3033 		}
3034 	}
3035 
3036 	if (status & XM_IMR_TX_UNDERRUN)
3037 		SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO);
3038 
3039 	if (status & XM_IMR_RX_OVERRUN)
3040 		SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO);
3041 
3042 	status = SK_XM_READ_2(sc_if, XM_ISR);
3043 
3044 	return;
3045 }
3046 
3047 static void
3048 sk_intr_yukon(sc_if)
3049 	struct sk_if_softc	*sc_if;
3050 {
3051 	u_int8_t status;
3052 
3053 	status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR);
3054 	/* RX overrun */
3055 	if ((status & SK_GMAC_INT_RX_OVER) != 0) {
3056 		SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST,
3057 		    SK_RFCTL_RX_FIFO_OVER);
3058 	}
3059 	/* TX underrun */
3060 	if ((status & SK_GMAC_INT_TX_UNDER) != 0) {
3061 		SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST,
3062 		    SK_TFCTL_TX_FIFO_UNDER);
3063 	}
3064 }
3065 
3066 static void
3067 sk_intr(xsc)
3068 	void			*xsc;
3069 {
3070 	struct sk_softc		*sc = xsc;
3071 	struct sk_if_softc	*sc_if0, *sc_if1;
3072 	struct ifnet		*ifp0 = NULL, *ifp1 = NULL;
3073 	u_int32_t		status;
3074 
3075 	SK_LOCK(sc);
3076 
3077 	status = CSR_READ_4(sc, SK_ISSR);
3078 	if (status == 0 || status == 0xffffffff || sc->sk_suspended)
3079 		goto done_locked;
3080 
3081 	sc_if0 = sc->sk_if[SK_PORT_A];
3082 	sc_if1 = sc->sk_if[SK_PORT_B];
3083 
3084 	if (sc_if0 != NULL)
3085 		ifp0 = sc_if0->sk_ifp;
3086 	if (sc_if1 != NULL)
3087 		ifp1 = sc_if1->sk_ifp;
3088 
3089 	for (; (status &= sc->sk_intrmask) != 0;) {
3090 		/* Handle receive interrupts first. */
3091 		if (status & SK_ISR_RX1_EOF) {
3092 			if (ifp0->if_mtu > SK_MAX_FRAMELEN)
3093 				sk_jumbo_rxeof(sc_if0);
3094 			else
3095 				sk_rxeof(sc_if0);
3096 			CSR_WRITE_4(sc, SK_BMU_RX_CSR0,
3097 			    SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
3098 		}
3099 		if (status & SK_ISR_RX2_EOF) {
3100 			if (ifp1->if_mtu > SK_MAX_FRAMELEN)
3101 				sk_jumbo_rxeof(sc_if1);
3102 			else
3103 				sk_rxeof(sc_if1);
3104 			CSR_WRITE_4(sc, SK_BMU_RX_CSR1,
3105 			    SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
3106 		}
3107 
3108 		/* Then transmit interrupts. */
3109 		if (status & SK_ISR_TX1_S_EOF) {
3110 			sk_txeof(sc_if0);
3111 			CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, SK_TXBMU_CLR_IRQ_EOF);
3112 		}
3113 		if (status & SK_ISR_TX2_S_EOF) {
3114 			sk_txeof(sc_if1);
3115 			CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, SK_TXBMU_CLR_IRQ_EOF);
3116 		}
3117 
3118 		/* Then MAC interrupts. */
3119 		if (status & SK_ISR_MAC1 &&
3120 		    ifp0->if_drv_flags & IFF_DRV_RUNNING) {
3121 			if (sc->sk_type == SK_GENESIS)
3122 				sk_intr_xmac(sc_if0);
3123 			else
3124 				sk_intr_yukon(sc_if0);
3125 		}
3126 
3127 		if (status & SK_ISR_MAC2 &&
3128 		    ifp1->if_drv_flags & IFF_DRV_RUNNING) {
3129 			if (sc->sk_type == SK_GENESIS)
3130 				sk_intr_xmac(sc_if1);
3131 			else
3132 				sk_intr_yukon(sc_if1);
3133 		}
3134 
3135 		if (status & SK_ISR_EXTERNAL_REG) {
3136 			if (ifp0 != NULL &&
3137 			    sc_if0->sk_phytype == SK_PHYTYPE_BCOM)
3138 				sk_intr_bcom(sc_if0);
3139 			if (ifp1 != NULL &&
3140 			    sc_if1->sk_phytype == SK_PHYTYPE_BCOM)
3141 				sk_intr_bcom(sc_if1);
3142 		}
3143 		status = CSR_READ_4(sc, SK_ISSR);
3144 	}
3145 
3146 	CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
3147 
3148 	if (ifp0 != NULL && !IFQ_DRV_IS_EMPTY(&ifp0->if_snd))
3149 		sk_start_locked(ifp0);
3150 	if (ifp1 != NULL && !IFQ_DRV_IS_EMPTY(&ifp1->if_snd))
3151 		sk_start_locked(ifp1);
3152 
3153 done_locked:
3154 	SK_UNLOCK(sc);
3155 }
3156 
3157 static void
3158 sk_init_xmac(sc_if)
3159 	struct sk_if_softc	*sc_if;
3160 {
3161 	struct sk_softc		*sc;
3162 	struct ifnet		*ifp;
3163 	u_int16_t		eaddr[(ETHER_ADDR_LEN+1)/2];
3164 	struct sk_bcom_hack	bhack[] = {
3165 	{ 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 },
3166 	{ 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 },
3167 	{ 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
3168 	{ 0, 0 } };
3169 
3170 	SK_IF_LOCK_ASSERT(sc_if);
3171 
3172 	sc = sc_if->sk_softc;
3173 	ifp = sc_if->sk_ifp;
3174 
3175 	/* Unreset the XMAC. */
3176 	SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET);
3177 	DELAY(1000);
3178 
3179 	/* Reset the XMAC's internal state. */
3180 	SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
3181 
3182 	/* Save the XMAC II revision */
3183 	sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID));
3184 
3185 	/*
3186 	 * Perform additional initialization for external PHYs,
3187 	 * namely for the 1000baseTX cards that use the XMAC's
3188 	 * GMII mode.
3189 	 */
3190 	if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
3191 		int			i = 0;
3192 		u_int32_t		val;
3193 
3194 		/* Take PHY out of reset. */
3195 		val = sk_win_read_4(sc, SK_GPIO);
3196 		if (sc_if->sk_port == SK_PORT_A)
3197 			val |= SK_GPIO_DIR0|SK_GPIO_DAT0;
3198 		else
3199 			val |= SK_GPIO_DIR2|SK_GPIO_DAT2;
3200 		sk_win_write_4(sc, SK_GPIO, val);
3201 
3202 		/* Enable GMII mode on the XMAC. */
3203 		SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE);
3204 
3205 		sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
3206 		    BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET);
3207 		DELAY(10000);
3208 		sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
3209 		    BRGPHY_MII_IMR, 0xFFF0);
3210 
3211 		/*
3212 		 * Early versions of the BCM5400 apparently have
3213 		 * a bug that requires them to have their reserved
3214 		 * registers initialized to some magic values. I don't
3215 		 * know what the numbers do, I'm just the messenger.
3216 		 */
3217 		if (sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 0x03)
3218 		    == 0x6041) {
3219 			while(bhack[i].reg) {
3220 				sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
3221 				    bhack[i].reg, bhack[i].val);
3222 				i++;
3223 			}
3224 		}
3225 	}
3226 
3227 	/* Set station address */
3228 	bcopy(IF_LLADDR(sc_if->sk_ifp), eaddr, ETHER_ADDR_LEN);
3229 	SK_XM_WRITE_2(sc_if, XM_PAR0, eaddr[0]);
3230 	SK_XM_WRITE_2(sc_if, XM_PAR1, eaddr[1]);
3231 	SK_XM_WRITE_2(sc_if, XM_PAR2, eaddr[2]);
3232 	SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION);
3233 
3234 	if (ifp->if_flags & IFF_BROADCAST) {
3235 		SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
3236 	} else {
3237 		SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
3238 	}
3239 
3240 	/* We don't need the FCS appended to the packet. */
3241 	SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS);
3242 
3243 	/* We want short frames padded to 60 bytes. */
3244 	SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD);
3245 
3246 	/*
3247 	 * Enable the reception of all error frames. This is is
3248 	 * a necessary evil due to the design of the XMAC. The
3249 	 * XMAC's receive FIFO is only 8K in size, however jumbo
3250 	 * frames can be up to 9000 bytes in length. When bad
3251 	 * frame filtering is enabled, the XMAC's RX FIFO operates
3252 	 * in 'store and forward' mode. For this to work, the
3253 	 * entire frame has to fit into the FIFO, but that means
3254 	 * that jumbo frames larger than 8192 bytes will be
3255 	 * truncated. Disabling all bad frame filtering causes
3256 	 * the RX FIFO to operate in streaming mode, in which
3257 	 * case the XMAC will start transfering frames out of the
3258 	 * RX FIFO as soon as the FIFO threshold is reached.
3259 	 */
3260 	if (ifp->if_mtu > SK_MAX_FRAMELEN) {
3261 		SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES|
3262 		    XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS|
3263 		    XM_MODE_RX_INRANGELEN);
3264 		SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK);
3265 	} else
3266 		SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK);
3267 
3268 	/*
3269 	 * Bump up the transmit threshold. This helps hold off transmit
3270 	 * underruns when we're blasting traffic from both ports at once.
3271 	 */
3272 	SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH);
3273 
3274 	/* Set Rx filter */
3275 	sk_rxfilter_genesis(sc_if);
3276 
3277 	/* Clear and enable interrupts */
3278 	SK_XM_READ_2(sc_if, XM_ISR);
3279 	if (sc_if->sk_phytype == SK_PHYTYPE_XMAC)
3280 		SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS);
3281 	else
3282 		SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
3283 
3284 	/* Configure MAC arbiter */
3285 	switch(sc_if->sk_xmac_rev) {
3286 	case XM_XMAC_REV_B2:
3287 		sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2);
3288 		sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2);
3289 		sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2);
3290 		sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2);
3291 		sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2);
3292 		sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2);
3293 		sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2);
3294 		sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2);
3295 		sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
3296 		break;
3297 	case XM_XMAC_REV_C1:
3298 		sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1);
3299 		sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1);
3300 		sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1);
3301 		sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1);
3302 		sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1);
3303 		sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1);
3304 		sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1);
3305 		sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1);
3306 		sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
3307 		break;
3308 	default:
3309 		break;
3310 	}
3311 	sk_win_write_2(sc, SK_MACARB_CTL,
3312 	    SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF);
3313 
3314 	sc_if->sk_link = 1;
3315 
3316 	return;
3317 }
3318 
3319 static void
3320 sk_init_yukon(sc_if)
3321 	struct sk_if_softc	*sc_if;
3322 {
3323 	u_int32_t		phy, v;
3324 	u_int16_t		reg;
3325 	struct sk_softc		*sc;
3326 	struct ifnet		*ifp;
3327 	int			i;
3328 
3329 	SK_IF_LOCK_ASSERT(sc_if);
3330 
3331 	sc = sc_if->sk_softc;
3332 	ifp = sc_if->sk_ifp;
3333 
3334 	if (sc->sk_type == SK_YUKON_LITE &&
3335 	    sc->sk_rev >= SK_YUKON_LITE_REV_A3) {
3336 		/*
3337 		 * Workaround code for COMA mode, set PHY reset.
3338 		 * Otherwise it will not correctly take chip out of
3339 		 * powerdown (coma)
3340 		 */
3341 		v = sk_win_read_4(sc, SK_GPIO);
3342 		v |= SK_GPIO_DIR9 | SK_GPIO_DAT9;
3343 		sk_win_write_4(sc, SK_GPIO, v);
3344 	}
3345 
3346 	/* GMAC and GPHY Reset */
3347 	SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET);
3348 	SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET);
3349 	DELAY(1000);
3350 
3351 	if (sc->sk_type == SK_YUKON_LITE &&
3352 	    sc->sk_rev >= SK_YUKON_LITE_REV_A3) {
3353 		/*
3354 		 * Workaround code for COMA mode, clear PHY reset
3355 		 */
3356 		v = sk_win_read_4(sc, SK_GPIO);
3357 		v |= SK_GPIO_DIR9;
3358 		v &= ~SK_GPIO_DAT9;
3359 		sk_win_write_4(sc, SK_GPIO, v);
3360 	}
3361 
3362 	phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP |
3363 		SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE;
3364 
3365 	if (sc->sk_coppertype)
3366 		phy |= SK_GPHY_COPPER;
3367 	else
3368 		phy |= SK_GPHY_FIBER;
3369 
3370 	SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET);
3371 	DELAY(1000);
3372 	SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR);
3373 	SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF |
3374 		      SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR);
3375 
3376 	/* unused read of the interrupt source register */
3377 	SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR);
3378 
3379 	reg = SK_YU_READ_2(sc_if, YUKON_PAR);
3380 
3381 	/* MIB Counter Clear Mode set */
3382 	reg |= YU_PAR_MIB_CLR;
3383 	SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
3384 
3385 	/* MIB Counter Clear Mode clear */
3386 	reg &= ~YU_PAR_MIB_CLR;
3387 	SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
3388 
3389 	/* receive control reg */
3390 	SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR);
3391 
3392 	/* transmit parameter register */
3393 	SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) |
3394 		      YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) );
3395 
3396 	/* serial mode register */
3397 	reg = YU_SMR_DATA_BLIND(0x1c) | YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e);
3398 	if (ifp->if_mtu > SK_MAX_FRAMELEN)
3399 		reg |= YU_SMR_MFL_JUMBO;
3400 	SK_YU_WRITE_2(sc_if, YUKON_SMR, reg);
3401 
3402 	/* Setup Yukon's address */
3403 	for (i = 0; i < 3; i++) {
3404 		/* Write Source Address 1 (unicast filter) */
3405 		SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4,
3406 			      IF_LLADDR(sc_if->sk_ifp)[i * 2] |
3407 			      IF_LLADDR(sc_if->sk_ifp)[i * 2 + 1] << 8);
3408 	}
3409 
3410 	for (i = 0; i < 3; i++) {
3411 		reg = sk_win_read_2(sc_if->sk_softc,
3412 				    SK_MAC1_0 + i * 2 + sc_if->sk_port * 8);
3413 		SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg);
3414 	}
3415 
3416 	/* Set Rx filter */
3417 	sk_rxfilter_yukon(sc_if);
3418 
3419 	/* enable interrupt mask for counter overflows */
3420 	SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0);
3421 	SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0);
3422 	SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0);
3423 
3424 	/* Configure RX MAC FIFO Flush Mask */
3425 	v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR |
3426 	    YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT |
3427 	    YU_RXSTAT_JABBER;
3428 	SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v);
3429 
3430 	/* Disable RX MAC FIFO Flush for YUKON-Lite Rev. A0 only */
3431 	if (sc->sk_type == SK_YUKON_LITE && sc->sk_rev == SK_YUKON_LITE_REV_A0)
3432 		v = SK_TFCTL_OPERATION_ON;
3433 	else
3434 		v = SK_TFCTL_OPERATION_ON | SK_RFCTL_FIFO_FLUSH_ON;
3435 	/* Configure RX MAC FIFO */
3436 	SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR);
3437 	SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, v);
3438 
3439 	/* Increase flush threshould to 64 bytes */
3440 	SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD,
3441 	    SK_RFCTL_FIFO_THRESHOLD + 1);
3442 
3443 	/* Configure TX MAC FIFO */
3444 	SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR);
3445 	SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON);
3446 }
3447 
3448 /*
3449  * Note that to properly initialize any part of the GEnesis chip,
3450  * you first have to take it out of reset mode.
3451  */
3452 static void
3453 sk_init(xsc)
3454 	void			*xsc;
3455 {
3456 	struct sk_if_softc	*sc_if = xsc;
3457 
3458 	SK_IF_LOCK(sc_if);
3459 	sk_init_locked(sc_if);
3460 	SK_IF_UNLOCK(sc_if);
3461 
3462 	return;
3463 }
3464 
3465 static void
3466 sk_init_locked(sc_if)
3467 	struct sk_if_softc	*sc_if;
3468 {
3469 	struct sk_softc		*sc;
3470 	struct ifnet		*ifp;
3471 	struct mii_data		*mii;
3472 	u_int16_t		reg;
3473 	u_int32_t		imr;
3474 	int			error;
3475 
3476 	SK_IF_LOCK_ASSERT(sc_if);
3477 
3478 	ifp = sc_if->sk_ifp;
3479 	sc = sc_if->sk_softc;
3480 	mii = device_get_softc(sc_if->sk_miibus);
3481 
3482 	if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3483 		return;
3484 
3485 	/* Cancel pending I/O and free all RX/TX buffers. */
3486 	sk_stop(sc_if);
3487 
3488 	if (sc->sk_type == SK_GENESIS) {
3489 		/* Configure LINK_SYNC LED */
3490 		SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON);
3491 		SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
3492 			SK_LINKLED_LINKSYNC_ON);
3493 
3494 		/* Configure RX LED */
3495 		SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL,
3496 			SK_RXLEDCTL_COUNTER_START);
3497 
3498 		/* Configure TX LED */
3499 		SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL,
3500 			SK_TXLEDCTL_COUNTER_START);
3501 	}
3502 
3503 	/*
3504 	 * Configure descriptor poll timer
3505 	 *
3506 	 * SK-NET GENESIS data sheet says that possibility of losing Start
3507 	 * transmit command due to CPU/cache related interim storage problems
3508 	 * under certain conditions. The document recommends a polling
3509 	 * mechanism to send a Start transmit command to initiate transfer
3510 	 * of ready descriptors regulary. To cope with this issue sk(4) now
3511 	 * enables descriptor poll timer to initiate descriptor processing
3512 	 * periodically as defined by SK_DPT_TIMER_MAX. However sk(4) still
3513 	 * issue SK_TXBMU_TX_START to Tx BMU to get fast execution of Tx
3514 	 * command instead of waiting for next descriptor polling time.
3515 	 * The same rule may apply to Rx side too but it seems that is not
3516 	 * needed at the moment.
3517 	 * Since sk(4) uses descriptor polling as a last resort there is no
3518 	 * need to set smaller polling time than maximum allowable one.
3519 	 */
3520 	SK_IF_WRITE_4(sc_if, 0, SK_DPT_INIT, SK_DPT_TIMER_MAX);
3521 
3522 	/* Configure I2C registers */
3523 
3524 	/* Configure XMAC(s) */
3525 	switch (sc->sk_type) {
3526 	case SK_GENESIS:
3527 		sk_init_xmac(sc_if);
3528 		break;
3529 	case SK_YUKON:
3530 	case SK_YUKON_LITE:
3531 	case SK_YUKON_LP:
3532 		sk_init_yukon(sc_if);
3533 		break;
3534 	}
3535 	mii_mediachg(mii);
3536 
3537 	if (sc->sk_type == SK_GENESIS) {
3538 		/* Configure MAC FIFOs */
3539 		SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET);
3540 		SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END);
3541 		SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON);
3542 
3543 		SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET);
3544 		SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END);
3545 		SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON);
3546 	}
3547 
3548 	/* Configure transmit arbiter(s) */
3549 	SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL,
3550 	    SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON);
3551 
3552 	/* Configure RAMbuffers */
3553 	SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET);
3554 	SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart);
3555 	SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart);
3556 	SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart);
3557 	SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend);
3558 	SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON);
3559 
3560 	SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET);
3561 	SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON);
3562 	SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart);
3563 	SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart);
3564 	SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart);
3565 	SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend);
3566 	SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON);
3567 
3568 	/* Configure BMUs */
3569 	SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE);
3570 	if (ifp->if_mtu > SK_MAX_FRAMELEN) {
3571 		SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO,
3572 		    SK_ADDR_LO(SK_JUMBO_RX_RING_ADDR(sc_if, 0)));
3573 		SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI,
3574 		    SK_ADDR_HI(SK_JUMBO_RX_RING_ADDR(sc_if, 0)));
3575 	} else {
3576 		SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO,
3577 		    SK_ADDR_LO(SK_RX_RING_ADDR(sc_if, 0)));
3578 		SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI,
3579 		    SK_ADDR_HI(SK_RX_RING_ADDR(sc_if, 0)));
3580 	}
3581 
3582 	SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE);
3583 	SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO,
3584 	    SK_ADDR_LO(SK_TX_RING_ADDR(sc_if, 0)));
3585 	SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI,
3586 	    SK_ADDR_HI(SK_TX_RING_ADDR(sc_if, 0)));
3587 
3588 	/* Init descriptors */
3589 	if (ifp->if_mtu > SK_MAX_FRAMELEN)
3590 		error = sk_init_jumbo_rx_ring(sc_if);
3591 	else
3592 		error = sk_init_rx_ring(sc_if);
3593 	if (error != 0) {
3594 		device_printf(sc_if->sk_if_dev,
3595 		    "initialization failed: no memory for rx buffers\n");
3596 		sk_stop(sc_if);
3597 		return;
3598 	}
3599 	sk_init_tx_ring(sc_if);
3600 
3601 	/* Set interrupt moderation if changed via sysctl. */
3602 	imr = sk_win_read_4(sc, SK_IMTIMERINIT);
3603 	if (imr != SK_IM_USECS(sc->sk_int_mod, sc->sk_int_ticks)) {
3604 		sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod,
3605 		    sc->sk_int_ticks));
3606 		if (bootverbose)
3607 			device_printf(sc_if->sk_if_dev,
3608 			    "interrupt moderation is %d us.\n",
3609 			    sc->sk_int_mod);
3610 	}
3611 
3612 	/* Configure interrupt handling */
3613 	CSR_READ_4(sc, SK_ISSR);
3614 	if (sc_if->sk_port == SK_PORT_A)
3615 		sc->sk_intrmask |= SK_INTRS1;
3616 	else
3617 		sc->sk_intrmask |= SK_INTRS2;
3618 
3619 	sc->sk_intrmask |= SK_ISR_EXTERNAL_REG;
3620 
3621 	CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
3622 
3623 	/* Start BMUs. */
3624 	SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START);
3625 
3626 	switch(sc->sk_type) {
3627 	case SK_GENESIS:
3628 		/* Enable XMACs TX and RX state machines */
3629 		SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE);
3630 		SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
3631 		break;
3632 	case SK_YUKON:
3633 	case SK_YUKON_LITE:
3634 	case SK_YUKON_LP:
3635 		reg = SK_YU_READ_2(sc_if, YUKON_GPCR);
3636 		reg |= YU_GPCR_TXEN | YU_GPCR_RXEN;
3637 #if 0
3638 		/* XXX disable 100Mbps and full duplex mode? */
3639 		reg &= ~(YU_GPCR_SPEED | YU_GPCR_DPLX_DIS);
3640 #endif
3641 		SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg);
3642 	}
3643 
3644 	/* Activate descriptor polling timer */
3645 	SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_START);
3646 	/* start transfer of Tx descriptors */
3647 	CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START);
3648 
3649 	ifp->if_drv_flags |= IFF_DRV_RUNNING;
3650 	ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3651 
3652 	switch (sc->sk_type) {
3653 	case SK_YUKON:
3654 	case SK_YUKON_LITE:
3655 	case SK_YUKON_LP:
3656 		callout_reset(&sc_if->sk_tick_ch, hz, sk_yukon_tick, sc_if);
3657 		break;
3658 	}
3659 
3660 	callout_reset(&sc_if->sk_watchdog_ch, hz, sk_watchdog, ifp);
3661 
3662 	return;
3663 }
3664 
3665 static void
3666 sk_stop(sc_if)
3667 	struct sk_if_softc	*sc_if;
3668 {
3669 	int			i;
3670 	struct sk_softc		*sc;
3671 	struct sk_txdesc	*txd;
3672 	struct sk_rxdesc	*rxd;
3673 	struct sk_rxdesc	*jrxd;
3674 	struct ifnet		*ifp;
3675 	u_int32_t		val;
3676 
3677 	SK_IF_LOCK_ASSERT(sc_if);
3678 	sc = sc_if->sk_softc;
3679 	ifp = sc_if->sk_ifp;
3680 
3681 	callout_stop(&sc_if->sk_tick_ch);
3682 	callout_stop(&sc_if->sk_watchdog_ch);
3683 
3684 	/* stop Tx descriptor polling timer */
3685 	SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP);
3686 	/* stop transfer of Tx descriptors */
3687 	CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_STOP);
3688 	for (i = 0; i < SK_TIMEOUT; i++) {
3689 		val = CSR_READ_4(sc, sc_if->sk_tx_bmu);
3690 		if ((val & SK_TXBMU_TX_STOP) == 0)
3691 			break;
3692 		DELAY(1);
3693 	}
3694 	if (i == SK_TIMEOUT)
3695 		device_printf(sc_if->sk_if_dev,
3696 		    "can not stop transfer of Tx descriptor\n");
3697 	/* stop transfer of Rx descriptors */
3698 	SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_STOP);
3699 	for (i = 0; i < SK_TIMEOUT; i++) {
3700 		val = SK_IF_READ_4(sc_if, 0, SK_RXQ1_BMU_CSR);
3701 		if ((val & SK_RXBMU_RX_STOP) == 0)
3702 			break;
3703 		DELAY(1);
3704 	}
3705 	if (i == SK_TIMEOUT)
3706 		device_printf(sc_if->sk_if_dev,
3707 		    "can not stop transfer of Rx descriptor\n");
3708 
3709 	if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
3710 		/* Put PHY back into reset. */
3711 		val = sk_win_read_4(sc, SK_GPIO);
3712 		if (sc_if->sk_port == SK_PORT_A) {
3713 			val |= SK_GPIO_DIR0;
3714 			val &= ~SK_GPIO_DAT0;
3715 		} else {
3716 			val |= SK_GPIO_DIR2;
3717 			val &= ~SK_GPIO_DAT2;
3718 		}
3719 		sk_win_write_4(sc, SK_GPIO, val);
3720 	}
3721 
3722 	/* Turn off various components of this interface. */
3723 	SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
3724 	switch (sc->sk_type) {
3725 	case SK_GENESIS:
3726 		SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_RESET);
3727 		SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET);
3728 		break;
3729 	case SK_YUKON:
3730 	case SK_YUKON_LITE:
3731 	case SK_YUKON_LP:
3732 		SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET);
3733 		SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET);
3734 		break;
3735 	}
3736 	SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE);
3737 	SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF);
3738 	SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE);
3739 	SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF);
3740 	SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF);
3741 	SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
3742 	SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
3743 	SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF);
3744 	SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF);
3745 
3746 	/* Disable interrupts */
3747 	if (sc_if->sk_port == SK_PORT_A)
3748 		sc->sk_intrmask &= ~SK_INTRS1;
3749 	else
3750 		sc->sk_intrmask &= ~SK_INTRS2;
3751 	CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
3752 
3753 	SK_XM_READ_2(sc_if, XM_ISR);
3754 	SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
3755 
3756 	/* Free RX and TX mbufs still in the queues. */
3757 	for (i = 0; i < SK_RX_RING_CNT; i++) {
3758 		rxd = &sc_if->sk_cdata.sk_rxdesc[i];
3759 		if (rxd->rx_m != NULL) {
3760 			bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag,
3761 			    rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
3762 			bus_dmamap_unload(sc_if->sk_cdata.sk_rx_tag,
3763 			    rxd->rx_dmamap);
3764 			m_freem(rxd->rx_m);
3765 			rxd->rx_m = NULL;
3766 		}
3767 	}
3768 	for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) {
3769 		jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i];
3770 		if (jrxd->rx_m != NULL) {
3771 			bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag,
3772 			    jrxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
3773 			bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_tag,
3774 			    jrxd->rx_dmamap);
3775 			m_freem(jrxd->rx_m);
3776 			jrxd->rx_m = NULL;
3777 		}
3778 	}
3779 	for (i = 0; i < SK_TX_RING_CNT; i++) {
3780 		txd = &sc_if->sk_cdata.sk_txdesc[i];
3781 		if (txd->tx_m != NULL) {
3782 			bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag,
3783 			    txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
3784 			bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag,
3785 			    txd->tx_dmamap);
3786 			m_freem(txd->tx_m);
3787 			txd->tx_m = NULL;
3788 		}
3789 	}
3790 
3791 	ifp->if_drv_flags &= ~(IFF_DRV_RUNNING|IFF_DRV_OACTIVE);
3792 
3793 	return;
3794 }
3795 
3796 static int
3797 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
3798 {
3799 	int error, value;
3800 
3801 	if (!arg1)
3802 		return (EINVAL);
3803 	value = *(int *)arg1;
3804 	error = sysctl_handle_int(oidp, &value, 0, req);
3805 	if (error || !req->newptr)
3806 		return (error);
3807 	if (value < low || value > high)
3808 		return (EINVAL);
3809 	*(int *)arg1 = value;
3810 	return (0);
3811 }
3812 
3813 static int
3814 sysctl_hw_sk_int_mod(SYSCTL_HANDLER_ARGS)
3815 {
3816 	return (sysctl_int_range(oidp, arg1, arg2, req, SK_IM_MIN, SK_IM_MAX));
3817 }
3818