1 /* 2 * Copyright (c) 1997, 1998, 1999, 2000 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD$ 33 */ 34 35 /* 36 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 37 * the SK-984x series adapters, both single port and dual port. 38 * References: 39 * The XaQti XMAC II datasheet, 40 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 41 * The SysKonnect GEnesis manual, http://www.syskonnect.com 42 * 43 * Note: XaQti has been aquired by Vitesse, and Vitesse does not have the 44 * XMAC II datasheet online. I have put my copy at www.freebsd.org as a 45 * convenience to others until Vitesse corrects this problem. 46 * 47 * Written by Bill Paul <wpaul@ee.columbia.edu> 48 * Department of Electrical Engineering 49 * Columbia University, New York City 50 */ 51 52 /* 53 * The SysKonnect gigabit ethernet adapters consist of two main 54 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 55 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 56 * components and a PHY while the GEnesis controller provides a PCI 57 * interface with DMA support. Each card may have between 512K and 58 * 2MB of SRAM on board depending on the configuration. 59 * 60 * The SysKonnect GEnesis controller can have either one or two XMAC 61 * chips connected to it, allowing single or dual port NIC configurations. 62 * SysKonnect has the distinction of being the only vendor on the market 63 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 64 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 65 * XMAC registers. This driver takes advantage of these features to allow 66 * both XMACs to operate as independent interfaces. 67 */ 68 69 #include <sys/param.h> 70 #include <sys/systm.h> 71 #include <sys/sockio.h> 72 #include <sys/mbuf.h> 73 #include <sys/malloc.h> 74 #include <sys/kernel.h> 75 #include <sys/socket.h> 76 #include <sys/queue.h> 77 78 #include <net/if.h> 79 #include <net/if_arp.h> 80 #include <net/ethernet.h> 81 #include <net/if_dl.h> 82 #include <net/if_media.h> 83 84 #include <net/bpf.h> 85 86 #include <vm/vm.h> /* for vtophys */ 87 #include <vm/pmap.h> /* for vtophys */ 88 #include <machine/clock.h> /* for DELAY */ 89 #include <machine/bus_pio.h> 90 #include <machine/bus_memio.h> 91 #include <machine/bus.h> 92 #include <machine/resource.h> 93 #include <sys/bus.h> 94 #include <sys/rman.h> 95 96 #include <dev/mii/mii.h> 97 #include <dev/mii/miivar.h> 98 #include <dev/mii/brgphyreg.h> 99 100 #include <pci/pcireg.h> 101 #include <pci/pcivar.h> 102 103 #define SK_USEIOSPACE 104 105 #include <pci/if_skreg.h> 106 #include <pci/xmaciireg.h> 107 108 MODULE_DEPEND(sk, miibus, 1, 1, 1); 109 110 /* "controller miibus0" required. See GENERIC if you get errors here. */ 111 #include "miibus_if.h" 112 113 #ifndef lint 114 static const char rcsid[] = 115 "$FreeBSD$"; 116 #endif 117 118 static struct sk_type sk_devs[] = { 119 { SK_VENDORID, SK_DEVICEID_GE, "SysKonnect Gigabit Ethernet" }, 120 { 0, 0, NULL } 121 }; 122 123 static int sk_probe __P((device_t)); 124 static int sk_attach __P((device_t)); 125 static int sk_detach __P((device_t)); 126 static int sk_detach_xmac __P((device_t)); 127 static int sk_probe_xmac __P((device_t)); 128 static int sk_attach_xmac __P((device_t)); 129 static void sk_tick __P((void *)); 130 static void sk_intr __P((void *)); 131 static void sk_intr_xmac __P((struct sk_if_softc *)); 132 static void sk_intr_bcom __P((struct sk_if_softc *)); 133 static void sk_rxeof __P((struct sk_if_softc *)); 134 static void sk_txeof __P((struct sk_if_softc *)); 135 static int sk_encap __P((struct sk_if_softc *, struct mbuf *, 136 u_int32_t *)); 137 static void sk_start __P((struct ifnet *)); 138 static int sk_ioctl __P((struct ifnet *, u_long, caddr_t)); 139 static void sk_init __P((void *)); 140 static void sk_init_xmac __P((struct sk_if_softc *)); 141 static void sk_stop __P((struct sk_if_softc *)); 142 static void sk_watchdog __P((struct ifnet *)); 143 static void sk_shutdown __P((device_t)); 144 static int sk_ifmedia_upd __P((struct ifnet *)); 145 static void sk_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 146 static void sk_reset __P((struct sk_softc *)); 147 static int sk_newbuf __P((struct sk_if_softc *, 148 struct sk_chain *, struct mbuf *)); 149 static int sk_alloc_jumbo_mem __P((struct sk_if_softc *)); 150 static void *sk_jalloc __P((struct sk_if_softc *)); 151 static void sk_jfree __P((caddr_t, u_int)); 152 static void sk_jref __P((caddr_t, u_int)); 153 static int sk_init_rx_ring __P((struct sk_if_softc *)); 154 static void sk_init_tx_ring __P((struct sk_if_softc *)); 155 static u_int32_t sk_win_read_4 __P((struct sk_softc *, int)); 156 static u_int16_t sk_win_read_2 __P((struct sk_softc *, int)); 157 static u_int8_t sk_win_read_1 __P((struct sk_softc *, int)); 158 static void sk_win_write_4 __P((struct sk_softc *, int, u_int32_t)); 159 static void sk_win_write_2 __P((struct sk_softc *, int, u_int32_t)); 160 static void sk_win_write_1 __P((struct sk_softc *, int, u_int32_t)); 161 static u_int8_t sk_vpd_readbyte __P((struct sk_softc *, int)); 162 static void sk_vpd_read_res __P((struct sk_softc *, 163 struct vpd_res *, int)); 164 static void sk_vpd_read __P((struct sk_softc *)); 165 166 static int sk_miibus_readreg __P((device_t, int, int)); 167 static int sk_miibus_writereg __P((device_t, int, int, int)); 168 static void sk_miibus_statchg __P((device_t)); 169 170 static u_int32_t sk_calchash __P((caddr_t)); 171 static void sk_setfilt __P((struct sk_if_softc *, caddr_t, int)); 172 static void sk_setmulti __P((struct sk_if_softc *)); 173 174 #ifdef SK_USEIOSPACE 175 #define SK_RES SYS_RES_IOPORT 176 #define SK_RID SK_PCI_LOIO 177 #else 178 #define SK_RES SYS_RES_MEMORY 179 #define SK_RID SK_PCI_LOMEM 180 #endif 181 182 /* 183 * Note that we have newbus methods for both the GEnesis controller 184 * itself and the XMAC(s). The XMACs are children of the GEnesis, and 185 * the miibus code is a child of the XMACs. We need to do it this way 186 * so that the miibus drivers can access the PHY registers on the 187 * right PHY. It's not quite what I had in mind, but it's the only 188 * design that achieves the desired effect. 189 */ 190 static device_method_t skc_methods[] = { 191 /* Device interface */ 192 DEVMETHOD(device_probe, sk_probe), 193 DEVMETHOD(device_attach, sk_attach), 194 DEVMETHOD(device_detach, sk_detach), 195 DEVMETHOD(device_shutdown, sk_shutdown), 196 197 /* bus interface */ 198 DEVMETHOD(bus_print_child, bus_generic_print_child), 199 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 200 201 { 0, 0 } 202 }; 203 204 static driver_t skc_driver = { 205 "skc", 206 skc_methods, 207 sizeof(struct sk_softc) 208 }; 209 210 static devclass_t skc_devclass; 211 212 static device_method_t sk_methods[] = { 213 /* Device interface */ 214 DEVMETHOD(device_probe, sk_probe_xmac), 215 DEVMETHOD(device_attach, sk_attach_xmac), 216 DEVMETHOD(device_detach, sk_detach_xmac), 217 DEVMETHOD(device_shutdown, bus_generic_shutdown), 218 219 /* bus interface */ 220 DEVMETHOD(bus_print_child, bus_generic_print_child), 221 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 222 223 /* MII interface */ 224 DEVMETHOD(miibus_readreg, sk_miibus_readreg), 225 DEVMETHOD(miibus_writereg, sk_miibus_writereg), 226 DEVMETHOD(miibus_statchg, sk_miibus_statchg), 227 228 { 0, 0 } 229 }; 230 231 static driver_t sk_driver = { 232 "sk", 233 sk_methods, 234 sizeof(struct sk_if_softc) 235 }; 236 237 static devclass_t sk_devclass; 238 239 DRIVER_MODULE(if_sk, pci, skc_driver, skc_devclass, 0, 0); 240 DRIVER_MODULE(sk, skc, sk_driver, sk_devclass, 0, 0); 241 DRIVER_MODULE(miibus, sk, miibus_driver, miibus_devclass, 0, 0); 242 243 #define SK_SETBIT(sc, reg, x) \ 244 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 245 246 #define SK_CLRBIT(sc, reg, x) \ 247 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 248 249 #define SK_WIN_SETBIT_4(sc, reg, x) \ 250 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x) 251 252 #define SK_WIN_CLRBIT_4(sc, reg, x) \ 253 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x) 254 255 #define SK_WIN_SETBIT_2(sc, reg, x) \ 256 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x) 257 258 #define SK_WIN_CLRBIT_2(sc, reg, x) \ 259 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x) 260 261 static u_int32_t sk_win_read_4(sc, reg) 262 struct sk_softc *sc; 263 int reg; 264 { 265 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 266 return(CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg))); 267 } 268 269 static u_int16_t sk_win_read_2(sc, reg) 270 struct sk_softc *sc; 271 int reg; 272 { 273 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 274 return(CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg))); 275 } 276 277 static u_int8_t sk_win_read_1(sc, reg) 278 struct sk_softc *sc; 279 int reg; 280 { 281 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 282 return(CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg))); 283 } 284 285 static void sk_win_write_4(sc, reg, val) 286 struct sk_softc *sc; 287 int reg; 288 u_int32_t val; 289 { 290 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 291 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), val); 292 return; 293 } 294 295 static void sk_win_write_2(sc, reg, val) 296 struct sk_softc *sc; 297 int reg; 298 u_int32_t val; 299 { 300 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 301 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), (u_int32_t)val); 302 return; 303 } 304 305 static void sk_win_write_1(sc, reg, val) 306 struct sk_softc *sc; 307 int reg; 308 u_int32_t val; 309 { 310 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 311 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), val); 312 return; 313 } 314 315 /* 316 * The VPD EEPROM contains Vital Product Data, as suggested in 317 * the PCI 2.1 specification. The VPD data is separared into areas 318 * denoted by resource IDs. The SysKonnect VPD contains an ID string 319 * resource (the name of the adapter), a read-only area resource 320 * containing various key/data fields and a read/write area which 321 * can be used to store asset management information or log messages. 322 * We read the ID string and read-only into buffers attached to 323 * the controller softc structure for later use. At the moment, 324 * we only use the ID string during sk_attach(). 325 */ 326 static u_int8_t sk_vpd_readbyte(sc, addr) 327 struct sk_softc *sc; 328 int addr; 329 { 330 int i; 331 332 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 333 for (i = 0; i < SK_TIMEOUT; i++) { 334 DELAY(1); 335 if (sk_win_read_2(sc, 336 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 337 break; 338 } 339 340 if (i == SK_TIMEOUT) 341 return(0); 342 343 return(sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA))); 344 } 345 346 static void sk_vpd_read_res(sc, res, addr) 347 struct sk_softc *sc; 348 struct vpd_res *res; 349 int addr; 350 { 351 int i; 352 u_int8_t *ptr; 353 354 ptr = (u_int8_t *)res; 355 for (i = 0; i < sizeof(struct vpd_res); i++) 356 ptr[i] = sk_vpd_readbyte(sc, i + addr); 357 358 return; 359 } 360 361 static void sk_vpd_read(sc) 362 struct sk_softc *sc; 363 { 364 int pos = 0, i; 365 struct vpd_res res; 366 367 if (sc->sk_vpd_prodname != NULL) 368 free(sc->sk_vpd_prodname, M_DEVBUF); 369 if (sc->sk_vpd_readonly != NULL) 370 free(sc->sk_vpd_readonly, M_DEVBUF); 371 sc->sk_vpd_prodname = NULL; 372 sc->sk_vpd_readonly = NULL; 373 374 sk_vpd_read_res(sc, &res, pos); 375 376 if (res.vr_id != VPD_RES_ID) { 377 printf("skc%d: bad VPD resource id: expected %x got %x\n", 378 sc->sk_unit, VPD_RES_ID, res.vr_id); 379 return; 380 } 381 382 pos += sizeof(res); 383 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 384 for (i = 0; i < res.vr_len; i++) 385 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 386 sc->sk_vpd_prodname[i] = '\0'; 387 pos += i; 388 389 sk_vpd_read_res(sc, &res, pos); 390 391 if (res.vr_id != VPD_RES_READ) { 392 printf("skc%d: bad VPD resource id: expected %x got %x\n", 393 sc->sk_unit, VPD_RES_READ, res.vr_id); 394 return; 395 } 396 397 pos += sizeof(res); 398 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 399 for (i = 0; i < res.vr_len + 1; i++) 400 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 401 402 return; 403 } 404 405 static int sk_miibus_readreg(dev, phy, reg) 406 device_t dev; 407 int phy, reg; 408 { 409 struct sk_if_softc *sc_if; 410 int i; 411 412 sc_if = device_get_softc(dev); 413 414 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 415 return(0); 416 417 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 418 SK_XM_READ_2(sc_if, XM_PHY_DATA); 419 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 420 for (i = 0; i < SK_TIMEOUT; i++) { 421 DELAY(1); 422 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 423 XM_MMUCMD_PHYDATARDY) 424 break; 425 } 426 427 if (i == SK_TIMEOUT) { 428 printf("sk%d: phy failed to come ready\n", 429 sc_if->sk_unit); 430 return(0); 431 } 432 } 433 DELAY(1); 434 return(SK_XM_READ_2(sc_if, XM_PHY_DATA)); 435 } 436 437 static int sk_miibus_writereg(dev, phy, reg, val) 438 device_t dev; 439 int phy, reg, val; 440 { 441 struct sk_if_softc *sc_if; 442 int i; 443 444 sc_if = device_get_softc(dev); 445 446 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 447 for (i = 0; i < SK_TIMEOUT; i++) { 448 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 449 break; 450 } 451 452 if (i == SK_TIMEOUT) { 453 printf("sk%d: phy failed to come ready\n", sc_if->sk_unit); 454 return(ETIMEDOUT); 455 } 456 457 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 458 for (i = 0; i < SK_TIMEOUT; i++) { 459 DELAY(1); 460 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 461 break; 462 } 463 464 if (i == SK_TIMEOUT) 465 printf("sk%d: phy write timed out\n", sc_if->sk_unit); 466 467 return(0); 468 } 469 470 static void sk_miibus_statchg(dev) 471 device_t dev; 472 { 473 struct sk_if_softc *sc_if; 474 struct mii_data *mii; 475 476 sc_if = device_get_softc(dev); 477 mii = device_get_softc(sc_if->sk_miibus); 478 479 /* 480 * If this is a GMII PHY, manually set the XMAC's 481 * duplex mode accordingly. 482 */ 483 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 484 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 485 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 486 } else { 487 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 488 } 489 } 490 491 return; 492 } 493 494 #define SK_POLY 0xEDB88320 495 #define SK_BITS 6 496 497 static u_int32_t sk_calchash(addr) 498 caddr_t addr; 499 { 500 u_int32_t idx, bit, data, crc; 501 502 /* Compute CRC for the address value. */ 503 crc = 0xFFFFFFFF; /* initial value */ 504 505 for (idx = 0; idx < 6; idx++) { 506 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 507 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? SK_POLY : 0); 508 } 509 510 return (~crc & ((1 << SK_BITS) - 1)); 511 } 512 513 static void sk_setfilt(sc_if, addr, slot) 514 struct sk_if_softc *sc_if; 515 caddr_t addr; 516 int slot; 517 { 518 int base; 519 520 base = XM_RXFILT_ENTRY(slot); 521 522 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 523 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 524 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 525 526 return; 527 } 528 529 static void sk_setmulti(sc_if) 530 struct sk_if_softc *sc_if; 531 { 532 struct ifnet *ifp; 533 u_int32_t hashes[2] = { 0, 0 }; 534 int h, i; 535 struct ifmultiaddr *ifma; 536 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 537 538 ifp = &sc_if->arpcom.ac_if; 539 540 /* First, zot all the existing filters. */ 541 for (i = 1; i < XM_RXFILT_MAX; i++) 542 sk_setfilt(sc_if, (caddr_t)&dummy, i); 543 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 544 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 545 546 /* Now program new ones. */ 547 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 548 hashes[0] = 0xFFFFFFFF; 549 hashes[1] = 0xFFFFFFFF; 550 } else { 551 i = 1; 552 /* First find the tail of the list. */ 553 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 554 ifma = ifma->ifma_link.le_next) { 555 if (ifma->ifma_link.le_next == NULL) 556 break; 557 } 558 /* Now traverse the list backwards. */ 559 for (; ifma != NULL && ifma != (void *)&ifp->if_multiaddrs; 560 ifma = (struct ifmultiaddr *)ifma->ifma_link.le_prev) { 561 if (ifma->ifma_addr->sa_family != AF_LINK) 562 continue; 563 /* 564 * Program the first XM_RXFILT_MAX multicast groups 565 * into the perfect filter. For all others, 566 * use the hash table. 567 */ 568 if (i < XM_RXFILT_MAX) { 569 sk_setfilt(sc_if, 570 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i); 571 i++; 572 continue; 573 } 574 575 h = sk_calchash( 576 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 577 if (h < 32) 578 hashes[0] |= (1 << h); 579 else 580 hashes[1] |= (1 << (h - 32)); 581 } 582 } 583 584 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 585 XM_MODE_RX_USE_PERFECT); 586 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 587 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 588 589 return; 590 } 591 592 static int sk_init_rx_ring(sc_if) 593 struct sk_if_softc *sc_if; 594 { 595 struct sk_chain_data *cd; 596 struct sk_ring_data *rd; 597 int i; 598 599 cd = &sc_if->sk_cdata; 600 rd = sc_if->sk_rdata; 601 602 bzero((char *)rd->sk_rx_ring, 603 sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 604 605 for (i = 0; i < SK_RX_RING_CNT; i++) { 606 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 607 if (sk_newbuf(sc_if, &cd->sk_rx_chain[i], NULL) == ENOBUFS) 608 return(ENOBUFS); 609 if (i == (SK_RX_RING_CNT - 1)) { 610 cd->sk_rx_chain[i].sk_next = 611 &cd->sk_rx_chain[0]; 612 rd->sk_rx_ring[i].sk_next = 613 vtophys(&rd->sk_rx_ring[0]); 614 } else { 615 cd->sk_rx_chain[i].sk_next = 616 &cd->sk_rx_chain[i + 1]; 617 rd->sk_rx_ring[i].sk_next = 618 vtophys(&rd->sk_rx_ring[i + 1]); 619 } 620 } 621 622 sc_if->sk_cdata.sk_rx_prod = 0; 623 sc_if->sk_cdata.sk_rx_cons = 0; 624 625 return(0); 626 } 627 628 static void sk_init_tx_ring(sc_if) 629 struct sk_if_softc *sc_if; 630 { 631 struct sk_chain_data *cd; 632 struct sk_ring_data *rd; 633 int i; 634 635 cd = &sc_if->sk_cdata; 636 rd = sc_if->sk_rdata; 637 638 bzero((char *)sc_if->sk_rdata->sk_tx_ring, 639 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 640 641 for (i = 0; i < SK_TX_RING_CNT; i++) { 642 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 643 if (i == (SK_TX_RING_CNT - 1)) { 644 cd->sk_tx_chain[i].sk_next = 645 &cd->sk_tx_chain[0]; 646 rd->sk_tx_ring[i].sk_next = 647 vtophys(&rd->sk_tx_ring[0]); 648 } else { 649 cd->sk_tx_chain[i].sk_next = 650 &cd->sk_tx_chain[i + 1]; 651 rd->sk_tx_ring[i].sk_next = 652 vtophys(&rd->sk_tx_ring[i + 1]); 653 } 654 } 655 656 sc_if->sk_cdata.sk_tx_prod = 0; 657 sc_if->sk_cdata.sk_tx_cons = 0; 658 sc_if->sk_cdata.sk_tx_cnt = 0; 659 660 return; 661 } 662 663 static int sk_newbuf(sc_if, c, m) 664 struct sk_if_softc *sc_if; 665 struct sk_chain *c; 666 struct mbuf *m; 667 { 668 struct mbuf *m_new = NULL; 669 struct sk_rx_desc *r; 670 671 if (m == NULL) { 672 caddr_t *buf = NULL; 673 674 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 675 if (m_new == NULL) { 676 printf("sk%d: no memory for rx list -- " 677 "packet dropped!\n", sc_if->sk_unit); 678 return(ENOBUFS); 679 } 680 681 /* Allocate the jumbo buffer */ 682 buf = sk_jalloc(sc_if); 683 if (buf == NULL) { 684 m_freem(m_new); 685 #ifdef SK_VERBOSE 686 printf("sk%d: jumbo allocation failed " 687 "-- packet dropped!\n", sc_if->sk_unit); 688 #endif 689 return(ENOBUFS); 690 } 691 692 /* Attach the buffer to the mbuf */ 693 m_new->m_data = m_new->m_ext.ext_buf = (void *)buf; 694 m_new->m_flags |= M_EXT; 695 m_new->m_ext.ext_size = m_new->m_pkthdr.len = 696 m_new->m_len = SK_MCLBYTES; 697 m_new->m_ext.ext_free = sk_jfree; 698 m_new->m_ext.ext_ref = sk_jref; 699 } else { 700 /* 701 * We're re-using a previously allocated mbuf; 702 * be sure to re-init pointers and lengths to 703 * default values. 704 */ 705 m_new = m; 706 m_new->m_len = m_new->m_pkthdr.len = SK_MCLBYTES; 707 m_new->m_data = m_new->m_ext.ext_buf; 708 } 709 710 /* 711 * Adjust alignment so packet payload begins on a 712 * longword boundary. Mandatory for Alpha, useful on 713 * x86 too. 714 */ 715 m_adj(m_new, ETHER_ALIGN); 716 717 r = c->sk_desc; 718 c->sk_mbuf = m_new; 719 r->sk_data_lo = vtophys(mtod(m_new, caddr_t)); 720 r->sk_ctl = m_new->m_len | SK_RXSTAT; 721 722 return(0); 723 } 724 725 /* 726 * Allocate jumbo buffer storage. The SysKonnect adapters support 727 * "jumbograms" (9K frames), although SysKonnect doesn't currently 728 * use them in their drivers. In order for us to use them, we need 729 * large 9K receive buffers, however standard mbuf clusters are only 730 * 2048 bytes in size. Consequently, we need to allocate and manage 731 * our own jumbo buffer pool. Fortunately, this does not require an 732 * excessive amount of additional code. 733 */ 734 static int sk_alloc_jumbo_mem(sc_if) 735 struct sk_if_softc *sc_if; 736 { 737 caddr_t ptr; 738 register int i; 739 struct sk_jpool_entry *entry; 740 741 /* Grab a big chunk o' storage. */ 742 sc_if->sk_cdata.sk_jumbo_buf = contigmalloc(SK_JMEM, M_DEVBUF, 743 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 744 745 if (sc_if->sk_cdata.sk_jumbo_buf == NULL) { 746 printf("sk%d: no memory for jumbo buffers!\n", sc_if->sk_unit); 747 return(ENOBUFS); 748 } 749 750 SLIST_INIT(&sc_if->sk_jfree_listhead); 751 SLIST_INIT(&sc_if->sk_jinuse_listhead); 752 753 /* 754 * Now divide it up into 9K pieces and save the addresses 755 * in an array. Note that we play an evil trick here by using 756 * the first few bytes in the buffer to hold the the address 757 * of the softc structure for this interface. This is because 758 * sk_jfree() needs it, but it is called by the mbuf management 759 * code which will not pass it to us explicitly. 760 */ 761 ptr = sc_if->sk_cdata.sk_jumbo_buf; 762 for (i = 0; i < SK_JSLOTS; i++) { 763 u_int64_t **aptr; 764 aptr = (u_int64_t **)ptr; 765 aptr[0] = (u_int64_t *)sc_if; 766 ptr += sizeof(u_int64_t); 767 sc_if->sk_cdata.sk_jslots[i].sk_buf = ptr; 768 sc_if->sk_cdata.sk_jslots[i].sk_inuse = 0; 769 ptr += SK_MCLBYTES; 770 entry = malloc(sizeof(struct sk_jpool_entry), 771 M_DEVBUF, M_NOWAIT); 772 if (entry == NULL) { 773 free(sc_if->sk_cdata.sk_jumbo_buf, M_DEVBUF); 774 sc_if->sk_cdata.sk_jumbo_buf = NULL; 775 printf("sk%d: no memory for jumbo " 776 "buffer queue!\n", sc_if->sk_unit); 777 return(ENOBUFS); 778 } 779 entry->slot = i; 780 SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 781 entry, jpool_entries); 782 } 783 784 return(0); 785 } 786 787 /* 788 * Allocate a jumbo buffer. 789 */ 790 static void *sk_jalloc(sc_if) 791 struct sk_if_softc *sc_if; 792 { 793 struct sk_jpool_entry *entry; 794 795 entry = SLIST_FIRST(&sc_if->sk_jfree_listhead); 796 797 if (entry == NULL) { 798 #ifdef SK_VERBOSE 799 printf("sk%d: no free jumbo buffers\n", sc_if->sk_unit); 800 #endif 801 return(NULL); 802 } 803 804 SLIST_REMOVE_HEAD(&sc_if->sk_jfree_listhead, jpool_entries); 805 SLIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 806 sc_if->sk_cdata.sk_jslots[entry->slot].sk_inuse = 1; 807 return(sc_if->sk_cdata.sk_jslots[entry->slot].sk_buf); 808 } 809 810 /* 811 * Adjust usage count on a jumbo buffer. In general this doesn't 812 * get used much because our jumbo buffers don't get passed around 813 * a lot, but it's implemented for correctness. 814 */ 815 static void sk_jref(buf, size) 816 caddr_t buf; 817 u_int size; 818 { 819 struct sk_if_softc *sc_if; 820 u_int64_t **aptr; 821 register int i; 822 823 /* Extract the softc struct pointer. */ 824 aptr = (u_int64_t **)(buf - sizeof(u_int64_t)); 825 sc_if = (struct sk_if_softc *)(aptr[0]); 826 827 if (sc_if == NULL) 828 panic("sk_jref: can't find softc pointer!"); 829 830 if (size != SK_MCLBYTES) 831 panic("sk_jref: adjusting refcount of buf of wrong size!"); 832 833 /* calculate the slot this buffer belongs to */ 834 835 i = ((vm_offset_t)aptr 836 - (vm_offset_t)sc_if->sk_cdata.sk_jumbo_buf) / SK_JLEN; 837 838 if ((i < 0) || (i >= SK_JSLOTS)) 839 panic("sk_jref: asked to reference buffer " 840 "that we don't manage!"); 841 else if (sc_if->sk_cdata.sk_jslots[i].sk_inuse == 0) 842 panic("sk_jref: buffer already free!"); 843 else 844 sc_if->sk_cdata.sk_jslots[i].sk_inuse++; 845 846 return; 847 } 848 849 /* 850 * Release a jumbo buffer. 851 */ 852 static void sk_jfree(buf, size) 853 caddr_t buf; 854 u_int size; 855 { 856 struct sk_if_softc *sc_if; 857 u_int64_t **aptr; 858 int i; 859 struct sk_jpool_entry *entry; 860 861 /* Extract the softc struct pointer. */ 862 aptr = (u_int64_t **)(buf - sizeof(u_int64_t)); 863 sc_if = (struct sk_if_softc *)(aptr[0]); 864 865 if (sc_if == NULL) 866 panic("sk_jfree: can't find softc pointer!"); 867 868 if (size != SK_MCLBYTES) 869 panic("sk_jfree: freeing buffer of wrong size!"); 870 871 /* calculate the slot this buffer belongs to */ 872 873 i = ((vm_offset_t)aptr 874 - (vm_offset_t)sc_if->sk_cdata.sk_jumbo_buf) / SK_JLEN; 875 876 if ((i < 0) || (i >= SK_JSLOTS)) 877 panic("sk_jfree: asked to free buffer that we don't manage!"); 878 else if (sc_if->sk_cdata.sk_jslots[i].sk_inuse == 0) 879 panic("sk_jfree: buffer already free!"); 880 else { 881 sc_if->sk_cdata.sk_jslots[i].sk_inuse--; 882 if(sc_if->sk_cdata.sk_jslots[i].sk_inuse == 0) { 883 entry = SLIST_FIRST(&sc_if->sk_jinuse_listhead); 884 if (entry == NULL) 885 panic("sk_jfree: buffer not in use!"); 886 entry->slot = i; 887 SLIST_REMOVE_HEAD(&sc_if->sk_jinuse_listhead, 888 jpool_entries); 889 SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 890 entry, jpool_entries); 891 } 892 } 893 894 return; 895 } 896 897 /* 898 * Set media options. 899 */ 900 static int sk_ifmedia_upd(ifp) 901 struct ifnet *ifp; 902 { 903 struct sk_if_softc *sc_if; 904 struct mii_data *mii; 905 906 sc_if = ifp->if_softc; 907 mii = device_get_softc(sc_if->sk_miibus); 908 sk_init(sc_if); 909 mii_mediachg(mii); 910 911 return(0); 912 } 913 914 /* 915 * Report current media status. 916 */ 917 static void sk_ifmedia_sts(ifp, ifmr) 918 struct ifnet *ifp; 919 struct ifmediareq *ifmr; 920 { 921 struct sk_if_softc *sc_if; 922 struct mii_data *mii; 923 924 sc_if = ifp->if_softc; 925 mii = device_get_softc(sc_if->sk_miibus); 926 927 mii_pollstat(mii); 928 ifmr->ifm_active = mii->mii_media_active; 929 ifmr->ifm_status = mii->mii_media_status; 930 931 return; 932 } 933 934 static int sk_ioctl(ifp, command, data) 935 struct ifnet *ifp; 936 u_long command; 937 caddr_t data; 938 { 939 struct sk_if_softc *sc_if = ifp->if_softc; 940 struct ifreq *ifr = (struct ifreq *) data; 941 int s, error = 0; 942 struct mii_data *mii; 943 944 s = splimp(); 945 946 switch(command) { 947 case SIOCSIFADDR: 948 case SIOCGIFADDR: 949 error = ether_ioctl(ifp, command, data); 950 break; 951 case SIOCSIFMTU: 952 if (ifr->ifr_mtu > SK_JUMBO_MTU) 953 error = EINVAL; 954 else { 955 ifp->if_mtu = ifr->ifr_mtu; 956 sk_init(sc_if); 957 } 958 break; 959 case SIOCSIFFLAGS: 960 if (ifp->if_flags & IFF_UP) { 961 if (ifp->if_flags & IFF_RUNNING && 962 ifp->if_flags & IFF_PROMISC && 963 !(sc_if->sk_if_flags & IFF_PROMISC)) { 964 SK_XM_SETBIT_4(sc_if, XM_MODE, 965 XM_MODE_RX_PROMISC); 966 sk_setmulti(sc_if); 967 } else if (ifp->if_flags & IFF_RUNNING && 968 !(ifp->if_flags & IFF_PROMISC) && 969 sc_if->sk_if_flags & IFF_PROMISC) { 970 SK_XM_CLRBIT_4(sc_if, XM_MODE, 971 XM_MODE_RX_PROMISC); 972 sk_setmulti(sc_if); 973 } else 974 sk_init(sc_if); 975 } else { 976 if (ifp->if_flags & IFF_RUNNING) 977 sk_stop(sc_if); 978 } 979 sc_if->sk_if_flags = ifp->if_flags; 980 error = 0; 981 break; 982 case SIOCADDMULTI: 983 case SIOCDELMULTI: 984 sk_setmulti(sc_if); 985 error = 0; 986 break; 987 case SIOCGIFMEDIA: 988 case SIOCSIFMEDIA: 989 mii = device_get_softc(sc_if->sk_miibus); 990 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 991 break; 992 default: 993 error = EINVAL; 994 break; 995 } 996 997 (void)splx(s); 998 999 return(error); 1000 } 1001 1002 /* 1003 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 1004 * IDs against our list and return a device name if we find a match. 1005 */ 1006 static int sk_probe(dev) 1007 device_t dev; 1008 { 1009 struct sk_type *t; 1010 1011 t = sk_devs; 1012 1013 while(t->sk_name != NULL) { 1014 if ((pci_get_vendor(dev) == t->sk_vid) && 1015 (pci_get_device(dev) == t->sk_did)) { 1016 device_set_desc(dev, t->sk_name); 1017 return(0); 1018 } 1019 t++; 1020 } 1021 1022 return(ENXIO); 1023 } 1024 1025 /* 1026 * Force the GEnesis into reset, then bring it out of reset. 1027 */ 1028 static void sk_reset(sc) 1029 struct sk_softc *sc; 1030 { 1031 CSR_WRITE_4(sc, SK_CSR, SK_CSR_SW_RESET); 1032 CSR_WRITE_4(sc, SK_CSR, SK_CSR_MASTER_RESET); 1033 DELAY(1000); 1034 CSR_WRITE_4(sc, SK_CSR, SK_CSR_SW_UNRESET); 1035 CSR_WRITE_4(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1036 1037 /* Configure packet arbiter */ 1038 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1039 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1040 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1041 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1042 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1043 1044 /* Enable RAM interface */ 1045 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1046 1047 /* 1048 * Configure interrupt moderation. The moderation timer 1049 * defers interrupts specified in the interrupt moderation 1050 * timer mask based on the timeout specified in the interrupt 1051 * moderation timer init register. Each bit in the timer 1052 * register represents 18.825ns, so to specify a timeout in 1053 * microseconds, we have to multiply by 54. 1054 */ 1055 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(200)); 1056 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 1057 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 1058 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1059 1060 return; 1061 } 1062 1063 static int sk_probe_xmac(dev) 1064 device_t dev; 1065 { 1066 /* 1067 * Not much to do here. We always know there will be 1068 * at least one XMAC present, and if there are two, 1069 * sk_attach() will create a second device instance 1070 * for us. 1071 */ 1072 device_set_desc(dev, "XaQti Corp. XMAC II"); 1073 1074 return(0); 1075 } 1076 1077 /* 1078 * Each XMAC chip is attached as a separate logical IP interface. 1079 * Single port cards will have only one logical interface of course. 1080 */ 1081 static int sk_attach_xmac(dev) 1082 device_t dev; 1083 { 1084 struct sk_softc *sc; 1085 struct sk_if_softc *sc_if; 1086 struct ifnet *ifp; 1087 int i, port; 1088 1089 if (dev == NULL) 1090 return(EINVAL); 1091 1092 sc_if = device_get_softc(dev); 1093 sc = device_get_softc(device_get_parent(dev)); 1094 port = *(int *)device_get_ivars(dev); 1095 free(device_get_ivars(dev), M_DEVBUF); 1096 device_set_ivars(dev, NULL); 1097 sc_if->sk_dev = dev; 1098 1099 bzero((char *)sc_if, sizeof(struct sk_if_softc)); 1100 1101 sc_if->sk_dev = dev; 1102 sc_if->sk_unit = device_get_unit(dev); 1103 sc_if->sk_port = port; 1104 sc_if->sk_softc = sc; 1105 sc->sk_if[port] = sc_if; 1106 if (port == SK_PORT_A) 1107 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1108 if (port == SK_PORT_B) 1109 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1110 1111 /* 1112 * Get station address for this interface. Note that 1113 * dual port cards actually come with three station 1114 * addresses: one for each port, plus an extra. The 1115 * extra one is used by the SysKonnect driver software 1116 * as a 'virtual' station address for when both ports 1117 * are operating in failover mode. Currently we don't 1118 * use this extra address. 1119 */ 1120 for (i = 0; i < ETHER_ADDR_LEN; i++) 1121 sc_if->arpcom.ac_enaddr[i] = 1122 sk_win_read_1(sc, SK_MAC0_0 + (port * 8) + i); 1123 1124 printf("sk%d: Ethernet address: %6D\n", 1125 sc_if->sk_unit, sc_if->arpcom.ac_enaddr, ":"); 1126 1127 /* 1128 * Set up RAM buffer addresses. The NIC will have a certain 1129 * amount of SRAM on it, somewhere between 512K and 2MB. We 1130 * need to divide this up a) between the transmitter and 1131 * receiver and b) between the two XMACs, if this is a 1132 * dual port NIC. Our algotithm is to divide up the memory 1133 * evenly so that everyone gets a fair share. 1134 */ 1135 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1136 u_int32_t chunk, val; 1137 1138 chunk = sc->sk_ramsize / 2; 1139 val = sc->sk_rboff / sizeof(u_int64_t); 1140 sc_if->sk_rx_ramstart = val; 1141 val += (chunk / sizeof(u_int64_t)); 1142 sc_if->sk_rx_ramend = val - 1; 1143 sc_if->sk_tx_ramstart = val; 1144 val += (chunk / sizeof(u_int64_t)); 1145 sc_if->sk_tx_ramend = val - 1; 1146 } else { 1147 u_int32_t chunk, val; 1148 1149 chunk = sc->sk_ramsize / 4; 1150 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1151 sizeof(u_int64_t); 1152 sc_if->sk_rx_ramstart = val; 1153 val += (chunk / sizeof(u_int64_t)); 1154 sc_if->sk_rx_ramend = val - 1; 1155 sc_if->sk_tx_ramstart = val; 1156 val += (chunk / sizeof(u_int64_t)); 1157 sc_if->sk_tx_ramend = val - 1; 1158 } 1159 1160 /* Read and save PHY type and set PHY address */ 1161 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1162 switch(sc_if->sk_phytype) { 1163 case SK_PHYTYPE_XMAC: 1164 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1165 break; 1166 case SK_PHYTYPE_BCOM: 1167 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1168 break; 1169 default: 1170 printf("skc%d: unsupported PHY type: %d\n", 1171 sc->sk_unit, sc_if->sk_phytype); 1172 return(ENODEV); 1173 } 1174 1175 /* Allocate the descriptor queues. */ 1176 sc_if->sk_rdata = contigmalloc(sizeof(struct sk_ring_data), M_DEVBUF, 1177 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1178 1179 if (sc_if->sk_rdata == NULL) { 1180 printf("sk%d: no memory for list buffers!\n", sc_if->sk_unit); 1181 sc->sk_if[port] = NULL; 1182 return(ENOMEM); 1183 } 1184 1185 bzero(sc_if->sk_rdata, sizeof(struct sk_ring_data)); 1186 1187 /* Try to allocate memory for jumbo buffers. */ 1188 if (sk_alloc_jumbo_mem(sc_if)) { 1189 printf("sk%d: jumbo buffer allocation failed\n", 1190 sc_if->sk_unit); 1191 contigfree(sc_if->sk_rdata, 1192 sizeof(struct sk_ring_data), M_DEVBUF); 1193 sc->sk_if[port] = NULL; 1194 return(ENOMEM); 1195 } 1196 1197 ifp = &sc_if->arpcom.ac_if; 1198 ifp->if_softc = sc_if; 1199 ifp->if_unit = sc_if->sk_unit; 1200 ifp->if_name = "sk"; 1201 ifp->if_mtu = ETHERMTU; 1202 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1203 ifp->if_ioctl = sk_ioctl; 1204 ifp->if_output = ether_output; 1205 ifp->if_start = sk_start; 1206 ifp->if_watchdog = sk_watchdog; 1207 ifp->if_init = sk_init; 1208 ifp->if_baudrate = 1000000000; 1209 ifp->if_snd.ifq_maxlen = SK_TX_RING_CNT - 1; 1210 1211 /* 1212 * Do miibus setup. 1213 */ 1214 sk_init_xmac(sc_if); 1215 if (mii_phy_probe(dev, &sc_if->sk_miibus, 1216 sk_ifmedia_upd, sk_ifmedia_sts)) { 1217 printf("skc%d: no PHY found!\n", sc_if->sk_unit); 1218 contigfree(sc_if->sk_rdata, 1219 sizeof(struct sk_ring_data), M_DEVBUF); 1220 return(ENXIO); 1221 } 1222 1223 /* 1224 * Call MI attach routines. 1225 */ 1226 if_attach(ifp); 1227 ether_ifattach(ifp); 1228 callout_handle_init(&sc_if->sk_tick_ch); 1229 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 1230 1231 return(0); 1232 } 1233 1234 /* 1235 * Attach the interface. Allocate softc structures, do ifmedia 1236 * setup and ethernet/BPF attach. 1237 */ 1238 static int sk_attach(dev) 1239 device_t dev; 1240 { 1241 int s; 1242 u_int32_t command; 1243 struct sk_softc *sc; 1244 int unit, error = 0, rid, *port; 1245 1246 s = splimp(); 1247 1248 sc = device_get_softc(dev); 1249 unit = device_get_unit(dev); 1250 bzero(sc, sizeof(struct sk_softc)); 1251 1252 /* 1253 * Handle power management nonsense. 1254 */ 1255 command = pci_read_config(dev, SK_PCI_CAPID, 4) & 0x000000FF; 1256 if (command == 0x01) { 1257 1258 command = pci_read_config(dev, SK_PCI_PWRMGMTCTRL, 4); 1259 if (command & SK_PSTATE_MASK) { 1260 u_int32_t iobase, membase, irq; 1261 1262 /* Save important PCI config data. */ 1263 iobase = pci_read_config(dev, SK_PCI_LOIO, 4); 1264 membase = pci_read_config(dev, SK_PCI_LOMEM, 4); 1265 irq = pci_read_config(dev, SK_PCI_INTLINE, 4); 1266 1267 /* Reset the power state. */ 1268 printf("skc%d: chip is in D%d power mode " 1269 "-- setting to D0\n", unit, command & SK_PSTATE_MASK); 1270 command &= 0xFFFFFFFC; 1271 pci_write_config(dev, SK_PCI_PWRMGMTCTRL, command, 4); 1272 1273 /* Restore PCI config data. */ 1274 pci_write_config(dev, SK_PCI_LOIO, iobase, 4); 1275 pci_write_config(dev, SK_PCI_LOMEM, membase, 4); 1276 pci_write_config(dev, SK_PCI_INTLINE, irq, 4); 1277 } 1278 } 1279 1280 /* 1281 * Map control/status registers. 1282 */ 1283 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 1284 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1285 pci_write_config(dev, PCI_COMMAND_STATUS_REG, command, 4); 1286 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 1287 1288 #ifdef SK_USEIOSPACE 1289 if (!(command & PCIM_CMD_PORTEN)) { 1290 printf("skc%d: failed to enable I/O ports!\n", unit); 1291 error = ENXIO; 1292 goto fail; 1293 } 1294 #else 1295 if (!(command & PCIM_CMD_MEMEN)) { 1296 printf("skc%d: failed to enable memory mapping!\n", unit); 1297 error = ENXIO; 1298 goto fail; 1299 } 1300 #endif 1301 1302 rid = SK_RID; 1303 sc->sk_res = bus_alloc_resource(dev, SK_RES, &rid, 1304 0, ~0, 1, RF_ACTIVE); 1305 1306 if (sc->sk_res == NULL) { 1307 printf("sk%d: couldn't map ports/memory\n", unit); 1308 error = ENXIO; 1309 goto fail; 1310 } 1311 1312 sc->sk_btag = rman_get_bustag(sc->sk_res); 1313 sc->sk_bhandle = rman_get_bushandle(sc->sk_res); 1314 1315 /* Allocate interrupt */ 1316 rid = 0; 1317 sc->sk_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1318 RF_SHAREABLE | RF_ACTIVE); 1319 1320 if (sc->sk_irq == NULL) { 1321 printf("skc%d: couldn't map interrupt\n", unit); 1322 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res); 1323 error = ENXIO; 1324 goto fail; 1325 } 1326 1327 error = bus_setup_intr(dev, sc->sk_irq, INTR_TYPE_NET, 1328 sk_intr, sc, &sc->sk_intrhand); 1329 1330 if (error) { 1331 printf("skc%d: couldn't set up irq\n", unit); 1332 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res); 1333 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_res); 1334 goto fail; 1335 } 1336 1337 /* Reset the adapter. */ 1338 sk_reset(sc); 1339 1340 sc->sk_unit = unit; 1341 1342 /* Read and save vital product data from EEPROM. */ 1343 sk_vpd_read(sc); 1344 1345 /* Read and save RAM size and RAMbuffer offset */ 1346 switch(sk_win_read_1(sc, SK_EPROM0)) { 1347 case SK_RAMSIZE_512K_64: 1348 sc->sk_ramsize = 0x80000; 1349 sc->sk_rboff = SK_RBOFF_0; 1350 break; 1351 case SK_RAMSIZE_1024K_64: 1352 sc->sk_ramsize = 0x100000; 1353 sc->sk_rboff = SK_RBOFF_80000; 1354 break; 1355 case SK_RAMSIZE_1024K_128: 1356 sc->sk_ramsize = 0x100000; 1357 sc->sk_rboff = SK_RBOFF_0; 1358 break; 1359 case SK_RAMSIZE_2048K_128: 1360 sc->sk_ramsize = 0x200000; 1361 sc->sk_rboff = SK_RBOFF_0; 1362 break; 1363 default: 1364 printf("skc%d: unknown ram size: %d\n", 1365 sc->sk_unit, sk_win_read_1(sc, SK_EPROM0)); 1366 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand); 1367 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq); 1368 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res); 1369 error = ENXIO; 1370 goto fail; 1371 break; 1372 } 1373 1374 /* Read and save physical media type */ 1375 switch(sk_win_read_1(sc, SK_PMDTYPE)) { 1376 case SK_PMD_1000BASESX: 1377 sc->sk_pmd = IFM_1000_SX; 1378 break; 1379 case SK_PMD_1000BASELX: 1380 sc->sk_pmd = IFM_1000_LX; 1381 break; 1382 case SK_PMD_1000BASECX: 1383 sc->sk_pmd = IFM_1000_CX; 1384 break; 1385 case SK_PMD_1000BASETX: 1386 sc->sk_pmd = IFM_1000_TX; 1387 break; 1388 default: 1389 printf("skc%d: unknown media type: 0x%x\n", 1390 sc->sk_unit, sk_win_read_1(sc, SK_PMDTYPE)); 1391 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand); 1392 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq); 1393 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res); 1394 error = ENXIO; 1395 goto fail; 1396 } 1397 1398 /* Announce the product name. */ 1399 printf("skc%d: %s\n", sc->sk_unit, sc->sk_vpd_prodname); 1400 sc->sk_devs[SK_PORT_A] = device_add_child(dev, "sk", -1); 1401 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT); 1402 *port = SK_PORT_A; 1403 device_set_ivars(sc->sk_devs[SK_PORT_A], port); 1404 1405 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1406 sc->sk_devs[SK_PORT_B] = device_add_child(dev, "sk", -1); 1407 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT); 1408 *port = SK_PORT_B; 1409 device_set_ivars(sc->sk_devs[SK_PORT_B], port); 1410 } 1411 1412 /* Turn on the 'driver is loaded' LED. */ 1413 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1414 1415 fail: 1416 splx(s); 1417 return(error); 1418 } 1419 1420 static int sk_detach_xmac(dev) 1421 device_t dev; 1422 { 1423 struct sk_softc *sc; 1424 struct sk_if_softc *sc_if; 1425 struct ifnet *ifp; 1426 int s; 1427 1428 s = splimp(); 1429 1430 sc = device_get_softc(device_get_parent(dev)); 1431 sc_if = device_get_softc(dev); 1432 ifp = &sc_if->arpcom.ac_if; 1433 sk_stop(sc_if); 1434 if_detach(ifp); 1435 bus_generic_detach(dev); 1436 if (sc_if->sk_miibus != NULL) 1437 device_delete_child(dev, sc_if->sk_miibus); 1438 contigfree(sc_if->sk_cdata.sk_jumbo_buf, SK_JMEM, M_DEVBUF); 1439 contigfree(sc_if->sk_rdata, sizeof(struct sk_ring_data), M_DEVBUF); 1440 1441 return(0); 1442 } 1443 1444 static int sk_detach(dev) 1445 device_t dev; 1446 { 1447 struct sk_softc *sc; 1448 int s; 1449 1450 s = splimp(); 1451 1452 sc = device_get_softc(dev); 1453 1454 bus_generic_detach(dev); 1455 if (sc->sk_devs[SK_PORT_A] != NULL) 1456 device_delete_child(dev, sc->sk_devs[SK_PORT_A]); 1457 if (sc->sk_devs[SK_PORT_B] != NULL) 1458 device_delete_child(dev, sc->sk_devs[SK_PORT_B]); 1459 1460 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand); 1461 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq); 1462 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res); 1463 1464 splx(s); 1465 1466 return(0); 1467 } 1468 1469 static int sk_encap(sc_if, m_head, txidx) 1470 struct sk_if_softc *sc_if; 1471 struct mbuf *m_head; 1472 u_int32_t *txidx; 1473 { 1474 struct sk_tx_desc *f = NULL; 1475 struct mbuf *m; 1476 u_int32_t frag, cur, cnt = 0; 1477 1478 m = m_head; 1479 cur = frag = *txidx; 1480 1481 /* 1482 * Start packing the mbufs in this chain into 1483 * the fragment pointers. Stop when we run out 1484 * of fragments or hit the end of the mbuf chain. 1485 */ 1486 for (m = m_head; m != NULL; m = m->m_next) { 1487 if (m->m_len != 0) { 1488 if ((SK_TX_RING_CNT - 1489 (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) 1490 return(ENOBUFS); 1491 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1492 f->sk_data_lo = vtophys(mtod(m, vm_offset_t)); 1493 f->sk_ctl = m->m_len | SK_OPCODE_DEFAULT; 1494 if (cnt == 0) 1495 f->sk_ctl |= SK_TXCTL_FIRSTFRAG; 1496 else 1497 f->sk_ctl |= SK_TXCTL_OWN; 1498 cur = frag; 1499 SK_INC(frag, SK_TX_RING_CNT); 1500 cnt++; 1501 } 1502 } 1503 1504 if (m != NULL) 1505 return(ENOBUFS); 1506 1507 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1508 SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR; 1509 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1510 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= SK_TXCTL_OWN; 1511 sc_if->sk_cdata.sk_tx_cnt += cnt; 1512 1513 *txidx = frag; 1514 1515 return(0); 1516 } 1517 1518 static void sk_start(ifp) 1519 struct ifnet *ifp; 1520 { 1521 struct sk_softc *sc; 1522 struct sk_if_softc *sc_if; 1523 struct mbuf *m_head = NULL; 1524 u_int32_t idx; 1525 1526 sc_if = ifp->if_softc; 1527 sc = sc_if->sk_softc; 1528 1529 idx = sc_if->sk_cdata.sk_tx_prod; 1530 1531 while(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1532 IF_DEQUEUE(&ifp->if_snd, m_head); 1533 if (m_head == NULL) 1534 break; 1535 1536 /* 1537 * Pack the data into the transmit ring. If we 1538 * don't have room, set the OACTIVE flag and wait 1539 * for the NIC to drain the ring. 1540 */ 1541 if (sk_encap(sc_if, m_head, &idx)) { 1542 IF_PREPEND(&ifp->if_snd, m_head); 1543 ifp->if_flags |= IFF_OACTIVE; 1544 break; 1545 } 1546 1547 /* 1548 * If there's a BPF listener, bounce a copy of this frame 1549 * to him. 1550 */ 1551 if (ifp->if_bpf) 1552 bpf_mtap(ifp, m_head); 1553 } 1554 1555 /* Transmit */ 1556 sc_if->sk_cdata.sk_tx_prod = idx; 1557 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1558 1559 /* Set a timeout in case the chip goes out to lunch. */ 1560 ifp->if_timer = 5; 1561 1562 return; 1563 } 1564 1565 1566 static void sk_watchdog(ifp) 1567 struct ifnet *ifp; 1568 { 1569 struct sk_if_softc *sc_if; 1570 1571 sc_if = ifp->if_softc; 1572 1573 printf("sk%d: watchdog timeout\n", sc_if->sk_unit); 1574 sk_init(sc_if); 1575 1576 return; 1577 } 1578 1579 static void sk_shutdown(dev) 1580 device_t dev; 1581 { 1582 struct sk_softc *sc; 1583 1584 sc = device_get_softc(dev); 1585 1586 /* Turn off the 'driver is loaded' LED. */ 1587 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1588 1589 /* 1590 * Reset the GEnesis controller. Doing this should also 1591 * assert the resets on the attached XMAC(s). 1592 */ 1593 sk_reset(sc); 1594 1595 return; 1596 } 1597 1598 static void sk_rxeof(sc_if) 1599 struct sk_if_softc *sc_if; 1600 { 1601 struct ether_header *eh; 1602 struct mbuf *m; 1603 struct ifnet *ifp; 1604 struct sk_chain *cur_rx; 1605 int total_len = 0; 1606 int i; 1607 u_int32_t rxstat; 1608 1609 ifp = &sc_if->arpcom.ac_if; 1610 i = sc_if->sk_cdata.sk_rx_prod; 1611 cur_rx = &sc_if->sk_cdata.sk_rx_chain[i]; 1612 1613 while(!(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl & SK_RXCTL_OWN)) { 1614 1615 cur_rx = &sc_if->sk_cdata.sk_rx_chain[i]; 1616 rxstat = sc_if->sk_rdata->sk_rx_ring[i].sk_xmac_rxstat; 1617 m = cur_rx->sk_mbuf; 1618 cur_rx->sk_mbuf = NULL; 1619 total_len = SK_RXBYTES(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl); 1620 SK_INC(i, SK_RX_RING_CNT); 1621 1622 if (rxstat & XM_RXSTAT_ERRFRAME) { 1623 ifp->if_ierrors++; 1624 sk_newbuf(sc_if, cur_rx, m); 1625 continue; 1626 } 1627 1628 /* 1629 * Try to allocate a new jumbo buffer. If that 1630 * fails, copy the packet to mbufs and put the 1631 * jumbo buffer back in the ring so it can be 1632 * re-used. If allocating mbufs fails, then we 1633 * have to drop the packet. 1634 */ 1635 if (sk_newbuf(sc_if, cur_rx, NULL) == ENOBUFS) { 1636 struct mbuf *m0; 1637 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1638 total_len + ETHER_ALIGN, 0, ifp, NULL); 1639 sk_newbuf(sc_if, cur_rx, m); 1640 if (m0 == NULL) { 1641 printf("sk%d: no receive buffers " 1642 "available -- packet dropped!\n", 1643 sc_if->sk_unit); 1644 ifp->if_ierrors++; 1645 continue; 1646 } 1647 m_adj(m0, ETHER_ALIGN); 1648 m = m0; 1649 } else { 1650 m->m_pkthdr.rcvif = ifp; 1651 m->m_pkthdr.len = m->m_len = total_len; 1652 } 1653 1654 ifp->if_ipackets++; 1655 eh = mtod(m, struct ether_header *); 1656 1657 if (ifp->if_bpf) { 1658 bpf_mtap(ifp, m); 1659 if (ifp->if_flags & IFF_PROMISC && 1660 (bcmp(eh->ether_dhost, sc_if->arpcom.ac_enaddr, 1661 ETHER_ADDR_LEN) && !(eh->ether_dhost[0] & 1))) { 1662 m_freem(m); 1663 continue; 1664 } 1665 } 1666 1667 /* Remove header from mbuf and pass it on. */ 1668 m_adj(m, sizeof(struct ether_header)); 1669 ether_input(ifp, eh, m); 1670 } 1671 1672 sc_if->sk_cdata.sk_rx_prod = i; 1673 1674 return; 1675 } 1676 1677 static void sk_txeof(sc_if) 1678 struct sk_if_softc *sc_if; 1679 { 1680 struct sk_tx_desc *cur_tx = NULL; 1681 struct ifnet *ifp; 1682 u_int32_t idx; 1683 1684 ifp = &sc_if->arpcom.ac_if; 1685 1686 /* 1687 * Go through our tx ring and free mbufs for those 1688 * frames that have been sent. 1689 */ 1690 idx = sc_if->sk_cdata.sk_tx_cons; 1691 while(idx != sc_if->sk_cdata.sk_tx_prod) { 1692 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 1693 if (cur_tx->sk_ctl & SK_TXCTL_OWN) 1694 break; 1695 if (cur_tx->sk_ctl & SK_TXCTL_LASTFRAG) 1696 ifp->if_opackets++; 1697 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 1698 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 1699 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 1700 } 1701 sc_if->sk_cdata.sk_tx_cnt--; 1702 SK_INC(idx, SK_TX_RING_CNT); 1703 ifp->if_timer = 0; 1704 } 1705 1706 sc_if->sk_cdata.sk_tx_cons = idx; 1707 1708 if (cur_tx != NULL) 1709 ifp->if_flags &= ~IFF_OACTIVE; 1710 1711 return; 1712 } 1713 1714 static void sk_tick(xsc_if) 1715 void *xsc_if; 1716 { 1717 struct sk_if_softc *sc_if; 1718 struct mii_data *mii; 1719 struct ifnet *ifp; 1720 int i; 1721 1722 sc_if = xsc_if; 1723 ifp = &sc_if->arpcom.ac_if; 1724 mii = device_get_softc(sc_if->sk_miibus); 1725 1726 if (!(ifp->if_flags & IFF_UP)) 1727 return; 1728 1729 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 1730 sk_intr_bcom(sc_if); 1731 return; 1732 } 1733 1734 /* 1735 * According to SysKonnect, the correct way to verify that 1736 * the link has come back up is to poll bit 0 of the GPIO 1737 * register three times. This pin has the signal from the 1738 * link_sync pin connected to it; if we read the same link 1739 * state 3 times in a row, we know the link is up. 1740 */ 1741 for (i = 0; i < 3; i++) { 1742 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 1743 break; 1744 } 1745 1746 if (i != 3) { 1747 sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz); 1748 return; 1749 } 1750 1751 /* Turn the GP0 interrupt back on. */ 1752 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 1753 SK_XM_READ_2(sc_if, XM_ISR); 1754 mii_tick(mii); 1755 mii_pollstat(mii); 1756 untimeout(sk_tick, sc_if, sc_if->sk_tick_ch); 1757 1758 return; 1759 } 1760 1761 static void sk_intr_bcom(sc_if) 1762 struct sk_if_softc *sc_if; 1763 { 1764 struct sk_softc *sc; 1765 struct mii_data *mii; 1766 struct ifnet *ifp; 1767 int status; 1768 1769 sc = sc_if->sk_softc; 1770 mii = device_get_softc(sc_if->sk_miibus); 1771 ifp = &sc_if->arpcom.ac_if; 1772 1773 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 1774 1775 /* 1776 * Read the PHY interrupt register to make sure 1777 * we clear any pending interrupts. 1778 */ 1779 status = sk_miibus_readreg(sc_if->sk_dev, 1780 SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 1781 1782 if (!(ifp->if_flags & IFF_RUNNING)) { 1783 sk_init_xmac(sc_if); 1784 return; 1785 } 1786 1787 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 1788 int lstat; 1789 lstat = sk_miibus_readreg(sc_if->sk_dev, 1790 SK_PHYADDR_BCOM, BRGPHY_MII_AUXSTS); 1791 1792 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 1793 mii_mediachg(mii); 1794 /* Turn off the link LED. */ 1795 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 1796 sc_if->sk_link = 0; 1797 } else if (status & BRGPHY_ISR_LNK_CHG) { 1798 sk_miibus_writereg(sc_if->sk_dev, SK_PHYADDR_BCOM, 1799 BRGPHY_MII_IMR, 0xFF00); 1800 mii_tick(mii); 1801 sc_if->sk_link = 1; 1802 /* Turn on the link LED. */ 1803 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 1804 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 1805 SK_LINKLED_BLINK_OFF); 1806 } else { 1807 mii_tick(mii); 1808 sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz); 1809 } 1810 } 1811 1812 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 1813 1814 return; 1815 } 1816 1817 static void sk_intr_xmac(sc_if) 1818 struct sk_if_softc *sc_if; 1819 { 1820 struct sk_softc *sc; 1821 u_int16_t status; 1822 struct mii_data *mii; 1823 1824 sc = sc_if->sk_softc; 1825 mii = device_get_softc(sc_if->sk_miibus); 1826 status = SK_XM_READ_2(sc_if, XM_ISR); 1827 1828 /* 1829 * Link has gone down. Start MII tick timeout to 1830 * watch for link resync. 1831 */ 1832 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 1833 if (status & XM_ISR_GP0_SET) { 1834 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 1835 sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz); 1836 } 1837 1838 if (status & XM_ISR_AUTONEG_DONE) { 1839 sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz); 1840 } 1841 } 1842 1843 if (status & XM_IMR_TX_UNDERRUN) 1844 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 1845 1846 if (status & XM_IMR_RX_OVERRUN) 1847 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 1848 1849 status = SK_XM_READ_2(sc_if, XM_ISR); 1850 1851 return; 1852 } 1853 1854 static void sk_intr(xsc) 1855 void *xsc; 1856 { 1857 struct sk_softc *sc = xsc; 1858 struct sk_if_softc *sc_if0 = NULL, *sc_if1 = NULL; 1859 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 1860 u_int32_t status; 1861 1862 sc_if0 = sc->sk_if[SK_PORT_A]; 1863 sc_if1 = sc->sk_if[SK_PORT_B]; 1864 1865 if (sc_if0 != NULL) 1866 ifp0 = &sc_if0->arpcom.ac_if; 1867 if (sc_if1 != NULL) 1868 ifp1 = &sc_if1->arpcom.ac_if; 1869 1870 for (;;) { 1871 status = CSR_READ_4(sc, SK_ISSR); 1872 if (!(status & sc->sk_intrmask)) 1873 break; 1874 1875 /* Handle receive interrupts first. */ 1876 if (status & SK_ISR_RX1_EOF) { 1877 sk_rxeof(sc_if0); 1878 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 1879 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 1880 } 1881 if (status & SK_ISR_RX2_EOF) { 1882 sk_rxeof(sc_if1); 1883 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 1884 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 1885 } 1886 1887 /* Then transmit interrupts. */ 1888 if (status & SK_ISR_TX1_S_EOF) { 1889 sk_txeof(sc_if0); 1890 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 1891 SK_TXBMU_CLR_IRQ_EOF); 1892 } 1893 if (status & SK_ISR_TX2_S_EOF) { 1894 sk_txeof(sc_if1); 1895 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 1896 SK_TXBMU_CLR_IRQ_EOF); 1897 } 1898 1899 /* Then MAC interrupts. */ 1900 if (status & SK_ISR_MAC1 && 1901 ifp0->if_flags & IFF_RUNNING) 1902 sk_intr_xmac(sc_if0); 1903 1904 if (status & SK_ISR_MAC2 && 1905 ifp1->if_flags & IFF_RUNNING) 1906 sk_intr_xmac(sc_if1); 1907 1908 if (status & SK_ISR_EXTERNAL_REG) { 1909 if (ifp0 != NULL) 1910 sk_intr_bcom(sc_if0); 1911 if (ifp1 != NULL) 1912 sk_intr_bcom(sc_if1); 1913 } 1914 } 1915 1916 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 1917 1918 if (ifp0 != NULL && ifp0->if_snd.ifq_head != NULL) 1919 sk_start(ifp0); 1920 if (ifp1 != NULL && ifp1->if_snd.ifq_head != NULL) 1921 sk_start(ifp1); 1922 1923 return; 1924 } 1925 1926 static void sk_init_xmac(sc_if) 1927 struct sk_if_softc *sc_if; 1928 { 1929 struct sk_softc *sc; 1930 struct ifnet *ifp; 1931 struct sk_bcom_hack bhack[] = { 1932 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 1933 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 1934 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 1935 { 0, 0 } }; 1936 1937 sc = sc_if->sk_softc; 1938 ifp = &sc_if->arpcom.ac_if; 1939 1940 /* Unreset the XMAC. */ 1941 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 1942 DELAY(1000); 1943 1944 /* Reset the XMAC's internal state. */ 1945 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 1946 1947 /* Save the XMAC II revision */ 1948 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 1949 1950 /* 1951 * Perform additional initialization for external PHYs, 1952 * namely for the 1000baseTX cards that use the XMAC's 1953 * GMII mode. 1954 */ 1955 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 1956 int i = 0; 1957 u_int32_t val; 1958 1959 /* Take PHY out of reset. */ 1960 val = sk_win_read_4(sc, SK_GPIO); 1961 if (sc_if->sk_port == SK_PORT_A) 1962 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 1963 else 1964 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 1965 sk_win_write_4(sc, SK_GPIO, val); 1966 1967 /* Enable GMII mode on the XMAC. */ 1968 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 1969 1970 sk_miibus_writereg(sc_if->sk_dev, SK_PHYADDR_BCOM, 1971 BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET); 1972 DELAY(10000); 1973 sk_miibus_writereg(sc_if->sk_dev, SK_PHYADDR_BCOM, 1974 BRGPHY_MII_IMR, 0xFFF0); 1975 1976 /* 1977 * Early versions of the BCM5400 apparently have 1978 * a bug that requires them to have their reserved 1979 * registers initialized to some magic values. I don't 1980 * know what the numbers do, I'm just the messenger. 1981 */ 1982 if (sk_miibus_readreg(sc_if->sk_dev, 1983 SK_PHYADDR_BCOM, 0x03) == 0x6041) { 1984 while(bhack[i].reg) { 1985 sk_miibus_writereg(sc_if->sk_dev, 1986 SK_PHYADDR_BCOM, bhack[i].reg, 1987 bhack[i].val); 1988 i++; 1989 } 1990 } 1991 } 1992 1993 /* Set station address */ 1994 SK_XM_WRITE_2(sc_if, XM_PAR0, 1995 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[0])); 1996 SK_XM_WRITE_2(sc_if, XM_PAR1, 1997 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[2])); 1998 SK_XM_WRITE_2(sc_if, XM_PAR2, 1999 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[4])); 2000 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 2001 2002 if (ifp->if_flags & IFF_PROMISC) { 2003 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2004 } else { 2005 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2006 } 2007 2008 if (ifp->if_flags & IFF_BROADCAST) { 2009 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2010 } else { 2011 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2012 } 2013 2014 /* We don't need the FCS appended to the packet. */ 2015 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 2016 2017 /* We want short frames padded to 60 bytes. */ 2018 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 2019 2020 /* 2021 * Enable the reception of all error frames. This is is 2022 * a necessary evil due to the design of the XMAC. The 2023 * XMAC's receive FIFO is only 8K in size, however jumbo 2024 * frames can be up to 9000 bytes in length. When bad 2025 * frame filtering is enabled, the XMAC's RX FIFO operates 2026 * in 'store and forward' mode. For this to work, the 2027 * entire frame has to fit into the FIFO, but that means 2028 * that jumbo frames larger than 8192 bytes will be 2029 * truncated. Disabling all bad frame filtering causes 2030 * the RX FIFO to operate in streaming mode, in which 2031 * case the XMAC will start transfering frames out of the 2032 * RX FIFO as soon as the FIFO threshold is reached. 2033 */ 2034 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 2035 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 2036 XM_MODE_RX_INRANGELEN); 2037 2038 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2039 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2040 else 2041 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2042 2043 /* 2044 * Bump up the transmit threshold. This helps hold off transmit 2045 * underruns when we're blasting traffic from both ports at once. 2046 */ 2047 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2048 2049 /* Set multicast filter */ 2050 sk_setmulti(sc_if); 2051 2052 /* Clear and enable interrupts */ 2053 SK_XM_READ_2(sc_if, XM_ISR); 2054 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2055 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2056 else 2057 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2058 2059 /* Configure MAC arbiter */ 2060 switch(sc_if->sk_xmac_rev) { 2061 case XM_XMAC_REV_B2: 2062 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2063 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2064 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2065 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2066 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2067 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2068 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2069 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2070 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2071 break; 2072 case XM_XMAC_REV_C1: 2073 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2074 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2075 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2076 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2077 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2078 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2079 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2080 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2081 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2082 break; 2083 default: 2084 break; 2085 } 2086 sk_win_write_2(sc, SK_MACARB_CTL, 2087 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 2088 2089 sc_if->sk_link = 1; 2090 2091 return; 2092 } 2093 2094 /* 2095 * Note that to properly initialize any part of the GEnesis chip, 2096 * you first have to take it out of reset mode. 2097 */ 2098 static void sk_init(xsc) 2099 void *xsc; 2100 { 2101 struct sk_if_softc *sc_if = xsc; 2102 struct sk_softc *sc; 2103 struct ifnet *ifp; 2104 struct mii_data *mii; 2105 int s; 2106 2107 s = splimp(); 2108 2109 ifp = &sc_if->arpcom.ac_if; 2110 sc = sc_if->sk_softc; 2111 mii = device_get_softc(sc_if->sk_miibus); 2112 2113 /* Cancel pending I/O and free all RX/TX buffers. */ 2114 sk_stop(sc_if); 2115 2116 /* Configure LINK_SYNC LED */ 2117 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2118 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_ON); 2119 2120 /* Configure RX LED */ 2121 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_START); 2122 2123 /* Configure TX LED */ 2124 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_TXLEDCTL_COUNTER_START); 2125 2126 /* Configure I2C registers */ 2127 2128 /* Configure XMAC(s) */ 2129 sk_init_xmac(sc_if); 2130 mii_mediachg(mii); 2131 2132 /* Configure MAC FIFOs */ 2133 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2134 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2135 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2136 2137 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2138 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2139 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2140 2141 /* Configure transmit arbiter(s) */ 2142 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2143 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2144 2145 /* Configure RAMbuffers */ 2146 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2147 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2148 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2149 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2150 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2151 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2152 2153 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2154 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2155 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2156 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2157 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2158 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2159 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2160 2161 /* Configure BMUs */ 2162 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2163 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2164 vtophys(&sc_if->sk_rdata->sk_rx_ring[0])); 2165 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2166 2167 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2168 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2169 vtophys(&sc_if->sk_rdata->sk_tx_ring[0])); 2170 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2171 2172 /* Init descriptors */ 2173 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2174 printf("sk%d: initialization failed: no " 2175 "memory for rx buffers\n", sc_if->sk_unit); 2176 sk_stop(sc_if); 2177 (void)splx(s); 2178 return; 2179 } 2180 sk_init_tx_ring(sc_if); 2181 2182 /* Configure interrupt handling */ 2183 CSR_READ_4(sc, SK_ISSR); 2184 if (sc_if->sk_port == SK_PORT_A) 2185 sc->sk_intrmask |= SK_INTRS1; 2186 else 2187 sc->sk_intrmask |= SK_INTRS2; 2188 2189 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2190 2191 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2192 2193 /* Start BMUs. */ 2194 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2195 2196 /* Enable XMACs TX and RX state machines */ 2197 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2198 2199 ifp->if_flags |= IFF_RUNNING; 2200 ifp->if_flags &= ~IFF_OACTIVE; 2201 2202 splx(s); 2203 2204 return; 2205 } 2206 2207 static void sk_stop(sc_if) 2208 struct sk_if_softc *sc_if; 2209 { 2210 int i; 2211 struct sk_softc *sc; 2212 struct ifnet *ifp; 2213 2214 sc = sc_if->sk_softc; 2215 ifp = &sc_if->arpcom.ac_if; 2216 2217 untimeout(sk_tick, sc_if, sc_if->sk_tick_ch); 2218 2219 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2220 u_int32_t val; 2221 2222 /* Put PHY back into reset. */ 2223 val = sk_win_read_4(sc, SK_GPIO); 2224 if (sc_if->sk_port == SK_PORT_A) { 2225 val |= SK_GPIO_DIR0; 2226 val &= ~SK_GPIO_DAT0; 2227 } else { 2228 val |= SK_GPIO_DIR2; 2229 val &= ~SK_GPIO_DAT2; 2230 } 2231 sk_win_write_4(sc, SK_GPIO, val); 2232 } 2233 2234 /* Turn off various components of this interface. */ 2235 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2236 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_RESET); 2237 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2238 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2239 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2240 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2241 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2242 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2243 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2244 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2245 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2246 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2247 2248 /* Disable interrupts */ 2249 if (sc_if->sk_port == SK_PORT_A) 2250 sc->sk_intrmask &= ~SK_INTRS1; 2251 else 2252 sc->sk_intrmask &= ~SK_INTRS2; 2253 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2254 2255 SK_XM_READ_2(sc_if, XM_ISR); 2256 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2257 2258 /* Free RX and TX mbufs still in the queues. */ 2259 for (i = 0; i < SK_RX_RING_CNT; i++) { 2260 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2261 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2262 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2263 } 2264 } 2265 2266 for (i = 0; i < SK_TX_RING_CNT; i++) { 2267 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2268 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2269 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2270 } 2271 } 2272 2273 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2274 2275 return; 2276 } 2277