1 /* $OpenBSD: if_sk.c,v 2.33 2003/08/12 05:23:06 nate Exp $ */ 2 3 /*- 4 * SPDX-License-Identifier: BSD-4-Clause 5 * 6 * Copyright (c) 1997, 1998, 1999, 2000 7 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Bill Paul. 20 * 4. Neither the name of the author nor the names of any co-contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 34 * THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 /*- 37 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 38 * 39 * Permission to use, copy, modify, and distribute this software for any 40 * purpose with or without fee is hereby granted, provided that the above 41 * copyright notice and this permission notice appear in all copies. 42 * 43 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 44 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 45 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 46 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 47 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 48 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 49 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 50 */ 51 52 #include <sys/cdefs.h> 53 __FBSDID("$FreeBSD$"); 54 55 /* 56 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 57 * the SK-984x series adapters, both single port and dual port. 58 * References: 59 * The XaQti XMAC II datasheet, 60 * https://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 61 * The SysKonnect GEnesis manual, http://www.syskonnect.com 62 * 63 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the 64 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 65 * convenience to others until Vitesse corrects this problem: 66 * 67 * https://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 68 * 69 * Written by Bill Paul <wpaul@ee.columbia.edu> 70 * Department of Electrical Engineering 71 * Columbia University, New York City 72 */ 73 /* 74 * The SysKonnect gigabit ethernet adapters consist of two main 75 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 76 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 77 * components and a PHY while the GEnesis controller provides a PCI 78 * interface with DMA support. Each card may have between 512K and 79 * 2MB of SRAM on board depending on the configuration. 80 * 81 * The SysKonnect GEnesis controller can have either one or two XMAC 82 * chips connected to it, allowing single or dual port NIC configurations. 83 * SysKonnect has the distinction of being the only vendor on the market 84 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 85 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 86 * XMAC registers. This driver takes advantage of these features to allow 87 * both XMACs to operate as independent interfaces. 88 */ 89 90 #include <sys/param.h> 91 #include <sys/systm.h> 92 #include <sys/bus.h> 93 #include <sys/endian.h> 94 #include <sys/mbuf.h> 95 #include <sys/malloc.h> 96 #include <sys/kernel.h> 97 #include <sys/module.h> 98 #include <sys/socket.h> 99 #include <sys/sockio.h> 100 #include <sys/queue.h> 101 #include <sys/sysctl.h> 102 103 #include <net/bpf.h> 104 #include <net/ethernet.h> 105 #include <net/if.h> 106 #include <net/if_var.h> 107 #include <net/if_arp.h> 108 #include <net/if_dl.h> 109 #include <net/if_media.h> 110 #include <net/if_types.h> 111 #include <net/if_vlan_var.h> 112 113 #include <netinet/in.h> 114 #include <netinet/in_systm.h> 115 #include <netinet/ip.h> 116 117 #include <machine/bus.h> 118 #include <machine/in_cksum.h> 119 #include <machine/resource.h> 120 #include <sys/rman.h> 121 122 #include <dev/mii/mii.h> 123 #include <dev/mii/miivar.h> 124 #include <dev/mii/brgphyreg.h> 125 126 #include <dev/pci/pcireg.h> 127 #include <dev/pci/pcivar.h> 128 129 #if 0 130 #define SK_USEIOSPACE 131 #endif 132 133 #include <dev/sk/if_skreg.h> 134 #include <dev/sk/xmaciireg.h> 135 #include <dev/sk/yukonreg.h> 136 137 MODULE_DEPEND(sk, pci, 1, 1, 1); 138 MODULE_DEPEND(sk, ether, 1, 1, 1); 139 MODULE_DEPEND(sk, miibus, 1, 1, 1); 140 141 /* "device miibus" required. See GENERIC if you get errors here. */ 142 #include "miibus_if.h" 143 144 static const struct sk_type sk_devs[] = { 145 { 146 VENDORID_SK, 147 DEVICEID_SK_V1, 148 "SysKonnect Gigabit Ethernet (V1.0)" 149 }, 150 { 151 VENDORID_SK, 152 DEVICEID_SK_V2, 153 "SysKonnect Gigabit Ethernet (V2.0)" 154 }, 155 { 156 VENDORID_MARVELL, 157 DEVICEID_SK_V2, 158 "Marvell Gigabit Ethernet" 159 }, 160 { 161 VENDORID_MARVELL, 162 DEVICEID_BELKIN_5005, 163 "Belkin F5D5005 Gigabit Ethernet" 164 }, 165 { 166 VENDORID_3COM, 167 DEVICEID_3COM_3C940, 168 "3Com 3C940 Gigabit Ethernet" 169 }, 170 { 171 VENDORID_LINKSYS, 172 DEVICEID_LINKSYS_EG1032, 173 "Linksys EG1032 Gigabit Ethernet" 174 }, 175 { 176 VENDORID_DLINK, 177 DEVICEID_DLINK_DGE530T_A1, 178 "D-Link DGE-530T Gigabit Ethernet" 179 }, 180 { 181 VENDORID_DLINK, 182 DEVICEID_DLINK_DGE530T_B1, 183 "D-Link DGE-530T Gigabit Ethernet" 184 }, 185 { 0, 0, NULL } 186 }; 187 188 static int skc_probe(device_t); 189 static int skc_attach(device_t); 190 static int skc_detach(device_t); 191 static int skc_shutdown(device_t); 192 static int skc_suspend(device_t); 193 static int skc_resume(device_t); 194 static bus_dma_tag_t skc_get_dma_tag(device_t, device_t); 195 static int sk_detach(device_t); 196 static int sk_probe(device_t); 197 static int sk_attach(device_t); 198 static void sk_tick(void *); 199 static void sk_yukon_tick(void *); 200 static void sk_intr(void *); 201 static void sk_intr_xmac(struct sk_if_softc *); 202 static void sk_intr_bcom(struct sk_if_softc *); 203 static void sk_intr_yukon(struct sk_if_softc *); 204 static __inline void sk_rxcksum(struct ifnet *, struct mbuf *, u_int32_t); 205 static __inline int sk_rxvalid(struct sk_softc *, u_int32_t, u_int32_t); 206 static void sk_rxeof(struct sk_if_softc *); 207 static void sk_jumbo_rxeof(struct sk_if_softc *); 208 static void sk_txeof(struct sk_if_softc *); 209 static void sk_txcksum(struct ifnet *, struct mbuf *, struct sk_tx_desc *); 210 static int sk_encap(struct sk_if_softc *, struct mbuf **); 211 static void sk_start(struct ifnet *); 212 static void sk_start_locked(struct ifnet *); 213 static int sk_ioctl(struct ifnet *, u_long, caddr_t); 214 static void sk_init(void *); 215 static void sk_init_locked(struct sk_if_softc *); 216 static void sk_init_xmac(struct sk_if_softc *); 217 static void sk_init_yukon(struct sk_if_softc *); 218 static void sk_stop(struct sk_if_softc *); 219 static void sk_watchdog(void *); 220 static int sk_ifmedia_upd(struct ifnet *); 221 static void sk_ifmedia_sts(struct ifnet *, struct ifmediareq *); 222 static void sk_reset(struct sk_softc *); 223 static __inline void sk_discard_rxbuf(struct sk_if_softc *, int); 224 static __inline void sk_discard_jumbo_rxbuf(struct sk_if_softc *, int); 225 static int sk_newbuf(struct sk_if_softc *, int); 226 static int sk_jumbo_newbuf(struct sk_if_softc *, int); 227 static void sk_dmamap_cb(void *, bus_dma_segment_t *, int, int); 228 static int sk_dma_alloc(struct sk_if_softc *); 229 static int sk_dma_jumbo_alloc(struct sk_if_softc *); 230 static void sk_dma_free(struct sk_if_softc *); 231 static void sk_dma_jumbo_free(struct sk_if_softc *); 232 static int sk_init_rx_ring(struct sk_if_softc *); 233 static int sk_init_jumbo_rx_ring(struct sk_if_softc *); 234 static void sk_init_tx_ring(struct sk_if_softc *); 235 static u_int32_t sk_win_read_4(struct sk_softc *, int); 236 static u_int16_t sk_win_read_2(struct sk_softc *, int); 237 static u_int8_t sk_win_read_1(struct sk_softc *, int); 238 static void sk_win_write_4(struct sk_softc *, int, u_int32_t); 239 static void sk_win_write_2(struct sk_softc *, int, u_int32_t); 240 static void sk_win_write_1(struct sk_softc *, int, u_int32_t); 241 242 static int sk_miibus_readreg(device_t, int, int); 243 static int sk_miibus_writereg(device_t, int, int, int); 244 static void sk_miibus_statchg(device_t); 245 246 static int sk_xmac_miibus_readreg(struct sk_if_softc *, int, int); 247 static int sk_xmac_miibus_writereg(struct sk_if_softc *, int, int, 248 int); 249 static void sk_xmac_miibus_statchg(struct sk_if_softc *); 250 251 static int sk_marv_miibus_readreg(struct sk_if_softc *, int, int); 252 static int sk_marv_miibus_writereg(struct sk_if_softc *, int, int, 253 int); 254 static void sk_marv_miibus_statchg(struct sk_if_softc *); 255 256 static uint32_t sk_xmchash(const uint8_t *); 257 static void sk_setfilt(struct sk_if_softc *, u_int16_t *, int); 258 static void sk_rxfilter(struct sk_if_softc *); 259 static void sk_rxfilter_genesis(struct sk_if_softc *); 260 static void sk_rxfilter_yukon(struct sk_if_softc *); 261 262 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high); 263 static int sysctl_hw_sk_int_mod(SYSCTL_HANDLER_ARGS); 264 265 /* Tunables. */ 266 static int jumbo_disable = 0; 267 TUNABLE_INT("hw.skc.jumbo_disable", &jumbo_disable); 268 269 /* 270 * It seems that SK-NET GENESIS supports very simple checksum offload 271 * capability for Tx and I believe it can generate 0 checksum value for 272 * UDP packets in Tx as the hardware can't differenciate UDP packets from 273 * TCP packets. 0 chcecksum value for UDP packet is an invalid one as it 274 * means sender didn't perforam checksum computation. For the safety I 275 * disabled UDP checksum offload capability at the moment. Alternatively 276 * we can intrduce a LINK0/LINK1 flag as hme(4) did in its Tx checksum 277 * offload routine. 278 */ 279 #define SK_CSUM_FEATURES (CSUM_TCP) 280 281 /* 282 * Note that we have newbus methods for both the GEnesis controller 283 * itself and the XMAC(s). The XMACs are children of the GEnesis, and 284 * the miibus code is a child of the XMACs. We need to do it this way 285 * so that the miibus drivers can access the PHY registers on the 286 * right PHY. It's not quite what I had in mind, but it's the only 287 * design that achieves the desired effect. 288 */ 289 static device_method_t skc_methods[] = { 290 /* Device interface */ 291 DEVMETHOD(device_probe, skc_probe), 292 DEVMETHOD(device_attach, skc_attach), 293 DEVMETHOD(device_detach, skc_detach), 294 DEVMETHOD(device_suspend, skc_suspend), 295 DEVMETHOD(device_resume, skc_resume), 296 DEVMETHOD(device_shutdown, skc_shutdown), 297 298 DEVMETHOD(bus_get_dma_tag, skc_get_dma_tag), 299 300 DEVMETHOD_END 301 }; 302 303 static driver_t skc_driver = { 304 "skc", 305 skc_methods, 306 sizeof(struct sk_softc) 307 }; 308 309 static devclass_t skc_devclass; 310 311 static device_method_t sk_methods[] = { 312 /* Device interface */ 313 DEVMETHOD(device_probe, sk_probe), 314 DEVMETHOD(device_attach, sk_attach), 315 DEVMETHOD(device_detach, sk_detach), 316 DEVMETHOD(device_shutdown, bus_generic_shutdown), 317 318 /* MII interface */ 319 DEVMETHOD(miibus_readreg, sk_miibus_readreg), 320 DEVMETHOD(miibus_writereg, sk_miibus_writereg), 321 DEVMETHOD(miibus_statchg, sk_miibus_statchg), 322 323 DEVMETHOD_END 324 }; 325 326 static driver_t sk_driver = { 327 "sk", 328 sk_methods, 329 sizeof(struct sk_if_softc) 330 }; 331 332 static devclass_t sk_devclass; 333 334 DRIVER_MODULE(skc, pci, skc_driver, skc_devclass, NULL, NULL); 335 DRIVER_MODULE(sk, skc, sk_driver, sk_devclass, NULL, NULL); 336 DRIVER_MODULE(miibus, sk, miibus_driver, miibus_devclass, NULL, NULL); 337 338 static struct resource_spec sk_res_spec_io[] = { 339 { SYS_RES_IOPORT, PCIR_BAR(1), RF_ACTIVE }, 340 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 341 { -1, 0, 0 } 342 }; 343 344 static struct resource_spec sk_res_spec_mem[] = { 345 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 346 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 347 { -1, 0, 0 } 348 }; 349 350 #define SK_SETBIT(sc, reg, x) \ 351 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 352 353 #define SK_CLRBIT(sc, reg, x) \ 354 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 355 356 #define SK_WIN_SETBIT_4(sc, reg, x) \ 357 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x) 358 359 #define SK_WIN_CLRBIT_4(sc, reg, x) \ 360 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x) 361 362 #define SK_WIN_SETBIT_2(sc, reg, x) \ 363 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x) 364 365 #define SK_WIN_CLRBIT_2(sc, reg, x) \ 366 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x) 367 368 static u_int32_t 369 sk_win_read_4(sc, reg) 370 struct sk_softc *sc; 371 int reg; 372 { 373 #ifdef SK_USEIOSPACE 374 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 375 return(CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg))); 376 #else 377 return(CSR_READ_4(sc, reg)); 378 #endif 379 } 380 381 static u_int16_t 382 sk_win_read_2(sc, reg) 383 struct sk_softc *sc; 384 int reg; 385 { 386 #ifdef SK_USEIOSPACE 387 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 388 return(CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg))); 389 #else 390 return(CSR_READ_2(sc, reg)); 391 #endif 392 } 393 394 static u_int8_t 395 sk_win_read_1(sc, reg) 396 struct sk_softc *sc; 397 int reg; 398 { 399 #ifdef SK_USEIOSPACE 400 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 401 return(CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg))); 402 #else 403 return(CSR_READ_1(sc, reg)); 404 #endif 405 } 406 407 static void 408 sk_win_write_4(sc, reg, val) 409 struct sk_softc *sc; 410 int reg; 411 u_int32_t val; 412 { 413 #ifdef SK_USEIOSPACE 414 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 415 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), val); 416 #else 417 CSR_WRITE_4(sc, reg, val); 418 #endif 419 return; 420 } 421 422 static void 423 sk_win_write_2(sc, reg, val) 424 struct sk_softc *sc; 425 int reg; 426 u_int32_t val; 427 { 428 #ifdef SK_USEIOSPACE 429 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 430 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), val); 431 #else 432 CSR_WRITE_2(sc, reg, val); 433 #endif 434 return; 435 } 436 437 static void 438 sk_win_write_1(sc, reg, val) 439 struct sk_softc *sc; 440 int reg; 441 u_int32_t val; 442 { 443 #ifdef SK_USEIOSPACE 444 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 445 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), val); 446 #else 447 CSR_WRITE_1(sc, reg, val); 448 #endif 449 return; 450 } 451 452 static int 453 sk_miibus_readreg(dev, phy, reg) 454 device_t dev; 455 int phy, reg; 456 { 457 struct sk_if_softc *sc_if; 458 int v; 459 460 sc_if = device_get_softc(dev); 461 462 SK_IF_MII_LOCK(sc_if); 463 switch(sc_if->sk_softc->sk_type) { 464 case SK_GENESIS: 465 v = sk_xmac_miibus_readreg(sc_if, phy, reg); 466 break; 467 case SK_YUKON: 468 case SK_YUKON_LITE: 469 case SK_YUKON_LP: 470 v = sk_marv_miibus_readreg(sc_if, phy, reg); 471 break; 472 default: 473 v = 0; 474 break; 475 } 476 SK_IF_MII_UNLOCK(sc_if); 477 478 return (v); 479 } 480 481 static int 482 sk_miibus_writereg(dev, phy, reg, val) 483 device_t dev; 484 int phy, reg, val; 485 { 486 struct sk_if_softc *sc_if; 487 int v; 488 489 sc_if = device_get_softc(dev); 490 491 SK_IF_MII_LOCK(sc_if); 492 switch(sc_if->sk_softc->sk_type) { 493 case SK_GENESIS: 494 v = sk_xmac_miibus_writereg(sc_if, phy, reg, val); 495 break; 496 case SK_YUKON: 497 case SK_YUKON_LITE: 498 case SK_YUKON_LP: 499 v = sk_marv_miibus_writereg(sc_if, phy, reg, val); 500 break; 501 default: 502 v = 0; 503 break; 504 } 505 SK_IF_MII_UNLOCK(sc_if); 506 507 return (v); 508 } 509 510 static void 511 sk_miibus_statchg(dev) 512 device_t dev; 513 { 514 struct sk_if_softc *sc_if; 515 516 sc_if = device_get_softc(dev); 517 518 SK_IF_MII_LOCK(sc_if); 519 switch(sc_if->sk_softc->sk_type) { 520 case SK_GENESIS: 521 sk_xmac_miibus_statchg(sc_if); 522 break; 523 case SK_YUKON: 524 case SK_YUKON_LITE: 525 case SK_YUKON_LP: 526 sk_marv_miibus_statchg(sc_if); 527 break; 528 } 529 SK_IF_MII_UNLOCK(sc_if); 530 531 return; 532 } 533 534 static int 535 sk_xmac_miibus_readreg(sc_if, phy, reg) 536 struct sk_if_softc *sc_if; 537 int phy, reg; 538 { 539 int i; 540 541 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 542 SK_XM_READ_2(sc_if, XM_PHY_DATA); 543 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 544 for (i = 0; i < SK_TIMEOUT; i++) { 545 DELAY(1); 546 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 547 XM_MMUCMD_PHYDATARDY) 548 break; 549 } 550 551 if (i == SK_TIMEOUT) { 552 if_printf(sc_if->sk_ifp, "phy failed to come ready\n"); 553 return(0); 554 } 555 } 556 DELAY(1); 557 i = SK_XM_READ_2(sc_if, XM_PHY_DATA); 558 559 return(i); 560 } 561 562 static int 563 sk_xmac_miibus_writereg(sc_if, phy, reg, val) 564 struct sk_if_softc *sc_if; 565 int phy, reg, val; 566 { 567 int i; 568 569 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 570 for (i = 0; i < SK_TIMEOUT; i++) { 571 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 572 break; 573 } 574 575 if (i == SK_TIMEOUT) { 576 if_printf(sc_if->sk_ifp, "phy failed to come ready\n"); 577 return (ETIMEDOUT); 578 } 579 580 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 581 for (i = 0; i < SK_TIMEOUT; i++) { 582 DELAY(1); 583 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 584 break; 585 } 586 if (i == SK_TIMEOUT) 587 if_printf(sc_if->sk_ifp, "phy write timed out\n"); 588 589 return(0); 590 } 591 592 static void 593 sk_xmac_miibus_statchg(sc_if) 594 struct sk_if_softc *sc_if; 595 { 596 struct mii_data *mii; 597 598 mii = device_get_softc(sc_if->sk_miibus); 599 600 /* 601 * If this is a GMII PHY, manually set the XMAC's 602 * duplex mode accordingly. 603 */ 604 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 605 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 606 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 607 } else { 608 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 609 } 610 } 611 } 612 613 static int 614 sk_marv_miibus_readreg(sc_if, phy, reg) 615 struct sk_if_softc *sc_if; 616 int phy, reg; 617 { 618 u_int16_t val; 619 int i; 620 621 if (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 622 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER) { 623 return(0); 624 } 625 626 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 627 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 628 629 for (i = 0; i < SK_TIMEOUT; i++) { 630 DELAY(1); 631 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 632 if (val & YU_SMICR_READ_VALID) 633 break; 634 } 635 636 if (i == SK_TIMEOUT) { 637 if_printf(sc_if->sk_ifp, "phy failed to come ready\n"); 638 return(0); 639 } 640 641 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 642 643 return(val); 644 } 645 646 static int 647 sk_marv_miibus_writereg(sc_if, phy, reg, val) 648 struct sk_if_softc *sc_if; 649 int phy, reg, val; 650 { 651 int i; 652 653 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 654 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 655 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 656 657 for (i = 0; i < SK_TIMEOUT; i++) { 658 DELAY(1); 659 if ((SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY) == 0) 660 break; 661 } 662 if (i == SK_TIMEOUT) 663 if_printf(sc_if->sk_ifp, "phy write timeout\n"); 664 665 return(0); 666 } 667 668 static void 669 sk_marv_miibus_statchg(sc_if) 670 struct sk_if_softc *sc_if; 671 { 672 return; 673 } 674 675 #define HASH_BITS 6 676 677 static u_int32_t 678 sk_xmchash(addr) 679 const uint8_t *addr; 680 { 681 uint32_t crc; 682 683 /* Compute CRC for the address value. */ 684 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 685 686 return (~crc & ((1 << HASH_BITS) - 1)); 687 } 688 689 static void 690 sk_setfilt(sc_if, addr, slot) 691 struct sk_if_softc *sc_if; 692 u_int16_t *addr; 693 int slot; 694 { 695 int base; 696 697 base = XM_RXFILT_ENTRY(slot); 698 699 SK_XM_WRITE_2(sc_if, base, addr[0]); 700 SK_XM_WRITE_2(sc_if, base + 2, addr[1]); 701 SK_XM_WRITE_2(sc_if, base + 4, addr[2]); 702 703 return; 704 } 705 706 static void 707 sk_rxfilter(sc_if) 708 struct sk_if_softc *sc_if; 709 { 710 struct sk_softc *sc; 711 712 SK_IF_LOCK_ASSERT(sc_if); 713 714 sc = sc_if->sk_softc; 715 if (sc->sk_type == SK_GENESIS) 716 sk_rxfilter_genesis(sc_if); 717 else 718 sk_rxfilter_yukon(sc_if); 719 } 720 721 struct sk_add_maddr_genesis_ctx { 722 struct sk_if_softc *sc_if; 723 uint32_t hashes[2]; 724 uint32_t mode; 725 }; 726 727 static u_int 728 sk_add_maddr_genesis(void *arg, struct sockaddr_dl *sdl, u_int cnt) 729 { 730 struct sk_add_maddr_genesis_ctx *ctx = arg; 731 int h; 732 733 /* 734 * Program the first XM_RXFILT_MAX multicast groups 735 * into the perfect filter. 736 */ 737 if (cnt + 1 < XM_RXFILT_MAX) { 738 sk_setfilt(ctx->sc_if, (uint16_t *)LLADDR(sdl), cnt + 1); 739 ctx->mode |= XM_MODE_RX_USE_PERFECT; 740 return (1); 741 } 742 h = sk_xmchash((const uint8_t *)LLADDR(sdl)); 743 if (h < 32) 744 ctx->hashes[0] |= (1 << h); 745 else 746 ctx->hashes[1] |= (1 << (h - 32)); 747 ctx->mode |= XM_MODE_RX_USE_HASH; 748 749 return (1); 750 } 751 752 static void 753 sk_rxfilter_genesis(struct sk_if_softc *sc_if) 754 { 755 struct ifnet *ifp = sc_if->sk_ifp; 756 struct sk_add_maddr_genesis_ctx ctx = { sc_if, { 0, 0 } }; 757 int i; 758 u_int16_t dummy[] = { 0, 0, 0 }; 759 760 SK_IF_LOCK_ASSERT(sc_if); 761 762 ctx.mode = SK_XM_READ_4(sc_if, XM_MODE); 763 ctx.mode &= ~(XM_MODE_RX_PROMISC | XM_MODE_RX_USE_HASH | 764 XM_MODE_RX_USE_PERFECT); 765 /* First, zot all the existing perfect filters. */ 766 for (i = 1; i < XM_RXFILT_MAX; i++) 767 sk_setfilt(sc_if, dummy, i); 768 769 /* Now program new ones. */ 770 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 771 if (ifp->if_flags & IFF_ALLMULTI) 772 ctx.mode |= XM_MODE_RX_USE_HASH; 773 if (ifp->if_flags & IFF_PROMISC) 774 ctx.mode |= XM_MODE_RX_PROMISC; 775 ctx.hashes[0] = 0xFFFFFFFF; 776 ctx.hashes[1] = 0xFFFFFFFF; 777 } else 778 /* XXX want to maintain reverse semantics */ 779 if_foreach_llmaddr(ifp, sk_add_maddr_genesis, &ctx); 780 781 SK_XM_WRITE_4(sc_if, XM_MODE, ctx.mode); 782 SK_XM_WRITE_4(sc_if, XM_MAR0, ctx.hashes[0]); 783 SK_XM_WRITE_4(sc_if, XM_MAR2, ctx.hashes[1]); 784 } 785 786 static u_int 787 sk_hash_maddr_yukon(void *arg, struct sockaddr_dl *sdl, u_int cnt) 788 { 789 uint32_t crc, *hashes = arg; 790 791 crc = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN); 792 /* Just want the 6 least significant bits. */ 793 crc &= 0x3f; 794 /* Set the corresponding bit in the hash table. */ 795 hashes[crc >> 5] |= 1 << (crc & 0x1f); 796 797 return (1); 798 } 799 800 static void 801 sk_rxfilter_yukon(struct sk_if_softc *sc_if) 802 { 803 struct ifnet *ifp; 804 uint32_t hashes[2] = { 0, 0 }, mode; 805 806 SK_IF_LOCK_ASSERT(sc_if); 807 808 ifp = sc_if->sk_ifp; 809 mode = SK_YU_READ_2(sc_if, YUKON_RCR); 810 if (ifp->if_flags & IFF_PROMISC) 811 mode &= ~(YU_RCR_UFLEN | YU_RCR_MUFLEN); 812 else if (ifp->if_flags & IFF_ALLMULTI) { 813 mode |= YU_RCR_UFLEN | YU_RCR_MUFLEN; 814 hashes[0] = 0xFFFFFFFF; 815 hashes[1] = 0xFFFFFFFF; 816 } else { 817 mode |= YU_RCR_UFLEN; 818 if_foreach_llmaddr(ifp, sk_hash_maddr_yukon, hashes); 819 if (hashes[0] != 0 || hashes[1] != 0) 820 mode |= YU_RCR_MUFLEN; 821 } 822 823 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 824 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 825 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 826 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 827 SK_YU_WRITE_2(sc_if, YUKON_RCR, mode); 828 } 829 830 static int 831 sk_init_rx_ring(sc_if) 832 struct sk_if_softc *sc_if; 833 { 834 struct sk_ring_data *rd; 835 bus_addr_t addr; 836 u_int32_t csum_start; 837 int i; 838 839 sc_if->sk_cdata.sk_rx_cons = 0; 840 841 csum_start = (ETHER_HDR_LEN + sizeof(struct ip)) << 16 | 842 ETHER_HDR_LEN; 843 rd = &sc_if->sk_rdata; 844 bzero(rd->sk_rx_ring, sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 845 for (i = 0; i < SK_RX_RING_CNT; i++) { 846 if (sk_newbuf(sc_if, i) != 0) 847 return (ENOBUFS); 848 if (i == (SK_RX_RING_CNT - 1)) 849 addr = SK_RX_RING_ADDR(sc_if, 0); 850 else 851 addr = SK_RX_RING_ADDR(sc_if, i + 1); 852 rd->sk_rx_ring[i].sk_next = htole32(SK_ADDR_LO(addr)); 853 rd->sk_rx_ring[i].sk_csum_start = htole32(csum_start); 854 } 855 856 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag, 857 sc_if->sk_cdata.sk_rx_ring_map, 858 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 859 860 return(0); 861 } 862 863 static int 864 sk_init_jumbo_rx_ring(sc_if) 865 struct sk_if_softc *sc_if; 866 { 867 struct sk_ring_data *rd; 868 bus_addr_t addr; 869 u_int32_t csum_start; 870 int i; 871 872 sc_if->sk_cdata.sk_jumbo_rx_cons = 0; 873 874 csum_start = ((ETHER_HDR_LEN + sizeof(struct ip)) << 16) | 875 ETHER_HDR_LEN; 876 rd = &sc_if->sk_rdata; 877 bzero(rd->sk_jumbo_rx_ring, 878 sizeof(struct sk_rx_desc) * SK_JUMBO_RX_RING_CNT); 879 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) { 880 if (sk_jumbo_newbuf(sc_if, i) != 0) 881 return (ENOBUFS); 882 if (i == (SK_JUMBO_RX_RING_CNT - 1)) 883 addr = SK_JUMBO_RX_RING_ADDR(sc_if, 0); 884 else 885 addr = SK_JUMBO_RX_RING_ADDR(sc_if, i + 1); 886 rd->sk_jumbo_rx_ring[i].sk_next = htole32(SK_ADDR_LO(addr)); 887 rd->sk_jumbo_rx_ring[i].sk_csum_start = htole32(csum_start); 888 } 889 890 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 891 sc_if->sk_cdata.sk_jumbo_rx_ring_map, 892 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 893 894 return (0); 895 } 896 897 static void 898 sk_init_tx_ring(sc_if) 899 struct sk_if_softc *sc_if; 900 { 901 struct sk_ring_data *rd; 902 struct sk_txdesc *txd; 903 bus_addr_t addr; 904 int i; 905 906 STAILQ_INIT(&sc_if->sk_cdata.sk_txfreeq); 907 STAILQ_INIT(&sc_if->sk_cdata.sk_txbusyq); 908 909 sc_if->sk_cdata.sk_tx_prod = 0; 910 sc_if->sk_cdata.sk_tx_cons = 0; 911 sc_if->sk_cdata.sk_tx_cnt = 0; 912 913 rd = &sc_if->sk_rdata; 914 bzero(rd->sk_tx_ring, sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 915 for (i = 0; i < SK_TX_RING_CNT; i++) { 916 if (i == (SK_TX_RING_CNT - 1)) 917 addr = SK_TX_RING_ADDR(sc_if, 0); 918 else 919 addr = SK_TX_RING_ADDR(sc_if, i + 1); 920 rd->sk_tx_ring[i].sk_next = htole32(SK_ADDR_LO(addr)); 921 txd = &sc_if->sk_cdata.sk_txdesc[i]; 922 STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txfreeq, txd, tx_q); 923 } 924 925 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag, 926 sc_if->sk_cdata.sk_tx_ring_map, 927 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 928 } 929 930 static __inline void 931 sk_discard_rxbuf(sc_if, idx) 932 struct sk_if_softc *sc_if; 933 int idx; 934 { 935 struct sk_rx_desc *r; 936 struct sk_rxdesc *rxd; 937 struct mbuf *m; 938 939 940 r = &sc_if->sk_rdata.sk_rx_ring[idx]; 941 rxd = &sc_if->sk_cdata.sk_rxdesc[idx]; 942 m = rxd->rx_m; 943 r->sk_ctl = htole32(m->m_len | SK_RXSTAT | SK_OPCODE_CSUM); 944 } 945 946 static __inline void 947 sk_discard_jumbo_rxbuf(sc_if, idx) 948 struct sk_if_softc *sc_if; 949 int idx; 950 { 951 struct sk_rx_desc *r; 952 struct sk_rxdesc *rxd; 953 struct mbuf *m; 954 955 r = &sc_if->sk_rdata.sk_jumbo_rx_ring[idx]; 956 rxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[idx]; 957 m = rxd->rx_m; 958 r->sk_ctl = htole32(m->m_len | SK_RXSTAT | SK_OPCODE_CSUM); 959 } 960 961 static int 962 sk_newbuf(sc_if, idx) 963 struct sk_if_softc *sc_if; 964 int idx; 965 { 966 struct sk_rx_desc *r; 967 struct sk_rxdesc *rxd; 968 struct mbuf *m; 969 bus_dma_segment_t segs[1]; 970 bus_dmamap_t map; 971 int nsegs; 972 973 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 974 if (m == NULL) 975 return (ENOBUFS); 976 m->m_len = m->m_pkthdr.len = MCLBYTES; 977 m_adj(m, ETHER_ALIGN); 978 979 if (bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_rx_tag, 980 sc_if->sk_cdata.sk_rx_sparemap, m, segs, &nsegs, 0) != 0) { 981 m_freem(m); 982 return (ENOBUFS); 983 } 984 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 985 986 rxd = &sc_if->sk_cdata.sk_rxdesc[idx]; 987 if (rxd->rx_m != NULL) { 988 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap, 989 BUS_DMASYNC_POSTREAD); 990 bus_dmamap_unload(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap); 991 } 992 map = rxd->rx_dmamap; 993 rxd->rx_dmamap = sc_if->sk_cdata.sk_rx_sparemap; 994 sc_if->sk_cdata.sk_rx_sparemap = map; 995 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap, 996 BUS_DMASYNC_PREREAD); 997 rxd->rx_m = m; 998 r = &sc_if->sk_rdata.sk_rx_ring[idx]; 999 r->sk_data_lo = htole32(SK_ADDR_LO(segs[0].ds_addr)); 1000 r->sk_data_hi = htole32(SK_ADDR_HI(segs[0].ds_addr)); 1001 r->sk_ctl = htole32(segs[0].ds_len | SK_RXSTAT | SK_OPCODE_CSUM); 1002 1003 return (0); 1004 } 1005 1006 static int 1007 sk_jumbo_newbuf(sc_if, idx) 1008 struct sk_if_softc *sc_if; 1009 int idx; 1010 { 1011 struct sk_rx_desc *r; 1012 struct sk_rxdesc *rxd; 1013 struct mbuf *m; 1014 bus_dma_segment_t segs[1]; 1015 bus_dmamap_t map; 1016 int nsegs; 1017 1018 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 1019 if (m == NULL) 1020 return (ENOBUFS); 1021 m->m_pkthdr.len = m->m_len = MJUM9BYTES; 1022 /* 1023 * Adjust alignment so packet payload begins on a 1024 * longword boundary. Mandatory for Alpha, useful on 1025 * x86 too. 1026 */ 1027 m_adj(m, ETHER_ALIGN); 1028 1029 if (bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_jumbo_rx_tag, 1030 sc_if->sk_cdata.sk_jumbo_rx_sparemap, m, segs, &nsegs, 0) != 0) { 1031 m_freem(m); 1032 return (ENOBUFS); 1033 } 1034 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1035 1036 rxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[idx]; 1037 if (rxd->rx_m != NULL) { 1038 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag, rxd->rx_dmamap, 1039 BUS_DMASYNC_POSTREAD); 1040 bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_tag, 1041 rxd->rx_dmamap); 1042 } 1043 map = rxd->rx_dmamap; 1044 rxd->rx_dmamap = sc_if->sk_cdata.sk_jumbo_rx_sparemap; 1045 sc_if->sk_cdata.sk_jumbo_rx_sparemap = map; 1046 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag, rxd->rx_dmamap, 1047 BUS_DMASYNC_PREREAD); 1048 rxd->rx_m = m; 1049 r = &sc_if->sk_rdata.sk_jumbo_rx_ring[idx]; 1050 r->sk_data_lo = htole32(SK_ADDR_LO(segs[0].ds_addr)); 1051 r->sk_data_hi = htole32(SK_ADDR_HI(segs[0].ds_addr)); 1052 r->sk_ctl = htole32(segs[0].ds_len | SK_RXSTAT | SK_OPCODE_CSUM); 1053 1054 return (0); 1055 } 1056 1057 /* 1058 * Set media options. 1059 */ 1060 static int 1061 sk_ifmedia_upd(ifp) 1062 struct ifnet *ifp; 1063 { 1064 struct sk_if_softc *sc_if = ifp->if_softc; 1065 struct mii_data *mii; 1066 1067 mii = device_get_softc(sc_if->sk_miibus); 1068 sk_init(sc_if); 1069 mii_mediachg(mii); 1070 1071 return(0); 1072 } 1073 1074 /* 1075 * Report current media status. 1076 */ 1077 static void 1078 sk_ifmedia_sts(ifp, ifmr) 1079 struct ifnet *ifp; 1080 struct ifmediareq *ifmr; 1081 { 1082 struct sk_if_softc *sc_if; 1083 struct mii_data *mii; 1084 1085 sc_if = ifp->if_softc; 1086 mii = device_get_softc(sc_if->sk_miibus); 1087 1088 mii_pollstat(mii); 1089 ifmr->ifm_active = mii->mii_media_active; 1090 ifmr->ifm_status = mii->mii_media_status; 1091 1092 return; 1093 } 1094 1095 static int 1096 sk_ioctl(ifp, command, data) 1097 struct ifnet *ifp; 1098 u_long command; 1099 caddr_t data; 1100 { 1101 struct sk_if_softc *sc_if = ifp->if_softc; 1102 struct ifreq *ifr = (struct ifreq *) data; 1103 int error, mask; 1104 struct mii_data *mii; 1105 1106 error = 0; 1107 switch(command) { 1108 case SIOCSIFMTU: 1109 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > SK_JUMBO_MTU) 1110 error = EINVAL; 1111 else if (ifp->if_mtu != ifr->ifr_mtu) { 1112 if (sc_if->sk_jumbo_disable != 0 && 1113 ifr->ifr_mtu > SK_MAX_FRAMELEN) 1114 error = EINVAL; 1115 else { 1116 SK_IF_LOCK(sc_if); 1117 ifp->if_mtu = ifr->ifr_mtu; 1118 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1119 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1120 sk_init_locked(sc_if); 1121 } 1122 SK_IF_UNLOCK(sc_if); 1123 } 1124 } 1125 break; 1126 case SIOCSIFFLAGS: 1127 SK_IF_LOCK(sc_if); 1128 if (ifp->if_flags & IFF_UP) { 1129 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1130 if ((ifp->if_flags ^ sc_if->sk_if_flags) 1131 & (IFF_PROMISC | IFF_ALLMULTI)) 1132 sk_rxfilter(sc_if); 1133 } else 1134 sk_init_locked(sc_if); 1135 } else { 1136 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1137 sk_stop(sc_if); 1138 } 1139 sc_if->sk_if_flags = ifp->if_flags; 1140 SK_IF_UNLOCK(sc_if); 1141 break; 1142 case SIOCADDMULTI: 1143 case SIOCDELMULTI: 1144 SK_IF_LOCK(sc_if); 1145 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1146 sk_rxfilter(sc_if); 1147 SK_IF_UNLOCK(sc_if); 1148 break; 1149 case SIOCGIFMEDIA: 1150 case SIOCSIFMEDIA: 1151 mii = device_get_softc(sc_if->sk_miibus); 1152 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1153 break; 1154 case SIOCSIFCAP: 1155 SK_IF_LOCK(sc_if); 1156 if (sc_if->sk_softc->sk_type == SK_GENESIS) { 1157 SK_IF_UNLOCK(sc_if); 1158 break; 1159 } 1160 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1161 if ((mask & IFCAP_TXCSUM) != 0 && 1162 (IFCAP_TXCSUM & ifp->if_capabilities) != 0) { 1163 ifp->if_capenable ^= IFCAP_TXCSUM; 1164 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 1165 ifp->if_hwassist |= SK_CSUM_FEATURES; 1166 else 1167 ifp->if_hwassist &= ~SK_CSUM_FEATURES; 1168 } 1169 if ((mask & IFCAP_RXCSUM) != 0 && 1170 (IFCAP_RXCSUM & ifp->if_capabilities) != 0) 1171 ifp->if_capenable ^= IFCAP_RXCSUM; 1172 SK_IF_UNLOCK(sc_if); 1173 break; 1174 default: 1175 error = ether_ioctl(ifp, command, data); 1176 break; 1177 } 1178 1179 return (error); 1180 } 1181 1182 /* 1183 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device 1184 * IDs against our list and return a device name if we find a match. 1185 */ 1186 static int 1187 skc_probe(dev) 1188 device_t dev; 1189 { 1190 const struct sk_type *t = sk_devs; 1191 1192 while(t->sk_name != NULL) { 1193 if ((pci_get_vendor(dev) == t->sk_vid) && 1194 (pci_get_device(dev) == t->sk_did)) { 1195 /* 1196 * Only attach to rev. 2 of the Linksys EG1032 adapter. 1197 * Rev. 3 is supported by re(4). 1198 */ 1199 if ((t->sk_vid == VENDORID_LINKSYS) && 1200 (t->sk_did == DEVICEID_LINKSYS_EG1032) && 1201 (pci_get_subdevice(dev) != 1202 SUBDEVICEID_LINKSYS_EG1032_REV2)) { 1203 t++; 1204 continue; 1205 } 1206 device_set_desc(dev, t->sk_name); 1207 return (BUS_PROBE_DEFAULT); 1208 } 1209 t++; 1210 } 1211 1212 return(ENXIO); 1213 } 1214 1215 /* 1216 * Force the GEnesis into reset, then bring it out of reset. 1217 */ 1218 static void 1219 sk_reset(sc) 1220 struct sk_softc *sc; 1221 { 1222 1223 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 1224 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 1225 if (SK_YUKON_FAMILY(sc->sk_type)) 1226 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 1227 1228 DELAY(1000); 1229 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 1230 DELAY(2); 1231 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1232 if (SK_YUKON_FAMILY(sc->sk_type)) 1233 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 1234 1235 if (sc->sk_type == SK_GENESIS) { 1236 /* Configure packet arbiter */ 1237 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1238 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1239 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1240 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1241 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1242 } 1243 1244 /* Enable RAM interface */ 1245 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1246 1247 /* 1248 * Configure interrupt moderation. The moderation timer 1249 * defers interrupts specified in the interrupt moderation 1250 * timer mask based on the timeout specified in the interrupt 1251 * moderation timer init register. Each bit in the timer 1252 * register represents one tick, so to specify a timeout in 1253 * microseconds, we have to multiply by the correct number of 1254 * ticks-per-microsecond. 1255 */ 1256 switch (sc->sk_type) { 1257 case SK_GENESIS: 1258 sc->sk_int_ticks = SK_IMTIMER_TICKS_GENESIS; 1259 break; 1260 default: 1261 sc->sk_int_ticks = SK_IMTIMER_TICKS_YUKON; 1262 break; 1263 } 1264 if (bootverbose) 1265 device_printf(sc->sk_dev, "interrupt moderation is %d us\n", 1266 sc->sk_int_mod); 1267 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod, 1268 sc->sk_int_ticks)); 1269 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 1270 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 1271 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1272 1273 return; 1274 } 1275 1276 static int 1277 sk_probe(dev) 1278 device_t dev; 1279 { 1280 struct sk_softc *sc; 1281 1282 sc = device_get_softc(device_get_parent(dev)); 1283 1284 /* 1285 * Not much to do here. We always know there will be 1286 * at least one XMAC present, and if there are two, 1287 * skc_attach() will create a second device instance 1288 * for us. 1289 */ 1290 switch (sc->sk_type) { 1291 case SK_GENESIS: 1292 device_set_desc(dev, "XaQti Corp. XMAC II"); 1293 break; 1294 case SK_YUKON: 1295 case SK_YUKON_LITE: 1296 case SK_YUKON_LP: 1297 device_set_desc(dev, "Marvell Semiconductor, Inc. Yukon"); 1298 break; 1299 } 1300 1301 return (BUS_PROBE_DEFAULT); 1302 } 1303 1304 /* 1305 * Each XMAC chip is attached as a separate logical IP interface. 1306 * Single port cards will have only one logical interface of course. 1307 */ 1308 static int 1309 sk_attach(dev) 1310 device_t dev; 1311 { 1312 struct sk_softc *sc; 1313 struct sk_if_softc *sc_if; 1314 struct ifnet *ifp; 1315 u_int32_t r; 1316 int error, i, phy, port; 1317 u_char eaddr[6]; 1318 u_char inv_mac[] = {0, 0, 0, 0, 0, 0}; 1319 1320 if (dev == NULL) 1321 return(EINVAL); 1322 1323 error = 0; 1324 sc_if = device_get_softc(dev); 1325 sc = device_get_softc(device_get_parent(dev)); 1326 port = *(int *)device_get_ivars(dev); 1327 1328 sc_if->sk_if_dev = dev; 1329 sc_if->sk_port = port; 1330 sc_if->sk_softc = sc; 1331 sc->sk_if[port] = sc_if; 1332 if (port == SK_PORT_A) 1333 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1334 if (port == SK_PORT_B) 1335 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1336 1337 callout_init_mtx(&sc_if->sk_tick_ch, &sc_if->sk_softc->sk_mtx, 0); 1338 callout_init_mtx(&sc_if->sk_watchdog_ch, &sc_if->sk_softc->sk_mtx, 0); 1339 1340 if (sk_dma_alloc(sc_if) != 0) { 1341 error = ENOMEM; 1342 goto fail; 1343 } 1344 sk_dma_jumbo_alloc(sc_if); 1345 1346 ifp = sc_if->sk_ifp = if_alloc(IFT_ETHER); 1347 if (ifp == NULL) { 1348 device_printf(sc_if->sk_if_dev, "can not if_alloc()\n"); 1349 error = ENOSPC; 1350 goto fail; 1351 } 1352 ifp->if_softc = sc_if; 1353 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1354 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1355 /* 1356 * SK_GENESIS has a bug in checksum offload - From linux. 1357 */ 1358 if (sc_if->sk_softc->sk_type != SK_GENESIS) { 1359 ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_RXCSUM; 1360 ifp->if_hwassist = 0; 1361 } else { 1362 ifp->if_capabilities = 0; 1363 ifp->if_hwassist = 0; 1364 } 1365 ifp->if_capenable = ifp->if_capabilities; 1366 /* 1367 * Some revision of Yukon controller generates corrupted 1368 * frame when TX checksum offloading is enabled. The 1369 * frame has a valid checksum value so payload might be 1370 * modified during TX checksum calculation. Disable TX 1371 * checksum offloading but give users chance to enable it 1372 * when they know their controller works without problems 1373 * with TX checksum offloading. 1374 */ 1375 ifp->if_capenable &= ~IFCAP_TXCSUM; 1376 ifp->if_ioctl = sk_ioctl; 1377 ifp->if_start = sk_start; 1378 ifp->if_init = sk_init; 1379 IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1); 1380 ifp->if_snd.ifq_drv_maxlen = SK_TX_RING_CNT - 1; 1381 IFQ_SET_READY(&ifp->if_snd); 1382 1383 /* 1384 * Get station address for this interface. Note that 1385 * dual port cards actually come with three station 1386 * addresses: one for each port, plus an extra. The 1387 * extra one is used by the SysKonnect driver software 1388 * as a 'virtual' station address for when both ports 1389 * are operating in failover mode. Currently we don't 1390 * use this extra address. 1391 */ 1392 SK_IF_LOCK(sc_if); 1393 for (i = 0; i < ETHER_ADDR_LEN; i++) 1394 eaddr[i] = 1395 sk_win_read_1(sc, SK_MAC0_0 + (port * 8) + i); 1396 1397 /* Verify whether the station address is invalid or not. */ 1398 if (bcmp(eaddr, inv_mac, sizeof(inv_mac)) == 0) { 1399 device_printf(sc_if->sk_if_dev, 1400 "Generating random ethernet address\n"); 1401 r = arc4random(); 1402 /* 1403 * Set OUI to convenient locally assigned address. 'b' 1404 * is 0x62, which has the locally assigned bit set, and 1405 * the broadcast/multicast bit clear. 1406 */ 1407 eaddr[0] = 'b'; 1408 eaddr[1] = 's'; 1409 eaddr[2] = 'd'; 1410 eaddr[3] = (r >> 16) & 0xff; 1411 eaddr[4] = (r >> 8) & 0xff; 1412 eaddr[5] = (r >> 0) & 0xff; 1413 } 1414 /* 1415 * Set up RAM buffer addresses. The NIC will have a certain 1416 * amount of SRAM on it, somewhere between 512K and 2MB. We 1417 * need to divide this up a) between the transmitter and 1418 * receiver and b) between the two XMACs, if this is a 1419 * dual port NIC. Our algotithm is to divide up the memory 1420 * evenly so that everyone gets a fair share. 1421 * 1422 * Just to be contrary, Yukon2 appears to have separate memory 1423 * for each MAC. 1424 */ 1425 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1426 u_int32_t chunk, val; 1427 1428 chunk = sc->sk_ramsize / 2; 1429 val = sc->sk_rboff / sizeof(u_int64_t); 1430 sc_if->sk_rx_ramstart = val; 1431 val += (chunk / sizeof(u_int64_t)); 1432 sc_if->sk_rx_ramend = val - 1; 1433 sc_if->sk_tx_ramstart = val; 1434 val += (chunk / sizeof(u_int64_t)); 1435 sc_if->sk_tx_ramend = val - 1; 1436 } else { 1437 u_int32_t chunk, val; 1438 1439 chunk = sc->sk_ramsize / 4; 1440 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1441 sizeof(u_int64_t); 1442 sc_if->sk_rx_ramstart = val; 1443 val += (chunk / sizeof(u_int64_t)); 1444 sc_if->sk_rx_ramend = val - 1; 1445 sc_if->sk_tx_ramstart = val; 1446 val += (chunk / sizeof(u_int64_t)); 1447 sc_if->sk_tx_ramend = val - 1; 1448 } 1449 1450 /* Read and save PHY type and set PHY address */ 1451 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1452 if (!SK_YUKON_FAMILY(sc->sk_type)) { 1453 switch(sc_if->sk_phytype) { 1454 case SK_PHYTYPE_XMAC: 1455 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1456 break; 1457 case SK_PHYTYPE_BCOM: 1458 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1459 break; 1460 default: 1461 device_printf(sc->sk_dev, "unsupported PHY type: %d\n", 1462 sc_if->sk_phytype); 1463 error = ENODEV; 1464 SK_IF_UNLOCK(sc_if); 1465 goto fail; 1466 } 1467 } else { 1468 if (sc_if->sk_phytype < SK_PHYTYPE_MARV_COPPER && 1469 sc->sk_pmd != 'S') { 1470 /* not initialized, punt */ 1471 sc_if->sk_phytype = SK_PHYTYPE_MARV_COPPER; 1472 sc->sk_coppertype = 1; 1473 } 1474 1475 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1476 1477 if (!(sc->sk_coppertype)) 1478 sc_if->sk_phytype = SK_PHYTYPE_MARV_FIBER; 1479 } 1480 1481 /* 1482 * Call MI attach routine. Can't hold locks when calling into ether_*. 1483 */ 1484 SK_IF_UNLOCK(sc_if); 1485 ether_ifattach(ifp, eaddr); 1486 SK_IF_LOCK(sc_if); 1487 1488 /* 1489 * The hardware should be ready for VLAN_MTU by default: 1490 * XMAC II has 0x8100 in VLAN Tag Level 1 register initially; 1491 * YU_SMR_MFL_VLAN is set by this driver in Yukon. 1492 * 1493 */ 1494 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1495 ifp->if_capenable |= IFCAP_VLAN_MTU; 1496 /* 1497 * Tell the upper layer(s) we support long frames. 1498 * Must appear after the call to ether_ifattach() because 1499 * ether_ifattach() sets ifi_hdrlen to the default value. 1500 */ 1501 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 1502 1503 /* 1504 * Do miibus setup. 1505 */ 1506 phy = MII_PHY_ANY; 1507 switch (sc->sk_type) { 1508 case SK_GENESIS: 1509 sk_init_xmac(sc_if); 1510 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 1511 phy = 0; 1512 break; 1513 case SK_YUKON: 1514 case SK_YUKON_LITE: 1515 case SK_YUKON_LP: 1516 sk_init_yukon(sc_if); 1517 phy = 0; 1518 break; 1519 } 1520 1521 SK_IF_UNLOCK(sc_if); 1522 error = mii_attach(dev, &sc_if->sk_miibus, ifp, sk_ifmedia_upd, 1523 sk_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0); 1524 if (error != 0) { 1525 device_printf(sc_if->sk_if_dev, "attaching PHYs failed\n"); 1526 ether_ifdetach(ifp); 1527 goto fail; 1528 } 1529 1530 fail: 1531 if (error) { 1532 /* Access should be ok even though lock has been dropped */ 1533 sc->sk_if[port] = NULL; 1534 sk_detach(dev); 1535 } 1536 1537 return(error); 1538 } 1539 1540 /* 1541 * Attach the interface. Allocate softc structures, do ifmedia 1542 * setup and ethernet/BPF attach. 1543 */ 1544 static int 1545 skc_attach(dev) 1546 device_t dev; 1547 { 1548 struct sk_softc *sc; 1549 int error = 0, *port; 1550 uint8_t skrs; 1551 const char *pname = NULL; 1552 char *revstr; 1553 1554 sc = device_get_softc(dev); 1555 sc->sk_dev = dev; 1556 1557 mtx_init(&sc->sk_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1558 MTX_DEF); 1559 mtx_init(&sc->sk_mii_mtx, "sk_mii_mutex", NULL, MTX_DEF); 1560 /* 1561 * Map control/status registers. 1562 */ 1563 pci_enable_busmaster(dev); 1564 1565 /* Allocate resources */ 1566 #ifdef SK_USEIOSPACE 1567 sc->sk_res_spec = sk_res_spec_io; 1568 #else 1569 sc->sk_res_spec = sk_res_spec_mem; 1570 #endif 1571 error = bus_alloc_resources(dev, sc->sk_res_spec, sc->sk_res); 1572 if (error) { 1573 if (sc->sk_res_spec == sk_res_spec_mem) 1574 sc->sk_res_spec = sk_res_spec_io; 1575 else 1576 sc->sk_res_spec = sk_res_spec_mem; 1577 error = bus_alloc_resources(dev, sc->sk_res_spec, sc->sk_res); 1578 if (error) { 1579 device_printf(dev, "couldn't allocate %s resources\n", 1580 sc->sk_res_spec == sk_res_spec_mem ? "memory" : 1581 "I/O"); 1582 goto fail; 1583 } 1584 } 1585 1586 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1587 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4) & 0xf; 1588 1589 /* Bail out if chip is not recognized. */ 1590 if (sc->sk_type != SK_GENESIS && !SK_YUKON_FAMILY(sc->sk_type)) { 1591 device_printf(dev, "unknown device: chipver=%02x, rev=%x\n", 1592 sc->sk_type, sc->sk_rev); 1593 error = ENXIO; 1594 goto fail; 1595 } 1596 1597 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 1598 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 1599 OID_AUTO, "int_mod", 1600 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 1601 &sc->sk_int_mod, 0, sysctl_hw_sk_int_mod, "I", 1602 "SK interrupt moderation"); 1603 1604 /* Pull in device tunables. */ 1605 sc->sk_int_mod = SK_IM_DEFAULT; 1606 error = resource_int_value(device_get_name(dev), device_get_unit(dev), 1607 "int_mod", &sc->sk_int_mod); 1608 if (error == 0) { 1609 if (sc->sk_int_mod < SK_IM_MIN || 1610 sc->sk_int_mod > SK_IM_MAX) { 1611 device_printf(dev, "int_mod value out of range; " 1612 "using default: %d\n", SK_IM_DEFAULT); 1613 sc->sk_int_mod = SK_IM_DEFAULT; 1614 } 1615 } 1616 1617 /* Reset the adapter. */ 1618 sk_reset(sc); 1619 1620 skrs = sk_win_read_1(sc, SK_EPROM0); 1621 if (sc->sk_type == SK_GENESIS) { 1622 /* Read and save RAM size and RAMbuffer offset */ 1623 switch(skrs) { 1624 case SK_RAMSIZE_512K_64: 1625 sc->sk_ramsize = 0x80000; 1626 sc->sk_rboff = SK_RBOFF_0; 1627 break; 1628 case SK_RAMSIZE_1024K_64: 1629 sc->sk_ramsize = 0x100000; 1630 sc->sk_rboff = SK_RBOFF_80000; 1631 break; 1632 case SK_RAMSIZE_1024K_128: 1633 sc->sk_ramsize = 0x100000; 1634 sc->sk_rboff = SK_RBOFF_0; 1635 break; 1636 case SK_RAMSIZE_2048K_128: 1637 sc->sk_ramsize = 0x200000; 1638 sc->sk_rboff = SK_RBOFF_0; 1639 break; 1640 default: 1641 device_printf(dev, "unknown ram size: %d\n", skrs); 1642 error = ENXIO; 1643 goto fail; 1644 } 1645 } else { /* SK_YUKON_FAMILY */ 1646 if (skrs == 0x00) 1647 sc->sk_ramsize = 0x20000; 1648 else 1649 sc->sk_ramsize = skrs * (1<<12); 1650 sc->sk_rboff = SK_RBOFF_0; 1651 } 1652 1653 /* Read and save physical media type */ 1654 sc->sk_pmd = sk_win_read_1(sc, SK_PMDTYPE); 1655 1656 if (sc->sk_pmd == 'T' || sc->sk_pmd == '1') 1657 sc->sk_coppertype = 1; 1658 else 1659 sc->sk_coppertype = 0; 1660 1661 /* Determine whether to name it with VPD PN or just make it up. 1662 * Marvell Yukon VPD PN seems to freqently be bogus. */ 1663 switch (pci_get_device(dev)) { 1664 case DEVICEID_SK_V1: 1665 case DEVICEID_BELKIN_5005: 1666 case DEVICEID_3COM_3C940: 1667 case DEVICEID_LINKSYS_EG1032: 1668 case DEVICEID_DLINK_DGE530T_A1: 1669 case DEVICEID_DLINK_DGE530T_B1: 1670 /* Stay with VPD PN. */ 1671 (void) pci_get_vpd_ident(dev, &pname); 1672 break; 1673 case DEVICEID_SK_V2: 1674 /* YUKON VPD PN might bear no resemblance to reality. */ 1675 switch (sc->sk_type) { 1676 case SK_GENESIS: 1677 /* Stay with VPD PN. */ 1678 (void) pci_get_vpd_ident(dev, &pname); 1679 break; 1680 case SK_YUKON: 1681 pname = "Marvell Yukon Gigabit Ethernet"; 1682 break; 1683 case SK_YUKON_LITE: 1684 pname = "Marvell Yukon Lite Gigabit Ethernet"; 1685 break; 1686 case SK_YUKON_LP: 1687 pname = "Marvell Yukon LP Gigabit Ethernet"; 1688 break; 1689 default: 1690 pname = "Marvell Yukon (Unknown) Gigabit Ethernet"; 1691 break; 1692 } 1693 1694 /* Yukon Lite Rev. A0 needs special test. */ 1695 if (sc->sk_type == SK_YUKON || sc->sk_type == SK_YUKON_LP) { 1696 u_int32_t far; 1697 u_int8_t testbyte; 1698 1699 /* Save flash address register before testing. */ 1700 far = sk_win_read_4(sc, SK_EP_ADDR); 1701 1702 sk_win_write_1(sc, SK_EP_ADDR+0x03, 0xff); 1703 testbyte = sk_win_read_1(sc, SK_EP_ADDR+0x03); 1704 1705 if (testbyte != 0x00) { 1706 /* Yukon Lite Rev. A0 detected. */ 1707 sc->sk_type = SK_YUKON_LITE; 1708 sc->sk_rev = SK_YUKON_LITE_REV_A0; 1709 /* Restore flash address register. */ 1710 sk_win_write_4(sc, SK_EP_ADDR, far); 1711 } 1712 } 1713 break; 1714 default: 1715 device_printf(dev, "unknown device: vendor=%04x, device=%04x, " 1716 "chipver=%02x, rev=%x\n", 1717 pci_get_vendor(dev), pci_get_device(dev), 1718 sc->sk_type, sc->sk_rev); 1719 error = ENXIO; 1720 goto fail; 1721 } 1722 1723 if (sc->sk_type == SK_YUKON_LITE) { 1724 switch (sc->sk_rev) { 1725 case SK_YUKON_LITE_REV_A0: 1726 revstr = "A0"; 1727 break; 1728 case SK_YUKON_LITE_REV_A1: 1729 revstr = "A1"; 1730 break; 1731 case SK_YUKON_LITE_REV_A3: 1732 revstr = "A3"; 1733 break; 1734 default: 1735 revstr = ""; 1736 break; 1737 } 1738 } else { 1739 revstr = ""; 1740 } 1741 1742 /* Announce the product name and more VPD data if there. */ 1743 if (pname != NULL) 1744 device_printf(dev, "%s rev. %s(0x%x)\n", 1745 pname, revstr, sc->sk_rev); 1746 1747 if (bootverbose) { 1748 device_printf(dev, "chip ver = 0x%02x\n", sc->sk_type); 1749 device_printf(dev, "chip rev = 0x%02x\n", sc->sk_rev); 1750 device_printf(dev, "SK_EPROM0 = 0x%02x\n", skrs); 1751 device_printf(dev, "SRAM size = 0x%06x\n", sc->sk_ramsize); 1752 } 1753 1754 sc->sk_devs[SK_PORT_A] = device_add_child(dev, "sk", -1); 1755 if (sc->sk_devs[SK_PORT_A] == NULL) { 1756 device_printf(dev, "failed to add child for PORT_A\n"); 1757 error = ENXIO; 1758 goto fail; 1759 } 1760 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT); 1761 if (port == NULL) { 1762 device_printf(dev, "failed to allocate memory for " 1763 "ivars of PORT_A\n"); 1764 error = ENXIO; 1765 goto fail; 1766 } 1767 *port = SK_PORT_A; 1768 device_set_ivars(sc->sk_devs[SK_PORT_A], port); 1769 1770 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1771 sc->sk_devs[SK_PORT_B] = device_add_child(dev, "sk", -1); 1772 if (sc->sk_devs[SK_PORT_B] == NULL) { 1773 device_printf(dev, "failed to add child for PORT_B\n"); 1774 error = ENXIO; 1775 goto fail; 1776 } 1777 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT); 1778 if (port == NULL) { 1779 device_printf(dev, "failed to allocate memory for " 1780 "ivars of PORT_B\n"); 1781 error = ENXIO; 1782 goto fail; 1783 } 1784 *port = SK_PORT_B; 1785 device_set_ivars(sc->sk_devs[SK_PORT_B], port); 1786 } 1787 1788 /* Turn on the 'driver is loaded' LED. */ 1789 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1790 1791 error = bus_generic_attach(dev); 1792 if (error) { 1793 device_printf(dev, "failed to attach port(s)\n"); 1794 goto fail; 1795 } 1796 1797 /* Hook interrupt last to avoid having to lock softc */ 1798 error = bus_setup_intr(dev, sc->sk_res[1], INTR_TYPE_NET|INTR_MPSAFE, 1799 NULL, sk_intr, sc, &sc->sk_intrhand); 1800 1801 if (error) { 1802 device_printf(dev, "couldn't set up irq\n"); 1803 goto fail; 1804 } 1805 1806 fail: 1807 if (error) 1808 skc_detach(dev); 1809 1810 return(error); 1811 } 1812 1813 /* 1814 * Shutdown hardware and free up resources. This can be called any 1815 * time after the mutex has been initialized. It is called in both 1816 * the error case in attach and the normal detach case so it needs 1817 * to be careful about only freeing resources that have actually been 1818 * allocated. 1819 */ 1820 static int 1821 sk_detach(dev) 1822 device_t dev; 1823 { 1824 struct sk_if_softc *sc_if; 1825 struct ifnet *ifp; 1826 1827 sc_if = device_get_softc(dev); 1828 KASSERT(mtx_initialized(&sc_if->sk_softc->sk_mtx), 1829 ("sk mutex not initialized in sk_detach")); 1830 SK_IF_LOCK(sc_if); 1831 1832 ifp = sc_if->sk_ifp; 1833 /* These should only be active if attach_xmac succeeded */ 1834 if (device_is_attached(dev)) { 1835 sk_stop(sc_if); 1836 /* Can't hold locks while calling detach */ 1837 SK_IF_UNLOCK(sc_if); 1838 callout_drain(&sc_if->sk_tick_ch); 1839 callout_drain(&sc_if->sk_watchdog_ch); 1840 ether_ifdetach(ifp); 1841 SK_IF_LOCK(sc_if); 1842 } 1843 /* 1844 * We're generally called from skc_detach() which is using 1845 * device_delete_child() to get to here. It's already trashed 1846 * miibus for us, so don't do it here or we'll panic. 1847 */ 1848 /* 1849 if (sc_if->sk_miibus != NULL) 1850 device_delete_child(dev, sc_if->sk_miibus); 1851 */ 1852 bus_generic_detach(dev); 1853 sk_dma_jumbo_free(sc_if); 1854 sk_dma_free(sc_if); 1855 SK_IF_UNLOCK(sc_if); 1856 if (ifp) 1857 if_free(ifp); 1858 1859 return(0); 1860 } 1861 1862 static int 1863 skc_detach(dev) 1864 device_t dev; 1865 { 1866 struct sk_softc *sc; 1867 1868 sc = device_get_softc(dev); 1869 KASSERT(mtx_initialized(&sc->sk_mtx), ("sk mutex not initialized")); 1870 1871 if (device_is_alive(dev)) { 1872 if (sc->sk_devs[SK_PORT_A] != NULL) { 1873 free(device_get_ivars(sc->sk_devs[SK_PORT_A]), M_DEVBUF); 1874 device_delete_child(dev, sc->sk_devs[SK_PORT_A]); 1875 } 1876 if (sc->sk_devs[SK_PORT_B] != NULL) { 1877 free(device_get_ivars(sc->sk_devs[SK_PORT_B]), M_DEVBUF); 1878 device_delete_child(dev, sc->sk_devs[SK_PORT_B]); 1879 } 1880 bus_generic_detach(dev); 1881 } 1882 1883 if (sc->sk_intrhand) 1884 bus_teardown_intr(dev, sc->sk_res[1], sc->sk_intrhand); 1885 bus_release_resources(dev, sc->sk_res_spec, sc->sk_res); 1886 1887 mtx_destroy(&sc->sk_mii_mtx); 1888 mtx_destroy(&sc->sk_mtx); 1889 1890 return(0); 1891 } 1892 1893 static bus_dma_tag_t 1894 skc_get_dma_tag(device_t bus, device_t child __unused) 1895 { 1896 1897 return (bus_get_dma_tag(bus)); 1898 } 1899 1900 struct sk_dmamap_arg { 1901 bus_addr_t sk_busaddr; 1902 }; 1903 1904 static void 1905 sk_dmamap_cb(arg, segs, nseg, error) 1906 void *arg; 1907 bus_dma_segment_t *segs; 1908 int nseg; 1909 int error; 1910 { 1911 struct sk_dmamap_arg *ctx; 1912 1913 if (error != 0) 1914 return; 1915 1916 ctx = arg; 1917 ctx->sk_busaddr = segs[0].ds_addr; 1918 } 1919 1920 /* 1921 * Allocate jumbo buffer storage. The SysKonnect adapters support 1922 * "jumbograms" (9K frames), although SysKonnect doesn't currently 1923 * use them in their drivers. In order for us to use them, we need 1924 * large 9K receive buffers, however standard mbuf clusters are only 1925 * 2048 bytes in size. Consequently, we need to allocate and manage 1926 * our own jumbo buffer pool. Fortunately, this does not require an 1927 * excessive amount of additional code. 1928 */ 1929 static int 1930 sk_dma_alloc(sc_if) 1931 struct sk_if_softc *sc_if; 1932 { 1933 struct sk_dmamap_arg ctx; 1934 struct sk_txdesc *txd; 1935 struct sk_rxdesc *rxd; 1936 int error, i; 1937 1938 /* create parent tag */ 1939 /* 1940 * XXX 1941 * This driver should use BUS_SPACE_MAXADDR for lowaddr argument 1942 * in bus_dma_tag_create(9) as the NIC would support DAC mode. 1943 * However bz@ reported that it does not work on amd64 with > 4GB 1944 * RAM. Until we have more clues of the breakage, disable DAC mode 1945 * by limiting DMA address to be in 32bit address space. 1946 */ 1947 error = bus_dma_tag_create( 1948 bus_get_dma_tag(sc_if->sk_if_dev),/* parent */ 1949 1, 0, /* algnmnt, boundary */ 1950 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1951 BUS_SPACE_MAXADDR, /* highaddr */ 1952 NULL, NULL, /* filter, filterarg */ 1953 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1954 0, /* nsegments */ 1955 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1956 0, /* flags */ 1957 NULL, NULL, /* lockfunc, lockarg */ 1958 &sc_if->sk_cdata.sk_parent_tag); 1959 if (error != 0) { 1960 device_printf(sc_if->sk_if_dev, 1961 "failed to create parent DMA tag\n"); 1962 goto fail; 1963 } 1964 1965 /* create tag for Tx ring */ 1966 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */ 1967 SK_RING_ALIGN, 0, /* algnmnt, boundary */ 1968 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1969 BUS_SPACE_MAXADDR, /* highaddr */ 1970 NULL, NULL, /* filter, filterarg */ 1971 SK_TX_RING_SZ, /* maxsize */ 1972 1, /* nsegments */ 1973 SK_TX_RING_SZ, /* maxsegsize */ 1974 0, /* flags */ 1975 NULL, NULL, /* lockfunc, lockarg */ 1976 &sc_if->sk_cdata.sk_tx_ring_tag); 1977 if (error != 0) { 1978 device_printf(sc_if->sk_if_dev, 1979 "failed to allocate Tx ring DMA tag\n"); 1980 goto fail; 1981 } 1982 1983 /* create tag for Rx ring */ 1984 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */ 1985 SK_RING_ALIGN, 0, /* algnmnt, boundary */ 1986 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1987 BUS_SPACE_MAXADDR, /* highaddr */ 1988 NULL, NULL, /* filter, filterarg */ 1989 SK_RX_RING_SZ, /* maxsize */ 1990 1, /* nsegments */ 1991 SK_RX_RING_SZ, /* maxsegsize */ 1992 0, /* flags */ 1993 NULL, NULL, /* lockfunc, lockarg */ 1994 &sc_if->sk_cdata.sk_rx_ring_tag); 1995 if (error != 0) { 1996 device_printf(sc_if->sk_if_dev, 1997 "failed to allocate Rx ring DMA tag\n"); 1998 goto fail; 1999 } 2000 2001 /* create tag for Tx buffers */ 2002 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */ 2003 1, 0, /* algnmnt, boundary */ 2004 BUS_SPACE_MAXADDR, /* lowaddr */ 2005 BUS_SPACE_MAXADDR, /* highaddr */ 2006 NULL, NULL, /* filter, filterarg */ 2007 MCLBYTES * SK_MAXTXSEGS, /* maxsize */ 2008 SK_MAXTXSEGS, /* nsegments */ 2009 MCLBYTES, /* maxsegsize */ 2010 0, /* flags */ 2011 NULL, NULL, /* lockfunc, lockarg */ 2012 &sc_if->sk_cdata.sk_tx_tag); 2013 if (error != 0) { 2014 device_printf(sc_if->sk_if_dev, 2015 "failed to allocate Tx DMA tag\n"); 2016 goto fail; 2017 } 2018 2019 /* create tag for Rx buffers */ 2020 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */ 2021 1, 0, /* algnmnt, boundary */ 2022 BUS_SPACE_MAXADDR, /* lowaddr */ 2023 BUS_SPACE_MAXADDR, /* highaddr */ 2024 NULL, NULL, /* filter, filterarg */ 2025 MCLBYTES, /* maxsize */ 2026 1, /* nsegments */ 2027 MCLBYTES, /* maxsegsize */ 2028 0, /* flags */ 2029 NULL, NULL, /* lockfunc, lockarg */ 2030 &sc_if->sk_cdata.sk_rx_tag); 2031 if (error != 0) { 2032 device_printf(sc_if->sk_if_dev, 2033 "failed to allocate Rx DMA tag\n"); 2034 goto fail; 2035 } 2036 2037 /* allocate DMA'able memory and load the DMA map for Tx ring */ 2038 error = bus_dmamem_alloc(sc_if->sk_cdata.sk_tx_ring_tag, 2039 (void **)&sc_if->sk_rdata.sk_tx_ring, BUS_DMA_NOWAIT | 2040 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->sk_cdata.sk_tx_ring_map); 2041 if (error != 0) { 2042 device_printf(sc_if->sk_if_dev, 2043 "failed to allocate DMA'able memory for Tx ring\n"); 2044 goto fail; 2045 } 2046 2047 ctx.sk_busaddr = 0; 2048 error = bus_dmamap_load(sc_if->sk_cdata.sk_tx_ring_tag, 2049 sc_if->sk_cdata.sk_tx_ring_map, sc_if->sk_rdata.sk_tx_ring, 2050 SK_TX_RING_SZ, sk_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 2051 if (error != 0) { 2052 device_printf(sc_if->sk_if_dev, 2053 "failed to load DMA'able memory for Tx ring\n"); 2054 goto fail; 2055 } 2056 sc_if->sk_rdata.sk_tx_ring_paddr = ctx.sk_busaddr; 2057 2058 /* allocate DMA'able memory and load the DMA map for Rx ring */ 2059 error = bus_dmamem_alloc(sc_if->sk_cdata.sk_rx_ring_tag, 2060 (void **)&sc_if->sk_rdata.sk_rx_ring, BUS_DMA_NOWAIT | 2061 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->sk_cdata.sk_rx_ring_map); 2062 if (error != 0) { 2063 device_printf(sc_if->sk_if_dev, 2064 "failed to allocate DMA'able memory for Rx ring\n"); 2065 goto fail; 2066 } 2067 2068 ctx.sk_busaddr = 0; 2069 error = bus_dmamap_load(sc_if->sk_cdata.sk_rx_ring_tag, 2070 sc_if->sk_cdata.sk_rx_ring_map, sc_if->sk_rdata.sk_rx_ring, 2071 SK_RX_RING_SZ, sk_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 2072 if (error != 0) { 2073 device_printf(sc_if->sk_if_dev, 2074 "failed to load DMA'able memory for Rx ring\n"); 2075 goto fail; 2076 } 2077 sc_if->sk_rdata.sk_rx_ring_paddr = ctx.sk_busaddr; 2078 2079 /* create DMA maps for Tx buffers */ 2080 for (i = 0; i < SK_TX_RING_CNT; i++) { 2081 txd = &sc_if->sk_cdata.sk_txdesc[i]; 2082 txd->tx_m = NULL; 2083 txd->tx_dmamap = NULL; 2084 error = bus_dmamap_create(sc_if->sk_cdata.sk_tx_tag, 0, 2085 &txd->tx_dmamap); 2086 if (error != 0) { 2087 device_printf(sc_if->sk_if_dev, 2088 "failed to create Tx dmamap\n"); 2089 goto fail; 2090 } 2091 } 2092 2093 /* create DMA maps for Rx buffers */ 2094 if ((error = bus_dmamap_create(sc_if->sk_cdata.sk_rx_tag, 0, 2095 &sc_if->sk_cdata.sk_rx_sparemap)) != 0) { 2096 device_printf(sc_if->sk_if_dev, 2097 "failed to create spare Rx dmamap\n"); 2098 goto fail; 2099 } 2100 for (i = 0; i < SK_RX_RING_CNT; i++) { 2101 rxd = &sc_if->sk_cdata.sk_rxdesc[i]; 2102 rxd->rx_m = NULL; 2103 rxd->rx_dmamap = NULL; 2104 error = bus_dmamap_create(sc_if->sk_cdata.sk_rx_tag, 0, 2105 &rxd->rx_dmamap); 2106 if (error != 0) { 2107 device_printf(sc_if->sk_if_dev, 2108 "failed to create Rx dmamap\n"); 2109 goto fail; 2110 } 2111 } 2112 2113 fail: 2114 return (error); 2115 } 2116 2117 static int 2118 sk_dma_jumbo_alloc(sc_if) 2119 struct sk_if_softc *sc_if; 2120 { 2121 struct sk_dmamap_arg ctx; 2122 struct sk_rxdesc *jrxd; 2123 int error, i; 2124 2125 if (jumbo_disable != 0) { 2126 device_printf(sc_if->sk_if_dev, "disabling jumbo frame support\n"); 2127 sc_if->sk_jumbo_disable = 1; 2128 return (0); 2129 } 2130 /* create tag for jumbo Rx ring */ 2131 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */ 2132 SK_RING_ALIGN, 0, /* algnmnt, boundary */ 2133 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 2134 BUS_SPACE_MAXADDR, /* highaddr */ 2135 NULL, NULL, /* filter, filterarg */ 2136 SK_JUMBO_RX_RING_SZ, /* maxsize */ 2137 1, /* nsegments */ 2138 SK_JUMBO_RX_RING_SZ, /* maxsegsize */ 2139 0, /* flags */ 2140 NULL, NULL, /* lockfunc, lockarg */ 2141 &sc_if->sk_cdata.sk_jumbo_rx_ring_tag); 2142 if (error != 0) { 2143 device_printf(sc_if->sk_if_dev, 2144 "failed to allocate jumbo Rx ring DMA tag\n"); 2145 goto jumbo_fail; 2146 } 2147 2148 /* create tag for jumbo Rx buffers */ 2149 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */ 2150 1, 0, /* algnmnt, boundary */ 2151 BUS_SPACE_MAXADDR, /* lowaddr */ 2152 BUS_SPACE_MAXADDR, /* highaddr */ 2153 NULL, NULL, /* filter, filterarg */ 2154 MJUM9BYTES, /* maxsize */ 2155 1, /* nsegments */ 2156 MJUM9BYTES, /* maxsegsize */ 2157 0, /* flags */ 2158 NULL, NULL, /* lockfunc, lockarg */ 2159 &sc_if->sk_cdata.sk_jumbo_rx_tag); 2160 if (error != 0) { 2161 device_printf(sc_if->sk_if_dev, 2162 "failed to allocate jumbo Rx DMA tag\n"); 2163 goto jumbo_fail; 2164 } 2165 2166 /* allocate DMA'able memory and load the DMA map for jumbo Rx ring */ 2167 error = bus_dmamem_alloc(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 2168 (void **)&sc_if->sk_rdata.sk_jumbo_rx_ring, BUS_DMA_NOWAIT | 2169 BUS_DMA_COHERENT | BUS_DMA_ZERO, 2170 &sc_if->sk_cdata.sk_jumbo_rx_ring_map); 2171 if (error != 0) { 2172 device_printf(sc_if->sk_if_dev, 2173 "failed to allocate DMA'able memory for jumbo Rx ring\n"); 2174 goto jumbo_fail; 2175 } 2176 2177 ctx.sk_busaddr = 0; 2178 error = bus_dmamap_load(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 2179 sc_if->sk_cdata.sk_jumbo_rx_ring_map, 2180 sc_if->sk_rdata.sk_jumbo_rx_ring, SK_JUMBO_RX_RING_SZ, sk_dmamap_cb, 2181 &ctx, BUS_DMA_NOWAIT); 2182 if (error != 0) { 2183 device_printf(sc_if->sk_if_dev, 2184 "failed to load DMA'able memory for jumbo Rx ring\n"); 2185 goto jumbo_fail; 2186 } 2187 sc_if->sk_rdata.sk_jumbo_rx_ring_paddr = ctx.sk_busaddr; 2188 2189 /* create DMA maps for jumbo Rx buffers */ 2190 if ((error = bus_dmamap_create(sc_if->sk_cdata.sk_jumbo_rx_tag, 0, 2191 &sc_if->sk_cdata.sk_jumbo_rx_sparemap)) != 0) { 2192 device_printf(sc_if->sk_if_dev, 2193 "failed to create spare jumbo Rx dmamap\n"); 2194 goto jumbo_fail; 2195 } 2196 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) { 2197 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i]; 2198 jrxd->rx_m = NULL; 2199 jrxd->rx_dmamap = NULL; 2200 error = bus_dmamap_create(sc_if->sk_cdata.sk_jumbo_rx_tag, 0, 2201 &jrxd->rx_dmamap); 2202 if (error != 0) { 2203 device_printf(sc_if->sk_if_dev, 2204 "failed to create jumbo Rx dmamap\n"); 2205 goto jumbo_fail; 2206 } 2207 } 2208 2209 return (0); 2210 2211 jumbo_fail: 2212 sk_dma_jumbo_free(sc_if); 2213 device_printf(sc_if->sk_if_dev, "disabling jumbo frame support due to " 2214 "resource shortage\n"); 2215 sc_if->sk_jumbo_disable = 1; 2216 return (0); 2217 } 2218 2219 static void 2220 sk_dma_free(sc_if) 2221 struct sk_if_softc *sc_if; 2222 { 2223 struct sk_txdesc *txd; 2224 struct sk_rxdesc *rxd; 2225 int i; 2226 2227 /* Tx ring */ 2228 if (sc_if->sk_cdata.sk_tx_ring_tag) { 2229 if (sc_if->sk_rdata.sk_tx_ring_paddr) 2230 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_ring_tag, 2231 sc_if->sk_cdata.sk_tx_ring_map); 2232 if (sc_if->sk_rdata.sk_tx_ring) 2233 bus_dmamem_free(sc_if->sk_cdata.sk_tx_ring_tag, 2234 sc_if->sk_rdata.sk_tx_ring, 2235 sc_if->sk_cdata.sk_tx_ring_map); 2236 sc_if->sk_rdata.sk_tx_ring = NULL; 2237 sc_if->sk_rdata.sk_tx_ring_paddr = 0; 2238 bus_dma_tag_destroy(sc_if->sk_cdata.sk_tx_ring_tag); 2239 sc_if->sk_cdata.sk_tx_ring_tag = NULL; 2240 } 2241 /* Rx ring */ 2242 if (sc_if->sk_cdata.sk_rx_ring_tag) { 2243 if (sc_if->sk_rdata.sk_rx_ring_paddr) 2244 bus_dmamap_unload(sc_if->sk_cdata.sk_rx_ring_tag, 2245 sc_if->sk_cdata.sk_rx_ring_map); 2246 if (sc_if->sk_rdata.sk_rx_ring) 2247 bus_dmamem_free(sc_if->sk_cdata.sk_rx_ring_tag, 2248 sc_if->sk_rdata.sk_rx_ring, 2249 sc_if->sk_cdata.sk_rx_ring_map); 2250 sc_if->sk_rdata.sk_rx_ring = NULL; 2251 sc_if->sk_rdata.sk_rx_ring_paddr = 0; 2252 bus_dma_tag_destroy(sc_if->sk_cdata.sk_rx_ring_tag); 2253 sc_if->sk_cdata.sk_rx_ring_tag = NULL; 2254 } 2255 /* Tx buffers */ 2256 if (sc_if->sk_cdata.sk_tx_tag) { 2257 for (i = 0; i < SK_TX_RING_CNT; i++) { 2258 txd = &sc_if->sk_cdata.sk_txdesc[i]; 2259 if (txd->tx_dmamap) { 2260 bus_dmamap_destroy(sc_if->sk_cdata.sk_tx_tag, 2261 txd->tx_dmamap); 2262 txd->tx_dmamap = NULL; 2263 } 2264 } 2265 bus_dma_tag_destroy(sc_if->sk_cdata.sk_tx_tag); 2266 sc_if->sk_cdata.sk_tx_tag = NULL; 2267 } 2268 /* Rx buffers */ 2269 if (sc_if->sk_cdata.sk_rx_tag) { 2270 for (i = 0; i < SK_RX_RING_CNT; i++) { 2271 rxd = &sc_if->sk_cdata.sk_rxdesc[i]; 2272 if (rxd->rx_dmamap) { 2273 bus_dmamap_destroy(sc_if->sk_cdata.sk_rx_tag, 2274 rxd->rx_dmamap); 2275 rxd->rx_dmamap = NULL; 2276 } 2277 } 2278 if (sc_if->sk_cdata.sk_rx_sparemap) { 2279 bus_dmamap_destroy(sc_if->sk_cdata.sk_rx_tag, 2280 sc_if->sk_cdata.sk_rx_sparemap); 2281 sc_if->sk_cdata.sk_rx_sparemap = NULL; 2282 } 2283 bus_dma_tag_destroy(sc_if->sk_cdata.sk_rx_tag); 2284 sc_if->sk_cdata.sk_rx_tag = NULL; 2285 } 2286 2287 if (sc_if->sk_cdata.sk_parent_tag) { 2288 bus_dma_tag_destroy(sc_if->sk_cdata.sk_parent_tag); 2289 sc_if->sk_cdata.sk_parent_tag = NULL; 2290 } 2291 } 2292 2293 static void 2294 sk_dma_jumbo_free(sc_if) 2295 struct sk_if_softc *sc_if; 2296 { 2297 struct sk_rxdesc *jrxd; 2298 int i; 2299 2300 /* jumbo Rx ring */ 2301 if (sc_if->sk_cdata.sk_jumbo_rx_ring_tag) { 2302 if (sc_if->sk_rdata.sk_jumbo_rx_ring_paddr) 2303 bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 2304 sc_if->sk_cdata.sk_jumbo_rx_ring_map); 2305 if (sc_if->sk_rdata.sk_jumbo_rx_ring) 2306 bus_dmamem_free(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 2307 sc_if->sk_rdata.sk_jumbo_rx_ring, 2308 sc_if->sk_cdata.sk_jumbo_rx_ring_map); 2309 sc_if->sk_rdata.sk_jumbo_rx_ring = NULL; 2310 sc_if->sk_rdata.sk_jumbo_rx_ring_paddr = 0; 2311 bus_dma_tag_destroy(sc_if->sk_cdata.sk_jumbo_rx_ring_tag); 2312 sc_if->sk_cdata.sk_jumbo_rx_ring_tag = NULL; 2313 } 2314 2315 /* jumbo Rx buffers */ 2316 if (sc_if->sk_cdata.sk_jumbo_rx_tag) { 2317 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) { 2318 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i]; 2319 if (jrxd->rx_dmamap) { 2320 bus_dmamap_destroy( 2321 sc_if->sk_cdata.sk_jumbo_rx_tag, 2322 jrxd->rx_dmamap); 2323 jrxd->rx_dmamap = NULL; 2324 } 2325 } 2326 if (sc_if->sk_cdata.sk_jumbo_rx_sparemap) { 2327 bus_dmamap_destroy(sc_if->sk_cdata.sk_jumbo_rx_tag, 2328 sc_if->sk_cdata.sk_jumbo_rx_sparemap); 2329 sc_if->sk_cdata.sk_jumbo_rx_sparemap = NULL; 2330 } 2331 bus_dma_tag_destroy(sc_if->sk_cdata.sk_jumbo_rx_tag); 2332 sc_if->sk_cdata.sk_jumbo_rx_tag = NULL; 2333 } 2334 } 2335 2336 static void 2337 sk_txcksum(ifp, m, f) 2338 struct ifnet *ifp; 2339 struct mbuf *m; 2340 struct sk_tx_desc *f; 2341 { 2342 struct ip *ip; 2343 u_int16_t offset; 2344 u_int8_t *p; 2345 2346 offset = sizeof(struct ip) + ETHER_HDR_LEN; 2347 for(; m && m->m_len == 0; m = m->m_next) 2348 ; 2349 if (m == NULL || m->m_len < ETHER_HDR_LEN) { 2350 if_printf(ifp, "%s: m_len < ETHER_HDR_LEN\n", __func__); 2351 /* checksum may be corrupted */ 2352 goto sendit; 2353 } 2354 if (m->m_len < ETHER_HDR_LEN + sizeof(u_int32_t)) { 2355 if (m->m_len != ETHER_HDR_LEN) { 2356 if_printf(ifp, "%s: m_len != ETHER_HDR_LEN\n", 2357 __func__); 2358 /* checksum may be corrupted */ 2359 goto sendit; 2360 } 2361 for(m = m->m_next; m && m->m_len == 0; m = m->m_next) 2362 ; 2363 if (m == NULL) { 2364 offset = sizeof(struct ip) + ETHER_HDR_LEN; 2365 /* checksum may be corrupted */ 2366 goto sendit; 2367 } 2368 ip = mtod(m, struct ip *); 2369 } else { 2370 p = mtod(m, u_int8_t *); 2371 p += ETHER_HDR_LEN; 2372 ip = (struct ip *)p; 2373 } 2374 offset = (ip->ip_hl << 2) + ETHER_HDR_LEN; 2375 2376 sendit: 2377 f->sk_csum_startval = 0; 2378 f->sk_csum_start = htole32(((offset + m->m_pkthdr.csum_data) & 0xffff) | 2379 (offset << 16)); 2380 } 2381 2382 static int 2383 sk_encap(sc_if, m_head) 2384 struct sk_if_softc *sc_if; 2385 struct mbuf **m_head; 2386 { 2387 struct sk_txdesc *txd; 2388 struct sk_tx_desc *f = NULL; 2389 struct mbuf *m; 2390 bus_dma_segment_t txsegs[SK_MAXTXSEGS]; 2391 u_int32_t cflags, frag, si, sk_ctl; 2392 int error, i, nseg; 2393 2394 SK_IF_LOCK_ASSERT(sc_if); 2395 2396 if ((txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txfreeq)) == NULL) 2397 return (ENOBUFS); 2398 2399 error = bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_tx_tag, 2400 txd->tx_dmamap, *m_head, txsegs, &nseg, 0); 2401 if (error == EFBIG) { 2402 m = m_defrag(*m_head, M_NOWAIT); 2403 if (m == NULL) { 2404 m_freem(*m_head); 2405 *m_head = NULL; 2406 return (ENOMEM); 2407 } 2408 *m_head = m; 2409 error = bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_tx_tag, 2410 txd->tx_dmamap, *m_head, txsegs, &nseg, 0); 2411 if (error != 0) { 2412 m_freem(*m_head); 2413 *m_head = NULL; 2414 return (error); 2415 } 2416 } else if (error != 0) 2417 return (error); 2418 if (nseg == 0) { 2419 m_freem(*m_head); 2420 *m_head = NULL; 2421 return (EIO); 2422 } 2423 if (sc_if->sk_cdata.sk_tx_cnt + nseg >= SK_TX_RING_CNT) { 2424 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap); 2425 return (ENOBUFS); 2426 } 2427 2428 m = *m_head; 2429 if ((m->m_pkthdr.csum_flags & sc_if->sk_ifp->if_hwassist) != 0) 2430 cflags = SK_OPCODE_CSUM; 2431 else 2432 cflags = SK_OPCODE_DEFAULT; 2433 si = frag = sc_if->sk_cdata.sk_tx_prod; 2434 for (i = 0; i < nseg; i++) { 2435 f = &sc_if->sk_rdata.sk_tx_ring[frag]; 2436 f->sk_data_lo = htole32(SK_ADDR_LO(txsegs[i].ds_addr)); 2437 f->sk_data_hi = htole32(SK_ADDR_HI(txsegs[i].ds_addr)); 2438 sk_ctl = txsegs[i].ds_len | cflags; 2439 if (i == 0) { 2440 if (cflags == SK_OPCODE_CSUM) 2441 sk_txcksum(sc_if->sk_ifp, m, f); 2442 sk_ctl |= SK_TXCTL_FIRSTFRAG; 2443 } else 2444 sk_ctl |= SK_TXCTL_OWN; 2445 f->sk_ctl = htole32(sk_ctl); 2446 sc_if->sk_cdata.sk_tx_cnt++; 2447 SK_INC(frag, SK_TX_RING_CNT); 2448 } 2449 sc_if->sk_cdata.sk_tx_prod = frag; 2450 2451 /* set EOF on the last desciptor */ 2452 frag = (frag + SK_TX_RING_CNT - 1) % SK_TX_RING_CNT; 2453 f = &sc_if->sk_rdata.sk_tx_ring[frag]; 2454 f->sk_ctl |= htole32(SK_TXCTL_LASTFRAG | SK_TXCTL_EOF_INTR); 2455 2456 /* turn the first descriptor ownership to NIC */ 2457 f = &sc_if->sk_rdata.sk_tx_ring[si]; 2458 f->sk_ctl |= htole32(SK_TXCTL_OWN); 2459 2460 STAILQ_REMOVE_HEAD(&sc_if->sk_cdata.sk_txfreeq, tx_q); 2461 STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txbusyq, txd, tx_q); 2462 txd->tx_m = m; 2463 2464 /* sync descriptors */ 2465 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap, 2466 BUS_DMASYNC_PREWRITE); 2467 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag, 2468 sc_if->sk_cdata.sk_tx_ring_map, 2469 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2470 2471 return (0); 2472 } 2473 2474 static void 2475 sk_start(ifp) 2476 struct ifnet *ifp; 2477 { 2478 struct sk_if_softc *sc_if; 2479 2480 sc_if = ifp->if_softc; 2481 2482 SK_IF_LOCK(sc_if); 2483 sk_start_locked(ifp); 2484 SK_IF_UNLOCK(sc_if); 2485 2486 return; 2487 } 2488 2489 static void 2490 sk_start_locked(ifp) 2491 struct ifnet *ifp; 2492 { 2493 struct sk_softc *sc; 2494 struct sk_if_softc *sc_if; 2495 struct mbuf *m_head; 2496 int enq; 2497 2498 sc_if = ifp->if_softc; 2499 sc = sc_if->sk_softc; 2500 2501 SK_IF_LOCK_ASSERT(sc_if); 2502 2503 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2504 sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 1; ) { 2505 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2506 if (m_head == NULL) 2507 break; 2508 2509 /* 2510 * Pack the data into the transmit ring. If we 2511 * don't have room, set the OACTIVE flag and wait 2512 * for the NIC to drain the ring. 2513 */ 2514 if (sk_encap(sc_if, &m_head)) { 2515 if (m_head == NULL) 2516 break; 2517 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2518 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2519 break; 2520 } 2521 2522 enq++; 2523 /* 2524 * If there's a BPF listener, bounce a copy of this frame 2525 * to him. 2526 */ 2527 BPF_MTAP(ifp, m_head); 2528 } 2529 2530 if (enq > 0) { 2531 /* Transmit */ 2532 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 2533 2534 /* Set a timeout in case the chip goes out to lunch. */ 2535 sc_if->sk_watchdog_timer = 5; 2536 } 2537 } 2538 2539 2540 static void 2541 sk_watchdog(arg) 2542 void *arg; 2543 { 2544 struct sk_if_softc *sc_if; 2545 struct ifnet *ifp; 2546 2547 ifp = arg; 2548 sc_if = ifp->if_softc; 2549 2550 SK_IF_LOCK_ASSERT(sc_if); 2551 2552 if (sc_if->sk_watchdog_timer == 0 || --sc_if->sk_watchdog_timer) 2553 goto done; 2554 2555 /* 2556 * Reclaim first as there is a possibility of losing Tx completion 2557 * interrupts. 2558 */ 2559 sk_txeof(sc_if); 2560 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 2561 if_printf(sc_if->sk_ifp, "watchdog timeout\n"); 2562 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2563 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2564 sk_init_locked(sc_if); 2565 } 2566 2567 done: 2568 callout_reset(&sc_if->sk_watchdog_ch, hz, sk_watchdog, ifp); 2569 2570 return; 2571 } 2572 2573 static int 2574 skc_shutdown(dev) 2575 device_t dev; 2576 { 2577 struct sk_softc *sc; 2578 2579 sc = device_get_softc(dev); 2580 SK_LOCK(sc); 2581 2582 /* Turn off the 'driver is loaded' LED. */ 2583 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 2584 2585 /* 2586 * Reset the GEnesis controller. Doing this should also 2587 * assert the resets on the attached XMAC(s). 2588 */ 2589 sk_reset(sc); 2590 SK_UNLOCK(sc); 2591 2592 return (0); 2593 } 2594 2595 static int 2596 skc_suspend(dev) 2597 device_t dev; 2598 { 2599 struct sk_softc *sc; 2600 struct sk_if_softc *sc_if0, *sc_if1; 2601 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2602 2603 sc = device_get_softc(dev); 2604 2605 SK_LOCK(sc); 2606 2607 sc_if0 = sc->sk_if[SK_PORT_A]; 2608 sc_if1 = sc->sk_if[SK_PORT_B]; 2609 if (sc_if0 != NULL) 2610 ifp0 = sc_if0->sk_ifp; 2611 if (sc_if1 != NULL) 2612 ifp1 = sc_if1->sk_ifp; 2613 if (ifp0 != NULL) 2614 sk_stop(sc_if0); 2615 if (ifp1 != NULL) 2616 sk_stop(sc_if1); 2617 sc->sk_suspended = 1; 2618 2619 SK_UNLOCK(sc); 2620 2621 return (0); 2622 } 2623 2624 static int 2625 skc_resume(dev) 2626 device_t dev; 2627 { 2628 struct sk_softc *sc; 2629 struct sk_if_softc *sc_if0, *sc_if1; 2630 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2631 2632 sc = device_get_softc(dev); 2633 2634 SK_LOCK(sc); 2635 2636 sc_if0 = sc->sk_if[SK_PORT_A]; 2637 sc_if1 = sc->sk_if[SK_PORT_B]; 2638 if (sc_if0 != NULL) 2639 ifp0 = sc_if0->sk_ifp; 2640 if (sc_if1 != NULL) 2641 ifp1 = sc_if1->sk_ifp; 2642 if (ifp0 != NULL && ifp0->if_flags & IFF_UP) 2643 sk_init_locked(sc_if0); 2644 if (ifp1 != NULL && ifp1->if_flags & IFF_UP) 2645 sk_init_locked(sc_if1); 2646 sc->sk_suspended = 0; 2647 2648 SK_UNLOCK(sc); 2649 2650 return (0); 2651 } 2652 2653 /* 2654 * According to the data sheet from SK-NET GENESIS the hardware can compute 2655 * two Rx checksums at the same time(Each checksum start position is 2656 * programmed in Rx descriptors). However it seems that TCP/UDP checksum 2657 * does not work at least on my Yukon hardware. I tried every possible ways 2658 * to get correct checksum value but couldn't get correct one. So TCP/UDP 2659 * checksum offload was disabled at the moment and only IP checksum offload 2660 * was enabled. 2661 * As nomral IP header size is 20 bytes I can't expect it would give an 2662 * increase in throughput. However it seems it doesn't hurt performance in 2663 * my testing. If there is a more detailed information for checksum secret 2664 * of the hardware in question please contact yongari@FreeBSD.org to add 2665 * TCP/UDP checksum offload support. 2666 */ 2667 static __inline void 2668 sk_rxcksum(ifp, m, csum) 2669 struct ifnet *ifp; 2670 struct mbuf *m; 2671 u_int32_t csum; 2672 { 2673 struct ether_header *eh; 2674 struct ip *ip; 2675 int32_t hlen, len, pktlen; 2676 u_int16_t csum1, csum2, ipcsum; 2677 2678 pktlen = m->m_pkthdr.len; 2679 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip)) 2680 return; 2681 eh = mtod(m, struct ether_header *); 2682 if (eh->ether_type != htons(ETHERTYPE_IP)) 2683 return; 2684 ip = (struct ip *)(eh + 1); 2685 if (ip->ip_v != IPVERSION) 2686 return; 2687 hlen = ip->ip_hl << 2; 2688 pktlen -= sizeof(struct ether_header); 2689 if (hlen < sizeof(struct ip)) 2690 return; 2691 if (ntohs(ip->ip_len) < hlen) 2692 return; 2693 if (ntohs(ip->ip_len) != pktlen) 2694 return; 2695 2696 csum1 = htons(csum & 0xffff); 2697 csum2 = htons((csum >> 16) & 0xffff); 2698 ipcsum = in_addword(csum1, ~csum2 & 0xffff); 2699 /* checksum fixup for IP options */ 2700 len = hlen - sizeof(struct ip); 2701 if (len > 0) { 2702 /* 2703 * If the second checksum value is correct we can compute IP 2704 * checksum with simple math. Unfortunately the second checksum 2705 * value is wrong so we can't verify the checksum from the 2706 * value(It seems there is some magic here to get correct 2707 * value). If the second checksum value is correct it also 2708 * means we can get TCP/UDP checksum) here. However, it still 2709 * needs pseudo header checksum calculation due to hardware 2710 * limitations. 2711 */ 2712 return; 2713 } 2714 m->m_pkthdr.csum_flags = CSUM_IP_CHECKED; 2715 if (ipcsum == 0xffff) 2716 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2717 } 2718 2719 static __inline int 2720 sk_rxvalid(sc, stat, len) 2721 struct sk_softc *sc; 2722 u_int32_t stat, len; 2723 { 2724 2725 if (sc->sk_type == SK_GENESIS) { 2726 if ((stat & XM_RXSTAT_ERRFRAME) == XM_RXSTAT_ERRFRAME || 2727 XM_RXSTAT_BYTES(stat) != len) 2728 return (0); 2729 } else { 2730 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR | 2731 YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | 2732 YU_RXSTAT_JABBER)) != 0 || 2733 (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK || 2734 YU_RXSTAT_BYTES(stat) != len) 2735 return (0); 2736 } 2737 2738 return (1); 2739 } 2740 2741 static void 2742 sk_rxeof(sc_if) 2743 struct sk_if_softc *sc_if; 2744 { 2745 struct sk_softc *sc; 2746 struct mbuf *m; 2747 struct ifnet *ifp; 2748 struct sk_rx_desc *cur_rx; 2749 struct sk_rxdesc *rxd; 2750 int cons, prog; 2751 u_int32_t csum, rxstat, sk_ctl; 2752 2753 sc = sc_if->sk_softc; 2754 ifp = sc_if->sk_ifp; 2755 2756 SK_IF_LOCK_ASSERT(sc_if); 2757 2758 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag, 2759 sc_if->sk_cdata.sk_rx_ring_map, BUS_DMASYNC_POSTREAD); 2760 2761 prog = 0; 2762 for (cons = sc_if->sk_cdata.sk_rx_cons; prog < SK_RX_RING_CNT; 2763 prog++, SK_INC(cons, SK_RX_RING_CNT)) { 2764 cur_rx = &sc_if->sk_rdata.sk_rx_ring[cons]; 2765 sk_ctl = le32toh(cur_rx->sk_ctl); 2766 if ((sk_ctl & SK_RXCTL_OWN) != 0) 2767 break; 2768 rxd = &sc_if->sk_cdata.sk_rxdesc[cons]; 2769 rxstat = le32toh(cur_rx->sk_xmac_rxstat); 2770 2771 if ((sk_ctl & (SK_RXCTL_STATUS_VALID | SK_RXCTL_FIRSTFRAG | 2772 SK_RXCTL_LASTFRAG)) != (SK_RXCTL_STATUS_VALID | 2773 SK_RXCTL_FIRSTFRAG | SK_RXCTL_LASTFRAG) || 2774 SK_RXBYTES(sk_ctl) < SK_MIN_FRAMELEN || 2775 SK_RXBYTES(sk_ctl) > SK_MAX_FRAMELEN || 2776 sk_rxvalid(sc, rxstat, SK_RXBYTES(sk_ctl)) == 0) { 2777 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2778 sk_discard_rxbuf(sc_if, cons); 2779 continue; 2780 } 2781 2782 m = rxd->rx_m; 2783 csum = le32toh(cur_rx->sk_csum); 2784 if (sk_newbuf(sc_if, cons) != 0) { 2785 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2786 /* reuse old buffer */ 2787 sk_discard_rxbuf(sc_if, cons); 2788 continue; 2789 } 2790 m->m_pkthdr.rcvif = ifp; 2791 m->m_pkthdr.len = m->m_len = SK_RXBYTES(sk_ctl); 2792 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 2793 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 2794 sk_rxcksum(ifp, m, csum); 2795 SK_IF_UNLOCK(sc_if); 2796 (*ifp->if_input)(ifp, m); 2797 SK_IF_LOCK(sc_if); 2798 } 2799 2800 if (prog > 0) { 2801 sc_if->sk_cdata.sk_rx_cons = cons; 2802 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag, 2803 sc_if->sk_cdata.sk_rx_ring_map, 2804 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2805 } 2806 } 2807 2808 static void 2809 sk_jumbo_rxeof(sc_if) 2810 struct sk_if_softc *sc_if; 2811 { 2812 struct sk_softc *sc; 2813 struct mbuf *m; 2814 struct ifnet *ifp; 2815 struct sk_rx_desc *cur_rx; 2816 struct sk_rxdesc *jrxd; 2817 int cons, prog; 2818 u_int32_t csum, rxstat, sk_ctl; 2819 2820 sc = sc_if->sk_softc; 2821 ifp = sc_if->sk_ifp; 2822 2823 SK_IF_LOCK_ASSERT(sc_if); 2824 2825 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 2826 sc_if->sk_cdata.sk_jumbo_rx_ring_map, BUS_DMASYNC_POSTREAD); 2827 2828 prog = 0; 2829 for (cons = sc_if->sk_cdata.sk_jumbo_rx_cons; 2830 prog < SK_JUMBO_RX_RING_CNT; 2831 prog++, SK_INC(cons, SK_JUMBO_RX_RING_CNT)) { 2832 cur_rx = &sc_if->sk_rdata.sk_jumbo_rx_ring[cons]; 2833 sk_ctl = le32toh(cur_rx->sk_ctl); 2834 if ((sk_ctl & SK_RXCTL_OWN) != 0) 2835 break; 2836 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[cons]; 2837 rxstat = le32toh(cur_rx->sk_xmac_rxstat); 2838 2839 if ((sk_ctl & (SK_RXCTL_STATUS_VALID | SK_RXCTL_FIRSTFRAG | 2840 SK_RXCTL_LASTFRAG)) != (SK_RXCTL_STATUS_VALID | 2841 SK_RXCTL_FIRSTFRAG | SK_RXCTL_LASTFRAG) || 2842 SK_RXBYTES(sk_ctl) < SK_MIN_FRAMELEN || 2843 SK_RXBYTES(sk_ctl) > SK_JUMBO_FRAMELEN || 2844 sk_rxvalid(sc, rxstat, SK_RXBYTES(sk_ctl)) == 0) { 2845 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2846 sk_discard_jumbo_rxbuf(sc_if, cons); 2847 continue; 2848 } 2849 2850 m = jrxd->rx_m; 2851 csum = le32toh(cur_rx->sk_csum); 2852 if (sk_jumbo_newbuf(sc_if, cons) != 0) { 2853 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2854 /* reuse old buffer */ 2855 sk_discard_jumbo_rxbuf(sc_if, cons); 2856 continue; 2857 } 2858 m->m_pkthdr.rcvif = ifp; 2859 m->m_pkthdr.len = m->m_len = SK_RXBYTES(sk_ctl); 2860 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 2861 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 2862 sk_rxcksum(ifp, m, csum); 2863 SK_IF_UNLOCK(sc_if); 2864 (*ifp->if_input)(ifp, m); 2865 SK_IF_LOCK(sc_if); 2866 } 2867 2868 if (prog > 0) { 2869 sc_if->sk_cdata.sk_jumbo_rx_cons = cons; 2870 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag, 2871 sc_if->sk_cdata.sk_jumbo_rx_ring_map, 2872 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2873 } 2874 } 2875 2876 static void 2877 sk_txeof(sc_if) 2878 struct sk_if_softc *sc_if; 2879 { 2880 struct sk_txdesc *txd; 2881 struct sk_tx_desc *cur_tx; 2882 struct ifnet *ifp; 2883 u_int32_t idx, sk_ctl; 2884 2885 ifp = sc_if->sk_ifp; 2886 2887 txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txbusyq); 2888 if (txd == NULL) 2889 return; 2890 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag, 2891 sc_if->sk_cdata.sk_tx_ring_map, BUS_DMASYNC_POSTREAD); 2892 /* 2893 * Go through our tx ring and free mbufs for those 2894 * frames that have been sent. 2895 */ 2896 for (idx = sc_if->sk_cdata.sk_tx_cons;; SK_INC(idx, SK_TX_RING_CNT)) { 2897 if (sc_if->sk_cdata.sk_tx_cnt <= 0) 2898 break; 2899 cur_tx = &sc_if->sk_rdata.sk_tx_ring[idx]; 2900 sk_ctl = le32toh(cur_tx->sk_ctl); 2901 if (sk_ctl & SK_TXCTL_OWN) 2902 break; 2903 sc_if->sk_cdata.sk_tx_cnt--; 2904 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2905 if ((sk_ctl & SK_TXCTL_LASTFRAG) == 0) 2906 continue; 2907 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap, 2908 BUS_DMASYNC_POSTWRITE); 2909 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap); 2910 2911 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 2912 m_freem(txd->tx_m); 2913 txd->tx_m = NULL; 2914 STAILQ_REMOVE_HEAD(&sc_if->sk_cdata.sk_txbusyq, tx_q); 2915 STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txfreeq, txd, tx_q); 2916 txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txbusyq); 2917 } 2918 sc_if->sk_cdata.sk_tx_cons = idx; 2919 sc_if->sk_watchdog_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0; 2920 2921 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag, 2922 sc_if->sk_cdata.sk_tx_ring_map, 2923 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2924 } 2925 2926 static void 2927 sk_tick(xsc_if) 2928 void *xsc_if; 2929 { 2930 struct sk_if_softc *sc_if; 2931 struct mii_data *mii; 2932 struct ifnet *ifp; 2933 int i; 2934 2935 sc_if = xsc_if; 2936 ifp = sc_if->sk_ifp; 2937 mii = device_get_softc(sc_if->sk_miibus); 2938 2939 if (!(ifp->if_flags & IFF_UP)) 2940 return; 2941 2942 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2943 sk_intr_bcom(sc_if); 2944 return; 2945 } 2946 2947 /* 2948 * According to SysKonnect, the correct way to verify that 2949 * the link has come back up is to poll bit 0 of the GPIO 2950 * register three times. This pin has the signal from the 2951 * link_sync pin connected to it; if we read the same link 2952 * state 3 times in a row, we know the link is up. 2953 */ 2954 for (i = 0; i < 3; i++) { 2955 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 2956 break; 2957 } 2958 2959 if (i != 3) { 2960 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2961 return; 2962 } 2963 2964 /* Turn the GP0 interrupt back on. */ 2965 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2966 SK_XM_READ_2(sc_if, XM_ISR); 2967 mii_tick(mii); 2968 callout_stop(&sc_if->sk_tick_ch); 2969 } 2970 2971 static void 2972 sk_yukon_tick(xsc_if) 2973 void *xsc_if; 2974 { 2975 struct sk_if_softc *sc_if; 2976 struct mii_data *mii; 2977 2978 sc_if = xsc_if; 2979 mii = device_get_softc(sc_if->sk_miibus); 2980 2981 mii_tick(mii); 2982 callout_reset(&sc_if->sk_tick_ch, hz, sk_yukon_tick, sc_if); 2983 } 2984 2985 static void 2986 sk_intr_bcom(sc_if) 2987 struct sk_if_softc *sc_if; 2988 { 2989 struct mii_data *mii; 2990 struct ifnet *ifp; 2991 int status; 2992 mii = device_get_softc(sc_if->sk_miibus); 2993 ifp = sc_if->sk_ifp; 2994 2995 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2996 2997 /* 2998 * Read the PHY interrupt register to make sure 2999 * we clear any pending interrupts. 3000 */ 3001 status = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 3002 3003 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3004 sk_init_xmac(sc_if); 3005 return; 3006 } 3007 3008 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 3009 int lstat; 3010 lstat = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 3011 BRGPHY_MII_AUXSTS); 3012 3013 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 3014 mii_mediachg(mii); 3015 /* Turn off the link LED. */ 3016 SK_IF_WRITE_1(sc_if, 0, 3017 SK_LINKLED1_CTL, SK_LINKLED_OFF); 3018 sc_if->sk_link = 0; 3019 } else if (status & BRGPHY_ISR_LNK_CHG) { 3020 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 3021 BRGPHY_MII_IMR, 0xFF00); 3022 mii_tick(mii); 3023 sc_if->sk_link = 1; 3024 /* Turn on the link LED. */ 3025 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 3026 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 3027 SK_LINKLED_BLINK_OFF); 3028 } else { 3029 mii_tick(mii); 3030 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 3031 } 3032 } 3033 3034 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 3035 3036 return; 3037 } 3038 3039 static void 3040 sk_intr_xmac(sc_if) 3041 struct sk_if_softc *sc_if; 3042 { 3043 struct sk_softc *sc; 3044 u_int16_t status; 3045 3046 sc = sc_if->sk_softc; 3047 status = SK_XM_READ_2(sc_if, XM_ISR); 3048 3049 /* 3050 * Link has gone down. Start MII tick timeout to 3051 * watch for link resync. 3052 */ 3053 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 3054 if (status & XM_ISR_GP0_SET) { 3055 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 3056 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 3057 } 3058 3059 if (status & XM_ISR_AUTONEG_DONE) { 3060 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 3061 } 3062 } 3063 3064 if (status & XM_IMR_TX_UNDERRUN) 3065 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 3066 3067 if (status & XM_IMR_RX_OVERRUN) 3068 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 3069 3070 status = SK_XM_READ_2(sc_if, XM_ISR); 3071 3072 return; 3073 } 3074 3075 static void 3076 sk_intr_yukon(sc_if) 3077 struct sk_if_softc *sc_if; 3078 { 3079 u_int8_t status; 3080 3081 status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR); 3082 /* RX overrun */ 3083 if ((status & SK_GMAC_INT_RX_OVER) != 0) { 3084 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 3085 SK_RFCTL_RX_FIFO_OVER); 3086 } 3087 /* TX underrun */ 3088 if ((status & SK_GMAC_INT_TX_UNDER) != 0) { 3089 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, 3090 SK_TFCTL_TX_FIFO_UNDER); 3091 } 3092 } 3093 3094 static void 3095 sk_intr(xsc) 3096 void *xsc; 3097 { 3098 struct sk_softc *sc = xsc; 3099 struct sk_if_softc *sc_if0, *sc_if1; 3100 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 3101 u_int32_t status; 3102 3103 SK_LOCK(sc); 3104 3105 status = CSR_READ_4(sc, SK_ISSR); 3106 if (status == 0 || status == 0xffffffff || sc->sk_suspended) 3107 goto done_locked; 3108 3109 sc_if0 = sc->sk_if[SK_PORT_A]; 3110 sc_if1 = sc->sk_if[SK_PORT_B]; 3111 3112 if (sc_if0 != NULL) 3113 ifp0 = sc_if0->sk_ifp; 3114 if (sc_if1 != NULL) 3115 ifp1 = sc_if1->sk_ifp; 3116 3117 for (; (status &= sc->sk_intrmask) != 0;) { 3118 /* Handle receive interrupts first. */ 3119 if (status & SK_ISR_RX1_EOF) { 3120 if (ifp0->if_mtu > SK_MAX_FRAMELEN) 3121 sk_jumbo_rxeof(sc_if0); 3122 else 3123 sk_rxeof(sc_if0); 3124 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 3125 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 3126 } 3127 if (status & SK_ISR_RX2_EOF) { 3128 if (ifp1->if_mtu > SK_MAX_FRAMELEN) 3129 sk_jumbo_rxeof(sc_if1); 3130 else 3131 sk_rxeof(sc_if1); 3132 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 3133 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 3134 } 3135 3136 /* Then transmit interrupts. */ 3137 if (status & SK_ISR_TX1_S_EOF) { 3138 sk_txeof(sc_if0); 3139 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, SK_TXBMU_CLR_IRQ_EOF); 3140 } 3141 if (status & SK_ISR_TX2_S_EOF) { 3142 sk_txeof(sc_if1); 3143 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, SK_TXBMU_CLR_IRQ_EOF); 3144 } 3145 3146 /* Then MAC interrupts. */ 3147 if (status & SK_ISR_MAC1 && 3148 ifp0->if_drv_flags & IFF_DRV_RUNNING) { 3149 if (sc->sk_type == SK_GENESIS) 3150 sk_intr_xmac(sc_if0); 3151 else 3152 sk_intr_yukon(sc_if0); 3153 } 3154 3155 if (status & SK_ISR_MAC2 && 3156 ifp1->if_drv_flags & IFF_DRV_RUNNING) { 3157 if (sc->sk_type == SK_GENESIS) 3158 sk_intr_xmac(sc_if1); 3159 else 3160 sk_intr_yukon(sc_if1); 3161 } 3162 3163 if (status & SK_ISR_EXTERNAL_REG) { 3164 if (ifp0 != NULL && 3165 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 3166 sk_intr_bcom(sc_if0); 3167 if (ifp1 != NULL && 3168 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 3169 sk_intr_bcom(sc_if1); 3170 } 3171 status = CSR_READ_4(sc, SK_ISSR); 3172 } 3173 3174 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 3175 3176 if (ifp0 != NULL && !IFQ_DRV_IS_EMPTY(&ifp0->if_snd)) 3177 sk_start_locked(ifp0); 3178 if (ifp1 != NULL && !IFQ_DRV_IS_EMPTY(&ifp1->if_snd)) 3179 sk_start_locked(ifp1); 3180 3181 done_locked: 3182 SK_UNLOCK(sc); 3183 } 3184 3185 static void 3186 sk_init_xmac(sc_if) 3187 struct sk_if_softc *sc_if; 3188 { 3189 struct sk_softc *sc; 3190 struct ifnet *ifp; 3191 u_int16_t eaddr[(ETHER_ADDR_LEN+1)/2]; 3192 static const struct sk_bcom_hack bhack[] = { 3193 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 3194 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 3195 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 3196 { 0, 0 } }; 3197 3198 SK_IF_LOCK_ASSERT(sc_if); 3199 3200 sc = sc_if->sk_softc; 3201 ifp = sc_if->sk_ifp; 3202 3203 /* Unreset the XMAC. */ 3204 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 3205 DELAY(1000); 3206 3207 /* Reset the XMAC's internal state. */ 3208 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 3209 3210 /* Save the XMAC II revision */ 3211 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 3212 3213 /* 3214 * Perform additional initialization for external PHYs, 3215 * namely for the 1000baseTX cards that use the XMAC's 3216 * GMII mode. 3217 */ 3218 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 3219 int i = 0; 3220 u_int32_t val; 3221 3222 /* Take PHY out of reset. */ 3223 val = sk_win_read_4(sc, SK_GPIO); 3224 if (sc_if->sk_port == SK_PORT_A) 3225 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 3226 else 3227 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 3228 sk_win_write_4(sc, SK_GPIO, val); 3229 3230 /* Enable GMII mode on the XMAC. */ 3231 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 3232 3233 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 3234 BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET); 3235 DELAY(10000); 3236 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 3237 BRGPHY_MII_IMR, 0xFFF0); 3238 3239 /* 3240 * Early versions of the BCM5400 apparently have 3241 * a bug that requires them to have their reserved 3242 * registers initialized to some magic values. I don't 3243 * know what the numbers do, I'm just the messenger. 3244 */ 3245 if (sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 0x03) 3246 == 0x6041) { 3247 while(bhack[i].reg) { 3248 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM, 3249 bhack[i].reg, bhack[i].val); 3250 i++; 3251 } 3252 } 3253 } 3254 3255 /* Set station address */ 3256 bcopy(IF_LLADDR(sc_if->sk_ifp), eaddr, ETHER_ADDR_LEN); 3257 SK_XM_WRITE_2(sc_if, XM_PAR0, eaddr[0]); 3258 SK_XM_WRITE_2(sc_if, XM_PAR1, eaddr[1]); 3259 SK_XM_WRITE_2(sc_if, XM_PAR2, eaddr[2]); 3260 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 3261 3262 if (ifp->if_flags & IFF_BROADCAST) { 3263 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 3264 } else { 3265 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 3266 } 3267 3268 /* We don't need the FCS appended to the packet. */ 3269 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 3270 3271 /* We want short frames padded to 60 bytes. */ 3272 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 3273 3274 /* 3275 * Enable the reception of all error frames. This is is 3276 * a necessary evil due to the design of the XMAC. The 3277 * XMAC's receive FIFO is only 8K in size, however jumbo 3278 * frames can be up to 9000 bytes in length. When bad 3279 * frame filtering is enabled, the XMAC's RX FIFO operates 3280 * in 'store and forward' mode. For this to work, the 3281 * entire frame has to fit into the FIFO, but that means 3282 * that jumbo frames larger than 8192 bytes will be 3283 * truncated. Disabling all bad frame filtering causes 3284 * the RX FIFO to operate in streaming mode, in which 3285 * case the XMAC will start transferring frames out of the 3286 * RX FIFO as soon as the FIFO threshold is reached. 3287 */ 3288 if (ifp->if_mtu > SK_MAX_FRAMELEN) { 3289 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 3290 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 3291 XM_MODE_RX_INRANGELEN); 3292 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 3293 } else 3294 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 3295 3296 /* 3297 * Bump up the transmit threshold. This helps hold off transmit 3298 * underruns when we're blasting traffic from both ports at once. 3299 */ 3300 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 3301 3302 /* Set Rx filter */ 3303 sk_rxfilter_genesis(sc_if); 3304 3305 /* Clear and enable interrupts */ 3306 SK_XM_READ_2(sc_if, XM_ISR); 3307 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 3308 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 3309 else 3310 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 3311 3312 /* Configure MAC arbiter */ 3313 switch(sc_if->sk_xmac_rev) { 3314 case XM_XMAC_REV_B2: 3315 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 3316 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 3317 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 3318 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 3319 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 3320 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 3321 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 3322 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 3323 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 3324 break; 3325 case XM_XMAC_REV_C1: 3326 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 3327 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 3328 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 3329 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 3330 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 3331 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 3332 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 3333 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 3334 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 3335 break; 3336 default: 3337 break; 3338 } 3339 sk_win_write_2(sc, SK_MACARB_CTL, 3340 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 3341 3342 sc_if->sk_link = 1; 3343 3344 return; 3345 } 3346 3347 static void 3348 sk_init_yukon(sc_if) 3349 struct sk_if_softc *sc_if; 3350 { 3351 u_int32_t phy, v; 3352 u_int16_t reg; 3353 struct sk_softc *sc; 3354 struct ifnet *ifp; 3355 u_int8_t *eaddr; 3356 int i; 3357 3358 SK_IF_LOCK_ASSERT(sc_if); 3359 3360 sc = sc_if->sk_softc; 3361 ifp = sc_if->sk_ifp; 3362 3363 if (sc->sk_type == SK_YUKON_LITE && 3364 sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 3365 /* 3366 * Workaround code for COMA mode, set PHY reset. 3367 * Otherwise it will not correctly take chip out of 3368 * powerdown (coma) 3369 */ 3370 v = sk_win_read_4(sc, SK_GPIO); 3371 v |= SK_GPIO_DIR9 | SK_GPIO_DAT9; 3372 sk_win_write_4(sc, SK_GPIO, v); 3373 } 3374 3375 /* GMAC and GPHY Reset */ 3376 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 3377 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 3378 DELAY(1000); 3379 3380 if (sc->sk_type == SK_YUKON_LITE && 3381 sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 3382 /* 3383 * Workaround code for COMA mode, clear PHY reset 3384 */ 3385 v = sk_win_read_4(sc, SK_GPIO); 3386 v |= SK_GPIO_DIR9; 3387 v &= ~SK_GPIO_DAT9; 3388 sk_win_write_4(sc, SK_GPIO, v); 3389 } 3390 3391 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 3392 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 3393 3394 if (sc->sk_coppertype) 3395 phy |= SK_GPHY_COPPER; 3396 else 3397 phy |= SK_GPHY_FIBER; 3398 3399 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 3400 DELAY(1000); 3401 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 3402 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 3403 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 3404 3405 /* unused read of the interrupt source register */ 3406 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 3407 3408 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 3409 3410 /* MIB Counter Clear Mode set */ 3411 reg |= YU_PAR_MIB_CLR; 3412 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 3413 3414 /* MIB Counter Clear Mode clear */ 3415 reg &= ~YU_PAR_MIB_CLR; 3416 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 3417 3418 /* receive control reg */ 3419 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR); 3420 3421 /* transmit parameter register */ 3422 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 3423 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 3424 3425 /* serial mode register */ 3426 reg = YU_SMR_DATA_BLIND(0x1c) | YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e); 3427 if (ifp->if_mtu > SK_MAX_FRAMELEN) 3428 reg |= YU_SMR_MFL_JUMBO; 3429 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg); 3430 3431 /* Setup Yukon's station address */ 3432 eaddr = IF_LLADDR(sc_if->sk_ifp); 3433 for (i = 0; i < 3; i++) 3434 SK_YU_WRITE_2(sc_if, SK_MAC0_0 + i * 4, 3435 eaddr[i * 2] | eaddr[i * 2 + 1] << 8); 3436 /* Set GMAC source address of flow control. */ 3437 for (i = 0; i < 3; i++) 3438 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 3439 eaddr[i * 2] | eaddr[i * 2 + 1] << 8); 3440 /* Set GMAC virtual address. */ 3441 for (i = 0; i < 3; i++) 3442 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, 3443 eaddr[i * 2] | eaddr[i * 2 + 1] << 8); 3444 3445 /* Set Rx filter */ 3446 sk_rxfilter_yukon(sc_if); 3447 3448 /* enable interrupt mask for counter overflows */ 3449 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 3450 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 3451 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 3452 3453 /* Configure RX MAC FIFO Flush Mask */ 3454 v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR | 3455 YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT | 3456 YU_RXSTAT_JABBER; 3457 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v); 3458 3459 /* Disable RX MAC FIFO Flush for YUKON-Lite Rev. A0 only */ 3460 if (sc->sk_type == SK_YUKON_LITE && sc->sk_rev == SK_YUKON_LITE_REV_A0) 3461 v = SK_TFCTL_OPERATION_ON; 3462 else 3463 v = SK_TFCTL_OPERATION_ON | SK_RFCTL_FIFO_FLUSH_ON; 3464 /* Configure RX MAC FIFO */ 3465 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 3466 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, v); 3467 3468 /* Increase flush threshould to 64 bytes */ 3469 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD, 3470 SK_RFCTL_FIFO_THRESHOLD + 1); 3471 3472 /* Configure TX MAC FIFO */ 3473 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 3474 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 3475 } 3476 3477 /* 3478 * Note that to properly initialize any part of the GEnesis chip, 3479 * you first have to take it out of reset mode. 3480 */ 3481 static void 3482 sk_init(xsc) 3483 void *xsc; 3484 { 3485 struct sk_if_softc *sc_if = xsc; 3486 3487 SK_IF_LOCK(sc_if); 3488 sk_init_locked(sc_if); 3489 SK_IF_UNLOCK(sc_if); 3490 3491 return; 3492 } 3493 3494 static void 3495 sk_init_locked(sc_if) 3496 struct sk_if_softc *sc_if; 3497 { 3498 struct sk_softc *sc; 3499 struct ifnet *ifp; 3500 struct mii_data *mii; 3501 u_int16_t reg; 3502 u_int32_t imr; 3503 int error; 3504 3505 SK_IF_LOCK_ASSERT(sc_if); 3506 3507 ifp = sc_if->sk_ifp; 3508 sc = sc_if->sk_softc; 3509 mii = device_get_softc(sc_if->sk_miibus); 3510 3511 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3512 return; 3513 3514 /* Cancel pending I/O and free all RX/TX buffers. */ 3515 sk_stop(sc_if); 3516 3517 if (sc->sk_type == SK_GENESIS) { 3518 /* Configure LINK_SYNC LED */ 3519 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 3520 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 3521 SK_LINKLED_LINKSYNC_ON); 3522 3523 /* Configure RX LED */ 3524 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 3525 SK_RXLEDCTL_COUNTER_START); 3526 3527 /* Configure TX LED */ 3528 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 3529 SK_TXLEDCTL_COUNTER_START); 3530 } 3531 3532 /* 3533 * Configure descriptor poll timer 3534 * 3535 * SK-NET GENESIS data sheet says that possibility of losing Start 3536 * transmit command due to CPU/cache related interim storage problems 3537 * under certain conditions. The document recommends a polling 3538 * mechanism to send a Start transmit command to initiate transfer 3539 * of ready descriptors regulary. To cope with this issue sk(4) now 3540 * enables descriptor poll timer to initiate descriptor processing 3541 * periodically as defined by SK_DPT_TIMER_MAX. However sk(4) still 3542 * issue SK_TXBMU_TX_START to Tx BMU to get fast execution of Tx 3543 * command instead of waiting for next descriptor polling time. 3544 * The same rule may apply to Rx side too but it seems that is not 3545 * needed at the moment. 3546 * Since sk(4) uses descriptor polling as a last resort there is no 3547 * need to set smaller polling time than maximum allowable one. 3548 */ 3549 SK_IF_WRITE_4(sc_if, 0, SK_DPT_INIT, SK_DPT_TIMER_MAX); 3550 3551 /* Configure I2C registers */ 3552 3553 /* Configure XMAC(s) */ 3554 switch (sc->sk_type) { 3555 case SK_GENESIS: 3556 sk_init_xmac(sc_if); 3557 break; 3558 case SK_YUKON: 3559 case SK_YUKON_LITE: 3560 case SK_YUKON_LP: 3561 sk_init_yukon(sc_if); 3562 break; 3563 } 3564 mii_mediachg(mii); 3565 3566 if (sc->sk_type == SK_GENESIS) { 3567 /* Configure MAC FIFOs */ 3568 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 3569 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 3570 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 3571 3572 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 3573 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 3574 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 3575 } 3576 3577 /* Configure transmit arbiter(s) */ 3578 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 3579 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 3580 3581 /* Configure RAMbuffers */ 3582 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 3583 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 3584 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 3585 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 3586 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 3587 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 3588 3589 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 3590 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 3591 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 3592 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 3593 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 3594 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 3595 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 3596 3597 /* Configure BMUs */ 3598 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 3599 if (ifp->if_mtu > SK_MAX_FRAMELEN) { 3600 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 3601 SK_ADDR_LO(SK_JUMBO_RX_RING_ADDR(sc_if, 0))); 3602 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 3603 SK_ADDR_HI(SK_JUMBO_RX_RING_ADDR(sc_if, 0))); 3604 } else { 3605 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 3606 SK_ADDR_LO(SK_RX_RING_ADDR(sc_if, 0))); 3607 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 3608 SK_ADDR_HI(SK_RX_RING_ADDR(sc_if, 0))); 3609 } 3610 3611 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 3612 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 3613 SK_ADDR_LO(SK_TX_RING_ADDR(sc_if, 0))); 3614 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 3615 SK_ADDR_HI(SK_TX_RING_ADDR(sc_if, 0))); 3616 3617 /* Init descriptors */ 3618 if (ifp->if_mtu > SK_MAX_FRAMELEN) 3619 error = sk_init_jumbo_rx_ring(sc_if); 3620 else 3621 error = sk_init_rx_ring(sc_if); 3622 if (error != 0) { 3623 device_printf(sc_if->sk_if_dev, 3624 "initialization failed: no memory for rx buffers\n"); 3625 sk_stop(sc_if); 3626 return; 3627 } 3628 sk_init_tx_ring(sc_if); 3629 3630 /* Set interrupt moderation if changed via sysctl. */ 3631 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 3632 if (imr != SK_IM_USECS(sc->sk_int_mod, sc->sk_int_ticks)) { 3633 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod, 3634 sc->sk_int_ticks)); 3635 if (bootverbose) 3636 device_printf(sc_if->sk_if_dev, 3637 "interrupt moderation is %d us.\n", 3638 sc->sk_int_mod); 3639 } 3640 3641 /* Configure interrupt handling */ 3642 CSR_READ_4(sc, SK_ISSR); 3643 if (sc_if->sk_port == SK_PORT_A) 3644 sc->sk_intrmask |= SK_INTRS1; 3645 else 3646 sc->sk_intrmask |= SK_INTRS2; 3647 3648 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 3649 3650 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 3651 3652 /* Start BMUs. */ 3653 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 3654 3655 switch(sc->sk_type) { 3656 case SK_GENESIS: 3657 /* Enable XMACs TX and RX state machines */ 3658 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 3659 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 3660 break; 3661 case SK_YUKON: 3662 case SK_YUKON_LITE: 3663 case SK_YUKON_LP: 3664 reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 3665 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 3666 #if 0 3667 /* XXX disable 100Mbps and full duplex mode? */ 3668 reg &= ~(YU_GPCR_SPEED | YU_GPCR_DPLX_DIS); 3669 #endif 3670 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 3671 } 3672 3673 /* Activate descriptor polling timer */ 3674 SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_START); 3675 /* start transfer of Tx descriptors */ 3676 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 3677 3678 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3679 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3680 3681 switch (sc->sk_type) { 3682 case SK_YUKON: 3683 case SK_YUKON_LITE: 3684 case SK_YUKON_LP: 3685 callout_reset(&sc_if->sk_tick_ch, hz, sk_yukon_tick, sc_if); 3686 break; 3687 } 3688 3689 callout_reset(&sc_if->sk_watchdog_ch, hz, sk_watchdog, ifp); 3690 3691 return; 3692 } 3693 3694 static void 3695 sk_stop(sc_if) 3696 struct sk_if_softc *sc_if; 3697 { 3698 int i; 3699 struct sk_softc *sc; 3700 struct sk_txdesc *txd; 3701 struct sk_rxdesc *rxd; 3702 struct sk_rxdesc *jrxd; 3703 struct ifnet *ifp; 3704 u_int32_t val; 3705 3706 SK_IF_LOCK_ASSERT(sc_if); 3707 sc = sc_if->sk_softc; 3708 ifp = sc_if->sk_ifp; 3709 3710 callout_stop(&sc_if->sk_tick_ch); 3711 callout_stop(&sc_if->sk_watchdog_ch); 3712 3713 /* stop Tx descriptor polling timer */ 3714 SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP); 3715 /* stop transfer of Tx descriptors */ 3716 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_STOP); 3717 for (i = 0; i < SK_TIMEOUT; i++) { 3718 val = CSR_READ_4(sc, sc_if->sk_tx_bmu); 3719 if ((val & SK_TXBMU_TX_STOP) == 0) 3720 break; 3721 DELAY(1); 3722 } 3723 if (i == SK_TIMEOUT) 3724 device_printf(sc_if->sk_if_dev, 3725 "can not stop transfer of Tx descriptor\n"); 3726 /* stop transfer of Rx descriptors */ 3727 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_STOP); 3728 for (i = 0; i < SK_TIMEOUT; i++) { 3729 val = SK_IF_READ_4(sc_if, 0, SK_RXQ1_BMU_CSR); 3730 if ((val & SK_RXBMU_RX_STOP) == 0) 3731 break; 3732 DELAY(1); 3733 } 3734 if (i == SK_TIMEOUT) 3735 device_printf(sc_if->sk_if_dev, 3736 "can not stop transfer of Rx descriptor\n"); 3737 3738 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 3739 /* Put PHY back into reset. */ 3740 val = sk_win_read_4(sc, SK_GPIO); 3741 if (sc_if->sk_port == SK_PORT_A) { 3742 val |= SK_GPIO_DIR0; 3743 val &= ~SK_GPIO_DAT0; 3744 } else { 3745 val |= SK_GPIO_DIR2; 3746 val &= ~SK_GPIO_DAT2; 3747 } 3748 sk_win_write_4(sc, SK_GPIO, val); 3749 } 3750 3751 /* Turn off various components of this interface. */ 3752 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 3753 switch (sc->sk_type) { 3754 case SK_GENESIS: 3755 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_RESET); 3756 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 3757 break; 3758 case SK_YUKON: 3759 case SK_YUKON_LITE: 3760 case SK_YUKON_LP: 3761 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 3762 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 3763 break; 3764 } 3765 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 3766 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 3767 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 3768 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 3769 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 3770 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 3771 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 3772 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 3773 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 3774 3775 /* Disable interrupts */ 3776 if (sc_if->sk_port == SK_PORT_A) 3777 sc->sk_intrmask &= ~SK_INTRS1; 3778 else 3779 sc->sk_intrmask &= ~SK_INTRS2; 3780 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 3781 3782 SK_XM_READ_2(sc_if, XM_ISR); 3783 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 3784 3785 /* Free RX and TX mbufs still in the queues. */ 3786 for (i = 0; i < SK_RX_RING_CNT; i++) { 3787 rxd = &sc_if->sk_cdata.sk_rxdesc[i]; 3788 if (rxd->rx_m != NULL) { 3789 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag, 3790 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3791 bus_dmamap_unload(sc_if->sk_cdata.sk_rx_tag, 3792 rxd->rx_dmamap); 3793 m_freem(rxd->rx_m); 3794 rxd->rx_m = NULL; 3795 } 3796 } 3797 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) { 3798 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i]; 3799 if (jrxd->rx_m != NULL) { 3800 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag, 3801 jrxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3802 bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_tag, 3803 jrxd->rx_dmamap); 3804 m_freem(jrxd->rx_m); 3805 jrxd->rx_m = NULL; 3806 } 3807 } 3808 for (i = 0; i < SK_TX_RING_CNT; i++) { 3809 txd = &sc_if->sk_cdata.sk_txdesc[i]; 3810 if (txd->tx_m != NULL) { 3811 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag, 3812 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 3813 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag, 3814 txd->tx_dmamap); 3815 m_freem(txd->tx_m); 3816 txd->tx_m = NULL; 3817 } 3818 } 3819 3820 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING|IFF_DRV_OACTIVE); 3821 3822 return; 3823 } 3824 3825 static int 3826 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3827 { 3828 int error, value; 3829 3830 if (!arg1) 3831 return (EINVAL); 3832 value = *(int *)arg1; 3833 error = sysctl_handle_int(oidp, &value, 0, req); 3834 if (error || !req->newptr) 3835 return (error); 3836 if (value < low || value > high) 3837 return (EINVAL); 3838 *(int *)arg1 = value; 3839 return (0); 3840 } 3841 3842 static int 3843 sysctl_hw_sk_int_mod(SYSCTL_HANDLER_ARGS) 3844 { 3845 return (sysctl_int_range(oidp, arg1, arg2, req, SK_IM_MIN, SK_IM_MAX)); 3846 } 3847