1 /*- 2 * Copyright (c) 2005 Poul-Henning Kamp <phk@FreeBSD.org> 3 * Copyright (c) 1997, 1998, 1999 4 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 /* 38 * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are 39 * available from http://www.sis.com.tw. 40 * 41 * This driver also supports the NatSemi DP83815. Datasheets are 42 * available from http://www.national.com. 43 * 44 * Written by Bill Paul <wpaul@ee.columbia.edu> 45 * Electrical Engineering Department 46 * Columbia University, New York City 47 */ 48 /* 49 * The SiS 900 is a fairly simple chip. It uses bus master DMA with 50 * simple TX and RX descriptors of 3 longwords in size. The receiver 51 * has a single perfect filter entry for the station address and a 52 * 128-bit multicast hash table. The SiS 900 has a built-in MII-based 53 * transceiver while the 7016 requires an external transceiver chip. 54 * Both chips offer the standard bit-bang MII interface as well as 55 * an enchanced PHY interface which simplifies accessing MII registers. 56 * 57 * The only downside to this chipset is that RX descriptors must be 58 * longword aligned. 59 */ 60 61 #ifdef HAVE_KERNEL_OPTION_HEADERS 62 #include "opt_device_polling.h" 63 #endif 64 65 #include <sys/param.h> 66 #include <sys/systm.h> 67 #include <sys/bus.h> 68 #include <sys/endian.h> 69 #include <sys/kernel.h> 70 #include <sys/lock.h> 71 #include <sys/malloc.h> 72 #include <sys/mbuf.h> 73 #include <sys/module.h> 74 #include <sys/socket.h> 75 #include <sys/sockio.h> 76 #include <sys/sysctl.h> 77 78 #include <net/if.h> 79 #include <net/if_arp.h> 80 #include <net/ethernet.h> 81 #include <net/if_dl.h> 82 #include <net/if_media.h> 83 #include <net/if_types.h> 84 #include <net/if_vlan_var.h> 85 86 #include <net/bpf.h> 87 88 #include <machine/bus.h> 89 #include <machine/resource.h> 90 #include <sys/rman.h> 91 92 #include <dev/mii/mii.h> 93 #include <dev/mii/miivar.h> 94 95 #include <dev/pci/pcireg.h> 96 #include <dev/pci/pcivar.h> 97 98 #define SIS_USEIOSPACE 99 100 #include <dev/sis/if_sisreg.h> 101 102 MODULE_DEPEND(sis, pci, 1, 1, 1); 103 MODULE_DEPEND(sis, ether, 1, 1, 1); 104 MODULE_DEPEND(sis, miibus, 1, 1, 1); 105 106 /* "device miibus" required. See GENERIC if you get errors here. */ 107 #include "miibus_if.h" 108 109 #define SIS_LOCK(_sc) mtx_lock(&(_sc)->sis_mtx) 110 #define SIS_UNLOCK(_sc) mtx_unlock(&(_sc)->sis_mtx) 111 #define SIS_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sis_mtx, MA_OWNED) 112 113 /* 114 * register space access macros 115 */ 116 #define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->sis_res[0], reg, val) 117 118 #define CSR_READ_4(sc, reg) bus_read_4(sc->sis_res[0], reg) 119 120 #define CSR_READ_2(sc, reg) bus_read_2(sc->sis_res[0], reg) 121 122 /* 123 * Various supported device vendors/types and their names. 124 */ 125 static struct sis_type sis_devs[] = { 126 { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" }, 127 { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" }, 128 { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP8381[56] 10/100BaseTX" }, 129 { 0, 0, NULL } 130 }; 131 132 static int sis_detach(device_t); 133 static __inline void sis_discard_rxbuf(struct sis_rxdesc *); 134 static int sis_dma_alloc(struct sis_softc *); 135 static void sis_dma_free(struct sis_softc *); 136 static int sis_dma_ring_alloc(struct sis_softc *, bus_size_t, bus_size_t, 137 bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, const char *); 138 static void sis_dmamap_cb(void *, bus_dma_segment_t *, int, int); 139 #ifndef __NO_STRICT_ALIGNMENT 140 static __inline void sis_fixup_rx(struct mbuf *); 141 #endif 142 static void sis_ifmedia_sts(struct ifnet *, struct ifmediareq *); 143 static int sis_ifmedia_upd(struct ifnet *); 144 static void sis_init(void *); 145 static void sis_initl(struct sis_softc *); 146 static void sis_intr(void *); 147 static int sis_ioctl(struct ifnet *, u_long, caddr_t); 148 static int sis_newbuf(struct sis_softc *, struct sis_rxdesc *); 149 static int sis_resume(device_t); 150 static int sis_rxeof(struct sis_softc *); 151 static void sis_rxfilter(struct sis_softc *); 152 static void sis_rxfilter_ns(struct sis_softc *); 153 static void sis_rxfilter_sis(struct sis_softc *); 154 static void sis_start(struct ifnet *); 155 static void sis_startl(struct ifnet *); 156 static void sis_stop(struct sis_softc *); 157 static int sis_suspend(device_t); 158 static void sis_add_sysctls(struct sis_softc *); 159 static void sis_watchdog(struct sis_softc *); 160 static void sis_wol(struct sis_softc *); 161 162 163 static struct resource_spec sis_res_spec[] = { 164 #ifdef SIS_USEIOSPACE 165 { SYS_RES_IOPORT, SIS_PCI_LOIO, RF_ACTIVE}, 166 #else 167 { SYS_RES_MEMORY, SIS_PCI_LOMEM, RF_ACTIVE}, 168 #endif 169 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE}, 170 { -1, 0 } 171 }; 172 173 #define SIS_SETBIT(sc, reg, x) \ 174 CSR_WRITE_4(sc, reg, \ 175 CSR_READ_4(sc, reg) | (x)) 176 177 #define SIS_CLRBIT(sc, reg, x) \ 178 CSR_WRITE_4(sc, reg, \ 179 CSR_READ_4(sc, reg) & ~(x)) 180 181 #define SIO_SET(x) \ 182 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x) 183 184 #define SIO_CLR(x) \ 185 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x) 186 187 /* 188 * Routine to reverse the bits in a word. Stolen almost 189 * verbatim from /usr/games/fortune. 190 */ 191 static uint16_t 192 sis_reverse(uint16_t n) 193 { 194 n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa); 195 n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc); 196 n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0); 197 n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00); 198 199 return (n); 200 } 201 202 static void 203 sis_delay(struct sis_softc *sc) 204 { 205 int idx; 206 207 for (idx = (300 / 33) + 1; idx > 0; idx--) 208 CSR_READ_4(sc, SIS_CSR); 209 } 210 211 static void 212 sis_eeprom_idle(struct sis_softc *sc) 213 { 214 int i; 215 216 SIO_SET(SIS_EECTL_CSEL); 217 sis_delay(sc); 218 SIO_SET(SIS_EECTL_CLK); 219 sis_delay(sc); 220 221 for (i = 0; i < 25; i++) { 222 SIO_CLR(SIS_EECTL_CLK); 223 sis_delay(sc); 224 SIO_SET(SIS_EECTL_CLK); 225 sis_delay(sc); 226 } 227 228 SIO_CLR(SIS_EECTL_CLK); 229 sis_delay(sc); 230 SIO_CLR(SIS_EECTL_CSEL); 231 sis_delay(sc); 232 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000); 233 } 234 235 /* 236 * Send a read command and address to the EEPROM, check for ACK. 237 */ 238 static void 239 sis_eeprom_putbyte(struct sis_softc *sc, int addr) 240 { 241 int d, i; 242 243 d = addr | SIS_EECMD_READ; 244 245 /* 246 * Feed in each bit and stobe the clock. 247 */ 248 for (i = 0x400; i; i >>= 1) { 249 if (d & i) { 250 SIO_SET(SIS_EECTL_DIN); 251 } else { 252 SIO_CLR(SIS_EECTL_DIN); 253 } 254 sis_delay(sc); 255 SIO_SET(SIS_EECTL_CLK); 256 sis_delay(sc); 257 SIO_CLR(SIS_EECTL_CLK); 258 sis_delay(sc); 259 } 260 } 261 262 /* 263 * Read a word of data stored in the EEPROM at address 'addr.' 264 */ 265 static void 266 sis_eeprom_getword(struct sis_softc *sc, int addr, uint16_t *dest) 267 { 268 int i; 269 uint16_t word = 0; 270 271 /* Force EEPROM to idle state. */ 272 sis_eeprom_idle(sc); 273 274 /* Enter EEPROM access mode. */ 275 sis_delay(sc); 276 SIO_CLR(SIS_EECTL_CLK); 277 sis_delay(sc); 278 SIO_SET(SIS_EECTL_CSEL); 279 sis_delay(sc); 280 281 /* 282 * Send address of word we want to read. 283 */ 284 sis_eeprom_putbyte(sc, addr); 285 286 /* 287 * Start reading bits from EEPROM. 288 */ 289 for (i = 0x8000; i; i >>= 1) { 290 SIO_SET(SIS_EECTL_CLK); 291 sis_delay(sc); 292 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT) 293 word |= i; 294 sis_delay(sc); 295 SIO_CLR(SIS_EECTL_CLK); 296 sis_delay(sc); 297 } 298 299 /* Turn off EEPROM access mode. */ 300 sis_eeprom_idle(sc); 301 302 *dest = word; 303 } 304 305 /* 306 * Read a sequence of words from the EEPROM. 307 */ 308 static void 309 sis_read_eeprom(struct sis_softc *sc, caddr_t dest, int off, int cnt, int swap) 310 { 311 int i; 312 uint16_t word = 0, *ptr; 313 314 for (i = 0; i < cnt; i++) { 315 sis_eeprom_getword(sc, off + i, &word); 316 ptr = (uint16_t *)(dest + (i * 2)); 317 if (swap) 318 *ptr = ntohs(word); 319 else 320 *ptr = word; 321 } 322 } 323 324 #if defined(__i386__) || defined(__amd64__) 325 static device_t 326 sis_find_bridge(device_t dev) 327 { 328 devclass_t pci_devclass; 329 device_t *pci_devices; 330 int pci_count = 0; 331 device_t *pci_children; 332 int pci_childcount = 0; 333 device_t *busp, *childp; 334 device_t child = NULL; 335 int i, j; 336 337 if ((pci_devclass = devclass_find("pci")) == NULL) 338 return (NULL); 339 340 devclass_get_devices(pci_devclass, &pci_devices, &pci_count); 341 342 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) { 343 if (device_get_children(*busp, &pci_children, &pci_childcount)) 344 continue; 345 for (j = 0, childp = pci_children; 346 j < pci_childcount; j++, childp++) { 347 if (pci_get_vendor(*childp) == SIS_VENDORID && 348 pci_get_device(*childp) == 0x0008) { 349 child = *childp; 350 free(pci_children, M_TEMP); 351 goto done; 352 } 353 } 354 free(pci_children, M_TEMP); 355 } 356 357 done: 358 free(pci_devices, M_TEMP); 359 return (child); 360 } 361 362 static void 363 sis_read_cmos(struct sis_softc *sc, device_t dev, caddr_t dest, int off, int cnt) 364 { 365 device_t bridge; 366 uint8_t reg; 367 int i; 368 bus_space_tag_t btag; 369 370 bridge = sis_find_bridge(dev); 371 if (bridge == NULL) 372 return; 373 reg = pci_read_config(bridge, 0x48, 1); 374 pci_write_config(bridge, 0x48, reg|0x40, 1); 375 376 /* XXX */ 377 #if defined(__amd64__) || defined(__i386__) 378 btag = X86_BUS_SPACE_IO; 379 #endif 380 381 for (i = 0; i < cnt; i++) { 382 bus_space_write_1(btag, 0x0, 0x70, i + off); 383 *(dest + i) = bus_space_read_1(btag, 0x0, 0x71); 384 } 385 386 pci_write_config(bridge, 0x48, reg & ~0x40, 1); 387 } 388 389 static void 390 sis_read_mac(struct sis_softc *sc, device_t dev, caddr_t dest) 391 { 392 uint32_t filtsave, csrsave; 393 394 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); 395 csrsave = CSR_READ_4(sc, SIS_CSR); 396 397 CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave); 398 CSR_WRITE_4(sc, SIS_CSR, 0); 399 400 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE); 401 402 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 403 ((uint16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA); 404 CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1); 405 ((uint16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA); 406 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 407 ((uint16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA); 408 409 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); 410 CSR_WRITE_4(sc, SIS_CSR, csrsave); 411 } 412 #endif 413 414 /* 415 * Sync the PHYs by setting data bit and strobing the clock 32 times. 416 */ 417 static void 418 sis_mii_sync(struct sis_softc *sc) 419 { 420 int i; 421 422 SIO_SET(SIS_MII_DIR|SIS_MII_DATA); 423 424 for (i = 0; i < 32; i++) { 425 SIO_SET(SIS_MII_CLK); 426 DELAY(1); 427 SIO_CLR(SIS_MII_CLK); 428 DELAY(1); 429 } 430 } 431 432 /* 433 * Clock a series of bits through the MII. 434 */ 435 static void 436 sis_mii_send(struct sis_softc *sc, uint32_t bits, int cnt) 437 { 438 int i; 439 440 SIO_CLR(SIS_MII_CLK); 441 442 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 443 if (bits & i) { 444 SIO_SET(SIS_MII_DATA); 445 } else { 446 SIO_CLR(SIS_MII_DATA); 447 } 448 DELAY(1); 449 SIO_CLR(SIS_MII_CLK); 450 DELAY(1); 451 SIO_SET(SIS_MII_CLK); 452 } 453 } 454 455 /* 456 * Read an PHY register through the MII. 457 */ 458 static int 459 sis_mii_readreg(struct sis_softc *sc, struct sis_mii_frame *frame) 460 { 461 int i, ack; 462 463 /* 464 * Set up frame for RX. 465 */ 466 frame->mii_stdelim = SIS_MII_STARTDELIM; 467 frame->mii_opcode = SIS_MII_READOP; 468 frame->mii_turnaround = 0; 469 frame->mii_data = 0; 470 471 /* 472 * Turn on data xmit. 473 */ 474 SIO_SET(SIS_MII_DIR); 475 476 sis_mii_sync(sc); 477 478 /* 479 * Send command/address info. 480 */ 481 sis_mii_send(sc, frame->mii_stdelim, 2); 482 sis_mii_send(sc, frame->mii_opcode, 2); 483 sis_mii_send(sc, frame->mii_phyaddr, 5); 484 sis_mii_send(sc, frame->mii_regaddr, 5); 485 486 /* Idle bit */ 487 SIO_CLR((SIS_MII_CLK|SIS_MII_DATA)); 488 DELAY(1); 489 SIO_SET(SIS_MII_CLK); 490 DELAY(1); 491 492 /* Turn off xmit. */ 493 SIO_CLR(SIS_MII_DIR); 494 495 /* Check for ack */ 496 SIO_CLR(SIS_MII_CLK); 497 DELAY(1); 498 ack = CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA; 499 SIO_SET(SIS_MII_CLK); 500 DELAY(1); 501 502 /* 503 * Now try reading data bits. If the ack failed, we still 504 * need to clock through 16 cycles to keep the PHY(s) in sync. 505 */ 506 if (ack) { 507 for (i = 0; i < 16; i++) { 508 SIO_CLR(SIS_MII_CLK); 509 DELAY(1); 510 SIO_SET(SIS_MII_CLK); 511 DELAY(1); 512 } 513 goto fail; 514 } 515 516 for (i = 0x8000; i; i >>= 1) { 517 SIO_CLR(SIS_MII_CLK); 518 DELAY(1); 519 if (!ack) { 520 if (CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA) 521 frame->mii_data |= i; 522 DELAY(1); 523 } 524 SIO_SET(SIS_MII_CLK); 525 DELAY(1); 526 } 527 528 fail: 529 530 SIO_CLR(SIS_MII_CLK); 531 DELAY(1); 532 SIO_SET(SIS_MII_CLK); 533 DELAY(1); 534 535 if (ack) 536 return (1); 537 return (0); 538 } 539 540 /* 541 * Write to a PHY register through the MII. 542 */ 543 static int 544 sis_mii_writereg(struct sis_softc *sc, struct sis_mii_frame *frame) 545 { 546 547 /* 548 * Set up frame for TX. 549 */ 550 551 frame->mii_stdelim = SIS_MII_STARTDELIM; 552 frame->mii_opcode = SIS_MII_WRITEOP; 553 frame->mii_turnaround = SIS_MII_TURNAROUND; 554 555 /* 556 * Turn on data output. 557 */ 558 SIO_SET(SIS_MII_DIR); 559 560 sis_mii_sync(sc); 561 562 sis_mii_send(sc, frame->mii_stdelim, 2); 563 sis_mii_send(sc, frame->mii_opcode, 2); 564 sis_mii_send(sc, frame->mii_phyaddr, 5); 565 sis_mii_send(sc, frame->mii_regaddr, 5); 566 sis_mii_send(sc, frame->mii_turnaround, 2); 567 sis_mii_send(sc, frame->mii_data, 16); 568 569 /* Idle bit. */ 570 SIO_SET(SIS_MII_CLK); 571 DELAY(1); 572 SIO_CLR(SIS_MII_CLK); 573 DELAY(1); 574 575 /* 576 * Turn off xmit. 577 */ 578 SIO_CLR(SIS_MII_DIR); 579 580 return (0); 581 } 582 583 static int 584 sis_miibus_readreg(device_t dev, int phy, int reg) 585 { 586 struct sis_softc *sc; 587 struct sis_mii_frame frame; 588 589 sc = device_get_softc(dev); 590 591 if (sc->sis_type == SIS_TYPE_83815) { 592 if (phy != 0) 593 return (0); 594 /* 595 * The NatSemi chip can take a while after 596 * a reset to come ready, during which the BMSR 597 * returns a value of 0. This is *never* supposed 598 * to happen: some of the BMSR bits are meant to 599 * be hardwired in the on position, and this can 600 * confuse the miibus code a bit during the probe 601 * and attach phase. So we make an effort to check 602 * for this condition and wait for it to clear. 603 */ 604 if (!CSR_READ_4(sc, NS_BMSR)) 605 DELAY(1000); 606 return CSR_READ_4(sc, NS_BMCR + (reg * 4)); 607 } 608 609 /* 610 * Chipsets < SIS_635 seem not to be able to read/write 611 * through mdio. Use the enhanced PHY access register 612 * again for them. 613 */ 614 if (sc->sis_type == SIS_TYPE_900 && 615 sc->sis_rev < SIS_REV_635) { 616 int i, val = 0; 617 618 if (phy != 0) 619 return (0); 620 621 CSR_WRITE_4(sc, SIS_PHYCTL, 622 (phy << 11) | (reg << 6) | SIS_PHYOP_READ); 623 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 624 625 for (i = 0; i < SIS_TIMEOUT; i++) { 626 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 627 break; 628 } 629 630 if (i == SIS_TIMEOUT) { 631 device_printf(sc->sis_dev, "PHY failed to come ready\n"); 632 return (0); 633 } 634 635 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF; 636 637 if (val == 0xFFFF) 638 return (0); 639 640 return (val); 641 } else { 642 bzero((char *)&frame, sizeof(frame)); 643 644 frame.mii_phyaddr = phy; 645 frame.mii_regaddr = reg; 646 sis_mii_readreg(sc, &frame); 647 648 return (frame.mii_data); 649 } 650 } 651 652 static int 653 sis_miibus_writereg(device_t dev, int phy, int reg, int data) 654 { 655 struct sis_softc *sc; 656 struct sis_mii_frame frame; 657 658 sc = device_get_softc(dev); 659 660 if (sc->sis_type == SIS_TYPE_83815) { 661 if (phy != 0) 662 return (0); 663 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data); 664 return (0); 665 } 666 667 /* 668 * Chipsets < SIS_635 seem not to be able to read/write 669 * through mdio. Use the enhanced PHY access register 670 * again for them. 671 */ 672 if (sc->sis_type == SIS_TYPE_900 && 673 sc->sis_rev < SIS_REV_635) { 674 int i; 675 676 if (phy != 0) 677 return (0); 678 679 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) | 680 (reg << 6) | SIS_PHYOP_WRITE); 681 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); 682 683 for (i = 0; i < SIS_TIMEOUT; i++) { 684 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) 685 break; 686 } 687 688 if (i == SIS_TIMEOUT) 689 device_printf(sc->sis_dev, "PHY failed to come ready\n"); 690 } else { 691 bzero((char *)&frame, sizeof(frame)); 692 693 frame.mii_phyaddr = phy; 694 frame.mii_regaddr = reg; 695 frame.mii_data = data; 696 sis_mii_writereg(sc, &frame); 697 } 698 return (0); 699 } 700 701 static void 702 sis_miibus_statchg(device_t dev) 703 { 704 struct sis_softc *sc; 705 struct mii_data *mii; 706 struct ifnet *ifp; 707 uint32_t reg; 708 709 sc = device_get_softc(dev); 710 SIS_LOCK_ASSERT(sc); 711 712 mii = device_get_softc(sc->sis_miibus); 713 ifp = sc->sis_ifp; 714 if (mii == NULL || ifp == NULL || 715 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 716 return; 717 718 sc->sis_flags &= ~SIS_FLAG_LINK; 719 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 720 (IFM_ACTIVE | IFM_AVALID)) { 721 switch (IFM_SUBTYPE(mii->mii_media_active)) { 722 case IFM_10_T: 723 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10); 724 sc->sis_flags |= SIS_FLAG_LINK; 725 break; 726 case IFM_100_TX: 727 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100); 728 sc->sis_flags |= SIS_FLAG_LINK; 729 break; 730 default: 731 break; 732 } 733 } 734 735 if ((sc->sis_flags & SIS_FLAG_LINK) == 0) { 736 /* 737 * Stopping MACs seem to reset SIS_TX_LISTPTR and 738 * SIS_RX_LISTPTR which in turn requires resetting 739 * TX/RX buffers. So just don't do anything for 740 * lost link. 741 */ 742 return; 743 } 744 745 /* Set full/half duplex mode. */ 746 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 747 SIS_SETBIT(sc, SIS_TX_CFG, 748 (SIS_TXCFG_IGN_HBEAT | SIS_TXCFG_IGN_CARR)); 749 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 750 } else { 751 SIS_CLRBIT(sc, SIS_TX_CFG, 752 (SIS_TXCFG_IGN_HBEAT | SIS_TXCFG_IGN_CARR)); 753 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); 754 } 755 756 if (sc->sis_type == SIS_TYPE_83816) { 757 /* 758 * MPII03.D: Half Duplex Excessive Collisions. 759 * Also page 49 in 83816 manual 760 */ 761 SIS_SETBIT(sc, SIS_TX_CFG, SIS_TXCFG_MPII03D); 762 } 763 764 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr < NS_SRR_16A && 765 IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 766 /* 767 * Short Cable Receive Errors (MP21.E) 768 */ 769 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 770 reg = CSR_READ_4(sc, NS_PHY_DSPCFG) & 0xfff; 771 CSR_WRITE_4(sc, NS_PHY_DSPCFG, reg | 0x1000); 772 DELAY(100); 773 reg = CSR_READ_4(sc, NS_PHY_TDATA) & 0xff; 774 if ((reg & 0x0080) == 0 || (reg > 0xd8 && reg <= 0xff)) { 775 device_printf(sc->sis_dev, 776 "Applying short cable fix (reg=%x)\n", reg); 777 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x00e8); 778 SIS_SETBIT(sc, NS_PHY_DSPCFG, 0x20); 779 } 780 CSR_WRITE_4(sc, NS_PHY_PAGE, 0); 781 } 782 /* Enable TX/RX MACs. */ 783 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE | SIS_CSR_RX_DISABLE); 784 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE | SIS_CSR_RX_ENABLE); 785 } 786 787 static uint32_t 788 sis_mchash(struct sis_softc *sc, const uint8_t *addr) 789 { 790 uint32_t crc; 791 792 /* Compute CRC for the address value. */ 793 crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 794 795 /* 796 * return the filter bit position 797 * 798 * The NatSemi chip has a 512-bit filter, which is 799 * different than the SiS, so we special-case it. 800 */ 801 if (sc->sis_type == SIS_TYPE_83815) 802 return (crc >> 23); 803 else if (sc->sis_rev >= SIS_REV_635 || 804 sc->sis_rev == SIS_REV_900B) 805 return (crc >> 24); 806 else 807 return (crc >> 25); 808 } 809 810 static void 811 sis_rxfilter(struct sis_softc *sc) 812 { 813 814 SIS_LOCK_ASSERT(sc); 815 816 if (sc->sis_type == SIS_TYPE_83815) 817 sis_rxfilter_ns(sc); 818 else 819 sis_rxfilter_sis(sc); 820 } 821 822 static void 823 sis_rxfilter_ns(struct sis_softc *sc) 824 { 825 struct ifnet *ifp; 826 struct ifmultiaddr *ifma; 827 uint32_t h, i, filter; 828 int bit, index; 829 830 ifp = sc->sis_ifp; 831 filter = CSR_READ_4(sc, SIS_RXFILT_CTL); 832 if (filter & SIS_RXFILTCTL_ENABLE) { 833 /* 834 * Filter should be disabled to program other bits. 835 */ 836 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter & ~SIS_RXFILTCTL_ENABLE); 837 CSR_READ_4(sc, SIS_RXFILT_CTL); 838 } 839 filter &= ~(NS_RXFILTCTL_ARP | NS_RXFILTCTL_PERFECT | 840 NS_RXFILTCTL_MCHASH | SIS_RXFILTCTL_ALLPHYS | SIS_RXFILTCTL_BROAD | 841 SIS_RXFILTCTL_ALLMULTI); 842 843 if (ifp->if_flags & IFF_BROADCAST) 844 filter |= SIS_RXFILTCTL_BROAD; 845 /* 846 * For the NatSemi chip, we have to explicitly enable the 847 * reception of ARP frames, as well as turn on the 'perfect 848 * match' filter where we store the station address, otherwise 849 * we won't receive unicasts meant for this host. 850 */ 851 filter |= NS_RXFILTCTL_ARP | NS_RXFILTCTL_PERFECT; 852 853 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 854 filter |= SIS_RXFILTCTL_ALLMULTI; 855 if (ifp->if_flags & IFF_PROMISC) 856 filter |= SIS_RXFILTCTL_ALLPHYS; 857 } else { 858 /* 859 * We have to explicitly enable the multicast hash table 860 * on the NatSemi chip if we want to use it, which we do. 861 */ 862 filter |= NS_RXFILTCTL_MCHASH; 863 864 /* first, zot all the existing hash bits */ 865 for (i = 0; i < 32; i++) { 866 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + 867 (i * 2)); 868 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0); 869 } 870 871 if_maddr_rlock(ifp); 872 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 873 if (ifma->ifma_addr->sa_family != AF_LINK) 874 continue; 875 h = sis_mchash(sc, 876 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 877 index = h >> 3; 878 bit = h & 0x1F; 879 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + 880 index); 881 if (bit > 0xF) 882 bit -= 0x10; 883 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit)); 884 } 885 if_maddr_runlock(ifp); 886 } 887 888 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter); 889 CSR_READ_4(sc, SIS_RXFILT_CTL); 890 } 891 892 static void 893 sis_rxfilter_sis(struct sis_softc *sc) 894 { 895 struct ifnet *ifp; 896 struct ifmultiaddr *ifma; 897 uint32_t filter, h, i, n; 898 uint16_t hashes[16]; 899 900 ifp = sc->sis_ifp; 901 902 /* hash table size */ 903 if (sc->sis_rev >= SIS_REV_635 || sc->sis_rev == SIS_REV_900B) 904 n = 16; 905 else 906 n = 8; 907 908 filter = CSR_READ_4(sc, SIS_RXFILT_CTL); 909 if (filter & SIS_RXFILTCTL_ENABLE) { 910 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter & ~SIS_RXFILT_CTL); 911 CSR_READ_4(sc, SIS_RXFILT_CTL); 912 } 913 filter &= ~(SIS_RXFILTCTL_ALLPHYS | SIS_RXFILTCTL_BROAD | 914 SIS_RXFILTCTL_ALLMULTI); 915 if (ifp->if_flags & IFF_BROADCAST) 916 filter |= SIS_RXFILTCTL_BROAD; 917 918 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 919 filter |= SIS_RXFILTCTL_ALLMULTI; 920 if (ifp->if_flags & IFF_PROMISC) 921 filter |= SIS_RXFILTCTL_ALLPHYS; 922 for (i = 0; i < n; i++) 923 hashes[i] = ~0; 924 } else { 925 for (i = 0; i < n; i++) 926 hashes[i] = 0; 927 i = 0; 928 if_maddr_rlock(ifp); 929 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 930 if (ifma->ifma_addr->sa_family != AF_LINK) 931 continue; 932 h = sis_mchash(sc, 933 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 934 hashes[h >> 4] |= 1 << (h & 0xf); 935 i++; 936 } 937 if_maddr_runlock(ifp); 938 if (i > n) { 939 filter |= SIS_RXFILTCTL_ALLMULTI; 940 for (i = 0; i < n; i++) 941 hashes[i] = ~0; 942 } 943 } 944 945 for (i = 0; i < n; i++) { 946 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16); 947 CSR_WRITE_4(sc, SIS_RXFILT_DATA, hashes[i]); 948 } 949 950 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter); 951 CSR_READ_4(sc, SIS_RXFILT_CTL); 952 } 953 954 static void 955 sis_reset(struct sis_softc *sc) 956 { 957 int i; 958 959 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET); 960 961 for (i = 0; i < SIS_TIMEOUT; i++) { 962 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET)) 963 break; 964 } 965 966 if (i == SIS_TIMEOUT) 967 device_printf(sc->sis_dev, "reset never completed\n"); 968 969 /* Wait a little while for the chip to get its brains in order. */ 970 DELAY(1000); 971 972 /* 973 * If this is a NetSemi chip, make sure to clear 974 * PME mode. 975 */ 976 if (sc->sis_type == SIS_TYPE_83815) { 977 CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS); 978 CSR_WRITE_4(sc, NS_CLKRUN, 0); 979 } else { 980 /* Disable WOL functions. */ 981 CSR_WRITE_4(sc, SIS_PWRMAN_CTL, 0); 982 } 983 } 984 985 /* 986 * Probe for an SiS chip. Check the PCI vendor and device 987 * IDs against our list and return a device name if we find a match. 988 */ 989 static int 990 sis_probe(device_t dev) 991 { 992 struct sis_type *t; 993 994 t = sis_devs; 995 996 while (t->sis_name != NULL) { 997 if ((pci_get_vendor(dev) == t->sis_vid) && 998 (pci_get_device(dev) == t->sis_did)) { 999 device_set_desc(dev, t->sis_name); 1000 return (BUS_PROBE_DEFAULT); 1001 } 1002 t++; 1003 } 1004 1005 return (ENXIO); 1006 } 1007 1008 /* 1009 * Attach the interface. Allocate softc structures, do ifmedia 1010 * setup and ethernet/BPF attach. 1011 */ 1012 static int 1013 sis_attach(device_t dev) 1014 { 1015 u_char eaddr[ETHER_ADDR_LEN]; 1016 struct sis_softc *sc; 1017 struct ifnet *ifp; 1018 int error = 0, pmc, waittime = 0; 1019 1020 waittime = 0; 1021 sc = device_get_softc(dev); 1022 1023 sc->sis_dev = dev; 1024 1025 mtx_init(&sc->sis_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1026 MTX_DEF); 1027 callout_init_mtx(&sc->sis_stat_ch, &sc->sis_mtx, 0); 1028 1029 if (pci_get_device(dev) == SIS_DEVICEID_900) 1030 sc->sis_type = SIS_TYPE_900; 1031 if (pci_get_device(dev) == SIS_DEVICEID_7016) 1032 sc->sis_type = SIS_TYPE_7016; 1033 if (pci_get_vendor(dev) == NS_VENDORID) 1034 sc->sis_type = SIS_TYPE_83815; 1035 1036 sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1); 1037 /* 1038 * Map control/status registers. 1039 */ 1040 pci_enable_busmaster(dev); 1041 1042 error = bus_alloc_resources(dev, sis_res_spec, sc->sis_res); 1043 if (error) { 1044 device_printf(dev, "couldn't allocate resources\n"); 1045 goto fail; 1046 } 1047 1048 /* Reset the adapter. */ 1049 sis_reset(sc); 1050 1051 if (sc->sis_type == SIS_TYPE_900 && 1052 (sc->sis_rev == SIS_REV_635 || 1053 sc->sis_rev == SIS_REV_900B)) { 1054 SIO_SET(SIS_CFG_RND_CNT); 1055 SIO_SET(SIS_CFG_PERR_DETECT); 1056 } 1057 1058 /* 1059 * Get station address from the EEPROM. 1060 */ 1061 switch (pci_get_vendor(dev)) { 1062 case NS_VENDORID: 1063 sc->sis_srr = CSR_READ_4(sc, NS_SRR); 1064 1065 /* We can't update the device description, so spew */ 1066 if (sc->sis_srr == NS_SRR_15C) 1067 device_printf(dev, "Silicon Revision: DP83815C\n"); 1068 else if (sc->sis_srr == NS_SRR_15D) 1069 device_printf(dev, "Silicon Revision: DP83815D\n"); 1070 else if (sc->sis_srr == NS_SRR_16A) 1071 device_printf(dev, "Silicon Revision: DP83816A\n"); 1072 else 1073 device_printf(dev, "Silicon Revision %x\n", sc->sis_srr); 1074 1075 /* 1076 * Reading the MAC address out of the EEPROM on 1077 * the NatSemi chip takes a bit more work than 1078 * you'd expect. The address spans 4 16-bit words, 1079 * with the first word containing only a single bit. 1080 * You have to shift everything over one bit to 1081 * get it aligned properly. Also, the bits are 1082 * stored backwards (the LSB is really the MSB, 1083 * and so on) so you have to reverse them in order 1084 * to get the MAC address into the form we want. 1085 * Why? Who the hell knows. 1086 */ 1087 { 1088 uint16_t tmp[4]; 1089 1090 sis_read_eeprom(sc, (caddr_t)&tmp, 1091 NS_EE_NODEADDR, 4, 0); 1092 1093 /* Shift everything over one bit. */ 1094 tmp[3] = tmp[3] >> 1; 1095 tmp[3] |= tmp[2] << 15; 1096 tmp[2] = tmp[2] >> 1; 1097 tmp[2] |= tmp[1] << 15; 1098 tmp[1] = tmp[1] >> 1; 1099 tmp[1] |= tmp[0] << 15; 1100 1101 /* Now reverse all the bits. */ 1102 tmp[3] = sis_reverse(tmp[3]); 1103 tmp[2] = sis_reverse(tmp[2]); 1104 tmp[1] = sis_reverse(tmp[1]); 1105 1106 eaddr[0] = (tmp[1] >> 0) & 0xFF; 1107 eaddr[1] = (tmp[1] >> 8) & 0xFF; 1108 eaddr[2] = (tmp[2] >> 0) & 0xFF; 1109 eaddr[3] = (tmp[2] >> 8) & 0xFF; 1110 eaddr[4] = (tmp[3] >> 0) & 0xFF; 1111 eaddr[5] = (tmp[3] >> 8) & 0xFF; 1112 } 1113 break; 1114 case SIS_VENDORID: 1115 default: 1116 #if defined(__i386__) || defined(__amd64__) 1117 /* 1118 * If this is a SiS 630E chipset with an embedded 1119 * SiS 900 controller, we have to read the MAC address 1120 * from the APC CMOS RAM. Our method for doing this 1121 * is very ugly since we have to reach out and grab 1122 * ahold of hardware for which we cannot properly 1123 * allocate resources. This code is only compiled on 1124 * the i386 architecture since the SiS 630E chipset 1125 * is for x86 motherboards only. Note that there are 1126 * a lot of magic numbers in this hack. These are 1127 * taken from SiS's Linux driver. I'd like to replace 1128 * them with proper symbolic definitions, but that 1129 * requires some datasheets that I don't have access 1130 * to at the moment. 1131 */ 1132 if (sc->sis_rev == SIS_REV_630S || 1133 sc->sis_rev == SIS_REV_630E || 1134 sc->sis_rev == SIS_REV_630EA1) 1135 sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6); 1136 1137 else if (sc->sis_rev == SIS_REV_635 || 1138 sc->sis_rev == SIS_REV_630ET) 1139 sis_read_mac(sc, dev, (caddr_t)&eaddr); 1140 else if (sc->sis_rev == SIS_REV_96x) { 1141 /* Allow to read EEPROM from LAN. It is shared 1142 * between a 1394 controller and the NIC and each 1143 * time we access it, we need to set SIS_EECMD_REQ. 1144 */ 1145 SIO_SET(SIS_EECMD_REQ); 1146 for (waittime = 0; waittime < SIS_TIMEOUT; 1147 waittime++) { 1148 /* Force EEPROM to idle state. */ 1149 sis_eeprom_idle(sc); 1150 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) { 1151 sis_read_eeprom(sc, (caddr_t)&eaddr, 1152 SIS_EE_NODEADDR, 3, 0); 1153 break; 1154 } 1155 DELAY(1); 1156 } 1157 /* 1158 * Set SIS_EECTL_CLK to high, so a other master 1159 * can operate on the i2c bus. 1160 */ 1161 SIO_SET(SIS_EECTL_CLK); 1162 /* Refuse EEPROM access by LAN */ 1163 SIO_SET(SIS_EECMD_DONE); 1164 } else 1165 #endif 1166 sis_read_eeprom(sc, (caddr_t)&eaddr, 1167 SIS_EE_NODEADDR, 3, 0); 1168 break; 1169 } 1170 1171 sis_add_sysctls(sc); 1172 1173 /* Allocate DMA'able memory. */ 1174 if ((error = sis_dma_alloc(sc)) != 0) 1175 goto fail; 1176 1177 ifp = sc->sis_ifp = if_alloc(IFT_ETHER); 1178 if (ifp == NULL) { 1179 device_printf(dev, "can not if_alloc()\n"); 1180 error = ENOSPC; 1181 goto fail; 1182 } 1183 ifp->if_softc = sc; 1184 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1185 ifp->if_mtu = ETHERMTU; 1186 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1187 ifp->if_ioctl = sis_ioctl; 1188 ifp->if_start = sis_start; 1189 ifp->if_init = sis_init; 1190 IFQ_SET_MAXLEN(&ifp->if_snd, SIS_TX_LIST_CNT - 1); 1191 ifp->if_snd.ifq_drv_maxlen = SIS_TX_LIST_CNT - 1; 1192 IFQ_SET_READY(&ifp->if_snd); 1193 1194 if (pci_find_cap(sc->sis_dev, PCIY_PMG, &pmc) == 0) { 1195 if (sc->sis_type == SIS_TYPE_83815) 1196 ifp->if_capabilities |= IFCAP_WOL; 1197 else 1198 ifp->if_capabilities |= IFCAP_WOL_MAGIC; 1199 ifp->if_capenable = ifp->if_capabilities; 1200 } 1201 1202 /* 1203 * Do MII setup. 1204 */ 1205 error = mii_attach(dev, &sc->sis_miibus, ifp, sis_ifmedia_upd, 1206 sis_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0); 1207 if (error != 0) { 1208 device_printf(dev, "attaching PHYs failed\n"); 1209 goto fail; 1210 } 1211 1212 /* 1213 * Call MI attach routine. 1214 */ 1215 ether_ifattach(ifp, eaddr); 1216 1217 /* 1218 * Tell the upper layer(s) we support long frames. 1219 */ 1220 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1221 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1222 ifp->if_capenable = ifp->if_capabilities; 1223 #ifdef DEVICE_POLLING 1224 ifp->if_capabilities |= IFCAP_POLLING; 1225 #endif 1226 1227 /* Hook interrupt last to avoid having to lock softc */ 1228 error = bus_setup_intr(dev, sc->sis_res[1], INTR_TYPE_NET | INTR_MPSAFE, 1229 NULL, sis_intr, sc, &sc->sis_intrhand); 1230 1231 if (error) { 1232 device_printf(dev, "couldn't set up irq\n"); 1233 ether_ifdetach(ifp); 1234 goto fail; 1235 } 1236 1237 fail: 1238 if (error) 1239 sis_detach(dev); 1240 1241 return (error); 1242 } 1243 1244 /* 1245 * Shutdown hardware and free up resources. This can be called any 1246 * time after the mutex has been initialized. It is called in both 1247 * the error case in attach and the normal detach case so it needs 1248 * to be careful about only freeing resources that have actually been 1249 * allocated. 1250 */ 1251 static int 1252 sis_detach(device_t dev) 1253 { 1254 struct sis_softc *sc; 1255 struct ifnet *ifp; 1256 1257 sc = device_get_softc(dev); 1258 KASSERT(mtx_initialized(&sc->sis_mtx), ("sis mutex not initialized")); 1259 ifp = sc->sis_ifp; 1260 1261 #ifdef DEVICE_POLLING 1262 if (ifp->if_capenable & IFCAP_POLLING) 1263 ether_poll_deregister(ifp); 1264 #endif 1265 1266 /* These should only be active if attach succeeded. */ 1267 if (device_is_attached(dev)) { 1268 SIS_LOCK(sc); 1269 sis_stop(sc); 1270 SIS_UNLOCK(sc); 1271 callout_drain(&sc->sis_stat_ch); 1272 ether_ifdetach(ifp); 1273 } 1274 if (sc->sis_miibus) 1275 device_delete_child(dev, sc->sis_miibus); 1276 bus_generic_detach(dev); 1277 1278 if (sc->sis_intrhand) 1279 bus_teardown_intr(dev, sc->sis_res[1], sc->sis_intrhand); 1280 bus_release_resources(dev, sis_res_spec, sc->sis_res); 1281 1282 if (ifp) 1283 if_free(ifp); 1284 1285 sis_dma_free(sc); 1286 1287 mtx_destroy(&sc->sis_mtx); 1288 1289 return (0); 1290 } 1291 1292 struct sis_dmamap_arg { 1293 bus_addr_t sis_busaddr; 1294 }; 1295 1296 static void 1297 sis_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1298 { 1299 struct sis_dmamap_arg *ctx; 1300 1301 if (error != 0) 1302 return; 1303 1304 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1305 1306 ctx = (struct sis_dmamap_arg *)arg; 1307 ctx->sis_busaddr = segs[0].ds_addr; 1308 } 1309 1310 static int 1311 sis_dma_ring_alloc(struct sis_softc *sc, bus_size_t alignment, 1312 bus_size_t maxsize, bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map, 1313 bus_addr_t *paddr, const char *msg) 1314 { 1315 struct sis_dmamap_arg ctx; 1316 int error; 1317 1318 error = bus_dma_tag_create(sc->sis_parent_tag, alignment, 0, 1319 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, maxsize, 1, 1320 maxsize, 0, NULL, NULL, tag); 1321 if (error != 0) { 1322 device_printf(sc->sis_dev, 1323 "could not create %s dma tag\n", msg); 1324 return (ENOMEM); 1325 } 1326 /* Allocate DMA'able memory for ring. */ 1327 error = bus_dmamem_alloc(*tag, (void **)ring, 1328 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map); 1329 if (error != 0) { 1330 device_printf(sc->sis_dev, 1331 "could not allocate DMA'able memory for %s\n", msg); 1332 return (ENOMEM); 1333 } 1334 /* Load the address of the ring. */ 1335 ctx.sis_busaddr = 0; 1336 error = bus_dmamap_load(*tag, *map, *ring, maxsize, sis_dmamap_cb, 1337 &ctx, BUS_DMA_NOWAIT); 1338 if (error != 0) { 1339 device_printf(sc->sis_dev, 1340 "could not load DMA'able memory for %s\n", msg); 1341 return (ENOMEM); 1342 } 1343 *paddr = ctx.sis_busaddr; 1344 return (0); 1345 } 1346 1347 static int 1348 sis_dma_alloc(struct sis_softc *sc) 1349 { 1350 struct sis_rxdesc *rxd; 1351 struct sis_txdesc *txd; 1352 int error, i; 1353 1354 /* Allocate the parent bus DMA tag appropriate for PCI. */ 1355 error = bus_dma_tag_create(bus_get_dma_tag(sc->sis_dev), 1356 1, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1357 NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 1358 0, NULL, NULL, &sc->sis_parent_tag); 1359 if (error != 0) { 1360 device_printf(sc->sis_dev, 1361 "could not allocate parent dma tag\n"); 1362 return (ENOMEM); 1363 } 1364 1365 /* Create RX ring. */ 1366 error = sis_dma_ring_alloc(sc, SIS_DESC_ALIGN, SIS_RX_LIST_SZ, 1367 &sc->sis_rx_list_tag, (uint8_t **)&sc->sis_rx_list, 1368 &sc->sis_rx_list_map, &sc->sis_rx_paddr, "RX ring"); 1369 if (error) 1370 return (error); 1371 1372 /* Create TX ring. */ 1373 error = sis_dma_ring_alloc(sc, SIS_DESC_ALIGN, SIS_TX_LIST_SZ, 1374 &sc->sis_tx_list_tag, (uint8_t **)&sc->sis_tx_list, 1375 &sc->sis_tx_list_map, &sc->sis_tx_paddr, "TX ring"); 1376 if (error) 1377 return (error); 1378 1379 /* Create tag for RX mbufs. */ 1380 error = bus_dma_tag_create(sc->sis_parent_tag, SIS_RX_BUF_ALIGN, 0, 1381 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, 1382 MCLBYTES, 0, NULL, NULL, &sc->sis_rx_tag); 1383 if (error) { 1384 device_printf(sc->sis_dev, "could not allocate RX dma tag\n"); 1385 return (error); 1386 } 1387 1388 /* Create tag for TX mbufs. */ 1389 error = bus_dma_tag_create(sc->sis_parent_tag, 1, 0, 1390 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1391 MCLBYTES * SIS_MAXTXSEGS, SIS_MAXTXSEGS, MCLBYTES, 0, NULL, NULL, 1392 &sc->sis_tx_tag); 1393 if (error) { 1394 device_printf(sc->sis_dev, "could not allocate TX dma tag\n"); 1395 return (error); 1396 } 1397 1398 /* Create DMA maps for RX buffers. */ 1399 error = bus_dmamap_create(sc->sis_rx_tag, 0, &sc->sis_rx_sparemap); 1400 if (error) { 1401 device_printf(sc->sis_dev, 1402 "can't create spare DMA map for RX\n"); 1403 return (error); 1404 } 1405 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 1406 rxd = &sc->sis_rxdesc[i]; 1407 rxd->rx_m = NULL; 1408 error = bus_dmamap_create(sc->sis_rx_tag, 0, &rxd->rx_dmamap); 1409 if (error) { 1410 device_printf(sc->sis_dev, 1411 "can't create DMA map for RX\n"); 1412 return (error); 1413 } 1414 } 1415 1416 /* Create DMA maps for TX buffers. */ 1417 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 1418 txd = &sc->sis_txdesc[i]; 1419 txd->tx_m = NULL; 1420 error = bus_dmamap_create(sc->sis_tx_tag, 0, &txd->tx_dmamap); 1421 if (error) { 1422 device_printf(sc->sis_dev, 1423 "can't create DMA map for TX\n"); 1424 return (error); 1425 } 1426 } 1427 1428 return (0); 1429 } 1430 1431 static void 1432 sis_dma_free(struct sis_softc *sc) 1433 { 1434 struct sis_rxdesc *rxd; 1435 struct sis_txdesc *txd; 1436 int i; 1437 1438 /* Destroy DMA maps for RX buffers. */ 1439 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 1440 rxd = &sc->sis_rxdesc[i]; 1441 if (rxd->rx_dmamap) 1442 bus_dmamap_destroy(sc->sis_rx_tag, rxd->rx_dmamap); 1443 } 1444 if (sc->sis_rx_sparemap) 1445 bus_dmamap_destroy(sc->sis_rx_tag, sc->sis_rx_sparemap); 1446 1447 /* Destroy DMA maps for TX buffers. */ 1448 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 1449 txd = &sc->sis_txdesc[i]; 1450 if (txd->tx_dmamap) 1451 bus_dmamap_destroy(sc->sis_tx_tag, txd->tx_dmamap); 1452 } 1453 1454 if (sc->sis_rx_tag) 1455 bus_dma_tag_destroy(sc->sis_rx_tag); 1456 if (sc->sis_tx_tag) 1457 bus_dma_tag_destroy(sc->sis_tx_tag); 1458 1459 /* Destroy RX ring. */ 1460 if (sc->sis_rx_list_map) 1461 bus_dmamap_unload(sc->sis_rx_list_tag, sc->sis_rx_list_map); 1462 if (sc->sis_rx_list_map && sc->sis_rx_list) 1463 bus_dmamem_free(sc->sis_rx_list_tag, sc->sis_rx_list, 1464 sc->sis_rx_list_map); 1465 1466 if (sc->sis_rx_list_tag) 1467 bus_dma_tag_destroy(sc->sis_rx_list_tag); 1468 1469 /* Destroy TX ring. */ 1470 if (sc->sis_tx_list_map) 1471 bus_dmamap_unload(sc->sis_tx_list_tag, sc->sis_tx_list_map); 1472 1473 if (sc->sis_tx_list_map && sc->sis_tx_list) 1474 bus_dmamem_free(sc->sis_tx_list_tag, sc->sis_tx_list, 1475 sc->sis_tx_list_map); 1476 1477 if (sc->sis_tx_list_tag) 1478 bus_dma_tag_destroy(sc->sis_tx_list_tag); 1479 1480 /* Destroy the parent tag. */ 1481 if (sc->sis_parent_tag) 1482 bus_dma_tag_destroy(sc->sis_parent_tag); 1483 } 1484 1485 /* 1486 * Initialize the TX and RX descriptors and allocate mbufs for them. Note that 1487 * we arrange the descriptors in a closed ring, so that the last descriptor 1488 * points back to the first. 1489 */ 1490 static int 1491 sis_ring_init(struct sis_softc *sc) 1492 { 1493 struct sis_rxdesc *rxd; 1494 struct sis_txdesc *txd; 1495 bus_addr_t next; 1496 int error, i; 1497 1498 bzero(&sc->sis_tx_list[0], SIS_TX_LIST_SZ); 1499 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 1500 txd = &sc->sis_txdesc[i]; 1501 txd->tx_m = NULL; 1502 if (i == SIS_TX_LIST_CNT - 1) 1503 next = SIS_TX_RING_ADDR(sc, 0); 1504 else 1505 next = SIS_TX_RING_ADDR(sc, i + 1); 1506 sc->sis_tx_list[i].sis_next = htole32(SIS_ADDR_LO(next)); 1507 } 1508 sc->sis_tx_prod = sc->sis_tx_cons = sc->sis_tx_cnt = 0; 1509 bus_dmamap_sync(sc->sis_tx_list_tag, sc->sis_tx_list_map, 1510 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1511 1512 sc->sis_rx_cons = 0; 1513 bzero(&sc->sis_rx_list[0], SIS_RX_LIST_SZ); 1514 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 1515 rxd = &sc->sis_rxdesc[i]; 1516 rxd->rx_desc = &sc->sis_rx_list[i]; 1517 if (i == SIS_RX_LIST_CNT - 1) 1518 next = SIS_RX_RING_ADDR(sc, 0); 1519 else 1520 next = SIS_RX_RING_ADDR(sc, i + 1); 1521 rxd->rx_desc->sis_next = htole32(SIS_ADDR_LO(next)); 1522 error = sis_newbuf(sc, rxd); 1523 if (error) 1524 return (error); 1525 } 1526 bus_dmamap_sync(sc->sis_rx_list_tag, sc->sis_rx_list_map, 1527 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1528 1529 return (0); 1530 } 1531 1532 /* 1533 * Initialize an RX descriptor and attach an MBUF cluster. 1534 */ 1535 static int 1536 sis_newbuf(struct sis_softc *sc, struct sis_rxdesc *rxd) 1537 { 1538 struct mbuf *m; 1539 bus_dma_segment_t segs[1]; 1540 bus_dmamap_t map; 1541 int nsegs; 1542 1543 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1544 if (m == NULL) 1545 return (ENOBUFS); 1546 m->m_len = m->m_pkthdr.len = SIS_RXLEN; 1547 #ifndef __NO_STRICT_ALIGNMENT 1548 m_adj(m, SIS_RX_BUF_ALIGN); 1549 #endif 1550 1551 if (bus_dmamap_load_mbuf_sg(sc->sis_rx_tag, sc->sis_rx_sparemap, m, 1552 segs, &nsegs, 0) != 0) { 1553 m_freem(m); 1554 return (ENOBUFS); 1555 } 1556 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1557 1558 if (rxd->rx_m != NULL) { 1559 bus_dmamap_sync(sc->sis_rx_tag, rxd->rx_dmamap, 1560 BUS_DMASYNC_POSTREAD); 1561 bus_dmamap_unload(sc->sis_rx_tag, rxd->rx_dmamap); 1562 } 1563 map = rxd->rx_dmamap; 1564 rxd->rx_dmamap = sc->sis_rx_sparemap; 1565 sc->sis_rx_sparemap = map; 1566 bus_dmamap_sync(sc->sis_rx_tag, rxd->rx_dmamap, BUS_DMASYNC_PREREAD); 1567 rxd->rx_m = m; 1568 rxd->rx_desc->sis_ptr = htole32(SIS_ADDR_LO(segs[0].ds_addr)); 1569 rxd->rx_desc->sis_cmdsts = htole32(SIS_RXLEN); 1570 return (0); 1571 } 1572 1573 static __inline void 1574 sis_discard_rxbuf(struct sis_rxdesc *rxd) 1575 { 1576 1577 rxd->rx_desc->sis_cmdsts = htole32(SIS_RXLEN); 1578 } 1579 1580 #ifndef __NO_STRICT_ALIGNMENT 1581 static __inline void 1582 sis_fixup_rx(struct mbuf *m) 1583 { 1584 uint16_t *src, *dst; 1585 int i; 1586 1587 src = mtod(m, uint16_t *); 1588 dst = src - (SIS_RX_BUF_ALIGN - ETHER_ALIGN) / sizeof(*src); 1589 1590 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1591 *dst++ = *src++; 1592 1593 m->m_data -= SIS_RX_BUF_ALIGN - ETHER_ALIGN; 1594 } 1595 #endif 1596 1597 /* 1598 * A frame has been uploaded: pass the resulting mbuf chain up to 1599 * the higher level protocols. 1600 */ 1601 static int 1602 sis_rxeof(struct sis_softc *sc) 1603 { 1604 struct mbuf *m; 1605 struct ifnet *ifp; 1606 struct sis_rxdesc *rxd; 1607 struct sis_desc *cur_rx; 1608 int prog, rx_cons, rx_npkts = 0, total_len; 1609 uint32_t rxstat; 1610 1611 SIS_LOCK_ASSERT(sc); 1612 1613 bus_dmamap_sync(sc->sis_rx_list_tag, sc->sis_rx_list_map, 1614 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1615 1616 rx_cons = sc->sis_rx_cons; 1617 ifp = sc->sis_ifp; 1618 1619 for (prog = 0; (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0; 1620 SIS_INC(rx_cons, SIS_RX_LIST_CNT), prog++) { 1621 #ifdef DEVICE_POLLING 1622 if (ifp->if_capenable & IFCAP_POLLING) { 1623 if (sc->rxcycles <= 0) 1624 break; 1625 sc->rxcycles--; 1626 } 1627 #endif 1628 cur_rx = &sc->sis_rx_list[rx_cons]; 1629 rxstat = le32toh(cur_rx->sis_cmdsts); 1630 if ((rxstat & SIS_CMDSTS_OWN) == 0) 1631 break; 1632 rxd = &sc->sis_rxdesc[rx_cons]; 1633 1634 total_len = (rxstat & SIS_CMDSTS_BUFLEN) - ETHER_CRC_LEN; 1635 if ((ifp->if_capenable & IFCAP_VLAN_MTU) != 0 && 1636 total_len <= (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN - 1637 ETHER_CRC_LEN)) 1638 rxstat &= ~SIS_RXSTAT_GIANT; 1639 if (SIS_RXSTAT_ERROR(rxstat) != 0) { 1640 ifp->if_ierrors++; 1641 if (rxstat & SIS_RXSTAT_COLL) 1642 ifp->if_collisions++; 1643 sis_discard_rxbuf(rxd); 1644 continue; 1645 } 1646 1647 /* Add a new receive buffer to the ring. */ 1648 m = rxd->rx_m; 1649 if (sis_newbuf(sc, rxd) != 0) { 1650 ifp->if_iqdrops++; 1651 sis_discard_rxbuf(rxd); 1652 continue; 1653 } 1654 1655 /* No errors; receive the packet. */ 1656 m->m_pkthdr.len = m->m_len = total_len; 1657 #ifndef __NO_STRICT_ALIGNMENT 1658 /* 1659 * On architectures without alignment problems we try to 1660 * allocate a new buffer for the receive ring, and pass up 1661 * the one where the packet is already, saving the expensive 1662 * copy operation. 1663 */ 1664 sis_fixup_rx(m); 1665 #endif 1666 ifp->if_ipackets++; 1667 m->m_pkthdr.rcvif = ifp; 1668 1669 SIS_UNLOCK(sc); 1670 (*ifp->if_input)(ifp, m); 1671 SIS_LOCK(sc); 1672 rx_npkts++; 1673 } 1674 1675 if (prog > 0) { 1676 sc->sis_rx_cons = rx_cons; 1677 bus_dmamap_sync(sc->sis_rx_list_tag, sc->sis_rx_list_map, 1678 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1679 } 1680 1681 return (rx_npkts); 1682 } 1683 1684 /* 1685 * A frame was downloaded to the chip. It's safe for us to clean up 1686 * the list buffers. 1687 */ 1688 1689 static void 1690 sis_txeof(struct sis_softc *sc) 1691 { 1692 struct ifnet *ifp; 1693 struct sis_desc *cur_tx; 1694 struct sis_txdesc *txd; 1695 uint32_t cons, txstat; 1696 1697 SIS_LOCK_ASSERT(sc); 1698 1699 cons = sc->sis_tx_cons; 1700 if (cons == sc->sis_tx_prod) 1701 return; 1702 1703 ifp = sc->sis_ifp; 1704 bus_dmamap_sync(sc->sis_tx_list_tag, sc->sis_tx_list_map, 1705 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1706 1707 /* 1708 * Go through our tx list and free mbufs for those 1709 * frames that have been transmitted. 1710 */ 1711 for (; cons != sc->sis_tx_prod; SIS_INC(cons, SIS_TX_LIST_CNT)) { 1712 cur_tx = &sc->sis_tx_list[cons]; 1713 txstat = le32toh(cur_tx->sis_cmdsts); 1714 if ((txstat & SIS_CMDSTS_OWN) != 0) 1715 break; 1716 txd = &sc->sis_txdesc[cons]; 1717 if (txd->tx_m != NULL) { 1718 bus_dmamap_sync(sc->sis_tx_tag, txd->tx_dmamap, 1719 BUS_DMASYNC_POSTWRITE); 1720 bus_dmamap_unload(sc->sis_tx_tag, txd->tx_dmamap); 1721 m_freem(txd->tx_m); 1722 txd->tx_m = NULL; 1723 if ((txstat & SIS_CMDSTS_PKT_OK) != 0) { 1724 ifp->if_opackets++; 1725 ifp->if_collisions += 1726 (txstat & SIS_TXSTAT_COLLCNT) >> 16; 1727 } else { 1728 ifp->if_oerrors++; 1729 if (txstat & SIS_TXSTAT_EXCESSCOLLS) 1730 ifp->if_collisions++; 1731 if (txstat & SIS_TXSTAT_OUTOFWINCOLL) 1732 ifp->if_collisions++; 1733 } 1734 } 1735 sc->sis_tx_cnt--; 1736 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1737 } 1738 sc->sis_tx_cons = cons; 1739 if (sc->sis_tx_cnt == 0) 1740 sc->sis_watchdog_timer = 0; 1741 } 1742 1743 static void 1744 sis_tick(void *xsc) 1745 { 1746 struct sis_softc *sc; 1747 struct mii_data *mii; 1748 struct ifnet *ifp; 1749 1750 sc = xsc; 1751 SIS_LOCK_ASSERT(sc); 1752 ifp = sc->sis_ifp; 1753 1754 mii = device_get_softc(sc->sis_miibus); 1755 mii_tick(mii); 1756 sis_watchdog(sc); 1757 if ((sc->sis_flags & SIS_FLAG_LINK) == 0) 1758 sis_miibus_statchg(sc->sis_dev); 1759 callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc); 1760 } 1761 1762 #ifdef DEVICE_POLLING 1763 static poll_handler_t sis_poll; 1764 1765 static int 1766 sis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1767 { 1768 struct sis_softc *sc = ifp->if_softc; 1769 int rx_npkts = 0; 1770 1771 SIS_LOCK(sc); 1772 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1773 SIS_UNLOCK(sc); 1774 return (rx_npkts); 1775 } 1776 1777 /* 1778 * On the sis, reading the status register also clears it. 1779 * So before returning to intr mode we must make sure that all 1780 * possible pending sources of interrupts have been served. 1781 * In practice this means run to completion the *eof routines, 1782 * and then call the interrupt routine 1783 */ 1784 sc->rxcycles = count; 1785 rx_npkts = sis_rxeof(sc); 1786 sis_txeof(sc); 1787 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1788 sis_startl(ifp); 1789 1790 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) { 1791 uint32_t status; 1792 1793 /* Reading the ISR register clears all interrupts. */ 1794 status = CSR_READ_4(sc, SIS_ISR); 1795 1796 if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW)) 1797 ifp->if_ierrors++; 1798 1799 if (status & (SIS_ISR_RX_IDLE)) 1800 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1801 1802 if (status & SIS_ISR_SYSERR) { 1803 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1804 sis_initl(sc); 1805 } 1806 } 1807 1808 SIS_UNLOCK(sc); 1809 return (rx_npkts); 1810 } 1811 #endif /* DEVICE_POLLING */ 1812 1813 static void 1814 sis_intr(void *arg) 1815 { 1816 struct sis_softc *sc; 1817 struct ifnet *ifp; 1818 uint32_t status; 1819 1820 sc = arg; 1821 ifp = sc->sis_ifp; 1822 1823 SIS_LOCK(sc); 1824 #ifdef DEVICE_POLLING 1825 if (ifp->if_capenable & IFCAP_POLLING) { 1826 SIS_UNLOCK(sc); 1827 return; 1828 } 1829 #endif 1830 1831 /* Reading the ISR register clears all interrupts. */ 1832 status = CSR_READ_4(sc, SIS_ISR); 1833 if ((status & SIS_INTRS) == 0) { 1834 /* Not ours. */ 1835 SIS_UNLOCK(sc); 1836 return; 1837 } 1838 1839 /* Disable interrupts. */ 1840 CSR_WRITE_4(sc, SIS_IER, 0); 1841 1842 for (;(status & SIS_INTRS) != 0;) { 1843 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1844 break; 1845 if (status & 1846 (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR | 1847 SIS_ISR_TX_OK | SIS_ISR_TX_IDLE) ) 1848 sis_txeof(sc); 1849 1850 if (status & (SIS_ISR_RX_DESC_OK | SIS_ISR_RX_OK | 1851 SIS_ISR_RX_ERR | SIS_ISR_RX_IDLE)) 1852 sis_rxeof(sc); 1853 1854 if (status & SIS_ISR_RX_OFLOW) 1855 ifp->if_ierrors++; 1856 1857 if (status & (SIS_ISR_RX_IDLE)) 1858 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 1859 1860 if (status & SIS_ISR_SYSERR) { 1861 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1862 sis_initl(sc); 1863 SIS_UNLOCK(sc); 1864 return; 1865 } 1866 status = CSR_READ_4(sc, SIS_ISR); 1867 } 1868 1869 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1870 /* Re-enable interrupts. */ 1871 CSR_WRITE_4(sc, SIS_IER, 1); 1872 1873 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1874 sis_startl(ifp); 1875 } 1876 1877 SIS_UNLOCK(sc); 1878 } 1879 1880 /* 1881 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1882 * pointers to the fragment pointers. 1883 */ 1884 static int 1885 sis_encap(struct sis_softc *sc, struct mbuf **m_head) 1886 { 1887 struct mbuf *m; 1888 struct sis_txdesc *txd; 1889 struct sis_desc *f; 1890 bus_dma_segment_t segs[SIS_MAXTXSEGS]; 1891 bus_dmamap_t map; 1892 int error, i, frag, nsegs, prod; 1893 int padlen; 1894 1895 prod = sc->sis_tx_prod; 1896 txd = &sc->sis_txdesc[prod]; 1897 if ((sc->sis_flags & SIS_FLAG_MANUAL_PAD) != 0 && 1898 (*m_head)->m_pkthdr.len < SIS_MIN_FRAMELEN) { 1899 m = *m_head; 1900 padlen = SIS_MIN_FRAMELEN - m->m_pkthdr.len; 1901 if (M_WRITABLE(m) == 0) { 1902 /* Get a writable copy. */ 1903 m = m_dup(*m_head, M_DONTWAIT); 1904 m_freem(*m_head); 1905 if (m == NULL) { 1906 *m_head = NULL; 1907 return (ENOBUFS); 1908 } 1909 *m_head = m; 1910 } 1911 if (m->m_next != NULL || M_TRAILINGSPACE(m) < padlen) { 1912 m = m_defrag(m, M_DONTWAIT); 1913 if (m == NULL) { 1914 m_freem(*m_head); 1915 *m_head = NULL; 1916 return (ENOBUFS); 1917 } 1918 } 1919 /* 1920 * Manually pad short frames, and zero the pad space 1921 * to avoid leaking data. 1922 */ 1923 bzero(mtod(m, char *) + m->m_pkthdr.len, padlen); 1924 m->m_pkthdr.len += padlen; 1925 m->m_len = m->m_pkthdr.len; 1926 *m_head = m; 1927 } 1928 error = bus_dmamap_load_mbuf_sg(sc->sis_tx_tag, txd->tx_dmamap, 1929 *m_head, segs, &nsegs, 0); 1930 if (error == EFBIG) { 1931 m = m_collapse(*m_head, M_DONTWAIT, SIS_MAXTXSEGS); 1932 if (m == NULL) { 1933 m_freem(*m_head); 1934 *m_head = NULL; 1935 return (ENOBUFS); 1936 } 1937 *m_head = m; 1938 error = bus_dmamap_load_mbuf_sg(sc->sis_tx_tag, txd->tx_dmamap, 1939 *m_head, segs, &nsegs, 0); 1940 if (error != 0) { 1941 m_freem(*m_head); 1942 *m_head = NULL; 1943 return (error); 1944 } 1945 } else if (error != 0) 1946 return (error); 1947 1948 /* Check for descriptor overruns. */ 1949 if (sc->sis_tx_cnt + nsegs > SIS_TX_LIST_CNT - 1) { 1950 bus_dmamap_unload(sc->sis_tx_tag, txd->tx_dmamap); 1951 return (ENOBUFS); 1952 } 1953 1954 bus_dmamap_sync(sc->sis_tx_tag, txd->tx_dmamap, BUS_DMASYNC_PREWRITE); 1955 1956 frag = prod; 1957 for (i = 0; i < nsegs; i++) { 1958 f = &sc->sis_tx_list[prod]; 1959 if (i == 0) 1960 f->sis_cmdsts = htole32(segs[i].ds_len | 1961 SIS_CMDSTS_MORE); 1962 else 1963 f->sis_cmdsts = htole32(segs[i].ds_len | 1964 SIS_CMDSTS_OWN | SIS_CMDSTS_MORE); 1965 f->sis_ptr = htole32(SIS_ADDR_LO(segs[i].ds_addr)); 1966 SIS_INC(prod, SIS_TX_LIST_CNT); 1967 sc->sis_tx_cnt++; 1968 } 1969 1970 /* Update producer index. */ 1971 sc->sis_tx_prod = prod; 1972 1973 /* Remove MORE flag on the last descriptor. */ 1974 prod = (prod - 1) & (SIS_TX_LIST_CNT - 1); 1975 f = &sc->sis_tx_list[prod]; 1976 f->sis_cmdsts &= ~htole32(SIS_CMDSTS_MORE); 1977 1978 /* Lastly transfer ownership of packet to the controller. */ 1979 f = &sc->sis_tx_list[frag]; 1980 f->sis_cmdsts |= htole32(SIS_CMDSTS_OWN); 1981 1982 /* Swap the last and the first dmamaps. */ 1983 map = txd->tx_dmamap; 1984 txd->tx_dmamap = sc->sis_txdesc[prod].tx_dmamap; 1985 sc->sis_txdesc[prod].tx_dmamap = map; 1986 sc->sis_txdesc[prod].tx_m = *m_head; 1987 1988 return (0); 1989 } 1990 1991 static void 1992 sis_start(struct ifnet *ifp) 1993 { 1994 struct sis_softc *sc; 1995 1996 sc = ifp->if_softc; 1997 SIS_LOCK(sc); 1998 sis_startl(ifp); 1999 SIS_UNLOCK(sc); 2000 } 2001 2002 static void 2003 sis_startl(struct ifnet *ifp) 2004 { 2005 struct sis_softc *sc; 2006 struct mbuf *m_head; 2007 int queued; 2008 2009 sc = ifp->if_softc; 2010 2011 SIS_LOCK_ASSERT(sc); 2012 2013 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2014 IFF_DRV_RUNNING || (sc->sis_flags & SIS_FLAG_LINK) == 0) 2015 return; 2016 2017 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2018 sc->sis_tx_cnt < SIS_TX_LIST_CNT - 4;) { 2019 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2020 if (m_head == NULL) 2021 break; 2022 2023 if (sis_encap(sc, &m_head) != 0) { 2024 if (m_head == NULL) 2025 break; 2026 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2027 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2028 break; 2029 } 2030 2031 queued++; 2032 2033 /* 2034 * If there's a BPF listener, bounce a copy of this frame 2035 * to him. 2036 */ 2037 BPF_MTAP(ifp, m_head); 2038 } 2039 2040 if (queued) { 2041 /* Transmit */ 2042 bus_dmamap_sync(sc->sis_tx_list_tag, sc->sis_tx_list_map, 2043 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2044 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE); 2045 2046 /* 2047 * Set a timeout in case the chip goes out to lunch. 2048 */ 2049 sc->sis_watchdog_timer = 5; 2050 } 2051 } 2052 2053 static void 2054 sis_init(void *xsc) 2055 { 2056 struct sis_softc *sc = xsc; 2057 2058 SIS_LOCK(sc); 2059 sis_initl(sc); 2060 SIS_UNLOCK(sc); 2061 } 2062 2063 static void 2064 sis_initl(struct sis_softc *sc) 2065 { 2066 struct ifnet *ifp = sc->sis_ifp; 2067 struct mii_data *mii; 2068 uint8_t *eaddr; 2069 2070 SIS_LOCK_ASSERT(sc); 2071 2072 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2073 return; 2074 2075 /* 2076 * Cancel pending I/O and free all RX/TX buffers. 2077 */ 2078 sis_stop(sc); 2079 /* 2080 * Reset the chip to a known state. 2081 */ 2082 sis_reset(sc); 2083 #ifdef notyet 2084 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr >= NS_SRR_16A) { 2085 /* 2086 * Configure 400usec of interrupt holdoff. This is based 2087 * on emperical tests on a Soekris 4801. 2088 */ 2089 CSR_WRITE_4(sc, NS_IHR, 0x100 | 4); 2090 } 2091 #endif 2092 2093 mii = device_get_softc(sc->sis_miibus); 2094 2095 /* Set MAC address */ 2096 eaddr = IF_LLADDR(sc->sis_ifp); 2097 if (sc->sis_type == SIS_TYPE_83815) { 2098 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0); 2099 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[0] | eaddr[1] << 8); 2100 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1); 2101 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[2] | eaddr[3] << 8); 2102 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2); 2103 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[4] | eaddr[5] << 8); 2104 } else { 2105 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); 2106 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[0] | eaddr[1] << 8); 2107 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1); 2108 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[2] | eaddr[3] << 8); 2109 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); 2110 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[4] | eaddr[5] << 8); 2111 } 2112 2113 /* Init circular TX/RX lists. */ 2114 if (sis_ring_init(sc) != 0) { 2115 device_printf(sc->sis_dev, 2116 "initialization failed: no memory for rx buffers\n"); 2117 sis_stop(sc); 2118 return; 2119 } 2120 2121 if (sc->sis_type == SIS_TYPE_83815 || sc->sis_type == SIS_TYPE_83816) { 2122 if (sc->sis_manual_pad != 0) 2123 sc->sis_flags |= SIS_FLAG_MANUAL_PAD; 2124 else 2125 sc->sis_flags &= ~SIS_FLAG_MANUAL_PAD; 2126 } 2127 2128 /* 2129 * Short Cable Receive Errors (MP21.E) 2130 * also: Page 78 of the DP83815 data sheet (september 2002 version) 2131 * recommends the following register settings "for optimum 2132 * performance." for rev 15C. Set this also for 15D parts as 2133 * they require it in practice. 2134 */ 2135 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr <= NS_SRR_15D) { 2136 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); 2137 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C); 2138 /* set val for c2 */ 2139 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000); 2140 /* load/kill c2 */ 2141 CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040); 2142 /* rais SD off, from 4 to c */ 2143 CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C); 2144 CSR_WRITE_4(sc, NS_PHY_PAGE, 0); 2145 } 2146 2147 sis_rxfilter(sc); 2148 /* Turn the receive filter on */ 2149 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE); 2150 2151 /* 2152 * Load the address of the RX and TX lists. 2153 */ 2154 CSR_WRITE_4(sc, SIS_RX_LISTPTR, SIS_ADDR_LO(sc->sis_rx_paddr)); 2155 CSR_WRITE_4(sc, SIS_TX_LISTPTR, SIS_ADDR_LO(sc->sis_tx_paddr)); 2156 2157 /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of 2158 * the PCI bus. When this bit is set, the Max DMA Burst Size 2159 * for TX/RX DMA should be no larger than 16 double words. 2160 */ 2161 if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN) { 2162 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64); 2163 } else { 2164 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256); 2165 } 2166 2167 /* Accept Long Packets for VLAN support */ 2168 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER); 2169 2170 /* 2171 * Assume 100Mbps link, actual MAC configuration is done 2172 * after getting a valid link. 2173 */ 2174 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100); 2175 2176 /* 2177 * Enable interrupts. 2178 */ 2179 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS); 2180 #ifdef DEVICE_POLLING 2181 /* 2182 * ... only enable interrupts if we are not polling, make sure 2183 * they are off otherwise. 2184 */ 2185 if (ifp->if_capenable & IFCAP_POLLING) 2186 CSR_WRITE_4(sc, SIS_IER, 0); 2187 else 2188 #endif 2189 CSR_WRITE_4(sc, SIS_IER, 1); 2190 2191 /* Clear MAC disable. */ 2192 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE | SIS_CSR_RX_DISABLE); 2193 2194 sc->sis_flags &= ~SIS_FLAG_LINK; 2195 mii_mediachg(mii); 2196 2197 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2198 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2199 2200 callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc); 2201 } 2202 2203 /* 2204 * Set media options. 2205 */ 2206 static int 2207 sis_ifmedia_upd(struct ifnet *ifp) 2208 { 2209 struct sis_softc *sc; 2210 struct mii_data *mii; 2211 struct mii_softc *miisc; 2212 int error; 2213 2214 sc = ifp->if_softc; 2215 2216 SIS_LOCK(sc); 2217 mii = device_get_softc(sc->sis_miibus); 2218 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 2219 PHY_RESET(miisc); 2220 error = mii_mediachg(mii); 2221 SIS_UNLOCK(sc); 2222 2223 return (error); 2224 } 2225 2226 /* 2227 * Report current media status. 2228 */ 2229 static void 2230 sis_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2231 { 2232 struct sis_softc *sc; 2233 struct mii_data *mii; 2234 2235 sc = ifp->if_softc; 2236 2237 SIS_LOCK(sc); 2238 mii = device_get_softc(sc->sis_miibus); 2239 mii_pollstat(mii); 2240 SIS_UNLOCK(sc); 2241 ifmr->ifm_active = mii->mii_media_active; 2242 ifmr->ifm_status = mii->mii_media_status; 2243 } 2244 2245 static int 2246 sis_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2247 { 2248 struct sis_softc *sc = ifp->if_softc; 2249 struct ifreq *ifr = (struct ifreq *) data; 2250 struct mii_data *mii; 2251 int error = 0, mask; 2252 2253 switch (command) { 2254 case SIOCSIFFLAGS: 2255 SIS_LOCK(sc); 2256 if (ifp->if_flags & IFF_UP) { 2257 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 2258 ((ifp->if_flags ^ sc->sis_if_flags) & 2259 (IFF_PROMISC | IFF_ALLMULTI)) != 0) 2260 sis_rxfilter(sc); 2261 else 2262 sis_initl(sc); 2263 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2264 sis_stop(sc); 2265 sc->sis_if_flags = ifp->if_flags; 2266 SIS_UNLOCK(sc); 2267 break; 2268 case SIOCADDMULTI: 2269 case SIOCDELMULTI: 2270 SIS_LOCK(sc); 2271 sis_rxfilter(sc); 2272 SIS_UNLOCK(sc); 2273 break; 2274 case SIOCGIFMEDIA: 2275 case SIOCSIFMEDIA: 2276 mii = device_get_softc(sc->sis_miibus); 2277 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2278 break; 2279 case SIOCSIFCAP: 2280 SIS_LOCK(sc); 2281 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2282 #ifdef DEVICE_POLLING 2283 if ((mask & IFCAP_POLLING) != 0 && 2284 (IFCAP_POLLING & ifp->if_capabilities) != 0) { 2285 ifp->if_capenable ^= IFCAP_POLLING; 2286 if ((IFCAP_POLLING & ifp->if_capenable) != 0) { 2287 error = ether_poll_register(sis_poll, ifp); 2288 if (error != 0) { 2289 SIS_UNLOCK(sc); 2290 break; 2291 } 2292 /* Disable interrupts. */ 2293 CSR_WRITE_4(sc, SIS_IER, 0); 2294 } else { 2295 error = ether_poll_deregister(ifp); 2296 /* Enable interrupts. */ 2297 CSR_WRITE_4(sc, SIS_IER, 1); 2298 } 2299 } 2300 #endif /* DEVICE_POLLING */ 2301 if ((mask & IFCAP_WOL) != 0 && 2302 (ifp->if_capabilities & IFCAP_WOL) != 0) { 2303 if ((mask & IFCAP_WOL_UCAST) != 0) 2304 ifp->if_capenable ^= IFCAP_WOL_UCAST; 2305 if ((mask & IFCAP_WOL_MCAST) != 0) 2306 ifp->if_capenable ^= IFCAP_WOL_MCAST; 2307 if ((mask & IFCAP_WOL_MAGIC) != 0) 2308 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2309 } 2310 SIS_UNLOCK(sc); 2311 break; 2312 default: 2313 error = ether_ioctl(ifp, command, data); 2314 break; 2315 } 2316 2317 return (error); 2318 } 2319 2320 static void 2321 sis_watchdog(struct sis_softc *sc) 2322 { 2323 2324 SIS_LOCK_ASSERT(sc); 2325 2326 if (sc->sis_watchdog_timer == 0 || --sc->sis_watchdog_timer >0) 2327 return; 2328 2329 device_printf(sc->sis_dev, "watchdog timeout\n"); 2330 sc->sis_ifp->if_oerrors++; 2331 2332 sc->sis_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2333 sis_initl(sc); 2334 2335 if (!IFQ_DRV_IS_EMPTY(&sc->sis_ifp->if_snd)) 2336 sis_startl(sc->sis_ifp); 2337 } 2338 2339 /* 2340 * Stop the adapter and free any mbufs allocated to the 2341 * RX and TX lists. 2342 */ 2343 static void 2344 sis_stop(struct sis_softc *sc) 2345 { 2346 struct ifnet *ifp; 2347 struct sis_rxdesc *rxd; 2348 struct sis_txdesc *txd; 2349 int i; 2350 2351 SIS_LOCK_ASSERT(sc); 2352 2353 ifp = sc->sis_ifp; 2354 sc->sis_watchdog_timer = 0; 2355 2356 callout_stop(&sc->sis_stat_ch); 2357 2358 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2359 CSR_WRITE_4(sc, SIS_IER, 0); 2360 CSR_WRITE_4(sc, SIS_IMR, 0); 2361 CSR_READ_4(sc, SIS_ISR); /* clear any interrupts already pending */ 2362 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); 2363 DELAY(1000); 2364 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0); 2365 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0); 2366 2367 sc->sis_flags &= ~SIS_FLAG_LINK; 2368 2369 /* 2370 * Free data in the RX lists. 2371 */ 2372 for (i = 0; i < SIS_RX_LIST_CNT; i++) { 2373 rxd = &sc->sis_rxdesc[i]; 2374 if (rxd->rx_m != NULL) { 2375 bus_dmamap_sync(sc->sis_rx_tag, rxd->rx_dmamap, 2376 BUS_DMASYNC_POSTREAD); 2377 bus_dmamap_unload(sc->sis_rx_tag, rxd->rx_dmamap); 2378 m_freem(rxd->rx_m); 2379 rxd->rx_m = NULL; 2380 } 2381 } 2382 2383 /* 2384 * Free the TX list buffers. 2385 */ 2386 for (i = 0; i < SIS_TX_LIST_CNT; i++) { 2387 txd = &sc->sis_txdesc[i]; 2388 if (txd->tx_m != NULL) { 2389 bus_dmamap_sync(sc->sis_tx_tag, txd->tx_dmamap, 2390 BUS_DMASYNC_POSTWRITE); 2391 bus_dmamap_unload(sc->sis_tx_tag, txd->tx_dmamap); 2392 m_freem(txd->tx_m); 2393 txd->tx_m = NULL; 2394 } 2395 } 2396 } 2397 2398 /* 2399 * Stop all chip I/O so that the kernel's probe routines don't 2400 * get confused by errant DMAs when rebooting. 2401 */ 2402 static int 2403 sis_shutdown(device_t dev) 2404 { 2405 2406 return (sis_suspend(dev)); 2407 } 2408 2409 static int 2410 sis_suspend(device_t dev) 2411 { 2412 struct sis_softc *sc; 2413 2414 sc = device_get_softc(dev); 2415 SIS_LOCK(sc); 2416 sis_stop(sc); 2417 sis_wol(sc); 2418 SIS_UNLOCK(sc); 2419 return (0); 2420 } 2421 2422 static int 2423 sis_resume(device_t dev) 2424 { 2425 struct sis_softc *sc; 2426 struct ifnet *ifp; 2427 2428 sc = device_get_softc(dev); 2429 SIS_LOCK(sc); 2430 ifp = sc->sis_ifp; 2431 if ((ifp->if_flags & IFF_UP) != 0) { 2432 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2433 sis_initl(sc); 2434 } 2435 SIS_UNLOCK(sc); 2436 return (0); 2437 } 2438 2439 static void 2440 sis_wol(struct sis_softc *sc) 2441 { 2442 struct ifnet *ifp; 2443 uint32_t val; 2444 uint16_t pmstat; 2445 int pmc; 2446 2447 ifp = sc->sis_ifp; 2448 if ((ifp->if_capenable & IFCAP_WOL) == 0) 2449 return; 2450 2451 if (sc->sis_type == SIS_TYPE_83815) { 2452 /* Reset RXDP. */ 2453 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0); 2454 2455 /* Configure WOL events. */ 2456 CSR_READ_4(sc, NS_WCSR); 2457 val = 0; 2458 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0) 2459 val |= NS_WCSR_WAKE_UCAST; 2460 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 2461 val |= NS_WCSR_WAKE_MCAST; 2462 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 2463 val |= NS_WCSR_WAKE_MAGIC; 2464 CSR_WRITE_4(sc, NS_WCSR, val); 2465 /* Enable PME and clear PMESTS. */ 2466 val = CSR_READ_4(sc, NS_CLKRUN); 2467 val |= NS_CLKRUN_PMEENB | NS_CLKRUN_PMESTS; 2468 CSR_WRITE_4(sc, NS_CLKRUN, val); 2469 /* Enable silent RX mode. */ 2470 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); 2471 } else { 2472 if (pci_find_cap(sc->sis_dev, PCIY_PMG, &pmc) != 0) 2473 return; 2474 val = 0; 2475 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 2476 val |= SIS_PWRMAN_WOL_MAGIC; 2477 CSR_WRITE_4(sc, SIS_PWRMAN_CTL, val); 2478 /* Request PME. */ 2479 pmstat = pci_read_config(sc->sis_dev, 2480 pmc + PCIR_POWER_STATUS, 2); 2481 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2482 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 2483 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2484 pci_write_config(sc->sis_dev, 2485 pmc + PCIR_POWER_STATUS, pmstat, 2); 2486 } 2487 } 2488 2489 static void 2490 sis_add_sysctls(struct sis_softc *sc) 2491 { 2492 struct sysctl_ctx_list *ctx; 2493 struct sysctl_oid_list *children; 2494 char tn[32]; 2495 int unit; 2496 2497 ctx = device_get_sysctl_ctx(sc->sis_dev); 2498 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->sis_dev)); 2499 2500 unit = device_get_unit(sc->sis_dev); 2501 /* 2502 * Unlike most other controllers, NS DP83815/DP83816 controllers 2503 * seem to pad with 0xFF when it encounter short frames. According 2504 * to RFC 1042 the pad bytes should be 0x00. Turning this tunable 2505 * on will have driver pad manully but it's disabled by default 2506 * because it will consume extra CPU cycles for short frames. 2507 */ 2508 sc->sis_manual_pad = 0; 2509 snprintf(tn, sizeof(tn), "dev.sis.%d.manual_pad", unit); 2510 TUNABLE_INT_FETCH(tn, &sc->sis_manual_pad); 2511 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "manual_pad", 2512 CTLFLAG_RW, &sc->sis_manual_pad, 0, "Manually pad short frames"); 2513 } 2514 2515 static device_method_t sis_methods[] = { 2516 /* Device interface */ 2517 DEVMETHOD(device_probe, sis_probe), 2518 DEVMETHOD(device_attach, sis_attach), 2519 DEVMETHOD(device_detach, sis_detach), 2520 DEVMETHOD(device_shutdown, sis_shutdown), 2521 DEVMETHOD(device_suspend, sis_suspend), 2522 DEVMETHOD(device_resume, sis_resume), 2523 2524 /* bus interface */ 2525 DEVMETHOD(bus_print_child, bus_generic_print_child), 2526 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 2527 2528 /* MII interface */ 2529 DEVMETHOD(miibus_readreg, sis_miibus_readreg), 2530 DEVMETHOD(miibus_writereg, sis_miibus_writereg), 2531 DEVMETHOD(miibus_statchg, sis_miibus_statchg), 2532 2533 { 0, 0 } 2534 }; 2535 2536 static driver_t sis_driver = { 2537 "sis", 2538 sis_methods, 2539 sizeof(struct sis_softc) 2540 }; 2541 2542 static devclass_t sis_devclass; 2543 2544 DRIVER_MODULE(sis, pci, sis_driver, sis_devclass, 0, 0); 2545 DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0); 2546