1 /*- 2 * Copyright (c) 2010-2016 Solarflare Communications Inc. 3 * All rights reserved. 4 * 5 * This software was developed in part by Philip Paeps under contract for 6 * Solarflare Communications, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright notice, 12 * this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright notice, 14 * this list of conditions and the following disclaimer in the documentation 15 * and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 19 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 21 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 22 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 23 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 24 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 25 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 26 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 27 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * The views and conclusions contained in the software and documentation are 30 * those of the authors and should not be interpreted as representing official 31 * policies, either expressed or implied, of the FreeBSD Project. 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 #include <sys/types.h> 38 #include <sys/limits.h> 39 #include <net/ethernet.h> 40 #include <net/if_dl.h> 41 42 #include "common/efx.h" 43 44 #include "sfxge.h" 45 46 static int sfxge_phy_cap_mask(struct sfxge_softc *, int, uint32_t *); 47 48 static int 49 sfxge_mac_stat_update(struct sfxge_softc *sc) 50 { 51 struct sfxge_port *port = &sc->port; 52 efsys_mem_t *esmp = &(port->mac_stats.dma_buf); 53 clock_t now; 54 unsigned int count; 55 int rc; 56 57 SFXGE_PORT_LOCK_ASSERT_OWNED(port); 58 59 if (__predict_false(port->init_state != SFXGE_PORT_STARTED)) { 60 rc = 0; 61 goto out; 62 } 63 64 now = ticks; 65 if ((unsigned int)(now - port->mac_stats.update_time) < (unsigned int)hz) { 66 rc = 0; 67 goto out; 68 } 69 70 port->mac_stats.update_time = now; 71 72 /* If we're unlucky enough to read statistics wduring the DMA, wait 73 * up to 10ms for it to finish (typically takes <500us) */ 74 for (count = 0; count < 100; ++count) { 75 EFSYS_PROBE1(wait, unsigned int, count); 76 77 /* Try to update the cached counters */ 78 if ((rc = efx_mac_stats_update(sc->enp, esmp, 79 port->mac_stats.decode_buf, NULL)) != EAGAIN) 80 goto out; 81 82 DELAY(100); 83 } 84 85 rc = ETIMEDOUT; 86 out: 87 return (rc); 88 } 89 90 uint64_t 91 sfxge_get_counter(struct ifnet *ifp, ift_counter c) 92 { 93 struct sfxge_softc *sc = ifp->if_softc; 94 uint64_t *mac_stats; 95 uint64_t val; 96 97 SFXGE_PORT_LOCK(&sc->port); 98 99 /* Ignore error and use old values */ 100 (void)sfxge_mac_stat_update(sc); 101 102 mac_stats = (uint64_t *)sc->port.mac_stats.decode_buf; 103 104 switch (c) { 105 case IFCOUNTER_IPACKETS: 106 val = mac_stats[EFX_MAC_RX_PKTS]; 107 break; 108 case IFCOUNTER_IERRORS: 109 val = mac_stats[EFX_MAC_RX_ERRORS]; 110 break; 111 case IFCOUNTER_OPACKETS: 112 val = mac_stats[EFX_MAC_TX_PKTS]; 113 break; 114 case IFCOUNTER_OERRORS: 115 val = mac_stats[EFX_MAC_TX_ERRORS]; 116 break; 117 case IFCOUNTER_COLLISIONS: 118 val = mac_stats[EFX_MAC_TX_SGL_COL_PKTS] + 119 mac_stats[EFX_MAC_TX_MULT_COL_PKTS] + 120 mac_stats[EFX_MAC_TX_EX_COL_PKTS] + 121 mac_stats[EFX_MAC_TX_LATE_COL_PKTS]; 122 break; 123 case IFCOUNTER_IBYTES: 124 val = mac_stats[EFX_MAC_RX_OCTETS]; 125 break; 126 case IFCOUNTER_OBYTES: 127 val = mac_stats[EFX_MAC_TX_OCTETS]; 128 break; 129 case IFCOUNTER_OMCASTS: 130 val = mac_stats[EFX_MAC_TX_MULTICST_PKTS] + 131 mac_stats[EFX_MAC_TX_BRDCST_PKTS]; 132 break; 133 case IFCOUNTER_OQDROPS: 134 SFXGE_PORT_UNLOCK(&sc->port); 135 return (sfxge_tx_get_drops(sc)); 136 case IFCOUNTER_IMCASTS: 137 /* if_imcasts is maintained in net/if_ethersubr.c */ 138 case IFCOUNTER_IQDROPS: 139 /* if_iqdrops is maintained in net/if_ethersubr.c */ 140 case IFCOUNTER_NOPROTO: 141 /* if_noproto is maintained in net/if_ethersubr.c */ 142 default: 143 SFXGE_PORT_UNLOCK(&sc->port); 144 return (if_get_counter_default(ifp, c)); 145 } 146 147 SFXGE_PORT_UNLOCK(&sc->port); 148 149 return (val); 150 } 151 152 static int 153 sfxge_mac_stat_handler(SYSCTL_HANDLER_ARGS) 154 { 155 struct sfxge_softc *sc = arg1; 156 unsigned int id = arg2; 157 int rc; 158 uint64_t val; 159 160 SFXGE_PORT_LOCK(&sc->port); 161 if ((rc = sfxge_mac_stat_update(sc)) == 0) 162 val = ((uint64_t *)sc->port.mac_stats.decode_buf)[id]; 163 SFXGE_PORT_UNLOCK(&sc->port); 164 165 if (rc == 0) 166 rc = SYSCTL_OUT(req, &val, sizeof(val)); 167 return (rc); 168 } 169 170 static void 171 sfxge_mac_stat_init(struct sfxge_softc *sc) 172 { 173 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->dev); 174 struct sysctl_oid_list *stat_list; 175 unsigned int id; 176 const char *name; 177 178 stat_list = SYSCTL_CHILDREN(sc->stats_node); 179 180 /* Initialise the named stats */ 181 for (id = 0; id < EFX_MAC_NSTATS; id++) { 182 name = efx_mac_stat_name(sc->enp, id); 183 SYSCTL_ADD_PROC( 184 ctx, stat_list, 185 OID_AUTO, name, CTLTYPE_U64|CTLFLAG_RD, 186 sc, id, sfxge_mac_stat_handler, "Q", 187 ""); 188 } 189 } 190 191 #ifdef SFXGE_HAVE_PAUSE_MEDIAOPTS 192 193 static unsigned int 194 sfxge_port_wanted_fc(struct sfxge_softc *sc) 195 { 196 struct ifmedia_entry *ifm = sc->media.ifm_cur; 197 198 if (ifm->ifm_media == (IFM_ETHER | IFM_AUTO)) 199 return (EFX_FCNTL_RESPOND | EFX_FCNTL_GENERATE); 200 return (((ifm->ifm_media & IFM_ETH_RXPAUSE) ? EFX_FCNTL_RESPOND : 0) | 201 ((ifm->ifm_media & IFM_ETH_TXPAUSE) ? EFX_FCNTL_GENERATE : 0)); 202 } 203 204 static unsigned int 205 sfxge_port_link_fc_ifm(struct sfxge_softc *sc) 206 { 207 unsigned int wanted_fc, link_fc; 208 209 efx_mac_fcntl_get(sc->enp, &wanted_fc, &link_fc); 210 return ((link_fc & EFX_FCNTL_RESPOND) ? IFM_ETH_RXPAUSE : 0) | 211 ((link_fc & EFX_FCNTL_GENERATE) ? IFM_ETH_TXPAUSE : 0); 212 } 213 214 #else /* !SFXGE_HAVE_PAUSE_MEDIAOPTS */ 215 216 static unsigned int 217 sfxge_port_wanted_fc(struct sfxge_softc *sc) 218 { 219 return (sc->port.wanted_fc); 220 } 221 222 static unsigned int 223 sfxge_port_link_fc_ifm(struct sfxge_softc *sc) 224 { 225 return (0); 226 } 227 228 static int 229 sfxge_port_wanted_fc_handler(SYSCTL_HANDLER_ARGS) 230 { 231 struct sfxge_softc *sc; 232 struct sfxge_port *port; 233 unsigned int fcntl; 234 int error; 235 236 sc = arg1; 237 port = &sc->port; 238 239 if (req->newptr != NULL) { 240 if ((error = SYSCTL_IN(req, &fcntl, sizeof(fcntl))) != 0) 241 return (error); 242 243 SFXGE_PORT_LOCK(port); 244 245 if (port->wanted_fc != fcntl) { 246 if (port->init_state == SFXGE_PORT_STARTED) 247 error = efx_mac_fcntl_set(sc->enp, 248 port->wanted_fc, 249 B_TRUE); 250 if (error == 0) 251 port->wanted_fc = fcntl; 252 } 253 254 SFXGE_PORT_UNLOCK(port); 255 } else { 256 SFXGE_PORT_LOCK(port); 257 fcntl = port->wanted_fc; 258 SFXGE_PORT_UNLOCK(port); 259 260 error = SYSCTL_OUT(req, &fcntl, sizeof(fcntl)); 261 } 262 263 return (error); 264 } 265 266 static int 267 sfxge_port_link_fc_handler(SYSCTL_HANDLER_ARGS) 268 { 269 struct sfxge_softc *sc; 270 struct sfxge_port *port; 271 unsigned int wanted_fc, link_fc; 272 273 sc = arg1; 274 port = &sc->port; 275 276 SFXGE_PORT_LOCK(port); 277 if (__predict_true(port->init_state == SFXGE_PORT_STARTED) && 278 SFXGE_LINK_UP(sc)) 279 efx_mac_fcntl_get(sc->enp, &wanted_fc, &link_fc); 280 else 281 link_fc = 0; 282 SFXGE_PORT_UNLOCK(port); 283 284 return (SYSCTL_OUT(req, &link_fc, sizeof(link_fc))); 285 } 286 287 #endif /* SFXGE_HAVE_PAUSE_MEDIAOPTS */ 288 289 static const uint64_t sfxge_link_baudrate[EFX_LINK_NMODES] = { 290 [EFX_LINK_10HDX] = IF_Mbps(10), 291 [EFX_LINK_10FDX] = IF_Mbps(10), 292 [EFX_LINK_100HDX] = IF_Mbps(100), 293 [EFX_LINK_100FDX] = IF_Mbps(100), 294 [EFX_LINK_1000HDX] = IF_Gbps(1), 295 [EFX_LINK_1000FDX] = IF_Gbps(1), 296 [EFX_LINK_10000FDX] = IF_Gbps(10), 297 [EFX_LINK_40000FDX] = IF_Gbps(40), 298 }; 299 300 void 301 sfxge_mac_link_update(struct sfxge_softc *sc, efx_link_mode_t mode) 302 { 303 struct sfxge_port *port; 304 int link_state; 305 306 port = &sc->port; 307 308 if (port->link_mode == mode) 309 return; 310 311 port->link_mode = mode; 312 313 /* Push link state update to the OS */ 314 link_state = (SFXGE_LINK_UP(sc) ? LINK_STATE_UP : LINK_STATE_DOWN); 315 sc->ifnet->if_baudrate = sfxge_link_baudrate[port->link_mode]; 316 if_link_state_change(sc->ifnet, link_state); 317 } 318 319 static void 320 sfxge_mac_poll_work(void *arg, int npending) 321 { 322 struct sfxge_softc *sc; 323 efx_nic_t *enp; 324 struct sfxge_port *port; 325 efx_link_mode_t mode; 326 327 sc = (struct sfxge_softc *)arg; 328 enp = sc->enp; 329 port = &sc->port; 330 331 SFXGE_PORT_LOCK(port); 332 333 if (__predict_false(port->init_state != SFXGE_PORT_STARTED)) 334 goto done; 335 336 /* This may sleep waiting for MCDI completion */ 337 (void)efx_port_poll(enp, &mode); 338 sfxge_mac_link_update(sc, mode); 339 340 done: 341 SFXGE_PORT_UNLOCK(port); 342 } 343 344 static int 345 sfxge_mac_multicast_list_set(struct sfxge_softc *sc) 346 { 347 struct ifnet *ifp = sc->ifnet; 348 struct sfxge_port *port = &sc->port; 349 uint8_t *mcast_addr = port->mcast_addrs; 350 struct ifmultiaddr *ifma; 351 struct sockaddr_dl *sa; 352 int rc = 0; 353 354 mtx_assert(&port->lock, MA_OWNED); 355 356 port->mcast_count = 0; 357 if_maddr_rlock(ifp); 358 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 359 if (ifma->ifma_addr->sa_family == AF_LINK) { 360 if (port->mcast_count == EFX_MAC_MULTICAST_LIST_MAX) { 361 device_printf(sc->dev, 362 "Too many multicast addresses\n"); 363 rc = EINVAL; 364 break; 365 } 366 367 sa = (struct sockaddr_dl *)ifma->ifma_addr; 368 memcpy(mcast_addr, LLADDR(sa), EFX_MAC_ADDR_LEN); 369 mcast_addr += EFX_MAC_ADDR_LEN; 370 ++port->mcast_count; 371 } 372 } 373 if_maddr_runlock(ifp); 374 375 if (rc == 0) { 376 rc = efx_mac_multicast_list_set(sc->enp, port->mcast_addrs, 377 port->mcast_count); 378 if (rc != 0) 379 device_printf(sc->dev, 380 "Cannot set multicast address list\n"); 381 } 382 383 return (rc); 384 } 385 386 static int 387 sfxge_mac_filter_set_locked(struct sfxge_softc *sc) 388 { 389 struct ifnet *ifp = sc->ifnet; 390 struct sfxge_port *port = &sc->port; 391 boolean_t all_mulcst; 392 int rc; 393 394 mtx_assert(&port->lock, MA_OWNED); 395 396 all_mulcst = !!(ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)); 397 398 rc = sfxge_mac_multicast_list_set(sc); 399 /* Fallback to all multicast if cannot set multicast list */ 400 if (rc != 0) 401 all_mulcst = B_TRUE; 402 403 rc = efx_mac_filter_set(sc->enp, !!(ifp->if_flags & IFF_PROMISC), 404 (port->mcast_count > 0), all_mulcst, B_TRUE); 405 406 return (rc); 407 } 408 409 int 410 sfxge_mac_filter_set(struct sfxge_softc *sc) 411 { 412 struct sfxge_port *port = &sc->port; 413 int rc; 414 415 SFXGE_PORT_LOCK(port); 416 /* 417 * The function may be called without softc_lock held in the 418 * case of SIOCADDMULTI and SIOCDELMULTI ioctls. ioctl handler 419 * checks IFF_DRV_RUNNING flag which implies port started, but 420 * it is not guaranteed to remain. softc_lock shared lock can't 421 * be held in the case of these ioctls processing, since it 422 * results in failure where kernel complains that non-sleepable 423 * lock is held in sleeping thread. Both problems are repeatable 424 * on LAG with LACP proto bring up. 425 */ 426 if (__predict_true(port->init_state == SFXGE_PORT_STARTED)) 427 rc = sfxge_mac_filter_set_locked(sc); 428 else 429 rc = 0; 430 SFXGE_PORT_UNLOCK(port); 431 return (rc); 432 } 433 434 void 435 sfxge_port_stop(struct sfxge_softc *sc) 436 { 437 struct sfxge_port *port; 438 efx_nic_t *enp; 439 440 port = &sc->port; 441 enp = sc->enp; 442 443 SFXGE_PORT_LOCK(port); 444 445 KASSERT(port->init_state == SFXGE_PORT_STARTED, 446 ("port not started")); 447 448 port->init_state = SFXGE_PORT_INITIALIZED; 449 450 port->mac_stats.update_time = 0; 451 452 /* This may call MCDI */ 453 (void)efx_mac_drain(enp, B_TRUE); 454 455 (void)efx_mac_stats_periodic(enp, &port->mac_stats.dma_buf, 0, B_FALSE); 456 457 port->link_mode = EFX_LINK_UNKNOWN; 458 459 /* Destroy the common code port object. */ 460 efx_port_fini(enp); 461 462 efx_filter_fini(enp); 463 464 SFXGE_PORT_UNLOCK(port); 465 } 466 467 int 468 sfxge_port_start(struct sfxge_softc *sc) 469 { 470 uint8_t mac_addr[ETHER_ADDR_LEN]; 471 struct ifnet *ifp = sc->ifnet; 472 struct sfxge_port *port; 473 efx_nic_t *enp; 474 size_t pdu; 475 int rc; 476 uint32_t phy_cap_mask; 477 478 port = &sc->port; 479 enp = sc->enp; 480 481 SFXGE_PORT_LOCK(port); 482 483 KASSERT(port->init_state == SFXGE_PORT_INITIALIZED, 484 ("port not initialized")); 485 486 /* Initialise the required filtering */ 487 if ((rc = efx_filter_init(enp)) != 0) 488 goto fail_filter_init; 489 490 /* Initialize the port object in the common code. */ 491 if ((rc = efx_port_init(sc->enp)) != 0) 492 goto fail; 493 494 /* Set the SDU */ 495 pdu = EFX_MAC_PDU(ifp->if_mtu); 496 if ((rc = efx_mac_pdu_set(enp, pdu)) != 0) 497 goto fail2; 498 499 if ((rc = efx_mac_fcntl_set(enp, sfxge_port_wanted_fc(sc), B_TRUE)) 500 != 0) 501 goto fail3; 502 503 /* Set the unicast address */ 504 if_addr_rlock(ifp); 505 bcopy(LLADDR((struct sockaddr_dl *)ifp->if_addr->ifa_addr), 506 mac_addr, sizeof(mac_addr)); 507 if_addr_runlock(ifp); 508 if ((rc = efx_mac_addr_set(enp, mac_addr)) != 0) 509 goto fail4; 510 511 sfxge_mac_filter_set_locked(sc); 512 513 /* Update MAC stats by DMA every second */ 514 if ((rc = efx_mac_stats_periodic(enp, &port->mac_stats.dma_buf, 515 1000, B_FALSE)) != 0) 516 goto fail6; 517 518 if ((rc = efx_mac_drain(enp, B_FALSE)) != 0) 519 goto fail8; 520 521 if ((rc = sfxge_phy_cap_mask(sc, sc->media.ifm_cur->ifm_media, 522 &phy_cap_mask)) != 0) 523 goto fail9; 524 525 if ((rc = efx_phy_adv_cap_set(sc->enp, phy_cap_mask)) != 0) 526 goto fail10; 527 528 port->init_state = SFXGE_PORT_STARTED; 529 530 /* Single poll in case there were missing initial events */ 531 SFXGE_PORT_UNLOCK(port); 532 sfxge_mac_poll_work(sc, 0); 533 534 return (0); 535 536 fail10: 537 fail9: 538 (void)efx_mac_drain(enp, B_TRUE); 539 fail8: 540 (void)efx_mac_stats_periodic(enp, &port->mac_stats.dma_buf, 0, B_FALSE); 541 fail6: 542 fail4: 543 fail3: 544 545 fail2: 546 efx_port_fini(enp); 547 fail: 548 efx_filter_fini(enp); 549 fail_filter_init: 550 SFXGE_PORT_UNLOCK(port); 551 552 return (rc); 553 } 554 555 static int 556 sfxge_phy_stat_update(struct sfxge_softc *sc) 557 { 558 struct sfxge_port *port = &sc->port; 559 efsys_mem_t *esmp = &port->phy_stats.dma_buf; 560 clock_t now; 561 unsigned int count; 562 int rc; 563 564 SFXGE_PORT_LOCK_ASSERT_OWNED(port); 565 566 if (__predict_false(port->init_state != SFXGE_PORT_STARTED)) { 567 rc = 0; 568 goto out; 569 } 570 571 now = ticks; 572 if ((unsigned int)(now - port->phy_stats.update_time) < (unsigned int)hz) { 573 rc = 0; 574 goto out; 575 } 576 577 port->phy_stats.update_time = now; 578 579 /* If we're unlucky enough to read statistics wduring the DMA, wait 580 * up to 10ms for it to finish (typically takes <500us) */ 581 for (count = 0; count < 100; ++count) { 582 EFSYS_PROBE1(wait, unsigned int, count); 583 584 /* Synchronize the DMA memory for reading */ 585 bus_dmamap_sync(esmp->esm_tag, esmp->esm_map, 586 BUS_DMASYNC_POSTREAD); 587 588 /* Try to update the cached counters */ 589 if ((rc = efx_phy_stats_update(sc->enp, esmp, 590 port->phy_stats.decode_buf)) != EAGAIN) 591 goto out; 592 593 DELAY(100); 594 } 595 596 rc = ETIMEDOUT; 597 out: 598 return (rc); 599 } 600 601 static int 602 sfxge_phy_stat_handler(SYSCTL_HANDLER_ARGS) 603 { 604 struct sfxge_softc *sc = arg1; 605 unsigned int id = arg2; 606 int rc; 607 uint32_t val; 608 609 SFXGE_PORT_LOCK(&sc->port); 610 if ((rc = sfxge_phy_stat_update(sc)) == 0) 611 val = ((uint32_t *)sc->port.phy_stats.decode_buf)[id]; 612 SFXGE_PORT_UNLOCK(&sc->port); 613 614 if (rc == 0) 615 rc = SYSCTL_OUT(req, &val, sizeof(val)); 616 return (rc); 617 } 618 619 static void 620 sfxge_phy_stat_init(struct sfxge_softc *sc) 621 { 622 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->dev); 623 struct sysctl_oid_list *stat_list; 624 unsigned int id; 625 const char *name; 626 uint64_t stat_mask = efx_nic_cfg_get(sc->enp)->enc_phy_stat_mask; 627 628 stat_list = SYSCTL_CHILDREN(sc->stats_node); 629 630 /* Initialise the named stats */ 631 for (id = 0; id < EFX_PHY_NSTATS; id++) { 632 if (!(stat_mask & ((uint64_t)1 << id))) 633 continue; 634 name = efx_phy_stat_name(sc->enp, id); 635 SYSCTL_ADD_PROC( 636 ctx, stat_list, 637 OID_AUTO, name, CTLTYPE_UINT|CTLFLAG_RD, 638 sc, id, sfxge_phy_stat_handler, 639 id == EFX_PHY_STAT_OUI ? "IX" : "IU", 640 ""); 641 } 642 } 643 644 void 645 sfxge_port_fini(struct sfxge_softc *sc) 646 { 647 struct sfxge_port *port; 648 efsys_mem_t *esmp; 649 650 port = &sc->port; 651 esmp = &port->mac_stats.dma_buf; 652 653 KASSERT(port->init_state == SFXGE_PORT_INITIALIZED, 654 ("Port not initialized")); 655 656 port->init_state = SFXGE_PORT_UNINITIALIZED; 657 658 port->link_mode = EFX_LINK_UNKNOWN; 659 660 /* Finish with PHY DMA memory */ 661 sfxge_dma_free(&port->phy_stats.dma_buf); 662 free(port->phy_stats.decode_buf, M_SFXGE); 663 664 sfxge_dma_free(esmp); 665 free(port->mac_stats.decode_buf, M_SFXGE); 666 667 SFXGE_PORT_LOCK_DESTROY(port); 668 669 port->sc = NULL; 670 } 671 672 int 673 sfxge_port_init(struct sfxge_softc *sc) 674 { 675 struct sfxge_port *port; 676 struct sysctl_ctx_list *sysctl_ctx; 677 struct sysctl_oid *sysctl_tree; 678 efsys_mem_t *mac_stats_buf, *phy_stats_buf; 679 int rc; 680 681 port = &sc->port; 682 mac_stats_buf = &port->mac_stats.dma_buf; 683 phy_stats_buf = &port->phy_stats.dma_buf; 684 685 KASSERT(port->init_state == SFXGE_PORT_UNINITIALIZED, 686 ("Port already initialized")); 687 688 port->sc = sc; 689 690 SFXGE_PORT_LOCK_INIT(port, device_get_nameunit(sc->dev)); 691 692 DBGPRINT(sc->dev, "alloc PHY stats"); 693 port->phy_stats.decode_buf = malloc(EFX_PHY_NSTATS * sizeof(uint32_t), 694 M_SFXGE, M_WAITOK | M_ZERO); 695 if ((rc = sfxge_dma_alloc(sc, EFX_PHY_STATS_SIZE, phy_stats_buf)) != 0) 696 goto fail; 697 sfxge_phy_stat_init(sc); 698 699 DBGPRINT(sc->dev, "init sysctl"); 700 sysctl_ctx = device_get_sysctl_ctx(sc->dev); 701 sysctl_tree = device_get_sysctl_tree(sc->dev); 702 703 #ifndef SFXGE_HAVE_PAUSE_MEDIAOPTS 704 /* If flow control cannot be configured or reported through 705 * ifmedia, provide sysctls for it. */ 706 port->wanted_fc = EFX_FCNTL_RESPOND | EFX_FCNTL_GENERATE; 707 SYSCTL_ADD_PROC(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), OID_AUTO, 708 "wanted_fc", CTLTYPE_UINT|CTLFLAG_RW, sc, 0, 709 sfxge_port_wanted_fc_handler, "IU", "wanted flow control mode"); 710 SYSCTL_ADD_PROC(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), OID_AUTO, 711 "link_fc", CTLTYPE_UINT|CTLFLAG_RD, sc, 0, 712 sfxge_port_link_fc_handler, "IU", "link flow control mode"); 713 #endif 714 715 DBGPRINT(sc->dev, "alloc MAC stats"); 716 port->mac_stats.decode_buf = malloc(EFX_MAC_NSTATS * sizeof(uint64_t), 717 M_SFXGE, M_WAITOK | M_ZERO); 718 if ((rc = sfxge_dma_alloc(sc, EFX_MAC_STATS_SIZE, mac_stats_buf)) != 0) 719 goto fail2; 720 sfxge_mac_stat_init(sc); 721 722 port->init_state = SFXGE_PORT_INITIALIZED; 723 724 DBGPRINT(sc->dev, "success"); 725 return (0); 726 727 fail2: 728 free(port->mac_stats.decode_buf, M_SFXGE); 729 sfxge_dma_free(phy_stats_buf); 730 fail: 731 free(port->phy_stats.decode_buf, M_SFXGE); 732 SFXGE_PORT_LOCK_DESTROY(port); 733 port->sc = NULL; 734 DBGPRINT(sc->dev, "failed %d", rc); 735 return (rc); 736 } 737 738 static const int sfxge_link_mode[EFX_PHY_MEDIA_NTYPES][EFX_LINK_NMODES] = { 739 [EFX_PHY_MEDIA_CX4] = { 740 [EFX_LINK_10000FDX] = IFM_ETHER | IFM_FDX | IFM_10G_CX4, 741 }, 742 [EFX_PHY_MEDIA_KX4] = { 743 [EFX_LINK_10000FDX] = IFM_ETHER | IFM_FDX | IFM_10G_KX4, 744 }, 745 [EFX_PHY_MEDIA_XFP] = { 746 /* Don't know the module type, but assume SR for now. */ 747 [EFX_LINK_10000FDX] = IFM_ETHER | IFM_FDX | IFM_10G_SR, 748 }, 749 [EFX_PHY_MEDIA_QSFP_PLUS] = { 750 /* Don't know the module type, but assume SR for now. */ 751 [EFX_LINK_10000FDX] = IFM_ETHER | IFM_FDX | IFM_10G_SR, 752 [EFX_LINK_40000FDX] = IFM_ETHER | IFM_FDX | IFM_40G_CR4, 753 }, 754 [EFX_PHY_MEDIA_SFP_PLUS] = { 755 /* Don't know the module type, but assume SX/SR for now. */ 756 [EFX_LINK_1000FDX] = IFM_ETHER | IFM_FDX | IFM_1000_SX, 757 [EFX_LINK_10000FDX] = IFM_ETHER | IFM_FDX | IFM_10G_SR, 758 }, 759 [EFX_PHY_MEDIA_BASE_T] = { 760 [EFX_LINK_10HDX] = IFM_ETHER | IFM_HDX | IFM_10_T, 761 [EFX_LINK_10FDX] = IFM_ETHER | IFM_FDX | IFM_10_T, 762 [EFX_LINK_100HDX] = IFM_ETHER | IFM_HDX | IFM_100_TX, 763 [EFX_LINK_100FDX] = IFM_ETHER | IFM_FDX | IFM_100_TX, 764 [EFX_LINK_1000HDX] = IFM_ETHER | IFM_HDX | IFM_1000_T, 765 [EFX_LINK_1000FDX] = IFM_ETHER | IFM_FDX | IFM_1000_T, 766 [EFX_LINK_10000FDX] = IFM_ETHER | IFM_FDX | IFM_10G_T, 767 }, 768 }; 769 770 static void 771 sfxge_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 772 { 773 struct sfxge_softc *sc; 774 efx_phy_media_type_t medium_type; 775 efx_link_mode_t mode; 776 777 sc = ifp->if_softc; 778 SFXGE_ADAPTER_LOCK(sc); 779 780 ifmr->ifm_status = IFM_AVALID; 781 ifmr->ifm_active = IFM_ETHER; 782 783 if (SFXGE_RUNNING(sc) && SFXGE_LINK_UP(sc)) { 784 ifmr->ifm_status |= IFM_ACTIVE; 785 786 efx_phy_media_type_get(sc->enp, &medium_type); 787 mode = sc->port.link_mode; 788 ifmr->ifm_active |= sfxge_link_mode[medium_type][mode]; 789 ifmr->ifm_active |= sfxge_port_link_fc_ifm(sc); 790 } 791 792 SFXGE_ADAPTER_UNLOCK(sc); 793 } 794 795 static efx_phy_cap_type_t 796 sfxge_link_mode_to_phy_cap(efx_link_mode_t mode) 797 { 798 switch (mode) { 799 case EFX_LINK_10HDX: 800 return (EFX_PHY_CAP_10HDX); 801 case EFX_LINK_10FDX: 802 return (EFX_PHY_CAP_10FDX); 803 case EFX_LINK_100HDX: 804 return (EFX_PHY_CAP_100HDX); 805 case EFX_LINK_100FDX: 806 return (EFX_PHY_CAP_100FDX); 807 case EFX_LINK_1000HDX: 808 return (EFX_PHY_CAP_1000HDX); 809 case EFX_LINK_1000FDX: 810 return (EFX_PHY_CAP_1000FDX); 811 case EFX_LINK_10000FDX: 812 return (EFX_PHY_CAP_10000FDX); 813 case EFX_LINK_40000FDX: 814 return (EFX_PHY_CAP_40000FDX); 815 default: 816 EFSYS_ASSERT(B_FALSE); 817 return (EFX_PHY_CAP_INVALID); 818 } 819 } 820 821 static int 822 sfxge_phy_cap_mask(struct sfxge_softc *sc, int ifmedia, uint32_t *phy_cap_mask) 823 { 824 /* Get global options (duplex), type and subtype bits */ 825 int ifmedia_masked = ifmedia & (IFM_GMASK | IFM_NMASK | IFM_TMASK); 826 efx_phy_media_type_t medium_type; 827 boolean_t mode_found = B_FALSE; 828 uint32_t cap_mask, mode_cap_mask; 829 efx_link_mode_t mode; 830 efx_phy_cap_type_t phy_cap; 831 832 efx_phy_media_type_get(sc->enp, &medium_type); 833 if (medium_type >= nitems(sfxge_link_mode)) { 834 if_printf(sc->ifnet, "unexpected media type %d\n", medium_type); 835 return (EINVAL); 836 } 837 838 efx_phy_adv_cap_get(sc->enp, EFX_PHY_CAP_PERM, &cap_mask); 839 840 for (mode = EFX_LINK_10HDX; mode < EFX_LINK_NMODES; mode++) { 841 if (ifmedia_masked == sfxge_link_mode[medium_type][mode]) { 842 mode_found = B_TRUE; 843 break; 844 } 845 } 846 847 if (!mode_found) { 848 /* 849 * If media is not in the table, it must be IFM_AUTO. 850 */ 851 KASSERT((cap_mask & (1 << EFX_PHY_CAP_AN)) && 852 ifmedia_masked == (IFM_ETHER | IFM_AUTO), 853 ("%s: no mode for media %#x", __func__, ifmedia)); 854 *phy_cap_mask = (cap_mask & ~(1 << EFX_PHY_CAP_ASYM)); 855 return (0); 856 } 857 858 phy_cap = sfxge_link_mode_to_phy_cap(mode); 859 if (phy_cap == EFX_PHY_CAP_INVALID) { 860 if_printf(sc->ifnet, 861 "cannot map link mode %d to phy capability\n", 862 mode); 863 return (EINVAL); 864 } 865 866 mode_cap_mask = (1 << phy_cap); 867 mode_cap_mask |= cap_mask & (1 << EFX_PHY_CAP_AN); 868 #ifdef SFXGE_HAVE_PAUSE_MEDIAOPTS 869 if (ifmedia & IFM_ETH_RXPAUSE) 870 mode_cap_mask |= cap_mask & (1 << EFX_PHY_CAP_PAUSE); 871 if (!(ifmedia & IFM_ETH_TXPAUSE)) 872 mode_cap_mask |= cap_mask & (1 << EFX_PHY_CAP_ASYM); 873 #else 874 mode_cap_mask |= cap_mask & (1 << EFX_PHY_CAP_PAUSE); 875 #endif 876 877 *phy_cap_mask = mode_cap_mask; 878 return (0); 879 } 880 881 static int 882 sfxge_media_change(struct ifnet *ifp) 883 { 884 struct sfxge_softc *sc; 885 struct ifmedia_entry *ifm; 886 int rc; 887 uint32_t phy_cap_mask; 888 889 sc = ifp->if_softc; 890 ifm = sc->media.ifm_cur; 891 892 SFXGE_ADAPTER_LOCK(sc); 893 894 if (!SFXGE_RUNNING(sc)) { 895 rc = 0; 896 goto out; 897 } 898 899 rc = efx_mac_fcntl_set(sc->enp, sfxge_port_wanted_fc(sc), B_TRUE); 900 if (rc != 0) 901 goto out; 902 903 if ((rc = sfxge_phy_cap_mask(sc, ifm->ifm_media, &phy_cap_mask)) != 0) 904 goto out; 905 906 rc = efx_phy_adv_cap_set(sc->enp, phy_cap_mask); 907 out: 908 SFXGE_ADAPTER_UNLOCK(sc); 909 910 return (rc); 911 } 912 913 int sfxge_port_ifmedia_init(struct sfxge_softc *sc) 914 { 915 efx_phy_media_type_t medium_type; 916 uint32_t cap_mask, mode_cap_mask; 917 efx_link_mode_t mode; 918 efx_phy_cap_type_t phy_cap; 919 int mode_ifm, best_mode_ifm = 0; 920 int rc; 921 922 /* 923 * We need port state to initialise the ifmedia list. 924 * It requires initialized NIC what is already done in 925 * sfxge_create() when resources are estimated. 926 */ 927 if ((rc = efx_filter_init(sc->enp)) != 0) 928 goto out1; 929 if ((rc = efx_port_init(sc->enp)) != 0) 930 goto out2; 931 932 /* 933 * Register ifconfig callbacks for querying and setting the 934 * link mode and link status. 935 */ 936 ifmedia_init(&sc->media, IFM_IMASK, sfxge_media_change, 937 sfxge_media_status); 938 939 /* 940 * Map firmware medium type and capabilities to ifmedia types. 941 * ifmedia does not distinguish between forcing the link mode 942 * and disabling auto-negotiation. 1000BASE-T and 10GBASE-T 943 * require AN even if only one link mode is enabled, and for 944 * 100BASE-TX it is useful even if the link mode is forced. 945 * Therefore we never disable auto-negotiation. 946 * 947 * Also enable and advertise flow control by default. 948 */ 949 950 efx_phy_media_type_get(sc->enp, &medium_type); 951 efx_phy_adv_cap_get(sc->enp, EFX_PHY_CAP_PERM, &cap_mask); 952 953 for (mode = EFX_LINK_10HDX; mode < EFX_LINK_NMODES; mode++) { 954 phy_cap = sfxge_link_mode_to_phy_cap(mode); 955 if (phy_cap == EFX_PHY_CAP_INVALID) 956 continue; 957 958 mode_cap_mask = (1 << phy_cap); 959 mode_ifm = sfxge_link_mode[medium_type][mode]; 960 961 if ((cap_mask & mode_cap_mask) && mode_ifm) { 962 /* No flow-control */ 963 ifmedia_add(&sc->media, mode_ifm, 0, NULL); 964 965 #ifdef SFXGE_HAVE_PAUSE_MEDIAOPTS 966 /* Respond-only. If using AN, we implicitly 967 * offer symmetric as well, but that doesn't 968 * mean we *have* to generate pause frames. 969 */ 970 mode_ifm |= IFM_ETH_RXPAUSE; 971 ifmedia_add(&sc->media, mode_ifm, 0, NULL); 972 973 /* Symmetric */ 974 mode_ifm |= IFM_ETH_TXPAUSE; 975 ifmedia_add(&sc->media, mode_ifm, 0, NULL); 976 #endif 977 978 /* Link modes are numbered in order of speed, 979 * so assume the last one available is the best. 980 */ 981 best_mode_ifm = mode_ifm; 982 } 983 } 984 985 if (cap_mask & (1 << EFX_PHY_CAP_AN)) { 986 /* Add autoselect mode. */ 987 mode_ifm = IFM_ETHER | IFM_AUTO; 988 ifmedia_add(&sc->media, mode_ifm, 0, NULL); 989 best_mode_ifm = mode_ifm; 990 } 991 992 if (best_mode_ifm != 0) 993 ifmedia_set(&sc->media, best_mode_ifm); 994 995 /* Now discard port state until interface is started. */ 996 efx_port_fini(sc->enp); 997 out2: 998 efx_filter_fini(sc->enp); 999 out1: 1000 return (rc); 1001 } 1002