1 /*- 2 * Copyright (c) 2010-2015 Solarflare Communications Inc. 3 * All rights reserved. 4 * 5 * This software was developed in part by Philip Paeps under contract for 6 * Solarflare Communications, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright notice, 12 * this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright notice, 14 * this list of conditions and the following disclaimer in the documentation 15 * and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 19 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 21 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 22 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 23 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 24 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 25 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 26 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 27 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * The views and conclusions contained in the software and documentation are 30 * those of the authors and should not be interpreted as representing official 31 * policies, either expressed or implied, of the FreeBSD Project. 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 #include <sys/types.h> 38 #include <sys/limits.h> 39 #include <net/ethernet.h> 40 #include <net/if_dl.h> 41 42 #include "common/efx.h" 43 44 #include "sfxge.h" 45 46 static int sfxge_phy_cap_mask(struct sfxge_softc *, int, uint32_t *); 47 48 static int 49 sfxge_mac_stat_update(struct sfxge_softc *sc) 50 { 51 struct sfxge_port *port = &sc->port; 52 efsys_mem_t *esmp = &(port->mac_stats.dma_buf); 53 clock_t now; 54 unsigned int count; 55 int rc; 56 57 SFXGE_PORT_LOCK_ASSERT_OWNED(port); 58 59 if (__predict_false(port->init_state != SFXGE_PORT_STARTED)) { 60 rc = 0; 61 goto out; 62 } 63 64 now = ticks; 65 if (now - port->mac_stats.update_time < hz) { 66 rc = 0; 67 goto out; 68 } 69 70 port->mac_stats.update_time = now; 71 72 /* If we're unlucky enough to read statistics wduring the DMA, wait 73 * up to 10ms for it to finish (typically takes <500us) */ 74 for (count = 0; count < 100; ++count) { 75 EFSYS_PROBE1(wait, unsigned int, count); 76 77 /* Try to update the cached counters */ 78 if ((rc = efx_mac_stats_update(sc->enp, esmp, 79 port->mac_stats.decode_buf, NULL)) != EAGAIN) 80 goto out; 81 82 DELAY(100); 83 } 84 85 rc = ETIMEDOUT; 86 out: 87 return (rc); 88 } 89 90 uint64_t 91 sfxge_get_counter(struct ifnet *ifp, ift_counter c) 92 { 93 struct sfxge_softc *sc = ifp->if_softc; 94 uint64_t *mac_stats; 95 uint64_t val; 96 97 SFXGE_PORT_LOCK(&sc->port); 98 99 /* Ignore error and use old values */ 100 (void)sfxge_mac_stat_update(sc); 101 102 mac_stats = (uint64_t *)sc->port.mac_stats.decode_buf; 103 104 switch (c) { 105 case IFCOUNTER_IPACKETS: 106 val = mac_stats[EFX_MAC_RX_PKTS]; 107 break; 108 case IFCOUNTER_IERRORS: 109 val = mac_stats[EFX_MAC_RX_ERRORS]; 110 break; 111 case IFCOUNTER_OPACKETS: 112 val = mac_stats[EFX_MAC_TX_PKTS]; 113 break; 114 case IFCOUNTER_OERRORS: 115 val = mac_stats[EFX_MAC_TX_ERRORS]; 116 break; 117 case IFCOUNTER_COLLISIONS: 118 val = mac_stats[EFX_MAC_TX_SGL_COL_PKTS] + 119 mac_stats[EFX_MAC_TX_MULT_COL_PKTS] + 120 mac_stats[EFX_MAC_TX_EX_COL_PKTS] + 121 mac_stats[EFX_MAC_TX_LATE_COL_PKTS]; 122 break; 123 case IFCOUNTER_IBYTES: 124 val = mac_stats[EFX_MAC_RX_OCTETS]; 125 break; 126 case IFCOUNTER_OBYTES: 127 val = mac_stats[EFX_MAC_TX_OCTETS]; 128 break; 129 case IFCOUNTER_OMCASTS: 130 val = mac_stats[EFX_MAC_TX_MULTICST_PKTS] + 131 mac_stats[EFX_MAC_TX_BRDCST_PKTS]; 132 break; 133 case IFCOUNTER_OQDROPS: 134 SFXGE_PORT_UNLOCK(&sc->port); 135 return (sfxge_tx_get_drops(sc)); 136 case IFCOUNTER_IMCASTS: 137 /* if_imcasts is maintained in net/if_ethersubr.c */ 138 case IFCOUNTER_IQDROPS: 139 /* if_iqdrops is maintained in net/if_ethersubr.c */ 140 case IFCOUNTER_NOPROTO: 141 /* if_noproto is maintained in net/if_ethersubr.c */ 142 default: 143 SFXGE_PORT_UNLOCK(&sc->port); 144 return (if_get_counter_default(ifp, c)); 145 } 146 147 SFXGE_PORT_UNLOCK(&sc->port); 148 149 return (val); 150 } 151 152 static int 153 sfxge_mac_stat_handler(SYSCTL_HANDLER_ARGS) 154 { 155 struct sfxge_softc *sc = arg1; 156 unsigned int id = arg2; 157 int rc; 158 uint64_t val; 159 160 SFXGE_PORT_LOCK(&sc->port); 161 if ((rc = sfxge_mac_stat_update(sc)) == 0) 162 val = ((uint64_t *)sc->port.mac_stats.decode_buf)[id]; 163 SFXGE_PORT_UNLOCK(&sc->port); 164 165 if (rc == 0) 166 rc = SYSCTL_OUT(req, &val, sizeof(val)); 167 return (rc); 168 } 169 170 static void 171 sfxge_mac_stat_init(struct sfxge_softc *sc) 172 { 173 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->dev); 174 struct sysctl_oid_list *stat_list; 175 unsigned int id; 176 const char *name; 177 178 stat_list = SYSCTL_CHILDREN(sc->stats_node); 179 180 /* Initialise the named stats */ 181 for (id = 0; id < EFX_MAC_NSTATS; id++) { 182 name = efx_mac_stat_name(sc->enp, id); 183 SYSCTL_ADD_PROC( 184 ctx, stat_list, 185 OID_AUTO, name, CTLTYPE_U64|CTLFLAG_RD, 186 sc, id, sfxge_mac_stat_handler, "Q", 187 ""); 188 } 189 } 190 191 #ifdef SFXGE_HAVE_PAUSE_MEDIAOPTS 192 193 static unsigned int 194 sfxge_port_wanted_fc(struct sfxge_softc *sc) 195 { 196 struct ifmedia_entry *ifm = sc->media.ifm_cur; 197 198 if (ifm->ifm_media == (IFM_ETHER | IFM_AUTO)) 199 return (EFX_FCNTL_RESPOND | EFX_FCNTL_GENERATE); 200 return (((ifm->ifm_media & IFM_ETH_RXPAUSE) ? EFX_FCNTL_RESPOND : 0) | 201 ((ifm->ifm_media & IFM_ETH_TXPAUSE) ? EFX_FCNTL_GENERATE : 0)); 202 } 203 204 static unsigned int 205 sfxge_port_link_fc_ifm(struct sfxge_softc *sc) 206 { 207 unsigned int wanted_fc, link_fc; 208 209 efx_mac_fcntl_get(sc->enp, &wanted_fc, &link_fc); 210 return ((link_fc & EFX_FCNTL_RESPOND) ? IFM_ETH_RXPAUSE : 0) | 211 ((link_fc & EFX_FCNTL_GENERATE) ? IFM_ETH_TXPAUSE : 0); 212 } 213 214 #else /* !SFXGE_HAVE_PAUSE_MEDIAOPTS */ 215 216 static unsigned int 217 sfxge_port_wanted_fc(struct sfxge_softc *sc) 218 { 219 return (sc->port.wanted_fc); 220 } 221 222 static unsigned int 223 sfxge_port_link_fc_ifm(struct sfxge_softc *sc) 224 { 225 return (0); 226 } 227 228 static int 229 sfxge_port_wanted_fc_handler(SYSCTL_HANDLER_ARGS) 230 { 231 struct sfxge_softc *sc; 232 struct sfxge_port *port; 233 unsigned int fcntl; 234 int error; 235 236 sc = arg1; 237 port = &sc->port; 238 239 if (req->newptr != NULL) { 240 if ((error = SYSCTL_IN(req, &fcntl, sizeof(fcntl))) != 0) 241 return (error); 242 243 SFXGE_PORT_LOCK(port); 244 245 if (port->wanted_fc != fcntl) { 246 if (port->init_state == SFXGE_PORT_STARTED) 247 error = efx_mac_fcntl_set(sc->enp, 248 port->wanted_fc, 249 B_TRUE); 250 if (error == 0) 251 port->wanted_fc = fcntl; 252 } 253 254 SFXGE_PORT_UNLOCK(port); 255 } else { 256 SFXGE_PORT_LOCK(port); 257 fcntl = port->wanted_fc; 258 SFXGE_PORT_UNLOCK(port); 259 260 error = SYSCTL_OUT(req, &fcntl, sizeof(fcntl)); 261 } 262 263 return (error); 264 } 265 266 static int 267 sfxge_port_link_fc_handler(SYSCTL_HANDLER_ARGS) 268 { 269 struct sfxge_softc *sc; 270 struct sfxge_port *port; 271 unsigned int wanted_fc, link_fc; 272 273 sc = arg1; 274 port = &sc->port; 275 276 SFXGE_PORT_LOCK(port); 277 if (__predict_true(port->init_state == SFXGE_PORT_STARTED) && 278 SFXGE_LINK_UP(sc)) 279 efx_mac_fcntl_get(sc->enp, &wanted_fc, &link_fc); 280 else 281 link_fc = 0; 282 SFXGE_PORT_UNLOCK(port); 283 284 return (SYSCTL_OUT(req, &link_fc, sizeof(link_fc))); 285 } 286 287 #endif /* SFXGE_HAVE_PAUSE_MEDIAOPTS */ 288 289 static const uint64_t sfxge_link_baudrate[EFX_LINK_NMODES] = { 290 [EFX_LINK_10HDX] = IF_Mbps(10), 291 [EFX_LINK_10FDX] = IF_Mbps(10), 292 [EFX_LINK_100HDX] = IF_Mbps(100), 293 [EFX_LINK_100FDX] = IF_Mbps(100), 294 [EFX_LINK_1000HDX] = IF_Gbps(1), 295 [EFX_LINK_1000FDX] = IF_Gbps(1), 296 [EFX_LINK_10000FDX] = IF_Gbps(10), 297 [EFX_LINK_40000FDX] = IF_Gbps(40), 298 }; 299 300 void 301 sfxge_mac_link_update(struct sfxge_softc *sc, efx_link_mode_t mode) 302 { 303 struct sfxge_port *port; 304 int link_state; 305 306 port = &sc->port; 307 308 if (port->link_mode == mode) 309 return; 310 311 port->link_mode = mode; 312 313 /* Push link state update to the OS */ 314 link_state = (port->link_mode != EFX_LINK_DOWN ? 315 LINK_STATE_UP : LINK_STATE_DOWN); 316 sc->ifnet->if_baudrate = sfxge_link_baudrate[port->link_mode]; 317 if_link_state_change(sc->ifnet, link_state); 318 } 319 320 static void 321 sfxge_mac_poll_work(void *arg, int npending) 322 { 323 struct sfxge_softc *sc; 324 efx_nic_t *enp; 325 struct sfxge_port *port; 326 efx_link_mode_t mode; 327 328 sc = (struct sfxge_softc *)arg; 329 enp = sc->enp; 330 port = &sc->port; 331 332 SFXGE_PORT_LOCK(port); 333 334 if (__predict_false(port->init_state != SFXGE_PORT_STARTED)) 335 goto done; 336 337 /* This may sleep waiting for MCDI completion */ 338 (void)efx_port_poll(enp, &mode); 339 sfxge_mac_link_update(sc, mode); 340 341 done: 342 SFXGE_PORT_UNLOCK(port); 343 } 344 345 static int 346 sfxge_mac_multicast_list_set(struct sfxge_softc *sc) 347 { 348 struct ifnet *ifp = sc->ifnet; 349 struct sfxge_port *port = &sc->port; 350 uint8_t *mcast_addr = port->mcast_addrs; 351 struct ifmultiaddr *ifma; 352 struct sockaddr_dl *sa; 353 int rc = 0; 354 355 mtx_assert(&port->lock, MA_OWNED); 356 357 port->mcast_count = 0; 358 if_maddr_rlock(ifp); 359 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 360 if (ifma->ifma_addr->sa_family == AF_LINK) { 361 if (port->mcast_count == EFX_MAC_MULTICAST_LIST_MAX) { 362 device_printf(sc->dev, 363 "Too many multicast addresses\n"); 364 rc = EINVAL; 365 break; 366 } 367 368 sa = (struct sockaddr_dl *)ifma->ifma_addr; 369 memcpy(mcast_addr, LLADDR(sa), EFX_MAC_ADDR_LEN); 370 mcast_addr += EFX_MAC_ADDR_LEN; 371 ++port->mcast_count; 372 } 373 } 374 if_maddr_runlock(ifp); 375 376 if (rc == 0) { 377 rc = efx_mac_multicast_list_set(sc->enp, port->mcast_addrs, 378 port->mcast_count); 379 if (rc != 0) 380 device_printf(sc->dev, 381 "Cannot set multicast address list\n"); 382 } 383 384 return (rc); 385 } 386 387 static int 388 sfxge_mac_filter_set_locked(struct sfxge_softc *sc) 389 { 390 struct ifnet *ifp = sc->ifnet; 391 struct sfxge_port *port = &sc->port; 392 boolean_t all_mulcst; 393 int rc; 394 395 mtx_assert(&port->lock, MA_OWNED); 396 397 all_mulcst = !!(ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)); 398 399 rc = sfxge_mac_multicast_list_set(sc); 400 /* Fallback to all multicast if cannot set multicast list */ 401 if (rc != 0) 402 all_mulcst = B_TRUE; 403 404 rc = efx_mac_filter_set(sc->enp, !!(ifp->if_flags & IFF_PROMISC), 405 (port->mcast_count > 0), all_mulcst, B_TRUE); 406 407 return (rc); 408 } 409 410 int 411 sfxge_mac_filter_set(struct sfxge_softc *sc) 412 { 413 struct sfxge_port *port = &sc->port; 414 int rc; 415 416 SFXGE_PORT_LOCK(port); 417 /* 418 * The function may be called without softc_lock held in the 419 * case of SIOCADDMULTI and SIOCDELMULTI ioctls. ioctl handler 420 * checks IFF_DRV_RUNNING flag which implies port started, but 421 * it is not guaranteed to remain. softc_lock shared lock can't 422 * be held in the case of these ioctls processing, since it 423 * results in failure where kernel complains that non-sleepable 424 * lock is held in sleeping thread. Both problems are repeatable 425 * on LAG with LACP proto bring up. 426 */ 427 if (__predict_true(port->init_state == SFXGE_PORT_STARTED)) 428 rc = sfxge_mac_filter_set_locked(sc); 429 else 430 rc = 0; 431 SFXGE_PORT_UNLOCK(port); 432 return (rc); 433 } 434 435 void 436 sfxge_port_stop(struct sfxge_softc *sc) 437 { 438 struct sfxge_port *port; 439 efx_nic_t *enp; 440 441 port = &sc->port; 442 enp = sc->enp; 443 444 SFXGE_PORT_LOCK(port); 445 446 KASSERT(port->init_state == SFXGE_PORT_STARTED, 447 ("port not started")); 448 449 port->init_state = SFXGE_PORT_INITIALIZED; 450 451 port->mac_stats.update_time = 0; 452 453 /* This may call MCDI */ 454 (void)efx_mac_drain(enp, B_TRUE); 455 456 (void)efx_mac_stats_periodic(enp, &port->mac_stats.dma_buf, 0, B_FALSE); 457 458 port->link_mode = EFX_LINK_UNKNOWN; 459 460 /* Destroy the common code port object. */ 461 efx_port_fini(enp); 462 463 efx_filter_fini(enp); 464 465 SFXGE_PORT_UNLOCK(port); 466 } 467 468 int 469 sfxge_port_start(struct sfxge_softc *sc) 470 { 471 uint8_t mac_addr[ETHER_ADDR_LEN]; 472 struct ifnet *ifp = sc->ifnet; 473 struct sfxge_port *port; 474 efx_nic_t *enp; 475 size_t pdu; 476 int rc; 477 uint32_t phy_cap_mask; 478 479 port = &sc->port; 480 enp = sc->enp; 481 482 SFXGE_PORT_LOCK(port); 483 484 KASSERT(port->init_state == SFXGE_PORT_INITIALIZED, 485 ("port not initialized")); 486 487 /* Initialise the required filtering */ 488 if ((rc = efx_filter_init(enp)) != 0) 489 goto fail_filter_init; 490 491 /* Initialize the port object in the common code. */ 492 if ((rc = efx_port_init(sc->enp)) != 0) 493 goto fail; 494 495 /* Set the SDU */ 496 pdu = EFX_MAC_PDU(ifp->if_mtu); 497 if ((rc = efx_mac_pdu_set(enp, pdu)) != 0) 498 goto fail2; 499 500 if ((rc = efx_mac_fcntl_set(enp, sfxge_port_wanted_fc(sc), B_TRUE)) 501 != 0) 502 goto fail3; 503 504 /* Set the unicast address */ 505 if_addr_rlock(ifp); 506 bcopy(LLADDR((struct sockaddr_dl *)ifp->if_addr->ifa_addr), 507 mac_addr, sizeof(mac_addr)); 508 if_addr_runlock(ifp); 509 if ((rc = efx_mac_addr_set(enp, mac_addr)) != 0) 510 goto fail4; 511 512 sfxge_mac_filter_set_locked(sc); 513 514 /* Update MAC stats by DMA every second */ 515 if ((rc = efx_mac_stats_periodic(enp, &port->mac_stats.dma_buf, 516 1000, B_FALSE)) != 0) 517 goto fail6; 518 519 if ((rc = efx_mac_drain(enp, B_FALSE)) != 0) 520 goto fail8; 521 522 if ((rc = sfxge_phy_cap_mask(sc, sc->media.ifm_cur->ifm_media, 523 &phy_cap_mask)) != 0) 524 goto fail9; 525 526 if ((rc = efx_phy_adv_cap_set(sc->enp, phy_cap_mask)) != 0) 527 goto fail10; 528 529 port->init_state = SFXGE_PORT_STARTED; 530 531 /* Single poll in case there were missing initial events */ 532 SFXGE_PORT_UNLOCK(port); 533 sfxge_mac_poll_work(sc, 0); 534 535 return (0); 536 537 fail10: 538 fail9: 539 (void)efx_mac_drain(enp, B_TRUE); 540 fail8: 541 (void)efx_mac_stats_periodic(enp, &port->mac_stats.dma_buf, 0, B_FALSE); 542 fail6: 543 fail4: 544 fail3: 545 546 fail2: 547 efx_port_fini(enp); 548 fail: 549 efx_filter_fini(enp); 550 fail_filter_init: 551 SFXGE_PORT_UNLOCK(port); 552 553 return (rc); 554 } 555 556 static int 557 sfxge_phy_stat_update(struct sfxge_softc *sc) 558 { 559 struct sfxge_port *port = &sc->port; 560 efsys_mem_t *esmp = &port->phy_stats.dma_buf; 561 clock_t now; 562 unsigned int count; 563 int rc; 564 565 SFXGE_PORT_LOCK_ASSERT_OWNED(port); 566 567 if (__predict_false(port->init_state != SFXGE_PORT_STARTED)) { 568 rc = 0; 569 goto out; 570 } 571 572 now = ticks; 573 if (now - port->phy_stats.update_time < hz) { 574 rc = 0; 575 goto out; 576 } 577 578 port->phy_stats.update_time = now; 579 580 /* If we're unlucky enough to read statistics wduring the DMA, wait 581 * up to 10ms for it to finish (typically takes <500us) */ 582 for (count = 0; count < 100; ++count) { 583 EFSYS_PROBE1(wait, unsigned int, count); 584 585 /* Synchronize the DMA memory for reading */ 586 bus_dmamap_sync(esmp->esm_tag, esmp->esm_map, 587 BUS_DMASYNC_POSTREAD); 588 589 /* Try to update the cached counters */ 590 if ((rc = efx_phy_stats_update(sc->enp, esmp, 591 port->phy_stats.decode_buf)) != EAGAIN) 592 goto out; 593 594 DELAY(100); 595 } 596 597 rc = ETIMEDOUT; 598 out: 599 return (rc); 600 } 601 602 static int 603 sfxge_phy_stat_handler(SYSCTL_HANDLER_ARGS) 604 { 605 struct sfxge_softc *sc = arg1; 606 unsigned int id = arg2; 607 int rc; 608 uint32_t val; 609 610 SFXGE_PORT_LOCK(&sc->port); 611 if ((rc = sfxge_phy_stat_update(sc)) == 0) 612 val = ((uint32_t *)sc->port.phy_stats.decode_buf)[id]; 613 SFXGE_PORT_UNLOCK(&sc->port); 614 615 if (rc == 0) 616 rc = SYSCTL_OUT(req, &val, sizeof(val)); 617 return (rc); 618 } 619 620 static void 621 sfxge_phy_stat_init(struct sfxge_softc *sc) 622 { 623 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->dev); 624 struct sysctl_oid_list *stat_list; 625 unsigned int id; 626 const char *name; 627 uint64_t stat_mask = efx_nic_cfg_get(sc->enp)->enc_phy_stat_mask; 628 629 stat_list = SYSCTL_CHILDREN(sc->stats_node); 630 631 /* Initialise the named stats */ 632 for (id = 0; id < EFX_PHY_NSTATS; id++) { 633 if (!(stat_mask & ((uint64_t)1 << id))) 634 continue; 635 name = efx_phy_stat_name(sc->enp, id); 636 SYSCTL_ADD_PROC( 637 ctx, stat_list, 638 OID_AUTO, name, CTLTYPE_UINT|CTLFLAG_RD, 639 sc, id, sfxge_phy_stat_handler, 640 id == EFX_PHY_STAT_OUI ? "IX" : "IU", 641 ""); 642 } 643 } 644 645 void 646 sfxge_port_fini(struct sfxge_softc *sc) 647 { 648 struct sfxge_port *port; 649 efsys_mem_t *esmp; 650 651 port = &sc->port; 652 esmp = &port->mac_stats.dma_buf; 653 654 KASSERT(port->init_state == SFXGE_PORT_INITIALIZED, 655 ("Port not initialized")); 656 657 port->init_state = SFXGE_PORT_UNINITIALIZED; 658 659 port->link_mode = EFX_LINK_UNKNOWN; 660 661 /* Finish with PHY DMA memory */ 662 sfxge_dma_free(&port->phy_stats.dma_buf); 663 free(port->phy_stats.decode_buf, M_SFXGE); 664 665 sfxge_dma_free(esmp); 666 free(port->mac_stats.decode_buf, M_SFXGE); 667 668 SFXGE_PORT_LOCK_DESTROY(port); 669 670 port->sc = NULL; 671 } 672 673 int 674 sfxge_port_init(struct sfxge_softc *sc) 675 { 676 struct sfxge_port *port; 677 struct sysctl_ctx_list *sysctl_ctx; 678 struct sysctl_oid *sysctl_tree; 679 efsys_mem_t *mac_stats_buf, *phy_stats_buf; 680 int rc; 681 682 port = &sc->port; 683 mac_stats_buf = &port->mac_stats.dma_buf; 684 phy_stats_buf = &port->phy_stats.dma_buf; 685 686 KASSERT(port->init_state == SFXGE_PORT_UNINITIALIZED, 687 ("Port already initialized")); 688 689 port->sc = sc; 690 691 SFXGE_PORT_LOCK_INIT(port, device_get_nameunit(sc->dev)); 692 693 DBGPRINT(sc->dev, "alloc PHY stats"); 694 port->phy_stats.decode_buf = malloc(EFX_PHY_NSTATS * sizeof(uint32_t), 695 M_SFXGE, M_WAITOK | M_ZERO); 696 if ((rc = sfxge_dma_alloc(sc, EFX_PHY_STATS_SIZE, phy_stats_buf)) != 0) 697 goto fail; 698 sfxge_phy_stat_init(sc); 699 700 DBGPRINT(sc->dev, "init sysctl"); 701 sysctl_ctx = device_get_sysctl_ctx(sc->dev); 702 sysctl_tree = device_get_sysctl_tree(sc->dev); 703 704 #ifndef SFXGE_HAVE_PAUSE_MEDIAOPTS 705 /* If flow control cannot be configured or reported through 706 * ifmedia, provide sysctls for it. */ 707 port->wanted_fc = EFX_FCNTL_RESPOND | EFX_FCNTL_GENERATE; 708 SYSCTL_ADD_PROC(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), OID_AUTO, 709 "wanted_fc", CTLTYPE_UINT|CTLFLAG_RW, sc, 0, 710 sfxge_port_wanted_fc_handler, "IU", "wanted flow control mode"); 711 SYSCTL_ADD_PROC(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), OID_AUTO, 712 "link_fc", CTLTYPE_UINT|CTLFLAG_RD, sc, 0, 713 sfxge_port_link_fc_handler, "IU", "link flow control mode"); 714 #endif 715 716 DBGPRINT(sc->dev, "alloc MAC stats"); 717 port->mac_stats.decode_buf = malloc(EFX_MAC_NSTATS * sizeof(uint64_t), 718 M_SFXGE, M_WAITOK | M_ZERO); 719 if ((rc = sfxge_dma_alloc(sc, EFX_MAC_STATS_SIZE, mac_stats_buf)) != 0) 720 goto fail2; 721 sfxge_mac_stat_init(sc); 722 723 port->init_state = SFXGE_PORT_INITIALIZED; 724 725 DBGPRINT(sc->dev, "success"); 726 return (0); 727 728 fail2: 729 free(port->mac_stats.decode_buf, M_SFXGE); 730 sfxge_dma_free(phy_stats_buf); 731 fail: 732 free(port->phy_stats.decode_buf, M_SFXGE); 733 SFXGE_PORT_LOCK_DESTROY(port); 734 port->sc = NULL; 735 DBGPRINT(sc->dev, "failed %d", rc); 736 return (rc); 737 } 738 739 static const int sfxge_link_mode[EFX_PHY_MEDIA_NTYPES][EFX_LINK_NMODES] = { 740 [EFX_PHY_MEDIA_CX4] = { 741 [EFX_LINK_10000FDX] = IFM_ETHER | IFM_FDX | IFM_10G_CX4, 742 }, 743 [EFX_PHY_MEDIA_KX4] = { 744 [EFX_LINK_10000FDX] = IFM_ETHER | IFM_FDX | IFM_10G_KX4, 745 }, 746 [EFX_PHY_MEDIA_XFP] = { 747 /* Don't know the module type, but assume SR for now. */ 748 [EFX_LINK_10000FDX] = IFM_ETHER | IFM_FDX | IFM_10G_SR, 749 }, 750 [EFX_PHY_MEDIA_QSFP_PLUS] = { 751 /* Don't know the module type, but assume SR for now. */ 752 [EFX_LINK_10000FDX] = IFM_ETHER | IFM_FDX | IFM_10G_SR, 753 [EFX_LINK_40000FDX] = IFM_ETHER | IFM_FDX | IFM_40G_CR4, 754 }, 755 [EFX_PHY_MEDIA_SFP_PLUS] = { 756 /* Don't know the module type, but assume SX/SR for now. */ 757 [EFX_LINK_1000FDX] = IFM_ETHER | IFM_FDX | IFM_1000_SX, 758 [EFX_LINK_10000FDX] = IFM_ETHER | IFM_FDX | IFM_10G_SR, 759 }, 760 [EFX_PHY_MEDIA_BASE_T] = { 761 [EFX_LINK_10HDX] = IFM_ETHER | IFM_HDX | IFM_10_T, 762 [EFX_LINK_10FDX] = IFM_ETHER | IFM_FDX | IFM_10_T, 763 [EFX_LINK_100HDX] = IFM_ETHER | IFM_HDX | IFM_100_TX, 764 [EFX_LINK_100FDX] = IFM_ETHER | IFM_FDX | IFM_100_TX, 765 [EFX_LINK_1000HDX] = IFM_ETHER | IFM_HDX | IFM_1000_T, 766 [EFX_LINK_1000FDX] = IFM_ETHER | IFM_FDX | IFM_1000_T, 767 [EFX_LINK_10000FDX] = IFM_ETHER | IFM_FDX | IFM_10G_T, 768 }, 769 }; 770 771 static void 772 sfxge_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 773 { 774 struct sfxge_softc *sc; 775 efx_phy_media_type_t medium_type; 776 efx_link_mode_t mode; 777 778 sc = ifp->if_softc; 779 SFXGE_ADAPTER_LOCK(sc); 780 781 ifmr->ifm_status = IFM_AVALID; 782 ifmr->ifm_active = IFM_ETHER; 783 784 if (SFXGE_RUNNING(sc) && SFXGE_LINK_UP(sc)) { 785 ifmr->ifm_status |= IFM_ACTIVE; 786 787 efx_phy_media_type_get(sc->enp, &medium_type); 788 mode = sc->port.link_mode; 789 ifmr->ifm_active |= sfxge_link_mode[medium_type][mode]; 790 ifmr->ifm_active |= sfxge_port_link_fc_ifm(sc); 791 } 792 793 SFXGE_ADAPTER_UNLOCK(sc); 794 } 795 796 static efx_phy_cap_type_t 797 sfxge_link_mode_to_phy_cap(efx_link_mode_t mode) 798 { 799 switch (mode) { 800 case EFX_LINK_10HDX: 801 return (EFX_PHY_CAP_10HDX); 802 case EFX_LINK_10FDX: 803 return (EFX_PHY_CAP_10FDX); 804 case EFX_LINK_100HDX: 805 return (EFX_PHY_CAP_100HDX); 806 case EFX_LINK_100FDX: 807 return (EFX_PHY_CAP_100FDX); 808 case EFX_LINK_1000HDX: 809 return (EFX_PHY_CAP_1000HDX); 810 case EFX_LINK_1000FDX: 811 return (EFX_PHY_CAP_1000FDX); 812 case EFX_LINK_10000FDX: 813 return (EFX_PHY_CAP_10000FDX); 814 case EFX_LINK_40000FDX: 815 return (EFX_PHY_CAP_40000FDX); 816 default: 817 EFSYS_ASSERT(B_FALSE); 818 return (EFX_PHY_CAP_INVALID); 819 } 820 } 821 822 static int 823 sfxge_phy_cap_mask(struct sfxge_softc *sc, int ifmedia, uint32_t *phy_cap_mask) 824 { 825 /* Get global options (duplex), type and subtype bits */ 826 int ifmedia_masked = ifmedia & (IFM_GMASK | IFM_NMASK | IFM_TMASK); 827 efx_phy_media_type_t medium_type; 828 boolean_t mode_found = B_FALSE; 829 uint32_t cap_mask, mode_cap_mask; 830 efx_link_mode_t mode; 831 efx_phy_cap_type_t phy_cap; 832 833 efx_phy_media_type_get(sc->enp, &medium_type); 834 if (medium_type >= nitems(sfxge_link_mode)) { 835 if_printf(sc->ifnet, "unexpected media type %d\n", medium_type); 836 return (EINVAL); 837 } 838 839 efx_phy_adv_cap_get(sc->enp, EFX_PHY_CAP_PERM, &cap_mask); 840 841 for (mode = EFX_LINK_10HDX; mode < EFX_LINK_NMODES; mode++) { 842 if (ifmedia_masked == sfxge_link_mode[medium_type][mode]) { 843 mode_found = B_TRUE; 844 break; 845 } 846 } 847 848 if (!mode_found) { 849 /* 850 * If media is not in the table, it must be IFM_AUTO. 851 */ 852 KASSERT((cap_mask & (1 << EFX_PHY_CAP_AN)) && 853 ifmedia_masked == (IFM_ETHER | IFM_AUTO), 854 ("%s: no mode for media %#x", __func__, ifmedia)); 855 *phy_cap_mask = (cap_mask & ~(1 << EFX_PHY_CAP_ASYM)); 856 return (0); 857 } 858 859 phy_cap = sfxge_link_mode_to_phy_cap(mode); 860 if (phy_cap == EFX_PHY_CAP_INVALID) { 861 if_printf(sc->ifnet, 862 "cannot map link mode %d to phy capability\n", 863 mode); 864 return (EINVAL); 865 } 866 867 mode_cap_mask = (1 << phy_cap); 868 mode_cap_mask |= cap_mask & (1 << EFX_PHY_CAP_AN); 869 #ifdef SFXGE_HAVE_PAUSE_MEDIAOPTS 870 if (ifmedia & IFM_ETH_RXPAUSE) 871 mode_cap_mask |= cap_mask & (1 << EFX_PHY_CAP_PAUSE); 872 if (!(ifmedia & IFM_ETH_TXPAUSE)) 873 mode_cap_mask |= cap_mask & (1 << EFX_PHY_CAP_ASYM); 874 #else 875 mode_cap_mask |= cap_mask & (1 << EFX_PHY_CAP_PAUSE); 876 #endif 877 878 *phy_cap_mask = mode_cap_mask; 879 return (0); 880 } 881 882 static int 883 sfxge_media_change(struct ifnet *ifp) 884 { 885 struct sfxge_softc *sc; 886 struct ifmedia_entry *ifm; 887 int rc; 888 uint32_t phy_cap_mask; 889 890 sc = ifp->if_softc; 891 ifm = sc->media.ifm_cur; 892 893 SFXGE_ADAPTER_LOCK(sc); 894 895 if (!SFXGE_RUNNING(sc)) { 896 rc = 0; 897 goto out; 898 } 899 900 rc = efx_mac_fcntl_set(sc->enp, sfxge_port_wanted_fc(sc), B_TRUE); 901 if (rc != 0) 902 goto out; 903 904 if ((rc = sfxge_phy_cap_mask(sc, ifm->ifm_media, &phy_cap_mask)) != 0) 905 goto out; 906 907 rc = efx_phy_adv_cap_set(sc->enp, phy_cap_mask); 908 out: 909 SFXGE_ADAPTER_UNLOCK(sc); 910 911 return (rc); 912 } 913 914 int sfxge_port_ifmedia_init(struct sfxge_softc *sc) 915 { 916 efx_phy_media_type_t medium_type; 917 uint32_t cap_mask, mode_cap_mask; 918 efx_link_mode_t mode; 919 efx_phy_cap_type_t phy_cap; 920 int mode_ifm, best_mode_ifm = 0; 921 int rc; 922 923 /* 924 * We need port state to initialise the ifmedia list. 925 * It requires initialized NIC what is already done in 926 * sfxge_create() when resources are estimated. 927 */ 928 if ((rc = efx_filter_init(sc->enp)) != 0) 929 goto out1; 930 if ((rc = efx_port_init(sc->enp)) != 0) 931 goto out2; 932 933 /* 934 * Register ifconfig callbacks for querying and setting the 935 * link mode and link status. 936 */ 937 ifmedia_init(&sc->media, IFM_IMASK, sfxge_media_change, 938 sfxge_media_status); 939 940 /* 941 * Map firmware medium type and capabilities to ifmedia types. 942 * ifmedia does not distinguish between forcing the link mode 943 * and disabling auto-negotiation. 1000BASE-T and 10GBASE-T 944 * require AN even if only one link mode is enabled, and for 945 * 100BASE-TX it is useful even if the link mode is forced. 946 * Therefore we never disable auto-negotiation. 947 * 948 * Also enable and advertise flow control by default. 949 */ 950 951 efx_phy_media_type_get(sc->enp, &medium_type); 952 efx_phy_adv_cap_get(sc->enp, EFX_PHY_CAP_PERM, &cap_mask); 953 954 for (mode = EFX_LINK_10HDX; mode < EFX_LINK_NMODES; mode++) { 955 phy_cap = sfxge_link_mode_to_phy_cap(mode); 956 if (phy_cap == EFX_PHY_CAP_INVALID) 957 continue; 958 959 mode_cap_mask = (1 << phy_cap); 960 mode_ifm = sfxge_link_mode[medium_type][mode]; 961 962 if ((cap_mask & mode_cap_mask) && mode_ifm) { 963 /* No flow-control */ 964 ifmedia_add(&sc->media, mode_ifm, 0, NULL); 965 966 #ifdef SFXGE_HAVE_PAUSE_MEDIAOPTS 967 /* Respond-only. If using AN, we implicitly 968 * offer symmetric as well, but that doesn't 969 * mean we *have* to generate pause frames. 970 */ 971 mode_ifm |= IFM_ETH_RXPAUSE; 972 ifmedia_add(&sc->media, mode_ifm, 0, NULL); 973 974 /* Symmetric */ 975 mode_ifm |= IFM_ETH_TXPAUSE; 976 ifmedia_add(&sc->media, mode_ifm, 0, NULL); 977 #endif 978 979 /* Link modes are numbered in order of speed, 980 * so assume the last one available is the best. 981 */ 982 best_mode_ifm = mode_ifm; 983 } 984 } 985 986 if (cap_mask & (1 << EFX_PHY_CAP_AN)) { 987 /* Add autoselect mode. */ 988 mode_ifm = IFM_ETHER | IFM_AUTO; 989 ifmedia_add(&sc->media, mode_ifm, 0, NULL); 990 best_mode_ifm = mode_ifm; 991 } 992 993 if (best_mode_ifm != 0) 994 ifmedia_set(&sc->media, best_mode_ifm); 995 996 /* Now discard port state until interface is started. */ 997 efx_port_fini(sc->enp); 998 out2: 999 efx_filter_fini(sc->enp); 1000 out1: 1001 return (rc); 1002 } 1003