1 /*- 2 * Copyright (c) 2010-2011 Solarflare Communications, Inc. 3 * All rights reserved. 4 * 5 * This software was developed in part by Philip Paeps under contract for 6 * Solarflare Communications, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/types.h> 34 #include <net/ethernet.h> 35 #include <net/if_dl.h> 36 37 #include "common/efx.h" 38 39 #include "sfxge.h" 40 41 static int 42 sfxge_mac_stat_update(struct sfxge_softc *sc) 43 { 44 struct sfxge_port *port = &sc->port; 45 efsys_mem_t *esmp = &(port->mac_stats.dma_buf); 46 clock_t now; 47 unsigned int count; 48 int rc; 49 50 mtx_lock(&port->lock); 51 52 if (port->init_state != SFXGE_PORT_STARTED) { 53 rc = 0; 54 goto out; 55 } 56 57 now = ticks; 58 if (now - port->mac_stats.update_time < hz) { 59 rc = 0; 60 goto out; 61 } 62 63 port->mac_stats.update_time = now; 64 65 /* If we're unlucky enough to read statistics wduring the DMA, wait 66 * up to 10ms for it to finish (typically takes <500us) */ 67 for (count = 0; count < 100; ++count) { 68 EFSYS_PROBE1(wait, unsigned int, count); 69 70 /* Synchronize the DMA memory for reading */ 71 bus_dmamap_sync(esmp->esm_tag, esmp->esm_map, 72 BUS_DMASYNC_POSTREAD); 73 74 /* Try to update the cached counters */ 75 if ((rc = efx_mac_stats_update(sc->enp, esmp, 76 port->mac_stats.decode_buf, NULL)) != EAGAIN) 77 goto out; 78 79 DELAY(100); 80 } 81 82 rc = ETIMEDOUT; 83 out: 84 mtx_unlock(&port->lock); 85 return rc; 86 } 87 88 static int 89 sfxge_mac_stat_handler(SYSCTL_HANDLER_ARGS) 90 { 91 struct sfxge_softc *sc = arg1; 92 unsigned int id = arg2; 93 int rc; 94 95 if ((rc = sfxge_mac_stat_update(sc)) != 0) 96 return rc; 97 98 return SYSCTL_OUT(req, 99 (uint64_t *)sc->port.mac_stats.decode_buf + id, 100 sizeof(uint64_t)); 101 } 102 103 static void 104 sfxge_mac_stat_init(struct sfxge_softc *sc) 105 { 106 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->dev); 107 struct sysctl_oid_list *stat_list; 108 unsigned int id; 109 const char *name; 110 111 stat_list = SYSCTL_CHILDREN(sc->stats_node); 112 113 /* Initialise the named stats */ 114 for (id = 0; id < EFX_MAC_NSTATS; id++) { 115 name = efx_mac_stat_name(sc->enp, id); 116 SYSCTL_ADD_PROC( 117 ctx, stat_list, 118 OID_AUTO, name, CTLTYPE_U64|CTLFLAG_RD, 119 sc, id, sfxge_mac_stat_handler, "Q", 120 ""); 121 } 122 } 123 124 #ifdef SFXGE_HAVE_PAUSE_MEDIAOPTS 125 126 static unsigned int 127 sfxge_port_wanted_fc(struct sfxge_softc *sc) 128 { 129 struct ifmedia_entry *ifm = sc->media.ifm_cur; 130 131 if (ifm->ifm_media == (IFM_ETHER | IFM_AUTO)) 132 return EFX_FCNTL_RESPOND | EFX_FCNTL_GENERATE; 133 return ((ifm->ifm_media & IFM_ETH_RXPAUSE) ? EFX_FCNTL_RESPOND : 0) | 134 ((ifm->ifm_media & IFM_ETH_TXPAUSE) ? EFX_FCNTL_GENERATE : 0); 135 } 136 137 static unsigned int 138 sfxge_port_link_fc_ifm(struct sfxge_softc *sc) 139 { 140 unsigned int wanted_fc, link_fc; 141 142 efx_mac_fcntl_get(sc->enp, &wanted_fc, &link_fc); 143 return ((link_fc & EFX_FCNTL_RESPOND) ? IFM_ETH_RXPAUSE : 0) | 144 ((link_fc & EFX_FCNTL_GENERATE) ? IFM_ETH_TXPAUSE : 0); 145 } 146 147 #else /* !SFXGE_HAVE_PAUSE_MEDIAOPTS */ 148 149 static unsigned int 150 sfxge_port_wanted_fc(struct sfxge_softc *sc) 151 { 152 return sc->port.wanted_fc; 153 } 154 155 static unsigned int 156 sfxge_port_link_fc_ifm(struct sfxge_softc *sc) 157 { 158 return 0; 159 } 160 161 static int 162 sfxge_port_wanted_fc_handler(SYSCTL_HANDLER_ARGS) 163 { 164 struct sfxge_softc *sc; 165 struct sfxge_port *port; 166 unsigned int fcntl; 167 int error; 168 169 sc = arg1; 170 port = &sc->port; 171 172 mtx_lock(&port->lock); 173 174 if (req->newptr) { 175 if ((error = SYSCTL_IN(req, &fcntl, sizeof(fcntl))) != 0) 176 goto out; 177 178 if (port->wanted_fc == fcntl) 179 goto out; 180 181 port->wanted_fc = fcntl; 182 183 if (port->init_state != SFXGE_PORT_STARTED) 184 goto out; 185 186 error = efx_mac_fcntl_set(sc->enp, port->wanted_fc, B_TRUE); 187 } else { 188 error = SYSCTL_OUT(req, &port->wanted_fc, 189 sizeof(port->wanted_fc)); 190 } 191 192 out: 193 mtx_unlock(&port->lock); 194 195 return (error); 196 } 197 198 static int 199 sfxge_port_link_fc_handler(SYSCTL_HANDLER_ARGS) 200 { 201 struct sfxge_softc *sc; 202 struct sfxge_port *port; 203 unsigned int wanted_fc, link_fc; 204 int error; 205 206 sc = arg1; 207 port = &sc->port; 208 209 mtx_lock(&port->lock); 210 if (port->init_state == SFXGE_PORT_STARTED && SFXGE_LINK_UP(sc)) 211 efx_mac_fcntl_get(sc->enp, &wanted_fc, &link_fc); 212 else 213 link_fc = 0; 214 error = SYSCTL_OUT(req, &link_fc, sizeof(link_fc)); 215 mtx_unlock(&port->lock); 216 217 return (error); 218 } 219 220 #endif /* SFXGE_HAVE_PAUSE_MEDIAOPTS */ 221 222 static const int sfxge_link_speed_kbit[EFX_LINK_NMODES] = { 223 [EFX_LINK_10HDX] = 10000, 224 [EFX_LINK_10FDX] = 10000, 225 [EFX_LINK_100HDX] = 100000, 226 [EFX_LINK_100FDX] = 100000, 227 [EFX_LINK_1000HDX] = 1000000, 228 [EFX_LINK_1000FDX] = 1000000, 229 [EFX_LINK_10000FDX] = 10000000, 230 }; 231 232 void 233 sfxge_mac_link_update(struct sfxge_softc *sc, efx_link_mode_t mode) 234 { 235 struct sfxge_port *port; 236 int link_state; 237 238 port = &sc->port; 239 240 if (port->link_mode == mode) 241 return; 242 243 port->link_mode = mode; 244 245 /* Push link state update to the OS */ 246 link_state = (port->link_mode != EFX_LINK_DOWN ? 247 LINK_STATE_UP : LINK_STATE_DOWN); 248 sc->ifnet->if_baudrate = sfxge_link_speed_kbit[port->link_mode]; 249 if_link_state_change(sc->ifnet, link_state); 250 } 251 252 static void 253 sfxge_mac_poll_work(void *arg, int npending) 254 { 255 struct sfxge_softc *sc; 256 efx_nic_t *enp; 257 struct sfxge_port *port; 258 efx_link_mode_t mode; 259 260 sc = (struct sfxge_softc *)arg; 261 enp = sc->enp; 262 port = &sc->port; 263 264 mtx_lock(&port->lock); 265 266 if (port->init_state != SFXGE_PORT_STARTED) 267 goto done; 268 269 /* This may sleep waiting for MCDI completion */ 270 (void)efx_port_poll(enp, &mode); 271 sfxge_mac_link_update(sc, mode); 272 273 done: 274 mtx_unlock(&port->lock); 275 } 276 277 static int 278 sfxge_mac_filter_set_locked(struct sfxge_softc *sc) 279 { 280 unsigned int bucket[EFX_MAC_HASH_BITS]; 281 struct ifnet *ifp = sc->ifnet; 282 struct ifmultiaddr *ifma; 283 struct sockaddr_dl *sa; 284 efx_nic_t *enp = sc->enp; 285 unsigned int index; 286 int rc; 287 288 /* Set promisc-unicast and broadcast filter bits */ 289 if ((rc = efx_mac_filter_set(enp, !!(ifp->if_flags & IFF_PROMISC), 290 B_TRUE)) != 0) 291 return rc; 292 293 /* Set multicast hash filter */ 294 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) { 295 for (index = 0; index < EFX_MAC_HASH_BITS; index++) 296 bucket[index] = 1; 297 } else { 298 /* Broadcast frames also go through the multicast 299 * filter, and the broadcast address hashes to 300 * 0xff. */ 301 bucket[0xff] = 1; 302 303 IF_ADDR_LOCK(ifp); 304 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 305 if (ifma->ifma_addr->sa_family == AF_LINK) { 306 sa = (struct sockaddr_dl *)ifma->ifma_addr; 307 index = ether_crc32_le(LLADDR(sa), 6) & 0xff; 308 bucket[index] = 1; 309 } 310 } 311 IF_ADDR_UNLOCK(ifp); 312 } 313 return efx_mac_hash_set(enp, bucket); 314 } 315 316 int 317 sfxge_mac_filter_set(struct sfxge_softc *sc) 318 { 319 struct sfxge_port *port = &sc->port; 320 int rc; 321 322 KASSERT(port->init_state == SFXGE_PORT_STARTED, ("port not started")); 323 324 mtx_lock(&port->lock); 325 rc = sfxge_mac_filter_set_locked(sc); 326 mtx_unlock(&port->lock); 327 return rc; 328 } 329 330 void 331 sfxge_port_stop(struct sfxge_softc *sc) 332 { 333 struct sfxge_port *port; 334 efx_nic_t *enp; 335 336 port = &sc->port; 337 enp = sc->enp; 338 339 mtx_lock(&port->lock); 340 341 KASSERT(port->init_state == SFXGE_PORT_STARTED, 342 ("port not started")); 343 344 port->init_state = SFXGE_PORT_INITIALIZED; 345 346 port->mac_stats.update_time = 0; 347 348 /* This may call MCDI */ 349 (void)efx_mac_drain(enp, B_TRUE); 350 351 (void)efx_mac_stats_periodic(enp, &port->mac_stats.dma_buf, 0, B_FALSE); 352 353 port->link_mode = EFX_LINK_UNKNOWN; 354 355 /* Destroy the common code port object. */ 356 efx_port_fini(sc->enp); 357 358 mtx_unlock(&port->lock); 359 } 360 361 int 362 sfxge_port_start(struct sfxge_softc *sc) 363 { 364 uint8_t mac_addr[ETHER_ADDR_LEN]; 365 struct ifnet *ifp = sc->ifnet; 366 struct sfxge_port *port; 367 efx_nic_t *enp; 368 size_t pdu; 369 int rc; 370 371 port = &sc->port; 372 enp = sc->enp; 373 374 mtx_lock(&port->lock); 375 376 KASSERT(port->init_state == SFXGE_PORT_INITIALIZED, 377 ("port not initialized")); 378 379 /* Initialize the port object in the common code. */ 380 if ((rc = efx_port_init(sc->enp)) != 0) 381 goto fail; 382 383 /* Set the SDU */ 384 pdu = EFX_MAC_PDU(ifp->if_mtu); 385 if ((rc = efx_mac_pdu_set(enp, pdu)) != 0) 386 goto fail2; 387 388 if ((rc = efx_mac_fcntl_set(enp, sfxge_port_wanted_fc(sc), B_TRUE)) 389 != 0) 390 goto fail2; 391 392 /* Set the unicast address */ 393 IF_ADDR_LOCK(ifp); 394 bcopy(LLADDR((struct sockaddr_dl *)ifp->if_addr->ifa_addr), 395 mac_addr, sizeof(mac_addr)); 396 IF_ADDR_UNLOCK(ifp); 397 if ((rc = efx_mac_addr_set(enp, mac_addr)) != 0) 398 goto fail; 399 400 sfxge_mac_filter_set_locked(sc); 401 402 /* Update MAC stats by DMA every second */ 403 if ((rc = efx_mac_stats_periodic(enp, &port->mac_stats.dma_buf, 404 1000, B_FALSE)) != 0) 405 goto fail2; 406 407 if ((rc = efx_mac_drain(enp, B_FALSE)) != 0) 408 goto fail3; 409 410 if ((rc = efx_phy_adv_cap_set(sc->enp, sc->media.ifm_cur->ifm_data)) 411 != 0) 412 goto fail4; 413 414 port->init_state = SFXGE_PORT_STARTED; 415 416 /* Single poll in case there were missing initial events */ 417 mtx_unlock(&port->lock); 418 sfxge_mac_poll_work(sc, 0); 419 420 return (0); 421 422 fail4: 423 (void)efx_mac_drain(enp, B_TRUE); 424 fail3: 425 (void)efx_mac_stats_periodic(enp, &port->mac_stats.dma_buf, 426 0, B_FALSE); 427 fail2: 428 efx_port_fini(sc->enp); 429 fail: 430 mtx_unlock(&port->lock); 431 432 return (rc); 433 } 434 435 static int 436 sfxge_phy_stat_update(struct sfxge_softc *sc) 437 { 438 struct sfxge_port *port = &sc->port; 439 efsys_mem_t *esmp = &port->phy_stats.dma_buf; 440 clock_t now; 441 unsigned int count; 442 int rc; 443 444 mtx_lock(&port->lock); 445 446 if (port->init_state != SFXGE_PORT_STARTED) { 447 rc = 0; 448 goto out; 449 } 450 451 now = ticks; 452 if (now - port->phy_stats.update_time < hz) { 453 rc = 0; 454 goto out; 455 } 456 457 port->phy_stats.update_time = now; 458 459 /* If we're unlucky enough to read statistics wduring the DMA, wait 460 * up to 10ms for it to finish (typically takes <500us) */ 461 for (count = 0; count < 100; ++count) { 462 EFSYS_PROBE1(wait, unsigned int, count); 463 464 /* Synchronize the DMA memory for reading */ 465 bus_dmamap_sync(esmp->esm_tag, esmp->esm_map, 466 BUS_DMASYNC_POSTREAD); 467 468 /* Try to update the cached counters */ 469 if ((rc = efx_phy_stats_update(sc->enp, esmp, 470 port->phy_stats.decode_buf)) != EAGAIN) 471 goto out; 472 473 DELAY(100); 474 } 475 476 rc = ETIMEDOUT; 477 out: 478 mtx_unlock(&port->lock); 479 return rc; 480 } 481 482 static int 483 sfxge_phy_stat_handler(SYSCTL_HANDLER_ARGS) 484 { 485 struct sfxge_softc *sc = arg1; 486 unsigned int id = arg2; 487 int rc; 488 489 if ((rc = sfxge_phy_stat_update(sc)) != 0) 490 return rc; 491 492 return SYSCTL_OUT(req, 493 (uint32_t *)sc->port.phy_stats.decode_buf + id, 494 sizeof(uint32_t)); 495 } 496 497 static void 498 sfxge_phy_stat_init(struct sfxge_softc *sc) 499 { 500 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->dev); 501 struct sysctl_oid_list *stat_list; 502 unsigned int id; 503 const char *name; 504 uint64_t stat_mask = efx_nic_cfg_get(sc->enp)->enc_phy_stat_mask; 505 506 stat_list = SYSCTL_CHILDREN(sc->stats_node); 507 508 /* Initialise the named stats */ 509 for (id = 0; id < EFX_PHY_NSTATS; id++) { 510 if (!(stat_mask & ((uint64_t)1 << id))) 511 continue; 512 name = efx_phy_stat_name(sc->enp, id); 513 SYSCTL_ADD_PROC( 514 ctx, stat_list, 515 OID_AUTO, name, CTLTYPE_UINT|CTLFLAG_RD, 516 sc, id, sfxge_phy_stat_handler, 517 id == EFX_PHY_STAT_OUI ? "IX" : "IU", 518 ""); 519 } 520 } 521 522 void 523 sfxge_port_fini(struct sfxge_softc *sc) 524 { 525 struct sfxge_port *port; 526 efsys_mem_t *esmp; 527 528 port = &sc->port; 529 esmp = &port->mac_stats.dma_buf; 530 531 KASSERT(port->init_state == SFXGE_PORT_INITIALIZED, 532 ("Port not initialized")); 533 534 port->init_state = SFXGE_PORT_UNINITIALIZED; 535 536 port->link_mode = EFX_LINK_UNKNOWN; 537 538 /* Finish with PHY DMA memory */ 539 sfxge_dma_free(&port->phy_stats.dma_buf); 540 free(port->phy_stats.decode_buf, M_SFXGE); 541 542 sfxge_dma_free(esmp); 543 free(port->mac_stats.decode_buf, M_SFXGE); 544 545 mtx_destroy(&port->lock); 546 547 port->sc = NULL; 548 } 549 550 int 551 sfxge_port_init(struct sfxge_softc *sc) 552 { 553 struct sfxge_port *port; 554 struct sysctl_ctx_list *sysctl_ctx; 555 struct sysctl_oid *sysctl_tree; 556 efsys_mem_t *mac_stats_buf, *phy_stats_buf; 557 int rc; 558 559 port = &sc->port; 560 mac_stats_buf = &port->mac_stats.dma_buf; 561 phy_stats_buf = &port->phy_stats.dma_buf; 562 563 KASSERT(port->init_state == SFXGE_PORT_UNINITIALIZED, 564 ("Port already initialized")); 565 566 port->sc = sc; 567 568 mtx_init(&port->lock, "sfxge_port", NULL, MTX_DEF); 569 570 port->phy_stats.decode_buf = malloc(EFX_PHY_NSTATS * sizeof(uint32_t), 571 M_SFXGE, M_WAITOK | M_ZERO); 572 if ((rc = sfxge_dma_alloc(sc, EFX_PHY_STATS_SIZE, phy_stats_buf)) != 0) 573 goto fail; 574 bzero(phy_stats_buf->esm_base, phy_stats_buf->esm_size); 575 sfxge_phy_stat_init(sc); 576 577 sysctl_ctx = device_get_sysctl_ctx(sc->dev); 578 sysctl_tree = device_get_sysctl_tree(sc->dev); 579 580 #ifndef SFXGE_HAVE_PAUSE_MEDIAOPTS 581 /* If flow control cannot be configured or reported through 582 * ifmedia, provide sysctls for it. */ 583 port->wanted_fc = EFX_FCNTL_RESPOND | EFX_FCNTL_GENERATE; 584 SYSCTL_ADD_PROC(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), OID_AUTO, 585 "wanted_fc", CTLTYPE_UINT|CTLFLAG_RW, sc, 0, 586 sfxge_port_wanted_fc_handler, "IU", "wanted flow control mode"); 587 SYSCTL_ADD_PROC(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), OID_AUTO, 588 "link_fc", CTLTYPE_UINT|CTLFLAG_RD, sc, 0, 589 sfxge_port_link_fc_handler, "IU", "link flow control mode"); 590 #endif 591 592 port->mac_stats.decode_buf = malloc(EFX_MAC_NSTATS * sizeof(uint64_t), 593 M_SFXGE, M_WAITOK | M_ZERO); 594 if ((rc = sfxge_dma_alloc(sc, EFX_MAC_STATS_SIZE, mac_stats_buf)) != 0) 595 goto fail2; 596 bzero(mac_stats_buf->esm_base, mac_stats_buf->esm_size); 597 sfxge_mac_stat_init(sc); 598 599 port->init_state = SFXGE_PORT_INITIALIZED; 600 601 return (0); 602 603 fail2: 604 free(port->mac_stats.decode_buf, M_SFXGE); 605 sfxge_dma_free(phy_stats_buf); 606 fail: 607 free(port->phy_stats.decode_buf, M_SFXGE); 608 (void)mtx_destroy(&port->lock); 609 port->sc = NULL; 610 return rc; 611 } 612 613 static int sfxge_link_mode[EFX_PHY_MEDIA_NTYPES][EFX_LINK_NMODES] = { 614 [EFX_PHY_MEDIA_CX4] = { 615 [EFX_LINK_10000FDX] = IFM_ETHER | IFM_FDX | IFM_10G_CX4, 616 }, 617 [EFX_PHY_MEDIA_KX4] = { 618 [EFX_LINK_10000FDX] = IFM_ETHER | IFM_FDX | IFM_10G_KX4, 619 }, 620 [EFX_PHY_MEDIA_XFP] = { 621 /* Don't know the module type, but assume SR for now. */ 622 [EFX_LINK_10000FDX] = IFM_ETHER | IFM_FDX | IFM_10G_SR, 623 }, 624 [EFX_PHY_MEDIA_SFP_PLUS] = { 625 /* Don't know the module type, but assume SX/SR for now. */ 626 [EFX_LINK_1000FDX] = IFM_ETHER | IFM_FDX | IFM_1000_SX, 627 [EFX_LINK_10000FDX] = IFM_ETHER | IFM_FDX | IFM_10G_SR, 628 }, 629 [EFX_PHY_MEDIA_BASE_T] = { 630 [EFX_LINK_10HDX] = IFM_ETHER | IFM_HDX | IFM_10_T, 631 [EFX_LINK_10FDX] = IFM_ETHER | IFM_FDX | IFM_10_T, 632 [EFX_LINK_100HDX] = IFM_ETHER | IFM_HDX | IFM_100_TX, 633 [EFX_LINK_100FDX] = IFM_ETHER | IFM_FDX | IFM_100_TX, 634 [EFX_LINK_1000HDX] = IFM_ETHER | IFM_HDX | IFM_1000_T, 635 [EFX_LINK_1000FDX] = IFM_ETHER | IFM_FDX | IFM_1000_T, 636 [EFX_LINK_10000FDX] = IFM_ETHER | IFM_FDX | IFM_10G_T, 637 }, 638 }; 639 640 static void 641 sfxge_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 642 { 643 struct sfxge_softc *sc; 644 efx_phy_media_type_t medium_type; 645 efx_link_mode_t mode; 646 647 sc = ifp->if_softc; 648 sx_xlock(&sc->softc_lock); 649 650 ifmr->ifm_status = IFM_AVALID; 651 ifmr->ifm_active = IFM_ETHER; 652 653 if (SFXGE_RUNNING(sc) && SFXGE_LINK_UP(sc)) { 654 ifmr->ifm_status |= IFM_ACTIVE; 655 656 efx_phy_media_type_get(sc->enp, &medium_type); 657 mode = sc->port.link_mode; 658 ifmr->ifm_active |= sfxge_link_mode[medium_type][mode]; 659 ifmr->ifm_active |= sfxge_port_link_fc_ifm(sc); 660 } 661 662 sx_xunlock(&sc->softc_lock); 663 } 664 665 static int 666 sfxge_media_change(struct ifnet *ifp) 667 { 668 struct sfxge_softc *sc; 669 struct ifmedia_entry *ifm; 670 int rc; 671 672 sc = ifp->if_softc; 673 ifm = sc->media.ifm_cur; 674 675 sx_xlock(&sc->softc_lock); 676 677 if (!SFXGE_RUNNING(sc)) { 678 rc = 0; 679 goto out; 680 } 681 682 rc = efx_mac_fcntl_set(sc->enp, sfxge_port_wanted_fc(sc), B_TRUE); 683 if (rc != 0) 684 goto out; 685 686 rc = efx_phy_adv_cap_set(sc->enp, ifm->ifm_data); 687 out: 688 sx_xunlock(&sc->softc_lock); 689 690 return rc; 691 } 692 693 int sfxge_port_ifmedia_init(struct sfxge_softc *sc) 694 { 695 efx_phy_media_type_t medium_type; 696 uint32_t cap_mask, mode_cap_mask; 697 efx_link_mode_t mode; 698 int mode_ifm, best_mode_ifm = 0; 699 int rc; 700 701 /* We need port state to initialise the ifmedia list. */ 702 if ((rc = efx_nic_init(sc->enp)) != 0) 703 goto out; 704 if ((rc = efx_port_init(sc->enp)) != 0) 705 goto out2; 706 707 /* 708 * Register ifconfig callbacks for querying and setting the 709 * link mode and link status. 710 */ 711 ifmedia_init(&sc->media, IFM_IMASK, sfxge_media_change, 712 sfxge_media_status); 713 714 /* 715 * Map firmware medium type and capabilities to ifmedia types. 716 * ifmedia does not distinguish between forcing the link mode 717 * and disabling auto-negotiation. 1000BASE-T and 10GBASE-T 718 * require AN even if only one link mode is enabled, and for 719 * 100BASE-TX it is useful even if the link mode is forced. 720 * Therefore we never disable auto-negotiation. 721 * 722 * Also enable and advertise flow control by default. 723 */ 724 725 efx_phy_media_type_get(sc->enp, &medium_type); 726 efx_phy_adv_cap_get(sc->enp, EFX_PHY_CAP_PERM, &cap_mask); 727 728 EFX_STATIC_ASSERT(EFX_LINK_10HDX == EFX_PHY_CAP_10HDX + 1); 729 EFX_STATIC_ASSERT(EFX_LINK_10FDX == EFX_PHY_CAP_10FDX + 1); 730 EFX_STATIC_ASSERT(EFX_LINK_100HDX == EFX_PHY_CAP_100HDX + 1); 731 EFX_STATIC_ASSERT(EFX_LINK_100FDX == EFX_PHY_CAP_100FDX + 1); 732 EFX_STATIC_ASSERT(EFX_LINK_1000HDX == EFX_PHY_CAP_1000HDX + 1); 733 EFX_STATIC_ASSERT(EFX_LINK_1000FDX == EFX_PHY_CAP_1000FDX + 1); 734 EFX_STATIC_ASSERT(EFX_LINK_10000FDX == EFX_PHY_CAP_10000FDX + 1); 735 736 for (mode = EFX_LINK_10HDX; mode <= EFX_LINK_10000FDX; mode++) { 737 mode_cap_mask = 1 << (mode - 1); 738 mode_ifm = sfxge_link_mode[medium_type][mode]; 739 740 if ((cap_mask & mode_cap_mask) && mode_ifm) { 741 mode_cap_mask |= cap_mask & (1 << EFX_PHY_CAP_AN); 742 743 #ifdef SFXGE_HAVE_PAUSE_MEDIAOPTS 744 /* No flow-control */ 745 ifmedia_add(&sc->media, mode_ifm, mode_cap_mask, NULL); 746 747 /* Respond-only. If using AN, we implicitly 748 * offer symmetric as well, but that doesn't 749 * mean we *have* to generate pause frames. 750 */ 751 mode_cap_mask |= cap_mask & ((1 << EFX_PHY_CAP_PAUSE) | 752 (1 << EFX_PHY_CAP_ASYM)); 753 mode_ifm |= IFM_ETH_RXPAUSE; 754 ifmedia_add(&sc->media, mode_ifm, mode_cap_mask, NULL); 755 756 /* Symmetric */ 757 mode_cap_mask &= ~(1 << EFX_PHY_CAP_ASYM); 758 mode_ifm |= IFM_ETH_TXPAUSE; 759 #else /* !SFXGE_HAVE_PAUSE_MEDIAOPTS */ 760 mode_cap_mask |= cap_mask & (1 << EFX_PHY_CAP_PAUSE); 761 #endif 762 ifmedia_add(&sc->media, mode_ifm, mode_cap_mask, NULL); 763 764 /* Link modes are numbered in order of speed, 765 * so assume the last one available is the best. 766 */ 767 best_mode_ifm = mode_ifm; 768 } 769 } 770 771 if (cap_mask & (1 << EFX_PHY_CAP_AN)) { 772 /* Add autoselect mode. */ 773 mode_ifm = IFM_ETHER | IFM_AUTO; 774 ifmedia_add(&sc->media, mode_ifm, 775 cap_mask & ~(1 << EFX_PHY_CAP_ASYM), NULL); 776 best_mode_ifm = mode_ifm; 777 } 778 779 if (best_mode_ifm) 780 ifmedia_set(&sc->media, best_mode_ifm); 781 782 /* Now discard port state until interface is started. */ 783 efx_port_fini(sc->enp); 784 out2: 785 efx_nic_fini(sc->enp); 786 out: 787 return rc; 788 } 789