1 /*- 2 * Copyright (c) 2010-2016 Solarflare Communications, Inc. 3 * All rights reserved. 4 * 5 * This software was developed in part by OKTET Labs Ltd. under contract for 6 * Solarflare Communications, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/types.h> 31 #include <sys/malloc.h> 32 33 #include "common/efx.h" 34 #include "sfxge.h" 35 36 /* These data make no real sense, they are here just to make sfupdate happy. 37 * Any code that would rely on it is broken. 38 */ 39 static const uint8_t fake_dynamic_cfg_nvram[] = { 40 0x7a, 0xda, 0x10, 0xef, 0x0c, 0x00, 0x00, 0x00, 41 0x00, 0x05, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 42 0x48, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x10, 43 0x08, 0x00, 0x00, 0x00, 0x90, 0x04, 0x00, 0x52, 44 0x56, 0x01, 0xc3, 0x78, 0x01, 0x00, 0x03, 0x10, 45 0x08, 0x00, 0x00, 0x00, 0x90, 0x04, 0x00, 0x52, 46 0x56, 0x01, 0xc3, 0x78, 0x57, 0x1a, 0x10, 0xef, 47 0x08, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 48 0x02, 0x0b, 0x64, 0x7d, 0xee, 0xee, 0xee, 0xee 49 }; 50 51 static int 52 sfxge_nvram_rw(struct sfxge_softc *sc, sfxge_ioc_t *ip, efx_nvram_type_t type, 53 boolean_t write) 54 { 55 efx_nic_t *enp = sc->enp; 56 size_t total_size = ip->u.nvram.size; 57 size_t chunk_size; 58 off_t off; 59 int rc = 0; 60 uint8_t *buf; 61 62 if (type == EFX_NVRAM_DYNAMIC_CFG && sc->family == EFX_FAMILY_SIENA) { 63 if (write) 64 return (0); 65 rc = copyout(fake_dynamic_cfg_nvram, ip->u.nvram.data, 66 MIN(total_size, sizeof(fake_dynamic_cfg_nvram))); 67 return (rc); 68 } 69 70 if ((rc = efx_nvram_rw_start(enp, type, &chunk_size)) != 0) 71 goto fail1; 72 73 buf = malloc(chunk_size, M_TEMP, M_WAITOK); 74 75 off = 0; 76 while (total_size) { 77 size_t len = MIN(chunk_size, total_size); 78 79 if (write) { 80 rc = copyin(ip->u.nvram.data + off, buf, len); 81 if (rc != 0) 82 goto fail3; 83 rc = efx_nvram_write_chunk(enp, type, 84 ip->u.nvram.offset + off, buf, len); 85 if (rc != 0) 86 goto fail3; 87 } else { 88 rc = efx_nvram_read_chunk(enp, type, 89 ip->u.nvram.offset + off, buf, len); 90 if (rc != 0) 91 goto fail3; 92 rc = copyout(buf, ip->u.nvram.data + off, len); 93 if (rc != 0) 94 goto fail3; 95 } 96 97 total_size -= len; 98 off += len; 99 } 100 101 fail3: 102 free(buf, M_TEMP); 103 efx_nvram_rw_finish(enp, type, NULL); 104 fail1: 105 return (rc); 106 } 107 108 static int 109 sfxge_nvram_erase(struct sfxge_softc *sc, efx_nvram_type_t type) 110 { 111 efx_nic_t *enp = sc->enp; 112 size_t chunk_size; 113 int rc = 0; 114 115 if (type == EFX_NVRAM_DYNAMIC_CFG && sc->family == EFX_FAMILY_SIENA) 116 return (0); 117 118 if ((rc = efx_nvram_rw_start(enp, type, &chunk_size)) != 0) 119 return (rc); 120 121 rc = efx_nvram_erase(enp, type); 122 123 efx_nvram_rw_finish(enp, type, NULL); 124 return (rc); 125 } 126 127 int 128 sfxge_nvram_ioctl(struct sfxge_softc *sc, sfxge_ioc_t *ip) 129 { 130 static const efx_nvram_type_t nvram_types[] = { 131 [SFXGE_NVRAM_TYPE_BOOTROM] = EFX_NVRAM_BOOTROM, 132 [SFXGE_NVRAM_TYPE_BOOTROM_CFG] = EFX_NVRAM_BOOTROM_CFG, 133 [SFXGE_NVRAM_TYPE_MC] = EFX_NVRAM_MC_FIRMWARE, 134 [SFXGE_NVRAM_TYPE_MC_GOLDEN] = EFX_NVRAM_MC_GOLDEN, 135 [SFXGE_NVRAM_TYPE_PHY] = EFX_NVRAM_PHY, 136 [SFXGE_NVRAM_TYPE_NULL_PHY] = EFX_NVRAM_NULLPHY, 137 [SFXGE_NVRAM_TYPE_FPGA] = EFX_NVRAM_FPGA, 138 [SFXGE_NVRAM_TYPE_FCFW] = EFX_NVRAM_FCFW, 139 [SFXGE_NVRAM_TYPE_CPLD] = EFX_NVRAM_CPLD, 140 [SFXGE_NVRAM_TYPE_FPGA_BACKUP] = EFX_NVRAM_FPGA_BACKUP, 141 [SFXGE_NVRAM_TYPE_DYNAMIC_CFG] = EFX_NVRAM_DYNAMIC_CFG, 142 }; 143 144 efx_nic_t *enp = sc->enp; 145 efx_nvram_type_t type; 146 int rc = 0; 147 148 if (ip->u.nvram.type > SFXGE_NVRAM_TYPE_DYNAMIC_CFG) 149 return (EINVAL); 150 type = nvram_types[ip->u.nvram.type]; 151 if (type == EFX_NVRAM_MC_GOLDEN && 152 (ip->u.nvram.op == SFXGE_NVRAM_OP_WRITE || 153 ip->u.nvram.op == SFXGE_NVRAM_OP_ERASE || 154 ip->u.nvram.op == SFXGE_NVRAM_OP_SET_VER)) 155 return (EOPNOTSUPP); 156 157 switch (ip->u.nvram.op) { 158 case SFXGE_NVRAM_OP_SIZE: 159 { 160 size_t size; 161 162 if (type == EFX_NVRAM_DYNAMIC_CFG && sc->family == EFX_FAMILY_SIENA) { 163 ip->u.nvram.size = sizeof(fake_dynamic_cfg_nvram); 164 } else { 165 if ((rc = efx_nvram_size(enp, type, &size)) != 0) 166 return (rc); 167 ip->u.nvram.size = size; 168 } 169 break; 170 } 171 case SFXGE_NVRAM_OP_READ: 172 rc = sfxge_nvram_rw(sc, ip, type, B_FALSE); 173 break; 174 case SFXGE_NVRAM_OP_WRITE: 175 rc = sfxge_nvram_rw(sc, ip, type, B_TRUE); 176 break; 177 case SFXGE_NVRAM_OP_ERASE: 178 rc = sfxge_nvram_erase(sc, type); 179 break; 180 case SFXGE_NVRAM_OP_GET_VER: 181 rc = efx_nvram_get_version(enp, type, &ip->u.nvram.subtype, 182 &ip->u.nvram.version[0]); 183 break; 184 case SFXGE_NVRAM_OP_SET_VER: 185 rc = efx_nvram_set_version(enp, type, &ip->u.nvram.version[0]); 186 break; 187 default: 188 rc = EOPNOTSUPP; 189 break; 190 } 191 192 return (rc); 193 } 194