1 /*- 2 * Copyright (c) 2010-2016 Solarflare Communications, Inc. 3 * All rights reserved. 4 * 5 * This software was developed in part by OKTET Labs Ltd. under contract for 6 * Solarflare Communications, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 #include <sys/types.h> 32 #include <sys/malloc.h> 33 34 #include "common/efx.h" 35 #include "sfxge.h" 36 37 /* These data make no real sense, they are here just to make sfupdate happy. 38 * Any code that would rely on it is broken. 39 */ 40 static const uint8_t fake_dynamic_cfg_nvram[] = { 41 0x7a, 0xda, 0x10, 0xef, 0x0c, 0x00, 0x00, 0x00, 42 0x00, 0x05, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 43 0x48, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x10, 44 0x08, 0x00, 0x00, 0x00, 0x90, 0x04, 0x00, 0x52, 45 0x56, 0x01, 0xc3, 0x78, 0x01, 0x00, 0x03, 0x10, 46 0x08, 0x00, 0x00, 0x00, 0x90, 0x04, 0x00, 0x52, 47 0x56, 0x01, 0xc3, 0x78, 0x57, 0x1a, 0x10, 0xef, 48 0x08, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 49 0x02, 0x0b, 0x64, 0x7d, 0xee, 0xee, 0xee, 0xee 50 }; 51 52 static int 53 sfxge_nvram_rw(struct sfxge_softc *sc, sfxge_ioc_t *ip, efx_nvram_type_t type, 54 boolean_t write) 55 { 56 efx_nic_t *enp = sc->enp; 57 size_t total_size = ip->u.nvram.size; 58 size_t chunk_size; 59 off_t off; 60 int rc = 0; 61 uint8_t *buf; 62 63 if (type == EFX_NVRAM_DYNAMIC_CFG && sc->family == EFX_FAMILY_SIENA) { 64 if (write) 65 return (0); 66 rc = copyout(fake_dynamic_cfg_nvram, ip->u.nvram.data, 67 MIN(total_size, sizeof(fake_dynamic_cfg_nvram))); 68 return (rc); 69 } 70 71 if ((rc = efx_nvram_rw_start(enp, type, &chunk_size)) != 0) 72 goto fail1; 73 74 buf = malloc(chunk_size, M_TEMP, M_WAITOK); 75 76 off = 0; 77 while (total_size) { 78 size_t len = MIN(chunk_size, total_size); 79 80 if (write) { 81 rc = copyin(ip->u.nvram.data + off, buf, len); 82 if (rc != 0) 83 goto fail3; 84 rc = efx_nvram_write_chunk(enp, type, 85 ip->u.nvram.offset + off, buf, len); 86 if (rc != 0) 87 goto fail3; 88 } else { 89 rc = efx_nvram_read_chunk(enp, type, 90 ip->u.nvram.offset + off, buf, len); 91 if (rc != 0) 92 goto fail3; 93 rc = copyout(buf, ip->u.nvram.data + off, len); 94 if (rc != 0) 95 goto fail3; 96 } 97 98 total_size -= len; 99 off += len; 100 } 101 102 fail3: 103 free(buf, M_TEMP); 104 efx_nvram_rw_finish(enp, type, NULL); 105 fail1: 106 return (rc); 107 } 108 109 static int 110 sfxge_nvram_erase(struct sfxge_softc *sc, efx_nvram_type_t type) 111 { 112 efx_nic_t *enp = sc->enp; 113 size_t chunk_size; 114 int rc = 0; 115 116 if (type == EFX_NVRAM_DYNAMIC_CFG && sc->family == EFX_FAMILY_SIENA) 117 return (0); 118 119 if ((rc = efx_nvram_rw_start(enp, type, &chunk_size)) != 0) 120 return (rc); 121 122 rc = efx_nvram_erase(enp, type); 123 124 efx_nvram_rw_finish(enp, type, NULL); 125 return (rc); 126 } 127 128 int 129 sfxge_nvram_ioctl(struct sfxge_softc *sc, sfxge_ioc_t *ip) 130 { 131 static const efx_nvram_type_t nvram_types[] = { 132 [SFXGE_NVRAM_TYPE_BOOTROM] = EFX_NVRAM_BOOTROM, 133 [SFXGE_NVRAM_TYPE_BOOTROM_CFG] = EFX_NVRAM_BOOTROM_CFG, 134 [SFXGE_NVRAM_TYPE_MC] = EFX_NVRAM_MC_FIRMWARE, 135 [SFXGE_NVRAM_TYPE_MC_GOLDEN] = EFX_NVRAM_MC_GOLDEN, 136 [SFXGE_NVRAM_TYPE_PHY] = EFX_NVRAM_PHY, 137 [SFXGE_NVRAM_TYPE_NULL_PHY] = EFX_NVRAM_NULLPHY, 138 [SFXGE_NVRAM_TYPE_FPGA] = EFX_NVRAM_FPGA, 139 [SFXGE_NVRAM_TYPE_FCFW] = EFX_NVRAM_FCFW, 140 [SFXGE_NVRAM_TYPE_CPLD] = EFX_NVRAM_CPLD, 141 [SFXGE_NVRAM_TYPE_FPGA_BACKUP] = EFX_NVRAM_FPGA_BACKUP, 142 [SFXGE_NVRAM_TYPE_DYNAMIC_CFG] = EFX_NVRAM_DYNAMIC_CFG, 143 }; 144 145 efx_nic_t *enp = sc->enp; 146 efx_nvram_type_t type; 147 int rc = 0; 148 149 if (ip->u.nvram.type > SFXGE_NVRAM_TYPE_DYNAMIC_CFG) 150 return (EINVAL); 151 type = nvram_types[ip->u.nvram.type]; 152 if (type == EFX_NVRAM_MC_GOLDEN && 153 (ip->u.nvram.op == SFXGE_NVRAM_OP_WRITE || 154 ip->u.nvram.op == SFXGE_NVRAM_OP_ERASE || 155 ip->u.nvram.op == SFXGE_NVRAM_OP_SET_VER)) 156 return (EOPNOTSUPP); 157 158 switch (ip->u.nvram.op) { 159 case SFXGE_NVRAM_OP_SIZE: 160 { 161 size_t size; 162 163 if (type == EFX_NVRAM_DYNAMIC_CFG && sc->family == EFX_FAMILY_SIENA) { 164 ip->u.nvram.size = sizeof(fake_dynamic_cfg_nvram); 165 } else { 166 if ((rc = efx_nvram_size(enp, type, &size)) != 0) 167 return (rc); 168 ip->u.nvram.size = size; 169 } 170 break; 171 } 172 case SFXGE_NVRAM_OP_READ: 173 rc = sfxge_nvram_rw(sc, ip, type, B_FALSE); 174 break; 175 case SFXGE_NVRAM_OP_WRITE: 176 rc = sfxge_nvram_rw(sc, ip, type, B_TRUE); 177 break; 178 case SFXGE_NVRAM_OP_ERASE: 179 rc = sfxge_nvram_erase(sc, type); 180 break; 181 case SFXGE_NVRAM_OP_GET_VER: 182 rc = efx_nvram_get_version(enp, type, &ip->u.nvram.subtype, 183 &ip->u.nvram.version[0]); 184 break; 185 case SFXGE_NVRAM_OP_SET_VER: 186 rc = efx_nvram_set_version(enp, type, &ip->u.nvram.version[0]); 187 break; 188 default: 189 rc = EOPNOTSUPP; 190 break; 191 } 192 193 return (rc); 194 } 195