1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2009-2016 Solarflare Communications Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 18 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 26 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * The views and conclusions contained in the software and documentation are 29 * those of the authors and should not be interpreted as representing official 30 * policies, either expressed or implied, of the FreeBSD Project. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 #include "efx.h" 37 #include "efx_impl.h" 38 39 #if EFSYS_OPT_SIENA 40 41 static void 42 siena_phy_decode_cap( 43 __in uint32_t mcdi_cap, 44 __out uint32_t *maskp) 45 { 46 uint32_t mask; 47 48 mask = 0; 49 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_10HDX_LBN)) 50 mask |= (1 << EFX_PHY_CAP_10HDX); 51 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_10FDX_LBN)) 52 mask |= (1 << EFX_PHY_CAP_10FDX); 53 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_100HDX_LBN)) 54 mask |= (1 << EFX_PHY_CAP_100HDX); 55 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_100FDX_LBN)) 56 mask |= (1 << EFX_PHY_CAP_100FDX); 57 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_1000HDX_LBN)) 58 mask |= (1 << EFX_PHY_CAP_1000HDX); 59 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_1000FDX_LBN)) 60 mask |= (1 << EFX_PHY_CAP_1000FDX); 61 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_10000FDX_LBN)) 62 mask |= (1 << EFX_PHY_CAP_10000FDX); 63 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_PAUSE_LBN)) 64 mask |= (1 << EFX_PHY_CAP_PAUSE); 65 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_ASYM_LBN)) 66 mask |= (1 << EFX_PHY_CAP_ASYM); 67 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_AN_LBN)) 68 mask |= (1 << EFX_PHY_CAP_AN); 69 70 *maskp = mask; 71 } 72 73 static void 74 siena_phy_decode_link_mode( 75 __in efx_nic_t *enp, 76 __in uint32_t link_flags, 77 __in unsigned int speed, 78 __in unsigned int fcntl, 79 __out efx_link_mode_t *link_modep, 80 __out unsigned int *fcntlp) 81 { 82 boolean_t fd = !!(link_flags & 83 (1 << MC_CMD_GET_LINK_OUT_FULL_DUPLEX_LBN)); 84 boolean_t up = !!(link_flags & 85 (1 << MC_CMD_GET_LINK_OUT_LINK_UP_LBN)); 86 87 _NOTE(ARGUNUSED(enp)) 88 89 if (!up) 90 *link_modep = EFX_LINK_DOWN; 91 else if (speed == 10000 && fd) 92 *link_modep = EFX_LINK_10000FDX; 93 else if (speed == 1000) 94 *link_modep = fd ? EFX_LINK_1000FDX : EFX_LINK_1000HDX; 95 else if (speed == 100) 96 *link_modep = fd ? EFX_LINK_100FDX : EFX_LINK_100HDX; 97 else if (speed == 10) 98 *link_modep = fd ? EFX_LINK_10FDX : EFX_LINK_10HDX; 99 else 100 *link_modep = EFX_LINK_UNKNOWN; 101 102 if (fcntl == MC_CMD_FCNTL_OFF) 103 *fcntlp = 0; 104 else if (fcntl == MC_CMD_FCNTL_RESPOND) 105 *fcntlp = EFX_FCNTL_RESPOND; 106 else if (fcntl == MC_CMD_FCNTL_BIDIR) 107 *fcntlp = EFX_FCNTL_RESPOND | EFX_FCNTL_GENERATE; 108 else { 109 EFSYS_PROBE1(mc_pcol_error, int, fcntl); 110 *fcntlp = 0; 111 } 112 } 113 114 void 115 siena_phy_link_ev( 116 __in efx_nic_t *enp, 117 __in efx_qword_t *eqp, 118 __out efx_link_mode_t *link_modep) 119 { 120 efx_port_t *epp = &(enp->en_port); 121 unsigned int link_flags; 122 unsigned int speed; 123 unsigned int fcntl; 124 efx_link_mode_t link_mode; 125 uint32_t lp_cap_mask; 126 127 /* 128 * Convert the LINKCHANGE speed enumeration into mbit/s, in the 129 * same way as GET_LINK encodes the speed 130 */ 131 switch (MCDI_EV_FIELD(eqp, LINKCHANGE_SPEED)) { 132 case MCDI_EVENT_LINKCHANGE_SPEED_100M: 133 speed = 100; 134 break; 135 case MCDI_EVENT_LINKCHANGE_SPEED_1G: 136 speed = 1000; 137 break; 138 case MCDI_EVENT_LINKCHANGE_SPEED_10G: 139 speed = 10000; 140 break; 141 default: 142 speed = 0; 143 break; 144 } 145 146 link_flags = MCDI_EV_FIELD(eqp, LINKCHANGE_LINK_FLAGS); 147 siena_phy_decode_link_mode(enp, link_flags, speed, 148 MCDI_EV_FIELD(eqp, LINKCHANGE_FCNTL), 149 &link_mode, &fcntl); 150 siena_phy_decode_cap(MCDI_EV_FIELD(eqp, LINKCHANGE_LP_CAP), 151 &lp_cap_mask); 152 153 /* 154 * It's safe to update ep_lp_cap_mask without the driver's port lock 155 * because presumably any concurrently running efx_port_poll() is 156 * only going to arrive at the same value. 157 * 158 * ep_fcntl has two meanings. It's either the link common fcntl 159 * (if the PHY supports AN), or it's the forced link state. If 160 * the former, it's safe to update the value for the same reason as 161 * for ep_lp_cap_mask. If the latter, then just ignore the value, 162 * because we can race with efx_mac_fcntl_set(). 163 */ 164 epp->ep_lp_cap_mask = lp_cap_mask; 165 if (epp->ep_phy_cap_mask & (1 << EFX_PHY_CAP_AN)) 166 epp->ep_fcntl = fcntl; 167 168 *link_modep = link_mode; 169 } 170 171 __checkReturn efx_rc_t 172 siena_phy_power( 173 __in efx_nic_t *enp, 174 __in boolean_t power) 175 { 176 efx_rc_t rc; 177 178 if (!power) 179 return (0); 180 181 /* Check if the PHY is a zombie */ 182 if ((rc = siena_phy_verify(enp)) != 0) 183 goto fail1; 184 185 enp->en_reset_flags |= EFX_RESET_PHY; 186 187 return (0); 188 189 fail1: 190 EFSYS_PROBE1(fail1, efx_rc_t, rc); 191 192 return (rc); 193 } 194 195 __checkReturn efx_rc_t 196 siena_phy_get_link( 197 __in efx_nic_t *enp, 198 __out siena_link_state_t *slsp) 199 { 200 efx_mcdi_req_t req; 201 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_LINK_IN_LEN, 202 MC_CMD_GET_LINK_OUT_LEN); 203 efx_rc_t rc; 204 205 req.emr_cmd = MC_CMD_GET_LINK; 206 req.emr_in_buf = payload; 207 req.emr_in_length = MC_CMD_GET_LINK_IN_LEN; 208 req.emr_out_buf = payload; 209 req.emr_out_length = MC_CMD_GET_LINK_OUT_LEN; 210 211 efx_mcdi_execute(enp, &req); 212 213 if (req.emr_rc != 0) { 214 rc = req.emr_rc; 215 goto fail1; 216 } 217 218 if (req.emr_out_length_used < MC_CMD_GET_LINK_OUT_LEN) { 219 rc = EMSGSIZE; 220 goto fail2; 221 } 222 223 siena_phy_decode_cap(MCDI_OUT_DWORD(req, GET_LINK_OUT_CAP), 224 &slsp->sls_adv_cap_mask); 225 siena_phy_decode_cap(MCDI_OUT_DWORD(req, GET_LINK_OUT_LP_CAP), 226 &slsp->sls_lp_cap_mask); 227 228 siena_phy_decode_link_mode(enp, MCDI_OUT_DWORD(req, GET_LINK_OUT_FLAGS), 229 MCDI_OUT_DWORD(req, GET_LINK_OUT_LINK_SPEED), 230 MCDI_OUT_DWORD(req, GET_LINK_OUT_FCNTL), 231 &slsp->sls_link_mode, &slsp->sls_fcntl); 232 233 #if EFSYS_OPT_LOOPBACK 234 /* Assert the MC_CMD_LOOPBACK and EFX_LOOPBACK namespace agree */ 235 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_NONE == EFX_LOOPBACK_OFF); 236 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_DATA == EFX_LOOPBACK_DATA); 237 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GMAC == EFX_LOOPBACK_GMAC); 238 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XGMII == EFX_LOOPBACK_XGMII); 239 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XGXS == EFX_LOOPBACK_XGXS); 240 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XAUI == EFX_LOOPBACK_XAUI); 241 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GMII == EFX_LOOPBACK_GMII); 242 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SGMII == EFX_LOOPBACK_SGMII); 243 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XGBR == EFX_LOOPBACK_XGBR); 244 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XFI == EFX_LOOPBACK_XFI); 245 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XAUI_FAR == EFX_LOOPBACK_XAUI_FAR); 246 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GMII_FAR == EFX_LOOPBACK_GMII_FAR); 247 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SGMII_FAR == EFX_LOOPBACK_SGMII_FAR); 248 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XFI_FAR == EFX_LOOPBACK_XFI_FAR); 249 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GPHY == EFX_LOOPBACK_GPHY); 250 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PHYXS == EFX_LOOPBACK_PHY_XS); 251 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PCS == EFX_LOOPBACK_PCS); 252 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PMAPMD == EFX_LOOPBACK_PMA_PMD); 253 254 slsp->sls_loopback = MCDI_OUT_DWORD(req, GET_LINK_OUT_LOOPBACK_MODE); 255 #endif /* EFSYS_OPT_LOOPBACK */ 256 257 slsp->sls_mac_up = MCDI_OUT_DWORD(req, GET_LINK_OUT_MAC_FAULT) == 0; 258 259 return (0); 260 261 fail2: 262 EFSYS_PROBE(fail2); 263 fail1: 264 EFSYS_PROBE1(fail1, efx_rc_t, rc); 265 266 return (rc); 267 } 268 269 __checkReturn efx_rc_t 270 siena_phy_reconfigure( 271 __in efx_nic_t *enp) 272 { 273 efx_port_t *epp = &(enp->en_port); 274 efx_mcdi_req_t req; 275 EFX_MCDI_DECLARE_BUF(payload, 276 MAX(MC_CMD_SET_ID_LED_IN_LEN, MC_CMD_SET_LINK_IN_LEN), 277 MAX(MC_CMD_SET_ID_LED_OUT_LEN, MC_CMD_SET_LINK_OUT_LEN)); 278 uint32_t cap_mask; 279 #if EFSYS_OPT_PHY_LED_CONTROL 280 unsigned int led_mode; 281 #endif 282 unsigned int speed; 283 efx_rc_t rc; 284 285 req.emr_cmd = MC_CMD_SET_LINK; 286 req.emr_in_buf = payload; 287 req.emr_in_length = MC_CMD_SET_LINK_IN_LEN; 288 req.emr_out_buf = payload; 289 req.emr_out_length = MC_CMD_SET_LINK_OUT_LEN; 290 291 cap_mask = epp->ep_adv_cap_mask; 292 MCDI_IN_POPULATE_DWORD_10(req, SET_LINK_IN_CAP, 293 PHY_CAP_10HDX, (cap_mask >> EFX_PHY_CAP_10HDX) & 0x1, 294 PHY_CAP_10FDX, (cap_mask >> EFX_PHY_CAP_10FDX) & 0x1, 295 PHY_CAP_100HDX, (cap_mask >> EFX_PHY_CAP_100HDX) & 0x1, 296 PHY_CAP_100FDX, (cap_mask >> EFX_PHY_CAP_100FDX) & 0x1, 297 PHY_CAP_1000HDX, (cap_mask >> EFX_PHY_CAP_1000HDX) & 0x1, 298 PHY_CAP_1000FDX, (cap_mask >> EFX_PHY_CAP_1000FDX) & 0x1, 299 PHY_CAP_10000FDX, (cap_mask >> EFX_PHY_CAP_10000FDX) & 0x1, 300 PHY_CAP_PAUSE, (cap_mask >> EFX_PHY_CAP_PAUSE) & 0x1, 301 PHY_CAP_ASYM, (cap_mask >> EFX_PHY_CAP_ASYM) & 0x1, 302 PHY_CAP_AN, (cap_mask >> EFX_PHY_CAP_AN) & 0x1); 303 304 #if EFSYS_OPT_LOOPBACK 305 MCDI_IN_SET_DWORD(req, SET_LINK_IN_LOOPBACK_MODE, 306 epp->ep_loopback_type); 307 switch (epp->ep_loopback_link_mode) { 308 case EFX_LINK_100FDX: 309 speed = 100; 310 break; 311 case EFX_LINK_1000FDX: 312 speed = 1000; 313 break; 314 case EFX_LINK_10000FDX: 315 speed = 10000; 316 break; 317 default: 318 speed = 0; 319 } 320 #else 321 MCDI_IN_SET_DWORD(req, SET_LINK_IN_LOOPBACK_MODE, MC_CMD_LOOPBACK_NONE); 322 speed = 0; 323 #endif /* EFSYS_OPT_LOOPBACK */ 324 MCDI_IN_SET_DWORD(req, SET_LINK_IN_LOOPBACK_SPEED, speed); 325 326 #if EFSYS_OPT_PHY_FLAGS 327 MCDI_IN_SET_DWORD(req, SET_LINK_IN_FLAGS, epp->ep_phy_flags); 328 #else 329 MCDI_IN_SET_DWORD(req, SET_LINK_IN_FLAGS, 0); 330 #endif /* EFSYS_OPT_PHY_FLAGS */ 331 332 efx_mcdi_execute(enp, &req); 333 334 if (req.emr_rc != 0) { 335 rc = req.emr_rc; 336 goto fail1; 337 } 338 339 /* And set the blink mode */ 340 (void) memset(payload, 0, sizeof (payload)); 341 req.emr_cmd = MC_CMD_SET_ID_LED; 342 req.emr_in_buf = payload; 343 req.emr_in_length = MC_CMD_SET_ID_LED_IN_LEN; 344 req.emr_out_buf = payload; 345 req.emr_out_length = MC_CMD_SET_ID_LED_OUT_LEN; 346 347 #if EFSYS_OPT_PHY_LED_CONTROL 348 switch (epp->ep_phy_led_mode) { 349 case EFX_PHY_LED_DEFAULT: 350 led_mode = MC_CMD_LED_DEFAULT; 351 break; 352 case EFX_PHY_LED_OFF: 353 led_mode = MC_CMD_LED_OFF; 354 break; 355 case EFX_PHY_LED_ON: 356 led_mode = MC_CMD_LED_ON; 357 break; 358 default: 359 EFSYS_ASSERT(0); 360 led_mode = MC_CMD_LED_DEFAULT; 361 } 362 363 MCDI_IN_SET_DWORD(req, SET_ID_LED_IN_STATE, led_mode); 364 #else 365 MCDI_IN_SET_DWORD(req, SET_ID_LED_IN_STATE, MC_CMD_LED_DEFAULT); 366 #endif /* EFSYS_OPT_PHY_LED_CONTROL */ 367 368 efx_mcdi_execute(enp, &req); 369 370 if (req.emr_rc != 0) { 371 rc = req.emr_rc; 372 goto fail2; 373 } 374 375 return (0); 376 377 fail2: 378 EFSYS_PROBE(fail2); 379 fail1: 380 EFSYS_PROBE1(fail1, efx_rc_t, rc); 381 382 return (rc); 383 } 384 385 __checkReturn efx_rc_t 386 siena_phy_verify( 387 __in efx_nic_t *enp) 388 { 389 efx_mcdi_req_t req; 390 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_PHY_STATE_IN_LEN, 391 MC_CMD_GET_PHY_STATE_OUT_LEN); 392 uint32_t state; 393 efx_rc_t rc; 394 395 req.emr_cmd = MC_CMD_GET_PHY_STATE; 396 req.emr_in_buf = payload; 397 req.emr_in_length = MC_CMD_GET_PHY_STATE_IN_LEN; 398 req.emr_out_buf = payload; 399 req.emr_out_length = MC_CMD_GET_PHY_STATE_OUT_LEN; 400 401 efx_mcdi_execute(enp, &req); 402 403 if (req.emr_rc != 0) { 404 rc = req.emr_rc; 405 goto fail1; 406 } 407 408 if (req.emr_out_length_used < MC_CMD_GET_PHY_STATE_OUT_LEN) { 409 rc = EMSGSIZE; 410 goto fail2; 411 } 412 413 state = MCDI_OUT_DWORD(req, GET_PHY_STATE_OUT_STATE); 414 if (state != MC_CMD_PHY_STATE_OK) { 415 if (state != MC_CMD_PHY_STATE_ZOMBIE) 416 EFSYS_PROBE1(mc_pcol_error, int, state); 417 rc = ENOTACTIVE; 418 goto fail3; 419 } 420 421 return (0); 422 423 fail3: 424 EFSYS_PROBE(fail3); 425 fail2: 426 EFSYS_PROBE(fail2); 427 fail1: 428 EFSYS_PROBE1(fail1, efx_rc_t, rc); 429 430 return (rc); 431 } 432 433 __checkReturn efx_rc_t 434 siena_phy_oui_get( 435 __in efx_nic_t *enp, 436 __out uint32_t *ouip) 437 { 438 _NOTE(ARGUNUSED(enp, ouip)) 439 440 return (ENOTSUP); 441 } 442 443 #if EFSYS_OPT_PHY_STATS 444 445 #define SIENA_SIMPLE_STAT_SET(_vmask, _esmp, _smask, _stat, \ 446 _mc_record, _efx_record) \ 447 if ((_vmask) & (1ULL << (_mc_record))) { \ 448 (_smask) |= (1ULL << (_efx_record)); \ 449 if ((_stat) != NULL && !EFSYS_MEM_IS_NULL(_esmp)) { \ 450 efx_dword_t dword; \ 451 EFSYS_MEM_READD(_esmp, (_mc_record) * 4, &dword);\ 452 (_stat)[_efx_record] = \ 453 EFX_DWORD_FIELD(dword, EFX_DWORD_0); \ 454 } \ 455 } 456 457 #define SIENA_SIMPLE_STAT_SET2(_vmask, _esmp, _smask, _stat, _record) \ 458 SIENA_SIMPLE_STAT_SET(_vmask, _esmp, _smask, _stat, \ 459 MC_CMD_ ## _record, \ 460 EFX_PHY_STAT_ ## _record) 461 462 void 463 siena_phy_decode_stats( 464 __in efx_nic_t *enp, 465 __in uint32_t vmask, 466 __in_opt efsys_mem_t *esmp, 467 __out_opt uint64_t *smaskp, 468 __inout_ecount_opt(EFX_PHY_NSTATS) uint32_t *stat) 469 { 470 uint64_t smask = 0; 471 472 _NOTE(ARGUNUSED(enp)) 473 474 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, OUI); 475 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PMA_PMD_LINK_UP); 476 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PMA_PMD_RX_FAULT); 477 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PMA_PMD_TX_FAULT); 478 479 if (vmask & (1 << MC_CMD_PMA_PMD_SIGNAL)) { 480 smask |= ((1ULL << EFX_PHY_STAT_PMA_PMD_SIGNAL_A) | 481 (1ULL << EFX_PHY_STAT_PMA_PMD_SIGNAL_B) | 482 (1ULL << EFX_PHY_STAT_PMA_PMD_SIGNAL_C) | 483 (1ULL << EFX_PHY_STAT_PMA_PMD_SIGNAL_D)); 484 if (stat != NULL && esmp != NULL && !EFSYS_MEM_IS_NULL(esmp)) { 485 efx_dword_t dword; 486 uint32_t sig; 487 EFSYS_MEM_READD(esmp, 4 * MC_CMD_PMA_PMD_SIGNAL, 488 &dword); 489 sig = EFX_DWORD_FIELD(dword, EFX_DWORD_0); 490 stat[EFX_PHY_STAT_PMA_PMD_SIGNAL_A] = (sig >> 1) & 1; 491 stat[EFX_PHY_STAT_PMA_PMD_SIGNAL_B] = (sig >> 2) & 1; 492 stat[EFX_PHY_STAT_PMA_PMD_SIGNAL_C] = (sig >> 3) & 1; 493 stat[EFX_PHY_STAT_PMA_PMD_SIGNAL_D] = (sig >> 4) & 1; 494 } 495 } 496 497 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PMA_PMD_SNR_A, 498 EFX_PHY_STAT_SNR_A); 499 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PMA_PMD_SNR_B, 500 EFX_PHY_STAT_SNR_B); 501 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PMA_PMD_SNR_C, 502 EFX_PHY_STAT_SNR_C); 503 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PMA_PMD_SNR_D, 504 EFX_PHY_STAT_SNR_D); 505 506 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_LINK_UP); 507 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_RX_FAULT); 508 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_TX_FAULT); 509 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_BER); 510 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_BLOCK_ERRORS); 511 512 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PHYXS_LINK_UP, 513 EFX_PHY_STAT_PHY_XS_LINK_UP); 514 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PHYXS_RX_FAULT, 515 EFX_PHY_STAT_PHY_XS_RX_FAULT); 516 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PHYXS_TX_FAULT, 517 EFX_PHY_STAT_PHY_XS_TX_FAULT); 518 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PHYXS_ALIGN, 519 EFX_PHY_STAT_PHY_XS_ALIGN); 520 521 if (vmask & (1 << MC_CMD_PHYXS_SYNC)) { 522 smask |= ((1 << EFX_PHY_STAT_PHY_XS_SYNC_A) | 523 (1 << EFX_PHY_STAT_PHY_XS_SYNC_B) | 524 (1 << EFX_PHY_STAT_PHY_XS_SYNC_C) | 525 (1 << EFX_PHY_STAT_PHY_XS_SYNC_D)); 526 if (stat != NULL && !EFSYS_MEM_IS_NULL(esmp)) { 527 efx_dword_t dword; 528 uint32_t sync; 529 EFSYS_MEM_READD(esmp, 4 * MC_CMD_PHYXS_SYNC, &dword); 530 sync = EFX_DWORD_FIELD(dword, EFX_DWORD_0); 531 stat[EFX_PHY_STAT_PHY_XS_SYNC_A] = (sync >> 0) & 1; 532 stat[EFX_PHY_STAT_PHY_XS_SYNC_B] = (sync >> 1) & 1; 533 stat[EFX_PHY_STAT_PHY_XS_SYNC_C] = (sync >> 2) & 1; 534 stat[EFX_PHY_STAT_PHY_XS_SYNC_D] = (sync >> 3) & 1; 535 } 536 } 537 538 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, AN_LINK_UP); 539 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, AN_COMPLETE); 540 541 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_CL22_LINK_UP, 542 EFX_PHY_STAT_CL22EXT_LINK_UP); 543 544 if (smaskp != NULL) 545 *smaskp = smask; 546 } 547 548 __checkReturn efx_rc_t 549 siena_phy_stats_update( 550 __in efx_nic_t *enp, 551 __in efsys_mem_t *esmp, 552 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat) 553 { 554 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); 555 uint32_t vmask = encp->enc_mcdi_phy_stat_mask; 556 uint64_t smask; 557 efx_mcdi_req_t req; 558 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_PHY_STATS_IN_LEN, 559 MC_CMD_PHY_STATS_OUT_DMA_LEN); 560 efx_rc_t rc; 561 562 if ((esmp == NULL) || (EFSYS_MEM_SIZE(esmp) < EFX_PHY_STATS_SIZE)) { 563 rc = EINVAL; 564 goto fail1; 565 } 566 567 req.emr_cmd = MC_CMD_PHY_STATS; 568 req.emr_in_buf = payload; 569 req.emr_in_length = MC_CMD_PHY_STATS_IN_LEN; 570 req.emr_out_buf = payload; 571 req.emr_out_length = MC_CMD_PHY_STATS_OUT_DMA_LEN; 572 573 MCDI_IN_SET_DWORD(req, PHY_STATS_IN_DMA_ADDR_LO, 574 EFSYS_MEM_ADDR(esmp) & 0xffffffff); 575 MCDI_IN_SET_DWORD(req, PHY_STATS_IN_DMA_ADDR_HI, 576 EFSYS_MEM_ADDR(esmp) >> 32); 577 578 efx_mcdi_execute(enp, &req); 579 580 if (req.emr_rc != 0) { 581 rc = req.emr_rc; 582 goto fail2; 583 } 584 EFSYS_ASSERT3U(req.emr_out_length, ==, MC_CMD_PHY_STATS_OUT_DMA_LEN); 585 586 siena_phy_decode_stats(enp, vmask, esmp, &smask, stat); 587 EFSYS_ASSERT(smask == encp->enc_phy_stat_mask); 588 589 return (0); 590 591 fail2: 592 EFSYS_PROBE(fail2); 593 fail1: 594 EFSYS_PROBE1(fail1, efx_rc_t, rc); 595 596 return (0); 597 } 598 599 #endif /* EFSYS_OPT_PHY_STATS */ 600 601 #if EFSYS_OPT_BIST 602 603 __checkReturn efx_rc_t 604 siena_phy_bist_start( 605 __in efx_nic_t *enp, 606 __in efx_bist_type_t type) 607 { 608 efx_rc_t rc; 609 610 if ((rc = efx_mcdi_bist_start(enp, type)) != 0) 611 goto fail1; 612 613 return (0); 614 615 fail1: 616 EFSYS_PROBE1(fail1, efx_rc_t, rc); 617 618 return (rc); 619 } 620 621 static __checkReturn unsigned long 622 siena_phy_sft9001_bist_status( 623 __in uint16_t code) 624 { 625 switch (code) { 626 case MC_CMD_POLL_BIST_SFT9001_PAIR_BUSY: 627 return (EFX_PHY_CABLE_STATUS_BUSY); 628 case MC_CMD_POLL_BIST_SFT9001_INTER_PAIR_SHORT: 629 return (EFX_PHY_CABLE_STATUS_INTERPAIRSHORT); 630 case MC_CMD_POLL_BIST_SFT9001_INTRA_PAIR_SHORT: 631 return (EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT); 632 case MC_CMD_POLL_BIST_SFT9001_PAIR_OPEN: 633 return (EFX_PHY_CABLE_STATUS_OPEN); 634 case MC_CMD_POLL_BIST_SFT9001_PAIR_OK: 635 return (EFX_PHY_CABLE_STATUS_OK); 636 default: 637 return (EFX_PHY_CABLE_STATUS_INVALID); 638 } 639 } 640 641 __checkReturn efx_rc_t 642 siena_phy_bist_poll( 643 __in efx_nic_t *enp, 644 __in efx_bist_type_t type, 645 __out efx_bist_result_t *resultp, 646 __out_opt __drv_when(count > 0, __notnull) 647 uint32_t *value_maskp, 648 __out_ecount_opt(count) __drv_when(count > 0, __notnull) 649 unsigned long *valuesp, 650 __in size_t count) 651 { 652 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); 653 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_POLL_BIST_IN_LEN, 654 MCDI_CTL_SDU_LEN_MAX); 655 uint32_t value_mask = 0; 656 efx_mcdi_req_t req; 657 uint32_t result; 658 efx_rc_t rc; 659 660 req.emr_cmd = MC_CMD_POLL_BIST; 661 req.emr_in_buf = payload; 662 req.emr_in_length = MC_CMD_POLL_BIST_IN_LEN; 663 req.emr_out_buf = payload; 664 req.emr_out_length = MCDI_CTL_SDU_LEN_MAX; 665 666 efx_mcdi_execute(enp, &req); 667 668 if (req.emr_rc != 0) { 669 rc = req.emr_rc; 670 goto fail1; 671 } 672 673 if (req.emr_out_length_used < MC_CMD_POLL_BIST_OUT_RESULT_OFST + 4) { 674 rc = EMSGSIZE; 675 goto fail2; 676 } 677 678 if (count > 0) 679 (void) memset(valuesp, '\0', count * sizeof (unsigned long)); 680 681 result = MCDI_OUT_DWORD(req, POLL_BIST_OUT_RESULT); 682 683 /* Extract PHY specific results */ 684 if (result == MC_CMD_POLL_BIST_PASSED && 685 encp->enc_phy_type == EFX_PHY_SFT9001B && 686 req.emr_out_length_used >= MC_CMD_POLL_BIST_OUT_SFT9001_LEN && 687 (type == EFX_BIST_TYPE_PHY_CABLE_SHORT || 688 type == EFX_BIST_TYPE_PHY_CABLE_LONG)) { 689 uint16_t word; 690 691 if (count > EFX_BIST_PHY_CABLE_LENGTH_A) { 692 if (valuesp != NULL) 693 valuesp[EFX_BIST_PHY_CABLE_LENGTH_A] = 694 MCDI_OUT_DWORD(req, 695 POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A); 696 value_mask |= (1 << EFX_BIST_PHY_CABLE_LENGTH_A); 697 } 698 699 if (count > EFX_BIST_PHY_CABLE_LENGTH_B) { 700 if (valuesp != NULL) 701 valuesp[EFX_BIST_PHY_CABLE_LENGTH_B] = 702 MCDI_OUT_DWORD(req, 703 POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B); 704 value_mask |= (1 << EFX_BIST_PHY_CABLE_LENGTH_B); 705 } 706 707 if (count > EFX_BIST_PHY_CABLE_LENGTH_C) { 708 if (valuesp != NULL) 709 valuesp[EFX_BIST_PHY_CABLE_LENGTH_C] = 710 MCDI_OUT_DWORD(req, 711 POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C); 712 value_mask |= (1 << EFX_BIST_PHY_CABLE_LENGTH_C); 713 } 714 715 if (count > EFX_BIST_PHY_CABLE_LENGTH_D) { 716 if (valuesp != NULL) 717 valuesp[EFX_BIST_PHY_CABLE_LENGTH_D] = 718 MCDI_OUT_DWORD(req, 719 POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D); 720 value_mask |= (1 << EFX_BIST_PHY_CABLE_LENGTH_D); 721 } 722 723 if (count > EFX_BIST_PHY_CABLE_STATUS_A) { 724 if (valuesp != NULL) { 725 word = MCDI_OUT_WORD(req, 726 POLL_BIST_OUT_SFT9001_CABLE_STATUS_A); 727 valuesp[EFX_BIST_PHY_CABLE_STATUS_A] = 728 siena_phy_sft9001_bist_status(word); 729 } 730 value_mask |= (1 << EFX_BIST_PHY_CABLE_STATUS_A); 731 } 732 733 if (count > EFX_BIST_PHY_CABLE_STATUS_B) { 734 if (valuesp != NULL) { 735 word = MCDI_OUT_WORD(req, 736 POLL_BIST_OUT_SFT9001_CABLE_STATUS_B); 737 valuesp[EFX_BIST_PHY_CABLE_STATUS_B] = 738 siena_phy_sft9001_bist_status(word); 739 } 740 value_mask |= (1 << EFX_BIST_PHY_CABLE_STATUS_B); 741 } 742 743 if (count > EFX_BIST_PHY_CABLE_STATUS_C) { 744 if (valuesp != NULL) { 745 word = MCDI_OUT_WORD(req, 746 POLL_BIST_OUT_SFT9001_CABLE_STATUS_C); 747 valuesp[EFX_BIST_PHY_CABLE_STATUS_C] = 748 siena_phy_sft9001_bist_status(word); 749 } 750 value_mask |= (1 << EFX_BIST_PHY_CABLE_STATUS_C); 751 } 752 753 if (count > EFX_BIST_PHY_CABLE_STATUS_D) { 754 if (valuesp != NULL) { 755 word = MCDI_OUT_WORD(req, 756 POLL_BIST_OUT_SFT9001_CABLE_STATUS_D); 757 valuesp[EFX_BIST_PHY_CABLE_STATUS_D] = 758 siena_phy_sft9001_bist_status(word); 759 } 760 value_mask |= (1 << EFX_BIST_PHY_CABLE_STATUS_D); 761 } 762 763 } else if (result == MC_CMD_POLL_BIST_FAILED && 764 encp->enc_phy_type == EFX_PHY_QLX111V && 765 req.emr_out_length >= MC_CMD_POLL_BIST_OUT_MRSFP_LEN && 766 count > EFX_BIST_FAULT_CODE) { 767 if (valuesp != NULL) 768 valuesp[EFX_BIST_FAULT_CODE] = 769 MCDI_OUT_DWORD(req, POLL_BIST_OUT_MRSFP_TEST); 770 value_mask |= 1 << EFX_BIST_FAULT_CODE; 771 } 772 773 if (value_maskp != NULL) 774 *value_maskp = value_mask; 775 776 EFSYS_ASSERT(resultp != NULL); 777 if (result == MC_CMD_POLL_BIST_RUNNING) 778 *resultp = EFX_BIST_RESULT_RUNNING; 779 else if (result == MC_CMD_POLL_BIST_PASSED) 780 *resultp = EFX_BIST_RESULT_PASSED; 781 else 782 *resultp = EFX_BIST_RESULT_FAILED; 783 784 return (0); 785 786 fail2: 787 EFSYS_PROBE(fail2); 788 fail1: 789 EFSYS_PROBE1(fail1, efx_rc_t, rc); 790 791 return (rc); 792 } 793 794 void 795 siena_phy_bist_stop( 796 __in efx_nic_t *enp, 797 __in efx_bist_type_t type) 798 { 799 /* There is no way to stop BIST on Siena */ 800 _NOTE(ARGUNUSED(enp, type)) 801 } 802 803 #endif /* EFSYS_OPT_BIST */ 804 805 #endif /* EFSYS_OPT_SIENA */ 806