1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2009-2016 Solarflare Communications Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 18 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 26 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * The views and conclusions contained in the software and documentation are 29 * those of the authors and should not be interpreted as representing official 30 * policies, either expressed or implied, of the FreeBSD Project. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 #include "efx.h" 37 #include "efx_impl.h" 38 39 #if EFSYS_OPT_SIENA 40 41 static void 42 siena_phy_decode_cap( 43 __in uint32_t mcdi_cap, 44 __out uint32_t *maskp) 45 { 46 uint32_t mask; 47 48 mask = 0; 49 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_10HDX_LBN)) 50 mask |= (1 << EFX_PHY_CAP_10HDX); 51 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_10FDX_LBN)) 52 mask |= (1 << EFX_PHY_CAP_10FDX); 53 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_100HDX_LBN)) 54 mask |= (1 << EFX_PHY_CAP_100HDX); 55 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_100FDX_LBN)) 56 mask |= (1 << EFX_PHY_CAP_100FDX); 57 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_1000HDX_LBN)) 58 mask |= (1 << EFX_PHY_CAP_1000HDX); 59 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_1000FDX_LBN)) 60 mask |= (1 << EFX_PHY_CAP_1000FDX); 61 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_10000FDX_LBN)) 62 mask |= (1 << EFX_PHY_CAP_10000FDX); 63 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_PAUSE_LBN)) 64 mask |= (1 << EFX_PHY_CAP_PAUSE); 65 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_ASYM_LBN)) 66 mask |= (1 << EFX_PHY_CAP_ASYM); 67 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_AN_LBN)) 68 mask |= (1 << EFX_PHY_CAP_AN); 69 70 *maskp = mask; 71 } 72 73 static void 74 siena_phy_decode_link_mode( 75 __in efx_nic_t *enp, 76 __in uint32_t link_flags, 77 __in unsigned int speed, 78 __in unsigned int fcntl, 79 __out efx_link_mode_t *link_modep, 80 __out unsigned int *fcntlp) 81 { 82 boolean_t fd = !!(link_flags & 83 (1 << MC_CMD_GET_LINK_OUT_FULL_DUPLEX_LBN)); 84 boolean_t up = !!(link_flags & 85 (1 << MC_CMD_GET_LINK_OUT_LINK_UP_LBN)); 86 87 _NOTE(ARGUNUSED(enp)) 88 89 if (!up) 90 *link_modep = EFX_LINK_DOWN; 91 else if (speed == 10000 && fd) 92 *link_modep = EFX_LINK_10000FDX; 93 else if (speed == 1000) 94 *link_modep = fd ? EFX_LINK_1000FDX : EFX_LINK_1000HDX; 95 else if (speed == 100) 96 *link_modep = fd ? EFX_LINK_100FDX : EFX_LINK_100HDX; 97 else if (speed == 10) 98 *link_modep = fd ? EFX_LINK_10FDX : EFX_LINK_10HDX; 99 else 100 *link_modep = EFX_LINK_UNKNOWN; 101 102 if (fcntl == MC_CMD_FCNTL_OFF) 103 *fcntlp = 0; 104 else if (fcntl == MC_CMD_FCNTL_RESPOND) 105 *fcntlp = EFX_FCNTL_RESPOND; 106 else if (fcntl == MC_CMD_FCNTL_BIDIR) 107 *fcntlp = EFX_FCNTL_RESPOND | EFX_FCNTL_GENERATE; 108 else { 109 EFSYS_PROBE1(mc_pcol_error, int, fcntl); 110 *fcntlp = 0; 111 } 112 } 113 114 void 115 siena_phy_link_ev( 116 __in efx_nic_t *enp, 117 __in efx_qword_t *eqp, 118 __out efx_link_mode_t *link_modep) 119 { 120 efx_port_t *epp = &(enp->en_port); 121 unsigned int link_flags; 122 unsigned int speed; 123 unsigned int fcntl; 124 efx_link_mode_t link_mode; 125 uint32_t lp_cap_mask; 126 127 /* 128 * Convert the LINKCHANGE speed enumeration into mbit/s, in the 129 * same way as GET_LINK encodes the speed 130 */ 131 switch (MCDI_EV_FIELD(eqp, LINKCHANGE_SPEED)) { 132 case MCDI_EVENT_LINKCHANGE_SPEED_100M: 133 speed = 100; 134 break; 135 case MCDI_EVENT_LINKCHANGE_SPEED_1G: 136 speed = 1000; 137 break; 138 case MCDI_EVENT_LINKCHANGE_SPEED_10G: 139 speed = 10000; 140 break; 141 default: 142 speed = 0; 143 break; 144 } 145 146 link_flags = MCDI_EV_FIELD(eqp, LINKCHANGE_LINK_FLAGS); 147 siena_phy_decode_link_mode(enp, link_flags, speed, 148 MCDI_EV_FIELD(eqp, LINKCHANGE_FCNTL), 149 &link_mode, &fcntl); 150 siena_phy_decode_cap(MCDI_EV_FIELD(eqp, LINKCHANGE_LP_CAP), 151 &lp_cap_mask); 152 153 /* 154 * It's safe to update ep_lp_cap_mask without the driver's port lock 155 * because presumably any concurrently running efx_port_poll() is 156 * only going to arrive at the same value. 157 * 158 * ep_fcntl has two meanings. It's either the link common fcntl 159 * (if the PHY supports AN), or it's the forced link state. If 160 * the former, it's safe to update the value for the same reason as 161 * for ep_lp_cap_mask. If the latter, then just ignore the value, 162 * because we can race with efx_mac_fcntl_set(). 163 */ 164 epp->ep_lp_cap_mask = lp_cap_mask; 165 if (epp->ep_phy_cap_mask & (1 << EFX_PHY_CAP_AN)) 166 epp->ep_fcntl = fcntl; 167 168 *link_modep = link_mode; 169 } 170 171 __checkReturn efx_rc_t 172 siena_phy_power( 173 __in efx_nic_t *enp, 174 __in boolean_t power) 175 { 176 efx_rc_t rc; 177 178 if (!power) 179 return (0); 180 181 /* Check if the PHY is a zombie */ 182 if ((rc = siena_phy_verify(enp)) != 0) 183 goto fail1; 184 185 enp->en_reset_flags |= EFX_RESET_PHY; 186 187 return (0); 188 189 fail1: 190 EFSYS_PROBE1(fail1, efx_rc_t, rc); 191 192 return (rc); 193 } 194 195 __checkReturn efx_rc_t 196 siena_phy_get_link( 197 __in efx_nic_t *enp, 198 __out siena_link_state_t *slsp) 199 { 200 efx_mcdi_req_t req; 201 uint8_t payload[MAX(MC_CMD_GET_LINK_IN_LEN, 202 MC_CMD_GET_LINK_OUT_LEN)]; 203 efx_rc_t rc; 204 205 (void) memset(payload, 0, sizeof (payload)); 206 req.emr_cmd = MC_CMD_GET_LINK; 207 req.emr_in_buf = payload; 208 req.emr_in_length = MC_CMD_GET_LINK_IN_LEN; 209 req.emr_out_buf = payload; 210 req.emr_out_length = MC_CMD_GET_LINK_OUT_LEN; 211 212 efx_mcdi_execute(enp, &req); 213 214 if (req.emr_rc != 0) { 215 rc = req.emr_rc; 216 goto fail1; 217 } 218 219 if (req.emr_out_length_used < MC_CMD_GET_LINK_OUT_LEN) { 220 rc = EMSGSIZE; 221 goto fail2; 222 } 223 224 siena_phy_decode_cap(MCDI_OUT_DWORD(req, GET_LINK_OUT_CAP), 225 &slsp->sls_adv_cap_mask); 226 siena_phy_decode_cap(MCDI_OUT_DWORD(req, GET_LINK_OUT_LP_CAP), 227 &slsp->sls_lp_cap_mask); 228 229 siena_phy_decode_link_mode(enp, MCDI_OUT_DWORD(req, GET_LINK_OUT_FLAGS), 230 MCDI_OUT_DWORD(req, GET_LINK_OUT_LINK_SPEED), 231 MCDI_OUT_DWORD(req, GET_LINK_OUT_FCNTL), 232 &slsp->sls_link_mode, &slsp->sls_fcntl); 233 234 #if EFSYS_OPT_LOOPBACK 235 /* Assert the MC_CMD_LOOPBACK and EFX_LOOPBACK namespace agree */ 236 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_NONE == EFX_LOOPBACK_OFF); 237 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_DATA == EFX_LOOPBACK_DATA); 238 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GMAC == EFX_LOOPBACK_GMAC); 239 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XGMII == EFX_LOOPBACK_XGMII); 240 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XGXS == EFX_LOOPBACK_XGXS); 241 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XAUI == EFX_LOOPBACK_XAUI); 242 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GMII == EFX_LOOPBACK_GMII); 243 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SGMII == EFX_LOOPBACK_SGMII); 244 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XGBR == EFX_LOOPBACK_XGBR); 245 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XFI == EFX_LOOPBACK_XFI); 246 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XAUI_FAR == EFX_LOOPBACK_XAUI_FAR); 247 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GMII_FAR == EFX_LOOPBACK_GMII_FAR); 248 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SGMII_FAR == EFX_LOOPBACK_SGMII_FAR); 249 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XFI_FAR == EFX_LOOPBACK_XFI_FAR); 250 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GPHY == EFX_LOOPBACK_GPHY); 251 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PHYXS == EFX_LOOPBACK_PHY_XS); 252 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PCS == EFX_LOOPBACK_PCS); 253 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PMAPMD == EFX_LOOPBACK_PMA_PMD); 254 255 slsp->sls_loopback = MCDI_OUT_DWORD(req, GET_LINK_OUT_LOOPBACK_MODE); 256 #endif /* EFSYS_OPT_LOOPBACK */ 257 258 slsp->sls_mac_up = MCDI_OUT_DWORD(req, GET_LINK_OUT_MAC_FAULT) == 0; 259 260 return (0); 261 262 fail2: 263 EFSYS_PROBE(fail2); 264 fail1: 265 EFSYS_PROBE1(fail1, efx_rc_t, rc); 266 267 return (rc); 268 } 269 270 __checkReturn efx_rc_t 271 siena_phy_reconfigure( 272 __in efx_nic_t *enp) 273 { 274 efx_port_t *epp = &(enp->en_port); 275 efx_mcdi_req_t req; 276 uint8_t payload[MAX(MAX(MC_CMD_SET_ID_LED_IN_LEN, 277 MC_CMD_SET_ID_LED_OUT_LEN), 278 MAX(MC_CMD_SET_LINK_IN_LEN, 279 MC_CMD_SET_LINK_OUT_LEN))]; 280 uint32_t cap_mask; 281 #if EFSYS_OPT_PHY_LED_CONTROL 282 unsigned int led_mode; 283 #endif 284 unsigned int speed; 285 efx_rc_t rc; 286 287 (void) memset(payload, 0, sizeof (payload)); 288 req.emr_cmd = MC_CMD_SET_LINK; 289 req.emr_in_buf = payload; 290 req.emr_in_length = MC_CMD_SET_LINK_IN_LEN; 291 req.emr_out_buf = payload; 292 req.emr_out_length = MC_CMD_SET_LINK_OUT_LEN; 293 294 cap_mask = epp->ep_adv_cap_mask; 295 MCDI_IN_POPULATE_DWORD_10(req, SET_LINK_IN_CAP, 296 PHY_CAP_10HDX, (cap_mask >> EFX_PHY_CAP_10HDX) & 0x1, 297 PHY_CAP_10FDX, (cap_mask >> EFX_PHY_CAP_10FDX) & 0x1, 298 PHY_CAP_100HDX, (cap_mask >> EFX_PHY_CAP_100HDX) & 0x1, 299 PHY_CAP_100FDX, (cap_mask >> EFX_PHY_CAP_100FDX) & 0x1, 300 PHY_CAP_1000HDX, (cap_mask >> EFX_PHY_CAP_1000HDX) & 0x1, 301 PHY_CAP_1000FDX, (cap_mask >> EFX_PHY_CAP_1000FDX) & 0x1, 302 PHY_CAP_10000FDX, (cap_mask >> EFX_PHY_CAP_10000FDX) & 0x1, 303 PHY_CAP_PAUSE, (cap_mask >> EFX_PHY_CAP_PAUSE) & 0x1, 304 PHY_CAP_ASYM, (cap_mask >> EFX_PHY_CAP_ASYM) & 0x1, 305 PHY_CAP_AN, (cap_mask >> EFX_PHY_CAP_AN) & 0x1); 306 307 #if EFSYS_OPT_LOOPBACK 308 MCDI_IN_SET_DWORD(req, SET_LINK_IN_LOOPBACK_MODE, 309 epp->ep_loopback_type); 310 switch (epp->ep_loopback_link_mode) { 311 case EFX_LINK_100FDX: 312 speed = 100; 313 break; 314 case EFX_LINK_1000FDX: 315 speed = 1000; 316 break; 317 case EFX_LINK_10000FDX: 318 speed = 10000; 319 break; 320 default: 321 speed = 0; 322 } 323 #else 324 MCDI_IN_SET_DWORD(req, SET_LINK_IN_LOOPBACK_MODE, MC_CMD_LOOPBACK_NONE); 325 speed = 0; 326 #endif /* EFSYS_OPT_LOOPBACK */ 327 MCDI_IN_SET_DWORD(req, SET_LINK_IN_LOOPBACK_SPEED, speed); 328 329 #if EFSYS_OPT_PHY_FLAGS 330 MCDI_IN_SET_DWORD(req, SET_LINK_IN_FLAGS, epp->ep_phy_flags); 331 #else 332 MCDI_IN_SET_DWORD(req, SET_LINK_IN_FLAGS, 0); 333 #endif /* EFSYS_OPT_PHY_FLAGS */ 334 335 efx_mcdi_execute(enp, &req); 336 337 if (req.emr_rc != 0) { 338 rc = req.emr_rc; 339 goto fail1; 340 } 341 342 /* And set the blink mode */ 343 (void) memset(payload, 0, sizeof (payload)); 344 req.emr_cmd = MC_CMD_SET_ID_LED; 345 req.emr_in_buf = payload; 346 req.emr_in_length = MC_CMD_SET_ID_LED_IN_LEN; 347 req.emr_out_buf = payload; 348 req.emr_out_length = MC_CMD_SET_ID_LED_OUT_LEN; 349 350 #if EFSYS_OPT_PHY_LED_CONTROL 351 switch (epp->ep_phy_led_mode) { 352 case EFX_PHY_LED_DEFAULT: 353 led_mode = MC_CMD_LED_DEFAULT; 354 break; 355 case EFX_PHY_LED_OFF: 356 led_mode = MC_CMD_LED_OFF; 357 break; 358 case EFX_PHY_LED_ON: 359 led_mode = MC_CMD_LED_ON; 360 break; 361 default: 362 EFSYS_ASSERT(0); 363 led_mode = MC_CMD_LED_DEFAULT; 364 } 365 366 MCDI_IN_SET_DWORD(req, SET_ID_LED_IN_STATE, led_mode); 367 #else 368 MCDI_IN_SET_DWORD(req, SET_ID_LED_IN_STATE, MC_CMD_LED_DEFAULT); 369 #endif /* EFSYS_OPT_PHY_LED_CONTROL */ 370 371 efx_mcdi_execute(enp, &req); 372 373 if (req.emr_rc != 0) { 374 rc = req.emr_rc; 375 goto fail2; 376 } 377 378 return (0); 379 380 fail2: 381 EFSYS_PROBE(fail2); 382 fail1: 383 EFSYS_PROBE1(fail1, efx_rc_t, rc); 384 385 return (rc); 386 } 387 388 __checkReturn efx_rc_t 389 siena_phy_verify( 390 __in efx_nic_t *enp) 391 { 392 efx_mcdi_req_t req; 393 uint8_t payload[MAX(MC_CMD_GET_PHY_STATE_IN_LEN, 394 MC_CMD_GET_PHY_STATE_OUT_LEN)]; 395 uint32_t state; 396 efx_rc_t rc; 397 398 (void) memset(payload, 0, sizeof (payload)); 399 req.emr_cmd = MC_CMD_GET_PHY_STATE; 400 req.emr_in_buf = payload; 401 req.emr_in_length = MC_CMD_GET_PHY_STATE_IN_LEN; 402 req.emr_out_buf = payload; 403 req.emr_out_length = MC_CMD_GET_PHY_STATE_OUT_LEN; 404 405 efx_mcdi_execute(enp, &req); 406 407 if (req.emr_rc != 0) { 408 rc = req.emr_rc; 409 goto fail1; 410 } 411 412 if (req.emr_out_length_used < MC_CMD_GET_PHY_STATE_OUT_LEN) { 413 rc = EMSGSIZE; 414 goto fail2; 415 } 416 417 state = MCDI_OUT_DWORD(req, GET_PHY_STATE_OUT_STATE); 418 if (state != MC_CMD_PHY_STATE_OK) { 419 if (state != MC_CMD_PHY_STATE_ZOMBIE) 420 EFSYS_PROBE1(mc_pcol_error, int, state); 421 rc = ENOTACTIVE; 422 goto fail3; 423 } 424 425 return (0); 426 427 fail3: 428 EFSYS_PROBE(fail3); 429 fail2: 430 EFSYS_PROBE(fail2); 431 fail1: 432 EFSYS_PROBE1(fail1, efx_rc_t, rc); 433 434 return (rc); 435 } 436 437 __checkReturn efx_rc_t 438 siena_phy_oui_get( 439 __in efx_nic_t *enp, 440 __out uint32_t *ouip) 441 { 442 _NOTE(ARGUNUSED(enp, ouip)) 443 444 return (ENOTSUP); 445 } 446 447 #if EFSYS_OPT_PHY_STATS 448 449 #define SIENA_SIMPLE_STAT_SET(_vmask, _esmp, _smask, _stat, \ 450 _mc_record, _efx_record) \ 451 if ((_vmask) & (1ULL << (_mc_record))) { \ 452 (_smask) |= (1ULL << (_efx_record)); \ 453 if ((_stat) != NULL && !EFSYS_MEM_IS_NULL(_esmp)) { \ 454 efx_dword_t dword; \ 455 EFSYS_MEM_READD(_esmp, (_mc_record) * 4, &dword);\ 456 (_stat)[_efx_record] = \ 457 EFX_DWORD_FIELD(dword, EFX_DWORD_0); \ 458 } \ 459 } 460 461 #define SIENA_SIMPLE_STAT_SET2(_vmask, _esmp, _smask, _stat, _record) \ 462 SIENA_SIMPLE_STAT_SET(_vmask, _esmp, _smask, _stat, \ 463 MC_CMD_ ## _record, \ 464 EFX_PHY_STAT_ ## _record) 465 466 void 467 siena_phy_decode_stats( 468 __in efx_nic_t *enp, 469 __in uint32_t vmask, 470 __in_opt efsys_mem_t *esmp, 471 __out_opt uint64_t *smaskp, 472 __inout_ecount_opt(EFX_PHY_NSTATS) uint32_t *stat) 473 { 474 uint64_t smask = 0; 475 476 _NOTE(ARGUNUSED(enp)) 477 478 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, OUI); 479 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PMA_PMD_LINK_UP); 480 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PMA_PMD_RX_FAULT); 481 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PMA_PMD_TX_FAULT); 482 483 if (vmask & (1 << MC_CMD_PMA_PMD_SIGNAL)) { 484 smask |= ((1ULL << EFX_PHY_STAT_PMA_PMD_SIGNAL_A) | 485 (1ULL << EFX_PHY_STAT_PMA_PMD_SIGNAL_B) | 486 (1ULL << EFX_PHY_STAT_PMA_PMD_SIGNAL_C) | 487 (1ULL << EFX_PHY_STAT_PMA_PMD_SIGNAL_D)); 488 if (stat != NULL && esmp != NULL && !EFSYS_MEM_IS_NULL(esmp)) { 489 efx_dword_t dword; 490 uint32_t sig; 491 EFSYS_MEM_READD(esmp, 4 * MC_CMD_PMA_PMD_SIGNAL, 492 &dword); 493 sig = EFX_DWORD_FIELD(dword, EFX_DWORD_0); 494 stat[EFX_PHY_STAT_PMA_PMD_SIGNAL_A] = (sig >> 1) & 1; 495 stat[EFX_PHY_STAT_PMA_PMD_SIGNAL_B] = (sig >> 2) & 1; 496 stat[EFX_PHY_STAT_PMA_PMD_SIGNAL_C] = (sig >> 3) & 1; 497 stat[EFX_PHY_STAT_PMA_PMD_SIGNAL_D] = (sig >> 4) & 1; 498 } 499 } 500 501 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PMA_PMD_SNR_A, 502 EFX_PHY_STAT_SNR_A); 503 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PMA_PMD_SNR_B, 504 EFX_PHY_STAT_SNR_B); 505 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PMA_PMD_SNR_C, 506 EFX_PHY_STAT_SNR_C); 507 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PMA_PMD_SNR_D, 508 EFX_PHY_STAT_SNR_D); 509 510 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_LINK_UP); 511 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_RX_FAULT); 512 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_TX_FAULT); 513 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_BER); 514 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_BLOCK_ERRORS); 515 516 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PHYXS_LINK_UP, 517 EFX_PHY_STAT_PHY_XS_LINK_UP); 518 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PHYXS_RX_FAULT, 519 EFX_PHY_STAT_PHY_XS_RX_FAULT); 520 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PHYXS_TX_FAULT, 521 EFX_PHY_STAT_PHY_XS_TX_FAULT); 522 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PHYXS_ALIGN, 523 EFX_PHY_STAT_PHY_XS_ALIGN); 524 525 if (vmask & (1 << MC_CMD_PHYXS_SYNC)) { 526 smask |= ((1 << EFX_PHY_STAT_PHY_XS_SYNC_A) | 527 (1 << EFX_PHY_STAT_PHY_XS_SYNC_B) | 528 (1 << EFX_PHY_STAT_PHY_XS_SYNC_C) | 529 (1 << EFX_PHY_STAT_PHY_XS_SYNC_D)); 530 if (stat != NULL && !EFSYS_MEM_IS_NULL(esmp)) { 531 efx_dword_t dword; 532 uint32_t sync; 533 EFSYS_MEM_READD(esmp, 4 * MC_CMD_PHYXS_SYNC, &dword); 534 sync = EFX_DWORD_FIELD(dword, EFX_DWORD_0); 535 stat[EFX_PHY_STAT_PHY_XS_SYNC_A] = (sync >> 0) & 1; 536 stat[EFX_PHY_STAT_PHY_XS_SYNC_B] = (sync >> 1) & 1; 537 stat[EFX_PHY_STAT_PHY_XS_SYNC_C] = (sync >> 2) & 1; 538 stat[EFX_PHY_STAT_PHY_XS_SYNC_D] = (sync >> 3) & 1; 539 } 540 } 541 542 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, AN_LINK_UP); 543 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, AN_COMPLETE); 544 545 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_CL22_LINK_UP, 546 EFX_PHY_STAT_CL22EXT_LINK_UP); 547 548 if (smaskp != NULL) 549 *smaskp = smask; 550 } 551 552 __checkReturn efx_rc_t 553 siena_phy_stats_update( 554 __in efx_nic_t *enp, 555 __in efsys_mem_t *esmp, 556 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat) 557 { 558 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); 559 uint32_t vmask = encp->enc_mcdi_phy_stat_mask; 560 uint64_t smask; 561 efx_mcdi_req_t req; 562 uint8_t payload[MAX(MC_CMD_PHY_STATS_IN_LEN, 563 MC_CMD_PHY_STATS_OUT_DMA_LEN)]; 564 efx_rc_t rc; 565 566 (void) memset(payload, 0, sizeof (payload)); 567 req.emr_cmd = MC_CMD_PHY_STATS; 568 req.emr_in_buf = payload; 569 req.emr_in_length = MC_CMD_PHY_STATS_IN_LEN; 570 req.emr_out_buf = payload; 571 req.emr_out_length = MC_CMD_PHY_STATS_OUT_DMA_LEN; 572 573 MCDI_IN_SET_DWORD(req, PHY_STATS_IN_DMA_ADDR_LO, 574 EFSYS_MEM_ADDR(esmp) & 0xffffffff); 575 MCDI_IN_SET_DWORD(req, PHY_STATS_IN_DMA_ADDR_HI, 576 EFSYS_MEM_ADDR(esmp) >> 32); 577 578 efx_mcdi_execute(enp, &req); 579 580 if (req.emr_rc != 0) { 581 rc = req.emr_rc; 582 goto fail1; 583 } 584 EFSYS_ASSERT3U(req.emr_out_length, ==, MC_CMD_PHY_STATS_OUT_DMA_LEN); 585 586 siena_phy_decode_stats(enp, vmask, esmp, &smask, stat); 587 EFSYS_ASSERT(smask == encp->enc_phy_stat_mask); 588 589 return (0); 590 591 fail1: 592 EFSYS_PROBE1(fail1, efx_rc_t, rc); 593 594 return (0); 595 } 596 597 #endif /* EFSYS_OPT_PHY_STATS */ 598 599 #if EFSYS_OPT_BIST 600 601 __checkReturn efx_rc_t 602 siena_phy_bist_start( 603 __in efx_nic_t *enp, 604 __in efx_bist_type_t type) 605 { 606 efx_rc_t rc; 607 608 if ((rc = efx_mcdi_bist_start(enp, type)) != 0) 609 goto fail1; 610 611 return (0); 612 613 fail1: 614 EFSYS_PROBE1(fail1, efx_rc_t, rc); 615 616 return (rc); 617 } 618 619 static __checkReturn unsigned long 620 siena_phy_sft9001_bist_status( 621 __in uint16_t code) 622 { 623 switch (code) { 624 case MC_CMD_POLL_BIST_SFT9001_PAIR_BUSY: 625 return (EFX_PHY_CABLE_STATUS_BUSY); 626 case MC_CMD_POLL_BIST_SFT9001_INTER_PAIR_SHORT: 627 return (EFX_PHY_CABLE_STATUS_INTERPAIRSHORT); 628 case MC_CMD_POLL_BIST_SFT9001_INTRA_PAIR_SHORT: 629 return (EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT); 630 case MC_CMD_POLL_BIST_SFT9001_PAIR_OPEN: 631 return (EFX_PHY_CABLE_STATUS_OPEN); 632 case MC_CMD_POLL_BIST_SFT9001_PAIR_OK: 633 return (EFX_PHY_CABLE_STATUS_OK); 634 default: 635 return (EFX_PHY_CABLE_STATUS_INVALID); 636 } 637 } 638 639 __checkReturn efx_rc_t 640 siena_phy_bist_poll( 641 __in efx_nic_t *enp, 642 __in efx_bist_type_t type, 643 __out efx_bist_result_t *resultp, 644 __out_opt __drv_when(count > 0, __notnull) 645 uint32_t *value_maskp, 646 __out_ecount_opt(count) __drv_when(count > 0, __notnull) 647 unsigned long *valuesp, 648 __in size_t count) 649 { 650 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); 651 uint8_t payload[MAX(MC_CMD_POLL_BIST_IN_LEN, 652 MCDI_CTL_SDU_LEN_MAX)]; 653 uint32_t value_mask = 0; 654 efx_mcdi_req_t req; 655 uint32_t result; 656 efx_rc_t rc; 657 658 (void) memset(payload, 0, sizeof (payload)); 659 req.emr_cmd = MC_CMD_POLL_BIST; 660 req.emr_in_buf = payload; 661 req.emr_in_length = MC_CMD_POLL_BIST_IN_LEN; 662 req.emr_out_buf = payload; 663 req.emr_out_length = MCDI_CTL_SDU_LEN_MAX; 664 665 efx_mcdi_execute(enp, &req); 666 667 if (req.emr_rc != 0) { 668 rc = req.emr_rc; 669 goto fail1; 670 } 671 672 if (req.emr_out_length_used < MC_CMD_POLL_BIST_OUT_RESULT_OFST + 4) { 673 rc = EMSGSIZE; 674 goto fail2; 675 } 676 677 if (count > 0) 678 (void) memset(valuesp, '\0', count * sizeof (unsigned long)); 679 680 result = MCDI_OUT_DWORD(req, POLL_BIST_OUT_RESULT); 681 682 /* Extract PHY specific results */ 683 if (result == MC_CMD_POLL_BIST_PASSED && 684 encp->enc_phy_type == EFX_PHY_SFT9001B && 685 req.emr_out_length_used >= MC_CMD_POLL_BIST_OUT_SFT9001_LEN && 686 (type == EFX_BIST_TYPE_PHY_CABLE_SHORT || 687 type == EFX_BIST_TYPE_PHY_CABLE_LONG)) { 688 uint16_t word; 689 690 if (count > EFX_BIST_PHY_CABLE_LENGTH_A) { 691 if (valuesp != NULL) 692 valuesp[EFX_BIST_PHY_CABLE_LENGTH_A] = 693 MCDI_OUT_DWORD(req, 694 POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A); 695 value_mask |= (1 << EFX_BIST_PHY_CABLE_LENGTH_A); 696 } 697 698 if (count > EFX_BIST_PHY_CABLE_LENGTH_B) { 699 if (valuesp != NULL) 700 valuesp[EFX_BIST_PHY_CABLE_LENGTH_B] = 701 MCDI_OUT_DWORD(req, 702 POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B); 703 value_mask |= (1 << EFX_BIST_PHY_CABLE_LENGTH_B); 704 } 705 706 if (count > EFX_BIST_PHY_CABLE_LENGTH_C) { 707 if (valuesp != NULL) 708 valuesp[EFX_BIST_PHY_CABLE_LENGTH_C] = 709 MCDI_OUT_DWORD(req, 710 POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C); 711 value_mask |= (1 << EFX_BIST_PHY_CABLE_LENGTH_C); 712 } 713 714 if (count > EFX_BIST_PHY_CABLE_LENGTH_D) { 715 if (valuesp != NULL) 716 valuesp[EFX_BIST_PHY_CABLE_LENGTH_D] = 717 MCDI_OUT_DWORD(req, 718 POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D); 719 value_mask |= (1 << EFX_BIST_PHY_CABLE_LENGTH_D); 720 } 721 722 if (count > EFX_BIST_PHY_CABLE_STATUS_A) { 723 if (valuesp != NULL) { 724 word = MCDI_OUT_WORD(req, 725 POLL_BIST_OUT_SFT9001_CABLE_STATUS_A); 726 valuesp[EFX_BIST_PHY_CABLE_STATUS_A] = 727 siena_phy_sft9001_bist_status(word); 728 } 729 value_mask |= (1 << EFX_BIST_PHY_CABLE_STATUS_A); 730 } 731 732 if (count > EFX_BIST_PHY_CABLE_STATUS_B) { 733 if (valuesp != NULL) { 734 word = MCDI_OUT_WORD(req, 735 POLL_BIST_OUT_SFT9001_CABLE_STATUS_B); 736 valuesp[EFX_BIST_PHY_CABLE_STATUS_B] = 737 siena_phy_sft9001_bist_status(word); 738 } 739 value_mask |= (1 << EFX_BIST_PHY_CABLE_STATUS_B); 740 } 741 742 if (count > EFX_BIST_PHY_CABLE_STATUS_C) { 743 if (valuesp != NULL) { 744 word = MCDI_OUT_WORD(req, 745 POLL_BIST_OUT_SFT9001_CABLE_STATUS_C); 746 valuesp[EFX_BIST_PHY_CABLE_STATUS_C] = 747 siena_phy_sft9001_bist_status(word); 748 } 749 value_mask |= (1 << EFX_BIST_PHY_CABLE_STATUS_C); 750 } 751 752 if (count > EFX_BIST_PHY_CABLE_STATUS_D) { 753 if (valuesp != NULL) { 754 word = MCDI_OUT_WORD(req, 755 POLL_BIST_OUT_SFT9001_CABLE_STATUS_D); 756 valuesp[EFX_BIST_PHY_CABLE_STATUS_D] = 757 siena_phy_sft9001_bist_status(word); 758 } 759 value_mask |= (1 << EFX_BIST_PHY_CABLE_STATUS_D); 760 } 761 762 } else if (result == MC_CMD_POLL_BIST_FAILED && 763 encp->enc_phy_type == EFX_PHY_QLX111V && 764 req.emr_out_length >= MC_CMD_POLL_BIST_OUT_MRSFP_LEN && 765 count > EFX_BIST_FAULT_CODE) { 766 if (valuesp != NULL) 767 valuesp[EFX_BIST_FAULT_CODE] = 768 MCDI_OUT_DWORD(req, POLL_BIST_OUT_MRSFP_TEST); 769 value_mask |= 1 << EFX_BIST_FAULT_CODE; 770 } 771 772 if (value_maskp != NULL) 773 *value_maskp = value_mask; 774 775 EFSYS_ASSERT(resultp != NULL); 776 if (result == MC_CMD_POLL_BIST_RUNNING) 777 *resultp = EFX_BIST_RESULT_RUNNING; 778 else if (result == MC_CMD_POLL_BIST_PASSED) 779 *resultp = EFX_BIST_RESULT_PASSED; 780 else 781 *resultp = EFX_BIST_RESULT_FAILED; 782 783 return (0); 784 785 fail2: 786 EFSYS_PROBE(fail2); 787 fail1: 788 EFSYS_PROBE1(fail1, efx_rc_t, rc); 789 790 return (rc); 791 } 792 793 void 794 siena_phy_bist_stop( 795 __in efx_nic_t *enp, 796 __in efx_bist_type_t type) 797 { 798 /* There is no way to stop BIST on Siena */ 799 _NOTE(ARGUNUSED(enp, type)) 800 } 801 802 #endif /* EFSYS_OPT_BIST */ 803 804 #endif /* EFSYS_OPT_SIENA */ 805