1 /*- 2 * Copyright (c) 2009-2016 Solarflare Communications Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * The views and conclusions contained in the software and documentation are 27 * those of the authors and should not be interpreted as representing official 28 * policies, either expressed or implied, of the FreeBSD Project. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include "efx.h" 35 #include "efx_impl.h" 36 37 #if EFSYS_OPT_SIENA 38 39 static void 40 siena_phy_decode_cap( 41 __in uint32_t mcdi_cap, 42 __out uint32_t *maskp) 43 { 44 uint32_t mask; 45 46 mask = 0; 47 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_10HDX_LBN)) 48 mask |= (1 << EFX_PHY_CAP_10HDX); 49 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_10FDX_LBN)) 50 mask |= (1 << EFX_PHY_CAP_10FDX); 51 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_100HDX_LBN)) 52 mask |= (1 << EFX_PHY_CAP_100HDX); 53 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_100FDX_LBN)) 54 mask |= (1 << EFX_PHY_CAP_100FDX); 55 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_1000HDX_LBN)) 56 mask |= (1 << EFX_PHY_CAP_1000HDX); 57 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_1000FDX_LBN)) 58 mask |= (1 << EFX_PHY_CAP_1000FDX); 59 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_10000FDX_LBN)) 60 mask |= (1 << EFX_PHY_CAP_10000FDX); 61 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_PAUSE_LBN)) 62 mask |= (1 << EFX_PHY_CAP_PAUSE); 63 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_ASYM_LBN)) 64 mask |= (1 << EFX_PHY_CAP_ASYM); 65 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_AN_LBN)) 66 mask |= (1 << EFX_PHY_CAP_AN); 67 68 *maskp = mask; 69 } 70 71 static void 72 siena_phy_decode_link_mode( 73 __in efx_nic_t *enp, 74 __in uint32_t link_flags, 75 __in unsigned int speed, 76 __in unsigned int fcntl, 77 __out efx_link_mode_t *link_modep, 78 __out unsigned int *fcntlp) 79 { 80 boolean_t fd = !!(link_flags & 81 (1 << MC_CMD_GET_LINK_OUT_FULL_DUPLEX_LBN)); 82 boolean_t up = !!(link_flags & 83 (1 << MC_CMD_GET_LINK_OUT_LINK_UP_LBN)); 84 85 _NOTE(ARGUNUSED(enp)) 86 87 if (!up) 88 *link_modep = EFX_LINK_DOWN; 89 else if (speed == 10000 && fd) 90 *link_modep = EFX_LINK_10000FDX; 91 else if (speed == 1000) 92 *link_modep = fd ? EFX_LINK_1000FDX : EFX_LINK_1000HDX; 93 else if (speed == 100) 94 *link_modep = fd ? EFX_LINK_100FDX : EFX_LINK_100HDX; 95 else if (speed == 10) 96 *link_modep = fd ? EFX_LINK_10FDX : EFX_LINK_10HDX; 97 else 98 *link_modep = EFX_LINK_UNKNOWN; 99 100 if (fcntl == MC_CMD_FCNTL_OFF) 101 *fcntlp = 0; 102 else if (fcntl == MC_CMD_FCNTL_RESPOND) 103 *fcntlp = EFX_FCNTL_RESPOND; 104 else if (fcntl == MC_CMD_FCNTL_BIDIR) 105 *fcntlp = EFX_FCNTL_RESPOND | EFX_FCNTL_GENERATE; 106 else { 107 EFSYS_PROBE1(mc_pcol_error, int, fcntl); 108 *fcntlp = 0; 109 } 110 } 111 112 void 113 siena_phy_link_ev( 114 __in efx_nic_t *enp, 115 __in efx_qword_t *eqp, 116 __out efx_link_mode_t *link_modep) 117 { 118 efx_port_t *epp = &(enp->en_port); 119 unsigned int link_flags; 120 unsigned int speed; 121 unsigned int fcntl; 122 efx_link_mode_t link_mode; 123 uint32_t lp_cap_mask; 124 125 /* 126 * Convert the LINKCHANGE speed enumeration into mbit/s, in the 127 * same way as GET_LINK encodes the speed 128 */ 129 switch (MCDI_EV_FIELD(eqp, LINKCHANGE_SPEED)) { 130 case MCDI_EVENT_LINKCHANGE_SPEED_100M: 131 speed = 100; 132 break; 133 case MCDI_EVENT_LINKCHANGE_SPEED_1G: 134 speed = 1000; 135 break; 136 case MCDI_EVENT_LINKCHANGE_SPEED_10G: 137 speed = 10000; 138 break; 139 default: 140 speed = 0; 141 break; 142 } 143 144 link_flags = MCDI_EV_FIELD(eqp, LINKCHANGE_LINK_FLAGS); 145 siena_phy_decode_link_mode(enp, link_flags, speed, 146 MCDI_EV_FIELD(eqp, LINKCHANGE_FCNTL), 147 &link_mode, &fcntl); 148 siena_phy_decode_cap(MCDI_EV_FIELD(eqp, LINKCHANGE_LP_CAP), 149 &lp_cap_mask); 150 151 /* 152 * It's safe to update ep_lp_cap_mask without the driver's port lock 153 * because presumably any concurrently running efx_port_poll() is 154 * only going to arrive at the same value. 155 * 156 * ep_fcntl has two meanings. It's either the link common fcntl 157 * (if the PHY supports AN), or it's the forced link state. If 158 * the former, it's safe to update the value for the same reason as 159 * for ep_lp_cap_mask. If the latter, then just ignore the value, 160 * because we can race with efx_mac_fcntl_set(). 161 */ 162 epp->ep_lp_cap_mask = lp_cap_mask; 163 if (epp->ep_phy_cap_mask & (1 << EFX_PHY_CAP_AN)) 164 epp->ep_fcntl = fcntl; 165 166 *link_modep = link_mode; 167 } 168 169 __checkReturn efx_rc_t 170 siena_phy_power( 171 __in efx_nic_t *enp, 172 __in boolean_t power) 173 { 174 efx_rc_t rc; 175 176 if (!power) 177 return (0); 178 179 /* Check if the PHY is a zombie */ 180 if ((rc = siena_phy_verify(enp)) != 0) 181 goto fail1; 182 183 enp->en_reset_flags |= EFX_RESET_PHY; 184 185 return (0); 186 187 fail1: 188 EFSYS_PROBE1(fail1, efx_rc_t, rc); 189 190 return (rc); 191 } 192 193 __checkReturn efx_rc_t 194 siena_phy_get_link( 195 __in efx_nic_t *enp, 196 __out siena_link_state_t *slsp) 197 { 198 efx_mcdi_req_t req; 199 uint8_t payload[MAX(MC_CMD_GET_LINK_IN_LEN, 200 MC_CMD_GET_LINK_OUT_LEN)]; 201 efx_rc_t rc; 202 203 (void) memset(payload, 0, sizeof (payload)); 204 req.emr_cmd = MC_CMD_GET_LINK; 205 req.emr_in_buf = payload; 206 req.emr_in_length = MC_CMD_GET_LINK_IN_LEN; 207 req.emr_out_buf = payload; 208 req.emr_out_length = MC_CMD_GET_LINK_OUT_LEN; 209 210 efx_mcdi_execute(enp, &req); 211 212 if (req.emr_rc != 0) { 213 rc = req.emr_rc; 214 goto fail1; 215 } 216 217 if (req.emr_out_length_used < MC_CMD_GET_LINK_OUT_LEN) { 218 rc = EMSGSIZE; 219 goto fail2; 220 } 221 222 siena_phy_decode_cap(MCDI_OUT_DWORD(req, GET_LINK_OUT_CAP), 223 &slsp->sls_adv_cap_mask); 224 siena_phy_decode_cap(MCDI_OUT_DWORD(req, GET_LINK_OUT_LP_CAP), 225 &slsp->sls_lp_cap_mask); 226 227 siena_phy_decode_link_mode(enp, MCDI_OUT_DWORD(req, GET_LINK_OUT_FLAGS), 228 MCDI_OUT_DWORD(req, GET_LINK_OUT_LINK_SPEED), 229 MCDI_OUT_DWORD(req, GET_LINK_OUT_FCNTL), 230 &slsp->sls_link_mode, &slsp->sls_fcntl); 231 232 #if EFSYS_OPT_LOOPBACK 233 /* Assert the MC_CMD_LOOPBACK and EFX_LOOPBACK namespace agree */ 234 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_NONE == EFX_LOOPBACK_OFF); 235 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_DATA == EFX_LOOPBACK_DATA); 236 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GMAC == EFX_LOOPBACK_GMAC); 237 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XGMII == EFX_LOOPBACK_XGMII); 238 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XGXS == EFX_LOOPBACK_XGXS); 239 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XAUI == EFX_LOOPBACK_XAUI); 240 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GMII == EFX_LOOPBACK_GMII); 241 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SGMII == EFX_LOOPBACK_SGMII); 242 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XGBR == EFX_LOOPBACK_XGBR); 243 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XFI == EFX_LOOPBACK_XFI); 244 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XAUI_FAR == EFX_LOOPBACK_XAUI_FAR); 245 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GMII_FAR == EFX_LOOPBACK_GMII_FAR); 246 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SGMII_FAR == EFX_LOOPBACK_SGMII_FAR); 247 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XFI_FAR == EFX_LOOPBACK_XFI_FAR); 248 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GPHY == EFX_LOOPBACK_GPHY); 249 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PHYXS == EFX_LOOPBACK_PHY_XS); 250 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PCS == EFX_LOOPBACK_PCS); 251 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PMAPMD == EFX_LOOPBACK_PMA_PMD); 252 253 slsp->sls_loopback = MCDI_OUT_DWORD(req, GET_LINK_OUT_LOOPBACK_MODE); 254 #endif /* EFSYS_OPT_LOOPBACK */ 255 256 slsp->sls_mac_up = MCDI_OUT_DWORD(req, GET_LINK_OUT_MAC_FAULT) == 0; 257 258 return (0); 259 260 fail2: 261 EFSYS_PROBE(fail2); 262 fail1: 263 EFSYS_PROBE1(fail1, efx_rc_t, rc); 264 265 return (rc); 266 } 267 268 __checkReturn efx_rc_t 269 siena_phy_reconfigure( 270 __in efx_nic_t *enp) 271 { 272 efx_port_t *epp = &(enp->en_port); 273 efx_mcdi_req_t req; 274 uint8_t payload[MAX(MAX(MC_CMD_SET_ID_LED_IN_LEN, 275 MC_CMD_SET_ID_LED_OUT_LEN), 276 MAX(MC_CMD_SET_LINK_IN_LEN, 277 MC_CMD_SET_LINK_OUT_LEN))]; 278 uint32_t cap_mask; 279 unsigned int led_mode; 280 unsigned int speed; 281 efx_rc_t rc; 282 283 (void) memset(payload, 0, sizeof (payload)); 284 req.emr_cmd = MC_CMD_SET_LINK; 285 req.emr_in_buf = payload; 286 req.emr_in_length = MC_CMD_SET_LINK_IN_LEN; 287 req.emr_out_buf = payload; 288 req.emr_out_length = MC_CMD_SET_LINK_OUT_LEN; 289 290 cap_mask = epp->ep_adv_cap_mask; 291 MCDI_IN_POPULATE_DWORD_10(req, SET_LINK_IN_CAP, 292 PHY_CAP_10HDX, (cap_mask >> EFX_PHY_CAP_10HDX) & 0x1, 293 PHY_CAP_10FDX, (cap_mask >> EFX_PHY_CAP_10FDX) & 0x1, 294 PHY_CAP_100HDX, (cap_mask >> EFX_PHY_CAP_100HDX) & 0x1, 295 PHY_CAP_100FDX, (cap_mask >> EFX_PHY_CAP_100FDX) & 0x1, 296 PHY_CAP_1000HDX, (cap_mask >> EFX_PHY_CAP_1000HDX) & 0x1, 297 PHY_CAP_1000FDX, (cap_mask >> EFX_PHY_CAP_1000FDX) & 0x1, 298 PHY_CAP_10000FDX, (cap_mask >> EFX_PHY_CAP_10000FDX) & 0x1, 299 PHY_CAP_PAUSE, (cap_mask >> EFX_PHY_CAP_PAUSE) & 0x1, 300 PHY_CAP_ASYM, (cap_mask >> EFX_PHY_CAP_ASYM) & 0x1, 301 PHY_CAP_AN, (cap_mask >> EFX_PHY_CAP_AN) & 0x1); 302 303 #if EFSYS_OPT_LOOPBACK 304 MCDI_IN_SET_DWORD(req, SET_LINK_IN_LOOPBACK_MODE, 305 epp->ep_loopback_type); 306 switch (epp->ep_loopback_link_mode) { 307 case EFX_LINK_100FDX: 308 speed = 100; 309 break; 310 case EFX_LINK_1000FDX: 311 speed = 1000; 312 break; 313 case EFX_LINK_10000FDX: 314 speed = 10000; 315 break; 316 default: 317 speed = 0; 318 } 319 #else 320 MCDI_IN_SET_DWORD(req, SET_LINK_IN_LOOPBACK_MODE, MC_CMD_LOOPBACK_NONE); 321 speed = 0; 322 #endif /* EFSYS_OPT_LOOPBACK */ 323 MCDI_IN_SET_DWORD(req, SET_LINK_IN_LOOPBACK_SPEED, speed); 324 325 #if EFSYS_OPT_PHY_FLAGS 326 MCDI_IN_SET_DWORD(req, SET_LINK_IN_FLAGS, epp->ep_phy_flags); 327 #else 328 MCDI_IN_SET_DWORD(req, SET_LINK_IN_FLAGS, 0); 329 #endif /* EFSYS_OPT_PHY_FLAGS */ 330 331 efx_mcdi_execute(enp, &req); 332 333 if (req.emr_rc != 0) { 334 rc = req.emr_rc; 335 goto fail1; 336 } 337 338 /* And set the blink mode */ 339 (void) memset(payload, 0, sizeof (payload)); 340 req.emr_cmd = MC_CMD_SET_ID_LED; 341 req.emr_in_buf = payload; 342 req.emr_in_length = MC_CMD_SET_ID_LED_IN_LEN; 343 req.emr_out_buf = payload; 344 req.emr_out_length = MC_CMD_SET_ID_LED_OUT_LEN; 345 346 #if EFSYS_OPT_PHY_LED_CONTROL 347 switch (epp->ep_phy_led_mode) { 348 case EFX_PHY_LED_DEFAULT: 349 led_mode = MC_CMD_LED_DEFAULT; 350 break; 351 case EFX_PHY_LED_OFF: 352 led_mode = MC_CMD_LED_OFF; 353 break; 354 case EFX_PHY_LED_ON: 355 led_mode = MC_CMD_LED_ON; 356 break; 357 default: 358 EFSYS_ASSERT(0); 359 led_mode = MC_CMD_LED_DEFAULT; 360 } 361 362 MCDI_IN_SET_DWORD(req, SET_ID_LED_IN_STATE, led_mode); 363 #else 364 MCDI_IN_SET_DWORD(req, SET_ID_LED_IN_STATE, MC_CMD_LED_DEFAULT); 365 #endif /* EFSYS_OPT_PHY_LED_CONTROL */ 366 367 efx_mcdi_execute(enp, &req); 368 369 if (req.emr_rc != 0) { 370 rc = req.emr_rc; 371 goto fail2; 372 } 373 374 return (0); 375 376 fail2: 377 EFSYS_PROBE(fail2); 378 fail1: 379 EFSYS_PROBE1(fail1, efx_rc_t, rc); 380 381 return (rc); 382 } 383 384 __checkReturn efx_rc_t 385 siena_phy_verify( 386 __in efx_nic_t *enp) 387 { 388 efx_mcdi_req_t req; 389 uint8_t payload[MAX(MC_CMD_GET_PHY_STATE_IN_LEN, 390 MC_CMD_GET_PHY_STATE_OUT_LEN)]; 391 uint32_t state; 392 efx_rc_t rc; 393 394 (void) memset(payload, 0, sizeof (payload)); 395 req.emr_cmd = MC_CMD_GET_PHY_STATE; 396 req.emr_in_buf = payload; 397 req.emr_in_length = MC_CMD_GET_PHY_STATE_IN_LEN; 398 req.emr_out_buf = payload; 399 req.emr_out_length = MC_CMD_GET_PHY_STATE_OUT_LEN; 400 401 efx_mcdi_execute(enp, &req); 402 403 if (req.emr_rc != 0) { 404 rc = req.emr_rc; 405 goto fail1; 406 } 407 408 if (req.emr_out_length_used < MC_CMD_GET_PHY_STATE_OUT_LEN) { 409 rc = EMSGSIZE; 410 goto fail2; 411 } 412 413 state = MCDI_OUT_DWORD(req, GET_PHY_STATE_OUT_STATE); 414 if (state != MC_CMD_PHY_STATE_OK) { 415 if (state != MC_CMD_PHY_STATE_ZOMBIE) 416 EFSYS_PROBE1(mc_pcol_error, int, state); 417 rc = ENOTACTIVE; 418 goto fail3; 419 } 420 421 return (0); 422 423 fail3: 424 EFSYS_PROBE(fail3); 425 fail2: 426 EFSYS_PROBE(fail2); 427 fail1: 428 EFSYS_PROBE1(fail1, efx_rc_t, rc); 429 430 return (rc); 431 } 432 433 __checkReturn efx_rc_t 434 siena_phy_oui_get( 435 __in efx_nic_t *enp, 436 __out uint32_t *ouip) 437 { 438 _NOTE(ARGUNUSED(enp, ouip)) 439 440 return (ENOTSUP); 441 } 442 443 #if EFSYS_OPT_PHY_STATS 444 445 #define SIENA_SIMPLE_STAT_SET(_vmask, _esmp, _smask, _stat, \ 446 _mc_record, _efx_record) \ 447 if ((_vmask) & (1ULL << (_mc_record))) { \ 448 (_smask) |= (1ULL << (_efx_record)); \ 449 if ((_stat) != NULL && !EFSYS_MEM_IS_NULL(_esmp)) { \ 450 efx_dword_t dword; \ 451 EFSYS_MEM_READD(_esmp, (_mc_record) * 4, &dword);\ 452 (_stat)[_efx_record] = \ 453 EFX_DWORD_FIELD(dword, EFX_DWORD_0); \ 454 } \ 455 } 456 457 #define SIENA_SIMPLE_STAT_SET2(_vmask, _esmp, _smask, _stat, _record) \ 458 SIENA_SIMPLE_STAT_SET(_vmask, _esmp, _smask, _stat, \ 459 MC_CMD_ ## _record, \ 460 EFX_PHY_STAT_ ## _record) 461 462 void 463 siena_phy_decode_stats( 464 __in efx_nic_t *enp, 465 __in uint32_t vmask, 466 __in_opt efsys_mem_t *esmp, 467 __out_opt uint64_t *smaskp, 468 __inout_ecount_opt(EFX_PHY_NSTATS) uint32_t *stat) 469 { 470 uint64_t smask = 0; 471 472 _NOTE(ARGUNUSED(enp)) 473 474 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, OUI); 475 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PMA_PMD_LINK_UP); 476 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PMA_PMD_RX_FAULT); 477 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PMA_PMD_TX_FAULT); 478 479 if (vmask & (1 << MC_CMD_PMA_PMD_SIGNAL)) { 480 smask |= ((1ULL << EFX_PHY_STAT_PMA_PMD_SIGNAL_A) | 481 (1ULL << EFX_PHY_STAT_PMA_PMD_SIGNAL_B) | 482 (1ULL << EFX_PHY_STAT_PMA_PMD_SIGNAL_C) | 483 (1ULL << EFX_PHY_STAT_PMA_PMD_SIGNAL_D)); 484 if (stat != NULL && esmp != NULL && !EFSYS_MEM_IS_NULL(esmp)) { 485 efx_dword_t dword; 486 uint32_t sig; 487 EFSYS_MEM_READD(esmp, 4 * MC_CMD_PMA_PMD_SIGNAL, 488 &dword); 489 sig = EFX_DWORD_FIELD(dword, EFX_DWORD_0); 490 stat[EFX_PHY_STAT_PMA_PMD_SIGNAL_A] = (sig >> 1) & 1; 491 stat[EFX_PHY_STAT_PMA_PMD_SIGNAL_B] = (sig >> 2) & 1; 492 stat[EFX_PHY_STAT_PMA_PMD_SIGNAL_C] = (sig >> 3) & 1; 493 stat[EFX_PHY_STAT_PMA_PMD_SIGNAL_D] = (sig >> 4) & 1; 494 } 495 } 496 497 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PMA_PMD_SNR_A, 498 EFX_PHY_STAT_SNR_A); 499 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PMA_PMD_SNR_B, 500 EFX_PHY_STAT_SNR_B); 501 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PMA_PMD_SNR_C, 502 EFX_PHY_STAT_SNR_C); 503 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PMA_PMD_SNR_D, 504 EFX_PHY_STAT_SNR_D); 505 506 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_LINK_UP); 507 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_RX_FAULT); 508 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_TX_FAULT); 509 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_BER); 510 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_BLOCK_ERRORS); 511 512 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PHYXS_LINK_UP, 513 EFX_PHY_STAT_PHY_XS_LINK_UP); 514 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PHYXS_RX_FAULT, 515 EFX_PHY_STAT_PHY_XS_RX_FAULT); 516 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PHYXS_TX_FAULT, 517 EFX_PHY_STAT_PHY_XS_TX_FAULT); 518 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PHYXS_ALIGN, 519 EFX_PHY_STAT_PHY_XS_ALIGN); 520 521 if (vmask & (1 << MC_CMD_PHYXS_SYNC)) { 522 smask |= ((1 << EFX_PHY_STAT_PHY_XS_SYNC_A) | 523 (1 << EFX_PHY_STAT_PHY_XS_SYNC_B) | 524 (1 << EFX_PHY_STAT_PHY_XS_SYNC_C) | 525 (1 << EFX_PHY_STAT_PHY_XS_SYNC_D)); 526 if (stat != NULL && !EFSYS_MEM_IS_NULL(esmp)) { 527 efx_dword_t dword; 528 uint32_t sync; 529 EFSYS_MEM_READD(esmp, 4 * MC_CMD_PHYXS_SYNC, &dword); 530 sync = EFX_DWORD_FIELD(dword, EFX_DWORD_0); 531 stat[EFX_PHY_STAT_PHY_XS_SYNC_A] = (sync >> 0) & 1; 532 stat[EFX_PHY_STAT_PHY_XS_SYNC_B] = (sync >> 1) & 1; 533 stat[EFX_PHY_STAT_PHY_XS_SYNC_C] = (sync >> 2) & 1; 534 stat[EFX_PHY_STAT_PHY_XS_SYNC_D] = (sync >> 3) & 1; 535 } 536 } 537 538 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, AN_LINK_UP); 539 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, AN_COMPLETE); 540 541 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_CL22_LINK_UP, 542 EFX_PHY_STAT_CL22EXT_LINK_UP); 543 544 if (smaskp != NULL) 545 *smaskp = smask; 546 } 547 548 __checkReturn efx_rc_t 549 siena_phy_stats_update( 550 __in efx_nic_t *enp, 551 __in efsys_mem_t *esmp, 552 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat) 553 { 554 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); 555 uint32_t vmask = encp->enc_mcdi_phy_stat_mask; 556 uint64_t smask; 557 efx_mcdi_req_t req; 558 uint8_t payload[MAX(MC_CMD_PHY_STATS_IN_LEN, 559 MC_CMD_PHY_STATS_OUT_DMA_LEN)]; 560 efx_rc_t rc; 561 562 (void) memset(payload, 0, sizeof (payload)); 563 req.emr_cmd = MC_CMD_PHY_STATS; 564 req.emr_in_buf = payload; 565 req.emr_in_length = MC_CMD_PHY_STATS_IN_LEN; 566 req.emr_out_buf = payload; 567 req.emr_out_length = MC_CMD_PHY_STATS_OUT_DMA_LEN; 568 569 MCDI_IN_SET_DWORD(req, PHY_STATS_IN_DMA_ADDR_LO, 570 EFSYS_MEM_ADDR(esmp) & 0xffffffff); 571 MCDI_IN_SET_DWORD(req, PHY_STATS_IN_DMA_ADDR_HI, 572 EFSYS_MEM_ADDR(esmp) >> 32); 573 574 efx_mcdi_execute(enp, &req); 575 576 if (req.emr_rc != 0) { 577 rc = req.emr_rc; 578 goto fail1; 579 } 580 EFSYS_ASSERT3U(req.emr_out_length, ==, MC_CMD_PHY_STATS_OUT_DMA_LEN); 581 582 siena_phy_decode_stats(enp, vmask, esmp, &smask, stat); 583 EFSYS_ASSERT(smask == encp->enc_phy_stat_mask); 584 585 return (0); 586 587 fail1: 588 EFSYS_PROBE1(fail1, efx_rc_t, rc); 589 590 return (0); 591 } 592 593 #endif /* EFSYS_OPT_PHY_STATS */ 594 595 #if EFSYS_OPT_BIST 596 597 __checkReturn efx_rc_t 598 siena_phy_bist_start( 599 __in efx_nic_t *enp, 600 __in efx_bist_type_t type) 601 { 602 efx_rc_t rc; 603 604 if ((rc = efx_mcdi_bist_start(enp, type)) != 0) 605 goto fail1; 606 607 return (0); 608 609 fail1: 610 EFSYS_PROBE1(fail1, efx_rc_t, rc); 611 612 return (rc); 613 } 614 615 static __checkReturn unsigned long 616 siena_phy_sft9001_bist_status( 617 __in uint16_t code) 618 { 619 switch (code) { 620 case MC_CMD_POLL_BIST_SFT9001_PAIR_BUSY: 621 return (EFX_PHY_CABLE_STATUS_BUSY); 622 case MC_CMD_POLL_BIST_SFT9001_INTER_PAIR_SHORT: 623 return (EFX_PHY_CABLE_STATUS_INTERPAIRSHORT); 624 case MC_CMD_POLL_BIST_SFT9001_INTRA_PAIR_SHORT: 625 return (EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT); 626 case MC_CMD_POLL_BIST_SFT9001_PAIR_OPEN: 627 return (EFX_PHY_CABLE_STATUS_OPEN); 628 case MC_CMD_POLL_BIST_SFT9001_PAIR_OK: 629 return (EFX_PHY_CABLE_STATUS_OK); 630 default: 631 return (EFX_PHY_CABLE_STATUS_INVALID); 632 } 633 } 634 635 __checkReturn efx_rc_t 636 siena_phy_bist_poll( 637 __in efx_nic_t *enp, 638 __in efx_bist_type_t type, 639 __out efx_bist_result_t *resultp, 640 __out_opt __drv_when(count > 0, __notnull) 641 uint32_t *value_maskp, 642 __out_ecount_opt(count) __drv_when(count > 0, __notnull) 643 unsigned long *valuesp, 644 __in size_t count) 645 { 646 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); 647 uint8_t payload[MAX(MC_CMD_POLL_BIST_IN_LEN, 648 MCDI_CTL_SDU_LEN_MAX)]; 649 uint32_t value_mask = 0; 650 efx_mcdi_req_t req; 651 uint32_t result; 652 efx_rc_t rc; 653 654 (void) memset(payload, 0, sizeof (payload)); 655 req.emr_cmd = MC_CMD_POLL_BIST; 656 req.emr_in_buf = payload; 657 req.emr_in_length = MC_CMD_POLL_BIST_IN_LEN; 658 req.emr_out_buf = payload; 659 req.emr_out_length = MCDI_CTL_SDU_LEN_MAX; 660 661 efx_mcdi_execute(enp, &req); 662 663 if (req.emr_rc != 0) { 664 rc = req.emr_rc; 665 goto fail1; 666 } 667 668 if (req.emr_out_length_used < MC_CMD_POLL_BIST_OUT_RESULT_OFST + 4) { 669 rc = EMSGSIZE; 670 goto fail2; 671 } 672 673 if (count > 0) 674 (void) memset(valuesp, '\0', count * sizeof (unsigned long)); 675 676 result = MCDI_OUT_DWORD(req, POLL_BIST_OUT_RESULT); 677 678 /* Extract PHY specific results */ 679 if (result == MC_CMD_POLL_BIST_PASSED && 680 encp->enc_phy_type == EFX_PHY_SFT9001B && 681 req.emr_out_length_used >= MC_CMD_POLL_BIST_OUT_SFT9001_LEN && 682 (type == EFX_BIST_TYPE_PHY_CABLE_SHORT || 683 type == EFX_BIST_TYPE_PHY_CABLE_LONG)) { 684 uint16_t word; 685 686 if (count > EFX_BIST_PHY_CABLE_LENGTH_A) { 687 if (valuesp != NULL) 688 valuesp[EFX_BIST_PHY_CABLE_LENGTH_A] = 689 MCDI_OUT_DWORD(req, 690 POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A); 691 value_mask |= (1 << EFX_BIST_PHY_CABLE_LENGTH_A); 692 } 693 694 if (count > EFX_BIST_PHY_CABLE_LENGTH_B) { 695 if (valuesp != NULL) 696 valuesp[EFX_BIST_PHY_CABLE_LENGTH_B] = 697 MCDI_OUT_DWORD(req, 698 POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B); 699 value_mask |= (1 << EFX_BIST_PHY_CABLE_LENGTH_B); 700 } 701 702 if (count > EFX_BIST_PHY_CABLE_LENGTH_C) { 703 if (valuesp != NULL) 704 valuesp[EFX_BIST_PHY_CABLE_LENGTH_C] = 705 MCDI_OUT_DWORD(req, 706 POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C); 707 value_mask |= (1 << EFX_BIST_PHY_CABLE_LENGTH_C); 708 } 709 710 if (count > EFX_BIST_PHY_CABLE_LENGTH_D) { 711 if (valuesp != NULL) 712 valuesp[EFX_BIST_PHY_CABLE_LENGTH_D] = 713 MCDI_OUT_DWORD(req, 714 POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D); 715 value_mask |= (1 << EFX_BIST_PHY_CABLE_LENGTH_D); 716 } 717 718 if (count > EFX_BIST_PHY_CABLE_STATUS_A) { 719 if (valuesp != NULL) { 720 word = MCDI_OUT_WORD(req, 721 POLL_BIST_OUT_SFT9001_CABLE_STATUS_A); 722 valuesp[EFX_BIST_PHY_CABLE_STATUS_A] = 723 siena_phy_sft9001_bist_status(word); 724 } 725 value_mask |= (1 << EFX_BIST_PHY_CABLE_STATUS_A); 726 } 727 728 if (count > EFX_BIST_PHY_CABLE_STATUS_B) { 729 if (valuesp != NULL) { 730 word = MCDI_OUT_WORD(req, 731 POLL_BIST_OUT_SFT9001_CABLE_STATUS_B); 732 valuesp[EFX_BIST_PHY_CABLE_STATUS_B] = 733 siena_phy_sft9001_bist_status(word); 734 } 735 value_mask |= (1 << EFX_BIST_PHY_CABLE_STATUS_B); 736 } 737 738 if (count > EFX_BIST_PHY_CABLE_STATUS_C) { 739 if (valuesp != NULL) { 740 word = MCDI_OUT_WORD(req, 741 POLL_BIST_OUT_SFT9001_CABLE_STATUS_C); 742 valuesp[EFX_BIST_PHY_CABLE_STATUS_C] = 743 siena_phy_sft9001_bist_status(word); 744 } 745 value_mask |= (1 << EFX_BIST_PHY_CABLE_STATUS_C); 746 } 747 748 if (count > EFX_BIST_PHY_CABLE_STATUS_D) { 749 if (valuesp != NULL) { 750 word = MCDI_OUT_WORD(req, 751 POLL_BIST_OUT_SFT9001_CABLE_STATUS_D); 752 valuesp[EFX_BIST_PHY_CABLE_STATUS_D] = 753 siena_phy_sft9001_bist_status(word); 754 } 755 value_mask |= (1 << EFX_BIST_PHY_CABLE_STATUS_D); 756 } 757 758 } else if (result == MC_CMD_POLL_BIST_FAILED && 759 encp->enc_phy_type == EFX_PHY_QLX111V && 760 req.emr_out_length >= MC_CMD_POLL_BIST_OUT_MRSFP_LEN && 761 count > EFX_BIST_FAULT_CODE) { 762 if (valuesp != NULL) 763 valuesp[EFX_BIST_FAULT_CODE] = 764 MCDI_OUT_DWORD(req, POLL_BIST_OUT_MRSFP_TEST); 765 value_mask |= 1 << EFX_BIST_FAULT_CODE; 766 } 767 768 if (value_maskp != NULL) 769 *value_maskp = value_mask; 770 771 EFSYS_ASSERT(resultp != NULL); 772 if (result == MC_CMD_POLL_BIST_RUNNING) 773 *resultp = EFX_BIST_RESULT_RUNNING; 774 else if (result == MC_CMD_POLL_BIST_PASSED) 775 *resultp = EFX_BIST_RESULT_PASSED; 776 else 777 *resultp = EFX_BIST_RESULT_FAILED; 778 779 return (0); 780 781 fail2: 782 EFSYS_PROBE(fail2); 783 fail1: 784 EFSYS_PROBE1(fail1, efx_rc_t, rc); 785 786 return (rc); 787 } 788 789 void 790 siena_phy_bist_stop( 791 __in efx_nic_t *enp, 792 __in efx_bist_type_t type) 793 { 794 /* There is no way to stop BIST on Siena */ 795 _NOTE(ARGUNUSED(enp, type)) 796 } 797 798 #endif /* EFSYS_OPT_BIST */ 799 800 #endif /* EFSYS_OPT_SIENA */ 801