1 /*- 2 * Copyright (c) 2009-2015 Solarflare Communications Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * The views and conclusions contained in the software and documentation are 27 * those of the authors and should not be interpreted as representing official 28 * policies, either expressed or implied, of the FreeBSD Project. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include "efx.h" 35 #include "efx_impl.h" 36 37 #if EFSYS_OPT_SIENA 38 39 __checkReturn efx_rc_t 40 siena_mac_poll( 41 __in efx_nic_t *enp, 42 __out efx_link_mode_t *link_modep) 43 { 44 efx_port_t *epp = &(enp->en_port); 45 siena_link_state_t sls; 46 efx_rc_t rc; 47 48 if ((rc = siena_phy_get_link(enp, &sls)) != 0) 49 goto fail1; 50 51 epp->ep_adv_cap_mask = sls.sls_adv_cap_mask; 52 epp->ep_fcntl = sls.sls_fcntl; 53 54 *link_modep = sls.sls_link_mode; 55 56 return (0); 57 58 fail1: 59 EFSYS_PROBE1(fail1, efx_rc_t, rc); 60 61 *link_modep = EFX_LINK_UNKNOWN; 62 63 return (rc); 64 } 65 66 __checkReturn efx_rc_t 67 siena_mac_up( 68 __in efx_nic_t *enp, 69 __out boolean_t *mac_upp) 70 { 71 siena_link_state_t sls; 72 efx_rc_t rc; 73 74 /* 75 * Because Siena doesn't *require* polling, we can't rely on 76 * siena_mac_poll() being executed to populate epp->ep_mac_up. 77 */ 78 if ((rc = siena_phy_get_link(enp, &sls)) != 0) 79 goto fail1; 80 81 *mac_upp = sls.sls_mac_up; 82 83 return (0); 84 85 fail1: 86 EFSYS_PROBE1(fail1, efx_rc_t, rc); 87 88 return (rc); 89 } 90 91 __checkReturn efx_rc_t 92 siena_mac_reconfigure( 93 __in efx_nic_t *enp) 94 { 95 efx_port_t *epp = &(enp->en_port); 96 efx_oword_t multicast_hash[2]; 97 efx_mcdi_req_t req; 98 uint8_t payload[MAX(MAX(MC_CMD_SET_MAC_IN_LEN, 99 MC_CMD_SET_MAC_OUT_LEN), 100 MAX(MC_CMD_SET_MCAST_HASH_IN_LEN, 101 MC_CMD_SET_MCAST_HASH_OUT_LEN))]; 102 unsigned int fcntl; 103 efx_rc_t rc; 104 105 (void) memset(payload, 0, sizeof (payload)); 106 req.emr_cmd = MC_CMD_SET_MAC; 107 req.emr_in_buf = payload; 108 req.emr_in_length = MC_CMD_SET_MAC_IN_LEN; 109 req.emr_out_buf = payload; 110 req.emr_out_length = MC_CMD_SET_MAC_OUT_LEN; 111 112 MCDI_IN_SET_DWORD(req, SET_MAC_IN_MTU, epp->ep_mac_pdu); 113 MCDI_IN_SET_DWORD(req, SET_MAC_IN_DRAIN, epp->ep_mac_drain ? 1 : 0); 114 EFX_MAC_ADDR_COPY(MCDI_IN2(req, uint8_t, SET_MAC_IN_ADDR), 115 epp->ep_mac_addr); 116 MCDI_IN_POPULATE_DWORD_2(req, SET_MAC_IN_REJECT, 117 SET_MAC_IN_REJECT_UNCST, !epp->ep_all_unicst, 118 SET_MAC_IN_REJECT_BRDCST, !epp->ep_brdcst); 119 120 if (epp->ep_fcntl_autoneg) 121 /* efx_fcntl_set() has already set the phy capabilities */ 122 fcntl = MC_CMD_FCNTL_AUTO; 123 else if (epp->ep_fcntl & EFX_FCNTL_RESPOND) 124 fcntl = (epp->ep_fcntl & EFX_FCNTL_GENERATE) 125 ? MC_CMD_FCNTL_BIDIR 126 : MC_CMD_FCNTL_RESPOND; 127 else 128 fcntl = MC_CMD_FCNTL_OFF; 129 130 MCDI_IN_SET_DWORD(req, SET_MAC_IN_FCNTL, fcntl); 131 132 efx_mcdi_execute(enp, &req); 133 134 if (req.emr_rc != 0) { 135 rc = req.emr_rc; 136 goto fail1; 137 } 138 139 /* Push multicast hash */ 140 141 if (epp->ep_all_mulcst) { 142 /* A hash matching all multicast is all 1s */ 143 EFX_SET_OWORD(multicast_hash[0]); 144 EFX_SET_OWORD(multicast_hash[1]); 145 } else if (epp->ep_mulcst) { 146 /* Use the hash set by the multicast list */ 147 multicast_hash[0] = epp->ep_multicst_hash[0]; 148 multicast_hash[1] = epp->ep_multicst_hash[1]; 149 } else { 150 /* A hash matching no traffic is simply 0 */ 151 EFX_ZERO_OWORD(multicast_hash[0]); 152 EFX_ZERO_OWORD(multicast_hash[1]); 153 } 154 155 /* 156 * Broadcast packets go through the multicast hash filter. 157 * The IEEE 802.3 CRC32 of the broadcast address is 0xbe2612ff 158 * so we always add bit 0xff to the mask (bit 0x7f in the 159 * second octword). 160 */ 161 if (epp->ep_brdcst) 162 EFX_SET_OWORD_BIT(multicast_hash[1], 0x7f); 163 164 (void) memset(payload, 0, sizeof (payload)); 165 req.emr_cmd = MC_CMD_SET_MCAST_HASH; 166 req.emr_in_buf = payload; 167 req.emr_in_length = MC_CMD_SET_MCAST_HASH_IN_LEN; 168 req.emr_out_buf = payload; 169 req.emr_out_length = MC_CMD_SET_MCAST_HASH_OUT_LEN; 170 171 memcpy(MCDI_IN2(req, uint8_t, SET_MCAST_HASH_IN_HASH0), 172 multicast_hash, sizeof (multicast_hash)); 173 174 efx_mcdi_execute(enp, &req); 175 176 if (req.emr_rc != 0) { 177 rc = req.emr_rc; 178 goto fail2; 179 } 180 181 return (0); 182 183 fail2: 184 EFSYS_PROBE(fail2); 185 fail1: 186 EFSYS_PROBE1(fail1, efx_rc_t, rc); 187 188 return (rc); 189 } 190 191 #if EFSYS_OPT_LOOPBACK 192 193 __checkReturn efx_rc_t 194 siena_mac_loopback_set( 195 __in efx_nic_t *enp, 196 __in efx_link_mode_t link_mode, 197 __in efx_loopback_type_t loopback_type) 198 { 199 efx_port_t *epp = &(enp->en_port); 200 efx_phy_ops_t *epop = epp->ep_epop; 201 efx_loopback_type_t old_loopback_type; 202 efx_link_mode_t old_loopback_link_mode; 203 efx_rc_t rc; 204 205 /* The PHY object handles this on Siena */ 206 old_loopback_type = epp->ep_loopback_type; 207 old_loopback_link_mode = epp->ep_loopback_link_mode; 208 epp->ep_loopback_type = loopback_type; 209 epp->ep_loopback_link_mode = link_mode; 210 211 if ((rc = epop->epo_reconfigure(enp)) != 0) 212 goto fail1; 213 214 return (0); 215 216 fail1: 217 EFSYS_PROBE(fail2); 218 219 epp->ep_loopback_type = old_loopback_type; 220 epp->ep_loopback_link_mode = old_loopback_link_mode; 221 222 return (rc); 223 } 224 225 #endif /* EFSYS_OPT_LOOPBACK */ 226 227 #if EFSYS_OPT_MAC_STATS 228 229 #define SIENA_MAC_STAT_READ(_esmp, _field, _eqp) \ 230 EFSYS_MEM_READQ((_esmp), (_field) * sizeof (efx_qword_t), _eqp) 231 232 __checkReturn efx_rc_t 233 siena_mac_stats_update( 234 __in efx_nic_t *enp, 235 __in efsys_mem_t *esmp, 236 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat, 237 __inout_opt uint32_t *generationp) 238 { 239 efx_qword_t value; 240 efx_qword_t generation_start; 241 efx_qword_t generation_end; 242 243 _NOTE(ARGUNUSED(enp)) 244 245 /* Read END first so we don't race with the MC */ 246 EFSYS_DMA_SYNC_FOR_KERNEL(esmp, 0, EFX_MAC_STATS_SIZE); 247 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_GENERATION_END, 248 &generation_end); 249 EFSYS_MEM_READ_BARRIER(); 250 251 /* TX */ 252 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_PKTS, &value); 253 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_PKTS]), &value); 254 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_CONTROL_PKTS, &value); 255 EFSYS_STAT_SUBR_QWORD(&(stat[EFX_MAC_TX_PKTS]), &value); 256 257 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_PAUSE_PKTS, &value); 258 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_PAUSE_PKTS]), &value); 259 260 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_UNICAST_PKTS, &value); 261 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_UNICST_PKTS]), &value); 262 263 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_MULTICAST_PKTS, &value); 264 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_MULTICST_PKTS]), &value); 265 266 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_BROADCAST_PKTS, &value); 267 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_BRDCST_PKTS]), &value); 268 269 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_BYTES, &value); 270 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_OCTETS]), &value); 271 272 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_LT64_PKTS, &value); 273 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_LE_64_PKTS]), &value); 274 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_64_PKTS, &value); 275 EFSYS_STAT_INCR_QWORD(&(stat[EFX_MAC_TX_LE_64_PKTS]), &value); 276 277 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_65_TO_127_PKTS, &value); 278 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_65_TO_127_PKTS]), &value); 279 280 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_128_TO_255_PKTS, &value); 281 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_128_TO_255_PKTS]), &value); 282 283 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_256_TO_511_PKTS, &value); 284 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_256_TO_511_PKTS]), &value); 285 286 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_512_TO_1023_PKTS, &value); 287 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_512_TO_1023_PKTS]), &value); 288 289 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_1024_TO_15XX_PKTS, &value); 290 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_1024_TO_15XX_PKTS]), &value); 291 292 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_15XX_TO_JUMBO_PKTS, &value); 293 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_GE_15XX_PKTS]), &value); 294 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_GTJUMBO_PKTS, &value); 295 EFSYS_STAT_INCR_QWORD(&(stat[EFX_MAC_TX_GE_15XX_PKTS]), &value); 296 297 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_BAD_FCS_PKTS, &value); 298 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_ERRORS]), &value); 299 300 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_SINGLE_COLLISION_PKTS, &value); 301 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_SGL_COL_PKTS]), &value); 302 303 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_MULTIPLE_COLLISION_PKTS, 304 &value); 305 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_MULT_COL_PKTS]), &value); 306 307 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_EXCESSIVE_COLLISION_PKTS, 308 &value); 309 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_EX_COL_PKTS]), &value); 310 311 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_LATE_COLLISION_PKTS, &value); 312 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_LATE_COL_PKTS]), &value); 313 314 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_DEFERRED_PKTS, &value); 315 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_DEF_PKTS]), &value); 316 317 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_EXCESSIVE_DEFERRED_PKTS, 318 &value); 319 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_EX_DEF_PKTS]), &value); 320 321 /* RX */ 322 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_BYTES, &value); 323 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_OCTETS]), &value); 324 325 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_PKTS, &value); 326 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_PKTS]), &value); 327 328 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_UNICAST_PKTS, &value); 329 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_UNICST_PKTS]), &value); 330 331 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_MULTICAST_PKTS, &value); 332 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_MULTICST_PKTS]), &value); 333 334 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_BROADCAST_PKTS, &value); 335 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_BRDCST_PKTS]), &value); 336 337 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_PAUSE_PKTS, &value); 338 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_PAUSE_PKTS]), &value); 339 340 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_UNDERSIZE_PKTS, &value); 341 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_LE_64_PKTS]), &value); 342 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_64_PKTS, &value); 343 EFSYS_STAT_INCR_QWORD(&(stat[EFX_MAC_RX_LE_64_PKTS]), &value); 344 345 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_65_TO_127_PKTS, &value); 346 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_65_TO_127_PKTS]), &value); 347 348 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_128_TO_255_PKTS, &value); 349 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_128_TO_255_PKTS]), &value); 350 351 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_256_TO_511_PKTS, &value); 352 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_256_TO_511_PKTS]), &value); 353 354 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_512_TO_1023_PKTS, &value); 355 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_512_TO_1023_PKTS]), &value); 356 357 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_1024_TO_15XX_PKTS, &value); 358 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_1024_TO_15XX_PKTS]), &value); 359 360 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_15XX_TO_JUMBO_PKTS, &value); 361 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_GE_15XX_PKTS]), &value); 362 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_GTJUMBO_PKTS, &value); 363 EFSYS_STAT_INCR_QWORD(&(stat[EFX_MAC_RX_GE_15XX_PKTS]), &value); 364 365 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_BAD_FCS_PKTS, &value); 366 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_FCS_ERRORS]), &value); 367 368 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_OVERFLOW_PKTS, &value); 369 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_DROP_EVENTS]), &value); 370 371 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_FALSE_CARRIER_PKTS, &value); 372 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_FALSE_CARRIER_ERRORS]), &value); 373 374 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_SYMBOL_ERROR_PKTS, &value); 375 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_SYMBOL_ERRORS]), &value); 376 377 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_ALIGN_ERROR_PKTS, &value); 378 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_ALIGN_ERRORS]), &value); 379 380 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_INTERNAL_ERROR_PKTS, &value); 381 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_INTERNAL_ERRORS]), &value); 382 383 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_JABBER_PKTS, &value); 384 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_JABBER_PKTS]), &value); 385 386 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_LANES01_CHAR_ERR, &value); 387 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE0_CHAR_ERR]), 388 &(value.eq_dword[0])); 389 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE1_CHAR_ERR]), 390 &(value.eq_dword[1])); 391 392 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_LANES23_CHAR_ERR, &value); 393 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE2_CHAR_ERR]), 394 &(value.eq_dword[0])); 395 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE3_CHAR_ERR]), 396 &(value.eq_dword[1])); 397 398 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_LANES01_DISP_ERR, &value); 399 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE0_DISP_ERR]), 400 &(value.eq_dword[0])); 401 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE1_DISP_ERR]), 402 &(value.eq_dword[1])); 403 404 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_LANES23_DISP_ERR, &value); 405 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE2_DISP_ERR]), 406 &(value.eq_dword[0])); 407 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE3_DISP_ERR]), 408 &(value.eq_dword[1])); 409 410 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_MATCH_FAULT, &value); 411 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_MATCH_FAULT]), &value); 412 413 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_NODESC_DROPS, &value); 414 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_NODESC_DROP_CNT]), &value); 415 416 EFSYS_DMA_SYNC_FOR_KERNEL(esmp, 0, EFX_MAC_STATS_SIZE); 417 EFSYS_MEM_READ_BARRIER(); 418 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_GENERATION_START, 419 &generation_start); 420 421 /* Check that we didn't read the stats in the middle of a DMA */ 422 /* Not a good enough check ? */ 423 if (memcmp(&generation_start, &generation_end, 424 sizeof (generation_start))) 425 return (EAGAIN); 426 427 if (generationp) 428 *generationp = EFX_QWORD_FIELD(generation_start, EFX_DWORD_0); 429 430 return (0); 431 } 432 433 #endif /* EFSYS_OPT_MAC_STATS */ 434 435 #endif /* EFSYS_OPT_SIENA */ 436