1 /*- 2 * Copyright (c) 2015 Solarflare Communications Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * The views and conclusions contained in the software and documentation are 27 * those of the authors and should not be interpreted as representing official 28 * policies, either expressed or implied, of the FreeBSD Project. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include "efx.h" 35 #include "efx_impl.h" 36 #include "mcdi_mon.h" 37 38 #if EFSYS_OPT_MEDFORD 39 40 #include "ef10_tlv_layout.h" 41 42 static __checkReturn efx_rc_t 43 efx_mcdi_get_rxdp_config( 44 __in efx_nic_t *enp, 45 __out uint32_t *end_paddingp) 46 { 47 efx_mcdi_req_t req; 48 uint8_t payload[MAX(MC_CMD_GET_RXDP_CONFIG_IN_LEN, 49 MC_CMD_GET_RXDP_CONFIG_OUT_LEN)]; 50 uint32_t end_padding; 51 efx_rc_t rc; 52 53 memset(payload, 0, sizeof (payload)); 54 req.emr_cmd = MC_CMD_GET_RXDP_CONFIG; 55 req.emr_in_buf = payload; 56 req.emr_in_length = MC_CMD_GET_RXDP_CONFIG_IN_LEN; 57 req.emr_out_buf = payload; 58 req.emr_out_length = MC_CMD_GET_RXDP_CONFIG_OUT_LEN; 59 60 efx_mcdi_execute(enp, &req); 61 if (req.emr_rc != 0) { 62 rc = req.emr_rc; 63 goto fail1; 64 } 65 66 if (MCDI_OUT_DWORD_FIELD(req, GET_RXDP_CONFIG_OUT_DATA, 67 GET_RXDP_CONFIG_OUT_PAD_HOST_DMA) == 0) { 68 /* RX DMA end padding is disabled */ 69 end_padding = 0; 70 } else { 71 switch(MCDI_OUT_DWORD_FIELD(req, GET_RXDP_CONFIG_OUT_DATA, 72 GET_RXDP_CONFIG_OUT_PAD_HOST_LEN)) { 73 case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_64: 74 end_padding = 64; 75 break; 76 case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_128: 77 end_padding = 128; 78 break; 79 case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_256: 80 end_padding = 256; 81 break; 82 default: 83 rc = ENOTSUP; 84 goto fail2; 85 } 86 } 87 88 *end_paddingp = end_padding; 89 90 return (0); 91 92 fail2: 93 EFSYS_PROBE(fail2); 94 fail1: 95 EFSYS_PROBE1(fail1, efx_rc_t, rc); 96 97 return (rc); 98 } 99 100 __checkReturn efx_rc_t 101 medford_board_cfg( 102 __in efx_nic_t *enp) 103 { 104 efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); 105 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); 106 uint8_t mac_addr[6] = { 0 }; 107 uint32_t board_type = 0; 108 ef10_link_state_t els; 109 efx_port_t *epp = &(enp->en_port); 110 uint32_t port; 111 uint32_t pf; 112 uint32_t vf; 113 uint32_t mask; 114 uint32_t flags; 115 uint32_t sysclk; 116 uint32_t base, nvec; 117 uint32_t end_padding; 118 efx_rc_t rc; 119 120 /* 121 * FIXME: Likely to be incomplete and incorrect. 122 * Parts of this should be shared with Huntington. 123 */ 124 125 if ((rc = efx_mcdi_get_port_assignment(enp, &port)) != 0) 126 goto fail1; 127 128 /* 129 * NOTE: The MCDI protocol numbers ports from zero. 130 * The common code MCDI interface numbers ports from one. 131 */ 132 emip->emi_port = port + 1; 133 134 if ((rc = ef10_external_port_mapping(enp, port, 135 &encp->enc_external_port)) != 0) 136 goto fail2; 137 138 /* 139 * Get PCIe function number from firmware (used for 140 * per-function privilege and dynamic config info). 141 * - PCIe PF: pf = PF number, vf = 0xffff. 142 * - PCIe VF: pf = parent PF, vf = VF number. 143 */ 144 if ((rc = efx_mcdi_get_function_info(enp, &pf, &vf)) != 0) 145 goto fail3; 146 147 encp->enc_pf = pf; 148 encp->enc_vf = vf; 149 150 /* MAC address for this function */ 151 if (EFX_PCI_FUNCTION_IS_PF(encp)) { 152 rc = efx_mcdi_get_mac_address_pf(enp, mac_addr); 153 if ((rc == 0) && (mac_addr[0] & 0x02)) { 154 /* 155 * If the static config does not include a global MAC 156 * address pool then the board may return a locally 157 * administered MAC address (this should only happen on 158 * incorrectly programmed boards). 159 */ 160 rc = EINVAL; 161 } 162 } else { 163 rc = efx_mcdi_get_mac_address_vf(enp, mac_addr); 164 } 165 if (rc != 0) 166 goto fail4; 167 168 EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr); 169 170 /* Board configuration */ 171 rc = efx_mcdi_get_board_cfg(enp, &board_type, NULL, NULL); 172 if (rc != 0) { 173 /* Unprivileged functions may not be able to read board cfg */ 174 if (rc == EACCES) 175 board_type = 0; 176 else 177 goto fail5; 178 } 179 180 encp->enc_board_type = board_type; 181 encp->enc_clk_mult = 1; /* not used for Medford */ 182 183 /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */ 184 if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0) 185 goto fail6; 186 187 /* Obtain the default PHY advertised capabilities */ 188 if ((rc = ef10_phy_get_link(enp, &els)) != 0) 189 goto fail7; 190 epp->ep_default_adv_cap_mask = els.els_adv_cap_mask; 191 epp->ep_adv_cap_mask = els.els_adv_cap_mask; 192 193 if (EFX_PCI_FUNCTION_IS_VF(encp)) { 194 /* 195 * Interrupt testing does not work for VFs. See bug50084. 196 * FIXME: Does this still apply to Medford? 197 */ 198 encp->enc_bug41750_workaround = B_TRUE; 199 } 200 201 /* Chained multicast is always enabled on Medford */ 202 encp->enc_bug26807_workaround = B_TRUE; 203 204 /* Get sysclk frequency (in MHz). */ 205 if ((rc = efx_mcdi_get_clock(enp, &sysclk)) != 0) 206 goto fail8; 207 208 /* 209 * The timer quantum is 1536 sysclk cycles, documented for the 210 * EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units. 211 */ 212 encp->enc_evq_timer_quantum_ns = 1536000UL / sysclk; /* 1536 cycles */ 213 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns << 214 FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000; 215 216 /* Check capabilities of running datapath firmware */ 217 if ((rc = ef10_get_datapath_caps(enp)) != 0) 218 goto fail9; 219 220 /* Alignment for receive packet DMA buffers */ 221 encp->enc_rx_buf_align_start = 1; 222 223 /* Get the RX DMA end padding alignment configuration */ 224 if ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0) 225 goto fail10; 226 encp->enc_rx_buf_align_end = end_padding; 227 228 /* Alignment for WPTR updates */ 229 encp->enc_rx_push_align = EF10_RX_WPTR_ALIGN; 230 231 /* 232 * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use 233 * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available 234 * resources (allocated to this PCIe function), which is zero until 235 * after we have allocated VIs. 236 */ 237 encp->enc_evq_limit = 1024; 238 encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET; 239 encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET; 240 241 encp->enc_buftbl_limit = 0xFFFFFFFF; 242 243 encp->enc_piobuf_limit = MEDFORD_PIOBUF_NBUFS; 244 encp->enc_piobuf_size = MEDFORD_PIOBUF_SIZE; 245 encp->enc_piobuf_min_alloc_size = MEDFORD_MIN_PIO_ALLOC_SIZE; 246 247 /* 248 * Get the current privilege mask. Note that this may be modified 249 * dynamically, so this value is informational only. DO NOT use 250 * the privilege mask to check for sufficient privileges, as that 251 * can result in time-of-check/time-of-use bugs. 252 */ 253 if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0) 254 goto fail11; 255 encp->enc_privilege_mask = mask; 256 257 /* Get interrupt vector limits */ 258 if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) { 259 if (EFX_PCI_FUNCTION_IS_PF(encp)) 260 goto fail12; 261 262 /* Ignore error (cannot query vector limits from a VF). */ 263 base = 0; 264 nvec = 1024; 265 } 266 encp->enc_intr_vec_base = base; 267 encp->enc_intr_limit = nvec; 268 269 /* 270 * Maximum number of bytes into the frame the TCP header can start for 271 * firmware assisted TSO to work. 272 */ 273 encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT; 274 275 /* 276 * Medford stores a single global copy of VPD, not per-PF as on 277 * Huntington. 278 */ 279 encp->enc_vpd_is_global = B_TRUE; 280 281 return (0); 282 283 fail12: 284 EFSYS_PROBE(fail12); 285 fail11: 286 EFSYS_PROBE(fail11); 287 fail10: 288 EFSYS_PROBE(fail10); 289 fail9: 290 EFSYS_PROBE(fail9); 291 fail8: 292 EFSYS_PROBE(fail8); 293 fail7: 294 EFSYS_PROBE(fail7); 295 fail6: 296 EFSYS_PROBE(fail6); 297 fail5: 298 EFSYS_PROBE(fail5); 299 fail4: 300 EFSYS_PROBE(fail4); 301 fail3: 302 EFSYS_PROBE(fail3); 303 fail2: 304 EFSYS_PROBE(fail2); 305 fail1: 306 EFSYS_PROBE1(fail1, efx_rc_t, rc); 307 308 return (rc); 309 } 310 311 #endif /* EFSYS_OPT_MEDFORD */ 312