1 /*- 2 * Copyright (c) 2015-2016 Solarflare Communications Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * The views and conclusions contained in the software and documentation are 27 * those of the authors and should not be interpreted as representing official 28 * policies, either expressed or implied, of the FreeBSD Project. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include "efx.h" 35 #include "efx_impl.h" 36 37 38 #if EFSYS_OPT_MEDFORD 39 40 static __checkReturn efx_rc_t 41 efx_mcdi_get_rxdp_config( 42 __in efx_nic_t *enp, 43 __out uint32_t *end_paddingp) 44 { 45 efx_mcdi_req_t req; 46 uint8_t payload[MAX(MC_CMD_GET_RXDP_CONFIG_IN_LEN, 47 MC_CMD_GET_RXDP_CONFIG_OUT_LEN)]; 48 uint32_t end_padding; 49 efx_rc_t rc; 50 51 memset(payload, 0, sizeof (payload)); 52 req.emr_cmd = MC_CMD_GET_RXDP_CONFIG; 53 req.emr_in_buf = payload; 54 req.emr_in_length = MC_CMD_GET_RXDP_CONFIG_IN_LEN; 55 req.emr_out_buf = payload; 56 req.emr_out_length = MC_CMD_GET_RXDP_CONFIG_OUT_LEN; 57 58 efx_mcdi_execute(enp, &req); 59 if (req.emr_rc != 0) { 60 rc = req.emr_rc; 61 goto fail1; 62 } 63 64 if (MCDI_OUT_DWORD_FIELD(req, GET_RXDP_CONFIG_OUT_DATA, 65 GET_RXDP_CONFIG_OUT_PAD_HOST_DMA) == 0) { 66 /* RX DMA end padding is disabled */ 67 end_padding = 0; 68 } else { 69 switch (MCDI_OUT_DWORD_FIELD(req, GET_RXDP_CONFIG_OUT_DATA, 70 GET_RXDP_CONFIG_OUT_PAD_HOST_LEN)) { 71 case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_64: 72 end_padding = 64; 73 break; 74 case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_128: 75 end_padding = 128; 76 break; 77 case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_256: 78 end_padding = 256; 79 break; 80 default: 81 rc = ENOTSUP; 82 goto fail2; 83 } 84 } 85 86 *end_paddingp = end_padding; 87 88 return (0); 89 90 fail2: 91 EFSYS_PROBE(fail2); 92 fail1: 93 EFSYS_PROBE1(fail1, efx_rc_t, rc); 94 95 return (rc); 96 } 97 98 static __checkReturn efx_rc_t 99 medford_nic_get_required_pcie_bandwidth( 100 __in efx_nic_t *enp, 101 __out uint32_t *bandwidth_mbpsp) 102 { 103 uint32_t port_modes; 104 uint32_t current_mode; 105 uint32_t bandwidth; 106 efx_rc_t rc; 107 108 if ((rc = efx_mcdi_get_port_modes(enp, &port_modes, 109 ¤t_mode)) != 0) { 110 /* No port mode info available. */ 111 bandwidth = 0; 112 goto out; 113 } 114 115 if ((rc = ef10_nic_get_port_mode_bandwidth(current_mode, 116 &bandwidth)) != 0) 117 goto fail1; 118 119 out: 120 *bandwidth_mbpsp = bandwidth; 121 122 return (0); 123 124 fail1: 125 EFSYS_PROBE1(fail1, efx_rc_t, rc); 126 127 return (rc); 128 } 129 130 __checkReturn efx_rc_t 131 medford_board_cfg( 132 __in efx_nic_t *enp) 133 { 134 efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); 135 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); 136 uint8_t mac_addr[6] = { 0 }; 137 uint32_t board_type = 0; 138 ef10_link_state_t els; 139 efx_port_t *epp = &(enp->en_port); 140 uint32_t port; 141 uint32_t pf; 142 uint32_t vf; 143 uint32_t mask; 144 uint32_t sysclk, dpcpu_clk; 145 uint32_t base, nvec; 146 uint32_t end_padding; 147 uint32_t bandwidth; 148 efx_rc_t rc; 149 150 /* 151 * FIXME: Likely to be incomplete and incorrect. 152 * Parts of this should be shared with Huntington. 153 */ 154 155 if ((rc = efx_mcdi_get_port_assignment(enp, &port)) != 0) 156 goto fail1; 157 158 /* 159 * NOTE: The MCDI protocol numbers ports from zero. 160 * The common code MCDI interface numbers ports from one. 161 */ 162 emip->emi_port = port + 1; 163 164 if ((rc = ef10_external_port_mapping(enp, port, 165 &encp->enc_external_port)) != 0) 166 goto fail2; 167 168 /* 169 * Get PCIe function number from firmware (used for 170 * per-function privilege and dynamic config info). 171 * - PCIe PF: pf = PF number, vf = 0xffff. 172 * - PCIe VF: pf = parent PF, vf = VF number. 173 */ 174 if ((rc = efx_mcdi_get_function_info(enp, &pf, &vf)) != 0) 175 goto fail3; 176 177 encp->enc_pf = pf; 178 encp->enc_vf = vf; 179 180 /* MAC address for this function */ 181 if (EFX_PCI_FUNCTION_IS_PF(encp)) { 182 rc = efx_mcdi_get_mac_address_pf(enp, mac_addr); 183 #if EFSYS_OPT_ALLOW_UNCONFIGURED_NIC 184 /* Disable static config checking for Medford NICs, ONLY 185 * for manufacturing test and setup at the factory, to 186 * allow the static config to be installed. 187 */ 188 #else /* EFSYS_OPT_ALLOW_UNCONFIGURED_NIC */ 189 if ((rc == 0) && (mac_addr[0] & 0x02)) { 190 /* 191 * If the static config does not include a global MAC 192 * address pool then the board may return a locally 193 * administered MAC address (this should only happen on 194 * incorrectly programmed boards). 195 */ 196 rc = EINVAL; 197 } 198 #endif /* EFSYS_OPT_ALLOW_UNCONFIGURED_NIC */ 199 } else { 200 rc = efx_mcdi_get_mac_address_vf(enp, mac_addr); 201 } 202 if (rc != 0) 203 goto fail4; 204 205 EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr); 206 207 /* Board configuration */ 208 rc = efx_mcdi_get_board_cfg(enp, &board_type, NULL, NULL); 209 if (rc != 0) { 210 /* Unprivileged functions may not be able to read board cfg */ 211 if (rc == EACCES) 212 board_type = 0; 213 else 214 goto fail5; 215 } 216 217 encp->enc_board_type = board_type; 218 encp->enc_clk_mult = 1; /* not used for Medford */ 219 220 /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */ 221 if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0) 222 goto fail6; 223 224 /* Obtain the default PHY advertised capabilities */ 225 if ((rc = ef10_phy_get_link(enp, &els)) != 0) 226 goto fail7; 227 epp->ep_default_adv_cap_mask = els.els_adv_cap_mask; 228 epp->ep_adv_cap_mask = els.els_adv_cap_mask; 229 230 /* 231 * Enable firmware workarounds for hardware errata. 232 * Expected responses are: 233 * - 0 (zero): 234 * Success: workaround enabled or disabled as requested. 235 * - MC_CMD_ERR_ENOSYS (reported as ENOTSUP): 236 * Firmware does not support the MC_CMD_WORKAROUND request. 237 * (assume that the workaround is not supported). 238 * - MC_CMD_ERR_ENOENT (reported as ENOENT): 239 * Firmware does not support the requested workaround. 240 * - MC_CMD_ERR_EPERM (reported as EACCES): 241 * Unprivileged function cannot enable/disable workarounds. 242 * 243 * See efx_mcdi_request_errcode() for MCDI error translations. 244 */ 245 246 247 if (EFX_PCI_FUNCTION_IS_VF(encp)) { 248 /* 249 * Interrupt testing does not work for VFs. See bug50084. 250 * FIXME: Does this still apply to Medford? 251 */ 252 encp->enc_bug41750_workaround = B_TRUE; 253 } 254 255 /* Chained multicast is always enabled on Medford */ 256 encp->enc_bug26807_workaround = B_TRUE; 257 258 /* 259 * If the bug61265 workaround is enabled, then interrupt holdoff timers 260 * cannot be controlled by timer table writes, so MCDI must be used 261 * (timer table writes can still be used for wakeup timers). 262 */ 263 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG61265, B_TRUE, 264 NULL); 265 if ((rc == 0) || (rc == EACCES)) 266 encp->enc_bug61265_workaround = B_TRUE; 267 else if ((rc == ENOTSUP) || (rc == ENOENT)) 268 encp->enc_bug61265_workaround = B_FALSE; 269 else 270 goto fail8; 271 272 /* Get clock frequencies (in MHz). */ 273 if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0) 274 goto fail9; 275 276 /* 277 * The Medford timer quantum is 1536 dpcpu_clk cycles, documented for 278 * the EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units. 279 */ 280 encp->enc_evq_timer_quantum_ns = 1536000UL / dpcpu_clk; /* 1536 cycles */ 281 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns << 282 FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000; 283 284 /* Check capabilities of running datapath firmware */ 285 if ((rc = ef10_get_datapath_caps(enp)) != 0) 286 goto fail10; 287 288 /* Alignment for receive packet DMA buffers */ 289 encp->enc_rx_buf_align_start = 1; 290 291 /* Get the RX DMA end padding alignment configuration */ 292 if ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0) { 293 if (rc != EACCES) 294 goto fail11; 295 296 /* Assume largest tail padding size supported by hardware */ 297 end_padding = 256; 298 } 299 encp->enc_rx_buf_align_end = end_padding; 300 301 /* Alignment for WPTR updates */ 302 encp->enc_rx_push_align = EF10_RX_WPTR_ALIGN; 303 304 encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT); 305 /* No boundary crossing limits */ 306 encp->enc_tx_dma_desc_boundary = 0; 307 308 /* 309 * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use 310 * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available 311 * resources (allocated to this PCIe function), which is zero until 312 * after we have allocated VIs. 313 */ 314 encp->enc_evq_limit = 1024; 315 encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET; 316 encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET; 317 318 encp->enc_buftbl_limit = 0xFFFFFFFF; 319 320 encp->enc_piobuf_limit = MEDFORD_PIOBUF_NBUFS; 321 encp->enc_piobuf_size = MEDFORD_PIOBUF_SIZE; 322 encp->enc_piobuf_min_alloc_size = MEDFORD_MIN_PIO_ALLOC_SIZE; 323 324 /* 325 * Get the current privilege mask. Note that this may be modified 326 * dynamically, so this value is informational only. DO NOT use 327 * the privilege mask to check for sufficient privileges, as that 328 * can result in time-of-check/time-of-use bugs. 329 */ 330 if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0) 331 goto fail12; 332 encp->enc_privilege_mask = mask; 333 334 /* Get interrupt vector limits */ 335 if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) { 336 if (EFX_PCI_FUNCTION_IS_PF(encp)) 337 goto fail13; 338 339 /* Ignore error (cannot query vector limits from a VF). */ 340 base = 0; 341 nvec = 1024; 342 } 343 encp->enc_intr_vec_base = base; 344 encp->enc_intr_limit = nvec; 345 346 /* 347 * Maximum number of bytes into the frame the TCP header can start for 348 * firmware assisted TSO to work. 349 */ 350 encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT; 351 352 /* 353 * Medford stores a single global copy of VPD, not per-PF as on 354 * Huntington. 355 */ 356 encp->enc_vpd_is_global = B_TRUE; 357 358 rc = medford_nic_get_required_pcie_bandwidth(enp, &bandwidth); 359 if (rc != 0) 360 goto fail14; 361 encp->enc_required_pcie_bandwidth_mbps = bandwidth; 362 encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3; 363 364 return (0); 365 366 fail14: 367 EFSYS_PROBE(fail14); 368 fail13: 369 EFSYS_PROBE(fail13); 370 fail12: 371 EFSYS_PROBE(fail12); 372 fail11: 373 EFSYS_PROBE(fail11); 374 fail10: 375 EFSYS_PROBE(fail10); 376 fail9: 377 EFSYS_PROBE(fail9); 378 fail8: 379 EFSYS_PROBE(fail8); 380 fail7: 381 EFSYS_PROBE(fail7); 382 fail6: 383 EFSYS_PROBE(fail6); 384 fail5: 385 EFSYS_PROBE(fail5); 386 fail4: 387 EFSYS_PROBE(fail4); 388 fail3: 389 EFSYS_PROBE(fail3); 390 fail2: 391 EFSYS_PROBE(fail2); 392 fail1: 393 EFSYS_PROBE1(fail1, efx_rc_t, rc); 394 395 return (rc); 396 } 397 398 #endif /* EFSYS_OPT_MEDFORD */ 399