1 /*- 2 * Copyright (c) 2015 Solarflare Communications Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * The views and conclusions contained in the software and documentation are 27 * those of the authors and should not be interpreted as representing official 28 * policies, either expressed or implied, of the FreeBSD Project. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include "efx.h" 35 #include "efx_impl.h" 36 37 38 #if EFSYS_OPT_MEDFORD 39 40 static __checkReturn efx_rc_t 41 efx_mcdi_get_rxdp_config( 42 __in efx_nic_t *enp, 43 __out uint32_t *end_paddingp) 44 { 45 efx_mcdi_req_t req; 46 uint8_t payload[MAX(MC_CMD_GET_RXDP_CONFIG_IN_LEN, 47 MC_CMD_GET_RXDP_CONFIG_OUT_LEN)]; 48 uint32_t end_padding; 49 efx_rc_t rc; 50 51 memset(payload, 0, sizeof (payload)); 52 req.emr_cmd = MC_CMD_GET_RXDP_CONFIG; 53 req.emr_in_buf = payload; 54 req.emr_in_length = MC_CMD_GET_RXDP_CONFIG_IN_LEN; 55 req.emr_out_buf = payload; 56 req.emr_out_length = MC_CMD_GET_RXDP_CONFIG_OUT_LEN; 57 58 efx_mcdi_execute(enp, &req); 59 if (req.emr_rc != 0) { 60 rc = req.emr_rc; 61 goto fail1; 62 } 63 64 if (MCDI_OUT_DWORD_FIELD(req, GET_RXDP_CONFIG_OUT_DATA, 65 GET_RXDP_CONFIG_OUT_PAD_HOST_DMA) == 0) { 66 /* RX DMA end padding is disabled */ 67 end_padding = 0; 68 } else { 69 switch(MCDI_OUT_DWORD_FIELD(req, GET_RXDP_CONFIG_OUT_DATA, 70 GET_RXDP_CONFIG_OUT_PAD_HOST_LEN)) { 71 case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_64: 72 end_padding = 64; 73 break; 74 case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_128: 75 end_padding = 128; 76 break; 77 case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_256: 78 end_padding = 256; 79 break; 80 default: 81 rc = ENOTSUP; 82 goto fail2; 83 } 84 } 85 86 *end_paddingp = end_padding; 87 88 return (0); 89 90 fail2: 91 EFSYS_PROBE(fail2); 92 fail1: 93 EFSYS_PROBE1(fail1, efx_rc_t, rc); 94 95 return (rc); 96 } 97 98 __checkReturn efx_rc_t 99 medford_board_cfg( 100 __in efx_nic_t *enp) 101 { 102 efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); 103 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); 104 uint8_t mac_addr[6] = { 0 }; 105 uint32_t board_type = 0; 106 ef10_link_state_t els; 107 efx_port_t *epp = &(enp->en_port); 108 uint32_t port; 109 uint32_t pf; 110 uint32_t vf; 111 uint32_t mask; 112 uint32_t sysclk; 113 uint32_t base, nvec; 114 uint32_t end_padding; 115 efx_rc_t rc; 116 117 /* 118 * FIXME: Likely to be incomplete and incorrect. 119 * Parts of this should be shared with Huntington. 120 */ 121 122 if ((rc = efx_mcdi_get_port_assignment(enp, &port)) != 0) 123 goto fail1; 124 125 /* 126 * NOTE: The MCDI protocol numbers ports from zero. 127 * The common code MCDI interface numbers ports from one. 128 */ 129 emip->emi_port = port + 1; 130 131 if ((rc = ef10_external_port_mapping(enp, port, 132 &encp->enc_external_port)) != 0) 133 goto fail2; 134 135 /* 136 * Get PCIe function number from firmware (used for 137 * per-function privilege and dynamic config info). 138 * - PCIe PF: pf = PF number, vf = 0xffff. 139 * - PCIe VF: pf = parent PF, vf = VF number. 140 */ 141 if ((rc = efx_mcdi_get_function_info(enp, &pf, &vf)) != 0) 142 goto fail3; 143 144 encp->enc_pf = pf; 145 encp->enc_vf = vf; 146 147 /* MAC address for this function */ 148 if (EFX_PCI_FUNCTION_IS_PF(encp)) { 149 rc = efx_mcdi_get_mac_address_pf(enp, mac_addr); 150 if ((rc == 0) && (mac_addr[0] & 0x02)) { 151 /* 152 * If the static config does not include a global MAC 153 * address pool then the board may return a locally 154 * administered MAC address (this should only happen on 155 * incorrectly programmed boards). 156 */ 157 rc = EINVAL; 158 } 159 } else { 160 rc = efx_mcdi_get_mac_address_vf(enp, mac_addr); 161 } 162 if (rc != 0) 163 goto fail4; 164 165 EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr); 166 167 /* Board configuration */ 168 rc = efx_mcdi_get_board_cfg(enp, &board_type, NULL, NULL); 169 if (rc != 0) { 170 /* Unprivileged functions may not be able to read board cfg */ 171 if (rc == EACCES) 172 board_type = 0; 173 else 174 goto fail5; 175 } 176 177 encp->enc_board_type = board_type; 178 encp->enc_clk_mult = 1; /* not used for Medford */ 179 180 /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */ 181 if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0) 182 goto fail6; 183 184 /* Obtain the default PHY advertised capabilities */ 185 if ((rc = ef10_phy_get_link(enp, &els)) != 0) 186 goto fail7; 187 epp->ep_default_adv_cap_mask = els.els_adv_cap_mask; 188 epp->ep_adv_cap_mask = els.els_adv_cap_mask; 189 190 if (EFX_PCI_FUNCTION_IS_VF(encp)) { 191 /* 192 * Interrupt testing does not work for VFs. See bug50084. 193 * FIXME: Does this still apply to Medford? 194 */ 195 encp->enc_bug41750_workaround = B_TRUE; 196 } 197 198 /* Chained multicast is always enabled on Medford */ 199 encp->enc_bug26807_workaround = B_TRUE; 200 201 /* Get sysclk frequency (in MHz). */ 202 if ((rc = efx_mcdi_get_clock(enp, &sysclk)) != 0) 203 goto fail8; 204 205 /* 206 * The timer quantum is 1536 sysclk cycles, documented for the 207 * EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units. 208 */ 209 encp->enc_evq_timer_quantum_ns = 1536000UL / sysclk; /* 1536 cycles */ 210 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns << 211 FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000; 212 213 /* Check capabilities of running datapath firmware */ 214 if ((rc = ef10_get_datapath_caps(enp)) != 0) 215 goto fail9; 216 217 /* Alignment for receive packet DMA buffers */ 218 encp->enc_rx_buf_align_start = 1; 219 220 /* Get the RX DMA end padding alignment configuration */ 221 if ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0) 222 goto fail10; 223 encp->enc_rx_buf_align_end = end_padding; 224 225 /* Alignment for WPTR updates */ 226 encp->enc_rx_push_align = EF10_RX_WPTR_ALIGN; 227 228 /* 229 * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use 230 * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available 231 * resources (allocated to this PCIe function), which is zero until 232 * after we have allocated VIs. 233 */ 234 encp->enc_evq_limit = 1024; 235 encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET; 236 encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET; 237 238 encp->enc_buftbl_limit = 0xFFFFFFFF; 239 240 encp->enc_piobuf_limit = MEDFORD_PIOBUF_NBUFS; 241 encp->enc_piobuf_size = MEDFORD_PIOBUF_SIZE; 242 encp->enc_piobuf_min_alloc_size = MEDFORD_MIN_PIO_ALLOC_SIZE; 243 244 /* 245 * Get the current privilege mask. Note that this may be modified 246 * dynamically, so this value is informational only. DO NOT use 247 * the privilege mask to check for sufficient privileges, as that 248 * can result in time-of-check/time-of-use bugs. 249 */ 250 if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0) 251 goto fail11; 252 encp->enc_privilege_mask = mask; 253 254 /* Get interrupt vector limits */ 255 if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) { 256 if (EFX_PCI_FUNCTION_IS_PF(encp)) 257 goto fail12; 258 259 /* Ignore error (cannot query vector limits from a VF). */ 260 base = 0; 261 nvec = 1024; 262 } 263 encp->enc_intr_vec_base = base; 264 encp->enc_intr_limit = nvec; 265 266 /* 267 * Maximum number of bytes into the frame the TCP header can start for 268 * firmware assisted TSO to work. 269 */ 270 encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT; 271 272 /* 273 * Medford stores a single global copy of VPD, not per-PF as on 274 * Huntington. 275 */ 276 encp->enc_vpd_is_global = B_TRUE; 277 278 return (0); 279 280 fail12: 281 EFSYS_PROBE(fail12); 282 fail11: 283 EFSYS_PROBE(fail11); 284 fail10: 285 EFSYS_PROBE(fail10); 286 fail9: 287 EFSYS_PROBE(fail9); 288 fail8: 289 EFSYS_PROBE(fail8); 290 fail7: 291 EFSYS_PROBE(fail7); 292 fail6: 293 EFSYS_PROBE(fail6); 294 fail5: 295 EFSYS_PROBE(fail5); 296 fail4: 297 EFSYS_PROBE(fail4); 298 fail3: 299 EFSYS_PROBE(fail3); 300 fail2: 301 EFSYS_PROBE(fail2); 302 fail1: 303 EFSYS_PROBE1(fail1, efx_rc_t, rc); 304 305 return (rc); 306 } 307 308 #endif /* EFSYS_OPT_MEDFORD */ 309