xref: /freebsd/sys/dev/sfxge/common/medford_nic.c (revision dcb49ebadec85516898a40df770073fd83ebf978)
15f5c71ccSAndrew Rybchenko /*-
25f5c71ccSAndrew Rybchenko  * Copyright (c) 2015 Solarflare Communications Inc.
35f5c71ccSAndrew Rybchenko  * All rights reserved.
45f5c71ccSAndrew Rybchenko  *
55f5c71ccSAndrew Rybchenko  * Redistribution and use in source and binary forms, with or without
65f5c71ccSAndrew Rybchenko  * modification, are permitted provided that the following conditions are met:
75f5c71ccSAndrew Rybchenko  *
85f5c71ccSAndrew Rybchenko  * 1. Redistributions of source code must retain the above copyright notice,
95f5c71ccSAndrew Rybchenko  *    this list of conditions and the following disclaimer.
105f5c71ccSAndrew Rybchenko  * 2. Redistributions in binary form must reproduce the above copyright notice,
115f5c71ccSAndrew Rybchenko  *    this list of conditions and the following disclaimer in the documentation
125f5c71ccSAndrew Rybchenko  *    and/or other materials provided with the distribution.
135f5c71ccSAndrew Rybchenko  *
145f5c71ccSAndrew Rybchenko  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
155f5c71ccSAndrew Rybchenko  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
165f5c71ccSAndrew Rybchenko  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
175f5c71ccSAndrew Rybchenko  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
185f5c71ccSAndrew Rybchenko  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
195f5c71ccSAndrew Rybchenko  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
205f5c71ccSAndrew Rybchenko  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
215f5c71ccSAndrew Rybchenko  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
225f5c71ccSAndrew Rybchenko  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
235f5c71ccSAndrew Rybchenko  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
245f5c71ccSAndrew Rybchenko  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
255f5c71ccSAndrew Rybchenko  *
265f5c71ccSAndrew Rybchenko  * The views and conclusions contained in the software and documentation are
275f5c71ccSAndrew Rybchenko  * those of the authors and should not be interpreted as representing official
285f5c71ccSAndrew Rybchenko  * policies, either expressed or implied, of the FreeBSD Project.
295f5c71ccSAndrew Rybchenko  */
305f5c71ccSAndrew Rybchenko 
315f5c71ccSAndrew Rybchenko #include <sys/cdefs.h>
325f5c71ccSAndrew Rybchenko __FBSDID("$FreeBSD$");
335f5c71ccSAndrew Rybchenko 
345f5c71ccSAndrew Rybchenko #include "efx.h"
355f5c71ccSAndrew Rybchenko #include "efx_impl.h"
36*dcb49ebaSAndrew Rybchenko 
375f5c71ccSAndrew Rybchenko 
385f5c71ccSAndrew Rybchenko #if EFSYS_OPT_MEDFORD
395f5c71ccSAndrew Rybchenko 
406de7c598SAndrew Rybchenko static	__checkReturn	efx_rc_t
416de7c598SAndrew Rybchenko efx_mcdi_get_rxdp_config(
426de7c598SAndrew Rybchenko 	__in		efx_nic_t *enp,
436de7c598SAndrew Rybchenko 	__out		uint32_t *end_paddingp)
446de7c598SAndrew Rybchenko {
456de7c598SAndrew Rybchenko 	efx_mcdi_req_t req;
466de7c598SAndrew Rybchenko 	uint8_t payload[MAX(MC_CMD_GET_RXDP_CONFIG_IN_LEN,
476de7c598SAndrew Rybchenko 			    MC_CMD_GET_RXDP_CONFIG_OUT_LEN)];
486de7c598SAndrew Rybchenko 	uint32_t end_padding;
496de7c598SAndrew Rybchenko 	efx_rc_t rc;
506de7c598SAndrew Rybchenko 
516de7c598SAndrew Rybchenko 	memset(payload, 0, sizeof (payload));
526de7c598SAndrew Rybchenko 	req.emr_cmd = MC_CMD_GET_RXDP_CONFIG;
536de7c598SAndrew Rybchenko 	req.emr_in_buf = payload;
546de7c598SAndrew Rybchenko 	req.emr_in_length = MC_CMD_GET_RXDP_CONFIG_IN_LEN;
556de7c598SAndrew Rybchenko 	req.emr_out_buf = payload;
566de7c598SAndrew Rybchenko 	req.emr_out_length = MC_CMD_GET_RXDP_CONFIG_OUT_LEN;
576de7c598SAndrew Rybchenko 
586de7c598SAndrew Rybchenko 	efx_mcdi_execute(enp, &req);
596de7c598SAndrew Rybchenko 	if (req.emr_rc != 0) {
606de7c598SAndrew Rybchenko 		rc = req.emr_rc;
616de7c598SAndrew Rybchenko 		goto fail1;
626de7c598SAndrew Rybchenko 	}
636de7c598SAndrew Rybchenko 
646de7c598SAndrew Rybchenko 	if (MCDI_OUT_DWORD_FIELD(req, GET_RXDP_CONFIG_OUT_DATA,
656de7c598SAndrew Rybchenko 				    GET_RXDP_CONFIG_OUT_PAD_HOST_DMA) == 0) {
666de7c598SAndrew Rybchenko 		/* RX DMA end padding is disabled */
676de7c598SAndrew Rybchenko 		end_padding = 0;
686de7c598SAndrew Rybchenko 	} else {
696de7c598SAndrew Rybchenko 		switch(MCDI_OUT_DWORD_FIELD(req, GET_RXDP_CONFIG_OUT_DATA,
706de7c598SAndrew Rybchenko 					    GET_RXDP_CONFIG_OUT_PAD_HOST_LEN)) {
716de7c598SAndrew Rybchenko 		case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_64:
726de7c598SAndrew Rybchenko 			end_padding = 64;
736de7c598SAndrew Rybchenko 			break;
746de7c598SAndrew Rybchenko 		case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_128:
756de7c598SAndrew Rybchenko 			end_padding = 128;
766de7c598SAndrew Rybchenko 			break;
776de7c598SAndrew Rybchenko 		case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_256:
786de7c598SAndrew Rybchenko 			end_padding = 256;
796de7c598SAndrew Rybchenko 			break;
806de7c598SAndrew Rybchenko 		default:
816de7c598SAndrew Rybchenko 			rc = ENOTSUP;
826de7c598SAndrew Rybchenko 			goto fail2;
836de7c598SAndrew Rybchenko 		}
846de7c598SAndrew Rybchenko 	}
856de7c598SAndrew Rybchenko 
866de7c598SAndrew Rybchenko 	*end_paddingp = end_padding;
876de7c598SAndrew Rybchenko 
886de7c598SAndrew Rybchenko 	return (0);
896de7c598SAndrew Rybchenko 
906de7c598SAndrew Rybchenko fail2:
916de7c598SAndrew Rybchenko 	EFSYS_PROBE(fail2);
926de7c598SAndrew Rybchenko fail1:
936de7c598SAndrew Rybchenko 	EFSYS_PROBE1(fail1, efx_rc_t, rc);
946de7c598SAndrew Rybchenko 
956de7c598SAndrew Rybchenko 	return (rc);
966de7c598SAndrew Rybchenko }
976de7c598SAndrew Rybchenko 
98cfa023ebSAndrew Rybchenko 	__checkReturn	efx_rc_t
99cfa023ebSAndrew Rybchenko medford_board_cfg(
100cfa023ebSAndrew Rybchenko 	__in		efx_nic_t *enp)
101cfa023ebSAndrew Rybchenko {
102cfa023ebSAndrew Rybchenko 	efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
103cfa023ebSAndrew Rybchenko 	efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
104cfa023ebSAndrew Rybchenko 	uint8_t mac_addr[6] = { 0 };
105cfa023ebSAndrew Rybchenko 	uint32_t board_type = 0;
106177347ddSAndrew Rybchenko 	ef10_link_state_t els;
107cfa023ebSAndrew Rybchenko 	efx_port_t *epp = &(enp->en_port);
108cfa023ebSAndrew Rybchenko 	uint32_t port;
109cfa023ebSAndrew Rybchenko 	uint32_t pf;
110cfa023ebSAndrew Rybchenko 	uint32_t vf;
111cfa023ebSAndrew Rybchenko 	uint32_t mask;
112cfa023ebSAndrew Rybchenko 	uint32_t flags;
113cfa023ebSAndrew Rybchenko 	uint32_t sysclk;
114cfa023ebSAndrew Rybchenko 	uint32_t base, nvec;
1156de7c598SAndrew Rybchenko 	uint32_t end_padding;
116cfa023ebSAndrew Rybchenko 	efx_rc_t rc;
1175f5c71ccSAndrew Rybchenko 
118cfa023ebSAndrew Rybchenko 	/*
119cfa023ebSAndrew Rybchenko 	 * FIXME: Likely to be incomplete and incorrect.
120cfa023ebSAndrew Rybchenko 	 * Parts of this should be shared with Huntington.
121cfa023ebSAndrew Rybchenko 	 */
1225f5c71ccSAndrew Rybchenko 
123cfa023ebSAndrew Rybchenko 	if ((rc = efx_mcdi_get_port_assignment(enp, &port)) != 0)
124cfa023ebSAndrew Rybchenko 		goto fail1;
125cfa023ebSAndrew Rybchenko 
126cfa023ebSAndrew Rybchenko 	/*
127cfa023ebSAndrew Rybchenko 	 * NOTE: The MCDI protocol numbers ports from zero.
128cfa023ebSAndrew Rybchenko 	 * The common code MCDI interface numbers ports from one.
129cfa023ebSAndrew Rybchenko 	 */
130cfa023ebSAndrew Rybchenko 	emip->emi_port = port + 1;
131cfa023ebSAndrew Rybchenko 
132cfa023ebSAndrew Rybchenko 	if ((rc = ef10_external_port_mapping(enp, port,
133cfa023ebSAndrew Rybchenko 		    &encp->enc_external_port)) != 0)
134cfa023ebSAndrew Rybchenko 		goto fail2;
135cfa023ebSAndrew Rybchenko 
136cfa023ebSAndrew Rybchenko 	/*
137cfa023ebSAndrew Rybchenko 	 * Get PCIe function number from firmware (used for
138cfa023ebSAndrew Rybchenko 	 * per-function privilege and dynamic config info).
139cfa023ebSAndrew Rybchenko 	 *  - PCIe PF: pf = PF number, vf = 0xffff.
140cfa023ebSAndrew Rybchenko 	 *  - PCIe VF: pf = parent PF, vf = VF number.
141cfa023ebSAndrew Rybchenko 	 */
142cfa023ebSAndrew Rybchenko 	if ((rc = efx_mcdi_get_function_info(enp, &pf, &vf)) != 0)
143cfa023ebSAndrew Rybchenko 		goto fail3;
144cfa023ebSAndrew Rybchenko 
145cfa023ebSAndrew Rybchenko 	encp->enc_pf = pf;
146cfa023ebSAndrew Rybchenko 	encp->enc_vf = vf;
147cfa023ebSAndrew Rybchenko 
148cfa023ebSAndrew Rybchenko 	/* MAC address for this function */
149cfa023ebSAndrew Rybchenko 	if (EFX_PCI_FUNCTION_IS_PF(encp)) {
150cfa023ebSAndrew Rybchenko 		rc = efx_mcdi_get_mac_address_pf(enp, mac_addr);
151cfa023ebSAndrew Rybchenko 		if ((rc == 0) && (mac_addr[0] & 0x02)) {
152cfa023ebSAndrew Rybchenko 			/*
153cfa023ebSAndrew Rybchenko 			 * If the static config does not include a global MAC
154cfa023ebSAndrew Rybchenko 			 * address pool then the board may return a locally
155cfa023ebSAndrew Rybchenko 			 * administered MAC address (this should only happen on
156cfa023ebSAndrew Rybchenko 			 * incorrectly programmed boards).
157cfa023ebSAndrew Rybchenko 			 */
158cfa023ebSAndrew Rybchenko 			rc = EINVAL;
159cfa023ebSAndrew Rybchenko 		}
160cfa023ebSAndrew Rybchenko 	} else {
161cfa023ebSAndrew Rybchenko 		rc = efx_mcdi_get_mac_address_vf(enp, mac_addr);
162cfa023ebSAndrew Rybchenko 	}
163cfa023ebSAndrew Rybchenko 	if (rc != 0)
164cfa023ebSAndrew Rybchenko 		goto fail4;
165cfa023ebSAndrew Rybchenko 
166cfa023ebSAndrew Rybchenko 	EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr);
167cfa023ebSAndrew Rybchenko 
168cfa023ebSAndrew Rybchenko 	/* Board configuration */
169cfa023ebSAndrew Rybchenko 	rc = efx_mcdi_get_board_cfg(enp, &board_type, NULL, NULL);
170cfa023ebSAndrew Rybchenko 	if (rc != 0) {
171cfa023ebSAndrew Rybchenko 		/* Unprivileged functions may not be able to read board cfg */
172cfa023ebSAndrew Rybchenko 		if (rc == EACCES)
173cfa023ebSAndrew Rybchenko 			board_type = 0;
174cfa023ebSAndrew Rybchenko 		else
175cfa023ebSAndrew Rybchenko 			goto fail5;
176cfa023ebSAndrew Rybchenko 	}
177cfa023ebSAndrew Rybchenko 
178cfa023ebSAndrew Rybchenko 	encp->enc_board_type = board_type;
179cfa023ebSAndrew Rybchenko 	encp->enc_clk_mult = 1; /* not used for Medford */
180cfa023ebSAndrew Rybchenko 
181cfa023ebSAndrew Rybchenko 	/* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
182cfa023ebSAndrew Rybchenko 	if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
183cfa023ebSAndrew Rybchenko 		goto fail6;
184cfa023ebSAndrew Rybchenko 
185cfa023ebSAndrew Rybchenko 	/* Obtain the default PHY advertised capabilities */
186ee2812adSAndrew Rybchenko 	if ((rc = ef10_phy_get_link(enp, &els)) != 0)
187cfa023ebSAndrew Rybchenko 		goto fail7;
188177347ddSAndrew Rybchenko 	epp->ep_default_adv_cap_mask = els.els_adv_cap_mask;
189177347ddSAndrew Rybchenko 	epp->ep_adv_cap_mask = els.els_adv_cap_mask;
190cfa023ebSAndrew Rybchenko 
191cfa023ebSAndrew Rybchenko 	if (EFX_PCI_FUNCTION_IS_VF(encp)) {
192cfa023ebSAndrew Rybchenko 		/*
193cfa023ebSAndrew Rybchenko 		 * Interrupt testing does not work for VFs. See bug50084.
194cfa023ebSAndrew Rybchenko 		 * FIXME: Does this still  apply to Medford?
195cfa023ebSAndrew Rybchenko 		 */
196cfa023ebSAndrew Rybchenko 		encp->enc_bug41750_workaround = B_TRUE;
197cfa023ebSAndrew Rybchenko 	}
198cfa023ebSAndrew Rybchenko 
199cfa023ebSAndrew Rybchenko 	/* Chained multicast is always enabled on Medford */
200cfa023ebSAndrew Rybchenko 	encp->enc_bug26807_workaround = B_TRUE;
201cfa023ebSAndrew Rybchenko 
202cfa023ebSAndrew Rybchenko 	/* Get sysclk frequency (in MHz). */
203cfa023ebSAndrew Rybchenko 	if ((rc = efx_mcdi_get_clock(enp, &sysclk)) != 0)
204cfa023ebSAndrew Rybchenko 		goto fail8;
205cfa023ebSAndrew Rybchenko 
206cfa023ebSAndrew Rybchenko 	/*
207cfa023ebSAndrew Rybchenko 	 * The timer quantum is 1536 sysclk cycles, documented for the
208cfa023ebSAndrew Rybchenko 	 * EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units.
209cfa023ebSAndrew Rybchenko 	 */
210cfa023ebSAndrew Rybchenko 	encp->enc_evq_timer_quantum_ns = 1536000UL / sysclk; /* 1536 cycles */
211cfa023ebSAndrew Rybchenko 	encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
212cfa023ebSAndrew Rybchenko 		    FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
213cfa023ebSAndrew Rybchenko 
214cfa023ebSAndrew Rybchenko 	/* Check capabilities of running datapath firmware */
215cfa023ebSAndrew Rybchenko 	if ((rc = ef10_get_datapath_caps(enp)) != 0)
216cfa023ebSAndrew Rybchenko 	    goto fail9;
217cfa023ebSAndrew Rybchenko 
218cfa023ebSAndrew Rybchenko 	/* Alignment for receive packet DMA buffers */
219cfa023ebSAndrew Rybchenko 	encp->enc_rx_buf_align_start = 1;
220cfa023ebSAndrew Rybchenko 
2216de7c598SAndrew Rybchenko 	/* Get the RX DMA end padding alignment configuration */
2226de7c598SAndrew Rybchenko 	if ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0)
2236de7c598SAndrew Rybchenko 		goto fail10;
2246de7c598SAndrew Rybchenko 	encp->enc_rx_buf_align_end = end_padding;
225cfa023ebSAndrew Rybchenko 
226cfa023ebSAndrew Rybchenko 	/* Alignment for WPTR updates */
227cfa023ebSAndrew Rybchenko 	encp->enc_rx_push_align = EF10_RX_WPTR_ALIGN;
228cfa023ebSAndrew Rybchenko 
229cfa023ebSAndrew Rybchenko 	/*
230cfa023ebSAndrew Rybchenko 	 * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
231cfa023ebSAndrew Rybchenko 	 * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available
232cfa023ebSAndrew Rybchenko 	 * resources (allocated to this PCIe function), which is zero until
233cfa023ebSAndrew Rybchenko 	 * after we have allocated VIs.
234cfa023ebSAndrew Rybchenko 	 */
235cfa023ebSAndrew Rybchenko 	encp->enc_evq_limit = 1024;
236cfa023ebSAndrew Rybchenko 	encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET;
237cfa023ebSAndrew Rybchenko 	encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET;
238cfa023ebSAndrew Rybchenko 
239cfa023ebSAndrew Rybchenko 	encp->enc_buftbl_limit = 0xFFFFFFFF;
240cfa023ebSAndrew Rybchenko 
241cfa023ebSAndrew Rybchenko 	encp->enc_piobuf_limit = MEDFORD_PIOBUF_NBUFS;
242cfa023ebSAndrew Rybchenko 	encp->enc_piobuf_size = MEDFORD_PIOBUF_SIZE;
243cfa023ebSAndrew Rybchenko 	encp->enc_piobuf_min_alloc_size = MEDFORD_MIN_PIO_ALLOC_SIZE;
244cfa023ebSAndrew Rybchenko 
245cfa023ebSAndrew Rybchenko 	/*
246cfa023ebSAndrew Rybchenko 	 * Get the current privilege mask. Note that this may be modified
247cfa023ebSAndrew Rybchenko 	 * dynamically, so this value is informational only. DO NOT use
248cfa023ebSAndrew Rybchenko 	 * the privilege mask to check for sufficient privileges, as that
249cfa023ebSAndrew Rybchenko 	 * can result in time-of-check/time-of-use bugs.
250cfa023ebSAndrew Rybchenko 	 */
25180af6f26SAndrew Rybchenko 	if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
2526de7c598SAndrew Rybchenko 		goto fail11;
253cfa023ebSAndrew Rybchenko 	encp->enc_privilege_mask = mask;
254cfa023ebSAndrew Rybchenko 
255cfa023ebSAndrew Rybchenko 	/* Get interrupt vector limits */
256cfa023ebSAndrew Rybchenko 	if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
257cfa023ebSAndrew Rybchenko 		if (EFX_PCI_FUNCTION_IS_PF(encp))
2586de7c598SAndrew Rybchenko 			goto fail12;
259cfa023ebSAndrew Rybchenko 
260cfa023ebSAndrew Rybchenko 		/* Ignore error (cannot query vector limits from a VF). */
261cfa023ebSAndrew Rybchenko 		base = 0;
262cfa023ebSAndrew Rybchenko 		nvec = 1024;
263cfa023ebSAndrew Rybchenko 	}
264cfa023ebSAndrew Rybchenko 	encp->enc_intr_vec_base = base;
265cfa023ebSAndrew Rybchenko 	encp->enc_intr_limit = nvec;
266cfa023ebSAndrew Rybchenko 
267cfa023ebSAndrew Rybchenko 	/*
268cfa023ebSAndrew Rybchenko 	 * Maximum number of bytes into the frame the TCP header can start for
269cfa023ebSAndrew Rybchenko 	 * firmware assisted TSO to work.
270cfa023ebSAndrew Rybchenko 	 */
271cfa023ebSAndrew Rybchenko 	encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;
272cfa023ebSAndrew Rybchenko 
273739ebba6SAndrew Rybchenko 	/*
274739ebba6SAndrew Rybchenko 	 * Medford stores a single global copy of VPD, not per-PF as on
275739ebba6SAndrew Rybchenko 	 * Huntington.
276739ebba6SAndrew Rybchenko 	 */
277739ebba6SAndrew Rybchenko 	encp->enc_vpd_is_global = B_TRUE;
278739ebba6SAndrew Rybchenko 
279cfa023ebSAndrew Rybchenko 	return (0);
280cfa023ebSAndrew Rybchenko 
2816de7c598SAndrew Rybchenko fail12:
2826de7c598SAndrew Rybchenko 	EFSYS_PROBE(fail12);
283cfa023ebSAndrew Rybchenko fail11:
284cfa023ebSAndrew Rybchenko 	EFSYS_PROBE(fail11);
285cfa023ebSAndrew Rybchenko fail10:
286cfa023ebSAndrew Rybchenko 	EFSYS_PROBE(fail10);
287cfa023ebSAndrew Rybchenko fail9:
288cfa023ebSAndrew Rybchenko 	EFSYS_PROBE(fail9);
289cfa023ebSAndrew Rybchenko fail8:
290cfa023ebSAndrew Rybchenko 	EFSYS_PROBE(fail8);
291cfa023ebSAndrew Rybchenko fail7:
292cfa023ebSAndrew Rybchenko 	EFSYS_PROBE(fail7);
293cfa023ebSAndrew Rybchenko fail6:
294cfa023ebSAndrew Rybchenko 	EFSYS_PROBE(fail6);
295cfa023ebSAndrew Rybchenko fail5:
296cfa023ebSAndrew Rybchenko 	EFSYS_PROBE(fail5);
297cfa023ebSAndrew Rybchenko fail4:
298cfa023ebSAndrew Rybchenko 	EFSYS_PROBE(fail4);
299cfa023ebSAndrew Rybchenko fail3:
300cfa023ebSAndrew Rybchenko 	EFSYS_PROBE(fail3);
301cfa023ebSAndrew Rybchenko fail2:
302cfa023ebSAndrew Rybchenko 	EFSYS_PROBE(fail2);
303cfa023ebSAndrew Rybchenko fail1:
304cfa023ebSAndrew Rybchenko 	EFSYS_PROBE1(fail1, efx_rc_t, rc);
305cfa023ebSAndrew Rybchenko 
306cfa023ebSAndrew Rybchenko 	return (rc);
307cfa023ebSAndrew Rybchenko }
3085f5c71ccSAndrew Rybchenko 
3095f5c71ccSAndrew Rybchenko #endif	/* EFSYS_OPT_MEDFORD */
310