xref: /freebsd/sys/dev/sfxge/common/medford_nic.c (revision 1c057dc0836aec832abe89461094aca86d9f15c4)
15f5c71ccSAndrew Rybchenko /*-
2929c7febSAndrew Rybchenko  * Copyright (c) 2015-2016 Solarflare Communications Inc.
35f5c71ccSAndrew Rybchenko  * All rights reserved.
45f5c71ccSAndrew Rybchenko  *
55f5c71ccSAndrew Rybchenko  * Redistribution and use in source and binary forms, with or without
65f5c71ccSAndrew Rybchenko  * modification, are permitted provided that the following conditions are met:
75f5c71ccSAndrew Rybchenko  *
85f5c71ccSAndrew Rybchenko  * 1. Redistributions of source code must retain the above copyright notice,
95f5c71ccSAndrew Rybchenko  *    this list of conditions and the following disclaimer.
105f5c71ccSAndrew Rybchenko  * 2. Redistributions in binary form must reproduce the above copyright notice,
115f5c71ccSAndrew Rybchenko  *    this list of conditions and the following disclaimer in the documentation
125f5c71ccSAndrew Rybchenko  *    and/or other materials provided with the distribution.
135f5c71ccSAndrew Rybchenko  *
145f5c71ccSAndrew Rybchenko  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
155f5c71ccSAndrew Rybchenko  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
165f5c71ccSAndrew Rybchenko  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
175f5c71ccSAndrew Rybchenko  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
185f5c71ccSAndrew Rybchenko  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
195f5c71ccSAndrew Rybchenko  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
205f5c71ccSAndrew Rybchenko  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
215f5c71ccSAndrew Rybchenko  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
225f5c71ccSAndrew Rybchenko  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
235f5c71ccSAndrew Rybchenko  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
245f5c71ccSAndrew Rybchenko  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
255f5c71ccSAndrew Rybchenko  *
265f5c71ccSAndrew Rybchenko  * The views and conclusions contained in the software and documentation are
275f5c71ccSAndrew Rybchenko  * those of the authors and should not be interpreted as representing official
285f5c71ccSAndrew Rybchenko  * policies, either expressed or implied, of the FreeBSD Project.
295f5c71ccSAndrew Rybchenko  */
305f5c71ccSAndrew Rybchenko 
315f5c71ccSAndrew Rybchenko #include <sys/cdefs.h>
325f5c71ccSAndrew Rybchenko __FBSDID("$FreeBSD$");
335f5c71ccSAndrew Rybchenko 
345f5c71ccSAndrew Rybchenko #include "efx.h"
355f5c71ccSAndrew Rybchenko #include "efx_impl.h"
36dcb49ebaSAndrew Rybchenko 
375f5c71ccSAndrew Rybchenko 
385f5c71ccSAndrew Rybchenko #if EFSYS_OPT_MEDFORD
395f5c71ccSAndrew Rybchenko 
406de7c598SAndrew Rybchenko static	__checkReturn	efx_rc_t
41f6d61784SAndrew Rybchenko medford_nic_get_required_pcie_bandwidth(
42f6d61784SAndrew Rybchenko 	__in		efx_nic_t *enp,
43f6d61784SAndrew Rybchenko 	__out		uint32_t *bandwidth_mbpsp)
44f6d61784SAndrew Rybchenko {
45f6d61784SAndrew Rybchenko 	uint32_t port_modes;
46f6d61784SAndrew Rybchenko 	uint32_t current_mode;
47f6d61784SAndrew Rybchenko 	uint32_t bandwidth;
48f6d61784SAndrew Rybchenko 	efx_rc_t rc;
49f6d61784SAndrew Rybchenko 
50f6d61784SAndrew Rybchenko 	if ((rc = efx_mcdi_get_port_modes(enp, &port_modes,
51f6d61784SAndrew Rybchenko 				    &current_mode)) != 0) {
52f6d61784SAndrew Rybchenko 		/* No port mode info available. */
53f6d61784SAndrew Rybchenko 		bandwidth = 0;
54f6d61784SAndrew Rybchenko 		goto out;
55f6d61784SAndrew Rybchenko 	}
56f6d61784SAndrew Rybchenko 
57f6d61784SAndrew Rybchenko 	if ((rc = ef10_nic_get_port_mode_bandwidth(current_mode,
58f6d61784SAndrew Rybchenko 						    &bandwidth)) != 0)
59f6d61784SAndrew Rybchenko 		goto fail1;
60f6d61784SAndrew Rybchenko 
61f6d61784SAndrew Rybchenko out:
62f6d61784SAndrew Rybchenko 	*bandwidth_mbpsp = bandwidth;
63f6d61784SAndrew Rybchenko 
64f6d61784SAndrew Rybchenko 	return (0);
65f6d61784SAndrew Rybchenko 
66f6d61784SAndrew Rybchenko fail1:
67f6d61784SAndrew Rybchenko 	EFSYS_PROBE1(fail1, efx_rc_t, rc);
68f6d61784SAndrew Rybchenko 
69f6d61784SAndrew Rybchenko 	return (rc);
70f6d61784SAndrew Rybchenko }
71f6d61784SAndrew Rybchenko 
72cfa023ebSAndrew Rybchenko 	__checkReturn	efx_rc_t
73cfa023ebSAndrew Rybchenko medford_board_cfg(
74cfa023ebSAndrew Rybchenko 	__in		efx_nic_t *enp)
75cfa023ebSAndrew Rybchenko {
76cfa023ebSAndrew Rybchenko 	efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
77cfa023ebSAndrew Rybchenko 	efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
78cfa023ebSAndrew Rybchenko 	uint8_t mac_addr[6] = { 0 };
79cfa023ebSAndrew Rybchenko 	uint32_t board_type = 0;
80177347ddSAndrew Rybchenko 	ef10_link_state_t els;
81cfa023ebSAndrew Rybchenko 	efx_port_t *epp = &(enp->en_port);
82cfa023ebSAndrew Rybchenko 	uint32_t port;
83cfa023ebSAndrew Rybchenko 	uint32_t pf;
84cfa023ebSAndrew Rybchenko 	uint32_t vf;
85cfa023ebSAndrew Rybchenko 	uint32_t mask;
8678e5c87cSAndrew Rybchenko 	uint32_t sysclk, dpcpu_clk;
87cfa023ebSAndrew Rybchenko 	uint32_t base, nvec;
886de7c598SAndrew Rybchenko 	uint32_t end_padding;
89f6d61784SAndrew Rybchenko 	uint32_t bandwidth;
90cfa023ebSAndrew Rybchenko 	efx_rc_t rc;
915f5c71ccSAndrew Rybchenko 
92cfa023ebSAndrew Rybchenko 	/*
93cfa023ebSAndrew Rybchenko 	 * FIXME: Likely to be incomplete and incorrect.
94cfa023ebSAndrew Rybchenko 	 * Parts of this should be shared with Huntington.
95cfa023ebSAndrew Rybchenko 	 */
965f5c71ccSAndrew Rybchenko 
97c63c8369SAndrew Rybchenko 	/* Medford has a fixed 8Kbyte VI window size */
98c63c8369SAndrew Rybchenko 	EFX_STATIC_ASSERT(ER_DZ_EVQ_RPTR_REG_STEP	== 8192);
99c63c8369SAndrew Rybchenko 	EFX_STATIC_ASSERT(ER_DZ_EVQ_TMR_REG_STEP	== 8192);
100c63c8369SAndrew Rybchenko 	EFX_STATIC_ASSERT(ER_DZ_RX_DESC_UPD_REG_STEP	== 8192);
101c63c8369SAndrew Rybchenko 	EFX_STATIC_ASSERT(ER_DZ_TX_DESC_UPD_REG_STEP	== 8192);
102c63c8369SAndrew Rybchenko 	EFX_STATIC_ASSERT(ER_DZ_TX_PIOBUF_STEP		== 8192);
103c63c8369SAndrew Rybchenko 
104c63c8369SAndrew Rybchenko 	EFX_STATIC_ASSERT(1U << EFX_VI_WINDOW_SHIFT_8K	== 8192);
105c63c8369SAndrew Rybchenko 	encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K;
106c63c8369SAndrew Rybchenko 
107c63c8369SAndrew Rybchenko 
108cfa023ebSAndrew Rybchenko 	if ((rc = efx_mcdi_get_port_assignment(enp, &port)) != 0)
109cfa023ebSAndrew Rybchenko 		goto fail1;
110cfa023ebSAndrew Rybchenko 
111cfa023ebSAndrew Rybchenko 	/*
112cfa023ebSAndrew Rybchenko 	 * NOTE: The MCDI protocol numbers ports from zero.
113cfa023ebSAndrew Rybchenko 	 * The common code MCDI interface numbers ports from one.
114cfa023ebSAndrew Rybchenko 	 */
115cfa023ebSAndrew Rybchenko 	emip->emi_port = port + 1;
116cfa023ebSAndrew Rybchenko 
117cfa023ebSAndrew Rybchenko 	if ((rc = ef10_external_port_mapping(enp, port,
118cfa023ebSAndrew Rybchenko 		    &encp->enc_external_port)) != 0)
119cfa023ebSAndrew Rybchenko 		goto fail2;
120cfa023ebSAndrew Rybchenko 
121cfa023ebSAndrew Rybchenko 	/*
122cfa023ebSAndrew Rybchenko 	 * Get PCIe function number from firmware (used for
123cfa023ebSAndrew Rybchenko 	 * per-function privilege and dynamic config info).
124cfa023ebSAndrew Rybchenko 	 *  - PCIe PF: pf = PF number, vf = 0xffff.
125cfa023ebSAndrew Rybchenko 	 *  - PCIe VF: pf = parent PF, vf = VF number.
126cfa023ebSAndrew Rybchenko 	 */
127cfa023ebSAndrew Rybchenko 	if ((rc = efx_mcdi_get_function_info(enp, &pf, &vf)) != 0)
128cfa023ebSAndrew Rybchenko 		goto fail3;
129cfa023ebSAndrew Rybchenko 
130cfa023ebSAndrew Rybchenko 	encp->enc_pf = pf;
131cfa023ebSAndrew Rybchenko 	encp->enc_vf = vf;
132cfa023ebSAndrew Rybchenko 
133cfa023ebSAndrew Rybchenko 	/* MAC address for this function */
134cfa023ebSAndrew Rybchenko 	if (EFX_PCI_FUNCTION_IS_PF(encp)) {
135cfa023ebSAndrew Rybchenko 		rc = efx_mcdi_get_mac_address_pf(enp, mac_addr);
136ecaa500cSAndrew Rybchenko #if EFSYS_OPT_ALLOW_UNCONFIGURED_NIC
13795c45bd0SAndrew Rybchenko 		/*
13895c45bd0SAndrew Rybchenko 		 * Disable static config checking for Medford NICs, ONLY
139ecaa500cSAndrew Rybchenko 		 * for manufacturing test and setup at the factory, to
140ecaa500cSAndrew Rybchenko 		 * allow the static config to be installed.
141ecaa500cSAndrew Rybchenko 		 */
142ecaa500cSAndrew Rybchenko #else /* EFSYS_OPT_ALLOW_UNCONFIGURED_NIC */
143cfa023ebSAndrew Rybchenko 		if ((rc == 0) && (mac_addr[0] & 0x02)) {
144cfa023ebSAndrew Rybchenko 			/*
145cfa023ebSAndrew Rybchenko 			 * If the static config does not include a global MAC
146cfa023ebSAndrew Rybchenko 			 * address pool then the board may return a locally
147cfa023ebSAndrew Rybchenko 			 * administered MAC address (this should only happen on
148cfa023ebSAndrew Rybchenko 			 * incorrectly programmed boards).
149cfa023ebSAndrew Rybchenko 			 */
150cfa023ebSAndrew Rybchenko 			rc = EINVAL;
151cfa023ebSAndrew Rybchenko 		}
152ecaa500cSAndrew Rybchenko #endif /* EFSYS_OPT_ALLOW_UNCONFIGURED_NIC */
153cfa023ebSAndrew Rybchenko 	} else {
154cfa023ebSAndrew Rybchenko 		rc = efx_mcdi_get_mac_address_vf(enp, mac_addr);
155cfa023ebSAndrew Rybchenko 	}
156cfa023ebSAndrew Rybchenko 	if (rc != 0)
157cfa023ebSAndrew Rybchenko 		goto fail4;
158cfa023ebSAndrew Rybchenko 
159cfa023ebSAndrew Rybchenko 	EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr);
160cfa023ebSAndrew Rybchenko 
161cfa023ebSAndrew Rybchenko 	/* Board configuration */
162cfa023ebSAndrew Rybchenko 	rc = efx_mcdi_get_board_cfg(enp, &board_type, NULL, NULL);
163cfa023ebSAndrew Rybchenko 	if (rc != 0) {
164cfa023ebSAndrew Rybchenko 		/* Unprivileged functions may not be able to read board cfg */
165cfa023ebSAndrew Rybchenko 		if (rc == EACCES)
166cfa023ebSAndrew Rybchenko 			board_type = 0;
167cfa023ebSAndrew Rybchenko 		else
168cfa023ebSAndrew Rybchenko 			goto fail5;
169cfa023ebSAndrew Rybchenko 	}
170cfa023ebSAndrew Rybchenko 
171cfa023ebSAndrew Rybchenko 	encp->enc_board_type = board_type;
172cfa023ebSAndrew Rybchenko 	encp->enc_clk_mult = 1; /* not used for Medford */
173cfa023ebSAndrew Rybchenko 
174cfa023ebSAndrew Rybchenko 	/* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
175cfa023ebSAndrew Rybchenko 	if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
176cfa023ebSAndrew Rybchenko 		goto fail6;
177cfa023ebSAndrew Rybchenko 
178cfa023ebSAndrew Rybchenko 	/* Obtain the default PHY advertised capabilities */
179ee2812adSAndrew Rybchenko 	if ((rc = ef10_phy_get_link(enp, &els)) != 0)
180cfa023ebSAndrew Rybchenko 		goto fail7;
181177347ddSAndrew Rybchenko 	epp->ep_default_adv_cap_mask = els.els_adv_cap_mask;
182177347ddSAndrew Rybchenko 	epp->ep_adv_cap_mask = els.els_adv_cap_mask;
183cfa023ebSAndrew Rybchenko 
184e26f5dacSAndrew Rybchenko 	/*
185e26f5dacSAndrew Rybchenko 	 * Enable firmware workarounds for hardware errata.
186e26f5dacSAndrew Rybchenko 	 * Expected responses are:
187e26f5dacSAndrew Rybchenko 	 *  - 0 (zero):
188e26f5dacSAndrew Rybchenko 	 *	Success: workaround enabled or disabled as requested.
189e26f5dacSAndrew Rybchenko 	 *  - MC_CMD_ERR_ENOSYS (reported as ENOTSUP):
190e26f5dacSAndrew Rybchenko 	 *	Firmware does not support the MC_CMD_WORKAROUND request.
191e26f5dacSAndrew Rybchenko 	 *	(assume that the workaround is not supported).
192e26f5dacSAndrew Rybchenko 	 *  - MC_CMD_ERR_ENOENT (reported as ENOENT):
193e26f5dacSAndrew Rybchenko 	 *	Firmware does not support the requested workaround.
194e26f5dacSAndrew Rybchenko 	 *  - MC_CMD_ERR_EPERM  (reported as EACCES):
195e26f5dacSAndrew Rybchenko 	 *	Unprivileged function cannot enable/disable workarounds.
196e26f5dacSAndrew Rybchenko 	 *
197e26f5dacSAndrew Rybchenko 	 * See efx_mcdi_request_errcode() for MCDI error translations.
198e26f5dacSAndrew Rybchenko 	 */
199e26f5dacSAndrew Rybchenko 
200e26f5dacSAndrew Rybchenko 
201cfa023ebSAndrew Rybchenko 	if (EFX_PCI_FUNCTION_IS_VF(encp)) {
202cfa023ebSAndrew Rybchenko 		/*
203*1c057dc0SAndrew Rybchenko 		 * Interrupt testing does not work for VFs. See bug50084 and
204*1c057dc0SAndrew Rybchenko 		 * bug71432 comment 21.
205cfa023ebSAndrew Rybchenko 		 */
206cfa023ebSAndrew Rybchenko 		encp->enc_bug41750_workaround = B_TRUE;
207cfa023ebSAndrew Rybchenko 	}
208cfa023ebSAndrew Rybchenko 
209cfa023ebSAndrew Rybchenko 	/* Chained multicast is always enabled on Medford */
210cfa023ebSAndrew Rybchenko 	encp->enc_bug26807_workaround = B_TRUE;
211cfa023ebSAndrew Rybchenko 
212e26f5dacSAndrew Rybchenko 	/*
213e26f5dacSAndrew Rybchenko 	 * If the bug61265 workaround is enabled, then interrupt holdoff timers
214e26f5dacSAndrew Rybchenko 	 * cannot be controlled by timer table writes, so MCDI must be used
215e26f5dacSAndrew Rybchenko 	 * (timer table writes can still be used for wakeup timers).
216e26f5dacSAndrew Rybchenko 	 */
217e26f5dacSAndrew Rybchenko 	rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG61265, B_TRUE,
218e26f5dacSAndrew Rybchenko 	    NULL);
219e26f5dacSAndrew Rybchenko 	if ((rc == 0) || (rc == EACCES))
220e26f5dacSAndrew Rybchenko 		encp->enc_bug61265_workaround = B_TRUE;
221e26f5dacSAndrew Rybchenko 	else if ((rc == ENOTSUP) || (rc == ENOENT))
222e26f5dacSAndrew Rybchenko 		encp->enc_bug61265_workaround = B_FALSE;
223e26f5dacSAndrew Rybchenko 	else
224e26f5dacSAndrew Rybchenko 		goto fail8;
225e26f5dacSAndrew Rybchenko 
22678e5c87cSAndrew Rybchenko 	/* Get clock frequencies (in MHz). */
22778e5c87cSAndrew Rybchenko 	if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
228e26f5dacSAndrew Rybchenko 		goto fail9;
229cfa023ebSAndrew Rybchenko 
230cfa023ebSAndrew Rybchenko 	/*
23178e5c87cSAndrew Rybchenko 	 * The Medford timer quantum is 1536 dpcpu_clk cycles, documented for
23278e5c87cSAndrew Rybchenko 	 * the EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units.
233cfa023ebSAndrew Rybchenko 	 */
23478e5c87cSAndrew Rybchenko 	encp->enc_evq_timer_quantum_ns = 1536000UL / dpcpu_clk; /* 1536 cycles */
235cfa023ebSAndrew Rybchenko 	encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
236cfa023ebSAndrew Rybchenko 		    FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
237cfa023ebSAndrew Rybchenko 
238cfa023ebSAndrew Rybchenko 	/* Check capabilities of running datapath firmware */
239cfa023ebSAndrew Rybchenko 	if ((rc = ef10_get_datapath_caps(enp)) != 0)
240e26f5dacSAndrew Rybchenko 		goto fail10;
241cfa023ebSAndrew Rybchenko 
242cfa023ebSAndrew Rybchenko 	/* Alignment for receive packet DMA buffers */
243cfa023ebSAndrew Rybchenko 	encp->enc_rx_buf_align_start = 1;
244cfa023ebSAndrew Rybchenko 
2456de7c598SAndrew Rybchenko 	/* Get the RX DMA end padding alignment configuration */
246ab72be51SAndrew Rybchenko 	if ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0) {
247ab72be51SAndrew Rybchenko 		if (rc != EACCES)
248e26f5dacSAndrew Rybchenko 			goto fail11;
249ab72be51SAndrew Rybchenko 
250ab72be51SAndrew Rybchenko 		/* Assume largest tail padding size supported by hardware */
251ab72be51SAndrew Rybchenko 		end_padding = 256;
252ab72be51SAndrew Rybchenko 	}
2536de7c598SAndrew Rybchenko 	encp->enc_rx_buf_align_end = end_padding;
254cfa023ebSAndrew Rybchenko 
255cfa023ebSAndrew Rybchenko 	/* Alignment for WPTR updates */
256cfa023ebSAndrew Rybchenko 	encp->enc_rx_push_align = EF10_RX_WPTR_ALIGN;
257cfa023ebSAndrew Rybchenko 
2587283cea3SAndrew Rybchenko 	/*
2597283cea3SAndrew Rybchenko 	 * Maximum number of exclusive RSS contexts which can be allocated. The
2607283cea3SAndrew Rybchenko 	 * hardware supports 64, but 6 are reserved for shared contexts. They
2617283cea3SAndrew Rybchenko 	 * are a global resource so not all may be available.
2627283cea3SAndrew Rybchenko 	 */
2637283cea3SAndrew Rybchenko 	encp->enc_rx_scale_max_exclusive_contexts = 58;
2647283cea3SAndrew Rybchenko 
2656a09b206SAndrew Rybchenko 	encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT);
2666a09b206SAndrew Rybchenko 	/* No boundary crossing limits */
2676a09b206SAndrew Rybchenko 	encp->enc_tx_dma_desc_boundary = 0;
2686a09b206SAndrew Rybchenko 
269cfa023ebSAndrew Rybchenko 	/*
270cfa023ebSAndrew Rybchenko 	 * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
271cfa023ebSAndrew Rybchenko 	 * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available
272cfa023ebSAndrew Rybchenko 	 * resources (allocated to this PCIe function), which is zero until
273cfa023ebSAndrew Rybchenko 	 * after we have allocated VIs.
274cfa023ebSAndrew Rybchenko 	 */
275cfa023ebSAndrew Rybchenko 	encp->enc_evq_limit = 1024;
276cfa023ebSAndrew Rybchenko 	encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET;
277cfa023ebSAndrew Rybchenko 	encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET;
278cfa023ebSAndrew Rybchenko 
279d343a7f4SAndrew Rybchenko 	/*
280d343a7f4SAndrew Rybchenko 	 * The maximum supported transmit queue size is 2048. TXQs with 4096
281d343a7f4SAndrew Rybchenko 	 * descriptors are not supported as the top bit is used for vfifo
282d343a7f4SAndrew Rybchenko 	 * stuffing.
283d343a7f4SAndrew Rybchenko 	 */
284d343a7f4SAndrew Rybchenko 	encp->enc_txq_max_ndescs = 2048;
285d343a7f4SAndrew Rybchenko 
286cfa023ebSAndrew Rybchenko 	encp->enc_buftbl_limit = 0xFFFFFFFF;
287cfa023ebSAndrew Rybchenko 
2884f58306cSAndrew Rybchenko 	EFX_STATIC_ASSERT(MEDFORD_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS);
289cfa023ebSAndrew Rybchenko 	encp->enc_piobuf_limit = MEDFORD_PIOBUF_NBUFS;
290cfa023ebSAndrew Rybchenko 	encp->enc_piobuf_size = MEDFORD_PIOBUF_SIZE;
291cfa023ebSAndrew Rybchenko 	encp->enc_piobuf_min_alloc_size = MEDFORD_MIN_PIO_ALLOC_SIZE;
292cfa023ebSAndrew Rybchenko 
293cfa023ebSAndrew Rybchenko 	/*
294cfa023ebSAndrew Rybchenko 	 * Get the current privilege mask. Note that this may be modified
295cfa023ebSAndrew Rybchenko 	 * dynamically, so this value is informational only. DO NOT use
296cfa023ebSAndrew Rybchenko 	 * the privilege mask to check for sufficient privileges, as that
297cfa023ebSAndrew Rybchenko 	 * can result in time-of-check/time-of-use bugs.
298cfa023ebSAndrew Rybchenko 	 */
29980af6f26SAndrew Rybchenko 	if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
300e26f5dacSAndrew Rybchenko 		goto fail12;
301cfa023ebSAndrew Rybchenko 	encp->enc_privilege_mask = mask;
302cfa023ebSAndrew Rybchenko 
303cfa023ebSAndrew Rybchenko 	/* Get interrupt vector limits */
304cfa023ebSAndrew Rybchenko 	if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
305cfa023ebSAndrew Rybchenko 		if (EFX_PCI_FUNCTION_IS_PF(encp))
306e26f5dacSAndrew Rybchenko 			goto fail13;
307cfa023ebSAndrew Rybchenko 
308cfa023ebSAndrew Rybchenko 		/* Ignore error (cannot query vector limits from a VF). */
309cfa023ebSAndrew Rybchenko 		base = 0;
310cfa023ebSAndrew Rybchenko 		nvec = 1024;
311cfa023ebSAndrew Rybchenko 	}
312cfa023ebSAndrew Rybchenko 	encp->enc_intr_vec_base = base;
313cfa023ebSAndrew Rybchenko 	encp->enc_intr_limit = nvec;
314cfa023ebSAndrew Rybchenko 
315cfa023ebSAndrew Rybchenko 	/*
316cfa023ebSAndrew Rybchenko 	 * Maximum number of bytes into the frame the TCP header can start for
317cfa023ebSAndrew Rybchenko 	 * firmware assisted TSO to work.
318cfa023ebSAndrew Rybchenko 	 */
319cfa023ebSAndrew Rybchenko 	encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;
320cfa023ebSAndrew Rybchenko 
321739ebba6SAndrew Rybchenko 	/*
322739ebba6SAndrew Rybchenko 	 * Medford stores a single global copy of VPD, not per-PF as on
323739ebba6SAndrew Rybchenko 	 * Huntington.
324739ebba6SAndrew Rybchenko 	 */
325739ebba6SAndrew Rybchenko 	encp->enc_vpd_is_global = B_TRUE;
326739ebba6SAndrew Rybchenko 
327f6d61784SAndrew Rybchenko 	rc = medford_nic_get_required_pcie_bandwidth(enp, &bandwidth);
328f6d61784SAndrew Rybchenko 	if (rc != 0)
329e26f5dacSAndrew Rybchenko 		goto fail14;
330f6d61784SAndrew Rybchenko 	encp->enc_required_pcie_bandwidth_mbps = bandwidth;
331f6d61784SAndrew Rybchenko 	encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
332f6d61784SAndrew Rybchenko 
333cfa023ebSAndrew Rybchenko 	return (0);
334cfa023ebSAndrew Rybchenko 
335e26f5dacSAndrew Rybchenko fail14:
336e26f5dacSAndrew Rybchenko 	EFSYS_PROBE(fail14);
337f6d61784SAndrew Rybchenko fail13:
338f6d61784SAndrew Rybchenko 	EFSYS_PROBE(fail13);
3396de7c598SAndrew Rybchenko fail12:
3406de7c598SAndrew Rybchenko 	EFSYS_PROBE(fail12);
341cfa023ebSAndrew Rybchenko fail11:
342cfa023ebSAndrew Rybchenko 	EFSYS_PROBE(fail11);
343cfa023ebSAndrew Rybchenko fail10:
344cfa023ebSAndrew Rybchenko 	EFSYS_PROBE(fail10);
345cfa023ebSAndrew Rybchenko fail9:
346cfa023ebSAndrew Rybchenko 	EFSYS_PROBE(fail9);
347cfa023ebSAndrew Rybchenko fail8:
348cfa023ebSAndrew Rybchenko 	EFSYS_PROBE(fail8);
349cfa023ebSAndrew Rybchenko fail7:
350cfa023ebSAndrew Rybchenko 	EFSYS_PROBE(fail7);
351cfa023ebSAndrew Rybchenko fail6:
352cfa023ebSAndrew Rybchenko 	EFSYS_PROBE(fail6);
353cfa023ebSAndrew Rybchenko fail5:
354cfa023ebSAndrew Rybchenko 	EFSYS_PROBE(fail5);
355cfa023ebSAndrew Rybchenko fail4:
356cfa023ebSAndrew Rybchenko 	EFSYS_PROBE(fail4);
357cfa023ebSAndrew Rybchenko fail3:
358cfa023ebSAndrew Rybchenko 	EFSYS_PROBE(fail3);
359cfa023ebSAndrew Rybchenko fail2:
360cfa023ebSAndrew Rybchenko 	EFSYS_PROBE(fail2);
361cfa023ebSAndrew Rybchenko fail1:
362cfa023ebSAndrew Rybchenko 	EFSYS_PROBE1(fail1, efx_rc_t, rc);
363cfa023ebSAndrew Rybchenko 
364cfa023ebSAndrew Rybchenko 	return (rc);
365cfa023ebSAndrew Rybchenko }
3665f5c71ccSAndrew Rybchenko 
3675f5c71ccSAndrew Rybchenko #endif	/* EFSYS_OPT_MEDFORD */
368