xref: /freebsd/sys/dev/sfxge/common/hunt_nic.c (revision bdd1243df58e60e85101c09001d9812a789b6bc4)
1 /*-
2  * Copyright (c) 2012-2016 Solarflare Communications Inc.
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions are met:
7  *
8  * 1. Redistributions of source code must retain the above copyright notice,
9  *    this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright notice,
11  *    this list of conditions and the following disclaimer in the documentation
12  *    and/or other materials provided with the distribution.
13  *
14  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25  *
26  * The views and conclusions contained in the software and documentation are
27  * those of the authors and should not be interpreted as representing official
28  * policies, either expressed or implied, of the FreeBSD Project.
29  */
30 
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
33 
34 #include "efx.h"
35 #include "efx_impl.h"
36 #if EFSYS_OPT_MON_MCDI
37 #include "mcdi_mon.h"
38 #endif
39 
40 #if EFSYS_OPT_HUNTINGTON
41 
42 #include "ef10_tlv_layout.h"
43 
44 static	__checkReturn	efx_rc_t
45 hunt_nic_get_required_pcie_bandwidth(
46 	__in		efx_nic_t *enp,
47 	__out		uint32_t *bandwidth_mbpsp)
48 {
49 	uint32_t port_modes;
50 	uint32_t bandwidth;
51 	efx_rc_t rc;
52 
53 	/*
54 	 * On Huntington, the firmware may not give us the current port mode, so
55 	 * we need to go by the set of available port modes and assume the most
56 	 * capable mode is in use.
57 	 */
58 
59 	if ((rc = efx_mcdi_get_port_modes(enp, &port_modes,
60 		    NULL, NULL)) != 0) {
61 		/* No port mode info available */
62 		bandwidth = 0;
63 		goto out;
64 	}
65 
66 	if (port_modes & (1U << TLV_PORT_MODE_40G_40G)) {
67 		/*
68 		 * This needs the full PCIe bandwidth (and could use
69 		 * more) - roughly 64 Gbit/s for 8 lanes of Gen3.
70 		 */
71 		if ((rc = efx_nic_calculate_pcie_link_bandwidth(8,
72 			    EFX_PCIE_LINK_SPEED_GEN3, &bandwidth)) != 0)
73 			goto fail1;
74 	} else {
75 		if (port_modes & (1U << TLV_PORT_MODE_40G)) {
76 			bandwidth = 40000;
77 		} else if (port_modes & (1U << TLV_PORT_MODE_10G_10G_10G_10G)) {
78 			bandwidth = 4 * 10000;
79 		} else {
80 			/* Assume two 10G ports */
81 			bandwidth = 2 * 10000;
82 		}
83 	}
84 
85 out:
86 	*bandwidth_mbpsp = bandwidth;
87 
88 	return (0);
89 
90 fail1:
91 	EFSYS_PROBE1(fail1, efx_rc_t, rc);
92 
93 	return (rc);
94 }
95 
96 	__checkReturn	efx_rc_t
97 hunt_board_cfg(
98 	__in		efx_nic_t *enp)
99 {
100 	efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
101 	efx_port_t *epp = &(enp->en_port);
102 	uint32_t flags;
103 	uint32_t sysclk, dpcpu_clk;
104 	uint32_t bandwidth;
105 	efx_rc_t rc;
106 
107 	/*
108 	 * Enable firmware workarounds for hardware errata.
109 	 * Expected responses are:
110 	 *  - 0 (zero):
111 	 *	Success: workaround enabled or disabled as requested.
112 	 *  - MC_CMD_ERR_ENOSYS (reported as ENOTSUP):
113 	 *	Firmware does not support the MC_CMD_WORKAROUND request.
114 	 *	(assume that the workaround is not supported).
115 	 *  - MC_CMD_ERR_ENOENT (reported as ENOENT):
116 	 *	Firmware does not support the requested workaround.
117 	 *  - MC_CMD_ERR_EPERM  (reported as EACCES):
118 	 *	Unprivileged function cannot enable/disable workarounds.
119 	 *
120 	 * See efx_mcdi_request_errcode() for MCDI error translations.
121 	 */
122 
123 	/*
124 	 * If the bug35388 workaround is enabled, then use an indirect access
125 	 * method to avoid unsafe EVQ writes.
126 	 */
127 	rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG35388, B_TRUE,
128 	    NULL);
129 	if ((rc == 0) || (rc == EACCES))
130 		encp->enc_bug35388_workaround = B_TRUE;
131 	else if ((rc == ENOTSUP) || (rc == ENOENT))
132 		encp->enc_bug35388_workaround = B_FALSE;
133 	else
134 		goto fail1;
135 
136 	/*
137 	 * If the bug41750 workaround is enabled, then do not test interrupts,
138 	 * as the test will fail (seen with Greenport controllers).
139 	 */
140 	rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG41750, B_TRUE,
141 	    NULL);
142 	if (rc == 0) {
143 		encp->enc_bug41750_workaround = B_TRUE;
144 	} else if (rc == EACCES) {
145 		/* Assume a controller with 40G ports needs the workaround. */
146 		if (epp->ep_default_adv_cap_mask & EFX_PHY_CAP_40000FDX)
147 			encp->enc_bug41750_workaround = B_TRUE;
148 		else
149 			encp->enc_bug41750_workaround = B_FALSE;
150 	} else if ((rc == ENOTSUP) || (rc == ENOENT)) {
151 		encp->enc_bug41750_workaround = B_FALSE;
152 	} else {
153 		goto fail2;
154 	}
155 	if (EFX_PCI_FUNCTION_IS_VF(encp)) {
156 		/* Interrupt testing does not work for VFs. See bug50084. */
157 		encp->enc_bug41750_workaround = B_TRUE;
158 	}
159 
160 	/*
161 	 * If the bug26807 workaround is enabled, then firmware has enabled
162 	 * support for chained multicast filters. Firmware will reset (FLR)
163 	 * functions which have filters in the hardware filter table when the
164 	 * workaround is enabled/disabled.
165 	 *
166 	 * We must recheck if the workaround is enabled after inserting the
167 	 * first hardware filter, in case it has been changed since this check.
168 	 */
169 	rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG26807,
170 	    B_TRUE, &flags);
171 	if (rc == 0) {
172 		encp->enc_bug26807_workaround = B_TRUE;
173 		if (flags & (1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN)) {
174 			/*
175 			 * Other functions had installed filters before the
176 			 * workaround was enabled, and they have been reset
177 			 * by firmware.
178 			 */
179 			EFSYS_PROBE(bug26807_workaround_flr_done);
180 			/* FIXME: bump MC warm boot count ? */
181 		}
182 	} else if (rc == EACCES) {
183 		/*
184 		 * Unprivileged functions cannot enable the workaround in older
185 		 * firmware.
186 		 */
187 		encp->enc_bug26807_workaround = B_FALSE;
188 	} else if ((rc == ENOTSUP) || (rc == ENOENT)) {
189 		encp->enc_bug26807_workaround = B_FALSE;
190 	} else {
191 		goto fail3;
192 	}
193 
194 	/* Get clock frequencies (in MHz). */
195 	if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
196 		goto fail4;
197 
198 	/*
199 	 * The Huntington timer quantum is 1536 sysclk cycles, documented for
200 	 * the EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units.
201 	 */
202 	encp->enc_evq_timer_quantum_ns = 1536000UL / sysclk; /* 1536 cycles */
203 	if (encp->enc_bug35388_workaround) {
204 		encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
205 		ERF_DD_EVQ_IND_TIMER_VAL_WIDTH) / 1000;
206 	} else {
207 		encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
208 		FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
209 	}
210 
211 	encp->enc_bug61265_workaround = B_FALSE; /* Medford only */
212 
213 	/* Checksums for TSO sends can be incorrect on Huntington. */
214 	encp->enc_bug61297_workaround = B_TRUE;
215 
216 	/* Alignment for receive packet DMA buffers */
217 	encp->enc_rx_buf_align_start = 1;
218 	encp->enc_rx_buf_align_end = 64; /* RX DMA end padding */
219 
220 	/*
221 	 * The workaround for bug35388 uses the top bit of transmit queue
222 	 * descriptor writes, preventing the use of 4096 descriptor TXQs.
223 	 */
224 	encp->enc_txq_max_ndescs = encp->enc_bug35388_workaround ? 2048 : 4096;
225 
226 	EFX_STATIC_ASSERT(HUNT_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS);
227 	encp->enc_piobuf_limit = HUNT_PIOBUF_NBUFS;
228 	encp->enc_piobuf_size = HUNT_PIOBUF_SIZE;
229 	encp->enc_piobuf_min_alloc_size = HUNT_MIN_PIO_ALLOC_SIZE;
230 
231 	if ((rc = hunt_nic_get_required_pcie_bandwidth(enp, &bandwidth)) != 0)
232 		goto fail5;
233 	encp->enc_required_pcie_bandwidth_mbps = bandwidth;
234 
235 	/* All Huntington devices have a PCIe Gen3, 8 lane connector */
236 	encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
237 
238 	return (0);
239 
240 fail5:
241 	EFSYS_PROBE(fail5);
242 fail4:
243 	EFSYS_PROBE(fail4);
244 fail3:
245 	EFSYS_PROBE(fail3);
246 fail2:
247 	EFSYS_PROBE(fail2);
248 fail1:
249 	EFSYS_PROBE1(fail1, efx_rc_t, rc);
250 
251 	return (rc);
252 }
253 
254 #endif	/* EFSYS_OPT_HUNTINGTON */
255