1 /*- 2 * Copyright (c) 2012-2016 Solarflare Communications Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * The views and conclusions contained in the software and documentation are 27 * those of the authors and should not be interpreted as representing official 28 * policies, either expressed or implied, of the FreeBSD Project. 29 */ 30 31 #include <sys/cdefs.h> 32 #include "efx.h" 33 #include "efx_impl.h" 34 #if EFSYS_OPT_MON_MCDI 35 #include "mcdi_mon.h" 36 #endif 37 38 #if EFSYS_OPT_HUNTINGTON 39 40 #include "ef10_tlv_layout.h" 41 42 static __checkReturn efx_rc_t 43 hunt_nic_get_required_pcie_bandwidth( 44 __in efx_nic_t *enp, 45 __out uint32_t *bandwidth_mbpsp) 46 { 47 uint32_t port_modes; 48 uint32_t bandwidth; 49 efx_rc_t rc; 50 51 /* 52 * On Huntington, the firmware may not give us the current port mode, so 53 * we need to go by the set of available port modes and assume the most 54 * capable mode is in use. 55 */ 56 57 if ((rc = efx_mcdi_get_port_modes(enp, &port_modes, 58 NULL, NULL)) != 0) { 59 /* No port mode info available */ 60 bandwidth = 0; 61 goto out; 62 } 63 64 if (port_modes & (1U << TLV_PORT_MODE_40G_40G)) { 65 /* 66 * This needs the full PCIe bandwidth (and could use 67 * more) - roughly 64 Gbit/s for 8 lanes of Gen3. 68 */ 69 if ((rc = efx_nic_calculate_pcie_link_bandwidth(8, 70 EFX_PCIE_LINK_SPEED_GEN3, &bandwidth)) != 0) 71 goto fail1; 72 } else { 73 if (port_modes & (1U << TLV_PORT_MODE_40G)) { 74 bandwidth = 40000; 75 } else if (port_modes & (1U << TLV_PORT_MODE_10G_10G_10G_10G)) { 76 bandwidth = 4 * 10000; 77 } else { 78 /* Assume two 10G ports */ 79 bandwidth = 2 * 10000; 80 } 81 } 82 83 out: 84 *bandwidth_mbpsp = bandwidth; 85 86 return (0); 87 88 fail1: 89 EFSYS_PROBE1(fail1, efx_rc_t, rc); 90 91 return (rc); 92 } 93 94 __checkReturn efx_rc_t 95 hunt_board_cfg( 96 __in efx_nic_t *enp) 97 { 98 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); 99 efx_port_t *epp = &(enp->en_port); 100 uint32_t flags; 101 uint32_t sysclk, dpcpu_clk; 102 uint32_t bandwidth; 103 efx_rc_t rc; 104 105 /* 106 * Enable firmware workarounds for hardware errata. 107 * Expected responses are: 108 * - 0 (zero): 109 * Success: workaround enabled or disabled as requested. 110 * - MC_CMD_ERR_ENOSYS (reported as ENOTSUP): 111 * Firmware does not support the MC_CMD_WORKAROUND request. 112 * (assume that the workaround is not supported). 113 * - MC_CMD_ERR_ENOENT (reported as ENOENT): 114 * Firmware does not support the requested workaround. 115 * - MC_CMD_ERR_EPERM (reported as EACCES): 116 * Unprivileged function cannot enable/disable workarounds. 117 * 118 * See efx_mcdi_request_errcode() for MCDI error translations. 119 */ 120 121 /* 122 * If the bug35388 workaround is enabled, then use an indirect access 123 * method to avoid unsafe EVQ writes. 124 */ 125 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG35388, B_TRUE, 126 NULL); 127 if ((rc == 0) || (rc == EACCES)) 128 encp->enc_bug35388_workaround = B_TRUE; 129 else if ((rc == ENOTSUP) || (rc == ENOENT)) 130 encp->enc_bug35388_workaround = B_FALSE; 131 else 132 goto fail1; 133 134 /* 135 * If the bug41750 workaround is enabled, then do not test interrupts, 136 * as the test will fail (seen with Greenport controllers). 137 */ 138 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG41750, B_TRUE, 139 NULL); 140 if (rc == 0) { 141 encp->enc_bug41750_workaround = B_TRUE; 142 } else if (rc == EACCES) { 143 /* Assume a controller with 40G ports needs the workaround. */ 144 if (epp->ep_default_adv_cap_mask & EFX_PHY_CAP_40000FDX) 145 encp->enc_bug41750_workaround = B_TRUE; 146 else 147 encp->enc_bug41750_workaround = B_FALSE; 148 } else if ((rc == ENOTSUP) || (rc == ENOENT)) { 149 encp->enc_bug41750_workaround = B_FALSE; 150 } else { 151 goto fail2; 152 } 153 if (EFX_PCI_FUNCTION_IS_VF(encp)) { 154 /* Interrupt testing does not work for VFs. See bug50084. */ 155 encp->enc_bug41750_workaround = B_TRUE; 156 } 157 158 /* 159 * If the bug26807 workaround is enabled, then firmware has enabled 160 * support for chained multicast filters. Firmware will reset (FLR) 161 * functions which have filters in the hardware filter table when the 162 * workaround is enabled/disabled. 163 * 164 * We must recheck if the workaround is enabled after inserting the 165 * first hardware filter, in case it has been changed since this check. 166 */ 167 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG26807, 168 B_TRUE, &flags); 169 if (rc == 0) { 170 encp->enc_bug26807_workaround = B_TRUE; 171 if (flags & (1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN)) { 172 /* 173 * Other functions had installed filters before the 174 * workaround was enabled, and they have been reset 175 * by firmware. 176 */ 177 EFSYS_PROBE(bug26807_workaround_flr_done); 178 /* FIXME: bump MC warm boot count ? */ 179 } 180 } else if (rc == EACCES) { 181 /* 182 * Unprivileged functions cannot enable the workaround in older 183 * firmware. 184 */ 185 encp->enc_bug26807_workaround = B_FALSE; 186 } else if ((rc == ENOTSUP) || (rc == ENOENT)) { 187 encp->enc_bug26807_workaround = B_FALSE; 188 } else { 189 goto fail3; 190 } 191 192 /* Get clock frequencies (in MHz). */ 193 if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0) 194 goto fail4; 195 196 /* 197 * The Huntington timer quantum is 1536 sysclk cycles, documented for 198 * the EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units. 199 */ 200 encp->enc_evq_timer_quantum_ns = 1536000UL / sysclk; /* 1536 cycles */ 201 if (encp->enc_bug35388_workaround) { 202 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns << 203 ERF_DD_EVQ_IND_TIMER_VAL_WIDTH) / 1000; 204 } else { 205 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns << 206 FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000; 207 } 208 209 encp->enc_bug61265_workaround = B_FALSE; /* Medford only */ 210 211 /* Checksums for TSO sends can be incorrect on Huntington. */ 212 encp->enc_bug61297_workaround = B_TRUE; 213 214 /* Alignment for receive packet DMA buffers */ 215 encp->enc_rx_buf_align_start = 1; 216 encp->enc_rx_buf_align_end = 64; /* RX DMA end padding */ 217 218 /* 219 * The workaround for bug35388 uses the top bit of transmit queue 220 * descriptor writes, preventing the use of 4096 descriptor TXQs. 221 */ 222 encp->enc_txq_max_ndescs = encp->enc_bug35388_workaround ? 2048 : 4096; 223 224 EFX_STATIC_ASSERT(HUNT_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS); 225 encp->enc_piobuf_limit = HUNT_PIOBUF_NBUFS; 226 encp->enc_piobuf_size = HUNT_PIOBUF_SIZE; 227 encp->enc_piobuf_min_alloc_size = HUNT_MIN_PIO_ALLOC_SIZE; 228 229 if ((rc = hunt_nic_get_required_pcie_bandwidth(enp, &bandwidth)) != 0) 230 goto fail5; 231 encp->enc_required_pcie_bandwidth_mbps = bandwidth; 232 233 /* All Huntington devices have a PCIe Gen3, 8 lane connector */ 234 encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3; 235 236 return (0); 237 238 fail5: 239 EFSYS_PROBE(fail5); 240 fail4: 241 EFSYS_PROBE(fail4); 242 fail3: 243 EFSYS_PROBE(fail3); 244 fail2: 245 EFSYS_PROBE(fail2); 246 fail1: 247 EFSYS_PROBE1(fail1, efx_rc_t, rc); 248 249 return (rc); 250 } 251 252 #endif /* EFSYS_OPT_HUNTINGTON */ 253