1 /*- 2 * Copyright (c) 2012-2015 Solarflare Communications Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * The views and conclusions contained in the software and documentation are 27 * those of the authors and should not be interpreted as representing official 28 * policies, either expressed or implied, of the FreeBSD Project. 29 * 30 * $FreeBSD$ 31 */ 32 33 #ifndef _SYS_HUNT_IMPL_H 34 #define _SYS_HUNT_IMPL_H 35 36 #include "efx.h" 37 #include "efx_regs.h" 38 #include "efx_regs_ef10.h" 39 #include "efx_mcdi.h" 40 41 #ifdef __cplusplus 42 extern "C" { 43 #endif 44 45 /* 46 * FIXME: This is just a power of 2 which fits in an MCDI v1 message, and could 47 * possibly be increased, or the write size reported by newer firmware used 48 * instead. 49 */ 50 #define EF10_NVRAM_CHUNK 0x80 51 52 /* Alignment requirement for value written to RX WPTR: 53 * the WPTR must be aligned to an 8 descriptor boundary 54 */ 55 #define EF10_RX_WPTR_ALIGN 8 56 57 /* 58 * Max byte offset into the packet the TCP header must start for the hardware 59 * to be able to parse the packet correctly. 60 * FIXME: Move to ef10_impl.h when it is included in all driver builds. 61 */ 62 #define EF10_TCP_HEADER_OFFSET_LIMIT 208 63 64 /* Invalid RSS context handle */ 65 #define EF10_RSS_CONTEXT_INVALID (0xffffffff) 66 67 68 /* EV */ 69 70 __checkReturn efx_rc_t 71 ef10_ev_init( 72 __in efx_nic_t *enp); 73 74 void 75 ef10_ev_fini( 76 __in efx_nic_t *enp); 77 78 __checkReturn efx_rc_t 79 ef10_ev_qcreate( 80 __in efx_nic_t *enp, 81 __in unsigned int index, 82 __in efsys_mem_t *esmp, 83 __in size_t n, 84 __in uint32_t id, 85 __in efx_evq_t *eep); 86 87 void 88 ef10_ev_qdestroy( 89 __in efx_evq_t *eep); 90 91 __checkReturn efx_rc_t 92 ef10_ev_qprime( 93 __in efx_evq_t *eep, 94 __in unsigned int count); 95 96 void 97 ef10_ev_qpost( 98 __in efx_evq_t *eep, 99 __in uint16_t data); 100 101 __checkReturn efx_rc_t 102 ef10_ev_qmoderate( 103 __in efx_evq_t *eep, 104 __in unsigned int us); 105 106 #if EFSYS_OPT_QSTATS 107 void 108 ef10_ev_qstats_update( 109 __in efx_evq_t *eep, 110 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat); 111 #endif /* EFSYS_OPT_QSTATS */ 112 113 void 114 ef10_ev_rxlabel_init( 115 __in efx_evq_t *eep, 116 __in efx_rxq_t *erp, 117 __in unsigned int label); 118 119 void 120 ef10_ev_rxlabel_fini( 121 __in efx_evq_t *eep, 122 __in unsigned int label); 123 124 /* INTR */ 125 126 __checkReturn efx_rc_t 127 ef10_intr_init( 128 __in efx_nic_t *enp, 129 __in efx_intr_type_t type, 130 __in efsys_mem_t *esmp); 131 132 void 133 ef10_intr_enable( 134 __in efx_nic_t *enp); 135 136 void 137 ef10_intr_disable( 138 __in efx_nic_t *enp); 139 140 void 141 ef10_intr_disable_unlocked( 142 __in efx_nic_t *enp); 143 144 __checkReturn efx_rc_t 145 ef10_intr_trigger( 146 __in efx_nic_t *enp, 147 __in unsigned int level); 148 149 void 150 ef10_intr_status_line( 151 __in efx_nic_t *enp, 152 __out boolean_t *fatalp, 153 __out uint32_t *qmaskp); 154 155 void 156 ef10_intr_status_message( 157 __in efx_nic_t *enp, 158 __in unsigned int message, 159 __out boolean_t *fatalp); 160 161 void 162 ef10_intr_fatal( 163 __in efx_nic_t *enp); 164 void 165 ef10_intr_fini( 166 __in efx_nic_t *enp); 167 168 /* NIC */ 169 170 extern __checkReturn efx_rc_t 171 ef10_nic_probe( 172 __in efx_nic_t *enp); 173 174 extern __checkReturn efx_rc_t 175 hunt_board_cfg( 176 __in efx_nic_t *enp); 177 178 extern __checkReturn efx_rc_t 179 ef10_nic_set_drv_limits( 180 __inout efx_nic_t *enp, 181 __in efx_drv_limits_t *edlp); 182 183 extern __checkReturn efx_rc_t 184 ef10_nic_get_vi_pool( 185 __in efx_nic_t *enp, 186 __out uint32_t *vi_countp); 187 188 extern __checkReturn efx_rc_t 189 ef10_nic_get_bar_region( 190 __in efx_nic_t *enp, 191 __in efx_nic_region_t region, 192 __out uint32_t *offsetp, 193 __out size_t *sizep); 194 195 extern __checkReturn efx_rc_t 196 ef10_nic_reset( 197 __in efx_nic_t *enp); 198 199 extern __checkReturn efx_rc_t 200 ef10_nic_init( 201 __in efx_nic_t *enp); 202 203 #if EFSYS_OPT_DIAG 204 205 extern __checkReturn efx_rc_t 206 ef10_nic_register_test( 207 __in efx_nic_t *enp); 208 209 #endif /* EFSYS_OPT_DIAG */ 210 211 extern void 212 ef10_nic_fini( 213 __in efx_nic_t *enp); 214 215 extern void 216 ef10_nic_unprobe( 217 __in efx_nic_t *enp); 218 219 220 /* MAC */ 221 222 extern __checkReturn efx_rc_t 223 ef10_mac_poll( 224 __in efx_nic_t *enp, 225 __out efx_link_mode_t *link_modep); 226 227 extern __checkReturn efx_rc_t 228 ef10_mac_up( 229 __in efx_nic_t *enp, 230 __out boolean_t *mac_upp); 231 232 extern __checkReturn efx_rc_t 233 ef10_mac_addr_set( 234 __in efx_nic_t *enp); 235 236 extern __checkReturn efx_rc_t 237 ef10_mac_reconfigure( 238 __in efx_nic_t *enp); 239 240 extern __checkReturn efx_rc_t 241 ef10_mac_multicast_list_set( 242 __in efx_nic_t *enp); 243 244 extern __checkReturn efx_rc_t 245 ef10_mac_filter_default_rxq_set( 246 __in efx_nic_t *enp, 247 __in efx_rxq_t *erp, 248 __in boolean_t using_rss); 249 250 extern void 251 ef10_mac_filter_default_rxq_clear( 252 __in efx_nic_t *enp); 253 254 #if EFSYS_OPT_LOOPBACK 255 256 extern __checkReturn efx_rc_t 257 ef10_mac_loopback_set( 258 __in efx_nic_t *enp, 259 __in efx_link_mode_t link_mode, 260 __in efx_loopback_type_t loopback_type); 261 262 #endif /* EFSYS_OPT_LOOPBACK */ 263 264 #if EFSYS_OPT_MAC_STATS 265 266 extern __checkReturn efx_rc_t 267 ef10_mac_stats_update( 268 __in efx_nic_t *enp, 269 __in efsys_mem_t *esmp, 270 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat, 271 __inout_opt uint32_t *generationp); 272 273 #endif /* EFSYS_OPT_MAC_STATS */ 274 275 276 /* MCDI */ 277 278 #if EFSYS_OPT_MCDI 279 280 extern __checkReturn efx_rc_t 281 ef10_mcdi_init( 282 __in efx_nic_t *enp, 283 __in const efx_mcdi_transport_t *mtp); 284 285 extern void 286 ef10_mcdi_fini( 287 __in efx_nic_t *enp); 288 289 extern void 290 ef10_mcdi_send_request( 291 __in efx_nic_t *enp, 292 __in void *hdrp, 293 __in size_t hdr_len, 294 __in void *sdup, 295 __in size_t sdu_len); 296 297 extern __checkReturn boolean_t 298 ef10_mcdi_poll_response( 299 __in efx_nic_t *enp); 300 301 extern void 302 ef10_mcdi_read_response( 303 __in efx_nic_t *enp, 304 __out_bcount(length) void *bufferp, 305 __in size_t offset, 306 __in size_t length); 307 308 extern efx_rc_t 309 ef10_mcdi_poll_reboot( 310 __in efx_nic_t *enp); 311 312 extern __checkReturn efx_rc_t 313 ef10_mcdi_feature_supported( 314 __in efx_nic_t *enp, 315 __in efx_mcdi_feature_id_t id, 316 __out boolean_t *supportedp); 317 318 #endif /* EFSYS_OPT_MCDI */ 319 320 /* NVRAM */ 321 322 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD 323 324 extern __checkReturn efx_rc_t 325 ef10_nvram_buf_read_tlv( 326 __in efx_nic_t *enp, 327 __in_bcount(max_seg_size) caddr_t seg_data, 328 __in size_t max_seg_size, 329 __in uint32_t tag, 330 __deref_out_bcount_opt(*sizep) caddr_t *datap, 331 __out size_t *sizep); 332 333 extern __checkReturn efx_rc_t 334 ef10_nvram_buf_write_tlv( 335 __inout_bcount(partn_size) caddr_t partn_data, 336 __in size_t partn_size, 337 __in uint32_t tag, 338 __in_bcount(tag_size) caddr_t tag_data, 339 __in size_t tag_size, 340 __out size_t *total_lengthp); 341 342 extern __checkReturn efx_rc_t 343 ef10_nvram_partn_read_tlv( 344 __in efx_nic_t *enp, 345 __in uint32_t partn, 346 __in uint32_t tag, 347 __deref_out_bcount_opt(*sizep) caddr_t *datap, 348 __out size_t *sizep); 349 350 extern __checkReturn efx_rc_t 351 ef10_nvram_partn_write_tlv( 352 __in efx_nic_t *enp, 353 __in uint32_t partn, 354 __in uint32_t tag, 355 __in_bcount(size) caddr_t data, 356 __in size_t size); 357 358 extern __checkReturn efx_rc_t 359 ef10_nvram_partn_write_segment_tlv( 360 __in efx_nic_t *enp, 361 __in uint32_t partn, 362 __in uint32_t tag, 363 __in_bcount(size) caddr_t data, 364 __in size_t size, 365 __in boolean_t all_segments); 366 367 extern __checkReturn efx_rc_t 368 ef10_nvram_partn_lock( 369 __in efx_nic_t *enp, 370 __in uint32_t partn); 371 372 extern __checkReturn efx_rc_t 373 ef10_nvram_partn_erase( 374 __in efx_nic_t *enp, 375 __in uint32_t partn, 376 __in unsigned int offset, 377 __in size_t size); 378 379 extern __checkReturn efx_rc_t 380 ef10_nvram_partn_write( 381 __in efx_nic_t *enp, 382 __in uint32_t partn, 383 __in unsigned int offset, 384 __out_bcount(size) caddr_t data, 385 __in size_t size); 386 387 extern void 388 ef10_nvram_partn_unlock( 389 __in efx_nic_t *enp, 390 __in uint32_t partn); 391 392 #endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */ 393 394 #if EFSYS_OPT_NVRAM 395 396 #if EFSYS_OPT_DIAG 397 398 extern __checkReturn efx_rc_t 399 ef10_nvram_test( 400 __in efx_nic_t *enp); 401 402 #endif /* EFSYS_OPT_DIAG */ 403 404 extern __checkReturn efx_rc_t 405 ef10_nvram_get_version( 406 __in efx_nic_t *enp, 407 __in efx_nvram_type_t type, 408 __out uint32_t *subtypep, 409 __out_ecount(4) uint16_t version[4]); 410 411 extern __checkReturn efx_rc_t 412 ef10_nvram_erase( 413 __in efx_nic_t *enp, 414 __in efx_nvram_type_t type); 415 416 extern __checkReturn efx_rc_t 417 ef10_nvram_write_chunk( 418 __in efx_nic_t *enp, 419 __in efx_nvram_type_t type, 420 __in unsigned int offset, 421 __in_bcount(size) caddr_t data, 422 __in size_t size); 423 424 extern void 425 ef10_nvram_rw_finish( 426 __in efx_nic_t *enp, 427 __in efx_nvram_type_t type); 428 429 extern __checkReturn efx_rc_t 430 ef10_nvram_partn_set_version( 431 __in efx_nic_t *enp, 432 __in uint32_t partn, 433 __in_ecount(4) uint16_t version[4]); 434 435 extern __checkReturn efx_rc_t 436 ef10_nvram_set_version( 437 __in efx_nic_t *enp, 438 __in efx_nvram_type_t type, 439 __in_ecount(4) uint16_t version[4]); 440 441 extern __checkReturn efx_rc_t 442 ef10_nvram_type_to_partn( 443 __in efx_nic_t *enp, 444 __in efx_nvram_type_t type, 445 __out uint32_t *partnp); 446 447 extern __checkReturn efx_rc_t 448 ef10_nvram_partn_size( 449 __in efx_nic_t *enp, 450 __in uint32_t partn, 451 __out size_t *sizep); 452 453 extern __checkReturn efx_rc_t 454 ef10_nvram_partn_rw_start( 455 __in efx_nic_t *enp, 456 __in uint32_t partn, 457 __out size_t *chunk_sizep); 458 459 extern __checkReturn efx_rc_t 460 ef10_nvram_partn_read( 461 __in efx_nic_t *enp, 462 __in uint32_t partn, 463 __in unsigned int offset, 464 __out_bcount(size) caddr_t data, 465 __in size_t size); 466 467 #endif /* EFSYS_OPT_NVRAM */ 468 469 470 /* PHY */ 471 472 typedef struct ef10_link_state_s { 473 uint32_t els_adv_cap_mask; 474 uint32_t els_lp_cap_mask; 475 unsigned int els_fcntl; 476 efx_link_mode_t els_link_mode; 477 #if EFSYS_OPT_LOOPBACK 478 efx_loopback_type_t els_loopback; 479 #endif 480 boolean_t els_mac_up; 481 } ef10_link_state_t; 482 483 extern void 484 ef10_phy_link_ev( 485 __in efx_nic_t *enp, 486 __in efx_qword_t *eqp, 487 __out efx_link_mode_t *link_modep); 488 489 extern __checkReturn efx_rc_t 490 ef10_phy_get_link( 491 __in efx_nic_t *enp, 492 __out ef10_link_state_t *elsp); 493 494 extern __checkReturn efx_rc_t 495 ef10_phy_power( 496 __in efx_nic_t *enp, 497 __in boolean_t on); 498 499 extern __checkReturn efx_rc_t 500 ef10_phy_reconfigure( 501 __in efx_nic_t *enp); 502 503 extern __checkReturn efx_rc_t 504 ef10_phy_verify( 505 __in efx_nic_t *enp); 506 507 extern __checkReturn efx_rc_t 508 ef10_phy_oui_get( 509 __in efx_nic_t *enp, 510 __out uint32_t *ouip); 511 512 #if EFSYS_OPT_PHY_STATS 513 514 extern __checkReturn efx_rc_t 515 ef10_phy_stats_update( 516 __in efx_nic_t *enp, 517 __in efsys_mem_t *esmp, 518 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat); 519 520 #endif /* EFSYS_OPT_PHY_STATS */ 521 522 #if EFSYS_OPT_PHY_PROPS 523 524 #if EFSYS_OPT_NAMES 525 526 extern const char * 527 ef10_phy_prop_name( 528 __in efx_nic_t *enp, 529 __in unsigned int id); 530 531 #endif /* EFSYS_OPT_NAMES */ 532 533 extern __checkReturn efx_rc_t 534 ef10_phy_prop_get( 535 __in efx_nic_t *enp, 536 __in unsigned int id, 537 __in uint32_t flags, 538 __out uint32_t *valp); 539 540 extern __checkReturn efx_rc_t 541 ef10_phy_prop_set( 542 __in efx_nic_t *enp, 543 __in unsigned int id, 544 __in uint32_t val); 545 546 #endif /* EFSYS_OPT_PHY_PROPS */ 547 548 #if EFSYS_OPT_BIST 549 550 extern __checkReturn efx_rc_t 551 hunt_bist_enable_offline( 552 __in efx_nic_t *enp); 553 554 extern __checkReturn efx_rc_t 555 hunt_bist_start( 556 __in efx_nic_t *enp, 557 __in efx_bist_type_t type); 558 559 extern __checkReturn efx_rc_t 560 hunt_bist_poll( 561 __in efx_nic_t *enp, 562 __in efx_bist_type_t type, 563 __out efx_bist_result_t *resultp, 564 __out_opt __drv_when(count > 0, __notnull) 565 uint32_t *value_maskp, 566 __out_ecount_opt(count) __drv_when(count > 0, __notnull) 567 unsigned long *valuesp, 568 __in size_t count); 569 570 extern void 571 hunt_bist_stop( 572 __in efx_nic_t *enp, 573 __in efx_bist_type_t type); 574 575 #endif /* EFSYS_OPT_BIST */ 576 577 578 /* SRAM */ 579 580 #if EFSYS_OPT_DIAG 581 582 extern __checkReturn efx_rc_t 583 ef10_sram_test( 584 __in efx_nic_t *enp, 585 __in efx_sram_pattern_fn_t func); 586 587 #endif /* EFSYS_OPT_DIAG */ 588 589 590 /* TX */ 591 592 extern __checkReturn efx_rc_t 593 ef10_tx_init( 594 __in efx_nic_t *enp); 595 596 extern void 597 ef10_tx_fini( 598 __in efx_nic_t *enp); 599 600 extern __checkReturn efx_rc_t 601 ef10_tx_qcreate( 602 __in efx_nic_t *enp, 603 __in unsigned int index, 604 __in unsigned int label, 605 __in efsys_mem_t *esmp, 606 __in size_t n, 607 __in uint32_t id, 608 __in uint16_t flags, 609 __in efx_evq_t *eep, 610 __in efx_txq_t *etp, 611 __out unsigned int *addedp); 612 613 extern void 614 ef10_tx_qdestroy( 615 __in efx_txq_t *etp); 616 617 extern __checkReturn efx_rc_t 618 ef10_tx_qpost( 619 __in efx_txq_t *etp, 620 __in_ecount(n) efx_buffer_t *eb, 621 __in unsigned int n, 622 __in unsigned int completed, 623 __inout unsigned int *addedp); 624 625 extern void 626 ef10_tx_qpush( 627 __in efx_txq_t *etp, 628 __in unsigned int added, 629 __in unsigned int pushed); 630 631 extern __checkReturn efx_rc_t 632 ef10_tx_qpace( 633 __in efx_txq_t *etp, 634 __in unsigned int ns); 635 636 extern __checkReturn efx_rc_t 637 ef10_tx_qflush( 638 __in efx_txq_t *etp); 639 640 extern void 641 ef10_tx_qenable( 642 __in efx_txq_t *etp); 643 644 extern __checkReturn efx_rc_t 645 ef10_tx_qpio_enable( 646 __in efx_txq_t *etp); 647 648 extern void 649 ef10_tx_qpio_disable( 650 __in efx_txq_t *etp); 651 652 extern __checkReturn efx_rc_t 653 ef10_tx_qpio_write( 654 __in efx_txq_t *etp, 655 __in_ecount(buf_length) uint8_t *buffer, 656 __in size_t buf_length, 657 __in size_t pio_buf_offset); 658 659 extern __checkReturn efx_rc_t 660 ef10_tx_qpio_post( 661 __in efx_txq_t *etp, 662 __in size_t pkt_length, 663 __in unsigned int completed, 664 __inout unsigned int *addedp); 665 666 extern __checkReturn efx_rc_t 667 ef10_tx_qdesc_post( 668 __in efx_txq_t *etp, 669 __in_ecount(n) efx_desc_t *ed, 670 __in unsigned int n, 671 __in unsigned int completed, 672 __inout unsigned int *addedp); 673 674 extern void 675 ef10_tx_qdesc_dma_create( 676 __in efx_txq_t *etp, 677 __in efsys_dma_addr_t addr, 678 __in size_t size, 679 __in boolean_t eop, 680 __out efx_desc_t *edp); 681 682 extern void 683 hunt_tx_qdesc_tso_create( 684 __in efx_txq_t *etp, 685 __in uint16_t ipv4_id, 686 __in uint32_t tcp_seq, 687 __in uint8_t tcp_flags, 688 __out efx_desc_t *edp); 689 690 extern void 691 ef10_tx_qdesc_tso2_create( 692 __in efx_txq_t *etp, 693 __in uint16_t ipv4_id, 694 __in uint32_t tcp_seq, 695 __in uint16_t tcp_mss, 696 __out_ecount(count) efx_desc_t *edp, 697 __in int count); 698 699 extern void 700 ef10_tx_qdesc_vlantci_create( 701 __in efx_txq_t *etp, 702 __in uint16_t vlan_tci, 703 __out efx_desc_t *edp); 704 705 706 #if EFSYS_OPT_QSTATS 707 708 extern void 709 ef10_tx_qstats_update( 710 __in efx_txq_t *etp, 711 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat); 712 713 #endif /* EFSYS_OPT_QSTATS */ 714 715 /* PIO */ 716 717 /* Missing register definitions */ 718 #ifndef ER_DZ_TX_PIOBUF_OFST 719 #define ER_DZ_TX_PIOBUF_OFST 0x00001000 720 #endif 721 #ifndef ER_DZ_TX_PIOBUF_STEP 722 #define ER_DZ_TX_PIOBUF_STEP 8192 723 #endif 724 #ifndef ER_DZ_TX_PIOBUF_ROWS 725 #define ER_DZ_TX_PIOBUF_ROWS 2048 726 #endif 727 728 #ifndef ER_DZ_TX_PIOBUF_SIZE 729 #define ER_DZ_TX_PIOBUF_SIZE 2048 730 #endif 731 732 #define HUNT_PIOBUF_NBUFS (16) 733 #define HUNT_PIOBUF_SIZE (ER_DZ_TX_PIOBUF_SIZE) 734 735 #define HUNT_MIN_PIO_ALLOC_SIZE (HUNT_PIOBUF_SIZE / 32) 736 737 #define EF10_LEGACY_PF_PRIVILEGE_MASK \ 738 (MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN | \ 739 MC_CMD_PRIVILEGE_MASK_IN_GRP_LINK | \ 740 MC_CMD_PRIVILEGE_MASK_IN_GRP_ONLOAD | \ 741 MC_CMD_PRIVILEGE_MASK_IN_GRP_PTP | \ 742 MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE_FILTERS | \ 743 MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING | \ 744 MC_CMD_PRIVILEGE_MASK_IN_GRP_UNICAST | \ 745 MC_CMD_PRIVILEGE_MASK_IN_GRP_MULTICAST | \ 746 MC_CMD_PRIVILEGE_MASK_IN_GRP_BROADCAST | \ 747 MC_CMD_PRIVILEGE_MASK_IN_GRP_ALL_MULTICAST | \ 748 MC_CMD_PRIVILEGE_MASK_IN_GRP_PROMISCUOUS) 749 750 #define EF10_LEGACY_VF_PRIVILEGE_MASK 0 751 752 typedef uint32_t efx_piobuf_handle_t; 753 754 #define EFX_PIOBUF_HANDLE_INVALID ((efx_piobuf_handle_t) -1) 755 756 extern __checkReturn efx_rc_t 757 ef10_nic_pio_alloc( 758 __inout efx_nic_t *enp, 759 __out uint32_t *bufnump, 760 __out efx_piobuf_handle_t *handlep, 761 __out uint32_t *blknump, 762 __out uint32_t *offsetp, 763 __out size_t *sizep); 764 765 extern __checkReturn efx_rc_t 766 ef10_nic_pio_free( 767 __inout efx_nic_t *enp, 768 __in uint32_t bufnum, 769 __in uint32_t blknum); 770 771 extern __checkReturn efx_rc_t 772 ef10_nic_pio_link( 773 __inout efx_nic_t *enp, 774 __in uint32_t vi_index, 775 __in efx_piobuf_handle_t handle); 776 777 extern __checkReturn efx_rc_t 778 ef10_nic_pio_unlink( 779 __inout efx_nic_t *enp, 780 __in uint32_t vi_index); 781 782 783 /* VPD */ 784 785 #if EFSYS_OPT_VPD 786 787 extern __checkReturn efx_rc_t 788 ef10_vpd_init( 789 __in efx_nic_t *enp); 790 791 extern __checkReturn efx_rc_t 792 ef10_vpd_size( 793 __in efx_nic_t *enp, 794 __out size_t *sizep); 795 796 extern __checkReturn efx_rc_t 797 ef10_vpd_read( 798 __in efx_nic_t *enp, 799 __out_bcount(size) caddr_t data, 800 __in size_t size); 801 802 extern __checkReturn efx_rc_t 803 ef10_vpd_verify( 804 __in efx_nic_t *enp, 805 __in_bcount(size) caddr_t data, 806 __in size_t size); 807 808 extern __checkReturn efx_rc_t 809 ef10_vpd_reinit( 810 __in efx_nic_t *enp, 811 __in_bcount(size) caddr_t data, 812 __in size_t size); 813 814 extern __checkReturn efx_rc_t 815 ef10_vpd_get( 816 __in efx_nic_t *enp, 817 __in_bcount(size) caddr_t data, 818 __in size_t size, 819 __inout efx_vpd_value_t *evvp); 820 821 extern __checkReturn efx_rc_t 822 ef10_vpd_set( 823 __in efx_nic_t *enp, 824 __in_bcount(size) caddr_t data, 825 __in size_t size, 826 __in efx_vpd_value_t *evvp); 827 828 extern __checkReturn efx_rc_t 829 ef10_vpd_next( 830 __in efx_nic_t *enp, 831 __in_bcount(size) caddr_t data, 832 __in size_t size, 833 __out efx_vpd_value_t *evvp, 834 __inout unsigned int *contp); 835 836 extern __checkReturn efx_rc_t 837 ef10_vpd_write( 838 __in efx_nic_t *enp, 839 __in_bcount(size) caddr_t data, 840 __in size_t size); 841 842 extern void 843 ef10_vpd_fini( 844 __in efx_nic_t *enp); 845 846 #endif /* EFSYS_OPT_VPD */ 847 848 849 /* RX */ 850 851 extern __checkReturn efx_rc_t 852 ef10_rx_init( 853 __in efx_nic_t *enp); 854 855 #if EFSYS_OPT_RX_SCATTER 856 extern __checkReturn efx_rc_t 857 ef10_rx_scatter_enable( 858 __in efx_nic_t *enp, 859 __in unsigned int buf_size); 860 #endif /* EFSYS_OPT_RX_SCATTER */ 861 862 863 #if EFSYS_OPT_RX_SCALE 864 865 extern __checkReturn efx_rc_t 866 ef10_rx_scale_mode_set( 867 __in efx_nic_t *enp, 868 __in efx_rx_hash_alg_t alg, 869 __in efx_rx_hash_type_t type, 870 __in boolean_t insert); 871 872 extern __checkReturn efx_rc_t 873 ef10_rx_scale_key_set( 874 __in efx_nic_t *enp, 875 __in_ecount(n) uint8_t *key, 876 __in size_t n); 877 878 extern __checkReturn efx_rc_t 879 ef10_rx_scale_tbl_set( 880 __in efx_nic_t *enp, 881 __in_ecount(n) unsigned int *table, 882 __in size_t n); 883 884 extern __checkReturn uint32_t 885 ef10_rx_prefix_hash( 886 __in efx_nic_t *enp, 887 __in efx_rx_hash_alg_t func, 888 __in uint8_t *buffer); 889 890 #endif /* EFSYS_OPT_RX_SCALE */ 891 892 extern __checkReturn efx_rc_t 893 ef10_rx_prefix_pktlen( 894 __in efx_nic_t *enp, 895 __in uint8_t *buffer, 896 __out uint16_t *lengthp); 897 898 extern void 899 ef10_rx_qpost( 900 __in efx_rxq_t *erp, 901 __in_ecount(n) efsys_dma_addr_t *addrp, 902 __in size_t size, 903 __in unsigned int n, 904 __in unsigned int completed, 905 __in unsigned int added); 906 907 extern void 908 ef10_rx_qpush( 909 __in efx_rxq_t *erp, 910 __in unsigned int added, 911 __inout unsigned int *pushedp); 912 913 extern __checkReturn efx_rc_t 914 ef10_rx_qflush( 915 __in efx_rxq_t *erp); 916 917 extern void 918 ef10_rx_qenable( 919 __in efx_rxq_t *erp); 920 921 extern __checkReturn efx_rc_t 922 ef10_rx_qcreate( 923 __in efx_nic_t *enp, 924 __in unsigned int index, 925 __in unsigned int label, 926 __in efx_rxq_type_t type, 927 __in efsys_mem_t *esmp, 928 __in size_t n, 929 __in uint32_t id, 930 __in efx_evq_t *eep, 931 __in efx_rxq_t *erp); 932 933 extern void 934 ef10_rx_qdestroy( 935 __in efx_rxq_t *erp); 936 937 extern void 938 ef10_rx_fini( 939 __in efx_nic_t *enp); 940 941 #if EFSYS_OPT_FILTER 942 943 typedef struct ef10_filter_handle_s { 944 uint32_t efh_lo; 945 uint32_t efh_hi; 946 } ef10_filter_handle_t; 947 948 typedef struct ef10_filter_entry_s { 949 uintptr_t efe_spec; /* pointer to filter spec plus busy bit */ 950 ef10_filter_handle_t efe_handle; 951 } ef10_filter_entry_t; 952 953 /* 954 * BUSY flag indicates that an update is in progress. 955 * AUTO_OLD flag is used to mark and sweep MAC packet filters. 956 */ 957 #define EFX_EF10_FILTER_FLAG_BUSY 1U 958 #define EFX_EF10_FILTER_FLAG_AUTO_OLD 2U 959 #define EFX_EF10_FILTER_FLAGS 3U 960 961 /* 962 * Size of the hash table used by the driver. Doesn't need to be the 963 * same size as the hardware's table. 964 */ 965 #define EFX_EF10_FILTER_TBL_ROWS 8192 966 967 /* Allow for the broadcast address to be added to the multicast list */ 968 #define EFX_EF10_FILTER_MULTICAST_FILTERS_MAX (EFX_MAC_MULTICAST_LIST_MAX + 1) 969 970 typedef struct ef10_filter_table_s { 971 ef10_filter_entry_t eft_entry[EFX_EF10_FILTER_TBL_ROWS]; 972 efx_rxq_t * eft_default_rxq; 973 boolean_t eft_using_rss; 974 uint32_t eft_unicst_filter_index; 975 boolean_t eft_unicst_filter_set; 976 uint32_t eft_mulcst_filter_indexes[ 977 EFX_EF10_FILTER_MULTICAST_FILTERS_MAX]; 978 uint32_t eft_mulcst_filter_count; 979 } ef10_filter_table_t; 980 981 __checkReturn efx_rc_t 982 ef10_filter_init( 983 __in efx_nic_t *enp); 984 985 void 986 ef10_filter_fini( 987 __in efx_nic_t *enp); 988 989 __checkReturn efx_rc_t 990 ef10_filter_restore( 991 __in efx_nic_t *enp); 992 993 __checkReturn efx_rc_t 994 ef10_filter_add( 995 __in efx_nic_t *enp, 996 __inout efx_filter_spec_t *spec, 997 __in boolean_t may_replace); 998 999 __checkReturn efx_rc_t 1000 ef10_filter_delete( 1001 __in efx_nic_t *enp, 1002 __inout efx_filter_spec_t *spec); 1003 1004 extern __checkReturn efx_rc_t 1005 ef10_filter_supported_filters( 1006 __in efx_nic_t *enp, 1007 __out uint32_t *list, 1008 __out size_t *length); 1009 1010 extern __checkReturn efx_rc_t 1011 ef10_filter_reconfigure( 1012 __in efx_nic_t *enp, 1013 __in_ecount(6) uint8_t const *mac_addr, 1014 __in boolean_t all_unicst, 1015 __in boolean_t mulcst, 1016 __in boolean_t all_mulcst, 1017 __in boolean_t brdcst, 1018 __in_ecount(6*count) uint8_t const *addrs, 1019 __in int count); 1020 1021 extern void 1022 ef10_filter_get_default_rxq( 1023 __in efx_nic_t *enp, 1024 __out efx_rxq_t **erpp, 1025 __out boolean_t *using_rss); 1026 1027 extern void 1028 ef10_filter_default_rxq_set( 1029 __in efx_nic_t *enp, 1030 __in efx_rxq_t *erp, 1031 __in boolean_t using_rss); 1032 1033 extern void 1034 ef10_filter_default_rxq_clear( 1035 __in efx_nic_t *enp); 1036 1037 1038 #endif /* EFSYS_OPT_FILTER */ 1039 1040 extern __checkReturn efx_rc_t 1041 efx_mcdi_get_function_info( 1042 __in efx_nic_t *enp, 1043 __out uint32_t *pfp, 1044 __out_opt uint32_t *vfp); 1045 1046 extern __checkReturn efx_rc_t 1047 efx_mcdi_privilege_mask( 1048 __in efx_nic_t *enp, 1049 __in uint32_t pf, 1050 __in uint32_t vf, 1051 __out uint32_t *maskp); 1052 1053 #ifdef __cplusplus 1054 } 1055 #endif 1056 1057 #endif /* _SYS_HUNT_IMPL_H */ 1058