1 /*- 2 * Copyright (c) 2012-2015 Solarflare Communications Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * The views and conclusions contained in the software and documentation are 27 * those of the authors and should not be interpreted as representing official 28 * policies, either expressed or implied, of the FreeBSD Project. 29 * 30 * $FreeBSD$ 31 */ 32 33 #ifndef _SYS_HUNT_IMPL_H 34 #define _SYS_HUNT_IMPL_H 35 36 #include "efx.h" 37 #include "efx_regs.h" 38 #include "efx_regs_ef10.h" 39 #include "efx_mcdi.h" 40 41 #ifdef __cplusplus 42 extern "C" { 43 #endif 44 45 /* 46 * FIXME: This is just a power of 2 which fits in an MCDI v1 message, and could 47 * possibly be increased, or the write size reported by newer firmware used 48 * instead. 49 */ 50 #define EF10_NVRAM_CHUNK 0x80 51 52 /* Alignment requirement for value written to RX WPTR: 53 * the WPTR must be aligned to an 8 descriptor boundary 54 */ 55 #define EF10_RX_WPTR_ALIGN 8 56 57 /* 58 * Max byte offset into the packet the TCP header must start for the hardware 59 * to be able to parse the packet correctly. 60 * FIXME: Move to ef10_impl.h when it is included in all driver builds. 61 */ 62 #define EF10_TCP_HEADER_OFFSET_LIMIT 208 63 64 /* Invalid RSS context handle */ 65 #define EF10_RSS_CONTEXT_INVALID (0xffffffff) 66 67 68 /* EV */ 69 70 __checkReturn efx_rc_t 71 ef10_ev_init( 72 __in efx_nic_t *enp); 73 74 void 75 ef10_ev_fini( 76 __in efx_nic_t *enp); 77 78 __checkReturn efx_rc_t 79 ef10_ev_qcreate( 80 __in efx_nic_t *enp, 81 __in unsigned int index, 82 __in efsys_mem_t *esmp, 83 __in size_t n, 84 __in uint32_t id, 85 __in efx_evq_t *eep); 86 87 void 88 ef10_ev_qdestroy( 89 __in efx_evq_t *eep); 90 91 __checkReturn efx_rc_t 92 ef10_ev_qprime( 93 __in efx_evq_t *eep, 94 __in unsigned int count); 95 96 void 97 ef10_ev_qpost( 98 __in efx_evq_t *eep, 99 __in uint16_t data); 100 101 __checkReturn efx_rc_t 102 ef10_ev_qmoderate( 103 __in efx_evq_t *eep, 104 __in unsigned int us); 105 106 #if EFSYS_OPT_QSTATS 107 void 108 ef10_ev_qstats_update( 109 __in efx_evq_t *eep, 110 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat); 111 #endif /* EFSYS_OPT_QSTATS */ 112 113 void 114 ef10_ev_rxlabel_init( 115 __in efx_evq_t *eep, 116 __in efx_rxq_t *erp, 117 __in unsigned int label); 118 119 void 120 ef10_ev_rxlabel_fini( 121 __in efx_evq_t *eep, 122 __in unsigned int label); 123 124 /* INTR */ 125 126 __checkReturn efx_rc_t 127 ef10_intr_init( 128 __in efx_nic_t *enp, 129 __in efx_intr_type_t type, 130 __in efsys_mem_t *esmp); 131 132 void 133 ef10_intr_enable( 134 __in efx_nic_t *enp); 135 136 void 137 ef10_intr_disable( 138 __in efx_nic_t *enp); 139 140 void 141 ef10_intr_disable_unlocked( 142 __in efx_nic_t *enp); 143 144 __checkReturn efx_rc_t 145 ef10_intr_trigger( 146 __in efx_nic_t *enp, 147 __in unsigned int level); 148 149 void 150 ef10_intr_status_line( 151 __in efx_nic_t *enp, 152 __out boolean_t *fatalp, 153 __out uint32_t *qmaskp); 154 155 void 156 ef10_intr_status_message( 157 __in efx_nic_t *enp, 158 __in unsigned int message, 159 __out boolean_t *fatalp); 160 161 void 162 ef10_intr_fatal( 163 __in efx_nic_t *enp); 164 void 165 ef10_intr_fini( 166 __in efx_nic_t *enp); 167 168 /* NIC */ 169 170 extern __checkReturn efx_rc_t 171 ef10_nic_probe( 172 __in efx_nic_t *enp); 173 174 extern __checkReturn efx_rc_t 175 hunt_board_cfg( 176 __in efx_nic_t *enp); 177 178 extern __checkReturn efx_rc_t 179 ef10_nic_set_drv_limits( 180 __inout efx_nic_t *enp, 181 __in efx_drv_limits_t *edlp); 182 183 extern __checkReturn efx_rc_t 184 ef10_nic_get_vi_pool( 185 __in efx_nic_t *enp, 186 __out uint32_t *vi_countp); 187 188 extern __checkReturn efx_rc_t 189 ef10_nic_get_bar_region( 190 __in efx_nic_t *enp, 191 __in efx_nic_region_t region, 192 __out uint32_t *offsetp, 193 __out size_t *sizep); 194 195 extern __checkReturn efx_rc_t 196 ef10_nic_reset( 197 __in efx_nic_t *enp); 198 199 extern __checkReturn efx_rc_t 200 ef10_nic_init( 201 __in efx_nic_t *enp); 202 203 #if EFSYS_OPT_DIAG 204 205 extern __checkReturn efx_rc_t 206 ef10_nic_register_test( 207 __in efx_nic_t *enp); 208 209 #endif /* EFSYS_OPT_DIAG */ 210 211 extern void 212 ef10_nic_fini( 213 __in efx_nic_t *enp); 214 215 extern void 216 ef10_nic_unprobe( 217 __in efx_nic_t *enp); 218 219 220 /* MAC */ 221 222 extern __checkReturn efx_rc_t 223 ef10_mac_poll( 224 __in efx_nic_t *enp, 225 __out efx_link_mode_t *link_modep); 226 227 extern __checkReturn efx_rc_t 228 ef10_mac_up( 229 __in efx_nic_t *enp, 230 __out boolean_t *mac_upp); 231 232 extern __checkReturn efx_rc_t 233 ef10_mac_addr_set( 234 __in efx_nic_t *enp); 235 236 extern __checkReturn efx_rc_t 237 ef10_mac_pdu_set( 238 __in efx_nic_t *enp); 239 240 extern __checkReturn efx_rc_t 241 ef10_mac_reconfigure( 242 __in efx_nic_t *enp); 243 244 extern __checkReturn efx_rc_t 245 ef10_mac_multicast_list_set( 246 __in efx_nic_t *enp); 247 248 extern __checkReturn efx_rc_t 249 ef10_mac_filter_default_rxq_set( 250 __in efx_nic_t *enp, 251 __in efx_rxq_t *erp, 252 __in boolean_t using_rss); 253 254 extern void 255 ef10_mac_filter_default_rxq_clear( 256 __in efx_nic_t *enp); 257 258 #if EFSYS_OPT_LOOPBACK 259 260 extern __checkReturn efx_rc_t 261 ef10_mac_loopback_set( 262 __in efx_nic_t *enp, 263 __in efx_link_mode_t link_mode, 264 __in efx_loopback_type_t loopback_type); 265 266 #endif /* EFSYS_OPT_LOOPBACK */ 267 268 #if EFSYS_OPT_MAC_STATS 269 270 extern __checkReturn efx_rc_t 271 ef10_mac_stats_update( 272 __in efx_nic_t *enp, 273 __in efsys_mem_t *esmp, 274 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat, 275 __inout_opt uint32_t *generationp); 276 277 #endif /* EFSYS_OPT_MAC_STATS */ 278 279 280 /* MCDI */ 281 282 #if EFSYS_OPT_MCDI 283 284 extern __checkReturn efx_rc_t 285 ef10_mcdi_init( 286 __in efx_nic_t *enp, 287 __in const efx_mcdi_transport_t *mtp); 288 289 extern void 290 ef10_mcdi_fini( 291 __in efx_nic_t *enp); 292 293 extern void 294 ef10_mcdi_send_request( 295 __in efx_nic_t *enp, 296 __in void *hdrp, 297 __in size_t hdr_len, 298 __in void *sdup, 299 __in size_t sdu_len); 300 301 extern __checkReturn boolean_t 302 ef10_mcdi_poll_response( 303 __in efx_nic_t *enp); 304 305 extern void 306 ef10_mcdi_read_response( 307 __in efx_nic_t *enp, 308 __out_bcount(length) void *bufferp, 309 __in size_t offset, 310 __in size_t length); 311 312 extern efx_rc_t 313 ef10_mcdi_poll_reboot( 314 __in efx_nic_t *enp); 315 316 extern __checkReturn efx_rc_t 317 ef10_mcdi_feature_supported( 318 __in efx_nic_t *enp, 319 __in efx_mcdi_feature_id_t id, 320 __out boolean_t *supportedp); 321 322 #endif /* EFSYS_OPT_MCDI */ 323 324 /* NVRAM */ 325 326 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD 327 328 extern __checkReturn efx_rc_t 329 ef10_nvram_buf_read_tlv( 330 __in efx_nic_t *enp, 331 __in_bcount(max_seg_size) caddr_t seg_data, 332 __in size_t max_seg_size, 333 __in uint32_t tag, 334 __deref_out_bcount_opt(*sizep) caddr_t *datap, 335 __out size_t *sizep); 336 337 extern __checkReturn efx_rc_t 338 ef10_nvram_buf_write_tlv( 339 __inout_bcount(partn_size) caddr_t partn_data, 340 __in size_t partn_size, 341 __in uint32_t tag, 342 __in_bcount(tag_size) caddr_t tag_data, 343 __in size_t tag_size, 344 __out size_t *total_lengthp); 345 346 extern __checkReturn efx_rc_t 347 ef10_nvram_partn_read_tlv( 348 __in efx_nic_t *enp, 349 __in uint32_t partn, 350 __in uint32_t tag, 351 __deref_out_bcount_opt(*sizep) caddr_t *datap, 352 __out size_t *sizep); 353 354 extern __checkReturn efx_rc_t 355 ef10_nvram_partn_write_tlv( 356 __in efx_nic_t *enp, 357 __in uint32_t partn, 358 __in uint32_t tag, 359 __in_bcount(size) caddr_t data, 360 __in size_t size); 361 362 extern __checkReturn efx_rc_t 363 ef10_nvram_partn_write_segment_tlv( 364 __in efx_nic_t *enp, 365 __in uint32_t partn, 366 __in uint32_t tag, 367 __in_bcount(size) caddr_t data, 368 __in size_t size, 369 __in boolean_t all_segments); 370 371 extern __checkReturn efx_rc_t 372 ef10_nvram_partn_lock( 373 __in efx_nic_t *enp, 374 __in uint32_t partn); 375 376 extern void 377 ef10_nvram_partn_unlock( 378 __in efx_nic_t *enp, 379 __in uint32_t partn); 380 381 #endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */ 382 383 #if EFSYS_OPT_NVRAM 384 385 #if EFSYS_OPT_DIAG 386 387 extern __checkReturn efx_rc_t 388 ef10_nvram_test( 389 __in efx_nic_t *enp); 390 391 #endif /* EFSYS_OPT_DIAG */ 392 393 extern __checkReturn efx_rc_t 394 ef10_nvram_type_to_partn( 395 __in efx_nic_t *enp, 396 __in efx_nvram_type_t type, 397 __out uint32_t *partnp); 398 399 extern __checkReturn efx_rc_t 400 ef10_nvram_partn_size( 401 __in efx_nic_t *enp, 402 __in uint32_t partn, 403 __out size_t *sizep); 404 405 extern __checkReturn efx_rc_t 406 ef10_nvram_partn_rw_start( 407 __in efx_nic_t *enp, 408 __in uint32_t partn, 409 __out size_t *chunk_sizep); 410 411 extern __checkReturn efx_rc_t 412 ef10_nvram_partn_read_mode( 413 __in efx_nic_t *enp, 414 __in uint32_t partn, 415 __in unsigned int offset, 416 __out_bcount(size) caddr_t data, 417 __in size_t size, 418 __in uint32_t mode); 419 420 extern __checkReturn efx_rc_t 421 ef10_nvram_partn_read( 422 __in efx_nic_t *enp, 423 __in uint32_t partn, 424 __in unsigned int offset, 425 __out_bcount(size) caddr_t data, 426 __in size_t size); 427 428 extern __checkReturn efx_rc_t 429 ef10_nvram_partn_erase( 430 __in efx_nic_t *enp, 431 __in uint32_t partn, 432 __in unsigned int offset, 433 __in size_t size); 434 435 extern __checkReturn efx_rc_t 436 ef10_nvram_partn_write( 437 __in efx_nic_t *enp, 438 __in uint32_t partn, 439 __in unsigned int offset, 440 __out_bcount(size) caddr_t data, 441 __in size_t size); 442 443 extern void 444 ef10_nvram_partn_rw_finish( 445 __in efx_nic_t *enp, 446 __in uint32_t partn); 447 448 extern __checkReturn efx_rc_t 449 ef10_nvram_partn_get_version( 450 __in efx_nic_t *enp, 451 __in uint32_t partn, 452 __out uint32_t *subtypep, 453 __out_ecount(4) uint16_t version[4]); 454 455 extern __checkReturn efx_rc_t 456 ef10_nvram_partn_set_version( 457 __in efx_nic_t *enp, 458 __in uint32_t partn, 459 __in_ecount(4) uint16_t version[4]); 460 461 #endif /* EFSYS_OPT_NVRAM */ 462 463 464 /* PHY */ 465 466 typedef struct ef10_link_state_s { 467 uint32_t els_adv_cap_mask; 468 uint32_t els_lp_cap_mask; 469 unsigned int els_fcntl; 470 efx_link_mode_t els_link_mode; 471 #if EFSYS_OPT_LOOPBACK 472 efx_loopback_type_t els_loopback; 473 #endif 474 boolean_t els_mac_up; 475 } ef10_link_state_t; 476 477 extern void 478 ef10_phy_link_ev( 479 __in efx_nic_t *enp, 480 __in efx_qword_t *eqp, 481 __out efx_link_mode_t *link_modep); 482 483 extern __checkReturn efx_rc_t 484 ef10_phy_get_link( 485 __in efx_nic_t *enp, 486 __out ef10_link_state_t *elsp); 487 488 extern __checkReturn efx_rc_t 489 ef10_phy_power( 490 __in efx_nic_t *enp, 491 __in boolean_t on); 492 493 extern __checkReturn efx_rc_t 494 ef10_phy_reconfigure( 495 __in efx_nic_t *enp); 496 497 extern __checkReturn efx_rc_t 498 ef10_phy_verify( 499 __in efx_nic_t *enp); 500 501 extern __checkReturn efx_rc_t 502 ef10_phy_oui_get( 503 __in efx_nic_t *enp, 504 __out uint32_t *ouip); 505 506 #if EFSYS_OPT_PHY_STATS 507 508 extern __checkReturn efx_rc_t 509 ef10_phy_stats_update( 510 __in efx_nic_t *enp, 511 __in efsys_mem_t *esmp, 512 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat); 513 514 #endif /* EFSYS_OPT_PHY_STATS */ 515 516 #if EFSYS_OPT_PHY_PROPS 517 518 #if EFSYS_OPT_NAMES 519 520 extern const char * 521 ef10_phy_prop_name( 522 __in efx_nic_t *enp, 523 __in unsigned int id); 524 525 #endif /* EFSYS_OPT_NAMES */ 526 527 extern __checkReturn efx_rc_t 528 ef10_phy_prop_get( 529 __in efx_nic_t *enp, 530 __in unsigned int id, 531 __in uint32_t flags, 532 __out uint32_t *valp); 533 534 extern __checkReturn efx_rc_t 535 ef10_phy_prop_set( 536 __in efx_nic_t *enp, 537 __in unsigned int id, 538 __in uint32_t val); 539 540 #endif /* EFSYS_OPT_PHY_PROPS */ 541 542 #if EFSYS_OPT_BIST 543 544 extern __checkReturn efx_rc_t 545 hunt_bist_enable_offline( 546 __in efx_nic_t *enp); 547 548 extern __checkReturn efx_rc_t 549 hunt_bist_start( 550 __in efx_nic_t *enp, 551 __in efx_bist_type_t type); 552 553 extern __checkReturn efx_rc_t 554 hunt_bist_poll( 555 __in efx_nic_t *enp, 556 __in efx_bist_type_t type, 557 __out efx_bist_result_t *resultp, 558 __out_opt __drv_when(count > 0, __notnull) 559 uint32_t *value_maskp, 560 __out_ecount_opt(count) __drv_when(count > 0, __notnull) 561 unsigned long *valuesp, 562 __in size_t count); 563 564 extern void 565 hunt_bist_stop( 566 __in efx_nic_t *enp, 567 __in efx_bist_type_t type); 568 569 #endif /* EFSYS_OPT_BIST */ 570 571 572 /* SRAM */ 573 574 #if EFSYS_OPT_DIAG 575 576 extern __checkReturn efx_rc_t 577 ef10_sram_test( 578 __in efx_nic_t *enp, 579 __in efx_sram_pattern_fn_t func); 580 581 #endif /* EFSYS_OPT_DIAG */ 582 583 584 /* TX */ 585 586 extern __checkReturn efx_rc_t 587 ef10_tx_init( 588 __in efx_nic_t *enp); 589 590 extern void 591 ef10_tx_fini( 592 __in efx_nic_t *enp); 593 594 extern __checkReturn efx_rc_t 595 ef10_tx_qcreate( 596 __in efx_nic_t *enp, 597 __in unsigned int index, 598 __in unsigned int label, 599 __in efsys_mem_t *esmp, 600 __in size_t n, 601 __in uint32_t id, 602 __in uint16_t flags, 603 __in efx_evq_t *eep, 604 __in efx_txq_t *etp, 605 __out unsigned int *addedp); 606 607 extern void 608 ef10_tx_qdestroy( 609 __in efx_txq_t *etp); 610 611 extern __checkReturn efx_rc_t 612 ef10_tx_qpost( 613 __in efx_txq_t *etp, 614 __in_ecount(n) efx_buffer_t *eb, 615 __in unsigned int n, 616 __in unsigned int completed, 617 __inout unsigned int *addedp); 618 619 extern void 620 ef10_tx_qpush( 621 __in efx_txq_t *etp, 622 __in unsigned int added, 623 __in unsigned int pushed); 624 625 extern __checkReturn efx_rc_t 626 ef10_tx_qpace( 627 __in efx_txq_t *etp, 628 __in unsigned int ns); 629 630 extern __checkReturn efx_rc_t 631 ef10_tx_qflush( 632 __in efx_txq_t *etp); 633 634 extern void 635 ef10_tx_qenable( 636 __in efx_txq_t *etp); 637 638 extern __checkReturn efx_rc_t 639 ef10_tx_qpio_enable( 640 __in efx_txq_t *etp); 641 642 extern void 643 ef10_tx_qpio_disable( 644 __in efx_txq_t *etp); 645 646 extern __checkReturn efx_rc_t 647 ef10_tx_qpio_write( 648 __in efx_txq_t *etp, 649 __in_ecount(buf_length) uint8_t *buffer, 650 __in size_t buf_length, 651 __in size_t pio_buf_offset); 652 653 extern __checkReturn efx_rc_t 654 ef10_tx_qpio_post( 655 __in efx_txq_t *etp, 656 __in size_t pkt_length, 657 __in unsigned int completed, 658 __inout unsigned int *addedp); 659 660 extern __checkReturn efx_rc_t 661 ef10_tx_qdesc_post( 662 __in efx_txq_t *etp, 663 __in_ecount(n) efx_desc_t *ed, 664 __in unsigned int n, 665 __in unsigned int completed, 666 __inout unsigned int *addedp); 667 668 extern void 669 ef10_tx_qdesc_dma_create( 670 __in efx_txq_t *etp, 671 __in efsys_dma_addr_t addr, 672 __in size_t size, 673 __in boolean_t eop, 674 __out efx_desc_t *edp); 675 676 extern void 677 hunt_tx_qdesc_tso_create( 678 __in efx_txq_t *etp, 679 __in uint16_t ipv4_id, 680 __in uint32_t tcp_seq, 681 __in uint8_t tcp_flags, 682 __out efx_desc_t *edp); 683 684 extern void 685 ef10_tx_qdesc_tso2_create( 686 __in efx_txq_t *etp, 687 __in uint16_t ipv4_id, 688 __in uint32_t tcp_seq, 689 __in uint16_t tcp_mss, 690 __out_ecount(count) efx_desc_t *edp, 691 __in int count); 692 693 extern void 694 ef10_tx_qdesc_vlantci_create( 695 __in efx_txq_t *etp, 696 __in uint16_t vlan_tci, 697 __out efx_desc_t *edp); 698 699 700 #if EFSYS_OPT_QSTATS 701 702 extern void 703 ef10_tx_qstats_update( 704 __in efx_txq_t *etp, 705 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat); 706 707 #endif /* EFSYS_OPT_QSTATS */ 708 709 /* PIO */ 710 711 /* Missing register definitions */ 712 #ifndef ER_DZ_TX_PIOBUF_OFST 713 #define ER_DZ_TX_PIOBUF_OFST 0x00001000 714 #endif 715 #ifndef ER_DZ_TX_PIOBUF_STEP 716 #define ER_DZ_TX_PIOBUF_STEP 8192 717 #endif 718 #ifndef ER_DZ_TX_PIOBUF_ROWS 719 #define ER_DZ_TX_PIOBUF_ROWS 2048 720 #endif 721 722 #ifndef ER_DZ_TX_PIOBUF_SIZE 723 #define ER_DZ_TX_PIOBUF_SIZE 2048 724 #endif 725 726 #define HUNT_PIOBUF_NBUFS (16) 727 #define HUNT_PIOBUF_SIZE (ER_DZ_TX_PIOBUF_SIZE) 728 729 #define HUNT_MIN_PIO_ALLOC_SIZE (HUNT_PIOBUF_SIZE / 32) 730 731 #define EF10_LEGACY_PF_PRIVILEGE_MASK \ 732 (MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN | \ 733 MC_CMD_PRIVILEGE_MASK_IN_GRP_LINK | \ 734 MC_CMD_PRIVILEGE_MASK_IN_GRP_ONLOAD | \ 735 MC_CMD_PRIVILEGE_MASK_IN_GRP_PTP | \ 736 MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE_FILTERS | \ 737 MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING | \ 738 MC_CMD_PRIVILEGE_MASK_IN_GRP_UNICAST | \ 739 MC_CMD_PRIVILEGE_MASK_IN_GRP_MULTICAST | \ 740 MC_CMD_PRIVILEGE_MASK_IN_GRP_BROADCAST | \ 741 MC_CMD_PRIVILEGE_MASK_IN_GRP_ALL_MULTICAST | \ 742 MC_CMD_PRIVILEGE_MASK_IN_GRP_PROMISCUOUS) 743 744 #define EF10_LEGACY_VF_PRIVILEGE_MASK 0 745 746 typedef uint32_t efx_piobuf_handle_t; 747 748 #define EFX_PIOBUF_HANDLE_INVALID ((efx_piobuf_handle_t) -1) 749 750 extern __checkReturn efx_rc_t 751 ef10_nic_pio_alloc( 752 __inout efx_nic_t *enp, 753 __out uint32_t *bufnump, 754 __out efx_piobuf_handle_t *handlep, 755 __out uint32_t *blknump, 756 __out uint32_t *offsetp, 757 __out size_t *sizep); 758 759 extern __checkReturn efx_rc_t 760 ef10_nic_pio_free( 761 __inout efx_nic_t *enp, 762 __in uint32_t bufnum, 763 __in uint32_t blknum); 764 765 extern __checkReturn efx_rc_t 766 ef10_nic_pio_link( 767 __inout efx_nic_t *enp, 768 __in uint32_t vi_index, 769 __in efx_piobuf_handle_t handle); 770 771 extern __checkReturn efx_rc_t 772 ef10_nic_pio_unlink( 773 __inout efx_nic_t *enp, 774 __in uint32_t vi_index); 775 776 777 /* VPD */ 778 779 #if EFSYS_OPT_VPD 780 781 extern __checkReturn efx_rc_t 782 ef10_vpd_init( 783 __in efx_nic_t *enp); 784 785 extern __checkReturn efx_rc_t 786 ef10_vpd_size( 787 __in efx_nic_t *enp, 788 __out size_t *sizep); 789 790 extern __checkReturn efx_rc_t 791 ef10_vpd_read( 792 __in efx_nic_t *enp, 793 __out_bcount(size) caddr_t data, 794 __in size_t size); 795 796 extern __checkReturn efx_rc_t 797 ef10_vpd_verify( 798 __in efx_nic_t *enp, 799 __in_bcount(size) caddr_t data, 800 __in size_t size); 801 802 extern __checkReturn efx_rc_t 803 ef10_vpd_reinit( 804 __in efx_nic_t *enp, 805 __in_bcount(size) caddr_t data, 806 __in size_t size); 807 808 extern __checkReturn efx_rc_t 809 ef10_vpd_get( 810 __in efx_nic_t *enp, 811 __in_bcount(size) caddr_t data, 812 __in size_t size, 813 __inout efx_vpd_value_t *evvp); 814 815 extern __checkReturn efx_rc_t 816 ef10_vpd_set( 817 __in efx_nic_t *enp, 818 __in_bcount(size) caddr_t data, 819 __in size_t size, 820 __in efx_vpd_value_t *evvp); 821 822 extern __checkReturn efx_rc_t 823 ef10_vpd_next( 824 __in efx_nic_t *enp, 825 __in_bcount(size) caddr_t data, 826 __in size_t size, 827 __out efx_vpd_value_t *evvp, 828 __inout unsigned int *contp); 829 830 extern __checkReturn efx_rc_t 831 ef10_vpd_write( 832 __in efx_nic_t *enp, 833 __in_bcount(size) caddr_t data, 834 __in size_t size); 835 836 extern void 837 ef10_vpd_fini( 838 __in efx_nic_t *enp); 839 840 #endif /* EFSYS_OPT_VPD */ 841 842 843 /* RX */ 844 845 extern __checkReturn efx_rc_t 846 ef10_rx_init( 847 __in efx_nic_t *enp); 848 849 #if EFSYS_OPT_RX_SCATTER 850 extern __checkReturn efx_rc_t 851 ef10_rx_scatter_enable( 852 __in efx_nic_t *enp, 853 __in unsigned int buf_size); 854 #endif /* EFSYS_OPT_RX_SCATTER */ 855 856 857 #if EFSYS_OPT_RX_SCALE 858 859 extern __checkReturn efx_rc_t 860 ef10_rx_scale_mode_set( 861 __in efx_nic_t *enp, 862 __in efx_rx_hash_alg_t alg, 863 __in efx_rx_hash_type_t type, 864 __in boolean_t insert); 865 866 extern __checkReturn efx_rc_t 867 ef10_rx_scale_key_set( 868 __in efx_nic_t *enp, 869 __in_ecount(n) uint8_t *key, 870 __in size_t n); 871 872 extern __checkReturn efx_rc_t 873 ef10_rx_scale_tbl_set( 874 __in efx_nic_t *enp, 875 __in_ecount(n) unsigned int *table, 876 __in size_t n); 877 878 extern __checkReturn uint32_t 879 ef10_rx_prefix_hash( 880 __in efx_nic_t *enp, 881 __in efx_rx_hash_alg_t func, 882 __in uint8_t *buffer); 883 884 #endif /* EFSYS_OPT_RX_SCALE */ 885 886 extern __checkReturn efx_rc_t 887 ef10_rx_prefix_pktlen( 888 __in efx_nic_t *enp, 889 __in uint8_t *buffer, 890 __out uint16_t *lengthp); 891 892 extern void 893 ef10_rx_qpost( 894 __in efx_rxq_t *erp, 895 __in_ecount(n) efsys_dma_addr_t *addrp, 896 __in size_t size, 897 __in unsigned int n, 898 __in unsigned int completed, 899 __in unsigned int added); 900 901 extern void 902 ef10_rx_qpush( 903 __in efx_rxq_t *erp, 904 __in unsigned int added, 905 __inout unsigned int *pushedp); 906 907 extern __checkReturn efx_rc_t 908 ef10_rx_qflush( 909 __in efx_rxq_t *erp); 910 911 extern void 912 ef10_rx_qenable( 913 __in efx_rxq_t *erp); 914 915 extern __checkReturn efx_rc_t 916 ef10_rx_qcreate( 917 __in efx_nic_t *enp, 918 __in unsigned int index, 919 __in unsigned int label, 920 __in efx_rxq_type_t type, 921 __in efsys_mem_t *esmp, 922 __in size_t n, 923 __in uint32_t id, 924 __in efx_evq_t *eep, 925 __in efx_rxq_t *erp); 926 927 extern void 928 ef10_rx_qdestroy( 929 __in efx_rxq_t *erp); 930 931 extern void 932 ef10_rx_fini( 933 __in efx_nic_t *enp); 934 935 #if EFSYS_OPT_FILTER 936 937 typedef struct ef10_filter_handle_s { 938 uint32_t efh_lo; 939 uint32_t efh_hi; 940 } ef10_filter_handle_t; 941 942 typedef struct ef10_filter_entry_s { 943 uintptr_t efe_spec; /* pointer to filter spec plus busy bit */ 944 ef10_filter_handle_t efe_handle; 945 } ef10_filter_entry_t; 946 947 /* 948 * BUSY flag indicates that an update is in progress. 949 * AUTO_OLD flag is used to mark and sweep MAC packet filters. 950 */ 951 #define EFX_EF10_FILTER_FLAG_BUSY 1U 952 #define EFX_EF10_FILTER_FLAG_AUTO_OLD 2U 953 #define EFX_EF10_FILTER_FLAGS 3U 954 955 /* 956 * Size of the hash table used by the driver. Doesn't need to be the 957 * same size as the hardware's table. 958 */ 959 #define EFX_EF10_FILTER_TBL_ROWS 8192 960 961 /* Allow for the broadcast address to be added to the multicast list */ 962 #define EFX_EF10_FILTER_MULTICAST_FILTERS_MAX (EFX_MAC_MULTICAST_LIST_MAX + 1) 963 964 typedef struct ef10_filter_table_s { 965 ef10_filter_entry_t eft_entry[EFX_EF10_FILTER_TBL_ROWS]; 966 efx_rxq_t * eft_default_rxq; 967 boolean_t eft_using_rss; 968 uint32_t eft_unicst_filter_index; 969 boolean_t eft_unicst_filter_set; 970 uint32_t eft_mulcst_filter_indexes[ 971 EFX_EF10_FILTER_MULTICAST_FILTERS_MAX]; 972 uint32_t eft_mulcst_filter_count; 973 } ef10_filter_table_t; 974 975 __checkReturn efx_rc_t 976 ef10_filter_init( 977 __in efx_nic_t *enp); 978 979 void 980 ef10_filter_fini( 981 __in efx_nic_t *enp); 982 983 __checkReturn efx_rc_t 984 ef10_filter_restore( 985 __in efx_nic_t *enp); 986 987 __checkReturn efx_rc_t 988 ef10_filter_add( 989 __in efx_nic_t *enp, 990 __inout efx_filter_spec_t *spec, 991 __in boolean_t may_replace); 992 993 __checkReturn efx_rc_t 994 ef10_filter_delete( 995 __in efx_nic_t *enp, 996 __inout efx_filter_spec_t *spec); 997 998 extern __checkReturn efx_rc_t 999 ef10_filter_supported_filters( 1000 __in efx_nic_t *enp, 1001 __out uint32_t *list, 1002 __out size_t *length); 1003 1004 extern __checkReturn efx_rc_t 1005 ef10_filter_reconfigure( 1006 __in efx_nic_t *enp, 1007 __in_ecount(6) uint8_t const *mac_addr, 1008 __in boolean_t all_unicst, 1009 __in boolean_t mulcst, 1010 __in boolean_t all_mulcst, 1011 __in boolean_t brdcst, 1012 __in_ecount(6*count) uint8_t const *addrs, 1013 __in int count); 1014 1015 extern void 1016 ef10_filter_get_default_rxq( 1017 __in efx_nic_t *enp, 1018 __out efx_rxq_t **erpp, 1019 __out boolean_t *using_rss); 1020 1021 extern void 1022 ef10_filter_default_rxq_set( 1023 __in efx_nic_t *enp, 1024 __in efx_rxq_t *erp, 1025 __in boolean_t using_rss); 1026 1027 extern void 1028 ef10_filter_default_rxq_clear( 1029 __in efx_nic_t *enp); 1030 1031 1032 #endif /* EFSYS_OPT_FILTER */ 1033 1034 extern __checkReturn efx_rc_t 1035 efx_mcdi_get_function_info( 1036 __in efx_nic_t *enp, 1037 __out uint32_t *pfp, 1038 __out_opt uint32_t *vfp); 1039 1040 extern __checkReturn efx_rc_t 1041 efx_mcdi_privilege_mask( 1042 __in efx_nic_t *enp, 1043 __in uint32_t pf, 1044 __in uint32_t vf, 1045 __out uint32_t *maskp); 1046 1047 #ifdef __cplusplus 1048 } 1049 #endif 1050 1051 #endif /* _SYS_HUNT_IMPL_H */ 1052