xref: /freebsd/sys/dev/sfxge/common/efx_regs_pci.h (revision e948693ed767ef8364d5fc71e363ed941432a6e8)
1 /*-
2  * Copyright 2007-2010 Solarflare Communications Inc.  All rights reserved.
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions
6  * are met:
7  * 1. Redistributions of source code must retain the above copyright
8  *    notice, this list of conditions and the following disclaimer.
9  * 2. Redistributions in binary form must reproduce the above copyright
10  *    notice, this list of conditions and the following disclaimer in the
11  *    documentation and/or other materials provided with the distribution.
12  *
13  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND
14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23  * SUCH DAMAGE.
24  */
25 
26 #ifndef	_SYS_EFX_REGS_PCI_H
27 #define	_SYS_EFX_REGS_PCI_H
28 
29 #ifdef	__cplusplus
30 extern "C" {
31 #endif
32 
33 /*
34  * PC_VEND_ID_REG(16bit):
35  * Vendor ID register
36  */
37 
38 #define	PCR_AZ_VEND_ID_REG 0x00000000
39 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
40 
41 #define	PCRF_AZ_VEND_ID_LBN 0
42 #define	PCRF_AZ_VEND_ID_WIDTH 16
43 
44 
45 /*
46  * PC_DEV_ID_REG(16bit):
47  * Device ID register
48  */
49 
50 #define	PCR_AZ_DEV_ID_REG 0x00000002
51 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
52 
53 #define	PCRF_AZ_DEV_ID_LBN 0
54 #define	PCRF_AZ_DEV_ID_WIDTH 16
55 
56 
57 /*
58  * PC_CMD_REG(16bit):
59  * Command register
60  */
61 
62 #define	PCR_AZ_CMD_REG 0x00000004
63 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
64 
65 #define	PCRF_AZ_INTX_DIS_LBN 10
66 #define	PCRF_AZ_INTX_DIS_WIDTH 1
67 #define	PCRF_AZ_FB2B_EN_LBN 9
68 #define	PCRF_AZ_FB2B_EN_WIDTH 1
69 #define	PCRF_AZ_SERR_EN_LBN 8
70 #define	PCRF_AZ_SERR_EN_WIDTH 1
71 #define	PCRF_AZ_IDSEL_CTL_LBN 7
72 #define	PCRF_AZ_IDSEL_CTL_WIDTH 1
73 #define	PCRF_AZ_PERR_EN_LBN 6
74 #define	PCRF_AZ_PERR_EN_WIDTH 1
75 #define	PCRF_AZ_VGA_PAL_SNP_LBN 5
76 #define	PCRF_AZ_VGA_PAL_SNP_WIDTH 1
77 #define	PCRF_AZ_MWI_EN_LBN 4
78 #define	PCRF_AZ_MWI_EN_WIDTH 1
79 #define	PCRF_AZ_SPEC_CYC_LBN 3
80 #define	PCRF_AZ_SPEC_CYC_WIDTH 1
81 #define	PCRF_AZ_MST_EN_LBN 2
82 #define	PCRF_AZ_MST_EN_WIDTH 1
83 #define	PCRF_AZ_MEM_EN_LBN 1
84 #define	PCRF_AZ_MEM_EN_WIDTH 1
85 #define	PCRF_AZ_IO_EN_LBN 0
86 #define	PCRF_AZ_IO_EN_WIDTH 1
87 
88 
89 /*
90  * PC_STAT_REG(16bit):
91  * Status register
92  */
93 
94 #define	PCR_AZ_STAT_REG 0x00000006
95 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
96 
97 #define	PCRF_AZ_DET_PERR_LBN 15
98 #define	PCRF_AZ_DET_PERR_WIDTH 1
99 #define	PCRF_AZ_SIG_SERR_LBN 14
100 #define	PCRF_AZ_SIG_SERR_WIDTH 1
101 #define	PCRF_AZ_GOT_MABRT_LBN 13
102 #define	PCRF_AZ_GOT_MABRT_WIDTH 1
103 #define	PCRF_AZ_GOT_TABRT_LBN 12
104 #define	PCRF_AZ_GOT_TABRT_WIDTH 1
105 #define	PCRF_AZ_SIG_TABRT_LBN 11
106 #define	PCRF_AZ_SIG_TABRT_WIDTH 1
107 #define	PCRF_AZ_DEVSEL_TIM_LBN 9
108 #define	PCRF_AZ_DEVSEL_TIM_WIDTH 2
109 #define	PCRF_AZ_MDAT_PERR_LBN 8
110 #define	PCRF_AZ_MDAT_PERR_WIDTH 1
111 #define	PCRF_AZ_FB2B_CAP_LBN 7
112 #define	PCRF_AZ_FB2B_CAP_WIDTH 1
113 #define	PCRF_AZ_66MHZ_CAP_LBN 5
114 #define	PCRF_AZ_66MHZ_CAP_WIDTH 1
115 #define	PCRF_AZ_CAP_LIST_LBN 4
116 #define	PCRF_AZ_CAP_LIST_WIDTH 1
117 #define	PCRF_AZ_INTX_STAT_LBN 3
118 #define	PCRF_AZ_INTX_STAT_WIDTH 1
119 
120 
121 /*
122  * PC_REV_ID_REG(8bit):
123  * Class code & revision ID register
124  */
125 
126 #define	PCR_AZ_REV_ID_REG 0x00000008
127 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
128 
129 #define	PCRF_AZ_REV_ID_LBN 0
130 #define	PCRF_AZ_REV_ID_WIDTH 8
131 
132 
133 /*
134  * PC_CC_REG(24bit):
135  * Class code register
136  */
137 
138 #define	PCR_AZ_CC_REG 0x00000009
139 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
140 
141 #define	PCRF_AZ_BASE_CC_LBN 16
142 #define	PCRF_AZ_BASE_CC_WIDTH 8
143 #define	PCRF_AZ_SUB_CC_LBN 8
144 #define	PCRF_AZ_SUB_CC_WIDTH 8
145 #define	PCRF_AZ_PROG_IF_LBN 0
146 #define	PCRF_AZ_PROG_IF_WIDTH 8
147 
148 
149 /*
150  * PC_CACHE_LSIZE_REG(8bit):
151  * Cache line size
152  */
153 
154 #define	PCR_AZ_CACHE_LSIZE_REG 0x0000000c
155 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
156 
157 #define	PCRF_AZ_CACHE_LSIZE_LBN 0
158 #define	PCRF_AZ_CACHE_LSIZE_WIDTH 8
159 
160 
161 /*
162  * PC_MST_LAT_REG(8bit):
163  * Master latency timer register
164  */
165 
166 #define	PCR_AZ_MST_LAT_REG 0x0000000d
167 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
168 
169 #define	PCRF_AZ_MST_LAT_LBN 0
170 #define	PCRF_AZ_MST_LAT_WIDTH 8
171 
172 
173 /*
174  * PC_HDR_TYPE_REG(8bit):
175  * Header type register
176  */
177 
178 #define	PCR_AZ_HDR_TYPE_REG 0x0000000e
179 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
180 
181 #define	PCRF_AZ_MULT_FUNC_LBN 7
182 #define	PCRF_AZ_MULT_FUNC_WIDTH 1
183 #define	PCRF_AZ_TYPE_LBN 0
184 #define	PCRF_AZ_TYPE_WIDTH 7
185 
186 
187 /*
188  * PC_BIST_REG(8bit):
189  * BIST register
190  */
191 
192 #define	PCR_AZ_BIST_REG 0x0000000f
193 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
194 
195 #define	PCRF_AZ_BIST_LBN 0
196 #define	PCRF_AZ_BIST_WIDTH 8
197 
198 
199 /*
200  * PC_BAR0_REG(32bit):
201  * Primary function base address register 0
202  */
203 
204 #define	PCR_AZ_BAR0_REG 0x00000010
205 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
206 
207 #define	PCRF_AZ_BAR0_LBN 4
208 #define	PCRF_AZ_BAR0_WIDTH 28
209 #define	PCRF_AZ_BAR0_PREF_LBN 3
210 #define	PCRF_AZ_BAR0_PREF_WIDTH 1
211 #define	PCRF_AZ_BAR0_TYPE_LBN 1
212 #define	PCRF_AZ_BAR0_TYPE_WIDTH 2
213 #define	PCRF_AZ_BAR0_IOM_LBN 0
214 #define	PCRF_AZ_BAR0_IOM_WIDTH 1
215 
216 
217 /*
218  * PC_BAR1_REG(32bit):
219  * Primary function base address register 1, BAR1 is not implemented so read only.
220  */
221 
222 #define	PCR_DZ_BAR1_REG 0x00000014
223 /* hunta0=pci_f0_config */
224 
225 #define	PCRF_DZ_BAR1_LBN 0
226 #define	PCRF_DZ_BAR1_WIDTH 32
227 
228 
229 /*
230  * PC_BAR2_LO_REG(32bit):
231  * Primary function base address register 2 low bits
232  */
233 
234 #define	PCR_AZ_BAR2_LO_REG 0x00000018
235 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
236 
237 #define	PCRF_AZ_BAR2_LO_LBN 4
238 #define	PCRF_AZ_BAR2_LO_WIDTH 28
239 #define	PCRF_AZ_BAR2_PREF_LBN 3
240 #define	PCRF_AZ_BAR2_PREF_WIDTH 1
241 #define	PCRF_AZ_BAR2_TYPE_LBN 1
242 #define	PCRF_AZ_BAR2_TYPE_WIDTH 2
243 #define	PCRF_AZ_BAR2_IOM_LBN 0
244 #define	PCRF_AZ_BAR2_IOM_WIDTH 1
245 
246 
247 /*
248  * PC_BAR2_HI_REG(32bit):
249  * Primary function base address register 2 high bits
250  */
251 
252 #define	PCR_AZ_BAR2_HI_REG 0x0000001c
253 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
254 
255 #define	PCRF_AZ_BAR2_HI_LBN 0
256 #define	PCRF_AZ_BAR2_HI_WIDTH 32
257 
258 
259 /*
260  * PC_BAR4_LO_REG(32bit):
261  * Primary function base address register 2 low bits
262  */
263 
264 #define	PCR_CZ_BAR4_LO_REG 0x00000020
265 /* sienaa0,hunta0=pci_f0_config */
266 
267 #define	PCRF_CZ_BAR4_LO_LBN 4
268 #define	PCRF_CZ_BAR4_LO_WIDTH 28
269 #define	PCRF_CZ_BAR4_PREF_LBN 3
270 #define	PCRF_CZ_BAR4_PREF_WIDTH 1
271 #define	PCRF_CZ_BAR4_TYPE_LBN 1
272 #define	PCRF_CZ_BAR4_TYPE_WIDTH 2
273 #define	PCRF_CZ_BAR4_IOM_LBN 0
274 #define	PCRF_CZ_BAR4_IOM_WIDTH 1
275 
276 
277 /*
278  * PC_BAR4_HI_REG(32bit):
279  * Primary function base address register 2 high bits
280  */
281 
282 #define	PCR_CZ_BAR4_HI_REG 0x00000024
283 /* sienaa0,hunta0=pci_f0_config */
284 
285 #define	PCRF_CZ_BAR4_HI_LBN 0
286 #define	PCRF_CZ_BAR4_HI_WIDTH 32
287 
288 
289 /*
290  * PC_SS_VEND_ID_REG(16bit):
291  * Sub-system vendor ID register
292  */
293 
294 #define	PCR_AZ_SS_VEND_ID_REG 0x0000002c
295 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
296 
297 #define	PCRF_AZ_SS_VEND_ID_LBN 0
298 #define	PCRF_AZ_SS_VEND_ID_WIDTH 16
299 
300 
301 /*
302  * PC_SS_ID_REG(16bit):
303  * Sub-system ID register
304  */
305 
306 #define	PCR_AZ_SS_ID_REG 0x0000002e
307 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
308 
309 #define	PCRF_AZ_SS_ID_LBN 0
310 #define	PCRF_AZ_SS_ID_WIDTH 16
311 
312 
313 /*
314  * PC_EXPROM_BAR_REG(32bit):
315  * Expansion ROM base address register
316  */
317 
318 #define	PCR_AZ_EXPROM_BAR_REG 0x00000030
319 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
320 
321 #define	PCRF_AZ_EXPROM_BAR_LBN 11
322 #define	PCRF_AZ_EXPROM_BAR_WIDTH 21
323 #define	PCRF_AB_EXPROM_MIN_SIZE_LBN 2
324 #define	PCRF_AB_EXPROM_MIN_SIZE_WIDTH 9
325 #define	PCRF_CZ_EXPROM_MIN_SIZE_LBN 1
326 #define	PCRF_CZ_EXPROM_MIN_SIZE_WIDTH 10
327 #define	PCRF_AB_EXPROM_FEATURE_ENABLE_LBN 1
328 #define	PCRF_AB_EXPROM_FEATURE_ENABLE_WIDTH 1
329 #define	PCRF_AZ_EXPROM_EN_LBN 0
330 #define	PCRF_AZ_EXPROM_EN_WIDTH 1
331 
332 
333 /*
334  * PC_CAP_PTR_REG(8bit):
335  * Capability pointer register
336  */
337 
338 #define	PCR_AZ_CAP_PTR_REG 0x00000034
339 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
340 
341 #define	PCRF_AZ_CAP_PTR_LBN 0
342 #define	PCRF_AZ_CAP_PTR_WIDTH 8
343 
344 
345 /*
346  * PC_INT_LINE_REG(8bit):
347  * Interrupt line register
348  */
349 
350 #define	PCR_AZ_INT_LINE_REG 0x0000003c
351 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
352 
353 #define	PCRF_AZ_INT_LINE_LBN 0
354 #define	PCRF_AZ_INT_LINE_WIDTH 8
355 
356 
357 /*
358  * PC_INT_PIN_REG(8bit):
359  * Interrupt pin register
360  */
361 
362 #define	PCR_AZ_INT_PIN_REG 0x0000003d
363 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
364 
365 #define	PCRF_AZ_INT_PIN_LBN 0
366 #define	PCRF_AZ_INT_PIN_WIDTH 8
367 
368 
369 /*
370  * PC_PM_CAP_ID_REG(8bit):
371  * Power management capability ID
372  */
373 
374 #define	PCR_AC_PM_CAP_ID_REG 0x00000040
375 /* falcona0,falconb0,sienaa0=pci_f0_config */
376 
377 #define	PCR_DZ_PM_CAP_ID_REG 0x00000080
378 /* hunta0=pci_f0_config */
379 
380 #define	PCRF_AZ_PM_CAP_ID_LBN 0
381 #define	PCRF_AZ_PM_CAP_ID_WIDTH 8
382 
383 
384 /*
385  * PC_PM_NXT_PTR_REG(8bit):
386  * Power management next item pointer
387  */
388 
389 #define	PCR_AC_PM_NXT_PTR_REG 0x00000041
390 /* falcona0,falconb0,sienaa0=pci_f0_config */
391 
392 #define	PCR_DZ_PM_NXT_PTR_REG 0x00000081
393 /* hunta0=pci_f0_config */
394 
395 #define	PCRF_AZ_PM_NXT_PTR_LBN 0
396 #define	PCRF_AZ_PM_NXT_PTR_WIDTH 8
397 
398 
399 /*
400  * PC_PM_CAP_REG(16bit):
401  * Power management capabilities register
402  */
403 
404 #define	PCR_AC_PM_CAP_REG 0x00000042
405 /* falcona0,falconb0,sienaa0=pci_f0_config */
406 
407 #define	PCR_DZ_PM_CAP_REG 0x00000082
408 /* hunta0=pci_f0_config */
409 
410 #define	PCRF_AZ_PM_PME_SUPT_LBN 11
411 #define	PCRF_AZ_PM_PME_SUPT_WIDTH 5
412 #define	PCRF_AZ_PM_D2_SUPT_LBN 10
413 #define	PCRF_AZ_PM_D2_SUPT_WIDTH 1
414 #define	PCRF_AZ_PM_D1_SUPT_LBN 9
415 #define	PCRF_AZ_PM_D1_SUPT_WIDTH 1
416 #define	PCRF_AZ_PM_AUX_CURR_LBN 6
417 #define	PCRF_AZ_PM_AUX_CURR_WIDTH 3
418 #define	PCRF_AZ_PM_DSI_LBN 5
419 #define	PCRF_AZ_PM_DSI_WIDTH 1
420 #define	PCRF_AZ_PM_PME_CLK_LBN 3
421 #define	PCRF_AZ_PM_PME_CLK_WIDTH 1
422 #define	PCRF_AZ_PM_PME_VER_LBN 0
423 #define	PCRF_AZ_PM_PME_VER_WIDTH 3
424 
425 
426 /*
427  * PC_PM_CS_REG(16bit):
428  * Power management control & status register
429  */
430 
431 #define	PCR_AC_PM_CS_REG 0x00000044
432 /* falcona0,falconb0,sienaa0=pci_f0_config */
433 
434 #define	PCR_DZ_PM_CS_REG 0x00000084
435 /* hunta0=pci_f0_config */
436 
437 #define	PCRF_AZ_PM_PME_STAT_LBN 15
438 #define	PCRF_AZ_PM_PME_STAT_WIDTH 1
439 #define	PCRF_AZ_PM_DAT_SCALE_LBN 13
440 #define	PCRF_AZ_PM_DAT_SCALE_WIDTH 2
441 #define	PCRF_AZ_PM_DAT_SEL_LBN 9
442 #define	PCRF_AZ_PM_DAT_SEL_WIDTH 4
443 #define	PCRF_AZ_PM_PME_EN_LBN 8
444 #define	PCRF_AZ_PM_PME_EN_WIDTH 1
445 #define	PCRF_CZ_NO_SOFT_RESET_LBN 3
446 #define	PCRF_CZ_NO_SOFT_RESET_WIDTH 1
447 #define	PCRF_AZ_PM_PWR_ST_LBN 0
448 #define	PCRF_AZ_PM_PWR_ST_WIDTH 2
449 
450 
451 /*
452  * PC_MSI_CAP_ID_REG(8bit):
453  * MSI capability ID
454  */
455 
456 #define	PCR_AC_MSI_CAP_ID_REG 0x00000050
457 /* falcona0,falconb0,sienaa0=pci_f0_config */
458 
459 #define	PCR_DZ_MSI_CAP_ID_REG 0x00000090
460 /* hunta0=pci_f0_config */
461 
462 #define	PCRF_AZ_MSI_CAP_ID_LBN 0
463 #define	PCRF_AZ_MSI_CAP_ID_WIDTH 8
464 
465 
466 /*
467  * PC_MSI_NXT_PTR_REG(8bit):
468  * MSI next item pointer
469  */
470 
471 #define	PCR_AC_MSI_NXT_PTR_REG 0x00000051
472 /* falcona0,falconb0,sienaa0=pci_f0_config */
473 
474 #define	PCR_DZ_MSI_NXT_PTR_REG 0x00000091
475 /* hunta0=pci_f0_config */
476 
477 #define	PCRF_AZ_MSI_NXT_PTR_LBN 0
478 #define	PCRF_AZ_MSI_NXT_PTR_WIDTH 8
479 
480 
481 /*
482  * PC_MSI_CTL_REG(16bit):
483  * MSI control register
484  */
485 
486 #define	PCR_AC_MSI_CTL_REG 0x00000052
487 /* falcona0,falconb0,sienaa0=pci_f0_config */
488 
489 #define	PCR_DZ_MSI_CTL_REG 0x00000092
490 /* hunta0=pci_f0_config */
491 
492 #define	PCRF_AZ_MSI_64_EN_LBN 7
493 #define	PCRF_AZ_MSI_64_EN_WIDTH 1
494 #define	PCRF_AZ_MSI_MULT_MSG_EN_LBN 4
495 #define	PCRF_AZ_MSI_MULT_MSG_EN_WIDTH 3
496 #define	PCRF_AZ_MSI_MULT_MSG_CAP_LBN 1
497 #define	PCRF_AZ_MSI_MULT_MSG_CAP_WIDTH 3
498 #define	PCRF_AZ_MSI_EN_LBN 0
499 #define	PCRF_AZ_MSI_EN_WIDTH 1
500 
501 
502 /*
503  * PC_MSI_ADR_LO_REG(32bit):
504  * MSI low 32 bits address register
505  */
506 
507 #define	PCR_AC_MSI_ADR_LO_REG 0x00000054
508 /* falcona0,falconb0,sienaa0=pci_f0_config */
509 
510 #define	PCR_DZ_MSI_ADR_LO_REG 0x00000094
511 /* hunta0=pci_f0_config */
512 
513 #define	PCRF_AZ_MSI_ADR_LO_LBN 2
514 #define	PCRF_AZ_MSI_ADR_LO_WIDTH 30
515 
516 
517 /*
518  * PC_VPD_CAP_CTL_REG(8bit):
519  * VPD control and capabilities register
520  */
521 
522 #define	PCR_DZ_VPD_CAP_CTL_REG 0x00000054
523 /* hunta0=pci_f0_config */
524 
525 #define	PCR_CC_VPD_CAP_CTL_REG 0x000000d0
526 /* sienaa0=pci_f0_config */
527 
528 #define	PCRF_CZ_VPD_FLAG_LBN 31
529 #define	PCRF_CZ_VPD_FLAG_WIDTH 1
530 #define	PCRF_CZ_VPD_ADDR_LBN 16
531 #define	PCRF_CZ_VPD_ADDR_WIDTH 15
532 #define	PCRF_CZ_VPD_NXT_PTR_LBN 8
533 #define	PCRF_CZ_VPD_NXT_PTR_WIDTH 8
534 #define	PCRF_CZ_VPD_CAP_ID_LBN 0
535 #define	PCRF_CZ_VPD_CAP_ID_WIDTH 8
536 
537 
538 /*
539  * PC_VPD_CAP_DATA_REG(32bit):
540  * documentation to be written for sum_PC_VPD_CAP_DATA_REG
541  */
542 
543 #define	PCR_DZ_VPD_CAP_DATA_REG 0x00000058
544 /* hunta0=pci_f0_config */
545 
546 #define	PCR_AB_VPD_CAP_DATA_REG 0x000000b4
547 /* falcona0,falconb0=pci_f0_config */
548 
549 #define	PCR_CC_VPD_CAP_DATA_REG 0x000000d4
550 /* sienaa0=pci_f0_config */
551 
552 #define	PCRF_AZ_VPD_DATA_LBN 0
553 #define	PCRF_AZ_VPD_DATA_WIDTH 32
554 
555 
556 /*
557  * PC_MSI_ADR_HI_REG(32bit):
558  * MSI high 32 bits address register
559  */
560 
561 #define	PCR_AC_MSI_ADR_HI_REG 0x00000058
562 /* falcona0,falconb0,sienaa0=pci_f0_config */
563 
564 #define	PCR_DZ_MSI_ADR_HI_REG 0x00000098
565 /* hunta0=pci_f0_config */
566 
567 #define	PCRF_AZ_MSI_ADR_HI_LBN 0
568 #define	PCRF_AZ_MSI_ADR_HI_WIDTH 32
569 
570 
571 /*
572  * PC_MSI_DAT_REG(16bit):
573  * MSI data register
574  */
575 
576 #define	PCR_AC_MSI_DAT_REG 0x0000005c
577 /* falcona0,falconb0,sienaa0=pci_f0_config */
578 
579 #define	PCR_DZ_MSI_DAT_REG 0x0000009c
580 /* hunta0=pci_f0_config */
581 
582 #define	PCRF_AZ_MSI_DAT_LBN 0
583 #define	PCRF_AZ_MSI_DAT_WIDTH 16
584 
585 
586 /*
587  * PC_PCIE_CAP_LIST_REG(16bit):
588  * PCIe capability list register
589  */
590 
591 #define	PCR_AB_PCIE_CAP_LIST_REG 0x00000060
592 /* falcona0,falconb0=pci_f0_config */
593 
594 #define	PCR_CC_PCIE_CAP_LIST_REG 0x00000070
595 /* sienaa0=pci_f0_config */
596 
597 #define	PCR_DZ_PCIE_CAP_LIST_REG 0x000000c0
598 /* hunta0=pci_f0_config */
599 
600 #define	PCRF_AZ_PCIE_NXT_PTR_LBN 8
601 #define	PCRF_AZ_PCIE_NXT_PTR_WIDTH 8
602 #define	PCRF_AZ_PCIE_CAP_ID_LBN 0
603 #define	PCRF_AZ_PCIE_CAP_ID_WIDTH 8
604 
605 
606 /*
607  * PC_PCIE_CAP_REG(16bit):
608  * PCIe capability register
609  */
610 
611 #define	PCR_AB_PCIE_CAP_REG 0x00000062
612 /* falcona0,falconb0=pci_f0_config */
613 
614 #define	PCR_CC_PCIE_CAP_REG 0x00000072
615 /* sienaa0=pci_f0_config */
616 
617 #define	PCR_DZ_PCIE_CAP_REG 0x000000c2
618 /* hunta0=pci_f0_config */
619 
620 #define	PCRF_AZ_PCIE_INT_MSG_NUM_LBN 9
621 #define	PCRF_AZ_PCIE_INT_MSG_NUM_WIDTH 5
622 #define	PCRF_AZ_PCIE_SLOT_IMP_LBN 8
623 #define	PCRF_AZ_PCIE_SLOT_IMP_WIDTH 1
624 #define	PCRF_AZ_PCIE_DEV_PORT_TYPE_LBN 4
625 #define	PCRF_AZ_PCIE_DEV_PORT_TYPE_WIDTH 4
626 #define	PCRF_AZ_PCIE_CAP_VER_LBN 0
627 #define	PCRF_AZ_PCIE_CAP_VER_WIDTH 4
628 
629 
630 /*
631  * PC_DEV_CAP_REG(32bit):
632  * PCIe device capabilities register
633  */
634 
635 #define	PCR_AB_DEV_CAP_REG 0x00000064
636 /* falcona0,falconb0=pci_f0_config */
637 
638 #define	PCR_CC_DEV_CAP_REG 0x00000074
639 /* sienaa0=pci_f0_config */
640 
641 #define	PCR_DZ_DEV_CAP_REG 0x000000c4
642 /* hunta0=pci_f0_config */
643 
644 #define	PCRF_CZ_CAP_FN_LEVEL_RESET_LBN 28
645 #define	PCRF_CZ_CAP_FN_LEVEL_RESET_WIDTH 1
646 #define	PCRF_AZ_CAP_SLOT_PWR_SCL_LBN 26
647 #define	PCRF_AZ_CAP_SLOT_PWR_SCL_WIDTH 2
648 #define	PCRF_AZ_CAP_SLOT_PWR_VAL_LBN 18
649 #define	PCRF_AZ_CAP_SLOT_PWR_VAL_WIDTH 8
650 #define	PCRF_CZ_ROLE_BASE_ERR_REPORTING_LBN 15
651 #define	PCRF_CZ_ROLE_BASE_ERR_REPORTING_WIDTH 1
652 #define	PCRF_AB_PWR_IND_LBN 14
653 #define	PCRF_AB_PWR_IND_WIDTH 1
654 #define	PCRF_AB_ATTN_IND_LBN 13
655 #define	PCRF_AB_ATTN_IND_WIDTH 1
656 #define	PCRF_AB_ATTN_BUTTON_LBN 12
657 #define	PCRF_AB_ATTN_BUTTON_WIDTH 1
658 #define	PCRF_AZ_ENDPT_L1_LAT_LBN 9
659 #define	PCRF_AZ_ENDPT_L1_LAT_WIDTH 3
660 #define	PCRF_AZ_ENDPT_L0_LAT_LBN 6
661 #define	PCRF_AZ_ENDPT_L0_LAT_WIDTH 3
662 #define	PCRF_AZ_TAG_FIELD_LBN 5
663 #define	PCRF_AZ_TAG_FIELD_WIDTH 1
664 #define	PCRF_AZ_PHAN_FUNC_LBN 3
665 #define	PCRF_AZ_PHAN_FUNC_WIDTH 2
666 #define	PCRF_AZ_MAX_PAYL_SIZE_SUPT_LBN 0
667 #define	PCRF_AZ_MAX_PAYL_SIZE_SUPT_WIDTH 3
668 
669 
670 /*
671  * PC_DEV_CTL_REG(16bit):
672  * PCIe device control register
673  */
674 
675 #define	PCR_AB_DEV_CTL_REG 0x00000068
676 /* falcona0,falconb0=pci_f0_config */
677 
678 #define	PCR_CC_DEV_CTL_REG 0x00000078
679 /* sienaa0=pci_f0_config */
680 
681 #define	PCR_DZ_DEV_CTL_REG 0x000000c8
682 /* hunta0=pci_f0_config */
683 
684 #define	PCRF_CZ_FN_LEVEL_RESET_LBN 15
685 #define	PCRF_CZ_FN_LEVEL_RESET_WIDTH 1
686 #define	PCRF_AZ_MAX_RD_REQ_SIZE_LBN 12
687 #define	PCRF_AZ_MAX_RD_REQ_SIZE_WIDTH 3
688 #define	PCFE_AZ_MAX_RD_REQ_SIZE_4096 5
689 #define	PCFE_AZ_MAX_RD_REQ_SIZE_2048 4
690 #define	PCFE_AZ_MAX_RD_REQ_SIZE_1024 3
691 #define	PCFE_AZ_MAX_RD_REQ_SIZE_512 2
692 #define	PCFE_AZ_MAX_RD_REQ_SIZE_256 1
693 #define	PCFE_AZ_MAX_RD_REQ_SIZE_128 0
694 #define	PCFE_DZ_OTHER other
695 #define	PCRF_AZ_EN_NO_SNOOP_LBN 11
696 #define	PCRF_AZ_EN_NO_SNOOP_WIDTH 1
697 #define	PCRF_AZ_AUX_PWR_PM_EN_LBN 10
698 #define	PCRF_AZ_AUX_PWR_PM_EN_WIDTH 1
699 #define	PCRF_AZ_PHAN_FUNC_EN_LBN 9
700 #define	PCRF_AZ_PHAN_FUNC_EN_WIDTH 1
701 #define	PCRF_AB_DEV_CAP_REG_RSVD0_LBN 8
702 #define	PCRF_AB_DEV_CAP_REG_RSVD0_WIDTH 1
703 #define	PCRF_CZ_EXTENDED_TAG_EN_LBN 8
704 #define	PCRF_CZ_EXTENDED_TAG_EN_WIDTH 1
705 #define	PCRF_AZ_MAX_PAYL_SIZE_LBN 5
706 #define	PCRF_AZ_MAX_PAYL_SIZE_WIDTH 3
707 #define	PCFE_AZ_MAX_PAYL_SIZE_4096 5
708 #define	PCFE_AZ_MAX_PAYL_SIZE_2048 4
709 #define	PCFE_AZ_MAX_PAYL_SIZE_1024 3
710 #define	PCFE_AZ_MAX_PAYL_SIZE_512 2
711 #define	PCFE_AZ_MAX_PAYL_SIZE_256 1
712 #define	PCFE_AZ_MAX_PAYL_SIZE_128 0
713 #define	PCFE_DZ_OTHER other
714 #define	PCRF_AZ_EN_RELAX_ORDER_LBN 4
715 #define	PCRF_AZ_EN_RELAX_ORDER_WIDTH 1
716 #define	PCRF_AZ_UNSUP_REQ_RPT_EN_LBN 3
717 #define	PCRF_AZ_UNSUP_REQ_RPT_EN_WIDTH 1
718 #define	PCRF_AZ_FATAL_ERR_RPT_EN_LBN 2
719 #define	PCRF_AZ_FATAL_ERR_RPT_EN_WIDTH 1
720 #define	PCRF_AZ_NONFATAL_ERR_RPT_EN_LBN 1
721 #define	PCRF_AZ_NONFATAL_ERR_RPT_EN_WIDTH 1
722 #define	PCRF_AZ_CORR_ERR_RPT_EN_LBN 0
723 #define	PCRF_AZ_CORR_ERR_RPT_EN_WIDTH 1
724 
725 
726 /*
727  * PC_DEV_STAT_REG(16bit):
728  * PCIe device status register
729  */
730 
731 #define	PCR_AB_DEV_STAT_REG 0x0000006a
732 /* falcona0,falconb0=pci_f0_config */
733 
734 #define	PCR_CC_DEV_STAT_REG 0x0000007a
735 /* sienaa0=pci_f0_config */
736 
737 #define	PCR_DZ_DEV_STAT_REG 0x000000ca
738 /* hunta0=pci_f0_config */
739 
740 #define	PCRF_AZ_TRNS_PEND_LBN 5
741 #define	PCRF_AZ_TRNS_PEND_WIDTH 1
742 #define	PCRF_AZ_AUX_PWR_DET_LBN 4
743 #define	PCRF_AZ_AUX_PWR_DET_WIDTH 1
744 #define	PCRF_AZ_UNSUP_REQ_DET_LBN 3
745 #define	PCRF_AZ_UNSUP_REQ_DET_WIDTH 1
746 #define	PCRF_AZ_FATAL_ERR_DET_LBN 2
747 #define	PCRF_AZ_FATAL_ERR_DET_WIDTH 1
748 #define	PCRF_AZ_NONFATAL_ERR_DET_LBN 1
749 #define	PCRF_AZ_NONFATAL_ERR_DET_WIDTH 1
750 #define	PCRF_AZ_CORR_ERR_DET_LBN 0
751 #define	PCRF_AZ_CORR_ERR_DET_WIDTH 1
752 
753 
754 /*
755  * PC_LNK_CAP_REG(32bit):
756  * PCIe link capabilities register
757  */
758 
759 #define	PCR_AB_LNK_CAP_REG 0x0000006c
760 /* falcona0,falconb0=pci_f0_config */
761 
762 #define	PCR_CC_LNK_CAP_REG 0x0000007c
763 /* sienaa0=pci_f0_config */
764 
765 #define	PCR_DZ_LNK_CAP_REG 0x000000cc
766 /* hunta0=pci_f0_config */
767 
768 #define	PCRF_AZ_PORT_NUM_LBN 24
769 #define	PCRF_AZ_PORT_NUM_WIDTH 8
770 #define	PCRF_CZ_LINK_BWDITH_NOTIF_CAP_LBN 21
771 #define	PCRF_CZ_LINK_BWDITH_NOTIF_CAP_WIDTH 1
772 #define	PCRF_CZ_DATA_LINK_ACTIVE_RPT_CAP_LBN 20
773 #define	PCRF_CZ_DATA_LINK_ACTIVE_RPT_CAP_WIDTH 1
774 #define	PCRF_CZ_SURPISE_DOWN_RPT_CAP_LBN 19
775 #define	PCRF_CZ_SURPISE_DOWN_RPT_CAP_WIDTH 1
776 #define	PCRF_CZ_CLOCK_PWR_MNGMNT_CAP_LBN 18
777 #define	PCRF_CZ_CLOCK_PWR_MNGMNT_CAP_WIDTH 1
778 #define	PCRF_AZ_DEF_L1_EXIT_LAT_LBN 15
779 #define	PCRF_AZ_DEF_L1_EXIT_LAT_WIDTH 3
780 #define	PCRF_AZ_DEF_L0_EXIT_LATPORT_NUM_LBN 12
781 #define	PCRF_AZ_DEF_L0_EXIT_LATPORT_NUM_WIDTH 3
782 #define	PCRF_AZ_AS_LNK_PM_SUPT_LBN 10
783 #define	PCRF_AZ_AS_LNK_PM_SUPT_WIDTH 2
784 #define	PCRF_AZ_MAX_LNK_WIDTH_LBN 4
785 #define	PCRF_AZ_MAX_LNK_WIDTH_WIDTH 6
786 #define	PCRF_AZ_MAX_LNK_SP_LBN 0
787 #define	PCRF_AZ_MAX_LNK_SP_WIDTH 4
788 
789 
790 /*
791  * PC_LNK_CTL_REG(16bit):
792  * PCIe link control register
793  */
794 
795 #define	PCR_AB_LNK_CTL_REG 0x00000070
796 /* falcona0,falconb0=pci_f0_config */
797 
798 #define	PCR_CC_LNK_CTL_REG 0x00000080
799 /* sienaa0=pci_f0_config */
800 
801 #define	PCR_DZ_LNK_CTL_REG 0x000000d0
802 /* hunta0=pci_f0_config */
803 
804 #define	PCRF_AZ_EXT_SYNC_LBN 7
805 #define	PCRF_AZ_EXT_SYNC_WIDTH 1
806 #define	PCRF_AZ_COMM_CLK_CFG_LBN 6
807 #define	PCRF_AZ_COMM_CLK_CFG_WIDTH 1
808 #define	PCRF_AB_LNK_CTL_REG_RSVD0_LBN 5
809 #define	PCRF_AB_LNK_CTL_REG_RSVD0_WIDTH 1
810 #define	PCRF_CZ_LNK_RETRAIN_LBN 5
811 #define	PCRF_CZ_LNK_RETRAIN_WIDTH 1
812 #define	PCRF_AZ_LNK_DIS_LBN 4
813 #define	PCRF_AZ_LNK_DIS_WIDTH 1
814 #define	PCRF_AZ_RD_COM_BDRY_LBN 3
815 #define	PCRF_AZ_RD_COM_BDRY_WIDTH 1
816 #define	PCRF_AZ_ACT_ST_LNK_PM_CTL_LBN 0
817 #define	PCRF_AZ_ACT_ST_LNK_PM_CTL_WIDTH 2
818 
819 
820 /*
821  * PC_LNK_STAT_REG(16bit):
822  * PCIe link status register
823  */
824 
825 #define	PCR_AB_LNK_STAT_REG 0x00000072
826 /* falcona0,falconb0=pci_f0_config */
827 
828 #define	PCR_CC_LNK_STAT_REG 0x00000082
829 /* sienaa0=pci_f0_config */
830 
831 #define	PCR_DZ_LNK_STAT_REG 0x000000d2
832 /* hunta0=pci_f0_config */
833 
834 #define	PCRF_AZ_SLOT_CLK_CFG_LBN 12
835 #define	PCRF_AZ_SLOT_CLK_CFG_WIDTH 1
836 #define	PCRF_AZ_LNK_TRAIN_LBN 11
837 #define	PCRF_AZ_LNK_TRAIN_WIDTH 1
838 #define	PCRF_AB_TRAIN_ERR_LBN 10
839 #define	PCRF_AB_TRAIN_ERR_WIDTH 1
840 #define	PCRF_AZ_LNK_WIDTH_LBN 4
841 #define	PCRF_AZ_LNK_WIDTH_WIDTH 6
842 #define	PCRF_AZ_LNK_SP_LBN 0
843 #define	PCRF_AZ_LNK_SP_WIDTH 4
844 
845 
846 /*
847  * PC_SLOT_CAP_REG(32bit):
848  * PCIe slot capabilities register
849  */
850 
851 #define	PCR_AB_SLOT_CAP_REG 0x00000074
852 /* falcona0,falconb0=pci_f0_config */
853 
854 #define	PCRF_AB_SLOT_NUM_LBN 19
855 #define	PCRF_AB_SLOT_NUM_WIDTH 13
856 #define	PCRF_AB_SLOT_PWR_LIM_SCL_LBN 15
857 #define	PCRF_AB_SLOT_PWR_LIM_SCL_WIDTH 2
858 #define	PCRF_AB_SLOT_PWR_LIM_VAL_LBN 7
859 #define	PCRF_AB_SLOT_PWR_LIM_VAL_WIDTH 8
860 #define	PCRF_AB_SLOT_HP_CAP_LBN 6
861 #define	PCRF_AB_SLOT_HP_CAP_WIDTH 1
862 #define	PCRF_AB_SLOT_HP_SURP_LBN 5
863 #define	PCRF_AB_SLOT_HP_SURP_WIDTH 1
864 #define	PCRF_AB_SLOT_PWR_IND_PRST_LBN 4
865 #define	PCRF_AB_SLOT_PWR_IND_PRST_WIDTH 1
866 #define	PCRF_AB_SLOT_ATTN_IND_PRST_LBN 3
867 #define	PCRF_AB_SLOT_ATTN_IND_PRST_WIDTH 1
868 #define	PCRF_AB_SLOT_MRL_SENS_PRST_LBN 2
869 #define	PCRF_AB_SLOT_MRL_SENS_PRST_WIDTH 1
870 #define	PCRF_AB_SLOT_PWR_CTL_PRST_LBN 1
871 #define	PCRF_AB_SLOT_PWR_CTL_PRST_WIDTH 1
872 #define	PCRF_AB_SLOT_ATTN_BUT_PRST_LBN 0
873 #define	PCRF_AB_SLOT_ATTN_BUT_PRST_WIDTH 1
874 
875 
876 /*
877  * PC_SLOT_CTL_REG(16bit):
878  * PCIe slot control register
879  */
880 
881 #define	PCR_AB_SLOT_CTL_REG 0x00000078
882 /* falcona0,falconb0=pci_f0_config */
883 
884 #define	PCRF_AB_SLOT_PWR_CTLR_CTL_LBN 10
885 #define	PCRF_AB_SLOT_PWR_CTLR_CTL_WIDTH 1
886 #define	PCRF_AB_SLOT_PWR_IND_CTL_LBN 8
887 #define	PCRF_AB_SLOT_PWR_IND_CTL_WIDTH 2
888 #define	PCRF_AB_SLOT_ATT_IND_CTL_LBN 6
889 #define	PCRF_AB_SLOT_ATT_IND_CTL_WIDTH 2
890 #define	PCRF_AB_SLOT_HP_INT_EN_LBN 5
891 #define	PCRF_AB_SLOT_HP_INT_EN_WIDTH 1
892 #define	PCRF_AB_SLOT_CMD_COMP_INT_EN_LBN 4
893 #define	PCRF_AB_SLOT_CMD_COMP_INT_EN_WIDTH 1
894 #define	PCRF_AB_SLOT_PRES_DET_CHG_EN_LBN 3
895 #define	PCRF_AB_SLOT_PRES_DET_CHG_EN_WIDTH 1
896 #define	PCRF_AB_SLOT_MRL_SENS_CHG_EN_LBN 2
897 #define	PCRF_AB_SLOT_MRL_SENS_CHG_EN_WIDTH 1
898 #define	PCRF_AB_SLOT_PWR_FLTDET_EN_LBN 1
899 #define	PCRF_AB_SLOT_PWR_FLTDET_EN_WIDTH 1
900 #define	PCRF_AB_SLOT_ATTN_BUT_EN_LBN 0
901 #define	PCRF_AB_SLOT_ATTN_BUT_EN_WIDTH 1
902 
903 
904 /*
905  * PC_SLOT_STAT_REG(16bit):
906  * PCIe slot status register
907  */
908 
909 #define	PCR_AB_SLOT_STAT_REG 0x0000007a
910 /* falcona0,falconb0=pci_f0_config */
911 
912 #define	PCRF_AB_PRES_DET_ST_LBN 6
913 #define	PCRF_AB_PRES_DET_ST_WIDTH 1
914 #define	PCRF_AB_MRL_SENS_ST_LBN 5
915 #define	PCRF_AB_MRL_SENS_ST_WIDTH 1
916 #define	PCRF_AB_SLOT_PWR_IND_LBN 4
917 #define	PCRF_AB_SLOT_PWR_IND_WIDTH 1
918 #define	PCRF_AB_SLOT_ATTN_IND_LBN 3
919 #define	PCRF_AB_SLOT_ATTN_IND_WIDTH 1
920 #define	PCRF_AB_SLOT_MRL_SENS_LBN 2
921 #define	PCRF_AB_SLOT_MRL_SENS_WIDTH 1
922 #define	PCRF_AB_PWR_FLTDET_LBN 1
923 #define	PCRF_AB_PWR_FLTDET_WIDTH 1
924 #define	PCRF_AB_ATTN_BUTDET_LBN 0
925 #define	PCRF_AB_ATTN_BUTDET_WIDTH 1
926 
927 
928 /*
929  * PC_MSIX_CAP_ID_REG(8bit):
930  * MSIX Capability ID
931  */
932 
933 #define	PCR_BB_MSIX_CAP_ID_REG 0x00000090
934 /* falconb0=pci_f0_config */
935 
936 #define	PCR_CZ_MSIX_CAP_ID_REG 0x000000b0
937 /* sienaa0,hunta0=pci_f0_config */
938 
939 #define	PCRF_BZ_MSIX_CAP_ID_LBN 0
940 #define	PCRF_BZ_MSIX_CAP_ID_WIDTH 8
941 
942 
943 /*
944  * PC_MSIX_NXT_PTR_REG(8bit):
945  * MSIX Capability Next Capability Ptr
946  */
947 
948 #define	PCR_BB_MSIX_NXT_PTR_REG 0x00000091
949 /* falconb0=pci_f0_config */
950 
951 #define	PCR_CZ_MSIX_NXT_PTR_REG 0x000000b1
952 /* sienaa0,hunta0=pci_f0_config */
953 
954 #define	PCRF_BZ_MSIX_NXT_PTR_LBN 0
955 #define	PCRF_BZ_MSIX_NXT_PTR_WIDTH 8
956 
957 
958 /*
959  * PC_MSIX_CTL_REG(16bit):
960  * MSIX control register
961  */
962 
963 #define	PCR_BB_MSIX_CTL_REG 0x00000092
964 /* falconb0=pci_f0_config */
965 
966 #define	PCR_CZ_MSIX_CTL_REG 0x000000b2
967 /* sienaa0,hunta0=pci_f0_config */
968 
969 #define	PCRF_BZ_MSIX_EN_LBN 15
970 #define	PCRF_BZ_MSIX_EN_WIDTH 1
971 #define	PCRF_BZ_MSIX_FUNC_MASK_LBN 14
972 #define	PCRF_BZ_MSIX_FUNC_MASK_WIDTH 1
973 #define	PCRF_BZ_MSIX_TBL_SIZE_LBN 0
974 #define	PCRF_BZ_MSIX_TBL_SIZE_WIDTH 11
975 
976 
977 /*
978  * PC_DEV_CAP2_REG(16bit):
979  * PCIe Device Capabilities 2
980  */
981 
982 #define	PCR_CC_DEV_CAP2_REG 0x00000094
983 /* sienaa0=pci_f0_config */
984 
985 #define	PCR_DZ_DEV_CAP2_REG 0x000000e4
986 /* hunta0=pci_f0_config */
987 
988 #define	PCRF_CZ_CMPL_TIMEOUT_DIS_LBN 4
989 #define	PCRF_CZ_CMPL_TIMEOUT_DIS_WIDTH 1
990 #define	PCRF_CZ_CMPL_TIMEOUT_LBN 0
991 #define	PCRF_CZ_CMPL_TIMEOUT_WIDTH 4
992 #define	PCFE_CZ_CMPL_TIMEOUT_17000_TO_6400MS 14
993 #define	PCFE_CZ_CMPL_TIMEOUT_4000_TO_1300MS 13
994 #define	PCFE_CZ_CMPL_TIMEOUT_1000_TO_3500MS 10
995 #define	PCFE_CZ_CMPL_TIMEOUT_260_TO_900MS 9
996 #define	PCFE_CZ_CMPL_TIMEOUT_65_TO_210MS 6
997 #define	PCFE_CZ_CMPL_TIMEOUT_16_TO_55MS 5
998 #define	PCFE_CZ_CMPL_TIMEOUT_1_TO_10MS 2
999 #define	PCFE_CZ_CMPL_TIMEOUT_50_TO_100US 1
1000 #define	PCFE_CZ_CMPL_TIMEOUT_DEFAULT 0
1001 
1002 
1003 /*
1004  * PC_MSIX_TBL_BASE_REG(32bit):
1005  * MSIX Capability Vector Table Base
1006  */
1007 
1008 #define	PCR_BB_MSIX_TBL_BASE_REG 0x00000094
1009 /* falconb0=pci_f0_config */
1010 
1011 #define	PCR_CZ_MSIX_TBL_BASE_REG 0x000000b4
1012 /* sienaa0,hunta0=pci_f0_config */
1013 
1014 #define	PCRF_BZ_MSIX_TBL_OFF_LBN 3
1015 #define	PCRF_BZ_MSIX_TBL_OFF_WIDTH 29
1016 #define	PCRF_BZ_MSIX_TBL_BIR_LBN 0
1017 #define	PCRF_BZ_MSIX_TBL_BIR_WIDTH 3
1018 
1019 
1020 /*
1021  * PC_DEV_CTL2_REG(16bit):
1022  * PCIe Device Control 2
1023  */
1024 
1025 #define	PCR_CC_DEV_CTL2_REG 0x00000098
1026 /* sienaa0=pci_f0_config */
1027 
1028 #define	PCR_DZ_DEV_CTL2_REG 0x000000e8
1029 /* hunta0=pci_f0_config */
1030 
1031 #define	PCRF_CZ_CMPL_TIMEOUT_DIS_CTL_LBN 4
1032 #define	PCRF_CZ_CMPL_TIMEOUT_DIS_CTL_WIDTH 1
1033 #define	PCRF_CZ_CMPL_TIMEOUT_CTL_LBN 0
1034 #define	PCRF_CZ_CMPL_TIMEOUT_CTL_WIDTH 4
1035 
1036 
1037 /*
1038  * PC_MSIX_PBA_BASE_REG(32bit):
1039  * MSIX Capability PBA Base
1040  */
1041 
1042 #define	PCR_BB_MSIX_PBA_BASE_REG 0x00000098
1043 /* falconb0=pci_f0_config */
1044 
1045 #define	PCR_CZ_MSIX_PBA_BASE_REG 0x000000b8
1046 /* sienaa0,hunta0=pci_f0_config */
1047 
1048 #define	PCRF_BZ_MSIX_PBA_OFF_LBN 3
1049 #define	PCRF_BZ_MSIX_PBA_OFF_WIDTH 29
1050 #define	PCRF_BZ_MSIX_PBA_BIR_LBN 0
1051 #define	PCRF_BZ_MSIX_PBA_BIR_WIDTH 3
1052 
1053 
1054 /*
1055  * PC_LNK_CTL2_REG(16bit):
1056  * PCIe Link Control 2
1057  */
1058 
1059 #define	PCR_CC_LNK_CTL2_REG 0x000000a0
1060 /* sienaa0=pci_f0_config */
1061 
1062 #define	PCR_DZ_LNK_CTL2_REG 0x000000f0
1063 /* hunta0=pci_f0_config */
1064 
1065 #define	PCRF_CZ_POLLING_DEEMPH_LVL_LBN 12
1066 #define	PCRF_CZ_POLLING_DEEMPH_LVL_WIDTH 1
1067 #define	PCRF_CZ_COMPLIANCE_SOS_CTL_LBN 11
1068 #define	PCRF_CZ_COMPLIANCE_SOS_CTL_WIDTH 1
1069 #define	PCRF_CZ_ENTER_MODIFIED_COMPLIANCE_CTL_LBN 10
1070 #define	PCRF_CZ_ENTER_MODIFIED_COMPLIANCE_CTL_WIDTH 1
1071 #define	PCRF_CZ_TRANSMIT_MARGIN_LBN 7
1072 #define	PCRF_CZ_TRANSMIT_MARGIN_WIDTH 3
1073 #define	PCRF_CZ_SELECT_DEEMPH_LBN 6
1074 #define	PCRF_CZ_SELECT_DEEMPH_WIDTH 1
1075 #define	PCRF_CZ_HW_AUTONOMOUS_SPEED_DIS_LBN 5
1076 #define	PCRF_CZ_HW_AUTONOMOUS_SPEED_DIS_WIDTH 1
1077 #define	PCRF_CZ_ENTER_COMPLIANCE_CTL_LBN 4
1078 #define	PCRF_CZ_ENTER_COMPLIANCE_CTL_WIDTH 1
1079 #define	PCRF_CZ_TGT_LNK_SPEED_CTL_LBN 0
1080 #define	PCRF_CZ_TGT_LNK_SPEED_CTL_WIDTH 4
1081 
1082 
1083 /*
1084  * PC_LNK_STAT2_REG(16bit):
1085  * PCIe Link Status 2
1086  */
1087 
1088 #define	PCR_CC_LNK_STAT2_REG 0x000000a2
1089 /* sienaa0=pci_f0_config */
1090 
1091 #define	PCR_DZ_LNK_STAT2_REG 0x000000f2
1092 /* hunta0=pci_f0_config */
1093 
1094 #define	PCRF_CZ_CURRENT_DEEMPH_LBN 0
1095 #define	PCRF_CZ_CURRENT_DEEMPH_WIDTH 1
1096 
1097 
1098 /*
1099  * PC_VPD_CAP_ID_REG(8bit):
1100  * VPD data register
1101  */
1102 
1103 #define	PCR_AB_VPD_CAP_ID_REG 0x000000b0
1104 /* falcona0,falconb0=pci_f0_config */
1105 
1106 #define	PCRF_AB_VPD_CAP_ID_LBN 0
1107 #define	PCRF_AB_VPD_CAP_ID_WIDTH 8
1108 
1109 
1110 /*
1111  * PC_VPD_NXT_PTR_REG(8bit):
1112  * VPD next item pointer
1113  */
1114 
1115 #define	PCR_AB_VPD_NXT_PTR_REG 0x000000b1
1116 /* falcona0,falconb0=pci_f0_config */
1117 
1118 #define	PCRF_AB_VPD_NXT_PTR_LBN 0
1119 #define	PCRF_AB_VPD_NXT_PTR_WIDTH 8
1120 
1121 
1122 /*
1123  * PC_VPD_ADDR_REG(16bit):
1124  * VPD address register
1125  */
1126 
1127 #define	PCR_AB_VPD_ADDR_REG 0x000000b2
1128 /* falcona0,falconb0=pci_f0_config */
1129 
1130 #define	PCRF_AB_VPD_FLAG_LBN 15
1131 #define	PCRF_AB_VPD_FLAG_WIDTH 1
1132 #define	PCRF_AB_VPD_ADDR_LBN 0
1133 #define	PCRF_AB_VPD_ADDR_WIDTH 15
1134 
1135 
1136 /*
1137  * PC_AER_CAP_HDR_REG(32bit):
1138  * AER capability header register
1139  */
1140 
1141 #define	PCR_AZ_AER_CAP_HDR_REG 0x00000100
1142 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
1143 
1144 #define	PCRF_AZ_AERCAPHDR_NXT_PTR_LBN 20
1145 #define	PCRF_AZ_AERCAPHDR_NXT_PTR_WIDTH 12
1146 #define	PCRF_AZ_AERCAPHDR_VER_LBN 16
1147 #define	PCRF_AZ_AERCAPHDR_VER_WIDTH 4
1148 #define	PCRF_AZ_AERCAPHDR_ID_LBN 0
1149 #define	PCRF_AZ_AERCAPHDR_ID_WIDTH 16
1150 
1151 
1152 /*
1153  * PC_AER_UNCORR_ERR_STAT_REG(32bit):
1154  * AER Uncorrectable error status register
1155  */
1156 
1157 #define	PCR_AZ_AER_UNCORR_ERR_STAT_REG 0x00000104
1158 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
1159 
1160 #define	PCRF_AZ_UNSUPT_REQ_ERR_STAT_LBN 20
1161 #define	PCRF_AZ_UNSUPT_REQ_ERR_STAT_WIDTH 1
1162 #define	PCRF_AZ_ECRC_ERR_STAT_LBN 19
1163 #define	PCRF_AZ_ECRC_ERR_STAT_WIDTH 1
1164 #define	PCRF_AZ_MALF_TLP_STAT_LBN 18
1165 #define	PCRF_AZ_MALF_TLP_STAT_WIDTH 1
1166 #define	PCRF_AZ_RX_OVF_STAT_LBN 17
1167 #define	PCRF_AZ_RX_OVF_STAT_WIDTH 1
1168 #define	PCRF_AZ_UNEXP_COMP_STAT_LBN 16
1169 #define	PCRF_AZ_UNEXP_COMP_STAT_WIDTH 1
1170 #define	PCRF_AZ_COMP_ABRT_STAT_LBN 15
1171 #define	PCRF_AZ_COMP_ABRT_STAT_WIDTH 1
1172 #define	PCRF_AZ_COMP_TIMEOUT_STAT_LBN 14
1173 #define	PCRF_AZ_COMP_TIMEOUT_STAT_WIDTH 1
1174 #define	PCRF_AZ_FC_PROTO_ERR_STAT_LBN 13
1175 #define	PCRF_AZ_FC_PROTO_ERR_STAT_WIDTH 1
1176 #define	PCRF_AZ_PSON_TLP_STAT_LBN 12
1177 #define	PCRF_AZ_PSON_TLP_STAT_WIDTH 1
1178 #define	PCRF_AZ_DL_PROTO_ERR_STAT_LBN 4
1179 #define	PCRF_AZ_DL_PROTO_ERR_STAT_WIDTH 1
1180 #define	PCRF_AB_TRAIN_ERR_STAT_LBN 0
1181 #define	PCRF_AB_TRAIN_ERR_STAT_WIDTH 1
1182 
1183 
1184 /*
1185  * PC_AER_UNCORR_ERR_MASK_REG(32bit):
1186  * AER Uncorrectable error mask register
1187  */
1188 
1189 #define	PCR_AZ_AER_UNCORR_ERR_MASK_REG 0x00000108
1190 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
1191 
1192 #define	PCRF_AZ_UNSUPT_REQ_ERR_MASK_LBN 20
1193 #define	PCRF_AZ_UNSUPT_REQ_ERR_MASK_WIDTH 1
1194 #define	PCRF_AZ_ECRC_ERR_MASK_LBN 19
1195 #define	PCRF_AZ_ECRC_ERR_MASK_WIDTH 1
1196 #define	PCRF_AZ_MALF_TLP_MASK_LBN 18
1197 #define	PCRF_AZ_MALF_TLP_MASK_WIDTH 1
1198 #define	PCRF_AZ_RX_OVF_MASK_LBN 17
1199 #define	PCRF_AZ_RX_OVF_MASK_WIDTH 1
1200 #define	PCRF_AZ_UNEXP_COMP_MASK_LBN 16
1201 #define	PCRF_AZ_UNEXP_COMP_MASK_WIDTH 1
1202 #define	PCRF_AZ_COMP_ABRT_MASK_LBN 15
1203 #define	PCRF_AZ_COMP_ABRT_MASK_WIDTH 1
1204 #define	PCRF_AZ_COMP_TIMEOUT_MASK_LBN 14
1205 #define	PCRF_AZ_COMP_TIMEOUT_MASK_WIDTH 1
1206 #define	PCRF_AZ_FC_PROTO_ERR_MASK_LBN 13
1207 #define	PCRF_AZ_FC_PROTO_ERR_MASK_WIDTH 1
1208 #define	PCRF_AZ_PSON_TLP_MASK_LBN 12
1209 #define	PCRF_AZ_PSON_TLP_MASK_WIDTH 1
1210 #define	PCRF_AZ_DL_PROTO_ERR_MASK_LBN 4
1211 #define	PCRF_AZ_DL_PROTO_ERR_MASK_WIDTH 1
1212 #define	PCRF_AB_TRAIN_ERR_MASK_LBN 0
1213 #define	PCRF_AB_TRAIN_ERR_MASK_WIDTH 1
1214 
1215 
1216 /*
1217  * PC_AER_UNCORR_ERR_SEV_REG(32bit):
1218  * AER Uncorrectable error severity register
1219  */
1220 
1221 #define	PCR_AZ_AER_UNCORR_ERR_SEV_REG 0x0000010c
1222 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
1223 
1224 #define	PCRF_AZ_UNSUPT_REQ_ERR_SEV_LBN 20
1225 #define	PCRF_AZ_UNSUPT_REQ_ERR_SEV_WIDTH 1
1226 #define	PCRF_AZ_ECRC_ERR_SEV_LBN 19
1227 #define	PCRF_AZ_ECRC_ERR_SEV_WIDTH 1
1228 #define	PCRF_AZ_MALF_TLP_SEV_LBN 18
1229 #define	PCRF_AZ_MALF_TLP_SEV_WIDTH 1
1230 #define	PCRF_AZ_RX_OVF_SEV_LBN 17
1231 #define	PCRF_AZ_RX_OVF_SEV_WIDTH 1
1232 #define	PCRF_AZ_UNEXP_COMP_SEV_LBN 16
1233 #define	PCRF_AZ_UNEXP_COMP_SEV_WIDTH 1
1234 #define	PCRF_AZ_COMP_ABRT_SEV_LBN 15
1235 #define	PCRF_AZ_COMP_ABRT_SEV_WIDTH 1
1236 #define	PCRF_AZ_COMP_TIMEOUT_SEV_LBN 14
1237 #define	PCRF_AZ_COMP_TIMEOUT_SEV_WIDTH 1
1238 #define	PCRF_AZ_FC_PROTO_ERR_SEV_LBN 13
1239 #define	PCRF_AZ_FC_PROTO_ERR_SEV_WIDTH 1
1240 #define	PCRF_AZ_PSON_TLP_SEV_LBN 12
1241 #define	PCRF_AZ_PSON_TLP_SEV_WIDTH 1
1242 #define	PCRF_AZ_DL_PROTO_ERR_SEV_LBN 4
1243 #define	PCRF_AZ_DL_PROTO_ERR_SEV_WIDTH 1
1244 #define	PCRF_AB_TRAIN_ERR_SEV_LBN 0
1245 #define	PCRF_AB_TRAIN_ERR_SEV_WIDTH 1
1246 
1247 
1248 /*
1249  * PC_AER_CORR_ERR_STAT_REG(32bit):
1250  * AER Correctable error status register
1251  */
1252 
1253 #define	PCR_AZ_AER_CORR_ERR_STAT_REG 0x00000110
1254 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
1255 
1256 #define	PCRF_CZ_ADVSY_NON_FATAL_STAT_LBN 13
1257 #define	PCRF_CZ_ADVSY_NON_FATAL_STAT_WIDTH 1
1258 #define	PCRF_AZ_RPLY_TMR_TOUT_STAT_LBN 12
1259 #define	PCRF_AZ_RPLY_TMR_TOUT_STAT_WIDTH 1
1260 #define	PCRF_AZ_RPLAY_NUM_RO_STAT_LBN 8
1261 #define	PCRF_AZ_RPLAY_NUM_RO_STAT_WIDTH 1
1262 #define	PCRF_AZ_BAD_DLLP_STAT_LBN 7
1263 #define	PCRF_AZ_BAD_DLLP_STAT_WIDTH 1
1264 #define	PCRF_AZ_BAD_TLP_STAT_LBN 6
1265 #define	PCRF_AZ_BAD_TLP_STAT_WIDTH 1
1266 #define	PCRF_AZ_RX_ERR_STAT_LBN 0
1267 #define	PCRF_AZ_RX_ERR_STAT_WIDTH 1
1268 
1269 
1270 /*
1271  * PC_AER_CORR_ERR_MASK_REG(32bit):
1272  * AER Correctable error status register
1273  */
1274 
1275 #define	PCR_AZ_AER_CORR_ERR_MASK_REG 0x00000114
1276 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
1277 
1278 #define	PCRF_CZ_ADVSY_NON_FATAL_MASK_LBN 13
1279 #define	PCRF_CZ_ADVSY_NON_FATAL_MASK_WIDTH 1
1280 #define	PCRF_AZ_RPLY_TMR_TOUT_MASK_LBN 12
1281 #define	PCRF_AZ_RPLY_TMR_TOUT_MASK_WIDTH 1
1282 #define	PCRF_AZ_RPLAY_NUM_RO_MASK_LBN 8
1283 #define	PCRF_AZ_RPLAY_NUM_RO_MASK_WIDTH 1
1284 #define	PCRF_AZ_BAD_DLLP_MASK_LBN 7
1285 #define	PCRF_AZ_BAD_DLLP_MASK_WIDTH 1
1286 #define	PCRF_AZ_BAD_TLP_MASK_LBN 6
1287 #define	PCRF_AZ_BAD_TLP_MASK_WIDTH 1
1288 #define	PCRF_AZ_RX_ERR_MASK_LBN 0
1289 #define	PCRF_AZ_RX_ERR_MASK_WIDTH 1
1290 
1291 
1292 /*
1293  * PC_AER_CAP_CTL_REG(32bit):
1294  * AER capability and control register
1295  */
1296 
1297 #define	PCR_AZ_AER_CAP_CTL_REG 0x00000118
1298 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
1299 
1300 #define	PCRF_AZ_ECRC_CHK_EN_LBN 8
1301 #define	PCRF_AZ_ECRC_CHK_EN_WIDTH 1
1302 #define	PCRF_AZ_ECRC_CHK_CAP_LBN 7
1303 #define	PCRF_AZ_ECRC_CHK_CAP_WIDTH 1
1304 #define	PCRF_AZ_ECRC_GEN_EN_LBN 6
1305 #define	PCRF_AZ_ECRC_GEN_EN_WIDTH 1
1306 #define	PCRF_AZ_ECRC_GEN_CAP_LBN 5
1307 #define	PCRF_AZ_ECRC_GEN_CAP_WIDTH 1
1308 #define	PCRF_AZ_1ST_ERR_PTR_LBN 0
1309 #define	PCRF_AZ_1ST_ERR_PTR_WIDTH 5
1310 
1311 
1312 /*
1313  * PC_AER_HDR_LOG_REG(128bit):
1314  * AER Header log register
1315  */
1316 
1317 #define	PCR_AZ_AER_HDR_LOG_REG 0x0000011c
1318 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
1319 
1320 #define	PCRF_AZ_HDR_LOG_LBN 0
1321 #define	PCRF_AZ_HDR_LOG_WIDTH 128
1322 
1323 
1324 /*
1325  * PC_DEVSN_CAP_HDR_REG(32bit):
1326  * Device serial number capability header register
1327  */
1328 
1329 #define	PCR_DZ_DEVSN_CAP_HDR_REG 0x00000130
1330 /* hunta0=pci_f0_config */
1331 
1332 #define	PCR_CC_DEVSN_CAP_HDR_REG 0x00000140
1333 /* sienaa0=pci_f0_config */
1334 
1335 #define	PCRF_CZ_DEVSNCAPHDR_NXT_PTR_LBN 20
1336 #define	PCRF_CZ_DEVSNCAPHDR_NXT_PTR_WIDTH 12
1337 #define	PCRF_CZ_DEVSNCAPHDR_VER_LBN 16
1338 #define	PCRF_CZ_DEVSNCAPHDR_VER_WIDTH 4
1339 #define	PCRF_CZ_DEVSNCAPHDR_ID_LBN 0
1340 #define	PCRF_CZ_DEVSNCAPHDR_ID_WIDTH 16
1341 
1342 
1343 /*
1344  * PC_DEVSN_DWORD0_REG(32bit):
1345  * Device serial number DWORD0
1346  */
1347 
1348 #define	PCR_DZ_DEVSN_DWORD0_REG 0x00000134
1349 /* hunta0=pci_f0_config */
1350 
1351 #define	PCR_CC_DEVSN_DWORD0_REG 0x00000144
1352 /* sienaa0=pci_f0_config */
1353 
1354 #define	PCRF_CZ_DEVSN_DWORD0_LBN 0
1355 #define	PCRF_CZ_DEVSN_DWORD0_WIDTH 32
1356 
1357 
1358 /*
1359  * PC_DEVSN_DWORD1_REG(32bit):
1360  * Device serial number DWORD0
1361  */
1362 
1363 #define	PCR_DZ_DEVSN_DWORD1_REG 0x00000138
1364 /* hunta0=pci_f0_config */
1365 
1366 #define	PCR_CC_DEVSN_DWORD1_REG 0x00000148
1367 /* sienaa0=pci_f0_config */
1368 
1369 #define	PCRF_CZ_DEVSN_DWORD1_LBN 0
1370 #define	PCRF_CZ_DEVSN_DWORD1_WIDTH 32
1371 
1372 
1373 /*
1374  * PC_ARI_CAP_HDR_REG(32bit):
1375  * ARI capability header register
1376  */
1377 
1378 #define	PCR_DZ_ARI_CAP_HDR_REG 0x00000140
1379 /* hunta0=pci_f0_config */
1380 
1381 #define	PCR_CC_ARI_CAP_HDR_REG 0x00000150
1382 /* sienaa0=pci_f0_config */
1383 
1384 #define	PCRF_CZ_ARICAPHDR_NXT_PTR_LBN 20
1385 #define	PCRF_CZ_ARICAPHDR_NXT_PTR_WIDTH 12
1386 #define	PCRF_CZ_ARICAPHDR_VER_LBN 16
1387 #define	PCRF_CZ_ARICAPHDR_VER_WIDTH 4
1388 #define	PCRF_CZ_ARICAPHDR_ID_LBN 0
1389 #define	PCRF_CZ_ARICAPHDR_ID_WIDTH 16
1390 
1391 
1392 /*
1393  * PC_ARI_CAP_REG(16bit):
1394  * ARI Capabilities
1395  */
1396 
1397 #define	PCR_DZ_ARI_CAP_REG 0x00000144
1398 /* hunta0=pci_f0_config */
1399 
1400 #define	PCR_CC_ARI_CAP_REG 0x00000154
1401 /* sienaa0=pci_f0_config */
1402 
1403 #define	PCRF_CZ_ARI_NXT_FN_NUM_LBN 8
1404 #define	PCRF_CZ_ARI_NXT_FN_NUM_WIDTH 8
1405 #define	PCRF_CZ_ARI_ACS_FNGRP_CAP_LBN 1
1406 #define	PCRF_CZ_ARI_ACS_FNGRP_CAP_WIDTH 1
1407 #define	PCRF_CZ_ARI_MFVC_FNGRP_CAP_LBN 0
1408 #define	PCRF_CZ_ARI_MFVC_FNGRP_CAP_WIDTH 1
1409 
1410 
1411 /*
1412  * PC_ARI_CTL_REG(16bit):
1413  * ARI Control
1414  */
1415 
1416 #define	PCR_DZ_ARI_CTL_REG 0x00000146
1417 /* hunta0=pci_f0_config */
1418 
1419 #define	PCR_CC_ARI_CTL_REG 0x00000156
1420 /* sienaa0=pci_f0_config */
1421 
1422 #define	PCRF_CZ_ARI_FN_GRP_LBN 4
1423 #define	PCRF_CZ_ARI_FN_GRP_WIDTH 3
1424 #define	PCRF_CZ_ARI_ACS_FNGRP_EN_LBN 1
1425 #define	PCRF_CZ_ARI_ACS_FNGRP_EN_WIDTH 1
1426 #define	PCRF_CZ_ARI_MFVC_FNGRP_EN_LBN 0
1427 #define	PCRF_CZ_ARI_MFVC_FNGRP_EN_WIDTH 1
1428 
1429 
1430 /*
1431  * PC_SRIOV_CAP_HDR_REG(32bit):
1432  * SRIOV capability header register
1433  */
1434 
1435 #define	PCR_CC_SRIOV_CAP_HDR_REG 0x00000160
1436 /* sienaa0=pci_f0_config */
1437 
1438 #define	PCR_DZ_SRIOV_CAP_HDR_REG 0x00000200
1439 /* hunta0=pci_f0_config */
1440 
1441 #define	PCRF_CZ_SRIOVCAPHDR_NXT_PTR_LBN 20
1442 #define	PCRF_CZ_SRIOVCAPHDR_NXT_PTR_WIDTH 12
1443 #define	PCRF_CZ_SRIOVCAPHDR_VER_LBN 16
1444 #define	PCRF_CZ_SRIOVCAPHDR_VER_WIDTH 4
1445 #define	PCRF_CZ_SRIOVCAPHDR_ID_LBN 0
1446 #define	PCRF_CZ_SRIOVCAPHDR_ID_WIDTH 16
1447 
1448 
1449 /*
1450  * PC_SRIOV_CAP_REG(32bit):
1451  * SRIOV Capabilities
1452  */
1453 
1454 #define	PCR_CC_SRIOV_CAP_REG 0x00000164
1455 /* sienaa0=pci_f0_config */
1456 
1457 #define	PCR_DZ_SRIOV_CAP_REG 0x00000204
1458 /* hunta0=pci_f0_config */
1459 
1460 #define	PCRF_CZ_VF_MIGR_INT_MSG_NUM_LBN 21
1461 #define	PCRF_CZ_VF_MIGR_INT_MSG_NUM_WIDTH 11
1462 #define	PCRF_CZ_VF_MIGR_CAP_LBN 0
1463 #define	PCRF_CZ_VF_MIGR_CAP_WIDTH 1
1464 
1465 
1466 /*
1467  * PC_SRIOV_CTL_REG(16bit):
1468  * SRIOV Control
1469  */
1470 
1471 #define	PCR_CC_SRIOV_CTL_REG 0x00000168
1472 /* sienaa0=pci_f0_config */
1473 
1474 #define	PCR_DZ_SRIOV_CTL_REG 0x00000208
1475 /* hunta0=pci_f0_config */
1476 
1477 #define	PCRF_CZ_VF_ARI_CAP_HRCHY_LBN 4
1478 #define	PCRF_CZ_VF_ARI_CAP_HRCHY_WIDTH 1
1479 #define	PCRF_CZ_VF_MSE_LBN 3
1480 #define	PCRF_CZ_VF_MSE_WIDTH 1
1481 #define	PCRF_CZ_VF_MIGR_INT_EN_LBN 2
1482 #define	PCRF_CZ_VF_MIGR_INT_EN_WIDTH 1
1483 #define	PCRF_CZ_VF_MIGR_EN_LBN 1
1484 #define	PCRF_CZ_VF_MIGR_EN_WIDTH 1
1485 #define	PCRF_CZ_VF_EN_LBN 0
1486 #define	PCRF_CZ_VF_EN_WIDTH 1
1487 
1488 
1489 /*
1490  * PC_SRIOV_STAT_REG(16bit):
1491  * SRIOV Status
1492  */
1493 
1494 #define	PCR_CC_SRIOV_STAT_REG 0x0000016a
1495 /* sienaa0=pci_f0_config */
1496 
1497 #define	PCR_DZ_SRIOV_STAT_REG 0x0000020a
1498 /* hunta0=pci_f0_config */
1499 
1500 #define	PCRF_CZ_VF_MIGR_STAT_LBN 0
1501 #define	PCRF_CZ_VF_MIGR_STAT_WIDTH 1
1502 
1503 
1504 /*
1505  * PC_SRIOV_INITIALVFS_REG(16bit):
1506  * SRIOV Initial VFs
1507  */
1508 
1509 #define	PCR_CC_SRIOV_INITIALVFS_REG 0x0000016c
1510 /* sienaa0=pci_f0_config */
1511 
1512 #define	PCR_DZ_SRIOV_INITIALVFS_REG 0x0000020c
1513 /* hunta0=pci_f0_config */
1514 
1515 #define	PCRF_CZ_VF_INITIALVFS_LBN 0
1516 #define	PCRF_CZ_VF_INITIALVFS_WIDTH 16
1517 
1518 
1519 /*
1520  * PC_SRIOV_TOTALVFS_REG(10bit):
1521  * SRIOV Total VFs
1522  */
1523 
1524 #define	PCR_CC_SRIOV_TOTALVFS_REG 0x0000016e
1525 /* sienaa0=pci_f0_config */
1526 
1527 #define	PCR_DZ_SRIOV_TOTALVFS_REG 0x0000020e
1528 /* hunta0=pci_f0_config */
1529 
1530 #define	PCRF_CZ_VF_TOTALVFS_LBN 0
1531 #define	PCRF_CZ_VF_TOTALVFS_WIDTH 16
1532 
1533 
1534 /*
1535  * PC_SRIOV_NUMVFS_REG(16bit):
1536  * SRIOV Number of VFs
1537  */
1538 
1539 #define	PCR_CC_SRIOV_NUMVFS_REG 0x00000170
1540 /* sienaa0=pci_f0_config */
1541 
1542 #define	PCR_DZ_SRIOV_NUMVFS_REG 0x00000210
1543 /* hunta0=pci_f0_config */
1544 
1545 #define	PCRF_CZ_VF_NUMVFS_LBN 0
1546 #define	PCRF_CZ_VF_NUMVFS_WIDTH 16
1547 
1548 
1549 /*
1550  * PC_SRIOV_FN_DPND_LNK_REG(16bit):
1551  * SRIOV Function dependency link
1552  */
1553 
1554 #define	PCR_CC_SRIOV_FN_DPND_LNK_REG 0x00000172
1555 /* sienaa0=pci_f0_config */
1556 
1557 #define	PCR_DZ_SRIOV_FN_DPND_LNK_REG 0x00000212
1558 /* hunta0=pci_f0_config */
1559 
1560 #define	PCRF_CZ_SRIOV_FN_DPND_LNK_LBN 0
1561 #define	PCRF_CZ_SRIOV_FN_DPND_LNK_WIDTH 8
1562 
1563 
1564 /*
1565  * PC_SRIOV_1STVF_OFFSET_REG(16bit):
1566  * SRIOV First VF Offset
1567  */
1568 
1569 #define	PCR_CC_SRIOV_1STVF_OFFSET_REG 0x00000174
1570 /* sienaa0=pci_f0_config */
1571 
1572 #define	PCR_DZ_SRIOV_1STVF_OFFSET_REG 0x00000214
1573 /* hunta0=pci_f0_config */
1574 
1575 #define	PCRF_CZ_VF_1STVF_OFFSET_LBN 0
1576 #define	PCRF_CZ_VF_1STVF_OFFSET_WIDTH 16
1577 
1578 
1579 /*
1580  * PC_SRIOV_VFSTRIDE_REG(16bit):
1581  * SRIOV VF Stride
1582  */
1583 
1584 #define	PCR_CC_SRIOV_VFSTRIDE_REG 0x00000176
1585 /* sienaa0=pci_f0_config */
1586 
1587 #define	PCR_DZ_SRIOV_VFSTRIDE_REG 0x00000216
1588 /* hunta0=pci_f0_config */
1589 
1590 #define	PCRF_CZ_VF_VFSTRIDE_LBN 0
1591 #define	PCRF_CZ_VF_VFSTRIDE_WIDTH 16
1592 
1593 
1594 /*
1595  * PC_SRIOV_DEVID_REG(16bit):
1596  * SRIOV VF Device ID
1597  */
1598 
1599 #define	PCR_CC_SRIOV_DEVID_REG 0x0000017a
1600 /* sienaa0=pci_f0_config */
1601 
1602 #define	PCR_DZ_SRIOV_DEVID_REG 0x0000021a
1603 /* hunta0=pci_f0_config */
1604 
1605 #define	PCRF_CZ_VF_DEVID_LBN 0
1606 #define	PCRF_CZ_VF_DEVID_WIDTH 16
1607 
1608 
1609 /*
1610  * PC_SRIOV_SUP_PAGESZ_REG(16bit):
1611  * SRIOV Supported Page Sizes
1612  */
1613 
1614 #define	PCR_CC_SRIOV_SUP_PAGESZ_REG 0x0000017c
1615 /* sienaa0=pci_f0_config */
1616 
1617 #define	PCR_DZ_SRIOV_SUP_PAGESZ_REG 0x0000021c
1618 /* hunta0=pci_f0_config */
1619 
1620 #define	PCRF_CZ_VF_SUP_PAGESZ_LBN 0
1621 #define	PCRF_CZ_VF_SUP_PAGESZ_WIDTH 16
1622 
1623 
1624 /*
1625  * PC_SRIOV_SYS_PAGESZ_REG(32bit):
1626  * SRIOV System Page Size
1627  */
1628 
1629 #define	PCR_CC_SRIOV_SYS_PAGESZ_REG 0x00000180
1630 /* sienaa0=pci_f0_config */
1631 
1632 #define	PCR_DZ_SRIOV_SYS_PAGESZ_REG 0x00000220
1633 /* hunta0=pci_f0_config */
1634 
1635 #define	PCRF_CZ_VF_SYS_PAGESZ_LBN 0
1636 #define	PCRF_CZ_VF_SYS_PAGESZ_WIDTH 16
1637 
1638 
1639 /*
1640  * PC_SRIOV_BAR0_REG(32bit):
1641  * SRIOV VF Bar0
1642  */
1643 
1644 #define	PCR_CC_SRIOV_BAR0_REG 0x00000184
1645 /* sienaa0=pci_f0_config */
1646 
1647 #define	PCR_DZ_SRIOV_BAR0_REG 0x00000224
1648 /* hunta0=pci_f0_config */
1649 
1650 #define	PCRF_CC_VF_BAR_ADDRESS_LBN 0
1651 #define	PCRF_CC_VF_BAR_ADDRESS_WIDTH 32
1652 #define	PCRF_DZ_VF_BAR0_ADDRESS_LBN 0
1653 #define	PCRF_DZ_VF_BAR0_ADDRESS_WIDTH 32
1654 
1655 
1656 /*
1657  * PC_SRIOV_BAR1_REG(32bit):
1658  * SRIOV Bar1
1659  */
1660 
1661 #define	PCR_CC_SRIOV_BAR1_REG 0x00000188
1662 /* sienaa0=pci_f0_config */
1663 
1664 #define	PCR_DZ_SRIOV_BAR1_REG 0x00000228
1665 /* hunta0=pci_f0_config */
1666 
1667 /* defined as PCRF_CC_VF_BAR_ADDRESS_LBN 0; */
1668 /* defined as PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 */
1669 #define	PCRF_DZ_VF_BAR1_ADDRESS_LBN 0
1670 #define	PCRF_DZ_VF_BAR1_ADDRESS_WIDTH 32
1671 
1672 
1673 /*
1674  * PC_SRIOV_BAR2_REG(32bit):
1675  * SRIOV Bar2
1676  */
1677 
1678 #define	PCR_CC_SRIOV_BAR2_REG 0x0000018c
1679 /* sienaa0=pci_f0_config */
1680 
1681 #define	PCR_DZ_SRIOV_BAR2_REG 0x0000022c
1682 /* hunta0=pci_f0_config */
1683 
1684 /* defined as PCRF_CC_VF_BAR_ADDRESS_LBN 0; */
1685 /* defined as PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 */
1686 #define	PCRF_DZ_VF_BAR2_ADDRESS_LBN 0
1687 #define	PCRF_DZ_VF_BAR2_ADDRESS_WIDTH 32
1688 
1689 
1690 /*
1691  * PC_SRIOV_BAR3_REG(32bit):
1692  * SRIOV Bar3
1693  */
1694 
1695 #define	PCR_CC_SRIOV_BAR3_REG 0x00000190
1696 /* sienaa0=pci_f0_config */
1697 
1698 #define	PCR_DZ_SRIOV_BAR3_REG 0x00000230
1699 /* hunta0=pci_f0_config */
1700 
1701 /* defined as PCRF_CC_VF_BAR_ADDRESS_LBN 0; */
1702 /* defined as PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 */
1703 #define	PCRF_DZ_VF_BAR3_ADDRESS_LBN 0
1704 #define	PCRF_DZ_VF_BAR3_ADDRESS_WIDTH 32
1705 
1706 
1707 /*
1708  * PC_SRIOV_BAR4_REG(32bit):
1709  * SRIOV Bar4
1710  */
1711 
1712 #define	PCR_CC_SRIOV_BAR4_REG 0x00000194
1713 /* sienaa0=pci_f0_config */
1714 
1715 #define	PCR_DZ_SRIOV_BAR4_REG 0x00000234
1716 /* hunta0=pci_f0_config */
1717 
1718 /* defined as PCRF_CC_VF_BAR_ADDRESS_LBN 0; */
1719 /* defined as PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 */
1720 #define	PCRF_DZ_VF_BAR4_ADDRESS_LBN 0
1721 #define	PCRF_DZ_VF_BAR4_ADDRESS_WIDTH 32
1722 
1723 
1724 /*
1725  * PC_SRIOV_BAR5_REG(32bit):
1726  * SRIOV Bar5
1727  */
1728 
1729 #define	PCR_CC_SRIOV_BAR5_REG 0x00000198
1730 /* sienaa0=pci_f0_config */
1731 
1732 #define	PCR_DZ_SRIOV_BAR5_REG 0x00000238
1733 /* hunta0=pci_f0_config */
1734 
1735 /* defined as PCRF_CC_VF_BAR_ADDRESS_LBN 0; */
1736 /* defined as PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 */
1737 #define	PCRF_DZ_VF_BAR5_ADDRESS_LBN 0
1738 #define	PCRF_DZ_VF_BAR5_ADDRESS_WIDTH 32
1739 
1740 
1741 /*
1742  * PC_SRIOV_MIBR_SARRAY_OFFSET_REG(32bit):
1743  * SRIOV VF Migration State Array Offset
1744  */
1745 
1746 #define	PCR_CC_SRIOV_MIBR_SARRAY_OFFSET_REG 0x0000019c
1747 /* sienaa0=pci_f0_config */
1748 
1749 #define	PCR_DZ_SRIOV_MIBR_SARRAY_OFFSET_REG 0x0000023c
1750 /* hunta0=pci_f0_config */
1751 
1752 #define	PCRF_CZ_VF_MIGR_OFFSET_LBN 3
1753 #define	PCRF_CZ_VF_MIGR_OFFSET_WIDTH 29
1754 #define	PCRF_CZ_VF_MIGR_BIR_LBN 0
1755 #define	PCRF_CZ_VF_MIGR_BIR_WIDTH 3
1756 
1757 
1758 /*
1759  * PC_LTR_CAP_HDR_REG(32bit):
1760  * Latency Tolerance Reporting Cap Header Reg
1761  */
1762 
1763 #define	PCR_DZ_LTR_CAP_HDR_REG 0x00000240
1764 /* hunta0=pci_f0_config */
1765 
1766 #define	PCRF_DZ_LTR_NXT_PTR_LBN 20
1767 #define	PCRF_DZ_LTR_NXT_PTR_WIDTH 12
1768 #define	PCRF_DZ_LTR_VERSION_LBN 16
1769 #define	PCRF_DZ_LTR_VERSION_WIDTH 4
1770 #define	PCRF_DZ_LTR_EXT_CAP_ID_LBN 0
1771 #define	PCRF_DZ_LTR_EXT_CAP_ID_WIDTH 16
1772 
1773 
1774 /*
1775  * PC_LTR_MAX_SNOOP_REG(32bit):
1776  * LTR Maximum Snoop/No Snoop Register
1777  */
1778 
1779 #define	PCR_DZ_LTR_MAX_SNOOP_REG 0x00000244
1780 /* hunta0=pci_f0_config */
1781 
1782 #define	PCRF_DZ_LTR_MAX_NOSNOOP_SCALE_LBN 26
1783 #define	PCRF_DZ_LTR_MAX_NOSNOOP_SCALE_WIDTH 3
1784 #define	PCRF_DZ_LTR_MAX_NOSNOOP_LAT_LBN 16
1785 #define	PCRF_DZ_LTR_MAX_NOSNOOP_LAT_WIDTH 10
1786 #define	PCRF_DZ_LTR_MAX_SNOOP_SCALE_LBN 10
1787 #define	PCRF_DZ_LTR_MAX_SNOOP_SCALE_WIDTH 3
1788 #define	PCRF_DZ_LTR_MAX_SNOOP_LAT_LBN 0
1789 #define	PCRF_DZ_LTR_MAX_SNOOP_LAT_WIDTH 10
1790 
1791 
1792 /*
1793  * PC_TPH_CAP_HDR_REG(32bit):
1794  * TPH Capability Header Register
1795  */
1796 
1797 #define	PCR_DZ_TPH_CAP_HDR_REG 0x00000274
1798 /* hunta0=pci_f0_config */
1799 
1800 #define	PCRF_DZ_TPH_NXT_PTR_LBN 20
1801 #define	PCRF_DZ_TPH_NXT_PTR_WIDTH 12
1802 #define	PCRF_DZ_TPH_VERSION_LBN 16
1803 #define	PCRF_DZ_TPH_VERSION_WIDTH 4
1804 #define	PCRF_DZ_TPH_EXT_CAP_ID_LBN 0
1805 #define	PCRF_DZ_TPH_EXT_CAP_ID_WIDTH 16
1806 
1807 
1808 /*
1809  * PC_TPH_REQ_CAP_REG(32bit):
1810  * TPH Requester Capability Register
1811  */
1812 
1813 #define	PCR_DZ_TPH_REQ_CAP_REG 0x00000278
1814 /* hunta0=pci_f0_config */
1815 
1816 #define	PCRF_DZ_ST_TBLE_SIZE_LBN 16
1817 #define	PCRF_DZ_ST_TBLE_SIZE_WIDTH 11
1818 #define	PCRF_DZ_ST_TBLE_LOC_LBN 9
1819 #define	PCRF_DZ_ST_TBLE_LOC_WIDTH 2
1820 #define	PCRF_DZ_EXT_TPH_MODE_SUP_LBN 8
1821 #define	PCRF_DZ_EXT_TPH_MODE_SUP_WIDTH 1
1822 #define	PCRF_DZ_TPH_DEV_MODE_SUP_LBN 2
1823 #define	PCRF_DZ_TPH_DEV_MODE_SUP_WIDTH 1
1824 #define	PCRF_DZ_TPH_INT_MODE_SUP_LBN 1
1825 #define	PCRF_DZ_TPH_INT_MODE_SUP_WIDTH 1
1826 #define	PCRF_DZ_TPH_NOST_MODE_SUP_LBN 0
1827 #define	PCRF_DZ_TPH_NOST_MODE_SUP_WIDTH 1
1828 
1829 
1830 /*
1831  * PC_TPH_REQ_CTL_REG(32bit):
1832  * TPH Requester Control Register
1833  */
1834 
1835 #define	PCR_DZ_TPH_REQ_CTL_REG 0x0000027c
1836 /* hunta0=pci_f0_config */
1837 
1838 #define	PCRF_DZ_TPH_REQ_ENABLE_LBN 8
1839 #define	PCRF_DZ_TPH_REQ_ENABLE_WIDTH 2
1840 #define	PCRF_DZ_TPH_ST_MODE_LBN 0
1841 #define	PCRF_DZ_TPH_ST_MODE_WIDTH 3
1842 
1843 
1844 /*
1845  * PC_SEC_PCIE_CAP_REG(32bit):
1846  * Secondary PCIE Capability Register
1847  */
1848 
1849 #define	PCR_DZ_SEC_PCIE_CAP_REG 0x00000300
1850 /* hunta0=pci_f0_config */
1851 
1852 #define	PCRF_DZ_SEC_NXT_PTR_LBN 20
1853 #define	PCRF_DZ_SEC_NXT_PTR_WIDTH 12
1854 #define	PCRF_DZ_SEC_VERSION_LBN 16
1855 #define	PCRF_DZ_SEC_VERSION_WIDTH 4
1856 #define	PCRF_DZ_SEC_EXT_CAP_ID_LBN 0
1857 #define	PCRF_DZ_SEC_EXT_CAP_ID_WIDTH 16
1858 
1859 
1860 /*
1861  * PC_LINK_CONTROL3_REG(32bit):
1862  * Link Control 3.
1863  */
1864 
1865 #define	PCR_DZ_LINK_CONTROL3_REG 0x00000304
1866 /* hunta0=pci_f0_config */
1867 
1868 #define	PCRF_DZ_LINK_EQ_INT_EN_LBN 1
1869 #define	PCRF_DZ_LINK_EQ_INT_EN_WIDTH 1
1870 #define	PCRF_DZ_PERFORM_EQL_LBN 0
1871 #define	PCRF_DZ_PERFORM_EQL_WIDTH 1
1872 
1873 
1874 /*
1875  * PC_LANE_ERROR_STAT_REG(32bit):
1876  * Lane Error Status Register.
1877  */
1878 
1879 #define	PCR_DZ_LANE_ERROR_STAT_REG 0x00000308
1880 /* hunta0=pci_f0_config */
1881 
1882 #define	PCRF_DZ_LANE_STATUS_LBN 0
1883 #define	PCRF_DZ_LANE_STATUS_WIDTH 8
1884 
1885 
1886 /*
1887  * PC_LANE01_EQU_CONTROL_REG(32bit):
1888  * Lanes 0,1 Equalization Control Register.
1889  */
1890 
1891 #define	PCR_DZ_LANE01_EQU_CONTROL_REG 0x0000030c
1892 /* hunta0=pci_f0_config */
1893 
1894 #define	PCRF_DZ_LANE1_EQ_CTRL_LBN 16
1895 #define	PCRF_DZ_LANE1_EQ_CTRL_WIDTH 16
1896 #define	PCRF_DZ_LANE0_EQ_CTRL_LBN 0
1897 #define	PCRF_DZ_LANE0_EQ_CTRL_WIDTH 16
1898 
1899 
1900 /*
1901  * PC_LANE23_EQU_CONTROL_REG(32bit):
1902  * Lanes 2,3 Equalization Control Register.
1903  */
1904 
1905 #define	PCR_DZ_LANE23_EQU_CONTROL_REG 0x00000310
1906 /* hunta0=pci_f0_config */
1907 
1908 #define	PCRF_DZ_LANE3_EQ_CTRL_LBN 16
1909 #define	PCRF_DZ_LANE3_EQ_CTRL_WIDTH 16
1910 #define	PCRF_DZ_LANE2_EQ_CTRL_LBN 0
1911 #define	PCRF_DZ_LANE2_EQ_CTRL_WIDTH 16
1912 
1913 
1914 /*
1915  * PC_LANE45_EQU_CONTROL_REG(32bit):
1916  * Lanes 4,5 Equalization Control Register.
1917  */
1918 
1919 #define	PCR_DZ_LANE45_EQU_CONTROL_REG 0x00000314
1920 /* hunta0=pci_f0_config */
1921 
1922 #define	PCRF_DZ_LANE5_EQ_CTRL_LBN 16
1923 #define	PCRF_DZ_LANE5_EQ_CTRL_WIDTH 16
1924 #define	PCRF_DZ_LANE4_EQ_CTRL_LBN 0
1925 #define	PCRF_DZ_LANE4_EQ_CTRL_WIDTH 16
1926 
1927 
1928 /*
1929  * PC_LANE67_EQU_CONTROL_REG(32bit):
1930  * Lanes 6,7 Equalization Control Register.
1931  */
1932 
1933 #define	PCR_DZ_LANE67_EQU_CONTROL_REG 0x00000318
1934 /* hunta0=pci_f0_config */
1935 
1936 #define	PCRF_DZ_LANE7_EQ_CTRL_LBN 16
1937 #define	PCRF_DZ_LANE7_EQ_CTRL_WIDTH 16
1938 #define	PCRF_DZ_LANE6_EQ_CTRL_LBN 0
1939 #define	PCRF_DZ_LANE6_EQ_CTRL_WIDTH 16
1940 
1941 
1942 /*
1943  * PC_ACK_LAT_TMR_REG(32bit):
1944  * ACK latency timer & replay timer register
1945  */
1946 
1947 #define	PCR_AC_ACK_LAT_TMR_REG 0x00000700
1948 /* falcona0,falconb0,sienaa0=pci_f0_config */
1949 
1950 #define	PCRF_AC_RT_LBN 16
1951 #define	PCRF_AC_RT_WIDTH 16
1952 #define	PCRF_AC_ALT_LBN 0
1953 #define	PCRF_AC_ALT_WIDTH 16
1954 
1955 
1956 /*
1957  * PC_OTHER_MSG_REG(32bit):
1958  * Other message register
1959  */
1960 
1961 #define	PCR_AC_OTHER_MSG_REG 0x00000704
1962 /* falcona0,falconb0,sienaa0=pci_f0_config */
1963 
1964 #define	PCRF_AC_OM_CRPT3_LBN 24
1965 #define	PCRF_AC_OM_CRPT3_WIDTH 8
1966 #define	PCRF_AC_OM_CRPT2_LBN 16
1967 #define	PCRF_AC_OM_CRPT2_WIDTH 8
1968 #define	PCRF_AC_OM_CRPT1_LBN 8
1969 #define	PCRF_AC_OM_CRPT1_WIDTH 8
1970 #define	PCRF_AC_OM_CRPT0_LBN 0
1971 #define	PCRF_AC_OM_CRPT0_WIDTH 8
1972 
1973 
1974 /*
1975  * PC_FORCE_LNK_REG(24bit):
1976  * Port force link register
1977  */
1978 
1979 #define	PCR_AC_FORCE_LNK_REG 0x00000708
1980 /* falcona0,falconb0,sienaa0=pci_f0_config */
1981 
1982 #define	PCRF_AC_LFS_LBN 16
1983 #define	PCRF_AC_LFS_WIDTH 6
1984 #define	PCRF_AC_FL_LBN 15
1985 #define	PCRF_AC_FL_WIDTH 1
1986 #define	PCRF_AC_LN_LBN 0
1987 #define	PCRF_AC_LN_WIDTH 8
1988 
1989 
1990 /*
1991  * PC_ACK_FREQ_REG(32bit):
1992  * ACK frequency register
1993  */
1994 
1995 #define	PCR_AC_ACK_FREQ_REG 0x0000070c
1996 /* falcona0,falconb0,sienaa0=pci_f0_config */
1997 
1998 #define	PCRF_CC_ALLOW_L1_WITHOUT_L0S_LBN 30
1999 #define	PCRF_CC_ALLOW_L1_WITHOUT_L0S_WIDTH 1
2000 #define	PCRF_AC_L1_ENTR_LAT_LBN 27
2001 #define	PCRF_AC_L1_ENTR_LAT_WIDTH 3
2002 #define	PCRF_AC_L0_ENTR_LAT_LBN 24
2003 #define	PCRF_AC_L0_ENTR_LAT_WIDTH 3
2004 #define	PCRF_CC_COMM_NFTS_LBN 16
2005 #define	PCRF_CC_COMM_NFTS_WIDTH 8
2006 #define	PCRF_AB_ACK_FREQ_REG_RSVD0_LBN 16
2007 #define	PCRF_AB_ACK_FREQ_REG_RSVD0_WIDTH 3
2008 #define	PCRF_AC_MAX_FTS_LBN 8
2009 #define	PCRF_AC_MAX_FTS_WIDTH 8
2010 #define	PCRF_AC_ACK_FREQ_LBN 0
2011 #define	PCRF_AC_ACK_FREQ_WIDTH 8
2012 
2013 
2014 /*
2015  * PC_PORT_LNK_CTL_REG(32bit):
2016  * Port link control register
2017  */
2018 
2019 #define	PCR_AC_PORT_LNK_CTL_REG 0x00000710
2020 /* falcona0,falconb0,sienaa0=pci_f0_config */
2021 
2022 #define	PCRF_AB_LRE_LBN 27
2023 #define	PCRF_AB_LRE_WIDTH 1
2024 #define	PCRF_AB_ESYNC_LBN 26
2025 #define	PCRF_AB_ESYNC_WIDTH 1
2026 #define	PCRF_AB_CRPT_LBN 25
2027 #define	PCRF_AB_CRPT_WIDTH 1
2028 #define	PCRF_AB_XB_LBN 24
2029 #define	PCRF_AB_XB_WIDTH 1
2030 #define	PCRF_AC_LC_LBN 16
2031 #define	PCRF_AC_LC_WIDTH 6
2032 #define	PCRF_AC_LDR_LBN 8
2033 #define	PCRF_AC_LDR_WIDTH 4
2034 #define	PCRF_AC_FLM_LBN 7
2035 #define	PCRF_AC_FLM_WIDTH 1
2036 #define	PCRF_AC_LKD_LBN 6
2037 #define	PCRF_AC_LKD_WIDTH 1
2038 #define	PCRF_AC_DLE_LBN 5
2039 #define	PCRF_AC_DLE_WIDTH 1
2040 #define	PCRF_AB_PORT_LNK_CTL_REG_RSVD0_LBN 4
2041 #define	PCRF_AB_PORT_LNK_CTL_REG_RSVD0_WIDTH 1
2042 #define	PCRF_AC_RA_LBN 3
2043 #define	PCRF_AC_RA_WIDTH 1
2044 #define	PCRF_AC_LE_LBN 2
2045 #define	PCRF_AC_LE_WIDTH 1
2046 #define	PCRF_AC_SD_LBN 1
2047 #define	PCRF_AC_SD_WIDTH 1
2048 #define	PCRF_AC_OMR_LBN 0
2049 #define	PCRF_AC_OMR_WIDTH 1
2050 
2051 
2052 /*
2053  * PC_LN_SKEW_REG(32bit):
2054  * Lane skew register
2055  */
2056 
2057 #define	PCR_AC_LN_SKEW_REG 0x00000714
2058 /* falcona0,falconb0,sienaa0=pci_f0_config */
2059 
2060 #define	PCRF_AC_DIS_LBN 31
2061 #define	PCRF_AC_DIS_WIDTH 1
2062 #define	PCRF_AB_RST_LBN 30
2063 #define	PCRF_AB_RST_WIDTH 1
2064 #define	PCRF_AC_AD_LBN 25
2065 #define	PCRF_AC_AD_WIDTH 1
2066 #define	PCRF_AC_FCD_LBN 24
2067 #define	PCRF_AC_FCD_WIDTH 1
2068 #define	PCRF_AC_LS2_LBN 16
2069 #define	PCRF_AC_LS2_WIDTH 8
2070 #define	PCRF_AC_LS1_LBN 8
2071 #define	PCRF_AC_LS1_WIDTH 8
2072 #define	PCRF_AC_LS0_LBN 0
2073 #define	PCRF_AC_LS0_WIDTH 8
2074 
2075 
2076 /*
2077  * PC_SYM_NUM_REG(16bit):
2078  * Symbol number register
2079  */
2080 
2081 #define	PCR_AC_SYM_NUM_REG 0x00000718
2082 /* falcona0,falconb0,sienaa0=pci_f0_config */
2083 
2084 #define	PCRF_CC_MAX_FUNCTIONS_LBN 29
2085 #define	PCRF_CC_MAX_FUNCTIONS_WIDTH 3
2086 #define	PCRF_CC_FC_WATCHDOG_TMR_LBN 24
2087 #define	PCRF_CC_FC_WATCHDOG_TMR_WIDTH 5
2088 #define	PCRF_CC_ACK_NAK_TMR_MOD_LBN 19
2089 #define	PCRF_CC_ACK_NAK_TMR_MOD_WIDTH 5
2090 #define	PCRF_CC_REPLAY_TMR_MOD_LBN 14
2091 #define	PCRF_CC_REPLAY_TMR_MOD_WIDTH 5
2092 #define	PCRF_AB_ES_LBN 12
2093 #define	PCRF_AB_ES_WIDTH 3
2094 #define	PCRF_AB_SYM_NUM_REG_RSVD0_LBN 11
2095 #define	PCRF_AB_SYM_NUM_REG_RSVD0_WIDTH 1
2096 #define	PCRF_CC_NUM_SKP_SYMS_LBN 8
2097 #define	PCRF_CC_NUM_SKP_SYMS_WIDTH 3
2098 #define	PCRF_AB_TS2_LBN 4
2099 #define	PCRF_AB_TS2_WIDTH 4
2100 #define	PCRF_AC_TS1_LBN 0
2101 #define	PCRF_AC_TS1_WIDTH 4
2102 
2103 
2104 /*
2105  * PC_SYM_TMR_FLT_MSK_REG(16bit):
2106  * Symbol timer and Filter Mask Register
2107  */
2108 
2109 #define	PCR_CC_SYM_TMR_FLT_MSK_REG 0x0000071c
2110 /* sienaa0=pci_f0_config */
2111 
2112 #define	PCRF_CC_DEFAULT_FLT_MSK1_LBN 16
2113 #define	PCRF_CC_DEFAULT_FLT_MSK1_WIDTH 16
2114 #define	PCRF_CC_FC_WDOG_TMR_DIS_LBN 15
2115 #define	PCRF_CC_FC_WDOG_TMR_DIS_WIDTH 1
2116 #define	PCRF_CC_SI1_LBN 8
2117 #define	PCRF_CC_SI1_WIDTH 3
2118 #define	PCRF_CC_SKIP_INT_VAL_LBN 0
2119 #define	PCRF_CC_SKIP_INT_VAL_WIDTH 11
2120 #define	PCRF_CC_SI0_LBN 0
2121 #define	PCRF_CC_SI0_WIDTH 8
2122 
2123 
2124 /*
2125  * PC_SYM_TMR_REG(16bit):
2126  * Symbol timer register
2127  */
2128 
2129 #define	PCR_AB_SYM_TMR_REG 0x0000071c
2130 /* falcona0,falconb0=pci_f0_config */
2131 
2132 #define	PCRF_AB_ET_LBN 11
2133 #define	PCRF_AB_ET_WIDTH 4
2134 #define	PCRF_AB_SI1_LBN 8
2135 #define	PCRF_AB_SI1_WIDTH 3
2136 #define	PCRF_AB_SI0_LBN 0
2137 #define	PCRF_AB_SI0_WIDTH 8
2138 
2139 
2140 /*
2141  * PC_PHY_STAT_REG(32bit):
2142  * PHY status register
2143  */
2144 
2145 #define	PCR_AB_PHY_STAT_REG 0x00000720
2146 /* falcona0,falconb0=pci_f0_config */
2147 
2148 #define	PCR_CC_PHY_STAT_REG 0x00000810
2149 /* sienaa0=pci_f0_config */
2150 
2151 #define	PCRF_AC_SSL_LBN 3
2152 #define	PCRF_AC_SSL_WIDTH 1
2153 #define	PCRF_AC_SSR_LBN 2
2154 #define	PCRF_AC_SSR_WIDTH 1
2155 #define	PCRF_AC_SSCL_LBN 1
2156 #define	PCRF_AC_SSCL_WIDTH 1
2157 #define	PCRF_AC_SSCD_LBN 0
2158 #define	PCRF_AC_SSCD_WIDTH 1
2159 
2160 
2161 /*
2162  * PC_FLT_MSK_REG(32bit):
2163  * Filter Mask Register 2
2164  */
2165 
2166 #define	PCR_CC_FLT_MSK_REG 0x00000720
2167 /* sienaa0=pci_f0_config */
2168 
2169 #define	PCRF_CC_DEFAULT_FLT_MSK2_LBN 0
2170 #define	PCRF_CC_DEFAULT_FLT_MSK2_WIDTH 32
2171 
2172 
2173 /*
2174  * PC_PHY_CTL_REG(32bit):
2175  * PHY control register
2176  */
2177 
2178 #define	PCR_AB_PHY_CTL_REG 0x00000724
2179 /* falcona0,falconb0=pci_f0_config */
2180 
2181 #define	PCR_CC_PHY_CTL_REG 0x00000814
2182 /* sienaa0=pci_f0_config */
2183 
2184 #define	PCRF_AC_BD_LBN 31
2185 #define	PCRF_AC_BD_WIDTH 1
2186 #define	PCRF_AC_CDS_LBN 30
2187 #define	PCRF_AC_CDS_WIDTH 1
2188 #define	PCRF_AC_DWRAP_LB_LBN 29
2189 #define	PCRF_AC_DWRAP_LB_WIDTH 1
2190 #define	PCRF_AC_EBD_LBN 28
2191 #define	PCRF_AC_EBD_WIDTH 1
2192 #define	PCRF_AC_SNR_LBN 27
2193 #define	PCRF_AC_SNR_WIDTH 1
2194 #define	PCRF_AC_RX_NOT_DET_LBN 2
2195 #define	PCRF_AC_RX_NOT_DET_WIDTH 1
2196 #define	PCRF_AC_FORCE_LOS_VAL_LBN 1
2197 #define	PCRF_AC_FORCE_LOS_VAL_WIDTH 1
2198 #define	PCRF_AC_FORCE_LOS_EN_LBN 0
2199 #define	PCRF_AC_FORCE_LOS_EN_WIDTH 1
2200 
2201 
2202 /*
2203  * PC_DEBUG0_REG(32bit):
2204  * Debug register 0
2205  */
2206 
2207 #define	PCR_AC_DEBUG0_REG 0x00000728
2208 /* falcona0,falconb0,sienaa0=pci_f0_config */
2209 
2210 #define	PCRF_AC_CDI03_LBN 24
2211 #define	PCRF_AC_CDI03_WIDTH 8
2212 #define	PCRF_AC_CDI0_LBN 0
2213 #define	PCRF_AC_CDI0_WIDTH 32
2214 #define	PCRF_AC_CDI02_LBN 16
2215 #define	PCRF_AC_CDI02_WIDTH 8
2216 #define	PCRF_AC_CDI01_LBN 8
2217 #define	PCRF_AC_CDI01_WIDTH 8
2218 #define	PCRF_AC_CDI00_LBN 0
2219 #define	PCRF_AC_CDI00_WIDTH 8
2220 
2221 
2222 /*
2223  * PC_DEBUG1_REG(32bit):
2224  * Debug register 1
2225  */
2226 
2227 #define	PCR_AC_DEBUG1_REG 0x0000072c
2228 /* falcona0,falconb0,sienaa0=pci_f0_config */
2229 
2230 #define	PCRF_AC_CDI13_LBN 24
2231 #define	PCRF_AC_CDI13_WIDTH 8
2232 #define	PCRF_AC_CDI1_LBN 0
2233 #define	PCRF_AC_CDI1_WIDTH 32
2234 #define	PCRF_AC_CDI12_LBN 16
2235 #define	PCRF_AC_CDI12_WIDTH 8
2236 #define	PCRF_AC_CDI11_LBN 8
2237 #define	PCRF_AC_CDI11_WIDTH 8
2238 #define	PCRF_AC_CDI10_LBN 0
2239 #define	PCRF_AC_CDI10_WIDTH 8
2240 
2241 
2242 /*
2243  * PC_XPFCC_STAT_REG(24bit):
2244  * documentation to be written for sum_PC_XPFCC_STAT_REG
2245  */
2246 
2247 #define	PCR_AC_XPFCC_STAT_REG 0x00000730
2248 /* falcona0,falconb0,sienaa0=pci_f0_config */
2249 
2250 #define	PCRF_AC_XPDC_LBN 12
2251 #define	PCRF_AC_XPDC_WIDTH 8
2252 #define	PCRF_AC_XPHC_LBN 0
2253 #define	PCRF_AC_XPHC_WIDTH 12
2254 
2255 
2256 /*
2257  * PC_XNPFCC_STAT_REG(24bit):
2258  * documentation to be written for sum_PC_XNPFCC_STAT_REG
2259  */
2260 
2261 #define	PCR_AC_XNPFCC_STAT_REG 0x00000734
2262 /* falcona0,falconb0,sienaa0=pci_f0_config */
2263 
2264 #define	PCRF_AC_XNPDC_LBN 12
2265 #define	PCRF_AC_XNPDC_WIDTH 8
2266 #define	PCRF_AC_XNPHC_LBN 0
2267 #define	PCRF_AC_XNPHC_WIDTH 12
2268 
2269 
2270 /*
2271  * PC_XCFCC_STAT_REG(24bit):
2272  * documentation to be written for sum_PC_XCFCC_STAT_REG
2273  */
2274 
2275 #define	PCR_AC_XCFCC_STAT_REG 0x00000738
2276 /* falcona0,falconb0,sienaa0=pci_f0_config */
2277 
2278 #define	PCRF_AC_XCDC_LBN 12
2279 #define	PCRF_AC_XCDC_WIDTH 8
2280 #define	PCRF_AC_XCHC_LBN 0
2281 #define	PCRF_AC_XCHC_WIDTH 12
2282 
2283 
2284 /*
2285  * PC_Q_STAT_REG(8bit):
2286  * documentation to be written for sum_PC_Q_STAT_REG
2287  */
2288 
2289 #define	PCR_AC_Q_STAT_REG 0x0000073c
2290 /* falcona0,falconb0,sienaa0=pci_f0_config */
2291 
2292 #define	PCRF_AC_RQNE_LBN 2
2293 #define	PCRF_AC_RQNE_WIDTH 1
2294 #define	PCRF_AC_XRNE_LBN 1
2295 #define	PCRF_AC_XRNE_WIDTH 1
2296 #define	PCRF_AC_RCNR_LBN 0
2297 #define	PCRF_AC_RCNR_WIDTH 1
2298 
2299 
2300 /*
2301  * PC_VC_XMIT_ARB1_REG(32bit):
2302  * VC Transmit Arbitration Register 1
2303  */
2304 
2305 #define	PCR_CC_VC_XMIT_ARB1_REG 0x00000740
2306 /* sienaa0=pci_f0_config */
2307 
2308 
2309 
2310 /*
2311  * PC_VC_XMIT_ARB2_REG(32bit):
2312  * VC Transmit Arbitration Register 2
2313  */
2314 
2315 #define	PCR_CC_VC_XMIT_ARB2_REG 0x00000744
2316 /* sienaa0=pci_f0_config */
2317 
2318 
2319 
2320 /*
2321  * PC_VC0_P_RQ_CTL_REG(32bit):
2322  * VC0 Posted Receive Queue Control
2323  */
2324 
2325 #define	PCR_CC_VC0_P_RQ_CTL_REG 0x00000748
2326 /* sienaa0=pci_f0_config */
2327 
2328 
2329 
2330 /*
2331  * PC_VC0_NP_RQ_CTL_REG(32bit):
2332  * VC0 Non-Posted Receive Queue Control
2333  */
2334 
2335 #define	PCR_CC_VC0_NP_RQ_CTL_REG 0x0000074c
2336 /* sienaa0=pci_f0_config */
2337 
2338 
2339 
2340 /*
2341  * PC_VC0_C_RQ_CTL_REG(32bit):
2342  * VC0 Completion Receive Queue Control
2343  */
2344 
2345 #define	PCR_CC_VC0_C_RQ_CTL_REG 0x00000750
2346 /* sienaa0=pci_f0_config */
2347 
2348 
2349 
2350 /*
2351  * PC_GEN2_REG(32bit):
2352  * Gen2 Register
2353  */
2354 
2355 #define	PCR_CC_GEN2_REG 0x0000080c
2356 /* sienaa0=pci_f0_config */
2357 
2358 #define	PCRF_CC_SET_DE_EMPHASIS_LBN 20
2359 #define	PCRF_CC_SET_DE_EMPHASIS_WIDTH 1
2360 #define	PCRF_CC_CFG_TX_COMPLIANCE_LBN 19
2361 #define	PCRF_CC_CFG_TX_COMPLIANCE_WIDTH 1
2362 #define	PCRF_CC_CFG_TX_SWING_LBN 18
2363 #define	PCRF_CC_CFG_TX_SWING_WIDTH 1
2364 #define	PCRF_CC_DIR_SPEED_CHANGE_LBN 17
2365 #define	PCRF_CC_DIR_SPEED_CHANGE_WIDTH 1
2366 #define	PCRF_CC_LANE_ENABLE_LBN 8
2367 #define	PCRF_CC_LANE_ENABLE_WIDTH 9
2368 #define	PCRF_CC_NUM_FTS_LBN 0
2369 #define	PCRF_CC_NUM_FTS_WIDTH 8
2370 
2371 
2372 #ifdef	__cplusplus
2373 }
2374 #endif
2375 
2376 #endif /* _SYS_EFX_REGS_PCI_H */
2377