1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2007-2016 Solarflare Communications Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 18 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 26 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * The views and conclusions contained in the software and documentation are 29 * those of the authors and should not be interpreted as representing official 30 * policies, either expressed or implied, of the FreeBSD Project. 31 * 32 * $FreeBSD$ 33 */ 34 35 #ifndef _SYS_EFX_REGS_PCI_H 36 #define _SYS_EFX_REGS_PCI_H 37 38 #ifdef __cplusplus 39 extern "C" { 40 #endif 41 42 /* 43 * PC_VEND_ID_REG(16bit): 44 * Vendor ID register 45 */ 46 47 #define PCR_AZ_VEND_ID_REG 0x00000000 48 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 49 50 #define PCRF_AZ_VEND_ID_LBN 0 51 #define PCRF_AZ_VEND_ID_WIDTH 16 52 53 /* 54 * PC_DEV_ID_REG(16bit): 55 * Device ID register 56 */ 57 58 #define PCR_AZ_DEV_ID_REG 0x00000002 59 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 60 61 #define PCRF_AZ_DEV_ID_LBN 0 62 #define PCRF_AZ_DEV_ID_WIDTH 16 63 64 /* 65 * PC_CMD_REG(16bit): 66 * Command register 67 */ 68 69 #define PCR_AZ_CMD_REG 0x00000004 70 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 71 72 #define PCRF_AZ_INTX_DIS_LBN 10 73 #define PCRF_AZ_INTX_DIS_WIDTH 1 74 #define PCRF_AZ_FB2B_EN_LBN 9 75 #define PCRF_AZ_FB2B_EN_WIDTH 1 76 #define PCRF_AZ_SERR_EN_LBN 8 77 #define PCRF_AZ_SERR_EN_WIDTH 1 78 #define PCRF_AZ_IDSEL_CTL_LBN 7 79 #define PCRF_AZ_IDSEL_CTL_WIDTH 1 80 #define PCRF_AZ_PERR_EN_LBN 6 81 #define PCRF_AZ_PERR_EN_WIDTH 1 82 #define PCRF_AZ_VGA_PAL_SNP_LBN 5 83 #define PCRF_AZ_VGA_PAL_SNP_WIDTH 1 84 #define PCRF_AZ_MWI_EN_LBN 4 85 #define PCRF_AZ_MWI_EN_WIDTH 1 86 #define PCRF_AZ_SPEC_CYC_LBN 3 87 #define PCRF_AZ_SPEC_CYC_WIDTH 1 88 #define PCRF_AZ_MST_EN_LBN 2 89 #define PCRF_AZ_MST_EN_WIDTH 1 90 #define PCRF_AZ_MEM_EN_LBN 1 91 #define PCRF_AZ_MEM_EN_WIDTH 1 92 #define PCRF_AZ_IO_EN_LBN 0 93 #define PCRF_AZ_IO_EN_WIDTH 1 94 95 /* 96 * PC_STAT_REG(16bit): 97 * Status register 98 */ 99 100 #define PCR_AZ_STAT_REG 0x00000006 101 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 102 103 #define PCRF_AZ_DET_PERR_LBN 15 104 #define PCRF_AZ_DET_PERR_WIDTH 1 105 #define PCRF_AZ_SIG_SERR_LBN 14 106 #define PCRF_AZ_SIG_SERR_WIDTH 1 107 #define PCRF_AZ_GOT_MABRT_LBN 13 108 #define PCRF_AZ_GOT_MABRT_WIDTH 1 109 #define PCRF_AZ_GOT_TABRT_LBN 12 110 #define PCRF_AZ_GOT_TABRT_WIDTH 1 111 #define PCRF_AZ_SIG_TABRT_LBN 11 112 #define PCRF_AZ_SIG_TABRT_WIDTH 1 113 #define PCRF_AZ_DEVSEL_TIM_LBN 9 114 #define PCRF_AZ_DEVSEL_TIM_WIDTH 2 115 #define PCRF_AZ_MDAT_PERR_LBN 8 116 #define PCRF_AZ_MDAT_PERR_WIDTH 1 117 #define PCRF_AZ_FB2B_CAP_LBN 7 118 #define PCRF_AZ_FB2B_CAP_WIDTH 1 119 #define PCRF_AZ_66MHZ_CAP_LBN 5 120 #define PCRF_AZ_66MHZ_CAP_WIDTH 1 121 #define PCRF_AZ_CAP_LIST_LBN 4 122 #define PCRF_AZ_CAP_LIST_WIDTH 1 123 #define PCRF_AZ_INTX_STAT_LBN 3 124 #define PCRF_AZ_INTX_STAT_WIDTH 1 125 126 /* 127 * PC_REV_ID_REG(8bit): 128 * Class code & revision ID register 129 */ 130 131 #define PCR_AZ_REV_ID_REG 0x00000008 132 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 133 134 #define PCRF_AZ_REV_ID_LBN 0 135 #define PCRF_AZ_REV_ID_WIDTH 8 136 137 /* 138 * PC_CC_REG(24bit): 139 * Class code register 140 */ 141 142 #define PCR_AZ_CC_REG 0x00000009 143 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 144 145 #define PCRF_AZ_BASE_CC_LBN 16 146 #define PCRF_AZ_BASE_CC_WIDTH 8 147 #define PCRF_AZ_SUB_CC_LBN 8 148 #define PCRF_AZ_SUB_CC_WIDTH 8 149 #define PCRF_AZ_PROG_IF_LBN 0 150 #define PCRF_AZ_PROG_IF_WIDTH 8 151 152 /* 153 * PC_CACHE_LSIZE_REG(8bit): 154 * Cache line size 155 */ 156 157 #define PCR_AZ_CACHE_LSIZE_REG 0x0000000c 158 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 159 160 #define PCRF_AZ_CACHE_LSIZE_LBN 0 161 #define PCRF_AZ_CACHE_LSIZE_WIDTH 8 162 163 /* 164 * PC_MST_LAT_REG(8bit): 165 * Master latency timer register 166 */ 167 168 #define PCR_AZ_MST_LAT_REG 0x0000000d 169 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 170 171 #define PCRF_AZ_MST_LAT_LBN 0 172 #define PCRF_AZ_MST_LAT_WIDTH 8 173 174 /* 175 * PC_HDR_TYPE_REG(8bit): 176 * Header type register 177 */ 178 179 #define PCR_AZ_HDR_TYPE_REG 0x0000000e 180 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 181 182 #define PCRF_AZ_MULT_FUNC_LBN 7 183 #define PCRF_AZ_MULT_FUNC_WIDTH 1 184 #define PCRF_AZ_TYPE_LBN 0 185 #define PCRF_AZ_TYPE_WIDTH 7 186 187 /* 188 * PC_BIST_REG(8bit): 189 * BIST register 190 */ 191 192 #define PCR_AZ_BIST_REG 0x0000000f 193 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 194 195 #define PCRF_AZ_BIST_LBN 0 196 #define PCRF_AZ_BIST_WIDTH 8 197 198 /* 199 * PC_BAR0_REG(32bit): 200 * Primary function base address register 0 201 */ 202 203 #define PCR_AZ_BAR0_REG 0x00000010 204 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 205 206 #define PCRF_AZ_BAR0_LBN 4 207 #define PCRF_AZ_BAR0_WIDTH 28 208 #define PCRF_AZ_BAR0_PREF_LBN 3 209 #define PCRF_AZ_BAR0_PREF_WIDTH 1 210 #define PCRF_AZ_BAR0_TYPE_LBN 1 211 #define PCRF_AZ_BAR0_TYPE_WIDTH 2 212 #define PCRF_AZ_BAR0_IOM_LBN 0 213 #define PCRF_AZ_BAR0_IOM_WIDTH 1 214 215 /* 216 * PC_BAR1_REG(32bit): 217 * Primary function base address register 1, BAR1 is not implemented so read only. 218 */ 219 220 #define PCR_DZ_BAR1_REG 0x00000014 221 /* hunta0=pci_f0_config */ 222 223 #define PCRF_DZ_BAR1_LBN 0 224 #define PCRF_DZ_BAR1_WIDTH 32 225 226 /* 227 * PC_BAR2_LO_REG(32bit): 228 * Primary function base address register 2 low bits 229 */ 230 231 #define PCR_AZ_BAR2_LO_REG 0x00000018 232 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 233 234 #define PCRF_AZ_BAR2_LO_LBN 4 235 #define PCRF_AZ_BAR2_LO_WIDTH 28 236 #define PCRF_AZ_BAR2_PREF_LBN 3 237 #define PCRF_AZ_BAR2_PREF_WIDTH 1 238 #define PCRF_AZ_BAR2_TYPE_LBN 1 239 #define PCRF_AZ_BAR2_TYPE_WIDTH 2 240 #define PCRF_AZ_BAR2_IOM_LBN 0 241 #define PCRF_AZ_BAR2_IOM_WIDTH 1 242 243 /* 244 * PC_BAR2_HI_REG(32bit): 245 * Primary function base address register 2 high bits 246 */ 247 248 #define PCR_AZ_BAR2_HI_REG 0x0000001c 249 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 250 251 #define PCRF_AZ_BAR2_HI_LBN 0 252 #define PCRF_AZ_BAR2_HI_WIDTH 32 253 254 /* 255 * PC_BAR4_LO_REG(32bit): 256 * Primary function base address register 2 low bits 257 */ 258 259 #define PCR_CZ_BAR4_LO_REG 0x00000020 260 /* sienaa0,hunta0=pci_f0_config */ 261 262 #define PCRF_CZ_BAR4_LO_LBN 4 263 #define PCRF_CZ_BAR4_LO_WIDTH 28 264 #define PCRF_CZ_BAR4_PREF_LBN 3 265 #define PCRF_CZ_BAR4_PREF_WIDTH 1 266 #define PCRF_CZ_BAR4_TYPE_LBN 1 267 #define PCRF_CZ_BAR4_TYPE_WIDTH 2 268 #define PCRF_CZ_BAR4_IOM_LBN 0 269 #define PCRF_CZ_BAR4_IOM_WIDTH 1 270 271 /* 272 * PC_BAR4_HI_REG(32bit): 273 * Primary function base address register 2 high bits 274 */ 275 276 #define PCR_CZ_BAR4_HI_REG 0x00000024 277 /* sienaa0,hunta0=pci_f0_config */ 278 279 #define PCRF_CZ_BAR4_HI_LBN 0 280 #define PCRF_CZ_BAR4_HI_WIDTH 32 281 282 /* 283 * PC_SS_VEND_ID_REG(16bit): 284 * Sub-system vendor ID register 285 */ 286 287 #define PCR_AZ_SS_VEND_ID_REG 0x0000002c 288 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 289 290 #define PCRF_AZ_SS_VEND_ID_LBN 0 291 #define PCRF_AZ_SS_VEND_ID_WIDTH 16 292 293 /* 294 * PC_SS_ID_REG(16bit): 295 * Sub-system ID register 296 */ 297 298 #define PCR_AZ_SS_ID_REG 0x0000002e 299 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 300 301 #define PCRF_AZ_SS_ID_LBN 0 302 #define PCRF_AZ_SS_ID_WIDTH 16 303 304 /* 305 * PC_EXPROM_BAR_REG(32bit): 306 * Expansion ROM base address register 307 */ 308 309 #define PCR_AZ_EXPROM_BAR_REG 0x00000030 310 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 311 312 #define PCRF_AZ_EXPROM_BAR_LBN 11 313 #define PCRF_AZ_EXPROM_BAR_WIDTH 21 314 #define PCRF_AB_EXPROM_MIN_SIZE_LBN 2 315 #define PCRF_AB_EXPROM_MIN_SIZE_WIDTH 9 316 #define PCRF_CZ_EXPROM_MIN_SIZE_LBN 1 317 #define PCRF_CZ_EXPROM_MIN_SIZE_WIDTH 10 318 #define PCRF_AB_EXPROM_FEATURE_ENABLE_LBN 1 319 #define PCRF_AB_EXPROM_FEATURE_ENABLE_WIDTH 1 320 #define PCRF_AZ_EXPROM_EN_LBN 0 321 #define PCRF_AZ_EXPROM_EN_WIDTH 1 322 323 /* 324 * PC_CAP_PTR_REG(8bit): 325 * Capability pointer register 326 */ 327 328 #define PCR_AZ_CAP_PTR_REG 0x00000034 329 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 330 331 #define PCRF_AZ_CAP_PTR_LBN 0 332 #define PCRF_AZ_CAP_PTR_WIDTH 8 333 334 /* 335 * PC_INT_LINE_REG(8bit): 336 * Interrupt line register 337 */ 338 339 #define PCR_AZ_INT_LINE_REG 0x0000003c 340 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 341 342 #define PCRF_AZ_INT_LINE_LBN 0 343 #define PCRF_AZ_INT_LINE_WIDTH 8 344 345 /* 346 * PC_INT_PIN_REG(8bit): 347 * Interrupt pin register 348 */ 349 350 #define PCR_AZ_INT_PIN_REG 0x0000003d 351 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 352 353 #define PCRF_AZ_INT_PIN_LBN 0 354 #define PCRF_AZ_INT_PIN_WIDTH 8 355 #define PCFE_DZ_INTPIN_INTD 4 356 #define PCFE_DZ_INTPIN_INTC 3 357 #define PCFE_DZ_INTPIN_INTB 2 358 #define PCFE_DZ_INTPIN_INTA 1 359 360 /* 361 * PC_PM_CAP_ID_REG(8bit): 362 * Power management capability ID 363 */ 364 365 #define PCR_AZ_PM_CAP_ID_REG 0x00000040 366 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 367 368 #define PCRF_AZ_PM_CAP_ID_LBN 0 369 #define PCRF_AZ_PM_CAP_ID_WIDTH 8 370 371 /* 372 * PC_PM_NXT_PTR_REG(8bit): 373 * Power management next item pointer 374 */ 375 376 #define PCR_AZ_PM_NXT_PTR_REG 0x00000041 377 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 378 379 #define PCRF_AZ_PM_NXT_PTR_LBN 0 380 #define PCRF_AZ_PM_NXT_PTR_WIDTH 8 381 382 /* 383 * PC_PM_CAP_REG(16bit): 384 * Power management capabilities register 385 */ 386 387 #define PCR_AZ_PM_CAP_REG 0x00000042 388 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 389 390 #define PCRF_AZ_PM_PME_SUPT_LBN 11 391 #define PCRF_AZ_PM_PME_SUPT_WIDTH 5 392 #define PCRF_AZ_PM_D2_SUPT_LBN 10 393 #define PCRF_AZ_PM_D2_SUPT_WIDTH 1 394 #define PCRF_AZ_PM_D1_SUPT_LBN 9 395 #define PCRF_AZ_PM_D1_SUPT_WIDTH 1 396 #define PCRF_AZ_PM_AUX_CURR_LBN 6 397 #define PCRF_AZ_PM_AUX_CURR_WIDTH 3 398 #define PCRF_AZ_PM_DSI_LBN 5 399 #define PCRF_AZ_PM_DSI_WIDTH 1 400 #define PCRF_AZ_PM_PME_CLK_LBN 3 401 #define PCRF_AZ_PM_PME_CLK_WIDTH 1 402 #define PCRF_AZ_PM_PME_VER_LBN 0 403 #define PCRF_AZ_PM_PME_VER_WIDTH 3 404 405 /* 406 * PC_PM_CS_REG(16bit): 407 * Power management control & status register 408 */ 409 410 #define PCR_AZ_PM_CS_REG 0x00000044 411 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 412 413 #define PCRF_AZ_PM_PME_STAT_LBN 15 414 #define PCRF_AZ_PM_PME_STAT_WIDTH 1 415 #define PCRF_AZ_PM_DAT_SCALE_LBN 13 416 #define PCRF_AZ_PM_DAT_SCALE_WIDTH 2 417 #define PCRF_AZ_PM_DAT_SEL_LBN 9 418 #define PCRF_AZ_PM_DAT_SEL_WIDTH 4 419 #define PCRF_AZ_PM_PME_EN_LBN 8 420 #define PCRF_AZ_PM_PME_EN_WIDTH 1 421 #define PCRF_CZ_NO_SOFT_RESET_LBN 3 422 #define PCRF_CZ_NO_SOFT_RESET_WIDTH 1 423 #define PCRF_AZ_PM_PWR_ST_LBN 0 424 #define PCRF_AZ_PM_PWR_ST_WIDTH 2 425 426 /* 427 * PC_MSI_CAP_ID_REG(8bit): 428 * MSI capability ID 429 */ 430 431 #define PCR_AZ_MSI_CAP_ID_REG 0x00000050 432 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 433 434 #define PCRF_AZ_MSI_CAP_ID_LBN 0 435 #define PCRF_AZ_MSI_CAP_ID_WIDTH 8 436 437 /* 438 * PC_MSI_NXT_PTR_REG(8bit): 439 * MSI next item pointer 440 */ 441 442 #define PCR_AZ_MSI_NXT_PTR_REG 0x00000051 443 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 444 445 #define PCRF_AZ_MSI_NXT_PTR_LBN 0 446 #define PCRF_AZ_MSI_NXT_PTR_WIDTH 8 447 448 /* 449 * PC_MSI_CTL_REG(16bit): 450 * MSI control register 451 */ 452 453 #define PCR_AZ_MSI_CTL_REG 0x00000052 454 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 455 456 #define PCRF_AZ_MSI_64_EN_LBN 7 457 #define PCRF_AZ_MSI_64_EN_WIDTH 1 458 #define PCRF_AZ_MSI_MULT_MSG_EN_LBN 4 459 #define PCRF_AZ_MSI_MULT_MSG_EN_WIDTH 3 460 #define PCRF_AZ_MSI_MULT_MSG_CAP_LBN 1 461 #define PCRF_AZ_MSI_MULT_MSG_CAP_WIDTH 3 462 #define PCRF_AZ_MSI_EN_LBN 0 463 #define PCRF_AZ_MSI_EN_WIDTH 1 464 465 /* 466 * PC_MSI_ADR_LO_REG(32bit): 467 * MSI low 32 bits address register 468 */ 469 470 #define PCR_AZ_MSI_ADR_LO_REG 0x00000054 471 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 472 473 #define PCRF_AZ_MSI_ADR_LO_LBN 2 474 #define PCRF_AZ_MSI_ADR_LO_WIDTH 30 475 476 /* 477 * PC_MSI_ADR_HI_REG(32bit): 478 * MSI high 32 bits address register 479 */ 480 481 #define PCR_AZ_MSI_ADR_HI_REG 0x00000058 482 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 483 484 #define PCRF_AZ_MSI_ADR_HI_LBN 0 485 #define PCRF_AZ_MSI_ADR_HI_WIDTH 32 486 487 /* 488 * PC_MSI_DAT_REG(16bit): 489 * MSI data register 490 */ 491 492 #define PCR_AZ_MSI_DAT_REG 0x0000005c 493 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 494 495 #define PCRF_AZ_MSI_DAT_LBN 0 496 #define PCRF_AZ_MSI_DAT_WIDTH 16 497 498 /* 499 * PC_PCIE_CAP_LIST_REG(16bit): 500 * PCIe capability list register 501 */ 502 503 #define PCR_AB_PCIE_CAP_LIST_REG 0x00000060 504 /* falcona0,falconb0=pci_f0_config */ 505 506 #define PCR_CZ_PCIE_CAP_LIST_REG 0x00000070 507 /* sienaa0,hunta0=pci_f0_config */ 508 509 #define PCRF_AZ_PCIE_NXT_PTR_LBN 8 510 #define PCRF_AZ_PCIE_NXT_PTR_WIDTH 8 511 #define PCRF_AZ_PCIE_CAP_ID_LBN 0 512 #define PCRF_AZ_PCIE_CAP_ID_WIDTH 8 513 514 /* 515 * PC_PCIE_CAP_REG(16bit): 516 * PCIe capability register 517 */ 518 519 #define PCR_AB_PCIE_CAP_REG 0x00000062 520 /* falcona0,falconb0=pci_f0_config */ 521 522 #define PCR_CZ_PCIE_CAP_REG 0x00000072 523 /* sienaa0,hunta0=pci_f0_config */ 524 525 #define PCRF_AZ_PCIE_INT_MSG_NUM_LBN 9 526 #define PCRF_AZ_PCIE_INT_MSG_NUM_WIDTH 5 527 #define PCRF_AZ_PCIE_SLOT_IMP_LBN 8 528 #define PCRF_AZ_PCIE_SLOT_IMP_WIDTH 1 529 #define PCRF_AZ_PCIE_DEV_PORT_TYPE_LBN 4 530 #define PCRF_AZ_PCIE_DEV_PORT_TYPE_WIDTH 4 531 #define PCRF_AZ_PCIE_CAP_VER_LBN 0 532 #define PCRF_AZ_PCIE_CAP_VER_WIDTH 4 533 534 /* 535 * PC_DEV_CAP_REG(32bit): 536 * PCIe device capabilities register 537 */ 538 539 #define PCR_AB_DEV_CAP_REG 0x00000064 540 /* falcona0,falconb0=pci_f0_config */ 541 542 #define PCR_CZ_DEV_CAP_REG 0x00000074 543 /* sienaa0=pci_f0_config,hunta0=pci_f0_config */ 544 545 #define PCRF_CZ_CAP_FN_LEVEL_RESET_LBN 28 546 #define PCRF_CZ_CAP_FN_LEVEL_RESET_WIDTH 1 547 #define PCRF_AZ_CAP_SLOT_PWR_SCL_LBN 26 548 #define PCRF_AZ_CAP_SLOT_PWR_SCL_WIDTH 2 549 #define PCRF_AZ_CAP_SLOT_PWR_VAL_LBN 18 550 #define PCRF_AZ_CAP_SLOT_PWR_VAL_WIDTH 8 551 #define PCRF_CZ_ROLE_BASE_ERR_REPORTING_LBN 15 552 #define PCRF_CZ_ROLE_BASE_ERR_REPORTING_WIDTH 1 553 #define PCRF_AB_PWR_IND_LBN 14 554 #define PCRF_AB_PWR_IND_WIDTH 1 555 #define PCRF_AB_ATTN_IND_LBN 13 556 #define PCRF_AB_ATTN_IND_WIDTH 1 557 #define PCRF_AB_ATTN_BUTTON_LBN 12 558 #define PCRF_AB_ATTN_BUTTON_WIDTH 1 559 #define PCRF_AZ_ENDPT_L1_LAT_LBN 9 560 #define PCRF_AZ_ENDPT_L1_LAT_WIDTH 3 561 #define PCRF_AZ_ENDPT_L0_LAT_LBN 6 562 #define PCRF_AZ_ENDPT_L0_LAT_WIDTH 3 563 #define PCRF_AZ_TAG_FIELD_LBN 5 564 #define PCRF_AZ_TAG_FIELD_WIDTH 1 565 #define PCRF_AZ_PHAN_FUNC_LBN 3 566 #define PCRF_AZ_PHAN_FUNC_WIDTH 2 567 #define PCRF_AZ_MAX_PAYL_SIZE_SUPT_LBN 0 568 #define PCRF_AZ_MAX_PAYL_SIZE_SUPT_WIDTH 3 569 570 /* 571 * PC_DEV_CTL_REG(16bit): 572 * PCIe device control register 573 */ 574 575 #define PCR_AB_DEV_CTL_REG 0x00000068 576 /* falcona0,falconb0=pci_f0_config */ 577 578 #define PCR_CZ_DEV_CTL_REG 0x00000078 579 /* sienaa0,hunta0=pci_f0_config */ 580 581 #define PCRF_CZ_FN_LEVEL_RESET_LBN 15 582 #define PCRF_CZ_FN_LEVEL_RESET_WIDTH 1 583 #define PCRF_AZ_MAX_RD_REQ_SIZE_LBN 12 584 #define PCRF_AZ_MAX_RD_REQ_SIZE_WIDTH 3 585 #define PCFE_AZ_MAX_RD_REQ_SIZE_4096 5 586 #define PCFE_AZ_MAX_RD_REQ_SIZE_2048 4 587 #define PCFE_AZ_MAX_RD_REQ_SIZE_1024 3 588 #define PCFE_AZ_MAX_RD_REQ_SIZE_512 2 589 #define PCFE_AZ_MAX_RD_REQ_SIZE_256 1 590 #define PCFE_AZ_MAX_RD_REQ_SIZE_128 0 591 #define PCRF_AZ_EN_NO_SNOOP_LBN 11 592 #define PCRF_AZ_EN_NO_SNOOP_WIDTH 1 593 #define PCRF_AZ_AUX_PWR_PM_EN_LBN 10 594 #define PCRF_AZ_AUX_PWR_PM_EN_WIDTH 1 595 #define PCRF_AZ_PHAN_FUNC_EN_LBN 9 596 #define PCRF_AZ_PHAN_FUNC_EN_WIDTH 1 597 #define PCRF_AB_DEV_CAP_REG_RSVD0_LBN 8 598 #define PCRF_AB_DEV_CAP_REG_RSVD0_WIDTH 1 599 #define PCRF_CZ_EXTENDED_TAG_EN_LBN 8 600 #define PCRF_CZ_EXTENDED_TAG_EN_WIDTH 1 601 #define PCRF_AZ_MAX_PAYL_SIZE_LBN 5 602 #define PCRF_AZ_MAX_PAYL_SIZE_WIDTH 3 603 #define PCFE_AZ_MAX_PAYL_SIZE_4096 5 604 #define PCFE_AZ_MAX_PAYL_SIZE_2048 4 605 #define PCFE_AZ_MAX_PAYL_SIZE_1024 3 606 #define PCFE_AZ_MAX_PAYL_SIZE_512 2 607 #define PCFE_AZ_MAX_PAYL_SIZE_256 1 608 #define PCFE_AZ_MAX_PAYL_SIZE_128 0 609 #define PCRF_AZ_EN_RELAX_ORDER_LBN 4 610 #define PCRF_AZ_EN_RELAX_ORDER_WIDTH 1 611 #define PCRF_AZ_UNSUP_REQ_RPT_EN_LBN 3 612 #define PCRF_AZ_UNSUP_REQ_RPT_EN_WIDTH 1 613 #define PCRF_AZ_FATAL_ERR_RPT_EN_LBN 2 614 #define PCRF_AZ_FATAL_ERR_RPT_EN_WIDTH 1 615 #define PCRF_AZ_NONFATAL_ERR_RPT_EN_LBN 1 616 #define PCRF_AZ_NONFATAL_ERR_RPT_EN_WIDTH 1 617 #define PCRF_AZ_CORR_ERR_RPT_EN_LBN 0 618 #define PCRF_AZ_CORR_ERR_RPT_EN_WIDTH 1 619 620 /* 621 * PC_DEV_STAT_REG(16bit): 622 * PCIe device status register 623 */ 624 625 #define PCR_AB_DEV_STAT_REG 0x0000006a 626 /* falcona0,falconb0=pci_f0_config */ 627 628 #define PCR_CZ_DEV_STAT_REG 0x0000007a 629 /* sienaa0,hunta0=pci_f0_config */ 630 631 #define PCRF_AZ_TRNS_PEND_LBN 5 632 #define PCRF_AZ_TRNS_PEND_WIDTH 1 633 #define PCRF_AZ_AUX_PWR_DET_LBN 4 634 #define PCRF_AZ_AUX_PWR_DET_WIDTH 1 635 #define PCRF_AZ_UNSUP_REQ_DET_LBN 3 636 #define PCRF_AZ_UNSUP_REQ_DET_WIDTH 1 637 #define PCRF_AZ_FATAL_ERR_DET_LBN 2 638 #define PCRF_AZ_FATAL_ERR_DET_WIDTH 1 639 #define PCRF_AZ_NONFATAL_ERR_DET_LBN 1 640 #define PCRF_AZ_NONFATAL_ERR_DET_WIDTH 1 641 #define PCRF_AZ_CORR_ERR_DET_LBN 0 642 #define PCRF_AZ_CORR_ERR_DET_WIDTH 1 643 644 /* 645 * PC_LNK_CAP_REG(32bit): 646 * PCIe link capabilities register 647 */ 648 649 #define PCR_AB_LNK_CAP_REG 0x0000006c 650 /* falcona0,falconb0=pci_f0_config */ 651 652 #define PCR_CZ_LNK_CAP_REG 0x0000007c 653 /* sienaa0,hunta0=pci_f0_config */ 654 655 #define PCRF_AZ_PORT_NUM_LBN 24 656 #define PCRF_AZ_PORT_NUM_WIDTH 8 657 #define PCRF_DZ_ASPM_OPTIONALITY_CAP_LBN 22 658 #define PCRF_DZ_ASPM_OPTIONALITY_CAP_WIDTH 1 659 #define PCRF_CZ_LINK_BWDITH_NOTIF_CAP_LBN 21 660 #define PCRF_CZ_LINK_BWDITH_NOTIF_CAP_WIDTH 1 661 #define PCRF_CZ_DATA_LINK_ACTIVE_RPT_CAP_LBN 20 662 #define PCRF_CZ_DATA_LINK_ACTIVE_RPT_CAP_WIDTH 1 663 #define PCRF_CZ_SURPISE_DOWN_RPT_CAP_LBN 19 664 #define PCRF_CZ_SURPISE_DOWN_RPT_CAP_WIDTH 1 665 #define PCRF_CZ_CLOCK_PWR_MNGMNT_CAP_LBN 18 666 #define PCRF_CZ_CLOCK_PWR_MNGMNT_CAP_WIDTH 1 667 #define PCRF_AZ_DEF_L1_EXIT_LAT_LBN 15 668 #define PCRF_AZ_DEF_L1_EXIT_LAT_WIDTH 3 669 #define PCRF_AZ_DEF_L0_EXIT_LATPORT_NUM_LBN 12 670 #define PCRF_AZ_DEF_L0_EXIT_LATPORT_NUM_WIDTH 3 671 #define PCRF_AZ_AS_LNK_PM_SUPT_LBN 10 672 #define PCRF_AZ_AS_LNK_PM_SUPT_WIDTH 2 673 #define PCRF_AZ_MAX_LNK_WIDTH_LBN 4 674 #define PCRF_AZ_MAX_LNK_WIDTH_WIDTH 6 675 #define PCRF_AZ_MAX_LNK_SP_LBN 0 676 #define PCRF_AZ_MAX_LNK_SP_WIDTH 4 677 678 /* 679 * PC_LNK_CTL_REG(16bit): 680 * PCIe link control register 681 */ 682 683 #define PCR_AB_LNK_CTL_REG 0x00000070 684 /* falcona0,falconb0=pci_f0_config */ 685 686 #define PCR_CZ_LNK_CTL_REG 0x00000080 687 /* sienaa0,hunta0=pci_f0_config */ 688 689 #define PCRF_AZ_EXT_SYNC_LBN 7 690 #define PCRF_AZ_EXT_SYNC_WIDTH 1 691 #define PCRF_AZ_COMM_CLK_CFG_LBN 6 692 #define PCRF_AZ_COMM_CLK_CFG_WIDTH 1 693 #define PCRF_AB_LNK_CTL_REG_RSVD0_LBN 5 694 #define PCRF_AB_LNK_CTL_REG_RSVD0_WIDTH 1 695 #define PCRF_CZ_LNK_RETRAIN_LBN 5 696 #define PCRF_CZ_LNK_RETRAIN_WIDTH 1 697 #define PCRF_AZ_LNK_DIS_LBN 4 698 #define PCRF_AZ_LNK_DIS_WIDTH 1 699 #define PCRF_AZ_RD_COM_BDRY_LBN 3 700 #define PCRF_AZ_RD_COM_BDRY_WIDTH 1 701 #define PCRF_AZ_ACT_ST_LNK_PM_CTL_LBN 0 702 #define PCRF_AZ_ACT_ST_LNK_PM_CTL_WIDTH 2 703 704 /* 705 * PC_LNK_STAT_REG(16bit): 706 * PCIe link status register 707 */ 708 709 #define PCR_AB_LNK_STAT_REG 0x00000072 710 /* falcona0,falconb0=pci_f0_config */ 711 712 #define PCR_CZ_LNK_STAT_REG 0x00000082 713 /* sienaa0,hunta0=pci_f0_config */ 714 715 #define PCRF_AZ_SLOT_CLK_CFG_LBN 12 716 #define PCRF_AZ_SLOT_CLK_CFG_WIDTH 1 717 #define PCRF_AZ_LNK_TRAIN_LBN 11 718 #define PCRF_AZ_LNK_TRAIN_WIDTH 1 719 #define PCRF_AB_TRAIN_ERR_LBN 10 720 #define PCRF_AB_TRAIN_ERR_WIDTH 1 721 #define PCRF_AZ_LNK_WIDTH_LBN 4 722 #define PCRF_AZ_LNK_WIDTH_WIDTH 6 723 #define PCRF_AZ_LNK_SP_LBN 0 724 #define PCRF_AZ_LNK_SP_WIDTH 4 725 726 /* 727 * PC_SLOT_CAP_REG(32bit): 728 * PCIe slot capabilities register 729 */ 730 731 #define PCR_AB_SLOT_CAP_REG 0x00000074 732 /* falcona0,falconb0=pci_f0_config */ 733 734 #define PCRF_AB_SLOT_NUM_LBN 19 735 #define PCRF_AB_SLOT_NUM_WIDTH 13 736 #define PCRF_AB_SLOT_PWR_LIM_SCL_LBN 15 737 #define PCRF_AB_SLOT_PWR_LIM_SCL_WIDTH 2 738 #define PCRF_AB_SLOT_PWR_LIM_VAL_LBN 7 739 #define PCRF_AB_SLOT_PWR_LIM_VAL_WIDTH 8 740 #define PCRF_AB_SLOT_HP_CAP_LBN 6 741 #define PCRF_AB_SLOT_HP_CAP_WIDTH 1 742 #define PCRF_AB_SLOT_HP_SURP_LBN 5 743 #define PCRF_AB_SLOT_HP_SURP_WIDTH 1 744 #define PCRF_AB_SLOT_PWR_IND_PRST_LBN 4 745 #define PCRF_AB_SLOT_PWR_IND_PRST_WIDTH 1 746 #define PCRF_AB_SLOT_ATTN_IND_PRST_LBN 3 747 #define PCRF_AB_SLOT_ATTN_IND_PRST_WIDTH 1 748 #define PCRF_AB_SLOT_MRL_SENS_PRST_LBN 2 749 #define PCRF_AB_SLOT_MRL_SENS_PRST_WIDTH 1 750 #define PCRF_AB_SLOT_PWR_CTL_PRST_LBN 1 751 #define PCRF_AB_SLOT_PWR_CTL_PRST_WIDTH 1 752 #define PCRF_AB_SLOT_ATTN_BUT_PRST_LBN 0 753 #define PCRF_AB_SLOT_ATTN_BUT_PRST_WIDTH 1 754 755 /* 756 * PC_SLOT_CTL_REG(16bit): 757 * PCIe slot control register 758 */ 759 760 #define PCR_AB_SLOT_CTL_REG 0x00000078 761 /* falcona0,falconb0=pci_f0_config */ 762 763 #define PCRF_AB_SLOT_PWR_CTLR_CTL_LBN 10 764 #define PCRF_AB_SLOT_PWR_CTLR_CTL_WIDTH 1 765 #define PCRF_AB_SLOT_PWR_IND_CTL_LBN 8 766 #define PCRF_AB_SLOT_PWR_IND_CTL_WIDTH 2 767 #define PCRF_AB_SLOT_ATT_IND_CTL_LBN 6 768 #define PCRF_AB_SLOT_ATT_IND_CTL_WIDTH 2 769 #define PCRF_AB_SLOT_HP_INT_EN_LBN 5 770 #define PCRF_AB_SLOT_HP_INT_EN_WIDTH 1 771 #define PCRF_AB_SLOT_CMD_COMP_INT_EN_LBN 4 772 #define PCRF_AB_SLOT_CMD_COMP_INT_EN_WIDTH 1 773 #define PCRF_AB_SLOT_PRES_DET_CHG_EN_LBN 3 774 #define PCRF_AB_SLOT_PRES_DET_CHG_EN_WIDTH 1 775 #define PCRF_AB_SLOT_MRL_SENS_CHG_EN_LBN 2 776 #define PCRF_AB_SLOT_MRL_SENS_CHG_EN_WIDTH 1 777 #define PCRF_AB_SLOT_PWR_FLTDET_EN_LBN 1 778 #define PCRF_AB_SLOT_PWR_FLTDET_EN_WIDTH 1 779 #define PCRF_AB_SLOT_ATTN_BUT_EN_LBN 0 780 #define PCRF_AB_SLOT_ATTN_BUT_EN_WIDTH 1 781 782 /* 783 * PC_SLOT_STAT_REG(16bit): 784 * PCIe slot status register 785 */ 786 787 #define PCR_AB_SLOT_STAT_REG 0x0000007a 788 /* falcona0,falconb0=pci_f0_config */ 789 790 #define PCRF_AB_PRES_DET_ST_LBN 6 791 #define PCRF_AB_PRES_DET_ST_WIDTH 1 792 #define PCRF_AB_MRL_SENS_ST_LBN 5 793 #define PCRF_AB_MRL_SENS_ST_WIDTH 1 794 #define PCRF_AB_SLOT_PWR_IND_LBN 4 795 #define PCRF_AB_SLOT_PWR_IND_WIDTH 1 796 #define PCRF_AB_SLOT_ATTN_IND_LBN 3 797 #define PCRF_AB_SLOT_ATTN_IND_WIDTH 1 798 #define PCRF_AB_SLOT_MRL_SENS_LBN 2 799 #define PCRF_AB_SLOT_MRL_SENS_WIDTH 1 800 #define PCRF_AB_PWR_FLTDET_LBN 1 801 #define PCRF_AB_PWR_FLTDET_WIDTH 1 802 #define PCRF_AB_ATTN_BUTDET_LBN 0 803 #define PCRF_AB_ATTN_BUTDET_WIDTH 1 804 805 /* 806 * PC_MSIX_CAP_ID_REG(8bit): 807 * MSIX Capability ID 808 */ 809 810 #define PCR_BB_MSIX_CAP_ID_REG 0x00000090 811 /* falconb0=pci_f0_config */ 812 813 #define PCR_CZ_MSIX_CAP_ID_REG 0x000000b0 814 /* sienaa0,hunta0=pci_f0_config */ 815 816 #define PCRF_BZ_MSIX_CAP_ID_LBN 0 817 #define PCRF_BZ_MSIX_CAP_ID_WIDTH 8 818 819 /* 820 * PC_MSIX_NXT_PTR_REG(8bit): 821 * MSIX Capability Next Capability Ptr 822 */ 823 824 #define PCR_BB_MSIX_NXT_PTR_REG 0x00000091 825 /* falconb0=pci_f0_config */ 826 827 #define PCR_CZ_MSIX_NXT_PTR_REG 0x000000b1 828 /* sienaa0,hunta0=pci_f0_config */ 829 830 #define PCRF_BZ_MSIX_NXT_PTR_LBN 0 831 #define PCRF_BZ_MSIX_NXT_PTR_WIDTH 8 832 833 /* 834 * PC_MSIX_CTL_REG(16bit): 835 * MSIX control register 836 */ 837 838 #define PCR_BB_MSIX_CTL_REG 0x00000092 839 /* falconb0=pci_f0_config */ 840 841 #define PCR_CZ_MSIX_CTL_REG 0x000000b2 842 /* sienaa0,hunta0=pci_f0_config */ 843 844 #define PCRF_BZ_MSIX_EN_LBN 15 845 #define PCRF_BZ_MSIX_EN_WIDTH 1 846 #define PCRF_BZ_MSIX_FUNC_MASK_LBN 14 847 #define PCRF_BZ_MSIX_FUNC_MASK_WIDTH 1 848 #define PCRF_BZ_MSIX_TBL_SIZE_LBN 0 849 #define PCRF_BZ_MSIX_TBL_SIZE_WIDTH 11 850 851 /* 852 * PC_MSIX_TBL_BASE_REG(32bit): 853 * MSIX Capability Vector Table Base 854 */ 855 856 #define PCR_BB_MSIX_TBL_BASE_REG 0x00000094 857 /* falconb0=pci_f0_config */ 858 859 #define PCR_CZ_MSIX_TBL_BASE_REG 0x000000b4 860 /* sienaa0,hunta0=pci_f0_config */ 861 862 #define PCRF_BZ_MSIX_TBL_OFF_LBN 3 863 #define PCRF_BZ_MSIX_TBL_OFF_WIDTH 29 864 #define PCRF_BZ_MSIX_TBL_BIR_LBN 0 865 #define PCRF_BZ_MSIX_TBL_BIR_WIDTH 3 866 867 /* 868 * PC_DEV_CAP2_REG(32bit): 869 * PCIe Device Capabilities 2 870 */ 871 872 #define PCR_CZ_DEV_CAP2_REG 0x00000094 873 /* sienaa0=pci_f0_config,hunta0=pci_f0_config */ 874 875 #define PCRF_DZ_OBFF_SUPPORTED_LBN 18 876 #define PCRF_DZ_OBFF_SUPPORTED_WIDTH 2 877 #define PCRF_DZ_TPH_CMPL_SUPPORTED_LBN 12 878 #define PCRF_DZ_TPH_CMPL_SUPPORTED_WIDTH 2 879 #define PCRF_DZ_LTR_M_SUPPORTED_LBN 11 880 #define PCRF_DZ_LTR_M_SUPPORTED_WIDTH 1 881 #define PCRF_CC_CMPL_TIMEOUT_DIS_LBN 4 882 #define PCRF_CC_CMPL_TIMEOUT_DIS_WIDTH 1 883 #define PCRF_DZ_CMPL_TIMEOUT_DIS_SUPPORTED_LBN 4 884 #define PCRF_DZ_CMPL_TIMEOUT_DIS_SUPPORTED_WIDTH 1 885 #define PCRF_CZ_CMPL_TIMEOUT_LBN 0 886 #define PCRF_CZ_CMPL_TIMEOUT_WIDTH 4 887 #define PCFE_CZ_CMPL_TIMEOUT_17000_TO_6400MS 14 888 #define PCFE_CZ_CMPL_TIMEOUT_4000_TO_1300MS 13 889 #define PCFE_CZ_CMPL_TIMEOUT_1000_TO_3500MS 10 890 #define PCFE_CZ_CMPL_TIMEOUT_260_TO_900MS 9 891 #define PCFE_CZ_CMPL_TIMEOUT_65_TO_210MS 6 892 #define PCFE_CZ_CMPL_TIMEOUT_16_TO_55MS 5 893 #define PCFE_CZ_CMPL_TIMEOUT_1_TO_10MS 2 894 #define PCFE_CZ_CMPL_TIMEOUT_50_TO_100US 1 895 #define PCFE_CZ_CMPL_TIMEOUT_DEFAULT 0 896 897 /* 898 * PC_DEV_CTL2_REG(16bit): 899 * PCIe Device Control 2 900 */ 901 902 #define PCR_CZ_DEV_CTL2_REG 0x00000098 903 /* sienaa0,hunta0=pci_f0_config */ 904 905 #define PCRF_DZ_OBFF_ENABLE_LBN 13 906 #define PCRF_DZ_OBFF_ENABLE_WIDTH 2 907 #define PCRF_DZ_LTR_ENABLE_LBN 10 908 #define PCRF_DZ_LTR_ENABLE_WIDTH 1 909 #define PCRF_DZ_IDO_COMPLETION_ENABLE_LBN 9 910 #define PCRF_DZ_IDO_COMPLETION_ENABLE_WIDTH 1 911 #define PCRF_DZ_IDO_REQUEST_ENABLE_LBN 8 912 #define PCRF_DZ_IDO_REQUEST_ENABLE_WIDTH 1 913 #define PCRF_CZ_CMPL_TIMEOUT_DIS_CTL_LBN 4 914 #define PCRF_CZ_CMPL_TIMEOUT_DIS_CTL_WIDTH 1 915 #define PCRF_CZ_CMPL_TIMEOUT_CTL_LBN 0 916 #define PCRF_CZ_CMPL_TIMEOUT_CTL_WIDTH 4 917 918 /* 919 * PC_MSIX_PBA_BASE_REG(32bit): 920 * MSIX Capability PBA Base 921 */ 922 923 #define PCR_BB_MSIX_PBA_BASE_REG 0x00000098 924 /* falconb0=pci_f0_config */ 925 926 #define PCR_CZ_MSIX_PBA_BASE_REG 0x000000b8 927 /* sienaa0,hunta0=pci_f0_config */ 928 929 #define PCRF_BZ_MSIX_PBA_OFF_LBN 3 930 #define PCRF_BZ_MSIX_PBA_OFF_WIDTH 29 931 #define PCRF_BZ_MSIX_PBA_BIR_LBN 0 932 #define PCRF_BZ_MSIX_PBA_BIR_WIDTH 3 933 934 /* 935 * PC_LNK_CAP2_REG(32bit): 936 * PCIe Link Capability 2 937 */ 938 939 #define PCR_DZ_LNK_CAP2_REG 0x0000009c 940 /* hunta0=pci_f0_config */ 941 942 #define PCRF_DZ_LNK_SPEED_SUP_LBN 1 943 #define PCRF_DZ_LNK_SPEED_SUP_WIDTH 7 944 945 /* 946 * PC_LNK_CTL2_REG(16bit): 947 * PCIe Link Control 2 948 */ 949 950 #define PCR_CZ_LNK_CTL2_REG 0x000000a0 951 /* sienaa0,hunta0=pci_f0_config */ 952 953 #define PCRF_CZ_POLLING_DEEMPH_LVL_LBN 12 954 #define PCRF_CZ_POLLING_DEEMPH_LVL_WIDTH 1 955 #define PCRF_CZ_COMPLIANCE_SOS_CTL_LBN 11 956 #define PCRF_CZ_COMPLIANCE_SOS_CTL_WIDTH 1 957 #define PCRF_CZ_ENTER_MODIFIED_COMPLIANCE_CTL_LBN 10 958 #define PCRF_CZ_ENTER_MODIFIED_COMPLIANCE_CTL_WIDTH 1 959 #define PCRF_CZ_TRANSMIT_MARGIN_LBN 7 960 #define PCRF_CZ_TRANSMIT_MARGIN_WIDTH 3 961 #define PCRF_CZ_SELECT_DEEMPH_LBN 6 962 #define PCRF_CZ_SELECT_DEEMPH_WIDTH 1 963 #define PCRF_CZ_HW_AUTONOMOUS_SPEED_DIS_LBN 5 964 #define PCRF_CZ_HW_AUTONOMOUS_SPEED_DIS_WIDTH 1 965 #define PCRF_CZ_ENTER_COMPLIANCE_CTL_LBN 4 966 #define PCRF_CZ_ENTER_COMPLIANCE_CTL_WIDTH 1 967 #define PCRF_CZ_TGT_LNK_SPEED_CTL_LBN 0 968 #define PCRF_CZ_TGT_LNK_SPEED_CTL_WIDTH 4 969 #define PCFE_DZ_LCTL2_TGT_SPEED_GEN3 3 970 #define PCFE_DZ_LCTL2_TGT_SPEED_GEN2 2 971 #define PCFE_DZ_LCTL2_TGT_SPEED_GEN1 1 972 973 /* 974 * PC_LNK_STAT2_REG(16bit): 975 * PCIe Link Status 2 976 */ 977 978 #define PCR_CZ_LNK_STAT2_REG 0x000000a2 979 /* sienaa0,hunta0=pci_f0_config */ 980 981 #define PCRF_CZ_CURRENT_DEEMPH_LBN 0 982 #define PCRF_CZ_CURRENT_DEEMPH_WIDTH 1 983 984 /* 985 * PC_VPD_CAP_ID_REG(8bit): 986 * VPD data register 987 */ 988 989 #define PCR_AB_VPD_CAP_ID_REG 0x000000b0 990 /* falcona0,falconb0=pci_f0_config */ 991 992 #define PCRF_AB_VPD_CAP_ID_LBN 0 993 #define PCRF_AB_VPD_CAP_ID_WIDTH 8 994 995 /* 996 * PC_VPD_NXT_PTR_REG(8bit): 997 * VPD next item pointer 998 */ 999 1000 #define PCR_AB_VPD_NXT_PTR_REG 0x000000b1 1001 /* falcona0,falconb0=pci_f0_config */ 1002 1003 #define PCRF_AB_VPD_NXT_PTR_LBN 0 1004 #define PCRF_AB_VPD_NXT_PTR_WIDTH 8 1005 1006 /* 1007 * PC_VPD_ADDR_REG(16bit): 1008 * VPD address register 1009 */ 1010 1011 #define PCR_AB_VPD_ADDR_REG 0x000000b2 1012 /* falcona0,falconb0=pci_f0_config */ 1013 1014 #define PCRF_AB_VPD_FLAG_LBN 15 1015 #define PCRF_AB_VPD_FLAG_WIDTH 1 1016 #define PCRF_AB_VPD_ADDR_LBN 0 1017 #define PCRF_AB_VPD_ADDR_WIDTH 15 1018 1019 /* 1020 * PC_VPD_CAP_DATA_REG(32bit): 1021 * documentation to be written for sum_PC_VPD_CAP_DATA_REG 1022 */ 1023 1024 #define PCR_AB_VPD_CAP_DATA_REG 0x000000b4 1025 /* falcona0,falconb0=pci_f0_config */ 1026 1027 #define PCR_CZ_VPD_CAP_DATA_REG 0x000000d4 1028 /* sienaa0,hunta0=pci_f0_config */ 1029 1030 #define PCRF_AZ_VPD_DATA_LBN 0 1031 #define PCRF_AZ_VPD_DATA_WIDTH 32 1032 1033 /* 1034 * PC_VPD_CAP_CTL_REG(8bit): 1035 * VPD control and capabilities register 1036 */ 1037 1038 #define PCR_CZ_VPD_CAP_CTL_REG 0x000000d0 1039 /* sienaa0,hunta0=pci_f0_config */ 1040 1041 #define PCRF_CZ_VPD_FLAG_LBN 31 1042 #define PCRF_CZ_VPD_FLAG_WIDTH 1 1043 #define PCRF_CZ_VPD_ADDR_LBN 16 1044 #define PCRF_CZ_VPD_ADDR_WIDTH 15 1045 #define PCRF_CZ_VPD_NXT_PTR_LBN 8 1046 #define PCRF_CZ_VPD_NXT_PTR_WIDTH 8 1047 #define PCRF_CZ_VPD_CAP_ID_LBN 0 1048 #define PCRF_CZ_VPD_CAP_ID_WIDTH 8 1049 1050 /* 1051 * PC_AER_CAP_HDR_REG(32bit): 1052 * AER capability header register 1053 */ 1054 1055 #define PCR_AZ_AER_CAP_HDR_REG 0x00000100 1056 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 1057 1058 #define PCRF_AZ_AERCAPHDR_NXT_PTR_LBN 20 1059 #define PCRF_AZ_AERCAPHDR_NXT_PTR_WIDTH 12 1060 #define PCRF_AZ_AERCAPHDR_VER_LBN 16 1061 #define PCRF_AZ_AERCAPHDR_VER_WIDTH 4 1062 #define PCRF_AZ_AERCAPHDR_ID_LBN 0 1063 #define PCRF_AZ_AERCAPHDR_ID_WIDTH 16 1064 1065 /* 1066 * PC_AER_UNCORR_ERR_STAT_REG(32bit): 1067 * AER Uncorrectable error status register 1068 */ 1069 1070 #define PCR_AZ_AER_UNCORR_ERR_STAT_REG 0x00000104 1071 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 1072 1073 #define PCRF_AZ_UNSUPT_REQ_ERR_STAT_LBN 20 1074 #define PCRF_AZ_UNSUPT_REQ_ERR_STAT_WIDTH 1 1075 #define PCRF_AZ_ECRC_ERR_STAT_LBN 19 1076 #define PCRF_AZ_ECRC_ERR_STAT_WIDTH 1 1077 #define PCRF_AZ_MALF_TLP_STAT_LBN 18 1078 #define PCRF_AZ_MALF_TLP_STAT_WIDTH 1 1079 #define PCRF_AZ_RX_OVF_STAT_LBN 17 1080 #define PCRF_AZ_RX_OVF_STAT_WIDTH 1 1081 #define PCRF_AZ_UNEXP_COMP_STAT_LBN 16 1082 #define PCRF_AZ_UNEXP_COMP_STAT_WIDTH 1 1083 #define PCRF_AZ_COMP_ABRT_STAT_LBN 15 1084 #define PCRF_AZ_COMP_ABRT_STAT_WIDTH 1 1085 #define PCRF_AZ_COMP_TIMEOUT_STAT_LBN 14 1086 #define PCRF_AZ_COMP_TIMEOUT_STAT_WIDTH 1 1087 #define PCRF_AZ_FC_PROTO_ERR_STAT_LBN 13 1088 #define PCRF_AZ_FC_PROTO_ERR_STAT_WIDTH 1 1089 #define PCRF_AZ_PSON_TLP_STAT_LBN 12 1090 #define PCRF_AZ_PSON_TLP_STAT_WIDTH 1 1091 #define PCRF_AZ_DL_PROTO_ERR_STAT_LBN 4 1092 #define PCRF_AZ_DL_PROTO_ERR_STAT_WIDTH 1 1093 #define PCRF_AB_TRAIN_ERR_STAT_LBN 0 1094 #define PCRF_AB_TRAIN_ERR_STAT_WIDTH 1 1095 1096 /* 1097 * PC_AER_UNCORR_ERR_MASK_REG(32bit): 1098 * AER Uncorrectable error mask register 1099 */ 1100 1101 #define PCR_AZ_AER_UNCORR_ERR_MASK_REG 0x00000108 1102 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 1103 1104 #define PCRF_DZ_ATOMIC_OP_EGR_BLOCKED_MASK_LBN 24 1105 #define PCRF_DZ_ATOMIC_OP_EGR_BLOCKED_MASK_WIDTH 1 1106 #define PCRF_DZ_UNCORR_INT_ERR_MASK_LBN 22 1107 #define PCRF_DZ_UNCORR_INT_ERR_MASK_WIDTH 1 1108 #define PCRF_AZ_UNSUPT_REQ_ERR_MASK_LBN 20 1109 #define PCRF_AZ_UNSUPT_REQ_ERR_MASK_WIDTH 1 1110 #define PCRF_AZ_ECRC_ERR_MASK_LBN 19 1111 #define PCRF_AZ_ECRC_ERR_MASK_WIDTH 1 1112 #define PCRF_AZ_MALF_TLP_MASK_LBN 18 1113 #define PCRF_AZ_MALF_TLP_MASK_WIDTH 1 1114 #define PCRF_AZ_RX_OVF_MASK_LBN 17 1115 #define PCRF_AZ_RX_OVF_MASK_WIDTH 1 1116 #define PCRF_AZ_UNEXP_COMP_MASK_LBN 16 1117 #define PCRF_AZ_UNEXP_COMP_MASK_WIDTH 1 1118 #define PCRF_AZ_COMP_ABRT_MASK_LBN 15 1119 #define PCRF_AZ_COMP_ABRT_MASK_WIDTH 1 1120 #define PCRF_AZ_COMP_TIMEOUT_MASK_LBN 14 1121 #define PCRF_AZ_COMP_TIMEOUT_MASK_WIDTH 1 1122 #define PCRF_AZ_FC_PROTO_ERR_MASK_LBN 13 1123 #define PCRF_AZ_FC_PROTO_ERR_MASK_WIDTH 1 1124 #define PCRF_AZ_PSON_TLP_MASK_LBN 12 1125 #define PCRF_AZ_PSON_TLP_MASK_WIDTH 1 1126 #define PCRF_AZ_DL_PROTO_ERR_MASK_LBN 4 1127 #define PCRF_AZ_DL_PROTO_ERR_MASK_WIDTH 1 1128 #define PCRF_AB_TRAIN_ERR_MASK_LBN 0 1129 #define PCRF_AB_TRAIN_ERR_MASK_WIDTH 1 1130 1131 /* 1132 * PC_AER_UNCORR_ERR_SEV_REG(32bit): 1133 * AER Uncorrectable error severity register 1134 */ 1135 1136 #define PCR_AZ_AER_UNCORR_ERR_SEV_REG 0x0000010c 1137 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 1138 1139 #define PCRF_AZ_UNSUPT_REQ_ERR_SEV_LBN 20 1140 #define PCRF_AZ_UNSUPT_REQ_ERR_SEV_WIDTH 1 1141 #define PCRF_AZ_ECRC_ERR_SEV_LBN 19 1142 #define PCRF_AZ_ECRC_ERR_SEV_WIDTH 1 1143 #define PCRF_AZ_MALF_TLP_SEV_LBN 18 1144 #define PCRF_AZ_MALF_TLP_SEV_WIDTH 1 1145 #define PCRF_AZ_RX_OVF_SEV_LBN 17 1146 #define PCRF_AZ_RX_OVF_SEV_WIDTH 1 1147 #define PCRF_AZ_UNEXP_COMP_SEV_LBN 16 1148 #define PCRF_AZ_UNEXP_COMP_SEV_WIDTH 1 1149 #define PCRF_AZ_COMP_ABRT_SEV_LBN 15 1150 #define PCRF_AZ_COMP_ABRT_SEV_WIDTH 1 1151 #define PCRF_AZ_COMP_TIMEOUT_SEV_LBN 14 1152 #define PCRF_AZ_COMP_TIMEOUT_SEV_WIDTH 1 1153 #define PCRF_AZ_FC_PROTO_ERR_SEV_LBN 13 1154 #define PCRF_AZ_FC_PROTO_ERR_SEV_WIDTH 1 1155 #define PCRF_AZ_PSON_TLP_SEV_LBN 12 1156 #define PCRF_AZ_PSON_TLP_SEV_WIDTH 1 1157 #define PCRF_AZ_DL_PROTO_ERR_SEV_LBN 4 1158 #define PCRF_AZ_DL_PROTO_ERR_SEV_WIDTH 1 1159 #define PCRF_AB_TRAIN_ERR_SEV_LBN 0 1160 #define PCRF_AB_TRAIN_ERR_SEV_WIDTH 1 1161 1162 /* 1163 * PC_AER_CORR_ERR_STAT_REG(32bit): 1164 * AER Correctable error status register 1165 */ 1166 1167 #define PCR_AZ_AER_CORR_ERR_STAT_REG 0x00000110 1168 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 1169 1170 #define PCRF_CZ_ADVSY_NON_FATAL_STAT_LBN 13 1171 #define PCRF_CZ_ADVSY_NON_FATAL_STAT_WIDTH 1 1172 #define PCRF_AZ_RPLY_TMR_TOUT_STAT_LBN 12 1173 #define PCRF_AZ_RPLY_TMR_TOUT_STAT_WIDTH 1 1174 #define PCRF_AZ_RPLAY_NUM_RO_STAT_LBN 8 1175 #define PCRF_AZ_RPLAY_NUM_RO_STAT_WIDTH 1 1176 #define PCRF_AZ_BAD_DLLP_STAT_LBN 7 1177 #define PCRF_AZ_BAD_DLLP_STAT_WIDTH 1 1178 #define PCRF_AZ_BAD_TLP_STAT_LBN 6 1179 #define PCRF_AZ_BAD_TLP_STAT_WIDTH 1 1180 #define PCRF_AZ_RX_ERR_STAT_LBN 0 1181 #define PCRF_AZ_RX_ERR_STAT_WIDTH 1 1182 1183 /* 1184 * PC_AER_CORR_ERR_MASK_REG(32bit): 1185 * AER Correctable error status register 1186 */ 1187 1188 #define PCR_AZ_AER_CORR_ERR_MASK_REG 0x00000114 1189 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 1190 1191 #define PCRF_CZ_ADVSY_NON_FATAL_MASK_LBN 13 1192 #define PCRF_CZ_ADVSY_NON_FATAL_MASK_WIDTH 1 1193 #define PCRF_AZ_RPLY_TMR_TOUT_MASK_LBN 12 1194 #define PCRF_AZ_RPLY_TMR_TOUT_MASK_WIDTH 1 1195 #define PCRF_AZ_RPLAY_NUM_RO_MASK_LBN 8 1196 #define PCRF_AZ_RPLAY_NUM_RO_MASK_WIDTH 1 1197 #define PCRF_AZ_BAD_DLLP_MASK_LBN 7 1198 #define PCRF_AZ_BAD_DLLP_MASK_WIDTH 1 1199 #define PCRF_AZ_BAD_TLP_MASK_LBN 6 1200 #define PCRF_AZ_BAD_TLP_MASK_WIDTH 1 1201 #define PCRF_AZ_RX_ERR_MASK_LBN 0 1202 #define PCRF_AZ_RX_ERR_MASK_WIDTH 1 1203 1204 /* 1205 * PC_AER_CAP_CTL_REG(32bit): 1206 * AER capability and control register 1207 */ 1208 1209 #define PCR_AZ_AER_CAP_CTL_REG 0x00000118 1210 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 1211 1212 #define PCRF_AZ_ECRC_CHK_EN_LBN 8 1213 #define PCRF_AZ_ECRC_CHK_EN_WIDTH 1 1214 #define PCRF_AZ_ECRC_CHK_CAP_LBN 7 1215 #define PCRF_AZ_ECRC_CHK_CAP_WIDTH 1 1216 #define PCRF_AZ_ECRC_GEN_EN_LBN 6 1217 #define PCRF_AZ_ECRC_GEN_EN_WIDTH 1 1218 #define PCRF_AZ_ECRC_GEN_CAP_LBN 5 1219 #define PCRF_AZ_ECRC_GEN_CAP_WIDTH 1 1220 #define PCRF_AZ_1ST_ERR_PTR_LBN 0 1221 #define PCRF_AZ_1ST_ERR_PTR_WIDTH 5 1222 1223 /* 1224 * PC_AER_HDR_LOG_REG(128bit): 1225 * AER Header log register 1226 */ 1227 1228 #define PCR_AZ_AER_HDR_LOG_REG 0x0000011c 1229 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 1230 1231 #define PCRF_AZ_HDR_LOG_LBN 0 1232 #define PCRF_AZ_HDR_LOG_WIDTH 128 1233 1234 /* 1235 * PC_DEVSN_CAP_HDR_REG(32bit): 1236 * Device serial number capability header register 1237 */ 1238 1239 #define PCR_CZ_DEVSN_CAP_HDR_REG 0x00000140 1240 /* sienaa0,hunta0=pci_f0_config */ 1241 1242 #define PCRF_CZ_DEVSNCAPHDR_NXT_PTR_LBN 20 1243 #define PCRF_CZ_DEVSNCAPHDR_NXT_PTR_WIDTH 12 1244 #define PCRF_CZ_DEVSNCAPHDR_VER_LBN 16 1245 #define PCRF_CZ_DEVSNCAPHDR_VER_WIDTH 4 1246 #define PCRF_CZ_DEVSNCAPHDR_ID_LBN 0 1247 #define PCRF_CZ_DEVSNCAPHDR_ID_WIDTH 16 1248 1249 /* 1250 * PC_DEVSN_DWORD0_REG(32bit): 1251 * Device serial number DWORD0 1252 */ 1253 1254 #define PCR_CZ_DEVSN_DWORD0_REG 0x00000144 1255 /* sienaa0,hunta0=pci_f0_config */ 1256 1257 #define PCRF_CZ_DEVSN_DWORD0_LBN 0 1258 #define PCRF_CZ_DEVSN_DWORD0_WIDTH 32 1259 1260 /* 1261 * PC_DEVSN_DWORD1_REG(32bit): 1262 * Device serial number DWORD0 1263 */ 1264 1265 #define PCR_CZ_DEVSN_DWORD1_REG 0x00000148 1266 /* sienaa0,hunta0=pci_f0_config */ 1267 1268 #define PCRF_CZ_DEVSN_DWORD1_LBN 0 1269 #define PCRF_CZ_DEVSN_DWORD1_WIDTH 32 1270 1271 /* 1272 * PC_ARI_CAP_HDR_REG(32bit): 1273 * ARI capability header register 1274 */ 1275 1276 #define PCR_CZ_ARI_CAP_HDR_REG 0x00000150 1277 /* sienaa0,hunta0=pci_f0_config */ 1278 1279 #define PCRF_CZ_ARICAPHDR_NXT_PTR_LBN 20 1280 #define PCRF_CZ_ARICAPHDR_NXT_PTR_WIDTH 12 1281 #define PCRF_CZ_ARICAPHDR_VER_LBN 16 1282 #define PCRF_CZ_ARICAPHDR_VER_WIDTH 4 1283 #define PCRF_CZ_ARICAPHDR_ID_LBN 0 1284 #define PCRF_CZ_ARICAPHDR_ID_WIDTH 16 1285 1286 /* 1287 * PC_ARI_CAP_REG(16bit): 1288 * ARI Capabilities 1289 */ 1290 1291 #define PCR_CZ_ARI_CAP_REG 0x00000154 1292 /* sienaa0,hunta0=pci_f0_config */ 1293 1294 #define PCRF_CZ_ARI_NXT_FN_NUM_LBN 8 1295 #define PCRF_CZ_ARI_NXT_FN_NUM_WIDTH 8 1296 #define PCRF_CZ_ARI_ACS_FNGRP_CAP_LBN 1 1297 #define PCRF_CZ_ARI_ACS_FNGRP_CAP_WIDTH 1 1298 #define PCRF_CZ_ARI_MFVC_FNGRP_CAP_LBN 0 1299 #define PCRF_CZ_ARI_MFVC_FNGRP_CAP_WIDTH 1 1300 1301 /* 1302 * PC_ARI_CTL_REG(16bit): 1303 * ARI Control 1304 */ 1305 1306 #define PCR_CZ_ARI_CTL_REG 0x00000156 1307 /* sienaa0,hunta0=pci_f0_config */ 1308 1309 #define PCRF_CZ_ARI_FN_GRP_LBN 4 1310 #define PCRF_CZ_ARI_FN_GRP_WIDTH 3 1311 #define PCRF_CZ_ARI_ACS_FNGRP_EN_LBN 1 1312 #define PCRF_CZ_ARI_ACS_FNGRP_EN_WIDTH 1 1313 #define PCRF_CZ_ARI_MFVC_FNGRP_EN_LBN 0 1314 #define PCRF_CZ_ARI_MFVC_FNGRP_EN_WIDTH 1 1315 1316 /* 1317 * PC_SEC_PCIE_CAP_REG(32bit): 1318 * Secondary PCIE Capability Register 1319 */ 1320 1321 #define PCR_DZ_SEC_PCIE_CAP_REG 0x00000160 1322 /* hunta0=pci_f0_config */ 1323 1324 #define PCRF_DZ_SEC_NXT_PTR_LBN 20 1325 #define PCRF_DZ_SEC_NXT_PTR_WIDTH 12 1326 #define PCRF_DZ_SEC_VERSION_LBN 16 1327 #define PCRF_DZ_SEC_VERSION_WIDTH 4 1328 #define PCRF_DZ_SEC_EXT_CAP_ID_LBN 0 1329 #define PCRF_DZ_SEC_EXT_CAP_ID_WIDTH 16 1330 1331 /* 1332 * PC_SRIOV_CAP_HDR_REG(32bit): 1333 * SRIOV capability header register 1334 */ 1335 1336 #define PCR_CC_SRIOV_CAP_HDR_REG 0x00000160 1337 /* sienaa0=pci_f0_config */ 1338 1339 #define PCR_DZ_SRIOV_CAP_HDR_REG 0x00000180 1340 /* hunta0=pci_f0_config */ 1341 1342 #define PCRF_CZ_SRIOVCAPHDR_NXT_PTR_LBN 20 1343 #define PCRF_CZ_SRIOVCAPHDR_NXT_PTR_WIDTH 12 1344 #define PCRF_CZ_SRIOVCAPHDR_VER_LBN 16 1345 #define PCRF_CZ_SRIOVCAPHDR_VER_WIDTH 4 1346 #define PCRF_CZ_SRIOVCAPHDR_ID_LBN 0 1347 #define PCRF_CZ_SRIOVCAPHDR_ID_WIDTH 16 1348 1349 /* 1350 * PC_SRIOV_CAP_REG(32bit): 1351 * SRIOV Capabilities 1352 */ 1353 1354 #define PCR_CC_SRIOV_CAP_REG 0x00000164 1355 /* sienaa0=pci_f0_config */ 1356 1357 #define PCR_DZ_SRIOV_CAP_REG 0x00000184 1358 /* hunta0=pci_f0_config */ 1359 1360 #define PCRF_CZ_VF_MIGR_INT_MSG_NUM_LBN 21 1361 #define PCRF_CZ_VF_MIGR_INT_MSG_NUM_WIDTH 11 1362 #define PCRF_DZ_VF_ARI_CAP_PRESV_LBN 1 1363 #define PCRF_DZ_VF_ARI_CAP_PRESV_WIDTH 1 1364 #define PCRF_CZ_VF_MIGR_CAP_LBN 0 1365 #define PCRF_CZ_VF_MIGR_CAP_WIDTH 1 1366 1367 /* 1368 * PC_LINK_CONTROL3_REG(32bit): 1369 * Link Control 3. 1370 */ 1371 1372 #define PCR_DZ_LINK_CONTROL3_REG 0x00000164 1373 /* hunta0=pci_f0_config */ 1374 1375 #define PCRF_DZ_LINK_EQ_INT_EN_LBN 1 1376 #define PCRF_DZ_LINK_EQ_INT_EN_WIDTH 1 1377 #define PCRF_DZ_PERFORM_EQL_LBN 0 1378 #define PCRF_DZ_PERFORM_EQL_WIDTH 1 1379 1380 /* 1381 * PC_LANE_ERROR_STAT_REG(32bit): 1382 * Lane Error Status Register. 1383 */ 1384 1385 #define PCR_DZ_LANE_ERROR_STAT_REG 0x00000168 1386 /* hunta0=pci_f0_config */ 1387 1388 #define PCRF_DZ_LANE_STATUS_LBN 0 1389 #define PCRF_DZ_LANE_STATUS_WIDTH 8 1390 1391 /* 1392 * PC_SRIOV_CTL_REG(16bit): 1393 * SRIOV Control 1394 */ 1395 1396 #define PCR_CC_SRIOV_CTL_REG 0x00000168 1397 /* sienaa0=pci_f0_config */ 1398 1399 #define PCR_DZ_SRIOV_CTL_REG 0x00000188 1400 /* hunta0=pci_f0_config */ 1401 1402 #define PCRF_CZ_VF_ARI_CAP_HRCHY_LBN 4 1403 #define PCRF_CZ_VF_ARI_CAP_HRCHY_WIDTH 1 1404 #define PCRF_CZ_VF_MSE_LBN 3 1405 #define PCRF_CZ_VF_MSE_WIDTH 1 1406 #define PCRF_CZ_VF_MIGR_INT_EN_LBN 2 1407 #define PCRF_CZ_VF_MIGR_INT_EN_WIDTH 1 1408 #define PCRF_CZ_VF_MIGR_EN_LBN 1 1409 #define PCRF_CZ_VF_MIGR_EN_WIDTH 1 1410 #define PCRF_CZ_VF_EN_LBN 0 1411 #define PCRF_CZ_VF_EN_WIDTH 1 1412 1413 /* 1414 * PC_SRIOV_STAT_REG(16bit): 1415 * SRIOV Status 1416 */ 1417 1418 #define PCR_CC_SRIOV_STAT_REG 0x0000016a 1419 /* sienaa0=pci_f0_config */ 1420 1421 #define PCR_DZ_SRIOV_STAT_REG 0x0000018a 1422 /* hunta0=pci_f0_config */ 1423 1424 #define PCRF_CZ_VF_MIGR_STAT_LBN 0 1425 #define PCRF_CZ_VF_MIGR_STAT_WIDTH 1 1426 1427 /* 1428 * PC_LANE01_EQU_CONTROL_REG(32bit): 1429 * Lanes 0,1 Equalization Control Register. 1430 */ 1431 1432 #define PCR_DZ_LANE01_EQU_CONTROL_REG 0x0000016c 1433 /* hunta0=pci_f0_config */ 1434 1435 #define PCRF_DZ_LANE1_EQ_CTRL_LBN 16 1436 #define PCRF_DZ_LANE1_EQ_CTRL_WIDTH 16 1437 #define PCRF_DZ_LANE0_EQ_CTRL_LBN 0 1438 #define PCRF_DZ_LANE0_EQ_CTRL_WIDTH 16 1439 1440 /* 1441 * PC_SRIOV_INITIALVFS_REG(16bit): 1442 * SRIOV Initial VFs 1443 */ 1444 1445 #define PCR_CC_SRIOV_INITIALVFS_REG 0x0000016c 1446 /* sienaa0=pci_f0_config */ 1447 1448 #define PCR_DZ_SRIOV_INITIALVFS_REG 0x0000018c 1449 /* hunta0=pci_f0_config */ 1450 1451 #define PCRF_CZ_VF_INITIALVFS_LBN 0 1452 #define PCRF_CZ_VF_INITIALVFS_WIDTH 16 1453 1454 /* 1455 * PC_SRIOV_TOTALVFS_REG(10bit): 1456 * SRIOV Total VFs 1457 */ 1458 1459 #define PCR_CC_SRIOV_TOTALVFS_REG 0x0000016e 1460 /* sienaa0=pci_f0_config */ 1461 1462 #define PCR_DZ_SRIOV_TOTALVFS_REG 0x0000018e 1463 /* hunta0=pci_f0_config */ 1464 1465 #define PCRF_CZ_VF_TOTALVFS_LBN 0 1466 #define PCRF_CZ_VF_TOTALVFS_WIDTH 16 1467 1468 /* 1469 * PC_SRIOV_NUMVFS_REG(16bit): 1470 * SRIOV Number of VFs 1471 */ 1472 1473 #define PCR_CC_SRIOV_NUMVFS_REG 0x00000170 1474 /* sienaa0=pci_f0_config */ 1475 1476 #define PCR_DZ_SRIOV_NUMVFS_REG 0x00000190 1477 /* hunta0=pci_f0_config */ 1478 1479 #define PCRF_CZ_VF_NUMVFS_LBN 0 1480 #define PCRF_CZ_VF_NUMVFS_WIDTH 16 1481 1482 /* 1483 * PC_LANE23_EQU_CONTROL_REG(32bit): 1484 * Lanes 2,3 Equalization Control Register. 1485 */ 1486 1487 #define PCR_DZ_LANE23_EQU_CONTROL_REG 0x00000170 1488 /* hunta0=pci_f0_config */ 1489 1490 #define PCRF_DZ_LANE3_EQ_CTRL_LBN 16 1491 #define PCRF_DZ_LANE3_EQ_CTRL_WIDTH 16 1492 #define PCRF_DZ_LANE2_EQ_CTRL_LBN 0 1493 #define PCRF_DZ_LANE2_EQ_CTRL_WIDTH 16 1494 1495 /* 1496 * PC_SRIOV_FN_DPND_LNK_REG(16bit): 1497 * SRIOV Function dependency link 1498 */ 1499 1500 #define PCR_CC_SRIOV_FN_DPND_LNK_REG 0x00000172 1501 /* sienaa0=pci_f0_config */ 1502 1503 #define PCR_DZ_SRIOV_FN_DPND_LNK_REG 0x00000192 1504 /* hunta0=pci_f0_config */ 1505 1506 #define PCRF_CZ_SRIOV_FN_DPND_LNK_LBN 0 1507 #define PCRF_CZ_SRIOV_FN_DPND_LNK_WIDTH 8 1508 1509 /* 1510 * PC_SRIOV_1STVF_OFFSET_REG(16bit): 1511 * SRIOV First VF Offset 1512 */ 1513 1514 #define PCR_CC_SRIOV_1STVF_OFFSET_REG 0x00000174 1515 /* sienaa0=pci_f0_config */ 1516 1517 #define PCR_DZ_SRIOV_1STVF_OFFSET_REG 0x00000194 1518 /* hunta0=pci_f0_config */ 1519 1520 #define PCRF_CZ_VF_1STVF_OFFSET_LBN 0 1521 #define PCRF_CZ_VF_1STVF_OFFSET_WIDTH 16 1522 1523 /* 1524 * PC_LANE45_EQU_CONTROL_REG(32bit): 1525 * Lanes 4,5 Equalization Control Register. 1526 */ 1527 1528 #define PCR_DZ_LANE45_EQU_CONTROL_REG 0x00000174 1529 /* hunta0=pci_f0_config */ 1530 1531 #define PCRF_DZ_LANE5_EQ_CTRL_LBN 16 1532 #define PCRF_DZ_LANE5_EQ_CTRL_WIDTH 16 1533 #define PCRF_DZ_LANE4_EQ_CTRL_LBN 0 1534 #define PCRF_DZ_LANE4_EQ_CTRL_WIDTH 16 1535 1536 /* 1537 * PC_SRIOV_VFSTRIDE_REG(16bit): 1538 * SRIOV VF Stride 1539 */ 1540 1541 #define PCR_CC_SRIOV_VFSTRIDE_REG 0x00000176 1542 /* sienaa0=pci_f0_config */ 1543 1544 #define PCR_DZ_SRIOV_VFSTRIDE_REG 0x00000196 1545 /* hunta0=pci_f0_config */ 1546 1547 #define PCRF_CZ_VF_VFSTRIDE_LBN 0 1548 #define PCRF_CZ_VF_VFSTRIDE_WIDTH 16 1549 1550 /* 1551 * PC_LANE67_EQU_CONTROL_REG(32bit): 1552 * Lanes 6,7 Equalization Control Register. 1553 */ 1554 1555 #define PCR_DZ_LANE67_EQU_CONTROL_REG 0x00000178 1556 /* hunta0=pci_f0_config */ 1557 1558 #define PCRF_DZ_LANE7_EQ_CTRL_LBN 16 1559 #define PCRF_DZ_LANE7_EQ_CTRL_WIDTH 16 1560 #define PCRF_DZ_LANE6_EQ_CTRL_LBN 0 1561 #define PCRF_DZ_LANE6_EQ_CTRL_WIDTH 16 1562 1563 /* 1564 * PC_SRIOV_DEVID_REG(16bit): 1565 * SRIOV VF Device ID 1566 */ 1567 1568 #define PCR_CC_SRIOV_DEVID_REG 0x0000017a 1569 /* sienaa0=pci_f0_config */ 1570 1571 #define PCR_DZ_SRIOV_DEVID_REG 0x0000019a 1572 /* hunta0=pci_f0_config */ 1573 1574 #define PCRF_CZ_VF_DEVID_LBN 0 1575 #define PCRF_CZ_VF_DEVID_WIDTH 16 1576 1577 /* 1578 * PC_SRIOV_SUP_PAGESZ_REG(16bit): 1579 * SRIOV Supported Page Sizes 1580 */ 1581 1582 #define PCR_CC_SRIOV_SUP_PAGESZ_REG 0x0000017c 1583 /* sienaa0=pci_f0_config */ 1584 1585 #define PCR_DZ_SRIOV_SUP_PAGESZ_REG 0x0000019c 1586 /* hunta0=pci_f0_config */ 1587 1588 #define PCRF_CZ_VF_SUP_PAGESZ_LBN 0 1589 #define PCRF_CZ_VF_SUP_PAGESZ_WIDTH 16 1590 1591 /* 1592 * PC_SRIOV_SYS_PAGESZ_REG(32bit): 1593 * SRIOV System Page Size 1594 */ 1595 1596 #define PCR_CC_SRIOV_SYS_PAGESZ_REG 0x00000180 1597 /* sienaa0=pci_f0_config */ 1598 1599 #define PCR_DZ_SRIOV_SYS_PAGESZ_REG 0x000001a0 1600 /* hunta0=pci_f0_config */ 1601 1602 #define PCRF_CZ_VF_SYS_PAGESZ_LBN 0 1603 #define PCRF_CZ_VF_SYS_PAGESZ_WIDTH 16 1604 1605 /* 1606 * PC_SRIOV_BAR0_REG(32bit): 1607 * SRIOV VF Bar0 1608 */ 1609 1610 #define PCR_CC_SRIOV_BAR0_REG 0x00000184 1611 /* sienaa0=pci_f0_config */ 1612 1613 #define PCR_DZ_SRIOV_BAR0_REG 0x000001a4 1614 /* hunta0=pci_f0_config */ 1615 1616 #define PCRF_CC_VF_BAR_ADDRESS_LBN 0 1617 #define PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 1618 #define PCRF_DZ_VF_BAR0_ADDRESS_LBN 4 1619 #define PCRF_DZ_VF_BAR0_ADDRESS_WIDTH 28 1620 #define PCRF_DZ_VF_BAR0_PREF_LBN 3 1621 #define PCRF_DZ_VF_BAR0_PREF_WIDTH 1 1622 #define PCRF_DZ_VF_BAR0_TYPE_LBN 1 1623 #define PCRF_DZ_VF_BAR0_TYPE_WIDTH 2 1624 #define PCRF_DZ_VF_BAR0_IOM_LBN 0 1625 #define PCRF_DZ_VF_BAR0_IOM_WIDTH 1 1626 1627 /* 1628 * PC_SRIOV_BAR1_REG(32bit): 1629 * SRIOV Bar1 1630 */ 1631 1632 #define PCR_CC_SRIOV_BAR1_REG 0x00000188 1633 /* sienaa0=pci_f0_config */ 1634 1635 #define PCR_DZ_SRIOV_BAR1_REG 0x000001a8 1636 /* hunta0=pci_f0_config */ 1637 1638 /* defined as PCRF_CC_VF_BAR_ADDRESS_LBN 0; */ 1639 /* defined as PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 */ 1640 #define PCRF_DZ_VF_BAR1_ADDRESS_LBN 0 1641 #define PCRF_DZ_VF_BAR1_ADDRESS_WIDTH 32 1642 1643 /* 1644 * PC_SRIOV_BAR2_REG(32bit): 1645 * SRIOV Bar2 1646 */ 1647 1648 #define PCR_CC_SRIOV_BAR2_REG 0x0000018c 1649 /* sienaa0=pci_f0_config */ 1650 1651 #define PCR_DZ_SRIOV_BAR2_REG 0x000001ac 1652 /* hunta0=pci_f0_config */ 1653 1654 /* defined as PCRF_CC_VF_BAR_ADDRESS_LBN 0; */ 1655 /* defined as PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 */ 1656 #define PCRF_DZ_VF_BAR2_ADDRESS_LBN 4 1657 #define PCRF_DZ_VF_BAR2_ADDRESS_WIDTH 28 1658 #define PCRF_DZ_VF_BAR2_PREF_LBN 3 1659 #define PCRF_DZ_VF_BAR2_PREF_WIDTH 1 1660 #define PCRF_DZ_VF_BAR2_TYPE_LBN 1 1661 #define PCRF_DZ_VF_BAR2_TYPE_WIDTH 2 1662 #define PCRF_DZ_VF_BAR2_IOM_LBN 0 1663 #define PCRF_DZ_VF_BAR2_IOM_WIDTH 1 1664 1665 /* 1666 * PC_SRIOV_BAR3_REG(32bit): 1667 * SRIOV Bar3 1668 */ 1669 1670 #define PCR_CC_SRIOV_BAR3_REG 0x00000190 1671 /* sienaa0=pci_f0_config */ 1672 1673 #define PCR_DZ_SRIOV_BAR3_REG 0x000001b0 1674 /* hunta0=pci_f0_config */ 1675 1676 /* defined as PCRF_CC_VF_BAR_ADDRESS_LBN 0; */ 1677 /* defined as PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 */ 1678 #define PCRF_DZ_VF_BAR3_ADDRESS_LBN 0 1679 #define PCRF_DZ_VF_BAR3_ADDRESS_WIDTH 32 1680 1681 /* 1682 * PC_SRIOV_BAR4_REG(32bit): 1683 * SRIOV Bar4 1684 */ 1685 1686 #define PCR_CC_SRIOV_BAR4_REG 0x00000194 1687 /* sienaa0=pci_f0_config */ 1688 1689 #define PCR_DZ_SRIOV_BAR4_REG 0x000001b4 1690 /* hunta0=pci_f0_config */ 1691 1692 /* defined as PCRF_CC_VF_BAR_ADDRESS_LBN 0; */ 1693 /* defined as PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 */ 1694 #define PCRF_DZ_VF_BAR4_ADDRESS_LBN 0 1695 #define PCRF_DZ_VF_BAR4_ADDRESS_WIDTH 32 1696 1697 /* 1698 * PC_SRIOV_BAR5_REG(32bit): 1699 * SRIOV Bar5 1700 */ 1701 1702 #define PCR_CC_SRIOV_BAR5_REG 0x00000198 1703 /* sienaa0=pci_f0_config */ 1704 1705 #define PCR_DZ_SRIOV_BAR5_REG 0x000001b8 1706 /* hunta0=pci_f0_config */ 1707 1708 /* defined as PCRF_CC_VF_BAR_ADDRESS_LBN 0; */ 1709 /* defined as PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 */ 1710 #define PCRF_DZ_VF_BAR5_ADDRESS_LBN 0 1711 #define PCRF_DZ_VF_BAR5_ADDRESS_WIDTH 32 1712 1713 /* 1714 * PC_SRIOV_RSVD_REG(16bit): 1715 * Reserved register 1716 */ 1717 1718 #define PCR_DZ_SRIOV_RSVD_REG 0x00000198 1719 /* hunta0=pci_f0_config */ 1720 1721 #define PCRF_DZ_VF_RSVD_LBN 0 1722 #define PCRF_DZ_VF_RSVD_WIDTH 16 1723 1724 /* 1725 * PC_SRIOV_MIBR_SARRAY_OFFSET_REG(32bit): 1726 * SRIOV VF Migration State Array Offset 1727 */ 1728 1729 #define PCR_CC_SRIOV_MIBR_SARRAY_OFFSET_REG 0x0000019c 1730 /* sienaa0=pci_f0_config */ 1731 1732 #define PCR_DZ_SRIOV_MIBR_SARRAY_OFFSET_REG 0x000001bc 1733 /* hunta0=pci_f0_config */ 1734 1735 #define PCRF_CZ_VF_MIGR_OFFSET_LBN 3 1736 #define PCRF_CZ_VF_MIGR_OFFSET_WIDTH 29 1737 #define PCRF_CZ_VF_MIGR_BIR_LBN 0 1738 #define PCRF_CZ_VF_MIGR_BIR_WIDTH 3 1739 1740 /* 1741 * PC_TPH_CAP_HDR_REG(32bit): 1742 * TPH Capability Header Register 1743 */ 1744 1745 #define PCR_DZ_TPH_CAP_HDR_REG 0x000001c0 1746 /* hunta0=pci_f0_config */ 1747 1748 #define PCRF_DZ_TPH_NXT_PTR_LBN 20 1749 #define PCRF_DZ_TPH_NXT_PTR_WIDTH 12 1750 #define PCRF_DZ_TPH_VERSION_LBN 16 1751 #define PCRF_DZ_TPH_VERSION_WIDTH 4 1752 #define PCRF_DZ_TPH_EXT_CAP_ID_LBN 0 1753 #define PCRF_DZ_TPH_EXT_CAP_ID_WIDTH 16 1754 1755 /* 1756 * PC_TPH_REQ_CAP_REG(32bit): 1757 * TPH Requester Capability Register 1758 */ 1759 1760 #define PCR_DZ_TPH_REQ_CAP_REG 0x000001c4 1761 /* hunta0=pci_f0_config */ 1762 1763 #define PCRF_DZ_ST_TBLE_SIZE_LBN 16 1764 #define PCRF_DZ_ST_TBLE_SIZE_WIDTH 11 1765 #define PCRF_DZ_ST_TBLE_LOC_LBN 9 1766 #define PCRF_DZ_ST_TBLE_LOC_WIDTH 2 1767 #define PCRF_DZ_EXT_TPH_MODE_SUP_LBN 8 1768 #define PCRF_DZ_EXT_TPH_MODE_SUP_WIDTH 1 1769 #define PCRF_DZ_TPH_DEV_MODE_SUP_LBN 2 1770 #define PCRF_DZ_TPH_DEV_MODE_SUP_WIDTH 1 1771 #define PCRF_DZ_TPH_INT_MODE_SUP_LBN 1 1772 #define PCRF_DZ_TPH_INT_MODE_SUP_WIDTH 1 1773 #define PCRF_DZ_TPH_NOST_MODE_SUP_LBN 0 1774 #define PCRF_DZ_TPH_NOST_MODE_SUP_WIDTH 1 1775 1776 /* 1777 * PC_TPH_REQ_CTL_REG(32bit): 1778 * TPH Requester Control Register 1779 */ 1780 1781 #define PCR_DZ_TPH_REQ_CTL_REG 0x000001c8 1782 /* hunta0=pci_f0_config */ 1783 1784 #define PCRF_DZ_TPH_REQ_ENABLE_LBN 8 1785 #define PCRF_DZ_TPH_REQ_ENABLE_WIDTH 2 1786 #define PCRF_DZ_TPH_ST_MODE_LBN 0 1787 #define PCRF_DZ_TPH_ST_MODE_WIDTH 3 1788 1789 /* 1790 * PC_LTR_CAP_HDR_REG(32bit): 1791 * Latency Tolerance Reporting Cap Header Reg 1792 */ 1793 1794 #define PCR_DZ_LTR_CAP_HDR_REG 0x00000290 1795 /* hunta0=pci_f0_config */ 1796 1797 #define PCRF_DZ_LTR_NXT_PTR_LBN 20 1798 #define PCRF_DZ_LTR_NXT_PTR_WIDTH 12 1799 #define PCRF_DZ_LTR_VERSION_LBN 16 1800 #define PCRF_DZ_LTR_VERSION_WIDTH 4 1801 #define PCRF_DZ_LTR_EXT_CAP_ID_LBN 0 1802 #define PCRF_DZ_LTR_EXT_CAP_ID_WIDTH 16 1803 1804 /* 1805 * PC_LTR_MAX_SNOOP_REG(32bit): 1806 * LTR Maximum Snoop/No Snoop Register 1807 */ 1808 1809 #define PCR_DZ_LTR_MAX_SNOOP_REG 0x00000294 1810 /* hunta0=pci_f0_config */ 1811 1812 #define PCRF_DZ_LTR_MAX_NOSNOOP_SCALE_LBN 26 1813 #define PCRF_DZ_LTR_MAX_NOSNOOP_SCALE_WIDTH 3 1814 #define PCRF_DZ_LTR_MAX_NOSNOOP_LAT_LBN 16 1815 #define PCRF_DZ_LTR_MAX_NOSNOOP_LAT_WIDTH 10 1816 #define PCRF_DZ_LTR_MAX_SNOOP_SCALE_LBN 10 1817 #define PCRF_DZ_LTR_MAX_SNOOP_SCALE_WIDTH 3 1818 #define PCRF_DZ_LTR_MAX_SNOOP_LAT_LBN 0 1819 #define PCRF_DZ_LTR_MAX_SNOOP_LAT_WIDTH 10 1820 1821 /* 1822 * PC_ACK_LAT_TMR_REG(32bit): 1823 * ACK latency timer & replay timer register 1824 */ 1825 1826 #define PCR_AC_ACK_LAT_TMR_REG 0x00000700 1827 /* falcona0,falconb0,sienaa0=pci_f0_config */ 1828 1829 #define PCRF_AC_RT_LBN 16 1830 #define PCRF_AC_RT_WIDTH 16 1831 #define PCRF_AC_ALT_LBN 0 1832 #define PCRF_AC_ALT_WIDTH 16 1833 1834 /* 1835 * PC_OTHER_MSG_REG(32bit): 1836 * Other message register 1837 */ 1838 1839 #define PCR_AC_OTHER_MSG_REG 0x00000704 1840 /* falcona0,falconb0,sienaa0=pci_f0_config */ 1841 1842 #define PCRF_AC_OM_CRPT3_LBN 24 1843 #define PCRF_AC_OM_CRPT3_WIDTH 8 1844 #define PCRF_AC_OM_CRPT2_LBN 16 1845 #define PCRF_AC_OM_CRPT2_WIDTH 8 1846 #define PCRF_AC_OM_CRPT1_LBN 8 1847 #define PCRF_AC_OM_CRPT1_WIDTH 8 1848 #define PCRF_AC_OM_CRPT0_LBN 0 1849 #define PCRF_AC_OM_CRPT0_WIDTH 8 1850 1851 /* 1852 * PC_FORCE_LNK_REG(24bit): 1853 * Port force link register 1854 */ 1855 1856 #define PCR_AC_FORCE_LNK_REG 0x00000708 1857 /* falcona0,falconb0,sienaa0=pci_f0_config */ 1858 1859 #define PCRF_AC_LFS_LBN 16 1860 #define PCRF_AC_LFS_WIDTH 6 1861 #define PCRF_AC_FL_LBN 15 1862 #define PCRF_AC_FL_WIDTH 1 1863 #define PCRF_AC_LN_LBN 0 1864 #define PCRF_AC_LN_WIDTH 8 1865 1866 /* 1867 * PC_ACK_FREQ_REG(32bit): 1868 * ACK frequency register 1869 */ 1870 1871 #define PCR_AC_ACK_FREQ_REG 0x0000070c 1872 /* falcona0,falconb0,sienaa0=pci_f0_config */ 1873 1874 #define PCRF_CC_ALLOW_L1_WITHOUT_L0S_LBN 30 1875 #define PCRF_CC_ALLOW_L1_WITHOUT_L0S_WIDTH 1 1876 #define PCRF_AC_L1_ENTR_LAT_LBN 27 1877 #define PCRF_AC_L1_ENTR_LAT_WIDTH 3 1878 #define PCRF_AC_L0_ENTR_LAT_LBN 24 1879 #define PCRF_AC_L0_ENTR_LAT_WIDTH 3 1880 #define PCRF_CC_COMM_NFTS_LBN 16 1881 #define PCRF_CC_COMM_NFTS_WIDTH 8 1882 #define PCRF_AB_ACK_FREQ_REG_RSVD0_LBN 16 1883 #define PCRF_AB_ACK_FREQ_REG_RSVD0_WIDTH 3 1884 #define PCRF_AC_MAX_FTS_LBN 8 1885 #define PCRF_AC_MAX_FTS_WIDTH 8 1886 #define PCRF_AC_ACK_FREQ_LBN 0 1887 #define PCRF_AC_ACK_FREQ_WIDTH 8 1888 1889 /* 1890 * PC_PORT_LNK_CTL_REG(32bit): 1891 * Port link control register 1892 */ 1893 1894 #define PCR_AC_PORT_LNK_CTL_REG 0x00000710 1895 /* falcona0,falconb0,sienaa0=pci_f0_config */ 1896 1897 #define PCRF_AB_LRE_LBN 27 1898 #define PCRF_AB_LRE_WIDTH 1 1899 #define PCRF_AB_ESYNC_LBN 26 1900 #define PCRF_AB_ESYNC_WIDTH 1 1901 #define PCRF_AB_CRPT_LBN 25 1902 #define PCRF_AB_CRPT_WIDTH 1 1903 #define PCRF_AB_XB_LBN 24 1904 #define PCRF_AB_XB_WIDTH 1 1905 #define PCRF_AC_LC_LBN 16 1906 #define PCRF_AC_LC_WIDTH 6 1907 #define PCRF_AC_LDR_LBN 8 1908 #define PCRF_AC_LDR_WIDTH 4 1909 #define PCRF_AC_FLM_LBN 7 1910 #define PCRF_AC_FLM_WIDTH 1 1911 #define PCRF_AC_LKD_LBN 6 1912 #define PCRF_AC_LKD_WIDTH 1 1913 #define PCRF_AC_DLE_LBN 5 1914 #define PCRF_AC_DLE_WIDTH 1 1915 #define PCRF_AB_PORT_LNK_CTL_REG_RSVD0_LBN 4 1916 #define PCRF_AB_PORT_LNK_CTL_REG_RSVD0_WIDTH 1 1917 #define PCRF_AC_RA_LBN 3 1918 #define PCRF_AC_RA_WIDTH 1 1919 #define PCRF_AC_LE_LBN 2 1920 #define PCRF_AC_LE_WIDTH 1 1921 #define PCRF_AC_SD_LBN 1 1922 #define PCRF_AC_SD_WIDTH 1 1923 #define PCRF_AC_OMR_LBN 0 1924 #define PCRF_AC_OMR_WIDTH 1 1925 1926 /* 1927 * PC_LN_SKEW_REG(32bit): 1928 * Lane skew register 1929 */ 1930 1931 #define PCR_AC_LN_SKEW_REG 0x00000714 1932 /* falcona0,falconb0,sienaa0=pci_f0_config */ 1933 1934 #define PCRF_AC_DIS_LBN 31 1935 #define PCRF_AC_DIS_WIDTH 1 1936 #define PCRF_AB_RST_LBN 30 1937 #define PCRF_AB_RST_WIDTH 1 1938 #define PCRF_AC_AD_LBN 25 1939 #define PCRF_AC_AD_WIDTH 1 1940 #define PCRF_AC_FCD_LBN 24 1941 #define PCRF_AC_FCD_WIDTH 1 1942 #define PCRF_AC_LS2_LBN 16 1943 #define PCRF_AC_LS2_WIDTH 8 1944 #define PCRF_AC_LS1_LBN 8 1945 #define PCRF_AC_LS1_WIDTH 8 1946 #define PCRF_AC_LS0_LBN 0 1947 #define PCRF_AC_LS0_WIDTH 8 1948 1949 /* 1950 * PC_SYM_NUM_REG(16bit): 1951 * Symbol number register 1952 */ 1953 1954 #define PCR_AC_SYM_NUM_REG 0x00000718 1955 /* falcona0,falconb0,sienaa0=pci_f0_config */ 1956 1957 #define PCRF_CC_MAX_FUNCTIONS_LBN 29 1958 #define PCRF_CC_MAX_FUNCTIONS_WIDTH 3 1959 #define PCRF_CC_FC_WATCHDOG_TMR_LBN 24 1960 #define PCRF_CC_FC_WATCHDOG_TMR_WIDTH 5 1961 #define PCRF_CC_ACK_NAK_TMR_MOD_LBN 19 1962 #define PCRF_CC_ACK_NAK_TMR_MOD_WIDTH 5 1963 #define PCRF_CC_REPLAY_TMR_MOD_LBN 14 1964 #define PCRF_CC_REPLAY_TMR_MOD_WIDTH 5 1965 #define PCRF_AB_ES_LBN 12 1966 #define PCRF_AB_ES_WIDTH 3 1967 #define PCRF_AB_SYM_NUM_REG_RSVD0_LBN 11 1968 #define PCRF_AB_SYM_NUM_REG_RSVD0_WIDTH 1 1969 #define PCRF_CC_NUM_SKP_SYMS_LBN 8 1970 #define PCRF_CC_NUM_SKP_SYMS_WIDTH 3 1971 #define PCRF_AB_TS2_LBN 4 1972 #define PCRF_AB_TS2_WIDTH 4 1973 #define PCRF_AC_TS1_LBN 0 1974 #define PCRF_AC_TS1_WIDTH 4 1975 1976 /* 1977 * PC_SYM_TMR_FLT_MSK_REG(16bit): 1978 * Symbol timer and Filter Mask Register 1979 */ 1980 1981 #define PCR_CC_SYM_TMR_FLT_MSK_REG 0x0000071c 1982 /* sienaa0=pci_f0_config */ 1983 1984 #define PCRF_CC_DEFAULT_FLT_MSK1_LBN 16 1985 #define PCRF_CC_DEFAULT_FLT_MSK1_WIDTH 16 1986 #define PCRF_CC_FC_WDOG_TMR_DIS_LBN 15 1987 #define PCRF_CC_FC_WDOG_TMR_DIS_WIDTH 1 1988 #define PCRF_CC_SI1_LBN 8 1989 #define PCRF_CC_SI1_WIDTH 3 1990 #define PCRF_CC_SKIP_INT_VAL_LBN 0 1991 #define PCRF_CC_SKIP_INT_VAL_WIDTH 11 1992 #define PCRF_CC_SI0_LBN 0 1993 #define PCRF_CC_SI0_WIDTH 8 1994 1995 /* 1996 * PC_SYM_TMR_REG(16bit): 1997 * Symbol timer register 1998 */ 1999 2000 #define PCR_AB_SYM_TMR_REG 0x0000071c 2001 /* falcona0,falconb0=pci_f0_config */ 2002 2003 #define PCRF_AB_ET_LBN 11 2004 #define PCRF_AB_ET_WIDTH 4 2005 #define PCRF_AB_SI1_LBN 8 2006 #define PCRF_AB_SI1_WIDTH 3 2007 #define PCRF_AB_SI0_LBN 0 2008 #define PCRF_AB_SI0_WIDTH 8 2009 2010 /* 2011 * PC_FLT_MSK_REG(32bit): 2012 * Filter Mask Register 2 2013 */ 2014 2015 #define PCR_CC_FLT_MSK_REG 0x00000720 2016 /* sienaa0=pci_f0_config */ 2017 2018 #define PCRF_CC_DEFAULT_FLT_MSK2_LBN 0 2019 #define PCRF_CC_DEFAULT_FLT_MSK2_WIDTH 32 2020 2021 /* 2022 * PC_PHY_STAT_REG(32bit): 2023 * PHY status register 2024 */ 2025 2026 #define PCR_AB_PHY_STAT_REG 0x00000720 2027 /* falcona0,falconb0=pci_f0_config */ 2028 2029 #define PCR_CC_PHY_STAT_REG 0x00000810 2030 /* sienaa0=pci_f0_config */ 2031 2032 #define PCRF_AC_SSL_LBN 3 2033 #define PCRF_AC_SSL_WIDTH 1 2034 #define PCRF_AC_SSR_LBN 2 2035 #define PCRF_AC_SSR_WIDTH 1 2036 #define PCRF_AC_SSCL_LBN 1 2037 #define PCRF_AC_SSCL_WIDTH 1 2038 #define PCRF_AC_SSCD_LBN 0 2039 #define PCRF_AC_SSCD_WIDTH 1 2040 2041 /* 2042 * PC_PHY_CTL_REG(32bit): 2043 * PHY control register 2044 */ 2045 2046 #define PCR_AB_PHY_CTL_REG 0x00000724 2047 /* falcona0,falconb0=pci_f0_config */ 2048 2049 #define PCR_CC_PHY_CTL_REG 0x00000814 2050 /* sienaa0=pci_f0_config */ 2051 2052 #define PCRF_AC_BD_LBN 31 2053 #define PCRF_AC_BD_WIDTH 1 2054 #define PCRF_AC_CDS_LBN 30 2055 #define PCRF_AC_CDS_WIDTH 1 2056 #define PCRF_AC_DWRAP_LB_LBN 29 2057 #define PCRF_AC_DWRAP_LB_WIDTH 1 2058 #define PCRF_AC_EBD_LBN 28 2059 #define PCRF_AC_EBD_WIDTH 1 2060 #define PCRF_AC_SNR_LBN 27 2061 #define PCRF_AC_SNR_WIDTH 1 2062 #define PCRF_AC_RX_NOT_DET_LBN 2 2063 #define PCRF_AC_RX_NOT_DET_WIDTH 1 2064 #define PCRF_AC_FORCE_LOS_VAL_LBN 1 2065 #define PCRF_AC_FORCE_LOS_VAL_WIDTH 1 2066 #define PCRF_AC_FORCE_LOS_EN_LBN 0 2067 #define PCRF_AC_FORCE_LOS_EN_WIDTH 1 2068 2069 /* 2070 * PC_DEBUG0_REG(32bit): 2071 * Debug register 0 2072 */ 2073 2074 #define PCR_AC_DEBUG0_REG 0x00000728 2075 /* falcona0,falconb0,sienaa0=pci_f0_config */ 2076 2077 #define PCRF_AC_CDI03_LBN 24 2078 #define PCRF_AC_CDI03_WIDTH 8 2079 #define PCRF_AC_CDI0_LBN 0 2080 #define PCRF_AC_CDI0_WIDTH 32 2081 #define PCRF_AC_CDI02_LBN 16 2082 #define PCRF_AC_CDI02_WIDTH 8 2083 #define PCRF_AC_CDI01_LBN 8 2084 #define PCRF_AC_CDI01_WIDTH 8 2085 #define PCRF_AC_CDI00_LBN 0 2086 #define PCRF_AC_CDI00_WIDTH 8 2087 2088 /* 2089 * PC_DEBUG1_REG(32bit): 2090 * Debug register 1 2091 */ 2092 2093 #define PCR_AC_DEBUG1_REG 0x0000072c 2094 /* falcona0,falconb0,sienaa0=pci_f0_config */ 2095 2096 #define PCRF_AC_CDI13_LBN 24 2097 #define PCRF_AC_CDI13_WIDTH 8 2098 #define PCRF_AC_CDI1_LBN 0 2099 #define PCRF_AC_CDI1_WIDTH 32 2100 #define PCRF_AC_CDI12_LBN 16 2101 #define PCRF_AC_CDI12_WIDTH 8 2102 #define PCRF_AC_CDI11_LBN 8 2103 #define PCRF_AC_CDI11_WIDTH 8 2104 #define PCRF_AC_CDI10_LBN 0 2105 #define PCRF_AC_CDI10_WIDTH 8 2106 2107 /* 2108 * PC_XPFCC_STAT_REG(24bit): 2109 * documentation to be written for sum_PC_XPFCC_STAT_REG 2110 */ 2111 2112 #define PCR_AC_XPFCC_STAT_REG 0x00000730 2113 /* falcona0,falconb0,sienaa0=pci_f0_config */ 2114 2115 #define PCRF_AC_XPDC_LBN 12 2116 #define PCRF_AC_XPDC_WIDTH 8 2117 #define PCRF_AC_XPHC_LBN 0 2118 #define PCRF_AC_XPHC_WIDTH 12 2119 2120 /* 2121 * PC_XNPFCC_STAT_REG(24bit): 2122 * documentation to be written for sum_PC_XNPFCC_STAT_REG 2123 */ 2124 2125 #define PCR_AC_XNPFCC_STAT_REG 0x00000734 2126 /* falcona0,falconb0,sienaa0=pci_f0_config */ 2127 2128 #define PCRF_AC_XNPDC_LBN 12 2129 #define PCRF_AC_XNPDC_WIDTH 8 2130 #define PCRF_AC_XNPHC_LBN 0 2131 #define PCRF_AC_XNPHC_WIDTH 12 2132 2133 /* 2134 * PC_XCFCC_STAT_REG(24bit): 2135 * documentation to be written for sum_PC_XCFCC_STAT_REG 2136 */ 2137 2138 #define PCR_AC_XCFCC_STAT_REG 0x00000738 2139 /* falcona0,falconb0,sienaa0=pci_f0_config */ 2140 2141 #define PCRF_AC_XCDC_LBN 12 2142 #define PCRF_AC_XCDC_WIDTH 8 2143 #define PCRF_AC_XCHC_LBN 0 2144 #define PCRF_AC_XCHC_WIDTH 12 2145 2146 /* 2147 * PC_Q_STAT_REG(8bit): 2148 * documentation to be written for sum_PC_Q_STAT_REG 2149 */ 2150 2151 #define PCR_AC_Q_STAT_REG 0x0000073c 2152 /* falcona0,falconb0,sienaa0=pci_f0_config */ 2153 2154 #define PCRF_AC_RQNE_LBN 2 2155 #define PCRF_AC_RQNE_WIDTH 1 2156 #define PCRF_AC_XRNE_LBN 1 2157 #define PCRF_AC_XRNE_WIDTH 1 2158 #define PCRF_AC_RCNR_LBN 0 2159 #define PCRF_AC_RCNR_WIDTH 1 2160 2161 /* 2162 * PC_VC_XMIT_ARB1_REG(32bit): 2163 * VC Transmit Arbitration Register 1 2164 */ 2165 2166 #define PCR_CC_VC_XMIT_ARB1_REG 0x00000740 2167 /* sienaa0=pci_f0_config */ 2168 2169 /* 2170 * PC_VC_XMIT_ARB2_REG(32bit): 2171 * VC Transmit Arbitration Register 2 2172 */ 2173 2174 #define PCR_CC_VC_XMIT_ARB2_REG 0x00000744 2175 /* sienaa0=pci_f0_config */ 2176 2177 /* 2178 * PC_VC0_P_RQ_CTL_REG(32bit): 2179 * VC0 Posted Receive Queue Control 2180 */ 2181 2182 #define PCR_CC_VC0_P_RQ_CTL_REG 0x00000748 2183 /* sienaa0=pci_f0_config */ 2184 2185 /* 2186 * PC_VC0_NP_RQ_CTL_REG(32bit): 2187 * VC0 Non-Posted Receive Queue Control 2188 */ 2189 2190 #define PCR_CC_VC0_NP_RQ_CTL_REG 0x0000074c 2191 /* sienaa0=pci_f0_config */ 2192 2193 /* 2194 * PC_VC0_C_RQ_CTL_REG(32bit): 2195 * VC0 Completion Receive Queue Control 2196 */ 2197 2198 #define PCR_CC_VC0_C_RQ_CTL_REG 0x00000750 2199 /* sienaa0=pci_f0_config */ 2200 2201 /* 2202 * PC_GEN2_REG(32bit): 2203 * Gen2 Register 2204 */ 2205 2206 #define PCR_CC_GEN2_REG 0x0000080c 2207 /* sienaa0=pci_f0_config */ 2208 2209 #define PCRF_CC_SET_DE_EMPHASIS_LBN 20 2210 #define PCRF_CC_SET_DE_EMPHASIS_WIDTH 1 2211 #define PCRF_CC_CFG_TX_COMPLIANCE_LBN 19 2212 #define PCRF_CC_CFG_TX_COMPLIANCE_WIDTH 1 2213 #define PCRF_CC_CFG_TX_SWING_LBN 18 2214 #define PCRF_CC_CFG_TX_SWING_WIDTH 1 2215 #define PCRF_CC_DIR_SPEED_CHANGE_LBN 17 2216 #define PCRF_CC_DIR_SPEED_CHANGE_WIDTH 1 2217 #define PCRF_CC_LANE_ENABLE_LBN 8 2218 #define PCRF_CC_LANE_ENABLE_WIDTH 9 2219 #define PCRF_CC_NUM_FTS_LBN 0 2220 #define PCRF_CC_NUM_FTS_WIDTH 8 2221 2222 #ifdef __cplusplus 2223 } 2224 #endif 2225 2226 #endif /* _SYS_EFX_REGS_PCI_H */ 2227