1 /*- 2 * Copyright 2007-2010 Solarflare Communications Inc. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #ifndef _SYS_EFX_REGS_PCI_H 29 #define _SYS_EFX_REGS_PCI_H 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 /* 36 * PC_VEND_ID_REG(16bit): 37 * Vendor ID register 38 */ 39 40 #define PCR_AZ_VEND_ID_REG 0x00000000 41 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 42 43 #define PCRF_AZ_VEND_ID_LBN 0 44 #define PCRF_AZ_VEND_ID_WIDTH 16 45 46 47 /* 48 * PC_DEV_ID_REG(16bit): 49 * Device ID register 50 */ 51 52 #define PCR_AZ_DEV_ID_REG 0x00000002 53 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 54 55 #define PCRF_AZ_DEV_ID_LBN 0 56 #define PCRF_AZ_DEV_ID_WIDTH 16 57 58 59 /* 60 * PC_CMD_REG(16bit): 61 * Command register 62 */ 63 64 #define PCR_AZ_CMD_REG 0x00000004 65 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 66 67 #define PCRF_AZ_INTX_DIS_LBN 10 68 #define PCRF_AZ_INTX_DIS_WIDTH 1 69 #define PCRF_AZ_FB2B_EN_LBN 9 70 #define PCRF_AZ_FB2B_EN_WIDTH 1 71 #define PCRF_AZ_SERR_EN_LBN 8 72 #define PCRF_AZ_SERR_EN_WIDTH 1 73 #define PCRF_AZ_IDSEL_CTL_LBN 7 74 #define PCRF_AZ_IDSEL_CTL_WIDTH 1 75 #define PCRF_AZ_PERR_EN_LBN 6 76 #define PCRF_AZ_PERR_EN_WIDTH 1 77 #define PCRF_AZ_VGA_PAL_SNP_LBN 5 78 #define PCRF_AZ_VGA_PAL_SNP_WIDTH 1 79 #define PCRF_AZ_MWI_EN_LBN 4 80 #define PCRF_AZ_MWI_EN_WIDTH 1 81 #define PCRF_AZ_SPEC_CYC_LBN 3 82 #define PCRF_AZ_SPEC_CYC_WIDTH 1 83 #define PCRF_AZ_MST_EN_LBN 2 84 #define PCRF_AZ_MST_EN_WIDTH 1 85 #define PCRF_AZ_MEM_EN_LBN 1 86 #define PCRF_AZ_MEM_EN_WIDTH 1 87 #define PCRF_AZ_IO_EN_LBN 0 88 #define PCRF_AZ_IO_EN_WIDTH 1 89 90 91 /* 92 * PC_STAT_REG(16bit): 93 * Status register 94 */ 95 96 #define PCR_AZ_STAT_REG 0x00000006 97 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 98 99 #define PCRF_AZ_DET_PERR_LBN 15 100 #define PCRF_AZ_DET_PERR_WIDTH 1 101 #define PCRF_AZ_SIG_SERR_LBN 14 102 #define PCRF_AZ_SIG_SERR_WIDTH 1 103 #define PCRF_AZ_GOT_MABRT_LBN 13 104 #define PCRF_AZ_GOT_MABRT_WIDTH 1 105 #define PCRF_AZ_GOT_TABRT_LBN 12 106 #define PCRF_AZ_GOT_TABRT_WIDTH 1 107 #define PCRF_AZ_SIG_TABRT_LBN 11 108 #define PCRF_AZ_SIG_TABRT_WIDTH 1 109 #define PCRF_AZ_DEVSEL_TIM_LBN 9 110 #define PCRF_AZ_DEVSEL_TIM_WIDTH 2 111 #define PCRF_AZ_MDAT_PERR_LBN 8 112 #define PCRF_AZ_MDAT_PERR_WIDTH 1 113 #define PCRF_AZ_FB2B_CAP_LBN 7 114 #define PCRF_AZ_FB2B_CAP_WIDTH 1 115 #define PCRF_AZ_66MHZ_CAP_LBN 5 116 #define PCRF_AZ_66MHZ_CAP_WIDTH 1 117 #define PCRF_AZ_CAP_LIST_LBN 4 118 #define PCRF_AZ_CAP_LIST_WIDTH 1 119 #define PCRF_AZ_INTX_STAT_LBN 3 120 #define PCRF_AZ_INTX_STAT_WIDTH 1 121 122 123 /* 124 * PC_REV_ID_REG(8bit): 125 * Class code & revision ID register 126 */ 127 128 #define PCR_AZ_REV_ID_REG 0x00000008 129 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 130 131 #define PCRF_AZ_REV_ID_LBN 0 132 #define PCRF_AZ_REV_ID_WIDTH 8 133 134 135 /* 136 * PC_CC_REG(24bit): 137 * Class code register 138 */ 139 140 #define PCR_AZ_CC_REG 0x00000009 141 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 142 143 #define PCRF_AZ_BASE_CC_LBN 16 144 #define PCRF_AZ_BASE_CC_WIDTH 8 145 #define PCRF_AZ_SUB_CC_LBN 8 146 #define PCRF_AZ_SUB_CC_WIDTH 8 147 #define PCRF_AZ_PROG_IF_LBN 0 148 #define PCRF_AZ_PROG_IF_WIDTH 8 149 150 151 /* 152 * PC_CACHE_LSIZE_REG(8bit): 153 * Cache line size 154 */ 155 156 #define PCR_AZ_CACHE_LSIZE_REG 0x0000000c 157 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 158 159 #define PCRF_AZ_CACHE_LSIZE_LBN 0 160 #define PCRF_AZ_CACHE_LSIZE_WIDTH 8 161 162 163 /* 164 * PC_MST_LAT_REG(8bit): 165 * Master latency timer register 166 */ 167 168 #define PCR_AZ_MST_LAT_REG 0x0000000d 169 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 170 171 #define PCRF_AZ_MST_LAT_LBN 0 172 #define PCRF_AZ_MST_LAT_WIDTH 8 173 174 175 /* 176 * PC_HDR_TYPE_REG(8bit): 177 * Header type register 178 */ 179 180 #define PCR_AZ_HDR_TYPE_REG 0x0000000e 181 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 182 183 #define PCRF_AZ_MULT_FUNC_LBN 7 184 #define PCRF_AZ_MULT_FUNC_WIDTH 1 185 #define PCRF_AZ_TYPE_LBN 0 186 #define PCRF_AZ_TYPE_WIDTH 7 187 188 189 /* 190 * PC_BIST_REG(8bit): 191 * BIST register 192 */ 193 194 #define PCR_AZ_BIST_REG 0x0000000f 195 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 196 197 #define PCRF_AZ_BIST_LBN 0 198 #define PCRF_AZ_BIST_WIDTH 8 199 200 201 /* 202 * PC_BAR0_REG(32bit): 203 * Primary function base address register 0 204 */ 205 206 #define PCR_AZ_BAR0_REG 0x00000010 207 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 208 209 #define PCRF_AZ_BAR0_LBN 4 210 #define PCRF_AZ_BAR0_WIDTH 28 211 #define PCRF_AZ_BAR0_PREF_LBN 3 212 #define PCRF_AZ_BAR0_PREF_WIDTH 1 213 #define PCRF_AZ_BAR0_TYPE_LBN 1 214 #define PCRF_AZ_BAR0_TYPE_WIDTH 2 215 #define PCRF_AZ_BAR0_IOM_LBN 0 216 #define PCRF_AZ_BAR0_IOM_WIDTH 1 217 218 219 /* 220 * PC_BAR1_REG(32bit): 221 * Primary function base address register 1, BAR1 is not implemented so read only. 222 */ 223 224 #define PCR_DZ_BAR1_REG 0x00000014 225 /* hunta0=pci_f0_config */ 226 227 #define PCRF_DZ_BAR1_LBN 0 228 #define PCRF_DZ_BAR1_WIDTH 32 229 230 231 /* 232 * PC_BAR2_LO_REG(32bit): 233 * Primary function base address register 2 low bits 234 */ 235 236 #define PCR_AZ_BAR2_LO_REG 0x00000018 237 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 238 239 #define PCRF_AZ_BAR2_LO_LBN 4 240 #define PCRF_AZ_BAR2_LO_WIDTH 28 241 #define PCRF_AZ_BAR2_PREF_LBN 3 242 #define PCRF_AZ_BAR2_PREF_WIDTH 1 243 #define PCRF_AZ_BAR2_TYPE_LBN 1 244 #define PCRF_AZ_BAR2_TYPE_WIDTH 2 245 #define PCRF_AZ_BAR2_IOM_LBN 0 246 #define PCRF_AZ_BAR2_IOM_WIDTH 1 247 248 249 /* 250 * PC_BAR2_HI_REG(32bit): 251 * Primary function base address register 2 high bits 252 */ 253 254 #define PCR_AZ_BAR2_HI_REG 0x0000001c 255 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 256 257 #define PCRF_AZ_BAR2_HI_LBN 0 258 #define PCRF_AZ_BAR2_HI_WIDTH 32 259 260 261 /* 262 * PC_BAR4_LO_REG(32bit): 263 * Primary function base address register 2 low bits 264 */ 265 266 #define PCR_CZ_BAR4_LO_REG 0x00000020 267 /* sienaa0,hunta0=pci_f0_config */ 268 269 #define PCRF_CZ_BAR4_LO_LBN 4 270 #define PCRF_CZ_BAR4_LO_WIDTH 28 271 #define PCRF_CZ_BAR4_PREF_LBN 3 272 #define PCRF_CZ_BAR4_PREF_WIDTH 1 273 #define PCRF_CZ_BAR4_TYPE_LBN 1 274 #define PCRF_CZ_BAR4_TYPE_WIDTH 2 275 #define PCRF_CZ_BAR4_IOM_LBN 0 276 #define PCRF_CZ_BAR4_IOM_WIDTH 1 277 278 279 /* 280 * PC_BAR4_HI_REG(32bit): 281 * Primary function base address register 2 high bits 282 */ 283 284 #define PCR_CZ_BAR4_HI_REG 0x00000024 285 /* sienaa0,hunta0=pci_f0_config */ 286 287 #define PCRF_CZ_BAR4_HI_LBN 0 288 #define PCRF_CZ_BAR4_HI_WIDTH 32 289 290 291 /* 292 * PC_SS_VEND_ID_REG(16bit): 293 * Sub-system vendor ID register 294 */ 295 296 #define PCR_AZ_SS_VEND_ID_REG 0x0000002c 297 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 298 299 #define PCRF_AZ_SS_VEND_ID_LBN 0 300 #define PCRF_AZ_SS_VEND_ID_WIDTH 16 301 302 303 /* 304 * PC_SS_ID_REG(16bit): 305 * Sub-system ID register 306 */ 307 308 #define PCR_AZ_SS_ID_REG 0x0000002e 309 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 310 311 #define PCRF_AZ_SS_ID_LBN 0 312 #define PCRF_AZ_SS_ID_WIDTH 16 313 314 315 /* 316 * PC_EXPROM_BAR_REG(32bit): 317 * Expansion ROM base address register 318 */ 319 320 #define PCR_AZ_EXPROM_BAR_REG 0x00000030 321 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 322 323 #define PCRF_AZ_EXPROM_BAR_LBN 11 324 #define PCRF_AZ_EXPROM_BAR_WIDTH 21 325 #define PCRF_AB_EXPROM_MIN_SIZE_LBN 2 326 #define PCRF_AB_EXPROM_MIN_SIZE_WIDTH 9 327 #define PCRF_CZ_EXPROM_MIN_SIZE_LBN 1 328 #define PCRF_CZ_EXPROM_MIN_SIZE_WIDTH 10 329 #define PCRF_AB_EXPROM_FEATURE_ENABLE_LBN 1 330 #define PCRF_AB_EXPROM_FEATURE_ENABLE_WIDTH 1 331 #define PCRF_AZ_EXPROM_EN_LBN 0 332 #define PCRF_AZ_EXPROM_EN_WIDTH 1 333 334 335 /* 336 * PC_CAP_PTR_REG(8bit): 337 * Capability pointer register 338 */ 339 340 #define PCR_AZ_CAP_PTR_REG 0x00000034 341 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 342 343 #define PCRF_AZ_CAP_PTR_LBN 0 344 #define PCRF_AZ_CAP_PTR_WIDTH 8 345 346 347 /* 348 * PC_INT_LINE_REG(8bit): 349 * Interrupt line register 350 */ 351 352 #define PCR_AZ_INT_LINE_REG 0x0000003c 353 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 354 355 #define PCRF_AZ_INT_LINE_LBN 0 356 #define PCRF_AZ_INT_LINE_WIDTH 8 357 358 359 /* 360 * PC_INT_PIN_REG(8bit): 361 * Interrupt pin register 362 */ 363 364 #define PCR_AZ_INT_PIN_REG 0x0000003d 365 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 366 367 #define PCRF_AZ_INT_PIN_LBN 0 368 #define PCRF_AZ_INT_PIN_WIDTH 8 369 370 371 /* 372 * PC_PM_CAP_ID_REG(8bit): 373 * Power management capability ID 374 */ 375 376 #define PCR_AC_PM_CAP_ID_REG 0x00000040 377 /* falcona0,falconb0,sienaa0=pci_f0_config */ 378 379 #define PCR_DZ_PM_CAP_ID_REG 0x00000080 380 /* hunta0=pci_f0_config */ 381 382 #define PCRF_AZ_PM_CAP_ID_LBN 0 383 #define PCRF_AZ_PM_CAP_ID_WIDTH 8 384 385 386 /* 387 * PC_PM_NXT_PTR_REG(8bit): 388 * Power management next item pointer 389 */ 390 391 #define PCR_AC_PM_NXT_PTR_REG 0x00000041 392 /* falcona0,falconb0,sienaa0=pci_f0_config */ 393 394 #define PCR_DZ_PM_NXT_PTR_REG 0x00000081 395 /* hunta0=pci_f0_config */ 396 397 #define PCRF_AZ_PM_NXT_PTR_LBN 0 398 #define PCRF_AZ_PM_NXT_PTR_WIDTH 8 399 400 401 /* 402 * PC_PM_CAP_REG(16bit): 403 * Power management capabilities register 404 */ 405 406 #define PCR_AC_PM_CAP_REG 0x00000042 407 /* falcona0,falconb0,sienaa0=pci_f0_config */ 408 409 #define PCR_DZ_PM_CAP_REG 0x00000082 410 /* hunta0=pci_f0_config */ 411 412 #define PCRF_AZ_PM_PME_SUPT_LBN 11 413 #define PCRF_AZ_PM_PME_SUPT_WIDTH 5 414 #define PCRF_AZ_PM_D2_SUPT_LBN 10 415 #define PCRF_AZ_PM_D2_SUPT_WIDTH 1 416 #define PCRF_AZ_PM_D1_SUPT_LBN 9 417 #define PCRF_AZ_PM_D1_SUPT_WIDTH 1 418 #define PCRF_AZ_PM_AUX_CURR_LBN 6 419 #define PCRF_AZ_PM_AUX_CURR_WIDTH 3 420 #define PCRF_AZ_PM_DSI_LBN 5 421 #define PCRF_AZ_PM_DSI_WIDTH 1 422 #define PCRF_AZ_PM_PME_CLK_LBN 3 423 #define PCRF_AZ_PM_PME_CLK_WIDTH 1 424 #define PCRF_AZ_PM_PME_VER_LBN 0 425 #define PCRF_AZ_PM_PME_VER_WIDTH 3 426 427 428 /* 429 * PC_PM_CS_REG(16bit): 430 * Power management control & status register 431 */ 432 433 #define PCR_AC_PM_CS_REG 0x00000044 434 /* falcona0,falconb0,sienaa0=pci_f0_config */ 435 436 #define PCR_DZ_PM_CS_REG 0x00000084 437 /* hunta0=pci_f0_config */ 438 439 #define PCRF_AZ_PM_PME_STAT_LBN 15 440 #define PCRF_AZ_PM_PME_STAT_WIDTH 1 441 #define PCRF_AZ_PM_DAT_SCALE_LBN 13 442 #define PCRF_AZ_PM_DAT_SCALE_WIDTH 2 443 #define PCRF_AZ_PM_DAT_SEL_LBN 9 444 #define PCRF_AZ_PM_DAT_SEL_WIDTH 4 445 #define PCRF_AZ_PM_PME_EN_LBN 8 446 #define PCRF_AZ_PM_PME_EN_WIDTH 1 447 #define PCRF_CZ_NO_SOFT_RESET_LBN 3 448 #define PCRF_CZ_NO_SOFT_RESET_WIDTH 1 449 #define PCRF_AZ_PM_PWR_ST_LBN 0 450 #define PCRF_AZ_PM_PWR_ST_WIDTH 2 451 452 453 /* 454 * PC_MSI_CAP_ID_REG(8bit): 455 * MSI capability ID 456 */ 457 458 #define PCR_AC_MSI_CAP_ID_REG 0x00000050 459 /* falcona0,falconb0,sienaa0=pci_f0_config */ 460 461 #define PCR_DZ_MSI_CAP_ID_REG 0x00000090 462 /* hunta0=pci_f0_config */ 463 464 #define PCRF_AZ_MSI_CAP_ID_LBN 0 465 #define PCRF_AZ_MSI_CAP_ID_WIDTH 8 466 467 468 /* 469 * PC_MSI_NXT_PTR_REG(8bit): 470 * MSI next item pointer 471 */ 472 473 #define PCR_AC_MSI_NXT_PTR_REG 0x00000051 474 /* falcona0,falconb0,sienaa0=pci_f0_config */ 475 476 #define PCR_DZ_MSI_NXT_PTR_REG 0x00000091 477 /* hunta0=pci_f0_config */ 478 479 #define PCRF_AZ_MSI_NXT_PTR_LBN 0 480 #define PCRF_AZ_MSI_NXT_PTR_WIDTH 8 481 482 483 /* 484 * PC_MSI_CTL_REG(16bit): 485 * MSI control register 486 */ 487 488 #define PCR_AC_MSI_CTL_REG 0x00000052 489 /* falcona0,falconb0,sienaa0=pci_f0_config */ 490 491 #define PCR_DZ_MSI_CTL_REG 0x00000092 492 /* hunta0=pci_f0_config */ 493 494 #define PCRF_AZ_MSI_64_EN_LBN 7 495 #define PCRF_AZ_MSI_64_EN_WIDTH 1 496 #define PCRF_AZ_MSI_MULT_MSG_EN_LBN 4 497 #define PCRF_AZ_MSI_MULT_MSG_EN_WIDTH 3 498 #define PCRF_AZ_MSI_MULT_MSG_CAP_LBN 1 499 #define PCRF_AZ_MSI_MULT_MSG_CAP_WIDTH 3 500 #define PCRF_AZ_MSI_EN_LBN 0 501 #define PCRF_AZ_MSI_EN_WIDTH 1 502 503 504 /* 505 * PC_MSI_ADR_LO_REG(32bit): 506 * MSI low 32 bits address register 507 */ 508 509 #define PCR_AC_MSI_ADR_LO_REG 0x00000054 510 /* falcona0,falconb0,sienaa0=pci_f0_config */ 511 512 #define PCR_DZ_MSI_ADR_LO_REG 0x00000094 513 /* hunta0=pci_f0_config */ 514 515 #define PCRF_AZ_MSI_ADR_LO_LBN 2 516 #define PCRF_AZ_MSI_ADR_LO_WIDTH 30 517 518 519 /* 520 * PC_VPD_CAP_CTL_REG(8bit): 521 * VPD control and capabilities register 522 */ 523 524 #define PCR_DZ_VPD_CAP_CTL_REG 0x00000054 525 /* hunta0=pci_f0_config */ 526 527 #define PCR_CC_VPD_CAP_CTL_REG 0x000000d0 528 /* sienaa0=pci_f0_config */ 529 530 #define PCRF_CZ_VPD_FLAG_LBN 31 531 #define PCRF_CZ_VPD_FLAG_WIDTH 1 532 #define PCRF_CZ_VPD_ADDR_LBN 16 533 #define PCRF_CZ_VPD_ADDR_WIDTH 15 534 #define PCRF_CZ_VPD_NXT_PTR_LBN 8 535 #define PCRF_CZ_VPD_NXT_PTR_WIDTH 8 536 #define PCRF_CZ_VPD_CAP_ID_LBN 0 537 #define PCRF_CZ_VPD_CAP_ID_WIDTH 8 538 539 540 /* 541 * PC_VPD_CAP_DATA_REG(32bit): 542 * documentation to be written for sum_PC_VPD_CAP_DATA_REG 543 */ 544 545 #define PCR_DZ_VPD_CAP_DATA_REG 0x00000058 546 /* hunta0=pci_f0_config */ 547 548 #define PCR_AB_VPD_CAP_DATA_REG 0x000000b4 549 /* falcona0,falconb0=pci_f0_config */ 550 551 #define PCR_CC_VPD_CAP_DATA_REG 0x000000d4 552 /* sienaa0=pci_f0_config */ 553 554 #define PCRF_AZ_VPD_DATA_LBN 0 555 #define PCRF_AZ_VPD_DATA_WIDTH 32 556 557 558 /* 559 * PC_MSI_ADR_HI_REG(32bit): 560 * MSI high 32 bits address register 561 */ 562 563 #define PCR_AC_MSI_ADR_HI_REG 0x00000058 564 /* falcona0,falconb0,sienaa0=pci_f0_config */ 565 566 #define PCR_DZ_MSI_ADR_HI_REG 0x00000098 567 /* hunta0=pci_f0_config */ 568 569 #define PCRF_AZ_MSI_ADR_HI_LBN 0 570 #define PCRF_AZ_MSI_ADR_HI_WIDTH 32 571 572 573 /* 574 * PC_MSI_DAT_REG(16bit): 575 * MSI data register 576 */ 577 578 #define PCR_AC_MSI_DAT_REG 0x0000005c 579 /* falcona0,falconb0,sienaa0=pci_f0_config */ 580 581 #define PCR_DZ_MSI_DAT_REG 0x0000009c 582 /* hunta0=pci_f0_config */ 583 584 #define PCRF_AZ_MSI_DAT_LBN 0 585 #define PCRF_AZ_MSI_DAT_WIDTH 16 586 587 588 /* 589 * PC_PCIE_CAP_LIST_REG(16bit): 590 * PCIe capability list register 591 */ 592 593 #define PCR_AB_PCIE_CAP_LIST_REG 0x00000060 594 /* falcona0,falconb0=pci_f0_config */ 595 596 #define PCR_CC_PCIE_CAP_LIST_REG 0x00000070 597 /* sienaa0=pci_f0_config */ 598 599 #define PCR_DZ_PCIE_CAP_LIST_REG 0x000000c0 600 /* hunta0=pci_f0_config */ 601 602 #define PCRF_AZ_PCIE_NXT_PTR_LBN 8 603 #define PCRF_AZ_PCIE_NXT_PTR_WIDTH 8 604 #define PCRF_AZ_PCIE_CAP_ID_LBN 0 605 #define PCRF_AZ_PCIE_CAP_ID_WIDTH 8 606 607 608 /* 609 * PC_PCIE_CAP_REG(16bit): 610 * PCIe capability register 611 */ 612 613 #define PCR_AB_PCIE_CAP_REG 0x00000062 614 /* falcona0,falconb0=pci_f0_config */ 615 616 #define PCR_CC_PCIE_CAP_REG 0x00000072 617 /* sienaa0=pci_f0_config */ 618 619 #define PCR_DZ_PCIE_CAP_REG 0x000000c2 620 /* hunta0=pci_f0_config */ 621 622 #define PCRF_AZ_PCIE_INT_MSG_NUM_LBN 9 623 #define PCRF_AZ_PCIE_INT_MSG_NUM_WIDTH 5 624 #define PCRF_AZ_PCIE_SLOT_IMP_LBN 8 625 #define PCRF_AZ_PCIE_SLOT_IMP_WIDTH 1 626 #define PCRF_AZ_PCIE_DEV_PORT_TYPE_LBN 4 627 #define PCRF_AZ_PCIE_DEV_PORT_TYPE_WIDTH 4 628 #define PCRF_AZ_PCIE_CAP_VER_LBN 0 629 #define PCRF_AZ_PCIE_CAP_VER_WIDTH 4 630 631 632 /* 633 * PC_DEV_CAP_REG(32bit): 634 * PCIe device capabilities register 635 */ 636 637 #define PCR_AB_DEV_CAP_REG 0x00000064 638 /* falcona0,falconb0=pci_f0_config */ 639 640 #define PCR_CC_DEV_CAP_REG 0x00000074 641 /* sienaa0=pci_f0_config */ 642 643 #define PCR_DZ_DEV_CAP_REG 0x000000c4 644 /* hunta0=pci_f0_config */ 645 646 #define PCRF_CZ_CAP_FN_LEVEL_RESET_LBN 28 647 #define PCRF_CZ_CAP_FN_LEVEL_RESET_WIDTH 1 648 #define PCRF_AZ_CAP_SLOT_PWR_SCL_LBN 26 649 #define PCRF_AZ_CAP_SLOT_PWR_SCL_WIDTH 2 650 #define PCRF_AZ_CAP_SLOT_PWR_VAL_LBN 18 651 #define PCRF_AZ_CAP_SLOT_PWR_VAL_WIDTH 8 652 #define PCRF_CZ_ROLE_BASE_ERR_REPORTING_LBN 15 653 #define PCRF_CZ_ROLE_BASE_ERR_REPORTING_WIDTH 1 654 #define PCRF_AB_PWR_IND_LBN 14 655 #define PCRF_AB_PWR_IND_WIDTH 1 656 #define PCRF_AB_ATTN_IND_LBN 13 657 #define PCRF_AB_ATTN_IND_WIDTH 1 658 #define PCRF_AB_ATTN_BUTTON_LBN 12 659 #define PCRF_AB_ATTN_BUTTON_WIDTH 1 660 #define PCRF_AZ_ENDPT_L1_LAT_LBN 9 661 #define PCRF_AZ_ENDPT_L1_LAT_WIDTH 3 662 #define PCRF_AZ_ENDPT_L0_LAT_LBN 6 663 #define PCRF_AZ_ENDPT_L0_LAT_WIDTH 3 664 #define PCRF_AZ_TAG_FIELD_LBN 5 665 #define PCRF_AZ_TAG_FIELD_WIDTH 1 666 #define PCRF_AZ_PHAN_FUNC_LBN 3 667 #define PCRF_AZ_PHAN_FUNC_WIDTH 2 668 #define PCRF_AZ_MAX_PAYL_SIZE_SUPT_LBN 0 669 #define PCRF_AZ_MAX_PAYL_SIZE_SUPT_WIDTH 3 670 671 672 /* 673 * PC_DEV_CTL_REG(16bit): 674 * PCIe device control register 675 */ 676 677 #define PCR_AB_DEV_CTL_REG 0x00000068 678 /* falcona0,falconb0=pci_f0_config */ 679 680 #define PCR_CC_DEV_CTL_REG 0x00000078 681 /* sienaa0=pci_f0_config */ 682 683 #define PCR_DZ_DEV_CTL_REG 0x000000c8 684 /* hunta0=pci_f0_config */ 685 686 #define PCRF_CZ_FN_LEVEL_RESET_LBN 15 687 #define PCRF_CZ_FN_LEVEL_RESET_WIDTH 1 688 #define PCRF_AZ_MAX_RD_REQ_SIZE_LBN 12 689 #define PCRF_AZ_MAX_RD_REQ_SIZE_WIDTH 3 690 #define PCFE_AZ_MAX_RD_REQ_SIZE_4096 5 691 #define PCFE_AZ_MAX_RD_REQ_SIZE_2048 4 692 #define PCFE_AZ_MAX_RD_REQ_SIZE_1024 3 693 #define PCFE_AZ_MAX_RD_REQ_SIZE_512 2 694 #define PCFE_AZ_MAX_RD_REQ_SIZE_256 1 695 #define PCFE_AZ_MAX_RD_REQ_SIZE_128 0 696 #define PCFE_DZ_OTHER other 697 #define PCRF_AZ_EN_NO_SNOOP_LBN 11 698 #define PCRF_AZ_EN_NO_SNOOP_WIDTH 1 699 #define PCRF_AZ_AUX_PWR_PM_EN_LBN 10 700 #define PCRF_AZ_AUX_PWR_PM_EN_WIDTH 1 701 #define PCRF_AZ_PHAN_FUNC_EN_LBN 9 702 #define PCRF_AZ_PHAN_FUNC_EN_WIDTH 1 703 #define PCRF_AB_DEV_CAP_REG_RSVD0_LBN 8 704 #define PCRF_AB_DEV_CAP_REG_RSVD0_WIDTH 1 705 #define PCRF_CZ_EXTENDED_TAG_EN_LBN 8 706 #define PCRF_CZ_EXTENDED_TAG_EN_WIDTH 1 707 #define PCRF_AZ_MAX_PAYL_SIZE_LBN 5 708 #define PCRF_AZ_MAX_PAYL_SIZE_WIDTH 3 709 #define PCFE_AZ_MAX_PAYL_SIZE_4096 5 710 #define PCFE_AZ_MAX_PAYL_SIZE_2048 4 711 #define PCFE_AZ_MAX_PAYL_SIZE_1024 3 712 #define PCFE_AZ_MAX_PAYL_SIZE_512 2 713 #define PCFE_AZ_MAX_PAYL_SIZE_256 1 714 #define PCFE_AZ_MAX_PAYL_SIZE_128 0 715 #define PCFE_DZ_OTHER other 716 #define PCRF_AZ_EN_RELAX_ORDER_LBN 4 717 #define PCRF_AZ_EN_RELAX_ORDER_WIDTH 1 718 #define PCRF_AZ_UNSUP_REQ_RPT_EN_LBN 3 719 #define PCRF_AZ_UNSUP_REQ_RPT_EN_WIDTH 1 720 #define PCRF_AZ_FATAL_ERR_RPT_EN_LBN 2 721 #define PCRF_AZ_FATAL_ERR_RPT_EN_WIDTH 1 722 #define PCRF_AZ_NONFATAL_ERR_RPT_EN_LBN 1 723 #define PCRF_AZ_NONFATAL_ERR_RPT_EN_WIDTH 1 724 #define PCRF_AZ_CORR_ERR_RPT_EN_LBN 0 725 #define PCRF_AZ_CORR_ERR_RPT_EN_WIDTH 1 726 727 728 /* 729 * PC_DEV_STAT_REG(16bit): 730 * PCIe device status register 731 */ 732 733 #define PCR_AB_DEV_STAT_REG 0x0000006a 734 /* falcona0,falconb0=pci_f0_config */ 735 736 #define PCR_CC_DEV_STAT_REG 0x0000007a 737 /* sienaa0=pci_f0_config */ 738 739 #define PCR_DZ_DEV_STAT_REG 0x000000ca 740 /* hunta0=pci_f0_config */ 741 742 #define PCRF_AZ_TRNS_PEND_LBN 5 743 #define PCRF_AZ_TRNS_PEND_WIDTH 1 744 #define PCRF_AZ_AUX_PWR_DET_LBN 4 745 #define PCRF_AZ_AUX_PWR_DET_WIDTH 1 746 #define PCRF_AZ_UNSUP_REQ_DET_LBN 3 747 #define PCRF_AZ_UNSUP_REQ_DET_WIDTH 1 748 #define PCRF_AZ_FATAL_ERR_DET_LBN 2 749 #define PCRF_AZ_FATAL_ERR_DET_WIDTH 1 750 #define PCRF_AZ_NONFATAL_ERR_DET_LBN 1 751 #define PCRF_AZ_NONFATAL_ERR_DET_WIDTH 1 752 #define PCRF_AZ_CORR_ERR_DET_LBN 0 753 #define PCRF_AZ_CORR_ERR_DET_WIDTH 1 754 755 756 /* 757 * PC_LNK_CAP_REG(32bit): 758 * PCIe link capabilities register 759 */ 760 761 #define PCR_AB_LNK_CAP_REG 0x0000006c 762 /* falcona0,falconb0=pci_f0_config */ 763 764 #define PCR_CC_LNK_CAP_REG 0x0000007c 765 /* sienaa0=pci_f0_config */ 766 767 #define PCR_DZ_LNK_CAP_REG 0x000000cc 768 /* hunta0=pci_f0_config */ 769 770 #define PCRF_AZ_PORT_NUM_LBN 24 771 #define PCRF_AZ_PORT_NUM_WIDTH 8 772 #define PCRF_CZ_LINK_BWDITH_NOTIF_CAP_LBN 21 773 #define PCRF_CZ_LINK_BWDITH_NOTIF_CAP_WIDTH 1 774 #define PCRF_CZ_DATA_LINK_ACTIVE_RPT_CAP_LBN 20 775 #define PCRF_CZ_DATA_LINK_ACTIVE_RPT_CAP_WIDTH 1 776 #define PCRF_CZ_SURPISE_DOWN_RPT_CAP_LBN 19 777 #define PCRF_CZ_SURPISE_DOWN_RPT_CAP_WIDTH 1 778 #define PCRF_CZ_CLOCK_PWR_MNGMNT_CAP_LBN 18 779 #define PCRF_CZ_CLOCK_PWR_MNGMNT_CAP_WIDTH 1 780 #define PCRF_AZ_DEF_L1_EXIT_LAT_LBN 15 781 #define PCRF_AZ_DEF_L1_EXIT_LAT_WIDTH 3 782 #define PCRF_AZ_DEF_L0_EXIT_LATPORT_NUM_LBN 12 783 #define PCRF_AZ_DEF_L0_EXIT_LATPORT_NUM_WIDTH 3 784 #define PCRF_AZ_AS_LNK_PM_SUPT_LBN 10 785 #define PCRF_AZ_AS_LNK_PM_SUPT_WIDTH 2 786 #define PCRF_AZ_MAX_LNK_WIDTH_LBN 4 787 #define PCRF_AZ_MAX_LNK_WIDTH_WIDTH 6 788 #define PCRF_AZ_MAX_LNK_SP_LBN 0 789 #define PCRF_AZ_MAX_LNK_SP_WIDTH 4 790 791 792 /* 793 * PC_LNK_CTL_REG(16bit): 794 * PCIe link control register 795 */ 796 797 #define PCR_AB_LNK_CTL_REG 0x00000070 798 /* falcona0,falconb0=pci_f0_config */ 799 800 #define PCR_CC_LNK_CTL_REG 0x00000080 801 /* sienaa0=pci_f0_config */ 802 803 #define PCR_DZ_LNK_CTL_REG 0x000000d0 804 /* hunta0=pci_f0_config */ 805 806 #define PCRF_AZ_EXT_SYNC_LBN 7 807 #define PCRF_AZ_EXT_SYNC_WIDTH 1 808 #define PCRF_AZ_COMM_CLK_CFG_LBN 6 809 #define PCRF_AZ_COMM_CLK_CFG_WIDTH 1 810 #define PCRF_AB_LNK_CTL_REG_RSVD0_LBN 5 811 #define PCRF_AB_LNK_CTL_REG_RSVD0_WIDTH 1 812 #define PCRF_CZ_LNK_RETRAIN_LBN 5 813 #define PCRF_CZ_LNK_RETRAIN_WIDTH 1 814 #define PCRF_AZ_LNK_DIS_LBN 4 815 #define PCRF_AZ_LNK_DIS_WIDTH 1 816 #define PCRF_AZ_RD_COM_BDRY_LBN 3 817 #define PCRF_AZ_RD_COM_BDRY_WIDTH 1 818 #define PCRF_AZ_ACT_ST_LNK_PM_CTL_LBN 0 819 #define PCRF_AZ_ACT_ST_LNK_PM_CTL_WIDTH 2 820 821 822 /* 823 * PC_LNK_STAT_REG(16bit): 824 * PCIe link status register 825 */ 826 827 #define PCR_AB_LNK_STAT_REG 0x00000072 828 /* falcona0,falconb0=pci_f0_config */ 829 830 #define PCR_CC_LNK_STAT_REG 0x00000082 831 /* sienaa0=pci_f0_config */ 832 833 #define PCR_DZ_LNK_STAT_REG 0x000000d2 834 /* hunta0=pci_f0_config */ 835 836 #define PCRF_AZ_SLOT_CLK_CFG_LBN 12 837 #define PCRF_AZ_SLOT_CLK_CFG_WIDTH 1 838 #define PCRF_AZ_LNK_TRAIN_LBN 11 839 #define PCRF_AZ_LNK_TRAIN_WIDTH 1 840 #define PCRF_AB_TRAIN_ERR_LBN 10 841 #define PCRF_AB_TRAIN_ERR_WIDTH 1 842 #define PCRF_AZ_LNK_WIDTH_LBN 4 843 #define PCRF_AZ_LNK_WIDTH_WIDTH 6 844 #define PCRF_AZ_LNK_SP_LBN 0 845 #define PCRF_AZ_LNK_SP_WIDTH 4 846 847 848 /* 849 * PC_SLOT_CAP_REG(32bit): 850 * PCIe slot capabilities register 851 */ 852 853 #define PCR_AB_SLOT_CAP_REG 0x00000074 854 /* falcona0,falconb0=pci_f0_config */ 855 856 #define PCRF_AB_SLOT_NUM_LBN 19 857 #define PCRF_AB_SLOT_NUM_WIDTH 13 858 #define PCRF_AB_SLOT_PWR_LIM_SCL_LBN 15 859 #define PCRF_AB_SLOT_PWR_LIM_SCL_WIDTH 2 860 #define PCRF_AB_SLOT_PWR_LIM_VAL_LBN 7 861 #define PCRF_AB_SLOT_PWR_LIM_VAL_WIDTH 8 862 #define PCRF_AB_SLOT_HP_CAP_LBN 6 863 #define PCRF_AB_SLOT_HP_CAP_WIDTH 1 864 #define PCRF_AB_SLOT_HP_SURP_LBN 5 865 #define PCRF_AB_SLOT_HP_SURP_WIDTH 1 866 #define PCRF_AB_SLOT_PWR_IND_PRST_LBN 4 867 #define PCRF_AB_SLOT_PWR_IND_PRST_WIDTH 1 868 #define PCRF_AB_SLOT_ATTN_IND_PRST_LBN 3 869 #define PCRF_AB_SLOT_ATTN_IND_PRST_WIDTH 1 870 #define PCRF_AB_SLOT_MRL_SENS_PRST_LBN 2 871 #define PCRF_AB_SLOT_MRL_SENS_PRST_WIDTH 1 872 #define PCRF_AB_SLOT_PWR_CTL_PRST_LBN 1 873 #define PCRF_AB_SLOT_PWR_CTL_PRST_WIDTH 1 874 #define PCRF_AB_SLOT_ATTN_BUT_PRST_LBN 0 875 #define PCRF_AB_SLOT_ATTN_BUT_PRST_WIDTH 1 876 877 878 /* 879 * PC_SLOT_CTL_REG(16bit): 880 * PCIe slot control register 881 */ 882 883 #define PCR_AB_SLOT_CTL_REG 0x00000078 884 /* falcona0,falconb0=pci_f0_config */ 885 886 #define PCRF_AB_SLOT_PWR_CTLR_CTL_LBN 10 887 #define PCRF_AB_SLOT_PWR_CTLR_CTL_WIDTH 1 888 #define PCRF_AB_SLOT_PWR_IND_CTL_LBN 8 889 #define PCRF_AB_SLOT_PWR_IND_CTL_WIDTH 2 890 #define PCRF_AB_SLOT_ATT_IND_CTL_LBN 6 891 #define PCRF_AB_SLOT_ATT_IND_CTL_WIDTH 2 892 #define PCRF_AB_SLOT_HP_INT_EN_LBN 5 893 #define PCRF_AB_SLOT_HP_INT_EN_WIDTH 1 894 #define PCRF_AB_SLOT_CMD_COMP_INT_EN_LBN 4 895 #define PCRF_AB_SLOT_CMD_COMP_INT_EN_WIDTH 1 896 #define PCRF_AB_SLOT_PRES_DET_CHG_EN_LBN 3 897 #define PCRF_AB_SLOT_PRES_DET_CHG_EN_WIDTH 1 898 #define PCRF_AB_SLOT_MRL_SENS_CHG_EN_LBN 2 899 #define PCRF_AB_SLOT_MRL_SENS_CHG_EN_WIDTH 1 900 #define PCRF_AB_SLOT_PWR_FLTDET_EN_LBN 1 901 #define PCRF_AB_SLOT_PWR_FLTDET_EN_WIDTH 1 902 #define PCRF_AB_SLOT_ATTN_BUT_EN_LBN 0 903 #define PCRF_AB_SLOT_ATTN_BUT_EN_WIDTH 1 904 905 906 /* 907 * PC_SLOT_STAT_REG(16bit): 908 * PCIe slot status register 909 */ 910 911 #define PCR_AB_SLOT_STAT_REG 0x0000007a 912 /* falcona0,falconb0=pci_f0_config */ 913 914 #define PCRF_AB_PRES_DET_ST_LBN 6 915 #define PCRF_AB_PRES_DET_ST_WIDTH 1 916 #define PCRF_AB_MRL_SENS_ST_LBN 5 917 #define PCRF_AB_MRL_SENS_ST_WIDTH 1 918 #define PCRF_AB_SLOT_PWR_IND_LBN 4 919 #define PCRF_AB_SLOT_PWR_IND_WIDTH 1 920 #define PCRF_AB_SLOT_ATTN_IND_LBN 3 921 #define PCRF_AB_SLOT_ATTN_IND_WIDTH 1 922 #define PCRF_AB_SLOT_MRL_SENS_LBN 2 923 #define PCRF_AB_SLOT_MRL_SENS_WIDTH 1 924 #define PCRF_AB_PWR_FLTDET_LBN 1 925 #define PCRF_AB_PWR_FLTDET_WIDTH 1 926 #define PCRF_AB_ATTN_BUTDET_LBN 0 927 #define PCRF_AB_ATTN_BUTDET_WIDTH 1 928 929 930 /* 931 * PC_MSIX_CAP_ID_REG(8bit): 932 * MSIX Capability ID 933 */ 934 935 #define PCR_BB_MSIX_CAP_ID_REG 0x00000090 936 /* falconb0=pci_f0_config */ 937 938 #define PCR_CZ_MSIX_CAP_ID_REG 0x000000b0 939 /* sienaa0,hunta0=pci_f0_config */ 940 941 #define PCRF_BZ_MSIX_CAP_ID_LBN 0 942 #define PCRF_BZ_MSIX_CAP_ID_WIDTH 8 943 944 945 /* 946 * PC_MSIX_NXT_PTR_REG(8bit): 947 * MSIX Capability Next Capability Ptr 948 */ 949 950 #define PCR_BB_MSIX_NXT_PTR_REG 0x00000091 951 /* falconb0=pci_f0_config */ 952 953 #define PCR_CZ_MSIX_NXT_PTR_REG 0x000000b1 954 /* sienaa0,hunta0=pci_f0_config */ 955 956 #define PCRF_BZ_MSIX_NXT_PTR_LBN 0 957 #define PCRF_BZ_MSIX_NXT_PTR_WIDTH 8 958 959 960 /* 961 * PC_MSIX_CTL_REG(16bit): 962 * MSIX control register 963 */ 964 965 #define PCR_BB_MSIX_CTL_REG 0x00000092 966 /* falconb0=pci_f0_config */ 967 968 #define PCR_CZ_MSIX_CTL_REG 0x000000b2 969 /* sienaa0,hunta0=pci_f0_config */ 970 971 #define PCRF_BZ_MSIX_EN_LBN 15 972 #define PCRF_BZ_MSIX_EN_WIDTH 1 973 #define PCRF_BZ_MSIX_FUNC_MASK_LBN 14 974 #define PCRF_BZ_MSIX_FUNC_MASK_WIDTH 1 975 #define PCRF_BZ_MSIX_TBL_SIZE_LBN 0 976 #define PCRF_BZ_MSIX_TBL_SIZE_WIDTH 11 977 978 979 /* 980 * PC_DEV_CAP2_REG(16bit): 981 * PCIe Device Capabilities 2 982 */ 983 984 #define PCR_CC_DEV_CAP2_REG 0x00000094 985 /* sienaa0=pci_f0_config */ 986 987 #define PCR_DZ_DEV_CAP2_REG 0x000000e4 988 /* hunta0=pci_f0_config */ 989 990 #define PCRF_CZ_CMPL_TIMEOUT_DIS_LBN 4 991 #define PCRF_CZ_CMPL_TIMEOUT_DIS_WIDTH 1 992 #define PCRF_CZ_CMPL_TIMEOUT_LBN 0 993 #define PCRF_CZ_CMPL_TIMEOUT_WIDTH 4 994 #define PCFE_CZ_CMPL_TIMEOUT_17000_TO_6400MS 14 995 #define PCFE_CZ_CMPL_TIMEOUT_4000_TO_1300MS 13 996 #define PCFE_CZ_CMPL_TIMEOUT_1000_TO_3500MS 10 997 #define PCFE_CZ_CMPL_TIMEOUT_260_TO_900MS 9 998 #define PCFE_CZ_CMPL_TIMEOUT_65_TO_210MS 6 999 #define PCFE_CZ_CMPL_TIMEOUT_16_TO_55MS 5 1000 #define PCFE_CZ_CMPL_TIMEOUT_1_TO_10MS 2 1001 #define PCFE_CZ_CMPL_TIMEOUT_50_TO_100US 1 1002 #define PCFE_CZ_CMPL_TIMEOUT_DEFAULT 0 1003 1004 1005 /* 1006 * PC_MSIX_TBL_BASE_REG(32bit): 1007 * MSIX Capability Vector Table Base 1008 */ 1009 1010 #define PCR_BB_MSIX_TBL_BASE_REG 0x00000094 1011 /* falconb0=pci_f0_config */ 1012 1013 #define PCR_CZ_MSIX_TBL_BASE_REG 0x000000b4 1014 /* sienaa0,hunta0=pci_f0_config */ 1015 1016 #define PCRF_BZ_MSIX_TBL_OFF_LBN 3 1017 #define PCRF_BZ_MSIX_TBL_OFF_WIDTH 29 1018 #define PCRF_BZ_MSIX_TBL_BIR_LBN 0 1019 #define PCRF_BZ_MSIX_TBL_BIR_WIDTH 3 1020 1021 1022 /* 1023 * PC_DEV_CTL2_REG(16bit): 1024 * PCIe Device Control 2 1025 */ 1026 1027 #define PCR_CC_DEV_CTL2_REG 0x00000098 1028 /* sienaa0=pci_f0_config */ 1029 1030 #define PCR_DZ_DEV_CTL2_REG 0x000000e8 1031 /* hunta0=pci_f0_config */ 1032 1033 #define PCRF_CZ_CMPL_TIMEOUT_DIS_CTL_LBN 4 1034 #define PCRF_CZ_CMPL_TIMEOUT_DIS_CTL_WIDTH 1 1035 #define PCRF_CZ_CMPL_TIMEOUT_CTL_LBN 0 1036 #define PCRF_CZ_CMPL_TIMEOUT_CTL_WIDTH 4 1037 1038 1039 /* 1040 * PC_MSIX_PBA_BASE_REG(32bit): 1041 * MSIX Capability PBA Base 1042 */ 1043 1044 #define PCR_BB_MSIX_PBA_BASE_REG 0x00000098 1045 /* falconb0=pci_f0_config */ 1046 1047 #define PCR_CZ_MSIX_PBA_BASE_REG 0x000000b8 1048 /* sienaa0,hunta0=pci_f0_config */ 1049 1050 #define PCRF_BZ_MSIX_PBA_OFF_LBN 3 1051 #define PCRF_BZ_MSIX_PBA_OFF_WIDTH 29 1052 #define PCRF_BZ_MSIX_PBA_BIR_LBN 0 1053 #define PCRF_BZ_MSIX_PBA_BIR_WIDTH 3 1054 1055 1056 /* 1057 * PC_LNK_CTL2_REG(16bit): 1058 * PCIe Link Control 2 1059 */ 1060 1061 #define PCR_CC_LNK_CTL2_REG 0x000000a0 1062 /* sienaa0=pci_f0_config */ 1063 1064 #define PCR_DZ_LNK_CTL2_REG 0x000000f0 1065 /* hunta0=pci_f0_config */ 1066 1067 #define PCRF_CZ_POLLING_DEEMPH_LVL_LBN 12 1068 #define PCRF_CZ_POLLING_DEEMPH_LVL_WIDTH 1 1069 #define PCRF_CZ_COMPLIANCE_SOS_CTL_LBN 11 1070 #define PCRF_CZ_COMPLIANCE_SOS_CTL_WIDTH 1 1071 #define PCRF_CZ_ENTER_MODIFIED_COMPLIANCE_CTL_LBN 10 1072 #define PCRF_CZ_ENTER_MODIFIED_COMPLIANCE_CTL_WIDTH 1 1073 #define PCRF_CZ_TRANSMIT_MARGIN_LBN 7 1074 #define PCRF_CZ_TRANSMIT_MARGIN_WIDTH 3 1075 #define PCRF_CZ_SELECT_DEEMPH_LBN 6 1076 #define PCRF_CZ_SELECT_DEEMPH_WIDTH 1 1077 #define PCRF_CZ_HW_AUTONOMOUS_SPEED_DIS_LBN 5 1078 #define PCRF_CZ_HW_AUTONOMOUS_SPEED_DIS_WIDTH 1 1079 #define PCRF_CZ_ENTER_COMPLIANCE_CTL_LBN 4 1080 #define PCRF_CZ_ENTER_COMPLIANCE_CTL_WIDTH 1 1081 #define PCRF_CZ_TGT_LNK_SPEED_CTL_LBN 0 1082 #define PCRF_CZ_TGT_LNK_SPEED_CTL_WIDTH 4 1083 1084 1085 /* 1086 * PC_LNK_STAT2_REG(16bit): 1087 * PCIe Link Status 2 1088 */ 1089 1090 #define PCR_CC_LNK_STAT2_REG 0x000000a2 1091 /* sienaa0=pci_f0_config */ 1092 1093 #define PCR_DZ_LNK_STAT2_REG 0x000000f2 1094 /* hunta0=pci_f0_config */ 1095 1096 #define PCRF_CZ_CURRENT_DEEMPH_LBN 0 1097 #define PCRF_CZ_CURRENT_DEEMPH_WIDTH 1 1098 1099 1100 /* 1101 * PC_VPD_CAP_ID_REG(8bit): 1102 * VPD data register 1103 */ 1104 1105 #define PCR_AB_VPD_CAP_ID_REG 0x000000b0 1106 /* falcona0,falconb0=pci_f0_config */ 1107 1108 #define PCRF_AB_VPD_CAP_ID_LBN 0 1109 #define PCRF_AB_VPD_CAP_ID_WIDTH 8 1110 1111 1112 /* 1113 * PC_VPD_NXT_PTR_REG(8bit): 1114 * VPD next item pointer 1115 */ 1116 1117 #define PCR_AB_VPD_NXT_PTR_REG 0x000000b1 1118 /* falcona0,falconb0=pci_f0_config */ 1119 1120 #define PCRF_AB_VPD_NXT_PTR_LBN 0 1121 #define PCRF_AB_VPD_NXT_PTR_WIDTH 8 1122 1123 1124 /* 1125 * PC_VPD_ADDR_REG(16bit): 1126 * VPD address register 1127 */ 1128 1129 #define PCR_AB_VPD_ADDR_REG 0x000000b2 1130 /* falcona0,falconb0=pci_f0_config */ 1131 1132 #define PCRF_AB_VPD_FLAG_LBN 15 1133 #define PCRF_AB_VPD_FLAG_WIDTH 1 1134 #define PCRF_AB_VPD_ADDR_LBN 0 1135 #define PCRF_AB_VPD_ADDR_WIDTH 15 1136 1137 1138 /* 1139 * PC_AER_CAP_HDR_REG(32bit): 1140 * AER capability header register 1141 */ 1142 1143 #define PCR_AZ_AER_CAP_HDR_REG 0x00000100 1144 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 1145 1146 #define PCRF_AZ_AERCAPHDR_NXT_PTR_LBN 20 1147 #define PCRF_AZ_AERCAPHDR_NXT_PTR_WIDTH 12 1148 #define PCRF_AZ_AERCAPHDR_VER_LBN 16 1149 #define PCRF_AZ_AERCAPHDR_VER_WIDTH 4 1150 #define PCRF_AZ_AERCAPHDR_ID_LBN 0 1151 #define PCRF_AZ_AERCAPHDR_ID_WIDTH 16 1152 1153 1154 /* 1155 * PC_AER_UNCORR_ERR_STAT_REG(32bit): 1156 * AER Uncorrectable error status register 1157 */ 1158 1159 #define PCR_AZ_AER_UNCORR_ERR_STAT_REG 0x00000104 1160 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 1161 1162 #define PCRF_AZ_UNSUPT_REQ_ERR_STAT_LBN 20 1163 #define PCRF_AZ_UNSUPT_REQ_ERR_STAT_WIDTH 1 1164 #define PCRF_AZ_ECRC_ERR_STAT_LBN 19 1165 #define PCRF_AZ_ECRC_ERR_STAT_WIDTH 1 1166 #define PCRF_AZ_MALF_TLP_STAT_LBN 18 1167 #define PCRF_AZ_MALF_TLP_STAT_WIDTH 1 1168 #define PCRF_AZ_RX_OVF_STAT_LBN 17 1169 #define PCRF_AZ_RX_OVF_STAT_WIDTH 1 1170 #define PCRF_AZ_UNEXP_COMP_STAT_LBN 16 1171 #define PCRF_AZ_UNEXP_COMP_STAT_WIDTH 1 1172 #define PCRF_AZ_COMP_ABRT_STAT_LBN 15 1173 #define PCRF_AZ_COMP_ABRT_STAT_WIDTH 1 1174 #define PCRF_AZ_COMP_TIMEOUT_STAT_LBN 14 1175 #define PCRF_AZ_COMP_TIMEOUT_STAT_WIDTH 1 1176 #define PCRF_AZ_FC_PROTO_ERR_STAT_LBN 13 1177 #define PCRF_AZ_FC_PROTO_ERR_STAT_WIDTH 1 1178 #define PCRF_AZ_PSON_TLP_STAT_LBN 12 1179 #define PCRF_AZ_PSON_TLP_STAT_WIDTH 1 1180 #define PCRF_AZ_DL_PROTO_ERR_STAT_LBN 4 1181 #define PCRF_AZ_DL_PROTO_ERR_STAT_WIDTH 1 1182 #define PCRF_AB_TRAIN_ERR_STAT_LBN 0 1183 #define PCRF_AB_TRAIN_ERR_STAT_WIDTH 1 1184 1185 1186 /* 1187 * PC_AER_UNCORR_ERR_MASK_REG(32bit): 1188 * AER Uncorrectable error mask register 1189 */ 1190 1191 #define PCR_AZ_AER_UNCORR_ERR_MASK_REG 0x00000108 1192 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 1193 1194 #define PCRF_AZ_UNSUPT_REQ_ERR_MASK_LBN 20 1195 #define PCRF_AZ_UNSUPT_REQ_ERR_MASK_WIDTH 1 1196 #define PCRF_AZ_ECRC_ERR_MASK_LBN 19 1197 #define PCRF_AZ_ECRC_ERR_MASK_WIDTH 1 1198 #define PCRF_AZ_MALF_TLP_MASK_LBN 18 1199 #define PCRF_AZ_MALF_TLP_MASK_WIDTH 1 1200 #define PCRF_AZ_RX_OVF_MASK_LBN 17 1201 #define PCRF_AZ_RX_OVF_MASK_WIDTH 1 1202 #define PCRF_AZ_UNEXP_COMP_MASK_LBN 16 1203 #define PCRF_AZ_UNEXP_COMP_MASK_WIDTH 1 1204 #define PCRF_AZ_COMP_ABRT_MASK_LBN 15 1205 #define PCRF_AZ_COMP_ABRT_MASK_WIDTH 1 1206 #define PCRF_AZ_COMP_TIMEOUT_MASK_LBN 14 1207 #define PCRF_AZ_COMP_TIMEOUT_MASK_WIDTH 1 1208 #define PCRF_AZ_FC_PROTO_ERR_MASK_LBN 13 1209 #define PCRF_AZ_FC_PROTO_ERR_MASK_WIDTH 1 1210 #define PCRF_AZ_PSON_TLP_MASK_LBN 12 1211 #define PCRF_AZ_PSON_TLP_MASK_WIDTH 1 1212 #define PCRF_AZ_DL_PROTO_ERR_MASK_LBN 4 1213 #define PCRF_AZ_DL_PROTO_ERR_MASK_WIDTH 1 1214 #define PCRF_AB_TRAIN_ERR_MASK_LBN 0 1215 #define PCRF_AB_TRAIN_ERR_MASK_WIDTH 1 1216 1217 1218 /* 1219 * PC_AER_UNCORR_ERR_SEV_REG(32bit): 1220 * AER Uncorrectable error severity register 1221 */ 1222 1223 #define PCR_AZ_AER_UNCORR_ERR_SEV_REG 0x0000010c 1224 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 1225 1226 #define PCRF_AZ_UNSUPT_REQ_ERR_SEV_LBN 20 1227 #define PCRF_AZ_UNSUPT_REQ_ERR_SEV_WIDTH 1 1228 #define PCRF_AZ_ECRC_ERR_SEV_LBN 19 1229 #define PCRF_AZ_ECRC_ERR_SEV_WIDTH 1 1230 #define PCRF_AZ_MALF_TLP_SEV_LBN 18 1231 #define PCRF_AZ_MALF_TLP_SEV_WIDTH 1 1232 #define PCRF_AZ_RX_OVF_SEV_LBN 17 1233 #define PCRF_AZ_RX_OVF_SEV_WIDTH 1 1234 #define PCRF_AZ_UNEXP_COMP_SEV_LBN 16 1235 #define PCRF_AZ_UNEXP_COMP_SEV_WIDTH 1 1236 #define PCRF_AZ_COMP_ABRT_SEV_LBN 15 1237 #define PCRF_AZ_COMP_ABRT_SEV_WIDTH 1 1238 #define PCRF_AZ_COMP_TIMEOUT_SEV_LBN 14 1239 #define PCRF_AZ_COMP_TIMEOUT_SEV_WIDTH 1 1240 #define PCRF_AZ_FC_PROTO_ERR_SEV_LBN 13 1241 #define PCRF_AZ_FC_PROTO_ERR_SEV_WIDTH 1 1242 #define PCRF_AZ_PSON_TLP_SEV_LBN 12 1243 #define PCRF_AZ_PSON_TLP_SEV_WIDTH 1 1244 #define PCRF_AZ_DL_PROTO_ERR_SEV_LBN 4 1245 #define PCRF_AZ_DL_PROTO_ERR_SEV_WIDTH 1 1246 #define PCRF_AB_TRAIN_ERR_SEV_LBN 0 1247 #define PCRF_AB_TRAIN_ERR_SEV_WIDTH 1 1248 1249 1250 /* 1251 * PC_AER_CORR_ERR_STAT_REG(32bit): 1252 * AER Correctable error status register 1253 */ 1254 1255 #define PCR_AZ_AER_CORR_ERR_STAT_REG 0x00000110 1256 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 1257 1258 #define PCRF_CZ_ADVSY_NON_FATAL_STAT_LBN 13 1259 #define PCRF_CZ_ADVSY_NON_FATAL_STAT_WIDTH 1 1260 #define PCRF_AZ_RPLY_TMR_TOUT_STAT_LBN 12 1261 #define PCRF_AZ_RPLY_TMR_TOUT_STAT_WIDTH 1 1262 #define PCRF_AZ_RPLAY_NUM_RO_STAT_LBN 8 1263 #define PCRF_AZ_RPLAY_NUM_RO_STAT_WIDTH 1 1264 #define PCRF_AZ_BAD_DLLP_STAT_LBN 7 1265 #define PCRF_AZ_BAD_DLLP_STAT_WIDTH 1 1266 #define PCRF_AZ_BAD_TLP_STAT_LBN 6 1267 #define PCRF_AZ_BAD_TLP_STAT_WIDTH 1 1268 #define PCRF_AZ_RX_ERR_STAT_LBN 0 1269 #define PCRF_AZ_RX_ERR_STAT_WIDTH 1 1270 1271 1272 /* 1273 * PC_AER_CORR_ERR_MASK_REG(32bit): 1274 * AER Correctable error status register 1275 */ 1276 1277 #define PCR_AZ_AER_CORR_ERR_MASK_REG 0x00000114 1278 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 1279 1280 #define PCRF_CZ_ADVSY_NON_FATAL_MASK_LBN 13 1281 #define PCRF_CZ_ADVSY_NON_FATAL_MASK_WIDTH 1 1282 #define PCRF_AZ_RPLY_TMR_TOUT_MASK_LBN 12 1283 #define PCRF_AZ_RPLY_TMR_TOUT_MASK_WIDTH 1 1284 #define PCRF_AZ_RPLAY_NUM_RO_MASK_LBN 8 1285 #define PCRF_AZ_RPLAY_NUM_RO_MASK_WIDTH 1 1286 #define PCRF_AZ_BAD_DLLP_MASK_LBN 7 1287 #define PCRF_AZ_BAD_DLLP_MASK_WIDTH 1 1288 #define PCRF_AZ_BAD_TLP_MASK_LBN 6 1289 #define PCRF_AZ_BAD_TLP_MASK_WIDTH 1 1290 #define PCRF_AZ_RX_ERR_MASK_LBN 0 1291 #define PCRF_AZ_RX_ERR_MASK_WIDTH 1 1292 1293 1294 /* 1295 * PC_AER_CAP_CTL_REG(32bit): 1296 * AER capability and control register 1297 */ 1298 1299 #define PCR_AZ_AER_CAP_CTL_REG 0x00000118 1300 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 1301 1302 #define PCRF_AZ_ECRC_CHK_EN_LBN 8 1303 #define PCRF_AZ_ECRC_CHK_EN_WIDTH 1 1304 #define PCRF_AZ_ECRC_CHK_CAP_LBN 7 1305 #define PCRF_AZ_ECRC_CHK_CAP_WIDTH 1 1306 #define PCRF_AZ_ECRC_GEN_EN_LBN 6 1307 #define PCRF_AZ_ECRC_GEN_EN_WIDTH 1 1308 #define PCRF_AZ_ECRC_GEN_CAP_LBN 5 1309 #define PCRF_AZ_ECRC_GEN_CAP_WIDTH 1 1310 #define PCRF_AZ_1ST_ERR_PTR_LBN 0 1311 #define PCRF_AZ_1ST_ERR_PTR_WIDTH 5 1312 1313 1314 /* 1315 * PC_AER_HDR_LOG_REG(128bit): 1316 * AER Header log register 1317 */ 1318 1319 #define PCR_AZ_AER_HDR_LOG_REG 0x0000011c 1320 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 1321 1322 #define PCRF_AZ_HDR_LOG_LBN 0 1323 #define PCRF_AZ_HDR_LOG_WIDTH 128 1324 1325 1326 /* 1327 * PC_DEVSN_CAP_HDR_REG(32bit): 1328 * Device serial number capability header register 1329 */ 1330 1331 #define PCR_DZ_DEVSN_CAP_HDR_REG 0x00000130 1332 /* hunta0=pci_f0_config */ 1333 1334 #define PCR_CC_DEVSN_CAP_HDR_REG 0x00000140 1335 /* sienaa0=pci_f0_config */ 1336 1337 #define PCRF_CZ_DEVSNCAPHDR_NXT_PTR_LBN 20 1338 #define PCRF_CZ_DEVSNCAPHDR_NXT_PTR_WIDTH 12 1339 #define PCRF_CZ_DEVSNCAPHDR_VER_LBN 16 1340 #define PCRF_CZ_DEVSNCAPHDR_VER_WIDTH 4 1341 #define PCRF_CZ_DEVSNCAPHDR_ID_LBN 0 1342 #define PCRF_CZ_DEVSNCAPHDR_ID_WIDTH 16 1343 1344 1345 /* 1346 * PC_DEVSN_DWORD0_REG(32bit): 1347 * Device serial number DWORD0 1348 */ 1349 1350 #define PCR_DZ_DEVSN_DWORD0_REG 0x00000134 1351 /* hunta0=pci_f0_config */ 1352 1353 #define PCR_CC_DEVSN_DWORD0_REG 0x00000144 1354 /* sienaa0=pci_f0_config */ 1355 1356 #define PCRF_CZ_DEVSN_DWORD0_LBN 0 1357 #define PCRF_CZ_DEVSN_DWORD0_WIDTH 32 1358 1359 1360 /* 1361 * PC_DEVSN_DWORD1_REG(32bit): 1362 * Device serial number DWORD0 1363 */ 1364 1365 #define PCR_DZ_DEVSN_DWORD1_REG 0x00000138 1366 /* hunta0=pci_f0_config */ 1367 1368 #define PCR_CC_DEVSN_DWORD1_REG 0x00000148 1369 /* sienaa0=pci_f0_config */ 1370 1371 #define PCRF_CZ_DEVSN_DWORD1_LBN 0 1372 #define PCRF_CZ_DEVSN_DWORD1_WIDTH 32 1373 1374 1375 /* 1376 * PC_ARI_CAP_HDR_REG(32bit): 1377 * ARI capability header register 1378 */ 1379 1380 #define PCR_DZ_ARI_CAP_HDR_REG 0x00000140 1381 /* hunta0=pci_f0_config */ 1382 1383 #define PCR_CC_ARI_CAP_HDR_REG 0x00000150 1384 /* sienaa0=pci_f0_config */ 1385 1386 #define PCRF_CZ_ARICAPHDR_NXT_PTR_LBN 20 1387 #define PCRF_CZ_ARICAPHDR_NXT_PTR_WIDTH 12 1388 #define PCRF_CZ_ARICAPHDR_VER_LBN 16 1389 #define PCRF_CZ_ARICAPHDR_VER_WIDTH 4 1390 #define PCRF_CZ_ARICAPHDR_ID_LBN 0 1391 #define PCRF_CZ_ARICAPHDR_ID_WIDTH 16 1392 1393 1394 /* 1395 * PC_ARI_CAP_REG(16bit): 1396 * ARI Capabilities 1397 */ 1398 1399 #define PCR_DZ_ARI_CAP_REG 0x00000144 1400 /* hunta0=pci_f0_config */ 1401 1402 #define PCR_CC_ARI_CAP_REG 0x00000154 1403 /* sienaa0=pci_f0_config */ 1404 1405 #define PCRF_CZ_ARI_NXT_FN_NUM_LBN 8 1406 #define PCRF_CZ_ARI_NXT_FN_NUM_WIDTH 8 1407 #define PCRF_CZ_ARI_ACS_FNGRP_CAP_LBN 1 1408 #define PCRF_CZ_ARI_ACS_FNGRP_CAP_WIDTH 1 1409 #define PCRF_CZ_ARI_MFVC_FNGRP_CAP_LBN 0 1410 #define PCRF_CZ_ARI_MFVC_FNGRP_CAP_WIDTH 1 1411 1412 1413 /* 1414 * PC_ARI_CTL_REG(16bit): 1415 * ARI Control 1416 */ 1417 1418 #define PCR_DZ_ARI_CTL_REG 0x00000146 1419 /* hunta0=pci_f0_config */ 1420 1421 #define PCR_CC_ARI_CTL_REG 0x00000156 1422 /* sienaa0=pci_f0_config */ 1423 1424 #define PCRF_CZ_ARI_FN_GRP_LBN 4 1425 #define PCRF_CZ_ARI_FN_GRP_WIDTH 3 1426 #define PCRF_CZ_ARI_ACS_FNGRP_EN_LBN 1 1427 #define PCRF_CZ_ARI_ACS_FNGRP_EN_WIDTH 1 1428 #define PCRF_CZ_ARI_MFVC_FNGRP_EN_LBN 0 1429 #define PCRF_CZ_ARI_MFVC_FNGRP_EN_WIDTH 1 1430 1431 1432 /* 1433 * PC_SRIOV_CAP_HDR_REG(32bit): 1434 * SRIOV capability header register 1435 */ 1436 1437 #define PCR_CC_SRIOV_CAP_HDR_REG 0x00000160 1438 /* sienaa0=pci_f0_config */ 1439 1440 #define PCR_DZ_SRIOV_CAP_HDR_REG 0x00000200 1441 /* hunta0=pci_f0_config */ 1442 1443 #define PCRF_CZ_SRIOVCAPHDR_NXT_PTR_LBN 20 1444 #define PCRF_CZ_SRIOVCAPHDR_NXT_PTR_WIDTH 12 1445 #define PCRF_CZ_SRIOVCAPHDR_VER_LBN 16 1446 #define PCRF_CZ_SRIOVCAPHDR_VER_WIDTH 4 1447 #define PCRF_CZ_SRIOVCAPHDR_ID_LBN 0 1448 #define PCRF_CZ_SRIOVCAPHDR_ID_WIDTH 16 1449 1450 1451 /* 1452 * PC_SRIOV_CAP_REG(32bit): 1453 * SRIOV Capabilities 1454 */ 1455 1456 #define PCR_CC_SRIOV_CAP_REG 0x00000164 1457 /* sienaa0=pci_f0_config */ 1458 1459 #define PCR_DZ_SRIOV_CAP_REG 0x00000204 1460 /* hunta0=pci_f0_config */ 1461 1462 #define PCRF_CZ_VF_MIGR_INT_MSG_NUM_LBN 21 1463 #define PCRF_CZ_VF_MIGR_INT_MSG_NUM_WIDTH 11 1464 #define PCRF_CZ_VF_MIGR_CAP_LBN 0 1465 #define PCRF_CZ_VF_MIGR_CAP_WIDTH 1 1466 1467 1468 /* 1469 * PC_SRIOV_CTL_REG(16bit): 1470 * SRIOV Control 1471 */ 1472 1473 #define PCR_CC_SRIOV_CTL_REG 0x00000168 1474 /* sienaa0=pci_f0_config */ 1475 1476 #define PCR_DZ_SRIOV_CTL_REG 0x00000208 1477 /* hunta0=pci_f0_config */ 1478 1479 #define PCRF_CZ_VF_ARI_CAP_HRCHY_LBN 4 1480 #define PCRF_CZ_VF_ARI_CAP_HRCHY_WIDTH 1 1481 #define PCRF_CZ_VF_MSE_LBN 3 1482 #define PCRF_CZ_VF_MSE_WIDTH 1 1483 #define PCRF_CZ_VF_MIGR_INT_EN_LBN 2 1484 #define PCRF_CZ_VF_MIGR_INT_EN_WIDTH 1 1485 #define PCRF_CZ_VF_MIGR_EN_LBN 1 1486 #define PCRF_CZ_VF_MIGR_EN_WIDTH 1 1487 #define PCRF_CZ_VF_EN_LBN 0 1488 #define PCRF_CZ_VF_EN_WIDTH 1 1489 1490 1491 /* 1492 * PC_SRIOV_STAT_REG(16bit): 1493 * SRIOV Status 1494 */ 1495 1496 #define PCR_CC_SRIOV_STAT_REG 0x0000016a 1497 /* sienaa0=pci_f0_config */ 1498 1499 #define PCR_DZ_SRIOV_STAT_REG 0x0000020a 1500 /* hunta0=pci_f0_config */ 1501 1502 #define PCRF_CZ_VF_MIGR_STAT_LBN 0 1503 #define PCRF_CZ_VF_MIGR_STAT_WIDTH 1 1504 1505 1506 /* 1507 * PC_SRIOV_INITIALVFS_REG(16bit): 1508 * SRIOV Initial VFs 1509 */ 1510 1511 #define PCR_CC_SRIOV_INITIALVFS_REG 0x0000016c 1512 /* sienaa0=pci_f0_config */ 1513 1514 #define PCR_DZ_SRIOV_INITIALVFS_REG 0x0000020c 1515 /* hunta0=pci_f0_config */ 1516 1517 #define PCRF_CZ_VF_INITIALVFS_LBN 0 1518 #define PCRF_CZ_VF_INITIALVFS_WIDTH 16 1519 1520 1521 /* 1522 * PC_SRIOV_TOTALVFS_REG(10bit): 1523 * SRIOV Total VFs 1524 */ 1525 1526 #define PCR_CC_SRIOV_TOTALVFS_REG 0x0000016e 1527 /* sienaa0=pci_f0_config */ 1528 1529 #define PCR_DZ_SRIOV_TOTALVFS_REG 0x0000020e 1530 /* hunta0=pci_f0_config */ 1531 1532 #define PCRF_CZ_VF_TOTALVFS_LBN 0 1533 #define PCRF_CZ_VF_TOTALVFS_WIDTH 16 1534 1535 1536 /* 1537 * PC_SRIOV_NUMVFS_REG(16bit): 1538 * SRIOV Number of VFs 1539 */ 1540 1541 #define PCR_CC_SRIOV_NUMVFS_REG 0x00000170 1542 /* sienaa0=pci_f0_config */ 1543 1544 #define PCR_DZ_SRIOV_NUMVFS_REG 0x00000210 1545 /* hunta0=pci_f0_config */ 1546 1547 #define PCRF_CZ_VF_NUMVFS_LBN 0 1548 #define PCRF_CZ_VF_NUMVFS_WIDTH 16 1549 1550 1551 /* 1552 * PC_SRIOV_FN_DPND_LNK_REG(16bit): 1553 * SRIOV Function dependency link 1554 */ 1555 1556 #define PCR_CC_SRIOV_FN_DPND_LNK_REG 0x00000172 1557 /* sienaa0=pci_f0_config */ 1558 1559 #define PCR_DZ_SRIOV_FN_DPND_LNK_REG 0x00000212 1560 /* hunta0=pci_f0_config */ 1561 1562 #define PCRF_CZ_SRIOV_FN_DPND_LNK_LBN 0 1563 #define PCRF_CZ_SRIOV_FN_DPND_LNK_WIDTH 8 1564 1565 1566 /* 1567 * PC_SRIOV_1STVF_OFFSET_REG(16bit): 1568 * SRIOV First VF Offset 1569 */ 1570 1571 #define PCR_CC_SRIOV_1STVF_OFFSET_REG 0x00000174 1572 /* sienaa0=pci_f0_config */ 1573 1574 #define PCR_DZ_SRIOV_1STVF_OFFSET_REG 0x00000214 1575 /* hunta0=pci_f0_config */ 1576 1577 #define PCRF_CZ_VF_1STVF_OFFSET_LBN 0 1578 #define PCRF_CZ_VF_1STVF_OFFSET_WIDTH 16 1579 1580 1581 /* 1582 * PC_SRIOV_VFSTRIDE_REG(16bit): 1583 * SRIOV VF Stride 1584 */ 1585 1586 #define PCR_CC_SRIOV_VFSTRIDE_REG 0x00000176 1587 /* sienaa0=pci_f0_config */ 1588 1589 #define PCR_DZ_SRIOV_VFSTRIDE_REG 0x00000216 1590 /* hunta0=pci_f0_config */ 1591 1592 #define PCRF_CZ_VF_VFSTRIDE_LBN 0 1593 #define PCRF_CZ_VF_VFSTRIDE_WIDTH 16 1594 1595 1596 /* 1597 * PC_SRIOV_DEVID_REG(16bit): 1598 * SRIOV VF Device ID 1599 */ 1600 1601 #define PCR_CC_SRIOV_DEVID_REG 0x0000017a 1602 /* sienaa0=pci_f0_config */ 1603 1604 #define PCR_DZ_SRIOV_DEVID_REG 0x0000021a 1605 /* hunta0=pci_f0_config */ 1606 1607 #define PCRF_CZ_VF_DEVID_LBN 0 1608 #define PCRF_CZ_VF_DEVID_WIDTH 16 1609 1610 1611 /* 1612 * PC_SRIOV_SUP_PAGESZ_REG(16bit): 1613 * SRIOV Supported Page Sizes 1614 */ 1615 1616 #define PCR_CC_SRIOV_SUP_PAGESZ_REG 0x0000017c 1617 /* sienaa0=pci_f0_config */ 1618 1619 #define PCR_DZ_SRIOV_SUP_PAGESZ_REG 0x0000021c 1620 /* hunta0=pci_f0_config */ 1621 1622 #define PCRF_CZ_VF_SUP_PAGESZ_LBN 0 1623 #define PCRF_CZ_VF_SUP_PAGESZ_WIDTH 16 1624 1625 1626 /* 1627 * PC_SRIOV_SYS_PAGESZ_REG(32bit): 1628 * SRIOV System Page Size 1629 */ 1630 1631 #define PCR_CC_SRIOV_SYS_PAGESZ_REG 0x00000180 1632 /* sienaa0=pci_f0_config */ 1633 1634 #define PCR_DZ_SRIOV_SYS_PAGESZ_REG 0x00000220 1635 /* hunta0=pci_f0_config */ 1636 1637 #define PCRF_CZ_VF_SYS_PAGESZ_LBN 0 1638 #define PCRF_CZ_VF_SYS_PAGESZ_WIDTH 16 1639 1640 1641 /* 1642 * PC_SRIOV_BAR0_REG(32bit): 1643 * SRIOV VF Bar0 1644 */ 1645 1646 #define PCR_CC_SRIOV_BAR0_REG 0x00000184 1647 /* sienaa0=pci_f0_config */ 1648 1649 #define PCR_DZ_SRIOV_BAR0_REG 0x00000224 1650 /* hunta0=pci_f0_config */ 1651 1652 #define PCRF_CC_VF_BAR_ADDRESS_LBN 0 1653 #define PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 1654 #define PCRF_DZ_VF_BAR0_ADDRESS_LBN 0 1655 #define PCRF_DZ_VF_BAR0_ADDRESS_WIDTH 32 1656 1657 1658 /* 1659 * PC_SRIOV_BAR1_REG(32bit): 1660 * SRIOV Bar1 1661 */ 1662 1663 #define PCR_CC_SRIOV_BAR1_REG 0x00000188 1664 /* sienaa0=pci_f0_config */ 1665 1666 #define PCR_DZ_SRIOV_BAR1_REG 0x00000228 1667 /* hunta0=pci_f0_config */ 1668 1669 /* defined as PCRF_CC_VF_BAR_ADDRESS_LBN 0; */ 1670 /* defined as PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 */ 1671 #define PCRF_DZ_VF_BAR1_ADDRESS_LBN 0 1672 #define PCRF_DZ_VF_BAR1_ADDRESS_WIDTH 32 1673 1674 1675 /* 1676 * PC_SRIOV_BAR2_REG(32bit): 1677 * SRIOV Bar2 1678 */ 1679 1680 #define PCR_CC_SRIOV_BAR2_REG 0x0000018c 1681 /* sienaa0=pci_f0_config */ 1682 1683 #define PCR_DZ_SRIOV_BAR2_REG 0x0000022c 1684 /* hunta0=pci_f0_config */ 1685 1686 /* defined as PCRF_CC_VF_BAR_ADDRESS_LBN 0; */ 1687 /* defined as PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 */ 1688 #define PCRF_DZ_VF_BAR2_ADDRESS_LBN 0 1689 #define PCRF_DZ_VF_BAR2_ADDRESS_WIDTH 32 1690 1691 1692 /* 1693 * PC_SRIOV_BAR3_REG(32bit): 1694 * SRIOV Bar3 1695 */ 1696 1697 #define PCR_CC_SRIOV_BAR3_REG 0x00000190 1698 /* sienaa0=pci_f0_config */ 1699 1700 #define PCR_DZ_SRIOV_BAR3_REG 0x00000230 1701 /* hunta0=pci_f0_config */ 1702 1703 /* defined as PCRF_CC_VF_BAR_ADDRESS_LBN 0; */ 1704 /* defined as PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 */ 1705 #define PCRF_DZ_VF_BAR3_ADDRESS_LBN 0 1706 #define PCRF_DZ_VF_BAR3_ADDRESS_WIDTH 32 1707 1708 1709 /* 1710 * PC_SRIOV_BAR4_REG(32bit): 1711 * SRIOV Bar4 1712 */ 1713 1714 #define PCR_CC_SRIOV_BAR4_REG 0x00000194 1715 /* sienaa0=pci_f0_config */ 1716 1717 #define PCR_DZ_SRIOV_BAR4_REG 0x00000234 1718 /* hunta0=pci_f0_config */ 1719 1720 /* defined as PCRF_CC_VF_BAR_ADDRESS_LBN 0; */ 1721 /* defined as PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 */ 1722 #define PCRF_DZ_VF_BAR4_ADDRESS_LBN 0 1723 #define PCRF_DZ_VF_BAR4_ADDRESS_WIDTH 32 1724 1725 1726 /* 1727 * PC_SRIOV_BAR5_REG(32bit): 1728 * SRIOV Bar5 1729 */ 1730 1731 #define PCR_CC_SRIOV_BAR5_REG 0x00000198 1732 /* sienaa0=pci_f0_config */ 1733 1734 #define PCR_DZ_SRIOV_BAR5_REG 0x00000238 1735 /* hunta0=pci_f0_config */ 1736 1737 /* defined as PCRF_CC_VF_BAR_ADDRESS_LBN 0; */ 1738 /* defined as PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 */ 1739 #define PCRF_DZ_VF_BAR5_ADDRESS_LBN 0 1740 #define PCRF_DZ_VF_BAR5_ADDRESS_WIDTH 32 1741 1742 1743 /* 1744 * PC_SRIOV_MIBR_SARRAY_OFFSET_REG(32bit): 1745 * SRIOV VF Migration State Array Offset 1746 */ 1747 1748 #define PCR_CC_SRIOV_MIBR_SARRAY_OFFSET_REG 0x0000019c 1749 /* sienaa0=pci_f0_config */ 1750 1751 #define PCR_DZ_SRIOV_MIBR_SARRAY_OFFSET_REG 0x0000023c 1752 /* hunta0=pci_f0_config */ 1753 1754 #define PCRF_CZ_VF_MIGR_OFFSET_LBN 3 1755 #define PCRF_CZ_VF_MIGR_OFFSET_WIDTH 29 1756 #define PCRF_CZ_VF_MIGR_BIR_LBN 0 1757 #define PCRF_CZ_VF_MIGR_BIR_WIDTH 3 1758 1759 1760 /* 1761 * PC_LTR_CAP_HDR_REG(32bit): 1762 * Latency Tolerance Reporting Cap Header Reg 1763 */ 1764 1765 #define PCR_DZ_LTR_CAP_HDR_REG 0x00000240 1766 /* hunta0=pci_f0_config */ 1767 1768 #define PCRF_DZ_LTR_NXT_PTR_LBN 20 1769 #define PCRF_DZ_LTR_NXT_PTR_WIDTH 12 1770 #define PCRF_DZ_LTR_VERSION_LBN 16 1771 #define PCRF_DZ_LTR_VERSION_WIDTH 4 1772 #define PCRF_DZ_LTR_EXT_CAP_ID_LBN 0 1773 #define PCRF_DZ_LTR_EXT_CAP_ID_WIDTH 16 1774 1775 1776 /* 1777 * PC_LTR_MAX_SNOOP_REG(32bit): 1778 * LTR Maximum Snoop/No Snoop Register 1779 */ 1780 1781 #define PCR_DZ_LTR_MAX_SNOOP_REG 0x00000244 1782 /* hunta0=pci_f0_config */ 1783 1784 #define PCRF_DZ_LTR_MAX_NOSNOOP_SCALE_LBN 26 1785 #define PCRF_DZ_LTR_MAX_NOSNOOP_SCALE_WIDTH 3 1786 #define PCRF_DZ_LTR_MAX_NOSNOOP_LAT_LBN 16 1787 #define PCRF_DZ_LTR_MAX_NOSNOOP_LAT_WIDTH 10 1788 #define PCRF_DZ_LTR_MAX_SNOOP_SCALE_LBN 10 1789 #define PCRF_DZ_LTR_MAX_SNOOP_SCALE_WIDTH 3 1790 #define PCRF_DZ_LTR_MAX_SNOOP_LAT_LBN 0 1791 #define PCRF_DZ_LTR_MAX_SNOOP_LAT_WIDTH 10 1792 1793 1794 /* 1795 * PC_TPH_CAP_HDR_REG(32bit): 1796 * TPH Capability Header Register 1797 */ 1798 1799 #define PCR_DZ_TPH_CAP_HDR_REG 0x00000274 1800 /* hunta0=pci_f0_config */ 1801 1802 #define PCRF_DZ_TPH_NXT_PTR_LBN 20 1803 #define PCRF_DZ_TPH_NXT_PTR_WIDTH 12 1804 #define PCRF_DZ_TPH_VERSION_LBN 16 1805 #define PCRF_DZ_TPH_VERSION_WIDTH 4 1806 #define PCRF_DZ_TPH_EXT_CAP_ID_LBN 0 1807 #define PCRF_DZ_TPH_EXT_CAP_ID_WIDTH 16 1808 1809 1810 /* 1811 * PC_TPH_REQ_CAP_REG(32bit): 1812 * TPH Requester Capability Register 1813 */ 1814 1815 #define PCR_DZ_TPH_REQ_CAP_REG 0x00000278 1816 /* hunta0=pci_f0_config */ 1817 1818 #define PCRF_DZ_ST_TBLE_SIZE_LBN 16 1819 #define PCRF_DZ_ST_TBLE_SIZE_WIDTH 11 1820 #define PCRF_DZ_ST_TBLE_LOC_LBN 9 1821 #define PCRF_DZ_ST_TBLE_LOC_WIDTH 2 1822 #define PCRF_DZ_EXT_TPH_MODE_SUP_LBN 8 1823 #define PCRF_DZ_EXT_TPH_MODE_SUP_WIDTH 1 1824 #define PCRF_DZ_TPH_DEV_MODE_SUP_LBN 2 1825 #define PCRF_DZ_TPH_DEV_MODE_SUP_WIDTH 1 1826 #define PCRF_DZ_TPH_INT_MODE_SUP_LBN 1 1827 #define PCRF_DZ_TPH_INT_MODE_SUP_WIDTH 1 1828 #define PCRF_DZ_TPH_NOST_MODE_SUP_LBN 0 1829 #define PCRF_DZ_TPH_NOST_MODE_SUP_WIDTH 1 1830 1831 1832 /* 1833 * PC_TPH_REQ_CTL_REG(32bit): 1834 * TPH Requester Control Register 1835 */ 1836 1837 #define PCR_DZ_TPH_REQ_CTL_REG 0x0000027c 1838 /* hunta0=pci_f0_config */ 1839 1840 #define PCRF_DZ_TPH_REQ_ENABLE_LBN 8 1841 #define PCRF_DZ_TPH_REQ_ENABLE_WIDTH 2 1842 #define PCRF_DZ_TPH_ST_MODE_LBN 0 1843 #define PCRF_DZ_TPH_ST_MODE_WIDTH 3 1844 1845 1846 /* 1847 * PC_SEC_PCIE_CAP_REG(32bit): 1848 * Secondary PCIE Capability Register 1849 */ 1850 1851 #define PCR_DZ_SEC_PCIE_CAP_REG 0x00000300 1852 /* hunta0=pci_f0_config */ 1853 1854 #define PCRF_DZ_SEC_NXT_PTR_LBN 20 1855 #define PCRF_DZ_SEC_NXT_PTR_WIDTH 12 1856 #define PCRF_DZ_SEC_VERSION_LBN 16 1857 #define PCRF_DZ_SEC_VERSION_WIDTH 4 1858 #define PCRF_DZ_SEC_EXT_CAP_ID_LBN 0 1859 #define PCRF_DZ_SEC_EXT_CAP_ID_WIDTH 16 1860 1861 1862 /* 1863 * PC_LINK_CONTROL3_REG(32bit): 1864 * Link Control 3. 1865 */ 1866 1867 #define PCR_DZ_LINK_CONTROL3_REG 0x00000304 1868 /* hunta0=pci_f0_config */ 1869 1870 #define PCRF_DZ_LINK_EQ_INT_EN_LBN 1 1871 #define PCRF_DZ_LINK_EQ_INT_EN_WIDTH 1 1872 #define PCRF_DZ_PERFORM_EQL_LBN 0 1873 #define PCRF_DZ_PERFORM_EQL_WIDTH 1 1874 1875 1876 /* 1877 * PC_LANE_ERROR_STAT_REG(32bit): 1878 * Lane Error Status Register. 1879 */ 1880 1881 #define PCR_DZ_LANE_ERROR_STAT_REG 0x00000308 1882 /* hunta0=pci_f0_config */ 1883 1884 #define PCRF_DZ_LANE_STATUS_LBN 0 1885 #define PCRF_DZ_LANE_STATUS_WIDTH 8 1886 1887 1888 /* 1889 * PC_LANE01_EQU_CONTROL_REG(32bit): 1890 * Lanes 0,1 Equalization Control Register. 1891 */ 1892 1893 #define PCR_DZ_LANE01_EQU_CONTROL_REG 0x0000030c 1894 /* hunta0=pci_f0_config */ 1895 1896 #define PCRF_DZ_LANE1_EQ_CTRL_LBN 16 1897 #define PCRF_DZ_LANE1_EQ_CTRL_WIDTH 16 1898 #define PCRF_DZ_LANE0_EQ_CTRL_LBN 0 1899 #define PCRF_DZ_LANE0_EQ_CTRL_WIDTH 16 1900 1901 1902 /* 1903 * PC_LANE23_EQU_CONTROL_REG(32bit): 1904 * Lanes 2,3 Equalization Control Register. 1905 */ 1906 1907 #define PCR_DZ_LANE23_EQU_CONTROL_REG 0x00000310 1908 /* hunta0=pci_f0_config */ 1909 1910 #define PCRF_DZ_LANE3_EQ_CTRL_LBN 16 1911 #define PCRF_DZ_LANE3_EQ_CTRL_WIDTH 16 1912 #define PCRF_DZ_LANE2_EQ_CTRL_LBN 0 1913 #define PCRF_DZ_LANE2_EQ_CTRL_WIDTH 16 1914 1915 1916 /* 1917 * PC_LANE45_EQU_CONTROL_REG(32bit): 1918 * Lanes 4,5 Equalization Control Register. 1919 */ 1920 1921 #define PCR_DZ_LANE45_EQU_CONTROL_REG 0x00000314 1922 /* hunta0=pci_f0_config */ 1923 1924 #define PCRF_DZ_LANE5_EQ_CTRL_LBN 16 1925 #define PCRF_DZ_LANE5_EQ_CTRL_WIDTH 16 1926 #define PCRF_DZ_LANE4_EQ_CTRL_LBN 0 1927 #define PCRF_DZ_LANE4_EQ_CTRL_WIDTH 16 1928 1929 1930 /* 1931 * PC_LANE67_EQU_CONTROL_REG(32bit): 1932 * Lanes 6,7 Equalization Control Register. 1933 */ 1934 1935 #define PCR_DZ_LANE67_EQU_CONTROL_REG 0x00000318 1936 /* hunta0=pci_f0_config */ 1937 1938 #define PCRF_DZ_LANE7_EQ_CTRL_LBN 16 1939 #define PCRF_DZ_LANE7_EQ_CTRL_WIDTH 16 1940 #define PCRF_DZ_LANE6_EQ_CTRL_LBN 0 1941 #define PCRF_DZ_LANE6_EQ_CTRL_WIDTH 16 1942 1943 1944 /* 1945 * PC_ACK_LAT_TMR_REG(32bit): 1946 * ACK latency timer & replay timer register 1947 */ 1948 1949 #define PCR_AC_ACK_LAT_TMR_REG 0x00000700 1950 /* falcona0,falconb0,sienaa0=pci_f0_config */ 1951 1952 #define PCRF_AC_RT_LBN 16 1953 #define PCRF_AC_RT_WIDTH 16 1954 #define PCRF_AC_ALT_LBN 0 1955 #define PCRF_AC_ALT_WIDTH 16 1956 1957 1958 /* 1959 * PC_OTHER_MSG_REG(32bit): 1960 * Other message register 1961 */ 1962 1963 #define PCR_AC_OTHER_MSG_REG 0x00000704 1964 /* falcona0,falconb0,sienaa0=pci_f0_config */ 1965 1966 #define PCRF_AC_OM_CRPT3_LBN 24 1967 #define PCRF_AC_OM_CRPT3_WIDTH 8 1968 #define PCRF_AC_OM_CRPT2_LBN 16 1969 #define PCRF_AC_OM_CRPT2_WIDTH 8 1970 #define PCRF_AC_OM_CRPT1_LBN 8 1971 #define PCRF_AC_OM_CRPT1_WIDTH 8 1972 #define PCRF_AC_OM_CRPT0_LBN 0 1973 #define PCRF_AC_OM_CRPT0_WIDTH 8 1974 1975 1976 /* 1977 * PC_FORCE_LNK_REG(24bit): 1978 * Port force link register 1979 */ 1980 1981 #define PCR_AC_FORCE_LNK_REG 0x00000708 1982 /* falcona0,falconb0,sienaa0=pci_f0_config */ 1983 1984 #define PCRF_AC_LFS_LBN 16 1985 #define PCRF_AC_LFS_WIDTH 6 1986 #define PCRF_AC_FL_LBN 15 1987 #define PCRF_AC_FL_WIDTH 1 1988 #define PCRF_AC_LN_LBN 0 1989 #define PCRF_AC_LN_WIDTH 8 1990 1991 1992 /* 1993 * PC_ACK_FREQ_REG(32bit): 1994 * ACK frequency register 1995 */ 1996 1997 #define PCR_AC_ACK_FREQ_REG 0x0000070c 1998 /* falcona0,falconb0,sienaa0=pci_f0_config */ 1999 2000 #define PCRF_CC_ALLOW_L1_WITHOUT_L0S_LBN 30 2001 #define PCRF_CC_ALLOW_L1_WITHOUT_L0S_WIDTH 1 2002 #define PCRF_AC_L1_ENTR_LAT_LBN 27 2003 #define PCRF_AC_L1_ENTR_LAT_WIDTH 3 2004 #define PCRF_AC_L0_ENTR_LAT_LBN 24 2005 #define PCRF_AC_L0_ENTR_LAT_WIDTH 3 2006 #define PCRF_CC_COMM_NFTS_LBN 16 2007 #define PCRF_CC_COMM_NFTS_WIDTH 8 2008 #define PCRF_AB_ACK_FREQ_REG_RSVD0_LBN 16 2009 #define PCRF_AB_ACK_FREQ_REG_RSVD0_WIDTH 3 2010 #define PCRF_AC_MAX_FTS_LBN 8 2011 #define PCRF_AC_MAX_FTS_WIDTH 8 2012 #define PCRF_AC_ACK_FREQ_LBN 0 2013 #define PCRF_AC_ACK_FREQ_WIDTH 8 2014 2015 2016 /* 2017 * PC_PORT_LNK_CTL_REG(32bit): 2018 * Port link control register 2019 */ 2020 2021 #define PCR_AC_PORT_LNK_CTL_REG 0x00000710 2022 /* falcona0,falconb0,sienaa0=pci_f0_config */ 2023 2024 #define PCRF_AB_LRE_LBN 27 2025 #define PCRF_AB_LRE_WIDTH 1 2026 #define PCRF_AB_ESYNC_LBN 26 2027 #define PCRF_AB_ESYNC_WIDTH 1 2028 #define PCRF_AB_CRPT_LBN 25 2029 #define PCRF_AB_CRPT_WIDTH 1 2030 #define PCRF_AB_XB_LBN 24 2031 #define PCRF_AB_XB_WIDTH 1 2032 #define PCRF_AC_LC_LBN 16 2033 #define PCRF_AC_LC_WIDTH 6 2034 #define PCRF_AC_LDR_LBN 8 2035 #define PCRF_AC_LDR_WIDTH 4 2036 #define PCRF_AC_FLM_LBN 7 2037 #define PCRF_AC_FLM_WIDTH 1 2038 #define PCRF_AC_LKD_LBN 6 2039 #define PCRF_AC_LKD_WIDTH 1 2040 #define PCRF_AC_DLE_LBN 5 2041 #define PCRF_AC_DLE_WIDTH 1 2042 #define PCRF_AB_PORT_LNK_CTL_REG_RSVD0_LBN 4 2043 #define PCRF_AB_PORT_LNK_CTL_REG_RSVD0_WIDTH 1 2044 #define PCRF_AC_RA_LBN 3 2045 #define PCRF_AC_RA_WIDTH 1 2046 #define PCRF_AC_LE_LBN 2 2047 #define PCRF_AC_LE_WIDTH 1 2048 #define PCRF_AC_SD_LBN 1 2049 #define PCRF_AC_SD_WIDTH 1 2050 #define PCRF_AC_OMR_LBN 0 2051 #define PCRF_AC_OMR_WIDTH 1 2052 2053 2054 /* 2055 * PC_LN_SKEW_REG(32bit): 2056 * Lane skew register 2057 */ 2058 2059 #define PCR_AC_LN_SKEW_REG 0x00000714 2060 /* falcona0,falconb0,sienaa0=pci_f0_config */ 2061 2062 #define PCRF_AC_DIS_LBN 31 2063 #define PCRF_AC_DIS_WIDTH 1 2064 #define PCRF_AB_RST_LBN 30 2065 #define PCRF_AB_RST_WIDTH 1 2066 #define PCRF_AC_AD_LBN 25 2067 #define PCRF_AC_AD_WIDTH 1 2068 #define PCRF_AC_FCD_LBN 24 2069 #define PCRF_AC_FCD_WIDTH 1 2070 #define PCRF_AC_LS2_LBN 16 2071 #define PCRF_AC_LS2_WIDTH 8 2072 #define PCRF_AC_LS1_LBN 8 2073 #define PCRF_AC_LS1_WIDTH 8 2074 #define PCRF_AC_LS0_LBN 0 2075 #define PCRF_AC_LS0_WIDTH 8 2076 2077 2078 /* 2079 * PC_SYM_NUM_REG(16bit): 2080 * Symbol number register 2081 */ 2082 2083 #define PCR_AC_SYM_NUM_REG 0x00000718 2084 /* falcona0,falconb0,sienaa0=pci_f0_config */ 2085 2086 #define PCRF_CC_MAX_FUNCTIONS_LBN 29 2087 #define PCRF_CC_MAX_FUNCTIONS_WIDTH 3 2088 #define PCRF_CC_FC_WATCHDOG_TMR_LBN 24 2089 #define PCRF_CC_FC_WATCHDOG_TMR_WIDTH 5 2090 #define PCRF_CC_ACK_NAK_TMR_MOD_LBN 19 2091 #define PCRF_CC_ACK_NAK_TMR_MOD_WIDTH 5 2092 #define PCRF_CC_REPLAY_TMR_MOD_LBN 14 2093 #define PCRF_CC_REPLAY_TMR_MOD_WIDTH 5 2094 #define PCRF_AB_ES_LBN 12 2095 #define PCRF_AB_ES_WIDTH 3 2096 #define PCRF_AB_SYM_NUM_REG_RSVD0_LBN 11 2097 #define PCRF_AB_SYM_NUM_REG_RSVD0_WIDTH 1 2098 #define PCRF_CC_NUM_SKP_SYMS_LBN 8 2099 #define PCRF_CC_NUM_SKP_SYMS_WIDTH 3 2100 #define PCRF_AB_TS2_LBN 4 2101 #define PCRF_AB_TS2_WIDTH 4 2102 #define PCRF_AC_TS1_LBN 0 2103 #define PCRF_AC_TS1_WIDTH 4 2104 2105 2106 /* 2107 * PC_SYM_TMR_FLT_MSK_REG(16bit): 2108 * Symbol timer and Filter Mask Register 2109 */ 2110 2111 #define PCR_CC_SYM_TMR_FLT_MSK_REG 0x0000071c 2112 /* sienaa0=pci_f0_config */ 2113 2114 #define PCRF_CC_DEFAULT_FLT_MSK1_LBN 16 2115 #define PCRF_CC_DEFAULT_FLT_MSK1_WIDTH 16 2116 #define PCRF_CC_FC_WDOG_TMR_DIS_LBN 15 2117 #define PCRF_CC_FC_WDOG_TMR_DIS_WIDTH 1 2118 #define PCRF_CC_SI1_LBN 8 2119 #define PCRF_CC_SI1_WIDTH 3 2120 #define PCRF_CC_SKIP_INT_VAL_LBN 0 2121 #define PCRF_CC_SKIP_INT_VAL_WIDTH 11 2122 #define PCRF_CC_SI0_LBN 0 2123 #define PCRF_CC_SI0_WIDTH 8 2124 2125 2126 /* 2127 * PC_SYM_TMR_REG(16bit): 2128 * Symbol timer register 2129 */ 2130 2131 #define PCR_AB_SYM_TMR_REG 0x0000071c 2132 /* falcona0,falconb0=pci_f0_config */ 2133 2134 #define PCRF_AB_ET_LBN 11 2135 #define PCRF_AB_ET_WIDTH 4 2136 #define PCRF_AB_SI1_LBN 8 2137 #define PCRF_AB_SI1_WIDTH 3 2138 #define PCRF_AB_SI0_LBN 0 2139 #define PCRF_AB_SI0_WIDTH 8 2140 2141 2142 /* 2143 * PC_PHY_STAT_REG(32bit): 2144 * PHY status register 2145 */ 2146 2147 #define PCR_AB_PHY_STAT_REG 0x00000720 2148 /* falcona0,falconb0=pci_f0_config */ 2149 2150 #define PCR_CC_PHY_STAT_REG 0x00000810 2151 /* sienaa0=pci_f0_config */ 2152 2153 #define PCRF_AC_SSL_LBN 3 2154 #define PCRF_AC_SSL_WIDTH 1 2155 #define PCRF_AC_SSR_LBN 2 2156 #define PCRF_AC_SSR_WIDTH 1 2157 #define PCRF_AC_SSCL_LBN 1 2158 #define PCRF_AC_SSCL_WIDTH 1 2159 #define PCRF_AC_SSCD_LBN 0 2160 #define PCRF_AC_SSCD_WIDTH 1 2161 2162 2163 /* 2164 * PC_FLT_MSK_REG(32bit): 2165 * Filter Mask Register 2 2166 */ 2167 2168 #define PCR_CC_FLT_MSK_REG 0x00000720 2169 /* sienaa0=pci_f0_config */ 2170 2171 #define PCRF_CC_DEFAULT_FLT_MSK2_LBN 0 2172 #define PCRF_CC_DEFAULT_FLT_MSK2_WIDTH 32 2173 2174 2175 /* 2176 * PC_PHY_CTL_REG(32bit): 2177 * PHY control register 2178 */ 2179 2180 #define PCR_AB_PHY_CTL_REG 0x00000724 2181 /* falcona0,falconb0=pci_f0_config */ 2182 2183 #define PCR_CC_PHY_CTL_REG 0x00000814 2184 /* sienaa0=pci_f0_config */ 2185 2186 #define PCRF_AC_BD_LBN 31 2187 #define PCRF_AC_BD_WIDTH 1 2188 #define PCRF_AC_CDS_LBN 30 2189 #define PCRF_AC_CDS_WIDTH 1 2190 #define PCRF_AC_DWRAP_LB_LBN 29 2191 #define PCRF_AC_DWRAP_LB_WIDTH 1 2192 #define PCRF_AC_EBD_LBN 28 2193 #define PCRF_AC_EBD_WIDTH 1 2194 #define PCRF_AC_SNR_LBN 27 2195 #define PCRF_AC_SNR_WIDTH 1 2196 #define PCRF_AC_RX_NOT_DET_LBN 2 2197 #define PCRF_AC_RX_NOT_DET_WIDTH 1 2198 #define PCRF_AC_FORCE_LOS_VAL_LBN 1 2199 #define PCRF_AC_FORCE_LOS_VAL_WIDTH 1 2200 #define PCRF_AC_FORCE_LOS_EN_LBN 0 2201 #define PCRF_AC_FORCE_LOS_EN_WIDTH 1 2202 2203 2204 /* 2205 * PC_DEBUG0_REG(32bit): 2206 * Debug register 0 2207 */ 2208 2209 #define PCR_AC_DEBUG0_REG 0x00000728 2210 /* falcona0,falconb0,sienaa0=pci_f0_config */ 2211 2212 #define PCRF_AC_CDI03_LBN 24 2213 #define PCRF_AC_CDI03_WIDTH 8 2214 #define PCRF_AC_CDI0_LBN 0 2215 #define PCRF_AC_CDI0_WIDTH 32 2216 #define PCRF_AC_CDI02_LBN 16 2217 #define PCRF_AC_CDI02_WIDTH 8 2218 #define PCRF_AC_CDI01_LBN 8 2219 #define PCRF_AC_CDI01_WIDTH 8 2220 #define PCRF_AC_CDI00_LBN 0 2221 #define PCRF_AC_CDI00_WIDTH 8 2222 2223 2224 /* 2225 * PC_DEBUG1_REG(32bit): 2226 * Debug register 1 2227 */ 2228 2229 #define PCR_AC_DEBUG1_REG 0x0000072c 2230 /* falcona0,falconb0,sienaa0=pci_f0_config */ 2231 2232 #define PCRF_AC_CDI13_LBN 24 2233 #define PCRF_AC_CDI13_WIDTH 8 2234 #define PCRF_AC_CDI1_LBN 0 2235 #define PCRF_AC_CDI1_WIDTH 32 2236 #define PCRF_AC_CDI12_LBN 16 2237 #define PCRF_AC_CDI12_WIDTH 8 2238 #define PCRF_AC_CDI11_LBN 8 2239 #define PCRF_AC_CDI11_WIDTH 8 2240 #define PCRF_AC_CDI10_LBN 0 2241 #define PCRF_AC_CDI10_WIDTH 8 2242 2243 2244 /* 2245 * PC_XPFCC_STAT_REG(24bit): 2246 * documentation to be written for sum_PC_XPFCC_STAT_REG 2247 */ 2248 2249 #define PCR_AC_XPFCC_STAT_REG 0x00000730 2250 /* falcona0,falconb0,sienaa0=pci_f0_config */ 2251 2252 #define PCRF_AC_XPDC_LBN 12 2253 #define PCRF_AC_XPDC_WIDTH 8 2254 #define PCRF_AC_XPHC_LBN 0 2255 #define PCRF_AC_XPHC_WIDTH 12 2256 2257 2258 /* 2259 * PC_XNPFCC_STAT_REG(24bit): 2260 * documentation to be written for sum_PC_XNPFCC_STAT_REG 2261 */ 2262 2263 #define PCR_AC_XNPFCC_STAT_REG 0x00000734 2264 /* falcona0,falconb0,sienaa0=pci_f0_config */ 2265 2266 #define PCRF_AC_XNPDC_LBN 12 2267 #define PCRF_AC_XNPDC_WIDTH 8 2268 #define PCRF_AC_XNPHC_LBN 0 2269 #define PCRF_AC_XNPHC_WIDTH 12 2270 2271 2272 /* 2273 * PC_XCFCC_STAT_REG(24bit): 2274 * documentation to be written for sum_PC_XCFCC_STAT_REG 2275 */ 2276 2277 #define PCR_AC_XCFCC_STAT_REG 0x00000738 2278 /* falcona0,falconb0,sienaa0=pci_f0_config */ 2279 2280 #define PCRF_AC_XCDC_LBN 12 2281 #define PCRF_AC_XCDC_WIDTH 8 2282 #define PCRF_AC_XCHC_LBN 0 2283 #define PCRF_AC_XCHC_WIDTH 12 2284 2285 2286 /* 2287 * PC_Q_STAT_REG(8bit): 2288 * documentation to be written for sum_PC_Q_STAT_REG 2289 */ 2290 2291 #define PCR_AC_Q_STAT_REG 0x0000073c 2292 /* falcona0,falconb0,sienaa0=pci_f0_config */ 2293 2294 #define PCRF_AC_RQNE_LBN 2 2295 #define PCRF_AC_RQNE_WIDTH 1 2296 #define PCRF_AC_XRNE_LBN 1 2297 #define PCRF_AC_XRNE_WIDTH 1 2298 #define PCRF_AC_RCNR_LBN 0 2299 #define PCRF_AC_RCNR_WIDTH 1 2300 2301 2302 /* 2303 * PC_VC_XMIT_ARB1_REG(32bit): 2304 * VC Transmit Arbitration Register 1 2305 */ 2306 2307 #define PCR_CC_VC_XMIT_ARB1_REG 0x00000740 2308 /* sienaa0=pci_f0_config */ 2309 2310 2311 2312 /* 2313 * PC_VC_XMIT_ARB2_REG(32bit): 2314 * VC Transmit Arbitration Register 2 2315 */ 2316 2317 #define PCR_CC_VC_XMIT_ARB2_REG 0x00000744 2318 /* sienaa0=pci_f0_config */ 2319 2320 2321 2322 /* 2323 * PC_VC0_P_RQ_CTL_REG(32bit): 2324 * VC0 Posted Receive Queue Control 2325 */ 2326 2327 #define PCR_CC_VC0_P_RQ_CTL_REG 0x00000748 2328 /* sienaa0=pci_f0_config */ 2329 2330 2331 2332 /* 2333 * PC_VC0_NP_RQ_CTL_REG(32bit): 2334 * VC0 Non-Posted Receive Queue Control 2335 */ 2336 2337 #define PCR_CC_VC0_NP_RQ_CTL_REG 0x0000074c 2338 /* sienaa0=pci_f0_config */ 2339 2340 2341 2342 /* 2343 * PC_VC0_C_RQ_CTL_REG(32bit): 2344 * VC0 Completion Receive Queue Control 2345 */ 2346 2347 #define PCR_CC_VC0_C_RQ_CTL_REG 0x00000750 2348 /* sienaa0=pci_f0_config */ 2349 2350 2351 2352 /* 2353 * PC_GEN2_REG(32bit): 2354 * Gen2 Register 2355 */ 2356 2357 #define PCR_CC_GEN2_REG 0x0000080c 2358 /* sienaa0=pci_f0_config */ 2359 2360 #define PCRF_CC_SET_DE_EMPHASIS_LBN 20 2361 #define PCRF_CC_SET_DE_EMPHASIS_WIDTH 1 2362 #define PCRF_CC_CFG_TX_COMPLIANCE_LBN 19 2363 #define PCRF_CC_CFG_TX_COMPLIANCE_WIDTH 1 2364 #define PCRF_CC_CFG_TX_SWING_LBN 18 2365 #define PCRF_CC_CFG_TX_SWING_WIDTH 1 2366 #define PCRF_CC_DIR_SPEED_CHANGE_LBN 17 2367 #define PCRF_CC_DIR_SPEED_CHANGE_WIDTH 1 2368 #define PCRF_CC_LANE_ENABLE_LBN 8 2369 #define PCRF_CC_LANE_ENABLE_WIDTH 9 2370 #define PCRF_CC_NUM_FTS_LBN 0 2371 #define PCRF_CC_NUM_FTS_WIDTH 8 2372 2373 2374 #ifdef __cplusplus 2375 } 2376 #endif 2377 2378 #endif /* _SYS_EFX_REGS_PCI_H */ 2379