1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2007-2016 Solarflare Communications Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 18 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 26 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * The views and conclusions contained in the software and documentation are 29 * those of the authors and should not be interpreted as representing official 30 * policies, either expressed or implied, of the FreeBSD Project. 31 */ 32 33 #ifndef _SYS_EFX_REGS_PCI_H 34 #define _SYS_EFX_REGS_PCI_H 35 36 #ifdef __cplusplus 37 extern "C" { 38 #endif 39 40 /* 41 * PC_VEND_ID_REG(16bit): 42 * Vendor ID register 43 */ 44 45 #define PCR_AZ_VEND_ID_REG 0x00000000 46 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 47 48 #define PCRF_AZ_VEND_ID_LBN 0 49 #define PCRF_AZ_VEND_ID_WIDTH 16 50 51 /* 52 * PC_DEV_ID_REG(16bit): 53 * Device ID register 54 */ 55 56 #define PCR_AZ_DEV_ID_REG 0x00000002 57 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 58 59 #define PCRF_AZ_DEV_ID_LBN 0 60 #define PCRF_AZ_DEV_ID_WIDTH 16 61 62 /* 63 * PC_CMD_REG(16bit): 64 * Command register 65 */ 66 67 #define PCR_AZ_CMD_REG 0x00000004 68 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 69 70 #define PCRF_AZ_INTX_DIS_LBN 10 71 #define PCRF_AZ_INTX_DIS_WIDTH 1 72 #define PCRF_AZ_FB2B_EN_LBN 9 73 #define PCRF_AZ_FB2B_EN_WIDTH 1 74 #define PCRF_AZ_SERR_EN_LBN 8 75 #define PCRF_AZ_SERR_EN_WIDTH 1 76 #define PCRF_AZ_IDSEL_CTL_LBN 7 77 #define PCRF_AZ_IDSEL_CTL_WIDTH 1 78 #define PCRF_AZ_PERR_EN_LBN 6 79 #define PCRF_AZ_PERR_EN_WIDTH 1 80 #define PCRF_AZ_VGA_PAL_SNP_LBN 5 81 #define PCRF_AZ_VGA_PAL_SNP_WIDTH 1 82 #define PCRF_AZ_MWI_EN_LBN 4 83 #define PCRF_AZ_MWI_EN_WIDTH 1 84 #define PCRF_AZ_SPEC_CYC_LBN 3 85 #define PCRF_AZ_SPEC_CYC_WIDTH 1 86 #define PCRF_AZ_MST_EN_LBN 2 87 #define PCRF_AZ_MST_EN_WIDTH 1 88 #define PCRF_AZ_MEM_EN_LBN 1 89 #define PCRF_AZ_MEM_EN_WIDTH 1 90 #define PCRF_AZ_IO_EN_LBN 0 91 #define PCRF_AZ_IO_EN_WIDTH 1 92 93 /* 94 * PC_STAT_REG(16bit): 95 * Status register 96 */ 97 98 #define PCR_AZ_STAT_REG 0x00000006 99 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 100 101 #define PCRF_AZ_DET_PERR_LBN 15 102 #define PCRF_AZ_DET_PERR_WIDTH 1 103 #define PCRF_AZ_SIG_SERR_LBN 14 104 #define PCRF_AZ_SIG_SERR_WIDTH 1 105 #define PCRF_AZ_GOT_MABRT_LBN 13 106 #define PCRF_AZ_GOT_MABRT_WIDTH 1 107 #define PCRF_AZ_GOT_TABRT_LBN 12 108 #define PCRF_AZ_GOT_TABRT_WIDTH 1 109 #define PCRF_AZ_SIG_TABRT_LBN 11 110 #define PCRF_AZ_SIG_TABRT_WIDTH 1 111 #define PCRF_AZ_DEVSEL_TIM_LBN 9 112 #define PCRF_AZ_DEVSEL_TIM_WIDTH 2 113 #define PCRF_AZ_MDAT_PERR_LBN 8 114 #define PCRF_AZ_MDAT_PERR_WIDTH 1 115 #define PCRF_AZ_FB2B_CAP_LBN 7 116 #define PCRF_AZ_FB2B_CAP_WIDTH 1 117 #define PCRF_AZ_66MHZ_CAP_LBN 5 118 #define PCRF_AZ_66MHZ_CAP_WIDTH 1 119 #define PCRF_AZ_CAP_LIST_LBN 4 120 #define PCRF_AZ_CAP_LIST_WIDTH 1 121 #define PCRF_AZ_INTX_STAT_LBN 3 122 #define PCRF_AZ_INTX_STAT_WIDTH 1 123 124 /* 125 * PC_REV_ID_REG(8bit): 126 * Class code & revision ID register 127 */ 128 129 #define PCR_AZ_REV_ID_REG 0x00000008 130 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 131 132 #define PCRF_AZ_REV_ID_LBN 0 133 #define PCRF_AZ_REV_ID_WIDTH 8 134 135 /* 136 * PC_CC_REG(24bit): 137 * Class code register 138 */ 139 140 #define PCR_AZ_CC_REG 0x00000009 141 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 142 143 #define PCRF_AZ_BASE_CC_LBN 16 144 #define PCRF_AZ_BASE_CC_WIDTH 8 145 #define PCRF_AZ_SUB_CC_LBN 8 146 #define PCRF_AZ_SUB_CC_WIDTH 8 147 #define PCRF_AZ_PROG_IF_LBN 0 148 #define PCRF_AZ_PROG_IF_WIDTH 8 149 150 /* 151 * PC_CACHE_LSIZE_REG(8bit): 152 * Cache line size 153 */ 154 155 #define PCR_AZ_CACHE_LSIZE_REG 0x0000000c 156 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 157 158 #define PCRF_AZ_CACHE_LSIZE_LBN 0 159 #define PCRF_AZ_CACHE_LSIZE_WIDTH 8 160 161 /* 162 * PC_MST_LAT_REG(8bit): 163 * Master latency timer register 164 */ 165 166 #define PCR_AZ_MST_LAT_REG 0x0000000d 167 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 168 169 #define PCRF_AZ_MST_LAT_LBN 0 170 #define PCRF_AZ_MST_LAT_WIDTH 8 171 172 /* 173 * PC_HDR_TYPE_REG(8bit): 174 * Header type register 175 */ 176 177 #define PCR_AZ_HDR_TYPE_REG 0x0000000e 178 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 179 180 #define PCRF_AZ_MULT_FUNC_LBN 7 181 #define PCRF_AZ_MULT_FUNC_WIDTH 1 182 #define PCRF_AZ_TYPE_LBN 0 183 #define PCRF_AZ_TYPE_WIDTH 7 184 185 /* 186 * PC_BIST_REG(8bit): 187 * BIST register 188 */ 189 190 #define PCR_AZ_BIST_REG 0x0000000f 191 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 192 193 #define PCRF_AZ_BIST_LBN 0 194 #define PCRF_AZ_BIST_WIDTH 8 195 196 /* 197 * PC_BAR0_REG(32bit): 198 * Primary function base address register 0 199 */ 200 201 #define PCR_AZ_BAR0_REG 0x00000010 202 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 203 204 #define PCRF_AZ_BAR0_LBN 4 205 #define PCRF_AZ_BAR0_WIDTH 28 206 #define PCRF_AZ_BAR0_PREF_LBN 3 207 #define PCRF_AZ_BAR0_PREF_WIDTH 1 208 #define PCRF_AZ_BAR0_TYPE_LBN 1 209 #define PCRF_AZ_BAR0_TYPE_WIDTH 2 210 #define PCRF_AZ_BAR0_IOM_LBN 0 211 #define PCRF_AZ_BAR0_IOM_WIDTH 1 212 213 /* 214 * PC_BAR1_REG(32bit): 215 * Primary function base address register 1, BAR1 is not implemented so read only. 216 */ 217 218 #define PCR_DZ_BAR1_REG 0x00000014 219 /* hunta0=pci_f0_config */ 220 221 #define PCRF_DZ_BAR1_LBN 0 222 #define PCRF_DZ_BAR1_WIDTH 32 223 224 /* 225 * PC_BAR2_LO_REG(32bit): 226 * Primary function base address register 2 low bits 227 */ 228 229 #define PCR_AZ_BAR2_LO_REG 0x00000018 230 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 231 232 #define PCRF_AZ_BAR2_LO_LBN 4 233 #define PCRF_AZ_BAR2_LO_WIDTH 28 234 #define PCRF_AZ_BAR2_PREF_LBN 3 235 #define PCRF_AZ_BAR2_PREF_WIDTH 1 236 #define PCRF_AZ_BAR2_TYPE_LBN 1 237 #define PCRF_AZ_BAR2_TYPE_WIDTH 2 238 #define PCRF_AZ_BAR2_IOM_LBN 0 239 #define PCRF_AZ_BAR2_IOM_WIDTH 1 240 241 /* 242 * PC_BAR2_HI_REG(32bit): 243 * Primary function base address register 2 high bits 244 */ 245 246 #define PCR_AZ_BAR2_HI_REG 0x0000001c 247 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 248 249 #define PCRF_AZ_BAR2_HI_LBN 0 250 #define PCRF_AZ_BAR2_HI_WIDTH 32 251 252 /* 253 * PC_BAR4_LO_REG(32bit): 254 * Primary function base address register 2 low bits 255 */ 256 257 #define PCR_CZ_BAR4_LO_REG 0x00000020 258 /* sienaa0,hunta0=pci_f0_config */ 259 260 #define PCRF_CZ_BAR4_LO_LBN 4 261 #define PCRF_CZ_BAR4_LO_WIDTH 28 262 #define PCRF_CZ_BAR4_PREF_LBN 3 263 #define PCRF_CZ_BAR4_PREF_WIDTH 1 264 #define PCRF_CZ_BAR4_TYPE_LBN 1 265 #define PCRF_CZ_BAR4_TYPE_WIDTH 2 266 #define PCRF_CZ_BAR4_IOM_LBN 0 267 #define PCRF_CZ_BAR4_IOM_WIDTH 1 268 269 /* 270 * PC_BAR4_HI_REG(32bit): 271 * Primary function base address register 2 high bits 272 */ 273 274 #define PCR_CZ_BAR4_HI_REG 0x00000024 275 /* sienaa0,hunta0=pci_f0_config */ 276 277 #define PCRF_CZ_BAR4_HI_LBN 0 278 #define PCRF_CZ_BAR4_HI_WIDTH 32 279 280 /* 281 * PC_SS_VEND_ID_REG(16bit): 282 * Sub-system vendor ID register 283 */ 284 285 #define PCR_AZ_SS_VEND_ID_REG 0x0000002c 286 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 287 288 #define PCRF_AZ_SS_VEND_ID_LBN 0 289 #define PCRF_AZ_SS_VEND_ID_WIDTH 16 290 291 /* 292 * PC_SS_ID_REG(16bit): 293 * Sub-system ID register 294 */ 295 296 #define PCR_AZ_SS_ID_REG 0x0000002e 297 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 298 299 #define PCRF_AZ_SS_ID_LBN 0 300 #define PCRF_AZ_SS_ID_WIDTH 16 301 302 /* 303 * PC_EXPROM_BAR_REG(32bit): 304 * Expansion ROM base address register 305 */ 306 307 #define PCR_AZ_EXPROM_BAR_REG 0x00000030 308 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 309 310 #define PCRF_AZ_EXPROM_BAR_LBN 11 311 #define PCRF_AZ_EXPROM_BAR_WIDTH 21 312 #define PCRF_AB_EXPROM_MIN_SIZE_LBN 2 313 #define PCRF_AB_EXPROM_MIN_SIZE_WIDTH 9 314 #define PCRF_CZ_EXPROM_MIN_SIZE_LBN 1 315 #define PCRF_CZ_EXPROM_MIN_SIZE_WIDTH 10 316 #define PCRF_AB_EXPROM_FEATURE_ENABLE_LBN 1 317 #define PCRF_AB_EXPROM_FEATURE_ENABLE_WIDTH 1 318 #define PCRF_AZ_EXPROM_EN_LBN 0 319 #define PCRF_AZ_EXPROM_EN_WIDTH 1 320 321 /* 322 * PC_CAP_PTR_REG(8bit): 323 * Capability pointer register 324 */ 325 326 #define PCR_AZ_CAP_PTR_REG 0x00000034 327 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 328 329 #define PCRF_AZ_CAP_PTR_LBN 0 330 #define PCRF_AZ_CAP_PTR_WIDTH 8 331 332 /* 333 * PC_INT_LINE_REG(8bit): 334 * Interrupt line register 335 */ 336 337 #define PCR_AZ_INT_LINE_REG 0x0000003c 338 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 339 340 #define PCRF_AZ_INT_LINE_LBN 0 341 #define PCRF_AZ_INT_LINE_WIDTH 8 342 343 /* 344 * PC_INT_PIN_REG(8bit): 345 * Interrupt pin register 346 */ 347 348 #define PCR_AZ_INT_PIN_REG 0x0000003d 349 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 350 351 #define PCRF_AZ_INT_PIN_LBN 0 352 #define PCRF_AZ_INT_PIN_WIDTH 8 353 #define PCFE_DZ_INTPIN_INTD 4 354 #define PCFE_DZ_INTPIN_INTC 3 355 #define PCFE_DZ_INTPIN_INTB 2 356 #define PCFE_DZ_INTPIN_INTA 1 357 358 /* 359 * PC_PM_CAP_ID_REG(8bit): 360 * Power management capability ID 361 */ 362 363 #define PCR_AZ_PM_CAP_ID_REG 0x00000040 364 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 365 366 #define PCRF_AZ_PM_CAP_ID_LBN 0 367 #define PCRF_AZ_PM_CAP_ID_WIDTH 8 368 369 /* 370 * PC_PM_NXT_PTR_REG(8bit): 371 * Power management next item pointer 372 */ 373 374 #define PCR_AZ_PM_NXT_PTR_REG 0x00000041 375 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 376 377 #define PCRF_AZ_PM_NXT_PTR_LBN 0 378 #define PCRF_AZ_PM_NXT_PTR_WIDTH 8 379 380 /* 381 * PC_PM_CAP_REG(16bit): 382 * Power management capabilities register 383 */ 384 385 #define PCR_AZ_PM_CAP_REG 0x00000042 386 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 387 388 #define PCRF_AZ_PM_PME_SUPT_LBN 11 389 #define PCRF_AZ_PM_PME_SUPT_WIDTH 5 390 #define PCRF_AZ_PM_D2_SUPT_LBN 10 391 #define PCRF_AZ_PM_D2_SUPT_WIDTH 1 392 #define PCRF_AZ_PM_D1_SUPT_LBN 9 393 #define PCRF_AZ_PM_D1_SUPT_WIDTH 1 394 #define PCRF_AZ_PM_AUX_CURR_LBN 6 395 #define PCRF_AZ_PM_AUX_CURR_WIDTH 3 396 #define PCRF_AZ_PM_DSI_LBN 5 397 #define PCRF_AZ_PM_DSI_WIDTH 1 398 #define PCRF_AZ_PM_PME_CLK_LBN 3 399 #define PCRF_AZ_PM_PME_CLK_WIDTH 1 400 #define PCRF_AZ_PM_PME_VER_LBN 0 401 #define PCRF_AZ_PM_PME_VER_WIDTH 3 402 403 /* 404 * PC_PM_CS_REG(16bit): 405 * Power management control & status register 406 */ 407 408 #define PCR_AZ_PM_CS_REG 0x00000044 409 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 410 411 #define PCRF_AZ_PM_PME_STAT_LBN 15 412 #define PCRF_AZ_PM_PME_STAT_WIDTH 1 413 #define PCRF_AZ_PM_DAT_SCALE_LBN 13 414 #define PCRF_AZ_PM_DAT_SCALE_WIDTH 2 415 #define PCRF_AZ_PM_DAT_SEL_LBN 9 416 #define PCRF_AZ_PM_DAT_SEL_WIDTH 4 417 #define PCRF_AZ_PM_PME_EN_LBN 8 418 #define PCRF_AZ_PM_PME_EN_WIDTH 1 419 #define PCRF_CZ_NO_SOFT_RESET_LBN 3 420 #define PCRF_CZ_NO_SOFT_RESET_WIDTH 1 421 #define PCRF_AZ_PM_PWR_ST_LBN 0 422 #define PCRF_AZ_PM_PWR_ST_WIDTH 2 423 424 /* 425 * PC_MSI_CAP_ID_REG(8bit): 426 * MSI capability ID 427 */ 428 429 #define PCR_AZ_MSI_CAP_ID_REG 0x00000050 430 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 431 432 #define PCRF_AZ_MSI_CAP_ID_LBN 0 433 #define PCRF_AZ_MSI_CAP_ID_WIDTH 8 434 435 /* 436 * PC_MSI_NXT_PTR_REG(8bit): 437 * MSI next item pointer 438 */ 439 440 #define PCR_AZ_MSI_NXT_PTR_REG 0x00000051 441 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 442 443 #define PCRF_AZ_MSI_NXT_PTR_LBN 0 444 #define PCRF_AZ_MSI_NXT_PTR_WIDTH 8 445 446 /* 447 * PC_MSI_CTL_REG(16bit): 448 * MSI control register 449 */ 450 451 #define PCR_AZ_MSI_CTL_REG 0x00000052 452 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 453 454 #define PCRF_AZ_MSI_64_EN_LBN 7 455 #define PCRF_AZ_MSI_64_EN_WIDTH 1 456 #define PCRF_AZ_MSI_MULT_MSG_EN_LBN 4 457 #define PCRF_AZ_MSI_MULT_MSG_EN_WIDTH 3 458 #define PCRF_AZ_MSI_MULT_MSG_CAP_LBN 1 459 #define PCRF_AZ_MSI_MULT_MSG_CAP_WIDTH 3 460 #define PCRF_AZ_MSI_EN_LBN 0 461 #define PCRF_AZ_MSI_EN_WIDTH 1 462 463 /* 464 * PC_MSI_ADR_LO_REG(32bit): 465 * MSI low 32 bits address register 466 */ 467 468 #define PCR_AZ_MSI_ADR_LO_REG 0x00000054 469 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 470 471 #define PCRF_AZ_MSI_ADR_LO_LBN 2 472 #define PCRF_AZ_MSI_ADR_LO_WIDTH 30 473 474 /* 475 * PC_MSI_ADR_HI_REG(32bit): 476 * MSI high 32 bits address register 477 */ 478 479 #define PCR_AZ_MSI_ADR_HI_REG 0x00000058 480 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 481 482 #define PCRF_AZ_MSI_ADR_HI_LBN 0 483 #define PCRF_AZ_MSI_ADR_HI_WIDTH 32 484 485 /* 486 * PC_MSI_DAT_REG(16bit): 487 * MSI data register 488 */ 489 490 #define PCR_AZ_MSI_DAT_REG 0x0000005c 491 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 492 493 #define PCRF_AZ_MSI_DAT_LBN 0 494 #define PCRF_AZ_MSI_DAT_WIDTH 16 495 496 /* 497 * PC_PCIE_CAP_LIST_REG(16bit): 498 * PCIe capability list register 499 */ 500 501 #define PCR_AB_PCIE_CAP_LIST_REG 0x00000060 502 /* falcona0,falconb0=pci_f0_config */ 503 504 #define PCR_CZ_PCIE_CAP_LIST_REG 0x00000070 505 /* sienaa0,hunta0=pci_f0_config */ 506 507 #define PCRF_AZ_PCIE_NXT_PTR_LBN 8 508 #define PCRF_AZ_PCIE_NXT_PTR_WIDTH 8 509 #define PCRF_AZ_PCIE_CAP_ID_LBN 0 510 #define PCRF_AZ_PCIE_CAP_ID_WIDTH 8 511 512 /* 513 * PC_PCIE_CAP_REG(16bit): 514 * PCIe capability register 515 */ 516 517 #define PCR_AB_PCIE_CAP_REG 0x00000062 518 /* falcona0,falconb0=pci_f0_config */ 519 520 #define PCR_CZ_PCIE_CAP_REG 0x00000072 521 /* sienaa0,hunta0=pci_f0_config */ 522 523 #define PCRF_AZ_PCIE_INT_MSG_NUM_LBN 9 524 #define PCRF_AZ_PCIE_INT_MSG_NUM_WIDTH 5 525 #define PCRF_AZ_PCIE_SLOT_IMP_LBN 8 526 #define PCRF_AZ_PCIE_SLOT_IMP_WIDTH 1 527 #define PCRF_AZ_PCIE_DEV_PORT_TYPE_LBN 4 528 #define PCRF_AZ_PCIE_DEV_PORT_TYPE_WIDTH 4 529 #define PCRF_AZ_PCIE_CAP_VER_LBN 0 530 #define PCRF_AZ_PCIE_CAP_VER_WIDTH 4 531 532 /* 533 * PC_DEV_CAP_REG(32bit): 534 * PCIe device capabilities register 535 */ 536 537 #define PCR_AB_DEV_CAP_REG 0x00000064 538 /* falcona0,falconb0=pci_f0_config */ 539 540 #define PCR_CZ_DEV_CAP_REG 0x00000074 541 /* sienaa0=pci_f0_config,hunta0=pci_f0_config */ 542 543 #define PCRF_CZ_CAP_FN_LEVEL_RESET_LBN 28 544 #define PCRF_CZ_CAP_FN_LEVEL_RESET_WIDTH 1 545 #define PCRF_AZ_CAP_SLOT_PWR_SCL_LBN 26 546 #define PCRF_AZ_CAP_SLOT_PWR_SCL_WIDTH 2 547 #define PCRF_AZ_CAP_SLOT_PWR_VAL_LBN 18 548 #define PCRF_AZ_CAP_SLOT_PWR_VAL_WIDTH 8 549 #define PCRF_CZ_ROLE_BASE_ERR_REPORTING_LBN 15 550 #define PCRF_CZ_ROLE_BASE_ERR_REPORTING_WIDTH 1 551 #define PCRF_AB_PWR_IND_LBN 14 552 #define PCRF_AB_PWR_IND_WIDTH 1 553 #define PCRF_AB_ATTN_IND_LBN 13 554 #define PCRF_AB_ATTN_IND_WIDTH 1 555 #define PCRF_AB_ATTN_BUTTON_LBN 12 556 #define PCRF_AB_ATTN_BUTTON_WIDTH 1 557 #define PCRF_AZ_ENDPT_L1_LAT_LBN 9 558 #define PCRF_AZ_ENDPT_L1_LAT_WIDTH 3 559 #define PCRF_AZ_ENDPT_L0_LAT_LBN 6 560 #define PCRF_AZ_ENDPT_L0_LAT_WIDTH 3 561 #define PCRF_AZ_TAG_FIELD_LBN 5 562 #define PCRF_AZ_TAG_FIELD_WIDTH 1 563 #define PCRF_AZ_PHAN_FUNC_LBN 3 564 #define PCRF_AZ_PHAN_FUNC_WIDTH 2 565 #define PCRF_AZ_MAX_PAYL_SIZE_SUPT_LBN 0 566 #define PCRF_AZ_MAX_PAYL_SIZE_SUPT_WIDTH 3 567 568 /* 569 * PC_DEV_CTL_REG(16bit): 570 * PCIe device control register 571 */ 572 573 #define PCR_AB_DEV_CTL_REG 0x00000068 574 /* falcona0,falconb0=pci_f0_config */ 575 576 #define PCR_CZ_DEV_CTL_REG 0x00000078 577 /* sienaa0,hunta0=pci_f0_config */ 578 579 #define PCRF_CZ_FN_LEVEL_RESET_LBN 15 580 #define PCRF_CZ_FN_LEVEL_RESET_WIDTH 1 581 #define PCRF_AZ_MAX_RD_REQ_SIZE_LBN 12 582 #define PCRF_AZ_MAX_RD_REQ_SIZE_WIDTH 3 583 #define PCFE_AZ_MAX_RD_REQ_SIZE_4096 5 584 #define PCFE_AZ_MAX_RD_REQ_SIZE_2048 4 585 #define PCFE_AZ_MAX_RD_REQ_SIZE_1024 3 586 #define PCFE_AZ_MAX_RD_REQ_SIZE_512 2 587 #define PCFE_AZ_MAX_RD_REQ_SIZE_256 1 588 #define PCFE_AZ_MAX_RD_REQ_SIZE_128 0 589 #define PCRF_AZ_EN_NO_SNOOP_LBN 11 590 #define PCRF_AZ_EN_NO_SNOOP_WIDTH 1 591 #define PCRF_AZ_AUX_PWR_PM_EN_LBN 10 592 #define PCRF_AZ_AUX_PWR_PM_EN_WIDTH 1 593 #define PCRF_AZ_PHAN_FUNC_EN_LBN 9 594 #define PCRF_AZ_PHAN_FUNC_EN_WIDTH 1 595 #define PCRF_AB_DEV_CAP_REG_RSVD0_LBN 8 596 #define PCRF_AB_DEV_CAP_REG_RSVD0_WIDTH 1 597 #define PCRF_CZ_EXTENDED_TAG_EN_LBN 8 598 #define PCRF_CZ_EXTENDED_TAG_EN_WIDTH 1 599 #define PCRF_AZ_MAX_PAYL_SIZE_LBN 5 600 #define PCRF_AZ_MAX_PAYL_SIZE_WIDTH 3 601 #define PCFE_AZ_MAX_PAYL_SIZE_4096 5 602 #define PCFE_AZ_MAX_PAYL_SIZE_2048 4 603 #define PCFE_AZ_MAX_PAYL_SIZE_1024 3 604 #define PCFE_AZ_MAX_PAYL_SIZE_512 2 605 #define PCFE_AZ_MAX_PAYL_SIZE_256 1 606 #define PCFE_AZ_MAX_PAYL_SIZE_128 0 607 #define PCRF_AZ_EN_RELAX_ORDER_LBN 4 608 #define PCRF_AZ_EN_RELAX_ORDER_WIDTH 1 609 #define PCRF_AZ_UNSUP_REQ_RPT_EN_LBN 3 610 #define PCRF_AZ_UNSUP_REQ_RPT_EN_WIDTH 1 611 #define PCRF_AZ_FATAL_ERR_RPT_EN_LBN 2 612 #define PCRF_AZ_FATAL_ERR_RPT_EN_WIDTH 1 613 #define PCRF_AZ_NONFATAL_ERR_RPT_EN_LBN 1 614 #define PCRF_AZ_NONFATAL_ERR_RPT_EN_WIDTH 1 615 #define PCRF_AZ_CORR_ERR_RPT_EN_LBN 0 616 #define PCRF_AZ_CORR_ERR_RPT_EN_WIDTH 1 617 618 /* 619 * PC_DEV_STAT_REG(16bit): 620 * PCIe device status register 621 */ 622 623 #define PCR_AB_DEV_STAT_REG 0x0000006a 624 /* falcona0,falconb0=pci_f0_config */ 625 626 #define PCR_CZ_DEV_STAT_REG 0x0000007a 627 /* sienaa0,hunta0=pci_f0_config */ 628 629 #define PCRF_AZ_TRNS_PEND_LBN 5 630 #define PCRF_AZ_TRNS_PEND_WIDTH 1 631 #define PCRF_AZ_AUX_PWR_DET_LBN 4 632 #define PCRF_AZ_AUX_PWR_DET_WIDTH 1 633 #define PCRF_AZ_UNSUP_REQ_DET_LBN 3 634 #define PCRF_AZ_UNSUP_REQ_DET_WIDTH 1 635 #define PCRF_AZ_FATAL_ERR_DET_LBN 2 636 #define PCRF_AZ_FATAL_ERR_DET_WIDTH 1 637 #define PCRF_AZ_NONFATAL_ERR_DET_LBN 1 638 #define PCRF_AZ_NONFATAL_ERR_DET_WIDTH 1 639 #define PCRF_AZ_CORR_ERR_DET_LBN 0 640 #define PCRF_AZ_CORR_ERR_DET_WIDTH 1 641 642 /* 643 * PC_LNK_CAP_REG(32bit): 644 * PCIe link capabilities register 645 */ 646 647 #define PCR_AB_LNK_CAP_REG 0x0000006c 648 /* falcona0,falconb0=pci_f0_config */ 649 650 #define PCR_CZ_LNK_CAP_REG 0x0000007c 651 /* sienaa0,hunta0=pci_f0_config */ 652 653 #define PCRF_AZ_PORT_NUM_LBN 24 654 #define PCRF_AZ_PORT_NUM_WIDTH 8 655 #define PCRF_DZ_ASPM_OPTIONALITY_CAP_LBN 22 656 #define PCRF_DZ_ASPM_OPTIONALITY_CAP_WIDTH 1 657 #define PCRF_CZ_LINK_BWDITH_NOTIF_CAP_LBN 21 658 #define PCRF_CZ_LINK_BWDITH_NOTIF_CAP_WIDTH 1 659 #define PCRF_CZ_DATA_LINK_ACTIVE_RPT_CAP_LBN 20 660 #define PCRF_CZ_DATA_LINK_ACTIVE_RPT_CAP_WIDTH 1 661 #define PCRF_CZ_SURPISE_DOWN_RPT_CAP_LBN 19 662 #define PCRF_CZ_SURPISE_DOWN_RPT_CAP_WIDTH 1 663 #define PCRF_CZ_CLOCK_PWR_MNGMNT_CAP_LBN 18 664 #define PCRF_CZ_CLOCK_PWR_MNGMNT_CAP_WIDTH 1 665 #define PCRF_AZ_DEF_L1_EXIT_LAT_LBN 15 666 #define PCRF_AZ_DEF_L1_EXIT_LAT_WIDTH 3 667 #define PCRF_AZ_DEF_L0_EXIT_LATPORT_NUM_LBN 12 668 #define PCRF_AZ_DEF_L0_EXIT_LATPORT_NUM_WIDTH 3 669 #define PCRF_AZ_AS_LNK_PM_SUPT_LBN 10 670 #define PCRF_AZ_AS_LNK_PM_SUPT_WIDTH 2 671 #define PCRF_AZ_MAX_LNK_WIDTH_LBN 4 672 #define PCRF_AZ_MAX_LNK_WIDTH_WIDTH 6 673 #define PCRF_AZ_MAX_LNK_SP_LBN 0 674 #define PCRF_AZ_MAX_LNK_SP_WIDTH 4 675 676 /* 677 * PC_LNK_CTL_REG(16bit): 678 * PCIe link control register 679 */ 680 681 #define PCR_AB_LNK_CTL_REG 0x00000070 682 /* falcona0,falconb0=pci_f0_config */ 683 684 #define PCR_CZ_LNK_CTL_REG 0x00000080 685 /* sienaa0,hunta0=pci_f0_config */ 686 687 #define PCRF_AZ_EXT_SYNC_LBN 7 688 #define PCRF_AZ_EXT_SYNC_WIDTH 1 689 #define PCRF_AZ_COMM_CLK_CFG_LBN 6 690 #define PCRF_AZ_COMM_CLK_CFG_WIDTH 1 691 #define PCRF_AB_LNK_CTL_REG_RSVD0_LBN 5 692 #define PCRF_AB_LNK_CTL_REG_RSVD0_WIDTH 1 693 #define PCRF_CZ_LNK_RETRAIN_LBN 5 694 #define PCRF_CZ_LNK_RETRAIN_WIDTH 1 695 #define PCRF_AZ_LNK_DIS_LBN 4 696 #define PCRF_AZ_LNK_DIS_WIDTH 1 697 #define PCRF_AZ_RD_COM_BDRY_LBN 3 698 #define PCRF_AZ_RD_COM_BDRY_WIDTH 1 699 #define PCRF_AZ_ACT_ST_LNK_PM_CTL_LBN 0 700 #define PCRF_AZ_ACT_ST_LNK_PM_CTL_WIDTH 2 701 702 /* 703 * PC_LNK_STAT_REG(16bit): 704 * PCIe link status register 705 */ 706 707 #define PCR_AB_LNK_STAT_REG 0x00000072 708 /* falcona0,falconb0=pci_f0_config */ 709 710 #define PCR_CZ_LNK_STAT_REG 0x00000082 711 /* sienaa0,hunta0=pci_f0_config */ 712 713 #define PCRF_AZ_SLOT_CLK_CFG_LBN 12 714 #define PCRF_AZ_SLOT_CLK_CFG_WIDTH 1 715 #define PCRF_AZ_LNK_TRAIN_LBN 11 716 #define PCRF_AZ_LNK_TRAIN_WIDTH 1 717 #define PCRF_AB_TRAIN_ERR_LBN 10 718 #define PCRF_AB_TRAIN_ERR_WIDTH 1 719 #define PCRF_AZ_LNK_WIDTH_LBN 4 720 #define PCRF_AZ_LNK_WIDTH_WIDTH 6 721 #define PCRF_AZ_LNK_SP_LBN 0 722 #define PCRF_AZ_LNK_SP_WIDTH 4 723 724 /* 725 * PC_SLOT_CAP_REG(32bit): 726 * PCIe slot capabilities register 727 */ 728 729 #define PCR_AB_SLOT_CAP_REG 0x00000074 730 /* falcona0,falconb0=pci_f0_config */ 731 732 #define PCRF_AB_SLOT_NUM_LBN 19 733 #define PCRF_AB_SLOT_NUM_WIDTH 13 734 #define PCRF_AB_SLOT_PWR_LIM_SCL_LBN 15 735 #define PCRF_AB_SLOT_PWR_LIM_SCL_WIDTH 2 736 #define PCRF_AB_SLOT_PWR_LIM_VAL_LBN 7 737 #define PCRF_AB_SLOT_PWR_LIM_VAL_WIDTH 8 738 #define PCRF_AB_SLOT_HP_CAP_LBN 6 739 #define PCRF_AB_SLOT_HP_CAP_WIDTH 1 740 #define PCRF_AB_SLOT_HP_SURP_LBN 5 741 #define PCRF_AB_SLOT_HP_SURP_WIDTH 1 742 #define PCRF_AB_SLOT_PWR_IND_PRST_LBN 4 743 #define PCRF_AB_SLOT_PWR_IND_PRST_WIDTH 1 744 #define PCRF_AB_SLOT_ATTN_IND_PRST_LBN 3 745 #define PCRF_AB_SLOT_ATTN_IND_PRST_WIDTH 1 746 #define PCRF_AB_SLOT_MRL_SENS_PRST_LBN 2 747 #define PCRF_AB_SLOT_MRL_SENS_PRST_WIDTH 1 748 #define PCRF_AB_SLOT_PWR_CTL_PRST_LBN 1 749 #define PCRF_AB_SLOT_PWR_CTL_PRST_WIDTH 1 750 #define PCRF_AB_SLOT_ATTN_BUT_PRST_LBN 0 751 #define PCRF_AB_SLOT_ATTN_BUT_PRST_WIDTH 1 752 753 /* 754 * PC_SLOT_CTL_REG(16bit): 755 * PCIe slot control register 756 */ 757 758 #define PCR_AB_SLOT_CTL_REG 0x00000078 759 /* falcona0,falconb0=pci_f0_config */ 760 761 #define PCRF_AB_SLOT_PWR_CTLR_CTL_LBN 10 762 #define PCRF_AB_SLOT_PWR_CTLR_CTL_WIDTH 1 763 #define PCRF_AB_SLOT_PWR_IND_CTL_LBN 8 764 #define PCRF_AB_SLOT_PWR_IND_CTL_WIDTH 2 765 #define PCRF_AB_SLOT_ATT_IND_CTL_LBN 6 766 #define PCRF_AB_SLOT_ATT_IND_CTL_WIDTH 2 767 #define PCRF_AB_SLOT_HP_INT_EN_LBN 5 768 #define PCRF_AB_SLOT_HP_INT_EN_WIDTH 1 769 #define PCRF_AB_SLOT_CMD_COMP_INT_EN_LBN 4 770 #define PCRF_AB_SLOT_CMD_COMP_INT_EN_WIDTH 1 771 #define PCRF_AB_SLOT_PRES_DET_CHG_EN_LBN 3 772 #define PCRF_AB_SLOT_PRES_DET_CHG_EN_WIDTH 1 773 #define PCRF_AB_SLOT_MRL_SENS_CHG_EN_LBN 2 774 #define PCRF_AB_SLOT_MRL_SENS_CHG_EN_WIDTH 1 775 #define PCRF_AB_SLOT_PWR_FLTDET_EN_LBN 1 776 #define PCRF_AB_SLOT_PWR_FLTDET_EN_WIDTH 1 777 #define PCRF_AB_SLOT_ATTN_BUT_EN_LBN 0 778 #define PCRF_AB_SLOT_ATTN_BUT_EN_WIDTH 1 779 780 /* 781 * PC_SLOT_STAT_REG(16bit): 782 * PCIe slot status register 783 */ 784 785 #define PCR_AB_SLOT_STAT_REG 0x0000007a 786 /* falcona0,falconb0=pci_f0_config */ 787 788 #define PCRF_AB_PRES_DET_ST_LBN 6 789 #define PCRF_AB_PRES_DET_ST_WIDTH 1 790 #define PCRF_AB_MRL_SENS_ST_LBN 5 791 #define PCRF_AB_MRL_SENS_ST_WIDTH 1 792 #define PCRF_AB_SLOT_PWR_IND_LBN 4 793 #define PCRF_AB_SLOT_PWR_IND_WIDTH 1 794 #define PCRF_AB_SLOT_ATTN_IND_LBN 3 795 #define PCRF_AB_SLOT_ATTN_IND_WIDTH 1 796 #define PCRF_AB_SLOT_MRL_SENS_LBN 2 797 #define PCRF_AB_SLOT_MRL_SENS_WIDTH 1 798 #define PCRF_AB_PWR_FLTDET_LBN 1 799 #define PCRF_AB_PWR_FLTDET_WIDTH 1 800 #define PCRF_AB_ATTN_BUTDET_LBN 0 801 #define PCRF_AB_ATTN_BUTDET_WIDTH 1 802 803 /* 804 * PC_MSIX_CAP_ID_REG(8bit): 805 * MSIX Capability ID 806 */ 807 808 #define PCR_BB_MSIX_CAP_ID_REG 0x00000090 809 /* falconb0=pci_f0_config */ 810 811 #define PCR_CZ_MSIX_CAP_ID_REG 0x000000b0 812 /* sienaa0,hunta0=pci_f0_config */ 813 814 #define PCRF_BZ_MSIX_CAP_ID_LBN 0 815 #define PCRF_BZ_MSIX_CAP_ID_WIDTH 8 816 817 /* 818 * PC_MSIX_NXT_PTR_REG(8bit): 819 * MSIX Capability Next Capability Ptr 820 */ 821 822 #define PCR_BB_MSIX_NXT_PTR_REG 0x00000091 823 /* falconb0=pci_f0_config */ 824 825 #define PCR_CZ_MSIX_NXT_PTR_REG 0x000000b1 826 /* sienaa0,hunta0=pci_f0_config */ 827 828 #define PCRF_BZ_MSIX_NXT_PTR_LBN 0 829 #define PCRF_BZ_MSIX_NXT_PTR_WIDTH 8 830 831 /* 832 * PC_MSIX_CTL_REG(16bit): 833 * MSIX control register 834 */ 835 836 #define PCR_BB_MSIX_CTL_REG 0x00000092 837 /* falconb0=pci_f0_config */ 838 839 #define PCR_CZ_MSIX_CTL_REG 0x000000b2 840 /* sienaa0,hunta0=pci_f0_config */ 841 842 #define PCRF_BZ_MSIX_EN_LBN 15 843 #define PCRF_BZ_MSIX_EN_WIDTH 1 844 #define PCRF_BZ_MSIX_FUNC_MASK_LBN 14 845 #define PCRF_BZ_MSIX_FUNC_MASK_WIDTH 1 846 #define PCRF_BZ_MSIX_TBL_SIZE_LBN 0 847 #define PCRF_BZ_MSIX_TBL_SIZE_WIDTH 11 848 849 /* 850 * PC_MSIX_TBL_BASE_REG(32bit): 851 * MSIX Capability Vector Table Base 852 */ 853 854 #define PCR_BB_MSIX_TBL_BASE_REG 0x00000094 855 /* falconb0=pci_f0_config */ 856 857 #define PCR_CZ_MSIX_TBL_BASE_REG 0x000000b4 858 /* sienaa0,hunta0=pci_f0_config */ 859 860 #define PCRF_BZ_MSIX_TBL_OFF_LBN 3 861 #define PCRF_BZ_MSIX_TBL_OFF_WIDTH 29 862 #define PCRF_BZ_MSIX_TBL_BIR_LBN 0 863 #define PCRF_BZ_MSIX_TBL_BIR_WIDTH 3 864 865 /* 866 * PC_DEV_CAP2_REG(32bit): 867 * PCIe Device Capabilities 2 868 */ 869 870 #define PCR_CZ_DEV_CAP2_REG 0x00000094 871 /* sienaa0=pci_f0_config,hunta0=pci_f0_config */ 872 873 #define PCRF_DZ_OBFF_SUPPORTED_LBN 18 874 #define PCRF_DZ_OBFF_SUPPORTED_WIDTH 2 875 #define PCRF_DZ_TPH_CMPL_SUPPORTED_LBN 12 876 #define PCRF_DZ_TPH_CMPL_SUPPORTED_WIDTH 2 877 #define PCRF_DZ_LTR_M_SUPPORTED_LBN 11 878 #define PCRF_DZ_LTR_M_SUPPORTED_WIDTH 1 879 #define PCRF_CC_CMPL_TIMEOUT_DIS_LBN 4 880 #define PCRF_CC_CMPL_TIMEOUT_DIS_WIDTH 1 881 #define PCRF_DZ_CMPL_TIMEOUT_DIS_SUPPORTED_LBN 4 882 #define PCRF_DZ_CMPL_TIMEOUT_DIS_SUPPORTED_WIDTH 1 883 #define PCRF_CZ_CMPL_TIMEOUT_LBN 0 884 #define PCRF_CZ_CMPL_TIMEOUT_WIDTH 4 885 #define PCFE_CZ_CMPL_TIMEOUT_17000_TO_6400MS 14 886 #define PCFE_CZ_CMPL_TIMEOUT_4000_TO_1300MS 13 887 #define PCFE_CZ_CMPL_TIMEOUT_1000_TO_3500MS 10 888 #define PCFE_CZ_CMPL_TIMEOUT_260_TO_900MS 9 889 #define PCFE_CZ_CMPL_TIMEOUT_65_TO_210MS 6 890 #define PCFE_CZ_CMPL_TIMEOUT_16_TO_55MS 5 891 #define PCFE_CZ_CMPL_TIMEOUT_1_TO_10MS 2 892 #define PCFE_CZ_CMPL_TIMEOUT_50_TO_100US 1 893 #define PCFE_CZ_CMPL_TIMEOUT_DEFAULT 0 894 895 /* 896 * PC_DEV_CTL2_REG(16bit): 897 * PCIe Device Control 2 898 */ 899 900 #define PCR_CZ_DEV_CTL2_REG 0x00000098 901 /* sienaa0,hunta0=pci_f0_config */ 902 903 #define PCRF_DZ_OBFF_ENABLE_LBN 13 904 #define PCRF_DZ_OBFF_ENABLE_WIDTH 2 905 #define PCRF_DZ_LTR_ENABLE_LBN 10 906 #define PCRF_DZ_LTR_ENABLE_WIDTH 1 907 #define PCRF_DZ_IDO_COMPLETION_ENABLE_LBN 9 908 #define PCRF_DZ_IDO_COMPLETION_ENABLE_WIDTH 1 909 #define PCRF_DZ_IDO_REQUEST_ENABLE_LBN 8 910 #define PCRF_DZ_IDO_REQUEST_ENABLE_WIDTH 1 911 #define PCRF_CZ_CMPL_TIMEOUT_DIS_CTL_LBN 4 912 #define PCRF_CZ_CMPL_TIMEOUT_DIS_CTL_WIDTH 1 913 #define PCRF_CZ_CMPL_TIMEOUT_CTL_LBN 0 914 #define PCRF_CZ_CMPL_TIMEOUT_CTL_WIDTH 4 915 916 /* 917 * PC_MSIX_PBA_BASE_REG(32bit): 918 * MSIX Capability PBA Base 919 */ 920 921 #define PCR_BB_MSIX_PBA_BASE_REG 0x00000098 922 /* falconb0=pci_f0_config */ 923 924 #define PCR_CZ_MSIX_PBA_BASE_REG 0x000000b8 925 /* sienaa0,hunta0=pci_f0_config */ 926 927 #define PCRF_BZ_MSIX_PBA_OFF_LBN 3 928 #define PCRF_BZ_MSIX_PBA_OFF_WIDTH 29 929 #define PCRF_BZ_MSIX_PBA_BIR_LBN 0 930 #define PCRF_BZ_MSIX_PBA_BIR_WIDTH 3 931 932 /* 933 * PC_LNK_CAP2_REG(32bit): 934 * PCIe Link Capability 2 935 */ 936 937 #define PCR_DZ_LNK_CAP2_REG 0x0000009c 938 /* hunta0=pci_f0_config */ 939 940 #define PCRF_DZ_LNK_SPEED_SUP_LBN 1 941 #define PCRF_DZ_LNK_SPEED_SUP_WIDTH 7 942 943 /* 944 * PC_LNK_CTL2_REG(16bit): 945 * PCIe Link Control 2 946 */ 947 948 #define PCR_CZ_LNK_CTL2_REG 0x000000a0 949 /* sienaa0,hunta0=pci_f0_config */ 950 951 #define PCRF_CZ_POLLING_DEEMPH_LVL_LBN 12 952 #define PCRF_CZ_POLLING_DEEMPH_LVL_WIDTH 1 953 #define PCRF_CZ_COMPLIANCE_SOS_CTL_LBN 11 954 #define PCRF_CZ_COMPLIANCE_SOS_CTL_WIDTH 1 955 #define PCRF_CZ_ENTER_MODIFIED_COMPLIANCE_CTL_LBN 10 956 #define PCRF_CZ_ENTER_MODIFIED_COMPLIANCE_CTL_WIDTH 1 957 #define PCRF_CZ_TRANSMIT_MARGIN_LBN 7 958 #define PCRF_CZ_TRANSMIT_MARGIN_WIDTH 3 959 #define PCRF_CZ_SELECT_DEEMPH_LBN 6 960 #define PCRF_CZ_SELECT_DEEMPH_WIDTH 1 961 #define PCRF_CZ_HW_AUTONOMOUS_SPEED_DIS_LBN 5 962 #define PCRF_CZ_HW_AUTONOMOUS_SPEED_DIS_WIDTH 1 963 #define PCRF_CZ_ENTER_COMPLIANCE_CTL_LBN 4 964 #define PCRF_CZ_ENTER_COMPLIANCE_CTL_WIDTH 1 965 #define PCRF_CZ_TGT_LNK_SPEED_CTL_LBN 0 966 #define PCRF_CZ_TGT_LNK_SPEED_CTL_WIDTH 4 967 #define PCFE_DZ_LCTL2_TGT_SPEED_GEN3 3 968 #define PCFE_DZ_LCTL2_TGT_SPEED_GEN2 2 969 #define PCFE_DZ_LCTL2_TGT_SPEED_GEN1 1 970 971 /* 972 * PC_LNK_STAT2_REG(16bit): 973 * PCIe Link Status 2 974 */ 975 976 #define PCR_CZ_LNK_STAT2_REG 0x000000a2 977 /* sienaa0,hunta0=pci_f0_config */ 978 979 #define PCRF_CZ_CURRENT_DEEMPH_LBN 0 980 #define PCRF_CZ_CURRENT_DEEMPH_WIDTH 1 981 982 /* 983 * PC_VPD_CAP_ID_REG(8bit): 984 * VPD data register 985 */ 986 987 #define PCR_AB_VPD_CAP_ID_REG 0x000000b0 988 /* falcona0,falconb0=pci_f0_config */ 989 990 #define PCRF_AB_VPD_CAP_ID_LBN 0 991 #define PCRF_AB_VPD_CAP_ID_WIDTH 8 992 993 /* 994 * PC_VPD_NXT_PTR_REG(8bit): 995 * VPD next item pointer 996 */ 997 998 #define PCR_AB_VPD_NXT_PTR_REG 0x000000b1 999 /* falcona0,falconb0=pci_f0_config */ 1000 1001 #define PCRF_AB_VPD_NXT_PTR_LBN 0 1002 #define PCRF_AB_VPD_NXT_PTR_WIDTH 8 1003 1004 /* 1005 * PC_VPD_ADDR_REG(16bit): 1006 * VPD address register 1007 */ 1008 1009 #define PCR_AB_VPD_ADDR_REG 0x000000b2 1010 /* falcona0,falconb0=pci_f0_config */ 1011 1012 #define PCRF_AB_VPD_FLAG_LBN 15 1013 #define PCRF_AB_VPD_FLAG_WIDTH 1 1014 #define PCRF_AB_VPD_ADDR_LBN 0 1015 #define PCRF_AB_VPD_ADDR_WIDTH 15 1016 1017 /* 1018 * PC_VPD_CAP_DATA_REG(32bit): 1019 * documentation to be written for sum_PC_VPD_CAP_DATA_REG 1020 */ 1021 1022 #define PCR_AB_VPD_CAP_DATA_REG 0x000000b4 1023 /* falcona0,falconb0=pci_f0_config */ 1024 1025 #define PCR_CZ_VPD_CAP_DATA_REG 0x000000d4 1026 /* sienaa0,hunta0=pci_f0_config */ 1027 1028 #define PCRF_AZ_VPD_DATA_LBN 0 1029 #define PCRF_AZ_VPD_DATA_WIDTH 32 1030 1031 /* 1032 * PC_VPD_CAP_CTL_REG(8bit): 1033 * VPD control and capabilities register 1034 */ 1035 1036 #define PCR_CZ_VPD_CAP_CTL_REG 0x000000d0 1037 /* sienaa0,hunta0=pci_f0_config */ 1038 1039 #define PCRF_CZ_VPD_FLAG_LBN 31 1040 #define PCRF_CZ_VPD_FLAG_WIDTH 1 1041 #define PCRF_CZ_VPD_ADDR_LBN 16 1042 #define PCRF_CZ_VPD_ADDR_WIDTH 15 1043 #define PCRF_CZ_VPD_NXT_PTR_LBN 8 1044 #define PCRF_CZ_VPD_NXT_PTR_WIDTH 8 1045 #define PCRF_CZ_VPD_CAP_ID_LBN 0 1046 #define PCRF_CZ_VPD_CAP_ID_WIDTH 8 1047 1048 /* 1049 * PC_AER_CAP_HDR_REG(32bit): 1050 * AER capability header register 1051 */ 1052 1053 #define PCR_AZ_AER_CAP_HDR_REG 0x00000100 1054 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 1055 1056 #define PCRF_AZ_AERCAPHDR_NXT_PTR_LBN 20 1057 #define PCRF_AZ_AERCAPHDR_NXT_PTR_WIDTH 12 1058 #define PCRF_AZ_AERCAPHDR_VER_LBN 16 1059 #define PCRF_AZ_AERCAPHDR_VER_WIDTH 4 1060 #define PCRF_AZ_AERCAPHDR_ID_LBN 0 1061 #define PCRF_AZ_AERCAPHDR_ID_WIDTH 16 1062 1063 /* 1064 * PC_AER_UNCORR_ERR_STAT_REG(32bit): 1065 * AER Uncorrectable error status register 1066 */ 1067 1068 #define PCR_AZ_AER_UNCORR_ERR_STAT_REG 0x00000104 1069 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 1070 1071 #define PCRF_AZ_UNSUPT_REQ_ERR_STAT_LBN 20 1072 #define PCRF_AZ_UNSUPT_REQ_ERR_STAT_WIDTH 1 1073 #define PCRF_AZ_ECRC_ERR_STAT_LBN 19 1074 #define PCRF_AZ_ECRC_ERR_STAT_WIDTH 1 1075 #define PCRF_AZ_MALF_TLP_STAT_LBN 18 1076 #define PCRF_AZ_MALF_TLP_STAT_WIDTH 1 1077 #define PCRF_AZ_RX_OVF_STAT_LBN 17 1078 #define PCRF_AZ_RX_OVF_STAT_WIDTH 1 1079 #define PCRF_AZ_UNEXP_COMP_STAT_LBN 16 1080 #define PCRF_AZ_UNEXP_COMP_STAT_WIDTH 1 1081 #define PCRF_AZ_COMP_ABRT_STAT_LBN 15 1082 #define PCRF_AZ_COMP_ABRT_STAT_WIDTH 1 1083 #define PCRF_AZ_COMP_TIMEOUT_STAT_LBN 14 1084 #define PCRF_AZ_COMP_TIMEOUT_STAT_WIDTH 1 1085 #define PCRF_AZ_FC_PROTO_ERR_STAT_LBN 13 1086 #define PCRF_AZ_FC_PROTO_ERR_STAT_WIDTH 1 1087 #define PCRF_AZ_PSON_TLP_STAT_LBN 12 1088 #define PCRF_AZ_PSON_TLP_STAT_WIDTH 1 1089 #define PCRF_AZ_DL_PROTO_ERR_STAT_LBN 4 1090 #define PCRF_AZ_DL_PROTO_ERR_STAT_WIDTH 1 1091 #define PCRF_AB_TRAIN_ERR_STAT_LBN 0 1092 #define PCRF_AB_TRAIN_ERR_STAT_WIDTH 1 1093 1094 /* 1095 * PC_AER_UNCORR_ERR_MASK_REG(32bit): 1096 * AER Uncorrectable error mask register 1097 */ 1098 1099 #define PCR_AZ_AER_UNCORR_ERR_MASK_REG 0x00000108 1100 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 1101 1102 #define PCRF_DZ_ATOMIC_OP_EGR_BLOCKED_MASK_LBN 24 1103 #define PCRF_DZ_ATOMIC_OP_EGR_BLOCKED_MASK_WIDTH 1 1104 #define PCRF_DZ_UNCORR_INT_ERR_MASK_LBN 22 1105 #define PCRF_DZ_UNCORR_INT_ERR_MASK_WIDTH 1 1106 #define PCRF_AZ_UNSUPT_REQ_ERR_MASK_LBN 20 1107 #define PCRF_AZ_UNSUPT_REQ_ERR_MASK_WIDTH 1 1108 #define PCRF_AZ_ECRC_ERR_MASK_LBN 19 1109 #define PCRF_AZ_ECRC_ERR_MASK_WIDTH 1 1110 #define PCRF_AZ_MALF_TLP_MASK_LBN 18 1111 #define PCRF_AZ_MALF_TLP_MASK_WIDTH 1 1112 #define PCRF_AZ_RX_OVF_MASK_LBN 17 1113 #define PCRF_AZ_RX_OVF_MASK_WIDTH 1 1114 #define PCRF_AZ_UNEXP_COMP_MASK_LBN 16 1115 #define PCRF_AZ_UNEXP_COMP_MASK_WIDTH 1 1116 #define PCRF_AZ_COMP_ABRT_MASK_LBN 15 1117 #define PCRF_AZ_COMP_ABRT_MASK_WIDTH 1 1118 #define PCRF_AZ_COMP_TIMEOUT_MASK_LBN 14 1119 #define PCRF_AZ_COMP_TIMEOUT_MASK_WIDTH 1 1120 #define PCRF_AZ_FC_PROTO_ERR_MASK_LBN 13 1121 #define PCRF_AZ_FC_PROTO_ERR_MASK_WIDTH 1 1122 #define PCRF_AZ_PSON_TLP_MASK_LBN 12 1123 #define PCRF_AZ_PSON_TLP_MASK_WIDTH 1 1124 #define PCRF_AZ_DL_PROTO_ERR_MASK_LBN 4 1125 #define PCRF_AZ_DL_PROTO_ERR_MASK_WIDTH 1 1126 #define PCRF_AB_TRAIN_ERR_MASK_LBN 0 1127 #define PCRF_AB_TRAIN_ERR_MASK_WIDTH 1 1128 1129 /* 1130 * PC_AER_UNCORR_ERR_SEV_REG(32bit): 1131 * AER Uncorrectable error severity register 1132 */ 1133 1134 #define PCR_AZ_AER_UNCORR_ERR_SEV_REG 0x0000010c 1135 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 1136 1137 #define PCRF_AZ_UNSUPT_REQ_ERR_SEV_LBN 20 1138 #define PCRF_AZ_UNSUPT_REQ_ERR_SEV_WIDTH 1 1139 #define PCRF_AZ_ECRC_ERR_SEV_LBN 19 1140 #define PCRF_AZ_ECRC_ERR_SEV_WIDTH 1 1141 #define PCRF_AZ_MALF_TLP_SEV_LBN 18 1142 #define PCRF_AZ_MALF_TLP_SEV_WIDTH 1 1143 #define PCRF_AZ_RX_OVF_SEV_LBN 17 1144 #define PCRF_AZ_RX_OVF_SEV_WIDTH 1 1145 #define PCRF_AZ_UNEXP_COMP_SEV_LBN 16 1146 #define PCRF_AZ_UNEXP_COMP_SEV_WIDTH 1 1147 #define PCRF_AZ_COMP_ABRT_SEV_LBN 15 1148 #define PCRF_AZ_COMP_ABRT_SEV_WIDTH 1 1149 #define PCRF_AZ_COMP_TIMEOUT_SEV_LBN 14 1150 #define PCRF_AZ_COMP_TIMEOUT_SEV_WIDTH 1 1151 #define PCRF_AZ_FC_PROTO_ERR_SEV_LBN 13 1152 #define PCRF_AZ_FC_PROTO_ERR_SEV_WIDTH 1 1153 #define PCRF_AZ_PSON_TLP_SEV_LBN 12 1154 #define PCRF_AZ_PSON_TLP_SEV_WIDTH 1 1155 #define PCRF_AZ_DL_PROTO_ERR_SEV_LBN 4 1156 #define PCRF_AZ_DL_PROTO_ERR_SEV_WIDTH 1 1157 #define PCRF_AB_TRAIN_ERR_SEV_LBN 0 1158 #define PCRF_AB_TRAIN_ERR_SEV_WIDTH 1 1159 1160 /* 1161 * PC_AER_CORR_ERR_STAT_REG(32bit): 1162 * AER Correctable error status register 1163 */ 1164 1165 #define PCR_AZ_AER_CORR_ERR_STAT_REG 0x00000110 1166 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 1167 1168 #define PCRF_CZ_ADVSY_NON_FATAL_STAT_LBN 13 1169 #define PCRF_CZ_ADVSY_NON_FATAL_STAT_WIDTH 1 1170 #define PCRF_AZ_RPLY_TMR_TOUT_STAT_LBN 12 1171 #define PCRF_AZ_RPLY_TMR_TOUT_STAT_WIDTH 1 1172 #define PCRF_AZ_RPLAY_NUM_RO_STAT_LBN 8 1173 #define PCRF_AZ_RPLAY_NUM_RO_STAT_WIDTH 1 1174 #define PCRF_AZ_BAD_DLLP_STAT_LBN 7 1175 #define PCRF_AZ_BAD_DLLP_STAT_WIDTH 1 1176 #define PCRF_AZ_BAD_TLP_STAT_LBN 6 1177 #define PCRF_AZ_BAD_TLP_STAT_WIDTH 1 1178 #define PCRF_AZ_RX_ERR_STAT_LBN 0 1179 #define PCRF_AZ_RX_ERR_STAT_WIDTH 1 1180 1181 /* 1182 * PC_AER_CORR_ERR_MASK_REG(32bit): 1183 * AER Correctable error status register 1184 */ 1185 1186 #define PCR_AZ_AER_CORR_ERR_MASK_REG 0x00000114 1187 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 1188 1189 #define PCRF_CZ_ADVSY_NON_FATAL_MASK_LBN 13 1190 #define PCRF_CZ_ADVSY_NON_FATAL_MASK_WIDTH 1 1191 #define PCRF_AZ_RPLY_TMR_TOUT_MASK_LBN 12 1192 #define PCRF_AZ_RPLY_TMR_TOUT_MASK_WIDTH 1 1193 #define PCRF_AZ_RPLAY_NUM_RO_MASK_LBN 8 1194 #define PCRF_AZ_RPLAY_NUM_RO_MASK_WIDTH 1 1195 #define PCRF_AZ_BAD_DLLP_MASK_LBN 7 1196 #define PCRF_AZ_BAD_DLLP_MASK_WIDTH 1 1197 #define PCRF_AZ_BAD_TLP_MASK_LBN 6 1198 #define PCRF_AZ_BAD_TLP_MASK_WIDTH 1 1199 #define PCRF_AZ_RX_ERR_MASK_LBN 0 1200 #define PCRF_AZ_RX_ERR_MASK_WIDTH 1 1201 1202 /* 1203 * PC_AER_CAP_CTL_REG(32bit): 1204 * AER capability and control register 1205 */ 1206 1207 #define PCR_AZ_AER_CAP_CTL_REG 0x00000118 1208 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 1209 1210 #define PCRF_AZ_ECRC_CHK_EN_LBN 8 1211 #define PCRF_AZ_ECRC_CHK_EN_WIDTH 1 1212 #define PCRF_AZ_ECRC_CHK_CAP_LBN 7 1213 #define PCRF_AZ_ECRC_CHK_CAP_WIDTH 1 1214 #define PCRF_AZ_ECRC_GEN_EN_LBN 6 1215 #define PCRF_AZ_ECRC_GEN_EN_WIDTH 1 1216 #define PCRF_AZ_ECRC_GEN_CAP_LBN 5 1217 #define PCRF_AZ_ECRC_GEN_CAP_WIDTH 1 1218 #define PCRF_AZ_1ST_ERR_PTR_LBN 0 1219 #define PCRF_AZ_1ST_ERR_PTR_WIDTH 5 1220 1221 /* 1222 * PC_AER_HDR_LOG_REG(128bit): 1223 * AER Header log register 1224 */ 1225 1226 #define PCR_AZ_AER_HDR_LOG_REG 0x0000011c 1227 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 1228 1229 #define PCRF_AZ_HDR_LOG_LBN 0 1230 #define PCRF_AZ_HDR_LOG_WIDTH 128 1231 1232 /* 1233 * PC_DEVSN_CAP_HDR_REG(32bit): 1234 * Device serial number capability header register 1235 */ 1236 1237 #define PCR_CZ_DEVSN_CAP_HDR_REG 0x00000140 1238 /* sienaa0,hunta0=pci_f0_config */ 1239 1240 #define PCRF_CZ_DEVSNCAPHDR_NXT_PTR_LBN 20 1241 #define PCRF_CZ_DEVSNCAPHDR_NXT_PTR_WIDTH 12 1242 #define PCRF_CZ_DEVSNCAPHDR_VER_LBN 16 1243 #define PCRF_CZ_DEVSNCAPHDR_VER_WIDTH 4 1244 #define PCRF_CZ_DEVSNCAPHDR_ID_LBN 0 1245 #define PCRF_CZ_DEVSNCAPHDR_ID_WIDTH 16 1246 1247 /* 1248 * PC_DEVSN_DWORD0_REG(32bit): 1249 * Device serial number DWORD0 1250 */ 1251 1252 #define PCR_CZ_DEVSN_DWORD0_REG 0x00000144 1253 /* sienaa0,hunta0=pci_f0_config */ 1254 1255 #define PCRF_CZ_DEVSN_DWORD0_LBN 0 1256 #define PCRF_CZ_DEVSN_DWORD0_WIDTH 32 1257 1258 /* 1259 * PC_DEVSN_DWORD1_REG(32bit): 1260 * Device serial number DWORD0 1261 */ 1262 1263 #define PCR_CZ_DEVSN_DWORD1_REG 0x00000148 1264 /* sienaa0,hunta0=pci_f0_config */ 1265 1266 #define PCRF_CZ_DEVSN_DWORD1_LBN 0 1267 #define PCRF_CZ_DEVSN_DWORD1_WIDTH 32 1268 1269 /* 1270 * PC_ARI_CAP_HDR_REG(32bit): 1271 * ARI capability header register 1272 */ 1273 1274 #define PCR_CZ_ARI_CAP_HDR_REG 0x00000150 1275 /* sienaa0,hunta0=pci_f0_config */ 1276 1277 #define PCRF_CZ_ARICAPHDR_NXT_PTR_LBN 20 1278 #define PCRF_CZ_ARICAPHDR_NXT_PTR_WIDTH 12 1279 #define PCRF_CZ_ARICAPHDR_VER_LBN 16 1280 #define PCRF_CZ_ARICAPHDR_VER_WIDTH 4 1281 #define PCRF_CZ_ARICAPHDR_ID_LBN 0 1282 #define PCRF_CZ_ARICAPHDR_ID_WIDTH 16 1283 1284 /* 1285 * PC_ARI_CAP_REG(16bit): 1286 * ARI Capabilities 1287 */ 1288 1289 #define PCR_CZ_ARI_CAP_REG 0x00000154 1290 /* sienaa0,hunta0=pci_f0_config */ 1291 1292 #define PCRF_CZ_ARI_NXT_FN_NUM_LBN 8 1293 #define PCRF_CZ_ARI_NXT_FN_NUM_WIDTH 8 1294 #define PCRF_CZ_ARI_ACS_FNGRP_CAP_LBN 1 1295 #define PCRF_CZ_ARI_ACS_FNGRP_CAP_WIDTH 1 1296 #define PCRF_CZ_ARI_MFVC_FNGRP_CAP_LBN 0 1297 #define PCRF_CZ_ARI_MFVC_FNGRP_CAP_WIDTH 1 1298 1299 /* 1300 * PC_ARI_CTL_REG(16bit): 1301 * ARI Control 1302 */ 1303 1304 #define PCR_CZ_ARI_CTL_REG 0x00000156 1305 /* sienaa0,hunta0=pci_f0_config */ 1306 1307 #define PCRF_CZ_ARI_FN_GRP_LBN 4 1308 #define PCRF_CZ_ARI_FN_GRP_WIDTH 3 1309 #define PCRF_CZ_ARI_ACS_FNGRP_EN_LBN 1 1310 #define PCRF_CZ_ARI_ACS_FNGRP_EN_WIDTH 1 1311 #define PCRF_CZ_ARI_MFVC_FNGRP_EN_LBN 0 1312 #define PCRF_CZ_ARI_MFVC_FNGRP_EN_WIDTH 1 1313 1314 /* 1315 * PC_SEC_PCIE_CAP_REG(32bit): 1316 * Secondary PCIE Capability Register 1317 */ 1318 1319 #define PCR_DZ_SEC_PCIE_CAP_REG 0x00000160 1320 /* hunta0=pci_f0_config */ 1321 1322 #define PCRF_DZ_SEC_NXT_PTR_LBN 20 1323 #define PCRF_DZ_SEC_NXT_PTR_WIDTH 12 1324 #define PCRF_DZ_SEC_VERSION_LBN 16 1325 #define PCRF_DZ_SEC_VERSION_WIDTH 4 1326 #define PCRF_DZ_SEC_EXT_CAP_ID_LBN 0 1327 #define PCRF_DZ_SEC_EXT_CAP_ID_WIDTH 16 1328 1329 /* 1330 * PC_SRIOV_CAP_HDR_REG(32bit): 1331 * SRIOV capability header register 1332 */ 1333 1334 #define PCR_CC_SRIOV_CAP_HDR_REG 0x00000160 1335 /* sienaa0=pci_f0_config */ 1336 1337 #define PCR_DZ_SRIOV_CAP_HDR_REG 0x00000180 1338 /* hunta0=pci_f0_config */ 1339 1340 #define PCRF_CZ_SRIOVCAPHDR_NXT_PTR_LBN 20 1341 #define PCRF_CZ_SRIOVCAPHDR_NXT_PTR_WIDTH 12 1342 #define PCRF_CZ_SRIOVCAPHDR_VER_LBN 16 1343 #define PCRF_CZ_SRIOVCAPHDR_VER_WIDTH 4 1344 #define PCRF_CZ_SRIOVCAPHDR_ID_LBN 0 1345 #define PCRF_CZ_SRIOVCAPHDR_ID_WIDTH 16 1346 1347 /* 1348 * PC_SRIOV_CAP_REG(32bit): 1349 * SRIOV Capabilities 1350 */ 1351 1352 #define PCR_CC_SRIOV_CAP_REG 0x00000164 1353 /* sienaa0=pci_f0_config */ 1354 1355 #define PCR_DZ_SRIOV_CAP_REG 0x00000184 1356 /* hunta0=pci_f0_config */ 1357 1358 #define PCRF_CZ_VF_MIGR_INT_MSG_NUM_LBN 21 1359 #define PCRF_CZ_VF_MIGR_INT_MSG_NUM_WIDTH 11 1360 #define PCRF_DZ_VF_ARI_CAP_PRESV_LBN 1 1361 #define PCRF_DZ_VF_ARI_CAP_PRESV_WIDTH 1 1362 #define PCRF_CZ_VF_MIGR_CAP_LBN 0 1363 #define PCRF_CZ_VF_MIGR_CAP_WIDTH 1 1364 1365 /* 1366 * PC_LINK_CONTROL3_REG(32bit): 1367 * Link Control 3. 1368 */ 1369 1370 #define PCR_DZ_LINK_CONTROL3_REG 0x00000164 1371 /* hunta0=pci_f0_config */ 1372 1373 #define PCRF_DZ_LINK_EQ_INT_EN_LBN 1 1374 #define PCRF_DZ_LINK_EQ_INT_EN_WIDTH 1 1375 #define PCRF_DZ_PERFORM_EQL_LBN 0 1376 #define PCRF_DZ_PERFORM_EQL_WIDTH 1 1377 1378 /* 1379 * PC_LANE_ERROR_STAT_REG(32bit): 1380 * Lane Error Status Register. 1381 */ 1382 1383 #define PCR_DZ_LANE_ERROR_STAT_REG 0x00000168 1384 /* hunta0=pci_f0_config */ 1385 1386 #define PCRF_DZ_LANE_STATUS_LBN 0 1387 #define PCRF_DZ_LANE_STATUS_WIDTH 8 1388 1389 /* 1390 * PC_SRIOV_CTL_REG(16bit): 1391 * SRIOV Control 1392 */ 1393 1394 #define PCR_CC_SRIOV_CTL_REG 0x00000168 1395 /* sienaa0=pci_f0_config */ 1396 1397 #define PCR_DZ_SRIOV_CTL_REG 0x00000188 1398 /* hunta0=pci_f0_config */ 1399 1400 #define PCRF_CZ_VF_ARI_CAP_HRCHY_LBN 4 1401 #define PCRF_CZ_VF_ARI_CAP_HRCHY_WIDTH 1 1402 #define PCRF_CZ_VF_MSE_LBN 3 1403 #define PCRF_CZ_VF_MSE_WIDTH 1 1404 #define PCRF_CZ_VF_MIGR_INT_EN_LBN 2 1405 #define PCRF_CZ_VF_MIGR_INT_EN_WIDTH 1 1406 #define PCRF_CZ_VF_MIGR_EN_LBN 1 1407 #define PCRF_CZ_VF_MIGR_EN_WIDTH 1 1408 #define PCRF_CZ_VF_EN_LBN 0 1409 #define PCRF_CZ_VF_EN_WIDTH 1 1410 1411 /* 1412 * PC_SRIOV_STAT_REG(16bit): 1413 * SRIOV Status 1414 */ 1415 1416 #define PCR_CC_SRIOV_STAT_REG 0x0000016a 1417 /* sienaa0=pci_f0_config */ 1418 1419 #define PCR_DZ_SRIOV_STAT_REG 0x0000018a 1420 /* hunta0=pci_f0_config */ 1421 1422 #define PCRF_CZ_VF_MIGR_STAT_LBN 0 1423 #define PCRF_CZ_VF_MIGR_STAT_WIDTH 1 1424 1425 /* 1426 * PC_LANE01_EQU_CONTROL_REG(32bit): 1427 * Lanes 0,1 Equalization Control Register. 1428 */ 1429 1430 #define PCR_DZ_LANE01_EQU_CONTROL_REG 0x0000016c 1431 /* hunta0=pci_f0_config */ 1432 1433 #define PCRF_DZ_LANE1_EQ_CTRL_LBN 16 1434 #define PCRF_DZ_LANE1_EQ_CTRL_WIDTH 16 1435 #define PCRF_DZ_LANE0_EQ_CTRL_LBN 0 1436 #define PCRF_DZ_LANE0_EQ_CTRL_WIDTH 16 1437 1438 /* 1439 * PC_SRIOV_INITIALVFS_REG(16bit): 1440 * SRIOV Initial VFs 1441 */ 1442 1443 #define PCR_CC_SRIOV_INITIALVFS_REG 0x0000016c 1444 /* sienaa0=pci_f0_config */ 1445 1446 #define PCR_DZ_SRIOV_INITIALVFS_REG 0x0000018c 1447 /* hunta0=pci_f0_config */ 1448 1449 #define PCRF_CZ_VF_INITIALVFS_LBN 0 1450 #define PCRF_CZ_VF_INITIALVFS_WIDTH 16 1451 1452 /* 1453 * PC_SRIOV_TOTALVFS_REG(10bit): 1454 * SRIOV Total VFs 1455 */ 1456 1457 #define PCR_CC_SRIOV_TOTALVFS_REG 0x0000016e 1458 /* sienaa0=pci_f0_config */ 1459 1460 #define PCR_DZ_SRIOV_TOTALVFS_REG 0x0000018e 1461 /* hunta0=pci_f0_config */ 1462 1463 #define PCRF_CZ_VF_TOTALVFS_LBN 0 1464 #define PCRF_CZ_VF_TOTALVFS_WIDTH 16 1465 1466 /* 1467 * PC_SRIOV_NUMVFS_REG(16bit): 1468 * SRIOV Number of VFs 1469 */ 1470 1471 #define PCR_CC_SRIOV_NUMVFS_REG 0x00000170 1472 /* sienaa0=pci_f0_config */ 1473 1474 #define PCR_DZ_SRIOV_NUMVFS_REG 0x00000190 1475 /* hunta0=pci_f0_config */ 1476 1477 #define PCRF_CZ_VF_NUMVFS_LBN 0 1478 #define PCRF_CZ_VF_NUMVFS_WIDTH 16 1479 1480 /* 1481 * PC_LANE23_EQU_CONTROL_REG(32bit): 1482 * Lanes 2,3 Equalization Control Register. 1483 */ 1484 1485 #define PCR_DZ_LANE23_EQU_CONTROL_REG 0x00000170 1486 /* hunta0=pci_f0_config */ 1487 1488 #define PCRF_DZ_LANE3_EQ_CTRL_LBN 16 1489 #define PCRF_DZ_LANE3_EQ_CTRL_WIDTH 16 1490 #define PCRF_DZ_LANE2_EQ_CTRL_LBN 0 1491 #define PCRF_DZ_LANE2_EQ_CTRL_WIDTH 16 1492 1493 /* 1494 * PC_SRIOV_FN_DPND_LNK_REG(16bit): 1495 * SRIOV Function dependency link 1496 */ 1497 1498 #define PCR_CC_SRIOV_FN_DPND_LNK_REG 0x00000172 1499 /* sienaa0=pci_f0_config */ 1500 1501 #define PCR_DZ_SRIOV_FN_DPND_LNK_REG 0x00000192 1502 /* hunta0=pci_f0_config */ 1503 1504 #define PCRF_CZ_SRIOV_FN_DPND_LNK_LBN 0 1505 #define PCRF_CZ_SRIOV_FN_DPND_LNK_WIDTH 8 1506 1507 /* 1508 * PC_SRIOV_1STVF_OFFSET_REG(16bit): 1509 * SRIOV First VF Offset 1510 */ 1511 1512 #define PCR_CC_SRIOV_1STVF_OFFSET_REG 0x00000174 1513 /* sienaa0=pci_f0_config */ 1514 1515 #define PCR_DZ_SRIOV_1STVF_OFFSET_REG 0x00000194 1516 /* hunta0=pci_f0_config */ 1517 1518 #define PCRF_CZ_VF_1STVF_OFFSET_LBN 0 1519 #define PCRF_CZ_VF_1STVF_OFFSET_WIDTH 16 1520 1521 /* 1522 * PC_LANE45_EQU_CONTROL_REG(32bit): 1523 * Lanes 4,5 Equalization Control Register. 1524 */ 1525 1526 #define PCR_DZ_LANE45_EQU_CONTROL_REG 0x00000174 1527 /* hunta0=pci_f0_config */ 1528 1529 #define PCRF_DZ_LANE5_EQ_CTRL_LBN 16 1530 #define PCRF_DZ_LANE5_EQ_CTRL_WIDTH 16 1531 #define PCRF_DZ_LANE4_EQ_CTRL_LBN 0 1532 #define PCRF_DZ_LANE4_EQ_CTRL_WIDTH 16 1533 1534 /* 1535 * PC_SRIOV_VFSTRIDE_REG(16bit): 1536 * SRIOV VF Stride 1537 */ 1538 1539 #define PCR_CC_SRIOV_VFSTRIDE_REG 0x00000176 1540 /* sienaa0=pci_f0_config */ 1541 1542 #define PCR_DZ_SRIOV_VFSTRIDE_REG 0x00000196 1543 /* hunta0=pci_f0_config */ 1544 1545 #define PCRF_CZ_VF_VFSTRIDE_LBN 0 1546 #define PCRF_CZ_VF_VFSTRIDE_WIDTH 16 1547 1548 /* 1549 * PC_LANE67_EQU_CONTROL_REG(32bit): 1550 * Lanes 6,7 Equalization Control Register. 1551 */ 1552 1553 #define PCR_DZ_LANE67_EQU_CONTROL_REG 0x00000178 1554 /* hunta0=pci_f0_config */ 1555 1556 #define PCRF_DZ_LANE7_EQ_CTRL_LBN 16 1557 #define PCRF_DZ_LANE7_EQ_CTRL_WIDTH 16 1558 #define PCRF_DZ_LANE6_EQ_CTRL_LBN 0 1559 #define PCRF_DZ_LANE6_EQ_CTRL_WIDTH 16 1560 1561 /* 1562 * PC_SRIOV_DEVID_REG(16bit): 1563 * SRIOV VF Device ID 1564 */ 1565 1566 #define PCR_CC_SRIOV_DEVID_REG 0x0000017a 1567 /* sienaa0=pci_f0_config */ 1568 1569 #define PCR_DZ_SRIOV_DEVID_REG 0x0000019a 1570 /* hunta0=pci_f0_config */ 1571 1572 #define PCRF_CZ_VF_DEVID_LBN 0 1573 #define PCRF_CZ_VF_DEVID_WIDTH 16 1574 1575 /* 1576 * PC_SRIOV_SUP_PAGESZ_REG(16bit): 1577 * SRIOV Supported Page Sizes 1578 */ 1579 1580 #define PCR_CC_SRIOV_SUP_PAGESZ_REG 0x0000017c 1581 /* sienaa0=pci_f0_config */ 1582 1583 #define PCR_DZ_SRIOV_SUP_PAGESZ_REG 0x0000019c 1584 /* hunta0=pci_f0_config */ 1585 1586 #define PCRF_CZ_VF_SUP_PAGESZ_LBN 0 1587 #define PCRF_CZ_VF_SUP_PAGESZ_WIDTH 16 1588 1589 /* 1590 * PC_SRIOV_SYS_PAGESZ_REG(32bit): 1591 * SRIOV System Page Size 1592 */ 1593 1594 #define PCR_CC_SRIOV_SYS_PAGESZ_REG 0x00000180 1595 /* sienaa0=pci_f0_config */ 1596 1597 #define PCR_DZ_SRIOV_SYS_PAGESZ_REG 0x000001a0 1598 /* hunta0=pci_f0_config */ 1599 1600 #define PCRF_CZ_VF_SYS_PAGESZ_LBN 0 1601 #define PCRF_CZ_VF_SYS_PAGESZ_WIDTH 16 1602 1603 /* 1604 * PC_SRIOV_BAR0_REG(32bit): 1605 * SRIOV VF Bar0 1606 */ 1607 1608 #define PCR_CC_SRIOV_BAR0_REG 0x00000184 1609 /* sienaa0=pci_f0_config */ 1610 1611 #define PCR_DZ_SRIOV_BAR0_REG 0x000001a4 1612 /* hunta0=pci_f0_config */ 1613 1614 #define PCRF_CC_VF_BAR_ADDRESS_LBN 0 1615 #define PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 1616 #define PCRF_DZ_VF_BAR0_ADDRESS_LBN 4 1617 #define PCRF_DZ_VF_BAR0_ADDRESS_WIDTH 28 1618 #define PCRF_DZ_VF_BAR0_PREF_LBN 3 1619 #define PCRF_DZ_VF_BAR0_PREF_WIDTH 1 1620 #define PCRF_DZ_VF_BAR0_TYPE_LBN 1 1621 #define PCRF_DZ_VF_BAR0_TYPE_WIDTH 2 1622 #define PCRF_DZ_VF_BAR0_IOM_LBN 0 1623 #define PCRF_DZ_VF_BAR0_IOM_WIDTH 1 1624 1625 /* 1626 * PC_SRIOV_BAR1_REG(32bit): 1627 * SRIOV Bar1 1628 */ 1629 1630 #define PCR_CC_SRIOV_BAR1_REG 0x00000188 1631 /* sienaa0=pci_f0_config */ 1632 1633 #define PCR_DZ_SRIOV_BAR1_REG 0x000001a8 1634 /* hunta0=pci_f0_config */ 1635 1636 /* defined as PCRF_CC_VF_BAR_ADDRESS_LBN 0; */ 1637 /* defined as PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 */ 1638 #define PCRF_DZ_VF_BAR1_ADDRESS_LBN 0 1639 #define PCRF_DZ_VF_BAR1_ADDRESS_WIDTH 32 1640 1641 /* 1642 * PC_SRIOV_BAR2_REG(32bit): 1643 * SRIOV Bar2 1644 */ 1645 1646 #define PCR_CC_SRIOV_BAR2_REG 0x0000018c 1647 /* sienaa0=pci_f0_config */ 1648 1649 #define PCR_DZ_SRIOV_BAR2_REG 0x000001ac 1650 /* hunta0=pci_f0_config */ 1651 1652 /* defined as PCRF_CC_VF_BAR_ADDRESS_LBN 0; */ 1653 /* defined as PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 */ 1654 #define PCRF_DZ_VF_BAR2_ADDRESS_LBN 4 1655 #define PCRF_DZ_VF_BAR2_ADDRESS_WIDTH 28 1656 #define PCRF_DZ_VF_BAR2_PREF_LBN 3 1657 #define PCRF_DZ_VF_BAR2_PREF_WIDTH 1 1658 #define PCRF_DZ_VF_BAR2_TYPE_LBN 1 1659 #define PCRF_DZ_VF_BAR2_TYPE_WIDTH 2 1660 #define PCRF_DZ_VF_BAR2_IOM_LBN 0 1661 #define PCRF_DZ_VF_BAR2_IOM_WIDTH 1 1662 1663 /* 1664 * PC_SRIOV_BAR3_REG(32bit): 1665 * SRIOV Bar3 1666 */ 1667 1668 #define PCR_CC_SRIOV_BAR3_REG 0x00000190 1669 /* sienaa0=pci_f0_config */ 1670 1671 #define PCR_DZ_SRIOV_BAR3_REG 0x000001b0 1672 /* hunta0=pci_f0_config */ 1673 1674 /* defined as PCRF_CC_VF_BAR_ADDRESS_LBN 0; */ 1675 /* defined as PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 */ 1676 #define PCRF_DZ_VF_BAR3_ADDRESS_LBN 0 1677 #define PCRF_DZ_VF_BAR3_ADDRESS_WIDTH 32 1678 1679 /* 1680 * PC_SRIOV_BAR4_REG(32bit): 1681 * SRIOV Bar4 1682 */ 1683 1684 #define PCR_CC_SRIOV_BAR4_REG 0x00000194 1685 /* sienaa0=pci_f0_config */ 1686 1687 #define PCR_DZ_SRIOV_BAR4_REG 0x000001b4 1688 /* hunta0=pci_f0_config */ 1689 1690 /* defined as PCRF_CC_VF_BAR_ADDRESS_LBN 0; */ 1691 /* defined as PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 */ 1692 #define PCRF_DZ_VF_BAR4_ADDRESS_LBN 0 1693 #define PCRF_DZ_VF_BAR4_ADDRESS_WIDTH 32 1694 1695 /* 1696 * PC_SRIOV_BAR5_REG(32bit): 1697 * SRIOV Bar5 1698 */ 1699 1700 #define PCR_CC_SRIOV_BAR5_REG 0x00000198 1701 /* sienaa0=pci_f0_config */ 1702 1703 #define PCR_DZ_SRIOV_BAR5_REG 0x000001b8 1704 /* hunta0=pci_f0_config */ 1705 1706 /* defined as PCRF_CC_VF_BAR_ADDRESS_LBN 0; */ 1707 /* defined as PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 */ 1708 #define PCRF_DZ_VF_BAR5_ADDRESS_LBN 0 1709 #define PCRF_DZ_VF_BAR5_ADDRESS_WIDTH 32 1710 1711 /* 1712 * PC_SRIOV_RSVD_REG(16bit): 1713 * Reserved register 1714 */ 1715 1716 #define PCR_DZ_SRIOV_RSVD_REG 0x00000198 1717 /* hunta0=pci_f0_config */ 1718 1719 #define PCRF_DZ_VF_RSVD_LBN 0 1720 #define PCRF_DZ_VF_RSVD_WIDTH 16 1721 1722 /* 1723 * PC_SRIOV_MIBR_SARRAY_OFFSET_REG(32bit): 1724 * SRIOV VF Migration State Array Offset 1725 */ 1726 1727 #define PCR_CC_SRIOV_MIBR_SARRAY_OFFSET_REG 0x0000019c 1728 /* sienaa0=pci_f0_config */ 1729 1730 #define PCR_DZ_SRIOV_MIBR_SARRAY_OFFSET_REG 0x000001bc 1731 /* hunta0=pci_f0_config */ 1732 1733 #define PCRF_CZ_VF_MIGR_OFFSET_LBN 3 1734 #define PCRF_CZ_VF_MIGR_OFFSET_WIDTH 29 1735 #define PCRF_CZ_VF_MIGR_BIR_LBN 0 1736 #define PCRF_CZ_VF_MIGR_BIR_WIDTH 3 1737 1738 /* 1739 * PC_TPH_CAP_HDR_REG(32bit): 1740 * TPH Capability Header Register 1741 */ 1742 1743 #define PCR_DZ_TPH_CAP_HDR_REG 0x000001c0 1744 /* hunta0=pci_f0_config */ 1745 1746 #define PCRF_DZ_TPH_NXT_PTR_LBN 20 1747 #define PCRF_DZ_TPH_NXT_PTR_WIDTH 12 1748 #define PCRF_DZ_TPH_VERSION_LBN 16 1749 #define PCRF_DZ_TPH_VERSION_WIDTH 4 1750 #define PCRF_DZ_TPH_EXT_CAP_ID_LBN 0 1751 #define PCRF_DZ_TPH_EXT_CAP_ID_WIDTH 16 1752 1753 /* 1754 * PC_TPH_REQ_CAP_REG(32bit): 1755 * TPH Requester Capability Register 1756 */ 1757 1758 #define PCR_DZ_TPH_REQ_CAP_REG 0x000001c4 1759 /* hunta0=pci_f0_config */ 1760 1761 #define PCRF_DZ_ST_TBLE_SIZE_LBN 16 1762 #define PCRF_DZ_ST_TBLE_SIZE_WIDTH 11 1763 #define PCRF_DZ_ST_TBLE_LOC_LBN 9 1764 #define PCRF_DZ_ST_TBLE_LOC_WIDTH 2 1765 #define PCRF_DZ_EXT_TPH_MODE_SUP_LBN 8 1766 #define PCRF_DZ_EXT_TPH_MODE_SUP_WIDTH 1 1767 #define PCRF_DZ_TPH_DEV_MODE_SUP_LBN 2 1768 #define PCRF_DZ_TPH_DEV_MODE_SUP_WIDTH 1 1769 #define PCRF_DZ_TPH_INT_MODE_SUP_LBN 1 1770 #define PCRF_DZ_TPH_INT_MODE_SUP_WIDTH 1 1771 #define PCRF_DZ_TPH_NOST_MODE_SUP_LBN 0 1772 #define PCRF_DZ_TPH_NOST_MODE_SUP_WIDTH 1 1773 1774 /* 1775 * PC_TPH_REQ_CTL_REG(32bit): 1776 * TPH Requester Control Register 1777 */ 1778 1779 #define PCR_DZ_TPH_REQ_CTL_REG 0x000001c8 1780 /* hunta0=pci_f0_config */ 1781 1782 #define PCRF_DZ_TPH_REQ_ENABLE_LBN 8 1783 #define PCRF_DZ_TPH_REQ_ENABLE_WIDTH 2 1784 #define PCRF_DZ_TPH_ST_MODE_LBN 0 1785 #define PCRF_DZ_TPH_ST_MODE_WIDTH 3 1786 1787 /* 1788 * PC_LTR_CAP_HDR_REG(32bit): 1789 * Latency Tolerance Reporting Cap Header Reg 1790 */ 1791 1792 #define PCR_DZ_LTR_CAP_HDR_REG 0x00000290 1793 /* hunta0=pci_f0_config */ 1794 1795 #define PCRF_DZ_LTR_NXT_PTR_LBN 20 1796 #define PCRF_DZ_LTR_NXT_PTR_WIDTH 12 1797 #define PCRF_DZ_LTR_VERSION_LBN 16 1798 #define PCRF_DZ_LTR_VERSION_WIDTH 4 1799 #define PCRF_DZ_LTR_EXT_CAP_ID_LBN 0 1800 #define PCRF_DZ_LTR_EXT_CAP_ID_WIDTH 16 1801 1802 /* 1803 * PC_LTR_MAX_SNOOP_REG(32bit): 1804 * LTR Maximum Snoop/No Snoop Register 1805 */ 1806 1807 #define PCR_DZ_LTR_MAX_SNOOP_REG 0x00000294 1808 /* hunta0=pci_f0_config */ 1809 1810 #define PCRF_DZ_LTR_MAX_NOSNOOP_SCALE_LBN 26 1811 #define PCRF_DZ_LTR_MAX_NOSNOOP_SCALE_WIDTH 3 1812 #define PCRF_DZ_LTR_MAX_NOSNOOP_LAT_LBN 16 1813 #define PCRF_DZ_LTR_MAX_NOSNOOP_LAT_WIDTH 10 1814 #define PCRF_DZ_LTR_MAX_SNOOP_SCALE_LBN 10 1815 #define PCRF_DZ_LTR_MAX_SNOOP_SCALE_WIDTH 3 1816 #define PCRF_DZ_LTR_MAX_SNOOP_LAT_LBN 0 1817 #define PCRF_DZ_LTR_MAX_SNOOP_LAT_WIDTH 10 1818 1819 /* 1820 * PC_ACK_LAT_TMR_REG(32bit): 1821 * ACK latency timer & replay timer register 1822 */ 1823 1824 #define PCR_AC_ACK_LAT_TMR_REG 0x00000700 1825 /* falcona0,falconb0,sienaa0=pci_f0_config */ 1826 1827 #define PCRF_AC_RT_LBN 16 1828 #define PCRF_AC_RT_WIDTH 16 1829 #define PCRF_AC_ALT_LBN 0 1830 #define PCRF_AC_ALT_WIDTH 16 1831 1832 /* 1833 * PC_OTHER_MSG_REG(32bit): 1834 * Other message register 1835 */ 1836 1837 #define PCR_AC_OTHER_MSG_REG 0x00000704 1838 /* falcona0,falconb0,sienaa0=pci_f0_config */ 1839 1840 #define PCRF_AC_OM_CRPT3_LBN 24 1841 #define PCRF_AC_OM_CRPT3_WIDTH 8 1842 #define PCRF_AC_OM_CRPT2_LBN 16 1843 #define PCRF_AC_OM_CRPT2_WIDTH 8 1844 #define PCRF_AC_OM_CRPT1_LBN 8 1845 #define PCRF_AC_OM_CRPT1_WIDTH 8 1846 #define PCRF_AC_OM_CRPT0_LBN 0 1847 #define PCRF_AC_OM_CRPT0_WIDTH 8 1848 1849 /* 1850 * PC_FORCE_LNK_REG(24bit): 1851 * Port force link register 1852 */ 1853 1854 #define PCR_AC_FORCE_LNK_REG 0x00000708 1855 /* falcona0,falconb0,sienaa0=pci_f0_config */ 1856 1857 #define PCRF_AC_LFS_LBN 16 1858 #define PCRF_AC_LFS_WIDTH 6 1859 #define PCRF_AC_FL_LBN 15 1860 #define PCRF_AC_FL_WIDTH 1 1861 #define PCRF_AC_LN_LBN 0 1862 #define PCRF_AC_LN_WIDTH 8 1863 1864 /* 1865 * PC_ACK_FREQ_REG(32bit): 1866 * ACK frequency register 1867 */ 1868 1869 #define PCR_AC_ACK_FREQ_REG 0x0000070c 1870 /* falcona0,falconb0,sienaa0=pci_f0_config */ 1871 1872 #define PCRF_CC_ALLOW_L1_WITHOUT_L0S_LBN 30 1873 #define PCRF_CC_ALLOW_L1_WITHOUT_L0S_WIDTH 1 1874 #define PCRF_AC_L1_ENTR_LAT_LBN 27 1875 #define PCRF_AC_L1_ENTR_LAT_WIDTH 3 1876 #define PCRF_AC_L0_ENTR_LAT_LBN 24 1877 #define PCRF_AC_L0_ENTR_LAT_WIDTH 3 1878 #define PCRF_CC_COMM_NFTS_LBN 16 1879 #define PCRF_CC_COMM_NFTS_WIDTH 8 1880 #define PCRF_AB_ACK_FREQ_REG_RSVD0_LBN 16 1881 #define PCRF_AB_ACK_FREQ_REG_RSVD0_WIDTH 3 1882 #define PCRF_AC_MAX_FTS_LBN 8 1883 #define PCRF_AC_MAX_FTS_WIDTH 8 1884 #define PCRF_AC_ACK_FREQ_LBN 0 1885 #define PCRF_AC_ACK_FREQ_WIDTH 8 1886 1887 /* 1888 * PC_PORT_LNK_CTL_REG(32bit): 1889 * Port link control register 1890 */ 1891 1892 #define PCR_AC_PORT_LNK_CTL_REG 0x00000710 1893 /* falcona0,falconb0,sienaa0=pci_f0_config */ 1894 1895 #define PCRF_AB_LRE_LBN 27 1896 #define PCRF_AB_LRE_WIDTH 1 1897 #define PCRF_AB_ESYNC_LBN 26 1898 #define PCRF_AB_ESYNC_WIDTH 1 1899 #define PCRF_AB_CRPT_LBN 25 1900 #define PCRF_AB_CRPT_WIDTH 1 1901 #define PCRF_AB_XB_LBN 24 1902 #define PCRF_AB_XB_WIDTH 1 1903 #define PCRF_AC_LC_LBN 16 1904 #define PCRF_AC_LC_WIDTH 6 1905 #define PCRF_AC_LDR_LBN 8 1906 #define PCRF_AC_LDR_WIDTH 4 1907 #define PCRF_AC_FLM_LBN 7 1908 #define PCRF_AC_FLM_WIDTH 1 1909 #define PCRF_AC_LKD_LBN 6 1910 #define PCRF_AC_LKD_WIDTH 1 1911 #define PCRF_AC_DLE_LBN 5 1912 #define PCRF_AC_DLE_WIDTH 1 1913 #define PCRF_AB_PORT_LNK_CTL_REG_RSVD0_LBN 4 1914 #define PCRF_AB_PORT_LNK_CTL_REG_RSVD0_WIDTH 1 1915 #define PCRF_AC_RA_LBN 3 1916 #define PCRF_AC_RA_WIDTH 1 1917 #define PCRF_AC_LE_LBN 2 1918 #define PCRF_AC_LE_WIDTH 1 1919 #define PCRF_AC_SD_LBN 1 1920 #define PCRF_AC_SD_WIDTH 1 1921 #define PCRF_AC_OMR_LBN 0 1922 #define PCRF_AC_OMR_WIDTH 1 1923 1924 /* 1925 * PC_LN_SKEW_REG(32bit): 1926 * Lane skew register 1927 */ 1928 1929 #define PCR_AC_LN_SKEW_REG 0x00000714 1930 /* falcona0,falconb0,sienaa0=pci_f0_config */ 1931 1932 #define PCRF_AC_DIS_LBN 31 1933 #define PCRF_AC_DIS_WIDTH 1 1934 #define PCRF_AB_RST_LBN 30 1935 #define PCRF_AB_RST_WIDTH 1 1936 #define PCRF_AC_AD_LBN 25 1937 #define PCRF_AC_AD_WIDTH 1 1938 #define PCRF_AC_FCD_LBN 24 1939 #define PCRF_AC_FCD_WIDTH 1 1940 #define PCRF_AC_LS2_LBN 16 1941 #define PCRF_AC_LS2_WIDTH 8 1942 #define PCRF_AC_LS1_LBN 8 1943 #define PCRF_AC_LS1_WIDTH 8 1944 #define PCRF_AC_LS0_LBN 0 1945 #define PCRF_AC_LS0_WIDTH 8 1946 1947 /* 1948 * PC_SYM_NUM_REG(16bit): 1949 * Symbol number register 1950 */ 1951 1952 #define PCR_AC_SYM_NUM_REG 0x00000718 1953 /* falcona0,falconb0,sienaa0=pci_f0_config */ 1954 1955 #define PCRF_CC_MAX_FUNCTIONS_LBN 29 1956 #define PCRF_CC_MAX_FUNCTIONS_WIDTH 3 1957 #define PCRF_CC_FC_WATCHDOG_TMR_LBN 24 1958 #define PCRF_CC_FC_WATCHDOG_TMR_WIDTH 5 1959 #define PCRF_CC_ACK_NAK_TMR_MOD_LBN 19 1960 #define PCRF_CC_ACK_NAK_TMR_MOD_WIDTH 5 1961 #define PCRF_CC_REPLAY_TMR_MOD_LBN 14 1962 #define PCRF_CC_REPLAY_TMR_MOD_WIDTH 5 1963 #define PCRF_AB_ES_LBN 12 1964 #define PCRF_AB_ES_WIDTH 3 1965 #define PCRF_AB_SYM_NUM_REG_RSVD0_LBN 11 1966 #define PCRF_AB_SYM_NUM_REG_RSVD0_WIDTH 1 1967 #define PCRF_CC_NUM_SKP_SYMS_LBN 8 1968 #define PCRF_CC_NUM_SKP_SYMS_WIDTH 3 1969 #define PCRF_AB_TS2_LBN 4 1970 #define PCRF_AB_TS2_WIDTH 4 1971 #define PCRF_AC_TS1_LBN 0 1972 #define PCRF_AC_TS1_WIDTH 4 1973 1974 /* 1975 * PC_SYM_TMR_FLT_MSK_REG(16bit): 1976 * Symbol timer and Filter Mask Register 1977 */ 1978 1979 #define PCR_CC_SYM_TMR_FLT_MSK_REG 0x0000071c 1980 /* sienaa0=pci_f0_config */ 1981 1982 #define PCRF_CC_DEFAULT_FLT_MSK1_LBN 16 1983 #define PCRF_CC_DEFAULT_FLT_MSK1_WIDTH 16 1984 #define PCRF_CC_FC_WDOG_TMR_DIS_LBN 15 1985 #define PCRF_CC_FC_WDOG_TMR_DIS_WIDTH 1 1986 #define PCRF_CC_SI1_LBN 8 1987 #define PCRF_CC_SI1_WIDTH 3 1988 #define PCRF_CC_SKIP_INT_VAL_LBN 0 1989 #define PCRF_CC_SKIP_INT_VAL_WIDTH 11 1990 #define PCRF_CC_SI0_LBN 0 1991 #define PCRF_CC_SI0_WIDTH 8 1992 1993 /* 1994 * PC_SYM_TMR_REG(16bit): 1995 * Symbol timer register 1996 */ 1997 1998 #define PCR_AB_SYM_TMR_REG 0x0000071c 1999 /* falcona0,falconb0=pci_f0_config */ 2000 2001 #define PCRF_AB_ET_LBN 11 2002 #define PCRF_AB_ET_WIDTH 4 2003 #define PCRF_AB_SI1_LBN 8 2004 #define PCRF_AB_SI1_WIDTH 3 2005 #define PCRF_AB_SI0_LBN 0 2006 #define PCRF_AB_SI0_WIDTH 8 2007 2008 /* 2009 * PC_FLT_MSK_REG(32bit): 2010 * Filter Mask Register 2 2011 */ 2012 2013 #define PCR_CC_FLT_MSK_REG 0x00000720 2014 /* sienaa0=pci_f0_config */ 2015 2016 #define PCRF_CC_DEFAULT_FLT_MSK2_LBN 0 2017 #define PCRF_CC_DEFAULT_FLT_MSK2_WIDTH 32 2018 2019 /* 2020 * PC_PHY_STAT_REG(32bit): 2021 * PHY status register 2022 */ 2023 2024 #define PCR_AB_PHY_STAT_REG 0x00000720 2025 /* falcona0,falconb0=pci_f0_config */ 2026 2027 #define PCR_CC_PHY_STAT_REG 0x00000810 2028 /* sienaa0=pci_f0_config */ 2029 2030 #define PCRF_AC_SSL_LBN 3 2031 #define PCRF_AC_SSL_WIDTH 1 2032 #define PCRF_AC_SSR_LBN 2 2033 #define PCRF_AC_SSR_WIDTH 1 2034 #define PCRF_AC_SSCL_LBN 1 2035 #define PCRF_AC_SSCL_WIDTH 1 2036 #define PCRF_AC_SSCD_LBN 0 2037 #define PCRF_AC_SSCD_WIDTH 1 2038 2039 /* 2040 * PC_PHY_CTL_REG(32bit): 2041 * PHY control register 2042 */ 2043 2044 #define PCR_AB_PHY_CTL_REG 0x00000724 2045 /* falcona0,falconb0=pci_f0_config */ 2046 2047 #define PCR_CC_PHY_CTL_REG 0x00000814 2048 /* sienaa0=pci_f0_config */ 2049 2050 #define PCRF_AC_BD_LBN 31 2051 #define PCRF_AC_BD_WIDTH 1 2052 #define PCRF_AC_CDS_LBN 30 2053 #define PCRF_AC_CDS_WIDTH 1 2054 #define PCRF_AC_DWRAP_LB_LBN 29 2055 #define PCRF_AC_DWRAP_LB_WIDTH 1 2056 #define PCRF_AC_EBD_LBN 28 2057 #define PCRF_AC_EBD_WIDTH 1 2058 #define PCRF_AC_SNR_LBN 27 2059 #define PCRF_AC_SNR_WIDTH 1 2060 #define PCRF_AC_RX_NOT_DET_LBN 2 2061 #define PCRF_AC_RX_NOT_DET_WIDTH 1 2062 #define PCRF_AC_FORCE_LOS_VAL_LBN 1 2063 #define PCRF_AC_FORCE_LOS_VAL_WIDTH 1 2064 #define PCRF_AC_FORCE_LOS_EN_LBN 0 2065 #define PCRF_AC_FORCE_LOS_EN_WIDTH 1 2066 2067 /* 2068 * PC_DEBUG0_REG(32bit): 2069 * Debug register 0 2070 */ 2071 2072 #define PCR_AC_DEBUG0_REG 0x00000728 2073 /* falcona0,falconb0,sienaa0=pci_f0_config */ 2074 2075 #define PCRF_AC_CDI03_LBN 24 2076 #define PCRF_AC_CDI03_WIDTH 8 2077 #define PCRF_AC_CDI0_LBN 0 2078 #define PCRF_AC_CDI0_WIDTH 32 2079 #define PCRF_AC_CDI02_LBN 16 2080 #define PCRF_AC_CDI02_WIDTH 8 2081 #define PCRF_AC_CDI01_LBN 8 2082 #define PCRF_AC_CDI01_WIDTH 8 2083 #define PCRF_AC_CDI00_LBN 0 2084 #define PCRF_AC_CDI00_WIDTH 8 2085 2086 /* 2087 * PC_DEBUG1_REG(32bit): 2088 * Debug register 1 2089 */ 2090 2091 #define PCR_AC_DEBUG1_REG 0x0000072c 2092 /* falcona0,falconb0,sienaa0=pci_f0_config */ 2093 2094 #define PCRF_AC_CDI13_LBN 24 2095 #define PCRF_AC_CDI13_WIDTH 8 2096 #define PCRF_AC_CDI1_LBN 0 2097 #define PCRF_AC_CDI1_WIDTH 32 2098 #define PCRF_AC_CDI12_LBN 16 2099 #define PCRF_AC_CDI12_WIDTH 8 2100 #define PCRF_AC_CDI11_LBN 8 2101 #define PCRF_AC_CDI11_WIDTH 8 2102 #define PCRF_AC_CDI10_LBN 0 2103 #define PCRF_AC_CDI10_WIDTH 8 2104 2105 /* 2106 * PC_XPFCC_STAT_REG(24bit): 2107 * documentation to be written for sum_PC_XPFCC_STAT_REG 2108 */ 2109 2110 #define PCR_AC_XPFCC_STAT_REG 0x00000730 2111 /* falcona0,falconb0,sienaa0=pci_f0_config */ 2112 2113 #define PCRF_AC_XPDC_LBN 12 2114 #define PCRF_AC_XPDC_WIDTH 8 2115 #define PCRF_AC_XPHC_LBN 0 2116 #define PCRF_AC_XPHC_WIDTH 12 2117 2118 /* 2119 * PC_XNPFCC_STAT_REG(24bit): 2120 * documentation to be written for sum_PC_XNPFCC_STAT_REG 2121 */ 2122 2123 #define PCR_AC_XNPFCC_STAT_REG 0x00000734 2124 /* falcona0,falconb0,sienaa0=pci_f0_config */ 2125 2126 #define PCRF_AC_XNPDC_LBN 12 2127 #define PCRF_AC_XNPDC_WIDTH 8 2128 #define PCRF_AC_XNPHC_LBN 0 2129 #define PCRF_AC_XNPHC_WIDTH 12 2130 2131 /* 2132 * PC_XCFCC_STAT_REG(24bit): 2133 * documentation to be written for sum_PC_XCFCC_STAT_REG 2134 */ 2135 2136 #define PCR_AC_XCFCC_STAT_REG 0x00000738 2137 /* falcona0,falconb0,sienaa0=pci_f0_config */ 2138 2139 #define PCRF_AC_XCDC_LBN 12 2140 #define PCRF_AC_XCDC_WIDTH 8 2141 #define PCRF_AC_XCHC_LBN 0 2142 #define PCRF_AC_XCHC_WIDTH 12 2143 2144 /* 2145 * PC_Q_STAT_REG(8bit): 2146 * documentation to be written for sum_PC_Q_STAT_REG 2147 */ 2148 2149 #define PCR_AC_Q_STAT_REG 0x0000073c 2150 /* falcona0,falconb0,sienaa0=pci_f0_config */ 2151 2152 #define PCRF_AC_RQNE_LBN 2 2153 #define PCRF_AC_RQNE_WIDTH 1 2154 #define PCRF_AC_XRNE_LBN 1 2155 #define PCRF_AC_XRNE_WIDTH 1 2156 #define PCRF_AC_RCNR_LBN 0 2157 #define PCRF_AC_RCNR_WIDTH 1 2158 2159 /* 2160 * PC_VC_XMIT_ARB1_REG(32bit): 2161 * VC Transmit Arbitration Register 1 2162 */ 2163 2164 #define PCR_CC_VC_XMIT_ARB1_REG 0x00000740 2165 /* sienaa0=pci_f0_config */ 2166 2167 /* 2168 * PC_VC_XMIT_ARB2_REG(32bit): 2169 * VC Transmit Arbitration Register 2 2170 */ 2171 2172 #define PCR_CC_VC_XMIT_ARB2_REG 0x00000744 2173 /* sienaa0=pci_f0_config */ 2174 2175 /* 2176 * PC_VC0_P_RQ_CTL_REG(32bit): 2177 * VC0 Posted Receive Queue Control 2178 */ 2179 2180 #define PCR_CC_VC0_P_RQ_CTL_REG 0x00000748 2181 /* sienaa0=pci_f0_config */ 2182 2183 /* 2184 * PC_VC0_NP_RQ_CTL_REG(32bit): 2185 * VC0 Non-Posted Receive Queue Control 2186 */ 2187 2188 #define PCR_CC_VC0_NP_RQ_CTL_REG 0x0000074c 2189 /* sienaa0=pci_f0_config */ 2190 2191 /* 2192 * PC_VC0_C_RQ_CTL_REG(32bit): 2193 * VC0 Completion Receive Queue Control 2194 */ 2195 2196 #define PCR_CC_VC0_C_RQ_CTL_REG 0x00000750 2197 /* sienaa0=pci_f0_config */ 2198 2199 /* 2200 * PC_GEN2_REG(32bit): 2201 * Gen2 Register 2202 */ 2203 2204 #define PCR_CC_GEN2_REG 0x0000080c 2205 /* sienaa0=pci_f0_config */ 2206 2207 #define PCRF_CC_SET_DE_EMPHASIS_LBN 20 2208 #define PCRF_CC_SET_DE_EMPHASIS_WIDTH 1 2209 #define PCRF_CC_CFG_TX_COMPLIANCE_LBN 19 2210 #define PCRF_CC_CFG_TX_COMPLIANCE_WIDTH 1 2211 #define PCRF_CC_CFG_TX_SWING_LBN 18 2212 #define PCRF_CC_CFG_TX_SWING_WIDTH 1 2213 #define PCRF_CC_DIR_SPEED_CHANGE_LBN 17 2214 #define PCRF_CC_DIR_SPEED_CHANGE_WIDTH 1 2215 #define PCRF_CC_LANE_ENABLE_LBN 8 2216 #define PCRF_CC_LANE_ENABLE_WIDTH 9 2217 #define PCRF_CC_NUM_FTS_LBN 0 2218 #define PCRF_CC_NUM_FTS_WIDTH 8 2219 2220 #ifdef __cplusplus 2221 } 2222 #endif 2223 2224 #endif /* _SYS_EFX_REGS_PCI_H */ 2225