xref: /freebsd/sys/dev/sfxge/common/efx_regs_pci.h (revision a0ee8cc636cd5c2374ec44ca71226564ea0bca95)
1 /*-
2  * Copyright (c) 2007-2015 Solarflare Communications Inc.
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions are met:
7  *
8  * 1. Redistributions of source code must retain the above copyright notice,
9  *    this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright notice,
11  *    this list of conditions and the following disclaimer in the documentation
12  *    and/or other materials provided with the distribution.
13  *
14  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25  *
26  * The views and conclusions contained in the software and documentation are
27  * those of the authors and should not be interpreted as representing official
28  * policies, either expressed or implied, of the FreeBSD Project.
29  *
30  * $FreeBSD$
31  */
32 
33 #ifndef	_SYS_EFX_REGS_PCI_H
34 #define	_SYS_EFX_REGS_PCI_H
35 
36 #ifdef	__cplusplus
37 extern "C" {
38 #endif
39 
40 /*
41  * PC_VEND_ID_REG(16bit):
42  * Vendor ID register
43  */
44 
45 #define	PCR_AZ_VEND_ID_REG 0x00000000
46 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
47 
48 #define	PCRF_AZ_VEND_ID_LBN 0
49 #define	PCRF_AZ_VEND_ID_WIDTH 16
50 
51 
52 /*
53  * PC_DEV_ID_REG(16bit):
54  * Device ID register
55  */
56 
57 #define	PCR_AZ_DEV_ID_REG 0x00000002
58 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
59 
60 #define	PCRF_AZ_DEV_ID_LBN 0
61 #define	PCRF_AZ_DEV_ID_WIDTH 16
62 
63 
64 /*
65  * PC_CMD_REG(16bit):
66  * Command register
67  */
68 
69 #define	PCR_AZ_CMD_REG 0x00000004
70 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
71 
72 #define	PCRF_AZ_INTX_DIS_LBN 10
73 #define	PCRF_AZ_INTX_DIS_WIDTH 1
74 #define	PCRF_AZ_FB2B_EN_LBN 9
75 #define	PCRF_AZ_FB2B_EN_WIDTH 1
76 #define	PCRF_AZ_SERR_EN_LBN 8
77 #define	PCRF_AZ_SERR_EN_WIDTH 1
78 #define	PCRF_AZ_IDSEL_CTL_LBN 7
79 #define	PCRF_AZ_IDSEL_CTL_WIDTH 1
80 #define	PCRF_AZ_PERR_EN_LBN 6
81 #define	PCRF_AZ_PERR_EN_WIDTH 1
82 #define	PCRF_AZ_VGA_PAL_SNP_LBN 5
83 #define	PCRF_AZ_VGA_PAL_SNP_WIDTH 1
84 #define	PCRF_AZ_MWI_EN_LBN 4
85 #define	PCRF_AZ_MWI_EN_WIDTH 1
86 #define	PCRF_AZ_SPEC_CYC_LBN 3
87 #define	PCRF_AZ_SPEC_CYC_WIDTH 1
88 #define	PCRF_AZ_MST_EN_LBN 2
89 #define	PCRF_AZ_MST_EN_WIDTH 1
90 #define	PCRF_AZ_MEM_EN_LBN 1
91 #define	PCRF_AZ_MEM_EN_WIDTH 1
92 #define	PCRF_AZ_IO_EN_LBN 0
93 #define	PCRF_AZ_IO_EN_WIDTH 1
94 
95 
96 /*
97  * PC_STAT_REG(16bit):
98  * Status register
99  */
100 
101 #define	PCR_AZ_STAT_REG 0x00000006
102 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
103 
104 #define	PCRF_AZ_DET_PERR_LBN 15
105 #define	PCRF_AZ_DET_PERR_WIDTH 1
106 #define	PCRF_AZ_SIG_SERR_LBN 14
107 #define	PCRF_AZ_SIG_SERR_WIDTH 1
108 #define	PCRF_AZ_GOT_MABRT_LBN 13
109 #define	PCRF_AZ_GOT_MABRT_WIDTH 1
110 #define	PCRF_AZ_GOT_TABRT_LBN 12
111 #define	PCRF_AZ_GOT_TABRT_WIDTH 1
112 #define	PCRF_AZ_SIG_TABRT_LBN 11
113 #define	PCRF_AZ_SIG_TABRT_WIDTH 1
114 #define	PCRF_AZ_DEVSEL_TIM_LBN 9
115 #define	PCRF_AZ_DEVSEL_TIM_WIDTH 2
116 #define	PCRF_AZ_MDAT_PERR_LBN 8
117 #define	PCRF_AZ_MDAT_PERR_WIDTH 1
118 #define	PCRF_AZ_FB2B_CAP_LBN 7
119 #define	PCRF_AZ_FB2B_CAP_WIDTH 1
120 #define	PCRF_AZ_66MHZ_CAP_LBN 5
121 #define	PCRF_AZ_66MHZ_CAP_WIDTH 1
122 #define	PCRF_AZ_CAP_LIST_LBN 4
123 #define	PCRF_AZ_CAP_LIST_WIDTH 1
124 #define	PCRF_AZ_INTX_STAT_LBN 3
125 #define	PCRF_AZ_INTX_STAT_WIDTH 1
126 
127 
128 /*
129  * PC_REV_ID_REG(8bit):
130  * Class code & revision ID register
131  */
132 
133 #define	PCR_AZ_REV_ID_REG 0x00000008
134 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
135 
136 #define	PCRF_AZ_REV_ID_LBN 0
137 #define	PCRF_AZ_REV_ID_WIDTH 8
138 
139 
140 /*
141  * PC_CC_REG(24bit):
142  * Class code register
143  */
144 
145 #define	PCR_AZ_CC_REG 0x00000009
146 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
147 
148 #define	PCRF_AZ_BASE_CC_LBN 16
149 #define	PCRF_AZ_BASE_CC_WIDTH 8
150 #define	PCRF_AZ_SUB_CC_LBN 8
151 #define	PCRF_AZ_SUB_CC_WIDTH 8
152 #define	PCRF_AZ_PROG_IF_LBN 0
153 #define	PCRF_AZ_PROG_IF_WIDTH 8
154 
155 
156 /*
157  * PC_CACHE_LSIZE_REG(8bit):
158  * Cache line size
159  */
160 
161 #define	PCR_AZ_CACHE_LSIZE_REG 0x0000000c
162 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
163 
164 #define	PCRF_AZ_CACHE_LSIZE_LBN 0
165 #define	PCRF_AZ_CACHE_LSIZE_WIDTH 8
166 
167 
168 /*
169  * PC_MST_LAT_REG(8bit):
170  * Master latency timer register
171  */
172 
173 #define	PCR_AZ_MST_LAT_REG 0x0000000d
174 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
175 
176 #define	PCRF_AZ_MST_LAT_LBN 0
177 #define	PCRF_AZ_MST_LAT_WIDTH 8
178 
179 
180 /*
181  * PC_HDR_TYPE_REG(8bit):
182  * Header type register
183  */
184 
185 #define	PCR_AZ_HDR_TYPE_REG 0x0000000e
186 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
187 
188 #define	PCRF_AZ_MULT_FUNC_LBN 7
189 #define	PCRF_AZ_MULT_FUNC_WIDTH 1
190 #define	PCRF_AZ_TYPE_LBN 0
191 #define	PCRF_AZ_TYPE_WIDTH 7
192 
193 
194 /*
195  * PC_BIST_REG(8bit):
196  * BIST register
197  */
198 
199 #define	PCR_AZ_BIST_REG 0x0000000f
200 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
201 
202 #define	PCRF_AZ_BIST_LBN 0
203 #define	PCRF_AZ_BIST_WIDTH 8
204 
205 
206 /*
207  * PC_BAR0_REG(32bit):
208  * Primary function base address register 0
209  */
210 
211 #define	PCR_AZ_BAR0_REG 0x00000010
212 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
213 
214 #define	PCRF_AZ_BAR0_LBN 4
215 #define	PCRF_AZ_BAR0_WIDTH 28
216 #define	PCRF_AZ_BAR0_PREF_LBN 3
217 #define	PCRF_AZ_BAR0_PREF_WIDTH 1
218 #define	PCRF_AZ_BAR0_TYPE_LBN 1
219 #define	PCRF_AZ_BAR0_TYPE_WIDTH 2
220 #define	PCRF_AZ_BAR0_IOM_LBN 0
221 #define	PCRF_AZ_BAR0_IOM_WIDTH 1
222 
223 
224 /*
225  * PC_BAR1_REG(32bit):
226  * Primary function base address register 1, BAR1 is not implemented so read only.
227  */
228 
229 #define	PCR_DZ_BAR1_REG 0x00000014
230 /* hunta0=pci_f0_config */
231 
232 #define	PCRF_DZ_BAR1_LBN 0
233 #define	PCRF_DZ_BAR1_WIDTH 32
234 
235 
236 /*
237  * PC_BAR2_LO_REG(32bit):
238  * Primary function base address register 2 low bits
239  */
240 
241 #define	PCR_AZ_BAR2_LO_REG 0x00000018
242 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
243 
244 #define	PCRF_AZ_BAR2_LO_LBN 4
245 #define	PCRF_AZ_BAR2_LO_WIDTH 28
246 #define	PCRF_AZ_BAR2_PREF_LBN 3
247 #define	PCRF_AZ_BAR2_PREF_WIDTH 1
248 #define	PCRF_AZ_BAR2_TYPE_LBN 1
249 #define	PCRF_AZ_BAR2_TYPE_WIDTH 2
250 #define	PCRF_AZ_BAR2_IOM_LBN 0
251 #define	PCRF_AZ_BAR2_IOM_WIDTH 1
252 
253 
254 /*
255  * PC_BAR2_HI_REG(32bit):
256  * Primary function base address register 2 high bits
257  */
258 
259 #define	PCR_AZ_BAR2_HI_REG 0x0000001c
260 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
261 
262 #define	PCRF_AZ_BAR2_HI_LBN 0
263 #define	PCRF_AZ_BAR2_HI_WIDTH 32
264 
265 
266 /*
267  * PC_BAR4_LO_REG(32bit):
268  * Primary function base address register 2 low bits
269  */
270 
271 #define	PCR_CZ_BAR4_LO_REG 0x00000020
272 /* sienaa0,hunta0=pci_f0_config */
273 
274 #define	PCRF_CZ_BAR4_LO_LBN 4
275 #define	PCRF_CZ_BAR4_LO_WIDTH 28
276 #define	PCRF_CZ_BAR4_PREF_LBN 3
277 #define	PCRF_CZ_BAR4_PREF_WIDTH 1
278 #define	PCRF_CZ_BAR4_TYPE_LBN 1
279 #define	PCRF_CZ_BAR4_TYPE_WIDTH 2
280 #define	PCRF_CZ_BAR4_IOM_LBN 0
281 #define	PCRF_CZ_BAR4_IOM_WIDTH 1
282 
283 
284 /*
285  * PC_BAR4_HI_REG(32bit):
286  * Primary function base address register 2 high bits
287  */
288 
289 #define	PCR_CZ_BAR4_HI_REG 0x00000024
290 /* sienaa0,hunta0=pci_f0_config */
291 
292 #define	PCRF_CZ_BAR4_HI_LBN 0
293 #define	PCRF_CZ_BAR4_HI_WIDTH 32
294 
295 
296 /*
297  * PC_SS_VEND_ID_REG(16bit):
298  * Sub-system vendor ID register
299  */
300 
301 #define	PCR_AZ_SS_VEND_ID_REG 0x0000002c
302 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
303 
304 #define	PCRF_AZ_SS_VEND_ID_LBN 0
305 #define	PCRF_AZ_SS_VEND_ID_WIDTH 16
306 
307 
308 /*
309  * PC_SS_ID_REG(16bit):
310  * Sub-system ID register
311  */
312 
313 #define	PCR_AZ_SS_ID_REG 0x0000002e
314 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
315 
316 #define	PCRF_AZ_SS_ID_LBN 0
317 #define	PCRF_AZ_SS_ID_WIDTH 16
318 
319 
320 /*
321  * PC_EXPROM_BAR_REG(32bit):
322  * Expansion ROM base address register
323  */
324 
325 #define	PCR_AZ_EXPROM_BAR_REG 0x00000030
326 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
327 
328 #define	PCRF_AZ_EXPROM_BAR_LBN 11
329 #define	PCRF_AZ_EXPROM_BAR_WIDTH 21
330 #define	PCRF_AB_EXPROM_MIN_SIZE_LBN 2
331 #define	PCRF_AB_EXPROM_MIN_SIZE_WIDTH 9
332 #define	PCRF_CZ_EXPROM_MIN_SIZE_LBN 1
333 #define	PCRF_CZ_EXPROM_MIN_SIZE_WIDTH 10
334 #define	PCRF_AB_EXPROM_FEATURE_ENABLE_LBN 1
335 #define	PCRF_AB_EXPROM_FEATURE_ENABLE_WIDTH 1
336 #define	PCRF_AZ_EXPROM_EN_LBN 0
337 #define	PCRF_AZ_EXPROM_EN_WIDTH 1
338 
339 
340 /*
341  * PC_CAP_PTR_REG(8bit):
342  * Capability pointer register
343  */
344 
345 #define	PCR_AZ_CAP_PTR_REG 0x00000034
346 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
347 
348 #define	PCRF_AZ_CAP_PTR_LBN 0
349 #define	PCRF_AZ_CAP_PTR_WIDTH 8
350 
351 
352 /*
353  * PC_INT_LINE_REG(8bit):
354  * Interrupt line register
355  */
356 
357 #define	PCR_AZ_INT_LINE_REG 0x0000003c
358 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
359 
360 #define	PCRF_AZ_INT_LINE_LBN 0
361 #define	PCRF_AZ_INT_LINE_WIDTH 8
362 
363 
364 /*
365  * PC_INT_PIN_REG(8bit):
366  * Interrupt pin register
367  */
368 
369 #define	PCR_AZ_INT_PIN_REG 0x0000003d
370 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
371 
372 #define	PCRF_AZ_INT_PIN_LBN 0
373 #define	PCRF_AZ_INT_PIN_WIDTH 8
374 #define	PCFE_DZ_INTPIN_INTD 4
375 #define	PCFE_DZ_INTPIN_INTC 3
376 #define	PCFE_DZ_INTPIN_INTB 2
377 #define	PCFE_DZ_INTPIN_INTA 1
378 
379 
380 /*
381  * PC_PM_CAP_ID_REG(8bit):
382  * Power management capability ID
383  */
384 
385 #define	PCR_AZ_PM_CAP_ID_REG 0x00000040
386 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
387 
388 #define	PCRF_AZ_PM_CAP_ID_LBN 0
389 #define	PCRF_AZ_PM_CAP_ID_WIDTH 8
390 
391 
392 /*
393  * PC_PM_NXT_PTR_REG(8bit):
394  * Power management next item pointer
395  */
396 
397 #define	PCR_AZ_PM_NXT_PTR_REG 0x00000041
398 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
399 
400 #define	PCRF_AZ_PM_NXT_PTR_LBN 0
401 #define	PCRF_AZ_PM_NXT_PTR_WIDTH 8
402 
403 
404 /*
405  * PC_PM_CAP_REG(16bit):
406  * Power management capabilities register
407  */
408 
409 #define	PCR_AZ_PM_CAP_REG 0x00000042
410 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
411 
412 #define	PCRF_AZ_PM_PME_SUPT_LBN 11
413 #define	PCRF_AZ_PM_PME_SUPT_WIDTH 5
414 #define	PCRF_AZ_PM_D2_SUPT_LBN 10
415 #define	PCRF_AZ_PM_D2_SUPT_WIDTH 1
416 #define	PCRF_AZ_PM_D1_SUPT_LBN 9
417 #define	PCRF_AZ_PM_D1_SUPT_WIDTH 1
418 #define	PCRF_AZ_PM_AUX_CURR_LBN 6
419 #define	PCRF_AZ_PM_AUX_CURR_WIDTH 3
420 #define	PCRF_AZ_PM_DSI_LBN 5
421 #define	PCRF_AZ_PM_DSI_WIDTH 1
422 #define	PCRF_AZ_PM_PME_CLK_LBN 3
423 #define	PCRF_AZ_PM_PME_CLK_WIDTH 1
424 #define	PCRF_AZ_PM_PME_VER_LBN 0
425 #define	PCRF_AZ_PM_PME_VER_WIDTH 3
426 
427 
428 /*
429  * PC_PM_CS_REG(16bit):
430  * Power management control & status register
431  */
432 
433 #define	PCR_AZ_PM_CS_REG 0x00000044
434 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
435 
436 #define	PCRF_AZ_PM_PME_STAT_LBN 15
437 #define	PCRF_AZ_PM_PME_STAT_WIDTH 1
438 #define	PCRF_AZ_PM_DAT_SCALE_LBN 13
439 #define	PCRF_AZ_PM_DAT_SCALE_WIDTH 2
440 #define	PCRF_AZ_PM_DAT_SEL_LBN 9
441 #define	PCRF_AZ_PM_DAT_SEL_WIDTH 4
442 #define	PCRF_AZ_PM_PME_EN_LBN 8
443 #define	PCRF_AZ_PM_PME_EN_WIDTH 1
444 #define	PCRF_CZ_NO_SOFT_RESET_LBN 3
445 #define	PCRF_CZ_NO_SOFT_RESET_WIDTH 1
446 #define	PCRF_AZ_PM_PWR_ST_LBN 0
447 #define	PCRF_AZ_PM_PWR_ST_WIDTH 2
448 
449 
450 /*
451  * PC_MSI_CAP_ID_REG(8bit):
452  * MSI capability ID
453  */
454 
455 #define	PCR_AZ_MSI_CAP_ID_REG 0x00000050
456 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
457 
458 #define	PCRF_AZ_MSI_CAP_ID_LBN 0
459 #define	PCRF_AZ_MSI_CAP_ID_WIDTH 8
460 
461 
462 /*
463  * PC_MSI_NXT_PTR_REG(8bit):
464  * MSI next item pointer
465  */
466 
467 #define	PCR_AZ_MSI_NXT_PTR_REG 0x00000051
468 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
469 
470 #define	PCRF_AZ_MSI_NXT_PTR_LBN 0
471 #define	PCRF_AZ_MSI_NXT_PTR_WIDTH 8
472 
473 
474 /*
475  * PC_MSI_CTL_REG(16bit):
476  * MSI control register
477  */
478 
479 #define	PCR_AZ_MSI_CTL_REG 0x00000052
480 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
481 
482 #define	PCRF_AZ_MSI_64_EN_LBN 7
483 #define	PCRF_AZ_MSI_64_EN_WIDTH 1
484 #define	PCRF_AZ_MSI_MULT_MSG_EN_LBN 4
485 #define	PCRF_AZ_MSI_MULT_MSG_EN_WIDTH 3
486 #define	PCRF_AZ_MSI_MULT_MSG_CAP_LBN 1
487 #define	PCRF_AZ_MSI_MULT_MSG_CAP_WIDTH 3
488 #define	PCRF_AZ_MSI_EN_LBN 0
489 #define	PCRF_AZ_MSI_EN_WIDTH 1
490 
491 
492 /*
493  * PC_MSI_ADR_LO_REG(32bit):
494  * MSI low 32 bits address register
495  */
496 
497 #define	PCR_AZ_MSI_ADR_LO_REG 0x00000054
498 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
499 
500 #define	PCRF_AZ_MSI_ADR_LO_LBN 2
501 #define	PCRF_AZ_MSI_ADR_LO_WIDTH 30
502 
503 
504 /*
505  * PC_MSI_ADR_HI_REG(32bit):
506  * MSI high 32 bits address register
507  */
508 
509 #define	PCR_AZ_MSI_ADR_HI_REG 0x00000058
510 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
511 
512 #define	PCRF_AZ_MSI_ADR_HI_LBN 0
513 #define	PCRF_AZ_MSI_ADR_HI_WIDTH 32
514 
515 
516 /*
517  * PC_MSI_DAT_REG(16bit):
518  * MSI data register
519  */
520 
521 #define	PCR_AZ_MSI_DAT_REG 0x0000005c
522 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
523 
524 #define	PCRF_AZ_MSI_DAT_LBN 0
525 #define	PCRF_AZ_MSI_DAT_WIDTH 16
526 
527 
528 /*
529  * PC_PCIE_CAP_LIST_REG(16bit):
530  * PCIe capability list register
531  */
532 
533 #define	PCR_AB_PCIE_CAP_LIST_REG 0x00000060
534 /* falcona0,falconb0=pci_f0_config */
535 
536 #define	PCR_CZ_PCIE_CAP_LIST_REG 0x00000070
537 /* sienaa0,hunta0=pci_f0_config */
538 
539 #define	PCRF_AZ_PCIE_NXT_PTR_LBN 8
540 #define	PCRF_AZ_PCIE_NXT_PTR_WIDTH 8
541 #define	PCRF_AZ_PCIE_CAP_ID_LBN 0
542 #define	PCRF_AZ_PCIE_CAP_ID_WIDTH 8
543 
544 
545 /*
546  * PC_PCIE_CAP_REG(16bit):
547  * PCIe capability register
548  */
549 
550 #define	PCR_AB_PCIE_CAP_REG 0x00000062
551 /* falcona0,falconb0=pci_f0_config */
552 
553 #define	PCR_CZ_PCIE_CAP_REG 0x00000072
554 /* sienaa0,hunta0=pci_f0_config */
555 
556 #define	PCRF_AZ_PCIE_INT_MSG_NUM_LBN 9
557 #define	PCRF_AZ_PCIE_INT_MSG_NUM_WIDTH 5
558 #define	PCRF_AZ_PCIE_SLOT_IMP_LBN 8
559 #define	PCRF_AZ_PCIE_SLOT_IMP_WIDTH 1
560 #define	PCRF_AZ_PCIE_DEV_PORT_TYPE_LBN 4
561 #define	PCRF_AZ_PCIE_DEV_PORT_TYPE_WIDTH 4
562 #define	PCRF_AZ_PCIE_CAP_VER_LBN 0
563 #define	PCRF_AZ_PCIE_CAP_VER_WIDTH 4
564 
565 
566 /*
567  * PC_DEV_CAP_REG(32bit):
568  * PCIe device capabilities register
569  */
570 
571 #define	PCR_AB_DEV_CAP_REG 0x00000064
572 /* falcona0,falconb0=pci_f0_config */
573 
574 #define	PCR_CZ_DEV_CAP_REG 0x00000074
575 /* sienaa0=pci_f0_config,hunta0=pci_f0_config */
576 
577 #define	PCRF_CZ_CAP_FN_LEVEL_RESET_LBN 28
578 #define	PCRF_CZ_CAP_FN_LEVEL_RESET_WIDTH 1
579 #define	PCRF_AZ_CAP_SLOT_PWR_SCL_LBN 26
580 #define	PCRF_AZ_CAP_SLOT_PWR_SCL_WIDTH 2
581 #define	PCRF_AZ_CAP_SLOT_PWR_VAL_LBN 18
582 #define	PCRF_AZ_CAP_SLOT_PWR_VAL_WIDTH 8
583 #define	PCRF_CZ_ROLE_BASE_ERR_REPORTING_LBN 15
584 #define	PCRF_CZ_ROLE_BASE_ERR_REPORTING_WIDTH 1
585 #define	PCRF_AB_PWR_IND_LBN 14
586 #define	PCRF_AB_PWR_IND_WIDTH 1
587 #define	PCRF_AB_ATTN_IND_LBN 13
588 #define	PCRF_AB_ATTN_IND_WIDTH 1
589 #define	PCRF_AB_ATTN_BUTTON_LBN 12
590 #define	PCRF_AB_ATTN_BUTTON_WIDTH 1
591 #define	PCRF_AZ_ENDPT_L1_LAT_LBN 9
592 #define	PCRF_AZ_ENDPT_L1_LAT_WIDTH 3
593 #define	PCRF_AZ_ENDPT_L0_LAT_LBN 6
594 #define	PCRF_AZ_ENDPT_L0_LAT_WIDTH 3
595 #define	PCRF_AZ_TAG_FIELD_LBN 5
596 #define	PCRF_AZ_TAG_FIELD_WIDTH 1
597 #define	PCRF_AZ_PHAN_FUNC_LBN 3
598 #define	PCRF_AZ_PHAN_FUNC_WIDTH 2
599 #define	PCRF_AZ_MAX_PAYL_SIZE_SUPT_LBN 0
600 #define	PCRF_AZ_MAX_PAYL_SIZE_SUPT_WIDTH 3
601 
602 
603 /*
604  * PC_DEV_CTL_REG(16bit):
605  * PCIe device control register
606  */
607 
608 #define	PCR_AB_DEV_CTL_REG 0x00000068
609 /* falcona0,falconb0=pci_f0_config */
610 
611 #define	PCR_CZ_DEV_CTL_REG 0x00000078
612 /* sienaa0,hunta0=pci_f0_config */
613 
614 #define	PCRF_CZ_FN_LEVEL_RESET_LBN 15
615 #define	PCRF_CZ_FN_LEVEL_RESET_WIDTH 1
616 #define	PCRF_AZ_MAX_RD_REQ_SIZE_LBN 12
617 #define	PCRF_AZ_MAX_RD_REQ_SIZE_WIDTH 3
618 #define	PCFE_AZ_MAX_RD_REQ_SIZE_4096 5
619 #define	PCFE_AZ_MAX_RD_REQ_SIZE_2048 4
620 #define	PCFE_AZ_MAX_RD_REQ_SIZE_1024 3
621 #define	PCFE_AZ_MAX_RD_REQ_SIZE_512 2
622 #define	PCFE_AZ_MAX_RD_REQ_SIZE_256 1
623 #define	PCFE_AZ_MAX_RD_REQ_SIZE_128 0
624 #define	PCRF_AZ_EN_NO_SNOOP_LBN 11
625 #define	PCRF_AZ_EN_NO_SNOOP_WIDTH 1
626 #define	PCRF_AZ_AUX_PWR_PM_EN_LBN 10
627 #define	PCRF_AZ_AUX_PWR_PM_EN_WIDTH 1
628 #define	PCRF_AZ_PHAN_FUNC_EN_LBN 9
629 #define	PCRF_AZ_PHAN_FUNC_EN_WIDTH 1
630 #define	PCRF_AB_DEV_CAP_REG_RSVD0_LBN 8
631 #define	PCRF_AB_DEV_CAP_REG_RSVD0_WIDTH 1
632 #define	PCRF_CZ_EXTENDED_TAG_EN_LBN 8
633 #define	PCRF_CZ_EXTENDED_TAG_EN_WIDTH 1
634 #define	PCRF_AZ_MAX_PAYL_SIZE_LBN 5
635 #define	PCRF_AZ_MAX_PAYL_SIZE_WIDTH 3
636 #define	PCFE_AZ_MAX_PAYL_SIZE_4096 5
637 #define	PCFE_AZ_MAX_PAYL_SIZE_2048 4
638 #define	PCFE_AZ_MAX_PAYL_SIZE_1024 3
639 #define	PCFE_AZ_MAX_PAYL_SIZE_512 2
640 #define	PCFE_AZ_MAX_PAYL_SIZE_256 1
641 #define	PCFE_AZ_MAX_PAYL_SIZE_128 0
642 #define	PCRF_AZ_EN_RELAX_ORDER_LBN 4
643 #define	PCRF_AZ_EN_RELAX_ORDER_WIDTH 1
644 #define	PCRF_AZ_UNSUP_REQ_RPT_EN_LBN 3
645 #define	PCRF_AZ_UNSUP_REQ_RPT_EN_WIDTH 1
646 #define	PCRF_AZ_FATAL_ERR_RPT_EN_LBN 2
647 #define	PCRF_AZ_FATAL_ERR_RPT_EN_WIDTH 1
648 #define	PCRF_AZ_NONFATAL_ERR_RPT_EN_LBN 1
649 #define	PCRF_AZ_NONFATAL_ERR_RPT_EN_WIDTH 1
650 #define	PCRF_AZ_CORR_ERR_RPT_EN_LBN 0
651 #define	PCRF_AZ_CORR_ERR_RPT_EN_WIDTH 1
652 
653 
654 /*
655  * PC_DEV_STAT_REG(16bit):
656  * PCIe device status register
657  */
658 
659 #define	PCR_AB_DEV_STAT_REG 0x0000006a
660 /* falcona0,falconb0=pci_f0_config */
661 
662 #define	PCR_CZ_DEV_STAT_REG 0x0000007a
663 /* sienaa0,hunta0=pci_f0_config */
664 
665 #define	PCRF_AZ_TRNS_PEND_LBN 5
666 #define	PCRF_AZ_TRNS_PEND_WIDTH 1
667 #define	PCRF_AZ_AUX_PWR_DET_LBN 4
668 #define	PCRF_AZ_AUX_PWR_DET_WIDTH 1
669 #define	PCRF_AZ_UNSUP_REQ_DET_LBN 3
670 #define	PCRF_AZ_UNSUP_REQ_DET_WIDTH 1
671 #define	PCRF_AZ_FATAL_ERR_DET_LBN 2
672 #define	PCRF_AZ_FATAL_ERR_DET_WIDTH 1
673 #define	PCRF_AZ_NONFATAL_ERR_DET_LBN 1
674 #define	PCRF_AZ_NONFATAL_ERR_DET_WIDTH 1
675 #define	PCRF_AZ_CORR_ERR_DET_LBN 0
676 #define	PCRF_AZ_CORR_ERR_DET_WIDTH 1
677 
678 
679 /*
680  * PC_LNK_CAP_REG(32bit):
681  * PCIe link capabilities register
682  */
683 
684 #define	PCR_AB_LNK_CAP_REG 0x0000006c
685 /* falcona0,falconb0=pci_f0_config */
686 
687 #define	PCR_CZ_LNK_CAP_REG 0x0000007c
688 /* sienaa0,hunta0=pci_f0_config */
689 
690 #define	PCRF_AZ_PORT_NUM_LBN 24
691 #define	PCRF_AZ_PORT_NUM_WIDTH 8
692 #define	PCRF_DZ_ASPM_OPTIONALITY_CAP_LBN 22
693 #define	PCRF_DZ_ASPM_OPTIONALITY_CAP_WIDTH 1
694 #define	PCRF_CZ_LINK_BWDITH_NOTIF_CAP_LBN 21
695 #define	PCRF_CZ_LINK_BWDITH_NOTIF_CAP_WIDTH 1
696 #define	PCRF_CZ_DATA_LINK_ACTIVE_RPT_CAP_LBN 20
697 #define	PCRF_CZ_DATA_LINK_ACTIVE_RPT_CAP_WIDTH 1
698 #define	PCRF_CZ_SURPISE_DOWN_RPT_CAP_LBN 19
699 #define	PCRF_CZ_SURPISE_DOWN_RPT_CAP_WIDTH 1
700 #define	PCRF_CZ_CLOCK_PWR_MNGMNT_CAP_LBN 18
701 #define	PCRF_CZ_CLOCK_PWR_MNGMNT_CAP_WIDTH 1
702 #define	PCRF_AZ_DEF_L1_EXIT_LAT_LBN 15
703 #define	PCRF_AZ_DEF_L1_EXIT_LAT_WIDTH 3
704 #define	PCRF_AZ_DEF_L0_EXIT_LATPORT_NUM_LBN 12
705 #define	PCRF_AZ_DEF_L0_EXIT_LATPORT_NUM_WIDTH 3
706 #define	PCRF_AZ_AS_LNK_PM_SUPT_LBN 10
707 #define	PCRF_AZ_AS_LNK_PM_SUPT_WIDTH 2
708 #define	PCRF_AZ_MAX_LNK_WIDTH_LBN 4
709 #define	PCRF_AZ_MAX_LNK_WIDTH_WIDTH 6
710 #define	PCRF_AZ_MAX_LNK_SP_LBN 0
711 #define	PCRF_AZ_MAX_LNK_SP_WIDTH 4
712 
713 
714 /*
715  * PC_LNK_CTL_REG(16bit):
716  * PCIe link control register
717  */
718 
719 #define	PCR_AB_LNK_CTL_REG 0x00000070
720 /* falcona0,falconb0=pci_f0_config */
721 
722 #define	PCR_CZ_LNK_CTL_REG 0x00000080
723 /* sienaa0,hunta0=pci_f0_config */
724 
725 #define	PCRF_AZ_EXT_SYNC_LBN 7
726 #define	PCRF_AZ_EXT_SYNC_WIDTH 1
727 #define	PCRF_AZ_COMM_CLK_CFG_LBN 6
728 #define	PCRF_AZ_COMM_CLK_CFG_WIDTH 1
729 #define	PCRF_AB_LNK_CTL_REG_RSVD0_LBN 5
730 #define	PCRF_AB_LNK_CTL_REG_RSVD0_WIDTH 1
731 #define	PCRF_CZ_LNK_RETRAIN_LBN 5
732 #define	PCRF_CZ_LNK_RETRAIN_WIDTH 1
733 #define	PCRF_AZ_LNK_DIS_LBN 4
734 #define	PCRF_AZ_LNK_DIS_WIDTH 1
735 #define	PCRF_AZ_RD_COM_BDRY_LBN 3
736 #define	PCRF_AZ_RD_COM_BDRY_WIDTH 1
737 #define	PCRF_AZ_ACT_ST_LNK_PM_CTL_LBN 0
738 #define	PCRF_AZ_ACT_ST_LNK_PM_CTL_WIDTH 2
739 
740 
741 /*
742  * PC_LNK_STAT_REG(16bit):
743  * PCIe link status register
744  */
745 
746 #define	PCR_AB_LNK_STAT_REG 0x00000072
747 /* falcona0,falconb0=pci_f0_config */
748 
749 #define	PCR_CZ_LNK_STAT_REG 0x00000082
750 /* sienaa0,hunta0=pci_f0_config */
751 
752 #define	PCRF_AZ_SLOT_CLK_CFG_LBN 12
753 #define	PCRF_AZ_SLOT_CLK_CFG_WIDTH 1
754 #define	PCRF_AZ_LNK_TRAIN_LBN 11
755 #define	PCRF_AZ_LNK_TRAIN_WIDTH 1
756 #define	PCRF_AB_TRAIN_ERR_LBN 10
757 #define	PCRF_AB_TRAIN_ERR_WIDTH 1
758 #define	PCRF_AZ_LNK_WIDTH_LBN 4
759 #define	PCRF_AZ_LNK_WIDTH_WIDTH 6
760 #define	PCRF_AZ_LNK_SP_LBN 0
761 #define	PCRF_AZ_LNK_SP_WIDTH 4
762 
763 
764 /*
765  * PC_SLOT_CAP_REG(32bit):
766  * PCIe slot capabilities register
767  */
768 
769 #define	PCR_AB_SLOT_CAP_REG 0x00000074
770 /* falcona0,falconb0=pci_f0_config */
771 
772 #define	PCRF_AB_SLOT_NUM_LBN 19
773 #define	PCRF_AB_SLOT_NUM_WIDTH 13
774 #define	PCRF_AB_SLOT_PWR_LIM_SCL_LBN 15
775 #define	PCRF_AB_SLOT_PWR_LIM_SCL_WIDTH 2
776 #define	PCRF_AB_SLOT_PWR_LIM_VAL_LBN 7
777 #define	PCRF_AB_SLOT_PWR_LIM_VAL_WIDTH 8
778 #define	PCRF_AB_SLOT_HP_CAP_LBN 6
779 #define	PCRF_AB_SLOT_HP_CAP_WIDTH 1
780 #define	PCRF_AB_SLOT_HP_SURP_LBN 5
781 #define	PCRF_AB_SLOT_HP_SURP_WIDTH 1
782 #define	PCRF_AB_SLOT_PWR_IND_PRST_LBN 4
783 #define	PCRF_AB_SLOT_PWR_IND_PRST_WIDTH 1
784 #define	PCRF_AB_SLOT_ATTN_IND_PRST_LBN 3
785 #define	PCRF_AB_SLOT_ATTN_IND_PRST_WIDTH 1
786 #define	PCRF_AB_SLOT_MRL_SENS_PRST_LBN 2
787 #define	PCRF_AB_SLOT_MRL_SENS_PRST_WIDTH 1
788 #define	PCRF_AB_SLOT_PWR_CTL_PRST_LBN 1
789 #define	PCRF_AB_SLOT_PWR_CTL_PRST_WIDTH 1
790 #define	PCRF_AB_SLOT_ATTN_BUT_PRST_LBN 0
791 #define	PCRF_AB_SLOT_ATTN_BUT_PRST_WIDTH 1
792 
793 
794 /*
795  * PC_SLOT_CTL_REG(16bit):
796  * PCIe slot control register
797  */
798 
799 #define	PCR_AB_SLOT_CTL_REG 0x00000078
800 /* falcona0,falconb0=pci_f0_config */
801 
802 #define	PCRF_AB_SLOT_PWR_CTLR_CTL_LBN 10
803 #define	PCRF_AB_SLOT_PWR_CTLR_CTL_WIDTH 1
804 #define	PCRF_AB_SLOT_PWR_IND_CTL_LBN 8
805 #define	PCRF_AB_SLOT_PWR_IND_CTL_WIDTH 2
806 #define	PCRF_AB_SLOT_ATT_IND_CTL_LBN 6
807 #define	PCRF_AB_SLOT_ATT_IND_CTL_WIDTH 2
808 #define	PCRF_AB_SLOT_HP_INT_EN_LBN 5
809 #define	PCRF_AB_SLOT_HP_INT_EN_WIDTH 1
810 #define	PCRF_AB_SLOT_CMD_COMP_INT_EN_LBN 4
811 #define	PCRF_AB_SLOT_CMD_COMP_INT_EN_WIDTH 1
812 #define	PCRF_AB_SLOT_PRES_DET_CHG_EN_LBN 3
813 #define	PCRF_AB_SLOT_PRES_DET_CHG_EN_WIDTH 1
814 #define	PCRF_AB_SLOT_MRL_SENS_CHG_EN_LBN 2
815 #define	PCRF_AB_SLOT_MRL_SENS_CHG_EN_WIDTH 1
816 #define	PCRF_AB_SLOT_PWR_FLTDET_EN_LBN 1
817 #define	PCRF_AB_SLOT_PWR_FLTDET_EN_WIDTH 1
818 #define	PCRF_AB_SLOT_ATTN_BUT_EN_LBN 0
819 #define	PCRF_AB_SLOT_ATTN_BUT_EN_WIDTH 1
820 
821 
822 /*
823  * PC_SLOT_STAT_REG(16bit):
824  * PCIe slot status register
825  */
826 
827 #define	PCR_AB_SLOT_STAT_REG 0x0000007a
828 /* falcona0,falconb0=pci_f0_config */
829 
830 #define	PCRF_AB_PRES_DET_ST_LBN 6
831 #define	PCRF_AB_PRES_DET_ST_WIDTH 1
832 #define	PCRF_AB_MRL_SENS_ST_LBN 5
833 #define	PCRF_AB_MRL_SENS_ST_WIDTH 1
834 #define	PCRF_AB_SLOT_PWR_IND_LBN 4
835 #define	PCRF_AB_SLOT_PWR_IND_WIDTH 1
836 #define	PCRF_AB_SLOT_ATTN_IND_LBN 3
837 #define	PCRF_AB_SLOT_ATTN_IND_WIDTH 1
838 #define	PCRF_AB_SLOT_MRL_SENS_LBN 2
839 #define	PCRF_AB_SLOT_MRL_SENS_WIDTH 1
840 #define	PCRF_AB_PWR_FLTDET_LBN 1
841 #define	PCRF_AB_PWR_FLTDET_WIDTH 1
842 #define	PCRF_AB_ATTN_BUTDET_LBN 0
843 #define	PCRF_AB_ATTN_BUTDET_WIDTH 1
844 
845 
846 /*
847  * PC_MSIX_CAP_ID_REG(8bit):
848  * MSIX Capability ID
849  */
850 
851 #define	PCR_BB_MSIX_CAP_ID_REG 0x00000090
852 /* falconb0=pci_f0_config */
853 
854 #define	PCR_CZ_MSIX_CAP_ID_REG 0x000000b0
855 /* sienaa0,hunta0=pci_f0_config */
856 
857 #define	PCRF_BZ_MSIX_CAP_ID_LBN 0
858 #define	PCRF_BZ_MSIX_CAP_ID_WIDTH 8
859 
860 
861 /*
862  * PC_MSIX_NXT_PTR_REG(8bit):
863  * MSIX Capability Next Capability Ptr
864  */
865 
866 #define	PCR_BB_MSIX_NXT_PTR_REG 0x00000091
867 /* falconb0=pci_f0_config */
868 
869 #define	PCR_CZ_MSIX_NXT_PTR_REG 0x000000b1
870 /* sienaa0,hunta0=pci_f0_config */
871 
872 #define	PCRF_BZ_MSIX_NXT_PTR_LBN 0
873 #define	PCRF_BZ_MSIX_NXT_PTR_WIDTH 8
874 
875 
876 /*
877  * PC_MSIX_CTL_REG(16bit):
878  * MSIX control register
879  */
880 
881 #define	PCR_BB_MSIX_CTL_REG 0x00000092
882 /* falconb0=pci_f0_config */
883 
884 #define	PCR_CZ_MSIX_CTL_REG 0x000000b2
885 /* sienaa0,hunta0=pci_f0_config */
886 
887 #define	PCRF_BZ_MSIX_EN_LBN 15
888 #define	PCRF_BZ_MSIX_EN_WIDTH 1
889 #define	PCRF_BZ_MSIX_FUNC_MASK_LBN 14
890 #define	PCRF_BZ_MSIX_FUNC_MASK_WIDTH 1
891 #define	PCRF_BZ_MSIX_TBL_SIZE_LBN 0
892 #define	PCRF_BZ_MSIX_TBL_SIZE_WIDTH 11
893 
894 
895 /*
896  * PC_MSIX_TBL_BASE_REG(32bit):
897  * MSIX Capability Vector Table Base
898  */
899 
900 #define	PCR_BB_MSIX_TBL_BASE_REG 0x00000094
901 /* falconb0=pci_f0_config */
902 
903 #define	PCR_CZ_MSIX_TBL_BASE_REG 0x000000b4
904 /* sienaa0,hunta0=pci_f0_config */
905 
906 #define	PCRF_BZ_MSIX_TBL_OFF_LBN 3
907 #define	PCRF_BZ_MSIX_TBL_OFF_WIDTH 29
908 #define	PCRF_BZ_MSIX_TBL_BIR_LBN 0
909 #define	PCRF_BZ_MSIX_TBL_BIR_WIDTH 3
910 
911 
912 /*
913  * PC_DEV_CAP2_REG(32bit):
914  * PCIe Device Capabilities 2
915  */
916 
917 #define	PCR_CZ_DEV_CAP2_REG 0x00000094
918 /* sienaa0=pci_f0_config,hunta0=pci_f0_config */
919 
920 #define	PCRF_DZ_OBFF_SUPPORTED_LBN 18
921 #define	PCRF_DZ_OBFF_SUPPORTED_WIDTH 2
922 #define	PCRF_DZ_TPH_CMPL_SUPPORTED_LBN 12
923 #define	PCRF_DZ_TPH_CMPL_SUPPORTED_WIDTH 2
924 #define	PCRF_DZ_LTR_M_SUPPORTED_LBN 11
925 #define	PCRF_DZ_LTR_M_SUPPORTED_WIDTH 1
926 #define	PCRF_CC_CMPL_TIMEOUT_DIS_LBN 4
927 #define	PCRF_CC_CMPL_TIMEOUT_DIS_WIDTH 1
928 #define	PCRF_DZ_CMPL_TIMEOUT_DIS_SUPPORTED_LBN 4
929 #define	PCRF_DZ_CMPL_TIMEOUT_DIS_SUPPORTED_WIDTH 1
930 #define	PCRF_CZ_CMPL_TIMEOUT_LBN 0
931 #define	PCRF_CZ_CMPL_TIMEOUT_WIDTH 4
932 #define	PCFE_CZ_CMPL_TIMEOUT_17000_TO_6400MS 14
933 #define	PCFE_CZ_CMPL_TIMEOUT_4000_TO_1300MS 13
934 #define	PCFE_CZ_CMPL_TIMEOUT_1000_TO_3500MS 10
935 #define	PCFE_CZ_CMPL_TIMEOUT_260_TO_900MS 9
936 #define	PCFE_CZ_CMPL_TIMEOUT_65_TO_210MS 6
937 #define	PCFE_CZ_CMPL_TIMEOUT_16_TO_55MS 5
938 #define	PCFE_CZ_CMPL_TIMEOUT_1_TO_10MS 2
939 #define	PCFE_CZ_CMPL_TIMEOUT_50_TO_100US 1
940 #define	PCFE_CZ_CMPL_TIMEOUT_DEFAULT 0
941 
942 
943 /*
944  * PC_DEV_CTL2_REG(16bit):
945  * PCIe Device Control 2
946  */
947 
948 #define	PCR_CZ_DEV_CTL2_REG 0x00000098
949 /* sienaa0,hunta0=pci_f0_config */
950 
951 #define	PCRF_DZ_OBFF_ENABLE_LBN 13
952 #define	PCRF_DZ_OBFF_ENABLE_WIDTH 2
953 #define	PCRF_DZ_LTR_ENABLE_LBN 10
954 #define	PCRF_DZ_LTR_ENABLE_WIDTH 1
955 #define	PCRF_DZ_IDO_COMPLETION_ENABLE_LBN 9
956 #define	PCRF_DZ_IDO_COMPLETION_ENABLE_WIDTH 1
957 #define	PCRF_DZ_IDO_REQUEST_ENABLE_LBN 8
958 #define	PCRF_DZ_IDO_REQUEST_ENABLE_WIDTH 1
959 #define	PCRF_CZ_CMPL_TIMEOUT_DIS_CTL_LBN 4
960 #define	PCRF_CZ_CMPL_TIMEOUT_DIS_CTL_WIDTH 1
961 #define	PCRF_CZ_CMPL_TIMEOUT_CTL_LBN 0
962 #define	PCRF_CZ_CMPL_TIMEOUT_CTL_WIDTH 4
963 
964 
965 /*
966  * PC_MSIX_PBA_BASE_REG(32bit):
967  * MSIX Capability PBA Base
968  */
969 
970 #define	PCR_BB_MSIX_PBA_BASE_REG 0x00000098
971 /* falconb0=pci_f0_config */
972 
973 #define	PCR_CZ_MSIX_PBA_BASE_REG 0x000000b8
974 /* sienaa0,hunta0=pci_f0_config */
975 
976 #define	PCRF_BZ_MSIX_PBA_OFF_LBN 3
977 #define	PCRF_BZ_MSIX_PBA_OFF_WIDTH 29
978 #define	PCRF_BZ_MSIX_PBA_BIR_LBN 0
979 #define	PCRF_BZ_MSIX_PBA_BIR_WIDTH 3
980 
981 
982 /*
983  * PC_LNK_CAP2_REG(32bit):
984  * PCIe Link Capability 2
985  */
986 
987 #define	PCR_DZ_LNK_CAP2_REG 0x0000009c
988 /* hunta0=pci_f0_config */
989 
990 #define	PCRF_DZ_LNK_SPEED_SUP_LBN 1
991 #define	PCRF_DZ_LNK_SPEED_SUP_WIDTH 7
992 
993 
994 /*
995  * PC_LNK_CTL2_REG(16bit):
996  * PCIe Link Control 2
997  */
998 
999 #define	PCR_CZ_LNK_CTL2_REG 0x000000a0
1000 /* sienaa0,hunta0=pci_f0_config */
1001 
1002 #define	PCRF_CZ_POLLING_DEEMPH_LVL_LBN 12
1003 #define	PCRF_CZ_POLLING_DEEMPH_LVL_WIDTH 1
1004 #define	PCRF_CZ_COMPLIANCE_SOS_CTL_LBN 11
1005 #define	PCRF_CZ_COMPLIANCE_SOS_CTL_WIDTH 1
1006 #define	PCRF_CZ_ENTER_MODIFIED_COMPLIANCE_CTL_LBN 10
1007 #define	PCRF_CZ_ENTER_MODIFIED_COMPLIANCE_CTL_WIDTH 1
1008 #define	PCRF_CZ_TRANSMIT_MARGIN_LBN 7
1009 #define	PCRF_CZ_TRANSMIT_MARGIN_WIDTH 3
1010 #define	PCRF_CZ_SELECT_DEEMPH_LBN 6
1011 #define	PCRF_CZ_SELECT_DEEMPH_WIDTH 1
1012 #define	PCRF_CZ_HW_AUTONOMOUS_SPEED_DIS_LBN 5
1013 #define	PCRF_CZ_HW_AUTONOMOUS_SPEED_DIS_WIDTH 1
1014 #define	PCRF_CZ_ENTER_COMPLIANCE_CTL_LBN 4
1015 #define	PCRF_CZ_ENTER_COMPLIANCE_CTL_WIDTH 1
1016 #define	PCRF_CZ_TGT_LNK_SPEED_CTL_LBN 0
1017 #define	PCRF_CZ_TGT_LNK_SPEED_CTL_WIDTH 4
1018 #define	PCFE_DZ_LCTL2_TGT_SPEED_GEN3 3
1019 #define	PCFE_DZ_LCTL2_TGT_SPEED_GEN2 2
1020 #define	PCFE_DZ_LCTL2_TGT_SPEED_GEN1 1
1021 
1022 
1023 /*
1024  * PC_LNK_STAT2_REG(16bit):
1025  * PCIe Link Status 2
1026  */
1027 
1028 #define	PCR_CZ_LNK_STAT2_REG 0x000000a2
1029 /* sienaa0,hunta0=pci_f0_config */
1030 
1031 #define	PCRF_CZ_CURRENT_DEEMPH_LBN 0
1032 #define	PCRF_CZ_CURRENT_DEEMPH_WIDTH 1
1033 
1034 
1035 /*
1036  * PC_VPD_CAP_ID_REG(8bit):
1037  * VPD data register
1038  */
1039 
1040 #define	PCR_AB_VPD_CAP_ID_REG 0x000000b0
1041 /* falcona0,falconb0=pci_f0_config */
1042 
1043 #define	PCRF_AB_VPD_CAP_ID_LBN 0
1044 #define	PCRF_AB_VPD_CAP_ID_WIDTH 8
1045 
1046 
1047 /*
1048  * PC_VPD_NXT_PTR_REG(8bit):
1049  * VPD next item pointer
1050  */
1051 
1052 #define	PCR_AB_VPD_NXT_PTR_REG 0x000000b1
1053 /* falcona0,falconb0=pci_f0_config */
1054 
1055 #define	PCRF_AB_VPD_NXT_PTR_LBN 0
1056 #define	PCRF_AB_VPD_NXT_PTR_WIDTH 8
1057 
1058 
1059 /*
1060  * PC_VPD_ADDR_REG(16bit):
1061  * VPD address register
1062  */
1063 
1064 #define	PCR_AB_VPD_ADDR_REG 0x000000b2
1065 /* falcona0,falconb0=pci_f0_config */
1066 
1067 #define	PCRF_AB_VPD_FLAG_LBN 15
1068 #define	PCRF_AB_VPD_FLAG_WIDTH 1
1069 #define	PCRF_AB_VPD_ADDR_LBN 0
1070 #define	PCRF_AB_VPD_ADDR_WIDTH 15
1071 
1072 
1073 /*
1074  * PC_VPD_CAP_DATA_REG(32bit):
1075  * documentation to be written for sum_PC_VPD_CAP_DATA_REG
1076  */
1077 
1078 #define	PCR_AB_VPD_CAP_DATA_REG 0x000000b4
1079 /* falcona0,falconb0=pci_f0_config */
1080 
1081 #define	PCR_CZ_VPD_CAP_DATA_REG 0x000000d4
1082 /* sienaa0,hunta0=pci_f0_config */
1083 
1084 #define	PCRF_AZ_VPD_DATA_LBN 0
1085 #define	PCRF_AZ_VPD_DATA_WIDTH 32
1086 
1087 
1088 /*
1089  * PC_VPD_CAP_CTL_REG(8bit):
1090  * VPD control and capabilities register
1091  */
1092 
1093 #define	PCR_CZ_VPD_CAP_CTL_REG 0x000000d0
1094 /* sienaa0,hunta0=pci_f0_config */
1095 
1096 #define	PCRF_CZ_VPD_FLAG_LBN 31
1097 #define	PCRF_CZ_VPD_FLAG_WIDTH 1
1098 #define	PCRF_CZ_VPD_ADDR_LBN 16
1099 #define	PCRF_CZ_VPD_ADDR_WIDTH 15
1100 #define	PCRF_CZ_VPD_NXT_PTR_LBN 8
1101 #define	PCRF_CZ_VPD_NXT_PTR_WIDTH 8
1102 #define	PCRF_CZ_VPD_CAP_ID_LBN 0
1103 #define	PCRF_CZ_VPD_CAP_ID_WIDTH 8
1104 
1105 
1106 /*
1107  * PC_AER_CAP_HDR_REG(32bit):
1108  * AER capability header register
1109  */
1110 
1111 #define	PCR_AZ_AER_CAP_HDR_REG 0x00000100
1112 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
1113 
1114 #define	PCRF_AZ_AERCAPHDR_NXT_PTR_LBN 20
1115 #define	PCRF_AZ_AERCAPHDR_NXT_PTR_WIDTH 12
1116 #define	PCRF_AZ_AERCAPHDR_VER_LBN 16
1117 #define	PCRF_AZ_AERCAPHDR_VER_WIDTH 4
1118 #define	PCRF_AZ_AERCAPHDR_ID_LBN 0
1119 #define	PCRF_AZ_AERCAPHDR_ID_WIDTH 16
1120 
1121 
1122 /*
1123  * PC_AER_UNCORR_ERR_STAT_REG(32bit):
1124  * AER Uncorrectable error status register
1125  */
1126 
1127 #define	PCR_AZ_AER_UNCORR_ERR_STAT_REG 0x00000104
1128 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
1129 
1130 #define	PCRF_AZ_UNSUPT_REQ_ERR_STAT_LBN 20
1131 #define	PCRF_AZ_UNSUPT_REQ_ERR_STAT_WIDTH 1
1132 #define	PCRF_AZ_ECRC_ERR_STAT_LBN 19
1133 #define	PCRF_AZ_ECRC_ERR_STAT_WIDTH 1
1134 #define	PCRF_AZ_MALF_TLP_STAT_LBN 18
1135 #define	PCRF_AZ_MALF_TLP_STAT_WIDTH 1
1136 #define	PCRF_AZ_RX_OVF_STAT_LBN 17
1137 #define	PCRF_AZ_RX_OVF_STAT_WIDTH 1
1138 #define	PCRF_AZ_UNEXP_COMP_STAT_LBN 16
1139 #define	PCRF_AZ_UNEXP_COMP_STAT_WIDTH 1
1140 #define	PCRF_AZ_COMP_ABRT_STAT_LBN 15
1141 #define	PCRF_AZ_COMP_ABRT_STAT_WIDTH 1
1142 #define	PCRF_AZ_COMP_TIMEOUT_STAT_LBN 14
1143 #define	PCRF_AZ_COMP_TIMEOUT_STAT_WIDTH 1
1144 #define	PCRF_AZ_FC_PROTO_ERR_STAT_LBN 13
1145 #define	PCRF_AZ_FC_PROTO_ERR_STAT_WIDTH 1
1146 #define	PCRF_AZ_PSON_TLP_STAT_LBN 12
1147 #define	PCRF_AZ_PSON_TLP_STAT_WIDTH 1
1148 #define	PCRF_AZ_DL_PROTO_ERR_STAT_LBN 4
1149 #define	PCRF_AZ_DL_PROTO_ERR_STAT_WIDTH 1
1150 #define	PCRF_AB_TRAIN_ERR_STAT_LBN 0
1151 #define	PCRF_AB_TRAIN_ERR_STAT_WIDTH 1
1152 
1153 
1154 /*
1155  * PC_AER_UNCORR_ERR_MASK_REG(32bit):
1156  * AER Uncorrectable error mask register
1157  */
1158 
1159 #define	PCR_AZ_AER_UNCORR_ERR_MASK_REG 0x00000108
1160 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
1161 
1162 #define	PCRF_DZ_ATOMIC_OP_EGR_BLOCKED_MASK_LBN 24
1163 #define	PCRF_DZ_ATOMIC_OP_EGR_BLOCKED_MASK_WIDTH 1
1164 #define	PCRF_DZ_UNCORR_INT_ERR_MASK_LBN 22
1165 #define	PCRF_DZ_UNCORR_INT_ERR_MASK_WIDTH 1
1166 #define	PCRF_AZ_UNSUPT_REQ_ERR_MASK_LBN 20
1167 #define	PCRF_AZ_UNSUPT_REQ_ERR_MASK_WIDTH 1
1168 #define	PCRF_AZ_ECRC_ERR_MASK_LBN 19
1169 #define	PCRF_AZ_ECRC_ERR_MASK_WIDTH 1
1170 #define	PCRF_AZ_MALF_TLP_MASK_LBN 18
1171 #define	PCRF_AZ_MALF_TLP_MASK_WIDTH 1
1172 #define	PCRF_AZ_RX_OVF_MASK_LBN 17
1173 #define	PCRF_AZ_RX_OVF_MASK_WIDTH 1
1174 #define	PCRF_AZ_UNEXP_COMP_MASK_LBN 16
1175 #define	PCRF_AZ_UNEXP_COMP_MASK_WIDTH 1
1176 #define	PCRF_AZ_COMP_ABRT_MASK_LBN 15
1177 #define	PCRF_AZ_COMP_ABRT_MASK_WIDTH 1
1178 #define	PCRF_AZ_COMP_TIMEOUT_MASK_LBN 14
1179 #define	PCRF_AZ_COMP_TIMEOUT_MASK_WIDTH 1
1180 #define	PCRF_AZ_FC_PROTO_ERR_MASK_LBN 13
1181 #define	PCRF_AZ_FC_PROTO_ERR_MASK_WIDTH 1
1182 #define	PCRF_AZ_PSON_TLP_MASK_LBN 12
1183 #define	PCRF_AZ_PSON_TLP_MASK_WIDTH 1
1184 #define	PCRF_AZ_DL_PROTO_ERR_MASK_LBN 4
1185 #define	PCRF_AZ_DL_PROTO_ERR_MASK_WIDTH 1
1186 #define	PCRF_AB_TRAIN_ERR_MASK_LBN 0
1187 #define	PCRF_AB_TRAIN_ERR_MASK_WIDTH 1
1188 
1189 
1190 /*
1191  * PC_AER_UNCORR_ERR_SEV_REG(32bit):
1192  * AER Uncorrectable error severity register
1193  */
1194 
1195 #define	PCR_AZ_AER_UNCORR_ERR_SEV_REG 0x0000010c
1196 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
1197 
1198 #define	PCRF_AZ_UNSUPT_REQ_ERR_SEV_LBN 20
1199 #define	PCRF_AZ_UNSUPT_REQ_ERR_SEV_WIDTH 1
1200 #define	PCRF_AZ_ECRC_ERR_SEV_LBN 19
1201 #define	PCRF_AZ_ECRC_ERR_SEV_WIDTH 1
1202 #define	PCRF_AZ_MALF_TLP_SEV_LBN 18
1203 #define	PCRF_AZ_MALF_TLP_SEV_WIDTH 1
1204 #define	PCRF_AZ_RX_OVF_SEV_LBN 17
1205 #define	PCRF_AZ_RX_OVF_SEV_WIDTH 1
1206 #define	PCRF_AZ_UNEXP_COMP_SEV_LBN 16
1207 #define	PCRF_AZ_UNEXP_COMP_SEV_WIDTH 1
1208 #define	PCRF_AZ_COMP_ABRT_SEV_LBN 15
1209 #define	PCRF_AZ_COMP_ABRT_SEV_WIDTH 1
1210 #define	PCRF_AZ_COMP_TIMEOUT_SEV_LBN 14
1211 #define	PCRF_AZ_COMP_TIMEOUT_SEV_WIDTH 1
1212 #define	PCRF_AZ_FC_PROTO_ERR_SEV_LBN 13
1213 #define	PCRF_AZ_FC_PROTO_ERR_SEV_WIDTH 1
1214 #define	PCRF_AZ_PSON_TLP_SEV_LBN 12
1215 #define	PCRF_AZ_PSON_TLP_SEV_WIDTH 1
1216 #define	PCRF_AZ_DL_PROTO_ERR_SEV_LBN 4
1217 #define	PCRF_AZ_DL_PROTO_ERR_SEV_WIDTH 1
1218 #define	PCRF_AB_TRAIN_ERR_SEV_LBN 0
1219 #define	PCRF_AB_TRAIN_ERR_SEV_WIDTH 1
1220 
1221 
1222 /*
1223  * PC_AER_CORR_ERR_STAT_REG(32bit):
1224  * AER Correctable error status register
1225  */
1226 
1227 #define	PCR_AZ_AER_CORR_ERR_STAT_REG 0x00000110
1228 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
1229 
1230 #define	PCRF_CZ_ADVSY_NON_FATAL_STAT_LBN 13
1231 #define	PCRF_CZ_ADVSY_NON_FATAL_STAT_WIDTH 1
1232 #define	PCRF_AZ_RPLY_TMR_TOUT_STAT_LBN 12
1233 #define	PCRF_AZ_RPLY_TMR_TOUT_STAT_WIDTH 1
1234 #define	PCRF_AZ_RPLAY_NUM_RO_STAT_LBN 8
1235 #define	PCRF_AZ_RPLAY_NUM_RO_STAT_WIDTH 1
1236 #define	PCRF_AZ_BAD_DLLP_STAT_LBN 7
1237 #define	PCRF_AZ_BAD_DLLP_STAT_WIDTH 1
1238 #define	PCRF_AZ_BAD_TLP_STAT_LBN 6
1239 #define	PCRF_AZ_BAD_TLP_STAT_WIDTH 1
1240 #define	PCRF_AZ_RX_ERR_STAT_LBN 0
1241 #define	PCRF_AZ_RX_ERR_STAT_WIDTH 1
1242 
1243 
1244 /*
1245  * PC_AER_CORR_ERR_MASK_REG(32bit):
1246  * AER Correctable error status register
1247  */
1248 
1249 #define	PCR_AZ_AER_CORR_ERR_MASK_REG 0x00000114
1250 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
1251 
1252 #define	PCRF_CZ_ADVSY_NON_FATAL_MASK_LBN 13
1253 #define	PCRF_CZ_ADVSY_NON_FATAL_MASK_WIDTH 1
1254 #define	PCRF_AZ_RPLY_TMR_TOUT_MASK_LBN 12
1255 #define	PCRF_AZ_RPLY_TMR_TOUT_MASK_WIDTH 1
1256 #define	PCRF_AZ_RPLAY_NUM_RO_MASK_LBN 8
1257 #define	PCRF_AZ_RPLAY_NUM_RO_MASK_WIDTH 1
1258 #define	PCRF_AZ_BAD_DLLP_MASK_LBN 7
1259 #define	PCRF_AZ_BAD_DLLP_MASK_WIDTH 1
1260 #define	PCRF_AZ_BAD_TLP_MASK_LBN 6
1261 #define	PCRF_AZ_BAD_TLP_MASK_WIDTH 1
1262 #define	PCRF_AZ_RX_ERR_MASK_LBN 0
1263 #define	PCRF_AZ_RX_ERR_MASK_WIDTH 1
1264 
1265 
1266 /*
1267  * PC_AER_CAP_CTL_REG(32bit):
1268  * AER capability and control register
1269  */
1270 
1271 #define	PCR_AZ_AER_CAP_CTL_REG 0x00000118
1272 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
1273 
1274 #define	PCRF_AZ_ECRC_CHK_EN_LBN 8
1275 #define	PCRF_AZ_ECRC_CHK_EN_WIDTH 1
1276 #define	PCRF_AZ_ECRC_CHK_CAP_LBN 7
1277 #define	PCRF_AZ_ECRC_CHK_CAP_WIDTH 1
1278 #define	PCRF_AZ_ECRC_GEN_EN_LBN 6
1279 #define	PCRF_AZ_ECRC_GEN_EN_WIDTH 1
1280 #define	PCRF_AZ_ECRC_GEN_CAP_LBN 5
1281 #define	PCRF_AZ_ECRC_GEN_CAP_WIDTH 1
1282 #define	PCRF_AZ_1ST_ERR_PTR_LBN 0
1283 #define	PCRF_AZ_1ST_ERR_PTR_WIDTH 5
1284 
1285 
1286 /*
1287  * PC_AER_HDR_LOG_REG(128bit):
1288  * AER Header log register
1289  */
1290 
1291 #define	PCR_AZ_AER_HDR_LOG_REG 0x0000011c
1292 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
1293 
1294 #define	PCRF_AZ_HDR_LOG_LBN 0
1295 #define	PCRF_AZ_HDR_LOG_WIDTH 128
1296 
1297 
1298 /*
1299  * PC_DEVSN_CAP_HDR_REG(32bit):
1300  * Device serial number capability header register
1301  */
1302 
1303 #define	PCR_CZ_DEVSN_CAP_HDR_REG 0x00000140
1304 /* sienaa0,hunta0=pci_f0_config */
1305 
1306 #define	PCRF_CZ_DEVSNCAPHDR_NXT_PTR_LBN 20
1307 #define	PCRF_CZ_DEVSNCAPHDR_NXT_PTR_WIDTH 12
1308 #define	PCRF_CZ_DEVSNCAPHDR_VER_LBN 16
1309 #define	PCRF_CZ_DEVSNCAPHDR_VER_WIDTH 4
1310 #define	PCRF_CZ_DEVSNCAPHDR_ID_LBN 0
1311 #define	PCRF_CZ_DEVSNCAPHDR_ID_WIDTH 16
1312 
1313 
1314 /*
1315  * PC_DEVSN_DWORD0_REG(32bit):
1316  * Device serial number DWORD0
1317  */
1318 
1319 #define	PCR_CZ_DEVSN_DWORD0_REG 0x00000144
1320 /* sienaa0,hunta0=pci_f0_config */
1321 
1322 #define	PCRF_CZ_DEVSN_DWORD0_LBN 0
1323 #define	PCRF_CZ_DEVSN_DWORD0_WIDTH 32
1324 
1325 
1326 /*
1327  * PC_DEVSN_DWORD1_REG(32bit):
1328  * Device serial number DWORD0
1329  */
1330 
1331 #define	PCR_CZ_DEVSN_DWORD1_REG 0x00000148
1332 /* sienaa0,hunta0=pci_f0_config */
1333 
1334 #define	PCRF_CZ_DEVSN_DWORD1_LBN 0
1335 #define	PCRF_CZ_DEVSN_DWORD1_WIDTH 32
1336 
1337 
1338 /*
1339  * PC_ARI_CAP_HDR_REG(32bit):
1340  * ARI capability header register
1341  */
1342 
1343 #define	PCR_CZ_ARI_CAP_HDR_REG 0x00000150
1344 /* sienaa0,hunta0=pci_f0_config */
1345 
1346 #define	PCRF_CZ_ARICAPHDR_NXT_PTR_LBN 20
1347 #define	PCRF_CZ_ARICAPHDR_NXT_PTR_WIDTH 12
1348 #define	PCRF_CZ_ARICAPHDR_VER_LBN 16
1349 #define	PCRF_CZ_ARICAPHDR_VER_WIDTH 4
1350 #define	PCRF_CZ_ARICAPHDR_ID_LBN 0
1351 #define	PCRF_CZ_ARICAPHDR_ID_WIDTH 16
1352 
1353 
1354 /*
1355  * PC_ARI_CAP_REG(16bit):
1356  * ARI Capabilities
1357  */
1358 
1359 #define	PCR_CZ_ARI_CAP_REG 0x00000154
1360 /* sienaa0,hunta0=pci_f0_config */
1361 
1362 #define	PCRF_CZ_ARI_NXT_FN_NUM_LBN 8
1363 #define	PCRF_CZ_ARI_NXT_FN_NUM_WIDTH 8
1364 #define	PCRF_CZ_ARI_ACS_FNGRP_CAP_LBN 1
1365 #define	PCRF_CZ_ARI_ACS_FNGRP_CAP_WIDTH 1
1366 #define	PCRF_CZ_ARI_MFVC_FNGRP_CAP_LBN 0
1367 #define	PCRF_CZ_ARI_MFVC_FNGRP_CAP_WIDTH 1
1368 
1369 
1370 /*
1371  * PC_ARI_CTL_REG(16bit):
1372  * ARI Control
1373  */
1374 
1375 #define	PCR_CZ_ARI_CTL_REG 0x00000156
1376 /* sienaa0,hunta0=pci_f0_config */
1377 
1378 #define	PCRF_CZ_ARI_FN_GRP_LBN 4
1379 #define	PCRF_CZ_ARI_FN_GRP_WIDTH 3
1380 #define	PCRF_CZ_ARI_ACS_FNGRP_EN_LBN 1
1381 #define	PCRF_CZ_ARI_ACS_FNGRP_EN_WIDTH 1
1382 #define	PCRF_CZ_ARI_MFVC_FNGRP_EN_LBN 0
1383 #define	PCRF_CZ_ARI_MFVC_FNGRP_EN_WIDTH 1
1384 
1385 
1386 /*
1387  * PC_SEC_PCIE_CAP_REG(32bit):
1388  * Secondary PCIE Capability Register
1389  */
1390 
1391 #define	PCR_DZ_SEC_PCIE_CAP_REG 0x00000160
1392 /* hunta0=pci_f0_config */
1393 
1394 #define	PCRF_DZ_SEC_NXT_PTR_LBN 20
1395 #define	PCRF_DZ_SEC_NXT_PTR_WIDTH 12
1396 #define	PCRF_DZ_SEC_VERSION_LBN 16
1397 #define	PCRF_DZ_SEC_VERSION_WIDTH 4
1398 #define	PCRF_DZ_SEC_EXT_CAP_ID_LBN 0
1399 #define	PCRF_DZ_SEC_EXT_CAP_ID_WIDTH 16
1400 
1401 
1402 /*
1403  * PC_SRIOV_CAP_HDR_REG(32bit):
1404  * SRIOV capability header register
1405  */
1406 
1407 #define	PCR_CC_SRIOV_CAP_HDR_REG 0x00000160
1408 /* sienaa0=pci_f0_config */
1409 
1410 #define	PCR_DZ_SRIOV_CAP_HDR_REG 0x00000180
1411 /* hunta0=pci_f0_config */
1412 
1413 #define	PCRF_CZ_SRIOVCAPHDR_NXT_PTR_LBN 20
1414 #define	PCRF_CZ_SRIOVCAPHDR_NXT_PTR_WIDTH 12
1415 #define	PCRF_CZ_SRIOVCAPHDR_VER_LBN 16
1416 #define	PCRF_CZ_SRIOVCAPHDR_VER_WIDTH 4
1417 #define	PCRF_CZ_SRIOVCAPHDR_ID_LBN 0
1418 #define	PCRF_CZ_SRIOVCAPHDR_ID_WIDTH 16
1419 
1420 
1421 /*
1422  * PC_SRIOV_CAP_REG(32bit):
1423  * SRIOV Capabilities
1424  */
1425 
1426 #define	PCR_CC_SRIOV_CAP_REG 0x00000164
1427 /* sienaa0=pci_f0_config */
1428 
1429 #define	PCR_DZ_SRIOV_CAP_REG 0x00000184
1430 /* hunta0=pci_f0_config */
1431 
1432 #define	PCRF_CZ_VF_MIGR_INT_MSG_NUM_LBN 21
1433 #define	PCRF_CZ_VF_MIGR_INT_MSG_NUM_WIDTH 11
1434 #define	PCRF_DZ_VF_ARI_CAP_PRESV_LBN 1
1435 #define	PCRF_DZ_VF_ARI_CAP_PRESV_WIDTH 1
1436 #define	PCRF_CZ_VF_MIGR_CAP_LBN 0
1437 #define	PCRF_CZ_VF_MIGR_CAP_WIDTH 1
1438 
1439 
1440 /*
1441  * PC_LINK_CONTROL3_REG(32bit):
1442  * Link Control 3.
1443  */
1444 
1445 #define	PCR_DZ_LINK_CONTROL3_REG 0x00000164
1446 /* hunta0=pci_f0_config */
1447 
1448 #define	PCRF_DZ_LINK_EQ_INT_EN_LBN 1
1449 #define	PCRF_DZ_LINK_EQ_INT_EN_WIDTH 1
1450 #define	PCRF_DZ_PERFORM_EQL_LBN 0
1451 #define	PCRF_DZ_PERFORM_EQL_WIDTH 1
1452 
1453 
1454 /*
1455  * PC_LANE_ERROR_STAT_REG(32bit):
1456  * Lane Error Status Register.
1457  */
1458 
1459 #define	PCR_DZ_LANE_ERROR_STAT_REG 0x00000168
1460 /* hunta0=pci_f0_config */
1461 
1462 #define	PCRF_DZ_LANE_STATUS_LBN 0
1463 #define	PCRF_DZ_LANE_STATUS_WIDTH 8
1464 
1465 
1466 /*
1467  * PC_SRIOV_CTL_REG(16bit):
1468  * SRIOV Control
1469  */
1470 
1471 #define	PCR_CC_SRIOV_CTL_REG 0x00000168
1472 /* sienaa0=pci_f0_config */
1473 
1474 #define	PCR_DZ_SRIOV_CTL_REG 0x00000188
1475 /* hunta0=pci_f0_config */
1476 
1477 #define	PCRF_CZ_VF_ARI_CAP_HRCHY_LBN 4
1478 #define	PCRF_CZ_VF_ARI_CAP_HRCHY_WIDTH 1
1479 #define	PCRF_CZ_VF_MSE_LBN 3
1480 #define	PCRF_CZ_VF_MSE_WIDTH 1
1481 #define	PCRF_CZ_VF_MIGR_INT_EN_LBN 2
1482 #define	PCRF_CZ_VF_MIGR_INT_EN_WIDTH 1
1483 #define	PCRF_CZ_VF_MIGR_EN_LBN 1
1484 #define	PCRF_CZ_VF_MIGR_EN_WIDTH 1
1485 #define	PCRF_CZ_VF_EN_LBN 0
1486 #define	PCRF_CZ_VF_EN_WIDTH 1
1487 
1488 
1489 /*
1490  * PC_SRIOV_STAT_REG(16bit):
1491  * SRIOV Status
1492  */
1493 
1494 #define	PCR_CC_SRIOV_STAT_REG 0x0000016a
1495 /* sienaa0=pci_f0_config */
1496 
1497 #define	PCR_DZ_SRIOV_STAT_REG 0x0000018a
1498 /* hunta0=pci_f0_config */
1499 
1500 #define	PCRF_CZ_VF_MIGR_STAT_LBN 0
1501 #define	PCRF_CZ_VF_MIGR_STAT_WIDTH 1
1502 
1503 
1504 /*
1505  * PC_LANE01_EQU_CONTROL_REG(32bit):
1506  * Lanes 0,1 Equalization Control Register.
1507  */
1508 
1509 #define	PCR_DZ_LANE01_EQU_CONTROL_REG 0x0000016c
1510 /* hunta0=pci_f0_config */
1511 
1512 #define	PCRF_DZ_LANE1_EQ_CTRL_LBN 16
1513 #define	PCRF_DZ_LANE1_EQ_CTRL_WIDTH 16
1514 #define	PCRF_DZ_LANE0_EQ_CTRL_LBN 0
1515 #define	PCRF_DZ_LANE0_EQ_CTRL_WIDTH 16
1516 
1517 
1518 /*
1519  * PC_SRIOV_INITIALVFS_REG(16bit):
1520  * SRIOV Initial VFs
1521  */
1522 
1523 #define	PCR_CC_SRIOV_INITIALVFS_REG 0x0000016c
1524 /* sienaa0=pci_f0_config */
1525 
1526 #define	PCR_DZ_SRIOV_INITIALVFS_REG 0x0000018c
1527 /* hunta0=pci_f0_config */
1528 
1529 #define	PCRF_CZ_VF_INITIALVFS_LBN 0
1530 #define	PCRF_CZ_VF_INITIALVFS_WIDTH 16
1531 
1532 
1533 /*
1534  * PC_SRIOV_TOTALVFS_REG(10bit):
1535  * SRIOV Total VFs
1536  */
1537 
1538 #define	PCR_CC_SRIOV_TOTALVFS_REG 0x0000016e
1539 /* sienaa0=pci_f0_config */
1540 
1541 #define	PCR_DZ_SRIOV_TOTALVFS_REG 0x0000018e
1542 /* hunta0=pci_f0_config */
1543 
1544 #define	PCRF_CZ_VF_TOTALVFS_LBN 0
1545 #define	PCRF_CZ_VF_TOTALVFS_WIDTH 16
1546 
1547 
1548 /*
1549  * PC_SRIOV_NUMVFS_REG(16bit):
1550  * SRIOV Number of VFs
1551  */
1552 
1553 #define	PCR_CC_SRIOV_NUMVFS_REG 0x00000170
1554 /* sienaa0=pci_f0_config */
1555 
1556 #define	PCR_DZ_SRIOV_NUMVFS_REG 0x00000190
1557 /* hunta0=pci_f0_config */
1558 
1559 #define	PCRF_CZ_VF_NUMVFS_LBN 0
1560 #define	PCRF_CZ_VF_NUMVFS_WIDTH 16
1561 
1562 
1563 /*
1564  * PC_LANE23_EQU_CONTROL_REG(32bit):
1565  * Lanes 2,3 Equalization Control Register.
1566  */
1567 
1568 #define	PCR_DZ_LANE23_EQU_CONTROL_REG 0x00000170
1569 /* hunta0=pci_f0_config */
1570 
1571 #define	PCRF_DZ_LANE3_EQ_CTRL_LBN 16
1572 #define	PCRF_DZ_LANE3_EQ_CTRL_WIDTH 16
1573 #define	PCRF_DZ_LANE2_EQ_CTRL_LBN 0
1574 #define	PCRF_DZ_LANE2_EQ_CTRL_WIDTH 16
1575 
1576 
1577 /*
1578  * PC_SRIOV_FN_DPND_LNK_REG(16bit):
1579  * SRIOV Function dependency link
1580  */
1581 
1582 #define	PCR_CC_SRIOV_FN_DPND_LNK_REG 0x00000172
1583 /* sienaa0=pci_f0_config */
1584 
1585 #define	PCR_DZ_SRIOV_FN_DPND_LNK_REG 0x00000192
1586 /* hunta0=pci_f0_config */
1587 
1588 #define	PCRF_CZ_SRIOV_FN_DPND_LNK_LBN 0
1589 #define	PCRF_CZ_SRIOV_FN_DPND_LNK_WIDTH 8
1590 
1591 
1592 /*
1593  * PC_SRIOV_1STVF_OFFSET_REG(16bit):
1594  * SRIOV First VF Offset
1595  */
1596 
1597 #define	PCR_CC_SRIOV_1STVF_OFFSET_REG 0x00000174
1598 /* sienaa0=pci_f0_config */
1599 
1600 #define	PCR_DZ_SRIOV_1STVF_OFFSET_REG 0x00000194
1601 /* hunta0=pci_f0_config */
1602 
1603 #define	PCRF_CZ_VF_1STVF_OFFSET_LBN 0
1604 #define	PCRF_CZ_VF_1STVF_OFFSET_WIDTH 16
1605 
1606 
1607 /*
1608  * PC_LANE45_EQU_CONTROL_REG(32bit):
1609  * Lanes 4,5 Equalization Control Register.
1610  */
1611 
1612 #define	PCR_DZ_LANE45_EQU_CONTROL_REG 0x00000174
1613 /* hunta0=pci_f0_config */
1614 
1615 #define	PCRF_DZ_LANE5_EQ_CTRL_LBN 16
1616 #define	PCRF_DZ_LANE5_EQ_CTRL_WIDTH 16
1617 #define	PCRF_DZ_LANE4_EQ_CTRL_LBN 0
1618 #define	PCRF_DZ_LANE4_EQ_CTRL_WIDTH 16
1619 
1620 
1621 /*
1622  * PC_SRIOV_VFSTRIDE_REG(16bit):
1623  * SRIOV VF Stride
1624  */
1625 
1626 #define	PCR_CC_SRIOV_VFSTRIDE_REG 0x00000176
1627 /* sienaa0=pci_f0_config */
1628 
1629 #define	PCR_DZ_SRIOV_VFSTRIDE_REG 0x00000196
1630 /* hunta0=pci_f0_config */
1631 
1632 #define	PCRF_CZ_VF_VFSTRIDE_LBN 0
1633 #define	PCRF_CZ_VF_VFSTRIDE_WIDTH 16
1634 
1635 
1636 /*
1637  * PC_LANE67_EQU_CONTROL_REG(32bit):
1638  * Lanes 6,7 Equalization Control Register.
1639  */
1640 
1641 #define	PCR_DZ_LANE67_EQU_CONTROL_REG 0x00000178
1642 /* hunta0=pci_f0_config */
1643 
1644 #define	PCRF_DZ_LANE7_EQ_CTRL_LBN 16
1645 #define	PCRF_DZ_LANE7_EQ_CTRL_WIDTH 16
1646 #define	PCRF_DZ_LANE6_EQ_CTRL_LBN 0
1647 #define	PCRF_DZ_LANE6_EQ_CTRL_WIDTH 16
1648 
1649 
1650 /*
1651  * PC_SRIOV_DEVID_REG(16bit):
1652  * SRIOV VF Device ID
1653  */
1654 
1655 #define	PCR_CC_SRIOV_DEVID_REG 0x0000017a
1656 /* sienaa0=pci_f0_config */
1657 
1658 #define	PCR_DZ_SRIOV_DEVID_REG 0x0000019a
1659 /* hunta0=pci_f0_config */
1660 
1661 #define	PCRF_CZ_VF_DEVID_LBN 0
1662 #define	PCRF_CZ_VF_DEVID_WIDTH 16
1663 
1664 
1665 /*
1666  * PC_SRIOV_SUP_PAGESZ_REG(16bit):
1667  * SRIOV Supported Page Sizes
1668  */
1669 
1670 #define	PCR_CC_SRIOV_SUP_PAGESZ_REG 0x0000017c
1671 /* sienaa0=pci_f0_config */
1672 
1673 #define	PCR_DZ_SRIOV_SUP_PAGESZ_REG 0x0000019c
1674 /* hunta0=pci_f0_config */
1675 
1676 #define	PCRF_CZ_VF_SUP_PAGESZ_LBN 0
1677 #define	PCRF_CZ_VF_SUP_PAGESZ_WIDTH 16
1678 
1679 
1680 /*
1681  * PC_SRIOV_SYS_PAGESZ_REG(32bit):
1682  * SRIOV System Page Size
1683  */
1684 
1685 #define	PCR_CC_SRIOV_SYS_PAGESZ_REG 0x00000180
1686 /* sienaa0=pci_f0_config */
1687 
1688 #define	PCR_DZ_SRIOV_SYS_PAGESZ_REG 0x000001a0
1689 /* hunta0=pci_f0_config */
1690 
1691 #define	PCRF_CZ_VF_SYS_PAGESZ_LBN 0
1692 #define	PCRF_CZ_VF_SYS_PAGESZ_WIDTH 16
1693 
1694 
1695 /*
1696  * PC_SRIOV_BAR0_REG(32bit):
1697  * SRIOV VF Bar0
1698  */
1699 
1700 #define	PCR_CC_SRIOV_BAR0_REG 0x00000184
1701 /* sienaa0=pci_f0_config */
1702 
1703 #define	PCR_DZ_SRIOV_BAR0_REG 0x000001a4
1704 /* hunta0=pci_f0_config */
1705 
1706 #define	PCRF_CC_VF_BAR_ADDRESS_LBN 0
1707 #define	PCRF_CC_VF_BAR_ADDRESS_WIDTH 32
1708 #define	PCRF_DZ_VF_BAR0_ADDRESS_LBN 4
1709 #define	PCRF_DZ_VF_BAR0_ADDRESS_WIDTH 28
1710 #define	PCRF_DZ_VF_BAR0_PREF_LBN 3
1711 #define	PCRF_DZ_VF_BAR0_PREF_WIDTH 1
1712 #define	PCRF_DZ_VF_BAR0_TYPE_LBN 1
1713 #define	PCRF_DZ_VF_BAR0_TYPE_WIDTH 2
1714 #define	PCRF_DZ_VF_BAR0_IOM_LBN 0
1715 #define	PCRF_DZ_VF_BAR0_IOM_WIDTH 1
1716 
1717 
1718 /*
1719  * PC_SRIOV_BAR1_REG(32bit):
1720  * SRIOV Bar1
1721  */
1722 
1723 #define	PCR_CC_SRIOV_BAR1_REG 0x00000188
1724 /* sienaa0=pci_f0_config */
1725 
1726 #define	PCR_DZ_SRIOV_BAR1_REG 0x000001a8
1727 /* hunta0=pci_f0_config */
1728 
1729 /* defined as PCRF_CC_VF_BAR_ADDRESS_LBN 0; */
1730 /* defined as PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 */
1731 #define	PCRF_DZ_VF_BAR1_ADDRESS_LBN 0
1732 #define	PCRF_DZ_VF_BAR1_ADDRESS_WIDTH 32
1733 
1734 
1735 /*
1736  * PC_SRIOV_BAR2_REG(32bit):
1737  * SRIOV Bar2
1738  */
1739 
1740 #define	PCR_CC_SRIOV_BAR2_REG 0x0000018c
1741 /* sienaa0=pci_f0_config */
1742 
1743 #define	PCR_DZ_SRIOV_BAR2_REG 0x000001ac
1744 /* hunta0=pci_f0_config */
1745 
1746 /* defined as PCRF_CC_VF_BAR_ADDRESS_LBN 0; */
1747 /* defined as PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 */
1748 #define	PCRF_DZ_VF_BAR2_ADDRESS_LBN 4
1749 #define	PCRF_DZ_VF_BAR2_ADDRESS_WIDTH 28
1750 #define	PCRF_DZ_VF_BAR2_PREF_LBN 3
1751 #define	PCRF_DZ_VF_BAR2_PREF_WIDTH 1
1752 #define	PCRF_DZ_VF_BAR2_TYPE_LBN 1
1753 #define	PCRF_DZ_VF_BAR2_TYPE_WIDTH 2
1754 #define	PCRF_DZ_VF_BAR2_IOM_LBN 0
1755 #define	PCRF_DZ_VF_BAR2_IOM_WIDTH 1
1756 
1757 
1758 /*
1759  * PC_SRIOV_BAR3_REG(32bit):
1760  * SRIOV Bar3
1761  */
1762 
1763 #define	PCR_CC_SRIOV_BAR3_REG 0x00000190
1764 /* sienaa0=pci_f0_config */
1765 
1766 #define	PCR_DZ_SRIOV_BAR3_REG 0x000001b0
1767 /* hunta0=pci_f0_config */
1768 
1769 /* defined as PCRF_CC_VF_BAR_ADDRESS_LBN 0; */
1770 /* defined as PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 */
1771 #define	PCRF_DZ_VF_BAR3_ADDRESS_LBN 0
1772 #define	PCRF_DZ_VF_BAR3_ADDRESS_WIDTH 32
1773 
1774 
1775 /*
1776  * PC_SRIOV_BAR4_REG(32bit):
1777  * SRIOV Bar4
1778  */
1779 
1780 #define	PCR_CC_SRIOV_BAR4_REG 0x00000194
1781 /* sienaa0=pci_f0_config */
1782 
1783 #define	PCR_DZ_SRIOV_BAR4_REG 0x000001b4
1784 /* hunta0=pci_f0_config */
1785 
1786 /* defined as PCRF_CC_VF_BAR_ADDRESS_LBN 0; */
1787 /* defined as PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 */
1788 #define	PCRF_DZ_VF_BAR4_ADDRESS_LBN 0
1789 #define	PCRF_DZ_VF_BAR4_ADDRESS_WIDTH 32
1790 
1791 
1792 /*
1793  * PC_SRIOV_BAR5_REG(32bit):
1794  * SRIOV Bar5
1795  */
1796 
1797 #define	PCR_CC_SRIOV_BAR5_REG 0x00000198
1798 /* sienaa0=pci_f0_config */
1799 
1800 #define	PCR_DZ_SRIOV_BAR5_REG 0x000001b8
1801 /* hunta0=pci_f0_config */
1802 
1803 /* defined as PCRF_CC_VF_BAR_ADDRESS_LBN 0; */
1804 /* defined as PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 */
1805 #define	PCRF_DZ_VF_BAR5_ADDRESS_LBN 0
1806 #define	PCRF_DZ_VF_BAR5_ADDRESS_WIDTH 32
1807 
1808 
1809 /*
1810  * PC_SRIOV_RSVD_REG(16bit):
1811  * Reserved register
1812  */
1813 
1814 #define	PCR_DZ_SRIOV_RSVD_REG 0x00000198
1815 /* hunta0=pci_f0_config */
1816 
1817 #define	PCRF_DZ_VF_RSVD_LBN 0
1818 #define	PCRF_DZ_VF_RSVD_WIDTH 16
1819 
1820 
1821 /*
1822  * PC_SRIOV_MIBR_SARRAY_OFFSET_REG(32bit):
1823  * SRIOV VF Migration State Array Offset
1824  */
1825 
1826 #define	PCR_CC_SRIOV_MIBR_SARRAY_OFFSET_REG 0x0000019c
1827 /* sienaa0=pci_f0_config */
1828 
1829 #define	PCR_DZ_SRIOV_MIBR_SARRAY_OFFSET_REG 0x000001bc
1830 /* hunta0=pci_f0_config */
1831 
1832 #define	PCRF_CZ_VF_MIGR_OFFSET_LBN 3
1833 #define	PCRF_CZ_VF_MIGR_OFFSET_WIDTH 29
1834 #define	PCRF_CZ_VF_MIGR_BIR_LBN 0
1835 #define	PCRF_CZ_VF_MIGR_BIR_WIDTH 3
1836 
1837 
1838 /*
1839  * PC_TPH_CAP_HDR_REG(32bit):
1840  * TPH Capability Header Register
1841  */
1842 
1843 #define	PCR_DZ_TPH_CAP_HDR_REG 0x000001c0
1844 /* hunta0=pci_f0_config */
1845 
1846 #define	PCRF_DZ_TPH_NXT_PTR_LBN 20
1847 #define	PCRF_DZ_TPH_NXT_PTR_WIDTH 12
1848 #define	PCRF_DZ_TPH_VERSION_LBN 16
1849 #define	PCRF_DZ_TPH_VERSION_WIDTH 4
1850 #define	PCRF_DZ_TPH_EXT_CAP_ID_LBN 0
1851 #define	PCRF_DZ_TPH_EXT_CAP_ID_WIDTH 16
1852 
1853 
1854 /*
1855  * PC_TPH_REQ_CAP_REG(32bit):
1856  * TPH Requester Capability Register
1857  */
1858 
1859 #define	PCR_DZ_TPH_REQ_CAP_REG 0x000001c4
1860 /* hunta0=pci_f0_config */
1861 
1862 #define	PCRF_DZ_ST_TBLE_SIZE_LBN 16
1863 #define	PCRF_DZ_ST_TBLE_SIZE_WIDTH 11
1864 #define	PCRF_DZ_ST_TBLE_LOC_LBN 9
1865 #define	PCRF_DZ_ST_TBLE_LOC_WIDTH 2
1866 #define	PCRF_DZ_EXT_TPH_MODE_SUP_LBN 8
1867 #define	PCRF_DZ_EXT_TPH_MODE_SUP_WIDTH 1
1868 #define	PCRF_DZ_TPH_DEV_MODE_SUP_LBN 2
1869 #define	PCRF_DZ_TPH_DEV_MODE_SUP_WIDTH 1
1870 #define	PCRF_DZ_TPH_INT_MODE_SUP_LBN 1
1871 #define	PCRF_DZ_TPH_INT_MODE_SUP_WIDTH 1
1872 #define	PCRF_DZ_TPH_NOST_MODE_SUP_LBN 0
1873 #define	PCRF_DZ_TPH_NOST_MODE_SUP_WIDTH 1
1874 
1875 
1876 /*
1877  * PC_TPH_REQ_CTL_REG(32bit):
1878  * TPH Requester Control Register
1879  */
1880 
1881 #define	PCR_DZ_TPH_REQ_CTL_REG 0x000001c8
1882 /* hunta0=pci_f0_config */
1883 
1884 #define	PCRF_DZ_TPH_REQ_ENABLE_LBN 8
1885 #define	PCRF_DZ_TPH_REQ_ENABLE_WIDTH 2
1886 #define	PCRF_DZ_TPH_ST_MODE_LBN 0
1887 #define	PCRF_DZ_TPH_ST_MODE_WIDTH 3
1888 
1889 
1890 /*
1891  * PC_LTR_CAP_HDR_REG(32bit):
1892  * Latency Tolerance Reporting Cap Header Reg
1893  */
1894 
1895 #define	PCR_DZ_LTR_CAP_HDR_REG 0x00000290
1896 /* hunta0=pci_f0_config */
1897 
1898 #define	PCRF_DZ_LTR_NXT_PTR_LBN 20
1899 #define	PCRF_DZ_LTR_NXT_PTR_WIDTH 12
1900 #define	PCRF_DZ_LTR_VERSION_LBN 16
1901 #define	PCRF_DZ_LTR_VERSION_WIDTH 4
1902 #define	PCRF_DZ_LTR_EXT_CAP_ID_LBN 0
1903 #define	PCRF_DZ_LTR_EXT_CAP_ID_WIDTH 16
1904 
1905 
1906 /*
1907  * PC_LTR_MAX_SNOOP_REG(32bit):
1908  * LTR Maximum Snoop/No Snoop Register
1909  */
1910 
1911 #define	PCR_DZ_LTR_MAX_SNOOP_REG 0x00000294
1912 /* hunta0=pci_f0_config */
1913 
1914 #define	PCRF_DZ_LTR_MAX_NOSNOOP_SCALE_LBN 26
1915 #define	PCRF_DZ_LTR_MAX_NOSNOOP_SCALE_WIDTH 3
1916 #define	PCRF_DZ_LTR_MAX_NOSNOOP_LAT_LBN 16
1917 #define	PCRF_DZ_LTR_MAX_NOSNOOP_LAT_WIDTH 10
1918 #define	PCRF_DZ_LTR_MAX_SNOOP_SCALE_LBN 10
1919 #define	PCRF_DZ_LTR_MAX_SNOOP_SCALE_WIDTH 3
1920 #define	PCRF_DZ_LTR_MAX_SNOOP_LAT_LBN 0
1921 #define	PCRF_DZ_LTR_MAX_SNOOP_LAT_WIDTH 10
1922 
1923 
1924 /*
1925  * PC_ACK_LAT_TMR_REG(32bit):
1926  * ACK latency timer & replay timer register
1927  */
1928 
1929 #define	PCR_AC_ACK_LAT_TMR_REG 0x00000700
1930 /* falcona0,falconb0,sienaa0=pci_f0_config */
1931 
1932 #define	PCRF_AC_RT_LBN 16
1933 #define	PCRF_AC_RT_WIDTH 16
1934 #define	PCRF_AC_ALT_LBN 0
1935 #define	PCRF_AC_ALT_WIDTH 16
1936 
1937 
1938 /*
1939  * PC_OTHER_MSG_REG(32bit):
1940  * Other message register
1941  */
1942 
1943 #define	PCR_AC_OTHER_MSG_REG 0x00000704
1944 /* falcona0,falconb0,sienaa0=pci_f0_config */
1945 
1946 #define	PCRF_AC_OM_CRPT3_LBN 24
1947 #define	PCRF_AC_OM_CRPT3_WIDTH 8
1948 #define	PCRF_AC_OM_CRPT2_LBN 16
1949 #define	PCRF_AC_OM_CRPT2_WIDTH 8
1950 #define	PCRF_AC_OM_CRPT1_LBN 8
1951 #define	PCRF_AC_OM_CRPT1_WIDTH 8
1952 #define	PCRF_AC_OM_CRPT0_LBN 0
1953 #define	PCRF_AC_OM_CRPT0_WIDTH 8
1954 
1955 
1956 /*
1957  * PC_FORCE_LNK_REG(24bit):
1958  * Port force link register
1959  */
1960 
1961 #define	PCR_AC_FORCE_LNK_REG 0x00000708
1962 /* falcona0,falconb0,sienaa0=pci_f0_config */
1963 
1964 #define	PCRF_AC_LFS_LBN 16
1965 #define	PCRF_AC_LFS_WIDTH 6
1966 #define	PCRF_AC_FL_LBN 15
1967 #define	PCRF_AC_FL_WIDTH 1
1968 #define	PCRF_AC_LN_LBN 0
1969 #define	PCRF_AC_LN_WIDTH 8
1970 
1971 
1972 /*
1973  * PC_ACK_FREQ_REG(32bit):
1974  * ACK frequency register
1975  */
1976 
1977 #define	PCR_AC_ACK_FREQ_REG 0x0000070c
1978 /* falcona0,falconb0,sienaa0=pci_f0_config */
1979 
1980 #define	PCRF_CC_ALLOW_L1_WITHOUT_L0S_LBN 30
1981 #define	PCRF_CC_ALLOW_L1_WITHOUT_L0S_WIDTH 1
1982 #define	PCRF_AC_L1_ENTR_LAT_LBN 27
1983 #define	PCRF_AC_L1_ENTR_LAT_WIDTH 3
1984 #define	PCRF_AC_L0_ENTR_LAT_LBN 24
1985 #define	PCRF_AC_L0_ENTR_LAT_WIDTH 3
1986 #define	PCRF_CC_COMM_NFTS_LBN 16
1987 #define	PCRF_CC_COMM_NFTS_WIDTH 8
1988 #define	PCRF_AB_ACK_FREQ_REG_RSVD0_LBN 16
1989 #define	PCRF_AB_ACK_FREQ_REG_RSVD0_WIDTH 3
1990 #define	PCRF_AC_MAX_FTS_LBN 8
1991 #define	PCRF_AC_MAX_FTS_WIDTH 8
1992 #define	PCRF_AC_ACK_FREQ_LBN 0
1993 #define	PCRF_AC_ACK_FREQ_WIDTH 8
1994 
1995 
1996 /*
1997  * PC_PORT_LNK_CTL_REG(32bit):
1998  * Port link control register
1999  */
2000 
2001 #define	PCR_AC_PORT_LNK_CTL_REG 0x00000710
2002 /* falcona0,falconb0,sienaa0=pci_f0_config */
2003 
2004 #define	PCRF_AB_LRE_LBN 27
2005 #define	PCRF_AB_LRE_WIDTH 1
2006 #define	PCRF_AB_ESYNC_LBN 26
2007 #define	PCRF_AB_ESYNC_WIDTH 1
2008 #define	PCRF_AB_CRPT_LBN 25
2009 #define	PCRF_AB_CRPT_WIDTH 1
2010 #define	PCRF_AB_XB_LBN 24
2011 #define	PCRF_AB_XB_WIDTH 1
2012 #define	PCRF_AC_LC_LBN 16
2013 #define	PCRF_AC_LC_WIDTH 6
2014 #define	PCRF_AC_LDR_LBN 8
2015 #define	PCRF_AC_LDR_WIDTH 4
2016 #define	PCRF_AC_FLM_LBN 7
2017 #define	PCRF_AC_FLM_WIDTH 1
2018 #define	PCRF_AC_LKD_LBN 6
2019 #define	PCRF_AC_LKD_WIDTH 1
2020 #define	PCRF_AC_DLE_LBN 5
2021 #define	PCRF_AC_DLE_WIDTH 1
2022 #define	PCRF_AB_PORT_LNK_CTL_REG_RSVD0_LBN 4
2023 #define	PCRF_AB_PORT_LNK_CTL_REG_RSVD0_WIDTH 1
2024 #define	PCRF_AC_RA_LBN 3
2025 #define	PCRF_AC_RA_WIDTH 1
2026 #define	PCRF_AC_LE_LBN 2
2027 #define	PCRF_AC_LE_WIDTH 1
2028 #define	PCRF_AC_SD_LBN 1
2029 #define	PCRF_AC_SD_WIDTH 1
2030 #define	PCRF_AC_OMR_LBN 0
2031 #define	PCRF_AC_OMR_WIDTH 1
2032 
2033 
2034 /*
2035  * PC_LN_SKEW_REG(32bit):
2036  * Lane skew register
2037  */
2038 
2039 #define	PCR_AC_LN_SKEW_REG 0x00000714
2040 /* falcona0,falconb0,sienaa0=pci_f0_config */
2041 
2042 #define	PCRF_AC_DIS_LBN 31
2043 #define	PCRF_AC_DIS_WIDTH 1
2044 #define	PCRF_AB_RST_LBN 30
2045 #define	PCRF_AB_RST_WIDTH 1
2046 #define	PCRF_AC_AD_LBN 25
2047 #define	PCRF_AC_AD_WIDTH 1
2048 #define	PCRF_AC_FCD_LBN 24
2049 #define	PCRF_AC_FCD_WIDTH 1
2050 #define	PCRF_AC_LS2_LBN 16
2051 #define	PCRF_AC_LS2_WIDTH 8
2052 #define	PCRF_AC_LS1_LBN 8
2053 #define	PCRF_AC_LS1_WIDTH 8
2054 #define	PCRF_AC_LS0_LBN 0
2055 #define	PCRF_AC_LS0_WIDTH 8
2056 
2057 
2058 /*
2059  * PC_SYM_NUM_REG(16bit):
2060  * Symbol number register
2061  */
2062 
2063 #define	PCR_AC_SYM_NUM_REG 0x00000718
2064 /* falcona0,falconb0,sienaa0=pci_f0_config */
2065 
2066 #define	PCRF_CC_MAX_FUNCTIONS_LBN 29
2067 #define	PCRF_CC_MAX_FUNCTIONS_WIDTH 3
2068 #define	PCRF_CC_FC_WATCHDOG_TMR_LBN 24
2069 #define	PCRF_CC_FC_WATCHDOG_TMR_WIDTH 5
2070 #define	PCRF_CC_ACK_NAK_TMR_MOD_LBN 19
2071 #define	PCRF_CC_ACK_NAK_TMR_MOD_WIDTH 5
2072 #define	PCRF_CC_REPLAY_TMR_MOD_LBN 14
2073 #define	PCRF_CC_REPLAY_TMR_MOD_WIDTH 5
2074 #define	PCRF_AB_ES_LBN 12
2075 #define	PCRF_AB_ES_WIDTH 3
2076 #define	PCRF_AB_SYM_NUM_REG_RSVD0_LBN 11
2077 #define	PCRF_AB_SYM_NUM_REG_RSVD0_WIDTH 1
2078 #define	PCRF_CC_NUM_SKP_SYMS_LBN 8
2079 #define	PCRF_CC_NUM_SKP_SYMS_WIDTH 3
2080 #define	PCRF_AB_TS2_LBN 4
2081 #define	PCRF_AB_TS2_WIDTH 4
2082 #define	PCRF_AC_TS1_LBN 0
2083 #define	PCRF_AC_TS1_WIDTH 4
2084 
2085 
2086 /*
2087  * PC_SYM_TMR_FLT_MSK_REG(16bit):
2088  * Symbol timer and Filter Mask Register
2089  */
2090 
2091 #define	PCR_CC_SYM_TMR_FLT_MSK_REG 0x0000071c
2092 /* sienaa0=pci_f0_config */
2093 
2094 #define	PCRF_CC_DEFAULT_FLT_MSK1_LBN 16
2095 #define	PCRF_CC_DEFAULT_FLT_MSK1_WIDTH 16
2096 #define	PCRF_CC_FC_WDOG_TMR_DIS_LBN 15
2097 #define	PCRF_CC_FC_WDOG_TMR_DIS_WIDTH 1
2098 #define	PCRF_CC_SI1_LBN 8
2099 #define	PCRF_CC_SI1_WIDTH 3
2100 #define	PCRF_CC_SKIP_INT_VAL_LBN 0
2101 #define	PCRF_CC_SKIP_INT_VAL_WIDTH 11
2102 #define	PCRF_CC_SI0_LBN 0
2103 #define	PCRF_CC_SI0_WIDTH 8
2104 
2105 
2106 /*
2107  * PC_SYM_TMR_REG(16bit):
2108  * Symbol timer register
2109  */
2110 
2111 #define	PCR_AB_SYM_TMR_REG 0x0000071c
2112 /* falcona0,falconb0=pci_f0_config */
2113 
2114 #define	PCRF_AB_ET_LBN 11
2115 #define	PCRF_AB_ET_WIDTH 4
2116 #define	PCRF_AB_SI1_LBN 8
2117 #define	PCRF_AB_SI1_WIDTH 3
2118 #define	PCRF_AB_SI0_LBN 0
2119 #define	PCRF_AB_SI0_WIDTH 8
2120 
2121 
2122 /*
2123  * PC_FLT_MSK_REG(32bit):
2124  * Filter Mask Register 2
2125  */
2126 
2127 #define	PCR_CC_FLT_MSK_REG 0x00000720
2128 /* sienaa0=pci_f0_config */
2129 
2130 #define	PCRF_CC_DEFAULT_FLT_MSK2_LBN 0
2131 #define	PCRF_CC_DEFAULT_FLT_MSK2_WIDTH 32
2132 
2133 
2134 /*
2135  * PC_PHY_STAT_REG(32bit):
2136  * PHY status register
2137  */
2138 
2139 #define	PCR_AB_PHY_STAT_REG 0x00000720
2140 /* falcona0,falconb0=pci_f0_config */
2141 
2142 #define	PCR_CC_PHY_STAT_REG 0x00000810
2143 /* sienaa0=pci_f0_config */
2144 
2145 #define	PCRF_AC_SSL_LBN 3
2146 #define	PCRF_AC_SSL_WIDTH 1
2147 #define	PCRF_AC_SSR_LBN 2
2148 #define	PCRF_AC_SSR_WIDTH 1
2149 #define	PCRF_AC_SSCL_LBN 1
2150 #define	PCRF_AC_SSCL_WIDTH 1
2151 #define	PCRF_AC_SSCD_LBN 0
2152 #define	PCRF_AC_SSCD_WIDTH 1
2153 
2154 
2155 /*
2156  * PC_PHY_CTL_REG(32bit):
2157  * PHY control register
2158  */
2159 
2160 #define	PCR_AB_PHY_CTL_REG 0x00000724
2161 /* falcona0,falconb0=pci_f0_config */
2162 
2163 #define	PCR_CC_PHY_CTL_REG 0x00000814
2164 /* sienaa0=pci_f0_config */
2165 
2166 #define	PCRF_AC_BD_LBN 31
2167 #define	PCRF_AC_BD_WIDTH 1
2168 #define	PCRF_AC_CDS_LBN 30
2169 #define	PCRF_AC_CDS_WIDTH 1
2170 #define	PCRF_AC_DWRAP_LB_LBN 29
2171 #define	PCRF_AC_DWRAP_LB_WIDTH 1
2172 #define	PCRF_AC_EBD_LBN 28
2173 #define	PCRF_AC_EBD_WIDTH 1
2174 #define	PCRF_AC_SNR_LBN 27
2175 #define	PCRF_AC_SNR_WIDTH 1
2176 #define	PCRF_AC_RX_NOT_DET_LBN 2
2177 #define	PCRF_AC_RX_NOT_DET_WIDTH 1
2178 #define	PCRF_AC_FORCE_LOS_VAL_LBN 1
2179 #define	PCRF_AC_FORCE_LOS_VAL_WIDTH 1
2180 #define	PCRF_AC_FORCE_LOS_EN_LBN 0
2181 #define	PCRF_AC_FORCE_LOS_EN_WIDTH 1
2182 
2183 
2184 /*
2185  * PC_DEBUG0_REG(32bit):
2186  * Debug register 0
2187  */
2188 
2189 #define	PCR_AC_DEBUG0_REG 0x00000728
2190 /* falcona0,falconb0,sienaa0=pci_f0_config */
2191 
2192 #define	PCRF_AC_CDI03_LBN 24
2193 #define	PCRF_AC_CDI03_WIDTH 8
2194 #define	PCRF_AC_CDI0_LBN 0
2195 #define	PCRF_AC_CDI0_WIDTH 32
2196 #define	PCRF_AC_CDI02_LBN 16
2197 #define	PCRF_AC_CDI02_WIDTH 8
2198 #define	PCRF_AC_CDI01_LBN 8
2199 #define	PCRF_AC_CDI01_WIDTH 8
2200 #define	PCRF_AC_CDI00_LBN 0
2201 #define	PCRF_AC_CDI00_WIDTH 8
2202 
2203 
2204 /*
2205  * PC_DEBUG1_REG(32bit):
2206  * Debug register 1
2207  */
2208 
2209 #define	PCR_AC_DEBUG1_REG 0x0000072c
2210 /* falcona0,falconb0,sienaa0=pci_f0_config */
2211 
2212 #define	PCRF_AC_CDI13_LBN 24
2213 #define	PCRF_AC_CDI13_WIDTH 8
2214 #define	PCRF_AC_CDI1_LBN 0
2215 #define	PCRF_AC_CDI1_WIDTH 32
2216 #define	PCRF_AC_CDI12_LBN 16
2217 #define	PCRF_AC_CDI12_WIDTH 8
2218 #define	PCRF_AC_CDI11_LBN 8
2219 #define	PCRF_AC_CDI11_WIDTH 8
2220 #define	PCRF_AC_CDI10_LBN 0
2221 #define	PCRF_AC_CDI10_WIDTH 8
2222 
2223 
2224 /*
2225  * PC_XPFCC_STAT_REG(24bit):
2226  * documentation to be written for sum_PC_XPFCC_STAT_REG
2227  */
2228 
2229 #define	PCR_AC_XPFCC_STAT_REG 0x00000730
2230 /* falcona0,falconb0,sienaa0=pci_f0_config */
2231 
2232 #define	PCRF_AC_XPDC_LBN 12
2233 #define	PCRF_AC_XPDC_WIDTH 8
2234 #define	PCRF_AC_XPHC_LBN 0
2235 #define	PCRF_AC_XPHC_WIDTH 12
2236 
2237 
2238 /*
2239  * PC_XNPFCC_STAT_REG(24bit):
2240  * documentation to be written for sum_PC_XNPFCC_STAT_REG
2241  */
2242 
2243 #define	PCR_AC_XNPFCC_STAT_REG 0x00000734
2244 /* falcona0,falconb0,sienaa0=pci_f0_config */
2245 
2246 #define	PCRF_AC_XNPDC_LBN 12
2247 #define	PCRF_AC_XNPDC_WIDTH 8
2248 #define	PCRF_AC_XNPHC_LBN 0
2249 #define	PCRF_AC_XNPHC_WIDTH 12
2250 
2251 
2252 /*
2253  * PC_XCFCC_STAT_REG(24bit):
2254  * documentation to be written for sum_PC_XCFCC_STAT_REG
2255  */
2256 
2257 #define	PCR_AC_XCFCC_STAT_REG 0x00000738
2258 /* falcona0,falconb0,sienaa0=pci_f0_config */
2259 
2260 #define	PCRF_AC_XCDC_LBN 12
2261 #define	PCRF_AC_XCDC_WIDTH 8
2262 #define	PCRF_AC_XCHC_LBN 0
2263 #define	PCRF_AC_XCHC_WIDTH 12
2264 
2265 
2266 /*
2267  * PC_Q_STAT_REG(8bit):
2268  * documentation to be written for sum_PC_Q_STAT_REG
2269  */
2270 
2271 #define	PCR_AC_Q_STAT_REG 0x0000073c
2272 /* falcona0,falconb0,sienaa0=pci_f0_config */
2273 
2274 #define	PCRF_AC_RQNE_LBN 2
2275 #define	PCRF_AC_RQNE_WIDTH 1
2276 #define	PCRF_AC_XRNE_LBN 1
2277 #define	PCRF_AC_XRNE_WIDTH 1
2278 #define	PCRF_AC_RCNR_LBN 0
2279 #define	PCRF_AC_RCNR_WIDTH 1
2280 
2281 
2282 /*
2283  * PC_VC_XMIT_ARB1_REG(32bit):
2284  * VC Transmit Arbitration Register 1
2285  */
2286 
2287 #define	PCR_CC_VC_XMIT_ARB1_REG 0x00000740
2288 /* sienaa0=pci_f0_config */
2289 
2290 
2291 
2292 /*
2293  * PC_VC_XMIT_ARB2_REG(32bit):
2294  * VC Transmit Arbitration Register 2
2295  */
2296 
2297 #define	PCR_CC_VC_XMIT_ARB2_REG 0x00000744
2298 /* sienaa0=pci_f0_config */
2299 
2300 
2301 
2302 /*
2303  * PC_VC0_P_RQ_CTL_REG(32bit):
2304  * VC0 Posted Receive Queue Control
2305  */
2306 
2307 #define	PCR_CC_VC0_P_RQ_CTL_REG 0x00000748
2308 /* sienaa0=pci_f0_config */
2309 
2310 
2311 
2312 /*
2313  * PC_VC0_NP_RQ_CTL_REG(32bit):
2314  * VC0 Non-Posted Receive Queue Control
2315  */
2316 
2317 #define	PCR_CC_VC0_NP_RQ_CTL_REG 0x0000074c
2318 /* sienaa0=pci_f0_config */
2319 
2320 
2321 
2322 /*
2323  * PC_VC0_C_RQ_CTL_REG(32bit):
2324  * VC0 Completion Receive Queue Control
2325  */
2326 
2327 #define	PCR_CC_VC0_C_RQ_CTL_REG 0x00000750
2328 /* sienaa0=pci_f0_config */
2329 
2330 
2331 
2332 /*
2333  * PC_GEN2_REG(32bit):
2334  * Gen2 Register
2335  */
2336 
2337 #define	PCR_CC_GEN2_REG 0x0000080c
2338 /* sienaa0=pci_f0_config */
2339 
2340 #define	PCRF_CC_SET_DE_EMPHASIS_LBN 20
2341 #define	PCRF_CC_SET_DE_EMPHASIS_WIDTH 1
2342 #define	PCRF_CC_CFG_TX_COMPLIANCE_LBN 19
2343 #define	PCRF_CC_CFG_TX_COMPLIANCE_WIDTH 1
2344 #define	PCRF_CC_CFG_TX_SWING_LBN 18
2345 #define	PCRF_CC_CFG_TX_SWING_WIDTH 1
2346 #define	PCRF_CC_DIR_SPEED_CHANGE_LBN 17
2347 #define	PCRF_CC_DIR_SPEED_CHANGE_WIDTH 1
2348 #define	PCRF_CC_LANE_ENABLE_LBN 8
2349 #define	PCRF_CC_LANE_ENABLE_WIDTH 9
2350 #define	PCRF_CC_NUM_FTS_LBN 0
2351 #define	PCRF_CC_NUM_FTS_WIDTH 8
2352 
2353 
2354 #ifdef	__cplusplus
2355 }
2356 #endif
2357 
2358 #endif /* _SYS_EFX_REGS_PCI_H */
2359