1 /*- 2 * Copyright 2008-2013 Solarflare Communications Inc. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #ifndef _SIENA_MC_DRIVER_PCOL_H 29 #define _SIENA_MC_DRIVER_PCOL_H 30 31 32 /* Values to be written into FMCR_CZ_RESET_STATE_REG to control boot. */ 33 /* Power-on reset state */ 34 #define MC_FW_STATE_POR (1) 35 /* If this is set in MC_RESET_STATE_REG then it should be 36 * possible to jump into IMEM without loading code from flash. */ 37 #define MC_FW_WARM_BOOT_OK (2) 38 /* The MC main image has started to boot. */ 39 #define MC_FW_STATE_BOOTING (4) 40 /* The Scheduler has started. */ 41 #define MC_FW_STATE_SCHED (8) 42 /* If this is set in MC_RESET_STATE_REG then it should be 43 * possible to jump into IMEM without loading code from flash. 44 * Unlike a warm boot, assume DMEM has been reloaded, so that 45 * the MC persistent data must be reinitialised. */ 46 #define MC_FW_TEPID_BOOT_OK (16) 47 /* We have entered the main firmware via recovery mode. This 48 * means that MC persistent data must be reinitialised, but that 49 * we shouldn't touch PCIe config. */ 50 #define MC_FW_RECOVERY_MODE_PCIE_INIT_OK (32) 51 /* BIST state has been initialized */ 52 #define MC_FW_BIST_INIT_OK (128) 53 54 /* Siena MC shared memmory offsets */ 55 /* The 'doorbell' addresses are hard-wired to alert the MC when written */ 56 #define MC_SMEM_P0_DOORBELL_OFST 0x000 57 #define MC_SMEM_P1_DOORBELL_OFST 0x004 58 /* The rest of these are firmware-defined */ 59 #define MC_SMEM_P0_PDU_OFST 0x008 60 #define MC_SMEM_P1_PDU_OFST 0x108 61 #define MC_SMEM_PDU_LEN 0x100 62 #define MC_SMEM_P0_PTP_TIME_OFST 0x7f0 63 #define MC_SMEM_P0_STATUS_OFST 0x7f8 64 #define MC_SMEM_P1_STATUS_OFST 0x7fc 65 66 /* Values to be written to the per-port status dword in shared 67 * memory on reboot and assert */ 68 #define MC_STATUS_DWORD_REBOOT (0xb007b007) 69 #define MC_STATUS_DWORD_ASSERT (0xdeaddead) 70 71 /* Check whether an mcfw version (in host order) belongs to a bootloader */ 72 #define MC_FW_VERSION_IS_BOOTLOADER(_v) (((_v) >> 16) == 0xb007) 73 74 /* The current version of the MCDI protocol. 75 * 76 * Note that the ROM burnt into the card only talks V0, so at the very 77 * least every driver must support version 0 and MCDI_PCOL_VERSION 78 */ 79 #ifdef WITH_MCDI_V2 80 #define MCDI_PCOL_VERSION 2 81 #else 82 #define MCDI_PCOL_VERSION 1 83 #endif 84 85 /* Unused commands: 0x23, 0x27, 0x30, 0x31 */ 86 87 /* MCDI version 1 88 * 89 * Each MCDI request starts with an MCDI_HEADER, which is a 32bit 90 * structure, filled in by the client. 91 * 92 * 0 7 8 16 20 22 23 24 31 93 * | CODE | R | LEN | SEQ | Rsvd | E | R | XFLAGS | 94 * | | | 95 * | | \--- Response 96 * | \------- Error 97 * \------------------------------ Resync (always set) 98 * 99 * The client writes it's request into MC shared memory, and rings the 100 * doorbell. Each request is completed by either by the MC writting 101 * back into shared memory, or by writting out an event. 102 * 103 * All MCDI commands support completion by shared memory response. Each 104 * request may also contain additional data (accounted for by HEADER.LEN), 105 * and some response's may also contain additional data (again, accounted 106 * for by HEADER.LEN). 107 * 108 * Some MCDI commands support completion by event, in which any associated 109 * response data is included in the event. 110 * 111 * The protocol requires one response to be delivered for every request, a 112 * request should not be sent unless the response for the previous request 113 * has been received (either by polling shared memory, or by receiving 114 * an event). 115 */ 116 117 /** Request/Response structure */ 118 #define MCDI_HEADER_OFST 0 119 #define MCDI_HEADER_CODE_LBN 0 120 #define MCDI_HEADER_CODE_WIDTH 7 121 #define MCDI_HEADER_RESYNC_LBN 7 122 #define MCDI_HEADER_RESYNC_WIDTH 1 123 #define MCDI_HEADER_DATALEN_LBN 8 124 #define MCDI_HEADER_DATALEN_WIDTH 8 125 #define MCDI_HEADER_SEQ_LBN 16 126 #define MCDI_HEADER_SEQ_WIDTH 4 127 #define MCDI_HEADER_RSVD_LBN 20 128 #define MCDI_HEADER_RSVD_WIDTH 1 129 #define MCDI_HEADER_NOT_EPOCH_LBN 21 130 #define MCDI_HEADER_NOT_EPOCH_WIDTH 1 131 #define MCDI_HEADER_ERROR_LBN 22 132 #define MCDI_HEADER_ERROR_WIDTH 1 133 #define MCDI_HEADER_RESPONSE_LBN 23 134 #define MCDI_HEADER_RESPONSE_WIDTH 1 135 #define MCDI_HEADER_XFLAGS_LBN 24 136 #define MCDI_HEADER_XFLAGS_WIDTH 8 137 /* Request response using event */ 138 #define MCDI_HEADER_XFLAGS_EVREQ 0x01 139 /* Request (and signal) early doorbell return */ 140 #define MCDI_HEADER_XFLAGS_DBRET 0x02 141 142 /* Maximum number of payload bytes */ 143 #define MCDI_CTL_SDU_LEN_MAX_V1 0xfc 144 #define MCDI_CTL_SDU_LEN_MAX_V2 0x400 145 146 #ifdef WITH_MCDI_V2 147 #define MCDI_CTL_SDU_LEN_MAX MCDI_CTL_SDU_LEN_MAX_V2 148 #else 149 #define MCDI_CTL_SDU_LEN_MAX MCDI_CTL_SDU_LEN_MAX_V1 150 #endif 151 152 153 /* The MC can generate events for two reasons: 154 * - To advance a shared memory request if XFLAGS_EVREQ was set 155 * - As a notification (link state, i2c event), controlled 156 * via MC_CMD_LOG_CTRL 157 * 158 * Both events share a common structure: 159 * 160 * 0 32 33 36 44 52 60 161 * | Data | Cont | Level | Src | Code | Rsvd | 162 * | 163 * \ There is another event pending in this notification 164 * 165 * If Code==CMDDONE, then the fields are further interpreted as: 166 * 167 * - LEVEL==INFO Command succeeded 168 * - LEVEL==ERR Command failed 169 * 170 * 0 8 16 24 32 171 * | Seq | Datalen | Errno | Rsvd | 172 * 173 * These fields are taken directly out of the standard MCDI header, i.e., 174 * LEVEL==ERR, Datalen == 0 => Reboot 175 * 176 * Events can be squirted out of the UART (using LOG_CTRL) without a 177 * MCDI header. An event can be distinguished from a MCDI response by 178 * examining the first byte which is 0xc0. This corresponds to the 179 * non-existent MCDI command MC_CMD_DEBUG_LOG. 180 * 181 * 0 7 8 182 * | command | Resync | = 0xc0 183 * 184 * Since the event is written in big-endian byte order, this works 185 * providing bits 56-63 of the event are 0xc0. 186 * 187 * 56 60 63 188 * | Rsvd | Code | = 0xc0 189 * 190 * Which means for convenience the event code is 0xc for all MC 191 * generated events. 192 */ 193 #define FSE_AZ_EV_CODE_MCDI_EVRESPONSE 0xc 194 195 196 /* Operation not permitted. */ 197 #define MC_CMD_ERR_EPERM 1 198 /* Non-existent command target */ 199 #define MC_CMD_ERR_ENOENT 2 200 /* assert() has killed the MC */ 201 #define MC_CMD_ERR_EINTR 4 202 /* I/O failure */ 203 #define MC_CMD_ERR_EIO 5 204 /* Already exists */ 205 #define MC_CMD_ERR_EEXIST 6 206 /* Try again */ 207 #define MC_CMD_ERR_EAGAIN 11 208 /* Out of memory */ 209 #define MC_CMD_ERR_ENOMEM 12 210 /* Caller does not hold required locks */ 211 #define MC_CMD_ERR_EACCES 13 212 /* Resource is currently unavailable (e.g. lock contention) */ 213 #define MC_CMD_ERR_EBUSY 16 214 /* No such device */ 215 #define MC_CMD_ERR_ENODEV 19 216 /* Invalid argument to target */ 217 #define MC_CMD_ERR_EINVAL 22 218 /* Broken pipe */ 219 #define MC_CMD_ERR_EPIPE 32 220 /* Read-only */ 221 #define MC_CMD_ERR_EROFS 30 222 /* Out of range */ 223 #define MC_CMD_ERR_ERANGE 34 224 /* Non-recursive resource is already acquired */ 225 #define MC_CMD_ERR_EDEADLK 35 226 /* Operation not implemented */ 227 #define MC_CMD_ERR_ENOSYS 38 228 /* Operation timed out */ 229 #define MC_CMD_ERR_ETIME 62 230 /* Link has been severed */ 231 #define MC_CMD_ERR_ENOLINK 67 232 /* Protocol error */ 233 #define MC_CMD_ERR_EPROTO 71 234 /* Operation not supported */ 235 #define MC_CMD_ERR_ENOTSUP 95 236 /* Address not available */ 237 #define MC_CMD_ERR_EADDRNOTAVAIL 99 238 /* Not connected */ 239 #define MC_CMD_ERR_ENOTCONN 107 240 /* Operation already in progress */ 241 #define MC_CMD_ERR_EALREADY 114 242 243 /* Resource allocation failed. */ 244 #define MC_CMD_ERR_ALLOC_FAIL 0x1000 245 /* V-adaptor not found. */ 246 #define MC_CMD_ERR_NO_VADAPTOR 0x1001 247 /* EVB port not found. */ 248 #define MC_CMD_ERR_NO_EVB_PORT 0x1002 249 /* V-switch not found. */ 250 #define MC_CMD_ERR_NO_VSWITCH 0x1003 251 /* Too many VLAN tags. */ 252 #define MC_CMD_ERR_VLAN_LIMIT 0x1004 253 /* Bad PCI function number. */ 254 #define MC_CMD_ERR_BAD_PCI_FUNC 0x1005 255 /* Invalid VLAN mode. */ 256 #define MC_CMD_ERR_BAD_VLAN_MODE 0x1006 257 /* Invalid v-switch type. */ 258 #define MC_CMD_ERR_BAD_VSWITCH_TYPE 0x1007 259 /* Invalid v-port type. */ 260 #define MC_CMD_ERR_BAD_VPORT_TYPE 0x1008 261 /* MAC address exists. */ 262 #define MC_CMD_ERR_MAC_EXIST 0x1009 263 /* Slave core not present */ 264 #define MC_CMD_ERR_SLAVE_NOT_PRESENT 0x100a 265 /* The datapath is disabled. */ 266 #define MC_CMD_ERR_DATAPATH_DISABLED 0x100b 267 /* The requesting client is not a function */ 268 #define MC_CMD_ERR_CLIENT_NOT_FN 0x100c 269 /* The requested operation might require the 270 command to be passed between MCs, and the 271 transport doesn't support that. Should 272 only ever been seen over the UART. */ 273 #define MC_CMD_ERR_TRANSPORT_NOPROXY 0x100d 274 /* VLAN tag(s) exists */ 275 #define MC_CMD_ERR_VLAN_EXIST 0x100e 276 /* No MAC address assigned to an EVB port */ 277 #define MC_CMD_ERR_NO_MAC_ADDR 0x100f 278 /* Notifies the driver that the request has been relayed 279 * to an admin function for authorization. The driver should 280 * wait for a PROXY_RESPONSE event and then resend its request. 281 * This error code is followed by a 32-bit handle that 282 * helps matching it with the respective PROXY_RESPONSE event. */ 283 #define MC_CMD_ERR_PROXY_PENDING 0x1010 284 #define MC_CMD_ERR_PROXY_PENDING_HANDLE_OFST 4 285 /* The request cannot be passed for authorization because 286 * another request from the same function is currently being 287 * authorized. The drvier should try again later. */ 288 #define MC_CMD_ERR_PROXY_INPROGRESS 0x1011 289 /* Returned by MC_CMD_PROXY_COMPLETE if the caller is not the function 290 * that has enabled proxying or BLOCK_INDEX points to a function that 291 * doesn't await an authorization. */ 292 #define MC_CMD_ERR_PROXY_UNEXPECTED 0x1012 293 /* This code is currently only used internally in FW. Its meaning is that 294 * an operation failed due to lack of SR-IOV privilege. 295 * Normally it is translated to EPERM by send_cmd_err(), 296 * but it may also be used to trigger some special mechanism 297 * for handling such case, e.g. to relay the failed request 298 * to a designated admin function for authorization. */ 299 #define MC_CMD_ERR_NO_PRIVILEGE 0x1013 300 /* Workaround 26807 could not be turned on/off because some functions 301 * have already installed filters. See the comment at 302 * MC_CMD_WORKAROUND_BUG26807. */ 303 #define MC_CMD_ERR_FILTERS_PRESENT 0x1014 304 /* The clock whose frequency you've attempted to set set 305 * doesn't exist on this NIC */ 306 #define MC_CMD_ERR_NO_CLOCK 0x1015 307 /* Returned by MC_CMD_TESTASSERT if the action that should 308 * have caused an assertion failed to do so. */ 309 #define MC_CMD_ERR_UNREACHABLE 0x1016 310 /* This command needs to be processed in the background but there were no 311 * resources to do so. Send it again after a command has completed. */ 312 #define MC_CMD_ERR_QUEUE_FULL 0x1017 313 314 #define MC_CMD_ERR_CODE_OFST 0 315 316 /* We define 8 "escape" commands to allow 317 for command number space extension */ 318 319 #define MC_CMD_CMD_SPACE_ESCAPE_0 0x78 320 #define MC_CMD_CMD_SPACE_ESCAPE_1 0x79 321 #define MC_CMD_CMD_SPACE_ESCAPE_2 0x7A 322 #define MC_CMD_CMD_SPACE_ESCAPE_3 0x7B 323 #define MC_CMD_CMD_SPACE_ESCAPE_4 0x7C 324 #define MC_CMD_CMD_SPACE_ESCAPE_5 0x7D 325 #define MC_CMD_CMD_SPACE_ESCAPE_6 0x7E 326 #define MC_CMD_CMD_SPACE_ESCAPE_7 0x7F 327 328 /* Vectors in the boot ROM */ 329 /* Point to the copycode entry point. */ 330 #define SIENA_MC_BOOTROM_COPYCODE_VEC (0x800 - 3 * 0x4) 331 #define HUNT_MC_BOOTROM_COPYCODE_VEC (0x8000 - 3 * 0x4) 332 #define MEDFORD_MC_BOOTROM_COPYCODE_VEC (0x10000 - 3 * 0x4) 333 /* Points to the recovery mode entry point. */ 334 #define SIENA_MC_BOOTROM_NOFLASH_VEC (0x800 - 2 * 0x4) 335 #define HUNT_MC_BOOTROM_NOFLASH_VEC (0x8000 - 2 * 0x4) 336 #define MEDFORD_MC_BOOTROM_NOFLASH_VEC (0x10000 - 2 * 0x4) 337 338 /* The command set exported by the boot ROM (MCDI v0) */ 339 #define MC_CMD_GET_VERSION_V0_SUPPORTED_FUNCS { \ 340 (1 << MC_CMD_READ32) | \ 341 (1 << MC_CMD_WRITE32) | \ 342 (1 << MC_CMD_COPYCODE) | \ 343 (1 << MC_CMD_GET_VERSION), \ 344 0, 0, 0 } 345 346 #define MC_CMD_SENSOR_INFO_OUT_OFFSET_OFST(_x) \ 347 (MC_CMD_SENSOR_ENTRY_OFST + (_x)) 348 349 #define MC_CMD_DBI_WRITE_IN_ADDRESS_OFST(n) \ 350 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \ 351 MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST + \ 352 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN) 353 354 #define MC_CMD_DBI_WRITE_IN_BYTE_MASK_OFST(n) \ 355 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \ 356 MC_CMD_DBIWROP_TYPEDEF_BYTE_MASK_OFST + \ 357 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN) 358 359 #define MC_CMD_DBI_WRITE_IN_VALUE_OFST(n) \ 360 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \ 361 MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST + \ 362 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN) 363 364 /* This may be ORed with an EVB_PORT_ID_xxx constant to pass a non-default 365 * stack ID (which must be in the range 1-255) along with an EVB port ID. 366 */ 367 #define EVB_STACK_ID(n) (((n) & 0xff) << 16) 368 369 370 #ifdef WITH_MCDI_V2 371 372 /* Version 2 adds an optional argument to error returns: the errno value 373 * may be followed by the (0-based) number of the first argument that 374 * could not be processed. 375 */ 376 #define MC_CMD_ERR_ARG_OFST 4 377 378 /* No space */ 379 #define MC_CMD_ERR_ENOSPC 28 380 381 #endif 382 383 /* MCDI_EVENT structuredef */ 384 #define MCDI_EVENT_LEN 8 385 #define MCDI_EVENT_CONT_LBN 32 386 #define MCDI_EVENT_CONT_WIDTH 1 387 #define MCDI_EVENT_LEVEL_LBN 33 388 #define MCDI_EVENT_LEVEL_WIDTH 3 389 /* enum: Info. */ 390 #define MCDI_EVENT_LEVEL_INFO 0x0 391 /* enum: Warning. */ 392 #define MCDI_EVENT_LEVEL_WARN 0x1 393 /* enum: Error. */ 394 #define MCDI_EVENT_LEVEL_ERR 0x2 395 /* enum: Fatal. */ 396 #define MCDI_EVENT_LEVEL_FATAL 0x3 397 #define MCDI_EVENT_DATA_OFST 0 398 #define MCDI_EVENT_CMDDONE_SEQ_LBN 0 399 #define MCDI_EVENT_CMDDONE_SEQ_WIDTH 8 400 #define MCDI_EVENT_CMDDONE_DATALEN_LBN 8 401 #define MCDI_EVENT_CMDDONE_DATALEN_WIDTH 8 402 #define MCDI_EVENT_CMDDONE_ERRNO_LBN 16 403 #define MCDI_EVENT_CMDDONE_ERRNO_WIDTH 8 404 #define MCDI_EVENT_LINKCHANGE_LP_CAP_LBN 0 405 #define MCDI_EVENT_LINKCHANGE_LP_CAP_WIDTH 16 406 #define MCDI_EVENT_LINKCHANGE_SPEED_LBN 16 407 #define MCDI_EVENT_LINKCHANGE_SPEED_WIDTH 4 408 /* enum: 100Mbs */ 409 #define MCDI_EVENT_LINKCHANGE_SPEED_100M 0x1 410 /* enum: 1Gbs */ 411 #define MCDI_EVENT_LINKCHANGE_SPEED_1G 0x2 412 /* enum: 10Gbs */ 413 #define MCDI_EVENT_LINKCHANGE_SPEED_10G 0x3 414 /* enum: 40Gbs */ 415 #define MCDI_EVENT_LINKCHANGE_SPEED_40G 0x4 416 #define MCDI_EVENT_LINKCHANGE_FCNTL_LBN 20 417 #define MCDI_EVENT_LINKCHANGE_FCNTL_WIDTH 4 418 #define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_LBN 24 419 #define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_WIDTH 8 420 #define MCDI_EVENT_SENSOREVT_MONITOR_LBN 0 421 #define MCDI_EVENT_SENSOREVT_MONITOR_WIDTH 8 422 #define MCDI_EVENT_SENSOREVT_STATE_LBN 8 423 #define MCDI_EVENT_SENSOREVT_STATE_WIDTH 8 424 #define MCDI_EVENT_SENSOREVT_VALUE_LBN 16 425 #define MCDI_EVENT_SENSOREVT_VALUE_WIDTH 16 426 #define MCDI_EVENT_FWALERT_DATA_LBN 8 427 #define MCDI_EVENT_FWALERT_DATA_WIDTH 24 428 #define MCDI_EVENT_FWALERT_REASON_LBN 0 429 #define MCDI_EVENT_FWALERT_REASON_WIDTH 8 430 /* enum: SRAM Access. */ 431 #define MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS 0x1 432 #define MCDI_EVENT_FLR_VF_LBN 0 433 #define MCDI_EVENT_FLR_VF_WIDTH 8 434 #define MCDI_EVENT_TX_ERR_TXQ_LBN 0 435 #define MCDI_EVENT_TX_ERR_TXQ_WIDTH 12 436 #define MCDI_EVENT_TX_ERR_TYPE_LBN 12 437 #define MCDI_EVENT_TX_ERR_TYPE_WIDTH 4 438 /* enum: Descriptor loader reported failure */ 439 #define MCDI_EVENT_TX_ERR_DL_FAIL 0x1 440 /* enum: Descriptor ring empty and no EOP seen for packet */ 441 #define MCDI_EVENT_TX_ERR_NO_EOP 0x2 442 /* enum: Overlength packet */ 443 #define MCDI_EVENT_TX_ERR_2BIG 0x3 444 /* enum: Malformed option descriptor */ 445 #define MCDI_EVENT_TX_BAD_OPTDESC 0x5 446 /* enum: Option descriptor part way through a packet */ 447 #define MCDI_EVENT_TX_OPT_IN_PKT 0x8 448 /* enum: DMA or PIO data access error */ 449 #define MCDI_EVENT_TX_ERR_BAD_DMA_OR_PIO 0x9 450 #define MCDI_EVENT_TX_ERR_INFO_LBN 16 451 #define MCDI_EVENT_TX_ERR_INFO_WIDTH 16 452 #define MCDI_EVENT_TX_FLUSH_TO_DRIVER_LBN 12 453 #define MCDI_EVENT_TX_FLUSH_TO_DRIVER_WIDTH 1 454 #define MCDI_EVENT_TX_FLUSH_TXQ_LBN 0 455 #define MCDI_EVENT_TX_FLUSH_TXQ_WIDTH 12 456 #define MCDI_EVENT_PTP_ERR_TYPE_LBN 0 457 #define MCDI_EVENT_PTP_ERR_TYPE_WIDTH 8 458 /* enum: PLL lost lock */ 459 #define MCDI_EVENT_PTP_ERR_PLL_LOST 0x1 460 /* enum: Filter overflow (PDMA) */ 461 #define MCDI_EVENT_PTP_ERR_FILTER 0x2 462 /* enum: FIFO overflow (FPGA) */ 463 #define MCDI_EVENT_PTP_ERR_FIFO 0x3 464 /* enum: Merge queue overflow */ 465 #define MCDI_EVENT_PTP_ERR_QUEUE 0x4 466 #define MCDI_EVENT_AOE_ERR_TYPE_LBN 0 467 #define MCDI_EVENT_AOE_ERR_TYPE_WIDTH 8 468 /* enum: AOE failed to load - no valid image? */ 469 #define MCDI_EVENT_AOE_NO_LOAD 0x1 470 /* enum: AOE FC reported an exception */ 471 #define MCDI_EVENT_AOE_FC_ASSERT 0x2 472 /* enum: AOE FC watchdogged */ 473 #define MCDI_EVENT_AOE_FC_WATCHDOG 0x3 474 /* enum: AOE FC failed to start */ 475 #define MCDI_EVENT_AOE_FC_NO_START 0x4 476 /* enum: Generic AOE fault - likely to have been reported via other means too 477 * but intended for use by aoex driver. 478 */ 479 #define MCDI_EVENT_AOE_FAULT 0x5 480 /* enum: Results of reprogramming the CPLD (status in AOE_ERR_DATA) */ 481 #define MCDI_EVENT_AOE_CPLD_REPROGRAMMED 0x6 482 /* enum: AOE loaded successfully */ 483 #define MCDI_EVENT_AOE_LOAD 0x7 484 /* enum: AOE DMA operation completed (LSB of HOST_HANDLE in AOE_ERR_DATA) */ 485 #define MCDI_EVENT_AOE_DMA 0x8 486 /* enum: AOE byteblaster connected/disconnected (Connection status in 487 * AOE_ERR_DATA) 488 */ 489 #define MCDI_EVENT_AOE_BYTEBLASTER 0x9 490 /* enum: DDR ECC status update */ 491 #define MCDI_EVENT_AOE_DDR_ECC_STATUS 0xa 492 /* enum: PTP status update */ 493 #define MCDI_EVENT_AOE_PTP_STATUS 0xb 494 /* enum: FPGA header incorrect */ 495 #define MCDI_EVENT_AOE_FPGA_LOAD_HEADER_ERR 0xc 496 /* enum: FPGA Powered Off due to error in powering up FPGA */ 497 #define MCDI_EVENT_AOE_FPGA_POWER_OFF 0xd 498 /* enum: AOE FPGA load failed due to MC to MUM communication failure */ 499 #define MCDI_EVENT_AOE_FPGA_LOAD_FAILED 0xe 500 /* enum: Notify that invalid flash type detected */ 501 #define MCDI_EVENT_AOE_INVALID_FPGA_FLASH_TYPE 0xf 502 /* enum: Notify that the attempt to run FPGA Controller firmware timedout */ 503 #define MCDI_EVENT_AOE_FC_RUN_TIMEDOUT 0x10 504 #define MCDI_EVENT_AOE_ERR_DATA_LBN 8 505 #define MCDI_EVENT_AOE_ERR_DATA_WIDTH 8 506 #define MCDI_EVENT_AOE_ERR_CODE_FPGA_HEADER_VERIFY_FAILED_LBN 8 507 #define MCDI_EVENT_AOE_ERR_CODE_FPGA_HEADER_VERIFY_FAILED_WIDTH 8 508 /* enum: Reading from NV failed */ 509 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_NV_READ_FAIL 0x0 510 /* enum: Invalid Magic Number if FPGA header */ 511 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_MAGIC_FAIL 0x1 512 /* enum: Invalid Silicon type detected in header */ 513 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_SILICON_TYPE 0x2 514 /* enum: Unsupported VRatio */ 515 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_VRATIO 0x3 516 /* enum: Unsupported DDR Type */ 517 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_TYPE 0x4 518 /* enum: DDR Voltage out of supported range */ 519 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_VOLTAGE 0x5 520 /* enum: Unsupported DDR speed */ 521 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_SPEED 0x6 522 /* enum: Unsupported DDR size */ 523 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_SIZE 0x7 524 /* enum: Unsupported DDR rank */ 525 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_RANK 0x8 526 #define MCDI_EVENT_AOE_ERR_CODE_INVALID_FPGA_FLASH_TYPE_INFO_LBN 8 527 #define MCDI_EVENT_AOE_ERR_CODE_INVALID_FPGA_FLASH_TYPE_INFO_WIDTH 8 528 /* enum: Primary boot flash */ 529 #define MCDI_EVENT_AOE_FLASH_TYPE_BOOT_PRIMARY 0x0 530 /* enum: Secondary boot flash */ 531 #define MCDI_EVENT_AOE_FLASH_TYPE_BOOT_SECONDARY 0x1 532 #define MCDI_EVENT_AOE_ERR_CODE_FPGA_POWER_OFF_LBN 8 533 #define MCDI_EVENT_AOE_ERR_CODE_FPGA_POWER_OFF_WIDTH 8 534 #define MCDI_EVENT_AOE_ERR_CODE_FPGA_LOAD_FAILED_LBN 8 535 #define MCDI_EVENT_AOE_ERR_CODE_FPGA_LOAD_FAILED_WIDTH 8 536 #define MCDI_EVENT_RX_ERR_RXQ_LBN 0 537 #define MCDI_EVENT_RX_ERR_RXQ_WIDTH 12 538 #define MCDI_EVENT_RX_ERR_TYPE_LBN 12 539 #define MCDI_EVENT_RX_ERR_TYPE_WIDTH 4 540 #define MCDI_EVENT_RX_ERR_INFO_LBN 16 541 #define MCDI_EVENT_RX_ERR_INFO_WIDTH 16 542 #define MCDI_EVENT_RX_FLUSH_TO_DRIVER_LBN 12 543 #define MCDI_EVENT_RX_FLUSH_TO_DRIVER_WIDTH 1 544 #define MCDI_EVENT_RX_FLUSH_RXQ_LBN 0 545 #define MCDI_EVENT_RX_FLUSH_RXQ_WIDTH 12 546 #define MCDI_EVENT_MC_REBOOT_COUNT_LBN 0 547 #define MCDI_EVENT_MC_REBOOT_COUNT_WIDTH 16 548 #define MCDI_EVENT_MUM_ERR_TYPE_LBN 0 549 #define MCDI_EVENT_MUM_ERR_TYPE_WIDTH 8 550 /* enum: MUM failed to load - no valid image? */ 551 #define MCDI_EVENT_MUM_NO_LOAD 0x1 552 /* enum: MUM f/w reported an exception */ 553 #define MCDI_EVENT_MUM_ASSERT 0x2 554 /* enum: MUM not kicking watchdog */ 555 #define MCDI_EVENT_MUM_WATCHDOG 0x3 556 #define MCDI_EVENT_MUM_ERR_DATA_LBN 8 557 #define MCDI_EVENT_MUM_ERR_DATA_WIDTH 8 558 #define MCDI_EVENT_DATA_LBN 0 559 #define MCDI_EVENT_DATA_WIDTH 32 560 #define MCDI_EVENT_SRC_LBN 36 561 #define MCDI_EVENT_SRC_WIDTH 8 562 #define MCDI_EVENT_EV_CODE_LBN 60 563 #define MCDI_EVENT_EV_CODE_WIDTH 4 564 #define MCDI_EVENT_CODE_LBN 44 565 #define MCDI_EVENT_CODE_WIDTH 8 566 /* enum: Event generated by host software */ 567 #define MCDI_EVENT_SW_EVENT 0x0 568 /* enum: Bad assert. */ 569 #define MCDI_EVENT_CODE_BADSSERT 0x1 570 /* enum: PM Notice. */ 571 #define MCDI_EVENT_CODE_PMNOTICE 0x2 572 /* enum: Command done. */ 573 #define MCDI_EVENT_CODE_CMDDONE 0x3 574 /* enum: Link change. */ 575 #define MCDI_EVENT_CODE_LINKCHANGE 0x4 576 /* enum: Sensor Event. */ 577 #define MCDI_EVENT_CODE_SENSOREVT 0x5 578 /* enum: Schedule error. */ 579 #define MCDI_EVENT_CODE_SCHEDERR 0x6 580 /* enum: Reboot. */ 581 #define MCDI_EVENT_CODE_REBOOT 0x7 582 /* enum: Mac stats DMA. */ 583 #define MCDI_EVENT_CODE_MAC_STATS_DMA 0x8 584 /* enum: Firmware alert. */ 585 #define MCDI_EVENT_CODE_FWALERT 0x9 586 /* enum: Function level reset. */ 587 #define MCDI_EVENT_CODE_FLR 0xa 588 /* enum: Transmit error */ 589 #define MCDI_EVENT_CODE_TX_ERR 0xb 590 /* enum: Tx flush has completed */ 591 #define MCDI_EVENT_CODE_TX_FLUSH 0xc 592 /* enum: PTP packet received timestamp */ 593 #define MCDI_EVENT_CODE_PTP_RX 0xd 594 /* enum: PTP NIC failure */ 595 #define MCDI_EVENT_CODE_PTP_FAULT 0xe 596 /* enum: PTP PPS event */ 597 #define MCDI_EVENT_CODE_PTP_PPS 0xf 598 /* enum: Rx flush has completed */ 599 #define MCDI_EVENT_CODE_RX_FLUSH 0x10 600 /* enum: Receive error */ 601 #define MCDI_EVENT_CODE_RX_ERR 0x11 602 /* enum: AOE fault */ 603 #define MCDI_EVENT_CODE_AOE 0x12 604 /* enum: Network port calibration failed (VCAL). */ 605 #define MCDI_EVENT_CODE_VCAL_FAIL 0x13 606 /* enum: HW PPS event */ 607 #define MCDI_EVENT_CODE_HW_PPS 0x14 608 /* enum: The MC has rebooted (huntington and later, siena uses CODE_REBOOT and 609 * a different format) 610 */ 611 #define MCDI_EVENT_CODE_MC_REBOOT 0x15 612 /* enum: the MC has detected a parity error */ 613 #define MCDI_EVENT_CODE_PAR_ERR 0x16 614 /* enum: the MC has detected a correctable error */ 615 #define MCDI_EVENT_CODE_ECC_CORR_ERR 0x17 616 /* enum: the MC has detected an uncorrectable error */ 617 #define MCDI_EVENT_CODE_ECC_FATAL_ERR 0x18 618 /* enum: The MC has entered offline BIST mode */ 619 #define MCDI_EVENT_CODE_MC_BIST 0x19 620 /* enum: PTP tick event providing current NIC time */ 621 #define MCDI_EVENT_CODE_PTP_TIME 0x1a 622 /* enum: MUM fault */ 623 #define MCDI_EVENT_CODE_MUM 0x1b 624 /* enum: notify the designated PF of a new authorization request */ 625 #define MCDI_EVENT_CODE_PROXY_REQUEST 0x1c 626 /* enum: notify a function that awaits an authorization that its request has 627 * been processed and it may now resend the command 628 */ 629 #define MCDI_EVENT_CODE_PROXY_RESPONSE 0x1d 630 /* enum: Artificial event generated by host and posted via MC for test 631 * purposes. 632 */ 633 #define MCDI_EVENT_CODE_TESTGEN 0xfa 634 #define MCDI_EVENT_CMDDONE_DATA_OFST 0 635 #define MCDI_EVENT_CMDDONE_DATA_LBN 0 636 #define MCDI_EVENT_CMDDONE_DATA_WIDTH 32 637 #define MCDI_EVENT_LINKCHANGE_DATA_OFST 0 638 #define MCDI_EVENT_LINKCHANGE_DATA_LBN 0 639 #define MCDI_EVENT_LINKCHANGE_DATA_WIDTH 32 640 #define MCDI_EVENT_SENSOREVT_DATA_OFST 0 641 #define MCDI_EVENT_SENSOREVT_DATA_LBN 0 642 #define MCDI_EVENT_SENSOREVT_DATA_WIDTH 32 643 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_OFST 0 644 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_LBN 0 645 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_WIDTH 32 646 #define MCDI_EVENT_TX_ERR_DATA_OFST 0 647 #define MCDI_EVENT_TX_ERR_DATA_LBN 0 648 #define MCDI_EVENT_TX_ERR_DATA_WIDTH 32 649 /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the seconds field of 650 * timestamp 651 */ 652 #define MCDI_EVENT_PTP_SECONDS_OFST 0 653 #define MCDI_EVENT_PTP_SECONDS_LBN 0 654 #define MCDI_EVENT_PTP_SECONDS_WIDTH 32 655 /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the major field of 656 * timestamp 657 */ 658 #define MCDI_EVENT_PTP_MAJOR_OFST 0 659 #define MCDI_EVENT_PTP_MAJOR_LBN 0 660 #define MCDI_EVENT_PTP_MAJOR_WIDTH 32 661 /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the nanoseconds field 662 * of timestamp 663 */ 664 #define MCDI_EVENT_PTP_NANOSECONDS_OFST 0 665 #define MCDI_EVENT_PTP_NANOSECONDS_LBN 0 666 #define MCDI_EVENT_PTP_NANOSECONDS_WIDTH 32 667 /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the minor field of 668 * timestamp 669 */ 670 #define MCDI_EVENT_PTP_MINOR_OFST 0 671 #define MCDI_EVENT_PTP_MINOR_LBN 0 672 #define MCDI_EVENT_PTP_MINOR_WIDTH 32 673 /* For CODE_PTP_RX events, the lowest four bytes of sourceUUID from PTP packet 674 */ 675 #define MCDI_EVENT_PTP_UUID_OFST 0 676 #define MCDI_EVENT_PTP_UUID_LBN 0 677 #define MCDI_EVENT_PTP_UUID_WIDTH 32 678 #define MCDI_EVENT_RX_ERR_DATA_OFST 0 679 #define MCDI_EVENT_RX_ERR_DATA_LBN 0 680 #define MCDI_EVENT_RX_ERR_DATA_WIDTH 32 681 #define MCDI_EVENT_PAR_ERR_DATA_OFST 0 682 #define MCDI_EVENT_PAR_ERR_DATA_LBN 0 683 #define MCDI_EVENT_PAR_ERR_DATA_WIDTH 32 684 #define MCDI_EVENT_ECC_CORR_ERR_DATA_OFST 0 685 #define MCDI_EVENT_ECC_CORR_ERR_DATA_LBN 0 686 #define MCDI_EVENT_ECC_CORR_ERR_DATA_WIDTH 32 687 #define MCDI_EVENT_ECC_FATAL_ERR_DATA_OFST 0 688 #define MCDI_EVENT_ECC_FATAL_ERR_DATA_LBN 0 689 #define MCDI_EVENT_ECC_FATAL_ERR_DATA_WIDTH 32 690 /* For CODE_PTP_TIME events, the major value of the PTP clock */ 691 #define MCDI_EVENT_PTP_TIME_MAJOR_OFST 0 692 #define MCDI_EVENT_PTP_TIME_MAJOR_LBN 0 693 #define MCDI_EVENT_PTP_TIME_MAJOR_WIDTH 32 694 /* For CODE_PTP_TIME events, bits 19-26 of the minor value of the PTP clock */ 695 #define MCDI_EVENT_PTP_TIME_MINOR_26_19_LBN 36 696 #define MCDI_EVENT_PTP_TIME_MINOR_26_19_WIDTH 8 697 /* For CODE_PTP_TIME events where report sync status is enabled, indicates 698 * whether the NIC clock has ever been set 699 */ 700 #define MCDI_EVENT_PTP_TIME_NIC_CLOCK_VALID_LBN 36 701 #define MCDI_EVENT_PTP_TIME_NIC_CLOCK_VALID_WIDTH 1 702 /* For CODE_PTP_TIME events where report sync status is enabled, indicates 703 * whether the NIC and System clocks are in sync 704 */ 705 #define MCDI_EVENT_PTP_TIME_HOST_NIC_IN_SYNC_LBN 37 706 #define MCDI_EVENT_PTP_TIME_HOST_NIC_IN_SYNC_WIDTH 1 707 /* For CODE_PTP_TIME events where report sync status is enabled, bits 21-26 of 708 * the minor value of the PTP clock 709 */ 710 #define MCDI_EVENT_PTP_TIME_MINOR_26_21_LBN 38 711 #define MCDI_EVENT_PTP_TIME_MINOR_26_21_WIDTH 6 712 #define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_OFST 0 713 #define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_LBN 0 714 #define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_WIDTH 32 715 #define MCDI_EVENT_PROXY_RESPONSE_HANDLE_OFST 0 716 #define MCDI_EVENT_PROXY_RESPONSE_HANDLE_LBN 0 717 #define MCDI_EVENT_PROXY_RESPONSE_HANDLE_WIDTH 32 718 /* Zero means that the request has been completed or authorized, and the driver 719 * should resend it. A non-zero value means that the authorization has been 720 * denied, and gives the reason. Typically it will be EPERM. 721 */ 722 #define MCDI_EVENT_PROXY_RESPONSE_RC_LBN 36 723 #define MCDI_EVENT_PROXY_RESPONSE_RC_WIDTH 8 724 725 /* FCDI_EVENT structuredef */ 726 #define FCDI_EVENT_LEN 8 727 #define FCDI_EVENT_CONT_LBN 32 728 #define FCDI_EVENT_CONT_WIDTH 1 729 #define FCDI_EVENT_LEVEL_LBN 33 730 #define FCDI_EVENT_LEVEL_WIDTH 3 731 /* enum: Info. */ 732 #define FCDI_EVENT_LEVEL_INFO 0x0 733 /* enum: Warning. */ 734 #define FCDI_EVENT_LEVEL_WARN 0x1 735 /* enum: Error. */ 736 #define FCDI_EVENT_LEVEL_ERR 0x2 737 /* enum: Fatal. */ 738 #define FCDI_EVENT_LEVEL_FATAL 0x3 739 #define FCDI_EVENT_DATA_OFST 0 740 #define FCDI_EVENT_LINK_STATE_STATUS_LBN 0 741 #define FCDI_EVENT_LINK_STATE_STATUS_WIDTH 1 742 #define FCDI_EVENT_LINK_DOWN 0x0 /* enum */ 743 #define FCDI_EVENT_LINK_UP 0x1 /* enum */ 744 #define FCDI_EVENT_DATA_LBN 0 745 #define FCDI_EVENT_DATA_WIDTH 32 746 #define FCDI_EVENT_SRC_LBN 36 747 #define FCDI_EVENT_SRC_WIDTH 8 748 #define FCDI_EVENT_EV_CODE_LBN 60 749 #define FCDI_EVENT_EV_CODE_WIDTH 4 750 #define FCDI_EVENT_CODE_LBN 44 751 #define FCDI_EVENT_CODE_WIDTH 8 752 /* enum: The FC was rebooted. */ 753 #define FCDI_EVENT_CODE_REBOOT 0x1 754 /* enum: Bad assert. */ 755 #define FCDI_EVENT_CODE_ASSERT 0x2 756 /* enum: DDR3 test result. */ 757 #define FCDI_EVENT_CODE_DDR_TEST_RESULT 0x3 758 /* enum: Link status. */ 759 #define FCDI_EVENT_CODE_LINK_STATE 0x4 760 /* enum: A timed read is ready to be serviced. */ 761 #define FCDI_EVENT_CODE_TIMED_READ 0x5 762 /* enum: One or more PPS IN events */ 763 #define FCDI_EVENT_CODE_PPS_IN 0x6 764 /* enum: Tick event from PTP clock */ 765 #define FCDI_EVENT_CODE_PTP_TICK 0x7 766 /* enum: ECC error counters */ 767 #define FCDI_EVENT_CODE_DDR_ECC_STATUS 0x8 768 /* enum: Current status of PTP */ 769 #define FCDI_EVENT_CODE_PTP_STATUS 0x9 770 /* enum: Port id config to map MC-FC port idx */ 771 #define FCDI_EVENT_CODE_PORT_CONFIG 0xa 772 /* enum: Boot result or error code */ 773 #define FCDI_EVENT_CODE_BOOT_RESULT 0xb 774 #define FCDI_EVENT_REBOOT_SRC_LBN 36 775 #define FCDI_EVENT_REBOOT_SRC_WIDTH 8 776 #define FCDI_EVENT_REBOOT_FC_FW 0x0 /* enum */ 777 #define FCDI_EVENT_REBOOT_FC_BOOTLOADER 0x1 /* enum */ 778 #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_OFST 0 779 #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_LBN 0 780 #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_WIDTH 32 781 #define FCDI_EVENT_ASSERT_TYPE_LBN 36 782 #define FCDI_EVENT_ASSERT_TYPE_WIDTH 8 783 #define FCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_LBN 36 784 #define FCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_WIDTH 8 785 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_OFST 0 786 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_LBN 0 787 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_WIDTH 32 788 #define FCDI_EVENT_LINK_STATE_DATA_OFST 0 789 #define FCDI_EVENT_LINK_STATE_DATA_LBN 0 790 #define FCDI_EVENT_LINK_STATE_DATA_WIDTH 32 791 #define FCDI_EVENT_PTP_STATE_OFST 0 792 #define FCDI_EVENT_PTP_UNDEFINED 0x0 /* enum */ 793 #define FCDI_EVENT_PTP_SETUP_FAILED 0x1 /* enum */ 794 #define FCDI_EVENT_PTP_OPERATIONAL 0x2 /* enum */ 795 #define FCDI_EVENT_PTP_STATE_LBN 0 796 #define FCDI_EVENT_PTP_STATE_WIDTH 32 797 #define FCDI_EVENT_DDR_ECC_STATUS_BANK_ID_LBN 36 798 #define FCDI_EVENT_DDR_ECC_STATUS_BANK_ID_WIDTH 8 799 #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_OFST 0 800 #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_LBN 0 801 #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_WIDTH 32 802 /* Index of MC port being referred to */ 803 #define FCDI_EVENT_PORT_CONFIG_SRC_LBN 36 804 #define FCDI_EVENT_PORT_CONFIG_SRC_WIDTH 8 805 /* FC Port index that matches the MC port index in SRC */ 806 #define FCDI_EVENT_PORT_CONFIG_DATA_OFST 0 807 #define FCDI_EVENT_PORT_CONFIG_DATA_LBN 0 808 #define FCDI_EVENT_PORT_CONFIG_DATA_WIDTH 32 809 #define FCDI_EVENT_BOOT_RESULT_OFST 0 810 /* Enum values, see field(s): */ 811 /* MC_CMD_AOE/MC_CMD_AOE_OUT_INFO/FC_BOOT_RESULT */ 812 #define FCDI_EVENT_BOOT_RESULT_LBN 0 813 #define FCDI_EVENT_BOOT_RESULT_WIDTH 32 814 815 /* FCDI_EXTENDED_EVENT_PPS structuredef: Extended FCDI event to send PPS events 816 * to the MC. Note that this structure | is overlayed over a normal FCDI event 817 * such that bits 32-63 containing | event code, level, source etc remain the 818 * same. In this case the data | field of the header is defined to be the 819 * number of timestamps 820 */ 821 #define FCDI_EXTENDED_EVENT_PPS_LENMIN 16 822 #define FCDI_EXTENDED_EVENT_PPS_LENMAX 248 823 #define FCDI_EXTENDED_EVENT_PPS_LEN(num) (8+8*(num)) 824 /* Number of timestamps following */ 825 #define FCDI_EXTENDED_EVENT_PPS_COUNT_OFST 0 826 #define FCDI_EXTENDED_EVENT_PPS_COUNT_LBN 0 827 #define FCDI_EXTENDED_EVENT_PPS_COUNT_WIDTH 32 828 /* Seconds field of a timestamp record */ 829 #define FCDI_EXTENDED_EVENT_PPS_SECONDS_OFST 8 830 #define FCDI_EXTENDED_EVENT_PPS_SECONDS_LBN 64 831 #define FCDI_EXTENDED_EVENT_PPS_SECONDS_WIDTH 32 832 /* Nanoseconds field of a timestamp record */ 833 #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_OFST 12 834 #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_LBN 96 835 #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_WIDTH 32 836 /* Timestamp records comprising the event */ 837 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_OFST 8 838 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LEN 8 839 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LO_OFST 8 840 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_HI_OFST 12 841 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MINNUM 1 842 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MAXNUM 30 843 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LBN 64 844 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_WIDTH 64 845 846 /* MUM_EVENT structuredef */ 847 #define MUM_EVENT_LEN 8 848 #define MUM_EVENT_CONT_LBN 32 849 #define MUM_EVENT_CONT_WIDTH 1 850 #define MUM_EVENT_LEVEL_LBN 33 851 #define MUM_EVENT_LEVEL_WIDTH 3 852 /* enum: Info. */ 853 #define MUM_EVENT_LEVEL_INFO 0x0 854 /* enum: Warning. */ 855 #define MUM_EVENT_LEVEL_WARN 0x1 856 /* enum: Error. */ 857 #define MUM_EVENT_LEVEL_ERR 0x2 858 /* enum: Fatal. */ 859 #define MUM_EVENT_LEVEL_FATAL 0x3 860 #define MUM_EVENT_DATA_OFST 0 861 #define MUM_EVENT_SENSOR_ID_LBN 0 862 #define MUM_EVENT_SENSOR_ID_WIDTH 8 863 /* Enum values, see field(s): */ 864 /* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */ 865 #define MUM_EVENT_SENSOR_STATE_LBN 8 866 #define MUM_EVENT_SENSOR_STATE_WIDTH 8 867 #define MUM_EVENT_PORT_PHY_READY_LBN 0 868 #define MUM_EVENT_PORT_PHY_READY_WIDTH 1 869 #define MUM_EVENT_PORT_PHY_LINK_UP_LBN 1 870 #define MUM_EVENT_PORT_PHY_LINK_UP_WIDTH 1 871 #define MUM_EVENT_PORT_PHY_TX_LOL_LBN 2 872 #define MUM_EVENT_PORT_PHY_TX_LOL_WIDTH 1 873 #define MUM_EVENT_PORT_PHY_RX_LOL_LBN 3 874 #define MUM_EVENT_PORT_PHY_RX_LOL_WIDTH 1 875 #define MUM_EVENT_PORT_PHY_TX_LOS_LBN 4 876 #define MUM_EVENT_PORT_PHY_TX_LOS_WIDTH 1 877 #define MUM_EVENT_PORT_PHY_RX_LOS_LBN 5 878 #define MUM_EVENT_PORT_PHY_RX_LOS_WIDTH 1 879 #define MUM_EVENT_PORT_PHY_TX_FAULT_LBN 6 880 #define MUM_EVENT_PORT_PHY_TX_FAULT_WIDTH 1 881 #define MUM_EVENT_DATA_LBN 0 882 #define MUM_EVENT_DATA_WIDTH 32 883 #define MUM_EVENT_SRC_LBN 36 884 #define MUM_EVENT_SRC_WIDTH 8 885 #define MUM_EVENT_EV_CODE_LBN 60 886 #define MUM_EVENT_EV_CODE_WIDTH 4 887 #define MUM_EVENT_CODE_LBN 44 888 #define MUM_EVENT_CODE_WIDTH 8 889 /* enum: The MUM was rebooted. */ 890 #define MUM_EVENT_CODE_REBOOT 0x1 891 /* enum: Bad assert. */ 892 #define MUM_EVENT_CODE_ASSERT 0x2 893 /* enum: Sensor failure. */ 894 #define MUM_EVENT_CODE_SENSOR 0x3 895 /* enum: Link fault has been asserted, or has cleared. */ 896 #define MUM_EVENT_CODE_QSFP_LASI_INTERRUPT 0x4 897 #define MUM_EVENT_SENSOR_DATA_OFST 0 898 #define MUM_EVENT_SENSOR_DATA_LBN 0 899 #define MUM_EVENT_SENSOR_DATA_WIDTH 32 900 #define MUM_EVENT_PORT_PHY_FLAGS_OFST 0 901 #define MUM_EVENT_PORT_PHY_FLAGS_LBN 0 902 #define MUM_EVENT_PORT_PHY_FLAGS_WIDTH 32 903 #define MUM_EVENT_PORT_PHY_COPPER_LEN_OFST 0 904 #define MUM_EVENT_PORT_PHY_COPPER_LEN_LBN 0 905 #define MUM_EVENT_PORT_PHY_COPPER_LEN_WIDTH 32 906 #define MUM_EVENT_PORT_PHY_CAPS_OFST 0 907 #define MUM_EVENT_PORT_PHY_CAPS_LBN 0 908 #define MUM_EVENT_PORT_PHY_CAPS_WIDTH 32 909 #define MUM_EVENT_PORT_PHY_TECH_OFST 0 910 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_UNKNOWN 0x0 /* enum */ 911 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_OPTICAL 0x1 /* enum */ 912 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_PASSIVE 0x2 /* enum */ 913 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_PASSIVE_EQUALIZED 0x3 /* enum */ 914 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_ACTIVE_LIMITING 0x4 /* enum */ 915 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_ACTIVE_LINEAR 0x5 /* enum */ 916 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_BASE_T 0x6 /* enum */ 917 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_LOOPBACK_PASSIVE 0x7 /* enum */ 918 #define MUM_EVENT_PORT_PHY_TECH_LBN 0 919 #define MUM_EVENT_PORT_PHY_TECH_WIDTH 32 920 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_LBN 36 921 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_WIDTH 4 922 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_FLAGS 0x0 /* enum */ 923 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_COPPER_LEN 0x1 /* enum */ 924 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_CAPS 0x2 /* enum */ 925 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_TECH 0x3 /* enum */ 926 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_MAX 0x4 /* enum */ 927 #define MUM_EVENT_PORT_PHY_SRC_PORT_NO_LBN 40 928 #define MUM_EVENT_PORT_PHY_SRC_PORT_NO_WIDTH 4 929 930 931 /***********************************/ 932 /* MC_CMD_READ32 933 * Read multiple 32byte words from MC memory. 934 */ 935 #define MC_CMD_READ32 0x1 936 #undef MC_CMD_0x1_PRIVILEGE_CTG 937 938 #define MC_CMD_0x1_PRIVILEGE_CTG SRIOV_CTG_ADMIN 939 940 /* MC_CMD_READ32_IN msgrequest */ 941 #define MC_CMD_READ32_IN_LEN 8 942 #define MC_CMD_READ32_IN_ADDR_OFST 0 943 #define MC_CMD_READ32_IN_NUMWORDS_OFST 4 944 945 /* MC_CMD_READ32_OUT msgresponse */ 946 #define MC_CMD_READ32_OUT_LENMIN 4 947 #define MC_CMD_READ32_OUT_LENMAX 252 948 #define MC_CMD_READ32_OUT_LEN(num) (0+4*(num)) 949 #define MC_CMD_READ32_OUT_BUFFER_OFST 0 950 #define MC_CMD_READ32_OUT_BUFFER_LEN 4 951 #define MC_CMD_READ32_OUT_BUFFER_MINNUM 1 952 #define MC_CMD_READ32_OUT_BUFFER_MAXNUM 63 953 954 955 /***********************************/ 956 /* MC_CMD_WRITE32 957 * Write multiple 32byte words to MC memory. 958 */ 959 #define MC_CMD_WRITE32 0x2 960 #undef MC_CMD_0x2_PRIVILEGE_CTG 961 962 #define MC_CMD_0x2_PRIVILEGE_CTG SRIOV_CTG_ADMIN 963 964 /* MC_CMD_WRITE32_IN msgrequest */ 965 #define MC_CMD_WRITE32_IN_LENMIN 8 966 #define MC_CMD_WRITE32_IN_LENMAX 252 967 #define MC_CMD_WRITE32_IN_LEN(num) (4+4*(num)) 968 #define MC_CMD_WRITE32_IN_ADDR_OFST 0 969 #define MC_CMD_WRITE32_IN_BUFFER_OFST 4 970 #define MC_CMD_WRITE32_IN_BUFFER_LEN 4 971 #define MC_CMD_WRITE32_IN_BUFFER_MINNUM 1 972 #define MC_CMD_WRITE32_IN_BUFFER_MAXNUM 62 973 974 /* MC_CMD_WRITE32_OUT msgresponse */ 975 #define MC_CMD_WRITE32_OUT_LEN 0 976 977 978 /***********************************/ 979 /* MC_CMD_COPYCODE 980 * Copy MC code between two locations and jump. 981 */ 982 #define MC_CMD_COPYCODE 0x3 983 #undef MC_CMD_0x3_PRIVILEGE_CTG 984 985 #define MC_CMD_0x3_PRIVILEGE_CTG SRIOV_CTG_ADMIN 986 987 /* MC_CMD_COPYCODE_IN msgrequest */ 988 #define MC_CMD_COPYCODE_IN_LEN 16 989 /* Source address 990 * 991 * The main image should be entered via a copy of a single word from and to a 992 * magic address, which controls various aspects of the boot. The magic address 993 * is a bitfield, with each bit as documented below. 994 */ 995 #define MC_CMD_COPYCODE_IN_SRC_ADDR_OFST 0 996 /* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT (see below) */ 997 #define MC_CMD_COPYCODE_HUNT_NO_MAGIC_ADDR 0x10000 998 /* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT and 999 * BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED (see below) 1000 */ 1001 #define MC_CMD_COPYCODE_HUNT_NO_DATAPATH_MAGIC_ADDR 0x1d0d0 1002 /* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT, 1003 * BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED and BOOT_MAGIC_IGNORE_CONFIG (see 1004 * below) 1005 */ 1006 #define MC_CMD_COPYCODE_HUNT_IGNORE_CONFIG_MAGIC_ADDR 0x1badc 1007 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_LBN 17 1008 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_WIDTH 1 1009 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_LBN 2 1010 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_WIDTH 1 1011 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_LBN 3 1012 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_WIDTH 1 1013 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_LBN 4 1014 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_WIDTH 1 1015 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_LBN 5 1016 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_WIDTH 1 1017 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_DISABLE_XIP_LBN 6 1018 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_DISABLE_XIP_WIDTH 1 1019 /* Destination address */ 1020 #define MC_CMD_COPYCODE_IN_DEST_ADDR_OFST 4 1021 #define MC_CMD_COPYCODE_IN_NUMWORDS_OFST 8 1022 /* Address of where to jump after copy. */ 1023 #define MC_CMD_COPYCODE_IN_JUMP_OFST 12 1024 /* enum: Control should return to the caller rather than jumping */ 1025 #define MC_CMD_COPYCODE_JUMP_NONE 0x1 1026 1027 /* MC_CMD_COPYCODE_OUT msgresponse */ 1028 #define MC_CMD_COPYCODE_OUT_LEN 0 1029 1030 1031 /***********************************/ 1032 /* MC_CMD_SET_FUNC 1033 * Select function for function-specific commands. 1034 */ 1035 #define MC_CMD_SET_FUNC 0x4 1036 #undef MC_CMD_0x4_PRIVILEGE_CTG 1037 1038 #define MC_CMD_0x4_PRIVILEGE_CTG SRIOV_CTG_ADMIN 1039 1040 /* MC_CMD_SET_FUNC_IN msgrequest */ 1041 #define MC_CMD_SET_FUNC_IN_LEN 4 1042 /* Set function */ 1043 #define MC_CMD_SET_FUNC_IN_FUNC_OFST 0 1044 1045 /* MC_CMD_SET_FUNC_OUT msgresponse */ 1046 #define MC_CMD_SET_FUNC_OUT_LEN 0 1047 1048 1049 /***********************************/ 1050 /* MC_CMD_GET_BOOT_STATUS 1051 * Get the instruction address from which the MC booted. 1052 */ 1053 #define MC_CMD_GET_BOOT_STATUS 0x5 1054 #undef MC_CMD_0x5_PRIVILEGE_CTG 1055 1056 #define MC_CMD_0x5_PRIVILEGE_CTG SRIOV_CTG_ADMIN 1057 1058 /* MC_CMD_GET_BOOT_STATUS_IN msgrequest */ 1059 #define MC_CMD_GET_BOOT_STATUS_IN_LEN 0 1060 1061 /* MC_CMD_GET_BOOT_STATUS_OUT msgresponse */ 1062 #define MC_CMD_GET_BOOT_STATUS_OUT_LEN 8 1063 /* ?? */ 1064 #define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_OFST 0 1065 /* enum: indicates that the MC wasn't flash booted */ 1066 #define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_NULL 0xdeadbeef 1067 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_OFST 4 1068 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_LBN 0 1069 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_WIDTH 1 1070 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_LBN 1 1071 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_WIDTH 1 1072 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_LBN 2 1073 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_WIDTH 1 1074 1075 1076 /***********************************/ 1077 /* MC_CMD_GET_ASSERTS 1078 * Get (and optionally clear) the current assertion status. Only 1079 * OUT.GLOBAL_FLAGS is guaranteed to exist in the completion payload. The other 1080 * fields will only be present if OUT.GLOBAL_FLAGS != NO_FAILS 1081 */ 1082 #define MC_CMD_GET_ASSERTS 0x6 1083 #undef MC_CMD_0x6_PRIVILEGE_CTG 1084 1085 #define MC_CMD_0x6_PRIVILEGE_CTG SRIOV_CTG_ADMIN 1086 1087 /* MC_CMD_GET_ASSERTS_IN msgrequest */ 1088 #define MC_CMD_GET_ASSERTS_IN_LEN 4 1089 /* Set to clear assertion */ 1090 #define MC_CMD_GET_ASSERTS_IN_CLEAR_OFST 0 1091 1092 /* MC_CMD_GET_ASSERTS_OUT msgresponse */ 1093 #define MC_CMD_GET_ASSERTS_OUT_LEN 140 1094 /* Assertion status flag. */ 1095 #define MC_CMD_GET_ASSERTS_OUT_GLOBAL_FLAGS_OFST 0 1096 /* enum: No assertions have failed. */ 1097 #define MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1 1098 /* enum: A system-level assertion has failed. */ 1099 #define MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2 1100 /* enum: A thread-level assertion has failed. */ 1101 #define MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3 1102 /* enum: The system was reset by the watchdog. */ 1103 #define MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4 1104 /* enum: An illegal address trap stopped the system (huntington and later) */ 1105 #define MC_CMD_GET_ASSERTS_FLAGS_ADDR_TRAP 0x5 1106 /* Failing PC value */ 1107 #define MC_CMD_GET_ASSERTS_OUT_SAVED_PC_OFFS_OFST 4 1108 /* Saved GP regs */ 1109 #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_OFST 8 1110 #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_LEN 4 1111 #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_NUM 31 1112 /* enum: A magic value hinting that the value in this register at the time of 1113 * the failure has likely been lost. 1114 */ 1115 #define MC_CMD_GET_ASSERTS_REG_NO_DATA 0xda7a1057 1116 /* Failing thread address */ 1117 #define MC_CMD_GET_ASSERTS_OUT_THREAD_OFFS_OFST 132 1118 #define MC_CMD_GET_ASSERTS_OUT_RESERVED_OFST 136 1119 1120 1121 /***********************************/ 1122 /* MC_CMD_LOG_CTRL 1123 * Configure the output stream for log events such as link state changes, 1124 * sensor notifications and MCDI completions 1125 */ 1126 #define MC_CMD_LOG_CTRL 0x7 1127 #undef MC_CMD_0x7_PRIVILEGE_CTG 1128 1129 #define MC_CMD_0x7_PRIVILEGE_CTG SRIOV_CTG_GENERAL 1130 1131 /* MC_CMD_LOG_CTRL_IN msgrequest */ 1132 #define MC_CMD_LOG_CTRL_IN_LEN 8 1133 /* Log destination */ 1134 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_OFST 0 1135 /* enum: UART. */ 1136 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_UART 0x1 1137 /* enum: Event queue. */ 1138 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ 0x2 1139 /* Legacy argument. Must be zero. */ 1140 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ_OFST 4 1141 1142 /* MC_CMD_LOG_CTRL_OUT msgresponse */ 1143 #define MC_CMD_LOG_CTRL_OUT_LEN 0 1144 1145 1146 /***********************************/ 1147 /* MC_CMD_GET_VERSION 1148 * Get version information about the MC firmware. 1149 */ 1150 #define MC_CMD_GET_VERSION 0x8 1151 #undef MC_CMD_0x8_PRIVILEGE_CTG 1152 1153 #define MC_CMD_0x8_PRIVILEGE_CTG SRIOV_CTG_GENERAL 1154 1155 /* MC_CMD_GET_VERSION_IN msgrequest */ 1156 #define MC_CMD_GET_VERSION_IN_LEN 0 1157 1158 /* MC_CMD_GET_VERSION_EXT_IN msgrequest: Asks for the extended version */ 1159 #define MC_CMD_GET_VERSION_EXT_IN_LEN 4 1160 /* placeholder, set to 0 */ 1161 #define MC_CMD_GET_VERSION_EXT_IN_EXT_FLAGS_OFST 0 1162 1163 /* MC_CMD_GET_VERSION_V0_OUT msgresponse: deprecated version format */ 1164 #define MC_CMD_GET_VERSION_V0_OUT_LEN 4 1165 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 1166 /* enum: Reserved version number to indicate "any" version. */ 1167 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_ANY 0xffffffff 1168 /* enum: Bootrom version value for Siena. */ 1169 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_SIENA_BOOTROM 0xb0070000 1170 /* enum: Bootrom version value for Huntington. */ 1171 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_HUNT_BOOTROM 0xb0070001 1172 1173 /* MC_CMD_GET_VERSION_OUT msgresponse */ 1174 #define MC_CMD_GET_VERSION_OUT_LEN 32 1175 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */ 1176 /* Enum values, see field(s): */ 1177 /* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */ 1178 #define MC_CMD_GET_VERSION_OUT_PCOL_OFST 4 1179 /* 128bit mask of functions supported by the current firmware */ 1180 #define MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_OFST 8 1181 #define MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_LEN 16 1182 #define MC_CMD_GET_VERSION_OUT_VERSION_OFST 24 1183 #define MC_CMD_GET_VERSION_OUT_VERSION_LEN 8 1184 #define MC_CMD_GET_VERSION_OUT_VERSION_LO_OFST 24 1185 #define MC_CMD_GET_VERSION_OUT_VERSION_HI_OFST 28 1186 1187 /* MC_CMD_GET_VERSION_EXT_OUT msgresponse */ 1188 #define MC_CMD_GET_VERSION_EXT_OUT_LEN 48 1189 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */ 1190 /* Enum values, see field(s): */ 1191 /* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */ 1192 #define MC_CMD_GET_VERSION_EXT_OUT_PCOL_OFST 4 1193 /* 128bit mask of functions supported by the current firmware */ 1194 #define MC_CMD_GET_VERSION_EXT_OUT_SUPPORTED_FUNCS_OFST 8 1195 #define MC_CMD_GET_VERSION_EXT_OUT_SUPPORTED_FUNCS_LEN 16 1196 #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_OFST 24 1197 #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LEN 8 1198 #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LO_OFST 24 1199 #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_HI_OFST 28 1200 /* extra info */ 1201 #define MC_CMD_GET_VERSION_EXT_OUT_EXTRA_OFST 32 1202 #define MC_CMD_GET_VERSION_EXT_OUT_EXTRA_LEN 16 1203 1204 1205 /***********************************/ 1206 /* MC_CMD_FC 1207 * Perform an FC operation 1208 */ 1209 #define MC_CMD_FC 0x9 1210 1211 /* MC_CMD_FC_IN msgrequest */ 1212 #define MC_CMD_FC_IN_LEN 4 1213 #define MC_CMD_FC_IN_OP_HDR_OFST 0 1214 #define MC_CMD_FC_IN_OP_LBN 0 1215 #define MC_CMD_FC_IN_OP_WIDTH 8 1216 /* enum: NULL MCDI command to FC. */ 1217 #define MC_CMD_FC_OP_NULL 0x1 1218 /* enum: Unused opcode */ 1219 #define MC_CMD_FC_OP_UNUSED 0x2 1220 /* enum: MAC driver commands */ 1221 #define MC_CMD_FC_OP_MAC 0x3 1222 /* enum: Read FC memory */ 1223 #define MC_CMD_FC_OP_READ32 0x4 1224 /* enum: Write to FC memory */ 1225 #define MC_CMD_FC_OP_WRITE32 0x5 1226 /* enum: Read FC memory */ 1227 #define MC_CMD_FC_OP_TRC_READ 0x6 1228 /* enum: Write to FC memory */ 1229 #define MC_CMD_FC_OP_TRC_WRITE 0x7 1230 /* enum: FC firmware Version */ 1231 #define MC_CMD_FC_OP_GET_VERSION 0x8 1232 /* enum: Read FC memory */ 1233 #define MC_CMD_FC_OP_TRC_RX_READ 0x9 1234 /* enum: Write to FC memory */ 1235 #define MC_CMD_FC_OP_TRC_RX_WRITE 0xa 1236 /* enum: SFP parameters */ 1237 #define MC_CMD_FC_OP_SFP 0xb 1238 /* enum: DDR3 test */ 1239 #define MC_CMD_FC_OP_DDR_TEST 0xc 1240 /* enum: Get Crash context from FC */ 1241 #define MC_CMD_FC_OP_GET_ASSERT 0xd 1242 /* enum: Get FPGA Build registers */ 1243 #define MC_CMD_FC_OP_FPGA_BUILD 0xe 1244 /* enum: Read map support commands */ 1245 #define MC_CMD_FC_OP_READ_MAP 0xf 1246 /* enum: FC Capabilities */ 1247 #define MC_CMD_FC_OP_CAPABILITIES 0x10 1248 /* enum: FC Global flags */ 1249 #define MC_CMD_FC_OP_GLOBAL_FLAGS 0x11 1250 /* enum: FC IO using relative addressing modes */ 1251 #define MC_CMD_FC_OP_IO_REL 0x12 1252 /* enum: FPGA link information */ 1253 #define MC_CMD_FC_OP_UHLINK 0x13 1254 /* enum: Configure loopbacks and link on FPGA ports */ 1255 #define MC_CMD_FC_OP_SET_LINK 0x14 1256 /* enum: Licensing operations relating to AOE */ 1257 #define MC_CMD_FC_OP_LICENSE 0x15 1258 /* enum: Startup information to the FC */ 1259 #define MC_CMD_FC_OP_STARTUP 0x16 1260 /* enum: Configure a DMA read */ 1261 #define MC_CMD_FC_OP_DMA 0x17 1262 /* enum: Configure a timed read */ 1263 #define MC_CMD_FC_OP_TIMED_READ 0x18 1264 /* enum: Control UART logging */ 1265 #define MC_CMD_FC_OP_LOG 0x19 1266 /* enum: Get the value of a given clock_id */ 1267 #define MC_CMD_FC_OP_CLOCK 0x1a 1268 /* enum: DDR3/QDR3 parameters */ 1269 #define MC_CMD_FC_OP_DDR 0x1b 1270 /* enum: PTP and timestamp control */ 1271 #define MC_CMD_FC_OP_TIMESTAMP 0x1c 1272 /* enum: Commands for SPI Flash interface */ 1273 #define MC_CMD_FC_OP_SPI 0x1d 1274 /* enum: Commands for diagnostic components */ 1275 #define MC_CMD_FC_OP_DIAG 0x1e 1276 /* enum: External AOE port. */ 1277 #define MC_CMD_FC_IN_PORT_EXT_OFST 0x0 1278 /* enum: Internal AOE port. */ 1279 #define MC_CMD_FC_IN_PORT_INT_OFST 0x40 1280 1281 /* MC_CMD_FC_IN_NULL msgrequest */ 1282 #define MC_CMD_FC_IN_NULL_LEN 4 1283 #define MC_CMD_FC_IN_CMD_OFST 0 1284 1285 /* MC_CMD_FC_IN_PHY msgrequest */ 1286 #define MC_CMD_FC_IN_PHY_LEN 5 1287 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1288 /* FC PHY driver operation code */ 1289 #define MC_CMD_FC_IN_PHY_OP_OFST 4 1290 #define MC_CMD_FC_IN_PHY_OP_LEN 1 1291 /* enum: PHY init handler */ 1292 #define MC_CMD_FC_OP_PHY_OP_INIT 0x1 1293 /* enum: PHY reconfigure handler */ 1294 #define MC_CMD_FC_OP_PHY_OP_RECONFIGURE 0x2 1295 /* enum: PHY reboot handler */ 1296 #define MC_CMD_FC_OP_PHY_OP_REBOOT 0x3 1297 /* enum: PHY get_supported_cap handler */ 1298 #define MC_CMD_FC_OP_PHY_OP_GET_SUPPORTED_CAP 0x4 1299 /* enum: PHY get_config handler */ 1300 #define MC_CMD_FC_OP_PHY_OP_GET_CONFIG 0x5 1301 /* enum: PHY get_media_info handler */ 1302 #define MC_CMD_FC_OP_PHY_OP_GET_MEDIA_INFO 0x6 1303 /* enum: PHY set_led handler */ 1304 #define MC_CMD_FC_OP_PHY_OP_SET_LED 0x7 1305 /* enum: PHY lasi_interrupt handler */ 1306 #define MC_CMD_FC_OP_PHY_OP_LASI_INTERRUPT 0x8 1307 /* enum: PHY check_link handler */ 1308 #define MC_CMD_FC_OP_PHY_OP_CHECK_LINK 0x9 1309 /* enum: PHY fill_stats handler */ 1310 #define MC_CMD_FC_OP_PHY_OP_FILL_STATS 0xa 1311 /* enum: PHY bpx_link_state_changed handler */ 1312 #define MC_CMD_FC_OP_PHY_OP_BPX_LINK_STATE_CHANGED 0xb 1313 /* enum: PHY get_state handler */ 1314 #define MC_CMD_FC_OP_PHY_OP_GET_STATE 0xc 1315 /* enum: PHY start_bist handler */ 1316 #define MC_CMD_FC_OP_PHY_OP_START_BIST 0xd 1317 /* enum: PHY poll_bist handler */ 1318 #define MC_CMD_FC_OP_PHY_OP_POLL_BIST 0xe 1319 /* enum: PHY nvram_test handler */ 1320 #define MC_CMD_FC_OP_PHY_OP_NVRAM_TEST 0xf 1321 /* enum: PHY relinquish handler */ 1322 #define MC_CMD_FC_OP_PHY_OP_RELINQUISH_SPI 0x10 1323 /* enum: PHY read connection from FC - may be not required */ 1324 #define MC_CMD_FC_OP_PHY_OP_GET_CONNECTION 0x11 1325 /* enum: PHY read flags from FC - may be not required */ 1326 #define MC_CMD_FC_OP_PHY_OP_GET_FLAGS 0x12 1327 1328 /* MC_CMD_FC_IN_PHY_INIT msgrequest */ 1329 #define MC_CMD_FC_IN_PHY_INIT_LEN 4 1330 #define MC_CMD_FC_IN_PHY_CMD_OFST 0 1331 1332 /* MC_CMD_FC_IN_MAC msgrequest */ 1333 #define MC_CMD_FC_IN_MAC_LEN 8 1334 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1335 #define MC_CMD_FC_IN_MAC_HEADER_OFST 4 1336 #define MC_CMD_FC_IN_MAC_OP_LBN 0 1337 #define MC_CMD_FC_IN_MAC_OP_WIDTH 8 1338 /* enum: MAC reconfigure handler */ 1339 #define MC_CMD_FC_OP_MAC_OP_RECONFIGURE 0x1 1340 /* enum: MAC Set command - same as MC_CMD_SET_MAC */ 1341 #define MC_CMD_FC_OP_MAC_OP_SET_LINK 0x2 1342 /* enum: MAC statistics */ 1343 #define MC_CMD_FC_OP_MAC_OP_GET_STATS 0x3 1344 /* enum: MAC RX statistics */ 1345 #define MC_CMD_FC_OP_MAC_OP_GET_RX_STATS 0x6 1346 /* enum: MAC TX statistics */ 1347 #define MC_CMD_FC_OP_MAC_OP_GET_TX_STATS 0x7 1348 /* enum: MAC Read status */ 1349 #define MC_CMD_FC_OP_MAC_OP_READ_STATUS 0x8 1350 #define MC_CMD_FC_IN_MAC_PORT_TYPE_LBN 8 1351 #define MC_CMD_FC_IN_MAC_PORT_TYPE_WIDTH 8 1352 /* enum: External FPGA port. */ 1353 #define MC_CMD_FC_PORT_EXT 0x0 1354 /* enum: Internal Siena-facing FPGA ports. */ 1355 #define MC_CMD_FC_PORT_INT 0x1 1356 #define MC_CMD_FC_IN_MAC_PORT_IDX_LBN 16 1357 #define MC_CMD_FC_IN_MAC_PORT_IDX_WIDTH 8 1358 #define MC_CMD_FC_IN_MAC_CMD_FORMAT_LBN 24 1359 #define MC_CMD_FC_IN_MAC_CMD_FORMAT_WIDTH 8 1360 /* enum: Default FC command format; the fields PORT_TYPE and PORT_IDX are 1361 * irrelevant. Port number is derived from pci_fn; passed in FC header. 1362 */ 1363 #define MC_CMD_FC_OP_MAC_CMD_FORMAT_DEFAULT 0x0 1364 /* enum: Override default port number. Port number determined by fields 1365 * PORT_TYPE and PORT_IDX. 1366 */ 1367 #define MC_CMD_FC_OP_MAC_CMD_FORMAT_PORT_OVERRIDE 0x1 1368 1369 /* MC_CMD_FC_IN_MAC_RECONFIGURE msgrequest */ 1370 #define MC_CMD_FC_IN_MAC_RECONFIGURE_LEN 8 1371 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1372 /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ 1373 1374 /* MC_CMD_FC_IN_MAC_SET_LINK msgrequest */ 1375 #define MC_CMD_FC_IN_MAC_SET_LINK_LEN 32 1376 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1377 /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ 1378 /* MTU size */ 1379 #define MC_CMD_FC_IN_MAC_SET_LINK_MTU_OFST 8 1380 /* Drain Tx FIFO */ 1381 #define MC_CMD_FC_IN_MAC_SET_LINK_DRAIN_OFST 12 1382 #define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_OFST 16 1383 #define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_LEN 8 1384 #define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_LO_OFST 16 1385 #define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_HI_OFST 20 1386 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_OFST 24 1387 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_UNICAST_LBN 0 1388 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_UNICAST_WIDTH 1 1389 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_BRDCAST_LBN 1 1390 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_BRDCAST_WIDTH 1 1391 #define MC_CMD_FC_IN_MAC_SET_LINK_FCNTL_OFST 28 1392 1393 /* MC_CMD_FC_IN_MAC_READ_STATUS msgrequest */ 1394 #define MC_CMD_FC_IN_MAC_READ_STATUS_LEN 8 1395 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1396 /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ 1397 1398 /* MC_CMD_FC_IN_MAC_GET_RX_STATS msgrequest */ 1399 #define MC_CMD_FC_IN_MAC_GET_RX_STATS_LEN 8 1400 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1401 /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ 1402 1403 /* MC_CMD_FC_IN_MAC_GET_TX_STATS msgrequest */ 1404 #define MC_CMD_FC_IN_MAC_GET_TX_STATS_LEN 8 1405 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1406 /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ 1407 1408 /* MC_CMD_FC_IN_MAC_GET_STATS msgrequest */ 1409 #define MC_CMD_FC_IN_MAC_GET_STATS_LEN 20 1410 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1411 /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ 1412 /* MC Statistics index */ 1413 #define MC_CMD_FC_IN_MAC_GET_STATS_STATS_INDEX_OFST 8 1414 #define MC_CMD_FC_IN_MAC_GET_STATS_FLAGS_OFST 12 1415 #define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_ALL_LBN 0 1416 #define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_ALL_WIDTH 1 1417 #define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_LBN 1 1418 #define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_WIDTH 1 1419 #define MC_CMD_FC_IN_MAC_GET_STATS_UPDATE_LBN 2 1420 #define MC_CMD_FC_IN_MAC_GET_STATS_UPDATE_WIDTH 1 1421 /* Number of statistics to read */ 1422 #define MC_CMD_FC_IN_MAC_GET_STATS_NUM_OFST 16 1423 #define MC_CMD_FC_MAC_NSTATS_PER_BLOCK 0x1e /* enum */ 1424 #define MC_CMD_FC_MAC_NBYTES_PER_STAT 0x8 /* enum */ 1425 1426 /* MC_CMD_FC_IN_READ32 msgrequest */ 1427 #define MC_CMD_FC_IN_READ32_LEN 16 1428 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1429 #define MC_CMD_FC_IN_READ32_ADDR_HI_OFST 4 1430 #define MC_CMD_FC_IN_READ32_ADDR_LO_OFST 8 1431 #define MC_CMD_FC_IN_READ32_NUMWORDS_OFST 12 1432 1433 /* MC_CMD_FC_IN_WRITE32 msgrequest */ 1434 #define MC_CMD_FC_IN_WRITE32_LENMIN 16 1435 #define MC_CMD_FC_IN_WRITE32_LENMAX 252 1436 #define MC_CMD_FC_IN_WRITE32_LEN(num) (12+4*(num)) 1437 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1438 #define MC_CMD_FC_IN_WRITE32_ADDR_HI_OFST 4 1439 #define MC_CMD_FC_IN_WRITE32_ADDR_LO_OFST 8 1440 #define MC_CMD_FC_IN_WRITE32_BUFFER_OFST 12 1441 #define MC_CMD_FC_IN_WRITE32_BUFFER_LEN 4 1442 #define MC_CMD_FC_IN_WRITE32_BUFFER_MINNUM 1 1443 #define MC_CMD_FC_IN_WRITE32_BUFFER_MAXNUM 60 1444 1445 /* MC_CMD_FC_IN_TRC_READ msgrequest */ 1446 #define MC_CMD_FC_IN_TRC_READ_LEN 12 1447 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1448 #define MC_CMD_FC_IN_TRC_READ_TRC_OFST 4 1449 #define MC_CMD_FC_IN_TRC_READ_CHANNEL_OFST 8 1450 1451 /* MC_CMD_FC_IN_TRC_WRITE msgrequest */ 1452 #define MC_CMD_FC_IN_TRC_WRITE_LEN 28 1453 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1454 #define MC_CMD_FC_IN_TRC_WRITE_TRC_OFST 4 1455 #define MC_CMD_FC_IN_TRC_WRITE_CHANNEL_OFST 8 1456 #define MC_CMD_FC_IN_TRC_WRITE_DATA_OFST 12 1457 #define MC_CMD_FC_IN_TRC_WRITE_DATA_LEN 4 1458 #define MC_CMD_FC_IN_TRC_WRITE_DATA_NUM 4 1459 1460 /* MC_CMD_FC_IN_GET_VERSION msgrequest */ 1461 #define MC_CMD_FC_IN_GET_VERSION_LEN 4 1462 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1463 1464 /* MC_CMD_FC_IN_TRC_RX_READ msgrequest */ 1465 #define MC_CMD_FC_IN_TRC_RX_READ_LEN 12 1466 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1467 #define MC_CMD_FC_IN_TRC_RX_READ_TRC_OFST 4 1468 #define MC_CMD_FC_IN_TRC_RX_READ_CHANNEL_OFST 8 1469 1470 /* MC_CMD_FC_IN_TRC_RX_WRITE msgrequest */ 1471 #define MC_CMD_FC_IN_TRC_RX_WRITE_LEN 20 1472 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1473 #define MC_CMD_FC_IN_TRC_RX_WRITE_TRC_OFST 4 1474 #define MC_CMD_FC_IN_TRC_RX_WRITE_CHANNEL_OFST 8 1475 #define MC_CMD_FC_IN_TRC_RX_WRITE_DATA_OFST 12 1476 #define MC_CMD_FC_IN_TRC_RX_WRITE_DATA_LEN 4 1477 #define MC_CMD_FC_IN_TRC_RX_WRITE_DATA_NUM 2 1478 1479 /* MC_CMD_FC_IN_SFP msgrequest */ 1480 #define MC_CMD_FC_IN_SFP_LEN 28 1481 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1482 /* Link speed is 100, 1000, 10000, 40000 */ 1483 #define MC_CMD_FC_IN_SFP_SPEED_OFST 4 1484 /* Length of copper cable - zero when not relevant (e.g. if cable is fibre) */ 1485 #define MC_CMD_FC_IN_SFP_COPPER_LEN_OFST 8 1486 /* Not relevant for cards with QSFP modules. For older cards, true if module is 1487 * a dual speed SFP+ module. 1488 */ 1489 #define MC_CMD_FC_IN_SFP_DUAL_SPEED_OFST 12 1490 /* True if an SFP Module is present (other fields valid when true) */ 1491 #define MC_CMD_FC_IN_SFP_PRESENT_OFST 16 1492 /* The type of the SFP+ Module. For later cards with QSFP modules, this field 1493 * is unused and the type is communicated by other means. 1494 */ 1495 #define MC_CMD_FC_IN_SFP_TYPE_OFST 20 1496 /* Capabilities corresponding to 1 bits. */ 1497 #define MC_CMD_FC_IN_SFP_CAPS_OFST 24 1498 1499 /* MC_CMD_FC_IN_DDR_TEST msgrequest */ 1500 #define MC_CMD_FC_IN_DDR_TEST_LEN 8 1501 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1502 #define MC_CMD_FC_IN_DDR_TEST_HEADER_OFST 4 1503 #define MC_CMD_FC_IN_DDR_TEST_OP_LBN 0 1504 #define MC_CMD_FC_IN_DDR_TEST_OP_WIDTH 8 1505 /* enum: DRAM Test Start */ 1506 #define MC_CMD_FC_OP_DDR_TEST_START 0x1 1507 /* enum: DRAM Test Poll */ 1508 #define MC_CMD_FC_OP_DDR_TEST_POLL 0x2 1509 1510 /* MC_CMD_FC_IN_DDR_TEST_START msgrequest */ 1511 #define MC_CMD_FC_IN_DDR_TEST_START_LEN 12 1512 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1513 /* MC_CMD_FC_IN_DDR_TEST_HEADER_OFST 4 */ 1514 #define MC_CMD_FC_IN_DDR_TEST_START_MASK_OFST 8 1515 #define MC_CMD_FC_IN_DDR_TEST_START_T0_LBN 0 1516 #define MC_CMD_FC_IN_DDR_TEST_START_T0_WIDTH 1 1517 #define MC_CMD_FC_IN_DDR_TEST_START_T1_LBN 1 1518 #define MC_CMD_FC_IN_DDR_TEST_START_T1_WIDTH 1 1519 #define MC_CMD_FC_IN_DDR_TEST_START_B0_LBN 2 1520 #define MC_CMD_FC_IN_DDR_TEST_START_B0_WIDTH 1 1521 #define MC_CMD_FC_IN_DDR_TEST_START_B1_LBN 3 1522 #define MC_CMD_FC_IN_DDR_TEST_START_B1_WIDTH 1 1523 1524 /* MC_CMD_FC_IN_DDR_TEST_POLL msgrequest */ 1525 #define MC_CMD_FC_IN_DDR_TEST_POLL_LEN 12 1526 #define MC_CMD_FC_IN_DDR_TEST_CMD_OFST 0 1527 /* MC_CMD_FC_IN_DDR_TEST_HEADER_OFST 4 */ 1528 /* Clear previous test result and prepare for restarting DDR test */ 1529 #define MC_CMD_FC_IN_DDR_TEST_POLL_CLEAR_RESULT_FOR_DDR_TEST_OFST 8 1530 1531 /* MC_CMD_FC_IN_GET_ASSERT msgrequest */ 1532 #define MC_CMD_FC_IN_GET_ASSERT_LEN 4 1533 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1534 1535 /* MC_CMD_FC_IN_FPGA_BUILD msgrequest */ 1536 #define MC_CMD_FC_IN_FPGA_BUILD_LEN 8 1537 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1538 /* FPGA build info operation code */ 1539 #define MC_CMD_FC_IN_FPGA_BUILD_OP_OFST 4 1540 /* enum: Get the build registers */ 1541 #define MC_CMD_FC_IN_FPGA_BUILD_BUILD 0x1 1542 /* enum: Get the services registers */ 1543 #define MC_CMD_FC_IN_FPGA_BUILD_SERVICES 0x2 1544 /* enum: Get the BSP version */ 1545 #define MC_CMD_FC_IN_FPGA_BUILD_BSP_VERSION 0x3 1546 /* enum: Get build register for V2 (SFA974X) */ 1547 #define MC_CMD_FC_IN_FPGA_BUILD_BUILD_V2 0x4 1548 /* enum: GEt the services register for V2 (SFA974X) */ 1549 #define MC_CMD_FC_IN_FPGA_BUILD_SERVICES_V2 0x5 1550 1551 /* MC_CMD_FC_IN_READ_MAP msgrequest */ 1552 #define MC_CMD_FC_IN_READ_MAP_LEN 8 1553 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1554 #define MC_CMD_FC_IN_READ_MAP_HEADER_OFST 4 1555 #define MC_CMD_FC_IN_READ_MAP_OP_LBN 0 1556 #define MC_CMD_FC_IN_READ_MAP_OP_WIDTH 8 1557 /* enum: Get the number of map regions */ 1558 #define MC_CMD_FC_OP_READ_MAP_COUNT 0x1 1559 /* enum: Get the specified map */ 1560 #define MC_CMD_FC_OP_READ_MAP_INDEX 0x2 1561 1562 /* MC_CMD_FC_IN_READ_MAP_COUNT msgrequest */ 1563 #define MC_CMD_FC_IN_READ_MAP_COUNT_LEN 8 1564 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1565 /* MC_CMD_FC_IN_READ_MAP_HEADER_OFST 4 */ 1566 1567 /* MC_CMD_FC_IN_READ_MAP_INDEX msgrequest */ 1568 #define MC_CMD_FC_IN_READ_MAP_INDEX_LEN 12 1569 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1570 /* MC_CMD_FC_IN_READ_MAP_HEADER_OFST 4 */ 1571 #define MC_CMD_FC_IN_MAP_INDEX_OFST 8 1572 1573 /* MC_CMD_FC_IN_CAPABILITIES msgrequest */ 1574 #define MC_CMD_FC_IN_CAPABILITIES_LEN 4 1575 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1576 1577 /* MC_CMD_FC_IN_GLOBAL_FLAGS msgrequest */ 1578 #define MC_CMD_FC_IN_GLOBAL_FLAGS_LEN 8 1579 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1580 #define MC_CMD_FC_IN_GLOBAL_FLAGS_FLAGS_OFST 4 1581 #define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_CABLE_PLUGGED_IN_LBN 0 1582 #define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_CABLE_PLUGGED_IN_WIDTH 1 1583 #define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_LINK_MONITORING_LBN 1 1584 #define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_LINK_MONITORING_WIDTH 1 1585 #define MC_CMD_FC_IN_GLOBAL_FLAGS_DFE_ENABLE_LBN 2 1586 #define MC_CMD_FC_IN_GLOBAL_FLAGS_DFE_ENABLE_WIDTH 1 1587 #define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_EYE_ENABLE_LBN 3 1588 #define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_EYE_ENABLE_WIDTH 1 1589 #define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_TUNING_ENABLE_LBN 4 1590 #define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_TUNING_ENABLE_WIDTH 1 1591 #define MC_CMD_FC_IN_GLOBAL_FLAGS_OFFCAL_ENABLE_LBN 5 1592 #define MC_CMD_FC_IN_GLOBAL_FLAGS_OFFCAL_ENABLE_WIDTH 1 1593 1594 /* MC_CMD_FC_IN_IO_REL msgrequest */ 1595 #define MC_CMD_FC_IN_IO_REL_LEN 8 1596 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1597 #define MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 1598 #define MC_CMD_FC_IN_IO_REL_OP_LBN 0 1599 #define MC_CMD_FC_IN_IO_REL_OP_WIDTH 8 1600 /* enum: Get the base address that the FC applies to relative commands */ 1601 #define MC_CMD_FC_IN_IO_REL_GET_ADDR 0x1 1602 /* enum: Read data */ 1603 #define MC_CMD_FC_IN_IO_REL_READ32 0x2 1604 /* enum: Write data */ 1605 #define MC_CMD_FC_IN_IO_REL_WRITE32 0x3 1606 #define MC_CMD_FC_IN_IO_REL_COMP_TYPE_LBN 8 1607 #define MC_CMD_FC_IN_IO_REL_COMP_TYPE_WIDTH 8 1608 /* enum: Application address space */ 1609 #define MC_CMD_FC_COMP_TYPE_APP_ADDR_SPACE 0x1 1610 /* enum: Flash address space */ 1611 #define MC_CMD_FC_COMP_TYPE_FLASH 0x2 1612 1613 /* MC_CMD_FC_IN_IO_REL_GET_ADDR msgrequest */ 1614 #define MC_CMD_FC_IN_IO_REL_GET_ADDR_LEN 8 1615 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1616 /* MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 */ 1617 1618 /* MC_CMD_FC_IN_IO_REL_READ32 msgrequest */ 1619 #define MC_CMD_FC_IN_IO_REL_READ32_LEN 20 1620 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1621 /* MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 */ 1622 #define MC_CMD_FC_IN_IO_REL_READ32_ADDR_HI_OFST 8 1623 #define MC_CMD_FC_IN_IO_REL_READ32_ADDR_LO_OFST 12 1624 #define MC_CMD_FC_IN_IO_REL_READ32_NUMWORDS_OFST 16 1625 1626 /* MC_CMD_FC_IN_IO_REL_WRITE32 msgrequest */ 1627 #define MC_CMD_FC_IN_IO_REL_WRITE32_LENMIN 20 1628 #define MC_CMD_FC_IN_IO_REL_WRITE32_LENMAX 252 1629 #define MC_CMD_FC_IN_IO_REL_WRITE32_LEN(num) (16+4*(num)) 1630 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1631 /* MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 */ 1632 #define MC_CMD_FC_IN_IO_REL_WRITE32_ADDR_HI_OFST 8 1633 #define MC_CMD_FC_IN_IO_REL_WRITE32_ADDR_LO_OFST 12 1634 #define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_OFST 16 1635 #define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_LEN 4 1636 #define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_MINNUM 1 1637 #define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_MAXNUM 59 1638 1639 /* MC_CMD_FC_IN_UHLINK msgrequest */ 1640 #define MC_CMD_FC_IN_UHLINK_LEN 8 1641 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1642 #define MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 1643 #define MC_CMD_FC_IN_UHLINK_OP_LBN 0 1644 #define MC_CMD_FC_IN_UHLINK_OP_WIDTH 8 1645 /* enum: Get PHY configuration info */ 1646 #define MC_CMD_FC_OP_UHLINK_PHY 0x1 1647 /* enum: Get MAC configuration info */ 1648 #define MC_CMD_FC_OP_UHLINK_MAC 0x2 1649 /* enum: Get Rx eye table */ 1650 #define MC_CMD_FC_OP_UHLINK_RX_EYE 0x3 1651 /* enum: Get Rx eye plot */ 1652 #define MC_CMD_FC_OP_UHLINK_DUMP_RX_EYE_PLOT 0x4 1653 /* enum: Get Rx eye plot */ 1654 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT 0x5 1655 /* enum: Retune Rx settings */ 1656 #define MC_CMD_FC_OP_UHLINK_RX_TUNE 0x6 1657 /* enum: Set loopback mode on fpga port */ 1658 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET 0x7 1659 /* enum: Get loopback mode config state on fpga port */ 1660 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_GET 0x8 1661 #define MC_CMD_FC_IN_UHLINK_PORT_TYPE_LBN 8 1662 #define MC_CMD_FC_IN_UHLINK_PORT_TYPE_WIDTH 8 1663 #define MC_CMD_FC_IN_UHLINK_PORT_IDX_LBN 16 1664 #define MC_CMD_FC_IN_UHLINK_PORT_IDX_WIDTH 8 1665 #define MC_CMD_FC_IN_UHLINK_CMD_FORMAT_LBN 24 1666 #define MC_CMD_FC_IN_UHLINK_CMD_FORMAT_WIDTH 8 1667 /* enum: Default FC command format; the fields PORT_TYPE and PORT_IDX are 1668 * irrelevant. Port number is derived from pci_fn; passed in FC header. 1669 */ 1670 #define MC_CMD_FC_OP_UHLINK_CMD_FORMAT_DEFAULT 0x0 1671 /* enum: Override default port number. Port number determined by fields 1672 * PORT_TYPE and PORT_IDX. 1673 */ 1674 #define MC_CMD_FC_OP_UHLINK_CMD_FORMAT_PORT_OVERRIDE 0x1 1675 1676 /* MC_CMD_FC_OP_UHLINK_PHY msgrequest */ 1677 #define MC_CMD_FC_OP_UHLINK_PHY_LEN 8 1678 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1679 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 1680 1681 /* MC_CMD_FC_OP_UHLINK_MAC msgrequest */ 1682 #define MC_CMD_FC_OP_UHLINK_MAC_LEN 8 1683 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1684 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 1685 1686 /* MC_CMD_FC_OP_UHLINK_RX_EYE msgrequest */ 1687 #define MC_CMD_FC_OP_UHLINK_RX_EYE_LEN 12 1688 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1689 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 1690 #define MC_CMD_FC_OP_UHLINK_RX_EYE_INDEX_OFST 8 1691 #define MC_CMD_FC_UHLINK_RX_EYE_PER_BLOCK 0x30 /* enum */ 1692 1693 /* MC_CMD_FC_OP_UHLINK_DUMP_RX_EYE_PLOT msgrequest */ 1694 #define MC_CMD_FC_OP_UHLINK_DUMP_RX_EYE_PLOT_LEN 8 1695 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1696 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 1697 1698 /* MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT msgrequest */ 1699 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_LEN 20 1700 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1701 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 1702 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_DC_GAIN_OFST 8 1703 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_EQ_CONTROL_OFST 12 1704 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_INDEX_OFST 16 1705 #define MC_CMD_FC_UHLINK_RX_EYE_PLOT_ROWS_PER_BLOCK 0x1e /* enum */ 1706 1707 /* MC_CMD_FC_OP_UHLINK_RX_TUNE msgrequest */ 1708 #define MC_CMD_FC_OP_UHLINK_RX_TUNE_LEN 8 1709 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1710 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 1711 1712 /* MC_CMD_FC_OP_UHLINK_LOOPBACK_SET msgrequest */ 1713 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET_LEN 16 1714 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1715 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 1716 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET_TYPE_OFST 8 1717 #define MC_CMD_FC_UHLINK_LOOPBACK_TYPE_PCS_SERIAL 0x0 /* enum */ 1718 #define MC_CMD_FC_UHLINK_LOOPBACK_TYPE_PMA_PRE_CDR 0x1 /* enum */ 1719 #define MC_CMD_FC_UHLINK_LOOPBACK_TYPE_PMA_POST_CDR 0x2 /* enum */ 1720 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET_STATE_OFST 12 1721 #define MC_CMD_FC_UHLINK_LOOPBACK_STATE_OFF 0x0 /* enum */ 1722 #define MC_CMD_FC_UHLINK_LOOPBACK_STATE_ON 0x1 /* enum */ 1723 1724 /* MC_CMD_FC_OP_UHLINK_LOOPBACK_GET msgrequest */ 1725 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_GET_LEN 12 1726 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1727 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 1728 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_GET_TYPE_OFST 8 1729 1730 /* MC_CMD_FC_IN_SET_LINK msgrequest */ 1731 #define MC_CMD_FC_IN_SET_LINK_LEN 16 1732 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1733 /* See MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */ 1734 #define MC_CMD_FC_IN_SET_LINK_MODE_OFST 4 1735 #define MC_CMD_FC_IN_SET_LINK_SPEED_OFST 8 1736 #define MC_CMD_FC_IN_SET_LINK_FLAGS_OFST 12 1737 #define MC_CMD_FC_IN_SET_LINK_LOWPOWER_LBN 0 1738 #define MC_CMD_FC_IN_SET_LINK_LOWPOWER_WIDTH 1 1739 #define MC_CMD_FC_IN_SET_LINK_POWEROFF_LBN 1 1740 #define MC_CMD_FC_IN_SET_LINK_POWEROFF_WIDTH 1 1741 #define MC_CMD_FC_IN_SET_LINK_TXDIS_LBN 2 1742 #define MC_CMD_FC_IN_SET_LINK_TXDIS_WIDTH 1 1743 1744 /* MC_CMD_FC_IN_LICENSE msgrequest */ 1745 #define MC_CMD_FC_IN_LICENSE_LEN 8 1746 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1747 #define MC_CMD_FC_IN_LICENSE_OP_OFST 4 1748 #define MC_CMD_FC_IN_LICENSE_UPDATE_LICENSE 0x0 /* enum */ 1749 #define MC_CMD_FC_IN_LICENSE_GET_KEY_STATS 0x1 /* enum */ 1750 1751 /* MC_CMD_FC_IN_STARTUP msgrequest */ 1752 #define MC_CMD_FC_IN_STARTUP_LEN 40 1753 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1754 #define MC_CMD_FC_IN_STARTUP_BASE_OFST 4 1755 #define MC_CMD_FC_IN_STARTUP_LENGTH_OFST 8 1756 /* Length of identifier */ 1757 #define MC_CMD_FC_IN_STARTUP_IDLENGTH_OFST 12 1758 /* Identifier for AOE FPGA */ 1759 #define MC_CMD_FC_IN_STARTUP_ID_OFST 16 1760 #define MC_CMD_FC_IN_STARTUP_ID_LEN 1 1761 #define MC_CMD_FC_IN_STARTUP_ID_NUM 24 1762 1763 /* MC_CMD_FC_IN_DMA msgrequest */ 1764 #define MC_CMD_FC_IN_DMA_LEN 8 1765 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1766 #define MC_CMD_FC_IN_DMA_OP_OFST 4 1767 #define MC_CMD_FC_IN_DMA_STOP 0x0 /* enum */ 1768 #define MC_CMD_FC_IN_DMA_READ 0x1 /* enum */ 1769 1770 /* MC_CMD_FC_IN_DMA_STOP msgrequest */ 1771 #define MC_CMD_FC_IN_DMA_STOP_LEN 12 1772 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1773 /* MC_CMD_FC_IN_DMA_OP_OFST 4 */ 1774 /* FC supplied handle */ 1775 #define MC_CMD_FC_IN_DMA_STOP_FC_HANDLE_OFST 8 1776 1777 /* MC_CMD_FC_IN_DMA_READ msgrequest */ 1778 #define MC_CMD_FC_IN_DMA_READ_LEN 16 1779 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1780 /* MC_CMD_FC_IN_DMA_OP_OFST 4 */ 1781 #define MC_CMD_FC_IN_DMA_READ_OFFSET_OFST 8 1782 #define MC_CMD_FC_IN_DMA_READ_LENGTH_OFST 12 1783 1784 /* MC_CMD_FC_IN_TIMED_READ msgrequest */ 1785 #define MC_CMD_FC_IN_TIMED_READ_LEN 8 1786 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1787 #define MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 1788 #define MC_CMD_FC_IN_TIMED_READ_SET 0x0 /* enum */ 1789 #define MC_CMD_FC_IN_TIMED_READ_GET 0x1 /* enum */ 1790 #define MC_CMD_FC_IN_TIMED_READ_CLEAR 0x2 /* enum */ 1791 1792 /* MC_CMD_FC_IN_TIMED_READ_SET msgrequest */ 1793 #define MC_CMD_FC_IN_TIMED_READ_SET_LEN 52 1794 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1795 /* MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 */ 1796 /* Host supplied handle (unique) */ 1797 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_HANDLE_OFST 8 1798 /* Address into which to transfer data in host */ 1799 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_OFST 12 1800 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_LEN 8 1801 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_LO_OFST 12 1802 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_HI_OFST 16 1803 /* AOE address from which to transfer data */ 1804 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_OFST 20 1805 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_LEN 8 1806 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_LO_OFST 20 1807 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_HI_OFST 24 1808 /* Length of AOE transfer (total) */ 1809 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_LENGTH_OFST 28 1810 /* Length of host transfer (total) */ 1811 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_LENGTH_OFST 32 1812 /* Offset back from aoe_address to apply operation to */ 1813 #define MC_CMD_FC_IN_TIMED_READ_SET_OFFSET_OFST 36 1814 /* Data to apply at offset */ 1815 #define MC_CMD_FC_IN_TIMED_READ_SET_DATA_OFST 40 1816 #define MC_CMD_FC_IN_TIMED_READ_SET_FLAGS_OFST 44 1817 #define MC_CMD_FC_IN_TIMED_READ_SET_INDIRECT_LBN 0 1818 #define MC_CMD_FC_IN_TIMED_READ_SET_INDIRECT_WIDTH 1 1819 #define MC_CMD_FC_IN_TIMED_READ_SET_DOUBLE_LBN 1 1820 #define MC_CMD_FC_IN_TIMED_READ_SET_DOUBLE_WIDTH 1 1821 #define MC_CMD_FC_IN_TIMED_READ_SET_EVENT_LBN 2 1822 #define MC_CMD_FC_IN_TIMED_READ_SET_EVENT_WIDTH 1 1823 #define MC_CMD_FC_IN_TIMED_READ_SET_PREREAD_LBN 3 1824 #define MC_CMD_FC_IN_TIMED_READ_SET_PREREAD_WIDTH 2 1825 #define MC_CMD_FC_IN_TIMED_READ_SET_NONE 0x0 /* enum */ 1826 #define MC_CMD_FC_IN_TIMED_READ_SET_READ 0x1 /* enum */ 1827 #define MC_CMD_FC_IN_TIMED_READ_SET_WRITE 0x2 /* enum */ 1828 #define MC_CMD_FC_IN_TIMED_READ_SET_READWRITE 0x3 /* enum */ 1829 /* Period at which reads are performed (100ms units) */ 1830 #define MC_CMD_FC_IN_TIMED_READ_SET_PERIOD_OFST 48 1831 1832 /* MC_CMD_FC_IN_TIMED_READ_GET msgrequest */ 1833 #define MC_CMD_FC_IN_TIMED_READ_GET_LEN 12 1834 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1835 /* MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 */ 1836 /* FC supplied handle */ 1837 #define MC_CMD_FC_IN_TIMED_READ_GET_FC_HANDLE_OFST 8 1838 1839 /* MC_CMD_FC_IN_TIMED_READ_CLEAR msgrequest */ 1840 #define MC_CMD_FC_IN_TIMED_READ_CLEAR_LEN 12 1841 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1842 /* MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 */ 1843 /* FC supplied handle */ 1844 #define MC_CMD_FC_IN_TIMED_READ_CLEAR_FC_HANDLE_OFST 8 1845 1846 /* MC_CMD_FC_IN_LOG msgrequest */ 1847 #define MC_CMD_FC_IN_LOG_LEN 8 1848 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1849 #define MC_CMD_FC_IN_LOG_OP_OFST 4 1850 #define MC_CMD_FC_IN_LOG_ADDR_RANGE 0x0 /* enum */ 1851 #define MC_CMD_FC_IN_LOG_JTAG_UART 0x1 /* enum */ 1852 1853 /* MC_CMD_FC_IN_LOG_ADDR_RANGE msgrequest */ 1854 #define MC_CMD_FC_IN_LOG_ADDR_RANGE_LEN 20 1855 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1856 /* MC_CMD_FC_IN_LOG_OP_OFST 4 */ 1857 /* Partition offset into flash */ 1858 #define MC_CMD_FC_IN_LOG_ADDR_RANGE_OFFSET_OFST 8 1859 /* Partition length */ 1860 #define MC_CMD_FC_IN_LOG_ADDR_RANGE_LENGTH_OFST 12 1861 /* Partition erase size */ 1862 #define MC_CMD_FC_IN_LOG_ADDR_RANGE_ERASE_SIZE_OFST 16 1863 1864 /* MC_CMD_FC_IN_LOG_JTAG_UART msgrequest */ 1865 #define MC_CMD_FC_IN_LOG_JTAG_UART_LEN 12 1866 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1867 /* MC_CMD_FC_IN_LOG_OP_OFST 4 */ 1868 /* Enable/disable printing to JTAG UART */ 1869 #define MC_CMD_FC_IN_LOG_JTAG_UART_ENABLE_OFST 8 1870 1871 /* MC_CMD_FC_IN_CLOCK msgrequest */ 1872 #define MC_CMD_FC_IN_CLOCK_LEN 12 1873 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1874 #define MC_CMD_FC_IN_CLOCK_OP_OFST 4 1875 #define MC_CMD_FC_IN_CLOCK_GET_TIME 0x0 /* enum */ 1876 #define MC_CMD_FC_IN_CLOCK_SET_TIME 0x1 /* enum */ 1877 /* Perform a clock operation */ 1878 #define MC_CMD_FC_IN_CLOCK_ID_OFST 8 1879 #define MC_CMD_FC_IN_CLOCK_STATS 0x0 /* enum */ 1880 #define MC_CMD_FC_IN_CLOCK_MAC 0x1 /* enum */ 1881 1882 /* MC_CMD_FC_IN_CLOCK_GET_TIME msgrequest */ 1883 #define MC_CMD_FC_IN_CLOCK_GET_TIME_LEN 12 1884 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1885 /* MC_CMD_FC_IN_CLOCK_OP_OFST 4 */ 1886 /* Retrieve the clock value of the specified clock */ 1887 /* MC_CMD_FC_IN_CLOCK_ID_OFST 8 */ 1888 1889 /* MC_CMD_FC_IN_CLOCK_SET_TIME msgrequest */ 1890 #define MC_CMD_FC_IN_CLOCK_SET_TIME_LEN 24 1891 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1892 /* MC_CMD_FC_IN_CLOCK_OP_OFST 4 */ 1893 /* MC_CMD_FC_IN_CLOCK_ID_OFST 8 */ 1894 #define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_OFST 12 1895 #define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LEN 8 1896 #define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LO_OFST 12 1897 #define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_HI_OFST 16 1898 /* Set the clock value of the specified clock */ 1899 #define MC_CMD_FC_IN_CLOCK_SET_TIME_NANOSECONDS_OFST 20 1900 1901 /* MC_CMD_FC_IN_DDR msgrequest */ 1902 #define MC_CMD_FC_IN_DDR_LEN 12 1903 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1904 #define MC_CMD_FC_IN_DDR_OP_OFST 4 1905 #define MC_CMD_FC_IN_DDR_SET_SPD 0x0 /* enum */ 1906 #define MC_CMD_FC_IN_DDR_GET_STATUS 0x1 /* enum */ 1907 #define MC_CMD_FC_IN_DDR_SET_INFO 0x2 /* enum */ 1908 #define MC_CMD_FC_IN_DDR_BANK_OFST 8 1909 #define MC_CMD_FC_IN_DDR_BANK_B0 0x0 /* enum */ 1910 #define MC_CMD_FC_IN_DDR_BANK_B1 0x1 /* enum */ 1911 #define MC_CMD_FC_IN_DDR_BANK_T0 0x2 /* enum */ 1912 #define MC_CMD_FC_IN_DDR_BANK_T1 0x3 /* enum */ 1913 #define MC_CMD_FC_IN_DDR_NUM_BANKS 0x4 /* enum */ 1914 1915 /* MC_CMD_FC_IN_DDR_SET_SPD msgrequest */ 1916 #define MC_CMD_FC_IN_DDR_SET_SPD_LEN 148 1917 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1918 /* MC_CMD_FC_IN_DDR_OP_OFST 4 */ 1919 /* Affected bank */ 1920 /* MC_CMD_FC_IN_DDR_BANK_OFST 8 */ 1921 /* Flags */ 1922 #define MC_CMD_FC_IN_DDR_FLAGS_OFST 12 1923 #define MC_CMD_FC_IN_DDR_SET_SPD_ACTIVE 0x1 /* enum */ 1924 /* 128-byte page of serial presence detect data read from module's EEPROM */ 1925 #define MC_CMD_FC_IN_DDR_SPD_OFST 16 1926 #define MC_CMD_FC_IN_DDR_SPD_LEN 1 1927 #define MC_CMD_FC_IN_DDR_SPD_NUM 128 1928 /* Page index of the spd data copied into MC_CMD_FC_IN_DDR_SPD */ 1929 #define MC_CMD_FC_IN_DDR_SPD_PAGE_ID_OFST 144 1930 1931 /* MC_CMD_FC_IN_DDR_SET_INFO msgrequest */ 1932 #define MC_CMD_FC_IN_DDR_SET_INFO_LEN 16 1933 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1934 /* MC_CMD_FC_IN_DDR_OP_OFST 4 */ 1935 /* Affected bank */ 1936 /* MC_CMD_FC_IN_DDR_BANK_OFST 8 */ 1937 /* Size of DDR */ 1938 #define MC_CMD_FC_IN_DDR_SIZE_OFST 12 1939 1940 /* MC_CMD_FC_IN_DDR_GET_STATUS msgrequest */ 1941 #define MC_CMD_FC_IN_DDR_GET_STATUS_LEN 12 1942 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1943 /* MC_CMD_FC_IN_DDR_OP_OFST 4 */ 1944 /* Affected bank */ 1945 /* MC_CMD_FC_IN_DDR_BANK_OFST 8 */ 1946 1947 /* MC_CMD_FC_IN_TIMESTAMP msgrequest */ 1948 #define MC_CMD_FC_IN_TIMESTAMP_LEN 8 1949 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1950 /* FC timestamp operation code */ 1951 #define MC_CMD_FC_IN_TIMESTAMP_OP_OFST 4 1952 /* enum: Read transmit timestamp(s) */ 1953 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT 0x0 1954 /* enum: Read snapshot timestamps */ 1955 #define MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT 0x1 1956 /* enum: Clear all transmit timestamps */ 1957 #define MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT 0x2 1958 1959 /* MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT msgrequest */ 1960 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_LEN 28 1961 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1962 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_OP_OFST 4 1963 /* Control filtering of the returned timestamp and sequence number specified 1964 * here 1965 */ 1966 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_FILTER_OFST 8 1967 /* enum: Return most recent timestamp. No filtering */ 1968 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_LATEST 0x0 1969 /* enum: Match timestamp against the PTP clock ID, port number and sequence 1970 * number specified 1971 */ 1972 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_MATCH 0x1 1973 /* Clock identity of PTP packet for which timestamp required */ 1974 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_OFST 12 1975 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_LEN 8 1976 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_LO_OFST 12 1977 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_HI_OFST 16 1978 /* Port number of PTP packet for which timestamp required */ 1979 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_PORT_NUM_OFST 20 1980 /* Sequence number of PTP packet for which timestamp required */ 1981 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_SEQ_NUM_OFST 24 1982 1983 /* MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT msgrequest */ 1984 #define MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT_LEN 8 1985 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1986 #define MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT_OP_OFST 4 1987 1988 /* MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT msgrequest */ 1989 #define MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT_LEN 8 1990 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1991 #define MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT_OP_OFST 4 1992 1993 /* MC_CMD_FC_IN_SPI msgrequest */ 1994 #define MC_CMD_FC_IN_SPI_LEN 8 1995 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1996 /* Basic commands for SPI Flash. */ 1997 #define MC_CMD_FC_IN_SPI_OP_OFST 4 1998 /* enum: SPI Flash read */ 1999 #define MC_CMD_FC_IN_SPI_READ 0x0 2000 /* enum: SPI Flash write */ 2001 #define MC_CMD_FC_IN_SPI_WRITE 0x1 2002 /* enum: SPI Flash erase */ 2003 #define MC_CMD_FC_IN_SPI_ERASE 0x2 2004 2005 /* MC_CMD_FC_IN_SPI_READ msgrequest */ 2006 #define MC_CMD_FC_IN_SPI_READ_LEN 16 2007 /* MC_CMD_FC_IN_CMD_OFST 0 */ 2008 #define MC_CMD_FC_IN_SPI_READ_OP_OFST 4 2009 #define MC_CMD_FC_IN_SPI_READ_ADDR_OFST 8 2010 #define MC_CMD_FC_IN_SPI_READ_NUMBYTES_OFST 12 2011 2012 /* MC_CMD_FC_IN_SPI_WRITE msgrequest */ 2013 #define MC_CMD_FC_IN_SPI_WRITE_LENMIN 16 2014 #define MC_CMD_FC_IN_SPI_WRITE_LENMAX 252 2015 #define MC_CMD_FC_IN_SPI_WRITE_LEN(num) (12+4*(num)) 2016 /* MC_CMD_FC_IN_CMD_OFST 0 */ 2017 #define MC_CMD_FC_IN_SPI_WRITE_OP_OFST 4 2018 #define MC_CMD_FC_IN_SPI_WRITE_ADDR_OFST 8 2019 #define MC_CMD_FC_IN_SPI_WRITE_BUFFER_OFST 12 2020 #define MC_CMD_FC_IN_SPI_WRITE_BUFFER_LEN 4 2021 #define MC_CMD_FC_IN_SPI_WRITE_BUFFER_MINNUM 1 2022 #define MC_CMD_FC_IN_SPI_WRITE_BUFFER_MAXNUM 60 2023 2024 /* MC_CMD_FC_IN_SPI_ERASE msgrequest */ 2025 #define MC_CMD_FC_IN_SPI_ERASE_LEN 16 2026 /* MC_CMD_FC_IN_CMD_OFST 0 */ 2027 #define MC_CMD_FC_IN_SPI_ERASE_OP_OFST 4 2028 #define MC_CMD_FC_IN_SPI_ERASE_ADDR_OFST 8 2029 #define MC_CMD_FC_IN_SPI_ERASE_NUMBYTES_OFST 12 2030 2031 /* MC_CMD_FC_IN_DIAG msgrequest */ 2032 #define MC_CMD_FC_IN_DIAG_LEN 8 2033 /* MC_CMD_FC_IN_CMD_OFST 0 */ 2034 /* Operation code indicating component type */ 2035 #define MC_CMD_FC_IN_DIAG_OP_OFST 4 2036 /* enum: Power noise generator. */ 2037 #define MC_CMD_FC_IN_DIAG_POWER_NOISE 0x0 2038 /* enum: DDR soak test component. */ 2039 #define MC_CMD_FC_IN_DIAG_DDR_SOAK 0x1 2040 /* enum: Diagnostics datapath control component. */ 2041 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL 0x2 2042 2043 /* MC_CMD_FC_IN_DIAG_POWER_NOISE msgrequest */ 2044 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_LEN 12 2045 /* MC_CMD_FC_IN_CMD_OFST 0 */ 2046 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_OP_OFST 4 2047 /* Sub-opcode describing the operation to be carried out */ 2048 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_SUB_OP_OFST 8 2049 /* enum: Read the configuration (the 32-bit values in each of the clock enable 2050 * count and toggle count registers) 2051 */ 2052 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG 0x0 2053 /* enum: Write a new configuration to the clock enable count and toggle count 2054 * registers 2055 */ 2056 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG 0x1 2057 2058 /* MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG msgrequest */ 2059 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_LEN 12 2060 /* MC_CMD_FC_IN_CMD_OFST 0 */ 2061 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_OP_OFST 4 2062 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_SUB_OP_OFST 8 2063 2064 /* MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG msgrequest */ 2065 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_LEN 20 2066 /* MC_CMD_FC_IN_CMD_OFST 0 */ 2067 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_OP_OFST 4 2068 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_SUB_OP_OFST 8 2069 /* The 32-bit value to be written to the toggle count register */ 2070 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_TOGGLE_COUNT_OFST 12 2071 /* The 32-bit value to be written to the clock enable count register */ 2072 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_CLKEN_COUNT_OFST 16 2073 2074 /* MC_CMD_FC_IN_DIAG_DDR_SOAK msgrequest */ 2075 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_LEN 12 2076 /* MC_CMD_FC_IN_CMD_OFST 0 */ 2077 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_OP_OFST 4 2078 /* Sub-opcode describing the operation to be carried out */ 2079 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_SUB_OP_OFST 8 2080 /* enum: Starts DDR soak test on selected banks */ 2081 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START 0x0 2082 /* enum: Read status of DDR soak test */ 2083 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT 0x1 2084 /* enum: Stop test */ 2085 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP 0x2 2086 /* enum: Set or clear bit that triggers fake errors. These cause subsequent 2087 * tests to fail until the bit is cleared. 2088 */ 2089 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR 0x3 2090 2091 /* MC_CMD_FC_IN_DIAG_DDR_SOAK_START msgrequest */ 2092 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_LEN 24 2093 /* MC_CMD_FC_IN_CMD_OFST 0 */ 2094 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_OP_OFST 4 2095 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_SUB_OP_OFST 8 2096 /* Mask of DDR banks to be tested */ 2097 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_BANK_MASK_OFST 12 2098 /* Pattern to use in the soak test */ 2099 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_TEST_PATTERN_OFST 16 2100 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_ZEROS 0x0 /* enum */ 2101 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_ONES 0x1 /* enum */ 2102 /* Either multiple automatic tests until a STOP command is issued, or one 2103 * single test 2104 */ 2105 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_TEST_TYPE_OFST 20 2106 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_ONGOING_TEST 0x0 /* enum */ 2107 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_SINGLE_TEST 0x1 /* enum */ 2108 2109 /* MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT msgrequest */ 2110 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_LEN 16 2111 /* MC_CMD_FC_IN_CMD_OFST 0 */ 2112 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_OP_OFST 4 2113 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_SUB_OP_OFST 8 2114 /* DDR bank to read status from */ 2115 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_BANK_ID_OFST 12 2116 #define MC_CMD_FC_DDR_BANK0 0x0 /* enum */ 2117 #define MC_CMD_FC_DDR_BANK1 0x1 /* enum */ 2118 #define MC_CMD_FC_DDR_BANK2 0x2 /* enum */ 2119 #define MC_CMD_FC_DDR_BANK3 0x3 /* enum */ 2120 #define MC_CMD_FC_DDR_AOEMEM_MAX_BANKS 0x4 /* enum */ 2121 2122 /* MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP msgrequest */ 2123 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_LEN 16 2124 /* MC_CMD_FC_IN_CMD_OFST 0 */ 2125 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_OP_OFST 4 2126 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_SUB_OP_OFST 8 2127 /* Mask of DDR banks to be tested */ 2128 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_BANK_MASK_OFST 12 2129 2130 /* MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR msgrequest */ 2131 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_LEN 20 2132 /* MC_CMD_FC_IN_CMD_OFST 0 */ 2133 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_OP_OFST 4 2134 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_SUB_OP_OFST 8 2135 /* Mask of DDR banks to set/clear error flag on */ 2136 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_BANK_MASK_OFST 12 2137 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_FLAG_ACTION_OFST 16 2138 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_CLEAR 0x0 /* enum */ 2139 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_SET 0x1 /* enum */ 2140 2141 /* MC_CMD_FC_IN_DIAG_DATAPATH_CTRL msgrequest */ 2142 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_LEN 12 2143 /* MC_CMD_FC_IN_CMD_OFST 0 */ 2144 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_OP_OFST 4 2145 /* Sub-opcode describing the operation to be carried out */ 2146 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SUB_OP_OFST 8 2147 /* enum: Set a known datapath configuration */ 2148 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE 0x0 2149 /* enum: Apply raw config to datapath control registers */ 2150 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG 0x1 2151 2152 /* MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE msgrequest */ 2153 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_LEN 16 2154 /* MC_CMD_FC_IN_CMD_OFST 0 */ 2155 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_OP_OFST 4 2156 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_SUB_OP_OFST 8 2157 /* Datapath configuration identifier */ 2158 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_MODE_OFST 12 2159 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_PASSTHROUGH 0x0 /* enum */ 2160 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_SNAKE 0x1 /* enum */ 2161 2162 /* MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG msgrequest */ 2163 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_LEN 24 2164 /* MC_CMD_FC_IN_CMD_OFST 0 */ 2165 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_OP_OFST 4 2166 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_SUB_OP_OFST 8 2167 /* Value to write into control register 1 */ 2168 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL1_OFST 12 2169 /* Value to write into control register 2 */ 2170 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL2_OFST 16 2171 /* Value to write into control register 3 */ 2172 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL3_OFST 20 2173 2174 /* MC_CMD_FC_OUT msgresponse */ 2175 #define MC_CMD_FC_OUT_LEN 0 2176 2177 /* MC_CMD_FC_OUT_NULL msgresponse */ 2178 #define MC_CMD_FC_OUT_NULL_LEN 0 2179 2180 /* MC_CMD_FC_OUT_READ32 msgresponse */ 2181 #define MC_CMD_FC_OUT_READ32_LENMIN 4 2182 #define MC_CMD_FC_OUT_READ32_LENMAX 252 2183 #define MC_CMD_FC_OUT_READ32_LEN(num) (0+4*(num)) 2184 #define MC_CMD_FC_OUT_READ32_BUFFER_OFST 0 2185 #define MC_CMD_FC_OUT_READ32_BUFFER_LEN 4 2186 #define MC_CMD_FC_OUT_READ32_BUFFER_MINNUM 1 2187 #define MC_CMD_FC_OUT_READ32_BUFFER_MAXNUM 63 2188 2189 /* MC_CMD_FC_OUT_WRITE32 msgresponse */ 2190 #define MC_CMD_FC_OUT_WRITE32_LEN 0 2191 2192 /* MC_CMD_FC_OUT_TRC_READ msgresponse */ 2193 #define MC_CMD_FC_OUT_TRC_READ_LEN 16 2194 #define MC_CMD_FC_OUT_TRC_READ_DATA_OFST 0 2195 #define MC_CMD_FC_OUT_TRC_READ_DATA_LEN 4 2196 #define MC_CMD_FC_OUT_TRC_READ_DATA_NUM 4 2197 2198 /* MC_CMD_FC_OUT_TRC_WRITE msgresponse */ 2199 #define MC_CMD_FC_OUT_TRC_WRITE_LEN 0 2200 2201 /* MC_CMD_FC_OUT_GET_VERSION msgresponse */ 2202 #define MC_CMD_FC_OUT_GET_VERSION_LEN 12 2203 #define MC_CMD_FC_OUT_GET_VERSION_FIRMWARE_OFST 0 2204 #define MC_CMD_FC_OUT_GET_VERSION_VERSION_OFST 4 2205 #define MC_CMD_FC_OUT_GET_VERSION_VERSION_LEN 8 2206 #define MC_CMD_FC_OUT_GET_VERSION_VERSION_LO_OFST 4 2207 #define MC_CMD_FC_OUT_GET_VERSION_VERSION_HI_OFST 8 2208 2209 /* MC_CMD_FC_OUT_TRC_RX_READ msgresponse */ 2210 #define MC_CMD_FC_OUT_TRC_RX_READ_LEN 8 2211 #define MC_CMD_FC_OUT_TRC_RX_READ_DATA_OFST 0 2212 #define MC_CMD_FC_OUT_TRC_RX_READ_DATA_LEN 4 2213 #define MC_CMD_FC_OUT_TRC_RX_READ_DATA_NUM 2 2214 2215 /* MC_CMD_FC_OUT_TRC_RX_WRITE msgresponse */ 2216 #define MC_CMD_FC_OUT_TRC_RX_WRITE_LEN 0 2217 2218 /* MC_CMD_FC_OUT_MAC_RECONFIGURE msgresponse */ 2219 #define MC_CMD_FC_OUT_MAC_RECONFIGURE_LEN 0 2220 2221 /* MC_CMD_FC_OUT_MAC_SET_LINK msgresponse */ 2222 #define MC_CMD_FC_OUT_MAC_SET_LINK_LEN 0 2223 2224 /* MC_CMD_FC_OUT_MAC_READ_STATUS msgresponse */ 2225 #define MC_CMD_FC_OUT_MAC_READ_STATUS_LEN 4 2226 #define MC_CMD_FC_OUT_MAC_READ_STATUS_STATUS_OFST 0 2227 2228 /* MC_CMD_FC_OUT_MAC_GET_RX_STATS msgresponse */ 2229 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_LEN ((((0-1+(64*MC_CMD_FC_MAC_RX_NSTATS))+1))>>3) 2230 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_OFST 0 2231 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_LEN 8 2232 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_LO_OFST 0 2233 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_HI_OFST 4 2234 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_NUM MC_CMD_FC_MAC_RX_NSTATS 2235 #define MC_CMD_FC_MAC_RX_STATS_OCTETS 0x0 /* enum */ 2236 #define MC_CMD_FC_MAC_RX_OCTETS_OK 0x1 /* enum */ 2237 #define MC_CMD_FC_MAC_RX_ALIGNMENT_ERRORS 0x2 /* enum */ 2238 #define MC_CMD_FC_MAC_RX_PAUSE_MAC_CTRL_FRAMES 0x3 /* enum */ 2239 #define MC_CMD_FC_MAC_RX_FRAMES_OK 0x4 /* enum */ 2240 #define MC_CMD_FC_MAC_RX_CRC_ERRORS 0x5 /* enum */ 2241 #define MC_CMD_FC_MAC_RX_VLAN_OK 0x6 /* enum */ 2242 #define MC_CMD_FC_MAC_RX_ERRORS 0x7 /* enum */ 2243 #define MC_CMD_FC_MAC_RX_UCAST_PKTS 0x8 /* enum */ 2244 #define MC_CMD_FC_MAC_RX_MULTICAST_PKTS 0x9 /* enum */ 2245 #define MC_CMD_FC_MAC_RX_BROADCAST_PKTS 0xa /* enum */ 2246 #define MC_CMD_FC_MAC_RX_STATS_DROP_EVENTS 0xb /* enum */ 2247 #define MC_CMD_FC_MAC_RX_STATS_PKTS 0xc /* enum */ 2248 #define MC_CMD_FC_MAC_RX_STATS_UNDERSIZE_PKTS 0xd /* enum */ 2249 #define MC_CMD_FC_MAC_RX_STATS_PKTS_64 0xe /* enum */ 2250 #define MC_CMD_FC_MAC_RX_STATS_PKTS_65_127 0xf /* enum */ 2251 #define MC_CMD_FC_MAC_RX_STATS_PKTS_128_255 0x10 /* enum */ 2252 #define MC_CMD_FC_MAC_RX_STATS_PKTS_256_511 0x11 /* enum */ 2253 #define MC_CMD_FC_MAC_RX_STATS_PKTS_512_1023 0x12 /* enum */ 2254 #define MC_CMD_FC_MAC_RX_STATS_PKTS_1024_1518 0x13 /* enum */ 2255 #define MC_CMD_FC_MAC_RX_STATS_PKTS_1519_MAX 0x14 /* enum */ 2256 #define MC_CMD_FC_MAC_RX_STATS_OVERSIZE_PKTS 0x15 /* enum */ 2257 #define MC_CMD_FC_MAC_RX_STATS_JABBERS 0x16 /* enum */ 2258 #define MC_CMD_FC_MAC_RX_STATS_FRAGMENTS 0x17 /* enum */ 2259 #define MC_CMD_FC_MAC_RX_MAC_CONTROL_FRAMES 0x18 /* enum */ 2260 /* enum: (Last entry) */ 2261 #define MC_CMD_FC_MAC_RX_NSTATS 0x19 2262 2263 /* MC_CMD_FC_OUT_MAC_GET_TX_STATS msgresponse */ 2264 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_LEN ((((0-1+(64*MC_CMD_FC_MAC_TX_NSTATS))+1))>>3) 2265 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_OFST 0 2266 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_LEN 8 2267 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_LO_OFST 0 2268 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_HI_OFST 4 2269 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_NUM MC_CMD_FC_MAC_TX_NSTATS 2270 #define MC_CMD_FC_MAC_TX_STATS_OCTETS 0x0 /* enum */ 2271 #define MC_CMD_FC_MAC_TX_OCTETS_OK 0x1 /* enum */ 2272 #define MC_CMD_FC_MAC_TX_ALIGNMENT_ERRORS 0x2 /* enum */ 2273 #define MC_CMD_FC_MAC_TX_PAUSE_MAC_CTRL_FRAMES 0x3 /* enum */ 2274 #define MC_CMD_FC_MAC_TX_FRAMES_OK 0x4 /* enum */ 2275 #define MC_CMD_FC_MAC_TX_CRC_ERRORS 0x5 /* enum */ 2276 #define MC_CMD_FC_MAC_TX_VLAN_OK 0x6 /* enum */ 2277 #define MC_CMD_FC_MAC_TX_ERRORS 0x7 /* enum */ 2278 #define MC_CMD_FC_MAC_TX_UCAST_PKTS 0x8 /* enum */ 2279 #define MC_CMD_FC_MAC_TX_MULTICAST_PKTS 0x9 /* enum */ 2280 #define MC_CMD_FC_MAC_TX_BROADCAST_PKTS 0xa /* enum */ 2281 #define MC_CMD_FC_MAC_TX_STATS_DROP_EVENTS 0xb /* enum */ 2282 #define MC_CMD_FC_MAC_TX_STATS_PKTS 0xc /* enum */ 2283 #define MC_CMD_FC_MAC_TX_STATS_UNDERSIZE_PKTS 0xd /* enum */ 2284 #define MC_CMD_FC_MAC_TX_STATS_PKTS_64 0xe /* enum */ 2285 #define MC_CMD_FC_MAC_TX_STATS_PKTS_65_127 0xf /* enum */ 2286 #define MC_CMD_FC_MAC_TX_STATS_PKTS_128_255 0x10 /* enum */ 2287 #define MC_CMD_FC_MAC_TX_STATS_PKTS_256_511 0x11 /* enum */ 2288 #define MC_CMD_FC_MAC_TX_STATS_PKTS_512_1023 0x12 /* enum */ 2289 #define MC_CMD_FC_MAC_TX_STATS_PKTS_1024_1518 0x13 /* enum */ 2290 #define MC_CMD_FC_MAC_TX_STATS_PKTS_1519_TX_MTU 0x14 /* enum */ 2291 #define MC_CMD_FC_MAC_TX_MAC_CONTROL_FRAMES 0x15 /* enum */ 2292 /* enum: (Last entry) */ 2293 #define MC_CMD_FC_MAC_TX_NSTATS 0x16 2294 2295 /* MC_CMD_FC_OUT_MAC_GET_STATS msgresponse */ 2296 #define MC_CMD_FC_OUT_MAC_GET_STATS_LEN ((((0-1+(64*MC_CMD_FC_MAC_NSTATS_PER_BLOCK))+1))>>3) 2297 /* MAC Statistics */ 2298 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_OFST 0 2299 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_LEN 8 2300 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_LO_OFST 0 2301 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_HI_OFST 4 2302 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_NUM MC_CMD_FC_MAC_NSTATS_PER_BLOCK 2303 2304 /* MC_CMD_FC_OUT_MAC msgresponse */ 2305 #define MC_CMD_FC_OUT_MAC_LEN 0 2306 2307 /* MC_CMD_FC_OUT_SFP msgresponse */ 2308 #define MC_CMD_FC_OUT_SFP_LEN 0 2309 2310 /* MC_CMD_FC_OUT_DDR_TEST_START msgresponse */ 2311 #define MC_CMD_FC_OUT_DDR_TEST_START_LEN 0 2312 2313 /* MC_CMD_FC_OUT_DDR_TEST_POLL msgresponse */ 2314 #define MC_CMD_FC_OUT_DDR_TEST_POLL_LEN 8 2315 #define MC_CMD_FC_OUT_DDR_TEST_POLL_STATUS_OFST 0 2316 #define MC_CMD_FC_OUT_DDR_TEST_POLL_CODE_LBN 0 2317 #define MC_CMD_FC_OUT_DDR_TEST_POLL_CODE_WIDTH 8 2318 /* enum: Test not yet initiated */ 2319 #define MC_CMD_FC_OP_DDR_TEST_NONE 0x0 2320 /* enum: Test is in progress */ 2321 #define MC_CMD_FC_OP_DDR_TEST_INPROGRESS 0x1 2322 /* enum: Timed completed */ 2323 #define MC_CMD_FC_OP_DDR_TEST_SUCCESS 0x2 2324 /* enum: Test did not complete in specified time */ 2325 #define MC_CMD_FC_OP_DDR_TEST_TIMER_EXPIRED 0x3 2326 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T0_LBN 11 2327 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T0_WIDTH 1 2328 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T1_LBN 10 2329 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T1_WIDTH 1 2330 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B0_LBN 9 2331 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B0_WIDTH 1 2332 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B1_LBN 8 2333 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B1_WIDTH 1 2334 /* Test result from FPGA */ 2335 #define MC_CMD_FC_OUT_DDR_TEST_POLL_RESULT_OFST 4 2336 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T0_LBN 31 2337 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T0_WIDTH 1 2338 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T1_LBN 30 2339 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T1_WIDTH 1 2340 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B0_LBN 29 2341 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B0_WIDTH 1 2342 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B1_LBN 28 2343 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B1_WIDTH 1 2344 #define MC_CMD_FC_OUT_DDR_TEST_POLL_T0_LBN 15 2345 #define MC_CMD_FC_OUT_DDR_TEST_POLL_T0_WIDTH 5 2346 #define MC_CMD_FC_OUT_DDR_TEST_POLL_T1_LBN 10 2347 #define MC_CMD_FC_OUT_DDR_TEST_POLL_T1_WIDTH 5 2348 #define MC_CMD_FC_OUT_DDR_TEST_POLL_B0_LBN 5 2349 #define MC_CMD_FC_OUT_DDR_TEST_POLL_B0_WIDTH 5 2350 #define MC_CMD_FC_OUT_DDR_TEST_POLL_B1_LBN 0 2351 #define MC_CMD_FC_OUT_DDR_TEST_POLL_B1_WIDTH 5 2352 #define MC_CMD_FC_OUT_DDR_TEST_POLL_TEST_COMPLETE 0x0 /* enum */ 2353 #define MC_CMD_FC_OUT_DDR_TEST_POLL_TEST_FAIL 0x1 /* enum */ 2354 #define MC_CMD_FC_OUT_DDR_TEST_POLL_TEST_PASS 0x2 /* enum */ 2355 #define MC_CMD_FC_OUT_DDR_TEST_POLL_CAL_FAIL 0x3 /* enum */ 2356 #define MC_CMD_FC_OUT_DDR_TEST_POLL_CAL_SUCCESS 0x4 /* enum */ 2357 2358 /* MC_CMD_FC_OUT_DDR_TEST msgresponse */ 2359 #define MC_CMD_FC_OUT_DDR_TEST_LEN 0 2360 2361 /* MC_CMD_FC_OUT_GET_ASSERT msgresponse */ 2362 #define MC_CMD_FC_OUT_GET_ASSERT_LEN 144 2363 /* Assertion status flag. */ 2364 #define MC_CMD_FC_OUT_GET_ASSERT_GLOBAL_FLAGS_OFST 0 2365 #define MC_CMD_FC_OUT_GET_ASSERT_STATE_LBN 8 2366 #define MC_CMD_FC_OUT_GET_ASSERT_STATE_WIDTH 8 2367 /* enum: No crash data available */ 2368 #define MC_CMD_FC_GET_ASSERT_FLAGS_STATE_CLEAR 0x0 2369 /* enum: New crash data available */ 2370 #define MC_CMD_FC_GET_ASSERT_FLAGS_STATE_NEW 0x1 2371 /* enum: Crash data has been sent */ 2372 #define MC_CMD_FC_GET_ASSERT_FLAGS_STATE_NOTIFIED 0x2 2373 #define MC_CMD_FC_OUT_GET_ASSERT_TYPE_LBN 0 2374 #define MC_CMD_FC_OUT_GET_ASSERT_TYPE_WIDTH 8 2375 /* enum: No crash has been recorded. */ 2376 #define MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_NONE 0x0 2377 /* enum: Crash due to exception. */ 2378 #define MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_EXCEPTION 0x1 2379 /* enum: Crash due to assertion. */ 2380 #define MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_ASSERTION 0x2 2381 /* Failing PC value */ 2382 #define MC_CMD_FC_OUT_GET_ASSERT_SAVED_PC_OFFS_OFST 4 2383 /* Saved GP regs */ 2384 #define MC_CMD_FC_OUT_GET_ASSERT_GP_REGS_OFFS_OFST 8 2385 #define MC_CMD_FC_OUT_GET_ASSERT_GP_REGS_OFFS_LEN 4 2386 #define MC_CMD_FC_OUT_GET_ASSERT_GP_REGS_OFFS_NUM 31 2387 /* Exception Type */ 2388 #define MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_TYPE_OFFS_OFST 132 2389 /* Instruction at which exception occurred */ 2390 #define MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_PC_ADDR_OFFS_OFST 136 2391 /* BAD Address that triggered address-based exception */ 2392 #define MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_BAD_ADDR_OFFS_OFST 140 2393 2394 /* MC_CMD_FC_OUT_FPGA_BUILD msgresponse */ 2395 #define MC_CMD_FC_OUT_FPGA_BUILD_LEN 32 2396 #define MC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_INFO_OFST 0 2397 #define MC_CMD_FC_OUT_FPGA_BUILD_IS_APPLICATION_LBN 31 2398 #define MC_CMD_FC_OUT_FPGA_BUILD_IS_APPLICATION_WIDTH 1 2399 #define MC_CMD_FC_OUT_FPGA_BUILD_IS_LICENSED_LBN 30 2400 #define MC_CMD_FC_OUT_FPGA_BUILD_IS_LICENSED_WIDTH 1 2401 #define MC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_ID_LBN 16 2402 #define MC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_ID_WIDTH 14 2403 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MAJOR_LBN 12 2404 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MAJOR_WIDTH 4 2405 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MINOR_LBN 4 2406 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MINOR_WIDTH 8 2407 #define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_NUM_LBN 0 2408 #define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_NUM_WIDTH 4 2409 /* Build timestamp (seconds since epoch) */ 2410 #define MC_CMD_FC_OUT_FPGA_BUILD_TIMESTAMP_OFST 4 2411 #define MC_CMD_FC_OUT_FPGA_BUILD_PARAMETERS_OFST 8 2412 #define MC_CMD_FC_OUT_FPGA_BUILD_FPGA_TYPE_LBN 0 2413 #define MC_CMD_FC_OUT_FPGA_BUILD_FPGA_TYPE_WIDTH 8 2414 #define MC_CMD_FC_FPGA_TYPE_A7 0xa7 /* enum */ 2415 #define MC_CMD_FC_FPGA_TYPE_A5 0xa5 /* enum */ 2416 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED1_LBN 8 2417 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED1_WIDTH 10 2418 #define MC_CMD_FC_OUT_FPGA_BUILD_PTP_ENABLED_LBN 18 2419 #define MC_CMD_FC_OUT_FPGA_BUILD_PTP_ENABLED_WIDTH 1 2420 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM1_RLDRAM_DEF_LBN 19 2421 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM1_RLDRAM_DEF_WIDTH 1 2422 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM2_RLDRAM_DEF_LBN 20 2423 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM2_RLDRAM_DEF_WIDTH 1 2424 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM3_RLDRAM_DEF_LBN 21 2425 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM3_RLDRAM_DEF_WIDTH 1 2426 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM4_RLDRAM_DEF_LBN 22 2427 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM4_RLDRAM_DEF_WIDTH 1 2428 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T0_DDR3_DEF_LBN 23 2429 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T0_DDR3_DEF_WIDTH 1 2430 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_DDR3_DEF_LBN 24 2431 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_DDR3_DEF_WIDTH 1 2432 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B0_DDR3_DEF_LBN 25 2433 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B0_DDR3_DEF_WIDTH 1 2434 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B1_DDR3_DEF_LBN 26 2435 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B1_DDR3_DEF_WIDTH 1 2436 #define MC_CMD_FC_OUT_FPGA_BUILD_DDR3_ECC_ENABLED_LBN 27 2437 #define MC_CMD_FC_OUT_FPGA_BUILD_DDR3_ECC_ENABLED_WIDTH 1 2438 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_QDR_DEF_LBN 28 2439 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_QDR_DEF_WIDTH 1 2440 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED2_LBN 29 2441 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED2_WIDTH 2 2442 #define MC_CMD_FC_OUT_FPGA_BUILD_CRC_APPEND_LBN 31 2443 #define MC_CMD_FC_OUT_FPGA_BUILD_CRC_APPEND_WIDTH 1 2444 #define MC_CMD_FC_OUT_FPGA_BUILD_IDENTIFIER_OFST 12 2445 #define MC_CMD_FC_OUT_FPGA_BUILD_CHANGESET_LBN 0 2446 #define MC_CMD_FC_OUT_FPGA_BUILD_CHANGESET_WIDTH 16 2447 #define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_FLAG_LBN 16 2448 #define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_FLAG_WIDTH 1 2449 #define MC_CMD_FC_FPGA_BUILD_FLAG_INTERNAL 0x0 /* enum */ 2450 #define MC_CMD_FC_FPGA_BUILD_FLAG_RELEASE 0x1 /* enum */ 2451 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED3_LBN 17 2452 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED3_WIDTH 15 2453 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_HI_OFST 16 2454 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MINOR_LBN 0 2455 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MINOR_WIDTH 16 2456 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MAJOR_LBN 16 2457 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MAJOR_WIDTH 16 2458 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_LO_OFST 20 2459 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_BUILD_LBN 0 2460 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_BUILD_WIDTH 16 2461 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MICRO_LBN 16 2462 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MICRO_WIDTH 16 2463 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_OFST 16 2464 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_LEN 8 2465 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_LO_OFST 16 2466 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_HI_OFST 20 2467 #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_LO_OFST 24 2468 #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HI_OFST 28 2469 #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HIGH_LBN 0 2470 #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HIGH_WIDTH 16 2471 2472 /* MC_CMD_FC_OUT_FPGA_BUILD_V2 msgresponse */ 2473 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_LEN 32 2474 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_INFO_OFST 0 2475 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_APPLICATION_LBN 31 2476 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_APPLICATION_WIDTH 1 2477 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_LICENSED_LBN 30 2478 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_LICENSED_WIDTH 1 2479 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_ID_LBN 16 2480 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_ID_WIDTH 14 2481 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MAJOR_LBN 12 2482 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MAJOR_WIDTH 4 2483 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MINOR_LBN 4 2484 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MINOR_WIDTH 8 2485 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_NUM_LBN 0 2486 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_NUM_WIDTH 4 2487 /* Build timestamp (seconds since epoch) */ 2488 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_TIMESTAMP_OFST 4 2489 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_PARAMETERS_OFST 8 2490 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_PMA_PASSTHROUGH_LBN 31 2491 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_PMA_PASSTHROUGH_WIDTH 1 2492 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_QDR_DEF_LBN 29 2493 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_QDR_DEF_WIDTH 1 2494 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_QDR_DEF_LBN 28 2495 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_QDR_DEF_WIDTH 1 2496 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DDR3_ECC_ENABLED_LBN 27 2497 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DDR3_ECC_ENABLED_WIDTH 1 2498 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_DDR3_DEF_LBN 26 2499 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_DDR3_DEF_WIDTH 1 2500 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_DDR3_DEF_LBN 25 2501 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_DDR3_DEF_WIDTH 1 2502 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_TO_DDR3_DEF_LBN 24 2503 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_TO_DDR3_DEF_WIDTH 1 2504 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_T0_DDR3_DEF_LBN 23 2505 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_T0_DDR3_DEF_WIDTH 1 2506 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_RLDRAM_DEF_LBN 22 2507 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_RLDRAM_DEF_WIDTH 1 2508 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_RLDRAM_DEF_LBN 21 2509 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_RLDRAM_DEF_WIDTH 1 2510 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_RLDRAM_DEF_LBN 20 2511 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_RLDRAM_DEF_WIDTH 1 2512 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_RLDRAM_DEF_LBN 19 2513 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_RLDRAM_DEF_WIDTH 1 2514 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_LBN 18 2515 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_WIDTH 1 2516 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_10G 0x0 /* enum */ 2517 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_40G 0x1 /* enum */ 2518 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_LBN 17 2519 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_WIDTH 1 2520 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_10G 0x0 /* enum */ 2521 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_40G 0x1 /* enum */ 2522 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_LBN 16 2523 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_WIDTH 1 2524 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_10G 0x0 /* enum */ 2525 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_40G 0x1 /* enum */ 2526 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP7_DEF_LBN 15 2527 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP7_DEF_WIDTH 1 2528 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP6_DEF_LBN 14 2529 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP6_DEF_WIDTH 1 2530 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP5_DEF_LBN 13 2531 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP5_DEF_WIDTH 1 2532 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_DEF_LBN 12 2533 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_DEF_WIDTH 1 2534 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP3_DEF_LBN 11 2535 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP3_DEF_WIDTH 1 2536 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP2_DEF_LBN 10 2537 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP2_DEF_WIDTH 1 2538 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP1_DEF_LBN 9 2539 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP1_DEF_WIDTH 1 2540 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_DEF_LBN 8 2541 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_DEF_WIDTH 1 2542 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC3_DEF_LBN 7 2543 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC3_DEF_WIDTH 1 2544 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC2_DEF_LBN 6 2545 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC2_DEF_WIDTH 1 2546 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC1_DEF_LBN 5 2547 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC1_DEF_WIDTH 1 2548 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_DEF_LBN 4 2549 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_DEF_WIDTH 1 2550 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_FPGA_TYPE_LBN 0 2551 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_FPGA_TYPE_WIDTH 4 2552 #define MC_CMD_FC_FPGA_V2_TYPE_A3 0x0 /* enum */ 2553 #define MC_CMD_FC_FPGA_V2_TYPE_A4 0x1 /* enum */ 2554 #define MC_CMD_FC_FPGA_V2_TYPE_A5 0x2 /* enum */ 2555 #define MC_CMD_FC_FPGA_V2_TYPE_A7 0x3 /* enum */ 2556 #define MC_CMD_FC_FPGA_V2_TYPE_D3 0x8 /* enum */ 2557 #define MC_CMD_FC_FPGA_V2_TYPE_D4 0x9 /* enum */ 2558 #define MC_CMD_FC_FPGA_V2_TYPE_D5 0xa /* enum */ 2559 #define MC_CMD_FC_FPGA_V2_TYPE_D7 0xb /* enum */ 2560 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_IDENTIFIER_OFST 12 2561 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_CHANGESET_LBN 0 2562 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_CHANGESET_WIDTH 16 2563 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_FLAG_LBN 16 2564 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_FLAG_WIDTH 1 2565 /* MC_CMD_FC_FPGA_BUILD_FLAG_INTERNAL 0x0 */ 2566 /* MC_CMD_FC_FPGA_BUILD_FLAG_RELEASE 0x1 */ 2567 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_HI_OFST 16 2568 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MINOR_LBN 0 2569 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MINOR_WIDTH 16 2570 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MAJOR_LBN 16 2571 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MAJOR_WIDTH 16 2572 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_LO_OFST 20 2573 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_BUILD_LBN 0 2574 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_BUILD_WIDTH 16 2575 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MICRO_LBN 16 2576 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MICRO_WIDTH 16 2577 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_LO_OFST 24 2578 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HI_OFST 28 2579 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HIGH_LBN 0 2580 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HIGH_WIDTH 16 2581 2582 /* MC_CMD_FC_OUT_FPGA_SERVICES msgresponse */ 2583 #define MC_CMD_FC_OUT_FPGA_SERVICES_LEN 32 2584 #define MC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_INFO_OFST 0 2585 #define MC_CMD_FC_OUT_FPGA_SERVICES_IS_APPLICATION_LBN 31 2586 #define MC_CMD_FC_OUT_FPGA_SERVICES_IS_APPLICATION_WIDTH 1 2587 #define MC_CMD_FC_OUT_FPGA_SERVICES_IS_LICENSED_LBN 30 2588 #define MC_CMD_FC_OUT_FPGA_SERVICES_IS_LICENSED_WIDTH 1 2589 #define MC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_ID_LBN 16 2590 #define MC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_ID_WIDTH 14 2591 #define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MAJOR_LBN 12 2592 #define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MAJOR_WIDTH 4 2593 #define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MINOR_LBN 4 2594 #define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MINOR_WIDTH 8 2595 #define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_NUM_LBN 0 2596 #define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_NUM_WIDTH 4 2597 /* Build timestamp (seconds since epoch) */ 2598 #define MC_CMD_FC_OUT_FPGA_SERVICES_TIMESTAMP_OFST 4 2599 #define MC_CMD_FC_OUT_FPGA_SERVICES_PARAMETERS_OFST 8 2600 #define MC_CMD_FC_OUT_FPGA_SERVICES_FC_FLASH_BOOTED_LBN 8 2601 #define MC_CMD_FC_OUT_FPGA_SERVICES_FC_FLASH_BOOTED_WIDTH 1 2602 #define MC_CMD_FC_OUT_FPGA_SERVICES_NIC0_DEF_LBN 27 2603 #define MC_CMD_FC_OUT_FPGA_SERVICES_NIC0_DEF_WIDTH 1 2604 #define MC_CMD_FC_OUT_FPGA_SERVICES_NIC1_DEF_LBN 28 2605 #define MC_CMD_FC_OUT_FPGA_SERVICES_NIC1_DEF_WIDTH 1 2606 #define MC_CMD_FC_OUT_FPGA_SERVICES_SFP0_DEF_LBN 29 2607 #define MC_CMD_FC_OUT_FPGA_SERVICES_SFP0_DEF_WIDTH 1 2608 #define MC_CMD_FC_OUT_FPGA_SERVICES_SFP1_DEF_LBN 30 2609 #define MC_CMD_FC_OUT_FPGA_SERVICES_SFP1_DEF_WIDTH 1 2610 #define MC_CMD_FC_OUT_FPGA_SERVICES_RESERVED_LBN 31 2611 #define MC_CMD_FC_OUT_FPGA_SERVICES_RESERVED_WIDTH 1 2612 #define MC_CMD_FC_OUT_FPGA_SERVICES_IDENTIFIER_OFST 12 2613 #define MC_CMD_FC_OUT_FPGA_SERVICES_CHANGESET_LBN 0 2614 #define MC_CMD_FC_OUT_FPGA_SERVICES_CHANGESET_WIDTH 16 2615 #define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_FLAG_LBN 16 2616 #define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_FLAG_WIDTH 1 2617 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_OFST 16 2618 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_WIDTH_LBN 0 2619 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_WIDTH_WIDTH 16 2620 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_COUNT_LBN 16 2621 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_COUNT_WIDTH 16 2622 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_OFST 20 2623 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_WIDTH_LBN 0 2624 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_WIDTH_WIDTH 16 2625 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_COUNT_LBN 16 2626 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_COUNT_WIDTH 16 2627 #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_LO_OFST 24 2628 #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HI_OFST 28 2629 #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HIGH_LBN 0 2630 #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HIGH_WIDTH 16 2631 2632 /* MC_CMD_FC_OUT_FPGA_SERVICES_V2 msgresponse */ 2633 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_LEN 32 2634 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_INFO_OFST 0 2635 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_APPLICATION_LBN 31 2636 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_APPLICATION_WIDTH 1 2637 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_LICENSED_LBN 30 2638 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_LICENSED_WIDTH 1 2639 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_ID_LBN 16 2640 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_ID_WIDTH 14 2641 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MAJOR_LBN 12 2642 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MAJOR_WIDTH 4 2643 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MINOR_LBN 4 2644 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MINOR_WIDTH 8 2645 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_NUM_LBN 0 2646 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_NUM_WIDTH 4 2647 /* Build timestamp (seconds since epoch) */ 2648 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_TIMESTAMP_OFST 4 2649 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_PARAMETERS_OFST 8 2650 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_PTP_ENABLED_LBN 0 2651 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_PTP_ENABLED_WIDTH 1 2652 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_FC_FLASH_BOOTED_LBN 8 2653 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_FC_FLASH_BOOTED_WIDTH 1 2654 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IDENTIFIER_OFST 12 2655 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_CHANGESET_LBN 0 2656 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_CHANGESET_WIDTH 16 2657 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_FLAG_LBN 16 2658 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_FLAG_WIDTH 1 2659 /* MC_CMD_FC_FPGA_BUILD_FLAG_INTERNAL 0x0 */ 2660 /* MC_CMD_FC_FPGA_BUILD_FLAG_RELEASE 0x1 */ 2661 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_LO_OFST 24 2662 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HI_OFST 28 2663 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HIGH_LBN 0 2664 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HIGH_WIDTH 16 2665 2666 /* MC_CMD_FC_OUT_BSP_VERSION msgresponse */ 2667 #define MC_CMD_FC_OUT_BSP_VERSION_LEN 4 2668 /* Qsys system ID */ 2669 #define MC_CMD_FC_OUT_BSP_VERSION_SYSID_OFST 0 2670 #define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MAJOR_LBN 12 2671 #define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MAJOR_WIDTH 4 2672 #define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MINOR_LBN 4 2673 #define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MINOR_WIDTH 8 2674 #define MC_CMD_FC_OUT_BSP_VERSION_BUILD_NUM_LBN 0 2675 #define MC_CMD_FC_OUT_BSP_VERSION_BUILD_NUM_WIDTH 4 2676 2677 /* MC_CMD_FC_OUT_READ_MAP_COUNT msgresponse */ 2678 #define MC_CMD_FC_OUT_READ_MAP_COUNT_LEN 4 2679 /* Number of maps */ 2680 #define MC_CMD_FC_OUT_READ_MAP_COUNT_NUM_MAPS_OFST 0 2681 2682 /* MC_CMD_FC_OUT_READ_MAP_INDEX msgresponse */ 2683 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN 164 2684 /* Index of the map */ 2685 #define MC_CMD_FC_OUT_READ_MAP_INDEX_INDEX_OFST 0 2686 /* Options for the map */ 2687 #define MC_CMD_FC_OUT_READ_MAP_INDEX_OPTIONS_OFST 4 2688 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_8 0x0 /* enum */ 2689 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_16 0x1 /* enum */ 2690 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_32 0x2 /* enum */ 2691 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_64 0x3 /* enum */ 2692 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_MASK 0x3 /* enum */ 2693 #define MC_CMD_FC_OUT_READ_MAP_INDEX_PATH_FC 0x4 /* enum */ 2694 #define MC_CMD_FC_OUT_READ_MAP_INDEX_PATH_MEM 0x8 /* enum */ 2695 #define MC_CMD_FC_OUT_READ_MAP_INDEX_PERM_READ 0x10 /* enum */ 2696 #define MC_CMD_FC_OUT_READ_MAP_INDEX_PERM_WRITE 0x20 /* enum */ 2697 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_FREE 0x0 /* enum */ 2698 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_LICENSED 0x40 /* enum */ 2699 /* Address of start of map */ 2700 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_OFST 8 2701 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_LEN 8 2702 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_LO_OFST 8 2703 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_HI_OFST 12 2704 /* Length of address map */ 2705 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_OFST 16 2706 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_LEN 8 2707 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_LO_OFST 16 2708 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_HI_OFST 20 2709 /* Component information field */ 2710 #define MC_CMD_FC_OUT_READ_MAP_INDEX_COMP_INFO_OFST 24 2711 /* License expiry data for map */ 2712 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_OFST 28 2713 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_LEN 8 2714 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_LO_OFST 28 2715 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_HI_OFST 32 2716 /* Name of the component */ 2717 #define MC_CMD_FC_OUT_READ_MAP_INDEX_NAME_OFST 36 2718 #define MC_CMD_FC_OUT_READ_MAP_INDEX_NAME_LEN 1 2719 #define MC_CMD_FC_OUT_READ_MAP_INDEX_NAME_NUM 128 2720 2721 /* MC_CMD_FC_OUT_READ_MAP msgresponse */ 2722 #define MC_CMD_FC_OUT_READ_MAP_LEN 0 2723 2724 /* MC_CMD_FC_OUT_CAPABILITIES msgresponse */ 2725 #define MC_CMD_FC_OUT_CAPABILITIES_LEN 8 2726 /* Number of internal ports */ 2727 #define MC_CMD_FC_OUT_CAPABILITIES_INTERNAL_OFST 0 2728 /* Number of external ports */ 2729 #define MC_CMD_FC_OUT_CAPABILITIES_EXTERNAL_OFST 4 2730 2731 /* MC_CMD_FC_OUT_GLOBAL_FLAGS msgresponse */ 2732 #define MC_CMD_FC_OUT_GLOBAL_FLAGS_LEN 4 2733 #define MC_CMD_FC_OUT_GLOBAL_FLAGS_FLAGS_OFST 0 2734 2735 /* MC_CMD_FC_OUT_IO_REL msgresponse */ 2736 #define MC_CMD_FC_OUT_IO_REL_LEN 0 2737 2738 /* MC_CMD_FC_OUT_IO_REL_GET_ADDR msgresponse */ 2739 #define MC_CMD_FC_OUT_IO_REL_GET_ADDR_LEN 8 2740 #define MC_CMD_FC_OUT_IO_REL_GET_ADDR_ADDR_HI_OFST 0 2741 #define MC_CMD_FC_OUT_IO_REL_GET_ADDR_ADDR_LO_OFST 4 2742 2743 /* MC_CMD_FC_OUT_IO_REL_READ32 msgresponse */ 2744 #define MC_CMD_FC_OUT_IO_REL_READ32_LENMIN 4 2745 #define MC_CMD_FC_OUT_IO_REL_READ32_LENMAX 252 2746 #define MC_CMD_FC_OUT_IO_REL_READ32_LEN(num) (0+4*(num)) 2747 #define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_OFST 0 2748 #define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_LEN 4 2749 #define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_MINNUM 1 2750 #define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_MAXNUM 63 2751 2752 /* MC_CMD_FC_OUT_IO_REL_WRITE32 msgresponse */ 2753 #define MC_CMD_FC_OUT_IO_REL_WRITE32_LEN 0 2754 2755 /* MC_CMD_FC_OUT_UHLINK_PHY msgresponse */ 2756 #define MC_CMD_FC_OUT_UHLINK_PHY_LEN 48 2757 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_SETTINGS_0_OFST 0 2758 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_VOD_LBN 0 2759 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_VOD_WIDTH 16 2760 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_1STPOSTTAP_LBN 16 2761 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_1STPOSTTAP_WIDTH 16 2762 /* Transceiver Transmit settings */ 2763 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_SETTINGS_1_OFST 4 2764 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_PRETAP_LBN 0 2765 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_PRETAP_WIDTH 16 2766 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_2NDPOSTTAP_LBN 16 2767 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_2NDPOSTTAP_WIDTH 16 2768 /* Transceiver Receive settings */ 2769 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_SETTINGS_OFST 8 2770 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_DC_GAIN_LBN 0 2771 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_DC_GAIN_WIDTH 16 2772 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_EQ_CONTROL_LBN 16 2773 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_EQ_CONTROL_WIDTH 16 2774 /* Rx eye opening */ 2775 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_OFST 12 2776 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_WIDTH_LBN 0 2777 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_WIDTH_WIDTH 16 2778 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_HEIGHT_LBN 16 2779 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_HEIGHT_WIDTH 16 2780 /* PCS status word */ 2781 #define MC_CMD_FC_OUT_UHLINK_PHY_PCS_STATUS_OFST 16 2782 /* Link status word */ 2783 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_WORD_OFST 20 2784 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_LBN 0 2785 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_WIDTH 1 2786 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_CONFIGURED_LBN 1 2787 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_CONFIGURED_WIDTH 1 2788 /* Current SFp parameters applied */ 2789 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_PARAMS_OFST 24 2790 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_PARAMS_LEN 20 2791 /* Link speed is 100, 1000, 10000 */ 2792 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_SPEED_OFST 24 2793 /* Length of copper cable - zero when not relevant */ 2794 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_COPPER_LEN_OFST 28 2795 /* True if a dual speed SFP+ module */ 2796 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_DUAL_SPEED_OFST 32 2797 /* True if an SFP Module is present (other fields valid when true) */ 2798 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_PRESENT_OFST 36 2799 /* The type of the SFP+ Module */ 2800 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_TYPE_OFST 40 2801 /* PHY config flags */ 2802 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_OFST 44 2803 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_DFE_LBN 0 2804 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_DFE_WIDTH 1 2805 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_AEQ_LBN 1 2806 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_AEQ_WIDTH 1 2807 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_RX_TUNING_LBN 2 2808 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_RX_TUNING_WIDTH 1 2809 2810 /* MC_CMD_FC_OUT_UHLINK_MAC msgresponse */ 2811 #define MC_CMD_FC_OUT_UHLINK_MAC_LEN 20 2812 /* MAC configuration applied */ 2813 #define MC_CMD_FC_OUT_UHLINK_MAC_CONFIG_OFST 0 2814 /* MTU size */ 2815 #define MC_CMD_FC_OUT_UHLINK_MAC_MTU_OFST 4 2816 /* IF Mode status */ 2817 #define MC_CMD_FC_OUT_UHLINK_MAC_IF_STATUS_OFST 8 2818 /* MAC address configured */ 2819 #define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_OFST 12 2820 #define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_LEN 8 2821 #define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_LO_OFST 12 2822 #define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_HI_OFST 16 2823 2824 /* MC_CMD_FC_OUT_UHLINK_RX_EYE msgresponse */ 2825 #define MC_CMD_FC_OUT_UHLINK_RX_EYE_LEN ((((0-1+(32*MC_CMD_FC_UHLINK_RX_EYE_PER_BLOCK))+1))>>3) 2826 /* Rx Eye measurements */ 2827 #define MC_CMD_FC_OUT_UHLINK_RX_EYE_RX_EYE_OFST 0 2828 #define MC_CMD_FC_OUT_UHLINK_RX_EYE_RX_EYE_LEN 4 2829 #define MC_CMD_FC_OUT_UHLINK_RX_EYE_RX_EYE_NUM MC_CMD_FC_UHLINK_RX_EYE_PER_BLOCK 2830 2831 /* MC_CMD_FC_OUT_UHLINK_DUMP_RX_EYE_PLOT msgresponse */ 2832 #define MC_CMD_FC_OUT_UHLINK_DUMP_RX_EYE_PLOT_LEN 0 2833 2834 /* MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT msgresponse */ 2835 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_LEN ((((32-1+(64*MC_CMD_FC_UHLINK_RX_EYE_PLOT_ROWS_PER_BLOCK))+1))>>3) 2836 /* Has the eye plot dump completed and data returned is valid? */ 2837 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_VALID_OFST 0 2838 /* Rx Eye binary plot */ 2839 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_OFST 4 2840 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_LEN 8 2841 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_LO_OFST 4 2842 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_HI_OFST 8 2843 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_NUM MC_CMD_FC_UHLINK_RX_EYE_PLOT_ROWS_PER_BLOCK 2844 2845 /* MC_CMD_FC_OUT_UHLINK_RX_TUNE msgresponse */ 2846 #define MC_CMD_FC_OUT_UHLINK_RX_TUNE_LEN 0 2847 2848 /* MC_CMD_FC_OUT_UHLINK_LOOPBACK_SET msgresponse */ 2849 #define MC_CMD_FC_OUT_UHLINK_LOOPBACK_SET_LEN 0 2850 2851 /* MC_CMD_FC_OUT_UHLINK_LOOPBACK_GET msgresponse */ 2852 #define MC_CMD_FC_OUT_UHLINK_LOOPBACK_GET_LEN 4 2853 #define MC_CMD_FC_OUT_UHLINK_LOOPBACK_GET_STATE_OFST 0 2854 2855 /* MC_CMD_FC_OUT_UHLINK msgresponse */ 2856 #define MC_CMD_FC_OUT_UHLINK_LEN 0 2857 2858 /* MC_CMD_FC_OUT_SET_LINK msgresponse */ 2859 #define MC_CMD_FC_OUT_SET_LINK_LEN 0 2860 2861 /* MC_CMD_FC_OUT_LICENSE msgresponse */ 2862 #define MC_CMD_FC_OUT_LICENSE_LEN 12 2863 /* Count of valid keys */ 2864 #define MC_CMD_FC_OUT_LICENSE_VALID_KEYS_OFST 0 2865 /* Count of invalid keys */ 2866 #define MC_CMD_FC_OUT_LICENSE_INVALID_KEYS_OFST 4 2867 /* Count of blacklisted keys */ 2868 #define MC_CMD_FC_OUT_LICENSE_BLACKLISTED_KEYS_OFST 8 2869 2870 /* MC_CMD_FC_OUT_STARTUP msgresponse */ 2871 #define MC_CMD_FC_OUT_STARTUP_LEN 4 2872 /* Capabilities of the FPGA/FC */ 2873 #define MC_CMD_FC_OUT_STARTUP_CAPABILITIES_OFST 0 2874 #define MC_CMD_FC_OUT_STARTUP_CAN_ACCESS_FLASH_LBN 0 2875 #define MC_CMD_FC_OUT_STARTUP_CAN_ACCESS_FLASH_WIDTH 1 2876 2877 /* MC_CMD_FC_OUT_DMA_READ msgresponse */ 2878 #define MC_CMD_FC_OUT_DMA_READ_LENMIN 1 2879 #define MC_CMD_FC_OUT_DMA_READ_LENMAX 252 2880 #define MC_CMD_FC_OUT_DMA_READ_LEN(num) (0+1*(num)) 2881 /* The data read */ 2882 #define MC_CMD_FC_OUT_DMA_READ_DATA_OFST 0 2883 #define MC_CMD_FC_OUT_DMA_READ_DATA_LEN 1 2884 #define MC_CMD_FC_OUT_DMA_READ_DATA_MINNUM 1 2885 #define MC_CMD_FC_OUT_DMA_READ_DATA_MAXNUM 252 2886 2887 /* MC_CMD_FC_OUT_TIMED_READ_SET msgresponse */ 2888 #define MC_CMD_FC_OUT_TIMED_READ_SET_LEN 4 2889 /* Timer handle */ 2890 #define MC_CMD_FC_OUT_TIMED_READ_SET_FC_HANDLE_OFST 0 2891 2892 /* MC_CMD_FC_OUT_TIMED_READ_GET msgresponse */ 2893 #define MC_CMD_FC_OUT_TIMED_READ_GET_LEN 52 2894 /* Host supplied handle (unique) */ 2895 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_HANDLE_OFST 0 2896 /* Address into which to transfer data in host */ 2897 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_OFST 4 2898 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_LEN 8 2899 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_LO_OFST 4 2900 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_HI_OFST 8 2901 /* AOE address from which to transfer data */ 2902 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_OFST 12 2903 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_LEN 8 2904 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_LO_OFST 12 2905 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_HI_OFST 16 2906 /* Length of AOE transfer (total) */ 2907 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_LENGTH_OFST 20 2908 /* Length of host transfer (total) */ 2909 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_LENGTH_OFST 24 2910 /* See FLAGS entry for MC_CMD_FC_IN_TIMED_READ_SET */ 2911 #define MC_CMD_FC_OUT_TIMED_READ_GET_FLAGS_OFST 28 2912 #define MC_CMD_FC_OUT_TIMED_READ_GET_PERIOD_OFST 32 2913 /* When active, start read time */ 2914 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_OFST 36 2915 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_LEN 8 2916 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_LO_OFST 36 2917 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_HI_OFST 40 2918 /* When active, end read time */ 2919 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_OFST 44 2920 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_LEN 8 2921 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_LO_OFST 44 2922 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_HI_OFST 48 2923 2924 /* MC_CMD_FC_OUT_LOG_ADDR_RANGE msgresponse */ 2925 #define MC_CMD_FC_OUT_LOG_ADDR_RANGE_LEN 0 2926 2927 /* MC_CMD_FC_OUT_LOG msgresponse */ 2928 #define MC_CMD_FC_OUT_LOG_LEN 0 2929 2930 /* MC_CMD_FC_OUT_CLOCK_GET_TIME msgresponse */ 2931 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_LEN 24 2932 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_CLOCK_ID_OFST 0 2933 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_OFST 4 2934 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_LEN 8 2935 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_LO_OFST 4 2936 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_HI_OFST 8 2937 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_NANOSECONDS_OFST 12 2938 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_RANGE_OFST 16 2939 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_PRECISION_OFST 20 2940 2941 /* MC_CMD_FC_OUT_CLOCK_SET_TIME msgresponse */ 2942 #define MC_CMD_FC_OUT_CLOCK_SET_TIME_LEN 0 2943 2944 /* MC_CMD_FC_OUT_DDR_SET_SPD msgresponse */ 2945 #define MC_CMD_FC_OUT_DDR_SET_SPD_LEN 0 2946 2947 /* MC_CMD_FC_OUT_DDR_SET_INFO msgresponse */ 2948 #define MC_CMD_FC_OUT_DDR_SET_INFO_LEN 0 2949 2950 /* MC_CMD_FC_OUT_DDR_GET_STATUS msgresponse */ 2951 #define MC_CMD_FC_OUT_DDR_GET_STATUS_LEN 4 2952 #define MC_CMD_FC_OUT_DDR_GET_STATUS_FLAGS_OFST 0 2953 #define MC_CMD_FC_OUT_DDR_GET_STATUS_READY_LBN 0 2954 #define MC_CMD_FC_OUT_DDR_GET_STATUS_READY_WIDTH 1 2955 #define MC_CMD_FC_OUT_DDR_GET_STATUS_CALIBRATED_LBN 1 2956 #define MC_CMD_FC_OUT_DDR_GET_STATUS_CALIBRATED_WIDTH 1 2957 2958 /* MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT msgresponse */ 2959 #define MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_LEN 8 2960 #define MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_SECONDS_OFST 0 2961 #define MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_NANOSECONDS_OFST 4 2962 2963 /* MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT msgresponse */ 2964 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LENMIN 8 2965 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LENMAX 248 2966 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LEN(num) (0+8*(num)) 2967 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_SECONDS_OFST 0 2968 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_NANOSECONDS_OFST 4 2969 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_OFST 0 2970 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_LEN 8 2971 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_LO_OFST 0 2972 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_HI_OFST 4 2973 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_MINNUM 0 2974 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_MAXNUM 31 2975 2976 /* MC_CMD_FC_OUT_SPI_READ msgresponse */ 2977 #define MC_CMD_FC_OUT_SPI_READ_LENMIN 4 2978 #define MC_CMD_FC_OUT_SPI_READ_LENMAX 252 2979 #define MC_CMD_FC_OUT_SPI_READ_LEN(num) (0+4*(num)) 2980 #define MC_CMD_FC_OUT_SPI_READ_BUFFER_OFST 0 2981 #define MC_CMD_FC_OUT_SPI_READ_BUFFER_LEN 4 2982 #define MC_CMD_FC_OUT_SPI_READ_BUFFER_MINNUM 1 2983 #define MC_CMD_FC_OUT_SPI_READ_BUFFER_MAXNUM 63 2984 2985 /* MC_CMD_FC_OUT_SPI_WRITE msgresponse */ 2986 #define MC_CMD_FC_OUT_SPI_WRITE_LEN 0 2987 2988 /* MC_CMD_FC_OUT_SPI_ERASE msgresponse */ 2989 #define MC_CMD_FC_OUT_SPI_ERASE_LEN 0 2990 2991 /* MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG msgresponse */ 2992 #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_LEN 8 2993 /* The 32-bit value read from the toggle count register */ 2994 #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_TOGGLE_COUNT_OFST 0 2995 /* The 32-bit value read from the clock enable count register */ 2996 #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_CLKEN_COUNT_OFST 4 2997 2998 /* MC_CMD_FC_OUT_DIAG_POWER_NOISE_WRITE_CONFIG msgresponse */ 2999 #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_WRITE_CONFIG_LEN 0 3000 3001 /* MC_CMD_FC_OUT_DIAG_DDR_SOAK_START msgresponse */ 3002 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_START_LEN 0 3003 3004 /* MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT msgresponse */ 3005 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_LEN 8 3006 /* DDR soak test status word; bits [4:0] are relevant. */ 3007 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_STATUS_OFST 0 3008 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PASSED_LBN 0 3009 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PASSED_WIDTH 1 3010 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_FAILED_LBN 1 3011 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_FAILED_WIDTH 1 3012 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_COMPLETED_LBN 2 3013 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_COMPLETED_WIDTH 1 3014 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_TIMEOUT_LBN 3 3015 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_TIMEOUT_WIDTH 1 3016 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PNF_LBN 4 3017 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PNF_WIDTH 1 3018 /* DDR soak test error count */ 3019 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_ERR_COUNT_OFST 4 3020 3021 /* MC_CMD_FC_OUT_DIAG_DDR_SOAK_STOP msgresponse */ 3022 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_STOP_LEN 0 3023 3024 /* MC_CMD_FC_OUT_DIAG_DDR_SOAK_ERROR msgresponse */ 3025 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_ERROR_LEN 0 3026 3027 /* MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_SET_MODE msgresponse */ 3028 #define MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_SET_MODE_LEN 0 3029 3030 /* MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_RAW_CONFIG msgresponse */ 3031 #define MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_RAW_CONFIG_LEN 0 3032 3033 3034 /***********************************/ 3035 /* MC_CMD_AOE 3036 * AOE operations on MC 3037 */ 3038 #define MC_CMD_AOE 0xa 3039 3040 /* MC_CMD_AOE_IN msgrequest */ 3041 #define MC_CMD_AOE_IN_LEN 4 3042 #define MC_CMD_AOE_IN_OP_HDR_OFST 0 3043 #define MC_CMD_AOE_IN_OP_LBN 0 3044 #define MC_CMD_AOE_IN_OP_WIDTH 8 3045 /* enum: FPGA and CPLD information */ 3046 #define MC_CMD_AOE_OP_INFO 0x1 3047 /* enum: Currents and voltages read from MCP3424s; DEBUG */ 3048 #define MC_CMD_AOE_OP_CURRENTS 0x2 3049 /* enum: Temperatures at locations around the PCB; DEBUG */ 3050 #define MC_CMD_AOE_OP_TEMPERATURES 0x3 3051 /* enum: Set CPLD to idle */ 3052 #define MC_CMD_AOE_OP_CPLD_IDLE 0x4 3053 /* enum: Read from CPLD register */ 3054 #define MC_CMD_AOE_OP_CPLD_READ 0x5 3055 /* enum: Write to CPLD register */ 3056 #define MC_CMD_AOE_OP_CPLD_WRITE 0x6 3057 /* enum: Execute CPLD instruction */ 3058 #define MC_CMD_AOE_OP_CPLD_INSTRUCTION 0x7 3059 /* enum: Reprogram the CPLD on the AOE device */ 3060 #define MC_CMD_AOE_OP_CPLD_REPROGRAM 0x8 3061 /* enum: AOE power control */ 3062 #define MC_CMD_AOE_OP_POWER 0x9 3063 /* enum: AOE image loading */ 3064 #define MC_CMD_AOE_OP_LOAD 0xa 3065 /* enum: Fan monitoring */ 3066 #define MC_CMD_AOE_OP_FAN_CONTROL 0xb 3067 /* enum: Fan failures since last reset */ 3068 #define MC_CMD_AOE_OP_FAN_FAILURES 0xc 3069 /* enum: Get generic AOE MAC statistics */ 3070 #define MC_CMD_AOE_OP_MAC_STATS 0xd 3071 /* enum: Retrieve PHY specific information */ 3072 #define MC_CMD_AOE_OP_GET_PHY_MEDIA_INFO 0xe 3073 /* enum: Write a number of JTAG primitive commands, return will give data */ 3074 #define MC_CMD_AOE_OP_JTAG_WRITE 0xf 3075 /* enum: Control access to the FPGA via the Siena JTAG Chain */ 3076 #define MC_CMD_AOE_OP_FPGA_ACCESS 0x10 3077 /* enum: Set the MTU offset between Siena and AOE MACs */ 3078 #define MC_CMD_AOE_OP_SET_MTU_OFFSET 0x11 3079 /* enum: How link state is handled */ 3080 #define MC_CMD_AOE_OP_LINK_STATE 0x12 3081 /* enum: How Siena MAC statistics are reported (deprecated - use 3082 * MC_CMD_AOE_OP_ASIC_STATS) 3083 */ 3084 #define MC_CMD_AOE_OP_SIENA_STATS 0x13 3085 /* enum: How native ASIC MAC statistics are reported - replaces the deprecated 3086 * command MC_CMD_AOE_OP_SIENA_STATS 3087 */ 3088 #define MC_CMD_AOE_OP_ASIC_STATS 0x13 3089 /* enum: DDR memory information */ 3090 #define MC_CMD_AOE_OP_DDR 0x14 3091 /* enum: FC control */ 3092 #define MC_CMD_AOE_OP_FC 0x15 3093 /* enum: DDR ECC status reads */ 3094 #define MC_CMD_AOE_OP_DDR_ECC_STATUS 0x16 3095 /* enum: Commands for MC-SPI Master emulation */ 3096 #define MC_CMD_AOE_OP_MC_SPI_MASTER 0x17 3097 /* enum: Commands for FC boot control */ 3098 #define MC_CMD_AOE_OP_FC_BOOT 0x18 3099 3100 /* MC_CMD_AOE_OUT msgresponse */ 3101 #define MC_CMD_AOE_OUT_LEN 0 3102 3103 /* MC_CMD_AOE_IN_INFO msgrequest */ 3104 #define MC_CMD_AOE_IN_INFO_LEN 4 3105 #define MC_CMD_AOE_IN_CMD_OFST 0 3106 3107 /* MC_CMD_AOE_IN_CURRENTS msgrequest */ 3108 #define MC_CMD_AOE_IN_CURRENTS_LEN 4 3109 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3110 3111 /* MC_CMD_AOE_IN_TEMPERATURES msgrequest */ 3112 #define MC_CMD_AOE_IN_TEMPERATURES_LEN 4 3113 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3114 3115 /* MC_CMD_AOE_IN_CPLD_IDLE msgrequest */ 3116 #define MC_CMD_AOE_IN_CPLD_IDLE_LEN 4 3117 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3118 3119 /* MC_CMD_AOE_IN_CPLD_READ msgrequest */ 3120 #define MC_CMD_AOE_IN_CPLD_READ_LEN 12 3121 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3122 #define MC_CMD_AOE_IN_CPLD_READ_REGISTER_OFST 4 3123 #define MC_CMD_AOE_IN_CPLD_READ_WIDTH_OFST 8 3124 3125 /* MC_CMD_AOE_IN_CPLD_WRITE msgrequest */ 3126 #define MC_CMD_AOE_IN_CPLD_WRITE_LEN 16 3127 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3128 #define MC_CMD_AOE_IN_CPLD_WRITE_REGISTER_OFST 4 3129 #define MC_CMD_AOE_IN_CPLD_WRITE_WIDTH_OFST 8 3130 #define MC_CMD_AOE_IN_CPLD_WRITE_VALUE_OFST 12 3131 3132 /* MC_CMD_AOE_IN_CPLD_INSTRUCTION msgrequest */ 3133 #define MC_CMD_AOE_IN_CPLD_INSTRUCTION_LEN 8 3134 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3135 #define MC_CMD_AOE_IN_CPLD_INSTRUCTION_INSTRUCTION_OFST 4 3136 3137 /* MC_CMD_AOE_IN_CPLD_REPROGRAM msgrequest */ 3138 #define MC_CMD_AOE_IN_CPLD_REPROGRAM_LEN 8 3139 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3140 #define MC_CMD_AOE_IN_CPLD_REPROGRAM_OP_OFST 4 3141 /* enum: Reprogram CPLD, poll for completion */ 3142 #define MC_CMD_AOE_IN_CPLD_REPROGRAM_REPROGRAM 0x1 3143 /* enum: Reprogram CPLD, send event on completion */ 3144 #define MC_CMD_AOE_IN_CPLD_REPROGRAM_REPROGRAM_EVENT 0x3 3145 /* enum: Get status of reprogramming operation */ 3146 #define MC_CMD_AOE_IN_CPLD_REPROGRAM_STATUS 0x4 3147 3148 /* MC_CMD_AOE_IN_POWER msgrequest */ 3149 #define MC_CMD_AOE_IN_POWER_LEN 8 3150 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3151 /* Turn on or off AOE power */ 3152 #define MC_CMD_AOE_IN_POWER_OP_OFST 4 3153 /* enum: Turn off FPGA power */ 3154 #define MC_CMD_AOE_IN_POWER_OFF 0x0 3155 /* enum: Turn on FPGA power */ 3156 #define MC_CMD_AOE_IN_POWER_ON 0x1 3157 /* enum: Clear peak power measurement */ 3158 #define MC_CMD_AOE_IN_POWER_CLEAR 0x2 3159 /* enum: Show current power in sensors output */ 3160 #define MC_CMD_AOE_IN_POWER_SHOW_CURRENT 0x3 3161 /* enum: Show peak power in sensors output */ 3162 #define MC_CMD_AOE_IN_POWER_SHOW_PEAK 0x4 3163 /* enum: Show current DDR current */ 3164 #define MC_CMD_AOE_IN_POWER_DDR_LAST 0x5 3165 /* enum: Show peak DDR current */ 3166 #define MC_CMD_AOE_IN_POWER_DDR_PEAK 0x6 3167 /* enum: Clear peak DDR current */ 3168 #define MC_CMD_AOE_IN_POWER_DDR_CLEAR 0x7 3169 3170 /* MC_CMD_AOE_IN_LOAD msgrequest */ 3171 #define MC_CMD_AOE_IN_LOAD_LEN 8 3172 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3173 /* Image to be loaded (0 - main or 1 - diagnostic) to load in normal sequence 3174 */ 3175 #define MC_CMD_AOE_IN_LOAD_IMAGE_OFST 4 3176 3177 /* MC_CMD_AOE_IN_FAN_CONTROL msgrequest */ 3178 #define MC_CMD_AOE_IN_FAN_CONTROL_LEN 8 3179 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3180 /* If non zero report measured fan RPM rather than nominal */ 3181 #define MC_CMD_AOE_IN_FAN_CONTROL_REAL_RPM_OFST 4 3182 3183 /* MC_CMD_AOE_IN_FAN_FAILURES msgrequest */ 3184 #define MC_CMD_AOE_IN_FAN_FAILURES_LEN 4 3185 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3186 3187 /* MC_CMD_AOE_IN_MAC_STATS msgrequest */ 3188 #define MC_CMD_AOE_IN_MAC_STATS_LEN 24 3189 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3190 /* AOE port */ 3191 #define MC_CMD_AOE_IN_MAC_STATS_PORT_OFST 4 3192 /* Host memory address for statistics */ 3193 #define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_OFST 8 3194 #define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_LEN 8 3195 #define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_LO_OFST 8 3196 #define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_HI_OFST 12 3197 #define MC_CMD_AOE_IN_MAC_STATS_CMD_OFST 16 3198 #define MC_CMD_AOE_IN_MAC_STATS_DMA_LBN 0 3199 #define MC_CMD_AOE_IN_MAC_STATS_DMA_WIDTH 1 3200 #define MC_CMD_AOE_IN_MAC_STATS_CLEAR_LBN 1 3201 #define MC_CMD_AOE_IN_MAC_STATS_CLEAR_WIDTH 1 3202 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CHANGE_LBN 2 3203 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CHANGE_WIDTH 1 3204 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_ENABLE_LBN 3 3205 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_ENABLE_WIDTH 1 3206 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CLEAR_LBN 4 3207 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CLEAR_WIDTH 1 3208 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_NOEVENT_LBN 5 3209 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_NOEVENT_WIDTH 1 3210 #define MC_CMD_AOE_IN_MAC_STATS_PERIOD_MS_LBN 16 3211 #define MC_CMD_AOE_IN_MAC_STATS_PERIOD_MS_WIDTH 16 3212 /* Length of DMA data (optional) */ 3213 #define MC_CMD_AOE_IN_MAC_STATS_DMA_LEN_OFST 20 3214 3215 /* MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO msgrequest */ 3216 #define MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_LEN 12 3217 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3218 /* AOE port */ 3219 #define MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_PORT_OFST 4 3220 #define MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_PAGE_OFST 8 3221 3222 /* MC_CMD_AOE_IN_JTAG_WRITE msgrequest */ 3223 #define MC_CMD_AOE_IN_JTAG_WRITE_LENMIN 12 3224 #define MC_CMD_AOE_IN_JTAG_WRITE_LENMAX 252 3225 #define MC_CMD_AOE_IN_JTAG_WRITE_LEN(num) (8+4*(num)) 3226 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3227 #define MC_CMD_AOE_IN_JTAG_WRITE_DATALEN_OFST 4 3228 #define MC_CMD_AOE_IN_JTAG_WRITE_DATA_OFST 8 3229 #define MC_CMD_AOE_IN_JTAG_WRITE_DATA_LEN 4 3230 #define MC_CMD_AOE_IN_JTAG_WRITE_DATA_MINNUM 1 3231 #define MC_CMD_AOE_IN_JTAG_WRITE_DATA_MAXNUM 61 3232 3233 /* MC_CMD_AOE_IN_FPGA_ACCESS msgrequest */ 3234 #define MC_CMD_AOE_IN_FPGA_ACCESS_LEN 8 3235 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3236 /* Enable or disable access */ 3237 #define MC_CMD_AOE_IN_FPGA_ACCESS_OP_OFST 4 3238 /* enum: Enable access */ 3239 #define MC_CMD_AOE_IN_FPGA_ACCESS_ENABLE 0x1 3240 /* enum: Disable access */ 3241 #define MC_CMD_AOE_IN_FPGA_ACCESS_DISABLE 0x2 3242 3243 /* MC_CMD_AOE_IN_SET_MTU_OFFSET msgrequest */ 3244 #define MC_CMD_AOE_IN_SET_MTU_OFFSET_LEN 12 3245 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3246 /* AOE port - when not ALL_EXTERNAL or ALL_INTERNAL specifies port number */ 3247 #define MC_CMD_AOE_IN_SET_MTU_OFFSET_PORT_OFST 4 3248 /* enum: Apply to all external ports */ 3249 #define MC_CMD_AOE_IN_SET_MTU_OFFSET_ALL_EXTERNAL 0x8000 3250 /* enum: Apply to all internal ports */ 3251 #define MC_CMD_AOE_IN_SET_MTU_OFFSET_ALL_INTERNAL 0x4000 3252 /* The MTU offset to be applied to the external ports */ 3253 #define MC_CMD_AOE_IN_SET_MTU_OFFSET_OFFSET_OFST 8 3254 3255 /* MC_CMD_AOE_IN_LINK_STATE msgrequest */ 3256 #define MC_CMD_AOE_IN_LINK_STATE_LEN 8 3257 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3258 #define MC_CMD_AOE_IN_LINK_STATE_MODE_OFST 4 3259 #define MC_CMD_AOE_IN_LINK_STATE_CONFIG_MODE_LBN 0 3260 #define MC_CMD_AOE_IN_LINK_STATE_CONFIG_MODE_WIDTH 8 3261 /* enum: AOE and associated external port */ 3262 #define MC_CMD_AOE_IN_LINK_STATE_SIMPLE_SEPARATE 0x0 3263 /* enum: AOE and OR of all external ports */ 3264 #define MC_CMD_AOE_IN_LINK_STATE_SIMPLE_COMBINED 0x1 3265 /* enum: Individual ports */ 3266 #define MC_CMD_AOE_IN_LINK_STATE_DIAGNOSTIC 0x2 3267 /* enum: Configure link state mode on given AOE port */ 3268 #define MC_CMD_AOE_IN_LINK_STATE_CUSTOM 0x3 3269 #define MC_CMD_AOE_IN_LINK_STATE_OPERATION_LBN 8 3270 #define MC_CMD_AOE_IN_LINK_STATE_OPERATION_WIDTH 8 3271 /* enum: No-op */ 3272 #define MC_CMD_AOE_IN_LINK_STATE_OP_NONE 0x0 3273 /* enum: logical OR of all SFP ports link status */ 3274 #define MC_CMD_AOE_IN_LINK_STATE_OP_OR 0x1 3275 /* enum: logical AND of all SFP ports link status */ 3276 #define MC_CMD_AOE_IN_LINK_STATE_OP_AND 0x2 3277 #define MC_CMD_AOE_IN_LINK_STATE_SFP_MASK_LBN 16 3278 #define MC_CMD_AOE_IN_LINK_STATE_SFP_MASK_WIDTH 16 3279 3280 /* MC_CMD_AOE_IN_SIENA_STATS msgrequest */ 3281 #define MC_CMD_AOE_IN_SIENA_STATS_LEN 8 3282 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3283 /* How MAC statistics are reported */ 3284 #define MC_CMD_AOE_IN_SIENA_STATS_MODE_OFST 4 3285 /* enum: Statistics from Siena (default) */ 3286 #define MC_CMD_AOE_IN_SIENA_STATS_STATS_SIENA 0x0 3287 /* enum: Statistics from AOE external ports */ 3288 #define MC_CMD_AOE_IN_SIENA_STATS_STATS_AOE 0x1 3289 3290 /* MC_CMD_AOE_IN_ASIC_STATS msgrequest */ 3291 #define MC_CMD_AOE_IN_ASIC_STATS_LEN 8 3292 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3293 /* How MAC statistics are reported */ 3294 #define MC_CMD_AOE_IN_ASIC_STATS_MODE_OFST 4 3295 /* enum: Statistics from the ASIC (default) */ 3296 #define MC_CMD_AOE_IN_ASIC_STATS_STATS_ASIC 0x0 3297 /* enum: Statistics from AOE external ports */ 3298 #define MC_CMD_AOE_IN_ASIC_STATS_STATS_AOE 0x1 3299 3300 /* MC_CMD_AOE_IN_DDR msgrequest */ 3301 #define MC_CMD_AOE_IN_DDR_LEN 12 3302 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3303 #define MC_CMD_AOE_IN_DDR_BANK_OFST 4 3304 /* Enum values, see field(s): */ 3305 /* MC_CMD_FC/MC_CMD_FC_IN_DDR/MC_CMD_FC_IN_DDR_BANK */ 3306 /* Page index of SPD data */ 3307 #define MC_CMD_AOE_IN_DDR_SPD_PAGE_ID_OFST 8 3308 3309 /* MC_CMD_AOE_IN_FC msgrequest */ 3310 #define MC_CMD_AOE_IN_FC_LEN 4 3311 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3312 3313 /* MC_CMD_AOE_IN_DDR_ECC_STATUS msgrequest */ 3314 #define MC_CMD_AOE_IN_DDR_ECC_STATUS_LEN 8 3315 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3316 #define MC_CMD_AOE_IN_DDR_ECC_STATUS_BANK_OFST 4 3317 /* Enum values, see field(s): */ 3318 /* MC_CMD_FC/MC_CMD_FC_IN_DDR/MC_CMD_FC_IN_DDR_BANK */ 3319 3320 /* MC_CMD_AOE_IN_MC_SPI_MASTER msgrequest */ 3321 #define MC_CMD_AOE_IN_MC_SPI_MASTER_LEN 8 3322 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3323 /* Basic commands for MC SPI Master emulation. */ 3324 #define MC_CMD_AOE_IN_MC_SPI_MASTER_OP_OFST 4 3325 /* enum: MC SPI read */ 3326 #define MC_CMD_AOE_IN_MC_SPI_MASTER_READ 0x0 3327 /* enum: MC SPI write */ 3328 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE 0x1 3329 3330 /* MC_CMD_AOE_IN_MC_SPI_MASTER_READ msgrequest */ 3331 #define MC_CMD_AOE_IN_MC_SPI_MASTER_READ_LEN 12 3332 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3333 #define MC_CMD_AOE_IN_MC_SPI_MASTER_READ_OP_OFST 4 3334 #define MC_CMD_AOE_IN_MC_SPI_MASTER_READ_OFFSET_OFST 8 3335 3336 /* MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE msgrequest */ 3337 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_LEN 16 3338 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3339 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_OP_OFST 4 3340 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_OFFSET_OFST 8 3341 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_DATA_OFST 12 3342 3343 /* MC_CMD_AOE_IN_FC_BOOT msgrequest */ 3344 #define MC_CMD_AOE_IN_FC_BOOT_LEN 8 3345 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3346 /* FC boot control flags */ 3347 #define MC_CMD_AOE_IN_FC_BOOT_CONTROL_OFST 4 3348 #define MC_CMD_AOE_IN_FC_BOOT_CONTROL_BOOT_ENABLE_LBN 0 3349 #define MC_CMD_AOE_IN_FC_BOOT_CONTROL_BOOT_ENABLE_WIDTH 1 3350 3351 /* MC_CMD_AOE_OUT_INFO msgresponse */ 3352 #define MC_CMD_AOE_OUT_INFO_LEN 44 3353 /* JTAG IDCODE of CPLD */ 3354 #define MC_CMD_AOE_OUT_INFO_CPLD_IDCODE_OFST 0 3355 /* Version of CPLD */ 3356 #define MC_CMD_AOE_OUT_INFO_CPLD_VERSION_OFST 4 3357 /* JTAG IDCODE of FPGA */ 3358 #define MC_CMD_AOE_OUT_INFO_FPGA_IDCODE_OFST 8 3359 /* JTAG USERCODE of FPGA */ 3360 #define MC_CMD_AOE_OUT_INFO_FPGA_VERSION_OFST 12 3361 /* FPGA type - read from CPLD straps */ 3362 #define MC_CMD_AOE_OUT_INFO_FPGA_TYPE_OFST 16 3363 #define MC_CMD_AOE_OUT_INFO_FPGA_TYPE_A5_C2 0x1 /* enum */ 3364 #define MC_CMD_AOE_OUT_INFO_FPGA_TYPE_A7_C2 0x2 /* enum */ 3365 /* FPGA state (debug) */ 3366 #define MC_CMD_AOE_OUT_INFO_FPGA_STATE_OFST 20 3367 /* FPGA image - partition from which loaded */ 3368 #define MC_CMD_AOE_OUT_INFO_FPGA_IMAGE_OFST 24 3369 /* FC state */ 3370 #define MC_CMD_AOE_OUT_INFO_FC_STATE_OFST 28 3371 /* enum: Set if watchdog working */ 3372 #define MC_CMD_AOE_OUT_INFO_WATCHDOG 0x1 3373 /* enum: Set if MC-FC communications working */ 3374 #define MC_CMD_AOE_OUT_INFO_COMMS 0x2 3375 /* Random pieces of information */ 3376 #define MC_CMD_AOE_OUT_INFO_FLAGS_OFST 32 3377 /* enum: Power to FPGA supplied by PEG connector, not PCIe bus */ 3378 #define MC_CMD_AOE_OUT_INFO_PEG_POWER 0x1 3379 /* enum: CPLD apparently good */ 3380 #define MC_CMD_AOE_OUT_INFO_CPLD_GOOD 0x2 3381 /* enum: FPGA working normally */ 3382 #define MC_CMD_AOE_OUT_INFO_FPGA_GOOD 0x4 3383 /* enum: FPGA is powered */ 3384 #define MC_CMD_AOE_OUT_INFO_FPGA_POWER 0x8 3385 /* enum: Board has incompatible SODIMMs fitted */ 3386 #define MC_CMD_AOE_OUT_INFO_BAD_SODIMM 0x10 3387 /* enum: Board has ByteBlaster connected */ 3388 #define MC_CMD_AOE_OUT_INFO_HAS_BYTEBLASTER 0x20 3389 /* enum: FPGA Boot flash has an invalid header. */ 3390 #define MC_CMD_AOE_OUT_INFO_FPGA_BAD_BOOT_HDR 0x40 3391 /* enum: FPGA Application flash is accessible. */ 3392 #define MC_CMD_AOE_OUT_INFO_FPGA_APP_FLASH_GOOD 0x80 3393 /* Revision of Modena and Sorrento boards. Sorrento can be R1_2 or R1_3. */ 3394 #define MC_CMD_AOE_OUT_INFO_BOARD_REVISION_OFST 36 3395 #define MC_CMD_AOE_OUT_INFO_UNKNOWN 0x0 /* enum */ 3396 #define MC_CMD_AOE_OUT_INFO_R1_0 0x10 /* enum */ 3397 #define MC_CMD_AOE_OUT_INFO_R1_1 0x11 /* enum */ 3398 #define MC_CMD_AOE_OUT_INFO_R1_2 0x12 /* enum */ 3399 #define MC_CMD_AOE_OUT_INFO_R1_3 0x13 /* enum */ 3400 /* Result of FC booting - not valid while a ByteBlaster is connected. */ 3401 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_RESULT_OFST 40 3402 /* enum: No error */ 3403 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_NO_ERROR 0x0 3404 /* enum: Bad address set in CPLD */ 3405 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_ADDRESS 0x1 3406 /* enum: Bad header */ 3407 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_MAGIC 0x2 3408 /* enum: Bad text section details */ 3409 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_TEXT 0x3 3410 /* enum: Bad checksum */ 3411 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_CHECKSUM 0x4 3412 /* enum: Bad BSP */ 3413 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_BSP 0x5 3414 /* enum: Flash mode is invalid */ 3415 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_INVALID_FLASH_MODE 0x6 3416 /* enum: FC application loaded and execution attempted */ 3417 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_APP_EXECUTE 0x80 3418 /* enum: FC application Started */ 3419 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_APP_STARTED 0x81 3420 /* enum: No bootrom in FPGA */ 3421 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_NO_BOOTROM 0xff 3422 3423 /* MC_CMD_AOE_OUT_CURRENTS msgresponse */ 3424 #define MC_CMD_AOE_OUT_CURRENTS_LEN 68 3425 /* Set of currents and voltages (mA or mV as appropriate) */ 3426 #define MC_CMD_AOE_OUT_CURRENTS_VALUES_OFST 0 3427 #define MC_CMD_AOE_OUT_CURRENTS_VALUES_LEN 4 3428 #define MC_CMD_AOE_OUT_CURRENTS_VALUES_NUM 17 3429 #define MC_CMD_AOE_OUT_CURRENTS_I_2V5 0x0 /* enum */ 3430 #define MC_CMD_AOE_OUT_CURRENTS_I_1V8 0x1 /* enum */ 3431 #define MC_CMD_AOE_OUT_CURRENTS_I_GXB 0x2 /* enum */ 3432 #define MC_CMD_AOE_OUT_CURRENTS_I_PGM 0x3 /* enum */ 3433 #define MC_CMD_AOE_OUT_CURRENTS_I_XCVR 0x4 /* enum */ 3434 #define MC_CMD_AOE_OUT_CURRENTS_I_1V5 0x5 /* enum */ 3435 #define MC_CMD_AOE_OUT_CURRENTS_V_3V3 0x6 /* enum */ 3436 #define MC_CMD_AOE_OUT_CURRENTS_V_1V5 0x7 /* enum */ 3437 #define MC_CMD_AOE_OUT_CURRENTS_I_IN 0x8 /* enum */ 3438 #define MC_CMD_AOE_OUT_CURRENTS_I_OUT 0x9 /* enum */ 3439 #define MC_CMD_AOE_OUT_CURRENTS_V_IN 0xa /* enum */ 3440 #define MC_CMD_AOE_OUT_CURRENTS_I_OUT_DDR1 0xb /* enum */ 3441 #define MC_CMD_AOE_OUT_CURRENTS_V_OUT_DDR1 0xc /* enum */ 3442 #define MC_CMD_AOE_OUT_CURRENTS_I_OUT_DDR2 0xd /* enum */ 3443 #define MC_CMD_AOE_OUT_CURRENTS_V_OUT_DDR2 0xe /* enum */ 3444 #define MC_CMD_AOE_OUT_CURRENTS_I_OUT_DDR3 0xf /* enum */ 3445 #define MC_CMD_AOE_OUT_CURRENTS_V_OUT_DDR3 0x10 /* enum */ 3446 3447 /* MC_CMD_AOE_OUT_TEMPERATURES msgresponse */ 3448 #define MC_CMD_AOE_OUT_TEMPERATURES_LEN 40 3449 /* Set of temperatures */ 3450 #define MC_CMD_AOE_OUT_TEMPERATURES_VALUES_OFST 0 3451 #define MC_CMD_AOE_OUT_TEMPERATURES_VALUES_LEN 4 3452 #define MC_CMD_AOE_OUT_TEMPERATURES_VALUES_NUM 10 3453 /* enum: The first set of enum values are for Modena code. */ 3454 #define MC_CMD_AOE_OUT_TEMPERATURES_MAIN_0 0x0 3455 #define MC_CMD_AOE_OUT_TEMPERATURES_MAIN_1 0x1 /* enum */ 3456 #define MC_CMD_AOE_OUT_TEMPERATURES_IND_0 0x2 /* enum */ 3457 #define MC_CMD_AOE_OUT_TEMPERATURES_IND_1 0x3 /* enum */ 3458 #define MC_CMD_AOE_OUT_TEMPERATURES_VCCIO1 0x4 /* enum */ 3459 #define MC_CMD_AOE_OUT_TEMPERATURES_VCCIO2 0x5 /* enum */ 3460 #define MC_CMD_AOE_OUT_TEMPERATURES_VCCIO3 0x6 /* enum */ 3461 #define MC_CMD_AOE_OUT_TEMPERATURES_PSU 0x7 /* enum */ 3462 #define MC_CMD_AOE_OUT_TEMPERATURES_FPGA 0x8 /* enum */ 3463 #define MC_CMD_AOE_OUT_TEMPERATURES_SIENA 0x9 /* enum */ 3464 /* enum: The second set of enum values are for Sorrento code. */ 3465 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_MAIN_0 0x0 3466 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_MAIN_1 0x1 /* enum */ 3467 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_IND_0 0x2 /* enum */ 3468 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_IND_1 0x3 /* enum */ 3469 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_SODIMM_0 0x4 /* enum */ 3470 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_SODIMM_1 0x5 /* enum */ 3471 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_FPGA 0x6 /* enum */ 3472 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_PHY0 0x7 /* enum */ 3473 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_PHY1 0x8 /* enum */ 3474 3475 /* MC_CMD_AOE_OUT_CPLD_READ msgresponse */ 3476 #define MC_CMD_AOE_OUT_CPLD_READ_LEN 4 3477 /* The value read from the CPLD */ 3478 #define MC_CMD_AOE_OUT_CPLD_READ_VALUE_OFST 0 3479 3480 /* MC_CMD_AOE_OUT_FAN_FAILURES msgresponse */ 3481 #define MC_CMD_AOE_OUT_FAN_FAILURES_LENMIN 4 3482 #define MC_CMD_AOE_OUT_FAN_FAILURES_LENMAX 252 3483 #define MC_CMD_AOE_OUT_FAN_FAILURES_LEN(num) (0+4*(num)) 3484 /* Failure counts for each fan */ 3485 #define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_OFST 0 3486 #define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_LEN 4 3487 #define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_MINNUM 1 3488 #define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_MAXNUM 63 3489 3490 /* MC_CMD_AOE_OUT_CPLD_REPROGRAM msgresponse */ 3491 #define MC_CMD_AOE_OUT_CPLD_REPROGRAM_LEN 4 3492 /* Results of status command (only) */ 3493 #define MC_CMD_AOE_OUT_CPLD_REPROGRAM_STATUS_OFST 0 3494 3495 /* MC_CMD_AOE_OUT_POWER_OFF msgresponse */ 3496 #define MC_CMD_AOE_OUT_POWER_OFF_LEN 0 3497 3498 /* MC_CMD_AOE_OUT_POWER_ON msgresponse */ 3499 #define MC_CMD_AOE_OUT_POWER_ON_LEN 0 3500 3501 /* MC_CMD_AOE_OUT_LOAD msgresponse */ 3502 #define MC_CMD_AOE_OUT_LOAD_LEN 0 3503 3504 /* MC_CMD_AOE_OUT_MAC_STATS_DMA msgresponse */ 3505 #define MC_CMD_AOE_OUT_MAC_STATS_DMA_LEN 0 3506 3507 /* MC_CMD_AOE_OUT_MAC_STATS_NO_DMA msgresponse: See MC_CMD_MAC_STATS_OUT_NO_DMA 3508 * for details 3509 */ 3510 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_LEN (((MC_CMD_MAC_NSTATS*64))>>3) 3511 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_OFST 0 3512 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_LEN 8 3513 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_LO_OFST 0 3514 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_HI_OFST 4 3515 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS 3516 3517 /* MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO msgresponse */ 3518 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LENMIN 5 3519 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LENMAX 252 3520 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LEN(num) (4+1*(num)) 3521 /* in bytes */ 3522 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATALEN_OFST 0 3523 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_OFST 4 3524 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_LEN 1 3525 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_MINNUM 1 3526 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_MAXNUM 248 3527 3528 /* MC_CMD_AOE_OUT_JTAG_WRITE msgresponse */ 3529 #define MC_CMD_AOE_OUT_JTAG_WRITE_LENMIN 12 3530 #define MC_CMD_AOE_OUT_JTAG_WRITE_LENMAX 252 3531 #define MC_CMD_AOE_OUT_JTAG_WRITE_LEN(num) (8+4*(num)) 3532 /* Used to align the in and out data blocks so the MC can re-use the cmd */ 3533 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATALEN_OFST 0 3534 /* out bytes */ 3535 #define MC_CMD_AOE_OUT_JTAG_WRITE_PAD_OFST 4 3536 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_OFST 8 3537 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_LEN 4 3538 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_MINNUM 1 3539 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_MAXNUM 61 3540 3541 /* MC_CMD_AOE_OUT_FPGA_ACCESS msgresponse */ 3542 #define MC_CMD_AOE_OUT_FPGA_ACCESS_LEN 0 3543 3544 /* MC_CMD_AOE_OUT_DDR msgresponse */ 3545 #define MC_CMD_AOE_OUT_DDR_LENMIN 17 3546 #define MC_CMD_AOE_OUT_DDR_LENMAX 252 3547 #define MC_CMD_AOE_OUT_DDR_LEN(num) (16+1*(num)) 3548 /* Information on the module. */ 3549 #define MC_CMD_AOE_OUT_DDR_FLAGS_OFST 0 3550 #define MC_CMD_AOE_OUT_DDR_PRESENT_LBN 0 3551 #define MC_CMD_AOE_OUT_DDR_PRESENT_WIDTH 1 3552 #define MC_CMD_AOE_OUT_DDR_POWERED_LBN 1 3553 #define MC_CMD_AOE_OUT_DDR_POWERED_WIDTH 1 3554 #define MC_CMD_AOE_OUT_DDR_OPERATIONAL_LBN 2 3555 #define MC_CMD_AOE_OUT_DDR_OPERATIONAL_WIDTH 1 3556 #define MC_CMD_AOE_OUT_DDR_NOT_REACHABLE_LBN 3 3557 #define MC_CMD_AOE_OUT_DDR_NOT_REACHABLE_WIDTH 1 3558 /* Memory size, in MB. */ 3559 #define MC_CMD_AOE_OUT_DDR_CAPACITY_OFST 4 3560 /* The memory type, as reported from SPD information */ 3561 #define MC_CMD_AOE_OUT_DDR_TYPE_OFST 8 3562 /* Nominal voltage of the module (as applied) */ 3563 #define MC_CMD_AOE_OUT_DDR_VOLTAGE_OFST 12 3564 /* SPD data read from the module */ 3565 #define MC_CMD_AOE_OUT_DDR_SPD_OFST 16 3566 #define MC_CMD_AOE_OUT_DDR_SPD_LEN 1 3567 #define MC_CMD_AOE_OUT_DDR_SPD_MINNUM 1 3568 #define MC_CMD_AOE_OUT_DDR_SPD_MAXNUM 236 3569 3570 /* MC_CMD_AOE_OUT_SET_MTU_OFFSET msgresponse */ 3571 #define MC_CMD_AOE_OUT_SET_MTU_OFFSET_LEN 0 3572 3573 /* MC_CMD_AOE_OUT_LINK_STATE msgresponse */ 3574 #define MC_CMD_AOE_OUT_LINK_STATE_LEN 0 3575 3576 /* MC_CMD_AOE_OUT_SIENA_STATS msgresponse */ 3577 #define MC_CMD_AOE_OUT_SIENA_STATS_LEN 0 3578 3579 /* MC_CMD_AOE_OUT_ASIC_STATS msgresponse */ 3580 #define MC_CMD_AOE_OUT_ASIC_STATS_LEN 0 3581 3582 /* MC_CMD_AOE_OUT_FC msgresponse */ 3583 #define MC_CMD_AOE_OUT_FC_LEN 0 3584 3585 /* MC_CMD_AOE_OUT_DDR_ECC_STATUS msgresponse */ 3586 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_LEN 8 3587 /* Flags describing status info on the module. */ 3588 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_FLAGS_OFST 0 3589 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_VALID_LBN 0 3590 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_VALID_WIDTH 1 3591 /* DDR ECC status on the module. */ 3592 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_STATUS_OFST 4 3593 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_LBN 0 3594 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_WIDTH 1 3595 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_LBN 1 3596 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_WIDTH 1 3597 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_LBN 2 3598 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_WIDTH 1 3599 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_COUNT_LBN 8 3600 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_COUNT_WIDTH 8 3601 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_COUNT_LBN 16 3602 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_COUNT_WIDTH 8 3603 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_COUNT_LBN 24 3604 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_COUNT_WIDTH 8 3605 3606 /* MC_CMD_AOE_OUT_MC_SPI_MASTER_READ msgresponse */ 3607 #define MC_CMD_AOE_OUT_MC_SPI_MASTER_READ_LEN 4 3608 #define MC_CMD_AOE_OUT_MC_SPI_MASTER_READ_DATA_OFST 0 3609 3610 /* MC_CMD_AOE_OUT_MC_SPI_MASTER_WRITE msgresponse */ 3611 #define MC_CMD_AOE_OUT_MC_SPI_MASTER_WRITE_LEN 0 3612 3613 /* MC_CMD_AOE_OUT_MC_SPI_MASTER msgresponse */ 3614 #define MC_CMD_AOE_OUT_MC_SPI_MASTER_LEN 0 3615 3616 /* MC_CMD_AOE_OUT_FC_BOOT msgresponse */ 3617 #define MC_CMD_AOE_OUT_FC_BOOT_LEN 0 3618 3619 3620 /***********************************/ 3621 /* MC_CMD_PTP 3622 * Perform PTP operation 3623 */ 3624 #define MC_CMD_PTP 0xb 3625 #undef MC_CMD_0xb_PRIVILEGE_CTG 3626 3627 #define MC_CMD_0xb_PRIVILEGE_CTG SRIOV_CTG_GENERAL 3628 3629 /* MC_CMD_PTP_IN msgrequest */ 3630 #define MC_CMD_PTP_IN_LEN 1 3631 /* PTP operation code */ 3632 #define MC_CMD_PTP_IN_OP_OFST 0 3633 #define MC_CMD_PTP_IN_OP_LEN 1 3634 /* enum: Enable PTP packet timestamping operation. */ 3635 #define MC_CMD_PTP_OP_ENABLE 0x1 3636 /* enum: Disable PTP packet timestamping operation. */ 3637 #define MC_CMD_PTP_OP_DISABLE 0x2 3638 /* enum: Send a PTP packet. */ 3639 #define MC_CMD_PTP_OP_TRANSMIT 0x3 3640 /* enum: Read the current NIC time. */ 3641 #define MC_CMD_PTP_OP_READ_NIC_TIME 0x4 3642 /* enum: Get the current PTP status. */ 3643 #define MC_CMD_PTP_OP_STATUS 0x5 3644 /* enum: Adjust the PTP NIC's time. */ 3645 #define MC_CMD_PTP_OP_ADJUST 0x6 3646 /* enum: Synchronize host and NIC time. */ 3647 #define MC_CMD_PTP_OP_SYNCHRONIZE 0x7 3648 /* enum: Basic manufacturing tests. */ 3649 #define MC_CMD_PTP_OP_MANFTEST_BASIC 0x8 3650 /* enum: Packet based manufacturing tests. */ 3651 #define MC_CMD_PTP_OP_MANFTEST_PACKET 0x9 3652 /* enum: Reset some of the PTP related statistics */ 3653 #define MC_CMD_PTP_OP_RESET_STATS 0xa 3654 /* enum: Debug operations to MC. */ 3655 #define MC_CMD_PTP_OP_DEBUG 0xb 3656 /* enum: Read an FPGA register */ 3657 #define MC_CMD_PTP_OP_FPGAREAD 0xc 3658 /* enum: Write an FPGA register */ 3659 #define MC_CMD_PTP_OP_FPGAWRITE 0xd 3660 /* enum: Apply an offset to the NIC clock */ 3661 #define MC_CMD_PTP_OP_CLOCK_OFFSET_ADJUST 0xe 3662 /* enum: Change Apply an offset to the NIC clock */ 3663 #define MC_CMD_PTP_OP_CLOCK_FREQ_ADJUST 0xf 3664 /* enum: Set the MC packet filter VLAN tags for received PTP packets */ 3665 #define MC_CMD_PTP_OP_RX_SET_VLAN_FILTER 0x10 3666 /* enum: Set the MC packet filter UUID for received PTP packets */ 3667 #define MC_CMD_PTP_OP_RX_SET_UUID_FILTER 0x11 3668 /* enum: Set the MC packet filter Domain for received PTP packets */ 3669 #define MC_CMD_PTP_OP_RX_SET_DOMAIN_FILTER 0x12 3670 /* enum: Set the clock source */ 3671 #define MC_CMD_PTP_OP_SET_CLK_SRC 0x13 3672 /* enum: Reset value of Timer Reg. */ 3673 #define MC_CMD_PTP_OP_RST_CLK 0x14 3674 /* enum: Enable the forwarding of PPS events to the host */ 3675 #define MC_CMD_PTP_OP_PPS_ENABLE 0x15 3676 /* enum: Get the time format used by this NIC for PTP operations */ 3677 #define MC_CMD_PTP_OP_GET_TIME_FORMAT 0x16 3678 /* enum: Get the clock attributes. NOTE- extended version of 3679 * MC_CMD_PTP_OP_GET_TIME_FORMAT 3680 */ 3681 #define MC_CMD_PTP_OP_GET_ATTRIBUTES 0x16 3682 /* enum: Get corrections that should be applied to the various different 3683 * timestamps 3684 */ 3685 #define MC_CMD_PTP_OP_GET_TIMESTAMP_CORRECTIONS 0x17 3686 /* enum: Subscribe to receive periodic time events indicating the current NIC 3687 * time 3688 */ 3689 #define MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE 0x18 3690 /* enum: Unsubscribe to stop receiving time events */ 3691 #define MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE 0x19 3692 /* enum: PPS based manfacturing tests. Requires PPS output to be looped to PPS 3693 * input on the same NIC. 3694 */ 3695 #define MC_CMD_PTP_OP_MANFTEST_PPS 0x1a 3696 /* enum: Set the PTP sync status. Status is used by firmware to report to event 3697 * subscribers. 3698 */ 3699 #define MC_CMD_PTP_OP_SET_SYNC_STATUS 0x1b 3700 /* enum: Above this for future use. */ 3701 #define MC_CMD_PTP_OP_MAX 0x1c 3702 3703 /* MC_CMD_PTP_IN_ENABLE msgrequest */ 3704 #define MC_CMD_PTP_IN_ENABLE_LEN 16 3705 #define MC_CMD_PTP_IN_CMD_OFST 0 3706 #define MC_CMD_PTP_IN_PERIPH_ID_OFST 4 3707 /* Event queue for PTP events */ 3708 #define MC_CMD_PTP_IN_ENABLE_QUEUE_OFST 8 3709 /* PTP timestamping mode */ 3710 #define MC_CMD_PTP_IN_ENABLE_MODE_OFST 12 3711 /* enum: PTP, version 1 */ 3712 #define MC_CMD_PTP_MODE_V1 0x0 3713 /* enum: PTP, version 1, with VLAN headers - deprecated */ 3714 #define MC_CMD_PTP_MODE_V1_VLAN 0x1 3715 /* enum: PTP, version 2 */ 3716 #define MC_CMD_PTP_MODE_V2 0x2 3717 /* enum: PTP, version 2, with VLAN headers - deprecated */ 3718 #define MC_CMD_PTP_MODE_V2_VLAN 0x3 3719 /* enum: PTP, version 2, with improved UUID filtering */ 3720 #define MC_CMD_PTP_MODE_V2_ENHANCED 0x4 3721 /* enum: FCoE (seconds and microseconds) */ 3722 #define MC_CMD_PTP_MODE_FCOE 0x5 3723 3724 /* MC_CMD_PTP_IN_DISABLE msgrequest */ 3725 #define MC_CMD_PTP_IN_DISABLE_LEN 8 3726 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3727 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3728 3729 /* MC_CMD_PTP_IN_TRANSMIT msgrequest */ 3730 #define MC_CMD_PTP_IN_TRANSMIT_LENMIN 13 3731 #define MC_CMD_PTP_IN_TRANSMIT_LENMAX 252 3732 #define MC_CMD_PTP_IN_TRANSMIT_LEN(num) (12+1*(num)) 3733 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3734 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3735 /* Transmit packet length */ 3736 #define MC_CMD_PTP_IN_TRANSMIT_LENGTH_OFST 8 3737 /* Transmit packet data */ 3738 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_OFST 12 3739 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_LEN 1 3740 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_MINNUM 1 3741 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_MAXNUM 240 3742 3743 /* MC_CMD_PTP_IN_READ_NIC_TIME msgrequest */ 3744 #define MC_CMD_PTP_IN_READ_NIC_TIME_LEN 8 3745 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3746 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3747 3748 /* MC_CMD_PTP_IN_STATUS msgrequest */ 3749 #define MC_CMD_PTP_IN_STATUS_LEN 8 3750 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3751 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3752 3753 /* MC_CMD_PTP_IN_ADJUST msgrequest */ 3754 #define MC_CMD_PTP_IN_ADJUST_LEN 24 3755 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3756 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3757 /* Frequency adjustment 40 bit fixed point ns */ 3758 #define MC_CMD_PTP_IN_ADJUST_FREQ_OFST 8 3759 #define MC_CMD_PTP_IN_ADJUST_FREQ_LEN 8 3760 #define MC_CMD_PTP_IN_ADJUST_FREQ_LO_OFST 8 3761 #define MC_CMD_PTP_IN_ADJUST_FREQ_HI_OFST 12 3762 /* enum: Number of fractional bits in frequency adjustment */ 3763 #define MC_CMD_PTP_IN_ADJUST_BITS 0x28 3764 /* Time adjustment in seconds */ 3765 #define MC_CMD_PTP_IN_ADJUST_SECONDS_OFST 16 3766 /* Time adjustment major value */ 3767 #define MC_CMD_PTP_IN_ADJUST_MAJOR_OFST 16 3768 /* Time adjustment in nanoseconds */ 3769 #define MC_CMD_PTP_IN_ADJUST_NANOSECONDS_OFST 20 3770 /* Time adjustment minor value */ 3771 #define MC_CMD_PTP_IN_ADJUST_MINOR_OFST 20 3772 3773 /* MC_CMD_PTP_IN_SYNCHRONIZE msgrequest */ 3774 #define MC_CMD_PTP_IN_SYNCHRONIZE_LEN 20 3775 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3776 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3777 /* Number of time readings to capture */ 3778 #define MC_CMD_PTP_IN_SYNCHRONIZE_NUMTIMESETS_OFST 8 3779 /* Host address in which to write "synchronization started" indication (64 3780 * bits) 3781 */ 3782 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_OFST 12 3783 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LEN 8 3784 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LO_OFST 12 3785 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_HI_OFST 16 3786 3787 /* MC_CMD_PTP_IN_MANFTEST_BASIC msgrequest */ 3788 #define MC_CMD_PTP_IN_MANFTEST_BASIC_LEN 8 3789 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3790 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3791 3792 /* MC_CMD_PTP_IN_MANFTEST_PACKET msgrequest */ 3793 #define MC_CMD_PTP_IN_MANFTEST_PACKET_LEN 12 3794 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3795 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3796 /* Enable or disable packet testing */ 3797 #define MC_CMD_PTP_IN_MANFTEST_PACKET_TEST_ENABLE_OFST 8 3798 3799 /* MC_CMD_PTP_IN_RESET_STATS msgrequest */ 3800 #define MC_CMD_PTP_IN_RESET_STATS_LEN 8 3801 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3802 /* Reset PTP statistics */ 3803 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3804 3805 /* MC_CMD_PTP_IN_DEBUG msgrequest */ 3806 #define MC_CMD_PTP_IN_DEBUG_LEN 12 3807 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3808 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3809 /* Debug operations */ 3810 #define MC_CMD_PTP_IN_DEBUG_DEBUG_PARAM_OFST 8 3811 3812 /* MC_CMD_PTP_IN_FPGAREAD msgrequest */ 3813 #define MC_CMD_PTP_IN_FPGAREAD_LEN 16 3814 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3815 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3816 #define MC_CMD_PTP_IN_FPGAREAD_ADDR_OFST 8 3817 #define MC_CMD_PTP_IN_FPGAREAD_NUMBYTES_OFST 12 3818 3819 /* MC_CMD_PTP_IN_FPGAWRITE msgrequest */ 3820 #define MC_CMD_PTP_IN_FPGAWRITE_LENMIN 13 3821 #define MC_CMD_PTP_IN_FPGAWRITE_LENMAX 252 3822 #define MC_CMD_PTP_IN_FPGAWRITE_LEN(num) (12+1*(num)) 3823 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3824 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3825 #define MC_CMD_PTP_IN_FPGAWRITE_ADDR_OFST 8 3826 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_OFST 12 3827 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_LEN 1 3828 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MINNUM 1 3829 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MAXNUM 240 3830 3831 /* MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST msgrequest */ 3832 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_LEN 16 3833 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3834 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3835 /* Time adjustment in seconds */ 3836 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_SECONDS_OFST 8 3837 /* Time adjustment major value */ 3838 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MAJOR_OFST 8 3839 /* Time adjustment in nanoseconds */ 3840 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_NANOSECONDS_OFST 12 3841 /* Time adjustment minor value */ 3842 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MINOR_OFST 12 3843 3844 /* MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST msgrequest */ 3845 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_LEN 16 3846 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3847 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3848 /* Frequency adjustment 40 bit fixed point ns */ 3849 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_OFST 8 3850 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LEN 8 3851 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LO_OFST 8 3852 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_HI_OFST 12 3853 /* enum: Number of fractional bits in frequency adjustment */ 3854 /* MC_CMD_PTP_IN_ADJUST_BITS 0x28 */ 3855 3856 /* MC_CMD_PTP_IN_RX_SET_VLAN_FILTER msgrequest */ 3857 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_LEN 24 3858 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3859 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3860 /* Number of VLAN tags, 0 if not VLAN */ 3861 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_NUM_VLAN_TAGS_OFST 8 3862 /* Set of VLAN tags to filter against */ 3863 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_OFST 12 3864 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_LEN 4 3865 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_NUM 3 3866 3867 /* MC_CMD_PTP_IN_RX_SET_UUID_FILTER msgrequest */ 3868 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_LEN 20 3869 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3870 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3871 /* 1 to enable UUID filtering, 0 to disable */ 3872 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_ENABLE_OFST 8 3873 /* UUID to filter against */ 3874 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_OFST 12 3875 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LEN 8 3876 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LO_OFST 12 3877 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_HI_OFST 16 3878 3879 /* MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER msgrequest */ 3880 #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_LEN 16 3881 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3882 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3883 /* 1 to enable Domain filtering, 0 to disable */ 3884 #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_ENABLE_OFST 8 3885 /* Domain number to filter against */ 3886 #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_DOMAIN_OFST 12 3887 3888 /* MC_CMD_PTP_IN_SET_CLK_SRC msgrequest */ 3889 #define MC_CMD_PTP_IN_SET_CLK_SRC_LEN 12 3890 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3891 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3892 /* Set the clock source. */ 3893 #define MC_CMD_PTP_IN_SET_CLK_SRC_CLK_OFST 8 3894 /* enum: Internal. */ 3895 #define MC_CMD_PTP_CLK_SRC_INTERNAL 0x0 3896 /* enum: External. */ 3897 #define MC_CMD_PTP_CLK_SRC_EXTERNAL 0x1 3898 3899 /* MC_CMD_PTP_IN_RST_CLK msgrequest */ 3900 #define MC_CMD_PTP_IN_RST_CLK_LEN 8 3901 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3902 /* Reset value of Timer Reg. */ 3903 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3904 3905 /* MC_CMD_PTP_IN_PPS_ENABLE msgrequest */ 3906 #define MC_CMD_PTP_IN_PPS_ENABLE_LEN 12 3907 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3908 /* Enable or disable */ 3909 #define MC_CMD_PTP_IN_PPS_ENABLE_OP_OFST 4 3910 /* enum: Enable */ 3911 #define MC_CMD_PTP_ENABLE_PPS 0x0 3912 /* enum: Disable */ 3913 #define MC_CMD_PTP_DISABLE_PPS 0x1 3914 /* Queue id to send events back */ 3915 #define MC_CMD_PTP_IN_PPS_ENABLE_QUEUE_ID_OFST 8 3916 3917 /* MC_CMD_PTP_IN_GET_TIME_FORMAT msgrequest */ 3918 #define MC_CMD_PTP_IN_GET_TIME_FORMAT_LEN 8 3919 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3920 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3921 3922 /* MC_CMD_PTP_IN_GET_ATTRIBUTES msgrequest */ 3923 #define MC_CMD_PTP_IN_GET_ATTRIBUTES_LEN 8 3924 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3925 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3926 3927 /* MC_CMD_PTP_IN_GET_TIMESTAMP_CORRECTIONS msgrequest */ 3928 #define MC_CMD_PTP_IN_GET_TIMESTAMP_CORRECTIONS_LEN 8 3929 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3930 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3931 3932 /* MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE msgrequest */ 3933 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN 12 3934 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3935 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3936 /* Original field containing queue ID. Now extended to include flags. */ 3937 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_OFST 8 3938 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_LBN 0 3939 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_WIDTH 16 3940 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_REPORT_SYNC_STATUS_LBN 31 3941 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_REPORT_SYNC_STATUS_WIDTH 1 3942 3943 /* MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE msgrequest */ 3944 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN 16 3945 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3946 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3947 /* Unsubscribe options */ 3948 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL_OFST 8 3949 /* enum: Unsubscribe a single queue */ 3950 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE 0x0 3951 /* enum: Unsubscribe all queues */ 3952 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_ALL 0x1 3953 /* Event queue ID */ 3954 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE_OFST 12 3955 3956 /* MC_CMD_PTP_IN_MANFTEST_PPS msgrequest */ 3957 #define MC_CMD_PTP_IN_MANFTEST_PPS_LEN 12 3958 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3959 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3960 /* 1 to enable PPS test mode, 0 to disable and return result. */ 3961 #define MC_CMD_PTP_IN_MANFTEST_PPS_TEST_ENABLE_OFST 8 3962 3963 /* MC_CMD_PTP_IN_SET_SYNC_STATUS msgrequest */ 3964 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_LEN 24 3965 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3966 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3967 /* NIC - Host System Clock Synchronization status */ 3968 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_STATUS_OFST 8 3969 /* enum: Host System clock and NIC clock are not in sync */ 3970 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_NOT_IN_SYNC 0x0 3971 /* enum: Host System clock and NIC clock are synchronized */ 3972 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_IN_SYNC 0x1 3973 /* If synchronized, number of seconds until clocks should be considered to be 3974 * no longer in sync. 3975 */ 3976 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_TIMEOUT_OFST 12 3977 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED0_OFST 16 3978 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED1_OFST 20 3979 3980 /* MC_CMD_PTP_OUT msgresponse */ 3981 #define MC_CMD_PTP_OUT_LEN 0 3982 3983 /* MC_CMD_PTP_OUT_TRANSMIT msgresponse */ 3984 #define MC_CMD_PTP_OUT_TRANSMIT_LEN 8 3985 /* Value of seconds timestamp */ 3986 #define MC_CMD_PTP_OUT_TRANSMIT_SECONDS_OFST 0 3987 /* Timestamp major value */ 3988 #define MC_CMD_PTP_OUT_TRANSMIT_MAJOR_OFST 0 3989 /* Value of nanoseconds timestamp */ 3990 #define MC_CMD_PTP_OUT_TRANSMIT_NANOSECONDS_OFST 4 3991 /* Timestamp minor value */ 3992 #define MC_CMD_PTP_OUT_TRANSMIT_MINOR_OFST 4 3993 3994 /* MC_CMD_PTP_OUT_TIME_EVENT_SUBSCRIBE msgresponse */ 3995 #define MC_CMD_PTP_OUT_TIME_EVENT_SUBSCRIBE_LEN 0 3996 3997 /* MC_CMD_PTP_OUT_TIME_EVENT_UNSUBSCRIBE msgresponse */ 3998 #define MC_CMD_PTP_OUT_TIME_EVENT_UNSUBSCRIBE_LEN 0 3999 4000 /* MC_CMD_PTP_OUT_READ_NIC_TIME msgresponse */ 4001 #define MC_CMD_PTP_OUT_READ_NIC_TIME_LEN 8 4002 /* Value of seconds timestamp */ 4003 #define MC_CMD_PTP_OUT_READ_NIC_TIME_SECONDS_OFST 0 4004 /* Timestamp major value */ 4005 #define MC_CMD_PTP_OUT_READ_NIC_TIME_MAJOR_OFST 0 4006 /* Value of nanoseconds timestamp */ 4007 #define MC_CMD_PTP_OUT_READ_NIC_TIME_NANOSECONDS_OFST 4 4008 /* Timestamp minor value */ 4009 #define MC_CMD_PTP_OUT_READ_NIC_TIME_MINOR_OFST 4 4010 4011 /* MC_CMD_PTP_OUT_STATUS msgresponse */ 4012 #define MC_CMD_PTP_OUT_STATUS_LEN 64 4013 /* Frequency of NIC's hardware clock */ 4014 #define MC_CMD_PTP_OUT_STATUS_CLOCK_FREQ_OFST 0 4015 /* Number of packets transmitted and timestamped */ 4016 #define MC_CMD_PTP_OUT_STATUS_STATS_TX_OFST 4 4017 /* Number of packets received and timestamped */ 4018 #define MC_CMD_PTP_OUT_STATUS_STATS_RX_OFST 8 4019 /* Number of packets timestamped by the FPGA */ 4020 #define MC_CMD_PTP_OUT_STATUS_STATS_TS_OFST 12 4021 /* Number of packets filter matched */ 4022 #define MC_CMD_PTP_OUT_STATUS_STATS_FM_OFST 16 4023 /* Number of packets not filter matched */ 4024 #define MC_CMD_PTP_OUT_STATUS_STATS_NFM_OFST 20 4025 /* Number of PPS overflows (noise on input?) */ 4026 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFLOW_OFST 24 4027 /* Number of PPS bad periods */ 4028 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_BAD_OFST 28 4029 /* Minimum period of PPS pulse in nanoseconds */ 4030 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MIN_OFST 32 4031 /* Maximum period of PPS pulse in nanoseconds */ 4032 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MAX_OFST 36 4033 /* Last period of PPS pulse in nanoseconds */ 4034 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_LAST_OFST 40 4035 /* Mean period of PPS pulse in nanoseconds */ 4036 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MEAN_OFST 44 4037 /* Minimum offset of PPS pulse in nanoseconds (signed) */ 4038 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MIN_OFST 48 4039 /* Maximum offset of PPS pulse in nanoseconds (signed) */ 4040 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MAX_OFST 52 4041 /* Last offset of PPS pulse in nanoseconds (signed) */ 4042 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_LAST_OFST 56 4043 /* Mean offset of PPS pulse in nanoseconds (signed) */ 4044 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MEAN_OFST 60 4045 4046 /* MC_CMD_PTP_OUT_SYNCHRONIZE msgresponse */ 4047 #define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMIN 20 4048 #define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMAX 240 4049 #define MC_CMD_PTP_OUT_SYNCHRONIZE_LEN(num) (0+20*(num)) 4050 /* A set of host and NIC times */ 4051 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_OFST 0 4052 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_LEN 20 4053 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MINNUM 1 4054 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MAXNUM 12 4055 /* Host time immediately before NIC's hardware clock read */ 4056 #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTSTART_OFST 0 4057 /* Value of seconds timestamp */ 4058 #define MC_CMD_PTP_OUT_SYNCHRONIZE_SECONDS_OFST 4 4059 /* Timestamp major value */ 4060 #define MC_CMD_PTP_OUT_SYNCHRONIZE_MAJOR_OFST 4 4061 /* Value of nanoseconds timestamp */ 4062 #define MC_CMD_PTP_OUT_SYNCHRONIZE_NANOSECONDS_OFST 8 4063 /* Timestamp minor value */ 4064 #define MC_CMD_PTP_OUT_SYNCHRONIZE_MINOR_OFST 8 4065 /* Host time immediately after NIC's hardware clock read */ 4066 #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTEND_OFST 12 4067 /* Number of nanoseconds waited after reading NIC's hardware clock */ 4068 #define MC_CMD_PTP_OUT_SYNCHRONIZE_WAITNS_OFST 16 4069 4070 /* MC_CMD_PTP_OUT_MANFTEST_BASIC msgresponse */ 4071 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_LEN 8 4072 /* Results of testing */ 4073 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_RESULT_OFST 0 4074 /* enum: Successful test */ 4075 #define MC_CMD_PTP_MANF_SUCCESS 0x0 4076 /* enum: FPGA load failed */ 4077 #define MC_CMD_PTP_MANF_FPGA_LOAD 0x1 4078 /* enum: FPGA version invalid */ 4079 #define MC_CMD_PTP_MANF_FPGA_VERSION 0x2 4080 /* enum: FPGA registers incorrect */ 4081 #define MC_CMD_PTP_MANF_FPGA_REGISTERS 0x3 4082 /* enum: Oscillator possibly not working? */ 4083 #define MC_CMD_PTP_MANF_OSCILLATOR 0x4 4084 /* enum: Timestamps not increasing */ 4085 #define MC_CMD_PTP_MANF_TIMESTAMPS 0x5 4086 /* enum: Mismatched packet count */ 4087 #define MC_CMD_PTP_MANF_PACKET_COUNT 0x6 4088 /* enum: Mismatched packet count (Siena filter and FPGA) */ 4089 #define MC_CMD_PTP_MANF_FILTER_COUNT 0x7 4090 /* enum: Not enough packets to perform timestamp check */ 4091 #define MC_CMD_PTP_MANF_PACKET_ENOUGH 0x8 4092 /* enum: Timestamp trigger GPIO not working */ 4093 #define MC_CMD_PTP_MANF_GPIO_TRIGGER 0x9 4094 /* enum: Insufficient PPS events to perform checks */ 4095 #define MC_CMD_PTP_MANF_PPS_ENOUGH 0xa 4096 /* enum: PPS time event period not sufficiently close to 1s. */ 4097 #define MC_CMD_PTP_MANF_PPS_PERIOD 0xb 4098 /* enum: PPS time event nS reading not sufficiently close to zero. */ 4099 #define MC_CMD_PTP_MANF_PPS_NS 0xc 4100 /* enum: PTP peripheral registers incorrect */ 4101 #define MC_CMD_PTP_MANF_REGISTERS 0xd 4102 /* enum: Failed to read time from PTP peripheral */ 4103 #define MC_CMD_PTP_MANF_CLOCK_READ 0xe 4104 /* Presence of external oscillator */ 4105 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_EXTOSC_OFST 4 4106 4107 /* MC_CMD_PTP_OUT_MANFTEST_PACKET msgresponse */ 4108 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_LEN 12 4109 /* Results of testing */ 4110 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_RESULT_OFST 0 4111 /* Number of packets received by FPGA */ 4112 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FPGACOUNT_OFST 4 4113 /* Number of packets received by Siena filters */ 4114 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FILTERCOUNT_OFST 8 4115 4116 /* MC_CMD_PTP_OUT_FPGAREAD msgresponse */ 4117 #define MC_CMD_PTP_OUT_FPGAREAD_LENMIN 1 4118 #define MC_CMD_PTP_OUT_FPGAREAD_LENMAX 252 4119 #define MC_CMD_PTP_OUT_FPGAREAD_LEN(num) (0+1*(num)) 4120 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_OFST 0 4121 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_LEN 1 4122 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MINNUM 1 4123 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MAXNUM 252 4124 4125 /* MC_CMD_PTP_OUT_GET_TIME_FORMAT msgresponse */ 4126 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_LEN 4 4127 /* Time format required/used by for this NIC. Applies to all PTP MCDI 4128 * operations that pass times between the host and firmware. If this operation 4129 * is not supported (older firmware) a format of seconds and nanoseconds should 4130 * be assumed. 4131 */ 4132 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_FORMAT_OFST 0 4133 /* enum: Times are in seconds and nanoseconds */ 4134 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_NANOSECONDS 0x0 4135 /* enum: Major register has units of 16 second per tick, minor 8 ns per tick */ 4136 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_16SECONDS_8NANOSECONDS 0x1 4137 /* enum: Major register has units of seconds, minor 2^-27s per tick */ 4138 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_27FRACTION 0x2 4139 4140 /* MC_CMD_PTP_OUT_GET_ATTRIBUTES msgresponse */ 4141 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_LEN 24 4142 /* Time format required/used by for this NIC. Applies to all PTP MCDI 4143 * operations that pass times between the host and firmware. If this operation 4144 * is not supported (older firmware) a format of seconds and nanoseconds should 4145 * be assumed. 4146 */ 4147 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_TIME_FORMAT_OFST 0 4148 /* enum: Times are in seconds and nanoseconds */ 4149 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_NANOSECONDS 0x0 4150 /* enum: Major register has units of 16 second per tick, minor 8 ns per tick */ 4151 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_16SECONDS_8NANOSECONDS 0x1 4152 /* enum: Major register has units of seconds, minor 2^-27s per tick */ 4153 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_27FRACTION 0x2 4154 /* Minimum acceptable value for a corrected synchronization timeset. When 4155 * comparing host and NIC clock times, the MC returns a set of samples that 4156 * contain the host start and end time, the MC time when the host start was 4157 * detected and the time the MC waited between reading the time and detecting 4158 * the host end. The corrected sync window is the difference between the host 4159 * end and start times minus the time that the MC waited for host end. 4160 */ 4161 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SYNC_WINDOW_MIN_OFST 4 4162 /* Various PTP capabilities */ 4163 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_CAPABILITIES_OFST 8 4164 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_LBN 0 4165 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_WIDTH 1 4166 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RX_TSTAMP_OOB_LBN 1 4167 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RX_TSTAMP_OOB_WIDTH 1 4168 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED0_OFST 12 4169 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED1_OFST 16 4170 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED2_OFST 20 4171 4172 /* MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS msgresponse */ 4173 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_LEN 16 4174 /* Uncorrected error on PTP transmit timestamps in NIC clock format */ 4175 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_TRANSMIT_OFST 0 4176 /* Uncorrected error on PTP receive timestamps in NIC clock format */ 4177 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_RECEIVE_OFST 4 4178 /* Uncorrected error on PPS output in NIC clock format */ 4179 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_OUT_OFST 8 4180 /* Uncorrected error on PPS input in NIC clock format */ 4181 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_IN_OFST 12 4182 4183 /* MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2 msgresponse */ 4184 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_LEN 24 4185 /* Uncorrected error on PTP transmit timestamps in NIC clock format */ 4186 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_TX_OFST 0 4187 /* Uncorrected error on PTP receive timestamps in NIC clock format */ 4188 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_RX_OFST 4 4189 /* Uncorrected error on PPS output in NIC clock format */ 4190 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_OUT_OFST 8 4191 /* Uncorrected error on PPS input in NIC clock format */ 4192 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_IN_OFST 12 4193 /* Uncorrected error on non-PTP transmit timestamps in NIC clock format */ 4194 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_TX_OFST 16 4195 /* Uncorrected error on non-PTP receive timestamps in NIC clock format */ 4196 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_RX_OFST 20 4197 4198 /* MC_CMD_PTP_OUT_MANFTEST_PPS msgresponse */ 4199 #define MC_CMD_PTP_OUT_MANFTEST_PPS_LEN 4 4200 /* Results of testing */ 4201 #define MC_CMD_PTP_OUT_MANFTEST_PPS_TEST_RESULT_OFST 0 4202 /* Enum values, see field(s): */ 4203 /* MC_CMD_PTP_OUT_MANFTEST_BASIC/TEST_RESULT */ 4204 4205 /* MC_CMD_PTP_OUT_SET_SYNC_STATUS msgresponse */ 4206 #define MC_CMD_PTP_OUT_SET_SYNC_STATUS_LEN 0 4207 4208 4209 /***********************************/ 4210 /* MC_CMD_CSR_READ32 4211 * Read 32bit words from the indirect memory map. 4212 */ 4213 #define MC_CMD_CSR_READ32 0xc 4214 #undef MC_CMD_0xc_PRIVILEGE_CTG 4215 4216 #define MC_CMD_0xc_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4217 4218 /* MC_CMD_CSR_READ32_IN msgrequest */ 4219 #define MC_CMD_CSR_READ32_IN_LEN 12 4220 /* Address */ 4221 #define MC_CMD_CSR_READ32_IN_ADDR_OFST 0 4222 #define MC_CMD_CSR_READ32_IN_STEP_OFST 4 4223 #define MC_CMD_CSR_READ32_IN_NUMWORDS_OFST 8 4224 4225 /* MC_CMD_CSR_READ32_OUT msgresponse */ 4226 #define MC_CMD_CSR_READ32_OUT_LENMIN 4 4227 #define MC_CMD_CSR_READ32_OUT_LENMAX 252 4228 #define MC_CMD_CSR_READ32_OUT_LEN(num) (0+4*(num)) 4229 /* The last dword is the status, not a value read */ 4230 #define MC_CMD_CSR_READ32_OUT_BUFFER_OFST 0 4231 #define MC_CMD_CSR_READ32_OUT_BUFFER_LEN 4 4232 #define MC_CMD_CSR_READ32_OUT_BUFFER_MINNUM 1 4233 #define MC_CMD_CSR_READ32_OUT_BUFFER_MAXNUM 63 4234 4235 4236 /***********************************/ 4237 /* MC_CMD_CSR_WRITE32 4238 * Write 32bit dwords to the indirect memory map. 4239 */ 4240 #define MC_CMD_CSR_WRITE32 0xd 4241 #undef MC_CMD_0xd_PRIVILEGE_CTG 4242 4243 #define MC_CMD_0xd_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4244 4245 /* MC_CMD_CSR_WRITE32_IN msgrequest */ 4246 #define MC_CMD_CSR_WRITE32_IN_LENMIN 12 4247 #define MC_CMD_CSR_WRITE32_IN_LENMAX 252 4248 #define MC_CMD_CSR_WRITE32_IN_LEN(num) (8+4*(num)) 4249 /* Address */ 4250 #define MC_CMD_CSR_WRITE32_IN_ADDR_OFST 0 4251 #define MC_CMD_CSR_WRITE32_IN_STEP_OFST 4 4252 #define MC_CMD_CSR_WRITE32_IN_BUFFER_OFST 8 4253 #define MC_CMD_CSR_WRITE32_IN_BUFFER_LEN 4 4254 #define MC_CMD_CSR_WRITE32_IN_BUFFER_MINNUM 1 4255 #define MC_CMD_CSR_WRITE32_IN_BUFFER_MAXNUM 61 4256 4257 /* MC_CMD_CSR_WRITE32_OUT msgresponse */ 4258 #define MC_CMD_CSR_WRITE32_OUT_LEN 4 4259 #define MC_CMD_CSR_WRITE32_OUT_STATUS_OFST 0 4260 4261 4262 /***********************************/ 4263 /* MC_CMD_HP 4264 * These commands are used for HP related features. They are grouped under one 4265 * MCDI command to avoid creating too many MCDI commands. 4266 */ 4267 #define MC_CMD_HP 0x54 4268 #undef MC_CMD_0x54_PRIVILEGE_CTG 4269 4270 #define MC_CMD_0x54_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4271 4272 /* MC_CMD_HP_IN msgrequest */ 4273 #define MC_CMD_HP_IN_LEN 16 4274 /* HP OCSD sub-command. When address is not NULL, request activation of OCSD at 4275 * the specified address with the specified interval.When address is NULL, 4276 * INTERVAL is interpreted as a command: 0: stop OCSD / 1: Report OCSD current 4277 * state / 2: (debug) Show temperature reported by one of the supported 4278 * sensors. 4279 */ 4280 #define MC_CMD_HP_IN_SUBCMD_OFST 0 4281 /* enum: OCSD (Option Card Sensor Data) sub-command. */ 4282 #define MC_CMD_HP_IN_OCSD_SUBCMD 0x0 4283 /* enum: Last known valid HP sub-command. */ 4284 #define MC_CMD_HP_IN_LAST_SUBCMD 0x0 4285 /* The address to the array of sensor fields. (Or NULL to use a sub-command.) 4286 */ 4287 #define MC_CMD_HP_IN_OCSD_ADDR_OFST 4 4288 #define MC_CMD_HP_IN_OCSD_ADDR_LEN 8 4289 #define MC_CMD_HP_IN_OCSD_ADDR_LO_OFST 4 4290 #define MC_CMD_HP_IN_OCSD_ADDR_HI_OFST 8 4291 /* The requested update interval, in seconds. (Or the sub-command if ADDR is 4292 * NULL.) 4293 */ 4294 #define MC_CMD_HP_IN_OCSD_INTERVAL_OFST 12 4295 4296 /* MC_CMD_HP_OUT msgresponse */ 4297 #define MC_CMD_HP_OUT_LEN 4 4298 #define MC_CMD_HP_OUT_OCSD_STATUS_OFST 0 4299 /* enum: OCSD stopped for this card. */ 4300 #define MC_CMD_HP_OUT_OCSD_STOPPED 0x1 4301 /* enum: OCSD was successfully started with the address provided. */ 4302 #define MC_CMD_HP_OUT_OCSD_STARTED 0x2 4303 /* enum: OCSD was already started for this card. */ 4304 #define MC_CMD_HP_OUT_OCSD_ALREADY_STARTED 0x3 4305 4306 4307 /***********************************/ 4308 /* MC_CMD_STACKINFO 4309 * Get stack information. 4310 */ 4311 #define MC_CMD_STACKINFO 0xf 4312 #undef MC_CMD_0xf_PRIVILEGE_CTG 4313 4314 #define MC_CMD_0xf_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4315 4316 /* MC_CMD_STACKINFO_IN msgrequest */ 4317 #define MC_CMD_STACKINFO_IN_LEN 0 4318 4319 /* MC_CMD_STACKINFO_OUT msgresponse */ 4320 #define MC_CMD_STACKINFO_OUT_LENMIN 12 4321 #define MC_CMD_STACKINFO_OUT_LENMAX 252 4322 #define MC_CMD_STACKINFO_OUT_LEN(num) (0+12*(num)) 4323 /* (thread ptr, stack size, free space) for each thread in system */ 4324 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_OFST 0 4325 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_LEN 12 4326 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_MINNUM 1 4327 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_MAXNUM 21 4328 4329 4330 /***********************************/ 4331 /* MC_CMD_MDIO_READ 4332 * MDIO register read. 4333 */ 4334 #define MC_CMD_MDIO_READ 0x10 4335 #undef MC_CMD_0x10_PRIVILEGE_CTG 4336 4337 #define MC_CMD_0x10_PRIVILEGE_CTG SRIOV_CTG_GENERAL 4338 4339 /* MC_CMD_MDIO_READ_IN msgrequest */ 4340 #define MC_CMD_MDIO_READ_IN_LEN 16 4341 /* Bus number; there are two MDIO buses: one for the internal PHY, and one for 4342 * external devices. 4343 */ 4344 #define MC_CMD_MDIO_READ_IN_BUS_OFST 0 4345 /* enum: Internal. */ 4346 #define MC_CMD_MDIO_BUS_INTERNAL 0x0 4347 /* enum: External. */ 4348 #define MC_CMD_MDIO_BUS_EXTERNAL 0x1 4349 /* Port address */ 4350 #define MC_CMD_MDIO_READ_IN_PRTAD_OFST 4 4351 /* Device Address or clause 22. */ 4352 #define MC_CMD_MDIO_READ_IN_DEVAD_OFST 8 4353 /* enum: By default all the MCDI MDIO operations perform clause45 mode. If you 4354 * want to use clause22 then set DEVAD = MC_CMD_MDIO_CLAUSE22. 4355 */ 4356 #define MC_CMD_MDIO_CLAUSE22 0x20 4357 /* Address */ 4358 #define MC_CMD_MDIO_READ_IN_ADDR_OFST 12 4359 4360 /* MC_CMD_MDIO_READ_OUT msgresponse */ 4361 #define MC_CMD_MDIO_READ_OUT_LEN 8 4362 /* Value */ 4363 #define MC_CMD_MDIO_READ_OUT_VALUE_OFST 0 4364 /* Status the MDIO commands return the raw status bits from the MDIO block. A 4365 * "good" transaction should have the DONE bit set and all other bits clear. 4366 */ 4367 #define MC_CMD_MDIO_READ_OUT_STATUS_OFST 4 4368 /* enum: Good. */ 4369 #define MC_CMD_MDIO_STATUS_GOOD 0x8 4370 4371 4372 /***********************************/ 4373 /* MC_CMD_MDIO_WRITE 4374 * MDIO register write. 4375 */ 4376 #define MC_CMD_MDIO_WRITE 0x11 4377 #undef MC_CMD_0x11_PRIVILEGE_CTG 4378 4379 #define MC_CMD_0x11_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4380 4381 /* MC_CMD_MDIO_WRITE_IN msgrequest */ 4382 #define MC_CMD_MDIO_WRITE_IN_LEN 20 4383 /* Bus number; there are two MDIO buses: one for the internal PHY, and one for 4384 * external devices. 4385 */ 4386 #define MC_CMD_MDIO_WRITE_IN_BUS_OFST 0 4387 /* enum: Internal. */ 4388 /* MC_CMD_MDIO_BUS_INTERNAL 0x0 */ 4389 /* enum: External. */ 4390 /* MC_CMD_MDIO_BUS_EXTERNAL 0x1 */ 4391 /* Port address */ 4392 #define MC_CMD_MDIO_WRITE_IN_PRTAD_OFST 4 4393 /* Device Address or clause 22. */ 4394 #define MC_CMD_MDIO_WRITE_IN_DEVAD_OFST 8 4395 /* enum: By default all the MCDI MDIO operations perform clause45 mode. If you 4396 * want to use clause22 then set DEVAD = MC_CMD_MDIO_CLAUSE22. 4397 */ 4398 /* MC_CMD_MDIO_CLAUSE22 0x20 */ 4399 /* Address */ 4400 #define MC_CMD_MDIO_WRITE_IN_ADDR_OFST 12 4401 /* Value */ 4402 #define MC_CMD_MDIO_WRITE_IN_VALUE_OFST 16 4403 4404 /* MC_CMD_MDIO_WRITE_OUT msgresponse */ 4405 #define MC_CMD_MDIO_WRITE_OUT_LEN 4 4406 /* Status; the MDIO commands return the raw status bits from the MDIO block. A 4407 * "good" transaction should have the DONE bit set and all other bits clear. 4408 */ 4409 #define MC_CMD_MDIO_WRITE_OUT_STATUS_OFST 0 4410 /* enum: Good. */ 4411 /* MC_CMD_MDIO_STATUS_GOOD 0x8 */ 4412 4413 4414 /***********************************/ 4415 /* MC_CMD_DBI_WRITE 4416 * Write DBI register(s). 4417 */ 4418 #define MC_CMD_DBI_WRITE 0x12 4419 #undef MC_CMD_0x12_PRIVILEGE_CTG 4420 4421 #define MC_CMD_0x12_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4422 4423 /* MC_CMD_DBI_WRITE_IN msgrequest */ 4424 #define MC_CMD_DBI_WRITE_IN_LENMIN 12 4425 #define MC_CMD_DBI_WRITE_IN_LENMAX 252 4426 #define MC_CMD_DBI_WRITE_IN_LEN(num) (0+12*(num)) 4427 /* Each write op consists of an address (offset 0), byte enable/VF/CS2 (offset 4428 * 32) and value (offset 64). See MC_CMD_DBIWROP_TYPEDEF. 4429 */ 4430 #define MC_CMD_DBI_WRITE_IN_DBIWROP_OFST 0 4431 #define MC_CMD_DBI_WRITE_IN_DBIWROP_LEN 12 4432 #define MC_CMD_DBI_WRITE_IN_DBIWROP_MINNUM 1 4433 #define MC_CMD_DBI_WRITE_IN_DBIWROP_MAXNUM 21 4434 4435 /* MC_CMD_DBI_WRITE_OUT msgresponse */ 4436 #define MC_CMD_DBI_WRITE_OUT_LEN 0 4437 4438 /* MC_CMD_DBIWROP_TYPEDEF structuredef */ 4439 #define MC_CMD_DBIWROP_TYPEDEF_LEN 12 4440 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST 0 4441 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_LBN 0 4442 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_WIDTH 32 4443 #define MC_CMD_DBIWROP_TYPEDEF_PARMS_OFST 4 4444 #define MC_CMD_DBIWROP_TYPEDEF_VF_NUM_LBN 16 4445 #define MC_CMD_DBIWROP_TYPEDEF_VF_NUM_WIDTH 16 4446 #define MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_LBN 15 4447 #define MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_WIDTH 1 4448 #define MC_CMD_DBIWROP_TYPEDEF_CS2_LBN 14 4449 #define MC_CMD_DBIWROP_TYPEDEF_CS2_WIDTH 1 4450 #define MC_CMD_DBIWROP_TYPEDEF_PARMS_LBN 32 4451 #define MC_CMD_DBIWROP_TYPEDEF_PARMS_WIDTH 32 4452 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST 8 4453 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_LBN 64 4454 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_WIDTH 32 4455 4456 4457 /***********************************/ 4458 /* MC_CMD_PORT_READ32 4459 * Read a 32-bit register from the indirect port register map. The port to 4460 * access is implied by the Shared memory channel used. 4461 */ 4462 #define MC_CMD_PORT_READ32 0x14 4463 4464 /* MC_CMD_PORT_READ32_IN msgrequest */ 4465 #define MC_CMD_PORT_READ32_IN_LEN 4 4466 /* Address */ 4467 #define MC_CMD_PORT_READ32_IN_ADDR_OFST 0 4468 4469 /* MC_CMD_PORT_READ32_OUT msgresponse */ 4470 #define MC_CMD_PORT_READ32_OUT_LEN 8 4471 /* Value */ 4472 #define MC_CMD_PORT_READ32_OUT_VALUE_OFST 0 4473 /* Status */ 4474 #define MC_CMD_PORT_READ32_OUT_STATUS_OFST 4 4475 4476 4477 /***********************************/ 4478 /* MC_CMD_PORT_WRITE32 4479 * Write a 32-bit register to the indirect port register map. The port to 4480 * access is implied by the Shared memory channel used. 4481 */ 4482 #define MC_CMD_PORT_WRITE32 0x15 4483 4484 /* MC_CMD_PORT_WRITE32_IN msgrequest */ 4485 #define MC_CMD_PORT_WRITE32_IN_LEN 8 4486 /* Address */ 4487 #define MC_CMD_PORT_WRITE32_IN_ADDR_OFST 0 4488 /* Value */ 4489 #define MC_CMD_PORT_WRITE32_IN_VALUE_OFST 4 4490 4491 /* MC_CMD_PORT_WRITE32_OUT msgresponse */ 4492 #define MC_CMD_PORT_WRITE32_OUT_LEN 4 4493 /* Status */ 4494 #define MC_CMD_PORT_WRITE32_OUT_STATUS_OFST 0 4495 4496 4497 /***********************************/ 4498 /* MC_CMD_PORT_READ128 4499 * Read a 128-bit register from the indirect port register map. The port to 4500 * access is implied by the Shared memory channel used. 4501 */ 4502 #define MC_CMD_PORT_READ128 0x16 4503 4504 /* MC_CMD_PORT_READ128_IN msgrequest */ 4505 #define MC_CMD_PORT_READ128_IN_LEN 4 4506 /* Address */ 4507 #define MC_CMD_PORT_READ128_IN_ADDR_OFST 0 4508 4509 /* MC_CMD_PORT_READ128_OUT msgresponse */ 4510 #define MC_CMD_PORT_READ128_OUT_LEN 20 4511 /* Value */ 4512 #define MC_CMD_PORT_READ128_OUT_VALUE_OFST 0 4513 #define MC_CMD_PORT_READ128_OUT_VALUE_LEN 16 4514 /* Status */ 4515 #define MC_CMD_PORT_READ128_OUT_STATUS_OFST 16 4516 4517 4518 /***********************************/ 4519 /* MC_CMD_PORT_WRITE128 4520 * Write a 128-bit register to the indirect port register map. The port to 4521 * access is implied by the Shared memory channel used. 4522 */ 4523 #define MC_CMD_PORT_WRITE128 0x17 4524 4525 /* MC_CMD_PORT_WRITE128_IN msgrequest */ 4526 #define MC_CMD_PORT_WRITE128_IN_LEN 20 4527 /* Address */ 4528 #define MC_CMD_PORT_WRITE128_IN_ADDR_OFST 0 4529 /* Value */ 4530 #define MC_CMD_PORT_WRITE128_IN_VALUE_OFST 4 4531 #define MC_CMD_PORT_WRITE128_IN_VALUE_LEN 16 4532 4533 /* MC_CMD_PORT_WRITE128_OUT msgresponse */ 4534 #define MC_CMD_PORT_WRITE128_OUT_LEN 4 4535 /* Status */ 4536 #define MC_CMD_PORT_WRITE128_OUT_STATUS_OFST 0 4537 4538 /* MC_CMD_CAPABILITIES structuredef */ 4539 #define MC_CMD_CAPABILITIES_LEN 4 4540 /* Small buf table. */ 4541 #define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_LBN 0 4542 #define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_WIDTH 1 4543 /* Turbo mode (for Maranello). */ 4544 #define MC_CMD_CAPABILITIES_TURBO_LBN 1 4545 #define MC_CMD_CAPABILITIES_TURBO_WIDTH 1 4546 /* Turbo mode active (for Maranello). */ 4547 #define MC_CMD_CAPABILITIES_TURBO_ACTIVE_LBN 2 4548 #define MC_CMD_CAPABILITIES_TURBO_ACTIVE_WIDTH 1 4549 /* PTP offload. */ 4550 #define MC_CMD_CAPABILITIES_PTP_LBN 3 4551 #define MC_CMD_CAPABILITIES_PTP_WIDTH 1 4552 /* AOE mode. */ 4553 #define MC_CMD_CAPABILITIES_AOE_LBN 4 4554 #define MC_CMD_CAPABILITIES_AOE_WIDTH 1 4555 /* AOE mode active. */ 4556 #define MC_CMD_CAPABILITIES_AOE_ACTIVE_LBN 5 4557 #define MC_CMD_CAPABILITIES_AOE_ACTIVE_WIDTH 1 4558 /* AOE mode active. */ 4559 #define MC_CMD_CAPABILITIES_FC_ACTIVE_LBN 6 4560 #define MC_CMD_CAPABILITIES_FC_ACTIVE_WIDTH 1 4561 #define MC_CMD_CAPABILITIES_RESERVED_LBN 7 4562 #define MC_CMD_CAPABILITIES_RESERVED_WIDTH 25 4563 4564 4565 /***********************************/ 4566 /* MC_CMD_GET_BOARD_CFG 4567 * Returns the MC firmware configuration structure. 4568 */ 4569 #define MC_CMD_GET_BOARD_CFG 0x18 4570 #undef MC_CMD_0x18_PRIVILEGE_CTG 4571 4572 #define MC_CMD_0x18_PRIVILEGE_CTG SRIOV_CTG_GENERAL 4573 4574 /* MC_CMD_GET_BOARD_CFG_IN msgrequest */ 4575 #define MC_CMD_GET_BOARD_CFG_IN_LEN 0 4576 4577 /* MC_CMD_GET_BOARD_CFG_OUT msgresponse */ 4578 #define MC_CMD_GET_BOARD_CFG_OUT_LENMIN 96 4579 #define MC_CMD_GET_BOARD_CFG_OUT_LENMAX 136 4580 #define MC_CMD_GET_BOARD_CFG_OUT_LEN(num) (72+2*(num)) 4581 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_OFST 0 4582 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_OFST 4 4583 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_LEN 32 4584 /* See MC_CMD_CAPABILITIES */ 4585 #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT0_OFST 36 4586 /* See MC_CMD_CAPABILITIES */ 4587 #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT1_OFST 40 4588 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_OFST 44 4589 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_LEN 6 4590 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_OFST 50 4591 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_LEN 6 4592 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT0_OFST 56 4593 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT1_OFST 60 4594 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT0_OFST 64 4595 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT1_OFST 68 4596 /* This field contains a 16-bit value for each of the types of NVRAM area. The 4597 * values are defined in the firmware/mc/platform/.c file for a specific board 4598 * type, but otherwise have no meaning to the MC; they are used by the driver 4599 * to manage selection of appropriate firmware updates. 4600 */ 4601 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_OFST 72 4602 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_LEN 2 4603 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MINNUM 12 4604 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM 32 4605 4606 4607 /***********************************/ 4608 /* MC_CMD_DBI_READX 4609 * Read DBI register(s) -- extended functionality 4610 */ 4611 #define MC_CMD_DBI_READX 0x19 4612 #undef MC_CMD_0x19_PRIVILEGE_CTG 4613 4614 #define MC_CMD_0x19_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4615 4616 /* MC_CMD_DBI_READX_IN msgrequest */ 4617 #define MC_CMD_DBI_READX_IN_LENMIN 8 4618 #define MC_CMD_DBI_READX_IN_LENMAX 248 4619 #define MC_CMD_DBI_READX_IN_LEN(num) (0+8*(num)) 4620 /* Each Read op consists of an address (offset 0), VF/CS2) */ 4621 #define MC_CMD_DBI_READX_IN_DBIRDOP_OFST 0 4622 #define MC_CMD_DBI_READX_IN_DBIRDOP_LEN 8 4623 #define MC_CMD_DBI_READX_IN_DBIRDOP_LO_OFST 0 4624 #define MC_CMD_DBI_READX_IN_DBIRDOP_HI_OFST 4 4625 #define MC_CMD_DBI_READX_IN_DBIRDOP_MINNUM 1 4626 #define MC_CMD_DBI_READX_IN_DBIRDOP_MAXNUM 31 4627 4628 /* MC_CMD_DBI_READX_OUT msgresponse */ 4629 #define MC_CMD_DBI_READX_OUT_LENMIN 4 4630 #define MC_CMD_DBI_READX_OUT_LENMAX 252 4631 #define MC_CMD_DBI_READX_OUT_LEN(num) (0+4*(num)) 4632 /* Value */ 4633 #define MC_CMD_DBI_READX_OUT_VALUE_OFST 0 4634 #define MC_CMD_DBI_READX_OUT_VALUE_LEN 4 4635 #define MC_CMD_DBI_READX_OUT_VALUE_MINNUM 1 4636 #define MC_CMD_DBI_READX_OUT_VALUE_MAXNUM 63 4637 4638 /* MC_CMD_DBIRDOP_TYPEDEF structuredef */ 4639 #define MC_CMD_DBIRDOP_TYPEDEF_LEN 8 4640 #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_OFST 0 4641 #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_LBN 0 4642 #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_WIDTH 32 4643 #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_OFST 4 4644 #define MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_LBN 16 4645 #define MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_WIDTH 16 4646 #define MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_LBN 15 4647 #define MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_WIDTH 1 4648 #define MC_CMD_DBIRDOP_TYPEDEF_CS2_LBN 14 4649 #define MC_CMD_DBIRDOP_TYPEDEF_CS2_WIDTH 1 4650 #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_LBN 32 4651 #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_WIDTH 32 4652 4653 4654 /***********************************/ 4655 /* MC_CMD_SET_RAND_SEED 4656 * Set the 16byte seed for the MC pseudo-random generator. 4657 */ 4658 #define MC_CMD_SET_RAND_SEED 0x1a 4659 #undef MC_CMD_0x1a_PRIVILEGE_CTG 4660 4661 #define MC_CMD_0x1a_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4662 4663 /* MC_CMD_SET_RAND_SEED_IN msgrequest */ 4664 #define MC_CMD_SET_RAND_SEED_IN_LEN 16 4665 /* Seed value. */ 4666 #define MC_CMD_SET_RAND_SEED_IN_SEED_OFST 0 4667 #define MC_CMD_SET_RAND_SEED_IN_SEED_LEN 16 4668 4669 /* MC_CMD_SET_RAND_SEED_OUT msgresponse */ 4670 #define MC_CMD_SET_RAND_SEED_OUT_LEN 0 4671 4672 4673 /***********************************/ 4674 /* MC_CMD_LTSSM_HIST 4675 * Retrieve the history of the LTSSM, if the build supports it. 4676 */ 4677 #define MC_CMD_LTSSM_HIST 0x1b 4678 4679 /* MC_CMD_LTSSM_HIST_IN msgrequest */ 4680 #define MC_CMD_LTSSM_HIST_IN_LEN 0 4681 4682 /* MC_CMD_LTSSM_HIST_OUT msgresponse */ 4683 #define MC_CMD_LTSSM_HIST_OUT_LENMIN 0 4684 #define MC_CMD_LTSSM_HIST_OUT_LENMAX 252 4685 #define MC_CMD_LTSSM_HIST_OUT_LEN(num) (0+4*(num)) 4686 /* variable number of LTSSM values, as bytes. The history is read-to-clear. */ 4687 #define MC_CMD_LTSSM_HIST_OUT_DATA_OFST 0 4688 #define MC_CMD_LTSSM_HIST_OUT_DATA_LEN 4 4689 #define MC_CMD_LTSSM_HIST_OUT_DATA_MINNUM 0 4690 #define MC_CMD_LTSSM_HIST_OUT_DATA_MAXNUM 63 4691 4692 4693 /***********************************/ 4694 /* MC_CMD_DRV_ATTACH 4695 * Inform MCPU that this port is managed on the host (i.e. driver active). For 4696 * Huntington, also request the preferred datapath firmware to use if possible 4697 * (it may not be possible for this request to be fulfilled; the driver must 4698 * issue a subsequent MC_CMD_GET_CAPABILITIES command to determine which 4699 * features are actually available). The FIRMWARE_ID field is ignored by older 4700 * platforms. 4701 */ 4702 #define MC_CMD_DRV_ATTACH 0x1c 4703 #undef MC_CMD_0x1c_PRIVILEGE_CTG 4704 4705 #define MC_CMD_0x1c_PRIVILEGE_CTG SRIOV_CTG_GENERAL 4706 4707 /* MC_CMD_DRV_ATTACH_IN msgrequest */ 4708 #define MC_CMD_DRV_ATTACH_IN_LEN 12 4709 /* new state to set if UPDATE=1 */ 4710 #define MC_CMD_DRV_ATTACH_IN_NEW_STATE_OFST 0 4711 #define MC_CMD_DRV_ATTACH_LBN 0 4712 #define MC_CMD_DRV_ATTACH_WIDTH 1 4713 #define MC_CMD_DRV_PREBOOT_LBN 1 4714 #define MC_CMD_DRV_PREBOOT_WIDTH 1 4715 /* 1 to set new state, or 0 to just report the existing state */ 4716 #define MC_CMD_DRV_ATTACH_IN_UPDATE_OFST 4 4717 /* preferred datapath firmware (for Huntington; ignored for Siena) */ 4718 #define MC_CMD_DRV_ATTACH_IN_FIRMWARE_ID_OFST 8 4719 /* enum: Prefer to use full featured firmware */ 4720 #define MC_CMD_FW_FULL_FEATURED 0x0 4721 /* enum: Prefer to use firmware with fewer features but lower latency */ 4722 #define MC_CMD_FW_LOW_LATENCY 0x1 4723 /* enum: Prefer to use firmware for SolarCapture packed stream mode */ 4724 #define MC_CMD_FW_PACKED_STREAM 0x2 4725 /* enum: Prefer to use firmware with fewer features and simpler TX event 4726 * batching but higher TX packet rate 4727 */ 4728 #define MC_CMD_FW_HIGH_TX_RATE 0x3 4729 /* enum: Reserved value */ 4730 #define MC_CMD_FW_PACKED_STREAM_HASH_MODE_1 0x4 4731 /* enum: Prefer to use firmware with additional "rules engine" filtering 4732 * support 4733 */ 4734 #define MC_CMD_FW_RULES_ENGINE 0x5 4735 /* enum: Only this option is allowed for non-admin functions */ 4736 #define MC_CMD_FW_DONT_CARE 0xffffffff 4737 4738 /* MC_CMD_DRV_ATTACH_OUT msgresponse */ 4739 #define MC_CMD_DRV_ATTACH_OUT_LEN 4 4740 /* previous or existing state, see the bitmask at NEW_STATE */ 4741 #define MC_CMD_DRV_ATTACH_OUT_OLD_STATE_OFST 0 4742 4743 /* MC_CMD_DRV_ATTACH_EXT_OUT msgresponse */ 4744 #define MC_CMD_DRV_ATTACH_EXT_OUT_LEN 8 4745 /* previous or existing state, see the bitmask at NEW_STATE */ 4746 #define MC_CMD_DRV_ATTACH_EXT_OUT_OLD_STATE_OFST 0 4747 /* Flags associated with this function */ 4748 #define MC_CMD_DRV_ATTACH_EXT_OUT_FUNC_FLAGS_OFST 4 4749 /* enum: Labels the lowest-numbered function visible to the OS */ 4750 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY 0x0 4751 /* enum: The function can control the link state of the physical port it is 4752 * bound to. 4753 */ 4754 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL 0x1 4755 /* enum: The function can perform privileged operations */ 4756 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TRUSTED 0x2 4757 /* enum: The function does not have an active port associated with it. The port 4758 * refers to the Sorrento external FPGA port. 4759 */ 4760 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_NO_ACTIVE_PORT 0x3 4761 4762 4763 /***********************************/ 4764 /* MC_CMD_SHMUART 4765 * Route UART output to circular buffer in shared memory instead. 4766 */ 4767 #define MC_CMD_SHMUART 0x1f 4768 4769 /* MC_CMD_SHMUART_IN msgrequest */ 4770 #define MC_CMD_SHMUART_IN_LEN 4 4771 /* ??? */ 4772 #define MC_CMD_SHMUART_IN_FLAG_OFST 0 4773 4774 /* MC_CMD_SHMUART_OUT msgresponse */ 4775 #define MC_CMD_SHMUART_OUT_LEN 0 4776 4777 4778 /***********************************/ 4779 /* MC_CMD_PORT_RESET 4780 * Generic per-port reset. There is no equivalent for per-board reset. Locks 4781 * required: None; Return code: 0, ETIME. NOTE: This command is deprecated - 4782 * use MC_CMD_ENTITY_RESET instead. 4783 */ 4784 #define MC_CMD_PORT_RESET 0x20 4785 #undef MC_CMD_0x20_PRIVILEGE_CTG 4786 4787 #define MC_CMD_0x20_PRIVILEGE_CTG SRIOV_CTG_GENERAL 4788 4789 /* MC_CMD_PORT_RESET_IN msgrequest */ 4790 #define MC_CMD_PORT_RESET_IN_LEN 0 4791 4792 /* MC_CMD_PORT_RESET_OUT msgresponse */ 4793 #define MC_CMD_PORT_RESET_OUT_LEN 0 4794 4795 4796 /***********************************/ 4797 /* MC_CMD_ENTITY_RESET 4798 * Generic per-resource reset. There is no equivalent for per-board reset. 4799 * Locks required: None; Return code: 0, ETIME. NOTE: This command is an 4800 * extended version of the deprecated MC_CMD_PORT_RESET with added fields. 4801 */ 4802 #define MC_CMD_ENTITY_RESET 0x20 4803 /* MC_CMD_0x20_PRIVILEGE_CTG SRIOV_CTG_GENERAL */ 4804 4805 /* MC_CMD_ENTITY_RESET_IN msgrequest */ 4806 #define MC_CMD_ENTITY_RESET_IN_LEN 4 4807 /* Optional flags field. Omitting this will perform a "legacy" reset action 4808 * (TBD). 4809 */ 4810 #define MC_CMD_ENTITY_RESET_IN_FLAG_OFST 0 4811 #define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_LBN 0 4812 #define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_WIDTH 1 4813 4814 /* MC_CMD_ENTITY_RESET_OUT msgresponse */ 4815 #define MC_CMD_ENTITY_RESET_OUT_LEN 0 4816 4817 4818 /***********************************/ 4819 /* MC_CMD_PCIE_CREDITS 4820 * Read instantaneous and minimum flow control thresholds. 4821 */ 4822 #define MC_CMD_PCIE_CREDITS 0x21 4823 4824 /* MC_CMD_PCIE_CREDITS_IN msgrequest */ 4825 #define MC_CMD_PCIE_CREDITS_IN_LEN 8 4826 /* poll period. 0 is disabled */ 4827 #define MC_CMD_PCIE_CREDITS_IN_POLL_PERIOD_OFST 0 4828 /* wipe statistics */ 4829 #define MC_CMD_PCIE_CREDITS_IN_WIPE_OFST 4 4830 4831 /* MC_CMD_PCIE_CREDITS_OUT msgresponse */ 4832 #define MC_CMD_PCIE_CREDITS_OUT_LEN 16 4833 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_OFST 0 4834 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_LEN 2 4835 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_OFST 2 4836 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_LEN 2 4837 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_OFST 4 4838 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_LEN 2 4839 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_OFST 6 4840 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_LEN 2 4841 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_OFST 8 4842 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_LEN 2 4843 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_OFST 10 4844 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_LEN 2 4845 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_OFST 12 4846 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_LEN 2 4847 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_OFST 14 4848 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_LEN 2 4849 4850 4851 /***********************************/ 4852 /* MC_CMD_RXD_MONITOR 4853 * Get histogram of RX queue fill level. 4854 */ 4855 #define MC_CMD_RXD_MONITOR 0x22 4856 4857 /* MC_CMD_RXD_MONITOR_IN msgrequest */ 4858 #define MC_CMD_RXD_MONITOR_IN_LEN 12 4859 #define MC_CMD_RXD_MONITOR_IN_QID_OFST 0 4860 #define MC_CMD_RXD_MONITOR_IN_POLL_PERIOD_OFST 4 4861 #define MC_CMD_RXD_MONITOR_IN_WIPE_OFST 8 4862 4863 /* MC_CMD_RXD_MONITOR_OUT msgresponse */ 4864 #define MC_CMD_RXD_MONITOR_OUT_LEN 80 4865 #define MC_CMD_RXD_MONITOR_OUT_QID_OFST 0 4866 #define MC_CMD_RXD_MONITOR_OUT_RING_FILL_OFST 4 4867 #define MC_CMD_RXD_MONITOR_OUT_CACHE_FILL_OFST 8 4868 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_1_OFST 12 4869 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_2_OFST 16 4870 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_4_OFST 20 4871 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_8_OFST 24 4872 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_16_OFST 28 4873 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_32_OFST 32 4874 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_64_OFST 36 4875 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_128_OFST 40 4876 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_256_OFST 44 4877 #define MC_CMD_RXD_MONITOR_OUT_RING_GE_256_OFST 48 4878 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_1_OFST 52 4879 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_2_OFST 56 4880 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_4_OFST 60 4881 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_8_OFST 64 4882 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_16_OFST 68 4883 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_32_OFST 72 4884 #define MC_CMD_RXD_MONITOR_OUT_CACHE_GE_32_OFST 76 4885 4886 4887 /***********************************/ 4888 /* MC_CMD_PUTS 4889 * Copy the given ASCII string out onto UART and/or out of the network port. 4890 */ 4891 #define MC_CMD_PUTS 0x23 4892 #undef MC_CMD_0x23_PRIVILEGE_CTG 4893 4894 #define MC_CMD_0x23_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4895 4896 /* MC_CMD_PUTS_IN msgrequest */ 4897 #define MC_CMD_PUTS_IN_LENMIN 13 4898 #define MC_CMD_PUTS_IN_LENMAX 252 4899 #define MC_CMD_PUTS_IN_LEN(num) (12+1*(num)) 4900 #define MC_CMD_PUTS_IN_DEST_OFST 0 4901 #define MC_CMD_PUTS_IN_UART_LBN 0 4902 #define MC_CMD_PUTS_IN_UART_WIDTH 1 4903 #define MC_CMD_PUTS_IN_PORT_LBN 1 4904 #define MC_CMD_PUTS_IN_PORT_WIDTH 1 4905 #define MC_CMD_PUTS_IN_DHOST_OFST 4 4906 #define MC_CMD_PUTS_IN_DHOST_LEN 6 4907 #define MC_CMD_PUTS_IN_STRING_OFST 12 4908 #define MC_CMD_PUTS_IN_STRING_LEN 1 4909 #define MC_CMD_PUTS_IN_STRING_MINNUM 1 4910 #define MC_CMD_PUTS_IN_STRING_MAXNUM 240 4911 4912 /* MC_CMD_PUTS_OUT msgresponse */ 4913 #define MC_CMD_PUTS_OUT_LEN 0 4914 4915 4916 /***********************************/ 4917 /* MC_CMD_GET_PHY_CFG 4918 * Report PHY configuration. This guarantees to succeed even if the PHY is in a 4919 * 'zombie' state. Locks required: None 4920 */ 4921 #define MC_CMD_GET_PHY_CFG 0x24 4922 #undef MC_CMD_0x24_PRIVILEGE_CTG 4923 4924 #define MC_CMD_0x24_PRIVILEGE_CTG SRIOV_CTG_GENERAL 4925 4926 /* MC_CMD_GET_PHY_CFG_IN msgrequest */ 4927 #define MC_CMD_GET_PHY_CFG_IN_LEN 0 4928 4929 /* MC_CMD_GET_PHY_CFG_OUT msgresponse */ 4930 #define MC_CMD_GET_PHY_CFG_OUT_LEN 72 4931 /* flags */ 4932 #define MC_CMD_GET_PHY_CFG_OUT_FLAGS_OFST 0 4933 #define MC_CMD_GET_PHY_CFG_OUT_PRESENT_LBN 0 4934 #define MC_CMD_GET_PHY_CFG_OUT_PRESENT_WIDTH 1 4935 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_LBN 1 4936 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_WIDTH 1 4937 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_LBN 2 4938 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_WIDTH 1 4939 #define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_LBN 3 4940 #define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_WIDTH 1 4941 #define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_LBN 4 4942 #define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_WIDTH 1 4943 #define MC_CMD_GET_PHY_CFG_OUT_TXDIS_LBN 5 4944 #define MC_CMD_GET_PHY_CFG_OUT_TXDIS_WIDTH 1 4945 #define MC_CMD_GET_PHY_CFG_OUT_BIST_LBN 6 4946 #define MC_CMD_GET_PHY_CFG_OUT_BIST_WIDTH 1 4947 /* ?? */ 4948 #define MC_CMD_GET_PHY_CFG_OUT_TYPE_OFST 4 4949 /* Bitmask of supported capabilities */ 4950 #define MC_CMD_GET_PHY_CFG_OUT_SUPPORTED_CAP_OFST 8 4951 #define MC_CMD_PHY_CAP_10HDX_LBN 1 4952 #define MC_CMD_PHY_CAP_10HDX_WIDTH 1 4953 #define MC_CMD_PHY_CAP_10FDX_LBN 2 4954 #define MC_CMD_PHY_CAP_10FDX_WIDTH 1 4955 #define MC_CMD_PHY_CAP_100HDX_LBN 3 4956 #define MC_CMD_PHY_CAP_100HDX_WIDTH 1 4957 #define MC_CMD_PHY_CAP_100FDX_LBN 4 4958 #define MC_CMD_PHY_CAP_100FDX_WIDTH 1 4959 #define MC_CMD_PHY_CAP_1000HDX_LBN 5 4960 #define MC_CMD_PHY_CAP_1000HDX_WIDTH 1 4961 #define MC_CMD_PHY_CAP_1000FDX_LBN 6 4962 #define MC_CMD_PHY_CAP_1000FDX_WIDTH 1 4963 #define MC_CMD_PHY_CAP_10000FDX_LBN 7 4964 #define MC_CMD_PHY_CAP_10000FDX_WIDTH 1 4965 #define MC_CMD_PHY_CAP_PAUSE_LBN 8 4966 #define MC_CMD_PHY_CAP_PAUSE_WIDTH 1 4967 #define MC_CMD_PHY_CAP_ASYM_LBN 9 4968 #define MC_CMD_PHY_CAP_ASYM_WIDTH 1 4969 #define MC_CMD_PHY_CAP_AN_LBN 10 4970 #define MC_CMD_PHY_CAP_AN_WIDTH 1 4971 #define MC_CMD_PHY_CAP_40000FDX_LBN 11 4972 #define MC_CMD_PHY_CAP_40000FDX_WIDTH 1 4973 #define MC_CMD_PHY_CAP_DDM_LBN 12 4974 #define MC_CMD_PHY_CAP_DDM_WIDTH 1 4975 /* ?? */ 4976 #define MC_CMD_GET_PHY_CFG_OUT_CHANNEL_OFST 12 4977 /* ?? */ 4978 #define MC_CMD_GET_PHY_CFG_OUT_PRT_OFST 16 4979 /* ?? */ 4980 #define MC_CMD_GET_PHY_CFG_OUT_STATS_MASK_OFST 20 4981 /* ?? */ 4982 #define MC_CMD_GET_PHY_CFG_OUT_NAME_OFST 24 4983 #define MC_CMD_GET_PHY_CFG_OUT_NAME_LEN 20 4984 /* ?? */ 4985 #define MC_CMD_GET_PHY_CFG_OUT_MEDIA_TYPE_OFST 44 4986 /* enum: Xaui. */ 4987 #define MC_CMD_MEDIA_XAUI 0x1 4988 /* enum: CX4. */ 4989 #define MC_CMD_MEDIA_CX4 0x2 4990 /* enum: KX4. */ 4991 #define MC_CMD_MEDIA_KX4 0x3 4992 /* enum: XFP Far. */ 4993 #define MC_CMD_MEDIA_XFP 0x4 4994 /* enum: SFP+. */ 4995 #define MC_CMD_MEDIA_SFP_PLUS 0x5 4996 /* enum: 10GBaseT. */ 4997 #define MC_CMD_MEDIA_BASE_T 0x6 4998 /* enum: QSFP+. */ 4999 #define MC_CMD_MEDIA_QSFP_PLUS 0x7 5000 #define MC_CMD_GET_PHY_CFG_OUT_MMD_MASK_OFST 48 5001 /* enum: Native clause 22 */ 5002 #define MC_CMD_MMD_CLAUSE22 0x0 5003 #define MC_CMD_MMD_CLAUSE45_PMAPMD 0x1 /* enum */ 5004 #define MC_CMD_MMD_CLAUSE45_WIS 0x2 /* enum */ 5005 #define MC_CMD_MMD_CLAUSE45_PCS 0x3 /* enum */ 5006 #define MC_CMD_MMD_CLAUSE45_PHYXS 0x4 /* enum */ 5007 #define MC_CMD_MMD_CLAUSE45_DTEXS 0x5 /* enum */ 5008 #define MC_CMD_MMD_CLAUSE45_TC 0x6 /* enum */ 5009 #define MC_CMD_MMD_CLAUSE45_AN 0x7 /* enum */ 5010 /* enum: Clause22 proxied over clause45 by PHY. */ 5011 #define MC_CMD_MMD_CLAUSE45_C22EXT 0x1d 5012 #define MC_CMD_MMD_CLAUSE45_VEND1 0x1e /* enum */ 5013 #define MC_CMD_MMD_CLAUSE45_VEND2 0x1f /* enum */ 5014 #define MC_CMD_GET_PHY_CFG_OUT_REVISION_OFST 52 5015 #define MC_CMD_GET_PHY_CFG_OUT_REVISION_LEN 20 5016 5017 5018 /***********************************/ 5019 /* MC_CMD_START_BIST 5020 * Start a BIST test on the PHY. Locks required: PHY_LOCK if doing a PHY BIST 5021 * Return code: 0, EINVAL, EACCES (if PHY_LOCK is not held) 5022 */ 5023 #define MC_CMD_START_BIST 0x25 5024 #undef MC_CMD_0x25_PRIVILEGE_CTG 5025 5026 #define MC_CMD_0x25_PRIVILEGE_CTG SRIOV_CTG_ADMIN 5027 5028 /* MC_CMD_START_BIST_IN msgrequest */ 5029 #define MC_CMD_START_BIST_IN_LEN 4 5030 /* Type of test. */ 5031 #define MC_CMD_START_BIST_IN_TYPE_OFST 0 5032 /* enum: Run the PHY's short cable BIST. */ 5033 #define MC_CMD_PHY_BIST_CABLE_SHORT 0x1 5034 /* enum: Run the PHY's long cable BIST. */ 5035 #define MC_CMD_PHY_BIST_CABLE_LONG 0x2 5036 /* enum: Run BIST on the currently selected BPX Serdes (XAUI or XFI) . */ 5037 #define MC_CMD_BPX_SERDES_BIST 0x3 5038 /* enum: Run the MC loopback tests. */ 5039 #define MC_CMD_MC_LOOPBACK_BIST 0x4 5040 /* enum: Run the PHY's standard BIST. */ 5041 #define MC_CMD_PHY_BIST 0x5 5042 /* enum: Run MC RAM test. */ 5043 #define MC_CMD_MC_MEM_BIST 0x6 5044 /* enum: Run Port RAM test. */ 5045 #define MC_CMD_PORT_MEM_BIST 0x7 5046 /* enum: Run register test. */ 5047 #define MC_CMD_REG_BIST 0x8 5048 5049 /* MC_CMD_START_BIST_OUT msgresponse */ 5050 #define MC_CMD_START_BIST_OUT_LEN 0 5051 5052 5053 /***********************************/ 5054 /* MC_CMD_POLL_BIST 5055 * Poll for BIST completion. Returns a single status code, and optionally some 5056 * PHY specific bist output. The driver should only consume the BIST output 5057 * after validating OUTLEN and MC_CMD_GET_PHY_CFG.TYPE. If a driver can't 5058 * successfully parse the BIST output, it should still respect the pass/Fail in 5059 * OUT.RESULT. Locks required: PHY_LOCK if doing a PHY BIST. Return code: 0, 5060 * EACCES (if PHY_LOCK is not held). 5061 */ 5062 #define MC_CMD_POLL_BIST 0x26 5063 #undef MC_CMD_0x26_PRIVILEGE_CTG 5064 5065 #define MC_CMD_0x26_PRIVILEGE_CTG SRIOV_CTG_ADMIN 5066 5067 /* MC_CMD_POLL_BIST_IN msgrequest */ 5068 #define MC_CMD_POLL_BIST_IN_LEN 0 5069 5070 /* MC_CMD_POLL_BIST_OUT msgresponse */ 5071 #define MC_CMD_POLL_BIST_OUT_LEN 8 5072 /* result */ 5073 #define MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 5074 /* enum: Running. */ 5075 #define MC_CMD_POLL_BIST_RUNNING 0x1 5076 /* enum: Passed. */ 5077 #define MC_CMD_POLL_BIST_PASSED 0x2 5078 /* enum: Failed. */ 5079 #define MC_CMD_POLL_BIST_FAILED 0x3 5080 /* enum: Timed-out. */ 5081 #define MC_CMD_POLL_BIST_TIMEOUT 0x4 5082 #define MC_CMD_POLL_BIST_OUT_PRIVATE_OFST 4 5083 5084 /* MC_CMD_POLL_BIST_OUT_SFT9001 msgresponse */ 5085 #define MC_CMD_POLL_BIST_OUT_SFT9001_LEN 36 5086 /* result */ 5087 /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */ 5088 /* Enum values, see field(s): */ 5089 /* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */ 5090 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A_OFST 4 5091 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B_OFST 8 5092 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C_OFST 12 5093 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D_OFST 16 5094 /* Status of each channel A */ 5095 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_A_OFST 20 5096 /* enum: Ok. */ 5097 #define MC_CMD_POLL_BIST_SFT9001_PAIR_OK 0x1 5098 /* enum: Open. */ 5099 #define MC_CMD_POLL_BIST_SFT9001_PAIR_OPEN 0x2 5100 /* enum: Intra-pair short. */ 5101 #define MC_CMD_POLL_BIST_SFT9001_INTRA_PAIR_SHORT 0x3 5102 /* enum: Inter-pair short. */ 5103 #define MC_CMD_POLL_BIST_SFT9001_INTER_PAIR_SHORT 0x4 5104 /* enum: Busy. */ 5105 #define MC_CMD_POLL_BIST_SFT9001_PAIR_BUSY 0x9 5106 /* Status of each channel B */ 5107 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_B_OFST 24 5108 /* Enum values, see field(s): */ 5109 /* CABLE_STATUS_A */ 5110 /* Status of each channel C */ 5111 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_C_OFST 28 5112 /* Enum values, see field(s): */ 5113 /* CABLE_STATUS_A */ 5114 /* Status of each channel D */ 5115 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_D_OFST 32 5116 /* Enum values, see field(s): */ 5117 /* CABLE_STATUS_A */ 5118 5119 /* MC_CMD_POLL_BIST_OUT_MRSFP msgresponse */ 5120 #define MC_CMD_POLL_BIST_OUT_MRSFP_LEN 8 5121 /* result */ 5122 /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */ 5123 /* Enum values, see field(s): */ 5124 /* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */ 5125 #define MC_CMD_POLL_BIST_OUT_MRSFP_TEST_OFST 4 5126 /* enum: Complete. */ 5127 #define MC_CMD_POLL_BIST_MRSFP_TEST_COMPLETE 0x0 5128 /* enum: Bus switch off I2C write. */ 5129 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_WRITE 0x1 5130 /* enum: Bus switch off I2C no access IO exp. */ 5131 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_IO_EXP 0x2 5132 /* enum: Bus switch off I2C no access module. */ 5133 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_MODULE 0x3 5134 /* enum: IO exp I2C configure. */ 5135 #define MC_CMD_POLL_BIST_MRSFP_TEST_IO_EXP_I2C_CONFIGURE 0x4 5136 /* enum: Bus switch I2C no cross talk. */ 5137 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_I2C_NO_CROSSTALK 0x5 5138 /* enum: Module presence. */ 5139 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_PRESENCE 0x6 5140 /* enum: Module ID I2C access. */ 5141 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_I2C_ACCESS 0x7 5142 /* enum: Module ID sane value. */ 5143 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_SANE_VALUE 0x8 5144 5145 /* MC_CMD_POLL_BIST_OUT_MEM msgresponse */ 5146 #define MC_CMD_POLL_BIST_OUT_MEM_LEN 36 5147 /* result */ 5148 /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */ 5149 /* Enum values, see field(s): */ 5150 /* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */ 5151 #define MC_CMD_POLL_BIST_OUT_MEM_TEST_OFST 4 5152 /* enum: Test has completed. */ 5153 #define MC_CMD_POLL_BIST_MEM_COMPLETE 0x0 5154 /* enum: RAM test - walk ones. */ 5155 #define MC_CMD_POLL_BIST_MEM_MEM_WALK_ONES 0x1 5156 /* enum: RAM test - walk zeros. */ 5157 #define MC_CMD_POLL_BIST_MEM_MEM_WALK_ZEROS 0x2 5158 /* enum: RAM test - walking inversions zeros/ones. */ 5159 #define MC_CMD_POLL_BIST_MEM_MEM_INV_ZERO_ONE 0x3 5160 /* enum: RAM test - walking inversions checkerboard. */ 5161 #define MC_CMD_POLL_BIST_MEM_MEM_INV_CHKBOARD 0x4 5162 /* enum: Register test - set / clear individual bits. */ 5163 #define MC_CMD_POLL_BIST_MEM_REG 0x5 5164 /* enum: ECC error detected. */ 5165 #define MC_CMD_POLL_BIST_MEM_ECC 0x6 5166 /* Failure address, only valid if result is POLL_BIST_FAILED */ 5167 #define MC_CMD_POLL_BIST_OUT_MEM_ADDR_OFST 8 5168 /* Bus or address space to which the failure address corresponds */ 5169 #define MC_CMD_POLL_BIST_OUT_MEM_BUS_OFST 12 5170 /* enum: MC MIPS bus. */ 5171 #define MC_CMD_POLL_BIST_MEM_BUS_MC 0x0 5172 /* enum: CSR IREG bus. */ 5173 #define MC_CMD_POLL_BIST_MEM_BUS_CSR 0x1 5174 /* enum: RX0 DPCPU bus. */ 5175 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_RX 0x2 5176 /* enum: TX0 DPCPU bus. */ 5177 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX0 0x3 5178 /* enum: TX1 DPCPU bus. */ 5179 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX1 0x4 5180 /* enum: RX0 DICPU bus. */ 5181 #define MC_CMD_POLL_BIST_MEM_BUS_DICPU_RX 0x5 5182 /* enum: TX DICPU bus. */ 5183 #define MC_CMD_POLL_BIST_MEM_BUS_DICPU_TX 0x6 5184 /* enum: RX1 DPCPU bus. */ 5185 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_RX1 0x7 5186 /* enum: RX1 DICPU bus. */ 5187 #define MC_CMD_POLL_BIST_MEM_BUS_DICPU_RX1 0x8 5188 /* Pattern written to RAM / register */ 5189 #define MC_CMD_POLL_BIST_OUT_MEM_EXPECT_OFST 16 5190 /* Actual value read from RAM / register */ 5191 #define MC_CMD_POLL_BIST_OUT_MEM_ACTUAL_OFST 20 5192 /* ECC error mask */ 5193 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_OFST 24 5194 /* ECC parity error mask */ 5195 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_PARITY_OFST 28 5196 /* ECC fatal error mask */ 5197 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_FATAL_OFST 32 5198 5199 5200 /***********************************/ 5201 /* MC_CMD_FLUSH_RX_QUEUES 5202 * Flush receive queue(s). If SRIOV is enabled (via MC_CMD_SRIOV), then RXQ 5203 * flushes should be initiated via this MCDI operation, rather than via 5204 * directly writing FLUSH_CMD. 5205 * 5206 * The flush is completed (either done/fail) asynchronously (after this command 5207 * returns). The driver must still wait for flush done/failure events as usual. 5208 */ 5209 #define MC_CMD_FLUSH_RX_QUEUES 0x27 5210 5211 /* MC_CMD_FLUSH_RX_QUEUES_IN msgrequest */ 5212 #define MC_CMD_FLUSH_RX_QUEUES_IN_LENMIN 4 5213 #define MC_CMD_FLUSH_RX_QUEUES_IN_LENMAX 252 5214 #define MC_CMD_FLUSH_RX_QUEUES_IN_LEN(num) (0+4*(num)) 5215 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_OFST 0 5216 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_LEN 4 5217 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MINNUM 1 5218 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MAXNUM 63 5219 5220 /* MC_CMD_FLUSH_RX_QUEUES_OUT msgresponse */ 5221 #define MC_CMD_FLUSH_RX_QUEUES_OUT_LEN 0 5222 5223 5224 /***********************************/ 5225 /* MC_CMD_GET_LOOPBACK_MODES 5226 * Returns a bitmask of loopback modes available at each speed. 5227 */ 5228 #define MC_CMD_GET_LOOPBACK_MODES 0x28 5229 #undef MC_CMD_0x28_PRIVILEGE_CTG 5230 5231 #define MC_CMD_0x28_PRIVILEGE_CTG SRIOV_CTG_GENERAL 5232 5233 /* MC_CMD_GET_LOOPBACK_MODES_IN msgrequest */ 5234 #define MC_CMD_GET_LOOPBACK_MODES_IN_LEN 0 5235 5236 /* MC_CMD_GET_LOOPBACK_MODES_OUT msgresponse */ 5237 #define MC_CMD_GET_LOOPBACK_MODES_OUT_LEN 40 5238 /* Supported loopbacks. */ 5239 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_OFST 0 5240 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LEN 8 5241 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_OFST 0 5242 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_OFST 4 5243 /* enum: None. */ 5244 #define MC_CMD_LOOPBACK_NONE 0x0 5245 /* enum: Data. */ 5246 #define MC_CMD_LOOPBACK_DATA 0x1 5247 /* enum: GMAC. */ 5248 #define MC_CMD_LOOPBACK_GMAC 0x2 5249 /* enum: XGMII. */ 5250 #define MC_CMD_LOOPBACK_XGMII 0x3 5251 /* enum: XGXS. */ 5252 #define MC_CMD_LOOPBACK_XGXS 0x4 5253 /* enum: XAUI. */ 5254 #define MC_CMD_LOOPBACK_XAUI 0x5 5255 /* enum: GMII. */ 5256 #define MC_CMD_LOOPBACK_GMII 0x6 5257 /* enum: SGMII. */ 5258 #define MC_CMD_LOOPBACK_SGMII 0x7 5259 /* enum: XGBR. */ 5260 #define MC_CMD_LOOPBACK_XGBR 0x8 5261 /* enum: XFI. */ 5262 #define MC_CMD_LOOPBACK_XFI 0x9 5263 /* enum: XAUI Far. */ 5264 #define MC_CMD_LOOPBACK_XAUI_FAR 0xa 5265 /* enum: GMII Far. */ 5266 #define MC_CMD_LOOPBACK_GMII_FAR 0xb 5267 /* enum: SGMII Far. */ 5268 #define MC_CMD_LOOPBACK_SGMII_FAR 0xc 5269 /* enum: XFI Far. */ 5270 #define MC_CMD_LOOPBACK_XFI_FAR 0xd 5271 /* enum: GPhy. */ 5272 #define MC_CMD_LOOPBACK_GPHY 0xe 5273 /* enum: PhyXS. */ 5274 #define MC_CMD_LOOPBACK_PHYXS 0xf 5275 /* enum: PCS. */ 5276 #define MC_CMD_LOOPBACK_PCS 0x10 5277 /* enum: PMA-PMD. */ 5278 #define MC_CMD_LOOPBACK_PMAPMD 0x11 5279 /* enum: Cross-Port. */ 5280 #define MC_CMD_LOOPBACK_XPORT 0x12 5281 /* enum: XGMII-Wireside. */ 5282 #define MC_CMD_LOOPBACK_XGMII_WS 0x13 5283 /* enum: XAUI Wireside. */ 5284 #define MC_CMD_LOOPBACK_XAUI_WS 0x14 5285 /* enum: XAUI Wireside Far. */ 5286 #define MC_CMD_LOOPBACK_XAUI_WS_FAR 0x15 5287 /* enum: XAUI Wireside near. */ 5288 #define MC_CMD_LOOPBACK_XAUI_WS_NEAR 0x16 5289 /* enum: GMII Wireside. */ 5290 #define MC_CMD_LOOPBACK_GMII_WS 0x17 5291 /* enum: XFI Wireside. */ 5292 #define MC_CMD_LOOPBACK_XFI_WS 0x18 5293 /* enum: XFI Wireside Far. */ 5294 #define MC_CMD_LOOPBACK_XFI_WS_FAR 0x19 5295 /* enum: PhyXS Wireside. */ 5296 #define MC_CMD_LOOPBACK_PHYXS_WS 0x1a 5297 /* enum: PMA lanes MAC-Serdes. */ 5298 #define MC_CMD_LOOPBACK_PMA_INT 0x1b 5299 /* enum: KR Serdes Parallel (Encoder). */ 5300 #define MC_CMD_LOOPBACK_SD_NEAR 0x1c 5301 /* enum: KR Serdes Serial. */ 5302 #define MC_CMD_LOOPBACK_SD_FAR 0x1d 5303 /* enum: PMA lanes MAC-Serdes Wireside. */ 5304 #define MC_CMD_LOOPBACK_PMA_INT_WS 0x1e 5305 /* enum: KR Serdes Parallel Wireside (Full PCS). */ 5306 #define MC_CMD_LOOPBACK_SD_FEP2_WS 0x1f 5307 /* enum: KR Serdes Parallel Wireside (Sym Aligner to TX). */ 5308 #define MC_CMD_LOOPBACK_SD_FEP1_5_WS 0x20 5309 /* enum: KR Serdes Parallel Wireside (Deserializer to Serializer). */ 5310 #define MC_CMD_LOOPBACK_SD_FEP_WS 0x21 5311 /* enum: KR Serdes Serial Wireside. */ 5312 #define MC_CMD_LOOPBACK_SD_FES_WS 0x22 5313 /* enum: Near side of AOE Siena side port */ 5314 #define MC_CMD_LOOPBACK_AOE_INT_NEAR 0x23 5315 /* enum: Medford Wireside datapath loopback */ 5316 #define MC_CMD_LOOPBACK_DATA_WS 0x24 5317 /* enum: Force link up without setting up any physical loopback (snapper use 5318 * only) 5319 */ 5320 #define MC_CMD_LOOPBACK_FORCE_EXT_LINK 0x25 5321 /* Supported loopbacks. */ 5322 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_OFST 8 5323 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LEN 8 5324 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LO_OFST 8 5325 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_HI_OFST 12 5326 /* Enum values, see field(s): */ 5327 /* 100M */ 5328 /* Supported loopbacks. */ 5329 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_OFST 16 5330 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LEN 8 5331 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LO_OFST 16 5332 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_HI_OFST 20 5333 /* Enum values, see field(s): */ 5334 /* 100M */ 5335 /* Supported loopbacks. */ 5336 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_OFST 24 5337 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LEN 8 5338 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LO_OFST 24 5339 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_HI_OFST 28 5340 /* Enum values, see field(s): */ 5341 /* 100M */ 5342 /* Supported loopbacks. */ 5343 #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_OFST 32 5344 #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LEN 8 5345 #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LO_OFST 32 5346 #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_HI_OFST 36 5347 /* Enum values, see field(s): */ 5348 /* 100M */ 5349 5350 5351 /***********************************/ 5352 /* MC_CMD_GET_LINK 5353 * Read the unified MAC/PHY link state. Locks required: None Return code: 0, 5354 * ETIME. 5355 */ 5356 #define MC_CMD_GET_LINK 0x29 5357 #undef MC_CMD_0x29_PRIVILEGE_CTG 5358 5359 #define MC_CMD_0x29_PRIVILEGE_CTG SRIOV_CTG_GENERAL 5360 5361 /* MC_CMD_GET_LINK_IN msgrequest */ 5362 #define MC_CMD_GET_LINK_IN_LEN 0 5363 5364 /* MC_CMD_GET_LINK_OUT msgresponse */ 5365 #define MC_CMD_GET_LINK_OUT_LEN 28 5366 /* near-side advertised capabilities */ 5367 #define MC_CMD_GET_LINK_OUT_CAP_OFST 0 5368 /* link-partner advertised capabilities */ 5369 #define MC_CMD_GET_LINK_OUT_LP_CAP_OFST 4 5370 /* Autonegotiated speed in mbit/s. The link may still be down even if this 5371 * reads non-zero. 5372 */ 5373 #define MC_CMD_GET_LINK_OUT_LINK_SPEED_OFST 8 5374 /* Current loopback setting. */ 5375 #define MC_CMD_GET_LINK_OUT_LOOPBACK_MODE_OFST 12 5376 /* Enum values, see field(s): */ 5377 /* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */ 5378 #define MC_CMD_GET_LINK_OUT_FLAGS_OFST 16 5379 #define MC_CMD_GET_LINK_OUT_LINK_UP_LBN 0 5380 #define MC_CMD_GET_LINK_OUT_LINK_UP_WIDTH 1 5381 #define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_LBN 1 5382 #define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_WIDTH 1 5383 #define MC_CMD_GET_LINK_OUT_BPX_LINK_LBN 2 5384 #define MC_CMD_GET_LINK_OUT_BPX_LINK_WIDTH 1 5385 #define MC_CMD_GET_LINK_OUT_PHY_LINK_LBN 3 5386 #define MC_CMD_GET_LINK_OUT_PHY_LINK_WIDTH 1 5387 #define MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_LBN 6 5388 #define MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_WIDTH 1 5389 #define MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_LBN 7 5390 #define MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_WIDTH 1 5391 /* This returns the negotiated flow control value. */ 5392 #define MC_CMD_GET_LINK_OUT_FCNTL_OFST 20 5393 /* Enum values, see field(s): */ 5394 /* MC_CMD_SET_MAC/MC_CMD_SET_MAC_IN/FCNTL */ 5395 #define MC_CMD_GET_LINK_OUT_MAC_FAULT_OFST 24 5396 #define MC_CMD_MAC_FAULT_XGMII_LOCAL_LBN 0 5397 #define MC_CMD_MAC_FAULT_XGMII_LOCAL_WIDTH 1 5398 #define MC_CMD_MAC_FAULT_XGMII_REMOTE_LBN 1 5399 #define MC_CMD_MAC_FAULT_XGMII_REMOTE_WIDTH 1 5400 #define MC_CMD_MAC_FAULT_SGMII_REMOTE_LBN 2 5401 #define MC_CMD_MAC_FAULT_SGMII_REMOTE_WIDTH 1 5402 #define MC_CMD_MAC_FAULT_PENDING_RECONFIG_LBN 3 5403 #define MC_CMD_MAC_FAULT_PENDING_RECONFIG_WIDTH 1 5404 5405 5406 /***********************************/ 5407 /* MC_CMD_SET_LINK 5408 * Write the unified MAC/PHY link configuration. Locks required: None. Return 5409 * code: 0, EINVAL, ETIME 5410 */ 5411 #define MC_CMD_SET_LINK 0x2a 5412 #undef MC_CMD_0x2a_PRIVILEGE_CTG 5413 5414 #define MC_CMD_0x2a_PRIVILEGE_CTG SRIOV_CTG_LINK 5415 5416 /* MC_CMD_SET_LINK_IN msgrequest */ 5417 #define MC_CMD_SET_LINK_IN_LEN 16 5418 /* ??? */ 5419 #define MC_CMD_SET_LINK_IN_CAP_OFST 0 5420 /* Flags */ 5421 #define MC_CMD_SET_LINK_IN_FLAGS_OFST 4 5422 #define MC_CMD_SET_LINK_IN_LOWPOWER_LBN 0 5423 #define MC_CMD_SET_LINK_IN_LOWPOWER_WIDTH 1 5424 #define MC_CMD_SET_LINK_IN_POWEROFF_LBN 1 5425 #define MC_CMD_SET_LINK_IN_POWEROFF_WIDTH 1 5426 #define MC_CMD_SET_LINK_IN_TXDIS_LBN 2 5427 #define MC_CMD_SET_LINK_IN_TXDIS_WIDTH 1 5428 /* Loopback mode. */ 5429 #define MC_CMD_SET_LINK_IN_LOOPBACK_MODE_OFST 8 5430 /* Enum values, see field(s): */ 5431 /* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */ 5432 /* A loopback speed of "0" is supported, and means (choose any available 5433 * speed). 5434 */ 5435 #define MC_CMD_SET_LINK_IN_LOOPBACK_SPEED_OFST 12 5436 5437 /* MC_CMD_SET_LINK_OUT msgresponse */ 5438 #define MC_CMD_SET_LINK_OUT_LEN 0 5439 5440 5441 /***********************************/ 5442 /* MC_CMD_SET_ID_LED 5443 * Set identification LED state. Locks required: None. Return code: 0, EINVAL 5444 */ 5445 #define MC_CMD_SET_ID_LED 0x2b 5446 #undef MC_CMD_0x2b_PRIVILEGE_CTG 5447 5448 #define MC_CMD_0x2b_PRIVILEGE_CTG SRIOV_CTG_LINK 5449 5450 /* MC_CMD_SET_ID_LED_IN msgrequest */ 5451 #define MC_CMD_SET_ID_LED_IN_LEN 4 5452 /* Set LED state. */ 5453 #define MC_CMD_SET_ID_LED_IN_STATE_OFST 0 5454 #define MC_CMD_LED_OFF 0x0 /* enum */ 5455 #define MC_CMD_LED_ON 0x1 /* enum */ 5456 #define MC_CMD_LED_DEFAULT 0x2 /* enum */ 5457 5458 /* MC_CMD_SET_ID_LED_OUT msgresponse */ 5459 #define MC_CMD_SET_ID_LED_OUT_LEN 0 5460 5461 5462 /***********************************/ 5463 /* MC_CMD_SET_MAC 5464 * Set MAC configuration. Locks required: None. Return code: 0, EINVAL 5465 */ 5466 #define MC_CMD_SET_MAC 0x2c 5467 #undef MC_CMD_0x2c_PRIVILEGE_CTG 5468 5469 #define MC_CMD_0x2c_PRIVILEGE_CTG SRIOV_CTG_GENERAL 5470 5471 /* MC_CMD_SET_MAC_IN msgrequest */ 5472 #define MC_CMD_SET_MAC_IN_LEN 28 5473 /* The MTU is the MTU programmed directly into the XMAC/GMAC (inclusive of 5474 * EtherII, VLAN, bug16011 padding). 5475 */ 5476 #define MC_CMD_SET_MAC_IN_MTU_OFST 0 5477 #define MC_CMD_SET_MAC_IN_DRAIN_OFST 4 5478 #define MC_CMD_SET_MAC_IN_ADDR_OFST 8 5479 #define MC_CMD_SET_MAC_IN_ADDR_LEN 8 5480 #define MC_CMD_SET_MAC_IN_ADDR_LO_OFST 8 5481 #define MC_CMD_SET_MAC_IN_ADDR_HI_OFST 12 5482 #define MC_CMD_SET_MAC_IN_REJECT_OFST 16 5483 #define MC_CMD_SET_MAC_IN_REJECT_UNCST_LBN 0 5484 #define MC_CMD_SET_MAC_IN_REJECT_UNCST_WIDTH 1 5485 #define MC_CMD_SET_MAC_IN_REJECT_BRDCST_LBN 1 5486 #define MC_CMD_SET_MAC_IN_REJECT_BRDCST_WIDTH 1 5487 #define MC_CMD_SET_MAC_IN_FCNTL_OFST 20 5488 /* enum: Flow control is off. */ 5489 #define MC_CMD_FCNTL_OFF 0x0 5490 /* enum: Respond to flow control. */ 5491 #define MC_CMD_FCNTL_RESPOND 0x1 5492 /* enum: Respond to and Issue flow control. */ 5493 #define MC_CMD_FCNTL_BIDIR 0x2 5494 /* enum: Auto neg flow control. */ 5495 #define MC_CMD_FCNTL_AUTO 0x3 5496 /* enum: Priority flow control (eftest builds only). */ 5497 #define MC_CMD_FCNTL_QBB 0x4 5498 /* enum: Issue flow control. */ 5499 #define MC_CMD_FCNTL_GENERATE 0x5 5500 #define MC_CMD_SET_MAC_IN_FLAGS_OFST 24 5501 #define MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_LBN 0 5502 #define MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_WIDTH 1 5503 5504 /* MC_CMD_SET_MAC_EXT_IN msgrequest */ 5505 #define MC_CMD_SET_MAC_EXT_IN_LEN 32 5506 /* The MTU is the MTU programmed directly into the XMAC/GMAC (inclusive of 5507 * EtherII, VLAN, bug16011 padding). 5508 */ 5509 #define MC_CMD_SET_MAC_EXT_IN_MTU_OFST 0 5510 #define MC_CMD_SET_MAC_EXT_IN_DRAIN_OFST 4 5511 #define MC_CMD_SET_MAC_EXT_IN_ADDR_OFST 8 5512 #define MC_CMD_SET_MAC_EXT_IN_ADDR_LEN 8 5513 #define MC_CMD_SET_MAC_EXT_IN_ADDR_LO_OFST 8 5514 #define MC_CMD_SET_MAC_EXT_IN_ADDR_HI_OFST 12 5515 #define MC_CMD_SET_MAC_EXT_IN_REJECT_OFST 16 5516 #define MC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_LBN 0 5517 #define MC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_WIDTH 1 5518 #define MC_CMD_SET_MAC_EXT_IN_REJECT_BRDCST_LBN 1 5519 #define MC_CMD_SET_MAC_EXT_IN_REJECT_BRDCST_WIDTH 1 5520 #define MC_CMD_SET_MAC_EXT_IN_FCNTL_OFST 20 5521 /* enum: Flow control is off. */ 5522 /* MC_CMD_FCNTL_OFF 0x0 */ 5523 /* enum: Respond to flow control. */ 5524 /* MC_CMD_FCNTL_RESPOND 0x1 */ 5525 /* enum: Respond to and Issue flow control. */ 5526 /* MC_CMD_FCNTL_BIDIR 0x2 */ 5527 /* enum: Auto neg flow control. */ 5528 /* MC_CMD_FCNTL_AUTO 0x3 */ 5529 /* enum: Priority flow control (eftest builds only). */ 5530 /* MC_CMD_FCNTL_QBB 0x4 */ 5531 /* enum: Issue flow control. */ 5532 /* MC_CMD_FCNTL_GENERATE 0x5 */ 5533 #define MC_CMD_SET_MAC_EXT_IN_FLAGS_OFST 24 5534 #define MC_CMD_SET_MAC_EXT_IN_FLAG_INCLUDE_FCS_LBN 0 5535 #define MC_CMD_SET_MAC_EXT_IN_FLAG_INCLUDE_FCS_WIDTH 1 5536 /* Select which parameters to configure. A parameter will only be modified if 5537 * the corresponding control flag is set. If SET_MAC_ENHANCED is not set in 5538 * capabilities then this field is ignored (and all flags are assumed to be 5539 * set). 5540 */ 5541 #define MC_CMD_SET_MAC_EXT_IN_CONTROL_OFST 28 5542 #define MC_CMD_SET_MAC_EXT_IN_CFG_MTU_LBN 0 5543 #define MC_CMD_SET_MAC_EXT_IN_CFG_MTU_WIDTH 1 5544 #define MC_CMD_SET_MAC_EXT_IN_CFG_DRAIN_LBN 1 5545 #define MC_CMD_SET_MAC_EXT_IN_CFG_DRAIN_WIDTH 1 5546 #define MC_CMD_SET_MAC_EXT_IN_CFG_REJECT_LBN 2 5547 #define MC_CMD_SET_MAC_EXT_IN_CFG_REJECT_WIDTH 1 5548 #define MC_CMD_SET_MAC_EXT_IN_CFG_FCNTL_LBN 3 5549 #define MC_CMD_SET_MAC_EXT_IN_CFG_FCNTL_WIDTH 1 5550 #define MC_CMD_SET_MAC_EXT_IN_CFG_FCS_LBN 4 5551 #define MC_CMD_SET_MAC_EXT_IN_CFG_FCS_WIDTH 1 5552 5553 /* MC_CMD_SET_MAC_OUT msgresponse */ 5554 #define MC_CMD_SET_MAC_OUT_LEN 0 5555 5556 /* MC_CMD_SET_MAC_V2_OUT msgresponse */ 5557 #define MC_CMD_SET_MAC_V2_OUT_LEN 4 5558 /* MTU as configured after processing the request. See comment at 5559 * MC_CMD_SET_MAC_IN/MTU. To query MTU without doing any changes, set CONTROL 5560 * to 0. 5561 */ 5562 #define MC_CMD_SET_MAC_V2_OUT_MTU_OFST 0 5563 5564 5565 /***********************************/ 5566 /* MC_CMD_PHY_STATS 5567 * Get generic PHY statistics. This call returns the statistics for a generic 5568 * PHY in a sparse array (indexed by the enumerate). Each value is represented 5569 * by a 32bit number. If the DMA_ADDR is 0, then no DMA is performed, and the 5570 * statistics may be read from the message response. If DMA_ADDR != 0, then the 5571 * statistics are dmad to that (page-aligned location). Locks required: None. 5572 * Returns: 0, ETIME 5573 */ 5574 #define MC_CMD_PHY_STATS 0x2d 5575 #undef MC_CMD_0x2d_PRIVILEGE_CTG 5576 5577 #define MC_CMD_0x2d_PRIVILEGE_CTG SRIOV_CTG_LINK 5578 5579 /* MC_CMD_PHY_STATS_IN msgrequest */ 5580 #define MC_CMD_PHY_STATS_IN_LEN 8 5581 /* ??? */ 5582 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_OFST 0 5583 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_LEN 8 5584 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_OFST 0 5585 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_HI_OFST 4 5586 5587 /* MC_CMD_PHY_STATS_OUT_DMA msgresponse */ 5588 #define MC_CMD_PHY_STATS_OUT_DMA_LEN 0 5589 5590 /* MC_CMD_PHY_STATS_OUT_NO_DMA msgresponse */ 5591 #define MC_CMD_PHY_STATS_OUT_NO_DMA_LEN (((MC_CMD_PHY_NSTATS*32))>>3) 5592 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_OFST 0 5593 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_LEN 4 5594 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_PHY_NSTATS 5595 /* enum: OUI. */ 5596 #define MC_CMD_OUI 0x0 5597 /* enum: PMA-PMD Link Up. */ 5598 #define MC_CMD_PMA_PMD_LINK_UP 0x1 5599 /* enum: PMA-PMD RX Fault. */ 5600 #define MC_CMD_PMA_PMD_RX_FAULT 0x2 5601 /* enum: PMA-PMD TX Fault. */ 5602 #define MC_CMD_PMA_PMD_TX_FAULT 0x3 5603 /* enum: PMA-PMD Signal */ 5604 #define MC_CMD_PMA_PMD_SIGNAL 0x4 5605 /* enum: PMA-PMD SNR A. */ 5606 #define MC_CMD_PMA_PMD_SNR_A 0x5 5607 /* enum: PMA-PMD SNR B. */ 5608 #define MC_CMD_PMA_PMD_SNR_B 0x6 5609 /* enum: PMA-PMD SNR C. */ 5610 #define MC_CMD_PMA_PMD_SNR_C 0x7 5611 /* enum: PMA-PMD SNR D. */ 5612 #define MC_CMD_PMA_PMD_SNR_D 0x8 5613 /* enum: PCS Link Up. */ 5614 #define MC_CMD_PCS_LINK_UP 0x9 5615 /* enum: PCS RX Fault. */ 5616 #define MC_CMD_PCS_RX_FAULT 0xa 5617 /* enum: PCS TX Fault. */ 5618 #define MC_CMD_PCS_TX_FAULT 0xb 5619 /* enum: PCS BER. */ 5620 #define MC_CMD_PCS_BER 0xc 5621 /* enum: PCS Block Errors. */ 5622 #define MC_CMD_PCS_BLOCK_ERRORS 0xd 5623 /* enum: PhyXS Link Up. */ 5624 #define MC_CMD_PHYXS_LINK_UP 0xe 5625 /* enum: PhyXS RX Fault. */ 5626 #define MC_CMD_PHYXS_RX_FAULT 0xf 5627 /* enum: PhyXS TX Fault. */ 5628 #define MC_CMD_PHYXS_TX_FAULT 0x10 5629 /* enum: PhyXS Align. */ 5630 #define MC_CMD_PHYXS_ALIGN 0x11 5631 /* enum: PhyXS Sync. */ 5632 #define MC_CMD_PHYXS_SYNC 0x12 5633 /* enum: AN link-up. */ 5634 #define MC_CMD_AN_LINK_UP 0x13 5635 /* enum: AN Complete. */ 5636 #define MC_CMD_AN_COMPLETE 0x14 5637 /* enum: AN 10GBaseT Status. */ 5638 #define MC_CMD_AN_10GBT_STATUS 0x15 5639 /* enum: Clause 22 Link-Up. */ 5640 #define MC_CMD_CL22_LINK_UP 0x16 5641 /* enum: (Last entry) */ 5642 #define MC_CMD_PHY_NSTATS 0x17 5643 5644 5645 /***********************************/ 5646 /* MC_CMD_MAC_STATS 5647 * Get generic MAC statistics. This call returns unified statistics maintained 5648 * by the MC as it switches between the GMAC and XMAC. The MC will write out 5649 * all supported stats. The driver should zero initialise the buffer to 5650 * guarantee consistent results. If the DMA_ADDR is 0, then no DMA is 5651 * performed, and the statistics may be read from the message response. If 5652 * DMA_ADDR != 0, then the statistics are dmad to that (page-aligned location). 5653 * Locks required: None. The PERIODIC_CLEAR option is not used and now has no 5654 * effect. Returns: 0, ETIME 5655 */ 5656 #define MC_CMD_MAC_STATS 0x2e 5657 #undef MC_CMD_0x2e_PRIVILEGE_CTG 5658 5659 #define MC_CMD_0x2e_PRIVILEGE_CTG SRIOV_CTG_GENERAL 5660 5661 /* MC_CMD_MAC_STATS_IN msgrequest */ 5662 #define MC_CMD_MAC_STATS_IN_LEN 20 5663 /* ??? */ 5664 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_OFST 0 5665 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_LEN 8 5666 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_OFST 0 5667 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_OFST 4 5668 #define MC_CMD_MAC_STATS_IN_CMD_OFST 8 5669 #define MC_CMD_MAC_STATS_IN_DMA_LBN 0 5670 #define MC_CMD_MAC_STATS_IN_DMA_WIDTH 1 5671 #define MC_CMD_MAC_STATS_IN_CLEAR_LBN 1 5672 #define MC_CMD_MAC_STATS_IN_CLEAR_WIDTH 1 5673 #define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_LBN 2 5674 #define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_WIDTH 1 5675 #define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_LBN 3 5676 #define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_WIDTH 1 5677 #define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_LBN 4 5678 #define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_WIDTH 1 5679 #define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_LBN 5 5680 #define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_WIDTH 1 5681 #define MC_CMD_MAC_STATS_IN_PERIOD_MS_LBN 16 5682 #define MC_CMD_MAC_STATS_IN_PERIOD_MS_WIDTH 16 5683 #define MC_CMD_MAC_STATS_IN_DMA_LEN_OFST 12 5684 /* port id so vadapter stats can be provided */ 5685 #define MC_CMD_MAC_STATS_IN_PORT_ID_OFST 16 5686 5687 /* MC_CMD_MAC_STATS_OUT_DMA msgresponse */ 5688 #define MC_CMD_MAC_STATS_OUT_DMA_LEN 0 5689 5690 /* MC_CMD_MAC_STATS_OUT_NO_DMA msgresponse */ 5691 #define MC_CMD_MAC_STATS_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS*64))>>3) 5692 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_OFST 0 5693 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LEN 8 5694 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_OFST 0 5695 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_OFST 4 5696 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS 5697 #define MC_CMD_MAC_GENERATION_START 0x0 /* enum */ 5698 #define MC_CMD_MAC_DMABUF_START 0x1 /* enum */ 5699 #define MC_CMD_MAC_TX_PKTS 0x1 /* enum */ 5700 #define MC_CMD_MAC_TX_PAUSE_PKTS 0x2 /* enum */ 5701 #define MC_CMD_MAC_TX_CONTROL_PKTS 0x3 /* enum */ 5702 #define MC_CMD_MAC_TX_UNICAST_PKTS 0x4 /* enum */ 5703 #define MC_CMD_MAC_TX_MULTICAST_PKTS 0x5 /* enum */ 5704 #define MC_CMD_MAC_TX_BROADCAST_PKTS 0x6 /* enum */ 5705 #define MC_CMD_MAC_TX_BYTES 0x7 /* enum */ 5706 #define MC_CMD_MAC_TX_BAD_BYTES 0x8 /* enum */ 5707 #define MC_CMD_MAC_TX_LT64_PKTS 0x9 /* enum */ 5708 #define MC_CMD_MAC_TX_64_PKTS 0xa /* enum */ 5709 #define MC_CMD_MAC_TX_65_TO_127_PKTS 0xb /* enum */ 5710 #define MC_CMD_MAC_TX_128_TO_255_PKTS 0xc /* enum */ 5711 #define MC_CMD_MAC_TX_256_TO_511_PKTS 0xd /* enum */ 5712 #define MC_CMD_MAC_TX_512_TO_1023_PKTS 0xe /* enum */ 5713 #define MC_CMD_MAC_TX_1024_TO_15XX_PKTS 0xf /* enum */ 5714 #define MC_CMD_MAC_TX_15XX_TO_JUMBO_PKTS 0x10 /* enum */ 5715 #define MC_CMD_MAC_TX_GTJUMBO_PKTS 0x11 /* enum */ 5716 #define MC_CMD_MAC_TX_BAD_FCS_PKTS 0x12 /* enum */ 5717 #define MC_CMD_MAC_TX_SINGLE_COLLISION_PKTS 0x13 /* enum */ 5718 #define MC_CMD_MAC_TX_MULTIPLE_COLLISION_PKTS 0x14 /* enum */ 5719 #define MC_CMD_MAC_TX_EXCESSIVE_COLLISION_PKTS 0x15 /* enum */ 5720 #define MC_CMD_MAC_TX_LATE_COLLISION_PKTS 0x16 /* enum */ 5721 #define MC_CMD_MAC_TX_DEFERRED_PKTS 0x17 /* enum */ 5722 #define MC_CMD_MAC_TX_EXCESSIVE_DEFERRED_PKTS 0x18 /* enum */ 5723 #define MC_CMD_MAC_TX_NON_TCPUDP_PKTS 0x19 /* enum */ 5724 #define MC_CMD_MAC_TX_MAC_SRC_ERR_PKTS 0x1a /* enum */ 5725 #define MC_CMD_MAC_TX_IP_SRC_ERR_PKTS 0x1b /* enum */ 5726 #define MC_CMD_MAC_RX_PKTS 0x1c /* enum */ 5727 #define MC_CMD_MAC_RX_PAUSE_PKTS 0x1d /* enum */ 5728 #define MC_CMD_MAC_RX_GOOD_PKTS 0x1e /* enum */ 5729 #define MC_CMD_MAC_RX_CONTROL_PKTS 0x1f /* enum */ 5730 #define MC_CMD_MAC_RX_UNICAST_PKTS 0x20 /* enum */ 5731 #define MC_CMD_MAC_RX_MULTICAST_PKTS 0x21 /* enum */ 5732 #define MC_CMD_MAC_RX_BROADCAST_PKTS 0x22 /* enum */ 5733 #define MC_CMD_MAC_RX_BYTES 0x23 /* enum */ 5734 #define MC_CMD_MAC_RX_BAD_BYTES 0x24 /* enum */ 5735 #define MC_CMD_MAC_RX_64_PKTS 0x25 /* enum */ 5736 #define MC_CMD_MAC_RX_65_TO_127_PKTS 0x26 /* enum */ 5737 #define MC_CMD_MAC_RX_128_TO_255_PKTS 0x27 /* enum */ 5738 #define MC_CMD_MAC_RX_256_TO_511_PKTS 0x28 /* enum */ 5739 #define MC_CMD_MAC_RX_512_TO_1023_PKTS 0x29 /* enum */ 5740 #define MC_CMD_MAC_RX_1024_TO_15XX_PKTS 0x2a /* enum */ 5741 #define MC_CMD_MAC_RX_15XX_TO_JUMBO_PKTS 0x2b /* enum */ 5742 #define MC_CMD_MAC_RX_GTJUMBO_PKTS 0x2c /* enum */ 5743 #define MC_CMD_MAC_RX_UNDERSIZE_PKTS 0x2d /* enum */ 5744 #define MC_CMD_MAC_RX_BAD_FCS_PKTS 0x2e /* enum */ 5745 #define MC_CMD_MAC_RX_OVERFLOW_PKTS 0x2f /* enum */ 5746 #define MC_CMD_MAC_RX_FALSE_CARRIER_PKTS 0x30 /* enum */ 5747 #define MC_CMD_MAC_RX_SYMBOL_ERROR_PKTS 0x31 /* enum */ 5748 #define MC_CMD_MAC_RX_ALIGN_ERROR_PKTS 0x32 /* enum */ 5749 #define MC_CMD_MAC_RX_LENGTH_ERROR_PKTS 0x33 /* enum */ 5750 #define MC_CMD_MAC_RX_INTERNAL_ERROR_PKTS 0x34 /* enum */ 5751 #define MC_CMD_MAC_RX_JABBER_PKTS 0x35 /* enum */ 5752 #define MC_CMD_MAC_RX_NODESC_DROPS 0x36 /* enum */ 5753 #define MC_CMD_MAC_RX_LANES01_CHAR_ERR 0x37 /* enum */ 5754 #define MC_CMD_MAC_RX_LANES23_CHAR_ERR 0x38 /* enum */ 5755 #define MC_CMD_MAC_RX_LANES01_DISP_ERR 0x39 /* enum */ 5756 #define MC_CMD_MAC_RX_LANES23_DISP_ERR 0x3a /* enum */ 5757 #define MC_CMD_MAC_RX_MATCH_FAULT 0x3b /* enum */ 5758 /* enum: PM trunc_bb_overflow counter. Valid for EF10 with PM_AND_RXDP_COUNTERS 5759 * capability only. 5760 */ 5761 #define MC_CMD_MAC_PM_TRUNC_BB_OVERFLOW 0x3c 5762 /* enum: PM discard_bb_overflow counter. Valid for EF10 with 5763 * PM_AND_RXDP_COUNTERS capability only. 5764 */ 5765 #define MC_CMD_MAC_PM_DISCARD_BB_OVERFLOW 0x3d 5766 /* enum: PM trunc_vfifo_full counter. Valid for EF10 with PM_AND_RXDP_COUNTERS 5767 * capability only. 5768 */ 5769 #define MC_CMD_MAC_PM_TRUNC_VFIFO_FULL 0x3e 5770 /* enum: PM discard_vfifo_full counter. Valid for EF10 with 5771 * PM_AND_RXDP_COUNTERS capability only. 5772 */ 5773 #define MC_CMD_MAC_PM_DISCARD_VFIFO_FULL 0x3f 5774 /* enum: PM trunc_qbb counter. Valid for EF10 with PM_AND_RXDP_COUNTERS 5775 * capability only. 5776 */ 5777 #define MC_CMD_MAC_PM_TRUNC_QBB 0x40 5778 /* enum: PM discard_qbb counter. Valid for EF10 with PM_AND_RXDP_COUNTERS 5779 * capability only. 5780 */ 5781 #define MC_CMD_MAC_PM_DISCARD_QBB 0x41 5782 /* enum: PM discard_mapping counter. Valid for EF10 with PM_AND_RXDP_COUNTERS 5783 * capability only. 5784 */ 5785 #define MC_CMD_MAC_PM_DISCARD_MAPPING 0x42 5786 /* enum: RXDP counter: Number of packets dropped due to the queue being 5787 * disabled. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only. 5788 */ 5789 #define MC_CMD_MAC_RXDP_Q_DISABLED_PKTS 0x43 5790 /* enum: RXDP counter: Number of packets dropped by the DICPU. Valid for EF10 5791 * with PM_AND_RXDP_COUNTERS capability only. 5792 */ 5793 #define MC_CMD_MAC_RXDP_DI_DROPPED_PKTS 0x45 5794 /* enum: RXDP counter: Number of non-host packets. Valid for EF10 with 5795 * PM_AND_RXDP_COUNTERS capability only. 5796 */ 5797 #define MC_CMD_MAC_RXDP_STREAMING_PKTS 0x46 5798 /* enum: RXDP counter: Number of times an hlb descriptor fetch was performed. 5799 * Valid for EF10 with PM_AND_RXDP_COUNTERS capability only. 5800 */ 5801 #define MC_CMD_MAC_RXDP_HLB_FETCH_CONDITIONS 0x47 5802 /* enum: RXDP counter: Number of times the DPCPU waited for an existing 5803 * descriptor fetch. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only. 5804 */ 5805 #define MC_CMD_MAC_RXDP_HLB_WAIT_CONDITIONS 0x48 5806 #define MC_CMD_MAC_VADAPTER_RX_DMABUF_START 0x4c /* enum */ 5807 #define MC_CMD_MAC_VADAPTER_RX_UNICAST_PACKETS 0x4c /* enum */ 5808 #define MC_CMD_MAC_VADAPTER_RX_UNICAST_BYTES 0x4d /* enum */ 5809 #define MC_CMD_MAC_VADAPTER_RX_MULTICAST_PACKETS 0x4e /* enum */ 5810 #define MC_CMD_MAC_VADAPTER_RX_MULTICAST_BYTES 0x4f /* enum */ 5811 #define MC_CMD_MAC_VADAPTER_RX_BROADCAST_PACKETS 0x50 /* enum */ 5812 #define MC_CMD_MAC_VADAPTER_RX_BROADCAST_BYTES 0x51 /* enum */ 5813 #define MC_CMD_MAC_VADAPTER_RX_BAD_PACKETS 0x52 /* enum */ 5814 #define MC_CMD_MAC_VADAPTER_RX_BAD_BYTES 0x53 /* enum */ 5815 #define MC_CMD_MAC_VADAPTER_RX_OVERFLOW 0x54 /* enum */ 5816 #define MC_CMD_MAC_VADAPTER_TX_DMABUF_START 0x57 /* enum */ 5817 #define MC_CMD_MAC_VADAPTER_TX_UNICAST_PACKETS 0x57 /* enum */ 5818 #define MC_CMD_MAC_VADAPTER_TX_UNICAST_BYTES 0x58 /* enum */ 5819 #define MC_CMD_MAC_VADAPTER_TX_MULTICAST_PACKETS 0x59 /* enum */ 5820 #define MC_CMD_MAC_VADAPTER_TX_MULTICAST_BYTES 0x5a /* enum */ 5821 #define MC_CMD_MAC_VADAPTER_TX_BROADCAST_PACKETS 0x5b /* enum */ 5822 #define MC_CMD_MAC_VADAPTER_TX_BROADCAST_BYTES 0x5c /* enum */ 5823 #define MC_CMD_MAC_VADAPTER_TX_BAD_PACKETS 0x5d /* enum */ 5824 #define MC_CMD_MAC_VADAPTER_TX_BAD_BYTES 0x5e /* enum */ 5825 #define MC_CMD_MAC_VADAPTER_TX_OVERFLOW 0x5f /* enum */ 5826 /* enum: Start of GMAC stats buffer space, for Siena only. */ 5827 #define MC_CMD_GMAC_DMABUF_START 0x40 5828 /* enum: End of GMAC stats buffer space, for Siena only. */ 5829 #define MC_CMD_GMAC_DMABUF_END 0x5f 5830 #define MC_CMD_MAC_GENERATION_END 0x60 /* enum */ 5831 #define MC_CMD_MAC_NSTATS 0x61 /* enum */ 5832 5833 5834 /***********************************/ 5835 /* MC_CMD_SRIOV 5836 * to be documented 5837 */ 5838 #define MC_CMD_SRIOV 0x30 5839 5840 /* MC_CMD_SRIOV_IN msgrequest */ 5841 #define MC_CMD_SRIOV_IN_LEN 12 5842 #define MC_CMD_SRIOV_IN_ENABLE_OFST 0 5843 #define MC_CMD_SRIOV_IN_VI_BASE_OFST 4 5844 #define MC_CMD_SRIOV_IN_VF_COUNT_OFST 8 5845 5846 /* MC_CMD_SRIOV_OUT msgresponse */ 5847 #define MC_CMD_SRIOV_OUT_LEN 8 5848 #define MC_CMD_SRIOV_OUT_VI_SCALE_OFST 0 5849 #define MC_CMD_SRIOV_OUT_VF_TOTAL_OFST 4 5850 5851 /* MC_CMD_MEMCPY_RECORD_TYPEDEF structuredef */ 5852 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LEN 32 5853 /* this is only used for the first record */ 5854 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_OFST 0 5855 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_LBN 0 5856 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_WIDTH 32 5857 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_OFST 4 5858 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_LBN 32 5859 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_WIDTH 32 5860 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_OFST 8 5861 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LEN 8 5862 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LO_OFST 8 5863 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_HI_OFST 12 5864 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LBN 64 5865 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_WIDTH 64 5866 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_OFST 16 5867 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_RID_INLINE 0x100 /* enum */ 5868 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_LBN 128 5869 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_WIDTH 32 5870 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_OFST 20 5871 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LEN 8 5872 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LO_OFST 20 5873 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_HI_OFST 24 5874 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LBN 160 5875 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_WIDTH 64 5876 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_OFST 28 5877 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_LBN 224 5878 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_WIDTH 32 5879 5880 5881 /***********************************/ 5882 /* MC_CMD_MEMCPY 5883 * DMA write data into (Rid,Addr), either by dma reading (Rid,Addr), or by data 5884 * embedded directly in the command. 5885 * 5886 * A common pattern is for a client to use generation counts to signal a dma 5887 * update of a datastructure. To facilitate this, this MCDI operation can 5888 * contain multiple requests which are executed in strict order. Requests take 5889 * the form of duplicating the entire MCDI request continuously (including the 5890 * requests record, which is ignored in all but the first structure) 5891 * 5892 * The source data can either come from a DMA from the host, or it can be 5893 * embedded within the request directly, thereby eliminating a DMA read. To 5894 * indicate this, the client sets FROM_RID=%RID_INLINE, ADDR_HI=0, and 5895 * ADDR_LO=offset, and inserts the data at %offset from the start of the 5896 * payload. It's the callers responsibility to ensure that the embedded data 5897 * doesn't overlap the records. 5898 * 5899 * Returns: 0, EINVAL (invalid RID) 5900 */ 5901 #define MC_CMD_MEMCPY 0x31 5902 5903 /* MC_CMD_MEMCPY_IN msgrequest */ 5904 #define MC_CMD_MEMCPY_IN_LENMIN 32 5905 #define MC_CMD_MEMCPY_IN_LENMAX 224 5906 #define MC_CMD_MEMCPY_IN_LEN(num) (0+32*(num)) 5907 /* see MC_CMD_MEMCPY_RECORD_TYPEDEF */ 5908 #define MC_CMD_MEMCPY_IN_RECORD_OFST 0 5909 #define MC_CMD_MEMCPY_IN_RECORD_LEN 32 5910 #define MC_CMD_MEMCPY_IN_RECORD_MINNUM 1 5911 #define MC_CMD_MEMCPY_IN_RECORD_MAXNUM 7 5912 5913 /* MC_CMD_MEMCPY_OUT msgresponse */ 5914 #define MC_CMD_MEMCPY_OUT_LEN 0 5915 5916 5917 /***********************************/ 5918 /* MC_CMD_WOL_FILTER_SET 5919 * Set a WoL filter. 5920 */ 5921 #define MC_CMD_WOL_FILTER_SET 0x32 5922 #undef MC_CMD_0x32_PRIVILEGE_CTG 5923 5924 #define MC_CMD_0x32_PRIVILEGE_CTG SRIOV_CTG_LINK 5925 5926 /* MC_CMD_WOL_FILTER_SET_IN msgrequest */ 5927 #define MC_CMD_WOL_FILTER_SET_IN_LEN 192 5928 #define MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 5929 #define MC_CMD_FILTER_MODE_SIMPLE 0x0 /* enum */ 5930 #define MC_CMD_FILTER_MODE_STRUCTURED 0xffffffff /* enum */ 5931 /* A type value of 1 is unused. */ 5932 #define MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 5933 /* enum: Magic */ 5934 #define MC_CMD_WOL_TYPE_MAGIC 0x0 5935 /* enum: MS Windows Magic */ 5936 #define MC_CMD_WOL_TYPE_WIN_MAGIC 0x2 5937 /* enum: IPv4 Syn */ 5938 #define MC_CMD_WOL_TYPE_IPV4_SYN 0x3 5939 /* enum: IPv6 Syn */ 5940 #define MC_CMD_WOL_TYPE_IPV6_SYN 0x4 5941 /* enum: Bitmap */ 5942 #define MC_CMD_WOL_TYPE_BITMAP 0x5 5943 /* enum: Link */ 5944 #define MC_CMD_WOL_TYPE_LINK 0x6 5945 /* enum: (Above this for future use) */ 5946 #define MC_CMD_WOL_TYPE_MAX 0x7 5947 #define MC_CMD_WOL_FILTER_SET_IN_DATA_OFST 8 5948 #define MC_CMD_WOL_FILTER_SET_IN_DATA_LEN 4 5949 #define MC_CMD_WOL_FILTER_SET_IN_DATA_NUM 46 5950 5951 /* MC_CMD_WOL_FILTER_SET_IN_MAGIC msgrequest */ 5952 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_LEN 16 5953 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 5954 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 5955 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_OFST 8 5956 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LEN 8 5957 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LO_OFST 8 5958 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_HI_OFST 12 5959 5960 /* MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN msgrequest */ 5961 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_LEN 20 5962 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 5963 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 5964 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_IP_OFST 8 5965 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_IP_OFST 12 5966 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_OFST 16 5967 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_LEN 2 5968 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_OFST 18 5969 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_LEN 2 5970 5971 /* MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN msgrequest */ 5972 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_LEN 44 5973 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 5974 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 5975 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_OFST 8 5976 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_LEN 16 5977 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_OFST 24 5978 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_LEN 16 5979 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_OFST 40 5980 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_LEN 2 5981 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_OFST 42 5982 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_LEN 2 5983 5984 /* MC_CMD_WOL_FILTER_SET_IN_BITMAP msgrequest */ 5985 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN 187 5986 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 5987 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 5988 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_OFST 8 5989 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_LEN 48 5990 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_OFST 56 5991 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_LEN 128 5992 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_OFST 184 5993 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_LEN 1 5994 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_OFST 185 5995 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_LEN 1 5996 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_OFST 186 5997 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_LEN 1 5998 5999 /* MC_CMD_WOL_FILTER_SET_IN_LINK msgrequest */ 6000 #define MC_CMD_WOL_FILTER_SET_IN_LINK_LEN 12 6001 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 6002 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 6003 #define MC_CMD_WOL_FILTER_SET_IN_LINK_MASK_OFST 8 6004 #define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_LBN 0 6005 #define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_WIDTH 1 6006 #define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_LBN 1 6007 #define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_WIDTH 1 6008 6009 /* MC_CMD_WOL_FILTER_SET_OUT msgresponse */ 6010 #define MC_CMD_WOL_FILTER_SET_OUT_LEN 4 6011 #define MC_CMD_WOL_FILTER_SET_OUT_FILTER_ID_OFST 0 6012 6013 6014 /***********************************/ 6015 /* MC_CMD_WOL_FILTER_REMOVE 6016 * Remove a WoL filter. Locks required: None. Returns: 0, EINVAL, ENOSYS 6017 */ 6018 #define MC_CMD_WOL_FILTER_REMOVE 0x33 6019 #undef MC_CMD_0x33_PRIVILEGE_CTG 6020 6021 #define MC_CMD_0x33_PRIVILEGE_CTG SRIOV_CTG_LINK 6022 6023 /* MC_CMD_WOL_FILTER_REMOVE_IN msgrequest */ 6024 #define MC_CMD_WOL_FILTER_REMOVE_IN_LEN 4 6025 #define MC_CMD_WOL_FILTER_REMOVE_IN_FILTER_ID_OFST 0 6026 6027 /* MC_CMD_WOL_FILTER_REMOVE_OUT msgresponse */ 6028 #define MC_CMD_WOL_FILTER_REMOVE_OUT_LEN 0 6029 6030 6031 /***********************************/ 6032 /* MC_CMD_WOL_FILTER_RESET 6033 * Reset (i.e. remove all) WoL filters. Locks required: None. Returns: 0, 6034 * ENOSYS 6035 */ 6036 #define MC_CMD_WOL_FILTER_RESET 0x34 6037 #undef MC_CMD_0x34_PRIVILEGE_CTG 6038 6039 #define MC_CMD_0x34_PRIVILEGE_CTG SRIOV_CTG_LINK 6040 6041 /* MC_CMD_WOL_FILTER_RESET_IN msgrequest */ 6042 #define MC_CMD_WOL_FILTER_RESET_IN_LEN 4 6043 #define MC_CMD_WOL_FILTER_RESET_IN_MASK_OFST 0 6044 #define MC_CMD_WOL_FILTER_RESET_IN_WAKE_FILTERS 0x1 /* enum */ 6045 #define MC_CMD_WOL_FILTER_RESET_IN_LIGHTSOUT_OFFLOADS 0x2 /* enum */ 6046 6047 /* MC_CMD_WOL_FILTER_RESET_OUT msgresponse */ 6048 #define MC_CMD_WOL_FILTER_RESET_OUT_LEN 0 6049 6050 6051 /***********************************/ 6052 /* MC_CMD_SET_MCAST_HASH 6053 * Set the MCAST hash value without otherwise reconfiguring the MAC 6054 */ 6055 #define MC_CMD_SET_MCAST_HASH 0x35 6056 6057 /* MC_CMD_SET_MCAST_HASH_IN msgrequest */ 6058 #define MC_CMD_SET_MCAST_HASH_IN_LEN 32 6059 #define MC_CMD_SET_MCAST_HASH_IN_HASH0_OFST 0 6060 #define MC_CMD_SET_MCAST_HASH_IN_HASH0_LEN 16 6061 #define MC_CMD_SET_MCAST_HASH_IN_HASH1_OFST 16 6062 #define MC_CMD_SET_MCAST_HASH_IN_HASH1_LEN 16 6063 6064 /* MC_CMD_SET_MCAST_HASH_OUT msgresponse */ 6065 #define MC_CMD_SET_MCAST_HASH_OUT_LEN 0 6066 6067 6068 /***********************************/ 6069 /* MC_CMD_NVRAM_TYPES 6070 * Return bitfield indicating available types of virtual NVRAM partitions. 6071 * Locks required: none. Returns: 0 6072 */ 6073 #define MC_CMD_NVRAM_TYPES 0x36 6074 #undef MC_CMD_0x36_PRIVILEGE_CTG 6075 6076 #define MC_CMD_0x36_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6077 6078 /* MC_CMD_NVRAM_TYPES_IN msgrequest */ 6079 #define MC_CMD_NVRAM_TYPES_IN_LEN 0 6080 6081 /* MC_CMD_NVRAM_TYPES_OUT msgresponse */ 6082 #define MC_CMD_NVRAM_TYPES_OUT_LEN 4 6083 /* Bit mask of supported types. */ 6084 #define MC_CMD_NVRAM_TYPES_OUT_TYPES_OFST 0 6085 /* enum: Disabled callisto. */ 6086 #define MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO 0x0 6087 /* enum: MC firmware. */ 6088 #define MC_CMD_NVRAM_TYPE_MC_FW 0x1 6089 /* enum: MC backup firmware. */ 6090 #define MC_CMD_NVRAM_TYPE_MC_FW_BACKUP 0x2 6091 /* enum: Static configuration Port0. */ 6092 #define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0 0x3 6093 /* enum: Static configuration Port1. */ 6094 #define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1 0x4 6095 /* enum: Dynamic configuration Port0. */ 6096 #define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0 0x5 6097 /* enum: Dynamic configuration Port1. */ 6098 #define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1 0x6 6099 /* enum: Expansion Rom. */ 6100 #define MC_CMD_NVRAM_TYPE_EXP_ROM 0x7 6101 /* enum: Expansion Rom Configuration Port0. */ 6102 #define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0 0x8 6103 /* enum: Expansion Rom Configuration Port1. */ 6104 #define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1 0x9 6105 /* enum: Phy Configuration Port0. */ 6106 #define MC_CMD_NVRAM_TYPE_PHY_PORT0 0xa 6107 /* enum: Phy Configuration Port1. */ 6108 #define MC_CMD_NVRAM_TYPE_PHY_PORT1 0xb 6109 /* enum: Log. */ 6110 #define MC_CMD_NVRAM_TYPE_LOG 0xc 6111 /* enum: FPGA image. */ 6112 #define MC_CMD_NVRAM_TYPE_FPGA 0xd 6113 /* enum: FPGA backup image */ 6114 #define MC_CMD_NVRAM_TYPE_FPGA_BACKUP 0xe 6115 /* enum: FC firmware. */ 6116 #define MC_CMD_NVRAM_TYPE_FC_FW 0xf 6117 /* enum: FC backup firmware. */ 6118 #define MC_CMD_NVRAM_TYPE_FC_FW_BACKUP 0x10 6119 /* enum: CPLD image. */ 6120 #define MC_CMD_NVRAM_TYPE_CPLD 0x11 6121 /* enum: Licensing information. */ 6122 #define MC_CMD_NVRAM_TYPE_LICENSE 0x12 6123 /* enum: FC Log. */ 6124 #define MC_CMD_NVRAM_TYPE_FC_LOG 0x13 6125 /* enum: Additional flash on FPGA. */ 6126 #define MC_CMD_NVRAM_TYPE_FC_EXTRA 0x14 6127 6128 6129 /***********************************/ 6130 /* MC_CMD_NVRAM_INFO 6131 * Read info about a virtual NVRAM partition. Locks required: none. Returns: 0, 6132 * EINVAL (bad type). 6133 */ 6134 #define MC_CMD_NVRAM_INFO 0x37 6135 #undef MC_CMD_0x37_PRIVILEGE_CTG 6136 6137 #define MC_CMD_0x37_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6138 6139 /* MC_CMD_NVRAM_INFO_IN msgrequest */ 6140 #define MC_CMD_NVRAM_INFO_IN_LEN 4 6141 #define MC_CMD_NVRAM_INFO_IN_TYPE_OFST 0 6142 /* Enum values, see field(s): */ 6143 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 6144 6145 /* MC_CMD_NVRAM_INFO_OUT msgresponse */ 6146 #define MC_CMD_NVRAM_INFO_OUT_LEN 24 6147 #define MC_CMD_NVRAM_INFO_OUT_TYPE_OFST 0 6148 /* Enum values, see field(s): */ 6149 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 6150 #define MC_CMD_NVRAM_INFO_OUT_SIZE_OFST 4 6151 #define MC_CMD_NVRAM_INFO_OUT_ERASESIZE_OFST 8 6152 #define MC_CMD_NVRAM_INFO_OUT_FLAGS_OFST 12 6153 #define MC_CMD_NVRAM_INFO_OUT_PROTECTED_LBN 0 6154 #define MC_CMD_NVRAM_INFO_OUT_PROTECTED_WIDTH 1 6155 #define MC_CMD_NVRAM_INFO_OUT_TLV_LBN 1 6156 #define MC_CMD_NVRAM_INFO_OUT_TLV_WIDTH 1 6157 #define MC_CMD_NVRAM_INFO_OUT_READ_ONLY_LBN 5 6158 #define MC_CMD_NVRAM_INFO_OUT_READ_ONLY_WIDTH 1 6159 #define MC_CMD_NVRAM_INFO_OUT_CMAC_LBN 6 6160 #define MC_CMD_NVRAM_INFO_OUT_CMAC_WIDTH 1 6161 #define MC_CMD_NVRAM_INFO_OUT_A_B_LBN 7 6162 #define MC_CMD_NVRAM_INFO_OUT_A_B_WIDTH 1 6163 #define MC_CMD_NVRAM_INFO_OUT_PHYSDEV_OFST 16 6164 #define MC_CMD_NVRAM_INFO_OUT_PHYSADDR_OFST 20 6165 6166 /* MC_CMD_NVRAM_INFO_V2_OUT msgresponse */ 6167 #define MC_CMD_NVRAM_INFO_V2_OUT_LEN 28 6168 #define MC_CMD_NVRAM_INFO_V2_OUT_TYPE_OFST 0 6169 /* Enum values, see field(s): */ 6170 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 6171 #define MC_CMD_NVRAM_INFO_V2_OUT_SIZE_OFST 4 6172 #define MC_CMD_NVRAM_INFO_V2_OUT_ERASESIZE_OFST 8 6173 #define MC_CMD_NVRAM_INFO_V2_OUT_FLAGS_OFST 12 6174 #define MC_CMD_NVRAM_INFO_V2_OUT_PROTECTED_LBN 0 6175 #define MC_CMD_NVRAM_INFO_V2_OUT_PROTECTED_WIDTH 1 6176 #define MC_CMD_NVRAM_INFO_V2_OUT_TLV_LBN 1 6177 #define MC_CMD_NVRAM_INFO_V2_OUT_TLV_WIDTH 1 6178 #define MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_LBN 5 6179 #define MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_WIDTH 1 6180 #define MC_CMD_NVRAM_INFO_V2_OUT_A_B_LBN 7 6181 #define MC_CMD_NVRAM_INFO_V2_OUT_A_B_WIDTH 1 6182 #define MC_CMD_NVRAM_INFO_V2_OUT_PHYSDEV_OFST 16 6183 #define MC_CMD_NVRAM_INFO_V2_OUT_PHYSADDR_OFST 20 6184 /* Writes must be multiples of this size. Added to support the MUM on Sorrento. 6185 */ 6186 #define MC_CMD_NVRAM_INFO_V2_OUT_WRITESIZE_OFST 24 6187 6188 6189 /***********************************/ 6190 /* MC_CMD_NVRAM_UPDATE_START 6191 * Start a group of update operations on a virtual NVRAM partition. Locks 6192 * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad type), EACCES (if 6193 * PHY_LOCK required and not held). 6194 */ 6195 #define MC_CMD_NVRAM_UPDATE_START 0x38 6196 #undef MC_CMD_0x38_PRIVILEGE_CTG 6197 6198 #define MC_CMD_0x38_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6199 6200 /* MC_CMD_NVRAM_UPDATE_START_IN msgrequest: Legacy NVRAM_UPDATE_START request. 6201 * Use NVRAM_UPDATE_START_V2_IN in new code 6202 */ 6203 #define MC_CMD_NVRAM_UPDATE_START_IN_LEN 4 6204 #define MC_CMD_NVRAM_UPDATE_START_IN_TYPE_OFST 0 6205 /* Enum values, see field(s): */ 6206 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 6207 6208 /* MC_CMD_NVRAM_UPDATE_START_V2_IN msgrequest: Extended NVRAM_UPDATE_START 6209 * request with additional flags indicating version of command in use. See 6210 * MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT for details of extended functionality. Use 6211 * paired up with NVRAM_UPDATE_FINISH_V2_IN. 6212 */ 6213 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_LEN 8 6214 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_TYPE_OFST 0 6215 /* Enum values, see field(s): */ 6216 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 6217 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAGS_OFST 4 6218 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAG_REPORT_VERIFY_RESULT_LBN 0 6219 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAG_REPORT_VERIFY_RESULT_WIDTH 1 6220 6221 /* MC_CMD_NVRAM_UPDATE_START_OUT msgresponse */ 6222 #define MC_CMD_NVRAM_UPDATE_START_OUT_LEN 0 6223 6224 6225 /***********************************/ 6226 /* MC_CMD_NVRAM_READ 6227 * Read data from a virtual NVRAM partition. Locks required: PHY_LOCK if 6228 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if 6229 * PHY_LOCK required and not held) 6230 */ 6231 #define MC_CMD_NVRAM_READ 0x39 6232 #undef MC_CMD_0x39_PRIVILEGE_CTG 6233 6234 #define MC_CMD_0x39_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6235 6236 /* MC_CMD_NVRAM_READ_IN msgrequest */ 6237 #define MC_CMD_NVRAM_READ_IN_LEN 12 6238 #define MC_CMD_NVRAM_READ_IN_TYPE_OFST 0 6239 /* Enum values, see field(s): */ 6240 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 6241 #define MC_CMD_NVRAM_READ_IN_OFFSET_OFST 4 6242 /* amount to read in bytes */ 6243 #define MC_CMD_NVRAM_READ_IN_LENGTH_OFST 8 6244 6245 /* MC_CMD_NVRAM_READ_IN_V2 msgrequest */ 6246 #define MC_CMD_NVRAM_READ_IN_V2_LEN 16 6247 #define MC_CMD_NVRAM_READ_IN_V2_TYPE_OFST 0 6248 /* Enum values, see field(s): */ 6249 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 6250 #define MC_CMD_NVRAM_READ_IN_V2_OFFSET_OFST 4 6251 /* amount to read in bytes */ 6252 #define MC_CMD_NVRAM_READ_IN_V2_LENGTH_OFST 8 6253 /* Optional control info. If a partition is stored with an A/B versioning 6254 * scheme (i.e. in more than one physical partition in NVRAM) the host can set 6255 * this to control which underlying physical partition is used to read data 6256 * from. This allows it to perform a read-modify-write-verify with the write 6257 * lock continuously held by calling NVRAM_UPDATE_START, reading the old 6258 * contents using MODE=TARGET_CURRENT, overwriting the old partition and then 6259 * verifying by reading with MODE=TARGET_BACKUP. 6260 */ 6261 #define MC_CMD_NVRAM_READ_IN_V2_MODE_OFST 12 6262 /* enum: Same as omitting MODE: caller sees data in current partition unless it 6263 * holds the write lock in which case it sees data in the partition it is 6264 * updating. 6265 */ 6266 #define MC_CMD_NVRAM_READ_IN_V2_DEFAULT 0x0 6267 /* enum: Read from the current partition of an A/B pair, even if holding the 6268 * write lock. 6269 */ 6270 #define MC_CMD_NVRAM_READ_IN_V2_TARGET_CURRENT 0x1 6271 /* enum: Read from the non-current (i.e. to be updated) partition of an A/B 6272 * pair 6273 */ 6274 #define MC_CMD_NVRAM_READ_IN_V2_TARGET_BACKUP 0x2 6275 6276 /* MC_CMD_NVRAM_READ_OUT msgresponse */ 6277 #define MC_CMD_NVRAM_READ_OUT_LENMIN 1 6278 #define MC_CMD_NVRAM_READ_OUT_LENMAX 252 6279 #define MC_CMD_NVRAM_READ_OUT_LEN(num) (0+1*(num)) 6280 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_OFST 0 6281 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_LEN 1 6282 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MINNUM 1 6283 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MAXNUM 252 6284 6285 6286 /***********************************/ 6287 /* MC_CMD_NVRAM_WRITE 6288 * Write data to a virtual NVRAM partition. Locks required: PHY_LOCK if 6289 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if 6290 * PHY_LOCK required and not held) 6291 */ 6292 #define MC_CMD_NVRAM_WRITE 0x3a 6293 #undef MC_CMD_0x3a_PRIVILEGE_CTG 6294 6295 #define MC_CMD_0x3a_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6296 6297 /* MC_CMD_NVRAM_WRITE_IN msgrequest */ 6298 #define MC_CMD_NVRAM_WRITE_IN_LENMIN 13 6299 #define MC_CMD_NVRAM_WRITE_IN_LENMAX 252 6300 #define MC_CMD_NVRAM_WRITE_IN_LEN(num) (12+1*(num)) 6301 #define MC_CMD_NVRAM_WRITE_IN_TYPE_OFST 0 6302 /* Enum values, see field(s): */ 6303 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 6304 #define MC_CMD_NVRAM_WRITE_IN_OFFSET_OFST 4 6305 #define MC_CMD_NVRAM_WRITE_IN_LENGTH_OFST 8 6306 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_OFST 12 6307 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_LEN 1 6308 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MINNUM 1 6309 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MAXNUM 240 6310 6311 /* MC_CMD_NVRAM_WRITE_OUT msgresponse */ 6312 #define MC_CMD_NVRAM_WRITE_OUT_LEN 0 6313 6314 6315 /***********************************/ 6316 /* MC_CMD_NVRAM_ERASE 6317 * Erase sector(s) from a virtual NVRAM partition. Locks required: PHY_LOCK if 6318 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if 6319 * PHY_LOCK required and not held) 6320 */ 6321 #define MC_CMD_NVRAM_ERASE 0x3b 6322 #undef MC_CMD_0x3b_PRIVILEGE_CTG 6323 6324 #define MC_CMD_0x3b_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6325 6326 /* MC_CMD_NVRAM_ERASE_IN msgrequest */ 6327 #define MC_CMD_NVRAM_ERASE_IN_LEN 12 6328 #define MC_CMD_NVRAM_ERASE_IN_TYPE_OFST 0 6329 /* Enum values, see field(s): */ 6330 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 6331 #define MC_CMD_NVRAM_ERASE_IN_OFFSET_OFST 4 6332 #define MC_CMD_NVRAM_ERASE_IN_LENGTH_OFST 8 6333 6334 /* MC_CMD_NVRAM_ERASE_OUT msgresponse */ 6335 #define MC_CMD_NVRAM_ERASE_OUT_LEN 0 6336 6337 6338 /***********************************/ 6339 /* MC_CMD_NVRAM_UPDATE_FINISH 6340 * Finish a group of update operations on a virtual NVRAM partition. Locks 6341 * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad 6342 * type/offset/length), EACCES (if PHY_LOCK required and not held) 6343 */ 6344 #define MC_CMD_NVRAM_UPDATE_FINISH 0x3c 6345 #undef MC_CMD_0x3c_PRIVILEGE_CTG 6346 6347 #define MC_CMD_0x3c_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6348 6349 /* MC_CMD_NVRAM_UPDATE_FINISH_IN msgrequest: Legacy NVRAM_UPDATE_FINISH 6350 * request. Use NVRAM_UPDATE_FINISH_V2_IN in new code 6351 */ 6352 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_LEN 8 6353 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_TYPE_OFST 0 6354 /* Enum values, see field(s): */ 6355 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 6356 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_REBOOT_OFST 4 6357 6358 /* MC_CMD_NVRAM_UPDATE_FINISH_V2_IN msgrequest: Extended NVRAM_UPDATE_FINISH 6359 * request with additional flags indicating version of NVRAM_UPDATE commands in 6360 * use. See MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT for details of extended 6361 * functionality. Use paired up with NVRAM_UPDATE_START_V2_IN. 6362 */ 6363 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_LEN 12 6364 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_TYPE_OFST 0 6365 /* Enum values, see field(s): */ 6366 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 6367 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_REBOOT_OFST 4 6368 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAGS_OFST 8 6369 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_REPORT_VERIFY_RESULT_LBN 0 6370 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_REPORT_VERIFY_RESULT_WIDTH 1 6371 6372 /* MC_CMD_NVRAM_UPDATE_FINISH_OUT msgresponse: Legacy NVRAM_UPDATE_FINISH 6373 * response. Use NVRAM_UPDATE_FINISH_V2_OUT in new code 6374 */ 6375 #define MC_CMD_NVRAM_UPDATE_FINISH_OUT_LEN 0 6376 6377 /* MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT msgresponse: 6378 * 6379 * Extended NVRAM_UPDATE_FINISH response that communicates the result of secure 6380 * firmware validation where applicable back to the host. 6381 * 6382 * Medford only: For signed firmware images, such as those for medford, the MC 6383 * firmware verifies the signature before marking the firmware image as valid. 6384 * This process takes a few seconds to complete. So is likely to take more than 6385 * the MCDI timeout. Hence signature verification is initiated when 6386 * MC_CMD_NVRAM_UPDATE_FINISH_V2_IN is received by the firmware, however, the 6387 * MCDI command is run in a background MCDI processing thread. This response 6388 * payload includes the results of the signature verification. Note that the 6389 * per-partition nvram lock in firmware is only released after the verification 6390 * has completed. 6391 */ 6392 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_LEN 4 6393 /* Result of nvram update completion processing */ 6394 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_RESULT_CODE_OFST 0 6395 /* enum: Invalid return code; only non-zero values are defined. Defined as 6396 * unknown for backwards compatibility with NVRAM_UPDATE_FINISH_OUT. 6397 */ 6398 #define MC_CMD_NVRAM_VERIFY_RC_UNKNOWN 0x0 6399 /* enum: Verify succeeded without any errors. */ 6400 #define MC_CMD_NVRAM_VERIFY_RC_SUCCESS 0x1 6401 /* enum: CMS format verification failed due to an internal error. */ 6402 #define MC_CMD_NVRAM_VERIFY_RC_CMS_CHECK_FAILED 0x2 6403 /* enum: Invalid CMS format in image metadata. */ 6404 #define MC_CMD_NVRAM_VERIFY_RC_INVALID_CMS_FORMAT 0x3 6405 /* enum: Message digest verification failed due to an internal error. */ 6406 #define MC_CMD_NVRAM_VERIFY_RC_MESSAGE_DIGEST_CHECK_FAILED 0x4 6407 /* enum: Error in message digest calculated over the reflash-header, payload 6408 * and reflash-trailer. 6409 */ 6410 #define MC_CMD_NVRAM_VERIFY_RC_BAD_MESSAGE_DIGEST 0x5 6411 /* enum: Signature verification failed due to an internal error. */ 6412 #define MC_CMD_NVRAM_VERIFY_RC_SIGNATURE_CHECK_FAILED 0x6 6413 /* enum: There are no valid signatures in the image. */ 6414 #define MC_CMD_NVRAM_VERIFY_RC_NO_VALID_SIGNATURES 0x7 6415 /* enum: Trusted approvers verification failed due to an internal error. */ 6416 #define MC_CMD_NVRAM_VERIFY_RC_TRUSTED_APPROVERS_CHECK_FAILED 0x8 6417 /* enum: The Trusted approver's list is empty. */ 6418 #define MC_CMD_NVRAM_VERIFY_RC_NO_TRUSTED_APPROVERS 0x9 6419 /* enum: Signature chain verification failed due to an internal error. */ 6420 #define MC_CMD_NVRAM_VERIFY_RC_SIGNATURE_CHAIN_CHECK_FAILED 0xa 6421 /* enum: The signers of the signatures in the image are not listed in the 6422 * Trusted approver's list. 6423 */ 6424 #define MC_CMD_NVRAM_VERIFY_RC_NO_SIGNATURE_MATCH 0xb 6425 /* enum: The image contains a test-signed certificate, but the adapter accepts 6426 * only production signed images. 6427 */ 6428 #define MC_CMD_NVRAM_VERIFY_RC_REJECT_TEST_SIGNED 0xc 6429 6430 6431 /***********************************/ 6432 /* MC_CMD_REBOOT 6433 * Reboot the MC. 6434 * 6435 * The AFTER_ASSERTION flag is intended to be used when the driver notices an 6436 * assertion failure (at which point it is expected to perform a complete tear 6437 * down and reinitialise), to allow both ports to reset the MC once in an 6438 * atomic fashion. 6439 * 6440 * Production mc firmwares are generally compiled with REBOOT_ON_ASSERT=1, 6441 * which means that they will automatically reboot out of the assertion 6442 * handler, so this is in practise an optional operation. It is still 6443 * recommended that drivers execute this to support custom firmwares with 6444 * REBOOT_ON_ASSERT=0. 6445 * 6446 * Locks required: NONE Returns: Nothing. You get back a response with ERR=1, 6447 * DATALEN=0 6448 */ 6449 #define MC_CMD_REBOOT 0x3d 6450 #undef MC_CMD_0x3d_PRIVILEGE_CTG 6451 6452 #define MC_CMD_0x3d_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6453 6454 /* MC_CMD_REBOOT_IN msgrequest */ 6455 #define MC_CMD_REBOOT_IN_LEN 4 6456 #define MC_CMD_REBOOT_IN_FLAGS_OFST 0 6457 #define MC_CMD_REBOOT_FLAGS_AFTER_ASSERTION 0x1 /* enum */ 6458 6459 /* MC_CMD_REBOOT_OUT msgresponse */ 6460 #define MC_CMD_REBOOT_OUT_LEN 0 6461 6462 6463 /***********************************/ 6464 /* MC_CMD_SCHEDINFO 6465 * Request scheduler info. Locks required: NONE. Returns: An array of 6466 * (timeslice,maximum overrun), one for each thread, in ascending order of 6467 * thread address. 6468 */ 6469 #define MC_CMD_SCHEDINFO 0x3e 6470 #undef MC_CMD_0x3e_PRIVILEGE_CTG 6471 6472 #define MC_CMD_0x3e_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6473 6474 /* MC_CMD_SCHEDINFO_IN msgrequest */ 6475 #define MC_CMD_SCHEDINFO_IN_LEN 0 6476 6477 /* MC_CMD_SCHEDINFO_OUT msgresponse */ 6478 #define MC_CMD_SCHEDINFO_OUT_LENMIN 4 6479 #define MC_CMD_SCHEDINFO_OUT_LENMAX 252 6480 #define MC_CMD_SCHEDINFO_OUT_LEN(num) (0+4*(num)) 6481 #define MC_CMD_SCHEDINFO_OUT_DATA_OFST 0 6482 #define MC_CMD_SCHEDINFO_OUT_DATA_LEN 4 6483 #define MC_CMD_SCHEDINFO_OUT_DATA_MINNUM 1 6484 #define MC_CMD_SCHEDINFO_OUT_DATA_MAXNUM 63 6485 6486 6487 /***********************************/ 6488 /* MC_CMD_REBOOT_MODE 6489 * Set the mode for the next MC reboot. Locks required: NONE. Sets the reboot 6490 * mode to the specified value. Returns the old mode. 6491 */ 6492 #define MC_CMD_REBOOT_MODE 0x3f 6493 #undef MC_CMD_0x3f_PRIVILEGE_CTG 6494 6495 #define MC_CMD_0x3f_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6496 6497 /* MC_CMD_REBOOT_MODE_IN msgrequest */ 6498 #define MC_CMD_REBOOT_MODE_IN_LEN 4 6499 #define MC_CMD_REBOOT_MODE_IN_VALUE_OFST 0 6500 /* enum: Normal. */ 6501 #define MC_CMD_REBOOT_MODE_NORMAL 0x0 6502 /* enum: Power-on Reset. */ 6503 #define MC_CMD_REBOOT_MODE_POR 0x2 6504 /* enum: Snapper. */ 6505 #define MC_CMD_REBOOT_MODE_SNAPPER 0x3 6506 /* enum: snapper fake POR */ 6507 #define MC_CMD_REBOOT_MODE_SNAPPER_POR 0x4 6508 #define MC_CMD_REBOOT_MODE_IN_FAKE_LBN 7 6509 #define MC_CMD_REBOOT_MODE_IN_FAKE_WIDTH 1 6510 6511 /* MC_CMD_REBOOT_MODE_OUT msgresponse */ 6512 #define MC_CMD_REBOOT_MODE_OUT_LEN 4 6513 #define MC_CMD_REBOOT_MODE_OUT_VALUE_OFST 0 6514 6515 6516 /***********************************/ 6517 /* MC_CMD_SENSOR_INFO 6518 * Returns information about every available sensor. 6519 * 6520 * Each sensor has a single (16bit) value, and a corresponding state. The 6521 * mapping between value and state is nominally determined by the MC, but may 6522 * be implemented using up to 2 ranges per sensor. 6523 * 6524 * This call returns a mask (32bit) of the sensors that are supported by this 6525 * platform, then an array of sensor information structures, in order of sensor 6526 * type (but without gaps for unimplemented sensors). Each structure defines 6527 * the ranges for the corresponding sensor. An unused range is indicated by 6528 * equal limit values. If one range is used, a value outside that range results 6529 * in STATE_FATAL. If two ranges are used, a value outside the second range 6530 * results in STATE_FATAL while a value outside the first and inside the second 6531 * range results in STATE_WARNING. 6532 * 6533 * Sensor masks and sensor information arrays are organised into pages. For 6534 * backward compatibility, older host software can only use sensors in page 0. 6535 * Bit 32 in the sensor mask was previously unused, and is no reserved for use 6536 * as the next page flag. 6537 * 6538 * If the request does not contain a PAGE value then firmware will only return 6539 * page 0 of sensor information, with bit 31 in the sensor mask cleared. 6540 * 6541 * If the request contains a PAGE value then firmware responds with the sensor 6542 * mask and sensor information array for that page of sensors. In this case bit 6543 * 31 in the mask is set if another page exists. 6544 * 6545 * Locks required: None Returns: 0 6546 */ 6547 #define MC_CMD_SENSOR_INFO 0x41 6548 #undef MC_CMD_0x41_PRIVILEGE_CTG 6549 6550 #define MC_CMD_0x41_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6551 6552 /* MC_CMD_SENSOR_INFO_IN msgrequest */ 6553 #define MC_CMD_SENSOR_INFO_IN_LEN 0 6554 6555 /* MC_CMD_SENSOR_INFO_EXT_IN msgrequest */ 6556 #define MC_CMD_SENSOR_INFO_EXT_IN_LEN 4 6557 /* Which page of sensors to report. 6558 * 6559 * Page 0 contains sensors 0 to 30 (sensor 31 is the next page bit). 6560 * 6561 * Page 1 contains sensors 32 to 62 (sensor 63 is the next page bit). etc. 6562 */ 6563 #define MC_CMD_SENSOR_INFO_EXT_IN_PAGE_OFST 0 6564 6565 /* MC_CMD_SENSOR_INFO_OUT msgresponse */ 6566 #define MC_CMD_SENSOR_INFO_OUT_LENMIN 4 6567 #define MC_CMD_SENSOR_INFO_OUT_LENMAX 252 6568 #define MC_CMD_SENSOR_INFO_OUT_LEN(num) (4+8*(num)) 6569 #define MC_CMD_SENSOR_INFO_OUT_MASK_OFST 0 6570 /* enum: Controller temperature: degC */ 6571 #define MC_CMD_SENSOR_CONTROLLER_TEMP 0x0 6572 /* enum: Phy common temperature: degC */ 6573 #define MC_CMD_SENSOR_PHY_COMMON_TEMP 0x1 6574 /* enum: Controller cooling: bool */ 6575 #define MC_CMD_SENSOR_CONTROLLER_COOLING 0x2 6576 /* enum: Phy 0 temperature: degC */ 6577 #define MC_CMD_SENSOR_PHY0_TEMP 0x3 6578 /* enum: Phy 0 cooling: bool */ 6579 #define MC_CMD_SENSOR_PHY0_COOLING 0x4 6580 /* enum: Phy 1 temperature: degC */ 6581 #define MC_CMD_SENSOR_PHY1_TEMP 0x5 6582 /* enum: Phy 1 cooling: bool */ 6583 #define MC_CMD_SENSOR_PHY1_COOLING 0x6 6584 /* enum: 1.0v power: mV */ 6585 #define MC_CMD_SENSOR_IN_1V0 0x7 6586 /* enum: 1.2v power: mV */ 6587 #define MC_CMD_SENSOR_IN_1V2 0x8 6588 /* enum: 1.8v power: mV */ 6589 #define MC_CMD_SENSOR_IN_1V8 0x9 6590 /* enum: 2.5v power: mV */ 6591 #define MC_CMD_SENSOR_IN_2V5 0xa 6592 /* enum: 3.3v power: mV */ 6593 #define MC_CMD_SENSOR_IN_3V3 0xb 6594 /* enum: 12v power: mV */ 6595 #define MC_CMD_SENSOR_IN_12V0 0xc 6596 /* enum: 1.2v analogue power: mV */ 6597 #define MC_CMD_SENSOR_IN_1V2A 0xd 6598 /* enum: reference voltage: mV */ 6599 #define MC_CMD_SENSOR_IN_VREF 0xe 6600 /* enum: AOE FPGA power: mV */ 6601 #define MC_CMD_SENSOR_OUT_VAOE 0xf 6602 /* enum: AOE FPGA temperature: degC */ 6603 #define MC_CMD_SENSOR_AOE_TEMP 0x10 6604 /* enum: AOE FPGA PSU temperature: degC */ 6605 #define MC_CMD_SENSOR_PSU_AOE_TEMP 0x11 6606 /* enum: AOE PSU temperature: degC */ 6607 #define MC_CMD_SENSOR_PSU_TEMP 0x12 6608 /* enum: Fan 0 speed: RPM */ 6609 #define MC_CMD_SENSOR_FAN_0 0x13 6610 /* enum: Fan 1 speed: RPM */ 6611 #define MC_CMD_SENSOR_FAN_1 0x14 6612 /* enum: Fan 2 speed: RPM */ 6613 #define MC_CMD_SENSOR_FAN_2 0x15 6614 /* enum: Fan 3 speed: RPM */ 6615 #define MC_CMD_SENSOR_FAN_3 0x16 6616 /* enum: Fan 4 speed: RPM */ 6617 #define MC_CMD_SENSOR_FAN_4 0x17 6618 /* enum: AOE FPGA input power: mV */ 6619 #define MC_CMD_SENSOR_IN_VAOE 0x18 6620 /* enum: AOE FPGA current: mA */ 6621 #define MC_CMD_SENSOR_OUT_IAOE 0x19 6622 /* enum: AOE FPGA input current: mA */ 6623 #define MC_CMD_SENSOR_IN_IAOE 0x1a 6624 /* enum: NIC power consumption: W */ 6625 #define MC_CMD_SENSOR_NIC_POWER 0x1b 6626 /* enum: 0.9v power voltage: mV */ 6627 #define MC_CMD_SENSOR_IN_0V9 0x1c 6628 /* enum: 0.9v power current: mA */ 6629 #define MC_CMD_SENSOR_IN_I0V9 0x1d 6630 /* enum: 1.2v power current: mA */ 6631 #define MC_CMD_SENSOR_IN_I1V2 0x1e 6632 /* enum: Not a sensor: reserved for the next page flag */ 6633 #define MC_CMD_SENSOR_PAGE0_NEXT 0x1f 6634 /* enum: 0.9v power voltage (at ADC): mV */ 6635 #define MC_CMD_SENSOR_IN_0V9_ADC 0x20 6636 /* enum: Controller temperature 2: degC */ 6637 #define MC_CMD_SENSOR_CONTROLLER_2_TEMP 0x21 6638 /* enum: Voltage regulator internal temperature: degC */ 6639 #define MC_CMD_SENSOR_VREG_INTERNAL_TEMP 0x22 6640 /* enum: 0.9V voltage regulator temperature: degC */ 6641 #define MC_CMD_SENSOR_VREG_0V9_TEMP 0x23 6642 /* enum: 1.2V voltage regulator temperature: degC */ 6643 #define MC_CMD_SENSOR_VREG_1V2_TEMP 0x24 6644 /* enum: controller internal temperature sensor voltage (internal ADC): mV */ 6645 #define MC_CMD_SENSOR_CONTROLLER_VPTAT 0x25 6646 /* enum: controller internal temperature (internal ADC): degC */ 6647 #define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP 0x26 6648 /* enum: controller internal temperature sensor voltage (external ADC): mV */ 6649 #define MC_CMD_SENSOR_CONTROLLER_VPTAT_EXTADC 0x27 6650 /* enum: controller internal temperature (external ADC): degC */ 6651 #define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP_EXTADC 0x28 6652 /* enum: ambient temperature: degC */ 6653 #define MC_CMD_SENSOR_AMBIENT_TEMP 0x29 6654 /* enum: air flow: bool */ 6655 #define MC_CMD_SENSOR_AIRFLOW 0x2a 6656 /* enum: voltage between VSS08D and VSS08D at CSR: mV */ 6657 #define MC_CMD_SENSOR_VDD08D_VSS08D_CSR 0x2b 6658 /* enum: voltage between VSS08D and VSS08D at CSR (external ADC): mV */ 6659 #define MC_CMD_SENSOR_VDD08D_VSS08D_CSR_EXTADC 0x2c 6660 /* enum: Hotpoint temperature: degC */ 6661 #define MC_CMD_SENSOR_HOTPOINT_TEMP 0x2d 6662 /* enum: Port 0 PHY power switch over-current: bool */ 6663 #define MC_CMD_SENSOR_PHY_POWER_PORT0 0x2e 6664 /* enum: Port 1 PHY power switch over-current: bool */ 6665 #define MC_CMD_SENSOR_PHY_POWER_PORT1 0x2f 6666 /* enum: Mop-up microcontroller reference voltage (millivolts) */ 6667 #define MC_CMD_SENSOR_MUM_VCC 0x30 6668 /* enum: 0.9v power phase A voltage: mV */ 6669 #define MC_CMD_SENSOR_IN_0V9_A 0x31 6670 /* enum: 0.9v power phase A current: mA */ 6671 #define MC_CMD_SENSOR_IN_I0V9_A 0x32 6672 /* enum: 0.9V voltage regulator phase A temperature: degC */ 6673 #define MC_CMD_SENSOR_VREG_0V9_A_TEMP 0x33 6674 /* enum: 0.9v power phase B voltage: mV */ 6675 #define MC_CMD_SENSOR_IN_0V9_B 0x34 6676 /* enum: 0.9v power phase B current: mA */ 6677 #define MC_CMD_SENSOR_IN_I0V9_B 0x35 6678 /* enum: 0.9V voltage regulator phase B temperature: degC */ 6679 #define MC_CMD_SENSOR_VREG_0V9_B_TEMP 0x36 6680 /* enum: CCOM AVREG 1v2 supply (interval ADC): mV */ 6681 #define MC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY 0x37 6682 /* enum: CCOM AVREG 1v2 supply (external ADC): mV */ 6683 #define MC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY_EXTADC 0x38 6684 /* enum: CCOM AVREG 1v8 supply (interval ADC): mV */ 6685 #define MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY 0x39 6686 /* enum: CCOM AVREG 1v8 supply (external ADC): mV */ 6687 #define MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY_EXTADC 0x3a 6688 /* enum: CCOM RTS temperature: degC */ 6689 #define MC_CMD_SENSOR_CONTROLLER_RTS 0x3b 6690 /* enum: Not a sensor: reserved for the next page flag */ 6691 #define MC_CMD_SENSOR_PAGE1_NEXT 0x3f 6692 /* enum: controller internal temperature sensor voltage on master core 6693 * (internal ADC): mV 6694 */ 6695 #define MC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT 0x40 6696 /* enum: controller internal temperature on master core (internal ADC): degC */ 6697 #define MC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP 0x41 6698 /* enum: controller internal temperature sensor voltage on master core 6699 * (external ADC): mV 6700 */ 6701 #define MC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT_EXTADC 0x42 6702 /* enum: controller internal temperature on master core (external ADC): degC */ 6703 #define MC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC 0x43 6704 /* enum: controller internal temperature on slave core sensor voltage (internal 6705 * ADC): mV 6706 */ 6707 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT 0x44 6708 /* enum: controller internal temperature on slave core (internal ADC): degC */ 6709 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP 0x45 6710 /* enum: controller internal temperature on slave core sensor voltage (external 6711 * ADC): mV 6712 */ 6713 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT_EXTADC 0x46 6714 /* enum: controller internal temperature on slave core (external ADC): degC */ 6715 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC 0x47 6716 /* enum: Voltage supplied to the SODIMMs from their power supply: mV */ 6717 #define MC_CMD_SENSOR_SODIMM_VOUT 0x49 6718 /* enum: Temperature of SODIMM 0 (if installed): degC */ 6719 #define MC_CMD_SENSOR_SODIMM_0_TEMP 0x4a 6720 /* enum: Temperature of SODIMM 1 (if installed): degC */ 6721 #define MC_CMD_SENSOR_SODIMM_1_TEMP 0x4b 6722 /* enum: Voltage supplied to the QSFP #0 from their power supply: mV */ 6723 #define MC_CMD_SENSOR_PHY0_VCC 0x4c 6724 /* enum: Voltage supplied to the QSFP #1 from their power supply: mV */ 6725 #define MC_CMD_SENSOR_PHY1_VCC 0x4d 6726 /* enum: Controller die temperature (TDIODE): degC */ 6727 #define MC_CMD_SENSOR_CONTROLLER_TDIODE_TEMP 0x4e 6728 /* enum: Board temperature (front): degC */ 6729 #define MC_CMD_SENSOR_BOARD_FRONT_TEMP 0x4f 6730 /* enum: Board temperature (back): degC */ 6731 #define MC_CMD_SENSOR_BOARD_BACK_TEMP 0x50 6732 /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */ 6733 #define MC_CMD_SENSOR_ENTRY_OFST 4 6734 #define MC_CMD_SENSOR_ENTRY_LEN 8 6735 #define MC_CMD_SENSOR_ENTRY_LO_OFST 4 6736 #define MC_CMD_SENSOR_ENTRY_HI_OFST 8 6737 #define MC_CMD_SENSOR_ENTRY_MINNUM 0 6738 #define MC_CMD_SENSOR_ENTRY_MAXNUM 31 6739 6740 /* MC_CMD_SENSOR_INFO_EXT_OUT msgresponse */ 6741 #define MC_CMD_SENSOR_INFO_EXT_OUT_LENMIN 4 6742 #define MC_CMD_SENSOR_INFO_EXT_OUT_LENMAX 252 6743 #define MC_CMD_SENSOR_INFO_EXT_OUT_LEN(num) (4+8*(num)) 6744 #define MC_CMD_SENSOR_INFO_EXT_OUT_MASK_OFST 0 6745 /* Enum values, see field(s): */ 6746 /* MC_CMD_SENSOR_INFO_OUT */ 6747 #define MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_LBN 31 6748 #define MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_WIDTH 1 6749 /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */ 6750 /* MC_CMD_SENSOR_ENTRY_OFST 4 */ 6751 /* MC_CMD_SENSOR_ENTRY_LEN 8 */ 6752 /* MC_CMD_SENSOR_ENTRY_LO_OFST 4 */ 6753 /* MC_CMD_SENSOR_ENTRY_HI_OFST 8 */ 6754 /* MC_CMD_SENSOR_ENTRY_MINNUM 0 */ 6755 /* MC_CMD_SENSOR_ENTRY_MAXNUM 31 */ 6756 6757 /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF structuredef */ 6758 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_LEN 8 6759 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_OFST 0 6760 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LEN 2 6761 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LBN 0 6762 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_WIDTH 16 6763 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_OFST 2 6764 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LEN 2 6765 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LBN 16 6766 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_WIDTH 16 6767 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_OFST 4 6768 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LEN 2 6769 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LBN 32 6770 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_WIDTH 16 6771 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_OFST 6 6772 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LEN 2 6773 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LBN 48 6774 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_WIDTH 16 6775 6776 6777 /***********************************/ 6778 /* MC_CMD_READ_SENSORS 6779 * Returns the current reading from each sensor. DMAs an array of sensor 6780 * readings, in order of sensor type (but without gaps for unimplemented 6781 * sensors), into host memory. Each array element is a 6782 * MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF dword. 6783 * 6784 * If the request does not contain the LENGTH field then only sensors 0 to 30 6785 * are reported, to avoid DMA buffer overflow in older host software. If the 6786 * sensor reading require more space than the LENGTH allows, then return 6787 * EINVAL. 6788 * 6789 * The MC will send a SENSOREVT event every time any sensor changes state. The 6790 * driver is responsible for ensuring that it doesn't miss any events. The 6791 * board will function normally if all sensors are in STATE_OK or 6792 * STATE_WARNING. Otherwise the board should not be expected to function. 6793 */ 6794 #define MC_CMD_READ_SENSORS 0x42 6795 #undef MC_CMD_0x42_PRIVILEGE_CTG 6796 6797 #define MC_CMD_0x42_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6798 6799 /* MC_CMD_READ_SENSORS_IN msgrequest */ 6800 #define MC_CMD_READ_SENSORS_IN_LEN 8 6801 /* DMA address of host buffer for sensor readings (must be 4Kbyte aligned). */ 6802 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_OFST 0 6803 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LEN 8 6804 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_OFST 0 6805 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_OFST 4 6806 6807 /* MC_CMD_READ_SENSORS_EXT_IN msgrequest */ 6808 #define MC_CMD_READ_SENSORS_EXT_IN_LEN 12 6809 /* DMA address of host buffer for sensor readings (must be 4Kbyte aligned). */ 6810 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_OFST 0 6811 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LEN 8 6812 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_OFST 0 6813 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_HI_OFST 4 6814 /* Size in bytes of host buffer. */ 6815 #define MC_CMD_READ_SENSORS_EXT_IN_LENGTH_OFST 8 6816 6817 /* MC_CMD_READ_SENSORS_OUT msgresponse */ 6818 #define MC_CMD_READ_SENSORS_OUT_LEN 0 6819 6820 /* MC_CMD_READ_SENSORS_EXT_OUT msgresponse */ 6821 #define MC_CMD_READ_SENSORS_EXT_OUT_LEN 0 6822 6823 /* MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF structuredef */ 6824 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_LEN 4 6825 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_OFST 0 6826 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LEN 2 6827 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LBN 0 6828 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_WIDTH 16 6829 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_OFST 2 6830 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LEN 1 6831 /* enum: Ok. */ 6832 #define MC_CMD_SENSOR_STATE_OK 0x0 6833 /* enum: Breached warning threshold. */ 6834 #define MC_CMD_SENSOR_STATE_WARNING 0x1 6835 /* enum: Breached fatal threshold. */ 6836 #define MC_CMD_SENSOR_STATE_FATAL 0x2 6837 /* enum: Fault with sensor. */ 6838 #define MC_CMD_SENSOR_STATE_BROKEN 0x3 6839 /* enum: Sensor is working but does not currently have a reading. */ 6840 #define MC_CMD_SENSOR_STATE_NO_READING 0x4 6841 /* enum: Sensor initialisation failed. */ 6842 #define MC_CMD_SENSOR_STATE_INIT_FAILED 0x5 6843 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LBN 16 6844 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_WIDTH 8 6845 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_OFST 3 6846 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_LEN 1 6847 /* Enum values, see field(s): */ 6848 /* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */ 6849 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_LBN 24 6850 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_WIDTH 8 6851 6852 6853 /***********************************/ 6854 /* MC_CMD_GET_PHY_STATE 6855 * Report current state of PHY. A 'zombie' PHY is a PHY that has failed to boot 6856 * (e.g. due to missing or corrupted firmware). Locks required: None. Return 6857 * code: 0 6858 */ 6859 #define MC_CMD_GET_PHY_STATE 0x43 6860 #undef MC_CMD_0x43_PRIVILEGE_CTG 6861 6862 #define MC_CMD_0x43_PRIVILEGE_CTG SRIOV_CTG_GENERAL 6863 6864 /* MC_CMD_GET_PHY_STATE_IN msgrequest */ 6865 #define MC_CMD_GET_PHY_STATE_IN_LEN 0 6866 6867 /* MC_CMD_GET_PHY_STATE_OUT msgresponse */ 6868 #define MC_CMD_GET_PHY_STATE_OUT_LEN 4 6869 #define MC_CMD_GET_PHY_STATE_OUT_STATE_OFST 0 6870 /* enum: Ok. */ 6871 #define MC_CMD_PHY_STATE_OK 0x1 6872 /* enum: Faulty. */ 6873 #define MC_CMD_PHY_STATE_ZOMBIE 0x2 6874 6875 6876 /***********************************/ 6877 /* MC_CMD_SETUP_8021QBB 6878 * 802.1Qbb control. 8 Tx queues that map to priorities 0 - 7. Use all 1s to 6879 * disable 802.Qbb for a given priority. 6880 */ 6881 #define MC_CMD_SETUP_8021QBB 0x44 6882 6883 /* MC_CMD_SETUP_8021QBB_IN msgrequest */ 6884 #define MC_CMD_SETUP_8021QBB_IN_LEN 32 6885 #define MC_CMD_SETUP_8021QBB_IN_TXQS_OFST 0 6886 #define MC_CMD_SETUP_8021QBB_IN_TXQS_LEN 32 6887 6888 /* MC_CMD_SETUP_8021QBB_OUT msgresponse */ 6889 #define MC_CMD_SETUP_8021QBB_OUT_LEN 0 6890 6891 6892 /***********************************/ 6893 /* MC_CMD_WOL_FILTER_GET 6894 * Retrieve ID of any WoL filters. Locks required: None. Returns: 0, ENOSYS 6895 */ 6896 #define MC_CMD_WOL_FILTER_GET 0x45 6897 #undef MC_CMD_0x45_PRIVILEGE_CTG 6898 6899 #define MC_CMD_0x45_PRIVILEGE_CTG SRIOV_CTG_LINK 6900 6901 /* MC_CMD_WOL_FILTER_GET_IN msgrequest */ 6902 #define MC_CMD_WOL_FILTER_GET_IN_LEN 0 6903 6904 /* MC_CMD_WOL_FILTER_GET_OUT msgresponse */ 6905 #define MC_CMD_WOL_FILTER_GET_OUT_LEN 4 6906 #define MC_CMD_WOL_FILTER_GET_OUT_FILTER_ID_OFST 0 6907 6908 6909 /***********************************/ 6910 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD 6911 * Add a protocol offload to NIC for lights-out state. Locks required: None. 6912 * Returns: 0, ENOSYS 6913 */ 6914 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD 0x46 6915 #undef MC_CMD_0x46_PRIVILEGE_CTG 6916 6917 #define MC_CMD_0x46_PRIVILEGE_CTG SRIOV_CTG_LINK 6918 6919 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN msgrequest */ 6920 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMIN 8 6921 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMAX 252 6922 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LEN(num) (4+4*(num)) 6923 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 6924 #define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_ARP 0x1 /* enum */ 6925 #define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_NS 0x2 /* enum */ 6926 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_OFST 4 6927 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_LEN 4 6928 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MINNUM 1 6929 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MAXNUM 62 6930 6931 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP msgrequest */ 6932 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_LEN 14 6933 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */ 6934 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_OFST 4 6935 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_LEN 6 6936 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_IP_OFST 10 6937 6938 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS msgrequest */ 6939 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_LEN 42 6940 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */ 6941 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_OFST 4 6942 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_LEN 6 6943 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_OFST 10 6944 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_LEN 16 6945 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_OFST 26 6946 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_LEN 16 6947 6948 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT msgresponse */ 6949 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_LEN 4 6950 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_FILTER_ID_OFST 0 6951 6952 6953 /***********************************/ 6954 /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD 6955 * Remove a protocol offload from NIC for lights-out state. Locks required: 6956 * None. Returns: 0, ENOSYS 6957 */ 6958 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD 0x47 6959 #undef MC_CMD_0x47_PRIVILEGE_CTG 6960 6961 #define MC_CMD_0x47_PRIVILEGE_CTG SRIOV_CTG_LINK 6962 6963 /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN msgrequest */ 6964 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_LEN 8 6965 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 6966 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_FILTER_ID_OFST 4 6967 6968 /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT msgresponse */ 6969 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT_LEN 0 6970 6971 6972 /***********************************/ 6973 /* MC_CMD_MAC_RESET_RESTORE 6974 * Restore MAC after block reset. Locks required: None. Returns: 0. 6975 */ 6976 #define MC_CMD_MAC_RESET_RESTORE 0x48 6977 6978 /* MC_CMD_MAC_RESET_RESTORE_IN msgrequest */ 6979 #define MC_CMD_MAC_RESET_RESTORE_IN_LEN 0 6980 6981 /* MC_CMD_MAC_RESET_RESTORE_OUT msgresponse */ 6982 #define MC_CMD_MAC_RESET_RESTORE_OUT_LEN 0 6983 6984 6985 /***********************************/ 6986 /* MC_CMD_TESTASSERT 6987 * Deliberately trigger an assert-detonation in the firmware for testing 6988 * purposes (i.e. to allow tests that the driver copes gracefully). Locks 6989 * required: None Returns: 0 6990 */ 6991 #define MC_CMD_TESTASSERT 0x49 6992 #undef MC_CMD_0x49_PRIVILEGE_CTG 6993 6994 #define MC_CMD_0x49_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6995 6996 /* MC_CMD_TESTASSERT_IN msgrequest */ 6997 #define MC_CMD_TESTASSERT_IN_LEN 0 6998 6999 /* MC_CMD_TESTASSERT_OUT msgresponse */ 7000 #define MC_CMD_TESTASSERT_OUT_LEN 0 7001 7002 /* MC_CMD_TESTASSERT_V2_IN msgrequest */ 7003 #define MC_CMD_TESTASSERT_V2_IN_LEN 4 7004 /* How to provoke the assertion */ 7005 #define MC_CMD_TESTASSERT_V2_IN_TYPE_OFST 0 7006 /* enum: Assert using the FAIL_ASSERTION_WITH_USEFUL_VALUES macro. Unless 7007 * you're testing firmware, this is what you want. 7008 */ 7009 #define MC_CMD_TESTASSERT_V2_IN_FAIL_ASSERTION_WITH_USEFUL_VALUES 0x0 7010 /* enum: Assert using assert(0); */ 7011 #define MC_CMD_TESTASSERT_V2_IN_ASSERT_FALSE 0x1 7012 /* enum: Deliberately trigger a watchdog */ 7013 #define MC_CMD_TESTASSERT_V2_IN_WATCHDOG 0x2 7014 /* enum: Deliberately trigger a trap by loading from an invalid address */ 7015 #define MC_CMD_TESTASSERT_V2_IN_LOAD_TRAP 0x3 7016 /* enum: Deliberately trigger a trap by storing to an invalid address */ 7017 #define MC_CMD_TESTASSERT_V2_IN_STORE_TRAP 0x4 7018 /* enum: Jump to an invalid address */ 7019 #define MC_CMD_TESTASSERT_V2_IN_JUMP_TRAP 0x5 7020 7021 /* MC_CMD_TESTASSERT_V2_OUT msgresponse */ 7022 #define MC_CMD_TESTASSERT_V2_OUT_LEN 0 7023 7024 7025 /***********************************/ 7026 /* MC_CMD_WORKAROUND 7027 * Enable/Disable a given workaround. The mcfw will return EINVAL if it doesn't 7028 * understand the given workaround number - which should not be treated as a 7029 * hard error by client code. This op does not imply any semantics about each 7030 * workaround, that's between the driver and the mcfw on a per-workaround 7031 * basis. Locks required: None. Returns: 0, EINVAL . 7032 */ 7033 #define MC_CMD_WORKAROUND 0x4a 7034 #undef MC_CMD_0x4a_PRIVILEGE_CTG 7035 7036 #define MC_CMD_0x4a_PRIVILEGE_CTG SRIOV_CTG_ADMIN 7037 7038 /* MC_CMD_WORKAROUND_IN msgrequest */ 7039 #define MC_CMD_WORKAROUND_IN_LEN 8 7040 /* The enums here must correspond with those in MC_CMD_GET_WORKAROUND. */ 7041 #define MC_CMD_WORKAROUND_IN_TYPE_OFST 0 7042 /* enum: Bug 17230 work around. */ 7043 #define MC_CMD_WORKAROUND_BUG17230 0x1 7044 /* enum: Bug 35388 work around (unsafe EVQ writes). */ 7045 #define MC_CMD_WORKAROUND_BUG35388 0x2 7046 /* enum: Bug35017 workaround (A64 tables must be identity map) */ 7047 #define MC_CMD_WORKAROUND_BUG35017 0x3 7048 /* enum: Bug 41750 present (MC_CMD_TRIGGER_INTERRUPT won't work) */ 7049 #define MC_CMD_WORKAROUND_BUG41750 0x4 7050 /* enum: Bug 42008 present (Interrupts can overtake associated events). Caution 7051 * - before adding code that queries this workaround, remember that there's 7052 * released Monza firmware that doesn't understand MC_CMD_WORKAROUND_BUG42008, 7053 * and will hence (incorrectly) report that the bug doesn't exist. 7054 */ 7055 #define MC_CMD_WORKAROUND_BUG42008 0x5 7056 /* enum: Bug 26807 features present in firmware (multicast filter chaining) 7057 * This feature cannot be turned on/off while there are any filters already 7058 * present. The behaviour in such case depends on the acting client's privilege 7059 * level. If the client has the admin privilege, then all functions that have 7060 * filters installed will be FLRed and the FLR_DONE flag will be set. Otherwise 7061 * the command will fail with MC_CMD_ERR_FILTERS_PRESENT. 7062 */ 7063 #define MC_CMD_WORKAROUND_BUG26807 0x6 7064 /* enum: Bug 61265 work around (broken EVQ TMR writes). */ 7065 #define MC_CMD_WORKAROUND_BUG61265 0x7 7066 /* 0 = disable the workaround indicated by TYPE; any non-zero value = enable 7067 * the workaround 7068 */ 7069 #define MC_CMD_WORKAROUND_IN_ENABLED_OFST 4 7070 7071 /* MC_CMD_WORKAROUND_OUT msgresponse */ 7072 #define MC_CMD_WORKAROUND_OUT_LEN 0 7073 7074 /* MC_CMD_WORKAROUND_EXT_OUT msgresponse: This response format will be used 7075 * when (TYPE == MC_CMD_WORKAROUND_BUG26807) 7076 */ 7077 #define MC_CMD_WORKAROUND_EXT_OUT_LEN 4 7078 #define MC_CMD_WORKAROUND_EXT_OUT_FLAGS_OFST 0 7079 #define MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN 0 7080 #define MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_WIDTH 1 7081 7082 7083 /***********************************/ 7084 /* MC_CMD_GET_PHY_MEDIA_INFO 7085 * Read media-specific data from PHY (e.g. SFP/SFP+ module ID information for 7086 * SFP+ PHYs). The 'media type' can be found via GET_PHY_CFG 7087 * (GET_PHY_CFG_OUT_MEDIA_TYPE); the valid 'page number' input values, and the 7088 * output data, are interpreted on a per-type basis. For SFP+: PAGE=0 or 1 7089 * returns a 128-byte block read from module I2C address 0xA0 offset 0 or 0x80. 7090 * Anything else: currently undefined. Locks required: None. Return code: 0. 7091 */ 7092 #define MC_CMD_GET_PHY_MEDIA_INFO 0x4b 7093 #undef MC_CMD_0x4b_PRIVILEGE_CTG 7094 7095 #define MC_CMD_0x4b_PRIVILEGE_CTG SRIOV_CTG_ADMIN 7096 7097 /* MC_CMD_GET_PHY_MEDIA_INFO_IN msgrequest */ 7098 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_LEN 4 7099 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_PAGE_OFST 0 7100 7101 /* MC_CMD_GET_PHY_MEDIA_INFO_OUT msgresponse */ 7102 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMIN 5 7103 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMAX 252 7104 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LEN(num) (4+1*(num)) 7105 /* in bytes */ 7106 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATALEN_OFST 0 7107 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_OFST 4 7108 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_LEN 1 7109 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MINNUM 1 7110 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MAXNUM 248 7111 7112 7113 /***********************************/ 7114 /* MC_CMD_NVRAM_TEST 7115 * Test a particular NVRAM partition for valid contents (where "valid" depends 7116 * on the type of partition). 7117 */ 7118 #define MC_CMD_NVRAM_TEST 0x4c 7119 #undef MC_CMD_0x4c_PRIVILEGE_CTG 7120 7121 #define MC_CMD_0x4c_PRIVILEGE_CTG SRIOV_CTG_ADMIN 7122 7123 /* MC_CMD_NVRAM_TEST_IN msgrequest */ 7124 #define MC_CMD_NVRAM_TEST_IN_LEN 4 7125 #define MC_CMD_NVRAM_TEST_IN_TYPE_OFST 0 7126 /* Enum values, see field(s): */ 7127 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 7128 7129 /* MC_CMD_NVRAM_TEST_OUT msgresponse */ 7130 #define MC_CMD_NVRAM_TEST_OUT_LEN 4 7131 #define MC_CMD_NVRAM_TEST_OUT_RESULT_OFST 0 7132 /* enum: Passed. */ 7133 #define MC_CMD_NVRAM_TEST_PASS 0x0 7134 /* enum: Failed. */ 7135 #define MC_CMD_NVRAM_TEST_FAIL 0x1 7136 /* enum: Not supported. */ 7137 #define MC_CMD_NVRAM_TEST_NOTSUPP 0x2 7138 7139 7140 /***********************************/ 7141 /* MC_CMD_MRSFP_TWEAK 7142 * Read status and/or set parameters for the 'mrsfp' driver in mr_rusty builds. 7143 * I2C I/O expander bits are always read; if equaliser parameters are supplied, 7144 * they are configured first. Locks required: None. Return code: 0, EINVAL. 7145 */ 7146 #define MC_CMD_MRSFP_TWEAK 0x4d 7147 7148 /* MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG msgrequest */ 7149 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_LEN 16 7150 /* 0-6 low->high de-emph. */ 7151 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_LEVEL_OFST 0 7152 /* 0-8 low->high ref.V */ 7153 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_DT_CFG_OFST 4 7154 /* 0-8 0-8 low->high boost */ 7155 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_BOOST_OFST 8 7156 /* 0-8 low->high ref.V */ 7157 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_DT_CFG_OFST 12 7158 7159 /* MC_CMD_MRSFP_TWEAK_IN_READ_ONLY msgrequest */ 7160 #define MC_CMD_MRSFP_TWEAK_IN_READ_ONLY_LEN 0 7161 7162 /* MC_CMD_MRSFP_TWEAK_OUT msgresponse */ 7163 #define MC_CMD_MRSFP_TWEAK_OUT_LEN 12 7164 /* input bits */ 7165 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_INPUTS_OFST 0 7166 /* output bits */ 7167 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_OUTPUTS_OFST 4 7168 /* direction */ 7169 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OFST 8 7170 /* enum: Out. */ 7171 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OUT 0x0 7172 /* enum: In. */ 7173 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_IN 0x1 7174 7175 7176 /***********************************/ 7177 /* MC_CMD_SENSOR_SET_LIMS 7178 * Adjusts the sensor limits. This is a warranty-voiding operation. Returns: 7179 * ENOENT if the sensor specified does not exist, EINVAL if the limits are out 7180 * of range. 7181 */ 7182 #define MC_CMD_SENSOR_SET_LIMS 0x4e 7183 #undef MC_CMD_0x4e_PRIVILEGE_CTG 7184 7185 #define MC_CMD_0x4e_PRIVILEGE_CTG SRIOV_CTG_ADMIN 7186 7187 /* MC_CMD_SENSOR_SET_LIMS_IN msgrequest */ 7188 #define MC_CMD_SENSOR_SET_LIMS_IN_LEN 20 7189 #define MC_CMD_SENSOR_SET_LIMS_IN_SENSOR_OFST 0 7190 /* Enum values, see field(s): */ 7191 /* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */ 7192 /* interpretation is is sensor-specific. */ 7193 #define MC_CMD_SENSOR_SET_LIMS_IN_LOW0_OFST 4 7194 /* interpretation is is sensor-specific. */ 7195 #define MC_CMD_SENSOR_SET_LIMS_IN_HI0_OFST 8 7196 /* interpretation is is sensor-specific. */ 7197 #define MC_CMD_SENSOR_SET_LIMS_IN_LOW1_OFST 12 7198 /* interpretation is is sensor-specific. */ 7199 #define MC_CMD_SENSOR_SET_LIMS_IN_HI1_OFST 16 7200 7201 /* MC_CMD_SENSOR_SET_LIMS_OUT msgresponse */ 7202 #define MC_CMD_SENSOR_SET_LIMS_OUT_LEN 0 7203 7204 7205 /***********************************/ 7206 /* MC_CMD_GET_RESOURCE_LIMITS 7207 */ 7208 #define MC_CMD_GET_RESOURCE_LIMITS 0x4f 7209 7210 /* MC_CMD_GET_RESOURCE_LIMITS_IN msgrequest */ 7211 #define MC_CMD_GET_RESOURCE_LIMITS_IN_LEN 0 7212 7213 /* MC_CMD_GET_RESOURCE_LIMITS_OUT msgresponse */ 7214 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_LEN 16 7215 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_BUFTBL_OFST 0 7216 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_EVQ_OFST 4 7217 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_RXQ_OFST 8 7218 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_TXQ_OFST 12 7219 7220 7221 /***********************************/ 7222 /* MC_CMD_NVRAM_PARTITIONS 7223 * Reads the list of available virtual NVRAM partition types. Locks required: 7224 * none. Returns: 0, EINVAL (bad type). 7225 */ 7226 #define MC_CMD_NVRAM_PARTITIONS 0x51 7227 #undef MC_CMD_0x51_PRIVILEGE_CTG 7228 7229 #define MC_CMD_0x51_PRIVILEGE_CTG SRIOV_CTG_ADMIN 7230 7231 /* MC_CMD_NVRAM_PARTITIONS_IN msgrequest */ 7232 #define MC_CMD_NVRAM_PARTITIONS_IN_LEN 0 7233 7234 /* MC_CMD_NVRAM_PARTITIONS_OUT msgresponse */ 7235 #define MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN 4 7236 #define MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX 252 7237 #define MC_CMD_NVRAM_PARTITIONS_OUT_LEN(num) (4+4*(num)) 7238 /* total number of partitions */ 7239 #define MC_CMD_NVRAM_PARTITIONS_OUT_NUM_PARTITIONS_OFST 0 7240 /* type ID code for each of NUM_PARTITIONS partitions */ 7241 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_OFST 4 7242 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_LEN 4 7243 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MINNUM 0 7244 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MAXNUM 62 7245 7246 7247 /***********************************/ 7248 /* MC_CMD_NVRAM_METADATA 7249 * Reads soft metadata for a virtual NVRAM partition type. Locks required: 7250 * none. Returns: 0, EINVAL (bad type). 7251 */ 7252 #define MC_CMD_NVRAM_METADATA 0x52 7253 #undef MC_CMD_0x52_PRIVILEGE_CTG 7254 7255 #define MC_CMD_0x52_PRIVILEGE_CTG SRIOV_CTG_ADMIN 7256 7257 /* MC_CMD_NVRAM_METADATA_IN msgrequest */ 7258 #define MC_CMD_NVRAM_METADATA_IN_LEN 4 7259 /* Partition type ID code */ 7260 #define MC_CMD_NVRAM_METADATA_IN_TYPE_OFST 0 7261 7262 /* MC_CMD_NVRAM_METADATA_OUT msgresponse */ 7263 #define MC_CMD_NVRAM_METADATA_OUT_LENMIN 20 7264 #define MC_CMD_NVRAM_METADATA_OUT_LENMAX 252 7265 #define MC_CMD_NVRAM_METADATA_OUT_LEN(num) (20+1*(num)) 7266 /* Partition type ID code */ 7267 #define MC_CMD_NVRAM_METADATA_OUT_TYPE_OFST 0 7268 #define MC_CMD_NVRAM_METADATA_OUT_FLAGS_OFST 4 7269 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN 0 7270 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_WIDTH 1 7271 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_LBN 1 7272 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_WIDTH 1 7273 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_LBN 2 7274 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_WIDTH 1 7275 /* Subtype ID code for content of this partition */ 7276 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_OFST 8 7277 /* 1st component of W.X.Y.Z version number for content of this partition */ 7278 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_W_OFST 12 7279 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_W_LEN 2 7280 /* 2nd component of W.X.Y.Z version number for content of this partition */ 7281 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_X_OFST 14 7282 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_X_LEN 2 7283 /* 3rd component of W.X.Y.Z version number for content of this partition */ 7284 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Y_OFST 16 7285 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Y_LEN 2 7286 /* 4th component of W.X.Y.Z version number for content of this partition */ 7287 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Z_OFST 18 7288 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Z_LEN 2 7289 /* Zero-terminated string describing the content of this partition */ 7290 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_OFST 20 7291 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_LEN 1 7292 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MINNUM 0 7293 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MAXNUM 232 7294 7295 7296 /***********************************/ 7297 /* MC_CMD_GET_MAC_ADDRESSES 7298 * Returns the base MAC, count and stride for the requesting function 7299 */ 7300 #define MC_CMD_GET_MAC_ADDRESSES 0x55 7301 #undef MC_CMD_0x55_PRIVILEGE_CTG 7302 7303 #define MC_CMD_0x55_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7304 7305 /* MC_CMD_GET_MAC_ADDRESSES_IN msgrequest */ 7306 #define MC_CMD_GET_MAC_ADDRESSES_IN_LEN 0 7307 7308 /* MC_CMD_GET_MAC_ADDRESSES_OUT msgresponse */ 7309 #define MC_CMD_GET_MAC_ADDRESSES_OUT_LEN 16 7310 /* Base MAC address */ 7311 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE_OFST 0 7312 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE_LEN 6 7313 /* Padding */ 7314 #define MC_CMD_GET_MAC_ADDRESSES_OUT_RESERVED_OFST 6 7315 #define MC_CMD_GET_MAC_ADDRESSES_OUT_RESERVED_LEN 2 7316 /* Number of allocated MAC addresses */ 7317 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_COUNT_OFST 8 7318 /* Spacing of allocated MAC addresses */ 7319 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_STRIDE_OFST 12 7320 7321 7322 /***********************************/ 7323 /* MC_CMD_CLP 7324 * Perform a CLP related operation 7325 */ 7326 #define MC_CMD_CLP 0x56 7327 #undef MC_CMD_0x56_PRIVILEGE_CTG 7328 7329 #define MC_CMD_0x56_PRIVILEGE_CTG SRIOV_CTG_ADMIN 7330 7331 /* MC_CMD_CLP_IN msgrequest */ 7332 #define MC_CMD_CLP_IN_LEN 4 7333 /* Sub operation */ 7334 #define MC_CMD_CLP_IN_OP_OFST 0 7335 /* enum: Return to factory default settings */ 7336 #define MC_CMD_CLP_OP_DEFAULT 0x1 7337 /* enum: Set MAC address */ 7338 #define MC_CMD_CLP_OP_SET_MAC 0x2 7339 /* enum: Get MAC address */ 7340 #define MC_CMD_CLP_OP_GET_MAC 0x3 7341 /* enum: Set UEFI/GPXE boot mode */ 7342 #define MC_CMD_CLP_OP_SET_BOOT 0x4 7343 /* enum: Get UEFI/GPXE boot mode */ 7344 #define MC_CMD_CLP_OP_GET_BOOT 0x5 7345 7346 /* MC_CMD_CLP_OUT msgresponse */ 7347 #define MC_CMD_CLP_OUT_LEN 0 7348 7349 /* MC_CMD_CLP_IN_DEFAULT msgrequest */ 7350 #define MC_CMD_CLP_IN_DEFAULT_LEN 4 7351 /* MC_CMD_CLP_IN_OP_OFST 0 */ 7352 7353 /* MC_CMD_CLP_OUT_DEFAULT msgresponse */ 7354 #define MC_CMD_CLP_OUT_DEFAULT_LEN 0 7355 7356 /* MC_CMD_CLP_IN_SET_MAC msgrequest */ 7357 #define MC_CMD_CLP_IN_SET_MAC_LEN 12 7358 /* MC_CMD_CLP_IN_OP_OFST 0 */ 7359 /* MAC address assigned to port */ 7360 #define MC_CMD_CLP_IN_SET_MAC_ADDR_OFST 4 7361 #define MC_CMD_CLP_IN_SET_MAC_ADDR_LEN 6 7362 /* Padding */ 7363 #define MC_CMD_CLP_IN_SET_MAC_RESERVED_OFST 10 7364 #define MC_CMD_CLP_IN_SET_MAC_RESERVED_LEN 2 7365 7366 /* MC_CMD_CLP_OUT_SET_MAC msgresponse */ 7367 #define MC_CMD_CLP_OUT_SET_MAC_LEN 0 7368 7369 /* MC_CMD_CLP_IN_GET_MAC msgrequest */ 7370 #define MC_CMD_CLP_IN_GET_MAC_LEN 4 7371 /* MC_CMD_CLP_IN_OP_OFST 0 */ 7372 7373 /* MC_CMD_CLP_OUT_GET_MAC msgresponse */ 7374 #define MC_CMD_CLP_OUT_GET_MAC_LEN 8 7375 /* MAC address assigned to port */ 7376 #define MC_CMD_CLP_OUT_GET_MAC_ADDR_OFST 0 7377 #define MC_CMD_CLP_OUT_GET_MAC_ADDR_LEN 6 7378 /* Padding */ 7379 #define MC_CMD_CLP_OUT_GET_MAC_RESERVED_OFST 6 7380 #define MC_CMD_CLP_OUT_GET_MAC_RESERVED_LEN 2 7381 7382 /* MC_CMD_CLP_IN_SET_BOOT msgrequest */ 7383 #define MC_CMD_CLP_IN_SET_BOOT_LEN 5 7384 /* MC_CMD_CLP_IN_OP_OFST 0 */ 7385 /* Boot flag */ 7386 #define MC_CMD_CLP_IN_SET_BOOT_FLAG_OFST 4 7387 #define MC_CMD_CLP_IN_SET_BOOT_FLAG_LEN 1 7388 7389 /* MC_CMD_CLP_OUT_SET_BOOT msgresponse */ 7390 #define MC_CMD_CLP_OUT_SET_BOOT_LEN 0 7391 7392 /* MC_CMD_CLP_IN_GET_BOOT msgrequest */ 7393 #define MC_CMD_CLP_IN_GET_BOOT_LEN 4 7394 /* MC_CMD_CLP_IN_OP_OFST 0 */ 7395 7396 /* MC_CMD_CLP_OUT_GET_BOOT msgresponse */ 7397 #define MC_CMD_CLP_OUT_GET_BOOT_LEN 4 7398 /* Boot flag */ 7399 #define MC_CMD_CLP_OUT_GET_BOOT_FLAG_OFST 0 7400 #define MC_CMD_CLP_OUT_GET_BOOT_FLAG_LEN 1 7401 /* Padding */ 7402 #define MC_CMD_CLP_OUT_GET_BOOT_RESERVED_OFST 1 7403 #define MC_CMD_CLP_OUT_GET_BOOT_RESERVED_LEN 3 7404 7405 7406 /***********************************/ 7407 /* MC_CMD_MUM 7408 * Perform a MUM operation 7409 */ 7410 #define MC_CMD_MUM 0x57 7411 #undef MC_CMD_0x57_PRIVILEGE_CTG 7412 7413 #define MC_CMD_0x57_PRIVILEGE_CTG SRIOV_CTG_ADMIN 7414 7415 /* MC_CMD_MUM_IN msgrequest */ 7416 #define MC_CMD_MUM_IN_LEN 4 7417 #define MC_CMD_MUM_IN_OP_HDR_OFST 0 7418 #define MC_CMD_MUM_IN_OP_LBN 0 7419 #define MC_CMD_MUM_IN_OP_WIDTH 8 7420 /* enum: NULL MCDI command to MUM */ 7421 #define MC_CMD_MUM_OP_NULL 0x1 7422 /* enum: Get MUM version */ 7423 #define MC_CMD_MUM_OP_GET_VERSION 0x2 7424 /* enum: Issue raw I2C command to MUM */ 7425 #define MC_CMD_MUM_OP_RAW_CMD 0x3 7426 /* enum: Read from registers on devices connected to MUM. */ 7427 #define MC_CMD_MUM_OP_READ 0x4 7428 /* enum: Write to registers on devices connected to MUM. */ 7429 #define MC_CMD_MUM_OP_WRITE 0x5 7430 /* enum: Control UART logging. */ 7431 #define MC_CMD_MUM_OP_LOG 0x6 7432 /* enum: Operations on MUM GPIO lines */ 7433 #define MC_CMD_MUM_OP_GPIO 0x7 7434 /* enum: Get sensor readings from MUM */ 7435 #define MC_CMD_MUM_OP_READ_SENSORS 0x8 7436 /* enum: Initiate clock programming on the MUM */ 7437 #define MC_CMD_MUM_OP_PROGRAM_CLOCKS 0x9 7438 /* enum: Initiate FPGA load from flash on the MUM */ 7439 #define MC_CMD_MUM_OP_FPGA_LOAD 0xa 7440 /* enum: Request sensor reading from MUM ADC resulting from earlier request via 7441 * MUM ATB 7442 */ 7443 #define MC_CMD_MUM_OP_READ_ATB_SENSOR 0xb 7444 /* enum: Send commands relating to the QSFP ports via the MUM for PHY 7445 * operations 7446 */ 7447 #define MC_CMD_MUM_OP_QSFP 0xc 7448 /* enum: Request discrete and SODIMM DDR info (type, size, speed grade, voltage 7449 * level) from MUM 7450 */ 7451 #define MC_CMD_MUM_OP_READ_DDR_INFO 0xd 7452 7453 /* MC_CMD_MUM_IN_NULL msgrequest */ 7454 #define MC_CMD_MUM_IN_NULL_LEN 4 7455 /* MUM cmd header */ 7456 #define MC_CMD_MUM_IN_CMD_OFST 0 7457 7458 /* MC_CMD_MUM_IN_GET_VERSION msgrequest */ 7459 #define MC_CMD_MUM_IN_GET_VERSION_LEN 4 7460 /* MUM cmd header */ 7461 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7462 7463 /* MC_CMD_MUM_IN_READ msgrequest */ 7464 #define MC_CMD_MUM_IN_READ_LEN 16 7465 /* MUM cmd header */ 7466 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7467 /* ID of (device connected to MUM) to read from registers of */ 7468 #define MC_CMD_MUM_IN_READ_DEVICE_OFST 4 7469 /* enum: Hittite HMC1035 clock generator on Sorrento board */ 7470 #define MC_CMD_MUM_DEV_HITTITE 0x1 7471 /* enum: Hittite HMC1035 clock generator for NIC-side on Sorrento board */ 7472 #define MC_CMD_MUM_DEV_HITTITE_NIC 0x2 7473 /* 32-bit address to read from */ 7474 #define MC_CMD_MUM_IN_READ_ADDR_OFST 8 7475 /* Number of words to read. */ 7476 #define MC_CMD_MUM_IN_READ_NUMWORDS_OFST 12 7477 7478 /* MC_CMD_MUM_IN_WRITE msgrequest */ 7479 #define MC_CMD_MUM_IN_WRITE_LENMIN 16 7480 #define MC_CMD_MUM_IN_WRITE_LENMAX 252 7481 #define MC_CMD_MUM_IN_WRITE_LEN(num) (12+4*(num)) 7482 /* MUM cmd header */ 7483 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7484 /* ID of (device connected to MUM) to write to registers of */ 7485 #define MC_CMD_MUM_IN_WRITE_DEVICE_OFST 4 7486 /* enum: Hittite HMC1035 clock generator on Sorrento board */ 7487 /* MC_CMD_MUM_DEV_HITTITE 0x1 */ 7488 /* 32-bit address to write to */ 7489 #define MC_CMD_MUM_IN_WRITE_ADDR_OFST 8 7490 /* Words to write */ 7491 #define MC_CMD_MUM_IN_WRITE_BUFFER_OFST 12 7492 #define MC_CMD_MUM_IN_WRITE_BUFFER_LEN 4 7493 #define MC_CMD_MUM_IN_WRITE_BUFFER_MINNUM 1 7494 #define MC_CMD_MUM_IN_WRITE_BUFFER_MAXNUM 60 7495 7496 /* MC_CMD_MUM_IN_RAW_CMD msgrequest */ 7497 #define MC_CMD_MUM_IN_RAW_CMD_LENMIN 17 7498 #define MC_CMD_MUM_IN_RAW_CMD_LENMAX 252 7499 #define MC_CMD_MUM_IN_RAW_CMD_LEN(num) (16+1*(num)) 7500 /* MUM cmd header */ 7501 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7502 /* MUM I2C cmd code */ 7503 #define MC_CMD_MUM_IN_RAW_CMD_CMD_CODE_OFST 4 7504 /* Number of bytes to write */ 7505 #define MC_CMD_MUM_IN_RAW_CMD_NUM_WRITE_OFST 8 7506 /* Number of bytes to read */ 7507 #define MC_CMD_MUM_IN_RAW_CMD_NUM_READ_OFST 12 7508 /* Bytes to write */ 7509 #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_OFST 16 7510 #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_LEN 1 7511 #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_MINNUM 1 7512 #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_MAXNUM 236 7513 7514 /* MC_CMD_MUM_IN_LOG msgrequest */ 7515 #define MC_CMD_MUM_IN_LOG_LEN 8 7516 /* MUM cmd header */ 7517 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7518 #define MC_CMD_MUM_IN_LOG_OP_OFST 4 7519 #define MC_CMD_MUM_IN_LOG_OP_UART 0x1 /* enum */ 7520 7521 /* MC_CMD_MUM_IN_LOG_OP_UART msgrequest */ 7522 #define MC_CMD_MUM_IN_LOG_OP_UART_LEN 12 7523 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7524 /* MC_CMD_MUM_IN_LOG_OP_OFST 4 */ 7525 /* Enable/disable debug output to UART */ 7526 #define MC_CMD_MUM_IN_LOG_OP_UART_ENABLE_OFST 8 7527 7528 /* MC_CMD_MUM_IN_GPIO msgrequest */ 7529 #define MC_CMD_MUM_IN_GPIO_LEN 8 7530 /* MUM cmd header */ 7531 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7532 #define MC_CMD_MUM_IN_GPIO_HDR_OFST 4 7533 #define MC_CMD_MUM_IN_GPIO_OPCODE_LBN 0 7534 #define MC_CMD_MUM_IN_GPIO_OPCODE_WIDTH 8 7535 #define MC_CMD_MUM_IN_GPIO_IN_READ 0x0 /* enum */ 7536 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE 0x1 /* enum */ 7537 #define MC_CMD_MUM_IN_GPIO_OUT_READ 0x2 /* enum */ 7538 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE 0x3 /* enum */ 7539 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ 0x4 /* enum */ 7540 #define MC_CMD_MUM_IN_GPIO_OP 0x5 /* enum */ 7541 7542 /* MC_CMD_MUM_IN_GPIO_IN_READ msgrequest */ 7543 #define MC_CMD_MUM_IN_GPIO_IN_READ_LEN 8 7544 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7545 #define MC_CMD_MUM_IN_GPIO_IN_READ_HDR_OFST 4 7546 7547 /* MC_CMD_MUM_IN_GPIO_OUT_WRITE msgrequest */ 7548 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_LEN 16 7549 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7550 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_HDR_OFST 4 7551 /* The first 32-bit word to be written to the GPIO OUT register. */ 7552 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK1_OFST 8 7553 /* The second 32-bit word to be written to the GPIO OUT register. */ 7554 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK2_OFST 12 7555 7556 /* MC_CMD_MUM_IN_GPIO_OUT_READ msgrequest */ 7557 #define MC_CMD_MUM_IN_GPIO_OUT_READ_LEN 8 7558 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7559 #define MC_CMD_MUM_IN_GPIO_OUT_READ_HDR_OFST 4 7560 7561 /* MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE msgrequest */ 7562 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_LEN 16 7563 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7564 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_HDR_OFST 4 7565 /* The first 32-bit word to be written to the GPIO OUT ENABLE register. */ 7566 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK1_OFST 8 7567 /* The second 32-bit word to be written to the GPIO OUT ENABLE register. */ 7568 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK2_OFST 12 7569 7570 /* MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ msgrequest */ 7571 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_LEN 8 7572 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7573 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_HDR_OFST 4 7574 7575 /* MC_CMD_MUM_IN_GPIO_OP msgrequest */ 7576 #define MC_CMD_MUM_IN_GPIO_OP_LEN 8 7577 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7578 #define MC_CMD_MUM_IN_GPIO_OP_HDR_OFST 4 7579 #define MC_CMD_MUM_IN_GPIO_OP_BITWISE_OP_LBN 8 7580 #define MC_CMD_MUM_IN_GPIO_OP_BITWISE_OP_WIDTH 8 7581 #define MC_CMD_MUM_IN_GPIO_OP_OUT_READ 0x0 /* enum */ 7582 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE 0x1 /* enum */ 7583 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG 0x2 /* enum */ 7584 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE 0x3 /* enum */ 7585 #define MC_CMD_MUM_IN_GPIO_OP_GPIO_NUMBER_LBN 16 7586 #define MC_CMD_MUM_IN_GPIO_OP_GPIO_NUMBER_WIDTH 8 7587 7588 /* MC_CMD_MUM_IN_GPIO_OP_OUT_READ msgrequest */ 7589 #define MC_CMD_MUM_IN_GPIO_OP_OUT_READ_LEN 8 7590 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7591 #define MC_CMD_MUM_IN_GPIO_OP_OUT_READ_HDR_OFST 4 7592 7593 /* MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE msgrequest */ 7594 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_LEN 8 7595 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7596 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_HDR_OFST 4 7597 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_WRITEBIT_LBN 24 7598 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_WRITEBIT_WIDTH 8 7599 7600 /* MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG msgrequest */ 7601 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_LEN 8 7602 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7603 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_HDR_OFST 4 7604 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_CFG_LBN 24 7605 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_CFG_WIDTH 8 7606 7607 /* MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE msgrequest */ 7608 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_LEN 8 7609 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7610 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_HDR_OFST 4 7611 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_ENABLEBIT_LBN 24 7612 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_ENABLEBIT_WIDTH 8 7613 7614 /* MC_CMD_MUM_IN_READ_SENSORS msgrequest */ 7615 #define MC_CMD_MUM_IN_READ_SENSORS_LEN 8 7616 /* MUM cmd header */ 7617 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7618 #define MC_CMD_MUM_IN_READ_SENSORS_PARAMS_OFST 4 7619 #define MC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_LBN 0 7620 #define MC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_WIDTH 8 7621 #define MC_CMD_MUM_IN_READ_SENSORS_NUM_SENSORS_LBN 8 7622 #define MC_CMD_MUM_IN_READ_SENSORS_NUM_SENSORS_WIDTH 8 7623 7624 /* MC_CMD_MUM_IN_PROGRAM_CLOCKS msgrequest */ 7625 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_LEN 12 7626 /* MUM cmd header */ 7627 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7628 /* Bit-mask of clocks to be programmed */ 7629 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_MASK_OFST 4 7630 #define MC_CMD_MUM_CLOCK_ID_FPGA 0x0 /* enum */ 7631 #define MC_CMD_MUM_CLOCK_ID_DDR 0x1 /* enum */ 7632 #define MC_CMD_MUM_CLOCK_ID_NIC 0x2 /* enum */ 7633 /* Control flags for clock programming */ 7634 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_FLAGS_OFST 8 7635 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_LBN 0 7636 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_WIDTH 1 7637 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_NIC_FROM_FPGA_LBN 1 7638 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_NIC_FROM_FPGA_WIDTH 1 7639 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_REF_FROM_XO_LBN 2 7640 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_REF_FROM_XO_WIDTH 1 7641 7642 /* MC_CMD_MUM_IN_FPGA_LOAD msgrequest */ 7643 #define MC_CMD_MUM_IN_FPGA_LOAD_LEN 8 7644 /* MUM cmd header */ 7645 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7646 /* Enable/Disable FPGA config from flash */ 7647 #define MC_CMD_MUM_IN_FPGA_LOAD_ENABLE_OFST 4 7648 7649 /* MC_CMD_MUM_IN_READ_ATB_SENSOR msgrequest */ 7650 #define MC_CMD_MUM_IN_READ_ATB_SENSOR_LEN 4 7651 /* MUM cmd header */ 7652 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7653 7654 /* MC_CMD_MUM_IN_QSFP msgrequest */ 7655 #define MC_CMD_MUM_IN_QSFP_LEN 12 7656 /* MUM cmd header */ 7657 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7658 #define MC_CMD_MUM_IN_QSFP_HDR_OFST 4 7659 #define MC_CMD_MUM_IN_QSFP_OPCODE_LBN 0 7660 #define MC_CMD_MUM_IN_QSFP_OPCODE_WIDTH 4 7661 #define MC_CMD_MUM_IN_QSFP_INIT 0x0 /* enum */ 7662 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE 0x1 /* enum */ 7663 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP 0x2 /* enum */ 7664 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO 0x3 /* enum */ 7665 #define MC_CMD_MUM_IN_QSFP_FILL_STATS 0x4 /* enum */ 7666 #define MC_CMD_MUM_IN_QSFP_POLL_BIST 0x5 /* enum */ 7667 #define MC_CMD_MUM_IN_QSFP_IDX_OFST 8 7668 7669 /* MC_CMD_MUM_IN_QSFP_INIT msgrequest */ 7670 #define MC_CMD_MUM_IN_QSFP_INIT_LEN 16 7671 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7672 #define MC_CMD_MUM_IN_QSFP_INIT_HDR_OFST 4 7673 #define MC_CMD_MUM_IN_QSFP_INIT_IDX_OFST 8 7674 #define MC_CMD_MUM_IN_QSFP_INIT_CAGE_OFST 12 7675 7676 /* MC_CMD_MUM_IN_QSFP_RECONFIGURE msgrequest */ 7677 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_LEN 24 7678 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7679 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_HDR_OFST 4 7680 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_IDX_OFST 8 7681 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_TX_DISABLE_OFST 12 7682 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LANES_OFST 16 7683 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LINK_SPEED_OFST 20 7684 7685 /* MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP msgrequest */ 7686 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_LEN 12 7687 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7688 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_HDR_OFST 4 7689 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_IDX_OFST 8 7690 7691 /* MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO msgrequest */ 7692 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_LEN 16 7693 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7694 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_HDR_OFST 4 7695 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_IDX_OFST 8 7696 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_PAGE_OFST 12 7697 7698 /* MC_CMD_MUM_IN_QSFP_FILL_STATS msgrequest */ 7699 #define MC_CMD_MUM_IN_QSFP_FILL_STATS_LEN 12 7700 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7701 #define MC_CMD_MUM_IN_QSFP_FILL_STATS_HDR_OFST 4 7702 #define MC_CMD_MUM_IN_QSFP_FILL_STATS_IDX_OFST 8 7703 7704 /* MC_CMD_MUM_IN_QSFP_POLL_BIST msgrequest */ 7705 #define MC_CMD_MUM_IN_QSFP_POLL_BIST_LEN 12 7706 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7707 #define MC_CMD_MUM_IN_QSFP_POLL_BIST_HDR_OFST 4 7708 #define MC_CMD_MUM_IN_QSFP_POLL_BIST_IDX_OFST 8 7709 7710 /* MC_CMD_MUM_IN_READ_DDR_INFO msgrequest */ 7711 #define MC_CMD_MUM_IN_READ_DDR_INFO_LEN 4 7712 /* MUM cmd header */ 7713 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7714 7715 /* MC_CMD_MUM_OUT msgresponse */ 7716 #define MC_CMD_MUM_OUT_LEN 0 7717 7718 /* MC_CMD_MUM_OUT_NULL msgresponse */ 7719 #define MC_CMD_MUM_OUT_NULL_LEN 0 7720 7721 /* MC_CMD_MUM_OUT_GET_VERSION msgresponse */ 7722 #define MC_CMD_MUM_OUT_GET_VERSION_LEN 12 7723 #define MC_CMD_MUM_OUT_GET_VERSION_FIRMWARE_OFST 0 7724 #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_OFST 4 7725 #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LEN 8 7726 #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LO_OFST 4 7727 #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_HI_OFST 8 7728 7729 /* MC_CMD_MUM_OUT_RAW_CMD msgresponse */ 7730 #define MC_CMD_MUM_OUT_RAW_CMD_LENMIN 1 7731 #define MC_CMD_MUM_OUT_RAW_CMD_LENMAX 252 7732 #define MC_CMD_MUM_OUT_RAW_CMD_LEN(num) (0+1*(num)) 7733 /* returned data */ 7734 #define MC_CMD_MUM_OUT_RAW_CMD_DATA_OFST 0 7735 #define MC_CMD_MUM_OUT_RAW_CMD_DATA_LEN 1 7736 #define MC_CMD_MUM_OUT_RAW_CMD_DATA_MINNUM 1 7737 #define MC_CMD_MUM_OUT_RAW_CMD_DATA_MAXNUM 252 7738 7739 /* MC_CMD_MUM_OUT_READ msgresponse */ 7740 #define MC_CMD_MUM_OUT_READ_LENMIN 4 7741 #define MC_CMD_MUM_OUT_READ_LENMAX 252 7742 #define MC_CMD_MUM_OUT_READ_LEN(num) (0+4*(num)) 7743 #define MC_CMD_MUM_OUT_READ_BUFFER_OFST 0 7744 #define MC_CMD_MUM_OUT_READ_BUFFER_LEN 4 7745 #define MC_CMD_MUM_OUT_READ_BUFFER_MINNUM 1 7746 #define MC_CMD_MUM_OUT_READ_BUFFER_MAXNUM 63 7747 7748 /* MC_CMD_MUM_OUT_WRITE msgresponse */ 7749 #define MC_CMD_MUM_OUT_WRITE_LEN 0 7750 7751 /* MC_CMD_MUM_OUT_LOG msgresponse */ 7752 #define MC_CMD_MUM_OUT_LOG_LEN 0 7753 7754 /* MC_CMD_MUM_OUT_LOG_OP_UART msgresponse */ 7755 #define MC_CMD_MUM_OUT_LOG_OP_UART_LEN 0 7756 7757 /* MC_CMD_MUM_OUT_GPIO_IN_READ msgresponse */ 7758 #define MC_CMD_MUM_OUT_GPIO_IN_READ_LEN 8 7759 /* The first 32-bit word read from the GPIO IN register. */ 7760 #define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK1_OFST 0 7761 /* The second 32-bit word read from the GPIO IN register. */ 7762 #define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK2_OFST 4 7763 7764 /* MC_CMD_MUM_OUT_GPIO_OUT_WRITE msgresponse */ 7765 #define MC_CMD_MUM_OUT_GPIO_OUT_WRITE_LEN 0 7766 7767 /* MC_CMD_MUM_OUT_GPIO_OUT_READ msgresponse */ 7768 #define MC_CMD_MUM_OUT_GPIO_OUT_READ_LEN 8 7769 /* The first 32-bit word read from the GPIO OUT register. */ 7770 #define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK1_OFST 0 7771 /* The second 32-bit word read from the GPIO OUT register. */ 7772 #define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK2_OFST 4 7773 7774 /* MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_WRITE msgresponse */ 7775 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_WRITE_LEN 0 7776 7777 /* MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ msgresponse */ 7778 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_LEN 8 7779 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK1_OFST 0 7780 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK2_OFST 4 7781 7782 /* MC_CMD_MUM_OUT_GPIO_OP_OUT_READ msgresponse */ 7783 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_LEN 4 7784 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_BIT_READ_OFST 0 7785 7786 /* MC_CMD_MUM_OUT_GPIO_OP_OUT_WRITE msgresponse */ 7787 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_WRITE_LEN 0 7788 7789 /* MC_CMD_MUM_OUT_GPIO_OP_OUT_CONFIG msgresponse */ 7790 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_CONFIG_LEN 0 7791 7792 /* MC_CMD_MUM_OUT_GPIO_OP_OUT_ENABLE msgresponse */ 7793 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_ENABLE_LEN 0 7794 7795 /* MC_CMD_MUM_OUT_READ_SENSORS msgresponse */ 7796 #define MC_CMD_MUM_OUT_READ_SENSORS_LENMIN 4 7797 #define MC_CMD_MUM_OUT_READ_SENSORS_LENMAX 252 7798 #define MC_CMD_MUM_OUT_READ_SENSORS_LEN(num) (0+4*(num)) 7799 #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_OFST 0 7800 #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_LEN 4 7801 #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_MINNUM 1 7802 #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_MAXNUM 63 7803 #define MC_CMD_MUM_OUT_READ_SENSORS_READING_LBN 0 7804 #define MC_CMD_MUM_OUT_READ_SENSORS_READING_WIDTH 16 7805 #define MC_CMD_MUM_OUT_READ_SENSORS_STATE_LBN 16 7806 #define MC_CMD_MUM_OUT_READ_SENSORS_STATE_WIDTH 8 7807 #define MC_CMD_MUM_OUT_READ_SENSORS_TYPE_LBN 24 7808 #define MC_CMD_MUM_OUT_READ_SENSORS_TYPE_WIDTH 8 7809 7810 /* MC_CMD_MUM_OUT_PROGRAM_CLOCKS msgresponse */ 7811 #define MC_CMD_MUM_OUT_PROGRAM_CLOCKS_LEN 4 7812 #define MC_CMD_MUM_OUT_PROGRAM_CLOCKS_OK_MASK_OFST 0 7813 7814 /* MC_CMD_MUM_OUT_FPGA_LOAD msgresponse */ 7815 #define MC_CMD_MUM_OUT_FPGA_LOAD_LEN 0 7816 7817 /* MC_CMD_MUM_OUT_READ_ATB_SENSOR msgresponse */ 7818 #define MC_CMD_MUM_OUT_READ_ATB_SENSOR_LEN 4 7819 #define MC_CMD_MUM_OUT_READ_ATB_SENSOR_RESULT_OFST 0 7820 7821 /* MC_CMD_MUM_OUT_QSFP_INIT msgresponse */ 7822 #define MC_CMD_MUM_OUT_QSFP_INIT_LEN 0 7823 7824 /* MC_CMD_MUM_OUT_QSFP_RECONFIGURE msgresponse */ 7825 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_LEN 8 7826 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LP_CAP_OFST 0 7827 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_FLAGS_OFST 4 7828 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_LBN 0 7829 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_WIDTH 1 7830 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_LBN 1 7831 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_WIDTH 1 7832 7833 /* MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP msgresponse */ 7834 #define MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_LEN 4 7835 #define MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_PORT_PHY_LP_CAP_OFST 0 7836 7837 /* MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO msgresponse */ 7838 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LENMIN 5 7839 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LENMAX 252 7840 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LEN(num) (4+1*(num)) 7841 /* in bytes */ 7842 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATALEN_OFST 0 7843 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_OFST 4 7844 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_LEN 1 7845 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_MINNUM 1 7846 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_MAXNUM 248 7847 7848 /* MC_CMD_MUM_OUT_QSFP_FILL_STATS msgresponse */ 7849 #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_LEN 8 7850 #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PMA_PMD_LINK_UP_OFST 0 7851 #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PCS_LINK_UP_OFST 4 7852 7853 /* MC_CMD_MUM_OUT_QSFP_POLL_BIST msgresponse */ 7854 #define MC_CMD_MUM_OUT_QSFP_POLL_BIST_LEN 4 7855 #define MC_CMD_MUM_OUT_QSFP_POLL_BIST_TEST_OFST 0 7856 7857 /* MC_CMD_MUM_OUT_READ_DDR_INFO msgresponse */ 7858 #define MC_CMD_MUM_OUT_READ_DDR_INFO_LENMIN 24 7859 #define MC_CMD_MUM_OUT_READ_DDR_INFO_LENMAX 248 7860 #define MC_CMD_MUM_OUT_READ_DDR_INFO_LEN(num) (8+8*(num)) 7861 /* Discrete (soldered) DDR resistor strap info */ 7862 #define MC_CMD_MUM_OUT_READ_DDR_INFO_DISCRETE_DDR_INFO_OFST 0 7863 #define MC_CMD_MUM_OUT_READ_DDR_INFO_VRATIO_LBN 0 7864 #define MC_CMD_MUM_OUT_READ_DDR_INFO_VRATIO_WIDTH 16 7865 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED1_LBN 16 7866 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED1_WIDTH 16 7867 /* Number of SODIMM info records */ 7868 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_RECORDS_OFST 4 7869 /* Array of SODIMM info records */ 7870 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_OFST 8 7871 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LEN 8 7872 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LO_OFST 8 7873 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_HI_OFST 12 7874 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MINNUM 2 7875 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MAXNUM 30 7876 #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK_ID_LBN 0 7877 #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK_ID_WIDTH 8 7878 /* enum: SODIMM bank 1 (Top SODIMM for Sorrento) */ 7879 #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK1 0x0 7880 /* enum: SODIMM bank 2 (Bottom SODDIMM for Sorrento) */ 7881 #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK2 0x1 7882 /* enum: Total number of SODIMM banks */ 7883 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_BANKS 0x2 7884 #define MC_CMD_MUM_OUT_READ_DDR_INFO_TYPE_LBN 8 7885 #define MC_CMD_MUM_OUT_READ_DDR_INFO_TYPE_WIDTH 8 7886 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RANK_LBN 16 7887 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RANK_WIDTH 4 7888 #define MC_CMD_MUM_OUT_READ_DDR_INFO_VOLTAGE_LBN 20 7889 #define MC_CMD_MUM_OUT_READ_DDR_INFO_VOLTAGE_WIDTH 4 7890 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NOT_POWERED 0x0 /* enum */ 7891 #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V25 0x1 /* enum */ 7892 #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V35 0x2 /* enum */ 7893 #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V5 0x3 /* enum */ 7894 /* enum: Values 5-15 are reserved for future usage */ 7895 #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V8 0x4 7896 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SIZE_LBN 24 7897 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SIZE_WIDTH 8 7898 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SPEED_LBN 32 7899 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SPEED_WIDTH 16 7900 #define MC_CMD_MUM_OUT_READ_DDR_INFO_STATE_LBN 48 7901 #define MC_CMD_MUM_OUT_READ_DDR_INFO_STATE_WIDTH 4 7902 /* enum: No module present */ 7903 #define MC_CMD_MUM_OUT_READ_DDR_INFO_ABSENT 0x0 7904 /* enum: Module present supported and powered on */ 7905 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_POWERED 0x1 7906 /* enum: Module present but bad type */ 7907 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_TYPE 0x2 7908 /* enum: Module present but incompatible voltage */ 7909 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_VOLTAGE 0x3 7910 /* enum: Module present but unknown SPD */ 7911 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_SPD 0x4 7912 /* enum: Module present but slot cannot support it */ 7913 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_SLOT 0x5 7914 /* enum: Modules may or may not be present, but cannot establish contact by I2C 7915 */ 7916 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NOT_REACHABLE 0x6 7917 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED2_LBN 52 7918 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED2_WIDTH 12 7919 7920 /* MC_CMD_RESOURCE_SPECIFIER enum */ 7921 /* enum: Any */ 7922 #define MC_CMD_RESOURCE_INSTANCE_ANY 0xffffffff 7923 /* enum: None */ 7924 #define MC_CMD_RESOURCE_INSTANCE_NONE 0xfffffffe 7925 7926 /* EVB_PORT_ID structuredef */ 7927 #define EVB_PORT_ID_LEN 4 7928 #define EVB_PORT_ID_PORT_ID_OFST 0 7929 /* enum: An invalid port handle. */ 7930 #define EVB_PORT_ID_NULL 0x0 7931 /* enum: The port assigned to this function.. */ 7932 #define EVB_PORT_ID_ASSIGNED 0x1000000 7933 /* enum: External network port 0 */ 7934 #define EVB_PORT_ID_MAC0 0x2000000 7935 /* enum: External network port 1 */ 7936 #define EVB_PORT_ID_MAC1 0x2000001 7937 /* enum: External network port 2 */ 7938 #define EVB_PORT_ID_MAC2 0x2000002 7939 /* enum: External network port 3 */ 7940 #define EVB_PORT_ID_MAC3 0x2000003 7941 #define EVB_PORT_ID_PORT_ID_LBN 0 7942 #define EVB_PORT_ID_PORT_ID_WIDTH 32 7943 7944 /* EVB_VLAN_TAG structuredef */ 7945 #define EVB_VLAN_TAG_LEN 2 7946 /* The VLAN tag value */ 7947 #define EVB_VLAN_TAG_VLAN_ID_LBN 0 7948 #define EVB_VLAN_TAG_VLAN_ID_WIDTH 12 7949 #define EVB_VLAN_TAG_MODE_LBN 12 7950 #define EVB_VLAN_TAG_MODE_WIDTH 4 7951 /* enum: Insert the VLAN. */ 7952 #define EVB_VLAN_TAG_INSERT 0x0 7953 /* enum: Replace the VLAN if already present. */ 7954 #define EVB_VLAN_TAG_REPLACE 0x1 7955 7956 /* BUFTBL_ENTRY structuredef */ 7957 #define BUFTBL_ENTRY_LEN 12 7958 /* the owner ID */ 7959 #define BUFTBL_ENTRY_OID_OFST 0 7960 #define BUFTBL_ENTRY_OID_LEN 2 7961 #define BUFTBL_ENTRY_OID_LBN 0 7962 #define BUFTBL_ENTRY_OID_WIDTH 16 7963 /* the page parameter as one of ESE_DZ_SMC_PAGE_SIZE_ */ 7964 #define BUFTBL_ENTRY_PGSZ_OFST 2 7965 #define BUFTBL_ENTRY_PGSZ_LEN 2 7966 #define BUFTBL_ENTRY_PGSZ_LBN 16 7967 #define BUFTBL_ENTRY_PGSZ_WIDTH 16 7968 /* the raw 64-bit address field from the SMC, not adjusted for page size */ 7969 #define BUFTBL_ENTRY_RAWADDR_OFST 4 7970 #define BUFTBL_ENTRY_RAWADDR_LEN 8 7971 #define BUFTBL_ENTRY_RAWADDR_LO_OFST 4 7972 #define BUFTBL_ENTRY_RAWADDR_HI_OFST 8 7973 #define BUFTBL_ENTRY_RAWADDR_LBN 32 7974 #define BUFTBL_ENTRY_RAWADDR_WIDTH 64 7975 7976 /* NVRAM_PARTITION_TYPE structuredef */ 7977 #define NVRAM_PARTITION_TYPE_LEN 2 7978 #define NVRAM_PARTITION_TYPE_ID_OFST 0 7979 #define NVRAM_PARTITION_TYPE_ID_LEN 2 7980 /* enum: Primary MC firmware partition */ 7981 #define NVRAM_PARTITION_TYPE_MC_FIRMWARE 0x100 7982 /* enum: Secondary MC firmware partition */ 7983 #define NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP 0x200 7984 /* enum: Expansion ROM partition */ 7985 #define NVRAM_PARTITION_TYPE_EXPANSION_ROM 0x300 7986 /* enum: Static configuration TLV partition */ 7987 #define NVRAM_PARTITION_TYPE_STATIC_CONFIG 0x400 7988 /* enum: Dynamic configuration TLV partition */ 7989 #define NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG 0x500 7990 /* enum: Expansion ROM configuration data for port 0 */ 7991 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0 0x600 7992 /* enum: Synonym for EXPROM_CONFIG_PORT0 as used in pmap files */ 7993 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG 0x600 7994 /* enum: Expansion ROM configuration data for port 1 */ 7995 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1 0x601 7996 /* enum: Expansion ROM configuration data for port 2 */ 7997 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2 0x602 7998 /* enum: Expansion ROM configuration data for port 3 */ 7999 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3 0x603 8000 /* enum: Non-volatile log output partition */ 8001 #define NVRAM_PARTITION_TYPE_LOG 0x700 8002 /* enum: Non-volatile log output of second core on dual-core device */ 8003 #define NVRAM_PARTITION_TYPE_LOG_SLAVE 0x701 8004 /* enum: Device state dump output partition */ 8005 #define NVRAM_PARTITION_TYPE_DUMP 0x800 8006 /* enum: Application license key storage partition */ 8007 #define NVRAM_PARTITION_TYPE_LICENSE 0x900 8008 /* enum: Start of range used for PHY partitions (low 8 bits are the PHY ID) */ 8009 #define NVRAM_PARTITION_TYPE_PHY_MIN 0xa00 8010 /* enum: End of range used for PHY partitions (low 8 bits are the PHY ID) */ 8011 #define NVRAM_PARTITION_TYPE_PHY_MAX 0xaff 8012 /* enum: Primary FPGA partition */ 8013 #define NVRAM_PARTITION_TYPE_FPGA 0xb00 8014 /* enum: Secondary FPGA partition */ 8015 #define NVRAM_PARTITION_TYPE_FPGA_BACKUP 0xb01 8016 /* enum: FC firmware partition */ 8017 #define NVRAM_PARTITION_TYPE_FC_FIRMWARE 0xb02 8018 /* enum: FC License partition */ 8019 #define NVRAM_PARTITION_TYPE_FC_LICENSE 0xb03 8020 /* enum: Non-volatile log output partition for FC */ 8021 #define NVRAM_PARTITION_TYPE_FC_LOG 0xb04 8022 /* enum: MUM firmware partition */ 8023 #define NVRAM_PARTITION_TYPE_MUM_FIRMWARE 0xc00 8024 /* enum: MUM Non-volatile log output partition. */ 8025 #define NVRAM_PARTITION_TYPE_MUM_LOG 0xc01 8026 /* enum: MUM Application table partition. */ 8027 #define NVRAM_PARTITION_TYPE_MUM_APPTABLE 0xc02 8028 /* enum: MUM boot rom partition. */ 8029 #define NVRAM_PARTITION_TYPE_MUM_BOOT_ROM 0xc03 8030 /* enum: MUM production signatures & calibration rom partition. */ 8031 #define NVRAM_PARTITION_TYPE_MUM_PROD_ROM 0xc04 8032 /* enum: MUM user signatures & calibration rom partition. */ 8033 #define NVRAM_PARTITION_TYPE_MUM_USER_ROM 0xc05 8034 /* enum: MUM fuses and lockbits partition. */ 8035 #define NVRAM_PARTITION_TYPE_MUM_FUSELOCK 0xc06 8036 /* enum: UEFI expansion ROM if separate from PXE */ 8037 #define NVRAM_PARTITION_TYPE_EXPANSION_UEFI 0xd00 8038 /* enum: Spare partition 0 */ 8039 #define NVRAM_PARTITION_TYPE_SPARE_0 0x1000 8040 /* enum: Used for XIP code of shmbooted images */ 8041 #define NVRAM_PARTITION_TYPE_XIP_SCRATCH 0x1100 8042 /* enum: Spare partition 2 */ 8043 #define NVRAM_PARTITION_TYPE_SPARE_2 0x1200 8044 /* enum: Manufacturing partition. Used during manufacture to pass information 8045 * between XJTAG and Manftest. 8046 */ 8047 #define NVRAM_PARTITION_TYPE_MANUFACTURING 0x1300 8048 /* enum: Spare partition 4 */ 8049 #define NVRAM_PARTITION_TYPE_SPARE_4 0x1400 8050 /* enum: Spare partition 5 */ 8051 #define NVRAM_PARTITION_TYPE_SPARE_5 0x1500 8052 /* enum: Partition for reporting MC status. See mc_flash_layout.h 8053 * medford_mc_status_hdr_t for layout on Medford. 8054 */ 8055 #define NVRAM_PARTITION_TYPE_STATUS 0x1600 8056 /* enum: Start of reserved value range (firmware may use for any purpose) */ 8057 #define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MIN 0xff00 8058 /* enum: End of reserved value range (firmware may use for any purpose) */ 8059 #define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MAX 0xfffd 8060 /* enum: Recovery partition map (provided if real map is missing or corrupt) */ 8061 #define NVRAM_PARTITION_TYPE_RECOVERY_MAP 0xfffe 8062 /* enum: Partition map (real map as stored in flash) */ 8063 #define NVRAM_PARTITION_TYPE_PARTITION_MAP 0xffff 8064 #define NVRAM_PARTITION_TYPE_ID_LBN 0 8065 #define NVRAM_PARTITION_TYPE_ID_WIDTH 16 8066 8067 /* LICENSED_APP_ID structuredef */ 8068 #define LICENSED_APP_ID_LEN 4 8069 #define LICENSED_APP_ID_ID_OFST 0 8070 /* enum: OpenOnload */ 8071 #define LICENSED_APP_ID_ONLOAD 0x1 8072 /* enum: PTP timestamping */ 8073 #define LICENSED_APP_ID_PTP 0x2 8074 /* enum: SolarCapture Pro */ 8075 #define LICENSED_APP_ID_SOLARCAPTURE_PRO 0x4 8076 /* enum: SolarSecure filter engine */ 8077 #define LICENSED_APP_ID_SOLARSECURE 0x8 8078 /* enum: Performance monitor */ 8079 #define LICENSED_APP_ID_PERF_MONITOR 0x10 8080 /* enum: SolarCapture Live */ 8081 #define LICENSED_APP_ID_SOLARCAPTURE_LIVE 0x20 8082 /* enum: Capture SolarSystem */ 8083 #define LICENSED_APP_ID_CAPTURE_SOLARSYSTEM 0x40 8084 /* enum: Network Access Control */ 8085 #define LICENSED_APP_ID_NETWORK_ACCESS_CONTROL 0x80 8086 /* enum: TCP Direct */ 8087 #define LICENSED_APP_ID_TCP_DIRECT 0x100 8088 /* enum: Low Latency */ 8089 #define LICENSED_APP_ID_LOW_LATENCY 0x200 8090 /* enum: SolarCapture Tap */ 8091 #define LICENSED_APP_ID_SOLARCAPTURE_TAP 0x400 8092 /* enum: Capture SolarSystem 40G */ 8093 #define LICENSED_APP_ID_CAPTURE_SOLARSYSTEM_40G 0x800 8094 /* enum: Capture SolarSystem 1G */ 8095 #define LICENSED_APP_ID_CAPTURE_SOLARSYSTEM_1G 0x1000 8096 #define LICENSED_APP_ID_ID_LBN 0 8097 #define LICENSED_APP_ID_ID_WIDTH 32 8098 8099 /* LICENSED_FEATURES structuredef */ 8100 #define LICENSED_FEATURES_LEN 8 8101 /* Bitmask of licensed firmware features */ 8102 #define LICENSED_FEATURES_MASK_OFST 0 8103 #define LICENSED_FEATURES_MASK_LEN 8 8104 #define LICENSED_FEATURES_MASK_LO_OFST 0 8105 #define LICENSED_FEATURES_MASK_HI_OFST 4 8106 #define LICENSED_FEATURES_RX_CUT_THROUGH_LBN 0 8107 #define LICENSED_FEATURES_RX_CUT_THROUGH_WIDTH 1 8108 #define LICENSED_FEATURES_PIO_LBN 1 8109 #define LICENSED_FEATURES_PIO_WIDTH 1 8110 #define LICENSED_FEATURES_EVQ_TIMER_LBN 2 8111 #define LICENSED_FEATURES_EVQ_TIMER_WIDTH 1 8112 #define LICENSED_FEATURES_CLOCK_LBN 3 8113 #define LICENSED_FEATURES_CLOCK_WIDTH 1 8114 #define LICENSED_FEATURES_RX_TIMESTAMPS_LBN 4 8115 #define LICENSED_FEATURES_RX_TIMESTAMPS_WIDTH 1 8116 #define LICENSED_FEATURES_TX_TIMESTAMPS_LBN 5 8117 #define LICENSED_FEATURES_TX_TIMESTAMPS_WIDTH 1 8118 #define LICENSED_FEATURES_RX_SNIFF_LBN 6 8119 #define LICENSED_FEATURES_RX_SNIFF_WIDTH 1 8120 #define LICENSED_FEATURES_TX_SNIFF_LBN 7 8121 #define LICENSED_FEATURES_TX_SNIFF_WIDTH 1 8122 #define LICENSED_FEATURES_PROXY_FILTER_OPS_LBN 8 8123 #define LICENSED_FEATURES_PROXY_FILTER_OPS_WIDTH 1 8124 #define LICENSED_FEATURES_EVENT_CUT_THROUGH_LBN 9 8125 #define LICENSED_FEATURES_EVENT_CUT_THROUGH_WIDTH 1 8126 #define LICENSED_FEATURES_MASK_LBN 0 8127 #define LICENSED_FEATURES_MASK_WIDTH 64 8128 8129 /* LICENSED_V3_APPS structuredef */ 8130 #define LICENSED_V3_APPS_LEN 8 8131 /* Bitmask of licensed applications */ 8132 #define LICENSED_V3_APPS_MASK_OFST 0 8133 #define LICENSED_V3_APPS_MASK_LEN 8 8134 #define LICENSED_V3_APPS_MASK_LO_OFST 0 8135 #define LICENSED_V3_APPS_MASK_HI_OFST 4 8136 #define LICENSED_V3_APPS_ONLOAD_LBN 0 8137 #define LICENSED_V3_APPS_ONLOAD_WIDTH 1 8138 #define LICENSED_V3_APPS_PTP_LBN 1 8139 #define LICENSED_V3_APPS_PTP_WIDTH 1 8140 #define LICENSED_V3_APPS_SOLARCAPTURE_PRO_LBN 2 8141 #define LICENSED_V3_APPS_SOLARCAPTURE_PRO_WIDTH 1 8142 #define LICENSED_V3_APPS_SOLARSECURE_LBN 3 8143 #define LICENSED_V3_APPS_SOLARSECURE_WIDTH 1 8144 #define LICENSED_V3_APPS_PERF_MONITOR_LBN 4 8145 #define LICENSED_V3_APPS_PERF_MONITOR_WIDTH 1 8146 #define LICENSED_V3_APPS_SOLARCAPTURE_LIVE_LBN 5 8147 #define LICENSED_V3_APPS_SOLARCAPTURE_LIVE_WIDTH 1 8148 #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_LBN 6 8149 #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_WIDTH 1 8150 #define LICENSED_V3_APPS_NETWORK_ACCESS_CONTROL_LBN 7 8151 #define LICENSED_V3_APPS_NETWORK_ACCESS_CONTROL_WIDTH 1 8152 #define LICENSED_V3_APPS_TCP_DIRECT_LBN 8 8153 #define LICENSED_V3_APPS_TCP_DIRECT_WIDTH 1 8154 #define LICENSED_V3_APPS_LOW_LATENCY_LBN 9 8155 #define LICENSED_V3_APPS_LOW_LATENCY_WIDTH 1 8156 #define LICENSED_V3_APPS_SOLARCAPTURE_TAP_LBN 10 8157 #define LICENSED_V3_APPS_SOLARCAPTURE_TAP_WIDTH 1 8158 #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_40G_LBN 11 8159 #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_40G_WIDTH 1 8160 #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_1G_LBN 12 8161 #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_1G_WIDTH 1 8162 #define LICENSED_V3_APPS_MASK_LBN 0 8163 #define LICENSED_V3_APPS_MASK_WIDTH 64 8164 8165 /* LICENSED_V3_FEATURES structuredef */ 8166 #define LICENSED_V3_FEATURES_LEN 8 8167 /* Bitmask of licensed firmware features */ 8168 #define LICENSED_V3_FEATURES_MASK_OFST 0 8169 #define LICENSED_V3_FEATURES_MASK_LEN 8 8170 #define LICENSED_V3_FEATURES_MASK_LO_OFST 0 8171 #define LICENSED_V3_FEATURES_MASK_HI_OFST 4 8172 #define LICENSED_V3_FEATURES_RX_CUT_THROUGH_LBN 0 8173 #define LICENSED_V3_FEATURES_RX_CUT_THROUGH_WIDTH 1 8174 #define LICENSED_V3_FEATURES_PIO_LBN 1 8175 #define LICENSED_V3_FEATURES_PIO_WIDTH 1 8176 #define LICENSED_V3_FEATURES_EVQ_TIMER_LBN 2 8177 #define LICENSED_V3_FEATURES_EVQ_TIMER_WIDTH 1 8178 #define LICENSED_V3_FEATURES_CLOCK_LBN 3 8179 #define LICENSED_V3_FEATURES_CLOCK_WIDTH 1 8180 #define LICENSED_V3_FEATURES_RX_TIMESTAMPS_LBN 4 8181 #define LICENSED_V3_FEATURES_RX_TIMESTAMPS_WIDTH 1 8182 #define LICENSED_V3_FEATURES_TX_TIMESTAMPS_LBN 5 8183 #define LICENSED_V3_FEATURES_TX_TIMESTAMPS_WIDTH 1 8184 #define LICENSED_V3_FEATURES_RX_SNIFF_LBN 6 8185 #define LICENSED_V3_FEATURES_RX_SNIFF_WIDTH 1 8186 #define LICENSED_V3_FEATURES_TX_SNIFF_LBN 7 8187 #define LICENSED_V3_FEATURES_TX_SNIFF_WIDTH 1 8188 #define LICENSED_V3_FEATURES_PROXY_FILTER_OPS_LBN 8 8189 #define LICENSED_V3_FEATURES_PROXY_FILTER_OPS_WIDTH 1 8190 #define LICENSED_V3_FEATURES_EVENT_CUT_THROUGH_LBN 9 8191 #define LICENSED_V3_FEATURES_EVENT_CUT_THROUGH_WIDTH 1 8192 #define LICENSED_V3_FEATURES_MASK_LBN 0 8193 #define LICENSED_V3_FEATURES_MASK_WIDTH 64 8194 8195 /* TX_TIMESTAMP_EVENT structuredef */ 8196 #define TX_TIMESTAMP_EVENT_LEN 6 8197 /* lower 16 bits of timestamp data */ 8198 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_OFST 0 8199 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_LEN 2 8200 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_LBN 0 8201 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_WIDTH 16 8202 /* Type of TX event, ordinary TX completion, low or high part of TX timestamp 8203 */ 8204 #define TX_TIMESTAMP_EVENT_TX_EV_TYPE_OFST 3 8205 #define TX_TIMESTAMP_EVENT_TX_EV_TYPE_LEN 1 8206 /* enum: This is a TX completion event, not a timestamp */ 8207 #define TX_TIMESTAMP_EVENT_TX_EV_COMPLETION 0x0 8208 /* enum: This is the low part of a TX timestamp event */ 8209 #define TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_LO 0x51 8210 /* enum: This is the high part of a TX timestamp event */ 8211 #define TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_HI 0x52 8212 #define TX_TIMESTAMP_EVENT_TX_EV_TYPE_LBN 24 8213 #define TX_TIMESTAMP_EVENT_TX_EV_TYPE_WIDTH 8 8214 /* upper 16 bits of timestamp data */ 8215 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_OFST 4 8216 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_LEN 2 8217 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_LBN 32 8218 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_WIDTH 16 8219 8220 /* RSS_MODE structuredef */ 8221 #define RSS_MODE_LEN 1 8222 /* The RSS mode for a particular packet type is a value from 0 - 15 which can 8223 * be considered as 4 bits selecting which fields are included in the hash. (A 8224 * value 0 effectively disables RSS spreading for the packet type.) The YAML 8225 * generation tools require this structure to be a whole number of bytes wide, 8226 * but only 4 bits are relevant. 8227 */ 8228 #define RSS_MODE_HASH_SELECTOR_OFST 0 8229 #define RSS_MODE_HASH_SELECTOR_LEN 1 8230 #define RSS_MODE_HASH_SRC_ADDR_LBN 0 8231 #define RSS_MODE_HASH_SRC_ADDR_WIDTH 1 8232 #define RSS_MODE_HASH_DST_ADDR_LBN 1 8233 #define RSS_MODE_HASH_DST_ADDR_WIDTH 1 8234 #define RSS_MODE_HASH_SRC_PORT_LBN 2 8235 #define RSS_MODE_HASH_SRC_PORT_WIDTH 1 8236 #define RSS_MODE_HASH_DST_PORT_LBN 3 8237 #define RSS_MODE_HASH_DST_PORT_WIDTH 1 8238 #define RSS_MODE_HASH_SELECTOR_LBN 0 8239 #define RSS_MODE_HASH_SELECTOR_WIDTH 8 8240 8241 /* CTPIO_STATS_MAP structuredef */ 8242 #define CTPIO_STATS_MAP_LEN 4 8243 /* The (function relative) VI number */ 8244 #define CTPIO_STATS_MAP_VI_OFST 0 8245 #define CTPIO_STATS_MAP_VI_LEN 2 8246 #define CTPIO_STATS_MAP_VI_LBN 0 8247 #define CTPIO_STATS_MAP_VI_WIDTH 16 8248 /* The target bucket for the VI */ 8249 #define CTPIO_STATS_MAP_BUCKET_OFST 2 8250 #define CTPIO_STATS_MAP_BUCKET_LEN 2 8251 #define CTPIO_STATS_MAP_BUCKET_LBN 16 8252 #define CTPIO_STATS_MAP_BUCKET_WIDTH 16 8253 8254 8255 /***********************************/ 8256 /* MC_CMD_READ_REGS 8257 * Get a dump of the MCPU registers 8258 */ 8259 #define MC_CMD_READ_REGS 0x50 8260 #undef MC_CMD_0x50_PRIVILEGE_CTG 8261 8262 #define MC_CMD_0x50_PRIVILEGE_CTG SRIOV_CTG_ADMIN 8263 8264 /* MC_CMD_READ_REGS_IN msgrequest */ 8265 #define MC_CMD_READ_REGS_IN_LEN 0 8266 8267 /* MC_CMD_READ_REGS_OUT msgresponse */ 8268 #define MC_CMD_READ_REGS_OUT_LEN 308 8269 /* Whether the corresponding register entry contains a valid value */ 8270 #define MC_CMD_READ_REGS_OUT_MASK_OFST 0 8271 #define MC_CMD_READ_REGS_OUT_MASK_LEN 16 8272 /* Same order as MIPS GDB (r0-r31, sr, lo, hi, bad, cause, 32 x float, fsr, 8273 * fir, fp) 8274 */ 8275 #define MC_CMD_READ_REGS_OUT_REGS_OFST 16 8276 #define MC_CMD_READ_REGS_OUT_REGS_LEN 4 8277 #define MC_CMD_READ_REGS_OUT_REGS_NUM 73 8278 8279 8280 /***********************************/ 8281 /* MC_CMD_INIT_EVQ 8282 * Set up an event queue according to the supplied parameters. The IN arguments 8283 * end with an address for each 4k of host memory required to back the EVQ. 8284 */ 8285 #define MC_CMD_INIT_EVQ 0x80 8286 #undef MC_CMD_0x80_PRIVILEGE_CTG 8287 8288 #define MC_CMD_0x80_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8289 8290 /* MC_CMD_INIT_EVQ_IN msgrequest */ 8291 #define MC_CMD_INIT_EVQ_IN_LENMIN 44 8292 #define MC_CMD_INIT_EVQ_IN_LENMAX 548 8293 #define MC_CMD_INIT_EVQ_IN_LEN(num) (36+8*(num)) 8294 /* Size, in entries */ 8295 #define MC_CMD_INIT_EVQ_IN_SIZE_OFST 0 8296 /* Desired instance. Must be set to a specific instance, which is a function 8297 * local queue index. 8298 */ 8299 #define MC_CMD_INIT_EVQ_IN_INSTANCE_OFST 4 8300 /* The initial timer value. The load value is ignored if the timer mode is DIS. 8301 */ 8302 #define MC_CMD_INIT_EVQ_IN_TMR_LOAD_OFST 8 8303 /* The reload value is ignored in one-shot modes */ 8304 #define MC_CMD_INIT_EVQ_IN_TMR_RELOAD_OFST 12 8305 /* tbd */ 8306 #define MC_CMD_INIT_EVQ_IN_FLAGS_OFST 16 8307 #define MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_LBN 0 8308 #define MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_WIDTH 1 8309 #define MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_LBN 1 8310 #define MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_WIDTH 1 8311 #define MC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_LBN 2 8312 #define MC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_WIDTH 1 8313 #define MC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_LBN 3 8314 #define MC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_WIDTH 1 8315 #define MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_LBN 4 8316 #define MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_WIDTH 1 8317 #define MC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_LBN 5 8318 #define MC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_WIDTH 1 8319 #define MC_CMD_INIT_EVQ_IN_FLAG_USE_TIMER_LBN 6 8320 #define MC_CMD_INIT_EVQ_IN_FLAG_USE_TIMER_WIDTH 1 8321 #define MC_CMD_INIT_EVQ_IN_TMR_MODE_OFST 20 8322 /* enum: Disabled */ 8323 #define MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS 0x0 8324 /* enum: Immediate */ 8325 #define MC_CMD_INIT_EVQ_IN_TMR_IMMED_START 0x1 8326 /* enum: Triggered */ 8327 #define MC_CMD_INIT_EVQ_IN_TMR_TRIG_START 0x2 8328 /* enum: Hold-off */ 8329 #define MC_CMD_INIT_EVQ_IN_TMR_INT_HLDOFF 0x3 8330 /* Target EVQ for wakeups if in wakeup mode. */ 8331 #define MC_CMD_INIT_EVQ_IN_TARGET_EVQ_OFST 24 8332 /* Target interrupt if in interrupting mode (note union with target EVQ). Use 8333 * MC_CMD_RESOURCE_INSTANCE_ANY unless a specific one required for test 8334 * purposes. 8335 */ 8336 #define MC_CMD_INIT_EVQ_IN_IRQ_NUM_OFST 24 8337 /* Event Counter Mode. */ 8338 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_OFST 28 8339 /* enum: Disabled */ 8340 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS 0x0 8341 /* enum: Disabled */ 8342 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_RX 0x1 8343 /* enum: Disabled */ 8344 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_TX 0x2 8345 /* enum: Disabled */ 8346 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_RXTX 0x3 8347 /* Event queue packet count threshold. */ 8348 #define MC_CMD_INIT_EVQ_IN_COUNT_THRSHLD_OFST 32 8349 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 8350 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_OFST 36 8351 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LEN 8 8352 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LO_OFST 36 8353 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_HI_OFST 40 8354 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MINNUM 1 8355 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MAXNUM 64 8356 8357 /* MC_CMD_INIT_EVQ_OUT msgresponse */ 8358 #define MC_CMD_INIT_EVQ_OUT_LEN 4 8359 /* Only valid if INTRFLAG was true */ 8360 #define MC_CMD_INIT_EVQ_OUT_IRQ_OFST 0 8361 8362 /* MC_CMD_INIT_EVQ_V2_IN msgrequest */ 8363 #define MC_CMD_INIT_EVQ_V2_IN_LENMIN 44 8364 #define MC_CMD_INIT_EVQ_V2_IN_LENMAX 548 8365 #define MC_CMD_INIT_EVQ_V2_IN_LEN(num) (36+8*(num)) 8366 /* Size, in entries */ 8367 #define MC_CMD_INIT_EVQ_V2_IN_SIZE_OFST 0 8368 /* Desired instance. Must be set to a specific instance, which is a function 8369 * local queue index. 8370 */ 8371 #define MC_CMD_INIT_EVQ_V2_IN_INSTANCE_OFST 4 8372 /* The initial timer value. The load value is ignored if the timer mode is DIS. 8373 */ 8374 #define MC_CMD_INIT_EVQ_V2_IN_TMR_LOAD_OFST 8 8375 /* The reload value is ignored in one-shot modes */ 8376 #define MC_CMD_INIT_EVQ_V2_IN_TMR_RELOAD_OFST 12 8377 /* tbd */ 8378 #define MC_CMD_INIT_EVQ_V2_IN_FLAGS_OFST 16 8379 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_INTERRUPTING_LBN 0 8380 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_INTERRUPTING_WIDTH 1 8381 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_RPTR_DOS_LBN 1 8382 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_RPTR_DOS_WIDTH 1 8383 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_INT_ARMD_LBN 2 8384 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_INT_ARMD_WIDTH 1 8385 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_CUT_THRU_LBN 3 8386 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_CUT_THRU_WIDTH 1 8387 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_RX_MERGE_LBN 4 8388 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_RX_MERGE_WIDTH 1 8389 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TX_MERGE_LBN 5 8390 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TX_MERGE_WIDTH 1 8391 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_USE_TIMER_LBN 6 8392 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_USE_TIMER_WIDTH 1 8393 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_LBN 7 8394 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_WIDTH 4 8395 /* enum: All initialisation flags specified by host. */ 8396 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_MANUAL 0x0 8397 /* enum: MEDFORD only. Certain initialisation flags specified by host may be 8398 * over-ridden by firmware based on licenses and firmware variant in order to 8399 * provide the lowest latency achievable. See 8400 * MC_CMD_INIT_EVQ_V2/MC_CMD_INIT_EVQ_V2_OUT/FLAGS for list of affected flags. 8401 */ 8402 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_LOW_LATENCY 0x1 8403 /* enum: MEDFORD only. Certain initialisation flags specified by host may be 8404 * over-ridden by firmware based on licenses and firmware variant in order to 8405 * provide the best throughput achievable. See 8406 * MC_CMD_INIT_EVQ_V2/MC_CMD_INIT_EVQ_V2_OUT/FLAGS for list of affected flags. 8407 */ 8408 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_THROUGHPUT 0x2 8409 /* enum: MEDFORD only. Certain initialisation flags may be over-ridden by 8410 * firmware based on licenses and firmware variant. See 8411 * MC_CMD_INIT_EVQ_V2/MC_CMD_INIT_EVQ_V2_OUT/FLAGS for list of affected flags. 8412 */ 8413 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_AUTO 0x3 8414 #define MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_OFST 20 8415 /* enum: Disabled */ 8416 #define MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_DIS 0x0 8417 /* enum: Immediate */ 8418 #define MC_CMD_INIT_EVQ_V2_IN_TMR_IMMED_START 0x1 8419 /* enum: Triggered */ 8420 #define MC_CMD_INIT_EVQ_V2_IN_TMR_TRIG_START 0x2 8421 /* enum: Hold-off */ 8422 #define MC_CMD_INIT_EVQ_V2_IN_TMR_INT_HLDOFF 0x3 8423 /* Target EVQ for wakeups if in wakeup mode. */ 8424 #define MC_CMD_INIT_EVQ_V2_IN_TARGET_EVQ_OFST 24 8425 /* Target interrupt if in interrupting mode (note union with target EVQ). Use 8426 * MC_CMD_RESOURCE_INSTANCE_ANY unless a specific one required for test 8427 * purposes. 8428 */ 8429 #define MC_CMD_INIT_EVQ_V2_IN_IRQ_NUM_OFST 24 8430 /* Event Counter Mode. */ 8431 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_OFST 28 8432 /* enum: Disabled */ 8433 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_DIS 0x0 8434 /* enum: Disabled */ 8435 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_RX 0x1 8436 /* enum: Disabled */ 8437 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_TX 0x2 8438 /* enum: Disabled */ 8439 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_RXTX 0x3 8440 /* Event queue packet count threshold. */ 8441 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_THRSHLD_OFST 32 8442 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 8443 #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_OFST 36 8444 #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_LEN 8 8445 #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_LO_OFST 36 8446 #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_HI_OFST 40 8447 #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_MINNUM 1 8448 #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_MAXNUM 64 8449 8450 /* MC_CMD_INIT_EVQ_V2_OUT msgresponse */ 8451 #define MC_CMD_INIT_EVQ_V2_OUT_LEN 8 8452 /* Only valid if INTRFLAG was true */ 8453 #define MC_CMD_INIT_EVQ_V2_OUT_IRQ_OFST 0 8454 /* Actual configuration applied on the card */ 8455 #define MC_CMD_INIT_EVQ_V2_OUT_FLAGS_OFST 4 8456 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_CUT_THRU_LBN 0 8457 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_CUT_THRU_WIDTH 1 8458 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RX_MERGE_LBN 1 8459 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RX_MERGE_WIDTH 1 8460 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_TX_MERGE_LBN 2 8461 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_TX_MERGE_WIDTH 1 8462 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RXQ_FORCE_EV_MERGING_LBN 3 8463 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RXQ_FORCE_EV_MERGING_WIDTH 1 8464 8465 /* QUEUE_CRC_MODE structuredef */ 8466 #define QUEUE_CRC_MODE_LEN 1 8467 #define QUEUE_CRC_MODE_MODE_LBN 0 8468 #define QUEUE_CRC_MODE_MODE_WIDTH 4 8469 /* enum: No CRC. */ 8470 #define QUEUE_CRC_MODE_NONE 0x0 8471 /* enum: CRC Fiber channel over ethernet. */ 8472 #define QUEUE_CRC_MODE_FCOE 0x1 8473 /* enum: CRC (digest) iSCSI header only. */ 8474 #define QUEUE_CRC_MODE_ISCSI_HDR 0x2 8475 /* enum: CRC (digest) iSCSI header and payload. */ 8476 #define QUEUE_CRC_MODE_ISCSI 0x3 8477 /* enum: CRC Fiber channel over IP over ethernet. */ 8478 #define QUEUE_CRC_MODE_FCOIPOE 0x4 8479 /* enum: CRC MPA. */ 8480 #define QUEUE_CRC_MODE_MPA 0x5 8481 #define QUEUE_CRC_MODE_SPARE_LBN 4 8482 #define QUEUE_CRC_MODE_SPARE_WIDTH 4 8483 8484 8485 /***********************************/ 8486 /* MC_CMD_INIT_RXQ 8487 * set up a receive queue according to the supplied parameters. The IN 8488 * arguments end with an address for each 4k of host memory required to back 8489 * the RXQ. 8490 */ 8491 #define MC_CMD_INIT_RXQ 0x81 8492 #undef MC_CMD_0x81_PRIVILEGE_CTG 8493 8494 #define MC_CMD_0x81_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8495 8496 /* MC_CMD_INIT_RXQ_IN msgrequest: Legacy RXQ_INIT request. Use extended version 8497 * in new code. 8498 */ 8499 #define MC_CMD_INIT_RXQ_IN_LENMIN 36 8500 #define MC_CMD_INIT_RXQ_IN_LENMAX 252 8501 #define MC_CMD_INIT_RXQ_IN_LEN(num) (28+8*(num)) 8502 /* Size, in entries */ 8503 #define MC_CMD_INIT_RXQ_IN_SIZE_OFST 0 8504 /* The EVQ to send events to. This is an index originally specified to INIT_EVQ 8505 */ 8506 #define MC_CMD_INIT_RXQ_IN_TARGET_EVQ_OFST 4 8507 /* The value to put in the event data. Check hardware spec. for valid range. */ 8508 #define MC_CMD_INIT_RXQ_IN_LABEL_OFST 8 8509 /* Desired instance. Must be set to a specific instance, which is a function 8510 * local queue index. 8511 */ 8512 #define MC_CMD_INIT_RXQ_IN_INSTANCE_OFST 12 8513 /* There will be more flags here. */ 8514 #define MC_CMD_INIT_RXQ_IN_FLAGS_OFST 16 8515 #define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_LBN 0 8516 #define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_WIDTH 1 8517 #define MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_LBN 1 8518 #define MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_WIDTH 1 8519 #define MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_LBN 2 8520 #define MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_WIDTH 1 8521 #define MC_CMD_INIT_RXQ_IN_CRC_MODE_LBN 3 8522 #define MC_CMD_INIT_RXQ_IN_CRC_MODE_WIDTH 4 8523 #define MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_LBN 7 8524 #define MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_WIDTH 1 8525 #define MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_LBN 8 8526 #define MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_WIDTH 1 8527 #define MC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_LBN 9 8528 #define MC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_WIDTH 1 8529 #define MC_CMD_INIT_RXQ_IN_UNUSED_LBN 10 8530 #define MC_CMD_INIT_RXQ_IN_UNUSED_WIDTH 1 8531 /* Owner ID to use if in buffer mode (zero if physical) */ 8532 #define MC_CMD_INIT_RXQ_IN_OWNER_ID_OFST 20 8533 /* The port ID associated with the v-adaptor which should contain this DMAQ. */ 8534 #define MC_CMD_INIT_RXQ_IN_PORT_ID_OFST 24 8535 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 8536 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_OFST 28 8537 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LEN 8 8538 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LO_OFST 28 8539 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_HI_OFST 32 8540 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MINNUM 1 8541 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MAXNUM 28 8542 8543 /* MC_CMD_INIT_RXQ_EXT_IN msgrequest: Extended RXQ_INIT with additional mode 8544 * flags 8545 */ 8546 #define MC_CMD_INIT_RXQ_EXT_IN_LEN 544 8547 /* Size, in entries */ 8548 #define MC_CMD_INIT_RXQ_EXT_IN_SIZE_OFST 0 8549 /* The EVQ to send events to. This is an index originally specified to INIT_EVQ 8550 */ 8551 #define MC_CMD_INIT_RXQ_EXT_IN_TARGET_EVQ_OFST 4 8552 /* The value to put in the event data. Check hardware spec. for valid range. */ 8553 #define MC_CMD_INIT_RXQ_EXT_IN_LABEL_OFST 8 8554 /* Desired instance. Must be set to a specific instance, which is a function 8555 * local queue index. 8556 */ 8557 #define MC_CMD_INIT_RXQ_EXT_IN_INSTANCE_OFST 12 8558 /* There will be more flags here. */ 8559 #define MC_CMD_INIT_RXQ_EXT_IN_FLAGS_OFST 16 8560 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_LBN 0 8561 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_WIDTH 1 8562 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT_LBN 1 8563 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT_WIDTH 1 8564 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_TIMESTAMP_LBN 2 8565 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_TIMESTAMP_WIDTH 1 8566 #define MC_CMD_INIT_RXQ_EXT_IN_CRC_MODE_LBN 3 8567 #define MC_CMD_INIT_RXQ_EXT_IN_CRC_MODE_WIDTH 4 8568 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_CHAIN_LBN 7 8569 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_CHAIN_WIDTH 1 8570 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_PREFIX_LBN 8 8571 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_PREFIX_WIDTH 1 8572 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER_LBN 9 8573 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER_WIDTH 1 8574 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_LBN 10 8575 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_WIDTH 4 8576 /* enum: One packet per descriptor (for normal networking) */ 8577 #define MC_CMD_INIT_RXQ_EXT_IN_SINGLE_PACKET 0x0 8578 /* enum: Pack multiple packets into large descriptors (for SolarCapture) */ 8579 #define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM 0x1 8580 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_LBN 14 8581 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_WIDTH 1 8582 #define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE_LBN 15 8583 #define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE_WIDTH 3 8584 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_1M 0x0 /* enum */ 8585 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_512K 0x1 /* enum */ 8586 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_256K 0x2 /* enum */ 8587 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_128K 0x3 /* enum */ 8588 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_64K 0x4 /* enum */ 8589 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES_LBN 18 8590 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 1 8591 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_FORCE_EV_MERGING_LBN 19 8592 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_FORCE_EV_MERGING_WIDTH 1 8593 /* Owner ID to use if in buffer mode (zero if physical) */ 8594 #define MC_CMD_INIT_RXQ_EXT_IN_OWNER_ID_OFST 20 8595 /* The port ID associated with the v-adaptor which should contain this DMAQ. */ 8596 #define MC_CMD_INIT_RXQ_EXT_IN_PORT_ID_OFST 24 8597 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 8598 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_OFST 28 8599 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LEN 8 8600 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LO_OFST 28 8601 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_HI_OFST 32 8602 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_NUM 64 8603 /* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */ 8604 #define MC_CMD_INIT_RXQ_EXT_IN_SNAPSHOT_LENGTH_OFST 540 8605 8606 /* MC_CMD_INIT_RXQ_OUT msgresponse */ 8607 #define MC_CMD_INIT_RXQ_OUT_LEN 0 8608 8609 /* MC_CMD_INIT_RXQ_EXT_OUT msgresponse */ 8610 #define MC_CMD_INIT_RXQ_EXT_OUT_LEN 0 8611 8612 8613 /***********************************/ 8614 /* MC_CMD_INIT_TXQ 8615 */ 8616 #define MC_CMD_INIT_TXQ 0x82 8617 #undef MC_CMD_0x82_PRIVILEGE_CTG 8618 8619 #define MC_CMD_0x82_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8620 8621 /* MC_CMD_INIT_TXQ_IN msgrequest: Legacy INIT_TXQ request. Use extended version 8622 * in new code. 8623 */ 8624 #define MC_CMD_INIT_TXQ_IN_LENMIN 36 8625 #define MC_CMD_INIT_TXQ_IN_LENMAX 252 8626 #define MC_CMD_INIT_TXQ_IN_LEN(num) (28+8*(num)) 8627 /* Size, in entries */ 8628 #define MC_CMD_INIT_TXQ_IN_SIZE_OFST 0 8629 /* The EVQ to send events to. This is an index originally specified to 8630 * INIT_EVQ. 8631 */ 8632 #define MC_CMD_INIT_TXQ_IN_TARGET_EVQ_OFST 4 8633 /* The value to put in the event data. Check hardware spec. for valid range. */ 8634 #define MC_CMD_INIT_TXQ_IN_LABEL_OFST 8 8635 /* Desired instance. Must be set to a specific instance, which is a function 8636 * local queue index. 8637 */ 8638 #define MC_CMD_INIT_TXQ_IN_INSTANCE_OFST 12 8639 /* There will be more flags here. */ 8640 #define MC_CMD_INIT_TXQ_IN_FLAGS_OFST 16 8641 #define MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_LBN 0 8642 #define MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_WIDTH 1 8643 #define MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_LBN 1 8644 #define MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_WIDTH 1 8645 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_LBN 2 8646 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_WIDTH 1 8647 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_LBN 3 8648 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_WIDTH 1 8649 #define MC_CMD_INIT_TXQ_IN_CRC_MODE_LBN 4 8650 #define MC_CMD_INIT_TXQ_IN_CRC_MODE_WIDTH 4 8651 #define MC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_LBN 8 8652 #define MC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_WIDTH 1 8653 #define MC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_LBN 9 8654 #define MC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_WIDTH 1 8655 #define MC_CMD_INIT_TXQ_IN_FLAG_INNER_IP_CSUM_EN_LBN 10 8656 #define MC_CMD_INIT_TXQ_IN_FLAG_INNER_IP_CSUM_EN_WIDTH 1 8657 #define MC_CMD_INIT_TXQ_IN_FLAG_INNER_TCP_CSUM_EN_LBN 11 8658 #define MC_CMD_INIT_TXQ_IN_FLAG_INNER_TCP_CSUM_EN_WIDTH 1 8659 /* Owner ID to use if in buffer mode (zero if physical) */ 8660 #define MC_CMD_INIT_TXQ_IN_OWNER_ID_OFST 20 8661 /* The port ID associated with the v-adaptor which should contain this DMAQ. */ 8662 #define MC_CMD_INIT_TXQ_IN_PORT_ID_OFST 24 8663 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 8664 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_OFST 28 8665 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LEN 8 8666 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LO_OFST 28 8667 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_HI_OFST 32 8668 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MINNUM 1 8669 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MAXNUM 28 8670 8671 /* MC_CMD_INIT_TXQ_EXT_IN msgrequest: Extended INIT_TXQ with additional mode 8672 * flags 8673 */ 8674 #define MC_CMD_INIT_TXQ_EXT_IN_LEN 544 8675 /* Size, in entries */ 8676 #define MC_CMD_INIT_TXQ_EXT_IN_SIZE_OFST 0 8677 /* The EVQ to send events to. This is an index originally specified to 8678 * INIT_EVQ. 8679 */ 8680 #define MC_CMD_INIT_TXQ_EXT_IN_TARGET_EVQ_OFST 4 8681 /* The value to put in the event data. Check hardware spec. for valid range. */ 8682 #define MC_CMD_INIT_TXQ_EXT_IN_LABEL_OFST 8 8683 /* Desired instance. Must be set to a specific instance, which is a function 8684 * local queue index. 8685 */ 8686 #define MC_CMD_INIT_TXQ_EXT_IN_INSTANCE_OFST 12 8687 /* There will be more flags here. */ 8688 #define MC_CMD_INIT_TXQ_EXT_IN_FLAGS_OFST 16 8689 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_BUFF_MODE_LBN 0 8690 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_BUFF_MODE_WIDTH 1 8691 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_IP_CSUM_DIS_LBN 1 8692 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_IP_CSUM_DIS_WIDTH 1 8693 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_CSUM_DIS_LBN 2 8694 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_CSUM_DIS_WIDTH 1 8695 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_UDP_ONLY_LBN 3 8696 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_UDP_ONLY_WIDTH 1 8697 #define MC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_LBN 4 8698 #define MC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_WIDTH 4 8699 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TIMESTAMP_LBN 8 8700 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TIMESTAMP_WIDTH 1 8701 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_PACER_BYPASS_LBN 9 8702 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_PACER_BYPASS_WIDTH 1 8703 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN_LBN 10 8704 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN_WIDTH 1 8705 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN_LBN 11 8706 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN_WIDTH 1 8707 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TSOV2_EN_LBN 12 8708 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TSOV2_EN_WIDTH 1 8709 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_LBN 13 8710 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_WIDTH 1 8711 /* Owner ID to use if in buffer mode (zero if physical) */ 8712 #define MC_CMD_INIT_TXQ_EXT_IN_OWNER_ID_OFST 20 8713 /* The port ID associated with the v-adaptor which should contain this DMAQ. */ 8714 #define MC_CMD_INIT_TXQ_EXT_IN_PORT_ID_OFST 24 8715 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 8716 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_OFST 28 8717 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LEN 8 8718 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LO_OFST 28 8719 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_HI_OFST 32 8720 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MINNUM 1 8721 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MAXNUM 64 8722 /* Flags related to Qbb flow control mode. */ 8723 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_FLAGS_OFST 540 8724 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_ENABLE_LBN 0 8725 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_ENABLE_WIDTH 1 8726 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_PRIORITY_LBN 1 8727 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_PRIORITY_WIDTH 3 8728 8729 /* MC_CMD_INIT_TXQ_OUT msgresponse */ 8730 #define MC_CMD_INIT_TXQ_OUT_LEN 0 8731 8732 8733 /***********************************/ 8734 /* MC_CMD_FINI_EVQ 8735 * Teardown an EVQ. 8736 * 8737 * All DMAQs or EVQs that point to the EVQ to tear down must be torn down first 8738 * or the operation will fail with EBUSY 8739 */ 8740 #define MC_CMD_FINI_EVQ 0x83 8741 #undef MC_CMD_0x83_PRIVILEGE_CTG 8742 8743 #define MC_CMD_0x83_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8744 8745 /* MC_CMD_FINI_EVQ_IN msgrequest */ 8746 #define MC_CMD_FINI_EVQ_IN_LEN 4 8747 /* Instance of EVQ to destroy. Should be the same instance as that previously 8748 * passed to INIT_EVQ 8749 */ 8750 #define MC_CMD_FINI_EVQ_IN_INSTANCE_OFST 0 8751 8752 /* MC_CMD_FINI_EVQ_OUT msgresponse */ 8753 #define MC_CMD_FINI_EVQ_OUT_LEN 0 8754 8755 8756 /***********************************/ 8757 /* MC_CMD_FINI_RXQ 8758 * Teardown a RXQ. 8759 */ 8760 #define MC_CMD_FINI_RXQ 0x84 8761 #undef MC_CMD_0x84_PRIVILEGE_CTG 8762 8763 #define MC_CMD_0x84_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8764 8765 /* MC_CMD_FINI_RXQ_IN msgrequest */ 8766 #define MC_CMD_FINI_RXQ_IN_LEN 4 8767 /* Instance of RXQ to destroy */ 8768 #define MC_CMD_FINI_RXQ_IN_INSTANCE_OFST 0 8769 8770 /* MC_CMD_FINI_RXQ_OUT msgresponse */ 8771 #define MC_CMD_FINI_RXQ_OUT_LEN 0 8772 8773 8774 /***********************************/ 8775 /* MC_CMD_FINI_TXQ 8776 * Teardown a TXQ. 8777 */ 8778 #define MC_CMD_FINI_TXQ 0x85 8779 #undef MC_CMD_0x85_PRIVILEGE_CTG 8780 8781 #define MC_CMD_0x85_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8782 8783 /* MC_CMD_FINI_TXQ_IN msgrequest */ 8784 #define MC_CMD_FINI_TXQ_IN_LEN 4 8785 /* Instance of TXQ to destroy */ 8786 #define MC_CMD_FINI_TXQ_IN_INSTANCE_OFST 0 8787 8788 /* MC_CMD_FINI_TXQ_OUT msgresponse */ 8789 #define MC_CMD_FINI_TXQ_OUT_LEN 0 8790 8791 8792 /***********************************/ 8793 /* MC_CMD_DRIVER_EVENT 8794 * Generate an event on an EVQ belonging to the function issuing the command. 8795 */ 8796 #define MC_CMD_DRIVER_EVENT 0x86 8797 #undef MC_CMD_0x86_PRIVILEGE_CTG 8798 8799 #define MC_CMD_0x86_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8800 8801 /* MC_CMD_DRIVER_EVENT_IN msgrequest */ 8802 #define MC_CMD_DRIVER_EVENT_IN_LEN 12 8803 /* Handle of target EVQ */ 8804 #define MC_CMD_DRIVER_EVENT_IN_EVQ_OFST 0 8805 /* Bits 0 - 63 of event */ 8806 #define MC_CMD_DRIVER_EVENT_IN_DATA_OFST 4 8807 #define MC_CMD_DRIVER_EVENT_IN_DATA_LEN 8 8808 #define MC_CMD_DRIVER_EVENT_IN_DATA_LO_OFST 4 8809 #define MC_CMD_DRIVER_EVENT_IN_DATA_HI_OFST 8 8810 8811 /* MC_CMD_DRIVER_EVENT_OUT msgresponse */ 8812 #define MC_CMD_DRIVER_EVENT_OUT_LEN 0 8813 8814 8815 /***********************************/ 8816 /* MC_CMD_PROXY_CMD 8817 * Execute an arbitrary MCDI command on behalf of a different function, subject 8818 * to security restrictions. The command to be proxied follows immediately 8819 * afterward in the host buffer (or on the UART). This command supercedes 8820 * MC_CMD_SET_FUNC, which remains available for Siena but now deprecated. 8821 */ 8822 #define MC_CMD_PROXY_CMD 0x5b 8823 #undef MC_CMD_0x5b_PRIVILEGE_CTG 8824 8825 #define MC_CMD_0x5b_PRIVILEGE_CTG SRIOV_CTG_ADMIN 8826 8827 /* MC_CMD_PROXY_CMD_IN msgrequest */ 8828 #define MC_CMD_PROXY_CMD_IN_LEN 4 8829 /* The handle of the target function. */ 8830 #define MC_CMD_PROXY_CMD_IN_TARGET_OFST 0 8831 #define MC_CMD_PROXY_CMD_IN_TARGET_PF_LBN 0 8832 #define MC_CMD_PROXY_CMD_IN_TARGET_PF_WIDTH 16 8833 #define MC_CMD_PROXY_CMD_IN_TARGET_VF_LBN 16 8834 #define MC_CMD_PROXY_CMD_IN_TARGET_VF_WIDTH 16 8835 #define MC_CMD_PROXY_CMD_IN_VF_NULL 0xffff /* enum */ 8836 8837 /* MC_CMD_PROXY_CMD_OUT msgresponse */ 8838 #define MC_CMD_PROXY_CMD_OUT_LEN 0 8839 8840 /* MC_PROXY_STATUS_BUFFER structuredef: Host memory status buffer used to 8841 * manage proxied requests 8842 */ 8843 #define MC_PROXY_STATUS_BUFFER_LEN 16 8844 /* Handle allocated by the firmware for this proxy transaction */ 8845 #define MC_PROXY_STATUS_BUFFER_HANDLE_OFST 0 8846 /* enum: An invalid handle. */ 8847 #define MC_PROXY_STATUS_BUFFER_HANDLE_INVALID 0x0 8848 #define MC_PROXY_STATUS_BUFFER_HANDLE_LBN 0 8849 #define MC_PROXY_STATUS_BUFFER_HANDLE_WIDTH 32 8850 /* The requesting physical function number */ 8851 #define MC_PROXY_STATUS_BUFFER_PF_OFST 4 8852 #define MC_PROXY_STATUS_BUFFER_PF_LEN 2 8853 #define MC_PROXY_STATUS_BUFFER_PF_LBN 32 8854 #define MC_PROXY_STATUS_BUFFER_PF_WIDTH 16 8855 /* The requesting virtual function number. Set to VF_NULL if the target is a 8856 * PF. 8857 */ 8858 #define MC_PROXY_STATUS_BUFFER_VF_OFST 6 8859 #define MC_PROXY_STATUS_BUFFER_VF_LEN 2 8860 #define MC_PROXY_STATUS_BUFFER_VF_LBN 48 8861 #define MC_PROXY_STATUS_BUFFER_VF_WIDTH 16 8862 /* The target function RID. */ 8863 #define MC_PROXY_STATUS_BUFFER_RID_OFST 8 8864 #define MC_PROXY_STATUS_BUFFER_RID_LEN 2 8865 #define MC_PROXY_STATUS_BUFFER_RID_LBN 64 8866 #define MC_PROXY_STATUS_BUFFER_RID_WIDTH 16 8867 /* The status of the proxy as described in MC_CMD_PROXY_COMPLETE. */ 8868 #define MC_PROXY_STATUS_BUFFER_STATUS_OFST 10 8869 #define MC_PROXY_STATUS_BUFFER_STATUS_LEN 2 8870 #define MC_PROXY_STATUS_BUFFER_STATUS_LBN 80 8871 #define MC_PROXY_STATUS_BUFFER_STATUS_WIDTH 16 8872 /* If a request is authorized rather than carried out by the host, this is the 8873 * elevated privilege mask granted to the requesting function. 8874 */ 8875 #define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_OFST 12 8876 #define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_LBN 96 8877 #define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_WIDTH 32 8878 8879 8880 /***********************************/ 8881 /* MC_CMD_PROXY_CONFIGURE 8882 * Enable/disable authorization of MCDI requests from unprivileged functions by 8883 * a designated admin function 8884 */ 8885 #define MC_CMD_PROXY_CONFIGURE 0x58 8886 #undef MC_CMD_0x58_PRIVILEGE_CTG 8887 8888 #define MC_CMD_0x58_PRIVILEGE_CTG SRIOV_CTG_ADMIN 8889 8890 /* MC_CMD_PROXY_CONFIGURE_IN msgrequest */ 8891 #define MC_CMD_PROXY_CONFIGURE_IN_LEN 108 8892 #define MC_CMD_PROXY_CONFIGURE_IN_FLAGS_OFST 0 8893 #define MC_CMD_PROXY_CONFIGURE_IN_ENABLE_LBN 0 8894 #define MC_CMD_PROXY_CONFIGURE_IN_ENABLE_WIDTH 1 8895 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 8896 * of blocks, each of the size REQUEST_BLOCK_SIZE. 8897 */ 8898 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_OFST 4 8899 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LEN 8 8900 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LO_OFST 4 8901 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_HI_OFST 8 8902 /* Must be a power of 2 */ 8903 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BLOCK_SIZE_OFST 12 8904 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 8905 * of blocks, each of the size REPLY_BLOCK_SIZE. 8906 */ 8907 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_OFST 16 8908 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LEN 8 8909 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LO_OFST 16 8910 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_HI_OFST 20 8911 /* Must be a power of 2 */ 8912 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BLOCK_SIZE_OFST 24 8913 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 8914 * of blocks, each of the size STATUS_BLOCK_SIZE. This buffer is only needed if 8915 * host intends to complete proxied operations by using MC_CMD_PROXY_CMD. 8916 */ 8917 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_OFST 28 8918 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LEN 8 8919 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LO_OFST 28 8920 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_HI_OFST 32 8921 /* Must be a power of 2, or zero if this buffer is not provided */ 8922 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BLOCK_SIZE_OFST 36 8923 /* Applies to all three buffers */ 8924 #define MC_CMD_PROXY_CONFIGURE_IN_NUM_BLOCKS_OFST 40 8925 /* A bit mask defining which MCDI operations may be proxied */ 8926 #define MC_CMD_PROXY_CONFIGURE_IN_ALLOWED_MCDI_MASK_OFST 44 8927 #define MC_CMD_PROXY_CONFIGURE_IN_ALLOWED_MCDI_MASK_LEN 64 8928 8929 /* MC_CMD_PROXY_CONFIGURE_EXT_IN msgrequest */ 8930 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_LEN 112 8931 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_FLAGS_OFST 0 8932 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_ENABLE_LBN 0 8933 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_ENABLE_WIDTH 1 8934 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 8935 * of blocks, each of the size REQUEST_BLOCK_SIZE. 8936 */ 8937 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_OFST 4 8938 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LEN 8 8939 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LO_OFST 4 8940 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_HI_OFST 8 8941 /* Must be a power of 2 */ 8942 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BLOCK_SIZE_OFST 12 8943 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 8944 * of blocks, each of the size REPLY_BLOCK_SIZE. 8945 */ 8946 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_OFST 16 8947 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_LEN 8 8948 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_LO_OFST 16 8949 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_HI_OFST 20 8950 /* Must be a power of 2 */ 8951 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BLOCK_SIZE_OFST 24 8952 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 8953 * of blocks, each of the size STATUS_BLOCK_SIZE. This buffer is only needed if 8954 * host intends to complete proxied operations by using MC_CMD_PROXY_CMD. 8955 */ 8956 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_OFST 28 8957 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_LEN 8 8958 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_LO_OFST 28 8959 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_HI_OFST 32 8960 /* Must be a power of 2, or zero if this buffer is not provided */ 8961 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BLOCK_SIZE_OFST 36 8962 /* Applies to all three buffers */ 8963 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_NUM_BLOCKS_OFST 40 8964 /* A bit mask defining which MCDI operations may be proxied */ 8965 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_ALLOWED_MCDI_MASK_OFST 44 8966 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_ALLOWED_MCDI_MASK_LEN 64 8967 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_RESERVED_OFST 108 8968 8969 /* MC_CMD_PROXY_CONFIGURE_OUT msgresponse */ 8970 #define MC_CMD_PROXY_CONFIGURE_OUT_LEN 0 8971 8972 8973 /***********************************/ 8974 /* MC_CMD_PROXY_COMPLETE 8975 * Tells FW that a requested proxy operation has either been completed (by 8976 * using MC_CMD_PROXY_CMD) or authorized/declined. May only be sent by the 8977 * function that enabled proxying/authorization (by using 8978 * MC_CMD_PROXY_CONFIGURE). 8979 */ 8980 #define MC_CMD_PROXY_COMPLETE 0x5f 8981 #undef MC_CMD_0x5f_PRIVILEGE_CTG 8982 8983 #define MC_CMD_0x5f_PRIVILEGE_CTG SRIOV_CTG_ADMIN 8984 8985 /* MC_CMD_PROXY_COMPLETE_IN msgrequest */ 8986 #define MC_CMD_PROXY_COMPLETE_IN_LEN 12 8987 #define MC_CMD_PROXY_COMPLETE_IN_BLOCK_INDEX_OFST 0 8988 #define MC_CMD_PROXY_COMPLETE_IN_STATUS_OFST 4 8989 /* enum: The operation has been completed by using MC_CMD_PROXY_CMD, the reply 8990 * is stored in the REPLY_BUFF. 8991 */ 8992 #define MC_CMD_PROXY_COMPLETE_IN_COMPLETE 0x0 8993 /* enum: The operation has been authorized. The originating function may now 8994 * try again. 8995 */ 8996 #define MC_CMD_PROXY_COMPLETE_IN_AUTHORIZED 0x1 8997 /* enum: The operation has been declined. */ 8998 #define MC_CMD_PROXY_COMPLETE_IN_DECLINED 0x2 8999 /* enum: The authorization failed because the relevant application did not 9000 * respond in time. 9001 */ 9002 #define MC_CMD_PROXY_COMPLETE_IN_TIMEDOUT 0x3 9003 #define MC_CMD_PROXY_COMPLETE_IN_HANDLE_OFST 8 9004 9005 /* MC_CMD_PROXY_COMPLETE_OUT msgresponse */ 9006 #define MC_CMD_PROXY_COMPLETE_OUT_LEN 0 9007 9008 9009 /***********************************/ 9010 /* MC_CMD_ALLOC_BUFTBL_CHUNK 9011 * Allocate a set of buffer table entries using the specified owner ID. This 9012 * operation allocates the required buffer table entries (and fails if it 9013 * cannot do so). The buffer table entries will initially be zeroed. 9014 */ 9015 #define MC_CMD_ALLOC_BUFTBL_CHUNK 0x87 9016 #undef MC_CMD_0x87_PRIVILEGE_CTG 9017 9018 #define MC_CMD_0x87_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 9019 9020 /* MC_CMD_ALLOC_BUFTBL_CHUNK_IN msgrequest */ 9021 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_LEN 8 9022 /* Owner ID to use */ 9023 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_OWNER_OFST 0 9024 /* Size of buffer table pages to use, in bytes (note that only a few values are 9025 * legal on any specific hardware). 9026 */ 9027 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_PAGE_SIZE_OFST 4 9028 9029 /* MC_CMD_ALLOC_BUFTBL_CHUNK_OUT msgresponse */ 9030 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_LEN 12 9031 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_HANDLE_OFST 0 9032 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_NUMENTRIES_OFST 4 9033 /* Buffer table IDs for use in DMA descriptors. */ 9034 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_ID_OFST 8 9035 9036 9037 /***********************************/ 9038 /* MC_CMD_PROGRAM_BUFTBL_ENTRIES 9039 * Reprogram a set of buffer table entries in the specified chunk. 9040 */ 9041 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES 0x88 9042 #undef MC_CMD_0x88_PRIVILEGE_CTG 9043 9044 #define MC_CMD_0x88_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 9045 9046 /* MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN msgrequest */ 9047 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMIN 20 9048 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMAX 268 9049 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LEN(num) (12+8*(num)) 9050 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_HANDLE_OFST 0 9051 /* ID */ 9052 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_FIRSTID_OFST 4 9053 /* Num entries */ 9054 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_NUMENTRIES_OFST 8 9055 /* Buffer table entry address */ 9056 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_OFST 12 9057 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LEN 8 9058 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LO_OFST 12 9059 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_HI_OFST 16 9060 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MINNUM 1 9061 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MAXNUM 32 9062 9063 /* MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT msgresponse */ 9064 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT_LEN 0 9065 9066 9067 /***********************************/ 9068 /* MC_CMD_FREE_BUFTBL_CHUNK 9069 */ 9070 #define MC_CMD_FREE_BUFTBL_CHUNK 0x89 9071 #undef MC_CMD_0x89_PRIVILEGE_CTG 9072 9073 #define MC_CMD_0x89_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 9074 9075 /* MC_CMD_FREE_BUFTBL_CHUNK_IN msgrequest */ 9076 #define MC_CMD_FREE_BUFTBL_CHUNK_IN_LEN 4 9077 #define MC_CMD_FREE_BUFTBL_CHUNK_IN_HANDLE_OFST 0 9078 9079 /* MC_CMD_FREE_BUFTBL_CHUNK_OUT msgresponse */ 9080 #define MC_CMD_FREE_BUFTBL_CHUNK_OUT_LEN 0 9081 9082 /* PORT_CONFIG_ENTRY structuredef */ 9083 #define PORT_CONFIG_ENTRY_LEN 16 9084 /* External port number (label) */ 9085 #define PORT_CONFIG_ENTRY_EXT_NUMBER_OFST 0 9086 #define PORT_CONFIG_ENTRY_EXT_NUMBER_LEN 1 9087 #define PORT_CONFIG_ENTRY_EXT_NUMBER_LBN 0 9088 #define PORT_CONFIG_ENTRY_EXT_NUMBER_WIDTH 8 9089 /* Port core location */ 9090 #define PORT_CONFIG_ENTRY_CORE_OFST 1 9091 #define PORT_CONFIG_ENTRY_CORE_LEN 1 9092 #define PORT_CONFIG_ENTRY_STANDALONE 0x0 /* enum */ 9093 #define PORT_CONFIG_ENTRY_MASTER 0x1 /* enum */ 9094 #define PORT_CONFIG_ENTRY_SLAVE 0x2 /* enum */ 9095 #define PORT_CONFIG_ENTRY_CORE_LBN 8 9096 #define PORT_CONFIG_ENTRY_CORE_WIDTH 8 9097 /* Internal number (HW resource) relative to the core */ 9098 #define PORT_CONFIG_ENTRY_INT_NUMBER_OFST 2 9099 #define PORT_CONFIG_ENTRY_INT_NUMBER_LEN 1 9100 #define PORT_CONFIG_ENTRY_INT_NUMBER_LBN 16 9101 #define PORT_CONFIG_ENTRY_INT_NUMBER_WIDTH 8 9102 /* Reserved */ 9103 #define PORT_CONFIG_ENTRY_RSVD_OFST 3 9104 #define PORT_CONFIG_ENTRY_RSVD_LEN 1 9105 #define PORT_CONFIG_ENTRY_RSVD_LBN 24 9106 #define PORT_CONFIG_ENTRY_RSVD_WIDTH 8 9107 /* Bitmask of KR lanes used by the port */ 9108 #define PORT_CONFIG_ENTRY_LANES_OFST 4 9109 #define PORT_CONFIG_ENTRY_LANES_LBN 32 9110 #define PORT_CONFIG_ENTRY_LANES_WIDTH 32 9111 /* Port capabilities (MC_CMD_PHY_CAP_*) */ 9112 #define PORT_CONFIG_ENTRY_SUPPORTED_CAPS_OFST 8 9113 #define PORT_CONFIG_ENTRY_SUPPORTED_CAPS_LBN 64 9114 #define PORT_CONFIG_ENTRY_SUPPORTED_CAPS_WIDTH 32 9115 /* Reserved (align to 16 bytes) */ 9116 #define PORT_CONFIG_ENTRY_RSVD2_OFST 12 9117 #define PORT_CONFIG_ENTRY_RSVD2_LBN 96 9118 #define PORT_CONFIG_ENTRY_RSVD2_WIDTH 32 9119 9120 9121 /***********************************/ 9122 /* MC_CMD_FILTER_OP 9123 * Multiplexed MCDI call for filter operations 9124 */ 9125 #define MC_CMD_FILTER_OP 0x8a 9126 #undef MC_CMD_0x8a_PRIVILEGE_CTG 9127 9128 #define MC_CMD_0x8a_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9129 9130 /* MC_CMD_FILTER_OP_IN msgrequest */ 9131 #define MC_CMD_FILTER_OP_IN_LEN 108 9132 /* identifies the type of operation requested */ 9133 #define MC_CMD_FILTER_OP_IN_OP_OFST 0 9134 /* enum: single-recipient filter insert */ 9135 #define MC_CMD_FILTER_OP_IN_OP_INSERT 0x0 9136 /* enum: single-recipient filter remove */ 9137 #define MC_CMD_FILTER_OP_IN_OP_REMOVE 0x1 9138 /* enum: multi-recipient filter subscribe */ 9139 #define MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE 0x2 9140 /* enum: multi-recipient filter unsubscribe */ 9141 #define MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE 0x3 9142 /* enum: replace one recipient with another (warning - the filter handle may 9143 * change) 9144 */ 9145 #define MC_CMD_FILTER_OP_IN_OP_REPLACE 0x4 9146 /* filter handle (for remove / unsubscribe operations) */ 9147 #define MC_CMD_FILTER_OP_IN_HANDLE_OFST 4 9148 #define MC_CMD_FILTER_OP_IN_HANDLE_LEN 8 9149 #define MC_CMD_FILTER_OP_IN_HANDLE_LO_OFST 4 9150 #define MC_CMD_FILTER_OP_IN_HANDLE_HI_OFST 8 9151 /* The port ID associated with the v-adaptor which should contain this filter. 9152 */ 9153 #define MC_CMD_FILTER_OP_IN_PORT_ID_OFST 12 9154 /* fields to include in match criteria */ 9155 #define MC_CMD_FILTER_OP_IN_MATCH_FIELDS_OFST 16 9156 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_LBN 0 9157 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_WIDTH 1 9158 #define MC_CMD_FILTER_OP_IN_MATCH_DST_IP_LBN 1 9159 #define MC_CMD_FILTER_OP_IN_MATCH_DST_IP_WIDTH 1 9160 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_LBN 2 9161 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_WIDTH 1 9162 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_LBN 3 9163 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_WIDTH 1 9164 #define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_LBN 4 9165 #define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_WIDTH 1 9166 #define MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_LBN 5 9167 #define MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_WIDTH 1 9168 #define MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_LBN 6 9169 #define MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_WIDTH 1 9170 #define MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_LBN 7 9171 #define MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_WIDTH 1 9172 #define MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_LBN 8 9173 #define MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_WIDTH 1 9174 #define MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_LBN 9 9175 #define MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_WIDTH 1 9176 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_LBN 10 9177 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_WIDTH 1 9178 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_LBN 11 9179 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_WIDTH 1 9180 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN 30 9181 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1 9182 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN 31 9183 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1 9184 /* receive destination */ 9185 #define MC_CMD_FILTER_OP_IN_RX_DEST_OFST 20 9186 /* enum: drop packets */ 9187 #define MC_CMD_FILTER_OP_IN_RX_DEST_DROP 0x0 9188 /* enum: receive to host */ 9189 #define MC_CMD_FILTER_OP_IN_RX_DEST_HOST 0x1 9190 /* enum: receive to MC */ 9191 #define MC_CMD_FILTER_OP_IN_RX_DEST_MC 0x2 9192 /* enum: loop back to TXDP 0 */ 9193 #define MC_CMD_FILTER_OP_IN_RX_DEST_TX0 0x3 9194 /* enum: loop back to TXDP 1 */ 9195 #define MC_CMD_FILTER_OP_IN_RX_DEST_TX1 0x4 9196 /* receive queue handle (for multiple queue modes, this is the base queue) */ 9197 #define MC_CMD_FILTER_OP_IN_RX_QUEUE_OFST 24 9198 /* receive mode */ 9199 #define MC_CMD_FILTER_OP_IN_RX_MODE_OFST 28 9200 /* enum: receive to just the specified queue */ 9201 #define MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE 0x0 9202 /* enum: receive to multiple queues using RSS context */ 9203 #define MC_CMD_FILTER_OP_IN_RX_MODE_RSS 0x1 9204 /* enum: receive to multiple queues using .1p mapping */ 9205 #define MC_CMD_FILTER_OP_IN_RX_MODE_DOT1P_MAPPING 0x2 9206 /* enum: install a filter entry that will never match; for test purposes only 9207 */ 9208 #define MC_CMD_FILTER_OP_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000 9209 /* RSS context (for RX_MODE_RSS) or .1p mapping handle (for 9210 * RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or 9211 * MC_CMD_DOT1P_MAPPING_ALLOC. 9212 */ 9213 #define MC_CMD_FILTER_OP_IN_RX_CONTEXT_OFST 32 9214 /* transmit domain (reserved; set to 0) */ 9215 #define MC_CMD_FILTER_OP_IN_TX_DOMAIN_OFST 36 9216 /* transmit destination (either set the MAC and/or PM bits for explicit 9217 * control, or set this field to TX_DEST_DEFAULT for sensible default 9218 * behaviour) 9219 */ 9220 #define MC_CMD_FILTER_OP_IN_TX_DEST_OFST 40 9221 /* enum: request default behaviour (based on filter type) */ 9222 #define MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT 0xffffffff 9223 #define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_LBN 0 9224 #define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_WIDTH 1 9225 #define MC_CMD_FILTER_OP_IN_TX_DEST_PM_LBN 1 9226 #define MC_CMD_FILTER_OP_IN_TX_DEST_PM_WIDTH 1 9227 /* source MAC address to match (as bytes in network order) */ 9228 #define MC_CMD_FILTER_OP_IN_SRC_MAC_OFST 44 9229 #define MC_CMD_FILTER_OP_IN_SRC_MAC_LEN 6 9230 /* source port to match (as bytes in network order) */ 9231 #define MC_CMD_FILTER_OP_IN_SRC_PORT_OFST 50 9232 #define MC_CMD_FILTER_OP_IN_SRC_PORT_LEN 2 9233 /* destination MAC address to match (as bytes in network order) */ 9234 #define MC_CMD_FILTER_OP_IN_DST_MAC_OFST 52 9235 #define MC_CMD_FILTER_OP_IN_DST_MAC_LEN 6 9236 /* destination port to match (as bytes in network order) */ 9237 #define MC_CMD_FILTER_OP_IN_DST_PORT_OFST 58 9238 #define MC_CMD_FILTER_OP_IN_DST_PORT_LEN 2 9239 /* Ethernet type to match (as bytes in network order) */ 9240 #define MC_CMD_FILTER_OP_IN_ETHER_TYPE_OFST 60 9241 #define MC_CMD_FILTER_OP_IN_ETHER_TYPE_LEN 2 9242 /* Inner VLAN tag to match (as bytes in network order) */ 9243 #define MC_CMD_FILTER_OP_IN_INNER_VLAN_OFST 62 9244 #define MC_CMD_FILTER_OP_IN_INNER_VLAN_LEN 2 9245 /* Outer VLAN tag to match (as bytes in network order) */ 9246 #define MC_CMD_FILTER_OP_IN_OUTER_VLAN_OFST 64 9247 #define MC_CMD_FILTER_OP_IN_OUTER_VLAN_LEN 2 9248 /* IP protocol to match (in low byte; set high byte to 0) */ 9249 #define MC_CMD_FILTER_OP_IN_IP_PROTO_OFST 66 9250 #define MC_CMD_FILTER_OP_IN_IP_PROTO_LEN 2 9251 /* Firmware defined register 0 to match (reserved; set to 0) */ 9252 #define MC_CMD_FILTER_OP_IN_FWDEF0_OFST 68 9253 /* Firmware defined register 1 to match (reserved; set to 0) */ 9254 #define MC_CMD_FILTER_OP_IN_FWDEF1_OFST 72 9255 /* source IP address to match (as bytes in network order; set last 12 bytes to 9256 * 0 for IPv4 address) 9257 */ 9258 #define MC_CMD_FILTER_OP_IN_SRC_IP_OFST 76 9259 #define MC_CMD_FILTER_OP_IN_SRC_IP_LEN 16 9260 /* destination IP address to match (as bytes in network order; set last 12 9261 * bytes to 0 for IPv4 address) 9262 */ 9263 #define MC_CMD_FILTER_OP_IN_DST_IP_OFST 92 9264 #define MC_CMD_FILTER_OP_IN_DST_IP_LEN 16 9265 9266 /* MC_CMD_FILTER_OP_EXT_IN msgrequest: Extension to MC_CMD_FILTER_OP_IN to 9267 * include handling of VXLAN/NVGRE encapsulated frame filtering (which is 9268 * supported on Medford only). 9269 */ 9270 #define MC_CMD_FILTER_OP_EXT_IN_LEN 172 9271 /* identifies the type of operation requested */ 9272 #define MC_CMD_FILTER_OP_EXT_IN_OP_OFST 0 9273 /* Enum values, see field(s): */ 9274 /* MC_CMD_FILTER_OP_IN/OP */ 9275 /* filter handle (for remove / unsubscribe operations) */ 9276 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_OFST 4 9277 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LEN 8 9278 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LO_OFST 4 9279 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_HI_OFST 8 9280 /* The port ID associated with the v-adaptor which should contain this filter. 9281 */ 9282 #define MC_CMD_FILTER_OP_EXT_IN_PORT_ID_OFST 12 9283 /* fields to include in match criteria */ 9284 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_FIELDS_OFST 16 9285 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_LBN 0 9286 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_WIDTH 1 9287 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_IP_LBN 1 9288 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_IP_WIDTH 1 9289 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_MAC_LBN 2 9290 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_MAC_WIDTH 1 9291 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_PORT_LBN 3 9292 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_PORT_WIDTH 1 9293 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_LBN 4 9294 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_WIDTH 1 9295 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_PORT_LBN 5 9296 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_PORT_WIDTH 1 9297 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_LBN 6 9298 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_WIDTH 1 9299 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_INNER_VLAN_LBN 7 9300 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_INNER_VLAN_WIDTH 1 9301 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_OUTER_VLAN_LBN 8 9302 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_OUTER_VLAN_WIDTH 1 9303 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_LBN 9 9304 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_WIDTH 1 9305 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_FWDEF0_LBN 10 9306 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_FWDEF0_WIDTH 1 9307 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_VNI_OR_VSID_LBN 11 9308 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_VNI_OR_VSID_WIDTH 1 9309 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_IP_LBN 12 9310 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_IP_WIDTH 1 9311 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_IP_LBN 13 9312 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_IP_WIDTH 1 9313 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_MAC_LBN 14 9314 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_MAC_WIDTH 1 9315 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_PORT_LBN 15 9316 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_PORT_WIDTH 1 9317 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_MAC_LBN 16 9318 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_MAC_WIDTH 1 9319 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_PORT_LBN 17 9320 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_PORT_WIDTH 1 9321 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ETHER_TYPE_LBN 18 9322 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ETHER_TYPE_WIDTH 1 9323 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_INNER_VLAN_LBN 19 9324 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_INNER_VLAN_WIDTH 1 9325 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_OUTER_VLAN_LBN 20 9326 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_OUTER_VLAN_WIDTH 1 9327 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_IP_PROTO_LBN 21 9328 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_IP_PROTO_WIDTH 1 9329 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF0_LBN 22 9330 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF0_WIDTH 1 9331 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF1_LBN 23 9332 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF1_WIDTH 1 9333 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_LBN 24 9334 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_WIDTH 1 9335 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_LBN 25 9336 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_WIDTH 1 9337 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_LBN 30 9338 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1 9339 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_LBN 31 9340 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1 9341 /* receive destination */ 9342 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_OFST 20 9343 /* enum: drop packets */ 9344 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_DROP 0x0 9345 /* enum: receive to host */ 9346 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_HOST 0x1 9347 /* enum: receive to MC */ 9348 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_MC 0x2 9349 /* enum: loop back to TXDP 0 */ 9350 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_TX0 0x3 9351 /* enum: loop back to TXDP 1 */ 9352 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_TX1 0x4 9353 /* receive queue handle (for multiple queue modes, this is the base queue) */ 9354 #define MC_CMD_FILTER_OP_EXT_IN_RX_QUEUE_OFST 24 9355 /* receive mode */ 9356 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_OFST 28 9357 /* enum: receive to just the specified queue */ 9358 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_SIMPLE 0x0 9359 /* enum: receive to multiple queues using RSS context */ 9360 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_RSS 0x1 9361 /* enum: receive to multiple queues using .1p mapping */ 9362 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_DOT1P_MAPPING 0x2 9363 /* enum: install a filter entry that will never match; for test purposes only 9364 */ 9365 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000 9366 /* RSS context (for RX_MODE_RSS) or .1p mapping handle (for 9367 * RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or 9368 * MC_CMD_DOT1P_MAPPING_ALLOC. 9369 */ 9370 #define MC_CMD_FILTER_OP_EXT_IN_RX_CONTEXT_OFST 32 9371 /* transmit domain (reserved; set to 0) */ 9372 #define MC_CMD_FILTER_OP_EXT_IN_TX_DOMAIN_OFST 36 9373 /* transmit destination (either set the MAC and/or PM bits for explicit 9374 * control, or set this field to TX_DEST_DEFAULT for sensible default 9375 * behaviour) 9376 */ 9377 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_OFST 40 9378 /* enum: request default behaviour (based on filter type) */ 9379 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_DEFAULT 0xffffffff 9380 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_LBN 0 9381 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_WIDTH 1 9382 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_PM_LBN 1 9383 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_PM_WIDTH 1 9384 /* source MAC address to match (as bytes in network order) */ 9385 #define MC_CMD_FILTER_OP_EXT_IN_SRC_MAC_OFST 44 9386 #define MC_CMD_FILTER_OP_EXT_IN_SRC_MAC_LEN 6 9387 /* source port to match (as bytes in network order) */ 9388 #define MC_CMD_FILTER_OP_EXT_IN_SRC_PORT_OFST 50 9389 #define MC_CMD_FILTER_OP_EXT_IN_SRC_PORT_LEN 2 9390 /* destination MAC address to match (as bytes in network order) */ 9391 #define MC_CMD_FILTER_OP_EXT_IN_DST_MAC_OFST 52 9392 #define MC_CMD_FILTER_OP_EXT_IN_DST_MAC_LEN 6 9393 /* destination port to match (as bytes in network order) */ 9394 #define MC_CMD_FILTER_OP_EXT_IN_DST_PORT_OFST 58 9395 #define MC_CMD_FILTER_OP_EXT_IN_DST_PORT_LEN 2 9396 /* Ethernet type to match (as bytes in network order) */ 9397 #define MC_CMD_FILTER_OP_EXT_IN_ETHER_TYPE_OFST 60 9398 #define MC_CMD_FILTER_OP_EXT_IN_ETHER_TYPE_LEN 2 9399 /* Inner VLAN tag to match (as bytes in network order) */ 9400 #define MC_CMD_FILTER_OP_EXT_IN_INNER_VLAN_OFST 62 9401 #define MC_CMD_FILTER_OP_EXT_IN_INNER_VLAN_LEN 2 9402 /* Outer VLAN tag to match (as bytes in network order) */ 9403 #define MC_CMD_FILTER_OP_EXT_IN_OUTER_VLAN_OFST 64 9404 #define MC_CMD_FILTER_OP_EXT_IN_OUTER_VLAN_LEN 2 9405 /* IP protocol to match (in low byte; set high byte to 0) */ 9406 #define MC_CMD_FILTER_OP_EXT_IN_IP_PROTO_OFST 66 9407 #define MC_CMD_FILTER_OP_EXT_IN_IP_PROTO_LEN 2 9408 /* Firmware defined register 0 to match (reserved; set to 0) */ 9409 #define MC_CMD_FILTER_OP_EXT_IN_FWDEF0_OFST 68 9410 /* VNI (for VXLAN/Geneve, when IP protocol is UDP) or VSID (for NVGRE, when IP 9411 * protocol is GRE) to match (as bytes in network order; set last byte to 0 for 9412 * VXLAN/NVGRE, or 1 for Geneve) 9413 */ 9414 #define MC_CMD_FILTER_OP_EXT_IN_VNI_OR_VSID_OFST 72 9415 #define MC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_LBN 0 9416 #define MC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_WIDTH 24 9417 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_LBN 24 9418 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_WIDTH 8 9419 /* enum: Match VXLAN traffic with this VNI */ 9420 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_VXLAN 0x0 9421 /* enum: Match Geneve traffic with this VNI */ 9422 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_GENEVE 0x1 9423 /* enum: Reserved for experimental development use */ 9424 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_EXPERIMENTAL 0xfe 9425 #define MC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_LBN 0 9426 #define MC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_WIDTH 24 9427 #define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_LBN 24 9428 #define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_WIDTH 8 9429 /* enum: Match NVGRE traffic with this VSID */ 9430 #define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_NVGRE 0x0 9431 /* source IP address to match (as bytes in network order; set last 12 bytes to 9432 * 0 for IPv4 address) 9433 */ 9434 #define MC_CMD_FILTER_OP_EXT_IN_SRC_IP_OFST 76 9435 #define MC_CMD_FILTER_OP_EXT_IN_SRC_IP_LEN 16 9436 /* destination IP address to match (as bytes in network order; set last 12 9437 * bytes to 0 for IPv4 address) 9438 */ 9439 #define MC_CMD_FILTER_OP_EXT_IN_DST_IP_OFST 92 9440 #define MC_CMD_FILTER_OP_EXT_IN_DST_IP_LEN 16 9441 /* VXLAN/NVGRE inner frame source MAC address to match (as bytes in network 9442 * order) 9443 */ 9444 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_MAC_OFST 108 9445 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_MAC_LEN 6 9446 /* VXLAN/NVGRE inner frame source port to match (as bytes in network order) */ 9447 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_PORT_OFST 114 9448 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_PORT_LEN 2 9449 /* VXLAN/NVGRE inner frame destination MAC address to match (as bytes in 9450 * network order) 9451 */ 9452 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_MAC_OFST 116 9453 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_MAC_LEN 6 9454 /* VXLAN/NVGRE inner frame destination port to match (as bytes in network 9455 * order) 9456 */ 9457 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_PORT_OFST 122 9458 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_PORT_LEN 2 9459 /* VXLAN/NVGRE inner frame Ethernet type to match (as bytes in network order) 9460 */ 9461 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_ETHER_TYPE_OFST 124 9462 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_ETHER_TYPE_LEN 2 9463 /* VXLAN/NVGRE inner frame Inner VLAN tag to match (as bytes in network order) 9464 */ 9465 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_INNER_VLAN_OFST 126 9466 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_INNER_VLAN_LEN 2 9467 /* VXLAN/NVGRE inner frame Outer VLAN tag to match (as bytes in network order) 9468 */ 9469 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_OUTER_VLAN_OFST 128 9470 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_OUTER_VLAN_LEN 2 9471 /* VXLAN/NVGRE inner frame IP protocol to match (in low byte; set high byte to 9472 * 0) 9473 */ 9474 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_IP_PROTO_OFST 130 9475 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_IP_PROTO_LEN 2 9476 /* VXLAN/NVGRE inner frame Firmware defined register 0 to match (reserved; set 9477 * to 0) 9478 */ 9479 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF0_OFST 132 9480 /* VXLAN/NVGRE inner frame Firmware defined register 1 to match (reserved; set 9481 * to 0) 9482 */ 9483 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF1_OFST 136 9484 /* VXLAN/NVGRE inner frame source IP address to match (as bytes in network 9485 * order; set last 12 bytes to 0 for IPv4 address) 9486 */ 9487 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_IP_OFST 140 9488 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_IP_LEN 16 9489 /* VXLAN/NVGRE inner frame destination IP address to match (as bytes in network 9490 * order; set last 12 bytes to 0 for IPv4 address) 9491 */ 9492 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_IP_OFST 156 9493 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_IP_LEN 16 9494 9495 /* MC_CMD_FILTER_OP_OUT msgresponse */ 9496 #define MC_CMD_FILTER_OP_OUT_LEN 12 9497 /* identifies the type of operation requested */ 9498 #define MC_CMD_FILTER_OP_OUT_OP_OFST 0 9499 /* Enum values, see field(s): */ 9500 /* MC_CMD_FILTER_OP_IN/OP */ 9501 /* Returned filter handle (for insert / subscribe operations). Note that these 9502 * handles should be considered opaque to the host, although a value of 9503 * 0xFFFFFFFF_FFFFFFFF is guaranteed never to be a valid handle. 9504 */ 9505 #define MC_CMD_FILTER_OP_OUT_HANDLE_OFST 4 9506 #define MC_CMD_FILTER_OP_OUT_HANDLE_LEN 8 9507 #define MC_CMD_FILTER_OP_OUT_HANDLE_LO_OFST 4 9508 #define MC_CMD_FILTER_OP_OUT_HANDLE_HI_OFST 8 9509 /* enum: guaranteed invalid filter handle (low 32 bits) */ 9510 #define MC_CMD_FILTER_OP_OUT_HANDLE_LO_INVALID 0xffffffff 9511 /* enum: guaranteed invalid filter handle (high 32 bits) */ 9512 #define MC_CMD_FILTER_OP_OUT_HANDLE_HI_INVALID 0xffffffff 9513 9514 /* MC_CMD_FILTER_OP_EXT_OUT msgresponse */ 9515 #define MC_CMD_FILTER_OP_EXT_OUT_LEN 12 9516 /* identifies the type of operation requested */ 9517 #define MC_CMD_FILTER_OP_EXT_OUT_OP_OFST 0 9518 /* Enum values, see field(s): */ 9519 /* MC_CMD_FILTER_OP_EXT_IN/OP */ 9520 /* Returned filter handle (for insert / subscribe operations). Note that these 9521 * handles should be considered opaque to the host, although a value of 9522 * 0xFFFFFFFF_FFFFFFFF is guaranteed never to be a valid handle. 9523 */ 9524 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_OFST 4 9525 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LEN 8 9526 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LO_OFST 4 9527 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_HI_OFST 8 9528 /* Enum values, see field(s): */ 9529 /* MC_CMD_FILTER_OP_OUT/HANDLE */ 9530 9531 9532 /***********************************/ 9533 /* MC_CMD_GET_PARSER_DISP_INFO 9534 * Get information related to the parser-dispatcher subsystem 9535 */ 9536 #define MC_CMD_GET_PARSER_DISP_INFO 0xe4 9537 #undef MC_CMD_0xe4_PRIVILEGE_CTG 9538 9539 #define MC_CMD_0xe4_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9540 9541 /* MC_CMD_GET_PARSER_DISP_INFO_IN msgrequest */ 9542 #define MC_CMD_GET_PARSER_DISP_INFO_IN_LEN 4 9543 /* identifies the type of operation requested */ 9544 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_OFST 0 9545 /* enum: read the list of supported RX filter matches */ 9546 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES 0x1 9547 /* enum: read flags indicating restrictions on filter insertion for the calling 9548 * client 9549 */ 9550 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_RESTRICTIONS 0x2 9551 /* enum: read properties relating to security rules (Medford-only; for use by 9552 * SolarSecure apps, not directly by drivers. See SF-114946-SW.) 9553 */ 9554 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SECURITY_RULE_INFO 0x3 9555 /* enum: read the list of supported RX filter matches for VXLAN/NVGRE 9556 * encapsulated frames, which follow a different match sequence to normal 9557 * frames (Medford only) 9558 */ 9559 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_ENCAP_RX_MATCHES 0x4 9560 9561 /* MC_CMD_GET_PARSER_DISP_INFO_OUT msgresponse */ 9562 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMIN 8 9563 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX 252 9564 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_LEN(num) (8+4*(num)) 9565 /* identifies the type of operation requested */ 9566 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_OP_OFST 0 9567 /* Enum values, see field(s): */ 9568 /* MC_CMD_GET_PARSER_DISP_INFO_IN/OP */ 9569 /* number of supported match types */ 9570 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_NUM_SUPPORTED_MATCHES_OFST 4 9571 /* array of supported match types (valid MATCH_FIELDS values for 9572 * MC_CMD_FILTER_OP) sorted in decreasing priority order 9573 */ 9574 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_OFST 8 9575 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_LEN 4 9576 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MINNUM 0 9577 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM 61 9578 9579 /* MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT msgresponse */ 9580 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_LEN 8 9581 /* identifies the type of operation requested */ 9582 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_OP_OFST 0 9583 /* Enum values, see field(s): */ 9584 /* MC_CMD_GET_PARSER_DISP_INFO_IN/OP */ 9585 /* bitfield of filter insertion restrictions */ 9586 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_RESTRICTION_FLAGS_OFST 4 9587 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_LBN 0 9588 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_WIDTH 1 9589 9590 /* MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT msgresponse: 9591 * GET_PARSER_DISP_INFO response format for OP_GET_SECURITY_RULE_INFO. 9592 * (Medford-only; for use by SolarSecure apps, not directly by drivers. See 9593 * SF-114946-SW.) NOTE - this message definition is provisional. It has not yet 9594 * been used in any released code and may change during development. This note 9595 * will be removed once it is regarded as stable. 9596 */ 9597 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_LEN 36 9598 /* identifies the type of operation requested */ 9599 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_OP_OFST 0 9600 /* Enum values, see field(s): */ 9601 /* MC_CMD_GET_PARSER_DISP_INFO_IN/OP */ 9602 /* a version number representing the set of rule lookups that are implemented 9603 * by the currently running firmware 9604 */ 9605 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_RULES_VERSION_OFST 4 9606 /* enum: implements lookup sequences described in SF-114946-SW draft C */ 9607 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_RULES_VERSION_SF_114946_SW_C 0x0 9608 /* the number of nodes in the subnet map */ 9609 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_MAP_NUM_NODES_OFST 8 9610 /* the number of entries in one subnet map node */ 9611 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_MAP_NUM_ENTRIES_PER_NODE_OFST 12 9612 /* minimum valid value for a subnet ID in a subnet map leaf */ 9613 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_ID_MIN_OFST 16 9614 /* maximum valid value for a subnet ID in a subnet map leaf */ 9615 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_ID_MAX_OFST 20 9616 /* the number of entries in the local and remote port range maps */ 9617 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_PORTRANGE_TREE_NUM_ENTRIES_OFST 24 9618 /* minimum valid value for a portrange ID in a port range map leaf */ 9619 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_PORTRANGE_ID_MIN_OFST 28 9620 /* maximum valid value for a portrange ID in a port range map leaf */ 9621 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_PORTRANGE_ID_MAX_OFST 32 9622 9623 9624 /***********************************/ 9625 /* MC_CMD_PARSER_DISP_RW 9626 * Direct read/write of parser-dispatcher state (DICPUs and LUE) for debugging. 9627 * Please note that this interface is only of use to debug tools which have 9628 * knowledge of firmware and hardware data structures; nothing here is intended 9629 * for use by normal driver code. 9630 */ 9631 #define MC_CMD_PARSER_DISP_RW 0xe5 9632 #undef MC_CMD_0xe5_PRIVILEGE_CTG 9633 9634 #define MC_CMD_0xe5_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9635 9636 /* MC_CMD_PARSER_DISP_RW_IN msgrequest */ 9637 #define MC_CMD_PARSER_DISP_RW_IN_LEN 32 9638 /* identifies the target of the operation */ 9639 #define MC_CMD_PARSER_DISP_RW_IN_TARGET_OFST 0 9640 /* enum: RX dispatcher CPU */ 9641 #define MC_CMD_PARSER_DISP_RW_IN_RX_DICPU 0x0 9642 /* enum: TX dispatcher CPU */ 9643 #define MC_CMD_PARSER_DISP_RW_IN_TX_DICPU 0x1 9644 /* enum: Lookup engine (with original metadata format). Deprecated; used only 9645 * by cmdclient as a fallback for very old Huntington firmware, and not 9646 * supported in firmware beyond v6.4.0.1005. Use LUE_VERSIONED_METADATA 9647 * instead. 9648 */ 9649 #define MC_CMD_PARSER_DISP_RW_IN_LUE 0x2 9650 /* enum: Lookup engine (with requested metadata format) */ 9651 #define MC_CMD_PARSER_DISP_RW_IN_LUE_VERSIONED_METADATA 0x3 9652 /* enum: RX0 dispatcher CPU (alias for RX_DICPU; Medford has 2 RX DICPUs) */ 9653 #define MC_CMD_PARSER_DISP_RW_IN_RX0_DICPU 0x0 9654 /* enum: RX1 dispatcher CPU (only valid for Medford) */ 9655 #define MC_CMD_PARSER_DISP_RW_IN_RX1_DICPU 0x4 9656 /* enum: Miscellaneous other state (only valid for Medford) */ 9657 #define MC_CMD_PARSER_DISP_RW_IN_MISC_STATE 0x5 9658 /* identifies the type of operation requested */ 9659 #define MC_CMD_PARSER_DISP_RW_IN_OP_OFST 4 9660 /* enum: read a word of DICPU DMEM or a LUE entry */ 9661 #define MC_CMD_PARSER_DISP_RW_IN_READ 0x0 9662 /* enum: write a word of DICPU DMEM or a LUE entry */ 9663 #define MC_CMD_PARSER_DISP_RW_IN_WRITE 0x1 9664 /* enum: read-modify-write a word of DICPU DMEM (not valid for LUE) */ 9665 #define MC_CMD_PARSER_DISP_RW_IN_RMW 0x2 9666 /* data memory address (DICPU targets) or LUE index (LUE targets) */ 9667 #define MC_CMD_PARSER_DISP_RW_IN_ADDRESS_OFST 8 9668 /* selector (for MISC_STATE target) */ 9669 #define MC_CMD_PARSER_DISP_RW_IN_SELECTOR_OFST 8 9670 /* enum: Port to datapath mapping */ 9671 #define MC_CMD_PARSER_DISP_RW_IN_PORT_DP_MAPPING 0x1 9672 /* value to write (for DMEM writes) */ 9673 #define MC_CMD_PARSER_DISP_RW_IN_DMEM_WRITE_VALUE_OFST 12 9674 /* XOR value (for DMEM read-modify-writes: new = (old & mask) ^ value) */ 9675 #define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_XOR_VALUE_OFST 12 9676 /* AND mask (for DMEM read-modify-writes: new = (old & mask) ^ value) */ 9677 #define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_AND_MASK_OFST 16 9678 /* metadata format (for LUE reads using LUE_VERSIONED_METADATA) */ 9679 #define MC_CMD_PARSER_DISP_RW_IN_LUE_READ_METADATA_VERSION_OFST 12 9680 /* value to write (for LUE writes) */ 9681 #define MC_CMD_PARSER_DISP_RW_IN_LUE_WRITE_VALUE_OFST 12 9682 #define MC_CMD_PARSER_DISP_RW_IN_LUE_WRITE_VALUE_LEN 20 9683 9684 /* MC_CMD_PARSER_DISP_RW_OUT msgresponse */ 9685 #define MC_CMD_PARSER_DISP_RW_OUT_LEN 52 9686 /* value read (for DMEM reads) */ 9687 #define MC_CMD_PARSER_DISP_RW_OUT_DMEM_READ_VALUE_OFST 0 9688 /* value read (for LUE reads) */ 9689 #define MC_CMD_PARSER_DISP_RW_OUT_LUE_READ_VALUE_OFST 0 9690 #define MC_CMD_PARSER_DISP_RW_OUT_LUE_READ_VALUE_LEN 20 9691 /* up to 8 32-bit words of additional soft state from the LUE manager (the 9692 * exact content is firmware-dependent and intended only for debug use) 9693 */ 9694 #define MC_CMD_PARSER_DISP_RW_OUT_LUE_MGR_STATE_OFST 20 9695 #define MC_CMD_PARSER_DISP_RW_OUT_LUE_MGR_STATE_LEN 32 9696 /* datapath(s) used for each port (for MISC_STATE PORT_DP_MAPPING selector) */ 9697 #define MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_OFST 0 9698 #define MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_LEN 4 9699 #define MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_NUM 4 9700 #define MC_CMD_PARSER_DISP_RW_OUT_DP0 0x1 /* enum */ 9701 #define MC_CMD_PARSER_DISP_RW_OUT_DP1 0x2 /* enum */ 9702 9703 9704 /***********************************/ 9705 /* MC_CMD_GET_PF_COUNT 9706 * Get number of PFs on the device. 9707 */ 9708 #define MC_CMD_GET_PF_COUNT 0xb6 9709 #undef MC_CMD_0xb6_PRIVILEGE_CTG 9710 9711 #define MC_CMD_0xb6_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9712 9713 /* MC_CMD_GET_PF_COUNT_IN msgrequest */ 9714 #define MC_CMD_GET_PF_COUNT_IN_LEN 0 9715 9716 /* MC_CMD_GET_PF_COUNT_OUT msgresponse */ 9717 #define MC_CMD_GET_PF_COUNT_OUT_LEN 1 9718 /* Identifies the number of PFs on the device. */ 9719 #define MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_OFST 0 9720 #define MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_LEN 1 9721 9722 9723 /***********************************/ 9724 /* MC_CMD_SET_PF_COUNT 9725 * Set number of PFs on the device. 9726 */ 9727 #define MC_CMD_SET_PF_COUNT 0xb7 9728 9729 /* MC_CMD_SET_PF_COUNT_IN msgrequest */ 9730 #define MC_CMD_SET_PF_COUNT_IN_LEN 4 9731 /* New number of PFs on the device. */ 9732 #define MC_CMD_SET_PF_COUNT_IN_PF_COUNT_OFST 0 9733 9734 /* MC_CMD_SET_PF_COUNT_OUT msgresponse */ 9735 #define MC_CMD_SET_PF_COUNT_OUT_LEN 0 9736 9737 9738 /***********************************/ 9739 /* MC_CMD_GET_PORT_ASSIGNMENT 9740 * Get port assignment for current PCI function. 9741 */ 9742 #define MC_CMD_GET_PORT_ASSIGNMENT 0xb8 9743 #undef MC_CMD_0xb8_PRIVILEGE_CTG 9744 9745 #define MC_CMD_0xb8_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9746 9747 /* MC_CMD_GET_PORT_ASSIGNMENT_IN msgrequest */ 9748 #define MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN 0 9749 9750 /* MC_CMD_GET_PORT_ASSIGNMENT_OUT msgresponse */ 9751 #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN 4 9752 /* Identifies the port assignment for this function. */ 9753 #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_PORT_OFST 0 9754 9755 9756 /***********************************/ 9757 /* MC_CMD_SET_PORT_ASSIGNMENT 9758 * Set port assignment for current PCI function. 9759 */ 9760 #define MC_CMD_SET_PORT_ASSIGNMENT 0xb9 9761 #undef MC_CMD_0xb9_PRIVILEGE_CTG 9762 9763 #define MC_CMD_0xb9_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9764 9765 /* MC_CMD_SET_PORT_ASSIGNMENT_IN msgrequest */ 9766 #define MC_CMD_SET_PORT_ASSIGNMENT_IN_LEN 4 9767 /* Identifies the port assignment for this function. */ 9768 #define MC_CMD_SET_PORT_ASSIGNMENT_IN_PORT_OFST 0 9769 9770 /* MC_CMD_SET_PORT_ASSIGNMENT_OUT msgresponse */ 9771 #define MC_CMD_SET_PORT_ASSIGNMENT_OUT_LEN 0 9772 9773 9774 /***********************************/ 9775 /* MC_CMD_ALLOC_VIS 9776 * Allocate VIs for current PCI function. 9777 */ 9778 #define MC_CMD_ALLOC_VIS 0x8b 9779 #undef MC_CMD_0x8b_PRIVILEGE_CTG 9780 9781 #define MC_CMD_0x8b_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9782 9783 /* MC_CMD_ALLOC_VIS_IN msgrequest */ 9784 #define MC_CMD_ALLOC_VIS_IN_LEN 8 9785 /* The minimum number of VIs that is acceptable */ 9786 #define MC_CMD_ALLOC_VIS_IN_MIN_VI_COUNT_OFST 0 9787 /* The maximum number of VIs that would be useful */ 9788 #define MC_CMD_ALLOC_VIS_IN_MAX_VI_COUNT_OFST 4 9789 9790 /* MC_CMD_ALLOC_VIS_OUT msgresponse: Huntington-compatible VI_ALLOC request. 9791 * Use extended version in new code. 9792 */ 9793 #define MC_CMD_ALLOC_VIS_OUT_LEN 8 9794 /* The number of VIs allocated on this function */ 9795 #define MC_CMD_ALLOC_VIS_OUT_VI_COUNT_OFST 0 9796 /* The base absolute VI number allocated to this function. Required to 9797 * correctly interpret wakeup events. 9798 */ 9799 #define MC_CMD_ALLOC_VIS_OUT_VI_BASE_OFST 4 9800 9801 /* MC_CMD_ALLOC_VIS_EXT_OUT msgresponse */ 9802 #define MC_CMD_ALLOC_VIS_EXT_OUT_LEN 12 9803 /* The number of VIs allocated on this function */ 9804 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_COUNT_OFST 0 9805 /* The base absolute VI number allocated to this function. Required to 9806 * correctly interpret wakeup events. 9807 */ 9808 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_BASE_OFST 4 9809 /* Function's port vi_shift value (always 0 on Huntington) */ 9810 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_SHIFT_OFST 8 9811 9812 9813 /***********************************/ 9814 /* MC_CMD_FREE_VIS 9815 * Free VIs for current PCI function. Any linked PIO buffers will be unlinked, 9816 * but not freed. 9817 */ 9818 #define MC_CMD_FREE_VIS 0x8c 9819 #undef MC_CMD_0x8c_PRIVILEGE_CTG 9820 9821 #define MC_CMD_0x8c_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9822 9823 /* MC_CMD_FREE_VIS_IN msgrequest */ 9824 #define MC_CMD_FREE_VIS_IN_LEN 0 9825 9826 /* MC_CMD_FREE_VIS_OUT msgresponse */ 9827 #define MC_CMD_FREE_VIS_OUT_LEN 0 9828 9829 9830 /***********************************/ 9831 /* MC_CMD_GET_SRIOV_CFG 9832 * Get SRIOV config for this PF. 9833 */ 9834 #define MC_CMD_GET_SRIOV_CFG 0xba 9835 #undef MC_CMD_0xba_PRIVILEGE_CTG 9836 9837 #define MC_CMD_0xba_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9838 9839 /* MC_CMD_GET_SRIOV_CFG_IN msgrequest */ 9840 #define MC_CMD_GET_SRIOV_CFG_IN_LEN 0 9841 9842 /* MC_CMD_GET_SRIOV_CFG_OUT msgresponse */ 9843 #define MC_CMD_GET_SRIOV_CFG_OUT_LEN 20 9844 /* Number of VFs currently enabled. */ 9845 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_CURRENT_OFST 0 9846 /* Max number of VFs before sriov stride and offset may need to be changed. */ 9847 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_MAX_OFST 4 9848 #define MC_CMD_GET_SRIOV_CFG_OUT_FLAGS_OFST 8 9849 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_LBN 0 9850 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_WIDTH 1 9851 /* RID offset of first VF from PF. */ 9852 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_OFFSET_OFST 12 9853 /* RID offset of each subsequent VF from the previous. */ 9854 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_STRIDE_OFST 16 9855 9856 9857 /***********************************/ 9858 /* MC_CMD_SET_SRIOV_CFG 9859 * Set SRIOV config for this PF. 9860 */ 9861 #define MC_CMD_SET_SRIOV_CFG 0xbb 9862 #undef MC_CMD_0xbb_PRIVILEGE_CTG 9863 9864 #define MC_CMD_0xbb_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9865 9866 /* MC_CMD_SET_SRIOV_CFG_IN msgrequest */ 9867 #define MC_CMD_SET_SRIOV_CFG_IN_LEN 20 9868 /* Number of VFs currently enabled. */ 9869 #define MC_CMD_SET_SRIOV_CFG_IN_VF_CURRENT_OFST 0 9870 /* Max number of VFs before sriov stride and offset may need to be changed. */ 9871 #define MC_CMD_SET_SRIOV_CFG_IN_VF_MAX_OFST 4 9872 #define MC_CMD_SET_SRIOV_CFG_IN_FLAGS_OFST 8 9873 #define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_LBN 0 9874 #define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_WIDTH 1 9875 /* RID offset of first VF from PF, or 0 for no change, or 9876 * MC_CMD_RESOURCE_INSTANCE_ANY to allow the system to allocate an offset. 9877 */ 9878 #define MC_CMD_SET_SRIOV_CFG_IN_VF_OFFSET_OFST 12 9879 /* RID offset of each subsequent VF from the previous, 0 for no change, or 9880 * MC_CMD_RESOURCE_INSTANCE_ANY to allow the system to allocate a stride. 9881 */ 9882 #define MC_CMD_SET_SRIOV_CFG_IN_VF_STRIDE_OFST 16 9883 9884 /* MC_CMD_SET_SRIOV_CFG_OUT msgresponse */ 9885 #define MC_CMD_SET_SRIOV_CFG_OUT_LEN 0 9886 9887 9888 /***********************************/ 9889 /* MC_CMD_GET_VI_ALLOC_INFO 9890 * Get information about number of VI's and base VI number allocated to this 9891 * function. 9892 */ 9893 #define MC_CMD_GET_VI_ALLOC_INFO 0x8d 9894 #undef MC_CMD_0x8d_PRIVILEGE_CTG 9895 9896 #define MC_CMD_0x8d_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9897 9898 /* MC_CMD_GET_VI_ALLOC_INFO_IN msgrequest */ 9899 #define MC_CMD_GET_VI_ALLOC_INFO_IN_LEN 0 9900 9901 /* MC_CMD_GET_VI_ALLOC_INFO_OUT msgresponse */ 9902 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_LEN 12 9903 /* The number of VIs allocated on this function */ 9904 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_COUNT_OFST 0 9905 /* The base absolute VI number allocated to this function. Required to 9906 * correctly interpret wakeup events. 9907 */ 9908 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_BASE_OFST 4 9909 /* Function's port vi_shift value (always 0 on Huntington) */ 9910 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_SHIFT_OFST 8 9911 9912 9913 /***********************************/ 9914 /* MC_CMD_DUMP_VI_STATE 9915 * For CmdClient use. Dump pertinent information on a specific absolute VI. 9916 */ 9917 #define MC_CMD_DUMP_VI_STATE 0x8e 9918 #undef MC_CMD_0x8e_PRIVILEGE_CTG 9919 9920 #define MC_CMD_0x8e_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9921 9922 /* MC_CMD_DUMP_VI_STATE_IN msgrequest */ 9923 #define MC_CMD_DUMP_VI_STATE_IN_LEN 4 9924 /* The VI number to query. */ 9925 #define MC_CMD_DUMP_VI_STATE_IN_VI_NUMBER_OFST 0 9926 9927 /* MC_CMD_DUMP_VI_STATE_OUT msgresponse */ 9928 #define MC_CMD_DUMP_VI_STATE_OUT_LEN 96 9929 /* The PF part of the function owning this VI. */ 9930 #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_OFST 0 9931 #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_LEN 2 9932 /* The VF part of the function owning this VI. */ 9933 #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_VF_OFST 2 9934 #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_VF_LEN 2 9935 /* Base of VIs allocated to this function. */ 9936 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_BASE_OFST 4 9937 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_BASE_LEN 2 9938 /* Count of VIs allocated to the owner function. */ 9939 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_COUNT_OFST 6 9940 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_COUNT_LEN 2 9941 /* Base interrupt vector allocated to this function. */ 9942 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_BASE_OFST 8 9943 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_BASE_LEN 2 9944 /* Number of interrupt vectors allocated to this function. */ 9945 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_COUNT_OFST 10 9946 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_COUNT_LEN 2 9947 /* Raw evq ptr table data. */ 9948 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_OFST 12 9949 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LEN 8 9950 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LO_OFST 12 9951 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_HI_OFST 16 9952 /* Raw evq timer table data. */ 9953 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_OFST 20 9954 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LEN 8 9955 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LO_OFST 20 9956 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_HI_OFST 24 9957 /* Combined metadata field. */ 9958 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_OFST 28 9959 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_LBN 0 9960 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_WIDTH 16 9961 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_LBN 16 9962 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_WIDTH 8 9963 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_LBN 24 9964 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_WIDTH 8 9965 /* TXDPCPU raw table data for queue. */ 9966 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_OFST 32 9967 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LEN 8 9968 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LO_OFST 32 9969 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_HI_OFST 36 9970 /* TXDPCPU raw table data for queue. */ 9971 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_OFST 40 9972 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LEN 8 9973 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LO_OFST 40 9974 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_HI_OFST 44 9975 /* TXDPCPU raw table data for queue. */ 9976 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_OFST 48 9977 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LEN 8 9978 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LO_OFST 48 9979 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_HI_OFST 52 9980 /* Combined metadata field. */ 9981 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_OFST 56 9982 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LEN 8 9983 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LO_OFST 56 9984 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_HI_OFST 60 9985 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_LBN 0 9986 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_WIDTH 16 9987 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_LBN 16 9988 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_WIDTH 8 9989 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_LBN 24 9990 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_WIDTH 8 9991 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_LBN 32 9992 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_WIDTH 8 9993 #define MC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_LBN 40 9994 #define MC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_WIDTH 24 9995 /* RXDPCPU raw table data for queue. */ 9996 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_OFST 64 9997 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LEN 8 9998 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LO_OFST 64 9999 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_HI_OFST 68 10000 /* RXDPCPU raw table data for queue. */ 10001 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_OFST 72 10002 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LEN 8 10003 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LO_OFST 72 10004 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_HI_OFST 76 10005 /* Reserved, currently 0. */ 10006 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_OFST 80 10007 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LEN 8 10008 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LO_OFST 80 10009 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_HI_OFST 84 10010 /* Combined metadata field. */ 10011 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_OFST 88 10012 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LEN 8 10013 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LO_OFST 88 10014 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_HI_OFST 92 10015 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_LBN 0 10016 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_WIDTH 16 10017 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_LBN 16 10018 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_WIDTH 8 10019 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_LBN 24 10020 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_WIDTH 8 10021 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_LBN 32 10022 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_WIDTH 8 10023 10024 10025 /***********************************/ 10026 /* MC_CMD_ALLOC_PIOBUF 10027 * Allocate a push I/O buffer for later use with a tx queue. 10028 */ 10029 #define MC_CMD_ALLOC_PIOBUF 0x8f 10030 #undef MC_CMD_0x8f_PRIVILEGE_CTG 10031 10032 #define MC_CMD_0x8f_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 10033 10034 /* MC_CMD_ALLOC_PIOBUF_IN msgrequest */ 10035 #define MC_CMD_ALLOC_PIOBUF_IN_LEN 0 10036 10037 /* MC_CMD_ALLOC_PIOBUF_OUT msgresponse */ 10038 #define MC_CMD_ALLOC_PIOBUF_OUT_LEN 4 10039 /* Handle for allocated push I/O buffer. */ 10040 #define MC_CMD_ALLOC_PIOBUF_OUT_PIOBUF_HANDLE_OFST 0 10041 10042 10043 /***********************************/ 10044 /* MC_CMD_FREE_PIOBUF 10045 * Free a push I/O buffer. 10046 */ 10047 #define MC_CMD_FREE_PIOBUF 0x90 10048 #undef MC_CMD_0x90_PRIVILEGE_CTG 10049 10050 #define MC_CMD_0x90_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 10051 10052 /* MC_CMD_FREE_PIOBUF_IN msgrequest */ 10053 #define MC_CMD_FREE_PIOBUF_IN_LEN 4 10054 /* Handle for allocated push I/O buffer. */ 10055 #define MC_CMD_FREE_PIOBUF_IN_PIOBUF_HANDLE_OFST 0 10056 10057 /* MC_CMD_FREE_PIOBUF_OUT msgresponse */ 10058 #define MC_CMD_FREE_PIOBUF_OUT_LEN 0 10059 10060 10061 /***********************************/ 10062 /* MC_CMD_GET_VI_TLP_PROCESSING 10063 * Get TLP steering and ordering information for a VI. 10064 */ 10065 #define MC_CMD_GET_VI_TLP_PROCESSING 0xb0 10066 #undef MC_CMD_0xb0_PRIVILEGE_CTG 10067 10068 #define MC_CMD_0xb0_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10069 10070 /* MC_CMD_GET_VI_TLP_PROCESSING_IN msgrequest */ 10071 #define MC_CMD_GET_VI_TLP_PROCESSING_IN_LEN 4 10072 /* VI number to get information for. */ 10073 #define MC_CMD_GET_VI_TLP_PROCESSING_IN_INSTANCE_OFST 0 10074 10075 /* MC_CMD_GET_VI_TLP_PROCESSING_OUT msgresponse */ 10076 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_LEN 4 10077 /* Transaction processing steering hint 1 for use with the Rx Queue. */ 10078 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG1_RX_OFST 0 10079 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG1_RX_LEN 1 10080 /* Transaction processing steering hint 2 for use with the Ev Queue. */ 10081 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG2_EV_OFST 1 10082 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG2_EV_LEN 1 10083 /* Use Relaxed ordering model for TLPs on this VI. */ 10084 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_RELAXED_ORDERING_LBN 16 10085 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_RELAXED_ORDERING_WIDTH 1 10086 /* Use ID based ordering for TLPs on this VI. */ 10087 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_ID_BASED_ORDERING_LBN 17 10088 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_ID_BASED_ORDERING_WIDTH 1 10089 /* Set no snoop bit for TLPs on this VI. */ 10090 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_NO_SNOOP_LBN 18 10091 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_NO_SNOOP_WIDTH 1 10092 /* Enable TPH for TLPs on this VI. */ 10093 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_ON_LBN 19 10094 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_ON_WIDTH 1 10095 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_DATA_OFST 0 10096 10097 10098 /***********************************/ 10099 /* MC_CMD_SET_VI_TLP_PROCESSING 10100 * Set TLP steering and ordering information for a VI. 10101 */ 10102 #define MC_CMD_SET_VI_TLP_PROCESSING 0xb1 10103 #undef MC_CMD_0xb1_PRIVILEGE_CTG 10104 10105 #define MC_CMD_0xb1_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10106 10107 /* MC_CMD_SET_VI_TLP_PROCESSING_IN msgrequest */ 10108 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_LEN 8 10109 /* VI number to set information for. */ 10110 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_INSTANCE_OFST 0 10111 /* Transaction processing steering hint 1 for use with the Rx Queue. */ 10112 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG1_RX_OFST 4 10113 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG1_RX_LEN 1 10114 /* Transaction processing steering hint 2 for use with the Ev Queue. */ 10115 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG2_EV_OFST 5 10116 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG2_EV_LEN 1 10117 /* Use Relaxed ordering model for TLPs on this VI. */ 10118 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_RELAXED_ORDERING_LBN 48 10119 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_RELAXED_ORDERING_WIDTH 1 10120 /* Use ID based ordering for TLPs on this VI. */ 10121 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_ID_BASED_ORDERING_LBN 49 10122 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_ID_BASED_ORDERING_WIDTH 1 10123 /* Set the no snoop bit for TLPs on this VI. */ 10124 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_NO_SNOOP_LBN 50 10125 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_NO_SNOOP_WIDTH 1 10126 /* Enable TPH for TLPs on this VI. */ 10127 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_ON_LBN 51 10128 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_ON_WIDTH 1 10129 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_DATA_OFST 4 10130 10131 /* MC_CMD_SET_VI_TLP_PROCESSING_OUT msgresponse */ 10132 #define MC_CMD_SET_VI_TLP_PROCESSING_OUT_LEN 0 10133 10134 10135 /***********************************/ 10136 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS 10137 * Get global PCIe steering and transaction processing configuration. 10138 */ 10139 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS 0xbc 10140 #undef MC_CMD_0xbc_PRIVILEGE_CTG 10141 10142 #define MC_CMD_0xbc_PRIVILEGE_CTG SRIOV_CTG_ADMIN 10143 10144 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN msgrequest */ 10145 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_LEN 4 10146 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_OFST 0 10147 /* enum: MISC. */ 10148 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_MISC 0x0 10149 /* enum: IDO. */ 10150 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_IDO 0x1 10151 /* enum: RO. */ 10152 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_RO 0x2 10153 /* enum: TPH Type. */ 10154 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_TPH_TYPE 0x3 10155 10156 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT msgresponse */ 10157 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_LEN 8 10158 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_GLOBAL_CATEGORY_OFST 0 10159 /* Enum values, see field(s): */ 10160 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN/TLP_GLOBAL_CATEGORY */ 10161 /* Amalgamated TLP info word. */ 10162 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_WORD_OFST 4 10163 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_LBN 0 10164 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_WIDTH 1 10165 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_LBN 1 10166 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_WIDTH 31 10167 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_LBN 0 10168 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_WIDTH 1 10169 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_LBN 1 10170 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_WIDTH 1 10171 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_EV_EN_LBN 2 10172 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_EV_EN_WIDTH 1 10173 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_LBN 3 10174 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_WIDTH 1 10175 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_LBN 4 10176 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_WIDTH 28 10177 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_LBN 0 10178 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_WIDTH 1 10179 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_LBN 1 10180 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_WIDTH 1 10181 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_LBN 2 10182 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_WIDTH 1 10183 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_LBN 3 10184 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_WIDTH 29 10185 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_LBN 0 10186 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_WIDTH 2 10187 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_DL_LBN 2 10188 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_DL_WIDTH 2 10189 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_LBN 4 10190 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_WIDTH 2 10191 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_EV_LBN 6 10192 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_EV_WIDTH 2 10193 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_LBN 8 10194 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_WIDTH 2 10195 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_LBN 9 10196 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_WIDTH 23 10197 10198 10199 /***********************************/ 10200 /* MC_CMD_SET_TLP_PROCESSING_GLOBALS 10201 * Set global PCIe steering and transaction processing configuration. 10202 */ 10203 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS 0xbd 10204 #undef MC_CMD_0xbd_PRIVILEGE_CTG 10205 10206 #define MC_CMD_0xbd_PRIVILEGE_CTG SRIOV_CTG_ADMIN 10207 10208 /* MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN msgrequest */ 10209 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_LEN 8 10210 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_OFST 0 10211 /* Enum values, see field(s): */ 10212 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS/MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN/TLP_GLOBAL_CATEGORY */ 10213 /* Amalgamated TLP info word. */ 10214 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_WORD_OFST 4 10215 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_LBN 0 10216 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_WIDTH 1 10217 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_LBN 0 10218 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_WIDTH 1 10219 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_LBN 1 10220 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_WIDTH 1 10221 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_EV_EN_LBN 2 10222 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_EV_EN_WIDTH 1 10223 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_RX_EN_LBN 3 10224 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_RX_EN_WIDTH 1 10225 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_LBN 0 10226 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_WIDTH 1 10227 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_LBN 1 10228 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_WIDTH 1 10229 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_DL_EN_LBN 2 10230 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_DL_EN_WIDTH 1 10231 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_LBN 0 10232 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_WIDTH 2 10233 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_DL_LBN 2 10234 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_DL_WIDTH 2 10235 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_LBN 4 10236 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_WIDTH 2 10237 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_EV_LBN 6 10238 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_EV_WIDTH 2 10239 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_LBN 8 10240 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_WIDTH 2 10241 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_LBN 10 10242 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_WIDTH 22 10243 10244 /* MC_CMD_SET_TLP_PROCESSING_GLOBALS_OUT msgresponse */ 10245 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_OUT_LEN 0 10246 10247 10248 /***********************************/ 10249 /* MC_CMD_SATELLITE_DOWNLOAD 10250 * Download a new set of images to the satellite CPUs from the host. 10251 */ 10252 #define MC_CMD_SATELLITE_DOWNLOAD 0x91 10253 #undef MC_CMD_0x91_PRIVILEGE_CTG 10254 10255 #define MC_CMD_0x91_PRIVILEGE_CTG SRIOV_CTG_ADMIN 10256 10257 /* MC_CMD_SATELLITE_DOWNLOAD_IN msgrequest: The reset requirements for the CPUs 10258 * are subtle, and so downloads must proceed in a number of phases. 10259 * 10260 * 1) PHASE_RESET with a target of TARGET_ALL and chunk ID/length of 0. 10261 * 10262 * 2) PHASE_IMEMS for each of the IMEM targets (target IDs 0-11). Each download 10263 * may consist of multiple chunks. The final chunk (with CHUNK_ID_LAST) should 10264 * be a checksum (a simple 32-bit sum) of the transferred data. An individual 10265 * download may be aborted using CHUNK_ID_ABORT. 10266 * 10267 * 3) PHASE_VECTORS for each of the vector table targets (target IDs 12-15), 10268 * similar to PHASE_IMEMS. 10269 * 10270 * 4) PHASE_READY with a target of TARGET_ALL and chunk ID/length of 0. 10271 * 10272 * After any error (a requested abort is not considered to be an error) the 10273 * sequence must be restarted from PHASE_RESET. 10274 */ 10275 #define MC_CMD_SATELLITE_DOWNLOAD_IN_LENMIN 20 10276 #define MC_CMD_SATELLITE_DOWNLOAD_IN_LENMAX 252 10277 #define MC_CMD_SATELLITE_DOWNLOAD_IN_LEN(num) (16+4*(num)) 10278 /* Download phase. (Note: the IDLE phase is used internally and is never valid 10279 * in a command from the host.) 10280 */ 10281 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_OFST 0 10282 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_IDLE 0x0 /* enum */ 10283 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_RESET 0x1 /* enum */ 10284 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_IMEMS 0x2 /* enum */ 10285 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_VECTORS 0x3 /* enum */ 10286 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_READY 0x4 /* enum */ 10287 /* Target for download. (These match the blob numbers defined in 10288 * mc_flash_layout.h.) 10289 */ 10290 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_OFST 4 10291 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 10292 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_TEXT 0x0 10293 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 10294 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_TEXT 0x1 10295 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 10296 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDP_TEXT 0x2 10297 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 10298 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDP_TEXT 0x3 10299 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 10300 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_LUT 0x4 10301 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 10302 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_LUT_CFG 0x5 10303 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 10304 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_LUT 0x6 10305 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 10306 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_LUT_CFG 0x7 10307 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 10308 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_PGM 0x8 10309 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 10310 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_SL_PGM 0x9 10311 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 10312 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_PGM 0xa 10313 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 10314 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_SL_PGM 0xb 10315 /* enum: Valid in phase 3 (PHASE_VECTORS) only */ 10316 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_VTBL0 0xc 10317 /* enum: Valid in phase 3 (PHASE_VECTORS) only */ 10318 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_VTBL0 0xd 10319 /* enum: Valid in phase 3 (PHASE_VECTORS) only */ 10320 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_VTBL1 0xe 10321 /* enum: Valid in phase 3 (PHASE_VECTORS) only */ 10322 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_VTBL1 0xf 10323 /* enum: Valid in phases 1 (PHASE_RESET) and 4 (PHASE_READY) only */ 10324 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_ALL 0xffffffff 10325 /* Chunk ID, or CHUNK_ID_LAST or CHUNK_ID_ABORT */ 10326 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_OFST 8 10327 /* enum: Last chunk, containing checksum rather than data */ 10328 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_LAST 0xffffffff 10329 /* enum: Abort download of this item */ 10330 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_ABORT 0xfffffffe 10331 /* Length of this chunk in bytes */ 10332 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_LEN_OFST 12 10333 /* Data for this chunk */ 10334 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_OFST 16 10335 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_LEN 4 10336 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_MINNUM 1 10337 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_MAXNUM 59 10338 10339 /* MC_CMD_SATELLITE_DOWNLOAD_OUT msgresponse */ 10340 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_LEN 8 10341 /* Same as MC_CMD_ERR field, but included as 0 in success cases */ 10342 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_RESULT_OFST 0 10343 /* Extra status information */ 10344 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_INFO_OFST 4 10345 /* enum: Code download OK, completed. */ 10346 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_COMPLETE 0x0 10347 /* enum: Code download aborted as requested. */ 10348 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_ABORTED 0x1 10349 /* enum: Code download OK so far, send next chunk. */ 10350 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_NEXT_CHUNK 0x2 10351 /* enum: Download phases out of sequence */ 10352 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_PHASE 0x100 10353 /* enum: Bad target for this phase */ 10354 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_TARGET 0x101 10355 /* enum: Chunk ID out of sequence */ 10356 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHUNK_ID 0x200 10357 /* enum: Chunk length zero or too large */ 10358 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHUNK_LEN 0x201 10359 /* enum: Checksum was incorrect */ 10360 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHECKSUM 0x300 10361 10362 10363 /***********************************/ 10364 /* MC_CMD_GET_CAPABILITIES 10365 * Get device capabilities. 10366 * 10367 * This is supplementary to the MC_CMD_GET_BOARD_CFG command, and intended to 10368 * reference inherent device capabilities as opposed to current NVRAM config. 10369 */ 10370 #define MC_CMD_GET_CAPABILITIES 0xbe 10371 #undef MC_CMD_0xbe_PRIVILEGE_CTG 10372 10373 #define MC_CMD_0xbe_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10374 10375 /* MC_CMD_GET_CAPABILITIES_IN msgrequest */ 10376 #define MC_CMD_GET_CAPABILITIES_IN_LEN 0 10377 10378 /* MC_CMD_GET_CAPABILITIES_OUT msgresponse */ 10379 #define MC_CMD_GET_CAPABILITIES_OUT_LEN 20 10380 /* First word of flags. */ 10381 #define MC_CMD_GET_CAPABILITIES_OUT_FLAGS1_OFST 0 10382 #define MC_CMD_GET_CAPABILITIES_OUT_VPORT_RECONFIGURE_LBN 3 10383 #define MC_CMD_GET_CAPABILITIES_OUT_VPORT_RECONFIGURE_WIDTH 1 10384 #define MC_CMD_GET_CAPABILITIES_OUT_TX_STRIPING_LBN 4 10385 #define MC_CMD_GET_CAPABILITIES_OUT_TX_STRIPING_WIDTH 1 10386 #define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_LBN 5 10387 #define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_WIDTH 1 10388 #define MC_CMD_GET_CAPABILITIES_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6 10389 #define MC_CMD_GET_CAPABILITIES_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1 10390 #define MC_CMD_GET_CAPABILITIES_OUT_DRV_ATTACH_PREBOOT_LBN 7 10391 #define MC_CMD_GET_CAPABILITIES_OUT_DRV_ATTACH_PREBOOT_WIDTH 1 10392 #define MC_CMD_GET_CAPABILITIES_OUT_RX_FORCE_EVENT_MERGING_LBN 8 10393 #define MC_CMD_GET_CAPABILITIES_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1 10394 #define MC_CMD_GET_CAPABILITIES_OUT_SET_MAC_ENHANCED_LBN 9 10395 #define MC_CMD_GET_CAPABILITIES_OUT_SET_MAC_ENHANCED_WIDTH 1 10396 #define MC_CMD_GET_CAPABILITIES_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10 10397 #define MC_CMD_GET_CAPABILITIES_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1 10398 #define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11 10399 #define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1 10400 #define MC_CMD_GET_CAPABILITIES_OUT_TX_MAC_SECURITY_FILTERING_LBN 12 10401 #define MC_CMD_GET_CAPABILITIES_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1 10402 #define MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_LBN 13 10403 #define MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_WIDTH 1 10404 #define MC_CMD_GET_CAPABILITIES_OUT_QBB_LBN 14 10405 #define MC_CMD_GET_CAPABILITIES_OUT_QBB_WIDTH 1 10406 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15 10407 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1 10408 #define MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_LBN 16 10409 #define MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_WIDTH 1 10410 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_LBN 17 10411 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_WIDTH 1 10412 #define MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_LBN 18 10413 #define MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_WIDTH 1 10414 #define MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_LBN 19 10415 #define MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_WIDTH 1 10416 #define MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_LBN 20 10417 #define MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_WIDTH 1 10418 #define MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN 21 10419 #define MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_WIDTH 1 10420 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_LBN 22 10421 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_WIDTH 1 10422 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN 23 10423 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_WIDTH 1 10424 #define MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_LBN 24 10425 #define MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_WIDTH 1 10426 #define MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN 25 10427 #define MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_WIDTH 1 10428 #define MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_LBN 26 10429 #define MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_WIDTH 1 10430 #define MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN 27 10431 #define MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1 10432 #define MC_CMD_GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER_LBN 28 10433 #define MC_CMD_GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER_WIDTH 1 10434 #define MC_CMD_GET_CAPABILITIES_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29 10435 #define MC_CMD_GET_CAPABILITIES_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1 10436 #define MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN 30 10437 #define MC_CMD_GET_CAPABILITIES_OUT_EVB_WIDTH 1 10438 #define MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN 31 10439 #define MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_WIDTH 1 10440 /* RxDPCPU firmware id. */ 10441 #define MC_CMD_GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID_OFST 4 10442 #define MC_CMD_GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID_LEN 2 10443 /* enum: Standard RXDP firmware */ 10444 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP 0x0 10445 /* enum: Low latency RXDP firmware */ 10446 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_LOW_LATENCY 0x1 10447 /* enum: Packed stream RXDP firmware */ 10448 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_PACKED_STREAM 0x2 10449 /* enum: BIST RXDP firmware */ 10450 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_BIST 0x10a 10451 /* enum: RXDP Test firmware image 1 */ 10452 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101 10453 /* enum: RXDP Test firmware image 2 */ 10454 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102 10455 /* enum: RXDP Test firmware image 3 */ 10456 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103 10457 /* enum: RXDP Test firmware image 4 */ 10458 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104 10459 /* enum: RXDP Test firmware image 5 */ 10460 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_BACKPRESSURE 0x105 10461 /* enum: RXDP Test firmware image 6 */ 10462 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106 10463 /* enum: RXDP Test firmware image 7 */ 10464 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107 10465 /* enum: RXDP Test firmware image 8 */ 10466 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_DISABLE_DL 0x108 10467 /* enum: RXDP Test firmware image 9 */ 10468 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b 10469 /* TxDPCPU firmware id. */ 10470 #define MC_CMD_GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID_OFST 6 10471 #define MC_CMD_GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID_LEN 2 10472 /* enum: Standard TXDP firmware */ 10473 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP 0x0 10474 /* enum: Low latency TXDP firmware */ 10475 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_LOW_LATENCY 0x1 10476 /* enum: High packet rate TXDP firmware */ 10477 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_HIGH_PACKET_RATE 0x3 10478 /* enum: BIST TXDP firmware */ 10479 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_BIST 0x12d 10480 /* enum: TXDP Test firmware image 1 */ 10481 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_TSO_EDIT 0x101 10482 /* enum: TXDP Test firmware image 2 */ 10483 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102 10484 /* enum: TXDP CSR bus test firmware */ 10485 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_CSR 0x103 10486 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_OFST 8 10487 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_LEN 2 10488 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_LBN 0 10489 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_WIDTH 12 10490 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_LBN 12 10491 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4 10492 /* enum: reserved value - do not use (may indicate alternative interpretation 10493 * of REV field in future) 10494 */ 10495 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_RESERVED 0x0 10496 /* enum: Trivial RX PD firmware for early Huntington development (Huntington 10497 * development only) 10498 */ 10499 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1 10500 /* enum: RX PD firmware with approximately Siena-compatible behaviour 10501 * (Huntington development only) 10502 */ 10503 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2 10504 /* enum: Full featured RX PD production firmware */ 10505 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3 10506 /* enum: (deprecated original name for the FULL_FEATURED variant) */ 10507 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_VSWITCH 0x3 10508 /* enum: siena_compat variant RX PD firmware using PM rather than MAC 10509 * (Huntington development only) 10510 */ 10511 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 10512 /* enum: Low latency RX PD production firmware */ 10513 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5 10514 /* enum: Packed stream RX PD production firmware */ 10515 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6 10516 /* enum: RX PD firmware handling layer 2 only for high packet rate performance 10517 * tests (Medford development only) 10518 */ 10519 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7 10520 /* enum: Rules engine RX PD production firmware */ 10521 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8 10522 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 10523 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 10524 /* enum: RX PD firmware parsing but not filtering network overlay tunnel 10525 * encapsulations (Medford development only) 10526 */ 10527 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf 10528 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_OFST 10 10529 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_LEN 2 10530 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_LBN 0 10531 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_WIDTH 12 10532 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_LBN 12 10533 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4 10534 /* enum: reserved value - do not use (may indicate alternative interpretation 10535 * of REV field in future) 10536 */ 10537 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_RESERVED 0x0 10538 /* enum: Trivial TX PD firmware for early Huntington development (Huntington 10539 * development only) 10540 */ 10541 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1 10542 /* enum: TX PD firmware with approximately Siena-compatible behaviour 10543 * (Huntington development only) 10544 */ 10545 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2 10546 /* enum: Full featured TX PD production firmware */ 10547 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3 10548 /* enum: (deprecated original name for the FULL_FEATURED variant) */ 10549 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_VSWITCH 0x3 10550 /* enum: siena_compat variant TX PD firmware using PM rather than MAC 10551 * (Huntington development only) 10552 */ 10553 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 10554 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */ 10555 /* enum: TX PD firmware handling layer 2 only for high packet rate performance 10556 * tests (Medford development only) 10557 */ 10558 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7 10559 /* enum: Rules engine TX PD production firmware */ 10560 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8 10561 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 10562 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 10563 /* Hardware capabilities of NIC */ 10564 #define MC_CMD_GET_CAPABILITIES_OUT_HW_CAPABILITIES_OFST 12 10565 /* Licensed capabilities */ 10566 #define MC_CMD_GET_CAPABILITIES_OUT_LICENSE_CAPABILITIES_OFST 16 10567 10568 /* MC_CMD_GET_CAPABILITIES_V2_IN msgrequest */ 10569 #define MC_CMD_GET_CAPABILITIES_V2_IN_LEN 0 10570 10571 /* MC_CMD_GET_CAPABILITIES_V2_OUT msgresponse */ 10572 #define MC_CMD_GET_CAPABILITIES_V2_OUT_LEN 72 10573 /* First word of flags. */ 10574 #define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS1_OFST 0 10575 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VPORT_RECONFIGURE_LBN 3 10576 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VPORT_RECONFIGURE_WIDTH 1 10577 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_STRIPING_LBN 4 10578 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_STRIPING_WIDTH 1 10579 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_QUERY_LBN 5 10580 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_QUERY_WIDTH 1 10581 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6 10582 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1 10583 #define MC_CMD_GET_CAPABILITIES_V2_OUT_DRV_ATTACH_PREBOOT_LBN 7 10584 #define MC_CMD_GET_CAPABILITIES_V2_OUT_DRV_ATTACH_PREBOOT_WIDTH 1 10585 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_FORCE_EVENT_MERGING_LBN 8 10586 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1 10587 #define MC_CMD_GET_CAPABILITIES_V2_OUT_SET_MAC_ENHANCED_LBN 9 10588 #define MC_CMD_GET_CAPABILITIES_V2_OUT_SET_MAC_ENHANCED_WIDTH 1 10589 #define MC_CMD_GET_CAPABILITIES_V2_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10 10590 #define MC_CMD_GET_CAPABILITIES_V2_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1 10591 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11 10592 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1 10593 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_SECURITY_FILTERING_LBN 12 10594 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1 10595 #define MC_CMD_GET_CAPABILITIES_V2_OUT_ADDITIONAL_RSS_MODES_LBN 13 10596 #define MC_CMD_GET_CAPABILITIES_V2_OUT_ADDITIONAL_RSS_MODES_WIDTH 1 10597 #define MC_CMD_GET_CAPABILITIES_V2_OUT_QBB_LBN 14 10598 #define MC_CMD_GET_CAPABILITIES_V2_OUT_QBB_WIDTH 1 10599 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15 10600 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1 10601 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_RSS_LIMITED_LBN 16 10602 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_RSS_LIMITED_WIDTH 1 10603 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_LBN 17 10604 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_WIDTH 1 10605 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_INCLUDE_FCS_LBN 18 10606 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_INCLUDE_FCS_WIDTH 1 10607 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VLAN_INSERTION_LBN 19 10608 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VLAN_INSERTION_WIDTH 1 10609 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_VLAN_STRIPPING_LBN 20 10610 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_VLAN_STRIPPING_WIDTH 1 10611 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_LBN 21 10612 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_WIDTH 1 10613 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_0_LBN 22 10614 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_0_WIDTH 1 10615 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_14_LBN 23 10616 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_14_WIDTH 1 10617 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_TIMESTAMP_LBN 24 10618 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_TIMESTAMP_WIDTH 1 10619 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_BATCHING_LBN 25 10620 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_BATCHING_WIDTH 1 10621 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MCAST_FILTER_CHAINING_LBN 26 10622 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MCAST_FILTER_CHAINING_WIDTH 1 10623 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PM_AND_RXDP_COUNTERS_LBN 27 10624 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1 10625 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DISABLE_SCATTER_LBN 28 10626 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DISABLE_SCATTER_WIDTH 1 10627 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29 10628 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1 10629 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_LBN 30 10630 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_WIDTH 1 10631 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VXLAN_NVGRE_LBN 31 10632 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VXLAN_NVGRE_WIDTH 1 10633 /* RxDPCPU firmware id. */ 10634 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DPCPU_FW_ID_OFST 4 10635 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DPCPU_FW_ID_LEN 2 10636 /* enum: Standard RXDP firmware */ 10637 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP 0x0 10638 /* enum: Low latency RXDP firmware */ 10639 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_LOW_LATENCY 0x1 10640 /* enum: Packed stream RXDP firmware */ 10641 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_PACKED_STREAM 0x2 10642 /* enum: BIST RXDP firmware */ 10643 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_BIST 0x10a 10644 /* enum: RXDP Test firmware image 1 */ 10645 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101 10646 /* enum: RXDP Test firmware image 2 */ 10647 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102 10648 /* enum: RXDP Test firmware image 3 */ 10649 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103 10650 /* enum: RXDP Test firmware image 4 */ 10651 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104 10652 /* enum: RXDP Test firmware image 5 */ 10653 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_BACKPRESSURE 0x105 10654 /* enum: RXDP Test firmware image 6 */ 10655 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106 10656 /* enum: RXDP Test firmware image 7 */ 10657 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107 10658 /* enum: RXDP Test firmware image 8 */ 10659 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_DISABLE_DL 0x108 10660 /* enum: RXDP Test firmware image 9 */ 10661 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b 10662 /* TxDPCPU firmware id. */ 10663 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DPCPU_FW_ID_OFST 6 10664 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DPCPU_FW_ID_LEN 2 10665 /* enum: Standard TXDP firmware */ 10666 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP 0x0 10667 /* enum: Low latency TXDP firmware */ 10668 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_LOW_LATENCY 0x1 10669 /* enum: High packet rate TXDP firmware */ 10670 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_HIGH_PACKET_RATE 0x3 10671 /* enum: BIST TXDP firmware */ 10672 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_BIST 0x12d 10673 /* enum: TXDP Test firmware image 1 */ 10674 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_TSO_EDIT 0x101 10675 /* enum: TXDP Test firmware image 2 */ 10676 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102 10677 /* enum: TXDP CSR bus test firmware */ 10678 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_CSR 0x103 10679 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_OFST 8 10680 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_LEN 2 10681 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_REV_LBN 0 10682 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_REV_WIDTH 12 10683 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_TYPE_LBN 12 10684 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4 10685 /* enum: reserved value - do not use (may indicate alternative interpretation 10686 * of REV field in future) 10687 */ 10688 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_RESERVED 0x0 10689 /* enum: Trivial RX PD firmware for early Huntington development (Huntington 10690 * development only) 10691 */ 10692 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1 10693 /* enum: RX PD firmware with approximately Siena-compatible behaviour 10694 * (Huntington development only) 10695 */ 10696 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2 10697 /* enum: Full featured RX PD production firmware */ 10698 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3 10699 /* enum: (deprecated original name for the FULL_FEATURED variant) */ 10700 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_VSWITCH 0x3 10701 /* enum: siena_compat variant RX PD firmware using PM rather than MAC 10702 * (Huntington development only) 10703 */ 10704 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 10705 /* enum: Low latency RX PD production firmware */ 10706 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5 10707 /* enum: Packed stream RX PD production firmware */ 10708 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6 10709 /* enum: RX PD firmware handling layer 2 only for high packet rate performance 10710 * tests (Medford development only) 10711 */ 10712 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7 10713 /* enum: Rules engine RX PD production firmware */ 10714 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8 10715 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 10716 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 10717 /* enum: RX PD firmware parsing but not filtering network overlay tunnel 10718 * encapsulations (Medford development only) 10719 */ 10720 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf 10721 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_OFST 10 10722 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_LEN 2 10723 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_REV_LBN 0 10724 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_REV_WIDTH 12 10725 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_TYPE_LBN 12 10726 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4 10727 /* enum: reserved value - do not use (may indicate alternative interpretation 10728 * of REV field in future) 10729 */ 10730 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_RESERVED 0x0 10731 /* enum: Trivial TX PD firmware for early Huntington development (Huntington 10732 * development only) 10733 */ 10734 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1 10735 /* enum: TX PD firmware with approximately Siena-compatible behaviour 10736 * (Huntington development only) 10737 */ 10738 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2 10739 /* enum: Full featured TX PD production firmware */ 10740 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3 10741 /* enum: (deprecated original name for the FULL_FEATURED variant) */ 10742 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_VSWITCH 0x3 10743 /* enum: siena_compat variant TX PD firmware using PM rather than MAC 10744 * (Huntington development only) 10745 */ 10746 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 10747 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */ 10748 /* enum: TX PD firmware handling layer 2 only for high packet rate performance 10749 * tests (Medford development only) 10750 */ 10751 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7 10752 /* enum: Rules engine TX PD production firmware */ 10753 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8 10754 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 10755 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 10756 /* Hardware capabilities of NIC */ 10757 #define MC_CMD_GET_CAPABILITIES_V2_OUT_HW_CAPABILITIES_OFST 12 10758 /* Licensed capabilities */ 10759 #define MC_CMD_GET_CAPABILITIES_V2_OUT_LICENSE_CAPABILITIES_OFST 16 10760 /* Second word of flags. Not present on older firmware (check the length). */ 10761 #define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS2_OFST 20 10762 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN 0 10763 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_WIDTH 1 10764 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_ENCAP_LBN 1 10765 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_ENCAP_WIDTH 1 10766 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVQ_TIMER_CTRL_LBN 2 10767 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVQ_TIMER_CTRL_WIDTH 1 10768 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVENT_CUT_THROUGH_LBN 3 10769 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVENT_CUT_THROUGH_WIDTH 1 10770 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_CUT_THROUGH_LBN 4 10771 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_CUT_THROUGH_WIDTH 1 10772 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VFIFO_ULL_MODE_LBN 5 10773 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VFIFO_ULL_MODE_WIDTH 1 10774 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6 10775 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1 10776 #define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_LBN 7 10777 #define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_WIDTH 1 10778 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_TIMESTAMPING_LBN 8 10779 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_TIMESTAMPING_WIDTH 1 10780 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TIMESTAMP_LBN 9 10781 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TIMESTAMP_WIDTH 1 10782 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_SNIFF_LBN 10 10783 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_SNIFF_WIDTH 1 10784 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_SNIFF_LBN 11 10785 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_SNIFF_WIDTH 1 10786 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12 10787 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1 10788 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_BACKGROUND_LBN 13 10789 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_BACKGROUND_WIDTH 1 10790 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_DB_RETURN_LBN 14 10791 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_DB_RETURN_WIDTH 1 10792 /* Number of FATSOv2 contexts per datapath supported by this NIC. Not present 10793 * on older firmware (check the length). 10794 */ 10795 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24 10796 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2 10797 /* One byte per PF containing the number of the external port assigned to this 10798 * PF, indexed by PF number. Special values indicate that a PF is either not 10799 * present or not assigned. 10800 */ 10801 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26 10802 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1 10803 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16 10804 /* enum: The caller is not permitted to access information on this PF. */ 10805 #define MC_CMD_GET_CAPABILITIES_V2_OUT_ACCESS_NOT_PERMITTED 0xff 10806 /* enum: PF does not exist. */ 10807 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_PRESENT 0xfe 10808 /* enum: PF does exist but is not assigned to any external port. */ 10809 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_ASSIGNED 0xfd 10810 /* enum: This value indicates that PF is assigned, but it cannot be expressed 10811 * in this field. It is intended for a possible future situation where a more 10812 * complex scheme of PFs to ports mapping is being used. The future driver 10813 * should look for a new field supporting the new scheme. The current/old 10814 * driver should treat this value as PF_NOT_ASSIGNED. 10815 */ 10816 #define MC_CMD_GET_CAPABILITIES_V2_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc 10817 /* One byte per PF containing the number of its VFs, indexed by PF number. A 10818 * special value indicates that a PF is not present. 10819 */ 10820 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VFS_PER_PF_OFST 42 10821 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VFS_PER_PF_LEN 1 10822 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VFS_PER_PF_NUM 16 10823 /* enum: The caller is not permitted to access information on this PF. */ 10824 /* MC_CMD_GET_CAPABILITIES_V2_OUT_ACCESS_NOT_PERMITTED 0xff */ 10825 /* enum: PF does not exist. */ 10826 /* MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_PRESENT 0xfe */ 10827 /* Number of VIs available for each external port */ 10828 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_OFST 58 10829 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_LEN 2 10830 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_NUM 4 10831 /* Size of RX descriptor cache expressed as binary logarithm The actual size 10832 * equals (2 ^ RX_DESC_CACHE_SIZE) 10833 */ 10834 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DESC_CACHE_SIZE_OFST 66 10835 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DESC_CACHE_SIZE_LEN 1 10836 /* Size of TX descriptor cache expressed as binary logarithm The actual size 10837 * equals (2 ^ TX_DESC_CACHE_SIZE) 10838 */ 10839 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DESC_CACHE_SIZE_OFST 67 10840 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DESC_CACHE_SIZE_LEN 1 10841 /* Total number of available PIO buffers */ 10842 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_PIO_BUFFS_OFST 68 10843 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_PIO_BUFFS_LEN 2 10844 /* Size of a single PIO buffer */ 10845 #define MC_CMD_GET_CAPABILITIES_V2_OUT_SIZE_PIO_BUFF_OFST 70 10846 #define MC_CMD_GET_CAPABILITIES_V2_OUT_SIZE_PIO_BUFF_LEN 2 10847 10848 /* MC_CMD_GET_CAPABILITIES_V3_OUT msgresponse */ 10849 #define MC_CMD_GET_CAPABILITIES_V3_OUT_LEN 76 10850 /* First word of flags. */ 10851 #define MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS1_OFST 0 10852 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VPORT_RECONFIGURE_LBN 3 10853 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VPORT_RECONFIGURE_WIDTH 1 10854 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_STRIPING_LBN 4 10855 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_STRIPING_WIDTH 1 10856 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_QUERY_LBN 5 10857 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_QUERY_WIDTH 1 10858 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6 10859 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1 10860 #define MC_CMD_GET_CAPABILITIES_V3_OUT_DRV_ATTACH_PREBOOT_LBN 7 10861 #define MC_CMD_GET_CAPABILITIES_V3_OUT_DRV_ATTACH_PREBOOT_WIDTH 1 10862 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_FORCE_EVENT_MERGING_LBN 8 10863 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1 10864 #define MC_CMD_GET_CAPABILITIES_V3_OUT_SET_MAC_ENHANCED_LBN 9 10865 #define MC_CMD_GET_CAPABILITIES_V3_OUT_SET_MAC_ENHANCED_WIDTH 1 10866 #define MC_CMD_GET_CAPABILITIES_V3_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10 10867 #define MC_CMD_GET_CAPABILITIES_V3_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1 10868 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11 10869 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1 10870 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_SECURITY_FILTERING_LBN 12 10871 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1 10872 #define MC_CMD_GET_CAPABILITIES_V3_OUT_ADDITIONAL_RSS_MODES_LBN 13 10873 #define MC_CMD_GET_CAPABILITIES_V3_OUT_ADDITIONAL_RSS_MODES_WIDTH 1 10874 #define MC_CMD_GET_CAPABILITIES_V3_OUT_QBB_LBN 14 10875 #define MC_CMD_GET_CAPABILITIES_V3_OUT_QBB_WIDTH 1 10876 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15 10877 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1 10878 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_RSS_LIMITED_LBN 16 10879 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_RSS_LIMITED_WIDTH 1 10880 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_LBN 17 10881 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_WIDTH 1 10882 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_INCLUDE_FCS_LBN 18 10883 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_INCLUDE_FCS_WIDTH 1 10884 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VLAN_INSERTION_LBN 19 10885 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VLAN_INSERTION_WIDTH 1 10886 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_VLAN_STRIPPING_LBN 20 10887 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_VLAN_STRIPPING_WIDTH 1 10888 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_LBN 21 10889 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_WIDTH 1 10890 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_0_LBN 22 10891 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_0_WIDTH 1 10892 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_14_LBN 23 10893 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_14_WIDTH 1 10894 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_TIMESTAMP_LBN 24 10895 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_TIMESTAMP_WIDTH 1 10896 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_BATCHING_LBN 25 10897 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_BATCHING_WIDTH 1 10898 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MCAST_FILTER_CHAINING_LBN 26 10899 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MCAST_FILTER_CHAINING_WIDTH 1 10900 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PM_AND_RXDP_COUNTERS_LBN 27 10901 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1 10902 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DISABLE_SCATTER_LBN 28 10903 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DISABLE_SCATTER_WIDTH 1 10904 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29 10905 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1 10906 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_LBN 30 10907 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_WIDTH 1 10908 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VXLAN_NVGRE_LBN 31 10909 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VXLAN_NVGRE_WIDTH 1 10910 /* RxDPCPU firmware id. */ 10911 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DPCPU_FW_ID_OFST 4 10912 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DPCPU_FW_ID_LEN 2 10913 /* enum: Standard RXDP firmware */ 10914 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP 0x0 10915 /* enum: Low latency RXDP firmware */ 10916 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_LOW_LATENCY 0x1 10917 /* enum: Packed stream RXDP firmware */ 10918 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_PACKED_STREAM 0x2 10919 /* enum: BIST RXDP firmware */ 10920 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_BIST 0x10a 10921 /* enum: RXDP Test firmware image 1 */ 10922 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101 10923 /* enum: RXDP Test firmware image 2 */ 10924 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102 10925 /* enum: RXDP Test firmware image 3 */ 10926 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103 10927 /* enum: RXDP Test firmware image 4 */ 10928 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104 10929 /* enum: RXDP Test firmware image 5 */ 10930 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_BACKPRESSURE 0x105 10931 /* enum: RXDP Test firmware image 6 */ 10932 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106 10933 /* enum: RXDP Test firmware image 7 */ 10934 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107 10935 /* enum: RXDP Test firmware image 8 */ 10936 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_DISABLE_DL 0x108 10937 /* enum: RXDP Test firmware image 9 */ 10938 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b 10939 /* TxDPCPU firmware id. */ 10940 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_DPCPU_FW_ID_OFST 6 10941 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_DPCPU_FW_ID_LEN 2 10942 /* enum: Standard TXDP firmware */ 10943 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP 0x0 10944 /* enum: Low latency TXDP firmware */ 10945 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_LOW_LATENCY 0x1 10946 /* enum: High packet rate TXDP firmware */ 10947 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_HIGH_PACKET_RATE 0x3 10948 /* enum: BIST TXDP firmware */ 10949 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_BIST 0x12d 10950 /* enum: TXDP Test firmware image 1 */ 10951 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_TSO_EDIT 0x101 10952 /* enum: TXDP Test firmware image 2 */ 10953 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102 10954 /* enum: TXDP CSR bus test firmware */ 10955 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_CSR 0x103 10956 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_OFST 8 10957 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_LEN 2 10958 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_REV_LBN 0 10959 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_REV_WIDTH 12 10960 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_TYPE_LBN 12 10961 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4 10962 /* enum: reserved value - do not use (may indicate alternative interpretation 10963 * of REV field in future) 10964 */ 10965 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_RESERVED 0x0 10966 /* enum: Trivial RX PD firmware for early Huntington development (Huntington 10967 * development only) 10968 */ 10969 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1 10970 /* enum: RX PD firmware with approximately Siena-compatible behaviour 10971 * (Huntington development only) 10972 */ 10973 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2 10974 /* enum: Full featured RX PD production firmware */ 10975 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3 10976 /* enum: (deprecated original name for the FULL_FEATURED variant) */ 10977 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_VSWITCH 0x3 10978 /* enum: siena_compat variant RX PD firmware using PM rather than MAC 10979 * (Huntington development only) 10980 */ 10981 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 10982 /* enum: Low latency RX PD production firmware */ 10983 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5 10984 /* enum: Packed stream RX PD production firmware */ 10985 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6 10986 /* enum: RX PD firmware handling layer 2 only for high packet rate performance 10987 * tests (Medford development only) 10988 */ 10989 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7 10990 /* enum: Rules engine RX PD production firmware */ 10991 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8 10992 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 10993 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 10994 /* enum: RX PD firmware parsing but not filtering network overlay tunnel 10995 * encapsulations (Medford development only) 10996 */ 10997 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf 10998 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_OFST 10 10999 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_LEN 2 11000 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_REV_LBN 0 11001 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_REV_WIDTH 12 11002 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_TYPE_LBN 12 11003 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4 11004 /* enum: reserved value - do not use (may indicate alternative interpretation 11005 * of REV field in future) 11006 */ 11007 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_RESERVED 0x0 11008 /* enum: Trivial TX PD firmware for early Huntington development (Huntington 11009 * development only) 11010 */ 11011 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1 11012 /* enum: TX PD firmware with approximately Siena-compatible behaviour 11013 * (Huntington development only) 11014 */ 11015 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2 11016 /* enum: Full featured TX PD production firmware */ 11017 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3 11018 /* enum: (deprecated original name for the FULL_FEATURED variant) */ 11019 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_VSWITCH 0x3 11020 /* enum: siena_compat variant TX PD firmware using PM rather than MAC 11021 * (Huntington development only) 11022 */ 11023 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 11024 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */ 11025 /* enum: TX PD firmware handling layer 2 only for high packet rate performance 11026 * tests (Medford development only) 11027 */ 11028 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7 11029 /* enum: Rules engine TX PD production firmware */ 11030 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8 11031 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 11032 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 11033 /* Hardware capabilities of NIC */ 11034 #define MC_CMD_GET_CAPABILITIES_V3_OUT_HW_CAPABILITIES_OFST 12 11035 /* Licensed capabilities */ 11036 #define MC_CMD_GET_CAPABILITIES_V3_OUT_LICENSE_CAPABILITIES_OFST 16 11037 /* Second word of flags. Not present on older firmware (check the length). */ 11038 #define MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS2_OFST 20 11039 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_LBN 0 11040 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_WIDTH 1 11041 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_ENCAP_LBN 1 11042 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_ENCAP_WIDTH 1 11043 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVQ_TIMER_CTRL_LBN 2 11044 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVQ_TIMER_CTRL_WIDTH 1 11045 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVENT_CUT_THROUGH_LBN 3 11046 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVENT_CUT_THROUGH_WIDTH 1 11047 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_CUT_THROUGH_LBN 4 11048 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_CUT_THROUGH_WIDTH 1 11049 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VFIFO_ULL_MODE_LBN 5 11050 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VFIFO_ULL_MODE_WIDTH 1 11051 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6 11052 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1 11053 #define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_V2_LBN 7 11054 #define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_V2_WIDTH 1 11055 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_TIMESTAMPING_LBN 8 11056 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_TIMESTAMPING_WIDTH 1 11057 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TIMESTAMP_LBN 9 11058 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TIMESTAMP_WIDTH 1 11059 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_SNIFF_LBN 10 11060 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_SNIFF_WIDTH 1 11061 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_SNIFF_LBN 11 11062 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_SNIFF_WIDTH 1 11063 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12 11064 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1 11065 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_BACKGROUND_LBN 13 11066 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_BACKGROUND_WIDTH 1 11067 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_DB_RETURN_LBN 14 11068 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_DB_RETURN_WIDTH 1 11069 /* Number of FATSOv2 contexts per datapath supported by this NIC. Not present 11070 * on older firmware (check the length). 11071 */ 11072 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24 11073 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2 11074 /* One byte per PF containing the number of the external port assigned to this 11075 * PF, indexed by PF number. Special values indicate that a PF is either not 11076 * present or not assigned. 11077 */ 11078 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26 11079 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1 11080 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16 11081 /* enum: The caller is not permitted to access information on this PF. */ 11082 #define MC_CMD_GET_CAPABILITIES_V3_OUT_ACCESS_NOT_PERMITTED 0xff 11083 /* enum: PF does not exist. */ 11084 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_PRESENT 0xfe 11085 /* enum: PF does exist but is not assigned to any external port. */ 11086 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_ASSIGNED 0xfd 11087 /* enum: This value indicates that PF is assigned, but it cannot be expressed 11088 * in this field. It is intended for a possible future situation where a more 11089 * complex scheme of PFs to ports mapping is being used. The future driver 11090 * should look for a new field supporting the new scheme. The current/old 11091 * driver should treat this value as PF_NOT_ASSIGNED. 11092 */ 11093 #define MC_CMD_GET_CAPABILITIES_V3_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc 11094 /* One byte per PF containing the number of its VFs, indexed by PF number. A 11095 * special value indicates that a PF is not present. 11096 */ 11097 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VFS_PER_PF_OFST 42 11098 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VFS_PER_PF_LEN 1 11099 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VFS_PER_PF_NUM 16 11100 /* enum: The caller is not permitted to access information on this PF. */ 11101 /* MC_CMD_GET_CAPABILITIES_V3_OUT_ACCESS_NOT_PERMITTED 0xff */ 11102 /* enum: PF does not exist. */ 11103 /* MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_PRESENT 0xfe */ 11104 /* Number of VIs available for each external port */ 11105 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VIS_PER_PORT_OFST 58 11106 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VIS_PER_PORT_LEN 2 11107 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VIS_PER_PORT_NUM 4 11108 /* Size of RX descriptor cache expressed as binary logarithm The actual size 11109 * equals (2 ^ RX_DESC_CACHE_SIZE) 11110 */ 11111 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DESC_CACHE_SIZE_OFST 66 11112 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DESC_CACHE_SIZE_LEN 1 11113 /* Size of TX descriptor cache expressed as binary logarithm The actual size 11114 * equals (2 ^ TX_DESC_CACHE_SIZE) 11115 */ 11116 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_DESC_CACHE_SIZE_OFST 67 11117 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_DESC_CACHE_SIZE_LEN 1 11118 /* Total number of available PIO buffers */ 11119 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_PIO_BUFFS_OFST 68 11120 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_PIO_BUFFS_LEN 2 11121 /* Size of a single PIO buffer */ 11122 #define MC_CMD_GET_CAPABILITIES_V3_OUT_SIZE_PIO_BUFF_OFST 70 11123 #define MC_CMD_GET_CAPABILITIES_V3_OUT_SIZE_PIO_BUFF_LEN 2 11124 /* On chips later than Medford the amount of address space assigned to each VI 11125 * is configurable. This is a global setting that the driver must query to 11126 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available 11127 * with 8k VI windows. 11128 */ 11129 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_OFST 72 11130 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_LEN 1 11131 /* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k. 11132 * CTPIO is not mapped. 11133 */ 11134 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_8K 0x0 11135 /* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */ 11136 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_16K 0x1 11137 /* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */ 11138 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_64K 0x2 11139 /* Number of vFIFOs per adapter that can be used for VFIFO Stuffing 11140 * (SF-115995-SW) in the present configuration of firmware and port mode. 11141 */ 11142 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 73 11143 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1 11144 /* Number of buffers per adapter that can be used for VFIFO Stuffing 11145 * (SF-115995-SW) in the present configuration of firmware and port mode. 11146 */ 11147 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 74 11148 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 2 11149 11150 11151 /***********************************/ 11152 /* MC_CMD_V2_EXTN 11153 * Encapsulation for a v2 extended command 11154 */ 11155 #define MC_CMD_V2_EXTN 0x7f 11156 11157 /* MC_CMD_V2_EXTN_IN msgrequest */ 11158 #define MC_CMD_V2_EXTN_IN_LEN 4 11159 /* the extended command number */ 11160 #define MC_CMD_V2_EXTN_IN_EXTENDED_CMD_LBN 0 11161 #define MC_CMD_V2_EXTN_IN_EXTENDED_CMD_WIDTH 15 11162 #define MC_CMD_V2_EXTN_IN_UNUSED_LBN 15 11163 #define MC_CMD_V2_EXTN_IN_UNUSED_WIDTH 1 11164 /* the actual length of the encapsulated command (which is not in the v1 11165 * header) 11166 */ 11167 #define MC_CMD_V2_EXTN_IN_ACTUAL_LEN_LBN 16 11168 #define MC_CMD_V2_EXTN_IN_ACTUAL_LEN_WIDTH 10 11169 #define MC_CMD_V2_EXTN_IN_UNUSED2_LBN 26 11170 #define MC_CMD_V2_EXTN_IN_UNUSED2_WIDTH 6 11171 11172 11173 /***********************************/ 11174 /* MC_CMD_TCM_BUCKET_ALLOC 11175 * Allocate a pacer bucket (for qau rp or a snapper test) 11176 */ 11177 #define MC_CMD_TCM_BUCKET_ALLOC 0xb2 11178 #undef MC_CMD_0xb2_PRIVILEGE_CTG 11179 11180 #define MC_CMD_0xb2_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11181 11182 /* MC_CMD_TCM_BUCKET_ALLOC_IN msgrequest */ 11183 #define MC_CMD_TCM_BUCKET_ALLOC_IN_LEN 0 11184 11185 /* MC_CMD_TCM_BUCKET_ALLOC_OUT msgresponse */ 11186 #define MC_CMD_TCM_BUCKET_ALLOC_OUT_LEN 4 11187 /* the bucket id */ 11188 #define MC_CMD_TCM_BUCKET_ALLOC_OUT_BUCKET_OFST 0 11189 11190 11191 /***********************************/ 11192 /* MC_CMD_TCM_BUCKET_FREE 11193 * Free a pacer bucket 11194 */ 11195 #define MC_CMD_TCM_BUCKET_FREE 0xb3 11196 #undef MC_CMD_0xb3_PRIVILEGE_CTG 11197 11198 #define MC_CMD_0xb3_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11199 11200 /* MC_CMD_TCM_BUCKET_FREE_IN msgrequest */ 11201 #define MC_CMD_TCM_BUCKET_FREE_IN_LEN 4 11202 /* the bucket id */ 11203 #define MC_CMD_TCM_BUCKET_FREE_IN_BUCKET_OFST 0 11204 11205 /* MC_CMD_TCM_BUCKET_FREE_OUT msgresponse */ 11206 #define MC_CMD_TCM_BUCKET_FREE_OUT_LEN 0 11207 11208 11209 /***********************************/ 11210 /* MC_CMD_TCM_BUCKET_INIT 11211 * Initialise pacer bucket with a given rate 11212 */ 11213 #define MC_CMD_TCM_BUCKET_INIT 0xb4 11214 #undef MC_CMD_0xb4_PRIVILEGE_CTG 11215 11216 #define MC_CMD_0xb4_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11217 11218 /* MC_CMD_TCM_BUCKET_INIT_IN msgrequest */ 11219 #define MC_CMD_TCM_BUCKET_INIT_IN_LEN 8 11220 /* the bucket id */ 11221 #define MC_CMD_TCM_BUCKET_INIT_IN_BUCKET_OFST 0 11222 /* the rate in mbps */ 11223 #define MC_CMD_TCM_BUCKET_INIT_IN_RATE_OFST 4 11224 11225 /* MC_CMD_TCM_BUCKET_INIT_EXT_IN msgrequest */ 11226 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_LEN 12 11227 /* the bucket id */ 11228 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_BUCKET_OFST 0 11229 /* the rate in mbps */ 11230 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_RATE_OFST 4 11231 /* the desired maximum fill level */ 11232 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_MAX_FILL_OFST 8 11233 11234 /* MC_CMD_TCM_BUCKET_INIT_OUT msgresponse */ 11235 #define MC_CMD_TCM_BUCKET_INIT_OUT_LEN 0 11236 11237 11238 /***********************************/ 11239 /* MC_CMD_TCM_TXQ_INIT 11240 * Initialise txq in pacer with given options or set options 11241 */ 11242 #define MC_CMD_TCM_TXQ_INIT 0xb5 11243 #undef MC_CMD_0xb5_PRIVILEGE_CTG 11244 11245 #define MC_CMD_0xb5_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11246 11247 /* MC_CMD_TCM_TXQ_INIT_IN msgrequest */ 11248 #define MC_CMD_TCM_TXQ_INIT_IN_LEN 28 11249 /* the txq id */ 11250 #define MC_CMD_TCM_TXQ_INIT_IN_QID_OFST 0 11251 /* the static priority associated with the txq */ 11252 #define MC_CMD_TCM_TXQ_INIT_IN_LABEL_OFST 4 11253 /* bitmask of the priority queues this txq is inserted into when inserted. */ 11254 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAGS_OFST 8 11255 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_GUARANTEED_LBN 0 11256 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_GUARANTEED_WIDTH 1 11257 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_NORMAL_LBN 1 11258 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_NORMAL_WIDTH 1 11259 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_LOW_LBN 2 11260 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_LOW_WIDTH 1 11261 /* the reaction point (RP) bucket */ 11262 #define MC_CMD_TCM_TXQ_INIT_IN_RP_BKT_OFST 12 11263 /* an already reserved bucket (typically set to bucket associated with outer 11264 * vswitch) 11265 */ 11266 #define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT1_OFST 16 11267 /* an already reserved bucket (typically set to bucket associated with inner 11268 * vswitch) 11269 */ 11270 #define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT2_OFST 20 11271 /* the min bucket (typically for ETS/minimum bandwidth) */ 11272 #define MC_CMD_TCM_TXQ_INIT_IN_MIN_BKT_OFST 24 11273 11274 /* MC_CMD_TCM_TXQ_INIT_EXT_IN msgrequest */ 11275 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_LEN 32 11276 /* the txq id */ 11277 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_QID_OFST 0 11278 /* the static priority associated with the txq */ 11279 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_NORMAL_OFST 4 11280 /* bitmask of the priority queues this txq is inserted into when inserted. */ 11281 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAGS_OFST 8 11282 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_GUARANTEED_LBN 0 11283 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_GUARANTEED_WIDTH 1 11284 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_NORMAL_LBN 1 11285 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_NORMAL_WIDTH 1 11286 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_LOW_LBN 2 11287 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_LOW_WIDTH 1 11288 /* the reaction point (RP) bucket */ 11289 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_RP_BKT_OFST 12 11290 /* an already reserved bucket (typically set to bucket associated with outer 11291 * vswitch) 11292 */ 11293 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT1_OFST 16 11294 /* an already reserved bucket (typically set to bucket associated with inner 11295 * vswitch) 11296 */ 11297 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT2_OFST 20 11298 /* the min bucket (typically for ETS/minimum bandwidth) */ 11299 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MIN_BKT_OFST 24 11300 /* the static priority associated with the txq */ 11301 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_GUARANTEED_OFST 28 11302 11303 /* MC_CMD_TCM_TXQ_INIT_OUT msgresponse */ 11304 #define MC_CMD_TCM_TXQ_INIT_OUT_LEN 0 11305 11306 11307 /***********************************/ 11308 /* MC_CMD_LINK_PIOBUF 11309 * Link a push I/O buffer to a TxQ 11310 */ 11311 #define MC_CMD_LINK_PIOBUF 0x92 11312 #undef MC_CMD_0x92_PRIVILEGE_CTG 11313 11314 #define MC_CMD_0x92_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 11315 11316 /* MC_CMD_LINK_PIOBUF_IN msgrequest */ 11317 #define MC_CMD_LINK_PIOBUF_IN_LEN 8 11318 /* Handle for allocated push I/O buffer. */ 11319 #define MC_CMD_LINK_PIOBUF_IN_PIOBUF_HANDLE_OFST 0 11320 /* Function Local Instance (VI) number. */ 11321 #define MC_CMD_LINK_PIOBUF_IN_TXQ_INSTANCE_OFST 4 11322 11323 /* MC_CMD_LINK_PIOBUF_OUT msgresponse */ 11324 #define MC_CMD_LINK_PIOBUF_OUT_LEN 0 11325 11326 11327 /***********************************/ 11328 /* MC_CMD_UNLINK_PIOBUF 11329 * Unlink a push I/O buffer from a TxQ 11330 */ 11331 #define MC_CMD_UNLINK_PIOBUF 0x93 11332 #undef MC_CMD_0x93_PRIVILEGE_CTG 11333 11334 #define MC_CMD_0x93_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 11335 11336 /* MC_CMD_UNLINK_PIOBUF_IN msgrequest */ 11337 #define MC_CMD_UNLINK_PIOBUF_IN_LEN 4 11338 /* Function Local Instance (VI) number. */ 11339 #define MC_CMD_UNLINK_PIOBUF_IN_TXQ_INSTANCE_OFST 0 11340 11341 /* MC_CMD_UNLINK_PIOBUF_OUT msgresponse */ 11342 #define MC_CMD_UNLINK_PIOBUF_OUT_LEN 0 11343 11344 11345 /***********************************/ 11346 /* MC_CMD_VSWITCH_ALLOC 11347 * allocate and initialise a v-switch. 11348 */ 11349 #define MC_CMD_VSWITCH_ALLOC 0x94 11350 #undef MC_CMD_0x94_PRIVILEGE_CTG 11351 11352 #define MC_CMD_0x94_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11353 11354 /* MC_CMD_VSWITCH_ALLOC_IN msgrequest */ 11355 #define MC_CMD_VSWITCH_ALLOC_IN_LEN 16 11356 /* The port to connect to the v-switch's upstream port. */ 11357 #define MC_CMD_VSWITCH_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 11358 /* The type of v-switch to create. */ 11359 #define MC_CMD_VSWITCH_ALLOC_IN_TYPE_OFST 4 11360 /* enum: VLAN */ 11361 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VLAN 0x1 11362 /* enum: VEB */ 11363 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEB 0x2 11364 /* enum: VEPA (obsolete) */ 11365 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEPA 0x3 11366 /* enum: MUX */ 11367 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_MUX 0x4 11368 /* enum: Snapper specific; semantics TBD */ 11369 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_TEST 0x5 11370 /* Flags controlling v-port creation */ 11371 #define MC_CMD_VSWITCH_ALLOC_IN_FLAGS_OFST 8 11372 #define MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_LBN 0 11373 #define MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_WIDTH 1 11374 /* The number of VLAN tags to allow for attached v-ports. For VLAN aggregators, 11375 * this must be one or greated, and the attached v-ports must have exactly this 11376 * number of tags. For other v-switch types, this must be zero of greater, and 11377 * is an upper limit on the number of VLAN tags for attached v-ports. An error 11378 * will be returned if existing configuration means we can't support attached 11379 * v-ports with this number of tags. 11380 */ 11381 #define MC_CMD_VSWITCH_ALLOC_IN_NUM_VLAN_TAGS_OFST 12 11382 11383 /* MC_CMD_VSWITCH_ALLOC_OUT msgresponse */ 11384 #define MC_CMD_VSWITCH_ALLOC_OUT_LEN 0 11385 11386 11387 /***********************************/ 11388 /* MC_CMD_VSWITCH_FREE 11389 * de-allocate a v-switch. 11390 */ 11391 #define MC_CMD_VSWITCH_FREE 0x95 11392 #undef MC_CMD_0x95_PRIVILEGE_CTG 11393 11394 #define MC_CMD_0x95_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11395 11396 /* MC_CMD_VSWITCH_FREE_IN msgrequest */ 11397 #define MC_CMD_VSWITCH_FREE_IN_LEN 4 11398 /* The port to which the v-switch is connected. */ 11399 #define MC_CMD_VSWITCH_FREE_IN_UPSTREAM_PORT_ID_OFST 0 11400 11401 /* MC_CMD_VSWITCH_FREE_OUT msgresponse */ 11402 #define MC_CMD_VSWITCH_FREE_OUT_LEN 0 11403 11404 11405 /***********************************/ 11406 /* MC_CMD_VSWITCH_QUERY 11407 * read some config of v-switch. For now this command is an empty placeholder. 11408 * It may be used to check if a v-switch is connected to a given EVB port (if 11409 * not, then the command returns ENOENT). 11410 */ 11411 #define MC_CMD_VSWITCH_QUERY 0x63 11412 #undef MC_CMD_0x63_PRIVILEGE_CTG 11413 11414 #define MC_CMD_0x63_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11415 11416 /* MC_CMD_VSWITCH_QUERY_IN msgrequest */ 11417 #define MC_CMD_VSWITCH_QUERY_IN_LEN 4 11418 /* The port to which the v-switch is connected. */ 11419 #define MC_CMD_VSWITCH_QUERY_IN_UPSTREAM_PORT_ID_OFST 0 11420 11421 /* MC_CMD_VSWITCH_QUERY_OUT msgresponse */ 11422 #define MC_CMD_VSWITCH_QUERY_OUT_LEN 0 11423 11424 11425 /***********************************/ 11426 /* MC_CMD_VPORT_ALLOC 11427 * allocate a v-port. 11428 */ 11429 #define MC_CMD_VPORT_ALLOC 0x96 11430 #undef MC_CMD_0x96_PRIVILEGE_CTG 11431 11432 #define MC_CMD_0x96_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11433 11434 /* MC_CMD_VPORT_ALLOC_IN msgrequest */ 11435 #define MC_CMD_VPORT_ALLOC_IN_LEN 20 11436 /* The port to which the v-switch is connected. */ 11437 #define MC_CMD_VPORT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 11438 /* The type of the new v-port. */ 11439 #define MC_CMD_VPORT_ALLOC_IN_TYPE_OFST 4 11440 /* enum: VLAN (obsolete) */ 11441 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VLAN 0x1 11442 /* enum: VEB (obsolete) */ 11443 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEB 0x2 11444 /* enum: VEPA (obsolete) */ 11445 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEPA 0x3 11446 /* enum: A normal v-port receives packets which match a specified MAC and/or 11447 * VLAN. 11448 */ 11449 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_NORMAL 0x4 11450 /* enum: An expansion v-port packets traffic which don't match any other 11451 * v-port. 11452 */ 11453 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_EXPANSION 0x5 11454 /* enum: An test v-port receives packets which match any filters installed by 11455 * its downstream components. 11456 */ 11457 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_TEST 0x6 11458 /* Flags controlling v-port creation */ 11459 #define MC_CMD_VPORT_ALLOC_IN_FLAGS_OFST 8 11460 #define MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_LBN 0 11461 #define MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_WIDTH 1 11462 #define MC_CMD_VPORT_ALLOC_IN_FLAG_VLAN_RESTRICT_LBN 1 11463 #define MC_CMD_VPORT_ALLOC_IN_FLAG_VLAN_RESTRICT_WIDTH 1 11464 /* The number of VLAN tags to insert/remove. An error will be returned if 11465 * incompatible with the number of VLAN tags specified for the upstream 11466 * v-switch. 11467 */ 11468 #define MC_CMD_VPORT_ALLOC_IN_NUM_VLAN_TAGS_OFST 12 11469 /* The actual VLAN tags to insert/remove */ 11470 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAGS_OFST 16 11471 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_LBN 0 11472 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_WIDTH 16 11473 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_LBN 16 11474 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_WIDTH 16 11475 11476 /* MC_CMD_VPORT_ALLOC_OUT msgresponse */ 11477 #define MC_CMD_VPORT_ALLOC_OUT_LEN 4 11478 /* The handle of the new v-port */ 11479 #define MC_CMD_VPORT_ALLOC_OUT_VPORT_ID_OFST 0 11480 11481 11482 /***********************************/ 11483 /* MC_CMD_VPORT_FREE 11484 * de-allocate a v-port. 11485 */ 11486 #define MC_CMD_VPORT_FREE 0x97 11487 #undef MC_CMD_0x97_PRIVILEGE_CTG 11488 11489 #define MC_CMD_0x97_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11490 11491 /* MC_CMD_VPORT_FREE_IN msgrequest */ 11492 #define MC_CMD_VPORT_FREE_IN_LEN 4 11493 /* The handle of the v-port */ 11494 #define MC_CMD_VPORT_FREE_IN_VPORT_ID_OFST 0 11495 11496 /* MC_CMD_VPORT_FREE_OUT msgresponse */ 11497 #define MC_CMD_VPORT_FREE_OUT_LEN 0 11498 11499 11500 /***********************************/ 11501 /* MC_CMD_VADAPTOR_ALLOC 11502 * allocate a v-adaptor. 11503 */ 11504 #define MC_CMD_VADAPTOR_ALLOC 0x98 11505 #undef MC_CMD_0x98_PRIVILEGE_CTG 11506 11507 #define MC_CMD_0x98_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11508 11509 /* MC_CMD_VADAPTOR_ALLOC_IN msgrequest */ 11510 #define MC_CMD_VADAPTOR_ALLOC_IN_LEN 30 11511 /* The port to connect to the v-adaptor's port. */ 11512 #define MC_CMD_VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 11513 /* Flags controlling v-adaptor creation */ 11514 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAGS_OFST 8 11515 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_LBN 0 11516 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_WIDTH 1 11517 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 1 11518 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1 11519 /* The number of VLAN tags to strip on receive */ 11520 #define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLANS_OFST 12 11521 /* The number of VLAN tags to transparently insert/remove. */ 11522 #define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLAN_TAGS_OFST 16 11523 /* The actual VLAN tags to insert/remove */ 11524 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAGS_OFST 20 11525 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_0_LBN 0 11526 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_0_WIDTH 16 11527 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_1_LBN 16 11528 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_1_WIDTH 16 11529 /* The MAC address to assign to this v-adaptor */ 11530 #define MC_CMD_VADAPTOR_ALLOC_IN_MACADDR_OFST 24 11531 #define MC_CMD_VADAPTOR_ALLOC_IN_MACADDR_LEN 6 11532 /* enum: Derive the MAC address from the upstream port */ 11533 #define MC_CMD_VADAPTOR_ALLOC_IN_AUTO_MAC 0x0 11534 11535 /* MC_CMD_VADAPTOR_ALLOC_OUT msgresponse */ 11536 #define MC_CMD_VADAPTOR_ALLOC_OUT_LEN 0 11537 11538 11539 /***********************************/ 11540 /* MC_CMD_VADAPTOR_FREE 11541 * de-allocate a v-adaptor. 11542 */ 11543 #define MC_CMD_VADAPTOR_FREE 0x99 11544 #undef MC_CMD_0x99_PRIVILEGE_CTG 11545 11546 #define MC_CMD_0x99_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11547 11548 /* MC_CMD_VADAPTOR_FREE_IN msgrequest */ 11549 #define MC_CMD_VADAPTOR_FREE_IN_LEN 4 11550 /* The port to which the v-adaptor is connected. */ 11551 #define MC_CMD_VADAPTOR_FREE_IN_UPSTREAM_PORT_ID_OFST 0 11552 11553 /* MC_CMD_VADAPTOR_FREE_OUT msgresponse */ 11554 #define MC_CMD_VADAPTOR_FREE_OUT_LEN 0 11555 11556 11557 /***********************************/ 11558 /* MC_CMD_VADAPTOR_SET_MAC 11559 * assign a new MAC address to a v-adaptor. 11560 */ 11561 #define MC_CMD_VADAPTOR_SET_MAC 0x5d 11562 #undef MC_CMD_0x5d_PRIVILEGE_CTG 11563 11564 #define MC_CMD_0x5d_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11565 11566 /* MC_CMD_VADAPTOR_SET_MAC_IN msgrequest */ 11567 #define MC_CMD_VADAPTOR_SET_MAC_IN_LEN 10 11568 /* The port to which the v-adaptor is connected. */ 11569 #define MC_CMD_VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID_OFST 0 11570 /* The new MAC address to assign to this v-adaptor */ 11571 #define MC_CMD_VADAPTOR_SET_MAC_IN_MACADDR_OFST 4 11572 #define MC_CMD_VADAPTOR_SET_MAC_IN_MACADDR_LEN 6 11573 11574 /* MC_CMD_VADAPTOR_SET_MAC_OUT msgresponse */ 11575 #define MC_CMD_VADAPTOR_SET_MAC_OUT_LEN 0 11576 11577 11578 /***********************************/ 11579 /* MC_CMD_VADAPTOR_GET_MAC 11580 * read the MAC address assigned to a v-adaptor. 11581 */ 11582 #define MC_CMD_VADAPTOR_GET_MAC 0x5e 11583 #undef MC_CMD_0x5e_PRIVILEGE_CTG 11584 11585 #define MC_CMD_0x5e_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11586 11587 /* MC_CMD_VADAPTOR_GET_MAC_IN msgrequest */ 11588 #define MC_CMD_VADAPTOR_GET_MAC_IN_LEN 4 11589 /* The port to which the v-adaptor is connected. */ 11590 #define MC_CMD_VADAPTOR_GET_MAC_IN_UPSTREAM_PORT_ID_OFST 0 11591 11592 /* MC_CMD_VADAPTOR_GET_MAC_OUT msgresponse */ 11593 #define MC_CMD_VADAPTOR_GET_MAC_OUT_LEN 6 11594 /* The MAC address assigned to this v-adaptor */ 11595 #define MC_CMD_VADAPTOR_GET_MAC_OUT_MACADDR_OFST 0 11596 #define MC_CMD_VADAPTOR_GET_MAC_OUT_MACADDR_LEN 6 11597 11598 11599 /***********************************/ 11600 /* MC_CMD_VADAPTOR_QUERY 11601 * read some config of v-adaptor. 11602 */ 11603 #define MC_CMD_VADAPTOR_QUERY 0x61 11604 #undef MC_CMD_0x61_PRIVILEGE_CTG 11605 11606 #define MC_CMD_0x61_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11607 11608 /* MC_CMD_VADAPTOR_QUERY_IN msgrequest */ 11609 #define MC_CMD_VADAPTOR_QUERY_IN_LEN 4 11610 /* The port to which the v-adaptor is connected. */ 11611 #define MC_CMD_VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID_OFST 0 11612 11613 /* MC_CMD_VADAPTOR_QUERY_OUT msgresponse */ 11614 #define MC_CMD_VADAPTOR_QUERY_OUT_LEN 12 11615 /* The EVB port flags as defined at MC_CMD_VPORT_ALLOC. */ 11616 #define MC_CMD_VADAPTOR_QUERY_OUT_PORT_FLAGS_OFST 0 11617 /* The v-adaptor flags as defined at MC_CMD_VADAPTOR_ALLOC. */ 11618 #define MC_CMD_VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS_OFST 4 11619 /* The number of VLAN tags that may still be added */ 11620 #define MC_CMD_VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_OFST 8 11621 11622 11623 /***********************************/ 11624 /* MC_CMD_EVB_PORT_ASSIGN 11625 * assign a port to a PCI function. 11626 */ 11627 #define MC_CMD_EVB_PORT_ASSIGN 0x9a 11628 #undef MC_CMD_0x9a_PRIVILEGE_CTG 11629 11630 #define MC_CMD_0x9a_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11631 11632 /* MC_CMD_EVB_PORT_ASSIGN_IN msgrequest */ 11633 #define MC_CMD_EVB_PORT_ASSIGN_IN_LEN 8 11634 /* The port to assign. */ 11635 #define MC_CMD_EVB_PORT_ASSIGN_IN_PORT_ID_OFST 0 11636 /* The target function to modify. */ 11637 #define MC_CMD_EVB_PORT_ASSIGN_IN_FUNCTION_OFST 4 11638 #define MC_CMD_EVB_PORT_ASSIGN_IN_PF_LBN 0 11639 #define MC_CMD_EVB_PORT_ASSIGN_IN_PF_WIDTH 16 11640 #define MC_CMD_EVB_PORT_ASSIGN_IN_VF_LBN 16 11641 #define MC_CMD_EVB_PORT_ASSIGN_IN_VF_WIDTH 16 11642 11643 /* MC_CMD_EVB_PORT_ASSIGN_OUT msgresponse */ 11644 #define MC_CMD_EVB_PORT_ASSIGN_OUT_LEN 0 11645 11646 11647 /***********************************/ 11648 /* MC_CMD_RDWR_A64_REGIONS 11649 * Assign the 64 bit region addresses. 11650 */ 11651 #define MC_CMD_RDWR_A64_REGIONS 0x9b 11652 #undef MC_CMD_0x9b_PRIVILEGE_CTG 11653 11654 #define MC_CMD_0x9b_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11655 11656 /* MC_CMD_RDWR_A64_REGIONS_IN msgrequest */ 11657 #define MC_CMD_RDWR_A64_REGIONS_IN_LEN 17 11658 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION0_OFST 0 11659 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION1_OFST 4 11660 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION2_OFST 8 11661 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION3_OFST 12 11662 /* Write enable bits 0-3, set to write, clear to read. */ 11663 #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_LBN 128 11664 #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_WIDTH 4 11665 #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_BYTE_OFST 16 11666 #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_BYTE_LEN 1 11667 11668 /* MC_CMD_RDWR_A64_REGIONS_OUT msgresponse: This data always included 11669 * regardless of state of write bits in the request. 11670 */ 11671 #define MC_CMD_RDWR_A64_REGIONS_OUT_LEN 16 11672 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION0_OFST 0 11673 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION1_OFST 4 11674 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION2_OFST 8 11675 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION3_OFST 12 11676 11677 11678 /***********************************/ 11679 /* MC_CMD_ONLOAD_STACK_ALLOC 11680 * Allocate an Onload stack ID. 11681 */ 11682 #define MC_CMD_ONLOAD_STACK_ALLOC 0x9c 11683 #undef MC_CMD_0x9c_PRIVILEGE_CTG 11684 11685 #define MC_CMD_0x9c_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 11686 11687 /* MC_CMD_ONLOAD_STACK_ALLOC_IN msgrequest */ 11688 #define MC_CMD_ONLOAD_STACK_ALLOC_IN_LEN 4 11689 /* The handle of the owning upstream port */ 11690 #define MC_CMD_ONLOAD_STACK_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 11691 11692 /* MC_CMD_ONLOAD_STACK_ALLOC_OUT msgresponse */ 11693 #define MC_CMD_ONLOAD_STACK_ALLOC_OUT_LEN 4 11694 /* The handle of the new Onload stack */ 11695 #define MC_CMD_ONLOAD_STACK_ALLOC_OUT_ONLOAD_STACK_ID_OFST 0 11696 11697 11698 /***********************************/ 11699 /* MC_CMD_ONLOAD_STACK_FREE 11700 * Free an Onload stack ID. 11701 */ 11702 #define MC_CMD_ONLOAD_STACK_FREE 0x9d 11703 #undef MC_CMD_0x9d_PRIVILEGE_CTG 11704 11705 #define MC_CMD_0x9d_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 11706 11707 /* MC_CMD_ONLOAD_STACK_FREE_IN msgrequest */ 11708 #define MC_CMD_ONLOAD_STACK_FREE_IN_LEN 4 11709 /* The handle of the Onload stack */ 11710 #define MC_CMD_ONLOAD_STACK_FREE_IN_ONLOAD_STACK_ID_OFST 0 11711 11712 /* MC_CMD_ONLOAD_STACK_FREE_OUT msgresponse */ 11713 #define MC_CMD_ONLOAD_STACK_FREE_OUT_LEN 0 11714 11715 11716 /***********************************/ 11717 /* MC_CMD_RSS_CONTEXT_ALLOC 11718 * Allocate an RSS context. 11719 */ 11720 #define MC_CMD_RSS_CONTEXT_ALLOC 0x9e 11721 #undef MC_CMD_0x9e_PRIVILEGE_CTG 11722 11723 #define MC_CMD_0x9e_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11724 11725 /* MC_CMD_RSS_CONTEXT_ALLOC_IN msgrequest */ 11726 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN 12 11727 /* The handle of the owning upstream port */ 11728 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 11729 /* The type of context to allocate */ 11730 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_OFST 4 11731 /* enum: Allocate a context for exclusive use. The key and indirection table 11732 * must be explicitly configured. 11733 */ 11734 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE 0x0 11735 /* enum: Allocate a context for shared use; this will spread across a range of 11736 * queues, but the key and indirection table are pre-configured and may not be 11737 * changed. For this mode, NUM_QUEUES must 2, 4, 8, 16, 32 or 64. 11738 */ 11739 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED 0x1 11740 /* Number of queues spanned by this context, in the range 1-64; valid offsets 11741 * in the indirection table will be in the range 0 to NUM_QUEUES-1. 11742 */ 11743 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_NUM_QUEUES_OFST 8 11744 11745 /* MC_CMD_RSS_CONTEXT_ALLOC_OUT msgresponse */ 11746 #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN 4 11747 /* The handle of the new RSS context. This should be considered opaque to the 11748 * host, although a value of 0xFFFFFFFF is guaranteed never to be a valid 11749 * handle. 11750 */ 11751 #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_OFST 0 11752 /* enum: guaranteed invalid RSS context handle value */ 11753 #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_INVALID 0xffffffff 11754 11755 11756 /***********************************/ 11757 /* MC_CMD_RSS_CONTEXT_FREE 11758 * Free an RSS context. 11759 */ 11760 #define MC_CMD_RSS_CONTEXT_FREE 0x9f 11761 #undef MC_CMD_0x9f_PRIVILEGE_CTG 11762 11763 #define MC_CMD_0x9f_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11764 11765 /* MC_CMD_RSS_CONTEXT_FREE_IN msgrequest */ 11766 #define MC_CMD_RSS_CONTEXT_FREE_IN_LEN 4 11767 /* The handle of the RSS context */ 11768 #define MC_CMD_RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID_OFST 0 11769 11770 /* MC_CMD_RSS_CONTEXT_FREE_OUT msgresponse */ 11771 #define MC_CMD_RSS_CONTEXT_FREE_OUT_LEN 0 11772 11773 11774 /***********************************/ 11775 /* MC_CMD_RSS_CONTEXT_SET_KEY 11776 * Set the Toeplitz hash key for an RSS context. 11777 */ 11778 #define MC_CMD_RSS_CONTEXT_SET_KEY 0xa0 11779 #undef MC_CMD_0xa0_PRIVILEGE_CTG 11780 11781 #define MC_CMD_0xa0_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11782 11783 /* MC_CMD_RSS_CONTEXT_SET_KEY_IN msgrequest */ 11784 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN 44 11785 /* The handle of the RSS context */ 11786 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID_OFST 0 11787 /* The 40-byte Toeplitz hash key (TBD endianness issues?) */ 11788 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_OFST 4 11789 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN 40 11790 11791 /* MC_CMD_RSS_CONTEXT_SET_KEY_OUT msgresponse */ 11792 #define MC_CMD_RSS_CONTEXT_SET_KEY_OUT_LEN 0 11793 11794 11795 /***********************************/ 11796 /* MC_CMD_RSS_CONTEXT_GET_KEY 11797 * Get the Toeplitz hash key for an RSS context. 11798 */ 11799 #define MC_CMD_RSS_CONTEXT_GET_KEY 0xa1 11800 #undef MC_CMD_0xa1_PRIVILEGE_CTG 11801 11802 #define MC_CMD_0xa1_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11803 11804 /* MC_CMD_RSS_CONTEXT_GET_KEY_IN msgrequest */ 11805 #define MC_CMD_RSS_CONTEXT_GET_KEY_IN_LEN 4 11806 /* The handle of the RSS context */ 11807 #define MC_CMD_RSS_CONTEXT_GET_KEY_IN_RSS_CONTEXT_ID_OFST 0 11808 11809 /* MC_CMD_RSS_CONTEXT_GET_KEY_OUT msgresponse */ 11810 #define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_LEN 44 11811 /* The 40-byte Toeplitz hash key (TBD endianness issues?) */ 11812 #define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY_OFST 4 11813 #define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY_LEN 40 11814 11815 11816 /***********************************/ 11817 /* MC_CMD_RSS_CONTEXT_SET_TABLE 11818 * Set the indirection table for an RSS context. 11819 */ 11820 #define MC_CMD_RSS_CONTEXT_SET_TABLE 0xa2 11821 #undef MC_CMD_0xa2_PRIVILEGE_CTG 11822 11823 #define MC_CMD_0xa2_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11824 11825 /* MC_CMD_RSS_CONTEXT_SET_TABLE_IN msgrequest */ 11826 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN 132 11827 /* The handle of the RSS context */ 11828 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID_OFST 0 11829 /* The 128-byte indirection table (1 byte per entry) */ 11830 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_OFST 4 11831 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN 128 11832 11833 /* MC_CMD_RSS_CONTEXT_SET_TABLE_OUT msgresponse */ 11834 #define MC_CMD_RSS_CONTEXT_SET_TABLE_OUT_LEN 0 11835 11836 11837 /***********************************/ 11838 /* MC_CMD_RSS_CONTEXT_GET_TABLE 11839 * Get the indirection table for an RSS context. 11840 */ 11841 #define MC_CMD_RSS_CONTEXT_GET_TABLE 0xa3 11842 #undef MC_CMD_0xa3_PRIVILEGE_CTG 11843 11844 #define MC_CMD_0xa3_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11845 11846 /* MC_CMD_RSS_CONTEXT_GET_TABLE_IN msgrequest */ 11847 #define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_LEN 4 11848 /* The handle of the RSS context */ 11849 #define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_RSS_CONTEXT_ID_OFST 0 11850 11851 /* MC_CMD_RSS_CONTEXT_GET_TABLE_OUT msgresponse */ 11852 #define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_LEN 132 11853 /* The 128-byte indirection table (1 byte per entry) */ 11854 #define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_OFST 4 11855 #define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_LEN 128 11856 11857 11858 /***********************************/ 11859 /* MC_CMD_RSS_CONTEXT_SET_FLAGS 11860 * Set various control flags for an RSS context. 11861 */ 11862 #define MC_CMD_RSS_CONTEXT_SET_FLAGS 0xe1 11863 #undef MC_CMD_0xe1_PRIVILEGE_CTG 11864 11865 #define MC_CMD_0xe1_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11866 11867 /* MC_CMD_RSS_CONTEXT_SET_FLAGS_IN msgrequest */ 11868 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_LEN 8 11869 /* The handle of the RSS context */ 11870 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID_OFST 0 11871 /* Hash control flags. The _EN bits are always supported, but new modes are 11872 * available when ADDITIONAL_RSS_MODES is reported by MC_CMD_GET_CAPABILITIES: 11873 * in this case, the MODE fields may be set to non-zero values, and will take 11874 * effect regardless of the settings of the _EN flags. See the RSS_MODE 11875 * structure for the meaning of the mode bits. Drivers must check the 11876 * capability before trying to set any _MODE fields, as older firmware will 11877 * reject any attempt to set the FLAGS field to a value > 0xff with EINVAL. In 11878 * the case where all the _MODE flags are zero, the _EN flags take effect, 11879 * providing backward compatibility for existing drivers. (Setting all _MODE 11880 * *and* all _EN flags to zero is valid, to disable RSS spreading for that 11881 * particular packet type.) 11882 */ 11883 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_FLAGS_OFST 4 11884 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_LBN 0 11885 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_WIDTH 1 11886 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_LBN 1 11887 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_WIDTH 1 11888 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_LBN 2 11889 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_WIDTH 1 11890 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_LBN 3 11891 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_WIDTH 1 11892 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_LBN 4 11893 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_WIDTH 4 11894 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_LBN 8 11895 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_WIDTH 4 11896 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE_LBN 12 11897 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE_WIDTH 4 11898 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_LBN 16 11899 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_WIDTH 4 11900 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_LBN 20 11901 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_WIDTH 4 11902 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE_LBN 24 11903 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE_WIDTH 4 11904 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_LBN 28 11905 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_WIDTH 4 11906 11907 /* MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT msgresponse */ 11908 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT_LEN 0 11909 11910 11911 /***********************************/ 11912 /* MC_CMD_RSS_CONTEXT_GET_FLAGS 11913 * Get various control flags for an RSS context. 11914 */ 11915 #define MC_CMD_RSS_CONTEXT_GET_FLAGS 0xe2 11916 #undef MC_CMD_0xe2_PRIVILEGE_CTG 11917 11918 #define MC_CMD_0xe2_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11919 11920 /* MC_CMD_RSS_CONTEXT_GET_FLAGS_IN msgrequest */ 11921 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_LEN 4 11922 /* The handle of the RSS context */ 11923 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_RSS_CONTEXT_ID_OFST 0 11924 11925 /* MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT msgresponse */ 11926 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN 8 11927 /* Hash control flags. If all _MODE bits are zero (which will always be true 11928 * for older firmware which does not report the ADDITIONAL_RSS_MODES 11929 * capability), the _EN bits report the state. If any _MODE bits are non-zero 11930 * (which will only be true when the firmware reports ADDITIONAL_RSS_MODES) 11931 * then the _EN bits should be disregarded, although the _MODE flags are 11932 * guaranteed to be consistent with the _EN flags for a freshly-allocated RSS 11933 * context and in the case where the _EN flags were used in the SET. This 11934 * provides backward compatibility: old drivers will not be attempting to 11935 * derive any meaning from the _MODE bits (and can never set them to any value 11936 * not representable by the _EN bits); new drivers can always determine the 11937 * mode by looking only at the _MODE bits; the value returned by a GET can 11938 * always be used for a SET regardless of old/new driver vs. old/new firmware. 11939 */ 11940 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_OFST 4 11941 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_LBN 0 11942 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_WIDTH 1 11943 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_LBN 1 11944 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_WIDTH 1 11945 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_LBN 2 11946 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_WIDTH 1 11947 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_LBN 3 11948 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_WIDTH 1 11949 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_LBN 4 11950 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_WIDTH 4 11951 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_LBN 8 11952 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_WIDTH 4 11953 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_LBN 12 11954 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_WIDTH 4 11955 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_LBN 16 11956 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_WIDTH 4 11957 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_LBN 20 11958 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_WIDTH 4 11959 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_LBN 24 11960 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_WIDTH 4 11961 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_LBN 28 11962 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_WIDTH 4 11963 11964 11965 /***********************************/ 11966 /* MC_CMD_DOT1P_MAPPING_ALLOC 11967 * Allocate a .1p mapping. 11968 */ 11969 #define MC_CMD_DOT1P_MAPPING_ALLOC 0xa4 11970 #undef MC_CMD_0xa4_PRIVILEGE_CTG 11971 11972 #define MC_CMD_0xa4_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11973 11974 /* MC_CMD_DOT1P_MAPPING_ALLOC_IN msgrequest */ 11975 #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_LEN 8 11976 /* The handle of the owning upstream port */ 11977 #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 11978 /* Number of queues spanned by this mapping, in the range 1-64; valid fixed 11979 * offsets in the mapping table will be in the range 0 to NUM_QUEUES-1, and 11980 * referenced RSS contexts must span no more than this number. 11981 */ 11982 #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_NUM_QUEUES_OFST 4 11983 11984 /* MC_CMD_DOT1P_MAPPING_ALLOC_OUT msgresponse */ 11985 #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_LEN 4 11986 /* The handle of the new .1p mapping. This should be considered opaque to the 11987 * host, although a value of 0xFFFFFFFF is guaranteed never to be a valid 11988 * handle. 11989 */ 11990 #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_OFST 0 11991 /* enum: guaranteed invalid .1p mapping handle value */ 11992 #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_INVALID 0xffffffff 11993 11994 11995 /***********************************/ 11996 /* MC_CMD_DOT1P_MAPPING_FREE 11997 * Free a .1p mapping. 11998 */ 11999 #define MC_CMD_DOT1P_MAPPING_FREE 0xa5 12000 #undef MC_CMD_0xa5_PRIVILEGE_CTG 12001 12002 #define MC_CMD_0xa5_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12003 12004 /* MC_CMD_DOT1P_MAPPING_FREE_IN msgrequest */ 12005 #define MC_CMD_DOT1P_MAPPING_FREE_IN_LEN 4 12006 /* The handle of the .1p mapping */ 12007 #define MC_CMD_DOT1P_MAPPING_FREE_IN_DOT1P_MAPPING_ID_OFST 0 12008 12009 /* MC_CMD_DOT1P_MAPPING_FREE_OUT msgresponse */ 12010 #define MC_CMD_DOT1P_MAPPING_FREE_OUT_LEN 0 12011 12012 12013 /***********************************/ 12014 /* MC_CMD_DOT1P_MAPPING_SET_TABLE 12015 * Set the mapping table for a .1p mapping. 12016 */ 12017 #define MC_CMD_DOT1P_MAPPING_SET_TABLE 0xa6 12018 #undef MC_CMD_0xa6_PRIVILEGE_CTG 12019 12020 #define MC_CMD_0xa6_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12021 12022 /* MC_CMD_DOT1P_MAPPING_SET_TABLE_IN msgrequest */ 12023 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_LEN 36 12024 /* The handle of the .1p mapping */ 12025 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_DOT1P_MAPPING_ID_OFST 0 12026 /* Per-priority mappings (1 32-bit word per entry - an offset or RSS context 12027 * handle) 12028 */ 12029 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_MAPPING_TABLE_OFST 4 12030 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_MAPPING_TABLE_LEN 32 12031 12032 /* MC_CMD_DOT1P_MAPPING_SET_TABLE_OUT msgresponse */ 12033 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_OUT_LEN 0 12034 12035 12036 /***********************************/ 12037 /* MC_CMD_DOT1P_MAPPING_GET_TABLE 12038 * Get the mapping table for a .1p mapping. 12039 */ 12040 #define MC_CMD_DOT1P_MAPPING_GET_TABLE 0xa7 12041 #undef MC_CMD_0xa7_PRIVILEGE_CTG 12042 12043 #define MC_CMD_0xa7_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12044 12045 /* MC_CMD_DOT1P_MAPPING_GET_TABLE_IN msgrequest */ 12046 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_IN_LEN 4 12047 /* The handle of the .1p mapping */ 12048 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_IN_DOT1P_MAPPING_ID_OFST 0 12049 12050 /* MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT msgresponse */ 12051 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_LEN 36 12052 /* Per-priority mappings (1 32-bit word per entry - an offset or RSS context 12053 * handle) 12054 */ 12055 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_MAPPING_TABLE_OFST 4 12056 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_MAPPING_TABLE_LEN 32 12057 12058 12059 /***********************************/ 12060 /* MC_CMD_GET_VECTOR_CFG 12061 * Get Interrupt Vector config for this PF. 12062 */ 12063 #define MC_CMD_GET_VECTOR_CFG 0xbf 12064 #undef MC_CMD_0xbf_PRIVILEGE_CTG 12065 12066 #define MC_CMD_0xbf_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12067 12068 /* MC_CMD_GET_VECTOR_CFG_IN msgrequest */ 12069 #define MC_CMD_GET_VECTOR_CFG_IN_LEN 0 12070 12071 /* MC_CMD_GET_VECTOR_CFG_OUT msgresponse */ 12072 #define MC_CMD_GET_VECTOR_CFG_OUT_LEN 12 12073 /* Base absolute interrupt vector number. */ 12074 #define MC_CMD_GET_VECTOR_CFG_OUT_VEC_BASE_OFST 0 12075 /* Number of interrupt vectors allocate to this PF. */ 12076 #define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_PF_OFST 4 12077 /* Number of interrupt vectors to allocate per VF. */ 12078 #define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_VF_OFST 8 12079 12080 12081 /***********************************/ 12082 /* MC_CMD_SET_VECTOR_CFG 12083 * Set Interrupt Vector config for this PF. 12084 */ 12085 #define MC_CMD_SET_VECTOR_CFG 0xc0 12086 #undef MC_CMD_0xc0_PRIVILEGE_CTG 12087 12088 #define MC_CMD_0xc0_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12089 12090 /* MC_CMD_SET_VECTOR_CFG_IN msgrequest */ 12091 #define MC_CMD_SET_VECTOR_CFG_IN_LEN 12 12092 /* Base absolute interrupt vector number, or MC_CMD_RESOURCE_INSTANCE_ANY to 12093 * let the system find a suitable base. 12094 */ 12095 #define MC_CMD_SET_VECTOR_CFG_IN_VEC_BASE_OFST 0 12096 /* Number of interrupt vectors allocate to this PF. */ 12097 #define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_PF_OFST 4 12098 /* Number of interrupt vectors to allocate per VF. */ 12099 #define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_VF_OFST 8 12100 12101 /* MC_CMD_SET_VECTOR_CFG_OUT msgresponse */ 12102 #define MC_CMD_SET_VECTOR_CFG_OUT_LEN 0 12103 12104 12105 /***********************************/ 12106 /* MC_CMD_VPORT_ADD_MAC_ADDRESS 12107 * Add a MAC address to a v-port 12108 */ 12109 #define MC_CMD_VPORT_ADD_MAC_ADDRESS 0xa8 12110 #undef MC_CMD_0xa8_PRIVILEGE_CTG 12111 12112 #define MC_CMD_0xa8_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12113 12114 /* MC_CMD_VPORT_ADD_MAC_ADDRESS_IN msgrequest */ 12115 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN 10 12116 /* The handle of the v-port */ 12117 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID_OFST 0 12118 /* MAC address to add */ 12119 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_MACADDR_OFST 4 12120 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_MACADDR_LEN 6 12121 12122 /* MC_CMD_VPORT_ADD_MAC_ADDRESS_OUT msgresponse */ 12123 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_OUT_LEN 0 12124 12125 12126 /***********************************/ 12127 /* MC_CMD_VPORT_DEL_MAC_ADDRESS 12128 * Delete a MAC address from a v-port 12129 */ 12130 #define MC_CMD_VPORT_DEL_MAC_ADDRESS 0xa9 12131 #undef MC_CMD_0xa9_PRIVILEGE_CTG 12132 12133 #define MC_CMD_0xa9_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12134 12135 /* MC_CMD_VPORT_DEL_MAC_ADDRESS_IN msgrequest */ 12136 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN 10 12137 /* The handle of the v-port */ 12138 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID_OFST 0 12139 /* MAC address to add */ 12140 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_MACADDR_OFST 4 12141 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_MACADDR_LEN 6 12142 12143 /* MC_CMD_VPORT_DEL_MAC_ADDRESS_OUT msgresponse */ 12144 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_OUT_LEN 0 12145 12146 12147 /***********************************/ 12148 /* MC_CMD_VPORT_GET_MAC_ADDRESSES 12149 * Delete a MAC address from a v-port 12150 */ 12151 #define MC_CMD_VPORT_GET_MAC_ADDRESSES 0xaa 12152 #undef MC_CMD_0xaa_PRIVILEGE_CTG 12153 12154 #define MC_CMD_0xaa_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12155 12156 /* MC_CMD_VPORT_GET_MAC_ADDRESSES_IN msgrequest */ 12157 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN 4 12158 /* The handle of the v-port */ 12159 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID_OFST 0 12160 12161 /* MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT msgresponse */ 12162 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN 4 12163 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX 250 12164 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LEN(num) (4+6*(num)) 12165 /* The number of MAC addresses returned */ 12166 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT_OFST 0 12167 /* Array of MAC addresses */ 12168 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_OFST 4 12169 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_LEN 6 12170 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MINNUM 0 12171 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MAXNUM 41 12172 12173 12174 /***********************************/ 12175 /* MC_CMD_VPORT_RECONFIGURE 12176 * Replace VLAN tags and/or MAC addresses of an existing v-port. If the v-port 12177 * has already been passed to another function (v-port's user), then that 12178 * function will be reset before applying the changes. 12179 */ 12180 #define MC_CMD_VPORT_RECONFIGURE 0xeb 12181 #undef MC_CMD_0xeb_PRIVILEGE_CTG 12182 12183 #define MC_CMD_0xeb_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12184 12185 /* MC_CMD_VPORT_RECONFIGURE_IN msgrequest */ 12186 #define MC_CMD_VPORT_RECONFIGURE_IN_LEN 44 12187 /* The handle of the v-port */ 12188 #define MC_CMD_VPORT_RECONFIGURE_IN_VPORT_ID_OFST 0 12189 /* Flags requesting what should be changed. */ 12190 #define MC_CMD_VPORT_RECONFIGURE_IN_FLAGS_OFST 4 12191 #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_VLAN_TAGS_LBN 0 12192 #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_VLAN_TAGS_WIDTH 1 12193 #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_MACADDRS_LBN 1 12194 #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_MACADDRS_WIDTH 1 12195 /* The number of VLAN tags to insert/remove. An error will be returned if 12196 * incompatible with the number of VLAN tags specified for the upstream 12197 * v-switch. 12198 */ 12199 #define MC_CMD_VPORT_RECONFIGURE_IN_NUM_VLAN_TAGS_OFST 8 12200 /* The actual VLAN tags to insert/remove */ 12201 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAGS_OFST 12 12202 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_0_LBN 0 12203 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_0_WIDTH 16 12204 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_1_LBN 16 12205 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_1_WIDTH 16 12206 /* The number of MAC addresses to add */ 12207 #define MC_CMD_VPORT_RECONFIGURE_IN_NUM_MACADDRS_OFST 16 12208 /* MAC addresses to add */ 12209 #define MC_CMD_VPORT_RECONFIGURE_IN_MACADDRS_OFST 20 12210 #define MC_CMD_VPORT_RECONFIGURE_IN_MACADDRS_LEN 6 12211 #define MC_CMD_VPORT_RECONFIGURE_IN_MACADDRS_NUM 4 12212 12213 /* MC_CMD_VPORT_RECONFIGURE_OUT msgresponse */ 12214 #define MC_CMD_VPORT_RECONFIGURE_OUT_LEN 4 12215 #define MC_CMD_VPORT_RECONFIGURE_OUT_FLAGS_OFST 0 12216 #define MC_CMD_VPORT_RECONFIGURE_OUT_RESET_DONE_LBN 0 12217 #define MC_CMD_VPORT_RECONFIGURE_OUT_RESET_DONE_WIDTH 1 12218 12219 12220 /***********************************/ 12221 /* MC_CMD_EVB_PORT_QUERY 12222 * read some config of v-port. 12223 */ 12224 #define MC_CMD_EVB_PORT_QUERY 0x62 12225 #undef MC_CMD_0x62_PRIVILEGE_CTG 12226 12227 #define MC_CMD_0x62_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12228 12229 /* MC_CMD_EVB_PORT_QUERY_IN msgrequest */ 12230 #define MC_CMD_EVB_PORT_QUERY_IN_LEN 4 12231 /* The handle of the v-port */ 12232 #define MC_CMD_EVB_PORT_QUERY_IN_PORT_ID_OFST 0 12233 12234 /* MC_CMD_EVB_PORT_QUERY_OUT msgresponse */ 12235 #define MC_CMD_EVB_PORT_QUERY_OUT_LEN 8 12236 /* The EVB port flags as defined at MC_CMD_VPORT_ALLOC. */ 12237 #define MC_CMD_EVB_PORT_QUERY_OUT_PORT_FLAGS_OFST 0 12238 /* The number of VLAN tags that may be used on a v-adaptor connected to this 12239 * EVB port. 12240 */ 12241 #define MC_CMD_EVB_PORT_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_OFST 4 12242 12243 12244 /***********************************/ 12245 /* MC_CMD_DUMP_BUFTBL_ENTRIES 12246 * Dump buffer table entries, mainly for command client debug use. Dumps 12247 * absolute entries, and does not use chunk handles. All entries must be in 12248 * range, and used for q page mapping, Although the latter restriction may be 12249 * lifted in future. 12250 */ 12251 #define MC_CMD_DUMP_BUFTBL_ENTRIES 0xab 12252 #undef MC_CMD_0xab_PRIVILEGE_CTG 12253 12254 #define MC_CMD_0xab_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12255 12256 /* MC_CMD_DUMP_BUFTBL_ENTRIES_IN msgrequest */ 12257 #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_LEN 8 12258 /* Index of the first buffer table entry. */ 12259 #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_FIRSTID_OFST 0 12260 /* Number of buffer table entries to dump. */ 12261 #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_NUMENTRIES_OFST 4 12262 12263 /* MC_CMD_DUMP_BUFTBL_ENTRIES_OUT msgresponse */ 12264 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LENMIN 12 12265 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LENMAX 252 12266 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LEN(num) (0+12*(num)) 12267 /* Raw buffer table entries, layed out as BUFTBL_ENTRY. */ 12268 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_OFST 0 12269 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_LEN 12 12270 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_MINNUM 1 12271 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_MAXNUM 21 12272 12273 12274 /***********************************/ 12275 /* MC_CMD_SET_RXDP_CONFIG 12276 * Set global RXDP configuration settings 12277 */ 12278 #define MC_CMD_SET_RXDP_CONFIG 0xc1 12279 #undef MC_CMD_0xc1_PRIVILEGE_CTG 12280 12281 #define MC_CMD_0xc1_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12282 12283 /* MC_CMD_SET_RXDP_CONFIG_IN msgrequest */ 12284 #define MC_CMD_SET_RXDP_CONFIG_IN_LEN 4 12285 #define MC_CMD_SET_RXDP_CONFIG_IN_DATA_OFST 0 12286 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_LBN 0 12287 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_WIDTH 1 12288 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_LEN_LBN 1 12289 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_LEN_WIDTH 2 12290 /* enum: pad to 64 bytes */ 12291 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_64 0x0 12292 /* enum: pad to 128 bytes (Medford only) */ 12293 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_128 0x1 12294 /* enum: pad to 256 bytes (Medford only) */ 12295 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_256 0x2 12296 12297 /* MC_CMD_SET_RXDP_CONFIG_OUT msgresponse */ 12298 #define MC_CMD_SET_RXDP_CONFIG_OUT_LEN 0 12299 12300 12301 /***********************************/ 12302 /* MC_CMD_GET_RXDP_CONFIG 12303 * Get global RXDP configuration settings 12304 */ 12305 #define MC_CMD_GET_RXDP_CONFIG 0xc2 12306 #undef MC_CMD_0xc2_PRIVILEGE_CTG 12307 12308 #define MC_CMD_0xc2_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12309 12310 /* MC_CMD_GET_RXDP_CONFIG_IN msgrequest */ 12311 #define MC_CMD_GET_RXDP_CONFIG_IN_LEN 0 12312 12313 /* MC_CMD_GET_RXDP_CONFIG_OUT msgresponse */ 12314 #define MC_CMD_GET_RXDP_CONFIG_OUT_LEN 4 12315 #define MC_CMD_GET_RXDP_CONFIG_OUT_DATA_OFST 0 12316 #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_LBN 0 12317 #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_WIDTH 1 12318 #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_LEN_LBN 1 12319 #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_LEN_WIDTH 2 12320 /* Enum values, see field(s): */ 12321 /* MC_CMD_SET_RXDP_CONFIG/MC_CMD_SET_RXDP_CONFIG_IN/PAD_HOST_LEN */ 12322 12323 12324 /***********************************/ 12325 /* MC_CMD_GET_CLOCK 12326 * Return the system and PDCPU clock frequencies. 12327 */ 12328 #define MC_CMD_GET_CLOCK 0xac 12329 #undef MC_CMD_0xac_PRIVILEGE_CTG 12330 12331 #define MC_CMD_0xac_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12332 12333 /* MC_CMD_GET_CLOCK_IN msgrequest */ 12334 #define MC_CMD_GET_CLOCK_IN_LEN 0 12335 12336 /* MC_CMD_GET_CLOCK_OUT msgresponse */ 12337 #define MC_CMD_GET_CLOCK_OUT_LEN 8 12338 /* System frequency, MHz */ 12339 #define MC_CMD_GET_CLOCK_OUT_SYS_FREQ_OFST 0 12340 /* DPCPU frequency, MHz */ 12341 #define MC_CMD_GET_CLOCK_OUT_DPCPU_FREQ_OFST 4 12342 12343 12344 /***********************************/ 12345 /* MC_CMD_SET_CLOCK 12346 * Control the system and DPCPU clock frequencies. Changes are lost reboot. 12347 */ 12348 #define MC_CMD_SET_CLOCK 0xad 12349 #undef MC_CMD_0xad_PRIVILEGE_CTG 12350 12351 #define MC_CMD_0xad_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12352 12353 /* MC_CMD_SET_CLOCK_IN msgrequest */ 12354 #define MC_CMD_SET_CLOCK_IN_LEN 28 12355 /* Requested frequency in MHz for system clock domain */ 12356 #define MC_CMD_SET_CLOCK_IN_SYS_FREQ_OFST 0 12357 /* enum: Leave the system clock domain frequency unchanged */ 12358 #define MC_CMD_SET_CLOCK_IN_SYS_DOMAIN_DONT_CHANGE 0x0 12359 /* Requested frequency in MHz for inter-core clock domain */ 12360 #define MC_CMD_SET_CLOCK_IN_ICORE_FREQ_OFST 4 12361 /* enum: Leave the inter-core clock domain frequency unchanged */ 12362 #define MC_CMD_SET_CLOCK_IN_ICORE_DOMAIN_DONT_CHANGE 0x0 12363 /* Requested frequency in MHz for DPCPU clock domain */ 12364 #define MC_CMD_SET_CLOCK_IN_DPCPU_FREQ_OFST 8 12365 /* enum: Leave the DPCPU clock domain frequency unchanged */ 12366 #define MC_CMD_SET_CLOCK_IN_DPCPU_DOMAIN_DONT_CHANGE 0x0 12367 /* Requested frequency in MHz for PCS clock domain */ 12368 #define MC_CMD_SET_CLOCK_IN_PCS_FREQ_OFST 12 12369 /* enum: Leave the PCS clock domain frequency unchanged */ 12370 #define MC_CMD_SET_CLOCK_IN_PCS_DOMAIN_DONT_CHANGE 0x0 12371 /* Requested frequency in MHz for MC clock domain */ 12372 #define MC_CMD_SET_CLOCK_IN_MC_FREQ_OFST 16 12373 /* enum: Leave the MC clock domain frequency unchanged */ 12374 #define MC_CMD_SET_CLOCK_IN_MC_DOMAIN_DONT_CHANGE 0x0 12375 /* Requested frequency in MHz for rmon clock domain */ 12376 #define MC_CMD_SET_CLOCK_IN_RMON_FREQ_OFST 20 12377 /* enum: Leave the rmon clock domain frequency unchanged */ 12378 #define MC_CMD_SET_CLOCK_IN_RMON_DOMAIN_DONT_CHANGE 0x0 12379 /* Requested frequency in MHz for vswitch clock domain */ 12380 #define MC_CMD_SET_CLOCK_IN_VSWITCH_FREQ_OFST 24 12381 /* enum: Leave the vswitch clock domain frequency unchanged */ 12382 #define MC_CMD_SET_CLOCK_IN_VSWITCH_DOMAIN_DONT_CHANGE 0x0 12383 12384 /* MC_CMD_SET_CLOCK_OUT msgresponse */ 12385 #define MC_CMD_SET_CLOCK_OUT_LEN 28 12386 /* Resulting system frequency in MHz */ 12387 #define MC_CMD_SET_CLOCK_OUT_SYS_FREQ_OFST 0 12388 /* enum: The system clock domain doesn't exist */ 12389 #define MC_CMD_SET_CLOCK_OUT_SYS_DOMAIN_UNSUPPORTED 0x0 12390 /* Resulting inter-core frequency in MHz */ 12391 #define MC_CMD_SET_CLOCK_OUT_ICORE_FREQ_OFST 4 12392 /* enum: The inter-core clock domain doesn't exist / isn't used */ 12393 #define MC_CMD_SET_CLOCK_OUT_ICORE_DOMAIN_UNSUPPORTED 0x0 12394 /* Resulting DPCPU frequency in MHz */ 12395 #define MC_CMD_SET_CLOCK_OUT_DPCPU_FREQ_OFST 8 12396 /* enum: The dpcpu clock domain doesn't exist */ 12397 #define MC_CMD_SET_CLOCK_OUT_DPCPU_DOMAIN_UNSUPPORTED 0x0 12398 /* Resulting PCS frequency in MHz */ 12399 #define MC_CMD_SET_CLOCK_OUT_PCS_FREQ_OFST 12 12400 /* enum: The PCS clock domain doesn't exist / isn't controlled */ 12401 #define MC_CMD_SET_CLOCK_OUT_PCS_DOMAIN_UNSUPPORTED 0x0 12402 /* Resulting MC frequency in MHz */ 12403 #define MC_CMD_SET_CLOCK_OUT_MC_FREQ_OFST 16 12404 /* enum: The MC clock domain doesn't exist / isn't controlled */ 12405 #define MC_CMD_SET_CLOCK_OUT_MC_DOMAIN_UNSUPPORTED 0x0 12406 /* Resulting rmon frequency in MHz */ 12407 #define MC_CMD_SET_CLOCK_OUT_RMON_FREQ_OFST 20 12408 /* enum: The rmon clock domain doesn't exist / isn't controlled */ 12409 #define MC_CMD_SET_CLOCK_OUT_RMON_DOMAIN_UNSUPPORTED 0x0 12410 /* Resulting vswitch frequency in MHz */ 12411 #define MC_CMD_SET_CLOCK_OUT_VSWITCH_FREQ_OFST 24 12412 /* enum: The vswitch clock domain doesn't exist / isn't controlled */ 12413 #define MC_CMD_SET_CLOCK_OUT_VSWITCH_DOMAIN_UNSUPPORTED 0x0 12414 12415 12416 /***********************************/ 12417 /* MC_CMD_DPCPU_RPC 12418 * Send an arbitrary DPCPU message. 12419 */ 12420 #define MC_CMD_DPCPU_RPC 0xae 12421 #undef MC_CMD_0xae_PRIVILEGE_CTG 12422 12423 #define MC_CMD_0xae_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12424 12425 /* MC_CMD_DPCPU_RPC_IN msgrequest */ 12426 #define MC_CMD_DPCPU_RPC_IN_LEN 36 12427 #define MC_CMD_DPCPU_RPC_IN_CPU_OFST 0 12428 /* enum: RxDPCPU0 */ 12429 #define MC_CMD_DPCPU_RPC_IN_DPCPU_RX0 0x0 12430 /* enum: TxDPCPU0 */ 12431 #define MC_CMD_DPCPU_RPC_IN_DPCPU_TX0 0x1 12432 /* enum: TxDPCPU1 */ 12433 #define MC_CMD_DPCPU_RPC_IN_DPCPU_TX1 0x2 12434 /* enum: RxDPCPU1 (Medford only) */ 12435 #define MC_CMD_DPCPU_RPC_IN_DPCPU_RX1 0x3 12436 /* enum: RxDPCPU (will be for the calling function; for now, just an alias of 12437 * DPCPU_RX0) 12438 */ 12439 #define MC_CMD_DPCPU_RPC_IN_DPCPU_RX 0x80 12440 /* enum: TxDPCPU (will be for the calling function; for now, just an alias of 12441 * DPCPU_TX0) 12442 */ 12443 #define MC_CMD_DPCPU_RPC_IN_DPCPU_TX 0x81 12444 /* First 8 bits [39:32] of DATA are consumed by MC-DPCPU protocol and must be 12445 * initialised to zero 12446 */ 12447 #define MC_CMD_DPCPU_RPC_IN_DATA_OFST 4 12448 #define MC_CMD_DPCPU_RPC_IN_DATA_LEN 32 12449 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_CMDNUM_LBN 8 12450 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_CMDNUM_WIDTH 8 12451 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_READ 0x6 /* enum */ 12452 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_WRITE 0x7 /* enum */ 12453 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_SELF_TEST 0xc /* enum */ 12454 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_CSR_ACCESS 0xe /* enum */ 12455 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_READ 0x46 /* enum */ 12456 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_WRITE 0x47 /* enum */ 12457 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_SELF_TEST 0x4a /* enum */ 12458 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_CSR_ACCESS 0x4c /* enum */ 12459 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_SET_MC_REPLAY_CNTXT 0x4d /* enum */ 12460 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_OBJID_LBN 16 12461 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_OBJID_WIDTH 16 12462 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_ADDR_LBN 16 12463 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_ADDR_WIDTH 16 12464 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_COUNT_LBN 48 12465 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_COUNT_WIDTH 16 12466 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_INFO_LBN 16 12467 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_INFO_WIDTH 240 12468 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_LBN 16 12469 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_WIDTH 16 12470 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_STOP_RETURN_RESULT 0x0 /* enum */ 12471 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_READ 0x1 /* enum */ 12472 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_WRITE 0x2 /* enum */ 12473 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_WRITE_READ 0x3 /* enum */ 12474 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_PIPELINED_READ 0x4 /* enum */ 12475 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_START_DELAY_LBN 48 12476 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_START_DELAY_WIDTH 16 12477 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_RPT_COUNT_LBN 64 12478 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_RPT_COUNT_WIDTH 16 12479 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_GAP_DELAY_LBN 80 12480 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_GAP_DELAY_WIDTH 16 12481 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_LBN 16 12482 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_WIDTH 16 12483 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_CUT_THROUGH 0x1 /* enum */ 12484 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_STORE_FORWARD 0x2 /* enum */ 12485 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_STORE_FORWARD_FIRST 0x3 /* enum */ 12486 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_CNTXT_LBN 64 12487 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_CNTXT_WIDTH 16 12488 #define MC_CMD_DPCPU_RPC_IN_WDATA_OFST 12 12489 #define MC_CMD_DPCPU_RPC_IN_WDATA_LEN 24 12490 /* Register data to write. Only valid in write/write-read. */ 12491 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_DATA_OFST 16 12492 /* Register address. */ 12493 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_ADDRESS_OFST 20 12494 12495 /* MC_CMD_DPCPU_RPC_OUT msgresponse */ 12496 #define MC_CMD_DPCPU_RPC_OUT_LEN 36 12497 #define MC_CMD_DPCPU_RPC_OUT_RC_OFST 0 12498 /* DATA */ 12499 #define MC_CMD_DPCPU_RPC_OUT_DATA_OFST 4 12500 #define MC_CMD_DPCPU_RPC_OUT_DATA_LEN 32 12501 #define MC_CMD_DPCPU_RPC_OUT_HDR_CMD_RESP_ERRCODE_LBN 32 12502 #define MC_CMD_DPCPU_RPC_OUT_HDR_CMD_RESP_ERRCODE_WIDTH 16 12503 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_COUNT_LBN 48 12504 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_COUNT_WIDTH 16 12505 #define MC_CMD_DPCPU_RPC_OUT_RDATA_OFST 12 12506 #define MC_CMD_DPCPU_RPC_OUT_RDATA_LEN 24 12507 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_1_OFST 12 12508 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_2_OFST 16 12509 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_3_OFST 20 12510 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_4_OFST 24 12511 12512 12513 /***********************************/ 12514 /* MC_CMD_TRIGGER_INTERRUPT 12515 * Trigger an interrupt by prodding the BIU. 12516 */ 12517 #define MC_CMD_TRIGGER_INTERRUPT 0xe3 12518 #undef MC_CMD_0xe3_PRIVILEGE_CTG 12519 12520 #define MC_CMD_0xe3_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12521 12522 /* MC_CMD_TRIGGER_INTERRUPT_IN msgrequest */ 12523 #define MC_CMD_TRIGGER_INTERRUPT_IN_LEN 4 12524 /* Interrupt level relative to base for function. */ 12525 #define MC_CMD_TRIGGER_INTERRUPT_IN_INTR_LEVEL_OFST 0 12526 12527 /* MC_CMD_TRIGGER_INTERRUPT_OUT msgresponse */ 12528 #define MC_CMD_TRIGGER_INTERRUPT_OUT_LEN 0 12529 12530 12531 /***********************************/ 12532 /* MC_CMD_SHMBOOT_OP 12533 * Special operations to support (for now) shmboot. 12534 */ 12535 #define MC_CMD_SHMBOOT_OP 0xe6 12536 #undef MC_CMD_0xe6_PRIVILEGE_CTG 12537 12538 #define MC_CMD_0xe6_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12539 12540 /* MC_CMD_SHMBOOT_OP_IN msgrequest */ 12541 #define MC_CMD_SHMBOOT_OP_IN_LEN 4 12542 /* Identifies the operation to perform */ 12543 #define MC_CMD_SHMBOOT_OP_IN_SHMBOOT_OP_OFST 0 12544 /* enum: Copy slave_data section to the slave core. (Greenport only) */ 12545 #define MC_CMD_SHMBOOT_OP_IN_PUSH_SLAVE_DATA 0x0 12546 12547 /* MC_CMD_SHMBOOT_OP_OUT msgresponse */ 12548 #define MC_CMD_SHMBOOT_OP_OUT_LEN 0 12549 12550 12551 /***********************************/ 12552 /* MC_CMD_CAP_BLK_READ 12553 * Read multiple 64bit words from capture block memory 12554 */ 12555 #define MC_CMD_CAP_BLK_READ 0xe7 12556 #undef MC_CMD_0xe7_PRIVILEGE_CTG 12557 12558 #define MC_CMD_0xe7_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12559 12560 /* MC_CMD_CAP_BLK_READ_IN msgrequest */ 12561 #define MC_CMD_CAP_BLK_READ_IN_LEN 12 12562 #define MC_CMD_CAP_BLK_READ_IN_CAP_REG_OFST 0 12563 #define MC_CMD_CAP_BLK_READ_IN_ADDR_OFST 4 12564 #define MC_CMD_CAP_BLK_READ_IN_COUNT_OFST 8 12565 12566 /* MC_CMD_CAP_BLK_READ_OUT msgresponse */ 12567 #define MC_CMD_CAP_BLK_READ_OUT_LENMIN 8 12568 #define MC_CMD_CAP_BLK_READ_OUT_LENMAX 248 12569 #define MC_CMD_CAP_BLK_READ_OUT_LEN(num) (0+8*(num)) 12570 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_OFST 0 12571 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LEN 8 12572 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LO_OFST 0 12573 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_HI_OFST 4 12574 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_MINNUM 1 12575 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_MAXNUM 31 12576 12577 12578 /***********************************/ 12579 /* MC_CMD_DUMP_DO 12580 * Take a dump of the DUT state 12581 */ 12582 #define MC_CMD_DUMP_DO 0xe8 12583 #undef MC_CMD_0xe8_PRIVILEGE_CTG 12584 12585 #define MC_CMD_0xe8_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12586 12587 /* MC_CMD_DUMP_DO_IN msgrequest */ 12588 #define MC_CMD_DUMP_DO_IN_LEN 52 12589 #define MC_CMD_DUMP_DO_IN_PADDING_OFST 0 12590 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_OFST 4 12591 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM 0x0 /* enum */ 12592 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_DEFAULT 0x1 /* enum */ 12593 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_TYPE_OFST 8 12594 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_NVRAM 0x1 /* enum */ 12595 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_HOST_MEMORY 0x2 /* enum */ 12596 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_HOST_MEMORY_MLI 0x3 /* enum */ 12597 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_UART 0x4 /* enum */ 12598 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 12 12599 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_OFST 16 12600 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 12 12601 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 16 12602 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 12 12603 #define MC_CMD_DUMP_DO_IN_HOST_MEMORY_MLI_PAGE_SIZE 0x1000 /* enum */ 12604 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 16 12605 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 20 12606 #define MC_CMD_DUMP_DO_IN_HOST_MEMORY_MLI_MAX_DEPTH 0x2 /* enum */ 12607 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_OFST 12 12608 /* enum: The uart port this command was received over (if using a uart 12609 * transport) 12610 */ 12611 #define MC_CMD_DUMP_DO_IN_UART_PORT_SRC 0xff 12612 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_SIZE_OFST 24 12613 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_OFST 28 12614 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM 0x0 /* enum */ 12615 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_NVRAM_DUMP_PARTITION 0x1 /* enum */ 12616 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_TYPE_OFST 32 12617 /* Enum values, see field(s): */ 12618 /* MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */ 12619 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 36 12620 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_OFST 40 12621 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 36 12622 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 40 12623 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 36 12624 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 40 12625 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 44 12626 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_UART_PORT_OFST 36 12627 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_SIZE_OFST 48 12628 12629 /* MC_CMD_DUMP_DO_OUT msgresponse */ 12630 #define MC_CMD_DUMP_DO_OUT_LEN 4 12631 #define MC_CMD_DUMP_DO_OUT_DUMPFILE_SIZE_OFST 0 12632 12633 12634 /***********************************/ 12635 /* MC_CMD_DUMP_CONFIGURE_UNSOLICITED 12636 * Configure unsolicited dumps 12637 */ 12638 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED 0xe9 12639 #undef MC_CMD_0xe9_PRIVILEGE_CTG 12640 12641 #define MC_CMD_0xe9_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12642 12643 /* MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN msgrequest */ 12644 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_LEN 52 12645 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_ENABLE_OFST 0 12646 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_OFST 4 12647 /* Enum values, see field(s): */ 12648 /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC */ 12649 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_TYPE_OFST 8 12650 /* Enum values, see field(s): */ 12651 /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */ 12652 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 12 12653 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_OFST 16 12654 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 12 12655 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 16 12656 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 12 12657 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 16 12658 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 20 12659 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_OFST 12 12660 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_SIZE_OFST 24 12661 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_OFST 28 12662 /* Enum values, see field(s): */ 12663 /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPFILE_DST */ 12664 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_TYPE_OFST 32 12665 /* Enum values, see field(s): */ 12666 /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */ 12667 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 36 12668 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_OFST 40 12669 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 36 12670 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 40 12671 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 36 12672 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 40 12673 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 44 12674 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_UART_PORT_OFST 36 12675 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_SIZE_OFST 48 12676 12677 12678 /***********************************/ 12679 /* MC_CMD_SET_PSU 12680 * Adjusts power supply parameters. This is a warranty-voiding operation. 12681 * Returns: ENOENT if the parameter or rail specified does not exist, EINVAL if 12682 * the parameter is out of range. 12683 */ 12684 #define MC_CMD_SET_PSU 0xea 12685 #undef MC_CMD_0xea_PRIVILEGE_CTG 12686 12687 #define MC_CMD_0xea_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12688 12689 /* MC_CMD_SET_PSU_IN msgrequest */ 12690 #define MC_CMD_SET_PSU_IN_LEN 12 12691 #define MC_CMD_SET_PSU_IN_PARAM_OFST 0 12692 #define MC_CMD_SET_PSU_IN_PARAM_SUPPLY_VOLTAGE 0x0 /* enum */ 12693 #define MC_CMD_SET_PSU_IN_RAIL_OFST 4 12694 #define MC_CMD_SET_PSU_IN_RAIL_0V9 0x0 /* enum */ 12695 #define MC_CMD_SET_PSU_IN_RAIL_1V2 0x1 /* enum */ 12696 /* desired value, eg voltage in mV */ 12697 #define MC_CMD_SET_PSU_IN_VALUE_OFST 8 12698 12699 /* MC_CMD_SET_PSU_OUT msgresponse */ 12700 #define MC_CMD_SET_PSU_OUT_LEN 0 12701 12702 12703 /***********************************/ 12704 /* MC_CMD_GET_FUNCTION_INFO 12705 * Get function information. PF and VF number. 12706 */ 12707 #define MC_CMD_GET_FUNCTION_INFO 0xec 12708 #undef MC_CMD_0xec_PRIVILEGE_CTG 12709 12710 #define MC_CMD_0xec_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12711 12712 /* MC_CMD_GET_FUNCTION_INFO_IN msgrequest */ 12713 #define MC_CMD_GET_FUNCTION_INFO_IN_LEN 0 12714 12715 /* MC_CMD_GET_FUNCTION_INFO_OUT msgresponse */ 12716 #define MC_CMD_GET_FUNCTION_INFO_OUT_LEN 8 12717 #define MC_CMD_GET_FUNCTION_INFO_OUT_PF_OFST 0 12718 #define MC_CMD_GET_FUNCTION_INFO_OUT_VF_OFST 4 12719 12720 12721 /***********************************/ 12722 /* MC_CMD_ENABLE_OFFLINE_BIST 12723 * Enters offline BIST mode. All queues are torn down, chip enters quiescent 12724 * mode, calling function gets exclusive MCDI ownership. The only way out is 12725 * reboot. 12726 */ 12727 #define MC_CMD_ENABLE_OFFLINE_BIST 0xed 12728 #undef MC_CMD_0xed_PRIVILEGE_CTG 12729 12730 #define MC_CMD_0xed_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12731 12732 /* MC_CMD_ENABLE_OFFLINE_BIST_IN msgrequest */ 12733 #define MC_CMD_ENABLE_OFFLINE_BIST_IN_LEN 0 12734 12735 /* MC_CMD_ENABLE_OFFLINE_BIST_OUT msgresponse */ 12736 #define MC_CMD_ENABLE_OFFLINE_BIST_OUT_LEN 0 12737 12738 12739 /***********************************/ 12740 /* MC_CMD_UART_SEND_DATA 12741 * Send checksummed[sic] block of data over the uart. Response is a placeholder 12742 * should we wish to make this reliable; currently requests are fire-and- 12743 * forget. 12744 */ 12745 #define MC_CMD_UART_SEND_DATA 0xee 12746 #undef MC_CMD_0xee_PRIVILEGE_CTG 12747 12748 #define MC_CMD_0xee_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12749 12750 /* MC_CMD_UART_SEND_DATA_OUT msgrequest */ 12751 #define MC_CMD_UART_SEND_DATA_OUT_LENMIN 16 12752 #define MC_CMD_UART_SEND_DATA_OUT_LENMAX 252 12753 #define MC_CMD_UART_SEND_DATA_OUT_LEN(num) (16+1*(num)) 12754 /* CRC32 over OFFSET, LENGTH, RESERVED, DATA */ 12755 #define MC_CMD_UART_SEND_DATA_OUT_CHECKSUM_OFST 0 12756 /* Offset at which to write the data */ 12757 #define MC_CMD_UART_SEND_DATA_OUT_OFFSET_OFST 4 12758 /* Length of data */ 12759 #define MC_CMD_UART_SEND_DATA_OUT_LENGTH_OFST 8 12760 /* Reserved for future use */ 12761 #define MC_CMD_UART_SEND_DATA_OUT_RESERVED_OFST 12 12762 #define MC_CMD_UART_SEND_DATA_OUT_DATA_OFST 16 12763 #define MC_CMD_UART_SEND_DATA_OUT_DATA_LEN 1 12764 #define MC_CMD_UART_SEND_DATA_OUT_DATA_MINNUM 0 12765 #define MC_CMD_UART_SEND_DATA_OUT_DATA_MAXNUM 236 12766 12767 /* MC_CMD_UART_SEND_DATA_IN msgresponse */ 12768 #define MC_CMD_UART_SEND_DATA_IN_LEN 0 12769 12770 12771 /***********************************/ 12772 /* MC_CMD_UART_RECV_DATA 12773 * Request checksummed[sic] block of data over the uart. Only a placeholder, 12774 * subject to change and not currently implemented. 12775 */ 12776 #define MC_CMD_UART_RECV_DATA 0xef 12777 #undef MC_CMD_0xef_PRIVILEGE_CTG 12778 12779 #define MC_CMD_0xef_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12780 12781 /* MC_CMD_UART_RECV_DATA_OUT msgrequest */ 12782 #define MC_CMD_UART_RECV_DATA_OUT_LEN 16 12783 /* CRC32 over OFFSET, LENGTH, RESERVED */ 12784 #define MC_CMD_UART_RECV_DATA_OUT_CHECKSUM_OFST 0 12785 /* Offset from which to read the data */ 12786 #define MC_CMD_UART_RECV_DATA_OUT_OFFSET_OFST 4 12787 /* Length of data */ 12788 #define MC_CMD_UART_RECV_DATA_OUT_LENGTH_OFST 8 12789 /* Reserved for future use */ 12790 #define MC_CMD_UART_RECV_DATA_OUT_RESERVED_OFST 12 12791 12792 /* MC_CMD_UART_RECV_DATA_IN msgresponse */ 12793 #define MC_CMD_UART_RECV_DATA_IN_LENMIN 16 12794 #define MC_CMD_UART_RECV_DATA_IN_LENMAX 252 12795 #define MC_CMD_UART_RECV_DATA_IN_LEN(num) (16+1*(num)) 12796 /* CRC32 over RESERVED1, RESERVED2, RESERVED3, DATA */ 12797 #define MC_CMD_UART_RECV_DATA_IN_CHECKSUM_OFST 0 12798 /* Offset at which to write the data */ 12799 #define MC_CMD_UART_RECV_DATA_IN_RESERVED1_OFST 4 12800 /* Length of data */ 12801 #define MC_CMD_UART_RECV_DATA_IN_RESERVED2_OFST 8 12802 /* Reserved for future use */ 12803 #define MC_CMD_UART_RECV_DATA_IN_RESERVED3_OFST 12 12804 #define MC_CMD_UART_RECV_DATA_IN_DATA_OFST 16 12805 #define MC_CMD_UART_RECV_DATA_IN_DATA_LEN 1 12806 #define MC_CMD_UART_RECV_DATA_IN_DATA_MINNUM 0 12807 #define MC_CMD_UART_RECV_DATA_IN_DATA_MAXNUM 236 12808 12809 12810 /***********************************/ 12811 /* MC_CMD_READ_FUSES 12812 * Read data programmed into the device One-Time-Programmable (OTP) Fuses 12813 */ 12814 #define MC_CMD_READ_FUSES 0xf0 12815 #undef MC_CMD_0xf0_PRIVILEGE_CTG 12816 12817 #define MC_CMD_0xf0_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12818 12819 /* MC_CMD_READ_FUSES_IN msgrequest */ 12820 #define MC_CMD_READ_FUSES_IN_LEN 8 12821 /* Offset in OTP to read */ 12822 #define MC_CMD_READ_FUSES_IN_OFFSET_OFST 0 12823 /* Length of data to read in bytes */ 12824 #define MC_CMD_READ_FUSES_IN_LENGTH_OFST 4 12825 12826 /* MC_CMD_READ_FUSES_OUT msgresponse */ 12827 #define MC_CMD_READ_FUSES_OUT_LENMIN 4 12828 #define MC_CMD_READ_FUSES_OUT_LENMAX 252 12829 #define MC_CMD_READ_FUSES_OUT_LEN(num) (4+1*(num)) 12830 /* Length of returned OTP data in bytes */ 12831 #define MC_CMD_READ_FUSES_OUT_LENGTH_OFST 0 12832 /* Returned data */ 12833 #define MC_CMD_READ_FUSES_OUT_DATA_OFST 4 12834 #define MC_CMD_READ_FUSES_OUT_DATA_LEN 1 12835 #define MC_CMD_READ_FUSES_OUT_DATA_MINNUM 0 12836 #define MC_CMD_READ_FUSES_OUT_DATA_MAXNUM 248 12837 12838 12839 /***********************************/ 12840 /* MC_CMD_KR_TUNE 12841 * Get or set KR Serdes RXEQ and TX Driver settings 12842 */ 12843 #define MC_CMD_KR_TUNE 0xf1 12844 #undef MC_CMD_0xf1_PRIVILEGE_CTG 12845 12846 #define MC_CMD_0xf1_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12847 12848 /* MC_CMD_KR_TUNE_IN msgrequest */ 12849 #define MC_CMD_KR_TUNE_IN_LENMIN 4 12850 #define MC_CMD_KR_TUNE_IN_LENMAX 252 12851 #define MC_CMD_KR_TUNE_IN_LEN(num) (4+4*(num)) 12852 /* Requested operation */ 12853 #define MC_CMD_KR_TUNE_IN_KR_TUNE_OP_OFST 0 12854 #define MC_CMD_KR_TUNE_IN_KR_TUNE_OP_LEN 1 12855 /* enum: Get current RXEQ settings */ 12856 #define MC_CMD_KR_TUNE_IN_RXEQ_GET 0x0 12857 /* enum: Override RXEQ settings */ 12858 #define MC_CMD_KR_TUNE_IN_RXEQ_SET 0x1 12859 /* enum: Get current TX Driver settings */ 12860 #define MC_CMD_KR_TUNE_IN_TXEQ_GET 0x2 12861 /* enum: Override TX Driver settings */ 12862 #define MC_CMD_KR_TUNE_IN_TXEQ_SET 0x3 12863 /* enum: Force KR Serdes reset / recalibration */ 12864 #define MC_CMD_KR_TUNE_IN_RECAL 0x4 12865 /* enum: Start KR Serdes Eye diagram plot on a given lane. Lane must have valid 12866 * signal. 12867 */ 12868 #define MC_CMD_KR_TUNE_IN_START_EYE_PLOT 0x5 12869 /* enum: Poll KR Serdes Eye diagram plot. Returns one row of BER data. The 12870 * caller should call this command repeatedly after starting eye plot, until no 12871 * more data is returned. 12872 */ 12873 #define MC_CMD_KR_TUNE_IN_POLL_EYE_PLOT 0x6 12874 /* enum: Read Figure Of Merit (eye quality, higher is better). */ 12875 #define MC_CMD_KR_TUNE_IN_READ_FOM 0x7 12876 /* Align the arguments to 32 bits */ 12877 #define MC_CMD_KR_TUNE_IN_KR_TUNE_RSVD_OFST 1 12878 #define MC_CMD_KR_TUNE_IN_KR_TUNE_RSVD_LEN 3 12879 /* Arguments specific to the operation */ 12880 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_OFST 4 12881 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_LEN 4 12882 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_MINNUM 0 12883 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_MAXNUM 62 12884 12885 /* MC_CMD_KR_TUNE_OUT msgresponse */ 12886 #define MC_CMD_KR_TUNE_OUT_LEN 0 12887 12888 /* MC_CMD_KR_TUNE_RXEQ_GET_IN msgrequest */ 12889 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_LEN 4 12890 /* Requested operation */ 12891 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_OP_OFST 0 12892 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_OP_LEN 1 12893 /* Align the arguments to 32 bits */ 12894 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_RSVD_OFST 1 12895 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_RSVD_LEN 3 12896 12897 /* MC_CMD_KR_TUNE_RXEQ_GET_OUT msgresponse */ 12898 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LENMIN 4 12899 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LENMAX 252 12900 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LEN(num) (0+4*(num)) 12901 /* RXEQ Parameter */ 12902 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_OFST 0 12903 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LEN 4 12904 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_MINNUM 1 12905 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_MAXNUM 63 12906 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_LBN 0 12907 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_WIDTH 8 12908 /* enum: Attenuation (0-15, Huntington) */ 12909 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_ATT 0x0 12910 /* enum: CTLE Boost (0-15, Huntington) */ 12911 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_BOOST 0x1 12912 /* enum: Edge DFE Tap1 (Huntington - 0 - max negative, 64 - zero, 127 - max 12913 * positive, Medford - 0-31) 12914 */ 12915 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP1 0x2 12916 /* enum: Edge DFE Tap2 (Huntington - 0 - max negative, 32 - zero, 63 - max 12917 * positive, Medford - 0-31) 12918 */ 12919 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP2 0x3 12920 /* enum: Edge DFE Tap3 (Huntington - 0 - max negative, 32 - zero, 63 - max 12921 * positive, Medford - 0-16) 12922 */ 12923 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP3 0x4 12924 /* enum: Edge DFE Tap4 (Huntington - 0 - max negative, 32 - zero, 63 - max 12925 * positive, Medford - 0-16) 12926 */ 12927 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP4 0x5 12928 /* enum: Edge DFE Tap5 (Huntington - 0 - max negative, 32 - zero, 63 - max 12929 * positive, Medford - 0-16) 12930 */ 12931 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP5 0x6 12932 /* enum: Edge DFE DLEV (0-128 for Medford) */ 12933 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_DLEV 0x7 12934 /* enum: Variable Gain Amplifier (0-15, Medford) */ 12935 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_VGA 0x8 12936 /* enum: CTLE EQ Capacitor (0-15, Medford) */ 12937 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_EQC 0x9 12938 /* enum: CTLE EQ Resistor (0-7, Medford) */ 12939 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_EQRES 0xa 12940 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_LBN 8 12941 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_WIDTH 3 12942 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */ 12943 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_1 0x1 /* enum */ 12944 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_2 0x2 /* enum */ 12945 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_3 0x3 /* enum */ 12946 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_ALL 0x4 /* enum */ 12947 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_LBN 11 12948 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_WIDTH 1 12949 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_RESERVED_LBN 12 12950 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_RESERVED_WIDTH 4 12951 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_INITIAL_LBN 16 12952 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_INITIAL_WIDTH 8 12953 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_LBN 24 12954 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8 12955 12956 /* MC_CMD_KR_TUNE_RXEQ_SET_IN msgrequest */ 12957 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_LENMIN 8 12958 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_LENMAX 252 12959 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_LEN(num) (4+4*(num)) 12960 /* Requested operation */ 12961 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_OP_OFST 0 12962 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_OP_LEN 1 12963 /* Align the arguments to 32 bits */ 12964 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_RSVD_OFST 1 12965 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_RSVD_LEN 3 12966 /* RXEQ Parameter */ 12967 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_OFST 4 12968 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LEN 4 12969 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_MINNUM 1 12970 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_MAXNUM 62 12971 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_ID_LBN 0 12972 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_ID_WIDTH 8 12973 /* Enum values, see field(s): */ 12974 /* MC_CMD_KR_TUNE_RXEQ_GET_OUT/PARAM_ID */ 12975 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LANE_LBN 8 12976 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LANE_WIDTH 3 12977 /* Enum values, see field(s): */ 12978 /* MC_CMD_KR_TUNE_RXEQ_GET_OUT/PARAM_LANE */ 12979 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_LBN 11 12980 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_WIDTH 1 12981 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED_LBN 12 12982 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED_WIDTH 4 12983 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_INITIAL_LBN 16 12984 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_INITIAL_WIDTH 8 12985 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED2_LBN 24 12986 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED2_WIDTH 8 12987 12988 /* MC_CMD_KR_TUNE_RXEQ_SET_OUT msgresponse */ 12989 #define MC_CMD_KR_TUNE_RXEQ_SET_OUT_LEN 0 12990 12991 /* MC_CMD_KR_TUNE_TXEQ_GET_IN msgrequest */ 12992 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_LEN 4 12993 /* Requested operation */ 12994 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_OP_OFST 0 12995 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_OP_LEN 1 12996 /* Align the arguments to 32 bits */ 12997 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_RSVD_OFST 1 12998 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_RSVD_LEN 3 12999 13000 /* MC_CMD_KR_TUNE_TXEQ_GET_OUT msgresponse */ 13001 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LENMIN 4 13002 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LENMAX 252 13003 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LEN(num) (0+4*(num)) 13004 /* TXEQ Parameter */ 13005 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_OFST 0 13006 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LEN 4 13007 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_MINNUM 1 13008 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_MAXNUM 63 13009 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_LBN 0 13010 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_WIDTH 8 13011 /* enum: TX Amplitude (Huntington, Medford) */ 13012 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV 0x0 13013 /* enum: De-Emphasis Tap1 Magnitude (0-7) (Huntington) */ 13014 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_MODE 0x1 13015 /* enum: De-Emphasis Tap1 Fine */ 13016 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_DTLEV 0x2 13017 /* enum: De-Emphasis Tap2 Magnitude (0-6) (Huntington) */ 13018 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_D2 0x3 13019 /* enum: De-Emphasis Tap2 Fine (Huntington) */ 13020 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_D2TLEV 0x4 13021 /* enum: Pre-Emphasis Magnitude (Huntington) */ 13022 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_E 0x5 13023 /* enum: Pre-Emphasis Fine (Huntington) */ 13024 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_ETLEV 0x6 13025 /* enum: TX Slew Rate Coarse control (Huntington) */ 13026 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_PREDRV_DLY 0x7 13027 /* enum: TX Slew Rate Fine control (Huntington) */ 13028 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_SR_SET 0x8 13029 /* enum: TX Termination Impedance control (Huntington) */ 13030 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_RT_SET 0x9 13031 /* enum: TX Amplitude Fine control (Medford) */ 13032 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV_FINE 0xa 13033 /* enum: Pre-shoot Tap (Medford) */ 13034 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_ADV 0xb 13035 /* enum: De-emphasis Tap (Medford) */ 13036 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_DLY 0xc 13037 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LANE_LBN 8 13038 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LANE_WIDTH 3 13039 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_0 0x0 /* enum */ 13040 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_1 0x1 /* enum */ 13041 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_2 0x2 /* enum */ 13042 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_3 0x3 /* enum */ 13043 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_ALL 0x4 /* enum */ 13044 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED_LBN 11 13045 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED_WIDTH 5 13046 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_INITIAL_LBN 16 13047 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_INITIAL_WIDTH 8 13048 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED2_LBN 24 13049 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED2_WIDTH 8 13050 13051 /* MC_CMD_KR_TUNE_TXEQ_SET_IN msgrequest */ 13052 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_LENMIN 8 13053 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_LENMAX 252 13054 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_LEN(num) (4+4*(num)) 13055 /* Requested operation */ 13056 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_OP_OFST 0 13057 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_OP_LEN 1 13058 /* Align the arguments to 32 bits */ 13059 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_RSVD_OFST 1 13060 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_RSVD_LEN 3 13061 /* TXEQ Parameter */ 13062 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_OFST 4 13063 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LEN 4 13064 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_MINNUM 1 13065 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_MAXNUM 62 13066 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_ID_LBN 0 13067 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_ID_WIDTH 8 13068 /* Enum values, see field(s): */ 13069 /* MC_CMD_KR_TUNE_TXEQ_GET_OUT/PARAM_ID */ 13070 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LANE_LBN 8 13071 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LANE_WIDTH 3 13072 /* Enum values, see field(s): */ 13073 /* MC_CMD_KR_TUNE_TXEQ_GET_OUT/PARAM_LANE */ 13074 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED_LBN 11 13075 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED_WIDTH 5 13076 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_INITIAL_LBN 16 13077 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_INITIAL_WIDTH 8 13078 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED2_LBN 24 13079 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED2_WIDTH 8 13080 13081 /* MC_CMD_KR_TUNE_TXEQ_SET_OUT msgresponse */ 13082 #define MC_CMD_KR_TUNE_TXEQ_SET_OUT_LEN 0 13083 13084 /* MC_CMD_KR_TUNE_RECAL_IN msgrequest */ 13085 #define MC_CMD_KR_TUNE_RECAL_IN_LEN 4 13086 /* Requested operation */ 13087 #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_OP_OFST 0 13088 #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_OP_LEN 1 13089 /* Align the arguments to 32 bits */ 13090 #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_RSVD_OFST 1 13091 #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_RSVD_LEN 3 13092 13093 /* MC_CMD_KR_TUNE_RECAL_OUT msgresponse */ 13094 #define MC_CMD_KR_TUNE_RECAL_OUT_LEN 0 13095 13096 /* MC_CMD_KR_TUNE_START_EYE_PLOT_IN msgrequest */ 13097 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_LEN 8 13098 /* Requested operation */ 13099 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_OP_OFST 0 13100 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_OP_LEN 1 13101 /* Align the arguments to 32 bits */ 13102 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_RSVD_OFST 1 13103 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_RSVD_LEN 3 13104 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_LANE_OFST 4 13105 13106 /* MC_CMD_KR_TUNE_START_EYE_PLOT_OUT msgresponse */ 13107 #define MC_CMD_KR_TUNE_START_EYE_PLOT_OUT_LEN 0 13108 13109 /* MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN msgrequest */ 13110 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_LEN 4 13111 /* Requested operation */ 13112 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_OP_OFST 0 13113 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_OP_LEN 1 13114 /* Align the arguments to 32 bits */ 13115 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_RSVD_OFST 1 13116 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_RSVD_LEN 3 13117 13118 /* MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT msgresponse */ 13119 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LENMIN 0 13120 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LENMAX 252 13121 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LEN(num) (0+2*(num)) 13122 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_OFST 0 13123 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_LEN 2 13124 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MINNUM 0 13125 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MAXNUM 126 13126 13127 /* MC_CMD_KR_TUNE_READ_FOM_IN msgrequest */ 13128 #define MC_CMD_KR_TUNE_READ_FOM_IN_LEN 8 13129 /* Requested operation */ 13130 #define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_OP_OFST 0 13131 #define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_OP_LEN 1 13132 /* Align the arguments to 32 bits */ 13133 #define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_RSVD_OFST 1 13134 #define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_RSVD_LEN 3 13135 #define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_OFST 4 13136 13137 /* MC_CMD_KR_TUNE_READ_FOM_OUT msgresponse */ 13138 #define MC_CMD_KR_TUNE_READ_FOM_OUT_LEN 4 13139 #define MC_CMD_KR_TUNE_READ_FOM_OUT_FOM_OFST 0 13140 13141 13142 /***********************************/ 13143 /* MC_CMD_PCIE_TUNE 13144 * Get or set PCIE Serdes RXEQ and TX Driver settings 13145 */ 13146 #define MC_CMD_PCIE_TUNE 0xf2 13147 #undef MC_CMD_0xf2_PRIVILEGE_CTG 13148 13149 #define MC_CMD_0xf2_PRIVILEGE_CTG SRIOV_CTG_ADMIN 13150 13151 /* MC_CMD_PCIE_TUNE_IN msgrequest */ 13152 #define MC_CMD_PCIE_TUNE_IN_LENMIN 4 13153 #define MC_CMD_PCIE_TUNE_IN_LENMAX 252 13154 #define MC_CMD_PCIE_TUNE_IN_LEN(num) (4+4*(num)) 13155 /* Requested operation */ 13156 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_OP_OFST 0 13157 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_OP_LEN 1 13158 /* enum: Get current RXEQ settings */ 13159 #define MC_CMD_PCIE_TUNE_IN_RXEQ_GET 0x0 13160 /* enum: Override RXEQ settings */ 13161 #define MC_CMD_PCIE_TUNE_IN_RXEQ_SET 0x1 13162 /* enum: Get current TX Driver settings */ 13163 #define MC_CMD_PCIE_TUNE_IN_TXEQ_GET 0x2 13164 /* enum: Override TX Driver settings */ 13165 #define MC_CMD_PCIE_TUNE_IN_TXEQ_SET 0x3 13166 /* enum: Start PCIe Serdes Eye diagram plot on a given lane. */ 13167 #define MC_CMD_PCIE_TUNE_IN_START_EYE_PLOT 0x5 13168 /* enum: Poll PCIe Serdes Eye diagram plot. Returns one row of BER data. The 13169 * caller should call this command repeatedly after starting eye plot, until no 13170 * more data is returned. 13171 */ 13172 #define MC_CMD_PCIE_TUNE_IN_POLL_EYE_PLOT 0x6 13173 /* enum: Enable the SERDES BIST and set it to generate a 200MHz square wave */ 13174 #define MC_CMD_PCIE_TUNE_IN_BIST_SQUARE_WAVE 0x7 13175 /* Align the arguments to 32 bits */ 13176 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_RSVD_OFST 1 13177 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_RSVD_LEN 3 13178 /* Arguments specific to the operation */ 13179 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_OFST 4 13180 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_LEN 4 13181 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_MINNUM 0 13182 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_MAXNUM 62 13183 13184 /* MC_CMD_PCIE_TUNE_OUT msgresponse */ 13185 #define MC_CMD_PCIE_TUNE_OUT_LEN 0 13186 13187 /* MC_CMD_PCIE_TUNE_RXEQ_GET_IN msgrequest */ 13188 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_LEN 4 13189 /* Requested operation */ 13190 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_OP_OFST 0 13191 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_OP_LEN 1 13192 /* Align the arguments to 32 bits */ 13193 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_RSVD_OFST 1 13194 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_RSVD_LEN 3 13195 13196 /* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT msgresponse */ 13197 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LENMIN 4 13198 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LENMAX 252 13199 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LEN(num) (0+4*(num)) 13200 /* RXEQ Parameter */ 13201 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_OFST 0 13202 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LEN 4 13203 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_MINNUM 1 13204 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_MAXNUM 63 13205 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_ID_LBN 0 13206 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_ID_WIDTH 8 13207 /* enum: Attenuation (0-15) */ 13208 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_ATT 0x0 13209 /* enum: CTLE Boost (0-15) */ 13210 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_BOOST 0x1 13211 /* enum: DFE Tap1 (0 - max negative, 64 - zero, 127 - max positive) */ 13212 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP1 0x2 13213 /* enum: DFE Tap2 (0 - max negative, 32 - zero, 63 - max positive) */ 13214 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP2 0x3 13215 /* enum: DFE Tap3 (0 - max negative, 32 - zero, 63 - max positive) */ 13216 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP3 0x4 13217 /* enum: DFE Tap4 (0 - max negative, 32 - zero, 63 - max positive) */ 13218 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP4 0x5 13219 /* enum: DFE Tap5 (0 - max negative, 32 - zero, 63 - max positive) */ 13220 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP5 0x6 13221 /* enum: DFE DLev */ 13222 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_DLEV 0x7 13223 /* enum: Figure of Merit */ 13224 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_FOM 0x8 13225 /* enum: CTLE EQ Capacitor (HF Gain) */ 13226 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_CTLE_EQC 0x9 13227 /* enum: CTLE EQ Resistor (DC Gain) */ 13228 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_CTLE_EQRES 0xa 13229 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_LBN 8 13230 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_WIDTH 5 13231 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */ 13232 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_1 0x1 /* enum */ 13233 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_2 0x2 /* enum */ 13234 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_3 0x3 /* enum */ 13235 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_4 0x4 /* enum */ 13236 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_5 0x5 /* enum */ 13237 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_6 0x6 /* enum */ 13238 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_7 0x7 /* enum */ 13239 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_8 0x8 /* enum */ 13240 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_9 0x9 /* enum */ 13241 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_10 0xa /* enum */ 13242 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_11 0xb /* enum */ 13243 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_12 0xc /* enum */ 13244 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_13 0xd /* enum */ 13245 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_14 0xe /* enum */ 13246 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_15 0xf /* enum */ 13247 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_ALL 0x10 /* enum */ 13248 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_LBN 13 13249 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_WIDTH 1 13250 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_LBN 14 13251 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_WIDTH 10 13252 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_LBN 24 13253 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8 13254 13255 /* MC_CMD_PCIE_TUNE_RXEQ_SET_IN msgrequest */ 13256 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LENMIN 8 13257 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LENMAX 252 13258 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LEN(num) (4+4*(num)) 13259 /* Requested operation */ 13260 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_OP_OFST 0 13261 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_OP_LEN 1 13262 /* Align the arguments to 32 bits */ 13263 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_RSVD_OFST 1 13264 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_RSVD_LEN 3 13265 /* RXEQ Parameter */ 13266 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_OFST 4 13267 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LEN 4 13268 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_MINNUM 1 13269 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_MAXNUM 62 13270 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_ID_LBN 0 13271 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_ID_WIDTH 8 13272 /* Enum values, see field(s): */ 13273 /* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_ID */ 13274 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LANE_LBN 8 13275 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LANE_WIDTH 5 13276 /* Enum values, see field(s): */ 13277 /* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_LANE */ 13278 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_LBN 13 13279 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_WIDTH 1 13280 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED_LBN 14 13281 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED_WIDTH 2 13282 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_INITIAL_LBN 16 13283 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_INITIAL_WIDTH 8 13284 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED2_LBN 24 13285 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED2_WIDTH 8 13286 13287 /* MC_CMD_PCIE_TUNE_RXEQ_SET_OUT msgresponse */ 13288 #define MC_CMD_PCIE_TUNE_RXEQ_SET_OUT_LEN 0 13289 13290 /* MC_CMD_PCIE_TUNE_TXEQ_GET_IN msgrequest */ 13291 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_LEN 4 13292 /* Requested operation */ 13293 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_OP_OFST 0 13294 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_OP_LEN 1 13295 /* Align the arguments to 32 bits */ 13296 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_RSVD_OFST 1 13297 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_RSVD_LEN 3 13298 13299 /* MC_CMD_PCIE_TUNE_TXEQ_GET_OUT msgresponse */ 13300 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LENMIN 4 13301 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LENMAX 252 13302 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LEN(num) (0+4*(num)) 13303 /* RXEQ Parameter */ 13304 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_OFST 0 13305 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LEN 4 13306 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_MINNUM 1 13307 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_MAXNUM 63 13308 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_ID_LBN 0 13309 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_ID_WIDTH 8 13310 /* enum: TxMargin (PIPE) */ 13311 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_TXMARGIN 0x0 13312 /* enum: TxSwing (PIPE) */ 13313 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_TXSWING 0x1 13314 /* enum: De-emphasis coefficient C(-1) (PIPE) */ 13315 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_CM1 0x2 13316 /* enum: De-emphasis coefficient C(0) (PIPE) */ 13317 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_C0 0x3 13318 /* enum: De-emphasis coefficient C(+1) (PIPE) */ 13319 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_CP1 0x4 13320 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LANE_LBN 8 13321 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LANE_WIDTH 4 13322 /* Enum values, see field(s): */ 13323 /* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_LANE */ 13324 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_RESERVED_LBN 12 13325 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_RESERVED_WIDTH 12 13326 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_CURRENT_LBN 24 13327 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8 13328 13329 /* MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN msgrequest */ 13330 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_LEN 8 13331 /* Requested operation */ 13332 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_OP_OFST 0 13333 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_OP_LEN 1 13334 /* Align the arguments to 32 bits */ 13335 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_RSVD_OFST 1 13336 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_RSVD_LEN 3 13337 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_LANE_OFST 4 13338 13339 /* MC_CMD_PCIE_TUNE_START_EYE_PLOT_OUT msgresponse */ 13340 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_OUT_LEN 0 13341 13342 /* MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN msgrequest */ 13343 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_LEN 4 13344 /* Requested operation */ 13345 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_OP_OFST 0 13346 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_OP_LEN 1 13347 /* Align the arguments to 32 bits */ 13348 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_RSVD_OFST 1 13349 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_RSVD_LEN 3 13350 13351 /* MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT msgresponse */ 13352 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LENMIN 0 13353 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LENMAX 252 13354 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LEN(num) (0+2*(num)) 13355 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_OFST 0 13356 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_LEN 2 13357 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MINNUM 0 13358 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MAXNUM 126 13359 13360 /* MC_CMD_PCIE_TUNE_BIST_SQUARE_WAVE_IN msgrequest */ 13361 #define MC_CMD_PCIE_TUNE_BIST_SQUARE_WAVE_IN_LEN 0 13362 13363 /* MC_CMD_PCIE_TUNE_BIST_SQUARE_WAVE_OUT msgrequest */ 13364 #define MC_CMD_PCIE_TUNE_BIST_SQUARE_WAVE_OUT_LEN 0 13365 13366 13367 /***********************************/ 13368 /* MC_CMD_LICENSING 13369 * Operations on the NVRAM_PARTITION_TYPE_LICENSE application license partition 13370 * - not used for V3 licensing 13371 */ 13372 #define MC_CMD_LICENSING 0xf3 13373 #undef MC_CMD_0xf3_PRIVILEGE_CTG 13374 13375 #define MC_CMD_0xf3_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13376 13377 /* MC_CMD_LICENSING_IN msgrequest */ 13378 #define MC_CMD_LICENSING_IN_LEN 4 13379 /* identifies the type of operation requested */ 13380 #define MC_CMD_LICENSING_IN_OP_OFST 0 13381 /* enum: re-read and apply licenses after a license key partition update; note 13382 * that this operation returns a zero-length response 13383 */ 13384 #define MC_CMD_LICENSING_IN_OP_UPDATE_LICENSE 0x0 13385 /* enum: report counts of installed licenses */ 13386 #define MC_CMD_LICENSING_IN_OP_GET_KEY_STATS 0x1 13387 13388 /* MC_CMD_LICENSING_OUT msgresponse */ 13389 #define MC_CMD_LICENSING_OUT_LEN 28 13390 /* count of application keys which are valid */ 13391 #define MC_CMD_LICENSING_OUT_VALID_APP_KEYS_OFST 0 13392 /* sum of UNVERIFIABLE_APP_KEYS + WRONG_NODE_APP_KEYS (for compatibility with 13393 * MC_CMD_FC_OP_LICENSE) 13394 */ 13395 #define MC_CMD_LICENSING_OUT_INVALID_APP_KEYS_OFST 4 13396 /* count of application keys which are invalid due to being blacklisted */ 13397 #define MC_CMD_LICENSING_OUT_BLACKLISTED_APP_KEYS_OFST 8 13398 /* count of application keys which are invalid due to being unverifiable */ 13399 #define MC_CMD_LICENSING_OUT_UNVERIFIABLE_APP_KEYS_OFST 12 13400 /* count of application keys which are invalid due to being for the wrong node 13401 */ 13402 #define MC_CMD_LICENSING_OUT_WRONG_NODE_APP_KEYS_OFST 16 13403 /* licensing state (for diagnostics; the exact meaning of the bits in this 13404 * field are private to the firmware) 13405 */ 13406 #define MC_CMD_LICENSING_OUT_LICENSING_STATE_OFST 20 13407 /* licensing subsystem self-test report (for manftest) */ 13408 #define MC_CMD_LICENSING_OUT_LICENSING_SELF_TEST_OFST 24 13409 /* enum: licensing subsystem self-test failed */ 13410 #define MC_CMD_LICENSING_OUT_SELF_TEST_FAIL 0x0 13411 /* enum: licensing subsystem self-test passed */ 13412 #define MC_CMD_LICENSING_OUT_SELF_TEST_PASS 0x1 13413 13414 13415 /***********************************/ 13416 /* MC_CMD_LICENSING_V3 13417 * Operations on the NVRAM_PARTITION_TYPE_LICENSE application license partition 13418 * - V3 licensing (Medford) 13419 */ 13420 #define MC_CMD_LICENSING_V3 0xd0 13421 #undef MC_CMD_0xd0_PRIVILEGE_CTG 13422 13423 #define MC_CMD_0xd0_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13424 13425 /* MC_CMD_LICENSING_V3_IN msgrequest */ 13426 #define MC_CMD_LICENSING_V3_IN_LEN 4 13427 /* identifies the type of operation requested */ 13428 #define MC_CMD_LICENSING_V3_IN_OP_OFST 0 13429 /* enum: re-read and apply licenses after a license key partition update; note 13430 * that this operation returns a zero-length response 13431 */ 13432 #define MC_CMD_LICENSING_V3_IN_OP_UPDATE_LICENSE 0x0 13433 /* enum: report counts of installed licenses Returns EAGAIN if license 13434 * processing (updating) has been started but not yet completed. 13435 */ 13436 #define MC_CMD_LICENSING_V3_IN_OP_REPORT_LICENSE 0x1 13437 13438 /* MC_CMD_LICENSING_V3_OUT msgresponse */ 13439 #define MC_CMD_LICENSING_V3_OUT_LEN 88 13440 /* count of keys which are valid */ 13441 #define MC_CMD_LICENSING_V3_OUT_VALID_KEYS_OFST 0 13442 /* sum of UNVERIFIABLE_KEYS + WRONG_NODE_KEYS (for compatibility with 13443 * MC_CMD_FC_OP_LICENSE) 13444 */ 13445 #define MC_CMD_LICENSING_V3_OUT_INVALID_KEYS_OFST 4 13446 /* count of keys which are invalid due to being unverifiable */ 13447 #define MC_CMD_LICENSING_V3_OUT_UNVERIFIABLE_KEYS_OFST 8 13448 /* count of keys which are invalid due to being for the wrong node */ 13449 #define MC_CMD_LICENSING_V3_OUT_WRONG_NODE_KEYS_OFST 12 13450 /* licensing state (for diagnostics; the exact meaning of the bits in this 13451 * field are private to the firmware) 13452 */ 13453 #define MC_CMD_LICENSING_V3_OUT_LICENSING_STATE_OFST 16 13454 /* licensing subsystem self-test report (for manftest) */ 13455 #define MC_CMD_LICENSING_V3_OUT_LICENSING_SELF_TEST_OFST 20 13456 /* enum: licensing subsystem self-test failed */ 13457 #define MC_CMD_LICENSING_V3_OUT_SELF_TEST_FAIL 0x0 13458 /* enum: licensing subsystem self-test passed */ 13459 #define MC_CMD_LICENSING_V3_OUT_SELF_TEST_PASS 0x1 13460 /* bitmask of licensed applications */ 13461 #define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_OFST 24 13462 #define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LEN 8 13463 #define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LO_OFST 24 13464 #define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_HI_OFST 28 13465 /* reserved for future use */ 13466 #define MC_CMD_LICENSING_V3_OUT_RESERVED_0_OFST 32 13467 #define MC_CMD_LICENSING_V3_OUT_RESERVED_0_LEN 24 13468 /* bitmask of licensed features */ 13469 #define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_OFST 56 13470 #define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LEN 8 13471 #define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LO_OFST 56 13472 #define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_HI_OFST 60 13473 /* reserved for future use */ 13474 #define MC_CMD_LICENSING_V3_OUT_RESERVED_1_OFST 64 13475 #define MC_CMD_LICENSING_V3_OUT_RESERVED_1_LEN 24 13476 13477 13478 /***********************************/ 13479 /* MC_CMD_LICENSING_GET_ID_V3 13480 * Get ID and type from the NVRAM_PARTITION_TYPE_LICENSE application license 13481 * partition - V3 licensing (Medford) 13482 */ 13483 #define MC_CMD_LICENSING_GET_ID_V3 0xd1 13484 #undef MC_CMD_0xd1_PRIVILEGE_CTG 13485 13486 #define MC_CMD_0xd1_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13487 13488 /* MC_CMD_LICENSING_GET_ID_V3_IN msgrequest */ 13489 #define MC_CMD_LICENSING_GET_ID_V3_IN_LEN 0 13490 13491 /* MC_CMD_LICENSING_GET_ID_V3_OUT msgresponse */ 13492 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LENMIN 8 13493 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LENMAX 252 13494 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LEN(num) (8+1*(num)) 13495 /* type of license (eg 3) */ 13496 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_TYPE_OFST 0 13497 /* length of the license ID (in bytes) */ 13498 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_LENGTH_OFST 4 13499 /* the unique license ID of the adapter */ 13500 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_OFST 8 13501 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_LEN 1 13502 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_MINNUM 0 13503 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_MAXNUM 244 13504 13505 13506 /***********************************/ 13507 /* MC_CMD_MC2MC_PROXY 13508 * Execute an arbitrary MCDI command on the slave MC of a dual-core device. 13509 * This will fail on a single-core system. 13510 */ 13511 #define MC_CMD_MC2MC_PROXY 0xf4 13512 #undef MC_CMD_0xf4_PRIVILEGE_CTG 13513 13514 #define MC_CMD_0xf4_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13515 13516 /* MC_CMD_MC2MC_PROXY_IN msgrequest */ 13517 #define MC_CMD_MC2MC_PROXY_IN_LEN 0 13518 13519 /* MC_CMD_MC2MC_PROXY_OUT msgresponse */ 13520 #define MC_CMD_MC2MC_PROXY_OUT_LEN 0 13521 13522 13523 /***********************************/ 13524 /* MC_CMD_GET_LICENSED_APP_STATE 13525 * Query the state of an individual licensed application. (Note that the actual 13526 * state may be invalidated by the MC_CMD_LICENSING OP_UPDATE_LICENSE operation 13527 * or a reboot of the MC.) Not used for V3 licensing 13528 */ 13529 #define MC_CMD_GET_LICENSED_APP_STATE 0xf5 13530 #undef MC_CMD_0xf5_PRIVILEGE_CTG 13531 13532 #define MC_CMD_0xf5_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13533 13534 /* MC_CMD_GET_LICENSED_APP_STATE_IN msgrequest */ 13535 #define MC_CMD_GET_LICENSED_APP_STATE_IN_LEN 4 13536 /* application ID to query (LICENSED_APP_ID_xxx) */ 13537 #define MC_CMD_GET_LICENSED_APP_STATE_IN_APP_ID_OFST 0 13538 13539 /* MC_CMD_GET_LICENSED_APP_STATE_OUT msgresponse */ 13540 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_LEN 4 13541 /* state of this application */ 13542 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_STATE_OFST 0 13543 /* enum: no (or invalid) license is present for the application */ 13544 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_NOT_LICENSED 0x0 13545 /* enum: a valid license is present for the application */ 13546 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_LICENSED 0x1 13547 13548 13549 /***********************************/ 13550 /* MC_CMD_GET_LICENSED_V3_APP_STATE 13551 * Query the state of an individual licensed application. (Note that the actual 13552 * state may be invalidated by the MC_CMD_LICENSING_V3 OP_UPDATE_LICENSE 13553 * operation or a reboot of the MC.) Used for V3 licensing (Medford) 13554 */ 13555 #define MC_CMD_GET_LICENSED_V3_APP_STATE 0xd2 13556 #undef MC_CMD_0xd2_PRIVILEGE_CTG 13557 13558 #define MC_CMD_0xd2_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13559 13560 /* MC_CMD_GET_LICENSED_V3_APP_STATE_IN msgrequest */ 13561 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_LEN 8 13562 /* application ID to query (LICENSED_V3_APPS_xxx) expressed as a single bit 13563 * mask 13564 */ 13565 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_OFST 0 13566 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LEN 8 13567 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LO_OFST 0 13568 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_HI_OFST 4 13569 13570 /* MC_CMD_GET_LICENSED_V3_APP_STATE_OUT msgresponse */ 13571 #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_LEN 4 13572 /* state of this application */ 13573 #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_STATE_OFST 0 13574 /* enum: no (or invalid) license is present for the application */ 13575 #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_NOT_LICENSED 0x0 13576 /* enum: a valid license is present for the application */ 13577 #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_LICENSED 0x1 13578 13579 13580 /***********************************/ 13581 /* MC_CMD_GET_LICENSED_V3_FEATURE_STATES 13582 * Query the state of an one or more licensed features. (Note that the actual 13583 * state may be invalidated by the MC_CMD_LICENSING_V3 OP_UPDATE_LICENSE 13584 * operation or a reboot of the MC.) Used for V3 licensing (Medford) 13585 */ 13586 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES 0xd3 13587 #undef MC_CMD_0xd3_PRIVILEGE_CTG 13588 13589 #define MC_CMD_0xd3_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13590 13591 /* MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN msgrequest */ 13592 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_LEN 8 13593 /* features to query (LICENSED_V3_FEATURES_xxx) expressed as a mask with one or 13594 * more bits set 13595 */ 13596 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_OFST 0 13597 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LEN 8 13598 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LO_OFST 0 13599 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_HI_OFST 4 13600 13601 /* MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT msgresponse */ 13602 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_LEN 8 13603 /* states of these features - bit set for licensed, clear for not licensed */ 13604 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_OFST 0 13605 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LEN 8 13606 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LO_OFST 0 13607 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_HI_OFST 4 13608 13609 13610 /***********************************/ 13611 /* MC_CMD_LICENSED_APP_OP 13612 * Perform an action for an individual licensed application - not used for V3 13613 * licensing. 13614 */ 13615 #define MC_CMD_LICENSED_APP_OP 0xf6 13616 #undef MC_CMD_0xf6_PRIVILEGE_CTG 13617 13618 #define MC_CMD_0xf6_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13619 13620 /* MC_CMD_LICENSED_APP_OP_IN msgrequest */ 13621 #define MC_CMD_LICENSED_APP_OP_IN_LENMIN 8 13622 #define MC_CMD_LICENSED_APP_OP_IN_LENMAX 252 13623 #define MC_CMD_LICENSED_APP_OP_IN_LEN(num) (8+4*(num)) 13624 /* application ID */ 13625 #define MC_CMD_LICENSED_APP_OP_IN_APP_ID_OFST 0 13626 /* the type of operation requested */ 13627 #define MC_CMD_LICENSED_APP_OP_IN_OP_OFST 4 13628 /* enum: validate application */ 13629 #define MC_CMD_LICENSED_APP_OP_IN_OP_VALIDATE 0x0 13630 /* enum: mask application */ 13631 #define MC_CMD_LICENSED_APP_OP_IN_OP_MASK 0x1 13632 /* arguments specific to this particular operation */ 13633 #define MC_CMD_LICENSED_APP_OP_IN_ARGS_OFST 8 13634 #define MC_CMD_LICENSED_APP_OP_IN_ARGS_LEN 4 13635 #define MC_CMD_LICENSED_APP_OP_IN_ARGS_MINNUM 0 13636 #define MC_CMD_LICENSED_APP_OP_IN_ARGS_MAXNUM 61 13637 13638 /* MC_CMD_LICENSED_APP_OP_OUT msgresponse */ 13639 #define MC_CMD_LICENSED_APP_OP_OUT_LENMIN 0 13640 #define MC_CMD_LICENSED_APP_OP_OUT_LENMAX 252 13641 #define MC_CMD_LICENSED_APP_OP_OUT_LEN(num) (0+4*(num)) 13642 /* result specific to this particular operation */ 13643 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_OFST 0 13644 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_LEN 4 13645 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_MINNUM 0 13646 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_MAXNUM 63 13647 13648 /* MC_CMD_LICENSED_APP_OP_VALIDATE_IN msgrequest */ 13649 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_LEN 72 13650 /* application ID */ 13651 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_APP_ID_OFST 0 13652 /* the type of operation requested */ 13653 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_OP_OFST 4 13654 /* validation challenge */ 13655 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_CHALLENGE_OFST 8 13656 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_CHALLENGE_LEN 64 13657 13658 /* MC_CMD_LICENSED_APP_OP_VALIDATE_OUT msgresponse */ 13659 #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_LEN 68 13660 /* feature expiry (time_t) */ 13661 #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_EXPIRY_OFST 0 13662 /* validation response */ 13663 #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_RESPONSE_OFST 4 13664 #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_RESPONSE_LEN 64 13665 13666 /* MC_CMD_LICENSED_APP_OP_MASK_IN msgrequest */ 13667 #define MC_CMD_LICENSED_APP_OP_MASK_IN_LEN 12 13668 /* application ID */ 13669 #define MC_CMD_LICENSED_APP_OP_MASK_IN_APP_ID_OFST 0 13670 /* the type of operation requested */ 13671 #define MC_CMD_LICENSED_APP_OP_MASK_IN_OP_OFST 4 13672 /* flag */ 13673 #define MC_CMD_LICENSED_APP_OP_MASK_IN_FLAG_OFST 8 13674 13675 /* MC_CMD_LICENSED_APP_OP_MASK_OUT msgresponse */ 13676 #define MC_CMD_LICENSED_APP_OP_MASK_OUT_LEN 0 13677 13678 13679 /***********************************/ 13680 /* MC_CMD_LICENSED_V3_VALIDATE_APP 13681 * Perform validation for an individual licensed application - V3 licensing 13682 * (Medford) 13683 */ 13684 #define MC_CMD_LICENSED_V3_VALIDATE_APP 0xd4 13685 #undef MC_CMD_0xd4_PRIVILEGE_CTG 13686 13687 #define MC_CMD_0xd4_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13688 13689 /* MC_CMD_LICENSED_V3_VALIDATE_APP_IN msgrequest */ 13690 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_LEN 56 13691 /* challenge for validation (384 bits) */ 13692 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_CHALLENGE_OFST 0 13693 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_CHALLENGE_LEN 48 13694 /* application ID expressed as a single bit mask */ 13695 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_OFST 48 13696 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LEN 8 13697 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LO_OFST 48 13698 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_HI_OFST 52 13699 13700 /* MC_CMD_LICENSED_V3_VALIDATE_APP_OUT msgresponse */ 13701 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_LEN 116 13702 /* validation response to challenge in the form of ECDSA signature consisting 13703 * of two 384-bit integers, r and s, in big-endian order. The signature signs a 13704 * SHA-384 digest of a message constructed from the concatenation of the input 13705 * message and the remaining fields of this output message, e.g. challenge[48 13706 * bytes] ... expiry_time[4 bytes] ... 13707 */ 13708 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_RESPONSE_OFST 0 13709 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_RESPONSE_LEN 96 13710 /* application expiry time */ 13711 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_TIME_OFST 96 13712 /* application expiry units */ 13713 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNITS_OFST 100 13714 /* enum: expiry units are accounting units */ 13715 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNIT_ACC 0x0 13716 /* enum: expiry units are calendar days */ 13717 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNIT_DAYS 0x1 13718 /* base MAC address of the NIC stored in NVRAM (note that this is a constant 13719 * value for a given NIC regardless which function is calling, effectively this 13720 * is PF0 base MAC address) 13721 */ 13722 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_BASE_MACADDR_OFST 104 13723 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_BASE_MACADDR_LEN 6 13724 /* MAC address of v-adaptor associated with the client. If no such v-adapator 13725 * exists, then the field is filled with 0xFF. 13726 */ 13727 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_VADAPTOR_MACADDR_OFST 110 13728 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_VADAPTOR_MACADDR_LEN 6 13729 13730 13731 /***********************************/ 13732 /* MC_CMD_LICENSED_V3_MASK_FEATURES 13733 * Mask features - V3 licensing (Medford) 13734 */ 13735 #define MC_CMD_LICENSED_V3_MASK_FEATURES 0xd5 13736 #undef MC_CMD_0xd5_PRIVILEGE_CTG 13737 13738 #define MC_CMD_0xd5_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13739 13740 /* MC_CMD_LICENSED_V3_MASK_FEATURES_IN msgrequest */ 13741 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_LEN 12 13742 /* mask to be applied to features to be changed */ 13743 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_OFST 0 13744 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LEN 8 13745 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LO_OFST 0 13746 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_HI_OFST 4 13747 /* whether to turn on or turn off the masked features */ 13748 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_FLAG_OFST 8 13749 /* enum: turn the features off */ 13750 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_OFF 0x0 13751 /* enum: turn the features back on */ 13752 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_ON 0x1 13753 13754 /* MC_CMD_LICENSED_V3_MASK_FEATURES_OUT msgresponse */ 13755 #define MC_CMD_LICENSED_V3_MASK_FEATURES_OUT_LEN 0 13756 13757 13758 /***********************************/ 13759 /* MC_CMD_LICENSING_V3_TEMPORARY 13760 * Perform operations to support installation of a single temporary license in 13761 * the adapter, in addition to those found in the licensing partition. See 13762 * SF-116124-SW for an overview of how this could be used. The license is 13763 * stored in MC persistent data and so will survive a MC reboot, but will be 13764 * erased when the adapter is power cycled 13765 */ 13766 #define MC_CMD_LICENSING_V3_TEMPORARY 0xd6 13767 #undef MC_CMD_0xd6_PRIVILEGE_CTG 13768 13769 #define MC_CMD_0xd6_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13770 13771 /* MC_CMD_LICENSING_V3_TEMPORARY_IN msgrequest */ 13772 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_LEN 4 13773 /* operation code */ 13774 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_OP_OFST 0 13775 /* enum: install a new license, overwriting any existing temporary license. 13776 * This is an asynchronous operation owing to the time taken to validate an 13777 * ECDSA license 13778 */ 13779 #define MC_CMD_LICENSING_V3_TEMPORARY_SET 0x0 13780 /* enum: clear the license immediately rather than waiting for the next power 13781 * cycle 13782 */ 13783 #define MC_CMD_LICENSING_V3_TEMPORARY_CLEAR 0x1 13784 /* enum: get the status of the asynchronous MC_CMD_LICENSING_V3_TEMPORARY_SET 13785 * operation 13786 */ 13787 #define MC_CMD_LICENSING_V3_TEMPORARY_STATUS 0x2 13788 13789 /* MC_CMD_LICENSING_V3_TEMPORARY_IN_SET msgrequest */ 13790 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_LEN 164 13791 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_OP_OFST 0 13792 /* ECDSA license and signature */ 13793 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_LICENSE_OFST 4 13794 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_LICENSE_LEN 160 13795 13796 /* MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR msgrequest */ 13797 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR_LEN 4 13798 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR_OP_OFST 0 13799 13800 /* MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS msgrequest */ 13801 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS_LEN 4 13802 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS_OP_OFST 0 13803 13804 /* MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS msgresponse */ 13805 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LEN 12 13806 /* status code */ 13807 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_STATUS_OFST 0 13808 /* enum: finished validating and installing license */ 13809 #define MC_CMD_LICENSING_V3_TEMPORARY_STATUS_OK 0x0 13810 /* enum: license validation and installation in progress */ 13811 #define MC_CMD_LICENSING_V3_TEMPORARY_STATUS_IN_PROGRESS 0x1 13812 /* enum: licensing error. More specific error messages are not provided to 13813 * avoid exposing details of the licensing system to the client 13814 */ 13815 #define MC_CMD_LICENSING_V3_TEMPORARY_STATUS_ERROR 0x2 13816 /* bitmask of licensed features */ 13817 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_OFST 4 13818 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_LEN 8 13819 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_LO_OFST 4 13820 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_HI_OFST 8 13821 13822 13823 /***********************************/ 13824 /* MC_CMD_SET_PORT_SNIFF_CONFIG 13825 * Configure RX port sniffing for the physical port associated with the calling 13826 * function. Only a privileged function may change the port sniffing 13827 * configuration. A copy of all traffic delivered to the host (non-promiscuous 13828 * mode) or all traffic arriving at the port (promiscuous mode) may be 13829 * delivered to a specific queue, or a set of queues with RSS. 13830 */ 13831 #define MC_CMD_SET_PORT_SNIFF_CONFIG 0xf7 13832 #undef MC_CMD_0xf7_PRIVILEGE_CTG 13833 13834 #define MC_CMD_0xf7_PRIVILEGE_CTG SRIOV_CTG_ADMIN 13835 13836 /* MC_CMD_SET_PORT_SNIFF_CONFIG_IN msgrequest */ 13837 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_LEN 16 13838 /* configuration flags */ 13839 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_FLAGS_OFST 0 13840 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_ENABLE_LBN 0 13841 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_ENABLE_WIDTH 1 13842 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_PROMISCUOUS_LBN 1 13843 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_PROMISCUOUS_WIDTH 1 13844 /* receive queue handle (for RSS mode, this is the base queue) */ 13845 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_QUEUE_OFST 4 13846 /* receive mode */ 13847 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_OFST 8 13848 /* enum: receive to just the specified queue */ 13849 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_SIMPLE 0x0 13850 /* enum: receive to multiple queues using RSS context */ 13851 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_RSS 0x1 13852 /* RSS context (for RX_MODE_RSS) as returned by MC_CMD_RSS_CONTEXT_ALLOC. Note 13853 * that these handles should be considered opaque to the host, although a value 13854 * of 0xFFFFFFFF is guaranteed never to be a valid handle. 13855 */ 13856 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_OFST 12 13857 13858 /* MC_CMD_SET_PORT_SNIFF_CONFIG_OUT msgresponse */ 13859 #define MC_CMD_SET_PORT_SNIFF_CONFIG_OUT_LEN 0 13860 13861 13862 /***********************************/ 13863 /* MC_CMD_GET_PORT_SNIFF_CONFIG 13864 * Obtain the current RX port sniffing configuration for the physical port 13865 * associated with the calling function. Only a privileged function may read 13866 * the configuration. 13867 */ 13868 #define MC_CMD_GET_PORT_SNIFF_CONFIG 0xf8 13869 #undef MC_CMD_0xf8_PRIVILEGE_CTG 13870 13871 #define MC_CMD_0xf8_PRIVILEGE_CTG SRIOV_CTG_ADMIN 13872 13873 /* MC_CMD_GET_PORT_SNIFF_CONFIG_IN msgrequest */ 13874 #define MC_CMD_GET_PORT_SNIFF_CONFIG_IN_LEN 0 13875 13876 /* MC_CMD_GET_PORT_SNIFF_CONFIG_OUT msgresponse */ 13877 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_LEN 16 13878 /* configuration flags */ 13879 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_FLAGS_OFST 0 13880 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_ENABLE_LBN 0 13881 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_ENABLE_WIDTH 1 13882 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_PROMISCUOUS_LBN 1 13883 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_PROMISCUOUS_WIDTH 1 13884 /* receiving queue handle (for RSS mode, this is the base queue) */ 13885 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_OFST 4 13886 /* receive mode */ 13887 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_OFST 8 13888 /* enum: receiving to just the specified queue */ 13889 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_SIMPLE 0x0 13890 /* enum: receiving to multiple queues using RSS context */ 13891 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_RSS 0x1 13892 /* RSS context (for RX_MODE_RSS) */ 13893 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_OFST 12 13894 13895 13896 /***********************************/ 13897 /* MC_CMD_SET_PARSER_DISP_CONFIG 13898 * Change configuration related to the parser-dispatcher subsystem. 13899 */ 13900 #define MC_CMD_SET_PARSER_DISP_CONFIG 0xf9 13901 #undef MC_CMD_0xf9_PRIVILEGE_CTG 13902 13903 #define MC_CMD_0xf9_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13904 13905 /* MC_CMD_SET_PARSER_DISP_CONFIG_IN msgrequest */ 13906 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LENMIN 12 13907 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LENMAX 252 13908 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LEN(num) (8+4*(num)) 13909 /* the type of configuration setting to change */ 13910 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_TYPE_OFST 0 13911 /* enum: Per-TXQ enable for multicast UDP destination lookup for possible 13912 * internal loopback. (ENTITY is a queue handle, VALUE is a single boolean.) 13913 */ 13914 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_TXQ_MCAST_UDP_DST_LOOKUP_EN 0x0 13915 /* enum: Per-v-adaptor enable for suppression of self-transmissions on the 13916 * internal loopback path. (ENTITY is an EVB_PORT_ID, VALUE is a single 13917 * boolean.) 13918 */ 13919 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VADAPTOR_SUPPRESS_SELF_TX 0x1 13920 /* handle for the entity to update: queue handle, EVB port ID, etc. depending 13921 * on the type of configuration setting being changed 13922 */ 13923 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_ENTITY_OFST 4 13924 /* new value: the details depend on the type of configuration setting being 13925 * changed 13926 */ 13927 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_OFST 8 13928 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_LEN 4 13929 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_MINNUM 1 13930 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_MAXNUM 61 13931 13932 /* MC_CMD_SET_PARSER_DISP_CONFIG_OUT msgresponse */ 13933 #define MC_CMD_SET_PARSER_DISP_CONFIG_OUT_LEN 0 13934 13935 13936 /***********************************/ 13937 /* MC_CMD_GET_PARSER_DISP_CONFIG 13938 * Read configuration related to the parser-dispatcher subsystem. 13939 */ 13940 #define MC_CMD_GET_PARSER_DISP_CONFIG 0xfa 13941 #undef MC_CMD_0xfa_PRIVILEGE_CTG 13942 13943 #define MC_CMD_0xfa_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13944 13945 /* MC_CMD_GET_PARSER_DISP_CONFIG_IN msgrequest */ 13946 #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_LEN 8 13947 /* the type of configuration setting to read */ 13948 #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_TYPE_OFST 0 13949 /* Enum values, see field(s): */ 13950 /* MC_CMD_SET_PARSER_DISP_CONFIG/MC_CMD_SET_PARSER_DISP_CONFIG_IN/TYPE */ 13951 /* handle for the entity to query: queue handle, EVB port ID, etc. depending on 13952 * the type of configuration setting being read 13953 */ 13954 #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_ENTITY_OFST 4 13955 13956 /* MC_CMD_GET_PARSER_DISP_CONFIG_OUT msgresponse */ 13957 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LENMIN 4 13958 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LENMAX 252 13959 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LEN(num) (0+4*(num)) 13960 /* current value: the details depend on the type of configuration setting being 13961 * read 13962 */ 13963 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_OFST 0 13964 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_LEN 4 13965 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_MINNUM 1 13966 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_MAXNUM 63 13967 13968 13969 /***********************************/ 13970 /* MC_CMD_SET_TX_PORT_SNIFF_CONFIG 13971 * Configure TX port sniffing for the physical port associated with the calling 13972 * function. Only a privileged function may change the port sniffing 13973 * configuration. A copy of all traffic transmitted through the port may be 13974 * delivered to a specific queue, or a set of queues with RSS. Note that these 13975 * packets are delivered with transmit timestamps in the packet prefix, not 13976 * receive timestamps, so it is likely that the queue(s) will need to be 13977 * dedicated as TX sniff receivers. 13978 */ 13979 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG 0xfb 13980 #undef MC_CMD_0xfb_PRIVILEGE_CTG 13981 13982 #define MC_CMD_0xfb_PRIVILEGE_CTG SRIOV_CTG_ADMIN 13983 13984 /* MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN msgrequest */ 13985 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_LEN 16 13986 /* configuration flags */ 13987 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_FLAGS_OFST 0 13988 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_ENABLE_LBN 0 13989 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_ENABLE_WIDTH 1 13990 /* receive queue handle (for RSS mode, this is the base queue) */ 13991 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_QUEUE_OFST 4 13992 /* receive mode */ 13993 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_OFST 8 13994 /* enum: receive to just the specified queue */ 13995 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_SIMPLE 0x0 13996 /* enum: receive to multiple queues using RSS context */ 13997 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_RSS 0x1 13998 /* RSS context (for RX_MODE_RSS) as returned by MC_CMD_RSS_CONTEXT_ALLOC. Note 13999 * that these handles should be considered opaque to the host, although a value 14000 * of 0xFFFFFFFF is guaranteed never to be a valid handle. 14001 */ 14002 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_OFST 12 14003 14004 /* MC_CMD_SET_TX_PORT_SNIFF_CONFIG_OUT msgresponse */ 14005 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_OUT_LEN 0 14006 14007 14008 /***********************************/ 14009 /* MC_CMD_GET_TX_PORT_SNIFF_CONFIG 14010 * Obtain the current TX port sniffing configuration for the physical port 14011 * associated with the calling function. Only a privileged function may read 14012 * the configuration. 14013 */ 14014 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG 0xfc 14015 #undef MC_CMD_0xfc_PRIVILEGE_CTG 14016 14017 #define MC_CMD_0xfc_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14018 14019 /* MC_CMD_GET_TX_PORT_SNIFF_CONFIG_IN msgrequest */ 14020 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_IN_LEN 0 14021 14022 /* MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT msgresponse */ 14023 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_LEN 16 14024 /* configuration flags */ 14025 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_FLAGS_OFST 0 14026 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_ENABLE_LBN 0 14027 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_ENABLE_WIDTH 1 14028 /* receiving queue handle (for RSS mode, this is the base queue) */ 14029 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_OFST 4 14030 /* receive mode */ 14031 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_OFST 8 14032 /* enum: receiving to just the specified queue */ 14033 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_SIMPLE 0x0 14034 /* enum: receiving to multiple queues using RSS context */ 14035 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_RSS 0x1 14036 /* RSS context (for RX_MODE_RSS) */ 14037 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_OFST 12 14038 14039 14040 /***********************************/ 14041 /* MC_CMD_RMON_STATS_RX_ERRORS 14042 * Per queue rx error stats. 14043 */ 14044 #define MC_CMD_RMON_STATS_RX_ERRORS 0xfe 14045 #undef MC_CMD_0xfe_PRIVILEGE_CTG 14046 14047 #define MC_CMD_0xfe_PRIVILEGE_CTG SRIOV_CTG_GENERAL 14048 14049 /* MC_CMD_RMON_STATS_RX_ERRORS_IN msgrequest */ 14050 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_LEN 8 14051 /* The rx queue to get stats for. */ 14052 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_RX_QUEUE_OFST 0 14053 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_FLAGS_OFST 4 14054 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_RST_LBN 0 14055 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_RST_WIDTH 1 14056 14057 /* MC_CMD_RMON_STATS_RX_ERRORS_OUT msgresponse */ 14058 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_LEN 16 14059 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_CRC_ERRORS_OFST 0 14060 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_TRUNC_ERRORS_OFST 4 14061 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_NO_DESC_DROPS_OFST 8 14062 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_ABORT_OFST 12 14063 14064 14065 /***********************************/ 14066 /* MC_CMD_GET_PCIE_RESOURCE_INFO 14067 * Find out about available PCIE resources 14068 */ 14069 #define MC_CMD_GET_PCIE_RESOURCE_INFO 0xfd 14070 14071 /* MC_CMD_GET_PCIE_RESOURCE_INFO_IN msgrequest */ 14072 #define MC_CMD_GET_PCIE_RESOURCE_INFO_IN_LEN 0 14073 14074 /* MC_CMD_GET_PCIE_RESOURCE_INFO_OUT msgresponse */ 14075 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_LEN 28 14076 /* The maximum number of PFs the device can expose */ 14077 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PFS_OFST 0 14078 /* The maximum number of VFs the device can expose in total */ 14079 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VFS_OFST 4 14080 /* The maximum number of MSI-X vectors the device can provide in total */ 14081 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VECTORS_OFST 8 14082 /* the number of MSI-X vectors the device will allocate by default to each PF 14083 */ 14084 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_PF_VECTORS_OFST 12 14085 /* the number of MSI-X vectors the device will allocate by default to each VF 14086 */ 14087 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_VF_VECTORS_OFST 16 14088 /* the maximum number of MSI-X vectors the device can allocate to any one PF */ 14089 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PF_VECTORS_OFST 20 14090 /* the maximum number of MSI-X vectors the device can allocate to any one VF */ 14091 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VF_VECTORS_OFST 24 14092 14093 14094 /***********************************/ 14095 /* MC_CMD_GET_PORT_MODES 14096 * Find out about available port modes 14097 */ 14098 #define MC_CMD_GET_PORT_MODES 0xff 14099 #undef MC_CMD_0xff_PRIVILEGE_CTG 14100 14101 #define MC_CMD_0xff_PRIVILEGE_CTG SRIOV_CTG_GENERAL 14102 14103 /* MC_CMD_GET_PORT_MODES_IN msgrequest */ 14104 #define MC_CMD_GET_PORT_MODES_IN_LEN 0 14105 14106 /* MC_CMD_GET_PORT_MODES_OUT msgresponse */ 14107 #define MC_CMD_GET_PORT_MODES_OUT_LEN 12 14108 /* Bitmask of port modes available on the board (indexed by TLV_PORT_MODE_*) */ 14109 #define MC_CMD_GET_PORT_MODES_OUT_MODES_OFST 0 14110 /* Default (canonical) board mode */ 14111 #define MC_CMD_GET_PORT_MODES_OUT_DEFAULT_MODE_OFST 4 14112 /* Current board mode */ 14113 #define MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST 8 14114 14115 14116 /***********************************/ 14117 /* MC_CMD_READ_ATB 14118 * Sample voltages on the ATB 14119 */ 14120 #define MC_CMD_READ_ATB 0x100 14121 #undef MC_CMD_0x100_PRIVILEGE_CTG 14122 14123 #define MC_CMD_0x100_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14124 14125 /* MC_CMD_READ_ATB_IN msgrequest */ 14126 #define MC_CMD_READ_ATB_IN_LEN 16 14127 #define MC_CMD_READ_ATB_IN_SIGNAL_BUS_OFST 0 14128 #define MC_CMD_READ_ATB_IN_BUS_CCOM 0x0 /* enum */ 14129 #define MC_CMD_READ_ATB_IN_BUS_CKR 0x1 /* enum */ 14130 #define MC_CMD_READ_ATB_IN_BUS_CPCIE 0x8 /* enum */ 14131 #define MC_CMD_READ_ATB_IN_SIGNAL_EN_BITNO_OFST 4 14132 #define MC_CMD_READ_ATB_IN_SIGNAL_SEL_OFST 8 14133 #define MC_CMD_READ_ATB_IN_SETTLING_TIME_US_OFST 12 14134 14135 /* MC_CMD_READ_ATB_OUT msgresponse */ 14136 #define MC_CMD_READ_ATB_OUT_LEN 4 14137 #define MC_CMD_READ_ATB_OUT_SAMPLE_MV_OFST 0 14138 14139 14140 /***********************************/ 14141 /* MC_CMD_GET_WORKAROUNDS 14142 * Read the list of all implemented and all currently enabled workarounds. The 14143 * enums here must correspond with those in MC_CMD_WORKAROUND. 14144 */ 14145 #define MC_CMD_GET_WORKAROUNDS 0x59 14146 #undef MC_CMD_0x59_PRIVILEGE_CTG 14147 14148 #define MC_CMD_0x59_PRIVILEGE_CTG SRIOV_CTG_GENERAL 14149 14150 /* MC_CMD_GET_WORKAROUNDS_OUT msgresponse */ 14151 #define MC_CMD_GET_WORKAROUNDS_OUT_LEN 8 14152 /* Each workaround is represented by a single bit according to the enums below. 14153 */ 14154 #define MC_CMD_GET_WORKAROUNDS_OUT_IMPLEMENTED_OFST 0 14155 #define MC_CMD_GET_WORKAROUNDS_OUT_ENABLED_OFST 4 14156 /* enum: Bug 17230 work around. */ 14157 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG17230 0x2 14158 /* enum: Bug 35388 work around (unsafe EVQ writes). */ 14159 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG35388 0x4 14160 /* enum: Bug35017 workaround (A64 tables must be identity map) */ 14161 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG35017 0x8 14162 /* enum: Bug 41750 present (MC_CMD_TRIGGER_INTERRUPT won't work) */ 14163 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG41750 0x10 14164 /* enum: Bug 42008 present (Interrupts can overtake associated events). Caution 14165 * - before adding code that queries this workaround, remember that there's 14166 * released Monza firmware that doesn't understand MC_CMD_WORKAROUND_BUG42008, 14167 * and will hence (incorrectly) report that the bug doesn't exist. 14168 */ 14169 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG42008 0x20 14170 /* enum: Bug 26807 features present in firmware (multicast filter chaining) */ 14171 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG26807 0x40 14172 /* enum: Bug 61265 work around (broken EVQ TMR writes). */ 14173 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG61265 0x80 14174 14175 14176 /***********************************/ 14177 /* MC_CMD_PRIVILEGE_MASK 14178 * Read/set privileges of an arbitrary PCIe function 14179 */ 14180 #define MC_CMD_PRIVILEGE_MASK 0x5a 14181 #undef MC_CMD_0x5a_PRIVILEGE_CTG 14182 14183 #define MC_CMD_0x5a_PRIVILEGE_CTG SRIOV_CTG_GENERAL 14184 14185 /* MC_CMD_PRIVILEGE_MASK_IN msgrequest */ 14186 #define MC_CMD_PRIVILEGE_MASK_IN_LEN 8 14187 /* The target function to have its mask read or set e.g. PF 0 = 0xFFFF0000, VF 14188 * 1,3 = 0x00030001 14189 */ 14190 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_OFST 0 14191 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_PF_LBN 0 14192 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_PF_WIDTH 16 14193 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_VF_LBN 16 14194 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_VF_WIDTH 16 14195 #define MC_CMD_PRIVILEGE_MASK_IN_VF_NULL 0xffff /* enum */ 14196 /* New privilege mask to be set. The mask will only be changed if the MSB is 14197 * set to 1. 14198 */ 14199 #define MC_CMD_PRIVILEGE_MASK_IN_NEW_MASK_OFST 4 14200 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN 0x1 /* enum */ 14201 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_LINK 0x2 /* enum */ 14202 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ONLOAD 0x4 /* enum */ 14203 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_PTP 0x8 /* enum */ 14204 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE_FILTERS 0x10 /* enum */ 14205 /* enum: Deprecated. Equivalent to MAC_SPOOFING_TX combined with CHANGE_MAC. */ 14206 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING 0x20 14207 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_UNICAST 0x40 /* enum */ 14208 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_MULTICAST 0x80 /* enum */ 14209 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_BROADCAST 0x100 /* enum */ 14210 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ALL_MULTICAST 0x200 /* enum */ 14211 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_PROMISCUOUS 0x400 /* enum */ 14212 /* enum: Allows to set the TX packets' source MAC address to any arbitrary MAC 14213 * adress. 14214 */ 14215 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING_TX 0x800 14216 /* enum: Privilege that allows a Function to change the MAC address configured 14217 * in its associated vAdapter/vPort. 14218 */ 14219 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_CHANGE_MAC 0x1000 14220 /* enum: Privilege that allows a Function to install filters that specify VLANs 14221 * that are not in the permit list for the associated vPort. This privilege is 14222 * primarily to support ESX where vPorts are created that restrict traffic to 14223 * only a set of permitted VLANs. See the vPort flag FLAG_VLAN_RESTRICT. 14224 */ 14225 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_UNRESTRICTED_VLAN 0x2000 14226 /* enum: Set this bit to indicate that a new privilege mask is to be set, 14227 * otherwise the command will only read the existing mask. 14228 */ 14229 #define MC_CMD_PRIVILEGE_MASK_IN_DO_CHANGE 0x80000000 14230 14231 /* MC_CMD_PRIVILEGE_MASK_OUT msgresponse */ 14232 #define MC_CMD_PRIVILEGE_MASK_OUT_LEN 4 14233 /* For an admin function, always all the privileges are reported. */ 14234 #define MC_CMD_PRIVILEGE_MASK_OUT_OLD_MASK_OFST 0 14235 14236 14237 /***********************************/ 14238 /* MC_CMD_LINK_STATE_MODE 14239 * Read/set link state mode of a VF 14240 */ 14241 #define MC_CMD_LINK_STATE_MODE 0x5c 14242 #undef MC_CMD_0x5c_PRIVILEGE_CTG 14243 14244 #define MC_CMD_0x5c_PRIVILEGE_CTG SRIOV_CTG_GENERAL 14245 14246 /* MC_CMD_LINK_STATE_MODE_IN msgrequest */ 14247 #define MC_CMD_LINK_STATE_MODE_IN_LEN 8 14248 /* The target function to have its link state mode read or set, must be a VF 14249 * e.g. VF 1,3 = 0x00030001 14250 */ 14251 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_OFST 0 14252 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_LBN 0 14253 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_WIDTH 16 14254 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_VF_LBN 16 14255 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_VF_WIDTH 16 14256 /* New link state mode to be set */ 14257 #define MC_CMD_LINK_STATE_MODE_IN_NEW_MODE_OFST 4 14258 #define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_AUTO 0x0 /* enum */ 14259 #define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_UP 0x1 /* enum */ 14260 #define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_DOWN 0x2 /* enum */ 14261 /* enum: Use this value to just read the existing setting without modifying it. 14262 */ 14263 #define MC_CMD_LINK_STATE_MODE_IN_DO_NOT_CHANGE 0xffffffff 14264 14265 /* MC_CMD_LINK_STATE_MODE_OUT msgresponse */ 14266 #define MC_CMD_LINK_STATE_MODE_OUT_LEN 4 14267 #define MC_CMD_LINK_STATE_MODE_OUT_OLD_MODE_OFST 0 14268 14269 14270 /***********************************/ 14271 /* MC_CMD_GET_SNAPSHOT_LENGTH 14272 * Obtain the curent range of allowable values for the SNAPSHOT_LENGTH 14273 * parameter to MC_CMD_INIT_RXQ. 14274 */ 14275 #define MC_CMD_GET_SNAPSHOT_LENGTH 0x101 14276 #undef MC_CMD_0x101_PRIVILEGE_CTG 14277 14278 #define MC_CMD_0x101_PRIVILEGE_CTG SRIOV_CTG_GENERAL 14279 14280 /* MC_CMD_GET_SNAPSHOT_LENGTH_IN msgrequest */ 14281 #define MC_CMD_GET_SNAPSHOT_LENGTH_IN_LEN 0 14282 14283 /* MC_CMD_GET_SNAPSHOT_LENGTH_OUT msgresponse */ 14284 #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_LEN 8 14285 /* Minimum acceptable snapshot length. */ 14286 #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MIN_OFST 0 14287 /* Maximum acceptable snapshot length. */ 14288 #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MAX_OFST 4 14289 14290 14291 /***********************************/ 14292 /* MC_CMD_FUSE_DIAGS 14293 * Additional fuse diagnostics 14294 */ 14295 #define MC_CMD_FUSE_DIAGS 0x102 14296 #undef MC_CMD_0x102_PRIVILEGE_CTG 14297 14298 #define MC_CMD_0x102_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14299 14300 /* MC_CMD_FUSE_DIAGS_IN msgrequest */ 14301 #define MC_CMD_FUSE_DIAGS_IN_LEN 0 14302 14303 /* MC_CMD_FUSE_DIAGS_OUT msgresponse */ 14304 #define MC_CMD_FUSE_DIAGS_OUT_LEN 48 14305 /* Total number of mismatched bits between pairs in area 0 */ 14306 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_MISMATCH_BITS_OFST 0 14307 /* Total number of unexpectedly clear (set in B but not A) bits in area 0 */ 14308 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_A_BAD_BITS_OFST 4 14309 /* Total number of unexpectedly clear (set in A but not B) bits in area 0 */ 14310 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_B_BAD_BITS_OFST 8 14311 /* Checksum of data after logical OR of pairs in area 0 */ 14312 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_CHECKSUM_OFST 12 14313 /* Total number of mismatched bits between pairs in area 1 */ 14314 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_MISMATCH_BITS_OFST 16 14315 /* Total number of unexpectedly clear (set in B but not A) bits in area 1 */ 14316 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_A_BAD_BITS_OFST 20 14317 /* Total number of unexpectedly clear (set in A but not B) bits in area 1 */ 14318 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_B_BAD_BITS_OFST 24 14319 /* Checksum of data after logical OR of pairs in area 1 */ 14320 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_CHECKSUM_OFST 28 14321 /* Total number of mismatched bits between pairs in area 2 */ 14322 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_MISMATCH_BITS_OFST 32 14323 /* Total number of unexpectedly clear (set in B but not A) bits in area 2 */ 14324 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_A_BAD_BITS_OFST 36 14325 /* Total number of unexpectedly clear (set in A but not B) bits in area 2 */ 14326 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_B_BAD_BITS_OFST 40 14327 /* Checksum of data after logical OR of pairs in area 2 */ 14328 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_CHECKSUM_OFST 44 14329 14330 14331 /***********************************/ 14332 /* MC_CMD_PRIVILEGE_MODIFY 14333 * Modify the privileges of a set of PCIe functions. Note that this operation 14334 * only effects non-admin functions unless the admin privilege itself is 14335 * included in one of the masks provided. 14336 */ 14337 #define MC_CMD_PRIVILEGE_MODIFY 0x60 14338 #undef MC_CMD_0x60_PRIVILEGE_CTG 14339 14340 #define MC_CMD_0x60_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14341 14342 /* MC_CMD_PRIVILEGE_MODIFY_IN msgrequest */ 14343 #define MC_CMD_PRIVILEGE_MODIFY_IN_LEN 16 14344 /* The groups of functions to have their privilege masks modified. */ 14345 #define MC_CMD_PRIVILEGE_MODIFY_IN_FN_GROUP_OFST 0 14346 #define MC_CMD_PRIVILEGE_MODIFY_IN_NONE 0x0 /* enum */ 14347 #define MC_CMD_PRIVILEGE_MODIFY_IN_ALL 0x1 /* enum */ 14348 #define MC_CMD_PRIVILEGE_MODIFY_IN_PFS_ONLY 0x2 /* enum */ 14349 #define MC_CMD_PRIVILEGE_MODIFY_IN_VFS_ONLY 0x3 /* enum */ 14350 #define MC_CMD_PRIVILEGE_MODIFY_IN_VFS_OF_PF 0x4 /* enum */ 14351 #define MC_CMD_PRIVILEGE_MODIFY_IN_ONE 0x5 /* enum */ 14352 /* For VFS_OF_PF specify the PF, for ONE specify the target function */ 14353 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_OFST 4 14354 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_PF_LBN 0 14355 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_PF_WIDTH 16 14356 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_VF_LBN 16 14357 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_VF_WIDTH 16 14358 /* Privileges to be added to the target functions. For privilege definitions 14359 * refer to the command MC_CMD_PRIVILEGE_MASK 14360 */ 14361 #define MC_CMD_PRIVILEGE_MODIFY_IN_ADD_MASK_OFST 8 14362 /* Privileges to be removed from the target functions. For privilege 14363 * definitions refer to the command MC_CMD_PRIVILEGE_MASK 14364 */ 14365 #define MC_CMD_PRIVILEGE_MODIFY_IN_REMOVE_MASK_OFST 12 14366 14367 /* MC_CMD_PRIVILEGE_MODIFY_OUT msgresponse */ 14368 #define MC_CMD_PRIVILEGE_MODIFY_OUT_LEN 0 14369 14370 14371 /***********************************/ 14372 /* MC_CMD_XPM_READ_BYTES 14373 * Read XPM memory 14374 */ 14375 #define MC_CMD_XPM_READ_BYTES 0x103 14376 #undef MC_CMD_0x103_PRIVILEGE_CTG 14377 14378 #define MC_CMD_0x103_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14379 14380 /* MC_CMD_XPM_READ_BYTES_IN msgrequest */ 14381 #define MC_CMD_XPM_READ_BYTES_IN_LEN 8 14382 /* Start address (byte) */ 14383 #define MC_CMD_XPM_READ_BYTES_IN_ADDR_OFST 0 14384 /* Count (bytes) */ 14385 #define MC_CMD_XPM_READ_BYTES_IN_COUNT_OFST 4 14386 14387 /* MC_CMD_XPM_READ_BYTES_OUT msgresponse */ 14388 #define MC_CMD_XPM_READ_BYTES_OUT_LENMIN 0 14389 #define MC_CMD_XPM_READ_BYTES_OUT_LENMAX 252 14390 #define MC_CMD_XPM_READ_BYTES_OUT_LEN(num) (0+1*(num)) 14391 /* Data */ 14392 #define MC_CMD_XPM_READ_BYTES_OUT_DATA_OFST 0 14393 #define MC_CMD_XPM_READ_BYTES_OUT_DATA_LEN 1 14394 #define MC_CMD_XPM_READ_BYTES_OUT_DATA_MINNUM 0 14395 #define MC_CMD_XPM_READ_BYTES_OUT_DATA_MAXNUM 252 14396 14397 14398 /***********************************/ 14399 /* MC_CMD_XPM_WRITE_BYTES 14400 * Write XPM memory 14401 */ 14402 #define MC_CMD_XPM_WRITE_BYTES 0x104 14403 #undef MC_CMD_0x104_PRIVILEGE_CTG 14404 14405 #define MC_CMD_0x104_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14406 14407 /* MC_CMD_XPM_WRITE_BYTES_IN msgrequest */ 14408 #define MC_CMD_XPM_WRITE_BYTES_IN_LENMIN 8 14409 #define MC_CMD_XPM_WRITE_BYTES_IN_LENMAX 252 14410 #define MC_CMD_XPM_WRITE_BYTES_IN_LEN(num) (8+1*(num)) 14411 /* Start address (byte) */ 14412 #define MC_CMD_XPM_WRITE_BYTES_IN_ADDR_OFST 0 14413 /* Count (bytes) */ 14414 #define MC_CMD_XPM_WRITE_BYTES_IN_COUNT_OFST 4 14415 /* Data */ 14416 #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_OFST 8 14417 #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_LEN 1 14418 #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_MINNUM 0 14419 #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_MAXNUM 244 14420 14421 /* MC_CMD_XPM_WRITE_BYTES_OUT msgresponse */ 14422 #define MC_CMD_XPM_WRITE_BYTES_OUT_LEN 0 14423 14424 14425 /***********************************/ 14426 /* MC_CMD_XPM_READ_SECTOR 14427 * Read XPM sector 14428 */ 14429 #define MC_CMD_XPM_READ_SECTOR 0x105 14430 #undef MC_CMD_0x105_PRIVILEGE_CTG 14431 14432 #define MC_CMD_0x105_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14433 14434 /* MC_CMD_XPM_READ_SECTOR_IN msgrequest */ 14435 #define MC_CMD_XPM_READ_SECTOR_IN_LEN 8 14436 /* Sector index */ 14437 #define MC_CMD_XPM_READ_SECTOR_IN_INDEX_OFST 0 14438 /* Sector size */ 14439 #define MC_CMD_XPM_READ_SECTOR_IN_SIZE_OFST 4 14440 14441 /* MC_CMD_XPM_READ_SECTOR_OUT msgresponse */ 14442 #define MC_CMD_XPM_READ_SECTOR_OUT_LENMIN 4 14443 #define MC_CMD_XPM_READ_SECTOR_OUT_LENMAX 36 14444 #define MC_CMD_XPM_READ_SECTOR_OUT_LEN(num) (4+1*(num)) 14445 /* Sector type */ 14446 #define MC_CMD_XPM_READ_SECTOR_OUT_TYPE_OFST 0 14447 #define MC_CMD_XPM_READ_SECTOR_OUT_BLANK 0x0 /* enum */ 14448 #define MC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_KEY_128 0x1 /* enum */ 14449 #define MC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_KEY_256 0x2 /* enum */ 14450 #define MC_CMD_XPM_READ_SECTOR_OUT_INVALID 0xff /* enum */ 14451 /* Sector data */ 14452 #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_OFST 4 14453 #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_LEN 1 14454 #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_MINNUM 0 14455 #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_MAXNUM 32 14456 14457 14458 /***********************************/ 14459 /* MC_CMD_XPM_WRITE_SECTOR 14460 * Write XPM sector 14461 */ 14462 #define MC_CMD_XPM_WRITE_SECTOR 0x106 14463 #undef MC_CMD_0x106_PRIVILEGE_CTG 14464 14465 #define MC_CMD_0x106_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14466 14467 /* MC_CMD_XPM_WRITE_SECTOR_IN msgrequest */ 14468 #define MC_CMD_XPM_WRITE_SECTOR_IN_LENMIN 12 14469 #define MC_CMD_XPM_WRITE_SECTOR_IN_LENMAX 44 14470 #define MC_CMD_XPM_WRITE_SECTOR_IN_LEN(num) (12+1*(num)) 14471 /* If writing fails due to an uncorrectable error, try up to RETRIES following 14472 * sectors (or until no more space available). If 0, only one write attempt is 14473 * made. Note that uncorrectable errors are unlikely, thanks to XPM self-repair 14474 * mechanism. 14475 */ 14476 #define MC_CMD_XPM_WRITE_SECTOR_IN_RETRIES_OFST 0 14477 #define MC_CMD_XPM_WRITE_SECTOR_IN_RETRIES_LEN 1 14478 #define MC_CMD_XPM_WRITE_SECTOR_IN_RESERVED_OFST 1 14479 #define MC_CMD_XPM_WRITE_SECTOR_IN_RESERVED_LEN 3 14480 /* Sector type */ 14481 #define MC_CMD_XPM_WRITE_SECTOR_IN_TYPE_OFST 4 14482 /* Enum values, see field(s): */ 14483 /* MC_CMD_XPM_READ_SECTOR/MC_CMD_XPM_READ_SECTOR_OUT/TYPE */ 14484 /* Sector size */ 14485 #define MC_CMD_XPM_WRITE_SECTOR_IN_SIZE_OFST 8 14486 /* Sector data */ 14487 #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_OFST 12 14488 #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_LEN 1 14489 #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_MINNUM 0 14490 #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_MAXNUM 32 14491 14492 /* MC_CMD_XPM_WRITE_SECTOR_OUT msgresponse */ 14493 #define MC_CMD_XPM_WRITE_SECTOR_OUT_LEN 4 14494 /* New sector index */ 14495 #define MC_CMD_XPM_WRITE_SECTOR_OUT_INDEX_OFST 0 14496 14497 14498 /***********************************/ 14499 /* MC_CMD_XPM_INVALIDATE_SECTOR 14500 * Invalidate XPM sector 14501 */ 14502 #define MC_CMD_XPM_INVALIDATE_SECTOR 0x107 14503 #undef MC_CMD_0x107_PRIVILEGE_CTG 14504 14505 #define MC_CMD_0x107_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14506 14507 /* MC_CMD_XPM_INVALIDATE_SECTOR_IN msgrequest */ 14508 #define MC_CMD_XPM_INVALIDATE_SECTOR_IN_LEN 4 14509 /* Sector index */ 14510 #define MC_CMD_XPM_INVALIDATE_SECTOR_IN_INDEX_OFST 0 14511 14512 /* MC_CMD_XPM_INVALIDATE_SECTOR_OUT msgresponse */ 14513 #define MC_CMD_XPM_INVALIDATE_SECTOR_OUT_LEN 0 14514 14515 14516 /***********************************/ 14517 /* MC_CMD_XPM_BLANK_CHECK 14518 * Blank-check XPM memory and report bad locations 14519 */ 14520 #define MC_CMD_XPM_BLANK_CHECK 0x108 14521 #undef MC_CMD_0x108_PRIVILEGE_CTG 14522 14523 #define MC_CMD_0x108_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14524 14525 /* MC_CMD_XPM_BLANK_CHECK_IN msgrequest */ 14526 #define MC_CMD_XPM_BLANK_CHECK_IN_LEN 8 14527 /* Start address (byte) */ 14528 #define MC_CMD_XPM_BLANK_CHECK_IN_ADDR_OFST 0 14529 /* Count (bytes) */ 14530 #define MC_CMD_XPM_BLANK_CHECK_IN_COUNT_OFST 4 14531 14532 /* MC_CMD_XPM_BLANK_CHECK_OUT msgresponse */ 14533 #define MC_CMD_XPM_BLANK_CHECK_OUT_LENMIN 4 14534 #define MC_CMD_XPM_BLANK_CHECK_OUT_LENMAX 252 14535 #define MC_CMD_XPM_BLANK_CHECK_OUT_LEN(num) (4+2*(num)) 14536 /* Total number of bad (non-blank) locations */ 14537 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_COUNT_OFST 0 14538 /* Addresses of bad locations (may be less than BAD_COUNT, if all cannot fit 14539 * into MCDI response) 14540 */ 14541 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_OFST 4 14542 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_LEN 2 14543 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_MINNUM 0 14544 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_MAXNUM 124 14545 14546 14547 /***********************************/ 14548 /* MC_CMD_XPM_REPAIR 14549 * Blank-check and repair XPM memory 14550 */ 14551 #define MC_CMD_XPM_REPAIR 0x109 14552 #undef MC_CMD_0x109_PRIVILEGE_CTG 14553 14554 #define MC_CMD_0x109_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14555 14556 /* MC_CMD_XPM_REPAIR_IN msgrequest */ 14557 #define MC_CMD_XPM_REPAIR_IN_LEN 8 14558 /* Start address (byte) */ 14559 #define MC_CMD_XPM_REPAIR_IN_ADDR_OFST 0 14560 /* Count (bytes) */ 14561 #define MC_CMD_XPM_REPAIR_IN_COUNT_OFST 4 14562 14563 /* MC_CMD_XPM_REPAIR_OUT msgresponse */ 14564 #define MC_CMD_XPM_REPAIR_OUT_LEN 0 14565 14566 14567 /***********************************/ 14568 /* MC_CMD_XPM_DECODER_TEST 14569 * Test XPM memory address decoders for gross manufacturing defects. Can only 14570 * be performed on an unprogrammed part. 14571 */ 14572 #define MC_CMD_XPM_DECODER_TEST 0x10a 14573 #undef MC_CMD_0x10a_PRIVILEGE_CTG 14574 14575 #define MC_CMD_0x10a_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14576 14577 /* MC_CMD_XPM_DECODER_TEST_IN msgrequest */ 14578 #define MC_CMD_XPM_DECODER_TEST_IN_LEN 0 14579 14580 /* MC_CMD_XPM_DECODER_TEST_OUT msgresponse */ 14581 #define MC_CMD_XPM_DECODER_TEST_OUT_LEN 0 14582 14583 14584 /***********************************/ 14585 /* MC_CMD_XPM_WRITE_TEST 14586 * XPM memory write test. Test XPM write logic for gross manufacturing defects 14587 * by writing to a dedicated test row. There are 16 locations in the test row 14588 * and the test can only be performed on locations that have not been 14589 * previously used (i.e. can be run at most 16 times). The test will pick the 14590 * first available location to use, or fail with ENOSPC if none left. 14591 */ 14592 #define MC_CMD_XPM_WRITE_TEST 0x10b 14593 #undef MC_CMD_0x10b_PRIVILEGE_CTG 14594 14595 #define MC_CMD_0x10b_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14596 14597 /* MC_CMD_XPM_WRITE_TEST_IN msgrequest */ 14598 #define MC_CMD_XPM_WRITE_TEST_IN_LEN 0 14599 14600 /* MC_CMD_XPM_WRITE_TEST_OUT msgresponse */ 14601 #define MC_CMD_XPM_WRITE_TEST_OUT_LEN 0 14602 14603 14604 /***********************************/ 14605 /* MC_CMD_EXEC_SIGNED 14606 * Check the CMAC of the contents of IMEM and DMEM against the value supplied 14607 * and if correct begin execution from the start of IMEM. The caller supplies a 14608 * key ID, the length of IMEM and DMEM to validate and the expected CMAC. CMAC 14609 * computation runs from the start of IMEM, and from the start of DMEM + 16k, 14610 * to match flash booting. The command will respond with EINVAL if the CMAC 14611 * does match, otherwise it will respond with success before it jumps to IMEM. 14612 */ 14613 #define MC_CMD_EXEC_SIGNED 0x10c 14614 #undef MC_CMD_0x10c_PRIVILEGE_CTG 14615 14616 #define MC_CMD_0x10c_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14617 14618 /* MC_CMD_EXEC_SIGNED_IN msgrequest */ 14619 #define MC_CMD_EXEC_SIGNED_IN_LEN 28 14620 /* the length of code to include in the CMAC */ 14621 #define MC_CMD_EXEC_SIGNED_IN_CODELEN_OFST 0 14622 /* the length of date to include in the CMAC */ 14623 #define MC_CMD_EXEC_SIGNED_IN_DATALEN_OFST 4 14624 /* the XPM sector containing the key to use */ 14625 #define MC_CMD_EXEC_SIGNED_IN_KEYSECTOR_OFST 8 14626 /* the expected CMAC value */ 14627 #define MC_CMD_EXEC_SIGNED_IN_CMAC_OFST 12 14628 #define MC_CMD_EXEC_SIGNED_IN_CMAC_LEN 16 14629 14630 /* MC_CMD_EXEC_SIGNED_OUT msgresponse */ 14631 #define MC_CMD_EXEC_SIGNED_OUT_LEN 0 14632 14633 14634 /***********************************/ 14635 /* MC_CMD_PREPARE_SIGNED 14636 * Prepare to upload a signed image. This will scrub the specified length of 14637 * the data region, which must be at least as large as the DATALEN supplied to 14638 * MC_CMD_EXEC_SIGNED. 14639 */ 14640 #define MC_CMD_PREPARE_SIGNED 0x10d 14641 #undef MC_CMD_0x10d_PRIVILEGE_CTG 14642 14643 #define MC_CMD_0x10d_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14644 14645 /* MC_CMD_PREPARE_SIGNED_IN msgrequest */ 14646 #define MC_CMD_PREPARE_SIGNED_IN_LEN 4 14647 /* the length of data area to clear */ 14648 #define MC_CMD_PREPARE_SIGNED_IN_DATALEN_OFST 0 14649 14650 /* MC_CMD_PREPARE_SIGNED_OUT msgresponse */ 14651 #define MC_CMD_PREPARE_SIGNED_OUT_LEN 0 14652 14653 14654 /***********************************/ 14655 /* MC_CMD_SET_SECURITY_RULE 14656 * Set blacklist and/or whitelist action for a particular match criteria. 14657 * (Medford-only; for use by SolarSecure apps, not directly by drivers. See 14658 * SF-114946-SW.) NOTE - this message definition is provisional. It has not yet 14659 * been used in any released code and may change during development. This note 14660 * will be removed once it is regarded as stable. 14661 */ 14662 #define MC_CMD_SET_SECURITY_RULE 0x10f 14663 #undef MC_CMD_0x10f_PRIVILEGE_CTG 14664 14665 #define MC_CMD_0x10f_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14666 14667 /* MC_CMD_SET_SECURITY_RULE_IN msgrequest */ 14668 #define MC_CMD_SET_SECURITY_RULE_IN_LEN 92 14669 /* fields to include in match criteria */ 14670 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_FIELDS_OFST 0 14671 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_IP_LBN 0 14672 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_IP_WIDTH 1 14673 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_IP_LBN 1 14674 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_IP_WIDTH 1 14675 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_MAC_LBN 2 14676 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_MAC_WIDTH 1 14677 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_PORT_LBN 3 14678 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_PORT_WIDTH 1 14679 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_MAC_LBN 4 14680 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_MAC_WIDTH 1 14681 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_PORT_LBN 5 14682 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_PORT_WIDTH 1 14683 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_ETHER_TYPE_LBN 6 14684 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_ETHER_TYPE_WIDTH 1 14685 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_INNER_VLAN_LBN 7 14686 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_INNER_VLAN_WIDTH 1 14687 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_OUTER_VLAN_LBN 8 14688 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_OUTER_VLAN_WIDTH 1 14689 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_IP_PROTO_LBN 9 14690 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_IP_PROTO_WIDTH 1 14691 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_PHYSICAL_PORT_LBN 10 14692 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_PHYSICAL_PORT_WIDTH 1 14693 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_RESERVED_LBN 11 14694 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_RESERVED_WIDTH 1 14695 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_SUBNET_ID_LBN 12 14696 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_SUBNET_ID_WIDTH 1 14697 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_PORTRANGE_ID_LBN 13 14698 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_PORTRANGE_ID_WIDTH 1 14699 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_PORTRANGE_ID_LBN 14 14700 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_PORTRANGE_ID_WIDTH 1 14701 /* remote MAC address to match (as bytes in network order) */ 14702 #define MC_CMD_SET_SECURITY_RULE_IN_REMOTE_MAC_OFST 4 14703 #define MC_CMD_SET_SECURITY_RULE_IN_REMOTE_MAC_LEN 6 14704 /* remote port to match (as bytes in network order) */ 14705 #define MC_CMD_SET_SECURITY_RULE_IN_REMOTE_PORT_OFST 10 14706 #define MC_CMD_SET_SECURITY_RULE_IN_REMOTE_PORT_LEN 2 14707 /* local MAC address to match (as bytes in network order) */ 14708 #define MC_CMD_SET_SECURITY_RULE_IN_LOCAL_MAC_OFST 12 14709 #define MC_CMD_SET_SECURITY_RULE_IN_LOCAL_MAC_LEN 6 14710 /* local port to match (as bytes in network order) */ 14711 #define MC_CMD_SET_SECURITY_RULE_IN_LOCAL_PORT_OFST 18 14712 #define MC_CMD_SET_SECURITY_RULE_IN_LOCAL_PORT_LEN 2 14713 /* Ethernet type to match (as bytes in network order) */ 14714 #define MC_CMD_SET_SECURITY_RULE_IN_ETHER_TYPE_OFST 20 14715 #define MC_CMD_SET_SECURITY_RULE_IN_ETHER_TYPE_LEN 2 14716 /* Inner VLAN tag to match (as bytes in network order) */ 14717 #define MC_CMD_SET_SECURITY_RULE_IN_INNER_VLAN_OFST 22 14718 #define MC_CMD_SET_SECURITY_RULE_IN_INNER_VLAN_LEN 2 14719 /* Outer VLAN tag to match (as bytes in network order) */ 14720 #define MC_CMD_SET_SECURITY_RULE_IN_OUTER_VLAN_OFST 24 14721 #define MC_CMD_SET_SECURITY_RULE_IN_OUTER_VLAN_LEN 2 14722 /* IP protocol to match (in low byte; set high byte to 0) */ 14723 #define MC_CMD_SET_SECURITY_RULE_IN_IP_PROTO_OFST 26 14724 #define MC_CMD_SET_SECURITY_RULE_IN_IP_PROTO_LEN 2 14725 /* Physical port to match (as little-endian 32-bit value) */ 14726 #define MC_CMD_SET_SECURITY_RULE_IN_PHYSICAL_PORT_OFST 28 14727 /* Reserved; set to 0 */ 14728 #define MC_CMD_SET_SECURITY_RULE_IN_RESERVED_OFST 32 14729 /* remote IP address to match (as bytes in network order; set last 12 bytes to 14730 * 0 for IPv4 address) 14731 */ 14732 #define MC_CMD_SET_SECURITY_RULE_IN_REMOTE_IP_OFST 36 14733 #define MC_CMD_SET_SECURITY_RULE_IN_REMOTE_IP_LEN 16 14734 /* local IP address to match (as bytes in network order; set last 12 bytes to 0 14735 * for IPv4 address) 14736 */ 14737 #define MC_CMD_SET_SECURITY_RULE_IN_LOCAL_IP_OFST 52 14738 #define MC_CMD_SET_SECURITY_RULE_IN_LOCAL_IP_LEN 16 14739 /* remote subnet ID to match (as little-endian 32-bit value); note that remote 14740 * subnets are matched by mapping the remote IP address to a "subnet ID" via a 14741 * data structure which must already have been configured using 14742 * MC_CMD_SUBNET_MAP_SET_NODE appropriately 14743 */ 14744 #define MC_CMD_SET_SECURITY_RULE_IN_REMOTE_SUBNET_ID_OFST 68 14745 /* remote portrange ID to match (as little-endian 32-bit value); note that 14746 * remote port ranges are matched by mapping the remote port to a "portrange 14747 * ID" via a data structure which must already have been configured using 14748 * MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE 14749 */ 14750 #define MC_CMD_SET_SECURITY_RULE_IN_REMOTE_PORTRANGE_ID_OFST 72 14751 /* local portrange ID to match (as little-endian 32-bit value); note that local 14752 * port ranges are matched by mapping the local port to a "portrange ID" via a 14753 * data structure which must already have been configured using 14754 * MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE 14755 */ 14756 #define MC_CMD_SET_SECURITY_RULE_IN_LOCAL_PORTRANGE_ID_OFST 76 14757 /* set the action for transmitted packets matching this rule */ 14758 #define MC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_OFST 80 14759 /* enum: make no decision */ 14760 #define MC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_NONE 0x0 14761 /* enum: decide to accept the packet */ 14762 #define MC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_WHITELIST 0x1 14763 /* enum: decide to drop the packet */ 14764 #define MC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_BLACKLIST 0x2 14765 /* enum: do not change the current TX action */ 14766 #define MC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_UNCHANGED 0xffffffff 14767 /* set the action for received packets matching this rule */ 14768 #define MC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_OFST 84 14769 /* enum: make no decision */ 14770 #define MC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_NONE 0x0 14771 /* enum: decide to accept the packet */ 14772 #define MC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_WHITELIST 0x1 14773 /* enum: decide to drop the packet */ 14774 #define MC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_BLACKLIST 0x2 14775 /* enum: do not change the current RX action */ 14776 #define MC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_UNCHANGED 0xffffffff 14777 /* counter ID to associate with this rule; IDs are allocated using 14778 * MC_CMD_SECURITY_RULE_COUNTER_ALLOC 14779 */ 14780 #define MC_CMD_SET_SECURITY_RULE_IN_COUNTER_ID_OFST 88 14781 /* enum: special value for the null counter ID */ 14782 #define MC_CMD_SET_SECURITY_RULE_IN_COUNTER_ID_NONE 0x0 14783 14784 /* MC_CMD_SET_SECURITY_RULE_OUT msgresponse */ 14785 #define MC_CMD_SET_SECURITY_RULE_OUT_LEN 28 14786 /* new reference count for uses of counter ID */ 14787 #define MC_CMD_SET_SECURITY_RULE_OUT_COUNTER_REFCNT_OFST 0 14788 /* constructed match bits for this rule (as a tracing aid only) */ 14789 #define MC_CMD_SET_SECURITY_RULE_OUT_LUE_MATCH_BITS_OFST 4 14790 #define MC_CMD_SET_SECURITY_RULE_OUT_LUE_MATCH_BITS_LEN 12 14791 /* constructed discriminator bits for this rule (as a tracing aid only) */ 14792 #define MC_CMD_SET_SECURITY_RULE_OUT_LUE_DISCRIMINATOR_OFST 16 14793 /* base location for probes for this rule (as a tracing aid only) */ 14794 #define MC_CMD_SET_SECURITY_RULE_OUT_LUE_PROBE_BASE_OFST 20 14795 /* step for probes for this rule (as a tracing aid only) */ 14796 #define MC_CMD_SET_SECURITY_RULE_OUT_LUE_PROBE_STEP_OFST 24 14797 14798 14799 /***********************************/ 14800 /* MC_CMD_RESET_SECURITY_RULES 14801 * Reset all blacklist and whitelist actions for a particular physical port, or 14802 * all ports. (Medford-only; for use by SolarSecure apps, not directly by 14803 * drivers. See SF-114946-SW.) NOTE - this message definition is provisional. 14804 * It has not yet been used in any released code and may change during 14805 * development. This note will be removed once it is regarded as stable. 14806 */ 14807 #define MC_CMD_RESET_SECURITY_RULES 0x110 14808 #undef MC_CMD_0x110_PRIVILEGE_CTG 14809 14810 #define MC_CMD_0x110_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14811 14812 /* MC_CMD_RESET_SECURITY_RULES_IN msgrequest */ 14813 #define MC_CMD_RESET_SECURITY_RULES_IN_LEN 4 14814 /* index of physical port to reset (or ALL_PHYSICAL_PORTS to reset all) */ 14815 #define MC_CMD_RESET_SECURITY_RULES_IN_PHYSICAL_PORT_OFST 0 14816 /* enum: special value to reset all physical ports */ 14817 #define MC_CMD_RESET_SECURITY_RULES_IN_ALL_PHYSICAL_PORTS 0xffffffff 14818 14819 /* MC_CMD_RESET_SECURITY_RULES_OUT msgresponse */ 14820 #define MC_CMD_RESET_SECURITY_RULES_OUT_LEN 0 14821 14822 14823 /***********************************/ 14824 /* MC_CMD_GET_SECURITY_RULESET_VERSION 14825 * Return a large hash value representing a "version" of the complete set of 14826 * currently active blacklist / whitelist rules and associated data structures. 14827 * (Medford-only; for use by SolarSecure apps, not directly by drivers. See 14828 * SF-114946-SW.) NOTE - this message definition is provisional. It has not yet 14829 * been used in any released code and may change during development. This note 14830 * will be removed once it is regarded as stable. 14831 */ 14832 #define MC_CMD_GET_SECURITY_RULESET_VERSION 0x111 14833 #undef MC_CMD_0x111_PRIVILEGE_CTG 14834 14835 #define MC_CMD_0x111_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14836 14837 /* MC_CMD_GET_SECURITY_RULESET_VERSION_IN msgrequest */ 14838 #define MC_CMD_GET_SECURITY_RULESET_VERSION_IN_LEN 0 14839 14840 /* MC_CMD_GET_SECURITY_RULESET_VERSION_OUT msgresponse */ 14841 #define MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_LENMIN 1 14842 #define MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_LENMAX 252 14843 #define MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_LEN(num) (0+1*(num)) 14844 /* Opaque hash value; length may vary depending on the hash scheme used */ 14845 #define MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_VERSION_OFST 0 14846 #define MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_VERSION_LEN 1 14847 #define MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_VERSION_MINNUM 1 14848 #define MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_VERSION_MAXNUM 252 14849 14850 14851 /***********************************/ 14852 /* MC_CMD_SECURITY_RULE_COUNTER_ALLOC 14853 * Allocate counters for use with blacklist / whitelist rules. (Medford-only; 14854 * for use by SolarSecure apps, not directly by drivers. See SF-114946-SW.) 14855 * NOTE - this message definition is provisional. It has not yet been used in 14856 * any released code and may change during development. This note will be 14857 * removed once it is regarded as stable. 14858 */ 14859 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC 0x112 14860 #undef MC_CMD_0x112_PRIVILEGE_CTG 14861 14862 #define MC_CMD_0x112_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14863 14864 /* MC_CMD_SECURITY_RULE_COUNTER_ALLOC_IN msgrequest */ 14865 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_IN_LEN 4 14866 /* the number of new counter IDs to request */ 14867 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_IN_NUM_COUNTERS_OFST 0 14868 14869 /* MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT msgresponse */ 14870 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_LENMIN 4 14871 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_LENMAX 252 14872 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_LEN(num) (4+4*(num)) 14873 /* the number of new counter IDs allocated (may be less than the number 14874 * requested if resources are unavailable) 14875 */ 14876 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_NUM_COUNTERS_OFST 0 14877 /* new counter ID(s) */ 14878 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_COUNTER_ID_OFST 4 14879 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_COUNTER_ID_LEN 4 14880 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_COUNTER_ID_MINNUM 0 14881 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_COUNTER_ID_MAXNUM 62 14882 14883 14884 /***********************************/ 14885 /* MC_CMD_SECURITY_RULE_COUNTER_FREE 14886 * Allocate counters for use with blacklist / whitelist rules. (Medford-only; 14887 * for use by SolarSecure apps, not directly by drivers. See SF-114946-SW.) 14888 * NOTE - this message definition is provisional. It has not yet been used in 14889 * any released code and may change during development. This note will be 14890 * removed once it is regarded as stable. 14891 */ 14892 #define MC_CMD_SECURITY_RULE_COUNTER_FREE 0x113 14893 #undef MC_CMD_0x113_PRIVILEGE_CTG 14894 14895 #define MC_CMD_0x113_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14896 14897 /* MC_CMD_SECURITY_RULE_COUNTER_FREE_IN msgrequest */ 14898 #define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_LENMIN 4 14899 #define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_LENMAX 252 14900 #define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_LEN(num) (4+4*(num)) 14901 /* the number of counter IDs to free */ 14902 #define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_NUM_COUNTERS_OFST 0 14903 /* the counter ID(s) to free */ 14904 #define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_COUNTER_ID_OFST 4 14905 #define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_COUNTER_ID_LEN 4 14906 #define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_COUNTER_ID_MINNUM 0 14907 #define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_COUNTER_ID_MAXNUM 62 14908 14909 /* MC_CMD_SECURITY_RULE_COUNTER_FREE_OUT msgresponse */ 14910 #define MC_CMD_SECURITY_RULE_COUNTER_FREE_OUT_LEN 0 14911 14912 14913 /***********************************/ 14914 /* MC_CMD_SUBNET_MAP_SET_NODE 14915 * Atomically update a trie node in the map of subnets to subnet IDs. The 14916 * constants in the descriptions of the fields of this message may be retrieved 14917 * by the GET_SECURITY_RULE_INFO op of MC_CMD_GET_PARSER_DISP_INFO. (Medford- 14918 * only; for use by SolarSecure apps, not directly by drivers. See 14919 * SF-114946-SW.) NOTE - this message definition is provisional. It has not yet 14920 * been used in any released code and may change during development. This note 14921 * will be removed once it is regarded as stable. 14922 */ 14923 #define MC_CMD_SUBNET_MAP_SET_NODE 0x114 14924 #undef MC_CMD_0x114_PRIVILEGE_CTG 14925 14926 #define MC_CMD_0x114_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14927 14928 /* MC_CMD_SUBNET_MAP_SET_NODE_IN msgrequest */ 14929 #define MC_CMD_SUBNET_MAP_SET_NODE_IN_LENMIN 6 14930 #define MC_CMD_SUBNET_MAP_SET_NODE_IN_LENMAX 252 14931 #define MC_CMD_SUBNET_MAP_SET_NODE_IN_LEN(num) (4+2*(num)) 14932 /* node to update in the range 0 .. SUBNET_MAP_NUM_NODES-1 */ 14933 #define MC_CMD_SUBNET_MAP_SET_NODE_IN_NODE_ID_OFST 0 14934 /* SUBNET_MAP_NUM_ENTRIES_PER_NODE new entries; each entry is either a pointer 14935 * to the next node, expressed as an offset in the trie memory (i.e. node ID 14936 * multiplied by SUBNET_MAP_NUM_ENTRIES_PER_NODE), or a leaf value in the range 14937 * SUBNET_ID_MIN .. SUBNET_ID_MAX 14938 */ 14939 #define MC_CMD_SUBNET_MAP_SET_NODE_IN_ENTRY_OFST 4 14940 #define MC_CMD_SUBNET_MAP_SET_NODE_IN_ENTRY_LEN 2 14941 #define MC_CMD_SUBNET_MAP_SET_NODE_IN_ENTRY_MINNUM 1 14942 #define MC_CMD_SUBNET_MAP_SET_NODE_IN_ENTRY_MAXNUM 124 14943 14944 /* MC_CMD_SUBNET_MAP_SET_NODE_OUT msgresponse */ 14945 #define MC_CMD_SUBNET_MAP_SET_NODE_OUT_LEN 0 14946 14947 /* PORTRANGE_TREE_ENTRY structuredef */ 14948 #define PORTRANGE_TREE_ENTRY_LEN 4 14949 /* key for branch nodes (<= key takes left branch, > key takes right branch), 14950 * or magic value for leaf nodes 14951 */ 14952 #define PORTRANGE_TREE_ENTRY_BRANCH_KEY_OFST 0 14953 #define PORTRANGE_TREE_ENTRY_BRANCH_KEY_LEN 2 14954 #define PORTRANGE_TREE_ENTRY_LEAF_NODE_KEY 0xffff /* enum */ 14955 #define PORTRANGE_TREE_ENTRY_BRANCH_KEY_LBN 0 14956 #define PORTRANGE_TREE_ENTRY_BRANCH_KEY_WIDTH 16 14957 /* final portrange ID for leaf nodes (don't care for branch nodes) */ 14958 #define PORTRANGE_TREE_ENTRY_LEAF_PORTRANGE_ID_OFST 2 14959 #define PORTRANGE_TREE_ENTRY_LEAF_PORTRANGE_ID_LEN 2 14960 #define PORTRANGE_TREE_ENTRY_LEAF_PORTRANGE_ID_LBN 16 14961 #define PORTRANGE_TREE_ENTRY_LEAF_PORTRANGE_ID_WIDTH 16 14962 14963 14964 /***********************************/ 14965 /* MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE 14966 * Atomically update the entire tree mapping remote port ranges to portrange 14967 * IDs. The constants in the descriptions of the fields of this message may be 14968 * retrieved by the GET_SECURITY_RULE_INFO op of MC_CMD_GET_PARSER_DISP_INFO. 14969 * (Medford-only; for use by SolarSecure apps, not directly by drivers. See 14970 * SF-114946-SW.) NOTE - this message definition is provisional. It has not yet 14971 * been used in any released code and may change during development. This note 14972 * will be removed once it is regarded as stable. 14973 */ 14974 #define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE 0x115 14975 #undef MC_CMD_0x115_PRIVILEGE_CTG 14976 14977 #define MC_CMD_0x115_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14978 14979 /* MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN msgrequest */ 14980 #define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN_LENMIN 4 14981 #define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN_LENMAX 252 14982 #define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN_LEN(num) (0+4*(num)) 14983 /* PORTRANGE_TREE_NUM_ENTRIES new entries, each laid out as a 14984 * PORTRANGE_TREE_ENTRY 14985 */ 14986 #define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_OFST 0 14987 #define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_LEN 4 14988 #define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_MINNUM 1 14989 #define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_MAXNUM 63 14990 14991 /* MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_OUT msgresponse */ 14992 #define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_OUT_LEN 0 14993 14994 14995 /***********************************/ 14996 /* MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE 14997 * Atomically update the entire tree mapping remote port ranges to portrange 14998 * IDs. The constants in the descriptions of the fields of this message may be 14999 * retrieved by the GET_SECURITY_RULE_INFO op of MC_CMD_GET_PARSER_DISP_INFO. 15000 * (Medford-only; for use by SolarSecure apps, not directly by drivers. See 15001 * SF-114946-SW.) NOTE - this message definition is provisional. It has not yet 15002 * been used in any released code and may change during development. This note 15003 * will be removed once it is regarded as stable. 15004 */ 15005 #define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE 0x116 15006 #undef MC_CMD_0x116_PRIVILEGE_CTG 15007 15008 #define MC_CMD_0x116_PRIVILEGE_CTG SRIOV_CTG_ADMIN 15009 15010 /* MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN msgrequest */ 15011 #define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN_LENMIN 4 15012 #define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN_LENMAX 252 15013 #define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN_LEN(num) (0+4*(num)) 15014 /* PORTRANGE_TREE_NUM_ENTRIES new entries, each laid out as a 15015 * PORTRANGE_TREE_ENTRY 15016 */ 15017 #define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_OFST 0 15018 #define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_LEN 4 15019 #define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_MINNUM 1 15020 #define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_MAXNUM 63 15021 15022 /* MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_OUT msgresponse */ 15023 #define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_OUT_LEN 0 15024 15025 /* TUNNEL_ENCAP_UDP_PORT_ENTRY structuredef */ 15026 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_LEN 4 15027 /* UDP port (the standard ports are named below but any port may be used) */ 15028 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_OFST 0 15029 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_LEN 2 15030 /* enum: the IANA allocated UDP port for VXLAN */ 15031 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_IANA_VXLAN_UDP_PORT 0x12b5 15032 /* enum: the IANA allocated UDP port for Geneve */ 15033 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_IANA_GENEVE_UDP_PORT 0x17c1 15034 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_LBN 0 15035 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_WIDTH 16 15036 /* tunnel encapsulation protocol (only those named below are supported) */ 15037 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_OFST 2 15038 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_LEN 2 15039 /* enum: This port will be used for VXLAN on both IPv4 and IPv6 */ 15040 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_VXLAN 0x0 15041 /* enum: This port will be used for Geneve on both IPv4 and IPv6 */ 15042 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_GENEVE 0x1 15043 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_LBN 16 15044 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_WIDTH 16 15045 15046 15047 /***********************************/ 15048 /* MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS 15049 * Configure UDP ports for tunnel encapsulation hardware acceleration. The 15050 * parser-dispatcher will attempt to parse traffic on these ports as tunnel 15051 * encapsulation PDUs and filter them using the tunnel encapsulation filter 15052 * chain rather than the standard filter chain. Note that this command can 15053 * cause all functions to see a reset. (Available on Medford only.) 15054 */ 15055 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS 0x117 15056 #undef MC_CMD_0x117_PRIVILEGE_CTG 15057 15058 #define MC_CMD_0x117_PRIVILEGE_CTG SRIOV_CTG_ADMIN 15059 15060 /* MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN msgrequest */ 15061 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMIN 4 15062 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMAX 68 15063 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LEN(num) (4+4*(num)) 15064 /* Flags */ 15065 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_OFST 0 15066 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_LEN 2 15067 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING_LBN 0 15068 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING_WIDTH 1 15069 /* The number of entries in the ENTRIES array */ 15070 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_OFST 2 15071 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_LEN 2 15072 /* Entries defining the UDP port to protocol mapping, each laid out as a 15073 * TUNNEL_ENCAP_UDP_PORT_ENTRY 15074 */ 15075 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_OFST 4 15076 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_LEN 4 15077 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MINNUM 0 15078 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MAXNUM 16 15079 15080 /* MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT msgresponse */ 15081 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_LEN 2 15082 /* Flags */ 15083 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_FLAGS_OFST 0 15084 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_FLAGS_LEN 2 15085 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_LBN 0 15086 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_WIDTH 1 15087 15088 15089 /***********************************/ 15090 /* MC_CMD_RX_BALANCING 15091 * Configure a port upconverter to distribute the packets on both RX engines. 15092 * Packets are distributed based on a table with the destination vFIFO. The 15093 * index of the table is a hash of source and destination of IPV4 and VLAN 15094 * priority. 15095 */ 15096 #define MC_CMD_RX_BALANCING 0x118 15097 #undef MC_CMD_0x118_PRIVILEGE_CTG 15098 15099 #define MC_CMD_0x118_PRIVILEGE_CTG SRIOV_CTG_ADMIN 15100 15101 /* MC_CMD_RX_BALANCING_IN msgrequest */ 15102 #define MC_CMD_RX_BALANCING_IN_LEN 16 15103 /* The RX port whose upconverter table will be modified */ 15104 #define MC_CMD_RX_BALANCING_IN_PORT_OFST 0 15105 /* The VLAN priority associated to the table index and vFIFO */ 15106 #define MC_CMD_RX_BALANCING_IN_PRIORITY_OFST 4 15107 /* The resulting bit of SRC^DST for indexing the table */ 15108 #define MC_CMD_RX_BALANCING_IN_SRC_DST_OFST 8 15109 /* The RX engine to which the vFIFO in the table entry will point to */ 15110 #define MC_CMD_RX_BALANCING_IN_ENG_OFST 12 15111 15112 /* MC_CMD_RX_BALANCING_OUT msgresponse */ 15113 #define MC_CMD_RX_BALANCING_OUT_LEN 0 15114 15115 15116 /***********************************/ 15117 /* MC_CMD_TSA_BIND 15118 * TSAN - TSAC binding communication protocol. Refer to SF-115479-TC for more 15119 * info in respect to the binding protocol. This MCDI command is only available 15120 * over a TLS secure connection between the TSAN and TSAC, and is not available 15121 * to host software. Note- The messages definitions that do comprise this MCDI 15122 * command deemed as provisional. This MCDI command has not yet been used in 15123 * any released code and may change during development. This note will be 15124 * removed once it is regarded as stable. 15125 */ 15126 #define MC_CMD_TSA_BIND 0x119 15127 #undef MC_CMD_0x119_PRIVILEGE_CTG 15128 15129 #define MC_CMD_0x119_PRIVILEGE_CTG SRIOV_CTG_ADMIN 15130 15131 /* MC_CMD_TSA_BIND_IN msgrequest: Protocol operation code */ 15132 #define MC_CMD_TSA_BIND_IN_LEN 4 15133 #define MC_CMD_TSA_BIND_IN_OP_OFST 0 15134 /* enum: Retrieve the TSAN ID from a TSAN. TSAN ID is a unique identifier for 15135 * the network adapter. More specifically, TSAN ID equals the MAC address of 15136 * the network adapter. TSAN ID is used as part of the TSAN authentication 15137 * protocol. Refer to SF-114946-SW for more information. 15138 */ 15139 #define MC_CMD_TSA_BIND_OP_GET_ID 0x1 15140 /* enum: Get a binding ticket from the TSAN. The binding ticket is used as part 15141 * of the binding procedure to authorize the binding of an adapter to a TSAID. 15142 * Refer to SF-114946-SW for more information. 15143 */ 15144 #define MC_CMD_TSA_BIND_OP_GET_TICKET 0x2 15145 /* enum: Opcode associated with the propagation of a private key that TSAN uses 15146 * as part of post-binding authentication procedure. More specifically, TSAN 15147 * uses this key for a signing operation. TSAC uses the counterpart public key 15148 * to verify the signature. Note - The post-binding authentication occurs when 15149 * the TSAN-TSAC connection terminates and TSAN tries to reconnect. Refer to 15150 * SF-114946-SW for more information. 15151 */ 15152 #define MC_CMD_TSA_BIND_OP_SET_KEY 0x3 15153 /* enum: Request an unbinding operation. Note- TSAN clears the binding ticket 15154 * from the Nvram section. 15155 */ 15156 #define MC_CMD_TSA_BIND_OP_UNBIND 0x4 15157 15158 /* MC_CMD_TSA_BIND_IN_GET_ID msgrequest */ 15159 #define MC_CMD_TSA_BIND_IN_GET_ID_LEN 20 15160 /* The operation requested. */ 15161 #define MC_CMD_TSA_BIND_IN_GET_ID_OP_OFST 0 15162 /* Cryptographic nonce that TSAC generates and sends to TSAN. TSAC generates 15163 * the nonce every time as part of the TSAN post-binding authentication 15164 * procedure when the TSAN-TSAC connection terminates and TSAN does need to re- 15165 * connect to the TSAC. Refer to SF-114946-SW for more information. 15166 */ 15167 #define MC_CMD_TSA_BIND_IN_GET_ID_NONCE_OFST 4 15168 #define MC_CMD_TSA_BIND_IN_GET_ID_NONCE_LEN 16 15169 15170 /* MC_CMD_TSA_BIND_IN_GET_TICKET msgrequest */ 15171 #define MC_CMD_TSA_BIND_IN_GET_TICKET_LEN 4 15172 /* The operation requested. */ 15173 #define MC_CMD_TSA_BIND_IN_GET_TICKET_OP_OFST 0 15174 15175 /* MC_CMD_TSA_BIND_IN_SET_KEY msgrequest */ 15176 #define MC_CMD_TSA_BIND_IN_SET_KEY_LENMIN 5 15177 #define MC_CMD_TSA_BIND_IN_SET_KEY_LENMAX 252 15178 #define MC_CMD_TSA_BIND_IN_SET_KEY_LEN(num) (4+1*(num)) 15179 /* The operation requested. */ 15180 #define MC_CMD_TSA_BIND_IN_SET_KEY_OP_OFST 0 15181 /* This data blob contains the private key generated by the TSAC. TSAN uses 15182 * this key for a signing operation. Note- This private key is used in 15183 * conjunction with the post-binding TSAN authentication procedure that occurs 15184 * when the TSAN-TSAC connection terminates and TSAN tries to reconnect. Refer 15185 * to SF-114946-SW for more information. 15186 */ 15187 #define MC_CMD_TSA_BIND_IN_SET_KEY_DATKEY_OFST 4 15188 #define MC_CMD_TSA_BIND_IN_SET_KEY_DATKEY_LEN 1 15189 #define MC_CMD_TSA_BIND_IN_SET_KEY_DATKEY_MINNUM 1 15190 #define MC_CMD_TSA_BIND_IN_SET_KEY_DATKEY_MAXNUM 248 15191 15192 /* MC_CMD_TSA_BIND_IN_UNBIND msgrequest: Asks for the un-binding procedure */ 15193 #define MC_CMD_TSA_BIND_IN_UNBIND_LEN 10 15194 /* The operation requested. */ 15195 #define MC_CMD_TSA_BIND_IN_UNBIND_OP_OFST 0 15196 /* TSAN unique identifier for the network adapter */ 15197 #define MC_CMD_TSA_BIND_IN_UNBIND_TSANID_OFST 4 15198 #define MC_CMD_TSA_BIND_IN_UNBIND_TSANID_LEN 6 15199 15200 /* MC_CMD_TSA_BIND_OUT_GET_ID msgresponse */ 15201 #define MC_CMD_TSA_BIND_OUT_GET_ID_LENMIN 15 15202 #define MC_CMD_TSA_BIND_OUT_GET_ID_LENMAX 252 15203 #define MC_CMD_TSA_BIND_OUT_GET_ID_LEN(num) (14+1*(num)) 15204 /* The operation completion code. */ 15205 #define MC_CMD_TSA_BIND_OUT_GET_ID_OP_OFST 0 15206 /* Rules engine type. Note- The rules engine type allows TSAC to further 15207 * identify the connected endpoint (e.g. TSAN, NIC Emulator) type and take the 15208 * proper action accordingly. As an example, TSAC uses the rules engine type to 15209 * select the SF key that differs in the case of TSAN vs. NIC Emulator. 15210 */ 15211 #define MC_CMD_TSA_BIND_OUT_GET_ID_RULE_ENGINE_OFST 4 15212 /* enum: Hardware rules engine. */ 15213 #define MC_CMD_TSA_BIND_OUT_GET_ID_RULE_ENGINE_TSAN 0x1 15214 /* enum: Nic emulator rules engine. */ 15215 #define MC_CMD_TSA_BIND_OUT_GET_ID_RULE_ENGINE_NEMU 0x2 15216 /* enum: SSFE. */ 15217 #define MC_CMD_TSA_BIND_OUT_GET_ID_RULE_ENGINE_SSFE 0x3 15218 /* TSAN unique identifier for the network adapter */ 15219 #define MC_CMD_TSA_BIND_OUT_GET_ID_TSANID_OFST 8 15220 #define MC_CMD_TSA_BIND_OUT_GET_ID_TSANID_LEN 6 15221 /* The signature data blob. The signature is computed against the message 15222 * formed by TSAN ID concatenated with the NONCE value. Refer to SF-115479-TC 15223 * for more information also in respect to the private keys that are used to 15224 * sign the message based on TSAN pre/post-binding authentication procedure. 15225 */ 15226 #define MC_CMD_TSA_BIND_OUT_GET_ID_SIG_OFST 14 15227 #define MC_CMD_TSA_BIND_OUT_GET_ID_SIG_LEN 1 15228 #define MC_CMD_TSA_BIND_OUT_GET_ID_SIG_MINNUM 1 15229 #define MC_CMD_TSA_BIND_OUT_GET_ID_SIG_MAXNUM 238 15230 15231 /* MC_CMD_TSA_BIND_OUT_GET_TICKET msgresponse */ 15232 #define MC_CMD_TSA_BIND_OUT_GET_TICKET_LENMIN 5 15233 #define MC_CMD_TSA_BIND_OUT_GET_TICKET_LENMAX 252 15234 #define MC_CMD_TSA_BIND_OUT_GET_TICKET_LEN(num) (4+1*(num)) 15235 /* The operation completion code. */ 15236 #define MC_CMD_TSA_BIND_OUT_GET_TICKET_OP_OFST 0 15237 /* The ticket represents the data blob construct that TSAN sends to TSAC as 15238 * part of the binding protocol. From the TSAN perspective the ticket is an 15239 * opaque construct. For more info refer to SF-115479-TC. 15240 */ 15241 #define MC_CMD_TSA_BIND_OUT_GET_TICKET_TICKET_OFST 4 15242 #define MC_CMD_TSA_BIND_OUT_GET_TICKET_TICKET_LEN 1 15243 #define MC_CMD_TSA_BIND_OUT_GET_TICKET_TICKET_MINNUM 1 15244 #define MC_CMD_TSA_BIND_OUT_GET_TICKET_TICKET_MAXNUM 248 15245 15246 /* MC_CMD_TSA_BIND_OUT_SET_KEY msgresponse */ 15247 #define MC_CMD_TSA_BIND_OUT_SET_KEY_LEN 4 15248 /* The operation completion code. */ 15249 #define MC_CMD_TSA_BIND_OUT_SET_KEY_OP_OFST 0 15250 15251 /* MC_CMD_TSA_BIND_OUT_UNBIND msgresponse */ 15252 #define MC_CMD_TSA_BIND_OUT_UNBIND_LEN 8 15253 /* Same as MC_CMD_ERR field, but included as 0 in success cases */ 15254 #define MC_CMD_TSA_BIND_OUT_UNBIND_RESULT_OFST 0 15255 /* Extra status information */ 15256 #define MC_CMD_TSA_BIND_OUT_UNBIND_INFO_OFST 4 15257 /* enum: Unbind successful. */ 15258 #define MC_CMD_TSA_BIND_OUT_UNBIND_OK_UNBOUND 0x0 15259 /* enum: TSANID mismatch */ 15260 #define MC_CMD_TSA_BIND_OUT_UNBIND_ERR_BAD_TSANID 0x1 15261 /* enum: Unable to remove the binding ticket from persistent storage. */ 15262 #define MC_CMD_TSA_BIND_OUT_UNBIND_ERR_REMOVE_TICKET 0x2 15263 /* enum: TSAN is not bound to a binding ticket. */ 15264 #define MC_CMD_TSA_BIND_OUT_UNBIND_ERR_NOT_BOUND 0x3 15265 15266 15267 /***********************************/ 15268 /* MC_CMD_MANAGE_SECURITY_RULESET_CACHE 15269 * Manage the persistent NVRAM cache of security rules created with 15270 * MC_CMD_SET_SECURITY_RULE. Note that the cache is not automatically updated 15271 * as rules are added or removed; the active ruleset must be explicitly 15272 * committed to the cache. The cache may also be explicitly invalidated, 15273 * without affecting the currently active ruleset. When the cache is valid, it 15274 * will be loaded at power on or MC reboot, instead of the default ruleset. 15275 * Rollback of the currently active ruleset to the cached version (when it is 15276 * valid) is also supported. (Medford-only; for use by SolarSecure apps, not 15277 * directly by drivers. See SF-114946-SW.) NOTE - this message definition is 15278 * provisional. It has not yet been used in any released code and may change 15279 * during development. This note will be removed once it is regarded as stable. 15280 */ 15281 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE 0x11a 15282 #undef MC_CMD_0x11a_PRIVILEGE_CTG 15283 15284 #define MC_CMD_0x11a_PRIVILEGE_CTG SRIOV_CTG_ADMIN 15285 15286 /* MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN msgrequest */ 15287 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_LEN 4 15288 /* the operation to perform */ 15289 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_OP_OFST 0 15290 /* enum: reports the ruleset version that is cached in persistent storage but 15291 * performs no other action 15292 */ 15293 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_OP_GET_CACHED_VERSION 0x0 15294 /* enum: rolls back the active state to the cached version. (May fail with 15295 * ENOENT if there is no valid cached version.) 15296 */ 15297 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_OP_ROLLBACK 0x1 15298 /* enum: commits the active state to the persistent cache */ 15299 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_OP_COMMIT 0x2 15300 /* enum: invalidates the persistent cache without affecting the active state */ 15301 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_OP_INVALIDATE 0x3 15302 15303 /* MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT msgresponse */ 15304 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_LENMIN 5 15305 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_LENMAX 252 15306 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_LEN(num) (4+1*(num)) 15307 /* indicates whether the persistent cache is valid (after completion of the 15308 * requested operation in the case of rollback, commit, or invalidate) 15309 */ 15310 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_STATE_OFST 0 15311 /* enum: persistent cache is invalid (the VERSION field will be empty in this 15312 * case) 15313 */ 15314 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_STATE_INVALID 0x0 15315 /* enum: persistent cache is valid */ 15316 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_STATE_VALID 0x1 15317 /* cached ruleset version (after completion of the requested operation, in the 15318 * case of rollback, commit, or invalidate) as an opaque hash value in the same 15319 * form as MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_VERSION 15320 */ 15321 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_VERSION_OFST 4 15322 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_VERSION_LEN 1 15323 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_VERSION_MINNUM 1 15324 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_VERSION_MAXNUM 248 15325 15326 15327 /***********************************/ 15328 /* MC_CMD_NVRAM_PRIVATE_APPEND 15329 * Append a single TLV to the MC_USAGE_TLV partition. Returns MC_CMD_ERR_EEXIST 15330 * if the tag is already present. 15331 */ 15332 #define MC_CMD_NVRAM_PRIVATE_APPEND 0x11c 15333 #undef MC_CMD_0x11c_PRIVILEGE_CTG 15334 15335 #define MC_CMD_0x11c_PRIVILEGE_CTG SRIOV_CTG_ADMIN 15336 15337 /* MC_CMD_NVRAM_PRIVATE_APPEND_IN msgrequest */ 15338 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_LENMIN 9 15339 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_LENMAX 252 15340 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_LEN(num) (8+1*(num)) 15341 /* The tag to be appended */ 15342 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_TAG_OFST 0 15343 /* The length of the data */ 15344 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_LENGTH_OFST 4 15345 /* The data to be contained in the TLV structure */ 15346 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_OFST 8 15347 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_LEN 1 15348 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_MINNUM 1 15349 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_MAXNUM 244 15350 15351 /* MC_CMD_NVRAM_PRIVATE_APPEND_OUT msgresponse */ 15352 #define MC_CMD_NVRAM_PRIVATE_APPEND_OUT_LEN 0 15353 15354 15355 /***********************************/ 15356 /* MC_CMD_XPM_VERIFY_CONTENTS 15357 * Verify that the contents of the XPM memory is correct (Medford only). This 15358 * is used during manufacture to check that the XPM memory has been programmed 15359 * correctly at ATE. 15360 */ 15361 #define MC_CMD_XPM_VERIFY_CONTENTS 0x11b 15362 #undef MC_CMD_0x11b_PRIVILEGE_CTG 15363 15364 #define MC_CMD_0x11b_PRIVILEGE_CTG SRIOV_CTG_ADMIN 15365 15366 /* MC_CMD_XPM_VERIFY_CONTENTS_IN msgrequest */ 15367 #define MC_CMD_XPM_VERIFY_CONTENTS_IN_LEN 4 15368 /* Data type to be checked */ 15369 #define MC_CMD_XPM_VERIFY_CONTENTS_IN_DATA_TYPE_OFST 0 15370 15371 /* MC_CMD_XPM_VERIFY_CONTENTS_OUT msgresponse */ 15372 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_LENMIN 12 15373 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_LENMAX 252 15374 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_LEN(num) (12+1*(num)) 15375 /* Number of sectors found (test builds only) */ 15376 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_NUM_SECTORS_OFST 0 15377 /* Number of bytes found (test builds only) */ 15378 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_NUM_BYTES_OFST 4 15379 /* Length of signature */ 15380 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIG_LENGTH_OFST 8 15381 /* Signature */ 15382 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_OFST 12 15383 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_LEN 1 15384 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_MINNUM 0 15385 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_MAXNUM 240 15386 15387 15388 /***********************************/ 15389 /* MC_CMD_SET_EVQ_TMR 15390 * Update the timer load, timer reload and timer mode values for a given EVQ. 15391 * The requested timer values (in TMR_LOAD_REQ_NS and TMR_RELOAD_REQ_NS) will 15392 * be rounded up to the granularity supported by the hardware, then truncated 15393 * to the range supported by the hardware. The resulting value after the 15394 * rounding and truncation will be returned to the caller (in TMR_LOAD_ACT_NS 15395 * and TMR_RELOAD_ACT_NS). 15396 */ 15397 #define MC_CMD_SET_EVQ_TMR 0x120 15398 #undef MC_CMD_0x120_PRIVILEGE_CTG 15399 15400 #define MC_CMD_0x120_PRIVILEGE_CTG SRIOV_CTG_GENERAL 15401 15402 /* MC_CMD_SET_EVQ_TMR_IN msgrequest */ 15403 #define MC_CMD_SET_EVQ_TMR_IN_LEN 16 15404 /* Function-relative queue instance */ 15405 #define MC_CMD_SET_EVQ_TMR_IN_INSTANCE_OFST 0 15406 /* Requested value for timer load (in nanoseconds) */ 15407 #define MC_CMD_SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS_OFST 4 15408 /* Requested value for timer reload (in nanoseconds) */ 15409 #define MC_CMD_SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS_OFST 8 15410 /* Timer mode. Meanings as per EVQ_TMR_REG.TC_TIMER_VAL */ 15411 #define MC_CMD_SET_EVQ_TMR_IN_TMR_MODE_OFST 12 15412 #define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_DIS 0x0 /* enum */ 15413 #define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_IMMED_START 0x1 /* enum */ 15414 #define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_TRIG_START 0x2 /* enum */ 15415 #define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_INT_HLDOFF 0x3 /* enum */ 15416 15417 /* MC_CMD_SET_EVQ_TMR_OUT msgresponse */ 15418 #define MC_CMD_SET_EVQ_TMR_OUT_LEN 8 15419 /* Actual value for timer load (in nanoseconds) */ 15420 #define MC_CMD_SET_EVQ_TMR_OUT_TMR_LOAD_ACT_NS_OFST 0 15421 /* Actual value for timer reload (in nanoseconds) */ 15422 #define MC_CMD_SET_EVQ_TMR_OUT_TMR_RELOAD_ACT_NS_OFST 4 15423 15424 15425 /***********************************/ 15426 /* MC_CMD_GET_EVQ_TMR_PROPERTIES 15427 * Query properties about the event queue timers. 15428 */ 15429 #define MC_CMD_GET_EVQ_TMR_PROPERTIES 0x122 15430 #undef MC_CMD_0x122_PRIVILEGE_CTG 15431 15432 #define MC_CMD_0x122_PRIVILEGE_CTG SRIOV_CTG_GENERAL 15433 15434 /* MC_CMD_GET_EVQ_TMR_PROPERTIES_IN msgrequest */ 15435 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_IN_LEN 0 15436 15437 /* MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT msgresponse */ 15438 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN 36 15439 /* Reserved for future use. */ 15440 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_FLAGS_OFST 0 15441 /* For timers updated via writes to EVQ_TMR_REG, this is the time interval (in 15442 * nanoseconds) for each increment of the timer load/reload count. The 15443 * requested duration of a timer is this value multiplied by the timer 15444 * load/reload count. 15445 */ 15446 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_NS_PER_COUNT_OFST 4 15447 /* For timers updated via writes to EVQ_TMR_REG, this is the maximum value 15448 * allowed for timer load/reload counts. 15449 */ 15450 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_MAX_COUNT_OFST 8 15451 /* For timers updated via writes to EVQ_TMR_REG, timer load/reload counts not a 15452 * multiple of this step size will be rounded in an implementation defined 15453 * manner. 15454 */ 15455 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_STEP_OFST 12 15456 /* Maximum timer duration (in nanoseconds) for timers updated via MCDI. Only 15457 * meaningful if MC_CMD_SET_EVQ_TMR is implemented. 15458 */ 15459 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_MAX_NS_OFST 16 15460 /* Timer durations requested via MCDI that are not a multiple of this step size 15461 * will be rounded up. Only meaningful if MC_CMD_SET_EVQ_TMR is implemented. 15462 */ 15463 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_STEP_NS_OFST 20 15464 /* For timers updated using the bug35388 workaround, this is the time interval 15465 * (in nanoseconds) for each increment of the timer load/reload count. The 15466 * requested duration of a timer is this value multiplied by the timer 15467 * load/reload count. This field is only meaningful if the bug35388 workaround 15468 * is enabled. 15469 */ 15470 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_NS_PER_COUNT_OFST 24 15471 /* For timers updated using the bug35388 workaround, this is the maximum value 15472 * allowed for timer load/reload counts. This field is only meaningful if the 15473 * bug35388 workaround is enabled. 15474 */ 15475 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_MAX_COUNT_OFST 28 15476 /* For timers updated using the bug35388 workaround, timer load/reload counts 15477 * not a multiple of this step size will be rounded in an implementation 15478 * defined manner. This field is only meaningful if the bug35388 workaround is 15479 * enabled. 15480 */ 15481 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_STEP_OFST 32 15482 15483 15484 /***********************************/ 15485 /* MC_CMD_ALLOCATE_TX_VFIFO_CP 15486 * When we use the TX_vFIFO_ULL mode, we can allocate common pools using the 15487 * non used switch buffers. 15488 */ 15489 #define MC_CMD_ALLOCATE_TX_VFIFO_CP 0x11d 15490 #undef MC_CMD_0x11d_PRIVILEGE_CTG 15491 15492 #define MC_CMD_0x11d_PRIVILEGE_CTG SRIOV_CTG_ADMIN 15493 15494 /* MC_CMD_ALLOCATE_TX_VFIFO_CP_IN msgrequest */ 15495 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_LEN 20 15496 /* Desired instance. Must be set to a specific instance, which is a function 15497 * local queue index. 15498 */ 15499 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_INSTANCE_OFST 0 15500 /* Will the common pool be used as TX_vFIFO_ULL (1) */ 15501 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_MODE_OFST 4 15502 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_ENABLED 0x1 /* enum */ 15503 /* enum: Using this interface without TX_vFIFO_ULL is not supported for now */ 15504 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_DISABLED 0x0 15505 /* Number of buffers to reserve for the common pool */ 15506 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_SIZE_OFST 8 15507 /* TX datapath to which the Common Pool is connected to. */ 15508 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_INGRESS_OFST 12 15509 /* enum: Extracts information from function */ 15510 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_USE_FUNCTION_VALUE -0x1 15511 /* Network port or RX Engine to which the common pool connects. */ 15512 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_EGRESS_OFST 16 15513 /* enum: Extracts information from function */ 15514 /* MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_USE_FUNCTION_VALUE -0x1 */ 15515 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT0 0x0 /* enum */ 15516 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT1 0x1 /* enum */ 15517 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT2 0x2 /* enum */ 15518 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT3 0x3 /* enum */ 15519 /* enum: To enable Switch loopback with Rx engine 0 */ 15520 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_RX_ENGINE0 0x4 15521 /* enum: To enable Switch loopback with Rx engine 1 */ 15522 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_RX_ENGINE1 0x5 15523 15524 /* MC_CMD_ALLOCATE_TX_VFIFO_CP_OUT msgresponse */ 15525 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_OUT_LEN 4 15526 /* ID of the common pool allocated */ 15527 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_OUT_CP_ID_OFST 0 15528 15529 15530 /***********************************/ 15531 /* MC_CMD_ALLOCATE_TX_VFIFO_VFIFO 15532 * When we use the TX_vFIFO_ULL mode, we can allocate vFIFOs using the 15533 * previously allocated common pools. 15534 */ 15535 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO 0x11e 15536 #undef MC_CMD_0x11e_PRIVILEGE_CTG 15537 15538 #define MC_CMD_0x11e_PRIVILEGE_CTG SRIOV_CTG_ADMIN 15539 15540 /* MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN msgrequest */ 15541 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_LEN 20 15542 /* Common pool previously allocated to which the new vFIFO will be associated 15543 */ 15544 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_CP_OFST 0 15545 /* Port or RX engine to associate the vFIFO egress */ 15546 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_EGRESS_OFST 4 15547 /* enum: Extracts information from common pool */ 15548 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_USE_CP_VALUE -0x1 15549 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT0 0x0 /* enum */ 15550 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT1 0x1 /* enum */ 15551 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT2 0x2 /* enum */ 15552 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT3 0x3 /* enum */ 15553 /* enum: To enable Switch loopback with Rx engine 0 */ 15554 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_RX_ENGINE0 0x4 15555 /* enum: To enable Switch loopback with Rx engine 1 */ 15556 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_RX_ENGINE1 0x5 15557 /* Minimum number of buffers that the pool must have */ 15558 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_SIZE_OFST 8 15559 /* enum: Do not check the space available */ 15560 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_NO_MINIMUM 0x0 15561 /* Will the vFIFO be used as TX_vFIFO_ULL */ 15562 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_MODE_OFST 12 15563 /* Network priority of the vFIFO,if applicable */ 15564 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PRIORITY_OFST 16 15565 /* enum: Search for the lowest unused priority */ 15566 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_LOWEST_AVAILABLE -0x1 15567 15568 /* MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT msgresponse */ 15569 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_LEN 8 15570 /* Short vFIFO ID */ 15571 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_VID_OFST 0 15572 /* Network priority of the vFIFO */ 15573 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_PRIORITY_OFST 4 15574 15575 15576 /***********************************/ 15577 /* MC_CMD_TEARDOWN_TX_VFIFO_VF 15578 * This interface clears the configuration of the given vFIFO and leaves it 15579 * ready to be re-used. 15580 */ 15581 #define MC_CMD_TEARDOWN_TX_VFIFO_VF 0x11f 15582 #undef MC_CMD_0x11f_PRIVILEGE_CTG 15583 15584 #define MC_CMD_0x11f_PRIVILEGE_CTG SRIOV_CTG_ADMIN 15585 15586 /* MC_CMD_TEARDOWN_TX_VFIFO_VF_IN msgrequest */ 15587 #define MC_CMD_TEARDOWN_TX_VFIFO_VF_IN_LEN 4 15588 /* Short vFIFO ID */ 15589 #define MC_CMD_TEARDOWN_TX_VFIFO_VF_IN_VFIFO_OFST 0 15590 15591 /* MC_CMD_TEARDOWN_TX_VFIFO_VF_OUT msgresponse */ 15592 #define MC_CMD_TEARDOWN_TX_VFIFO_VF_OUT_LEN 0 15593 15594 15595 /***********************************/ 15596 /* MC_CMD_DEALLOCATE_TX_VFIFO_CP 15597 * This interface clears the configuration of the given common pool and leaves 15598 * it ready to be re-used. 15599 */ 15600 #define MC_CMD_DEALLOCATE_TX_VFIFO_CP 0x121 15601 #undef MC_CMD_0x121_PRIVILEGE_CTG 15602 15603 #define MC_CMD_0x121_PRIVILEGE_CTG SRIOV_CTG_ADMIN 15604 15605 /* MC_CMD_DEALLOCATE_TX_VFIFO_CP_IN msgrequest */ 15606 #define MC_CMD_DEALLOCATE_TX_VFIFO_CP_IN_LEN 4 15607 /* Common pool ID given when pool allocated */ 15608 #define MC_CMD_DEALLOCATE_TX_VFIFO_CP_IN_POOL_ID_OFST 0 15609 15610 /* MC_CMD_DEALLOCATE_TX_VFIFO_CP_OUT msgresponse */ 15611 #define MC_CMD_DEALLOCATE_TX_VFIFO_CP_OUT_LEN 0 15612 15613 15614 /***********************************/ 15615 /* MC_CMD_REKEY 15616 * This request causes the NIC to generate a new per-NIC key and program it 15617 * into the write-once memory. During the process all flash partitions that are 15618 * protected with a CMAC are verified with the old per-NIC key and then signed 15619 * with the new per-NIC key. If the NIC has already reached its rekey limit the 15620 * REKEY op will return MC_CMD_ERR_ERANGE. The REKEY op may block until 15621 * completion or it may return 0 and continue processing, therefore the caller 15622 * must poll at least once to confirm that the rekeying has completed. The POLL 15623 * operation returns MC_CMD_ERR_EBUSY if the rekey process is still running 15624 * otherwise it will return the result of the last completed rekey operation, 15625 * or 0 if there has not been a previous rekey. 15626 */ 15627 #define MC_CMD_REKEY 0x123 15628 #undef MC_CMD_0x123_PRIVILEGE_CTG 15629 15630 #define MC_CMD_0x123_PRIVILEGE_CTG SRIOV_CTG_ADMIN 15631 15632 /* MC_CMD_REKEY_IN msgrequest */ 15633 #define MC_CMD_REKEY_IN_LEN 4 15634 /* the type of operation requested */ 15635 #define MC_CMD_REKEY_IN_OP_OFST 0 15636 /* enum: Start the rekeying operation */ 15637 #define MC_CMD_REKEY_IN_OP_REKEY 0x0 15638 /* enum: Poll for completion of the rekeying operation */ 15639 #define MC_CMD_REKEY_IN_OP_POLL 0x1 15640 15641 /* MC_CMD_REKEY_OUT msgresponse */ 15642 #define MC_CMD_REKEY_OUT_LEN 0 15643 15644 15645 /***********************************/ 15646 /* MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS 15647 * This interface allows the host to find out how many common pool buffers are 15648 * not yet assigned. 15649 */ 15650 #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS 0x124 15651 #undef MC_CMD_0x124_PRIVILEGE_CTG 15652 15653 #define MC_CMD_0x124_PRIVILEGE_CTG SRIOV_CTG_ADMIN 15654 15655 /* MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_IN msgrequest */ 15656 #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_IN_LEN 0 15657 15658 /* MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT msgresponse */ 15659 #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_LEN 8 15660 /* Available buffers for the ENG to NET vFIFOs. */ 15661 #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_NET_OFST 0 15662 /* Available buffers for the ENG to ENG and NET to ENG vFIFOs. */ 15663 #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_ENG_OFST 4 15664 15665 15666 /***********************************/ 15667 /* MC_CMD_SET_SECURITY_FUSES 15668 * Change the security level of the adapter by setting bits in the write-once 15669 * memory. The firmware maps each flag in the message to a set of one or more 15670 * hardware-defined or software-defined bits and sets these bits in the write- 15671 * once memory. For Medford the hardware-defined bits are defined in 15672 * SF-112079-PS 5.3, the software-defined bits are defined in xpm.h. Returns 0 15673 * if all of the required bits were set and returns MC_CMD_ERR_EIO if any of 15674 * the required bits were not set. 15675 */ 15676 #define MC_CMD_SET_SECURITY_FUSES 0x126 15677 #undef MC_CMD_0x126_PRIVILEGE_CTG 15678 15679 #define MC_CMD_0x126_PRIVILEGE_CTG SRIOV_CTG_ADMIN 15680 15681 /* MC_CMD_SET_SECURITY_FUSES_IN msgrequest */ 15682 #define MC_CMD_SET_SECURITY_FUSES_IN_LEN 4 15683 /* Flags specifying what type of security features are being set */ 15684 #define MC_CMD_SET_SECURITY_FUSES_IN_FLAGS_OFST 0 15685 #define MC_CMD_SET_SECURITY_FUSES_IN_SECURE_BOOT_LBN 0 15686 #define MC_CMD_SET_SECURITY_FUSES_IN_SECURE_BOOT_WIDTH 1 15687 #define MC_CMD_SET_SECURITY_FUSES_IN_REJECT_TEST_SIGNED_LBN 1 15688 #define MC_CMD_SET_SECURITY_FUSES_IN_REJECT_TEST_SIGNED_WIDTH 1 15689 15690 /* MC_CMD_SET_SECURITY_FUSES_OUT msgresponse */ 15691 #define MC_CMD_SET_SECURITY_FUSES_OUT_LEN 0 15692 15693 #endif /* _SIENA_MC_DRIVER_PCOL_H */ 15694