1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright 2008-2013 Solarflare Communications Inc. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 */ 29 30 #ifndef _SIENA_MC_DRIVER_PCOL_H 31 #define _SIENA_MC_DRIVER_PCOL_H 32 33 34 /* Values to be written into FMCR_CZ_RESET_STATE_REG to control boot. */ 35 /* Power-on reset state */ 36 #define MC_FW_STATE_POR (1) 37 /* If this is set in MC_RESET_STATE_REG then it should be 38 * possible to jump into IMEM without loading code from flash. */ 39 #define MC_FW_WARM_BOOT_OK (2) 40 /* The MC main image has started to boot. */ 41 #define MC_FW_STATE_BOOTING (4) 42 /* The Scheduler has started. */ 43 #define MC_FW_STATE_SCHED (8) 44 /* If this is set in MC_RESET_STATE_REG then it should be 45 * possible to jump into IMEM without loading code from flash. 46 * Unlike a warm boot, assume DMEM has been reloaded, so that 47 * the MC persistent data must be reinitialised. */ 48 #define MC_FW_TEPID_BOOT_OK (16) 49 /* We have entered the main firmware via recovery mode. This 50 * means that MC persistent data must be reinitialised, but that 51 * we shouldn't touch PCIe config. */ 52 #define MC_FW_RECOVERY_MODE_PCIE_INIT_OK (32) 53 /* BIST state has been initialized */ 54 #define MC_FW_BIST_INIT_OK (128) 55 56 /* Siena MC shared memmory offsets */ 57 /* The 'doorbell' addresses are hard-wired to alert the MC when written */ 58 #define MC_SMEM_P0_DOORBELL_OFST 0x000 59 #define MC_SMEM_P1_DOORBELL_OFST 0x004 60 /* The rest of these are firmware-defined */ 61 #define MC_SMEM_P0_PDU_OFST 0x008 62 #define MC_SMEM_P1_PDU_OFST 0x108 63 #define MC_SMEM_PDU_LEN 0x100 64 #define MC_SMEM_P0_PTP_TIME_OFST 0x7f0 65 #define MC_SMEM_P0_STATUS_OFST 0x7f8 66 #define MC_SMEM_P1_STATUS_OFST 0x7fc 67 68 /* Values to be written to the per-port status dword in shared 69 * memory on reboot and assert */ 70 #define MC_STATUS_DWORD_REBOOT (0xb007b007) 71 #define MC_STATUS_DWORD_ASSERT (0xdeaddead) 72 73 /* Check whether an mcfw version (in host order) belongs to a bootloader */ 74 #define MC_FW_VERSION_IS_BOOTLOADER(_v) (((_v) >> 16) == 0xb007) 75 76 /* The current version of the MCDI protocol. 77 * 78 * Note that the ROM burnt into the card only talks V0, so at the very 79 * least every driver must support version 0 and MCDI_PCOL_VERSION 80 */ 81 #ifdef WITH_MCDI_V2 82 #define MCDI_PCOL_VERSION 2 83 #else 84 #define MCDI_PCOL_VERSION 1 85 #endif 86 87 /* Unused commands: 0x23, 0x27, 0x30, 0x31 */ 88 89 /* MCDI version 1 90 * 91 * Each MCDI request starts with an MCDI_HEADER, which is a 32bit 92 * structure, filled in by the client. 93 * 94 * 0 7 8 16 20 22 23 24 31 95 * | CODE | R | LEN | SEQ | Rsvd | E | R | XFLAGS | 96 * | | | 97 * | | \--- Response 98 * | \------- Error 99 * \------------------------------ Resync (always set) 100 * 101 * The client writes it's request into MC shared memory, and rings the 102 * doorbell. Each request is completed by either by the MC writting 103 * back into shared memory, or by writting out an event. 104 * 105 * All MCDI commands support completion by shared memory response. Each 106 * request may also contain additional data (accounted for by HEADER.LEN), 107 * and some response's may also contain additional data (again, accounted 108 * for by HEADER.LEN). 109 * 110 * Some MCDI commands support completion by event, in which any associated 111 * response data is included in the event. 112 * 113 * The protocol requires one response to be delivered for every request, a 114 * request should not be sent unless the response for the previous request 115 * has been received (either by polling shared memory, or by receiving 116 * an event). 117 */ 118 119 /** Request/Response structure */ 120 #define MCDI_HEADER_OFST 0 121 #define MCDI_HEADER_CODE_LBN 0 122 #define MCDI_HEADER_CODE_WIDTH 7 123 #define MCDI_HEADER_RESYNC_LBN 7 124 #define MCDI_HEADER_RESYNC_WIDTH 1 125 #define MCDI_HEADER_DATALEN_LBN 8 126 #define MCDI_HEADER_DATALEN_WIDTH 8 127 #define MCDI_HEADER_SEQ_LBN 16 128 #define MCDI_HEADER_SEQ_WIDTH 4 129 #define MCDI_HEADER_RSVD_LBN 20 130 #define MCDI_HEADER_RSVD_WIDTH 1 131 #define MCDI_HEADER_NOT_EPOCH_LBN 21 132 #define MCDI_HEADER_NOT_EPOCH_WIDTH 1 133 #define MCDI_HEADER_ERROR_LBN 22 134 #define MCDI_HEADER_ERROR_WIDTH 1 135 #define MCDI_HEADER_RESPONSE_LBN 23 136 #define MCDI_HEADER_RESPONSE_WIDTH 1 137 #define MCDI_HEADER_XFLAGS_LBN 24 138 #define MCDI_HEADER_XFLAGS_WIDTH 8 139 /* Request response using event */ 140 #define MCDI_HEADER_XFLAGS_EVREQ 0x01 141 /* Request (and signal) early doorbell return */ 142 #define MCDI_HEADER_XFLAGS_DBRET 0x02 143 144 /* Maximum number of payload bytes */ 145 #define MCDI_CTL_SDU_LEN_MAX_V1 0xfc 146 #define MCDI_CTL_SDU_LEN_MAX_V2 0x400 147 148 #ifdef WITH_MCDI_V2 149 #define MCDI_CTL_SDU_LEN_MAX MCDI_CTL_SDU_LEN_MAX_V2 150 #else 151 #define MCDI_CTL_SDU_LEN_MAX MCDI_CTL_SDU_LEN_MAX_V1 152 #endif 153 154 155 /* The MC can generate events for two reasons: 156 * - To advance a shared memory request if XFLAGS_EVREQ was set 157 * - As a notification (link state, i2c event), controlled 158 * via MC_CMD_LOG_CTRL 159 * 160 * Both events share a common structure: 161 * 162 * 0 32 33 36 44 52 60 163 * | Data | Cont | Level | Src | Code | Rsvd | 164 * | 165 * \ There is another event pending in this notification 166 * 167 * If Code==CMDDONE, then the fields are further interpreted as: 168 * 169 * - LEVEL==INFO Command succeeded 170 * - LEVEL==ERR Command failed 171 * 172 * 0 8 16 24 32 173 * | Seq | Datalen | Errno | Rsvd | 174 * 175 * These fields are taken directly out of the standard MCDI header, i.e., 176 * LEVEL==ERR, Datalen == 0 => Reboot 177 * 178 * Events can be squirted out of the UART (using LOG_CTRL) without a 179 * MCDI header. An event can be distinguished from a MCDI response by 180 * examining the first byte which is 0xc0. This corresponds to the 181 * non-existent MCDI command MC_CMD_DEBUG_LOG. 182 * 183 * 0 7 8 184 * | command | Resync | = 0xc0 185 * 186 * Since the event is written in big-endian byte order, this works 187 * providing bits 56-63 of the event are 0xc0. 188 * 189 * 56 60 63 190 * | Rsvd | Code | = 0xc0 191 * 192 * Which means for convenience the event code is 0xc for all MC 193 * generated events. 194 */ 195 #define FSE_AZ_EV_CODE_MCDI_EVRESPONSE 0xc 196 197 198 /* Operation not permitted. */ 199 #define MC_CMD_ERR_EPERM 1 200 /* Non-existent command target */ 201 #define MC_CMD_ERR_ENOENT 2 202 /* assert() has killed the MC */ 203 #define MC_CMD_ERR_EINTR 4 204 /* I/O failure */ 205 #define MC_CMD_ERR_EIO 5 206 /* Already exists */ 207 #define MC_CMD_ERR_EEXIST 6 208 /* Try again */ 209 #define MC_CMD_ERR_EAGAIN 11 210 /* Out of memory */ 211 #define MC_CMD_ERR_ENOMEM 12 212 /* Caller does not hold required locks */ 213 #define MC_CMD_ERR_EACCES 13 214 /* Resource is currently unavailable (e.g. lock contention) */ 215 #define MC_CMD_ERR_EBUSY 16 216 /* No such device */ 217 #define MC_CMD_ERR_ENODEV 19 218 /* Invalid argument to target */ 219 #define MC_CMD_ERR_EINVAL 22 220 /* Broken pipe */ 221 #define MC_CMD_ERR_EPIPE 32 222 /* Read-only */ 223 #define MC_CMD_ERR_EROFS 30 224 /* Out of range */ 225 #define MC_CMD_ERR_ERANGE 34 226 /* Non-recursive resource is already acquired */ 227 #define MC_CMD_ERR_EDEADLK 35 228 /* Operation not implemented */ 229 #define MC_CMD_ERR_ENOSYS 38 230 /* Operation timed out */ 231 #define MC_CMD_ERR_ETIME 62 232 /* Link has been severed */ 233 #define MC_CMD_ERR_ENOLINK 67 234 /* Protocol error */ 235 #define MC_CMD_ERR_EPROTO 71 236 /* Operation not supported */ 237 #define MC_CMD_ERR_ENOTSUP 95 238 /* Address not available */ 239 #define MC_CMD_ERR_EADDRNOTAVAIL 99 240 /* Not connected */ 241 #define MC_CMD_ERR_ENOTCONN 107 242 /* Operation already in progress */ 243 #define MC_CMD_ERR_EALREADY 114 244 245 /* Resource allocation failed. */ 246 #define MC_CMD_ERR_ALLOC_FAIL 0x1000 247 /* V-adaptor not found. */ 248 #define MC_CMD_ERR_NO_VADAPTOR 0x1001 249 /* EVB port not found. */ 250 #define MC_CMD_ERR_NO_EVB_PORT 0x1002 251 /* V-switch not found. */ 252 #define MC_CMD_ERR_NO_VSWITCH 0x1003 253 /* Too many VLAN tags. */ 254 #define MC_CMD_ERR_VLAN_LIMIT 0x1004 255 /* Bad PCI function number. */ 256 #define MC_CMD_ERR_BAD_PCI_FUNC 0x1005 257 /* Invalid VLAN mode. */ 258 #define MC_CMD_ERR_BAD_VLAN_MODE 0x1006 259 /* Invalid v-switch type. */ 260 #define MC_CMD_ERR_BAD_VSWITCH_TYPE 0x1007 261 /* Invalid v-port type. */ 262 #define MC_CMD_ERR_BAD_VPORT_TYPE 0x1008 263 /* MAC address exists. */ 264 #define MC_CMD_ERR_MAC_EXIST 0x1009 265 /* Slave core not present */ 266 #define MC_CMD_ERR_SLAVE_NOT_PRESENT 0x100a 267 /* The datapath is disabled. */ 268 #define MC_CMD_ERR_DATAPATH_DISABLED 0x100b 269 /* The requesting client is not a function */ 270 #define MC_CMD_ERR_CLIENT_NOT_FN 0x100c 271 /* The requested operation might require the 272 command to be passed between MCs, and the 273 transport doesn't support that. Should 274 only ever been seen over the UART. */ 275 #define MC_CMD_ERR_TRANSPORT_NOPROXY 0x100d 276 /* VLAN tag(s) exists */ 277 #define MC_CMD_ERR_VLAN_EXIST 0x100e 278 /* No MAC address assigned to an EVB port */ 279 #define MC_CMD_ERR_NO_MAC_ADDR 0x100f 280 /* Notifies the driver that the request has been relayed 281 * to an admin function for authorization. The driver should 282 * wait for a PROXY_RESPONSE event and then resend its request. 283 * This error code is followed by a 32-bit handle that 284 * helps matching it with the respective PROXY_RESPONSE event. */ 285 #define MC_CMD_ERR_PROXY_PENDING 0x1010 286 #define MC_CMD_ERR_PROXY_PENDING_HANDLE_OFST 4 287 /* The request cannot be passed for authorization because 288 * another request from the same function is currently being 289 * authorized. The drvier should try again later. */ 290 #define MC_CMD_ERR_PROXY_INPROGRESS 0x1011 291 /* Returned by MC_CMD_PROXY_COMPLETE if the caller is not the function 292 * that has enabled proxying or BLOCK_INDEX points to a function that 293 * doesn't await an authorization. */ 294 #define MC_CMD_ERR_PROXY_UNEXPECTED 0x1012 295 /* This code is currently only used internally in FW. Its meaning is that 296 * an operation failed due to lack of SR-IOV privilege. 297 * Normally it is translated to EPERM by send_cmd_err(), 298 * but it may also be used to trigger some special mechanism 299 * for handling such case, e.g. to relay the failed request 300 * to a designated admin function for authorization. */ 301 #define MC_CMD_ERR_NO_PRIVILEGE 0x1013 302 /* Workaround 26807 could not be turned on/off because some functions 303 * have already installed filters. See the comment at 304 * MC_CMD_WORKAROUND_BUG26807. */ 305 #define MC_CMD_ERR_FILTERS_PRESENT 0x1014 306 /* The clock whose frequency you've attempted to set set 307 * doesn't exist on this NIC */ 308 #define MC_CMD_ERR_NO_CLOCK 0x1015 309 /* Returned by MC_CMD_TESTASSERT if the action that should 310 * have caused an assertion failed to do so. */ 311 #define MC_CMD_ERR_UNREACHABLE 0x1016 312 /* This command needs to be processed in the background but there were no 313 * resources to do so. Send it again after a command has completed. */ 314 #define MC_CMD_ERR_QUEUE_FULL 0x1017 315 /* The operation could not be completed because the PCIe link has gone 316 * away. This error code is never expected to be returned over the TLP 317 * transport. */ 318 #define MC_CMD_ERR_NO_PCIE 0x1018 319 /* The operation could not be completed because the datapath has gone 320 * away. This is distinct from MC_CMD_ERR_DATAPATH_DISABLED in that the 321 * datapath absence may be temporary*/ 322 #define MC_CMD_ERR_NO_DATAPATH 0x1019 323 324 #define MC_CMD_ERR_CODE_OFST 0 325 326 /* We define 8 "escape" commands to allow 327 for command number space extension */ 328 329 #define MC_CMD_CMD_SPACE_ESCAPE_0 0x78 330 #define MC_CMD_CMD_SPACE_ESCAPE_1 0x79 331 #define MC_CMD_CMD_SPACE_ESCAPE_2 0x7A 332 #define MC_CMD_CMD_SPACE_ESCAPE_3 0x7B 333 #define MC_CMD_CMD_SPACE_ESCAPE_4 0x7C 334 #define MC_CMD_CMD_SPACE_ESCAPE_5 0x7D 335 #define MC_CMD_CMD_SPACE_ESCAPE_6 0x7E 336 #define MC_CMD_CMD_SPACE_ESCAPE_7 0x7F 337 338 /* Vectors in the boot ROM */ 339 /* Point to the copycode entry point. */ 340 #define SIENA_MC_BOOTROM_COPYCODE_VEC (0x800 - 3 * 0x4) 341 #define HUNT_MC_BOOTROM_COPYCODE_VEC (0x8000 - 3 * 0x4) 342 #define MEDFORD_MC_BOOTROM_COPYCODE_VEC (0x10000 - 3 * 0x4) 343 /* Points to the recovery mode entry point. */ 344 #define SIENA_MC_BOOTROM_NOFLASH_VEC (0x800 - 2 * 0x4) 345 #define HUNT_MC_BOOTROM_NOFLASH_VEC (0x8000 - 2 * 0x4) 346 #define MEDFORD_MC_BOOTROM_NOFLASH_VEC (0x10000 - 2 * 0x4) 347 348 /* The command set exported by the boot ROM (MCDI v0) */ 349 #define MC_CMD_GET_VERSION_V0_SUPPORTED_FUNCS { \ 350 (1 << MC_CMD_READ32) | \ 351 (1 << MC_CMD_WRITE32) | \ 352 (1 << MC_CMD_COPYCODE) | \ 353 (1 << MC_CMD_GET_VERSION), \ 354 0, 0, 0 } 355 356 #define MC_CMD_SENSOR_INFO_OUT_OFFSET_OFST(_x) \ 357 (MC_CMD_SENSOR_ENTRY_OFST + (_x)) 358 359 #define MC_CMD_DBI_WRITE_IN_ADDRESS_OFST(n) \ 360 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \ 361 MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST + \ 362 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN) 363 364 #define MC_CMD_DBI_WRITE_IN_BYTE_MASK_OFST(n) \ 365 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \ 366 MC_CMD_DBIWROP_TYPEDEF_BYTE_MASK_OFST + \ 367 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN) 368 369 #define MC_CMD_DBI_WRITE_IN_VALUE_OFST(n) \ 370 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \ 371 MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST + \ 372 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN) 373 374 /* This may be ORed with an EVB_PORT_ID_xxx constant to pass a non-default 375 * stack ID (which must be in the range 1-255) along with an EVB port ID. 376 */ 377 #define EVB_STACK_ID(n) (((n) & 0xff) << 16) 378 379 380 #ifdef WITH_MCDI_V2 381 382 /* Version 2 adds an optional argument to error returns: the errno value 383 * may be followed by the (0-based) number of the first argument that 384 * could not be processed. 385 */ 386 #define MC_CMD_ERR_ARG_OFST 4 387 388 /* No space */ 389 #define MC_CMD_ERR_ENOSPC 28 390 391 #endif 392 393 /* MCDI_EVENT structuredef */ 394 #define MCDI_EVENT_LEN 8 395 #define MCDI_EVENT_CONT_LBN 32 396 #define MCDI_EVENT_CONT_WIDTH 1 397 #define MCDI_EVENT_LEVEL_LBN 33 398 #define MCDI_EVENT_LEVEL_WIDTH 3 399 /* enum: Info. */ 400 #define MCDI_EVENT_LEVEL_INFO 0x0 401 /* enum: Warning. */ 402 #define MCDI_EVENT_LEVEL_WARN 0x1 403 /* enum: Error. */ 404 #define MCDI_EVENT_LEVEL_ERR 0x2 405 /* enum: Fatal. */ 406 #define MCDI_EVENT_LEVEL_FATAL 0x3 407 #define MCDI_EVENT_DATA_OFST 0 408 #define MCDI_EVENT_DATA_LEN 4 409 #define MCDI_EVENT_CMDDONE_SEQ_LBN 0 410 #define MCDI_EVENT_CMDDONE_SEQ_WIDTH 8 411 #define MCDI_EVENT_CMDDONE_DATALEN_LBN 8 412 #define MCDI_EVENT_CMDDONE_DATALEN_WIDTH 8 413 #define MCDI_EVENT_CMDDONE_ERRNO_LBN 16 414 #define MCDI_EVENT_CMDDONE_ERRNO_WIDTH 8 415 #define MCDI_EVENT_LINKCHANGE_LP_CAP_LBN 0 416 #define MCDI_EVENT_LINKCHANGE_LP_CAP_WIDTH 16 417 #define MCDI_EVENT_LINKCHANGE_SPEED_LBN 16 418 #define MCDI_EVENT_LINKCHANGE_SPEED_WIDTH 4 419 /* enum: 100Mbs */ 420 #define MCDI_EVENT_LINKCHANGE_SPEED_100M 0x1 421 /* enum: 1Gbs */ 422 #define MCDI_EVENT_LINKCHANGE_SPEED_1G 0x2 423 /* enum: 10Gbs */ 424 #define MCDI_EVENT_LINKCHANGE_SPEED_10G 0x3 425 /* enum: 40Gbs */ 426 #define MCDI_EVENT_LINKCHANGE_SPEED_40G 0x4 427 /* enum: 25Gbs */ 428 #define MCDI_EVENT_LINKCHANGE_SPEED_25G 0x5 429 /* enum: 50Gbs */ 430 #define MCDI_EVENT_LINKCHANGE_SPEED_50G 0x6 431 /* enum: 100Gbs */ 432 #define MCDI_EVENT_LINKCHANGE_SPEED_100G 0x7 433 #define MCDI_EVENT_LINKCHANGE_FCNTL_LBN 20 434 #define MCDI_EVENT_LINKCHANGE_FCNTL_WIDTH 4 435 #define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_LBN 24 436 #define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_WIDTH 8 437 #define MCDI_EVENT_SENSOREVT_MONITOR_LBN 0 438 #define MCDI_EVENT_SENSOREVT_MONITOR_WIDTH 8 439 #define MCDI_EVENT_SENSOREVT_STATE_LBN 8 440 #define MCDI_EVENT_SENSOREVT_STATE_WIDTH 8 441 #define MCDI_EVENT_SENSOREVT_VALUE_LBN 16 442 #define MCDI_EVENT_SENSOREVT_VALUE_WIDTH 16 443 #define MCDI_EVENT_FWALERT_DATA_LBN 8 444 #define MCDI_EVENT_FWALERT_DATA_WIDTH 24 445 #define MCDI_EVENT_FWALERT_REASON_LBN 0 446 #define MCDI_EVENT_FWALERT_REASON_WIDTH 8 447 /* enum: SRAM Access. */ 448 #define MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS 0x1 449 #define MCDI_EVENT_FLR_VF_LBN 0 450 #define MCDI_EVENT_FLR_VF_WIDTH 8 451 #define MCDI_EVENT_TX_ERR_TXQ_LBN 0 452 #define MCDI_EVENT_TX_ERR_TXQ_WIDTH 12 453 #define MCDI_EVENT_TX_ERR_TYPE_LBN 12 454 #define MCDI_EVENT_TX_ERR_TYPE_WIDTH 4 455 /* enum: Descriptor loader reported failure */ 456 #define MCDI_EVENT_TX_ERR_DL_FAIL 0x1 457 /* enum: Descriptor ring empty and no EOP seen for packet */ 458 #define MCDI_EVENT_TX_ERR_NO_EOP 0x2 459 /* enum: Overlength packet */ 460 #define MCDI_EVENT_TX_ERR_2BIG 0x3 461 /* enum: Malformed option descriptor */ 462 #define MCDI_EVENT_TX_BAD_OPTDESC 0x5 463 /* enum: Option descriptor part way through a packet */ 464 #define MCDI_EVENT_TX_OPT_IN_PKT 0x8 465 /* enum: DMA or PIO data access error */ 466 #define MCDI_EVENT_TX_ERR_BAD_DMA_OR_PIO 0x9 467 #define MCDI_EVENT_TX_ERR_INFO_LBN 16 468 #define MCDI_EVENT_TX_ERR_INFO_WIDTH 16 469 #define MCDI_EVENT_TX_FLUSH_TO_DRIVER_LBN 12 470 #define MCDI_EVENT_TX_FLUSH_TO_DRIVER_WIDTH 1 471 #define MCDI_EVENT_TX_FLUSH_TXQ_LBN 0 472 #define MCDI_EVENT_TX_FLUSH_TXQ_WIDTH 12 473 #define MCDI_EVENT_PTP_ERR_TYPE_LBN 0 474 #define MCDI_EVENT_PTP_ERR_TYPE_WIDTH 8 475 /* enum: PLL lost lock */ 476 #define MCDI_EVENT_PTP_ERR_PLL_LOST 0x1 477 /* enum: Filter overflow (PDMA) */ 478 #define MCDI_EVENT_PTP_ERR_FILTER 0x2 479 /* enum: FIFO overflow (FPGA) */ 480 #define MCDI_EVENT_PTP_ERR_FIFO 0x3 481 /* enum: Merge queue overflow */ 482 #define MCDI_EVENT_PTP_ERR_QUEUE 0x4 483 #define MCDI_EVENT_AOE_ERR_TYPE_LBN 0 484 #define MCDI_EVENT_AOE_ERR_TYPE_WIDTH 8 485 /* enum: AOE failed to load - no valid image? */ 486 #define MCDI_EVENT_AOE_NO_LOAD 0x1 487 /* enum: AOE FC reported an exception */ 488 #define MCDI_EVENT_AOE_FC_ASSERT 0x2 489 /* enum: AOE FC watchdogged */ 490 #define MCDI_EVENT_AOE_FC_WATCHDOG 0x3 491 /* enum: AOE FC failed to start */ 492 #define MCDI_EVENT_AOE_FC_NO_START 0x4 493 /* enum: Generic AOE fault - likely to have been reported via other means too 494 * but intended for use by aoex driver. 495 */ 496 #define MCDI_EVENT_AOE_FAULT 0x5 497 /* enum: Results of reprogramming the CPLD (status in AOE_ERR_DATA) */ 498 #define MCDI_EVENT_AOE_CPLD_REPROGRAMMED 0x6 499 /* enum: AOE loaded successfully */ 500 #define MCDI_EVENT_AOE_LOAD 0x7 501 /* enum: AOE DMA operation completed (LSB of HOST_HANDLE in AOE_ERR_DATA) */ 502 #define MCDI_EVENT_AOE_DMA 0x8 503 /* enum: AOE byteblaster connected/disconnected (Connection status in 504 * AOE_ERR_DATA) 505 */ 506 #define MCDI_EVENT_AOE_BYTEBLASTER 0x9 507 /* enum: DDR ECC status update */ 508 #define MCDI_EVENT_AOE_DDR_ECC_STATUS 0xa 509 /* enum: PTP status update */ 510 #define MCDI_EVENT_AOE_PTP_STATUS 0xb 511 /* enum: FPGA header incorrect */ 512 #define MCDI_EVENT_AOE_FPGA_LOAD_HEADER_ERR 0xc 513 /* enum: FPGA Powered Off due to error in powering up FPGA */ 514 #define MCDI_EVENT_AOE_FPGA_POWER_OFF 0xd 515 /* enum: AOE FPGA load failed due to MC to MUM communication failure */ 516 #define MCDI_EVENT_AOE_FPGA_LOAD_FAILED 0xe 517 /* enum: Notify that invalid flash type detected */ 518 #define MCDI_EVENT_AOE_INVALID_FPGA_FLASH_TYPE 0xf 519 /* enum: Notify that the attempt to run FPGA Controller firmware timedout */ 520 #define MCDI_EVENT_AOE_FC_RUN_TIMEDOUT 0x10 521 /* enum: Failure to probe one or more FPGA boot flash chips */ 522 #define MCDI_EVENT_AOE_FPGA_BOOT_FLASH_INVALID 0x11 523 /* enum: FPGA boot-flash contains an invalid image header */ 524 #define MCDI_EVENT_AOE_FPGA_BOOT_FLASH_HDR_INVALID 0x12 525 /* enum: Failed to program clocks required by the FPGA */ 526 #define MCDI_EVENT_AOE_FPGA_CLOCKS_PROGRAM_FAILED 0x13 527 /* enum: Notify that FPGA Controller is alive to serve MCDI requests */ 528 #define MCDI_EVENT_AOE_FC_RUNNING 0x14 529 #define MCDI_EVENT_AOE_ERR_DATA_LBN 8 530 #define MCDI_EVENT_AOE_ERR_DATA_WIDTH 8 531 #define MCDI_EVENT_AOE_ERR_FC_ASSERT_INFO_LBN 8 532 #define MCDI_EVENT_AOE_ERR_FC_ASSERT_INFO_WIDTH 8 533 /* enum: FC Assert happened, but the register information is not available */ 534 #define MCDI_EVENT_AOE_ERR_FC_ASSERT_SEEN 0x0 535 /* enum: The register information for FC Assert is ready for readinng by driver 536 */ 537 #define MCDI_EVENT_AOE_ERR_FC_ASSERT_DATA_READY 0x1 538 #define MCDI_EVENT_AOE_ERR_CODE_FPGA_HEADER_VERIFY_FAILED_LBN 8 539 #define MCDI_EVENT_AOE_ERR_CODE_FPGA_HEADER_VERIFY_FAILED_WIDTH 8 540 /* enum: Reading from NV failed */ 541 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_NV_READ_FAIL 0x0 542 /* enum: Invalid Magic Number if FPGA header */ 543 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_MAGIC_FAIL 0x1 544 /* enum: Invalid Silicon type detected in header */ 545 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_SILICON_TYPE 0x2 546 /* enum: Unsupported VRatio */ 547 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_VRATIO 0x3 548 /* enum: Unsupported DDR Type */ 549 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_TYPE 0x4 550 /* enum: DDR Voltage out of supported range */ 551 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_VOLTAGE 0x5 552 /* enum: Unsupported DDR speed */ 553 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_SPEED 0x6 554 /* enum: Unsupported DDR size */ 555 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_SIZE 0x7 556 /* enum: Unsupported DDR rank */ 557 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_RANK 0x8 558 #define MCDI_EVENT_AOE_ERR_CODE_INVALID_FPGA_FLASH_TYPE_INFO_LBN 8 559 #define MCDI_EVENT_AOE_ERR_CODE_INVALID_FPGA_FLASH_TYPE_INFO_WIDTH 8 560 /* enum: Primary boot flash */ 561 #define MCDI_EVENT_AOE_FLASH_TYPE_BOOT_PRIMARY 0x0 562 /* enum: Secondary boot flash */ 563 #define MCDI_EVENT_AOE_FLASH_TYPE_BOOT_SECONDARY 0x1 564 #define MCDI_EVENT_AOE_ERR_CODE_FPGA_POWER_OFF_LBN 8 565 #define MCDI_EVENT_AOE_ERR_CODE_FPGA_POWER_OFF_WIDTH 8 566 #define MCDI_EVENT_AOE_ERR_CODE_FPGA_LOAD_FAILED_LBN 8 567 #define MCDI_EVENT_AOE_ERR_CODE_FPGA_LOAD_FAILED_WIDTH 8 568 #define MCDI_EVENT_RX_ERR_RXQ_LBN 0 569 #define MCDI_EVENT_RX_ERR_RXQ_WIDTH 12 570 #define MCDI_EVENT_RX_ERR_TYPE_LBN 12 571 #define MCDI_EVENT_RX_ERR_TYPE_WIDTH 4 572 #define MCDI_EVENT_RX_ERR_INFO_LBN 16 573 #define MCDI_EVENT_RX_ERR_INFO_WIDTH 16 574 #define MCDI_EVENT_RX_FLUSH_TO_DRIVER_LBN 12 575 #define MCDI_EVENT_RX_FLUSH_TO_DRIVER_WIDTH 1 576 #define MCDI_EVENT_RX_FLUSH_RXQ_LBN 0 577 #define MCDI_EVENT_RX_FLUSH_RXQ_WIDTH 12 578 #define MCDI_EVENT_MC_REBOOT_COUNT_LBN 0 579 #define MCDI_EVENT_MC_REBOOT_COUNT_WIDTH 16 580 #define MCDI_EVENT_MUM_ERR_TYPE_LBN 0 581 #define MCDI_EVENT_MUM_ERR_TYPE_WIDTH 8 582 /* enum: MUM failed to load - no valid image? */ 583 #define MCDI_EVENT_MUM_NO_LOAD 0x1 584 /* enum: MUM f/w reported an exception */ 585 #define MCDI_EVENT_MUM_ASSERT 0x2 586 /* enum: MUM not kicking watchdog */ 587 #define MCDI_EVENT_MUM_WATCHDOG 0x3 588 #define MCDI_EVENT_MUM_ERR_DATA_LBN 8 589 #define MCDI_EVENT_MUM_ERR_DATA_WIDTH 8 590 #define MCDI_EVENT_DBRET_SEQ_LBN 0 591 #define MCDI_EVENT_DBRET_SEQ_WIDTH 8 592 #define MCDI_EVENT_SUC_ERR_TYPE_LBN 0 593 #define MCDI_EVENT_SUC_ERR_TYPE_WIDTH 8 594 /* enum: Corrupted or bad SUC application. */ 595 #define MCDI_EVENT_SUC_BAD_APP 0x1 596 /* enum: SUC application reported an assert. */ 597 #define MCDI_EVENT_SUC_ASSERT 0x2 598 /* enum: SUC application reported an exception. */ 599 #define MCDI_EVENT_SUC_EXCEPTION 0x3 600 /* enum: SUC watchdog timer expired. */ 601 #define MCDI_EVENT_SUC_WATCHDOG 0x4 602 #define MCDI_EVENT_SUC_ERR_ADDRESS_LBN 8 603 #define MCDI_EVENT_SUC_ERR_ADDRESS_WIDTH 24 604 #define MCDI_EVENT_SUC_ERR_DATA_LBN 8 605 #define MCDI_EVENT_SUC_ERR_DATA_WIDTH 24 606 #define MCDI_EVENT_DATA_LBN 0 607 #define MCDI_EVENT_DATA_WIDTH 32 608 #define MCDI_EVENT_SRC_LBN 36 609 #define MCDI_EVENT_SRC_WIDTH 8 610 #define MCDI_EVENT_EV_CODE_LBN 60 611 #define MCDI_EVENT_EV_CODE_WIDTH 4 612 #define MCDI_EVENT_CODE_LBN 44 613 #define MCDI_EVENT_CODE_WIDTH 8 614 /* enum: Event generated by host software */ 615 #define MCDI_EVENT_SW_EVENT 0x0 616 /* enum: Bad assert. */ 617 #define MCDI_EVENT_CODE_BADSSERT 0x1 618 /* enum: PM Notice. */ 619 #define MCDI_EVENT_CODE_PMNOTICE 0x2 620 /* enum: Command done. */ 621 #define MCDI_EVENT_CODE_CMDDONE 0x3 622 /* enum: Link change. */ 623 #define MCDI_EVENT_CODE_LINKCHANGE 0x4 624 /* enum: Sensor Event. */ 625 #define MCDI_EVENT_CODE_SENSOREVT 0x5 626 /* enum: Schedule error. */ 627 #define MCDI_EVENT_CODE_SCHEDERR 0x6 628 /* enum: Reboot. */ 629 #define MCDI_EVENT_CODE_REBOOT 0x7 630 /* enum: Mac stats DMA. */ 631 #define MCDI_EVENT_CODE_MAC_STATS_DMA 0x8 632 /* enum: Firmware alert. */ 633 #define MCDI_EVENT_CODE_FWALERT 0x9 634 /* enum: Function level reset. */ 635 #define MCDI_EVENT_CODE_FLR 0xa 636 /* enum: Transmit error */ 637 #define MCDI_EVENT_CODE_TX_ERR 0xb 638 /* enum: Tx flush has completed */ 639 #define MCDI_EVENT_CODE_TX_FLUSH 0xc 640 /* enum: PTP packet received timestamp */ 641 #define MCDI_EVENT_CODE_PTP_RX 0xd 642 /* enum: PTP NIC failure */ 643 #define MCDI_EVENT_CODE_PTP_FAULT 0xe 644 /* enum: PTP PPS event */ 645 #define MCDI_EVENT_CODE_PTP_PPS 0xf 646 /* enum: Rx flush has completed */ 647 #define MCDI_EVENT_CODE_RX_FLUSH 0x10 648 /* enum: Receive error */ 649 #define MCDI_EVENT_CODE_RX_ERR 0x11 650 /* enum: AOE fault */ 651 #define MCDI_EVENT_CODE_AOE 0x12 652 /* enum: Network port calibration failed (VCAL). */ 653 #define MCDI_EVENT_CODE_VCAL_FAIL 0x13 654 /* enum: HW PPS event */ 655 #define MCDI_EVENT_CODE_HW_PPS 0x14 656 /* enum: The MC has rebooted (huntington and later, siena uses CODE_REBOOT and 657 * a different format) 658 */ 659 #define MCDI_EVENT_CODE_MC_REBOOT 0x15 660 /* enum: the MC has detected a parity error */ 661 #define MCDI_EVENT_CODE_PAR_ERR 0x16 662 /* enum: the MC has detected a correctable error */ 663 #define MCDI_EVENT_CODE_ECC_CORR_ERR 0x17 664 /* enum: the MC has detected an uncorrectable error */ 665 #define MCDI_EVENT_CODE_ECC_FATAL_ERR 0x18 666 /* enum: The MC has entered offline BIST mode */ 667 #define MCDI_EVENT_CODE_MC_BIST 0x19 668 /* enum: PTP tick event providing current NIC time */ 669 #define MCDI_EVENT_CODE_PTP_TIME 0x1a 670 /* enum: MUM fault */ 671 #define MCDI_EVENT_CODE_MUM 0x1b 672 /* enum: notify the designated PF of a new authorization request */ 673 #define MCDI_EVENT_CODE_PROXY_REQUEST 0x1c 674 /* enum: notify a function that awaits an authorization that its request has 675 * been processed and it may now resend the command 676 */ 677 #define MCDI_EVENT_CODE_PROXY_RESPONSE 0x1d 678 /* enum: MCDI command accepted. New commands can be issued but this command is 679 * not done yet. 680 */ 681 #define MCDI_EVENT_CODE_DBRET 0x1e 682 /* enum: The MC has detected a fault on the SUC */ 683 #define MCDI_EVENT_CODE_SUC 0x1f 684 /* enum: Artificial event generated by host and posted via MC for test 685 * purposes. 686 */ 687 #define MCDI_EVENT_CODE_TESTGEN 0xfa 688 #define MCDI_EVENT_CMDDONE_DATA_OFST 0 689 #define MCDI_EVENT_CMDDONE_DATA_LEN 4 690 #define MCDI_EVENT_CMDDONE_DATA_LBN 0 691 #define MCDI_EVENT_CMDDONE_DATA_WIDTH 32 692 #define MCDI_EVENT_LINKCHANGE_DATA_OFST 0 693 #define MCDI_EVENT_LINKCHANGE_DATA_LEN 4 694 #define MCDI_EVENT_LINKCHANGE_DATA_LBN 0 695 #define MCDI_EVENT_LINKCHANGE_DATA_WIDTH 32 696 #define MCDI_EVENT_SENSOREVT_DATA_OFST 0 697 #define MCDI_EVENT_SENSOREVT_DATA_LEN 4 698 #define MCDI_EVENT_SENSOREVT_DATA_LBN 0 699 #define MCDI_EVENT_SENSOREVT_DATA_WIDTH 32 700 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_OFST 0 701 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_LEN 4 702 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_LBN 0 703 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_WIDTH 32 704 #define MCDI_EVENT_TX_ERR_DATA_OFST 0 705 #define MCDI_EVENT_TX_ERR_DATA_LEN 4 706 #define MCDI_EVENT_TX_ERR_DATA_LBN 0 707 #define MCDI_EVENT_TX_ERR_DATA_WIDTH 32 708 /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the seconds field of 709 * timestamp 710 */ 711 #define MCDI_EVENT_PTP_SECONDS_OFST 0 712 #define MCDI_EVENT_PTP_SECONDS_LEN 4 713 #define MCDI_EVENT_PTP_SECONDS_LBN 0 714 #define MCDI_EVENT_PTP_SECONDS_WIDTH 32 715 /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the major field of 716 * timestamp 717 */ 718 #define MCDI_EVENT_PTP_MAJOR_OFST 0 719 #define MCDI_EVENT_PTP_MAJOR_LEN 4 720 #define MCDI_EVENT_PTP_MAJOR_LBN 0 721 #define MCDI_EVENT_PTP_MAJOR_WIDTH 32 722 /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the nanoseconds field 723 * of timestamp 724 */ 725 #define MCDI_EVENT_PTP_NANOSECONDS_OFST 0 726 #define MCDI_EVENT_PTP_NANOSECONDS_LEN 4 727 #define MCDI_EVENT_PTP_NANOSECONDS_LBN 0 728 #define MCDI_EVENT_PTP_NANOSECONDS_WIDTH 32 729 /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the minor field of 730 * timestamp 731 */ 732 #define MCDI_EVENT_PTP_MINOR_OFST 0 733 #define MCDI_EVENT_PTP_MINOR_LEN 4 734 #define MCDI_EVENT_PTP_MINOR_LBN 0 735 #define MCDI_EVENT_PTP_MINOR_WIDTH 32 736 /* For CODE_PTP_RX events, the lowest four bytes of sourceUUID from PTP packet 737 */ 738 #define MCDI_EVENT_PTP_UUID_OFST 0 739 #define MCDI_EVENT_PTP_UUID_LEN 4 740 #define MCDI_EVENT_PTP_UUID_LBN 0 741 #define MCDI_EVENT_PTP_UUID_WIDTH 32 742 #define MCDI_EVENT_RX_ERR_DATA_OFST 0 743 #define MCDI_EVENT_RX_ERR_DATA_LEN 4 744 #define MCDI_EVENT_RX_ERR_DATA_LBN 0 745 #define MCDI_EVENT_RX_ERR_DATA_WIDTH 32 746 #define MCDI_EVENT_PAR_ERR_DATA_OFST 0 747 #define MCDI_EVENT_PAR_ERR_DATA_LEN 4 748 #define MCDI_EVENT_PAR_ERR_DATA_LBN 0 749 #define MCDI_EVENT_PAR_ERR_DATA_WIDTH 32 750 #define MCDI_EVENT_ECC_CORR_ERR_DATA_OFST 0 751 #define MCDI_EVENT_ECC_CORR_ERR_DATA_LEN 4 752 #define MCDI_EVENT_ECC_CORR_ERR_DATA_LBN 0 753 #define MCDI_EVENT_ECC_CORR_ERR_DATA_WIDTH 32 754 #define MCDI_EVENT_ECC_FATAL_ERR_DATA_OFST 0 755 #define MCDI_EVENT_ECC_FATAL_ERR_DATA_LEN 4 756 #define MCDI_EVENT_ECC_FATAL_ERR_DATA_LBN 0 757 #define MCDI_EVENT_ECC_FATAL_ERR_DATA_WIDTH 32 758 /* For CODE_PTP_TIME events, the major value of the PTP clock */ 759 #define MCDI_EVENT_PTP_TIME_MAJOR_OFST 0 760 #define MCDI_EVENT_PTP_TIME_MAJOR_LEN 4 761 #define MCDI_EVENT_PTP_TIME_MAJOR_LBN 0 762 #define MCDI_EVENT_PTP_TIME_MAJOR_WIDTH 32 763 /* For CODE_PTP_TIME events, bits 19-26 of the minor value of the PTP clock */ 764 #define MCDI_EVENT_PTP_TIME_MINOR_26_19_LBN 36 765 #define MCDI_EVENT_PTP_TIME_MINOR_26_19_WIDTH 8 766 /* For CODE_PTP_TIME events, most significant bits of the minor value of the 767 * PTP clock. This is a more generic equivalent of PTP_TIME_MINOR_26_19. 768 */ 769 #define MCDI_EVENT_PTP_TIME_MINOR_MS_8BITS_LBN 36 770 #define MCDI_EVENT_PTP_TIME_MINOR_MS_8BITS_WIDTH 8 771 /* For CODE_PTP_TIME events where report sync status is enabled, indicates 772 * whether the NIC clock has ever been set 773 */ 774 #define MCDI_EVENT_PTP_TIME_NIC_CLOCK_VALID_LBN 36 775 #define MCDI_EVENT_PTP_TIME_NIC_CLOCK_VALID_WIDTH 1 776 /* For CODE_PTP_TIME events where report sync status is enabled, indicates 777 * whether the NIC and System clocks are in sync 778 */ 779 #define MCDI_EVENT_PTP_TIME_HOST_NIC_IN_SYNC_LBN 37 780 #define MCDI_EVENT_PTP_TIME_HOST_NIC_IN_SYNC_WIDTH 1 781 /* For CODE_PTP_TIME events where report sync status is enabled, bits 21-26 of 782 * the minor value of the PTP clock 783 */ 784 #define MCDI_EVENT_PTP_TIME_MINOR_26_21_LBN 38 785 #define MCDI_EVENT_PTP_TIME_MINOR_26_21_WIDTH 6 786 /* For CODE_PTP_TIME events, most significant bits of the minor value of the 787 * PTP clock. This is a more generic equivalent of PTP_TIME_MINOR_26_21. 788 */ 789 #define MCDI_EVENT_PTP_TIME_MINOR_MS_6BITS_LBN 38 790 #define MCDI_EVENT_PTP_TIME_MINOR_MS_6BITS_WIDTH 6 791 #define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_OFST 0 792 #define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_LEN 4 793 #define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_LBN 0 794 #define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_WIDTH 32 795 #define MCDI_EVENT_PROXY_RESPONSE_HANDLE_OFST 0 796 #define MCDI_EVENT_PROXY_RESPONSE_HANDLE_LEN 4 797 #define MCDI_EVENT_PROXY_RESPONSE_HANDLE_LBN 0 798 #define MCDI_EVENT_PROXY_RESPONSE_HANDLE_WIDTH 32 799 /* Zero means that the request has been completed or authorized, and the driver 800 * should resend it. A non-zero value means that the authorization has been 801 * denied, and gives the reason. Typically it will be EPERM. 802 */ 803 #define MCDI_EVENT_PROXY_RESPONSE_RC_LBN 36 804 #define MCDI_EVENT_PROXY_RESPONSE_RC_WIDTH 8 805 #define MCDI_EVENT_DBRET_DATA_OFST 0 806 #define MCDI_EVENT_DBRET_DATA_LEN 4 807 #define MCDI_EVENT_DBRET_DATA_LBN 0 808 #define MCDI_EVENT_DBRET_DATA_WIDTH 32 809 810 /* FCDI_EVENT structuredef */ 811 #define FCDI_EVENT_LEN 8 812 #define FCDI_EVENT_CONT_LBN 32 813 #define FCDI_EVENT_CONT_WIDTH 1 814 #define FCDI_EVENT_LEVEL_LBN 33 815 #define FCDI_EVENT_LEVEL_WIDTH 3 816 /* enum: Info. */ 817 #define FCDI_EVENT_LEVEL_INFO 0x0 818 /* enum: Warning. */ 819 #define FCDI_EVENT_LEVEL_WARN 0x1 820 /* enum: Error. */ 821 #define FCDI_EVENT_LEVEL_ERR 0x2 822 /* enum: Fatal. */ 823 #define FCDI_EVENT_LEVEL_FATAL 0x3 824 #define FCDI_EVENT_DATA_OFST 0 825 #define FCDI_EVENT_DATA_LEN 4 826 #define FCDI_EVENT_LINK_STATE_STATUS_LBN 0 827 #define FCDI_EVENT_LINK_STATE_STATUS_WIDTH 1 828 #define FCDI_EVENT_LINK_DOWN 0x0 /* enum */ 829 #define FCDI_EVENT_LINK_UP 0x1 /* enum */ 830 #define FCDI_EVENT_DATA_LBN 0 831 #define FCDI_EVENT_DATA_WIDTH 32 832 #define FCDI_EVENT_SRC_LBN 36 833 #define FCDI_EVENT_SRC_WIDTH 8 834 #define FCDI_EVENT_EV_CODE_LBN 60 835 #define FCDI_EVENT_EV_CODE_WIDTH 4 836 #define FCDI_EVENT_CODE_LBN 44 837 #define FCDI_EVENT_CODE_WIDTH 8 838 /* enum: The FC was rebooted. */ 839 #define FCDI_EVENT_CODE_REBOOT 0x1 840 /* enum: Bad assert. */ 841 #define FCDI_EVENT_CODE_ASSERT 0x2 842 /* enum: DDR3 test result. */ 843 #define FCDI_EVENT_CODE_DDR_TEST_RESULT 0x3 844 /* enum: Link status. */ 845 #define FCDI_EVENT_CODE_LINK_STATE 0x4 846 /* enum: A timed read is ready to be serviced. */ 847 #define FCDI_EVENT_CODE_TIMED_READ 0x5 848 /* enum: One or more PPS IN events */ 849 #define FCDI_EVENT_CODE_PPS_IN 0x6 850 /* enum: Tick event from PTP clock */ 851 #define FCDI_EVENT_CODE_PTP_TICK 0x7 852 /* enum: ECC error counters */ 853 #define FCDI_EVENT_CODE_DDR_ECC_STATUS 0x8 854 /* enum: Current status of PTP */ 855 #define FCDI_EVENT_CODE_PTP_STATUS 0x9 856 /* enum: Port id config to map MC-FC port idx */ 857 #define FCDI_EVENT_CODE_PORT_CONFIG 0xa 858 /* enum: Boot result or error code */ 859 #define FCDI_EVENT_CODE_BOOT_RESULT 0xb 860 #define FCDI_EVENT_REBOOT_SRC_LBN 36 861 #define FCDI_EVENT_REBOOT_SRC_WIDTH 8 862 #define FCDI_EVENT_REBOOT_FC_FW 0x0 /* enum */ 863 #define FCDI_EVENT_REBOOT_FC_BOOTLOADER 0x1 /* enum */ 864 #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_OFST 0 865 #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_LEN 4 866 #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_LBN 0 867 #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_WIDTH 32 868 #define FCDI_EVENT_ASSERT_TYPE_LBN 36 869 #define FCDI_EVENT_ASSERT_TYPE_WIDTH 8 870 #define FCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_LBN 36 871 #define FCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_WIDTH 8 872 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_OFST 0 873 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_LEN 4 874 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_LBN 0 875 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_WIDTH 32 876 #define FCDI_EVENT_LINK_STATE_DATA_OFST 0 877 #define FCDI_EVENT_LINK_STATE_DATA_LEN 4 878 #define FCDI_EVENT_LINK_STATE_DATA_LBN 0 879 #define FCDI_EVENT_LINK_STATE_DATA_WIDTH 32 880 #define FCDI_EVENT_PTP_STATE_OFST 0 881 #define FCDI_EVENT_PTP_STATE_LEN 4 882 #define FCDI_EVENT_PTP_UNDEFINED 0x0 /* enum */ 883 #define FCDI_EVENT_PTP_SETUP_FAILED 0x1 /* enum */ 884 #define FCDI_EVENT_PTP_OPERATIONAL 0x2 /* enum */ 885 #define FCDI_EVENT_PTP_STATE_LBN 0 886 #define FCDI_EVENT_PTP_STATE_WIDTH 32 887 #define FCDI_EVENT_DDR_ECC_STATUS_BANK_ID_LBN 36 888 #define FCDI_EVENT_DDR_ECC_STATUS_BANK_ID_WIDTH 8 889 #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_OFST 0 890 #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_LEN 4 891 #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_LBN 0 892 #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_WIDTH 32 893 /* Index of MC port being referred to */ 894 #define FCDI_EVENT_PORT_CONFIG_SRC_LBN 36 895 #define FCDI_EVENT_PORT_CONFIG_SRC_WIDTH 8 896 /* FC Port index that matches the MC port index in SRC */ 897 #define FCDI_EVENT_PORT_CONFIG_DATA_OFST 0 898 #define FCDI_EVENT_PORT_CONFIG_DATA_LEN 4 899 #define FCDI_EVENT_PORT_CONFIG_DATA_LBN 0 900 #define FCDI_EVENT_PORT_CONFIG_DATA_WIDTH 32 901 #define FCDI_EVENT_BOOT_RESULT_OFST 0 902 #define FCDI_EVENT_BOOT_RESULT_LEN 4 903 /* Enum values, see field(s): */ 904 /* MC_CMD_AOE/MC_CMD_AOE_OUT_INFO/FC_BOOT_RESULT */ 905 #define FCDI_EVENT_BOOT_RESULT_LBN 0 906 #define FCDI_EVENT_BOOT_RESULT_WIDTH 32 907 908 /* FCDI_EXTENDED_EVENT_PPS structuredef: Extended FCDI event to send PPS events 909 * to the MC. Note that this structure | is overlayed over a normal FCDI event 910 * such that bits 32-63 containing | event code, level, source etc remain the 911 * same. In this case the data | field of the header is defined to be the 912 * number of timestamps 913 */ 914 #define FCDI_EXTENDED_EVENT_PPS_LENMIN 16 915 #define FCDI_EXTENDED_EVENT_PPS_LENMAX 248 916 #define FCDI_EXTENDED_EVENT_PPS_LEN(num) (8+8*(num)) 917 /* Number of timestamps following */ 918 #define FCDI_EXTENDED_EVENT_PPS_COUNT_OFST 0 919 #define FCDI_EXTENDED_EVENT_PPS_COUNT_LEN 4 920 #define FCDI_EXTENDED_EVENT_PPS_COUNT_LBN 0 921 #define FCDI_EXTENDED_EVENT_PPS_COUNT_WIDTH 32 922 /* Seconds field of a timestamp record */ 923 #define FCDI_EXTENDED_EVENT_PPS_SECONDS_OFST 8 924 #define FCDI_EXTENDED_EVENT_PPS_SECONDS_LEN 4 925 #define FCDI_EXTENDED_EVENT_PPS_SECONDS_LBN 64 926 #define FCDI_EXTENDED_EVENT_PPS_SECONDS_WIDTH 32 927 /* Nanoseconds field of a timestamp record */ 928 #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_OFST 12 929 #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_LEN 4 930 #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_LBN 96 931 #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_WIDTH 32 932 /* Timestamp records comprising the event */ 933 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_OFST 8 934 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LEN 8 935 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LO_OFST 8 936 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_HI_OFST 12 937 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MINNUM 1 938 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MAXNUM 30 939 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LBN 64 940 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_WIDTH 64 941 942 /* MUM_EVENT structuredef */ 943 #define MUM_EVENT_LEN 8 944 #define MUM_EVENT_CONT_LBN 32 945 #define MUM_EVENT_CONT_WIDTH 1 946 #define MUM_EVENT_LEVEL_LBN 33 947 #define MUM_EVENT_LEVEL_WIDTH 3 948 /* enum: Info. */ 949 #define MUM_EVENT_LEVEL_INFO 0x0 950 /* enum: Warning. */ 951 #define MUM_EVENT_LEVEL_WARN 0x1 952 /* enum: Error. */ 953 #define MUM_EVENT_LEVEL_ERR 0x2 954 /* enum: Fatal. */ 955 #define MUM_EVENT_LEVEL_FATAL 0x3 956 #define MUM_EVENT_DATA_OFST 0 957 #define MUM_EVENT_DATA_LEN 4 958 #define MUM_EVENT_SENSOR_ID_LBN 0 959 #define MUM_EVENT_SENSOR_ID_WIDTH 8 960 /* Enum values, see field(s): */ 961 /* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */ 962 #define MUM_EVENT_SENSOR_STATE_LBN 8 963 #define MUM_EVENT_SENSOR_STATE_WIDTH 8 964 #define MUM_EVENT_PORT_PHY_READY_LBN 0 965 #define MUM_EVENT_PORT_PHY_READY_WIDTH 1 966 #define MUM_EVENT_PORT_PHY_LINK_UP_LBN 1 967 #define MUM_EVENT_PORT_PHY_LINK_UP_WIDTH 1 968 #define MUM_EVENT_PORT_PHY_TX_LOL_LBN 2 969 #define MUM_EVENT_PORT_PHY_TX_LOL_WIDTH 1 970 #define MUM_EVENT_PORT_PHY_RX_LOL_LBN 3 971 #define MUM_EVENT_PORT_PHY_RX_LOL_WIDTH 1 972 #define MUM_EVENT_PORT_PHY_TX_LOS_LBN 4 973 #define MUM_EVENT_PORT_PHY_TX_LOS_WIDTH 1 974 #define MUM_EVENT_PORT_PHY_RX_LOS_LBN 5 975 #define MUM_EVENT_PORT_PHY_RX_LOS_WIDTH 1 976 #define MUM_EVENT_PORT_PHY_TX_FAULT_LBN 6 977 #define MUM_EVENT_PORT_PHY_TX_FAULT_WIDTH 1 978 #define MUM_EVENT_DATA_LBN 0 979 #define MUM_EVENT_DATA_WIDTH 32 980 #define MUM_EVENT_SRC_LBN 36 981 #define MUM_EVENT_SRC_WIDTH 8 982 #define MUM_EVENT_EV_CODE_LBN 60 983 #define MUM_EVENT_EV_CODE_WIDTH 4 984 #define MUM_EVENT_CODE_LBN 44 985 #define MUM_EVENT_CODE_WIDTH 8 986 /* enum: The MUM was rebooted. */ 987 #define MUM_EVENT_CODE_REBOOT 0x1 988 /* enum: Bad assert. */ 989 #define MUM_EVENT_CODE_ASSERT 0x2 990 /* enum: Sensor failure. */ 991 #define MUM_EVENT_CODE_SENSOR 0x3 992 /* enum: Link fault has been asserted, or has cleared. */ 993 #define MUM_EVENT_CODE_QSFP_LASI_INTERRUPT 0x4 994 #define MUM_EVENT_SENSOR_DATA_OFST 0 995 #define MUM_EVENT_SENSOR_DATA_LEN 4 996 #define MUM_EVENT_SENSOR_DATA_LBN 0 997 #define MUM_EVENT_SENSOR_DATA_WIDTH 32 998 #define MUM_EVENT_PORT_PHY_FLAGS_OFST 0 999 #define MUM_EVENT_PORT_PHY_FLAGS_LEN 4 1000 #define MUM_EVENT_PORT_PHY_FLAGS_LBN 0 1001 #define MUM_EVENT_PORT_PHY_FLAGS_WIDTH 32 1002 #define MUM_EVENT_PORT_PHY_COPPER_LEN_OFST 0 1003 #define MUM_EVENT_PORT_PHY_COPPER_LEN_LEN 4 1004 #define MUM_EVENT_PORT_PHY_COPPER_LEN_LBN 0 1005 #define MUM_EVENT_PORT_PHY_COPPER_LEN_WIDTH 32 1006 #define MUM_EVENT_PORT_PHY_CAPS_OFST 0 1007 #define MUM_EVENT_PORT_PHY_CAPS_LEN 4 1008 #define MUM_EVENT_PORT_PHY_CAPS_LBN 0 1009 #define MUM_EVENT_PORT_PHY_CAPS_WIDTH 32 1010 #define MUM_EVENT_PORT_PHY_TECH_OFST 0 1011 #define MUM_EVENT_PORT_PHY_TECH_LEN 4 1012 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_UNKNOWN 0x0 /* enum */ 1013 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_OPTICAL 0x1 /* enum */ 1014 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_PASSIVE 0x2 /* enum */ 1015 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_PASSIVE_EQUALIZED 0x3 /* enum */ 1016 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_ACTIVE_LIMITING 0x4 /* enum */ 1017 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_ACTIVE_LINEAR 0x5 /* enum */ 1018 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_BASE_T 0x6 /* enum */ 1019 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_LOOPBACK_PASSIVE 0x7 /* enum */ 1020 #define MUM_EVENT_PORT_PHY_TECH_LBN 0 1021 #define MUM_EVENT_PORT_PHY_TECH_WIDTH 32 1022 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_LBN 36 1023 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_WIDTH 4 1024 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_FLAGS 0x0 /* enum */ 1025 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_COPPER_LEN 0x1 /* enum */ 1026 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_CAPS 0x2 /* enum */ 1027 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_TECH 0x3 /* enum */ 1028 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_MAX 0x4 /* enum */ 1029 #define MUM_EVENT_PORT_PHY_SRC_PORT_NO_LBN 40 1030 #define MUM_EVENT_PORT_PHY_SRC_PORT_NO_WIDTH 4 1031 1032 1033 /***********************************/ 1034 /* MC_CMD_READ32 1035 * Read multiple 32byte words from MC memory. Note - this command really 1036 * belongs to INSECURE category but is required by shmboot. The command handler 1037 * has additional checks to reject insecure calls. 1038 */ 1039 #define MC_CMD_READ32 0x1 1040 #undef MC_CMD_0x1_PRIVILEGE_CTG 1041 1042 #define MC_CMD_0x1_PRIVILEGE_CTG SRIOV_CTG_ADMIN 1043 1044 /* MC_CMD_READ32_IN msgrequest */ 1045 #define MC_CMD_READ32_IN_LEN 8 1046 #define MC_CMD_READ32_IN_ADDR_OFST 0 1047 #define MC_CMD_READ32_IN_ADDR_LEN 4 1048 #define MC_CMD_READ32_IN_NUMWORDS_OFST 4 1049 #define MC_CMD_READ32_IN_NUMWORDS_LEN 4 1050 1051 /* MC_CMD_READ32_OUT msgresponse */ 1052 #define MC_CMD_READ32_OUT_LENMIN 4 1053 #define MC_CMD_READ32_OUT_LENMAX 252 1054 #define MC_CMD_READ32_OUT_LEN(num) (0+4*(num)) 1055 #define MC_CMD_READ32_OUT_BUFFER_OFST 0 1056 #define MC_CMD_READ32_OUT_BUFFER_LEN 4 1057 #define MC_CMD_READ32_OUT_BUFFER_MINNUM 1 1058 #define MC_CMD_READ32_OUT_BUFFER_MAXNUM 63 1059 1060 1061 /***********************************/ 1062 /* MC_CMD_WRITE32 1063 * Write multiple 32byte words to MC memory. 1064 */ 1065 #define MC_CMD_WRITE32 0x2 1066 #undef MC_CMD_0x2_PRIVILEGE_CTG 1067 1068 #define MC_CMD_0x2_PRIVILEGE_CTG SRIOV_CTG_INSECURE 1069 1070 /* MC_CMD_WRITE32_IN msgrequest */ 1071 #define MC_CMD_WRITE32_IN_LENMIN 8 1072 #define MC_CMD_WRITE32_IN_LENMAX 252 1073 #define MC_CMD_WRITE32_IN_LEN(num) (4+4*(num)) 1074 #define MC_CMD_WRITE32_IN_ADDR_OFST 0 1075 #define MC_CMD_WRITE32_IN_ADDR_LEN 4 1076 #define MC_CMD_WRITE32_IN_BUFFER_OFST 4 1077 #define MC_CMD_WRITE32_IN_BUFFER_LEN 4 1078 #define MC_CMD_WRITE32_IN_BUFFER_MINNUM 1 1079 #define MC_CMD_WRITE32_IN_BUFFER_MAXNUM 62 1080 1081 /* MC_CMD_WRITE32_OUT msgresponse */ 1082 #define MC_CMD_WRITE32_OUT_LEN 0 1083 1084 1085 /***********************************/ 1086 /* MC_CMD_COPYCODE 1087 * Copy MC code between two locations and jump. Note - this command really 1088 * belongs to INSECURE category but is required by shmboot. The command handler 1089 * has additional checks to reject insecure calls. 1090 */ 1091 #define MC_CMD_COPYCODE 0x3 1092 #undef MC_CMD_0x3_PRIVILEGE_CTG 1093 1094 #define MC_CMD_0x3_PRIVILEGE_CTG SRIOV_CTG_ADMIN 1095 1096 /* MC_CMD_COPYCODE_IN msgrequest */ 1097 #define MC_CMD_COPYCODE_IN_LEN 16 1098 /* Source address 1099 * 1100 * The main image should be entered via a copy of a single word from and to a 1101 * magic address, which controls various aspects of the boot. The magic address 1102 * is a bitfield, with each bit as documented below. 1103 */ 1104 #define MC_CMD_COPYCODE_IN_SRC_ADDR_OFST 0 1105 #define MC_CMD_COPYCODE_IN_SRC_ADDR_LEN 4 1106 /* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT (see below) */ 1107 #define MC_CMD_COPYCODE_HUNT_NO_MAGIC_ADDR 0x10000 1108 /* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT and 1109 * BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED (see below) 1110 */ 1111 #define MC_CMD_COPYCODE_HUNT_NO_DATAPATH_MAGIC_ADDR 0x1d0d0 1112 /* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT, 1113 * BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED and BOOT_MAGIC_IGNORE_CONFIG (see 1114 * below) 1115 */ 1116 #define MC_CMD_COPYCODE_HUNT_IGNORE_CONFIG_MAGIC_ADDR 0x1badc 1117 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_LBN 17 1118 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_WIDTH 1 1119 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_LBN 2 1120 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_WIDTH 1 1121 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_LBN 3 1122 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_WIDTH 1 1123 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_LBN 4 1124 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_WIDTH 1 1125 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_LBN 5 1126 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_WIDTH 1 1127 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_DISABLE_XIP_LBN 6 1128 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_DISABLE_XIP_WIDTH 1 1129 /* Destination address */ 1130 #define MC_CMD_COPYCODE_IN_DEST_ADDR_OFST 4 1131 #define MC_CMD_COPYCODE_IN_DEST_ADDR_LEN 4 1132 #define MC_CMD_COPYCODE_IN_NUMWORDS_OFST 8 1133 #define MC_CMD_COPYCODE_IN_NUMWORDS_LEN 4 1134 /* Address of where to jump after copy. */ 1135 #define MC_CMD_COPYCODE_IN_JUMP_OFST 12 1136 #define MC_CMD_COPYCODE_IN_JUMP_LEN 4 1137 /* enum: Control should return to the caller rather than jumping */ 1138 #define MC_CMD_COPYCODE_JUMP_NONE 0x1 1139 1140 /* MC_CMD_COPYCODE_OUT msgresponse */ 1141 #define MC_CMD_COPYCODE_OUT_LEN 0 1142 1143 1144 /***********************************/ 1145 /* MC_CMD_SET_FUNC 1146 * Select function for function-specific commands. 1147 */ 1148 #define MC_CMD_SET_FUNC 0x4 1149 #undef MC_CMD_0x4_PRIVILEGE_CTG 1150 1151 #define MC_CMD_0x4_PRIVILEGE_CTG SRIOV_CTG_INSECURE 1152 1153 /* MC_CMD_SET_FUNC_IN msgrequest */ 1154 #define MC_CMD_SET_FUNC_IN_LEN 4 1155 /* Set function */ 1156 #define MC_CMD_SET_FUNC_IN_FUNC_OFST 0 1157 #define MC_CMD_SET_FUNC_IN_FUNC_LEN 4 1158 1159 /* MC_CMD_SET_FUNC_OUT msgresponse */ 1160 #define MC_CMD_SET_FUNC_OUT_LEN 0 1161 1162 1163 /***********************************/ 1164 /* MC_CMD_GET_BOOT_STATUS 1165 * Get the instruction address from which the MC booted. 1166 */ 1167 #define MC_CMD_GET_BOOT_STATUS 0x5 1168 #undef MC_CMD_0x5_PRIVILEGE_CTG 1169 1170 #define MC_CMD_0x5_PRIVILEGE_CTG SRIOV_CTG_GENERAL 1171 1172 /* MC_CMD_GET_BOOT_STATUS_IN msgrequest */ 1173 #define MC_CMD_GET_BOOT_STATUS_IN_LEN 0 1174 1175 /* MC_CMD_GET_BOOT_STATUS_OUT msgresponse */ 1176 #define MC_CMD_GET_BOOT_STATUS_OUT_LEN 8 1177 /* ?? */ 1178 #define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_OFST 0 1179 #define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_LEN 4 1180 /* enum: indicates that the MC wasn't flash booted */ 1181 #define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_NULL 0xdeadbeef 1182 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_OFST 4 1183 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_LEN 4 1184 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_LBN 0 1185 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_WIDTH 1 1186 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_LBN 1 1187 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_WIDTH 1 1188 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_LBN 2 1189 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_WIDTH 1 1190 1191 1192 /***********************************/ 1193 /* MC_CMD_GET_ASSERTS 1194 * Get (and optionally clear) the current assertion status. Only 1195 * OUT.GLOBAL_FLAGS is guaranteed to exist in the completion payload. The other 1196 * fields will only be present if OUT.GLOBAL_FLAGS != NO_FAILS 1197 */ 1198 #define MC_CMD_GET_ASSERTS 0x6 1199 #undef MC_CMD_0x6_PRIVILEGE_CTG 1200 1201 #define MC_CMD_0x6_PRIVILEGE_CTG SRIOV_CTG_ADMIN 1202 1203 /* MC_CMD_GET_ASSERTS_IN msgrequest */ 1204 #define MC_CMD_GET_ASSERTS_IN_LEN 4 1205 /* Set to clear assertion */ 1206 #define MC_CMD_GET_ASSERTS_IN_CLEAR_OFST 0 1207 #define MC_CMD_GET_ASSERTS_IN_CLEAR_LEN 4 1208 1209 /* MC_CMD_GET_ASSERTS_OUT msgresponse */ 1210 #define MC_CMD_GET_ASSERTS_OUT_LEN 140 1211 /* Assertion status flag. */ 1212 #define MC_CMD_GET_ASSERTS_OUT_GLOBAL_FLAGS_OFST 0 1213 #define MC_CMD_GET_ASSERTS_OUT_GLOBAL_FLAGS_LEN 4 1214 /* enum: No assertions have failed. */ 1215 #define MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1 1216 /* enum: A system-level assertion has failed. */ 1217 #define MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2 1218 /* enum: A thread-level assertion has failed. */ 1219 #define MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3 1220 /* enum: The system was reset by the watchdog. */ 1221 #define MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4 1222 /* enum: An illegal address trap stopped the system (huntington and later) */ 1223 #define MC_CMD_GET_ASSERTS_FLAGS_ADDR_TRAP 0x5 1224 /* Failing PC value */ 1225 #define MC_CMD_GET_ASSERTS_OUT_SAVED_PC_OFFS_OFST 4 1226 #define MC_CMD_GET_ASSERTS_OUT_SAVED_PC_OFFS_LEN 4 1227 /* Saved GP regs */ 1228 #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_OFST 8 1229 #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_LEN 4 1230 #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_NUM 31 1231 /* enum: A magic value hinting that the value in this register at the time of 1232 * the failure has likely been lost. 1233 */ 1234 #define MC_CMD_GET_ASSERTS_REG_NO_DATA 0xda7a1057 1235 /* Failing thread address */ 1236 #define MC_CMD_GET_ASSERTS_OUT_THREAD_OFFS_OFST 132 1237 #define MC_CMD_GET_ASSERTS_OUT_THREAD_OFFS_LEN 4 1238 #define MC_CMD_GET_ASSERTS_OUT_RESERVED_OFST 136 1239 #define MC_CMD_GET_ASSERTS_OUT_RESERVED_LEN 4 1240 1241 1242 /***********************************/ 1243 /* MC_CMD_LOG_CTRL 1244 * Configure the output stream for log events such as link state changes, 1245 * sensor notifications and MCDI completions 1246 */ 1247 #define MC_CMD_LOG_CTRL 0x7 1248 #undef MC_CMD_0x7_PRIVILEGE_CTG 1249 1250 #define MC_CMD_0x7_PRIVILEGE_CTG SRIOV_CTG_GENERAL 1251 1252 /* MC_CMD_LOG_CTRL_IN msgrequest */ 1253 #define MC_CMD_LOG_CTRL_IN_LEN 8 1254 /* Log destination */ 1255 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_OFST 0 1256 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_LEN 4 1257 /* enum: UART. */ 1258 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_UART 0x1 1259 /* enum: Event queue. */ 1260 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ 0x2 1261 /* Legacy argument. Must be zero. */ 1262 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ_OFST 4 1263 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ_LEN 4 1264 1265 /* MC_CMD_LOG_CTRL_OUT msgresponse */ 1266 #define MC_CMD_LOG_CTRL_OUT_LEN 0 1267 1268 1269 /***********************************/ 1270 /* MC_CMD_GET_VERSION 1271 * Get version information about the MC firmware. 1272 */ 1273 #define MC_CMD_GET_VERSION 0x8 1274 #undef MC_CMD_0x8_PRIVILEGE_CTG 1275 1276 #define MC_CMD_0x8_PRIVILEGE_CTG SRIOV_CTG_GENERAL 1277 1278 /* MC_CMD_GET_VERSION_IN msgrequest */ 1279 #define MC_CMD_GET_VERSION_IN_LEN 0 1280 1281 /* MC_CMD_GET_VERSION_EXT_IN msgrequest: Asks for the extended version */ 1282 #define MC_CMD_GET_VERSION_EXT_IN_LEN 4 1283 /* placeholder, set to 0 */ 1284 #define MC_CMD_GET_VERSION_EXT_IN_EXT_FLAGS_OFST 0 1285 #define MC_CMD_GET_VERSION_EXT_IN_EXT_FLAGS_LEN 4 1286 1287 /* MC_CMD_GET_VERSION_V0_OUT msgresponse: deprecated version format */ 1288 #define MC_CMD_GET_VERSION_V0_OUT_LEN 4 1289 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 1290 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 1291 /* enum: Reserved version number to indicate "any" version. */ 1292 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_ANY 0xffffffff 1293 /* enum: Bootrom version value for Siena. */ 1294 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_SIENA_BOOTROM 0xb0070000 1295 /* enum: Bootrom version value for Huntington. */ 1296 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_HUNT_BOOTROM 0xb0070001 1297 /* enum: Bootrom version value for Medford2. */ 1298 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_MEDFORD2_BOOTROM 0xb0070002 1299 1300 /* MC_CMD_GET_VERSION_OUT msgresponse */ 1301 #define MC_CMD_GET_VERSION_OUT_LEN 32 1302 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */ 1303 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */ 1304 /* Enum values, see field(s): */ 1305 /* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */ 1306 #define MC_CMD_GET_VERSION_OUT_PCOL_OFST 4 1307 #define MC_CMD_GET_VERSION_OUT_PCOL_LEN 4 1308 /* 128bit mask of functions supported by the current firmware */ 1309 #define MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_OFST 8 1310 #define MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_LEN 16 1311 #define MC_CMD_GET_VERSION_OUT_VERSION_OFST 24 1312 #define MC_CMD_GET_VERSION_OUT_VERSION_LEN 8 1313 #define MC_CMD_GET_VERSION_OUT_VERSION_LO_OFST 24 1314 #define MC_CMD_GET_VERSION_OUT_VERSION_HI_OFST 28 1315 1316 /* MC_CMD_GET_VERSION_EXT_OUT msgresponse */ 1317 #define MC_CMD_GET_VERSION_EXT_OUT_LEN 48 1318 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */ 1319 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */ 1320 /* Enum values, see field(s): */ 1321 /* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */ 1322 #define MC_CMD_GET_VERSION_EXT_OUT_PCOL_OFST 4 1323 #define MC_CMD_GET_VERSION_EXT_OUT_PCOL_LEN 4 1324 /* 128bit mask of functions supported by the current firmware */ 1325 #define MC_CMD_GET_VERSION_EXT_OUT_SUPPORTED_FUNCS_OFST 8 1326 #define MC_CMD_GET_VERSION_EXT_OUT_SUPPORTED_FUNCS_LEN 16 1327 #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_OFST 24 1328 #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LEN 8 1329 #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LO_OFST 24 1330 #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_HI_OFST 28 1331 /* extra info */ 1332 #define MC_CMD_GET_VERSION_EXT_OUT_EXTRA_OFST 32 1333 #define MC_CMD_GET_VERSION_EXT_OUT_EXTRA_LEN 16 1334 1335 1336 /***********************************/ 1337 /* MC_CMD_PTP 1338 * Perform PTP operation 1339 */ 1340 #define MC_CMD_PTP 0xb 1341 #undef MC_CMD_0xb_PRIVILEGE_CTG 1342 1343 #define MC_CMD_0xb_PRIVILEGE_CTG SRIOV_CTG_GENERAL 1344 1345 /* MC_CMD_PTP_IN msgrequest */ 1346 #define MC_CMD_PTP_IN_LEN 1 1347 /* PTP operation code */ 1348 #define MC_CMD_PTP_IN_OP_OFST 0 1349 #define MC_CMD_PTP_IN_OP_LEN 1 1350 /* enum: Enable PTP packet timestamping operation. */ 1351 #define MC_CMD_PTP_OP_ENABLE 0x1 1352 /* enum: Disable PTP packet timestamping operation. */ 1353 #define MC_CMD_PTP_OP_DISABLE 0x2 1354 /* enum: Send a PTP packet. This operation is used on Siena and Huntington. 1355 * From Medford onwards it is not supported: on those platforms PTP transmit 1356 * timestamping is done using the fast path. 1357 */ 1358 #define MC_CMD_PTP_OP_TRANSMIT 0x3 1359 /* enum: Read the current NIC time. */ 1360 #define MC_CMD_PTP_OP_READ_NIC_TIME 0x4 1361 /* enum: Get the current PTP status. Note that the clock frequency returned (in 1362 * Hz) is rounded to the nearest MHz (e.g. 666000000 for 666666666). 1363 */ 1364 #define MC_CMD_PTP_OP_STATUS 0x5 1365 /* enum: Adjust the PTP NIC's time. */ 1366 #define MC_CMD_PTP_OP_ADJUST 0x6 1367 /* enum: Synchronize host and NIC time. */ 1368 #define MC_CMD_PTP_OP_SYNCHRONIZE 0x7 1369 /* enum: Basic manufacturing tests. Siena PTP adapters only. */ 1370 #define MC_CMD_PTP_OP_MANFTEST_BASIC 0x8 1371 /* enum: Packet based manufacturing tests. Siena PTP adapters only. */ 1372 #define MC_CMD_PTP_OP_MANFTEST_PACKET 0x9 1373 /* enum: Reset some of the PTP related statistics */ 1374 #define MC_CMD_PTP_OP_RESET_STATS 0xa 1375 /* enum: Debug operations to MC. */ 1376 #define MC_CMD_PTP_OP_DEBUG 0xb 1377 /* enum: Read an FPGA register. Siena PTP adapters only. */ 1378 #define MC_CMD_PTP_OP_FPGAREAD 0xc 1379 /* enum: Write an FPGA register. Siena PTP adapters only. */ 1380 #define MC_CMD_PTP_OP_FPGAWRITE 0xd 1381 /* enum: Apply an offset to the NIC clock */ 1382 #define MC_CMD_PTP_OP_CLOCK_OFFSET_ADJUST 0xe 1383 /* enum: Change the frequency correction applied to the NIC clock */ 1384 #define MC_CMD_PTP_OP_CLOCK_FREQ_ADJUST 0xf 1385 /* enum: Set the MC packet filter VLAN tags for received PTP packets. 1386 * Deprecated for Huntington onwards. 1387 */ 1388 #define MC_CMD_PTP_OP_RX_SET_VLAN_FILTER 0x10 1389 /* enum: Set the MC packet filter UUID for received PTP packets. Deprecated for 1390 * Huntington onwards. 1391 */ 1392 #define MC_CMD_PTP_OP_RX_SET_UUID_FILTER 0x11 1393 /* enum: Set the MC packet filter Domain for received PTP packets. Deprecated 1394 * for Huntington onwards. 1395 */ 1396 #define MC_CMD_PTP_OP_RX_SET_DOMAIN_FILTER 0x12 1397 /* enum: Set the clock source. Required for snapper tests on Huntington and 1398 * Medford. Not implemented for Siena or Medford2. 1399 */ 1400 #define MC_CMD_PTP_OP_SET_CLK_SRC 0x13 1401 /* enum: Reset value of Timer Reg. Not implemented. */ 1402 #define MC_CMD_PTP_OP_RST_CLK 0x14 1403 /* enum: Enable the forwarding of PPS events to the host */ 1404 #define MC_CMD_PTP_OP_PPS_ENABLE 0x15 1405 /* enum: Get the time format used by this NIC for PTP operations */ 1406 #define MC_CMD_PTP_OP_GET_TIME_FORMAT 0x16 1407 /* enum: Get the clock attributes. NOTE- extended version of 1408 * MC_CMD_PTP_OP_GET_TIME_FORMAT 1409 */ 1410 #define MC_CMD_PTP_OP_GET_ATTRIBUTES 0x16 1411 /* enum: Get corrections that should be applied to the various different 1412 * timestamps 1413 */ 1414 #define MC_CMD_PTP_OP_GET_TIMESTAMP_CORRECTIONS 0x17 1415 /* enum: Subscribe to receive periodic time events indicating the current NIC 1416 * time 1417 */ 1418 #define MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE 0x18 1419 /* enum: Unsubscribe to stop receiving time events */ 1420 #define MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE 0x19 1421 /* enum: PPS based manfacturing tests. Requires PPS output to be looped to PPS 1422 * input on the same NIC. Siena PTP adapters only. 1423 */ 1424 #define MC_CMD_PTP_OP_MANFTEST_PPS 0x1a 1425 /* enum: Set the PTP sync status. Status is used by firmware to report to event 1426 * subscribers. 1427 */ 1428 #define MC_CMD_PTP_OP_SET_SYNC_STATUS 0x1b 1429 /* enum: Above this for future use. */ 1430 #define MC_CMD_PTP_OP_MAX 0x1c 1431 1432 /* MC_CMD_PTP_IN_ENABLE msgrequest */ 1433 #define MC_CMD_PTP_IN_ENABLE_LEN 16 1434 #define MC_CMD_PTP_IN_CMD_OFST 0 1435 #define MC_CMD_PTP_IN_CMD_LEN 4 1436 #define MC_CMD_PTP_IN_PERIPH_ID_OFST 4 1437 #define MC_CMD_PTP_IN_PERIPH_ID_LEN 4 1438 /* Not used. Events are always sent to function relative queue 0. */ 1439 #define MC_CMD_PTP_IN_ENABLE_QUEUE_OFST 8 1440 #define MC_CMD_PTP_IN_ENABLE_QUEUE_LEN 4 1441 /* PTP timestamping mode. Not used from Huntington onwards. */ 1442 #define MC_CMD_PTP_IN_ENABLE_MODE_OFST 12 1443 #define MC_CMD_PTP_IN_ENABLE_MODE_LEN 4 1444 /* enum: PTP, version 1 */ 1445 #define MC_CMD_PTP_MODE_V1 0x0 1446 /* enum: PTP, version 1, with VLAN headers - deprecated */ 1447 #define MC_CMD_PTP_MODE_V1_VLAN 0x1 1448 /* enum: PTP, version 2 */ 1449 #define MC_CMD_PTP_MODE_V2 0x2 1450 /* enum: PTP, version 2, with VLAN headers - deprecated */ 1451 #define MC_CMD_PTP_MODE_V2_VLAN 0x3 1452 /* enum: PTP, version 2, with improved UUID filtering */ 1453 #define MC_CMD_PTP_MODE_V2_ENHANCED 0x4 1454 /* enum: FCoE (seconds and microseconds) */ 1455 #define MC_CMD_PTP_MODE_FCOE 0x5 1456 1457 /* MC_CMD_PTP_IN_DISABLE msgrequest */ 1458 #define MC_CMD_PTP_IN_DISABLE_LEN 8 1459 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1460 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1461 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1462 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1463 1464 /* MC_CMD_PTP_IN_TRANSMIT msgrequest */ 1465 #define MC_CMD_PTP_IN_TRANSMIT_LENMIN 13 1466 #define MC_CMD_PTP_IN_TRANSMIT_LENMAX 252 1467 #define MC_CMD_PTP_IN_TRANSMIT_LEN(num) (12+1*(num)) 1468 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1469 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1470 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1471 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1472 /* Transmit packet length */ 1473 #define MC_CMD_PTP_IN_TRANSMIT_LENGTH_OFST 8 1474 #define MC_CMD_PTP_IN_TRANSMIT_LENGTH_LEN 4 1475 /* Transmit packet data */ 1476 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_OFST 12 1477 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_LEN 1 1478 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_MINNUM 1 1479 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_MAXNUM 240 1480 1481 /* MC_CMD_PTP_IN_READ_NIC_TIME msgrequest */ 1482 #define MC_CMD_PTP_IN_READ_NIC_TIME_LEN 8 1483 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1484 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1485 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1486 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1487 1488 /* MC_CMD_PTP_IN_READ_NIC_TIME_V2 msgrequest */ 1489 #define MC_CMD_PTP_IN_READ_NIC_TIME_V2_LEN 8 1490 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1491 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1492 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1493 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1494 1495 /* MC_CMD_PTP_IN_STATUS msgrequest */ 1496 #define MC_CMD_PTP_IN_STATUS_LEN 8 1497 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1498 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1499 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1500 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1501 1502 /* MC_CMD_PTP_IN_ADJUST msgrequest */ 1503 #define MC_CMD_PTP_IN_ADJUST_LEN 24 1504 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1505 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1506 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1507 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1508 /* Frequency adjustment 40 bit fixed point ns */ 1509 #define MC_CMD_PTP_IN_ADJUST_FREQ_OFST 8 1510 #define MC_CMD_PTP_IN_ADJUST_FREQ_LEN 8 1511 #define MC_CMD_PTP_IN_ADJUST_FREQ_LO_OFST 8 1512 #define MC_CMD_PTP_IN_ADJUST_FREQ_HI_OFST 12 1513 /* enum: Number of fractional bits in frequency adjustment */ 1514 #define MC_CMD_PTP_IN_ADJUST_BITS 0x28 1515 /* enum: Number of fractional bits in frequency adjustment when FP44_FREQ_ADJ 1516 * is indicated in the MC_CMD_PTP_OUT_GET_ATTRIBUTES command CAPABILITIES 1517 * field. 1518 */ 1519 #define MC_CMD_PTP_IN_ADJUST_BITS_FP44 0x2c 1520 /* Time adjustment in seconds */ 1521 #define MC_CMD_PTP_IN_ADJUST_SECONDS_OFST 16 1522 #define MC_CMD_PTP_IN_ADJUST_SECONDS_LEN 4 1523 /* Time adjustment major value */ 1524 #define MC_CMD_PTP_IN_ADJUST_MAJOR_OFST 16 1525 #define MC_CMD_PTP_IN_ADJUST_MAJOR_LEN 4 1526 /* Time adjustment in nanoseconds */ 1527 #define MC_CMD_PTP_IN_ADJUST_NANOSECONDS_OFST 20 1528 #define MC_CMD_PTP_IN_ADJUST_NANOSECONDS_LEN 4 1529 /* Time adjustment minor value */ 1530 #define MC_CMD_PTP_IN_ADJUST_MINOR_OFST 20 1531 #define MC_CMD_PTP_IN_ADJUST_MINOR_LEN 4 1532 1533 /* MC_CMD_PTP_IN_ADJUST_V2 msgrequest */ 1534 #define MC_CMD_PTP_IN_ADJUST_V2_LEN 28 1535 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1536 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1537 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1538 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1539 /* Frequency adjustment 40 bit fixed point ns */ 1540 #define MC_CMD_PTP_IN_ADJUST_V2_FREQ_OFST 8 1541 #define MC_CMD_PTP_IN_ADJUST_V2_FREQ_LEN 8 1542 #define MC_CMD_PTP_IN_ADJUST_V2_FREQ_LO_OFST 8 1543 #define MC_CMD_PTP_IN_ADJUST_V2_FREQ_HI_OFST 12 1544 /* enum: Number of fractional bits in frequency adjustment */ 1545 /* MC_CMD_PTP_IN_ADJUST_BITS 0x28 */ 1546 /* enum: Number of fractional bits in frequency adjustment when FP44_FREQ_ADJ 1547 * is indicated in the MC_CMD_PTP_OUT_GET_ATTRIBUTES command CAPABILITIES 1548 * field. 1549 */ 1550 /* MC_CMD_PTP_IN_ADJUST_BITS_FP44 0x2c */ 1551 /* Time adjustment in seconds */ 1552 #define MC_CMD_PTP_IN_ADJUST_V2_SECONDS_OFST 16 1553 #define MC_CMD_PTP_IN_ADJUST_V2_SECONDS_LEN 4 1554 /* Time adjustment major value */ 1555 #define MC_CMD_PTP_IN_ADJUST_V2_MAJOR_OFST 16 1556 #define MC_CMD_PTP_IN_ADJUST_V2_MAJOR_LEN 4 1557 /* Time adjustment in nanoseconds */ 1558 #define MC_CMD_PTP_IN_ADJUST_V2_NANOSECONDS_OFST 20 1559 #define MC_CMD_PTP_IN_ADJUST_V2_NANOSECONDS_LEN 4 1560 /* Time adjustment minor value */ 1561 #define MC_CMD_PTP_IN_ADJUST_V2_MINOR_OFST 20 1562 #define MC_CMD_PTP_IN_ADJUST_V2_MINOR_LEN 4 1563 /* Upper 32bits of major time offset adjustment */ 1564 #define MC_CMD_PTP_IN_ADJUST_V2_MAJOR_HI_OFST 24 1565 #define MC_CMD_PTP_IN_ADJUST_V2_MAJOR_HI_LEN 4 1566 1567 /* MC_CMD_PTP_IN_SYNCHRONIZE msgrequest */ 1568 #define MC_CMD_PTP_IN_SYNCHRONIZE_LEN 20 1569 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1570 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1571 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1572 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1573 /* Number of time readings to capture */ 1574 #define MC_CMD_PTP_IN_SYNCHRONIZE_NUMTIMESETS_OFST 8 1575 #define MC_CMD_PTP_IN_SYNCHRONIZE_NUMTIMESETS_LEN 4 1576 /* Host address in which to write "synchronization started" indication (64 1577 * bits) 1578 */ 1579 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_OFST 12 1580 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LEN 8 1581 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LO_OFST 12 1582 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_HI_OFST 16 1583 1584 /* MC_CMD_PTP_IN_MANFTEST_BASIC msgrequest */ 1585 #define MC_CMD_PTP_IN_MANFTEST_BASIC_LEN 8 1586 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1587 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1588 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1589 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1590 1591 /* MC_CMD_PTP_IN_MANFTEST_PACKET msgrequest */ 1592 #define MC_CMD_PTP_IN_MANFTEST_PACKET_LEN 12 1593 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1594 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1595 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1596 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1597 /* Enable or disable packet testing */ 1598 #define MC_CMD_PTP_IN_MANFTEST_PACKET_TEST_ENABLE_OFST 8 1599 #define MC_CMD_PTP_IN_MANFTEST_PACKET_TEST_ENABLE_LEN 4 1600 1601 /* MC_CMD_PTP_IN_RESET_STATS msgrequest */ 1602 #define MC_CMD_PTP_IN_RESET_STATS_LEN 8 1603 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1604 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1605 /* Reset PTP statistics */ 1606 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1607 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1608 1609 /* MC_CMD_PTP_IN_DEBUG msgrequest */ 1610 #define MC_CMD_PTP_IN_DEBUG_LEN 12 1611 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1612 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1613 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1614 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1615 /* Debug operations */ 1616 #define MC_CMD_PTP_IN_DEBUG_DEBUG_PARAM_OFST 8 1617 #define MC_CMD_PTP_IN_DEBUG_DEBUG_PARAM_LEN 4 1618 1619 /* MC_CMD_PTP_IN_FPGAREAD msgrequest */ 1620 #define MC_CMD_PTP_IN_FPGAREAD_LEN 16 1621 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1622 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1623 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1624 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1625 #define MC_CMD_PTP_IN_FPGAREAD_ADDR_OFST 8 1626 #define MC_CMD_PTP_IN_FPGAREAD_ADDR_LEN 4 1627 #define MC_CMD_PTP_IN_FPGAREAD_NUMBYTES_OFST 12 1628 #define MC_CMD_PTP_IN_FPGAREAD_NUMBYTES_LEN 4 1629 1630 /* MC_CMD_PTP_IN_FPGAWRITE msgrequest */ 1631 #define MC_CMD_PTP_IN_FPGAWRITE_LENMIN 13 1632 #define MC_CMD_PTP_IN_FPGAWRITE_LENMAX 252 1633 #define MC_CMD_PTP_IN_FPGAWRITE_LEN(num) (12+1*(num)) 1634 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1635 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1636 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1637 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1638 #define MC_CMD_PTP_IN_FPGAWRITE_ADDR_OFST 8 1639 #define MC_CMD_PTP_IN_FPGAWRITE_ADDR_LEN 4 1640 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_OFST 12 1641 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_LEN 1 1642 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MINNUM 1 1643 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MAXNUM 240 1644 1645 /* MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST msgrequest */ 1646 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_LEN 16 1647 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1648 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1649 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1650 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1651 /* Time adjustment in seconds */ 1652 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_SECONDS_OFST 8 1653 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_SECONDS_LEN 4 1654 /* Time adjustment major value */ 1655 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MAJOR_OFST 8 1656 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MAJOR_LEN 4 1657 /* Time adjustment in nanoseconds */ 1658 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_NANOSECONDS_OFST 12 1659 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_NANOSECONDS_LEN 4 1660 /* Time adjustment minor value */ 1661 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MINOR_OFST 12 1662 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MINOR_LEN 4 1663 1664 /* MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2 msgrequest */ 1665 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_LEN 20 1666 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1667 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1668 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1669 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1670 /* Time adjustment in seconds */ 1671 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_SECONDS_OFST 8 1672 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_SECONDS_LEN 4 1673 /* Time adjustment major value */ 1674 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MAJOR_OFST 8 1675 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MAJOR_LEN 4 1676 /* Time adjustment in nanoseconds */ 1677 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_NANOSECONDS_OFST 12 1678 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_NANOSECONDS_LEN 4 1679 /* Time adjustment minor value */ 1680 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MINOR_OFST 12 1681 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MINOR_LEN 4 1682 /* Upper 32bits of major time offset adjustment */ 1683 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MAJOR_HI_OFST 16 1684 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MAJOR_HI_LEN 4 1685 1686 /* MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST msgrequest */ 1687 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_LEN 16 1688 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1689 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1690 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1691 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1692 /* Frequency adjustment 40 bit fixed point ns */ 1693 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_OFST 8 1694 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LEN 8 1695 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LO_OFST 8 1696 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_HI_OFST 12 1697 /* Enum values, see field(s): */ 1698 /* MC_CMD_PTP/MC_CMD_PTP_IN_ADJUST/FREQ */ 1699 1700 /* MC_CMD_PTP_IN_RX_SET_VLAN_FILTER msgrequest */ 1701 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_LEN 24 1702 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1703 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1704 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1705 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1706 /* Number of VLAN tags, 0 if not VLAN */ 1707 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_NUM_VLAN_TAGS_OFST 8 1708 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_NUM_VLAN_TAGS_LEN 4 1709 /* Set of VLAN tags to filter against */ 1710 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_OFST 12 1711 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_LEN 4 1712 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_NUM 3 1713 1714 /* MC_CMD_PTP_IN_RX_SET_UUID_FILTER msgrequest */ 1715 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_LEN 20 1716 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1717 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1718 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1719 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1720 /* 1 to enable UUID filtering, 0 to disable */ 1721 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_ENABLE_OFST 8 1722 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_ENABLE_LEN 4 1723 /* UUID to filter against */ 1724 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_OFST 12 1725 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LEN 8 1726 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LO_OFST 12 1727 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_HI_OFST 16 1728 1729 /* MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER msgrequest */ 1730 #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_LEN 16 1731 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1732 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1733 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1734 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1735 /* 1 to enable Domain filtering, 0 to disable */ 1736 #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_ENABLE_OFST 8 1737 #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_ENABLE_LEN 4 1738 /* Domain number to filter against */ 1739 #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_DOMAIN_OFST 12 1740 #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_DOMAIN_LEN 4 1741 1742 /* MC_CMD_PTP_IN_SET_CLK_SRC msgrequest */ 1743 #define MC_CMD_PTP_IN_SET_CLK_SRC_LEN 12 1744 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1745 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1746 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1747 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1748 /* Set the clock source. */ 1749 #define MC_CMD_PTP_IN_SET_CLK_SRC_CLK_OFST 8 1750 #define MC_CMD_PTP_IN_SET_CLK_SRC_CLK_LEN 4 1751 /* enum: Internal. */ 1752 #define MC_CMD_PTP_CLK_SRC_INTERNAL 0x0 1753 /* enum: External. */ 1754 #define MC_CMD_PTP_CLK_SRC_EXTERNAL 0x1 1755 1756 /* MC_CMD_PTP_IN_RST_CLK msgrequest */ 1757 #define MC_CMD_PTP_IN_RST_CLK_LEN 8 1758 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1759 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1760 /* Reset value of Timer Reg. */ 1761 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1762 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1763 1764 /* MC_CMD_PTP_IN_PPS_ENABLE msgrequest */ 1765 #define MC_CMD_PTP_IN_PPS_ENABLE_LEN 12 1766 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1767 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1768 /* Enable or disable */ 1769 #define MC_CMD_PTP_IN_PPS_ENABLE_OP_OFST 4 1770 #define MC_CMD_PTP_IN_PPS_ENABLE_OP_LEN 4 1771 /* enum: Enable */ 1772 #define MC_CMD_PTP_ENABLE_PPS 0x0 1773 /* enum: Disable */ 1774 #define MC_CMD_PTP_DISABLE_PPS 0x1 1775 /* Not used. Events are always sent to function relative queue 0. */ 1776 #define MC_CMD_PTP_IN_PPS_ENABLE_QUEUE_ID_OFST 8 1777 #define MC_CMD_PTP_IN_PPS_ENABLE_QUEUE_ID_LEN 4 1778 1779 /* MC_CMD_PTP_IN_GET_TIME_FORMAT msgrequest */ 1780 #define MC_CMD_PTP_IN_GET_TIME_FORMAT_LEN 8 1781 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1782 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1783 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1784 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1785 1786 /* MC_CMD_PTP_IN_GET_ATTRIBUTES msgrequest */ 1787 #define MC_CMD_PTP_IN_GET_ATTRIBUTES_LEN 8 1788 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1789 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1790 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1791 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1792 1793 /* MC_CMD_PTP_IN_GET_TIMESTAMP_CORRECTIONS msgrequest */ 1794 #define MC_CMD_PTP_IN_GET_TIMESTAMP_CORRECTIONS_LEN 8 1795 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1796 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1797 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1798 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1799 1800 /* MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE msgrequest */ 1801 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN 12 1802 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1803 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1804 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1805 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1806 /* Original field containing queue ID. Now extended to include flags. */ 1807 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_OFST 8 1808 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_LEN 4 1809 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_LBN 0 1810 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_WIDTH 16 1811 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_REPORT_SYNC_STATUS_LBN 31 1812 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_REPORT_SYNC_STATUS_WIDTH 1 1813 1814 /* MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE msgrequest */ 1815 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN 16 1816 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1817 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1818 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1819 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1820 /* Unsubscribe options */ 1821 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL_OFST 8 1822 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL_LEN 4 1823 /* enum: Unsubscribe a single queue */ 1824 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE 0x0 1825 /* enum: Unsubscribe all queues */ 1826 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_ALL 0x1 1827 /* Event queue ID */ 1828 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE_OFST 12 1829 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE_LEN 4 1830 1831 /* MC_CMD_PTP_IN_MANFTEST_PPS msgrequest */ 1832 #define MC_CMD_PTP_IN_MANFTEST_PPS_LEN 12 1833 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1834 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1835 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1836 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1837 /* 1 to enable PPS test mode, 0 to disable and return result. */ 1838 #define MC_CMD_PTP_IN_MANFTEST_PPS_TEST_ENABLE_OFST 8 1839 #define MC_CMD_PTP_IN_MANFTEST_PPS_TEST_ENABLE_LEN 4 1840 1841 /* MC_CMD_PTP_IN_SET_SYNC_STATUS msgrequest */ 1842 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_LEN 24 1843 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 1844 /* MC_CMD_PTP_IN_CMD_LEN 4 */ 1845 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 1846 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */ 1847 /* NIC - Host System Clock Synchronization status */ 1848 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_STATUS_OFST 8 1849 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_STATUS_LEN 4 1850 /* enum: Host System clock and NIC clock are not in sync */ 1851 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_NOT_IN_SYNC 0x0 1852 /* enum: Host System clock and NIC clock are synchronized */ 1853 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_IN_SYNC 0x1 1854 /* If synchronized, number of seconds until clocks should be considered to be 1855 * no longer in sync. 1856 */ 1857 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_TIMEOUT_OFST 12 1858 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_TIMEOUT_LEN 4 1859 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED0_OFST 16 1860 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED0_LEN 4 1861 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED1_OFST 20 1862 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED1_LEN 4 1863 1864 /* MC_CMD_PTP_OUT msgresponse */ 1865 #define MC_CMD_PTP_OUT_LEN 0 1866 1867 /* MC_CMD_PTP_OUT_TRANSMIT msgresponse */ 1868 #define MC_CMD_PTP_OUT_TRANSMIT_LEN 8 1869 /* Value of seconds timestamp */ 1870 #define MC_CMD_PTP_OUT_TRANSMIT_SECONDS_OFST 0 1871 #define MC_CMD_PTP_OUT_TRANSMIT_SECONDS_LEN 4 1872 /* Timestamp major value */ 1873 #define MC_CMD_PTP_OUT_TRANSMIT_MAJOR_OFST 0 1874 #define MC_CMD_PTP_OUT_TRANSMIT_MAJOR_LEN 4 1875 /* Value of nanoseconds timestamp */ 1876 #define MC_CMD_PTP_OUT_TRANSMIT_NANOSECONDS_OFST 4 1877 #define MC_CMD_PTP_OUT_TRANSMIT_NANOSECONDS_LEN 4 1878 /* Timestamp minor value */ 1879 #define MC_CMD_PTP_OUT_TRANSMIT_MINOR_OFST 4 1880 #define MC_CMD_PTP_OUT_TRANSMIT_MINOR_LEN 4 1881 1882 /* MC_CMD_PTP_OUT_TIME_EVENT_SUBSCRIBE msgresponse */ 1883 #define MC_CMD_PTP_OUT_TIME_EVENT_SUBSCRIBE_LEN 0 1884 1885 /* MC_CMD_PTP_OUT_TIME_EVENT_UNSUBSCRIBE msgresponse */ 1886 #define MC_CMD_PTP_OUT_TIME_EVENT_UNSUBSCRIBE_LEN 0 1887 1888 /* MC_CMD_PTP_OUT_READ_NIC_TIME msgresponse */ 1889 #define MC_CMD_PTP_OUT_READ_NIC_TIME_LEN 8 1890 /* Value of seconds timestamp */ 1891 #define MC_CMD_PTP_OUT_READ_NIC_TIME_SECONDS_OFST 0 1892 #define MC_CMD_PTP_OUT_READ_NIC_TIME_SECONDS_LEN 4 1893 /* Timestamp major value */ 1894 #define MC_CMD_PTP_OUT_READ_NIC_TIME_MAJOR_OFST 0 1895 #define MC_CMD_PTP_OUT_READ_NIC_TIME_MAJOR_LEN 4 1896 /* Value of nanoseconds timestamp */ 1897 #define MC_CMD_PTP_OUT_READ_NIC_TIME_NANOSECONDS_OFST 4 1898 #define MC_CMD_PTP_OUT_READ_NIC_TIME_NANOSECONDS_LEN 4 1899 /* Timestamp minor value */ 1900 #define MC_CMD_PTP_OUT_READ_NIC_TIME_MINOR_OFST 4 1901 #define MC_CMD_PTP_OUT_READ_NIC_TIME_MINOR_LEN 4 1902 1903 /* MC_CMD_PTP_OUT_READ_NIC_TIME_V2 msgresponse */ 1904 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_LEN 12 1905 /* Value of seconds timestamp */ 1906 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_SECONDS_OFST 0 1907 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_SECONDS_LEN 4 1908 /* Timestamp major value */ 1909 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_OFST 0 1910 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_LEN 4 1911 /* Value of nanoseconds timestamp */ 1912 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_NANOSECONDS_OFST 4 1913 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_NANOSECONDS_LEN 4 1914 /* Timestamp minor value */ 1915 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MINOR_OFST 4 1916 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MINOR_LEN 4 1917 /* Upper 32bits of major timestamp value */ 1918 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_HI_OFST 8 1919 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_HI_LEN 4 1920 1921 /* MC_CMD_PTP_OUT_STATUS msgresponse */ 1922 #define MC_CMD_PTP_OUT_STATUS_LEN 64 1923 /* Frequency of NIC's hardware clock */ 1924 #define MC_CMD_PTP_OUT_STATUS_CLOCK_FREQ_OFST 0 1925 #define MC_CMD_PTP_OUT_STATUS_CLOCK_FREQ_LEN 4 1926 /* Number of packets transmitted and timestamped */ 1927 #define MC_CMD_PTP_OUT_STATUS_STATS_TX_OFST 4 1928 #define MC_CMD_PTP_OUT_STATUS_STATS_TX_LEN 4 1929 /* Number of packets received and timestamped */ 1930 #define MC_CMD_PTP_OUT_STATUS_STATS_RX_OFST 8 1931 #define MC_CMD_PTP_OUT_STATUS_STATS_RX_LEN 4 1932 /* Number of packets timestamped by the FPGA */ 1933 #define MC_CMD_PTP_OUT_STATUS_STATS_TS_OFST 12 1934 #define MC_CMD_PTP_OUT_STATUS_STATS_TS_LEN 4 1935 /* Number of packets filter matched */ 1936 #define MC_CMD_PTP_OUT_STATUS_STATS_FM_OFST 16 1937 #define MC_CMD_PTP_OUT_STATUS_STATS_FM_LEN 4 1938 /* Number of packets not filter matched */ 1939 #define MC_CMD_PTP_OUT_STATUS_STATS_NFM_OFST 20 1940 #define MC_CMD_PTP_OUT_STATUS_STATS_NFM_LEN 4 1941 /* Number of PPS overflows (noise on input?) */ 1942 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFLOW_OFST 24 1943 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFLOW_LEN 4 1944 /* Number of PPS bad periods */ 1945 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_BAD_OFST 28 1946 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_BAD_LEN 4 1947 /* Minimum period of PPS pulse in nanoseconds */ 1948 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MIN_OFST 32 1949 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MIN_LEN 4 1950 /* Maximum period of PPS pulse in nanoseconds */ 1951 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MAX_OFST 36 1952 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MAX_LEN 4 1953 /* Last period of PPS pulse in nanoseconds */ 1954 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_LAST_OFST 40 1955 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_LAST_LEN 4 1956 /* Mean period of PPS pulse in nanoseconds */ 1957 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MEAN_OFST 44 1958 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MEAN_LEN 4 1959 /* Minimum offset of PPS pulse in nanoseconds (signed) */ 1960 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MIN_OFST 48 1961 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MIN_LEN 4 1962 /* Maximum offset of PPS pulse in nanoseconds (signed) */ 1963 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MAX_OFST 52 1964 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MAX_LEN 4 1965 /* Last offset of PPS pulse in nanoseconds (signed) */ 1966 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_LAST_OFST 56 1967 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_LAST_LEN 4 1968 /* Mean offset of PPS pulse in nanoseconds (signed) */ 1969 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MEAN_OFST 60 1970 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MEAN_LEN 4 1971 1972 /* MC_CMD_PTP_OUT_SYNCHRONIZE msgresponse */ 1973 #define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMIN 20 1974 #define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMAX 240 1975 #define MC_CMD_PTP_OUT_SYNCHRONIZE_LEN(num) (0+20*(num)) 1976 /* A set of host and NIC times */ 1977 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_OFST 0 1978 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_LEN 20 1979 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MINNUM 1 1980 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MAXNUM 12 1981 /* Host time immediately before NIC's hardware clock read */ 1982 #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTSTART_OFST 0 1983 #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTSTART_LEN 4 1984 /* Value of seconds timestamp */ 1985 #define MC_CMD_PTP_OUT_SYNCHRONIZE_SECONDS_OFST 4 1986 #define MC_CMD_PTP_OUT_SYNCHRONIZE_SECONDS_LEN 4 1987 /* Timestamp major value */ 1988 #define MC_CMD_PTP_OUT_SYNCHRONIZE_MAJOR_OFST 4 1989 #define MC_CMD_PTP_OUT_SYNCHRONIZE_MAJOR_LEN 4 1990 /* Value of nanoseconds timestamp */ 1991 #define MC_CMD_PTP_OUT_SYNCHRONIZE_NANOSECONDS_OFST 8 1992 #define MC_CMD_PTP_OUT_SYNCHRONIZE_NANOSECONDS_LEN 4 1993 /* Timestamp minor value */ 1994 #define MC_CMD_PTP_OUT_SYNCHRONIZE_MINOR_OFST 8 1995 #define MC_CMD_PTP_OUT_SYNCHRONIZE_MINOR_LEN 4 1996 /* Host time immediately after NIC's hardware clock read */ 1997 #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTEND_OFST 12 1998 #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTEND_LEN 4 1999 /* Number of nanoseconds waited after reading NIC's hardware clock */ 2000 #define MC_CMD_PTP_OUT_SYNCHRONIZE_WAITNS_OFST 16 2001 #define MC_CMD_PTP_OUT_SYNCHRONIZE_WAITNS_LEN 4 2002 2003 /* MC_CMD_PTP_OUT_MANFTEST_BASIC msgresponse */ 2004 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_LEN 8 2005 /* Results of testing */ 2006 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_RESULT_OFST 0 2007 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_RESULT_LEN 4 2008 /* enum: Successful test */ 2009 #define MC_CMD_PTP_MANF_SUCCESS 0x0 2010 /* enum: FPGA load failed */ 2011 #define MC_CMD_PTP_MANF_FPGA_LOAD 0x1 2012 /* enum: FPGA version invalid */ 2013 #define MC_CMD_PTP_MANF_FPGA_VERSION 0x2 2014 /* enum: FPGA registers incorrect */ 2015 #define MC_CMD_PTP_MANF_FPGA_REGISTERS 0x3 2016 /* enum: Oscillator possibly not working? */ 2017 #define MC_CMD_PTP_MANF_OSCILLATOR 0x4 2018 /* enum: Timestamps not increasing */ 2019 #define MC_CMD_PTP_MANF_TIMESTAMPS 0x5 2020 /* enum: Mismatched packet count */ 2021 #define MC_CMD_PTP_MANF_PACKET_COUNT 0x6 2022 /* enum: Mismatched packet count (Siena filter and FPGA) */ 2023 #define MC_CMD_PTP_MANF_FILTER_COUNT 0x7 2024 /* enum: Not enough packets to perform timestamp check */ 2025 #define MC_CMD_PTP_MANF_PACKET_ENOUGH 0x8 2026 /* enum: Timestamp trigger GPIO not working */ 2027 #define MC_CMD_PTP_MANF_GPIO_TRIGGER 0x9 2028 /* enum: Insufficient PPS events to perform checks */ 2029 #define MC_CMD_PTP_MANF_PPS_ENOUGH 0xa 2030 /* enum: PPS time event period not sufficiently close to 1s. */ 2031 #define MC_CMD_PTP_MANF_PPS_PERIOD 0xb 2032 /* enum: PPS time event nS reading not sufficiently close to zero. */ 2033 #define MC_CMD_PTP_MANF_PPS_NS 0xc 2034 /* enum: PTP peripheral registers incorrect */ 2035 #define MC_CMD_PTP_MANF_REGISTERS 0xd 2036 /* enum: Failed to read time from PTP peripheral */ 2037 #define MC_CMD_PTP_MANF_CLOCK_READ 0xe 2038 /* Presence of external oscillator */ 2039 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_EXTOSC_OFST 4 2040 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_EXTOSC_LEN 4 2041 2042 /* MC_CMD_PTP_OUT_MANFTEST_PACKET msgresponse */ 2043 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_LEN 12 2044 /* Results of testing */ 2045 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_RESULT_OFST 0 2046 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_RESULT_LEN 4 2047 /* Number of packets received by FPGA */ 2048 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FPGACOUNT_OFST 4 2049 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FPGACOUNT_LEN 4 2050 /* Number of packets received by Siena filters */ 2051 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FILTERCOUNT_OFST 8 2052 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FILTERCOUNT_LEN 4 2053 2054 /* MC_CMD_PTP_OUT_FPGAREAD msgresponse */ 2055 #define MC_CMD_PTP_OUT_FPGAREAD_LENMIN 1 2056 #define MC_CMD_PTP_OUT_FPGAREAD_LENMAX 252 2057 #define MC_CMD_PTP_OUT_FPGAREAD_LEN(num) (0+1*(num)) 2058 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_OFST 0 2059 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_LEN 1 2060 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MINNUM 1 2061 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MAXNUM 252 2062 2063 /* MC_CMD_PTP_OUT_GET_TIME_FORMAT msgresponse */ 2064 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_LEN 4 2065 /* Time format required/used by for this NIC. Applies to all PTP MCDI 2066 * operations that pass times between the host and firmware. If this operation 2067 * is not supported (older firmware) a format of seconds and nanoseconds should 2068 * be assumed. Note this enum is deprecated. Do not add to it- use the 2069 * TIME_FORMAT field in MC_CMD_PTP_OUT_GET_ATTRIBUTES instead. 2070 */ 2071 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_FORMAT_OFST 0 2072 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_FORMAT_LEN 4 2073 /* enum: Times are in seconds and nanoseconds */ 2074 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_NANOSECONDS 0x0 2075 /* enum: Major register has units of 16 second per tick, minor 8 ns per tick */ 2076 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_16SECONDS_8NANOSECONDS 0x1 2077 /* enum: Major register has units of seconds, minor 2^-27s per tick */ 2078 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_27FRACTION 0x2 2079 2080 /* MC_CMD_PTP_OUT_GET_ATTRIBUTES msgresponse */ 2081 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_LEN 24 2082 /* Time format required/used by for this NIC. Applies to all PTP MCDI 2083 * operations that pass times between the host and firmware. If this operation 2084 * is not supported (older firmware) a format of seconds and nanoseconds should 2085 * be assumed. 2086 */ 2087 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_TIME_FORMAT_OFST 0 2088 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_TIME_FORMAT_LEN 4 2089 /* enum: Times are in seconds and nanoseconds */ 2090 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_NANOSECONDS 0x0 2091 /* enum: Major register has units of 16 second per tick, minor 8 ns per tick */ 2092 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_16SECONDS_8NANOSECONDS 0x1 2093 /* enum: Major register has units of seconds, minor 2^-27s per tick */ 2094 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_27FRACTION 0x2 2095 /* enum: Major register units are seconds, minor units are quarter nanoseconds 2096 */ 2097 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_QTR_NANOSECONDS 0x3 2098 /* Minimum acceptable value for a corrected synchronization timeset. When 2099 * comparing host and NIC clock times, the MC returns a set of samples that 2100 * contain the host start and end time, the MC time when the host start was 2101 * detected and the time the MC waited between reading the time and detecting 2102 * the host end. The corrected sync window is the difference between the host 2103 * end and start times minus the time that the MC waited for host end. 2104 */ 2105 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SYNC_WINDOW_MIN_OFST 4 2106 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SYNC_WINDOW_MIN_LEN 4 2107 /* Various PTP capabilities */ 2108 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_CAPABILITIES_OFST 8 2109 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_CAPABILITIES_LEN 4 2110 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_LBN 0 2111 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_WIDTH 1 2112 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RX_TSTAMP_OOB_LBN 1 2113 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RX_TSTAMP_OOB_WIDTH 1 2114 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_64BIT_SECONDS_LBN 2 2115 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_64BIT_SECONDS_WIDTH 1 2116 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_FP44_FREQ_ADJ_LBN 3 2117 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_FP44_FREQ_ADJ_WIDTH 1 2118 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED0_OFST 12 2119 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED0_LEN 4 2120 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED1_OFST 16 2121 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED1_LEN 4 2122 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED2_OFST 20 2123 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED2_LEN 4 2124 2125 /* MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS msgresponse */ 2126 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_LEN 16 2127 /* Uncorrected error on PTP transmit timestamps in NIC clock format */ 2128 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_TRANSMIT_OFST 0 2129 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_TRANSMIT_LEN 4 2130 /* Uncorrected error on PTP receive timestamps in NIC clock format */ 2131 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_RECEIVE_OFST 4 2132 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_RECEIVE_LEN 4 2133 /* Uncorrected error on PPS output in NIC clock format */ 2134 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_OUT_OFST 8 2135 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_OUT_LEN 4 2136 /* Uncorrected error on PPS input in NIC clock format */ 2137 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_IN_OFST 12 2138 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_IN_LEN 4 2139 2140 /* MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2 msgresponse */ 2141 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_LEN 24 2142 /* Uncorrected error on PTP transmit timestamps in NIC clock format */ 2143 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_TX_OFST 0 2144 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_TX_LEN 4 2145 /* Uncorrected error on PTP receive timestamps in NIC clock format */ 2146 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_RX_OFST 4 2147 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_RX_LEN 4 2148 /* Uncorrected error on PPS output in NIC clock format */ 2149 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_OUT_OFST 8 2150 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_OUT_LEN 4 2151 /* Uncorrected error on PPS input in NIC clock format */ 2152 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_IN_OFST 12 2153 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_IN_LEN 4 2154 /* Uncorrected error on non-PTP transmit timestamps in NIC clock format */ 2155 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_TX_OFST 16 2156 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_TX_LEN 4 2157 /* Uncorrected error on non-PTP receive timestamps in NIC clock format */ 2158 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_RX_OFST 20 2159 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_RX_LEN 4 2160 2161 /* MC_CMD_PTP_OUT_MANFTEST_PPS msgresponse */ 2162 #define MC_CMD_PTP_OUT_MANFTEST_PPS_LEN 4 2163 /* Results of testing */ 2164 #define MC_CMD_PTP_OUT_MANFTEST_PPS_TEST_RESULT_OFST 0 2165 #define MC_CMD_PTP_OUT_MANFTEST_PPS_TEST_RESULT_LEN 4 2166 /* Enum values, see field(s): */ 2167 /* MC_CMD_PTP_OUT_MANFTEST_BASIC/TEST_RESULT */ 2168 2169 /* MC_CMD_PTP_OUT_SET_SYNC_STATUS msgresponse */ 2170 #define MC_CMD_PTP_OUT_SET_SYNC_STATUS_LEN 0 2171 2172 2173 /***********************************/ 2174 /* MC_CMD_CSR_READ32 2175 * Read 32bit words from the indirect memory map. 2176 */ 2177 #define MC_CMD_CSR_READ32 0xc 2178 #undef MC_CMD_0xc_PRIVILEGE_CTG 2179 2180 #define MC_CMD_0xc_PRIVILEGE_CTG SRIOV_CTG_INSECURE 2181 2182 /* MC_CMD_CSR_READ32_IN msgrequest */ 2183 #define MC_CMD_CSR_READ32_IN_LEN 12 2184 /* Address */ 2185 #define MC_CMD_CSR_READ32_IN_ADDR_OFST 0 2186 #define MC_CMD_CSR_READ32_IN_ADDR_LEN 4 2187 #define MC_CMD_CSR_READ32_IN_STEP_OFST 4 2188 #define MC_CMD_CSR_READ32_IN_STEP_LEN 4 2189 #define MC_CMD_CSR_READ32_IN_NUMWORDS_OFST 8 2190 #define MC_CMD_CSR_READ32_IN_NUMWORDS_LEN 4 2191 2192 /* MC_CMD_CSR_READ32_OUT msgresponse */ 2193 #define MC_CMD_CSR_READ32_OUT_LENMIN 4 2194 #define MC_CMD_CSR_READ32_OUT_LENMAX 252 2195 #define MC_CMD_CSR_READ32_OUT_LEN(num) (0+4*(num)) 2196 /* The last dword is the status, not a value read */ 2197 #define MC_CMD_CSR_READ32_OUT_BUFFER_OFST 0 2198 #define MC_CMD_CSR_READ32_OUT_BUFFER_LEN 4 2199 #define MC_CMD_CSR_READ32_OUT_BUFFER_MINNUM 1 2200 #define MC_CMD_CSR_READ32_OUT_BUFFER_MAXNUM 63 2201 2202 2203 /***********************************/ 2204 /* MC_CMD_CSR_WRITE32 2205 * Write 32bit dwords to the indirect memory map. 2206 */ 2207 #define MC_CMD_CSR_WRITE32 0xd 2208 #undef MC_CMD_0xd_PRIVILEGE_CTG 2209 2210 #define MC_CMD_0xd_PRIVILEGE_CTG SRIOV_CTG_INSECURE 2211 2212 /* MC_CMD_CSR_WRITE32_IN msgrequest */ 2213 #define MC_CMD_CSR_WRITE32_IN_LENMIN 12 2214 #define MC_CMD_CSR_WRITE32_IN_LENMAX 252 2215 #define MC_CMD_CSR_WRITE32_IN_LEN(num) (8+4*(num)) 2216 /* Address */ 2217 #define MC_CMD_CSR_WRITE32_IN_ADDR_OFST 0 2218 #define MC_CMD_CSR_WRITE32_IN_ADDR_LEN 4 2219 #define MC_CMD_CSR_WRITE32_IN_STEP_OFST 4 2220 #define MC_CMD_CSR_WRITE32_IN_STEP_LEN 4 2221 #define MC_CMD_CSR_WRITE32_IN_BUFFER_OFST 8 2222 #define MC_CMD_CSR_WRITE32_IN_BUFFER_LEN 4 2223 #define MC_CMD_CSR_WRITE32_IN_BUFFER_MINNUM 1 2224 #define MC_CMD_CSR_WRITE32_IN_BUFFER_MAXNUM 61 2225 2226 /* MC_CMD_CSR_WRITE32_OUT msgresponse */ 2227 #define MC_CMD_CSR_WRITE32_OUT_LEN 4 2228 #define MC_CMD_CSR_WRITE32_OUT_STATUS_OFST 0 2229 #define MC_CMD_CSR_WRITE32_OUT_STATUS_LEN 4 2230 2231 2232 /***********************************/ 2233 /* MC_CMD_HP 2234 * These commands are used for HP related features. They are grouped under one 2235 * MCDI command to avoid creating too many MCDI commands. 2236 */ 2237 #define MC_CMD_HP 0x54 2238 #undef MC_CMD_0x54_PRIVILEGE_CTG 2239 2240 #define MC_CMD_0x54_PRIVILEGE_CTG SRIOV_CTG_ADMIN 2241 2242 /* MC_CMD_HP_IN msgrequest */ 2243 #define MC_CMD_HP_IN_LEN 16 2244 /* HP OCSD sub-command. When address is not NULL, request activation of OCSD at 2245 * the specified address with the specified interval.When address is NULL, 2246 * INTERVAL is interpreted as a command: 0: stop OCSD / 1: Report OCSD current 2247 * state / 2: (debug) Show temperature reported by one of the supported 2248 * sensors. 2249 */ 2250 #define MC_CMD_HP_IN_SUBCMD_OFST 0 2251 #define MC_CMD_HP_IN_SUBCMD_LEN 4 2252 /* enum: OCSD (Option Card Sensor Data) sub-command. */ 2253 #define MC_CMD_HP_IN_OCSD_SUBCMD 0x0 2254 /* enum: Last known valid HP sub-command. */ 2255 #define MC_CMD_HP_IN_LAST_SUBCMD 0x0 2256 /* The address to the array of sensor fields. (Or NULL to use a sub-command.) 2257 */ 2258 #define MC_CMD_HP_IN_OCSD_ADDR_OFST 4 2259 #define MC_CMD_HP_IN_OCSD_ADDR_LEN 8 2260 #define MC_CMD_HP_IN_OCSD_ADDR_LO_OFST 4 2261 #define MC_CMD_HP_IN_OCSD_ADDR_HI_OFST 8 2262 /* The requested update interval, in seconds. (Or the sub-command if ADDR is 2263 * NULL.) 2264 */ 2265 #define MC_CMD_HP_IN_OCSD_INTERVAL_OFST 12 2266 #define MC_CMD_HP_IN_OCSD_INTERVAL_LEN 4 2267 2268 /* MC_CMD_HP_OUT msgresponse */ 2269 #define MC_CMD_HP_OUT_LEN 4 2270 #define MC_CMD_HP_OUT_OCSD_STATUS_OFST 0 2271 #define MC_CMD_HP_OUT_OCSD_STATUS_LEN 4 2272 /* enum: OCSD stopped for this card. */ 2273 #define MC_CMD_HP_OUT_OCSD_STOPPED 0x1 2274 /* enum: OCSD was successfully started with the address provided. */ 2275 #define MC_CMD_HP_OUT_OCSD_STARTED 0x2 2276 /* enum: OCSD was already started for this card. */ 2277 #define MC_CMD_HP_OUT_OCSD_ALREADY_STARTED 0x3 2278 2279 2280 /***********************************/ 2281 /* MC_CMD_STACKINFO 2282 * Get stack information. 2283 */ 2284 #define MC_CMD_STACKINFO 0xf 2285 #undef MC_CMD_0xf_PRIVILEGE_CTG 2286 2287 #define MC_CMD_0xf_PRIVILEGE_CTG SRIOV_CTG_ADMIN 2288 2289 /* MC_CMD_STACKINFO_IN msgrequest */ 2290 #define MC_CMD_STACKINFO_IN_LEN 0 2291 2292 /* MC_CMD_STACKINFO_OUT msgresponse */ 2293 #define MC_CMD_STACKINFO_OUT_LENMIN 12 2294 #define MC_CMD_STACKINFO_OUT_LENMAX 252 2295 #define MC_CMD_STACKINFO_OUT_LEN(num) (0+12*(num)) 2296 /* (thread ptr, stack size, free space) for each thread in system */ 2297 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_OFST 0 2298 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_LEN 12 2299 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_MINNUM 1 2300 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_MAXNUM 21 2301 2302 2303 /***********************************/ 2304 /* MC_CMD_MDIO_READ 2305 * MDIO register read. 2306 */ 2307 #define MC_CMD_MDIO_READ 0x10 2308 #undef MC_CMD_0x10_PRIVILEGE_CTG 2309 2310 #define MC_CMD_0x10_PRIVILEGE_CTG SRIOV_CTG_GENERAL 2311 2312 /* MC_CMD_MDIO_READ_IN msgrequest */ 2313 #define MC_CMD_MDIO_READ_IN_LEN 16 2314 /* Bus number; there are two MDIO buses: one for the internal PHY, and one for 2315 * external devices. 2316 */ 2317 #define MC_CMD_MDIO_READ_IN_BUS_OFST 0 2318 #define MC_CMD_MDIO_READ_IN_BUS_LEN 4 2319 /* enum: Internal. */ 2320 #define MC_CMD_MDIO_BUS_INTERNAL 0x0 2321 /* enum: External. */ 2322 #define MC_CMD_MDIO_BUS_EXTERNAL 0x1 2323 /* Port address */ 2324 #define MC_CMD_MDIO_READ_IN_PRTAD_OFST 4 2325 #define MC_CMD_MDIO_READ_IN_PRTAD_LEN 4 2326 /* Device Address or clause 22. */ 2327 #define MC_CMD_MDIO_READ_IN_DEVAD_OFST 8 2328 #define MC_CMD_MDIO_READ_IN_DEVAD_LEN 4 2329 /* enum: By default all the MCDI MDIO operations perform clause45 mode. If you 2330 * want to use clause22 then set DEVAD = MC_CMD_MDIO_CLAUSE22. 2331 */ 2332 #define MC_CMD_MDIO_CLAUSE22 0x20 2333 /* Address */ 2334 #define MC_CMD_MDIO_READ_IN_ADDR_OFST 12 2335 #define MC_CMD_MDIO_READ_IN_ADDR_LEN 4 2336 2337 /* MC_CMD_MDIO_READ_OUT msgresponse */ 2338 #define MC_CMD_MDIO_READ_OUT_LEN 8 2339 /* Value */ 2340 #define MC_CMD_MDIO_READ_OUT_VALUE_OFST 0 2341 #define MC_CMD_MDIO_READ_OUT_VALUE_LEN 4 2342 /* Status the MDIO commands return the raw status bits from the MDIO block. A 2343 * "good" transaction should have the DONE bit set and all other bits clear. 2344 */ 2345 #define MC_CMD_MDIO_READ_OUT_STATUS_OFST 4 2346 #define MC_CMD_MDIO_READ_OUT_STATUS_LEN 4 2347 /* enum: Good. */ 2348 #define MC_CMD_MDIO_STATUS_GOOD 0x8 2349 2350 2351 /***********************************/ 2352 /* MC_CMD_MDIO_WRITE 2353 * MDIO register write. 2354 */ 2355 #define MC_CMD_MDIO_WRITE 0x11 2356 #undef MC_CMD_0x11_PRIVILEGE_CTG 2357 2358 #define MC_CMD_0x11_PRIVILEGE_CTG SRIOV_CTG_ADMIN 2359 2360 /* MC_CMD_MDIO_WRITE_IN msgrequest */ 2361 #define MC_CMD_MDIO_WRITE_IN_LEN 20 2362 /* Bus number; there are two MDIO buses: one for the internal PHY, and one for 2363 * external devices. 2364 */ 2365 #define MC_CMD_MDIO_WRITE_IN_BUS_OFST 0 2366 #define MC_CMD_MDIO_WRITE_IN_BUS_LEN 4 2367 /* enum: Internal. */ 2368 /* MC_CMD_MDIO_BUS_INTERNAL 0x0 */ 2369 /* enum: External. */ 2370 /* MC_CMD_MDIO_BUS_EXTERNAL 0x1 */ 2371 /* Port address */ 2372 #define MC_CMD_MDIO_WRITE_IN_PRTAD_OFST 4 2373 #define MC_CMD_MDIO_WRITE_IN_PRTAD_LEN 4 2374 /* Device Address or clause 22. */ 2375 #define MC_CMD_MDIO_WRITE_IN_DEVAD_OFST 8 2376 #define MC_CMD_MDIO_WRITE_IN_DEVAD_LEN 4 2377 /* enum: By default all the MCDI MDIO operations perform clause45 mode. If you 2378 * want to use clause22 then set DEVAD = MC_CMD_MDIO_CLAUSE22. 2379 */ 2380 /* MC_CMD_MDIO_CLAUSE22 0x20 */ 2381 /* Address */ 2382 #define MC_CMD_MDIO_WRITE_IN_ADDR_OFST 12 2383 #define MC_CMD_MDIO_WRITE_IN_ADDR_LEN 4 2384 /* Value */ 2385 #define MC_CMD_MDIO_WRITE_IN_VALUE_OFST 16 2386 #define MC_CMD_MDIO_WRITE_IN_VALUE_LEN 4 2387 2388 /* MC_CMD_MDIO_WRITE_OUT msgresponse */ 2389 #define MC_CMD_MDIO_WRITE_OUT_LEN 4 2390 /* Status; the MDIO commands return the raw status bits from the MDIO block. A 2391 * "good" transaction should have the DONE bit set and all other bits clear. 2392 */ 2393 #define MC_CMD_MDIO_WRITE_OUT_STATUS_OFST 0 2394 #define MC_CMD_MDIO_WRITE_OUT_STATUS_LEN 4 2395 /* enum: Good. */ 2396 /* MC_CMD_MDIO_STATUS_GOOD 0x8 */ 2397 2398 2399 /***********************************/ 2400 /* MC_CMD_DBI_WRITE 2401 * Write DBI register(s). 2402 */ 2403 #define MC_CMD_DBI_WRITE 0x12 2404 #undef MC_CMD_0x12_PRIVILEGE_CTG 2405 2406 #define MC_CMD_0x12_PRIVILEGE_CTG SRIOV_CTG_INSECURE 2407 2408 /* MC_CMD_DBI_WRITE_IN msgrequest */ 2409 #define MC_CMD_DBI_WRITE_IN_LENMIN 12 2410 #define MC_CMD_DBI_WRITE_IN_LENMAX 252 2411 #define MC_CMD_DBI_WRITE_IN_LEN(num) (0+12*(num)) 2412 /* Each write op consists of an address (offset 0), byte enable/VF/CS2 (offset 2413 * 32) and value (offset 64). See MC_CMD_DBIWROP_TYPEDEF. 2414 */ 2415 #define MC_CMD_DBI_WRITE_IN_DBIWROP_OFST 0 2416 #define MC_CMD_DBI_WRITE_IN_DBIWROP_LEN 12 2417 #define MC_CMD_DBI_WRITE_IN_DBIWROP_MINNUM 1 2418 #define MC_CMD_DBI_WRITE_IN_DBIWROP_MAXNUM 21 2419 2420 /* MC_CMD_DBI_WRITE_OUT msgresponse */ 2421 #define MC_CMD_DBI_WRITE_OUT_LEN 0 2422 2423 /* MC_CMD_DBIWROP_TYPEDEF structuredef */ 2424 #define MC_CMD_DBIWROP_TYPEDEF_LEN 12 2425 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST 0 2426 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_LEN 4 2427 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_LBN 0 2428 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_WIDTH 32 2429 #define MC_CMD_DBIWROP_TYPEDEF_PARMS_OFST 4 2430 #define MC_CMD_DBIWROP_TYPEDEF_PARMS_LEN 4 2431 #define MC_CMD_DBIWROP_TYPEDEF_VF_NUM_LBN 16 2432 #define MC_CMD_DBIWROP_TYPEDEF_VF_NUM_WIDTH 16 2433 #define MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_LBN 15 2434 #define MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_WIDTH 1 2435 #define MC_CMD_DBIWROP_TYPEDEF_CS2_LBN 14 2436 #define MC_CMD_DBIWROP_TYPEDEF_CS2_WIDTH 1 2437 #define MC_CMD_DBIWROP_TYPEDEF_PARMS_LBN 32 2438 #define MC_CMD_DBIWROP_TYPEDEF_PARMS_WIDTH 32 2439 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST 8 2440 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_LEN 4 2441 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_LBN 64 2442 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_WIDTH 32 2443 2444 2445 /***********************************/ 2446 /* MC_CMD_PORT_READ32 2447 * Read a 32-bit register from the indirect port register map. The port to 2448 * access is implied by the Shared memory channel used. 2449 */ 2450 #define MC_CMD_PORT_READ32 0x14 2451 2452 /* MC_CMD_PORT_READ32_IN msgrequest */ 2453 #define MC_CMD_PORT_READ32_IN_LEN 4 2454 /* Address */ 2455 #define MC_CMD_PORT_READ32_IN_ADDR_OFST 0 2456 #define MC_CMD_PORT_READ32_IN_ADDR_LEN 4 2457 2458 /* MC_CMD_PORT_READ32_OUT msgresponse */ 2459 #define MC_CMD_PORT_READ32_OUT_LEN 8 2460 /* Value */ 2461 #define MC_CMD_PORT_READ32_OUT_VALUE_OFST 0 2462 #define MC_CMD_PORT_READ32_OUT_VALUE_LEN 4 2463 /* Status */ 2464 #define MC_CMD_PORT_READ32_OUT_STATUS_OFST 4 2465 #define MC_CMD_PORT_READ32_OUT_STATUS_LEN 4 2466 2467 2468 /***********************************/ 2469 /* MC_CMD_PORT_WRITE32 2470 * Write a 32-bit register to the indirect port register map. The port to 2471 * access is implied by the Shared memory channel used. 2472 */ 2473 #define MC_CMD_PORT_WRITE32 0x15 2474 2475 /* MC_CMD_PORT_WRITE32_IN msgrequest */ 2476 #define MC_CMD_PORT_WRITE32_IN_LEN 8 2477 /* Address */ 2478 #define MC_CMD_PORT_WRITE32_IN_ADDR_OFST 0 2479 #define MC_CMD_PORT_WRITE32_IN_ADDR_LEN 4 2480 /* Value */ 2481 #define MC_CMD_PORT_WRITE32_IN_VALUE_OFST 4 2482 #define MC_CMD_PORT_WRITE32_IN_VALUE_LEN 4 2483 2484 /* MC_CMD_PORT_WRITE32_OUT msgresponse */ 2485 #define MC_CMD_PORT_WRITE32_OUT_LEN 4 2486 /* Status */ 2487 #define MC_CMD_PORT_WRITE32_OUT_STATUS_OFST 0 2488 #define MC_CMD_PORT_WRITE32_OUT_STATUS_LEN 4 2489 2490 2491 /***********************************/ 2492 /* MC_CMD_PORT_READ128 2493 * Read a 128-bit register from the indirect port register map. The port to 2494 * access is implied by the Shared memory channel used. 2495 */ 2496 #define MC_CMD_PORT_READ128 0x16 2497 2498 /* MC_CMD_PORT_READ128_IN msgrequest */ 2499 #define MC_CMD_PORT_READ128_IN_LEN 4 2500 /* Address */ 2501 #define MC_CMD_PORT_READ128_IN_ADDR_OFST 0 2502 #define MC_CMD_PORT_READ128_IN_ADDR_LEN 4 2503 2504 /* MC_CMD_PORT_READ128_OUT msgresponse */ 2505 #define MC_CMD_PORT_READ128_OUT_LEN 20 2506 /* Value */ 2507 #define MC_CMD_PORT_READ128_OUT_VALUE_OFST 0 2508 #define MC_CMD_PORT_READ128_OUT_VALUE_LEN 16 2509 /* Status */ 2510 #define MC_CMD_PORT_READ128_OUT_STATUS_OFST 16 2511 #define MC_CMD_PORT_READ128_OUT_STATUS_LEN 4 2512 2513 2514 /***********************************/ 2515 /* MC_CMD_PORT_WRITE128 2516 * Write a 128-bit register to the indirect port register map. The port to 2517 * access is implied by the Shared memory channel used. 2518 */ 2519 #define MC_CMD_PORT_WRITE128 0x17 2520 2521 /* MC_CMD_PORT_WRITE128_IN msgrequest */ 2522 #define MC_CMD_PORT_WRITE128_IN_LEN 20 2523 /* Address */ 2524 #define MC_CMD_PORT_WRITE128_IN_ADDR_OFST 0 2525 #define MC_CMD_PORT_WRITE128_IN_ADDR_LEN 4 2526 /* Value */ 2527 #define MC_CMD_PORT_WRITE128_IN_VALUE_OFST 4 2528 #define MC_CMD_PORT_WRITE128_IN_VALUE_LEN 16 2529 2530 /* MC_CMD_PORT_WRITE128_OUT msgresponse */ 2531 #define MC_CMD_PORT_WRITE128_OUT_LEN 4 2532 /* Status */ 2533 #define MC_CMD_PORT_WRITE128_OUT_STATUS_OFST 0 2534 #define MC_CMD_PORT_WRITE128_OUT_STATUS_LEN 4 2535 2536 /* MC_CMD_CAPABILITIES structuredef */ 2537 #define MC_CMD_CAPABILITIES_LEN 4 2538 /* Small buf table. */ 2539 #define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_LBN 0 2540 #define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_WIDTH 1 2541 /* Turbo mode (for Maranello). */ 2542 #define MC_CMD_CAPABILITIES_TURBO_LBN 1 2543 #define MC_CMD_CAPABILITIES_TURBO_WIDTH 1 2544 /* Turbo mode active (for Maranello). */ 2545 #define MC_CMD_CAPABILITIES_TURBO_ACTIVE_LBN 2 2546 #define MC_CMD_CAPABILITIES_TURBO_ACTIVE_WIDTH 1 2547 /* PTP offload. */ 2548 #define MC_CMD_CAPABILITIES_PTP_LBN 3 2549 #define MC_CMD_CAPABILITIES_PTP_WIDTH 1 2550 /* AOE mode. */ 2551 #define MC_CMD_CAPABILITIES_AOE_LBN 4 2552 #define MC_CMD_CAPABILITIES_AOE_WIDTH 1 2553 /* AOE mode active. */ 2554 #define MC_CMD_CAPABILITIES_AOE_ACTIVE_LBN 5 2555 #define MC_CMD_CAPABILITIES_AOE_ACTIVE_WIDTH 1 2556 /* AOE mode active. */ 2557 #define MC_CMD_CAPABILITIES_FC_ACTIVE_LBN 6 2558 #define MC_CMD_CAPABILITIES_FC_ACTIVE_WIDTH 1 2559 #define MC_CMD_CAPABILITIES_RESERVED_LBN 7 2560 #define MC_CMD_CAPABILITIES_RESERVED_WIDTH 25 2561 2562 2563 /***********************************/ 2564 /* MC_CMD_GET_BOARD_CFG 2565 * Returns the MC firmware configuration structure. 2566 */ 2567 #define MC_CMD_GET_BOARD_CFG 0x18 2568 #undef MC_CMD_0x18_PRIVILEGE_CTG 2569 2570 #define MC_CMD_0x18_PRIVILEGE_CTG SRIOV_CTG_GENERAL 2571 2572 /* MC_CMD_GET_BOARD_CFG_IN msgrequest */ 2573 #define MC_CMD_GET_BOARD_CFG_IN_LEN 0 2574 2575 /* MC_CMD_GET_BOARD_CFG_OUT msgresponse */ 2576 #define MC_CMD_GET_BOARD_CFG_OUT_LENMIN 96 2577 #define MC_CMD_GET_BOARD_CFG_OUT_LENMAX 136 2578 #define MC_CMD_GET_BOARD_CFG_OUT_LEN(num) (72+2*(num)) 2579 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_OFST 0 2580 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_LEN 4 2581 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_OFST 4 2582 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_LEN 32 2583 /* See MC_CMD_CAPABILITIES */ 2584 #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT0_OFST 36 2585 #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT0_LEN 4 2586 /* See MC_CMD_CAPABILITIES */ 2587 #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT1_OFST 40 2588 #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT1_LEN 4 2589 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_OFST 44 2590 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_LEN 6 2591 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_OFST 50 2592 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_LEN 6 2593 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT0_OFST 56 2594 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT0_LEN 4 2595 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT1_OFST 60 2596 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT1_LEN 4 2597 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT0_OFST 64 2598 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT0_LEN 4 2599 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT1_OFST 68 2600 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT1_LEN 4 2601 /* This field contains a 16-bit value for each of the types of NVRAM area. The 2602 * values are defined in the firmware/mc/platform/.c file for a specific board 2603 * type, but otherwise have no meaning to the MC; they are used by the driver 2604 * to manage selection of appropriate firmware updates. 2605 */ 2606 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_OFST 72 2607 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_LEN 2 2608 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MINNUM 12 2609 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM 32 2610 2611 2612 /***********************************/ 2613 /* MC_CMD_DBI_READX 2614 * Read DBI register(s) -- extended functionality 2615 */ 2616 #define MC_CMD_DBI_READX 0x19 2617 #undef MC_CMD_0x19_PRIVILEGE_CTG 2618 2619 #define MC_CMD_0x19_PRIVILEGE_CTG SRIOV_CTG_INSECURE 2620 2621 /* MC_CMD_DBI_READX_IN msgrequest */ 2622 #define MC_CMD_DBI_READX_IN_LENMIN 8 2623 #define MC_CMD_DBI_READX_IN_LENMAX 248 2624 #define MC_CMD_DBI_READX_IN_LEN(num) (0+8*(num)) 2625 /* Each Read op consists of an address (offset 0), VF/CS2) */ 2626 #define MC_CMD_DBI_READX_IN_DBIRDOP_OFST 0 2627 #define MC_CMD_DBI_READX_IN_DBIRDOP_LEN 8 2628 #define MC_CMD_DBI_READX_IN_DBIRDOP_LO_OFST 0 2629 #define MC_CMD_DBI_READX_IN_DBIRDOP_HI_OFST 4 2630 #define MC_CMD_DBI_READX_IN_DBIRDOP_MINNUM 1 2631 #define MC_CMD_DBI_READX_IN_DBIRDOP_MAXNUM 31 2632 2633 /* MC_CMD_DBI_READX_OUT msgresponse */ 2634 #define MC_CMD_DBI_READX_OUT_LENMIN 4 2635 #define MC_CMD_DBI_READX_OUT_LENMAX 252 2636 #define MC_CMD_DBI_READX_OUT_LEN(num) (0+4*(num)) 2637 /* Value */ 2638 #define MC_CMD_DBI_READX_OUT_VALUE_OFST 0 2639 #define MC_CMD_DBI_READX_OUT_VALUE_LEN 4 2640 #define MC_CMD_DBI_READX_OUT_VALUE_MINNUM 1 2641 #define MC_CMD_DBI_READX_OUT_VALUE_MAXNUM 63 2642 2643 /* MC_CMD_DBIRDOP_TYPEDEF structuredef */ 2644 #define MC_CMD_DBIRDOP_TYPEDEF_LEN 8 2645 #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_OFST 0 2646 #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_LEN 4 2647 #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_LBN 0 2648 #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_WIDTH 32 2649 #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_OFST 4 2650 #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_LEN 4 2651 #define MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_LBN 16 2652 #define MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_WIDTH 16 2653 #define MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_LBN 15 2654 #define MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_WIDTH 1 2655 #define MC_CMD_DBIRDOP_TYPEDEF_CS2_LBN 14 2656 #define MC_CMD_DBIRDOP_TYPEDEF_CS2_WIDTH 1 2657 #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_LBN 32 2658 #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_WIDTH 32 2659 2660 2661 /***********************************/ 2662 /* MC_CMD_SET_RAND_SEED 2663 * Set the 16byte seed for the MC pseudo-random generator. 2664 */ 2665 #define MC_CMD_SET_RAND_SEED 0x1a 2666 #undef MC_CMD_0x1a_PRIVILEGE_CTG 2667 2668 #define MC_CMD_0x1a_PRIVILEGE_CTG SRIOV_CTG_INSECURE 2669 2670 /* MC_CMD_SET_RAND_SEED_IN msgrequest */ 2671 #define MC_CMD_SET_RAND_SEED_IN_LEN 16 2672 /* Seed value. */ 2673 #define MC_CMD_SET_RAND_SEED_IN_SEED_OFST 0 2674 #define MC_CMD_SET_RAND_SEED_IN_SEED_LEN 16 2675 2676 /* MC_CMD_SET_RAND_SEED_OUT msgresponse */ 2677 #define MC_CMD_SET_RAND_SEED_OUT_LEN 0 2678 2679 2680 /***********************************/ 2681 /* MC_CMD_LTSSM_HIST 2682 * Retrieve the history of the LTSSM, if the build supports it. 2683 */ 2684 #define MC_CMD_LTSSM_HIST 0x1b 2685 2686 /* MC_CMD_LTSSM_HIST_IN msgrequest */ 2687 #define MC_CMD_LTSSM_HIST_IN_LEN 0 2688 2689 /* MC_CMD_LTSSM_HIST_OUT msgresponse */ 2690 #define MC_CMD_LTSSM_HIST_OUT_LENMIN 0 2691 #define MC_CMD_LTSSM_HIST_OUT_LENMAX 252 2692 #define MC_CMD_LTSSM_HIST_OUT_LEN(num) (0+4*(num)) 2693 /* variable number of LTSSM values, as bytes. The history is read-to-clear. */ 2694 #define MC_CMD_LTSSM_HIST_OUT_DATA_OFST 0 2695 #define MC_CMD_LTSSM_HIST_OUT_DATA_LEN 4 2696 #define MC_CMD_LTSSM_HIST_OUT_DATA_MINNUM 0 2697 #define MC_CMD_LTSSM_HIST_OUT_DATA_MAXNUM 63 2698 2699 2700 /***********************************/ 2701 /* MC_CMD_DRV_ATTACH 2702 * Inform MCPU that this port is managed on the host (i.e. driver active). For 2703 * Huntington, also request the preferred datapath firmware to use if possible 2704 * (it may not be possible for this request to be fulfilled; the driver must 2705 * issue a subsequent MC_CMD_GET_CAPABILITIES command to determine which 2706 * features are actually available). The FIRMWARE_ID field is ignored by older 2707 * platforms. 2708 */ 2709 #define MC_CMD_DRV_ATTACH 0x1c 2710 #undef MC_CMD_0x1c_PRIVILEGE_CTG 2711 2712 #define MC_CMD_0x1c_PRIVILEGE_CTG SRIOV_CTG_GENERAL 2713 2714 /* MC_CMD_DRV_ATTACH_IN msgrequest */ 2715 #define MC_CMD_DRV_ATTACH_IN_LEN 12 2716 /* new state to set if UPDATE=1 */ 2717 #define MC_CMD_DRV_ATTACH_IN_NEW_STATE_OFST 0 2718 #define MC_CMD_DRV_ATTACH_IN_NEW_STATE_LEN 4 2719 #define MC_CMD_DRV_ATTACH_LBN 0 2720 #define MC_CMD_DRV_ATTACH_WIDTH 1 2721 #define MC_CMD_DRV_PREBOOT_LBN 1 2722 #define MC_CMD_DRV_PREBOOT_WIDTH 1 2723 /* 1 to set new state, or 0 to just report the existing state */ 2724 #define MC_CMD_DRV_ATTACH_IN_UPDATE_OFST 4 2725 #define MC_CMD_DRV_ATTACH_IN_UPDATE_LEN 4 2726 /* preferred datapath firmware (for Huntington; ignored for Siena) */ 2727 #define MC_CMD_DRV_ATTACH_IN_FIRMWARE_ID_OFST 8 2728 #define MC_CMD_DRV_ATTACH_IN_FIRMWARE_ID_LEN 4 2729 /* enum: Prefer to use full featured firmware */ 2730 #define MC_CMD_FW_FULL_FEATURED 0x0 2731 /* enum: Prefer to use firmware with fewer features but lower latency */ 2732 #define MC_CMD_FW_LOW_LATENCY 0x1 2733 /* enum: Prefer to use firmware for SolarCapture packed stream mode */ 2734 #define MC_CMD_FW_PACKED_STREAM 0x2 2735 /* enum: Prefer to use firmware with fewer features and simpler TX event 2736 * batching but higher TX packet rate 2737 */ 2738 #define MC_CMD_FW_HIGH_TX_RATE 0x3 2739 /* enum: Reserved value */ 2740 #define MC_CMD_FW_PACKED_STREAM_HASH_MODE_1 0x4 2741 /* enum: Prefer to use firmware with additional "rules engine" filtering 2742 * support 2743 */ 2744 #define MC_CMD_FW_RULES_ENGINE 0x5 2745 /* enum: Only this option is allowed for non-admin functions */ 2746 #define MC_CMD_FW_DONT_CARE 0xffffffff 2747 2748 /* MC_CMD_DRV_ATTACH_OUT msgresponse */ 2749 #define MC_CMD_DRV_ATTACH_OUT_LEN 4 2750 /* previous or existing state, see the bitmask at NEW_STATE */ 2751 #define MC_CMD_DRV_ATTACH_OUT_OLD_STATE_OFST 0 2752 #define MC_CMD_DRV_ATTACH_OUT_OLD_STATE_LEN 4 2753 2754 /* MC_CMD_DRV_ATTACH_EXT_OUT msgresponse */ 2755 #define MC_CMD_DRV_ATTACH_EXT_OUT_LEN 8 2756 /* previous or existing state, see the bitmask at NEW_STATE */ 2757 #define MC_CMD_DRV_ATTACH_EXT_OUT_OLD_STATE_OFST 0 2758 #define MC_CMD_DRV_ATTACH_EXT_OUT_OLD_STATE_LEN 4 2759 /* Flags associated with this function */ 2760 #define MC_CMD_DRV_ATTACH_EXT_OUT_FUNC_FLAGS_OFST 4 2761 #define MC_CMD_DRV_ATTACH_EXT_OUT_FUNC_FLAGS_LEN 4 2762 /* enum: Labels the lowest-numbered function visible to the OS */ 2763 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY 0x0 2764 /* enum: The function can control the link state of the physical port it is 2765 * bound to. 2766 */ 2767 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL 0x1 2768 /* enum: The function can perform privileged operations */ 2769 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TRUSTED 0x2 2770 /* enum: The function does not have an active port associated with it. The port 2771 * refers to the Sorrento external FPGA port. 2772 */ 2773 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_NO_ACTIVE_PORT 0x3 2774 2775 2776 /***********************************/ 2777 /* MC_CMD_SHMUART 2778 * Route UART output to circular buffer in shared memory instead. 2779 */ 2780 #define MC_CMD_SHMUART 0x1f 2781 2782 /* MC_CMD_SHMUART_IN msgrequest */ 2783 #define MC_CMD_SHMUART_IN_LEN 4 2784 /* ??? */ 2785 #define MC_CMD_SHMUART_IN_FLAG_OFST 0 2786 #define MC_CMD_SHMUART_IN_FLAG_LEN 4 2787 2788 /* MC_CMD_SHMUART_OUT msgresponse */ 2789 #define MC_CMD_SHMUART_OUT_LEN 0 2790 2791 2792 /***********************************/ 2793 /* MC_CMD_PORT_RESET 2794 * Generic per-port reset. There is no equivalent for per-board reset. Locks 2795 * required: None; Return code: 0, ETIME. NOTE: This command is deprecated - 2796 * use MC_CMD_ENTITY_RESET instead. 2797 */ 2798 #define MC_CMD_PORT_RESET 0x20 2799 #undef MC_CMD_0x20_PRIVILEGE_CTG 2800 2801 #define MC_CMD_0x20_PRIVILEGE_CTG SRIOV_CTG_GENERAL 2802 2803 /* MC_CMD_PORT_RESET_IN msgrequest */ 2804 #define MC_CMD_PORT_RESET_IN_LEN 0 2805 2806 /* MC_CMD_PORT_RESET_OUT msgresponse */ 2807 #define MC_CMD_PORT_RESET_OUT_LEN 0 2808 2809 2810 /***********************************/ 2811 /* MC_CMD_ENTITY_RESET 2812 * Generic per-resource reset. There is no equivalent for per-board reset. 2813 * Locks required: None; Return code: 0, ETIME. NOTE: This command is an 2814 * extended version of the deprecated MC_CMD_PORT_RESET with added fields. 2815 */ 2816 #define MC_CMD_ENTITY_RESET 0x20 2817 /* MC_CMD_0x20_PRIVILEGE_CTG SRIOV_CTG_GENERAL */ 2818 2819 /* MC_CMD_ENTITY_RESET_IN msgrequest */ 2820 #define MC_CMD_ENTITY_RESET_IN_LEN 4 2821 /* Optional flags field. Omitting this will perform a "legacy" reset action 2822 * (TBD). 2823 */ 2824 #define MC_CMD_ENTITY_RESET_IN_FLAG_OFST 0 2825 #define MC_CMD_ENTITY_RESET_IN_FLAG_LEN 4 2826 #define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_LBN 0 2827 #define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_WIDTH 1 2828 2829 /* MC_CMD_ENTITY_RESET_OUT msgresponse */ 2830 #define MC_CMD_ENTITY_RESET_OUT_LEN 0 2831 2832 2833 /***********************************/ 2834 /* MC_CMD_PCIE_CREDITS 2835 * Read instantaneous and minimum flow control thresholds. 2836 */ 2837 #define MC_CMD_PCIE_CREDITS 0x21 2838 2839 /* MC_CMD_PCIE_CREDITS_IN msgrequest */ 2840 #define MC_CMD_PCIE_CREDITS_IN_LEN 8 2841 /* poll period. 0 is disabled */ 2842 #define MC_CMD_PCIE_CREDITS_IN_POLL_PERIOD_OFST 0 2843 #define MC_CMD_PCIE_CREDITS_IN_POLL_PERIOD_LEN 4 2844 /* wipe statistics */ 2845 #define MC_CMD_PCIE_CREDITS_IN_WIPE_OFST 4 2846 #define MC_CMD_PCIE_CREDITS_IN_WIPE_LEN 4 2847 2848 /* MC_CMD_PCIE_CREDITS_OUT msgresponse */ 2849 #define MC_CMD_PCIE_CREDITS_OUT_LEN 16 2850 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_OFST 0 2851 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_LEN 2 2852 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_OFST 2 2853 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_LEN 2 2854 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_OFST 4 2855 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_LEN 2 2856 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_OFST 6 2857 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_LEN 2 2858 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_OFST 8 2859 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_LEN 2 2860 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_OFST 10 2861 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_LEN 2 2862 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_OFST 12 2863 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_LEN 2 2864 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_OFST 14 2865 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_LEN 2 2866 2867 2868 /***********************************/ 2869 /* MC_CMD_RXD_MONITOR 2870 * Get histogram of RX queue fill level. 2871 */ 2872 #define MC_CMD_RXD_MONITOR 0x22 2873 2874 /* MC_CMD_RXD_MONITOR_IN msgrequest */ 2875 #define MC_CMD_RXD_MONITOR_IN_LEN 12 2876 #define MC_CMD_RXD_MONITOR_IN_QID_OFST 0 2877 #define MC_CMD_RXD_MONITOR_IN_QID_LEN 4 2878 #define MC_CMD_RXD_MONITOR_IN_POLL_PERIOD_OFST 4 2879 #define MC_CMD_RXD_MONITOR_IN_POLL_PERIOD_LEN 4 2880 #define MC_CMD_RXD_MONITOR_IN_WIPE_OFST 8 2881 #define MC_CMD_RXD_MONITOR_IN_WIPE_LEN 4 2882 2883 /* MC_CMD_RXD_MONITOR_OUT msgresponse */ 2884 #define MC_CMD_RXD_MONITOR_OUT_LEN 80 2885 #define MC_CMD_RXD_MONITOR_OUT_QID_OFST 0 2886 #define MC_CMD_RXD_MONITOR_OUT_QID_LEN 4 2887 #define MC_CMD_RXD_MONITOR_OUT_RING_FILL_OFST 4 2888 #define MC_CMD_RXD_MONITOR_OUT_RING_FILL_LEN 4 2889 #define MC_CMD_RXD_MONITOR_OUT_CACHE_FILL_OFST 8 2890 #define MC_CMD_RXD_MONITOR_OUT_CACHE_FILL_LEN 4 2891 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_1_OFST 12 2892 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_1_LEN 4 2893 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_2_OFST 16 2894 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_2_LEN 4 2895 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_4_OFST 20 2896 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_4_LEN 4 2897 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_8_OFST 24 2898 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_8_LEN 4 2899 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_16_OFST 28 2900 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_16_LEN 4 2901 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_32_OFST 32 2902 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_32_LEN 4 2903 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_64_OFST 36 2904 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_64_LEN 4 2905 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_128_OFST 40 2906 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_128_LEN 4 2907 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_256_OFST 44 2908 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_256_LEN 4 2909 #define MC_CMD_RXD_MONITOR_OUT_RING_GE_256_OFST 48 2910 #define MC_CMD_RXD_MONITOR_OUT_RING_GE_256_LEN 4 2911 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_1_OFST 52 2912 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_1_LEN 4 2913 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_2_OFST 56 2914 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_2_LEN 4 2915 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_4_OFST 60 2916 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_4_LEN 4 2917 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_8_OFST 64 2918 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_8_LEN 4 2919 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_16_OFST 68 2920 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_16_LEN 4 2921 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_32_OFST 72 2922 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_32_LEN 4 2923 #define MC_CMD_RXD_MONITOR_OUT_CACHE_GE_32_OFST 76 2924 #define MC_CMD_RXD_MONITOR_OUT_CACHE_GE_32_LEN 4 2925 2926 2927 /***********************************/ 2928 /* MC_CMD_PUTS 2929 * Copy the given ASCII string out onto UART and/or out of the network port. 2930 */ 2931 #define MC_CMD_PUTS 0x23 2932 #undef MC_CMD_0x23_PRIVILEGE_CTG 2933 2934 #define MC_CMD_0x23_PRIVILEGE_CTG SRIOV_CTG_INSECURE 2935 2936 /* MC_CMD_PUTS_IN msgrequest */ 2937 #define MC_CMD_PUTS_IN_LENMIN 13 2938 #define MC_CMD_PUTS_IN_LENMAX 252 2939 #define MC_CMD_PUTS_IN_LEN(num) (12+1*(num)) 2940 #define MC_CMD_PUTS_IN_DEST_OFST 0 2941 #define MC_CMD_PUTS_IN_DEST_LEN 4 2942 #define MC_CMD_PUTS_IN_UART_LBN 0 2943 #define MC_CMD_PUTS_IN_UART_WIDTH 1 2944 #define MC_CMD_PUTS_IN_PORT_LBN 1 2945 #define MC_CMD_PUTS_IN_PORT_WIDTH 1 2946 #define MC_CMD_PUTS_IN_DHOST_OFST 4 2947 #define MC_CMD_PUTS_IN_DHOST_LEN 6 2948 #define MC_CMD_PUTS_IN_STRING_OFST 12 2949 #define MC_CMD_PUTS_IN_STRING_LEN 1 2950 #define MC_CMD_PUTS_IN_STRING_MINNUM 1 2951 #define MC_CMD_PUTS_IN_STRING_MAXNUM 240 2952 2953 /* MC_CMD_PUTS_OUT msgresponse */ 2954 #define MC_CMD_PUTS_OUT_LEN 0 2955 2956 2957 /***********************************/ 2958 /* MC_CMD_GET_PHY_CFG 2959 * Report PHY configuration. This guarantees to succeed even if the PHY is in a 2960 * 'zombie' state. Locks required: None 2961 */ 2962 #define MC_CMD_GET_PHY_CFG 0x24 2963 #undef MC_CMD_0x24_PRIVILEGE_CTG 2964 2965 #define MC_CMD_0x24_PRIVILEGE_CTG SRIOV_CTG_GENERAL 2966 2967 /* MC_CMD_GET_PHY_CFG_IN msgrequest */ 2968 #define MC_CMD_GET_PHY_CFG_IN_LEN 0 2969 2970 /* MC_CMD_GET_PHY_CFG_OUT msgresponse */ 2971 #define MC_CMD_GET_PHY_CFG_OUT_LEN 72 2972 /* flags */ 2973 #define MC_CMD_GET_PHY_CFG_OUT_FLAGS_OFST 0 2974 #define MC_CMD_GET_PHY_CFG_OUT_FLAGS_LEN 4 2975 #define MC_CMD_GET_PHY_CFG_OUT_PRESENT_LBN 0 2976 #define MC_CMD_GET_PHY_CFG_OUT_PRESENT_WIDTH 1 2977 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_LBN 1 2978 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_WIDTH 1 2979 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_LBN 2 2980 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_WIDTH 1 2981 #define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_LBN 3 2982 #define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_WIDTH 1 2983 #define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_LBN 4 2984 #define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_WIDTH 1 2985 #define MC_CMD_GET_PHY_CFG_OUT_TXDIS_LBN 5 2986 #define MC_CMD_GET_PHY_CFG_OUT_TXDIS_WIDTH 1 2987 #define MC_CMD_GET_PHY_CFG_OUT_BIST_LBN 6 2988 #define MC_CMD_GET_PHY_CFG_OUT_BIST_WIDTH 1 2989 /* ?? */ 2990 #define MC_CMD_GET_PHY_CFG_OUT_TYPE_OFST 4 2991 #define MC_CMD_GET_PHY_CFG_OUT_TYPE_LEN 4 2992 /* Bitmask of supported capabilities */ 2993 #define MC_CMD_GET_PHY_CFG_OUT_SUPPORTED_CAP_OFST 8 2994 #define MC_CMD_GET_PHY_CFG_OUT_SUPPORTED_CAP_LEN 4 2995 #define MC_CMD_PHY_CAP_10HDX_LBN 1 2996 #define MC_CMD_PHY_CAP_10HDX_WIDTH 1 2997 #define MC_CMD_PHY_CAP_10FDX_LBN 2 2998 #define MC_CMD_PHY_CAP_10FDX_WIDTH 1 2999 #define MC_CMD_PHY_CAP_100HDX_LBN 3 3000 #define MC_CMD_PHY_CAP_100HDX_WIDTH 1 3001 #define MC_CMD_PHY_CAP_100FDX_LBN 4 3002 #define MC_CMD_PHY_CAP_100FDX_WIDTH 1 3003 #define MC_CMD_PHY_CAP_1000HDX_LBN 5 3004 #define MC_CMD_PHY_CAP_1000HDX_WIDTH 1 3005 #define MC_CMD_PHY_CAP_1000FDX_LBN 6 3006 #define MC_CMD_PHY_CAP_1000FDX_WIDTH 1 3007 #define MC_CMD_PHY_CAP_10000FDX_LBN 7 3008 #define MC_CMD_PHY_CAP_10000FDX_WIDTH 1 3009 #define MC_CMD_PHY_CAP_PAUSE_LBN 8 3010 #define MC_CMD_PHY_CAP_PAUSE_WIDTH 1 3011 #define MC_CMD_PHY_CAP_ASYM_LBN 9 3012 #define MC_CMD_PHY_CAP_ASYM_WIDTH 1 3013 #define MC_CMD_PHY_CAP_AN_LBN 10 3014 #define MC_CMD_PHY_CAP_AN_WIDTH 1 3015 #define MC_CMD_PHY_CAP_40000FDX_LBN 11 3016 #define MC_CMD_PHY_CAP_40000FDX_WIDTH 1 3017 #define MC_CMD_PHY_CAP_DDM_LBN 12 3018 #define MC_CMD_PHY_CAP_DDM_WIDTH 1 3019 #define MC_CMD_PHY_CAP_100000FDX_LBN 13 3020 #define MC_CMD_PHY_CAP_100000FDX_WIDTH 1 3021 #define MC_CMD_PHY_CAP_25000FDX_LBN 14 3022 #define MC_CMD_PHY_CAP_25000FDX_WIDTH 1 3023 #define MC_CMD_PHY_CAP_50000FDX_LBN 15 3024 #define MC_CMD_PHY_CAP_50000FDX_WIDTH 1 3025 #define MC_CMD_PHY_CAP_BASER_FEC_LBN 16 3026 #define MC_CMD_PHY_CAP_BASER_FEC_WIDTH 1 3027 #define MC_CMD_PHY_CAP_BASER_FEC_REQUESTED_LBN 17 3028 #define MC_CMD_PHY_CAP_BASER_FEC_REQUESTED_WIDTH 1 3029 #define MC_CMD_PHY_CAP_RS_FEC_LBN 18 3030 #define MC_CMD_PHY_CAP_RS_FEC_WIDTH 1 3031 #define MC_CMD_PHY_CAP_RS_FEC_REQUESTED_LBN 19 3032 #define MC_CMD_PHY_CAP_RS_FEC_REQUESTED_WIDTH 1 3033 #define MC_CMD_PHY_CAP_25G_BASER_FEC_LBN 20 3034 #define MC_CMD_PHY_CAP_25G_BASER_FEC_WIDTH 1 3035 #define MC_CMD_PHY_CAP_25G_BASER_FEC_REQUESTED_LBN 21 3036 #define MC_CMD_PHY_CAP_25G_BASER_FEC_REQUESTED_WIDTH 1 3037 /* ?? */ 3038 #define MC_CMD_GET_PHY_CFG_OUT_CHANNEL_OFST 12 3039 #define MC_CMD_GET_PHY_CFG_OUT_CHANNEL_LEN 4 3040 /* ?? */ 3041 #define MC_CMD_GET_PHY_CFG_OUT_PRT_OFST 16 3042 #define MC_CMD_GET_PHY_CFG_OUT_PRT_LEN 4 3043 /* ?? */ 3044 #define MC_CMD_GET_PHY_CFG_OUT_STATS_MASK_OFST 20 3045 #define MC_CMD_GET_PHY_CFG_OUT_STATS_MASK_LEN 4 3046 /* ?? */ 3047 #define MC_CMD_GET_PHY_CFG_OUT_NAME_OFST 24 3048 #define MC_CMD_GET_PHY_CFG_OUT_NAME_LEN 20 3049 /* ?? */ 3050 #define MC_CMD_GET_PHY_CFG_OUT_MEDIA_TYPE_OFST 44 3051 #define MC_CMD_GET_PHY_CFG_OUT_MEDIA_TYPE_LEN 4 3052 /* enum: Xaui. */ 3053 #define MC_CMD_MEDIA_XAUI 0x1 3054 /* enum: CX4. */ 3055 #define MC_CMD_MEDIA_CX4 0x2 3056 /* enum: KX4. */ 3057 #define MC_CMD_MEDIA_KX4 0x3 3058 /* enum: XFP Far. */ 3059 #define MC_CMD_MEDIA_XFP 0x4 3060 /* enum: SFP+. */ 3061 #define MC_CMD_MEDIA_SFP_PLUS 0x5 3062 /* enum: 10GBaseT. */ 3063 #define MC_CMD_MEDIA_BASE_T 0x6 3064 /* enum: QSFP+. */ 3065 #define MC_CMD_MEDIA_QSFP_PLUS 0x7 3066 #define MC_CMD_GET_PHY_CFG_OUT_MMD_MASK_OFST 48 3067 #define MC_CMD_GET_PHY_CFG_OUT_MMD_MASK_LEN 4 3068 /* enum: Native clause 22 */ 3069 #define MC_CMD_MMD_CLAUSE22 0x0 3070 #define MC_CMD_MMD_CLAUSE45_PMAPMD 0x1 /* enum */ 3071 #define MC_CMD_MMD_CLAUSE45_WIS 0x2 /* enum */ 3072 #define MC_CMD_MMD_CLAUSE45_PCS 0x3 /* enum */ 3073 #define MC_CMD_MMD_CLAUSE45_PHYXS 0x4 /* enum */ 3074 #define MC_CMD_MMD_CLAUSE45_DTEXS 0x5 /* enum */ 3075 #define MC_CMD_MMD_CLAUSE45_TC 0x6 /* enum */ 3076 #define MC_CMD_MMD_CLAUSE45_AN 0x7 /* enum */ 3077 /* enum: Clause22 proxied over clause45 by PHY. */ 3078 #define MC_CMD_MMD_CLAUSE45_C22EXT 0x1d 3079 #define MC_CMD_MMD_CLAUSE45_VEND1 0x1e /* enum */ 3080 #define MC_CMD_MMD_CLAUSE45_VEND2 0x1f /* enum */ 3081 #define MC_CMD_GET_PHY_CFG_OUT_REVISION_OFST 52 3082 #define MC_CMD_GET_PHY_CFG_OUT_REVISION_LEN 20 3083 3084 3085 /***********************************/ 3086 /* MC_CMD_START_BIST 3087 * Start a BIST test on the PHY. Locks required: PHY_LOCK if doing a PHY BIST 3088 * Return code: 0, EINVAL, EACCES (if PHY_LOCK is not held) 3089 */ 3090 #define MC_CMD_START_BIST 0x25 3091 #undef MC_CMD_0x25_PRIVILEGE_CTG 3092 3093 #define MC_CMD_0x25_PRIVILEGE_CTG SRIOV_CTG_ADMIN 3094 3095 /* MC_CMD_START_BIST_IN msgrequest */ 3096 #define MC_CMD_START_BIST_IN_LEN 4 3097 /* Type of test. */ 3098 #define MC_CMD_START_BIST_IN_TYPE_OFST 0 3099 #define MC_CMD_START_BIST_IN_TYPE_LEN 4 3100 /* enum: Run the PHY's short cable BIST. */ 3101 #define MC_CMD_PHY_BIST_CABLE_SHORT 0x1 3102 /* enum: Run the PHY's long cable BIST. */ 3103 #define MC_CMD_PHY_BIST_CABLE_LONG 0x2 3104 /* enum: Run BIST on the currently selected BPX Serdes (XAUI or XFI) . */ 3105 #define MC_CMD_BPX_SERDES_BIST 0x3 3106 /* enum: Run the MC loopback tests. */ 3107 #define MC_CMD_MC_LOOPBACK_BIST 0x4 3108 /* enum: Run the PHY's standard BIST. */ 3109 #define MC_CMD_PHY_BIST 0x5 3110 /* enum: Run MC RAM test. */ 3111 #define MC_CMD_MC_MEM_BIST 0x6 3112 /* enum: Run Port RAM test. */ 3113 #define MC_CMD_PORT_MEM_BIST 0x7 3114 /* enum: Run register test. */ 3115 #define MC_CMD_REG_BIST 0x8 3116 3117 /* MC_CMD_START_BIST_OUT msgresponse */ 3118 #define MC_CMD_START_BIST_OUT_LEN 0 3119 3120 3121 /***********************************/ 3122 /* MC_CMD_POLL_BIST 3123 * Poll for BIST completion. Returns a single status code, and optionally some 3124 * PHY specific bist output. The driver should only consume the BIST output 3125 * after validating OUTLEN and MC_CMD_GET_PHY_CFG.TYPE. If a driver can't 3126 * successfully parse the BIST output, it should still respect the pass/Fail in 3127 * OUT.RESULT. Locks required: PHY_LOCK if doing a PHY BIST. Return code: 0, 3128 * EACCES (if PHY_LOCK is not held). 3129 */ 3130 #define MC_CMD_POLL_BIST 0x26 3131 #undef MC_CMD_0x26_PRIVILEGE_CTG 3132 3133 #define MC_CMD_0x26_PRIVILEGE_CTG SRIOV_CTG_ADMIN 3134 3135 /* MC_CMD_POLL_BIST_IN msgrequest */ 3136 #define MC_CMD_POLL_BIST_IN_LEN 0 3137 3138 /* MC_CMD_POLL_BIST_OUT msgresponse */ 3139 #define MC_CMD_POLL_BIST_OUT_LEN 8 3140 /* result */ 3141 #define MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 3142 #define MC_CMD_POLL_BIST_OUT_RESULT_LEN 4 3143 /* enum: Running. */ 3144 #define MC_CMD_POLL_BIST_RUNNING 0x1 3145 /* enum: Passed. */ 3146 #define MC_CMD_POLL_BIST_PASSED 0x2 3147 /* enum: Failed. */ 3148 #define MC_CMD_POLL_BIST_FAILED 0x3 3149 /* enum: Timed-out. */ 3150 #define MC_CMD_POLL_BIST_TIMEOUT 0x4 3151 #define MC_CMD_POLL_BIST_OUT_PRIVATE_OFST 4 3152 #define MC_CMD_POLL_BIST_OUT_PRIVATE_LEN 4 3153 3154 /* MC_CMD_POLL_BIST_OUT_SFT9001 msgresponse */ 3155 #define MC_CMD_POLL_BIST_OUT_SFT9001_LEN 36 3156 /* result */ 3157 /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */ 3158 /* MC_CMD_POLL_BIST_OUT_RESULT_LEN 4 */ 3159 /* Enum values, see field(s): */ 3160 /* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */ 3161 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A_OFST 4 3162 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A_LEN 4 3163 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B_OFST 8 3164 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B_LEN 4 3165 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C_OFST 12 3166 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C_LEN 4 3167 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D_OFST 16 3168 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D_LEN 4 3169 /* Status of each channel A */ 3170 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_A_OFST 20 3171 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_A_LEN 4 3172 /* enum: Ok. */ 3173 #define MC_CMD_POLL_BIST_SFT9001_PAIR_OK 0x1 3174 /* enum: Open. */ 3175 #define MC_CMD_POLL_BIST_SFT9001_PAIR_OPEN 0x2 3176 /* enum: Intra-pair short. */ 3177 #define MC_CMD_POLL_BIST_SFT9001_INTRA_PAIR_SHORT 0x3 3178 /* enum: Inter-pair short. */ 3179 #define MC_CMD_POLL_BIST_SFT9001_INTER_PAIR_SHORT 0x4 3180 /* enum: Busy. */ 3181 #define MC_CMD_POLL_BIST_SFT9001_PAIR_BUSY 0x9 3182 /* Status of each channel B */ 3183 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_B_OFST 24 3184 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_B_LEN 4 3185 /* Enum values, see field(s): */ 3186 /* CABLE_STATUS_A */ 3187 /* Status of each channel C */ 3188 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_C_OFST 28 3189 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_C_LEN 4 3190 /* Enum values, see field(s): */ 3191 /* CABLE_STATUS_A */ 3192 /* Status of each channel D */ 3193 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_D_OFST 32 3194 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_D_LEN 4 3195 /* Enum values, see field(s): */ 3196 /* CABLE_STATUS_A */ 3197 3198 /* MC_CMD_POLL_BIST_OUT_MRSFP msgresponse */ 3199 #define MC_CMD_POLL_BIST_OUT_MRSFP_LEN 8 3200 /* result */ 3201 /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */ 3202 /* MC_CMD_POLL_BIST_OUT_RESULT_LEN 4 */ 3203 /* Enum values, see field(s): */ 3204 /* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */ 3205 #define MC_CMD_POLL_BIST_OUT_MRSFP_TEST_OFST 4 3206 #define MC_CMD_POLL_BIST_OUT_MRSFP_TEST_LEN 4 3207 /* enum: Complete. */ 3208 #define MC_CMD_POLL_BIST_MRSFP_TEST_COMPLETE 0x0 3209 /* enum: Bus switch off I2C write. */ 3210 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_WRITE 0x1 3211 /* enum: Bus switch off I2C no access IO exp. */ 3212 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_IO_EXP 0x2 3213 /* enum: Bus switch off I2C no access module. */ 3214 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_MODULE 0x3 3215 /* enum: IO exp I2C configure. */ 3216 #define MC_CMD_POLL_BIST_MRSFP_TEST_IO_EXP_I2C_CONFIGURE 0x4 3217 /* enum: Bus switch I2C no cross talk. */ 3218 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_I2C_NO_CROSSTALK 0x5 3219 /* enum: Module presence. */ 3220 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_PRESENCE 0x6 3221 /* enum: Module ID I2C access. */ 3222 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_I2C_ACCESS 0x7 3223 /* enum: Module ID sane value. */ 3224 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_SANE_VALUE 0x8 3225 3226 /* MC_CMD_POLL_BIST_OUT_MEM msgresponse */ 3227 #define MC_CMD_POLL_BIST_OUT_MEM_LEN 36 3228 /* result */ 3229 /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */ 3230 /* MC_CMD_POLL_BIST_OUT_RESULT_LEN 4 */ 3231 /* Enum values, see field(s): */ 3232 /* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */ 3233 #define MC_CMD_POLL_BIST_OUT_MEM_TEST_OFST 4 3234 #define MC_CMD_POLL_BIST_OUT_MEM_TEST_LEN 4 3235 /* enum: Test has completed. */ 3236 #define MC_CMD_POLL_BIST_MEM_COMPLETE 0x0 3237 /* enum: RAM test - walk ones. */ 3238 #define MC_CMD_POLL_BIST_MEM_MEM_WALK_ONES 0x1 3239 /* enum: RAM test - walk zeros. */ 3240 #define MC_CMD_POLL_BIST_MEM_MEM_WALK_ZEROS 0x2 3241 /* enum: RAM test - walking inversions zeros/ones. */ 3242 #define MC_CMD_POLL_BIST_MEM_MEM_INV_ZERO_ONE 0x3 3243 /* enum: RAM test - walking inversions checkerboard. */ 3244 #define MC_CMD_POLL_BIST_MEM_MEM_INV_CHKBOARD 0x4 3245 /* enum: Register test - set / clear individual bits. */ 3246 #define MC_CMD_POLL_BIST_MEM_REG 0x5 3247 /* enum: ECC error detected. */ 3248 #define MC_CMD_POLL_BIST_MEM_ECC 0x6 3249 /* Failure address, only valid if result is POLL_BIST_FAILED */ 3250 #define MC_CMD_POLL_BIST_OUT_MEM_ADDR_OFST 8 3251 #define MC_CMD_POLL_BIST_OUT_MEM_ADDR_LEN 4 3252 /* Bus or address space to which the failure address corresponds */ 3253 #define MC_CMD_POLL_BIST_OUT_MEM_BUS_OFST 12 3254 #define MC_CMD_POLL_BIST_OUT_MEM_BUS_LEN 4 3255 /* enum: MC MIPS bus. */ 3256 #define MC_CMD_POLL_BIST_MEM_BUS_MC 0x0 3257 /* enum: CSR IREG bus. */ 3258 #define MC_CMD_POLL_BIST_MEM_BUS_CSR 0x1 3259 /* enum: RX0 DPCPU bus. */ 3260 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_RX 0x2 3261 /* enum: TX0 DPCPU bus. */ 3262 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX0 0x3 3263 /* enum: TX1 DPCPU bus. */ 3264 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX1 0x4 3265 /* enum: RX0 DICPU bus. */ 3266 #define MC_CMD_POLL_BIST_MEM_BUS_DICPU_RX 0x5 3267 /* enum: TX DICPU bus. */ 3268 #define MC_CMD_POLL_BIST_MEM_BUS_DICPU_TX 0x6 3269 /* enum: RX1 DPCPU bus. */ 3270 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_RX1 0x7 3271 /* enum: RX1 DICPU bus. */ 3272 #define MC_CMD_POLL_BIST_MEM_BUS_DICPU_RX1 0x8 3273 /* Pattern written to RAM / register */ 3274 #define MC_CMD_POLL_BIST_OUT_MEM_EXPECT_OFST 16 3275 #define MC_CMD_POLL_BIST_OUT_MEM_EXPECT_LEN 4 3276 /* Actual value read from RAM / register */ 3277 #define MC_CMD_POLL_BIST_OUT_MEM_ACTUAL_OFST 20 3278 #define MC_CMD_POLL_BIST_OUT_MEM_ACTUAL_LEN 4 3279 /* ECC error mask */ 3280 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_OFST 24 3281 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_LEN 4 3282 /* ECC parity error mask */ 3283 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_PARITY_OFST 28 3284 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_PARITY_LEN 4 3285 /* ECC fatal error mask */ 3286 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_FATAL_OFST 32 3287 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_FATAL_LEN 4 3288 3289 3290 /***********************************/ 3291 /* MC_CMD_FLUSH_RX_QUEUES 3292 * Flush receive queue(s). If SRIOV is enabled (via MC_CMD_SRIOV), then RXQ 3293 * flushes should be initiated via this MCDI operation, rather than via 3294 * directly writing FLUSH_CMD. 3295 * 3296 * The flush is completed (either done/fail) asynchronously (after this command 3297 * returns). The driver must still wait for flush done/failure events as usual. 3298 */ 3299 #define MC_CMD_FLUSH_RX_QUEUES 0x27 3300 3301 /* MC_CMD_FLUSH_RX_QUEUES_IN msgrequest */ 3302 #define MC_CMD_FLUSH_RX_QUEUES_IN_LENMIN 4 3303 #define MC_CMD_FLUSH_RX_QUEUES_IN_LENMAX 252 3304 #define MC_CMD_FLUSH_RX_QUEUES_IN_LEN(num) (0+4*(num)) 3305 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_OFST 0 3306 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_LEN 4 3307 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MINNUM 1 3308 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MAXNUM 63 3309 3310 /* MC_CMD_FLUSH_RX_QUEUES_OUT msgresponse */ 3311 #define MC_CMD_FLUSH_RX_QUEUES_OUT_LEN 0 3312 3313 3314 /***********************************/ 3315 /* MC_CMD_GET_LOOPBACK_MODES 3316 * Returns a bitmask of loopback modes available at each speed. 3317 */ 3318 #define MC_CMD_GET_LOOPBACK_MODES 0x28 3319 #undef MC_CMD_0x28_PRIVILEGE_CTG 3320 3321 #define MC_CMD_0x28_PRIVILEGE_CTG SRIOV_CTG_GENERAL 3322 3323 /* MC_CMD_GET_LOOPBACK_MODES_IN msgrequest */ 3324 #define MC_CMD_GET_LOOPBACK_MODES_IN_LEN 0 3325 3326 /* MC_CMD_GET_LOOPBACK_MODES_OUT msgresponse */ 3327 #define MC_CMD_GET_LOOPBACK_MODES_OUT_LEN 40 3328 /* Supported loopbacks. */ 3329 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_OFST 0 3330 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LEN 8 3331 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_OFST 0 3332 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_OFST 4 3333 /* enum: None. */ 3334 #define MC_CMD_LOOPBACK_NONE 0x0 3335 /* enum: Data. */ 3336 #define MC_CMD_LOOPBACK_DATA 0x1 3337 /* enum: GMAC. */ 3338 #define MC_CMD_LOOPBACK_GMAC 0x2 3339 /* enum: XGMII. */ 3340 #define MC_CMD_LOOPBACK_XGMII 0x3 3341 /* enum: XGXS. */ 3342 #define MC_CMD_LOOPBACK_XGXS 0x4 3343 /* enum: XAUI. */ 3344 #define MC_CMD_LOOPBACK_XAUI 0x5 3345 /* enum: GMII. */ 3346 #define MC_CMD_LOOPBACK_GMII 0x6 3347 /* enum: SGMII. */ 3348 #define MC_CMD_LOOPBACK_SGMII 0x7 3349 /* enum: XGBR. */ 3350 #define MC_CMD_LOOPBACK_XGBR 0x8 3351 /* enum: XFI. */ 3352 #define MC_CMD_LOOPBACK_XFI 0x9 3353 /* enum: XAUI Far. */ 3354 #define MC_CMD_LOOPBACK_XAUI_FAR 0xa 3355 /* enum: GMII Far. */ 3356 #define MC_CMD_LOOPBACK_GMII_FAR 0xb 3357 /* enum: SGMII Far. */ 3358 #define MC_CMD_LOOPBACK_SGMII_FAR 0xc 3359 /* enum: XFI Far. */ 3360 #define MC_CMD_LOOPBACK_XFI_FAR 0xd 3361 /* enum: GPhy. */ 3362 #define MC_CMD_LOOPBACK_GPHY 0xe 3363 /* enum: PhyXS. */ 3364 #define MC_CMD_LOOPBACK_PHYXS 0xf 3365 /* enum: PCS. */ 3366 #define MC_CMD_LOOPBACK_PCS 0x10 3367 /* enum: PMA-PMD. */ 3368 #define MC_CMD_LOOPBACK_PMAPMD 0x11 3369 /* enum: Cross-Port. */ 3370 #define MC_CMD_LOOPBACK_XPORT 0x12 3371 /* enum: XGMII-Wireside. */ 3372 #define MC_CMD_LOOPBACK_XGMII_WS 0x13 3373 /* enum: XAUI Wireside. */ 3374 #define MC_CMD_LOOPBACK_XAUI_WS 0x14 3375 /* enum: XAUI Wireside Far. */ 3376 #define MC_CMD_LOOPBACK_XAUI_WS_FAR 0x15 3377 /* enum: XAUI Wireside near. */ 3378 #define MC_CMD_LOOPBACK_XAUI_WS_NEAR 0x16 3379 /* enum: GMII Wireside. */ 3380 #define MC_CMD_LOOPBACK_GMII_WS 0x17 3381 /* enum: XFI Wireside. */ 3382 #define MC_CMD_LOOPBACK_XFI_WS 0x18 3383 /* enum: XFI Wireside Far. */ 3384 #define MC_CMD_LOOPBACK_XFI_WS_FAR 0x19 3385 /* enum: PhyXS Wireside. */ 3386 #define MC_CMD_LOOPBACK_PHYXS_WS 0x1a 3387 /* enum: PMA lanes MAC-Serdes. */ 3388 #define MC_CMD_LOOPBACK_PMA_INT 0x1b 3389 /* enum: KR Serdes Parallel (Encoder). */ 3390 #define MC_CMD_LOOPBACK_SD_NEAR 0x1c 3391 /* enum: KR Serdes Serial. */ 3392 #define MC_CMD_LOOPBACK_SD_FAR 0x1d 3393 /* enum: PMA lanes MAC-Serdes Wireside. */ 3394 #define MC_CMD_LOOPBACK_PMA_INT_WS 0x1e 3395 /* enum: KR Serdes Parallel Wireside (Full PCS). */ 3396 #define MC_CMD_LOOPBACK_SD_FEP2_WS 0x1f 3397 /* enum: KR Serdes Parallel Wireside (Sym Aligner to TX). */ 3398 #define MC_CMD_LOOPBACK_SD_FEP1_5_WS 0x20 3399 /* enum: KR Serdes Parallel Wireside (Deserializer to Serializer). */ 3400 #define MC_CMD_LOOPBACK_SD_FEP_WS 0x21 3401 /* enum: KR Serdes Serial Wireside. */ 3402 #define MC_CMD_LOOPBACK_SD_FES_WS 0x22 3403 /* enum: Near side of AOE Siena side port */ 3404 #define MC_CMD_LOOPBACK_AOE_INT_NEAR 0x23 3405 /* enum: Medford Wireside datapath loopback */ 3406 #define MC_CMD_LOOPBACK_DATA_WS 0x24 3407 /* enum: Force link up without setting up any physical loopback (snapper use 3408 * only) 3409 */ 3410 #define MC_CMD_LOOPBACK_FORCE_EXT_LINK 0x25 3411 /* Supported loopbacks. */ 3412 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_OFST 8 3413 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LEN 8 3414 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LO_OFST 8 3415 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_HI_OFST 12 3416 /* Enum values, see field(s): */ 3417 /* 100M */ 3418 /* Supported loopbacks. */ 3419 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_OFST 16 3420 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LEN 8 3421 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LO_OFST 16 3422 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_HI_OFST 20 3423 /* Enum values, see field(s): */ 3424 /* 100M */ 3425 /* Supported loopbacks. */ 3426 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_OFST 24 3427 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LEN 8 3428 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LO_OFST 24 3429 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_HI_OFST 28 3430 /* Enum values, see field(s): */ 3431 /* 100M */ 3432 /* Supported loopbacks. */ 3433 #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_OFST 32 3434 #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LEN 8 3435 #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LO_OFST 32 3436 #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_HI_OFST 36 3437 /* Enum values, see field(s): */ 3438 /* 100M */ 3439 3440 /* MC_CMD_GET_LOOPBACK_MODES_OUT_V2 msgresponse: Supported loopback modes for 3441 * newer NICs with 25G/50G/100G support 3442 */ 3443 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_LEN 64 3444 /* Supported loopbacks. */ 3445 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_OFST 0 3446 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LEN 8 3447 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LO_OFST 0 3448 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_HI_OFST 4 3449 /* enum: None. */ 3450 /* MC_CMD_LOOPBACK_NONE 0x0 */ 3451 /* enum: Data. */ 3452 /* MC_CMD_LOOPBACK_DATA 0x1 */ 3453 /* enum: GMAC. */ 3454 /* MC_CMD_LOOPBACK_GMAC 0x2 */ 3455 /* enum: XGMII. */ 3456 /* MC_CMD_LOOPBACK_XGMII 0x3 */ 3457 /* enum: XGXS. */ 3458 /* MC_CMD_LOOPBACK_XGXS 0x4 */ 3459 /* enum: XAUI. */ 3460 /* MC_CMD_LOOPBACK_XAUI 0x5 */ 3461 /* enum: GMII. */ 3462 /* MC_CMD_LOOPBACK_GMII 0x6 */ 3463 /* enum: SGMII. */ 3464 /* MC_CMD_LOOPBACK_SGMII 0x7 */ 3465 /* enum: XGBR. */ 3466 /* MC_CMD_LOOPBACK_XGBR 0x8 */ 3467 /* enum: XFI. */ 3468 /* MC_CMD_LOOPBACK_XFI 0x9 */ 3469 /* enum: XAUI Far. */ 3470 /* MC_CMD_LOOPBACK_XAUI_FAR 0xa */ 3471 /* enum: GMII Far. */ 3472 /* MC_CMD_LOOPBACK_GMII_FAR 0xb */ 3473 /* enum: SGMII Far. */ 3474 /* MC_CMD_LOOPBACK_SGMII_FAR 0xc */ 3475 /* enum: XFI Far. */ 3476 /* MC_CMD_LOOPBACK_XFI_FAR 0xd */ 3477 /* enum: GPhy. */ 3478 /* MC_CMD_LOOPBACK_GPHY 0xe */ 3479 /* enum: PhyXS. */ 3480 /* MC_CMD_LOOPBACK_PHYXS 0xf */ 3481 /* enum: PCS. */ 3482 /* MC_CMD_LOOPBACK_PCS 0x10 */ 3483 /* enum: PMA-PMD. */ 3484 /* MC_CMD_LOOPBACK_PMAPMD 0x11 */ 3485 /* enum: Cross-Port. */ 3486 /* MC_CMD_LOOPBACK_XPORT 0x12 */ 3487 /* enum: XGMII-Wireside. */ 3488 /* MC_CMD_LOOPBACK_XGMII_WS 0x13 */ 3489 /* enum: XAUI Wireside. */ 3490 /* MC_CMD_LOOPBACK_XAUI_WS 0x14 */ 3491 /* enum: XAUI Wireside Far. */ 3492 /* MC_CMD_LOOPBACK_XAUI_WS_FAR 0x15 */ 3493 /* enum: XAUI Wireside near. */ 3494 /* MC_CMD_LOOPBACK_XAUI_WS_NEAR 0x16 */ 3495 /* enum: GMII Wireside. */ 3496 /* MC_CMD_LOOPBACK_GMII_WS 0x17 */ 3497 /* enum: XFI Wireside. */ 3498 /* MC_CMD_LOOPBACK_XFI_WS 0x18 */ 3499 /* enum: XFI Wireside Far. */ 3500 /* MC_CMD_LOOPBACK_XFI_WS_FAR 0x19 */ 3501 /* enum: PhyXS Wireside. */ 3502 /* MC_CMD_LOOPBACK_PHYXS_WS 0x1a */ 3503 /* enum: PMA lanes MAC-Serdes. */ 3504 /* MC_CMD_LOOPBACK_PMA_INT 0x1b */ 3505 /* enum: KR Serdes Parallel (Encoder). */ 3506 /* MC_CMD_LOOPBACK_SD_NEAR 0x1c */ 3507 /* enum: KR Serdes Serial. */ 3508 /* MC_CMD_LOOPBACK_SD_FAR 0x1d */ 3509 /* enum: PMA lanes MAC-Serdes Wireside. */ 3510 /* MC_CMD_LOOPBACK_PMA_INT_WS 0x1e */ 3511 /* enum: KR Serdes Parallel Wireside (Full PCS). */ 3512 /* MC_CMD_LOOPBACK_SD_FEP2_WS 0x1f */ 3513 /* enum: KR Serdes Parallel Wireside (Sym Aligner to TX). */ 3514 /* MC_CMD_LOOPBACK_SD_FEP1_5_WS 0x20 */ 3515 /* enum: KR Serdes Parallel Wireside (Deserializer to Serializer). */ 3516 /* MC_CMD_LOOPBACK_SD_FEP_WS 0x21 */ 3517 /* enum: KR Serdes Serial Wireside. */ 3518 /* MC_CMD_LOOPBACK_SD_FES_WS 0x22 */ 3519 /* enum: Near side of AOE Siena side port */ 3520 /* MC_CMD_LOOPBACK_AOE_INT_NEAR 0x23 */ 3521 /* enum: Medford Wireside datapath loopback */ 3522 /* MC_CMD_LOOPBACK_DATA_WS 0x24 */ 3523 /* enum: Force link up without setting up any physical loopback (snapper use 3524 * only) 3525 */ 3526 /* MC_CMD_LOOPBACK_FORCE_EXT_LINK 0x25 */ 3527 /* Supported loopbacks. */ 3528 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_OFST 8 3529 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_LEN 8 3530 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_LO_OFST 8 3531 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_HI_OFST 12 3532 /* Enum values, see field(s): */ 3533 /* 100M */ 3534 /* Supported loopbacks. */ 3535 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_OFST 16 3536 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_LEN 8 3537 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_LO_OFST 16 3538 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_HI_OFST 20 3539 /* Enum values, see field(s): */ 3540 /* 100M */ 3541 /* Supported loopbacks. */ 3542 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_OFST 24 3543 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_LEN 8 3544 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_LO_OFST 24 3545 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_HI_OFST 28 3546 /* Enum values, see field(s): */ 3547 /* 100M */ 3548 /* Supported loopbacks. */ 3549 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_OFST 32 3550 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_LEN 8 3551 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_LO_OFST 32 3552 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_HI_OFST 36 3553 /* Enum values, see field(s): */ 3554 /* 100M */ 3555 /* Supported 25G loopbacks. */ 3556 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_OFST 40 3557 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LEN 8 3558 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LO_OFST 40 3559 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_HI_OFST 44 3560 /* Enum values, see field(s): */ 3561 /* 100M */ 3562 /* Supported 50 loopbacks. */ 3563 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_OFST 48 3564 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LEN 8 3565 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LO_OFST 48 3566 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_HI_OFST 52 3567 /* Enum values, see field(s): */ 3568 /* 100M */ 3569 /* Supported 100G loopbacks. */ 3570 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_OFST 56 3571 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LEN 8 3572 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LO_OFST 56 3573 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_HI_OFST 60 3574 /* Enum values, see field(s): */ 3575 /* 100M */ 3576 3577 3578 /***********************************/ 3579 /* MC_CMD_GET_LINK 3580 * Read the unified MAC/PHY link state. Locks required: None Return code: 0, 3581 * ETIME. 3582 */ 3583 #define MC_CMD_GET_LINK 0x29 3584 #undef MC_CMD_0x29_PRIVILEGE_CTG 3585 3586 #define MC_CMD_0x29_PRIVILEGE_CTG SRIOV_CTG_GENERAL 3587 3588 /* MC_CMD_GET_LINK_IN msgrequest */ 3589 #define MC_CMD_GET_LINK_IN_LEN 0 3590 3591 /* MC_CMD_GET_LINK_OUT msgresponse */ 3592 #define MC_CMD_GET_LINK_OUT_LEN 28 3593 /* near-side advertised capabilities */ 3594 #define MC_CMD_GET_LINK_OUT_CAP_OFST 0 3595 #define MC_CMD_GET_LINK_OUT_CAP_LEN 4 3596 /* link-partner advertised capabilities */ 3597 #define MC_CMD_GET_LINK_OUT_LP_CAP_OFST 4 3598 #define MC_CMD_GET_LINK_OUT_LP_CAP_LEN 4 3599 /* Autonegotiated speed in mbit/s. The link may still be down even if this 3600 * reads non-zero. 3601 */ 3602 #define MC_CMD_GET_LINK_OUT_LINK_SPEED_OFST 8 3603 #define MC_CMD_GET_LINK_OUT_LINK_SPEED_LEN 4 3604 /* Current loopback setting. */ 3605 #define MC_CMD_GET_LINK_OUT_LOOPBACK_MODE_OFST 12 3606 #define MC_CMD_GET_LINK_OUT_LOOPBACK_MODE_LEN 4 3607 /* Enum values, see field(s): */ 3608 /* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */ 3609 #define MC_CMD_GET_LINK_OUT_FLAGS_OFST 16 3610 #define MC_CMD_GET_LINK_OUT_FLAGS_LEN 4 3611 #define MC_CMD_GET_LINK_OUT_LINK_UP_LBN 0 3612 #define MC_CMD_GET_LINK_OUT_LINK_UP_WIDTH 1 3613 #define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_LBN 1 3614 #define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_WIDTH 1 3615 #define MC_CMD_GET_LINK_OUT_BPX_LINK_LBN 2 3616 #define MC_CMD_GET_LINK_OUT_BPX_LINK_WIDTH 1 3617 #define MC_CMD_GET_LINK_OUT_PHY_LINK_LBN 3 3618 #define MC_CMD_GET_LINK_OUT_PHY_LINK_WIDTH 1 3619 #define MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_LBN 6 3620 #define MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_WIDTH 1 3621 #define MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_LBN 7 3622 #define MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_WIDTH 1 3623 /* This returns the negotiated flow control value. */ 3624 #define MC_CMD_GET_LINK_OUT_FCNTL_OFST 20 3625 #define MC_CMD_GET_LINK_OUT_FCNTL_LEN 4 3626 /* Enum values, see field(s): */ 3627 /* MC_CMD_SET_MAC/MC_CMD_SET_MAC_IN/FCNTL */ 3628 #define MC_CMD_GET_LINK_OUT_MAC_FAULT_OFST 24 3629 #define MC_CMD_GET_LINK_OUT_MAC_FAULT_LEN 4 3630 #define MC_CMD_MAC_FAULT_XGMII_LOCAL_LBN 0 3631 #define MC_CMD_MAC_FAULT_XGMII_LOCAL_WIDTH 1 3632 #define MC_CMD_MAC_FAULT_XGMII_REMOTE_LBN 1 3633 #define MC_CMD_MAC_FAULT_XGMII_REMOTE_WIDTH 1 3634 #define MC_CMD_MAC_FAULT_SGMII_REMOTE_LBN 2 3635 #define MC_CMD_MAC_FAULT_SGMII_REMOTE_WIDTH 1 3636 #define MC_CMD_MAC_FAULT_PENDING_RECONFIG_LBN 3 3637 #define MC_CMD_MAC_FAULT_PENDING_RECONFIG_WIDTH 1 3638 3639 3640 /***********************************/ 3641 /* MC_CMD_SET_LINK 3642 * Write the unified MAC/PHY link configuration. Locks required: None. Return 3643 * code: 0, EINVAL, ETIME 3644 */ 3645 #define MC_CMD_SET_LINK 0x2a 3646 #undef MC_CMD_0x2a_PRIVILEGE_CTG 3647 3648 #define MC_CMD_0x2a_PRIVILEGE_CTG SRIOV_CTG_LINK 3649 3650 /* MC_CMD_SET_LINK_IN msgrequest */ 3651 #define MC_CMD_SET_LINK_IN_LEN 16 3652 /* ??? */ 3653 #define MC_CMD_SET_LINK_IN_CAP_OFST 0 3654 #define MC_CMD_SET_LINK_IN_CAP_LEN 4 3655 /* Flags */ 3656 #define MC_CMD_SET_LINK_IN_FLAGS_OFST 4 3657 #define MC_CMD_SET_LINK_IN_FLAGS_LEN 4 3658 #define MC_CMD_SET_LINK_IN_LOWPOWER_LBN 0 3659 #define MC_CMD_SET_LINK_IN_LOWPOWER_WIDTH 1 3660 #define MC_CMD_SET_LINK_IN_POWEROFF_LBN 1 3661 #define MC_CMD_SET_LINK_IN_POWEROFF_WIDTH 1 3662 #define MC_CMD_SET_LINK_IN_TXDIS_LBN 2 3663 #define MC_CMD_SET_LINK_IN_TXDIS_WIDTH 1 3664 /* Loopback mode. */ 3665 #define MC_CMD_SET_LINK_IN_LOOPBACK_MODE_OFST 8 3666 #define MC_CMD_SET_LINK_IN_LOOPBACK_MODE_LEN 4 3667 /* Enum values, see field(s): */ 3668 /* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */ 3669 /* A loopback speed of "0" is supported, and means (choose any available 3670 * speed). 3671 */ 3672 #define MC_CMD_SET_LINK_IN_LOOPBACK_SPEED_OFST 12 3673 #define MC_CMD_SET_LINK_IN_LOOPBACK_SPEED_LEN 4 3674 3675 /* MC_CMD_SET_LINK_OUT msgresponse */ 3676 #define MC_CMD_SET_LINK_OUT_LEN 0 3677 3678 3679 /***********************************/ 3680 /* MC_CMD_SET_ID_LED 3681 * Set identification LED state. Locks required: None. Return code: 0, EINVAL 3682 */ 3683 #define MC_CMD_SET_ID_LED 0x2b 3684 #undef MC_CMD_0x2b_PRIVILEGE_CTG 3685 3686 #define MC_CMD_0x2b_PRIVILEGE_CTG SRIOV_CTG_LINK 3687 3688 /* MC_CMD_SET_ID_LED_IN msgrequest */ 3689 #define MC_CMD_SET_ID_LED_IN_LEN 4 3690 /* Set LED state. */ 3691 #define MC_CMD_SET_ID_LED_IN_STATE_OFST 0 3692 #define MC_CMD_SET_ID_LED_IN_STATE_LEN 4 3693 #define MC_CMD_LED_OFF 0x0 /* enum */ 3694 #define MC_CMD_LED_ON 0x1 /* enum */ 3695 #define MC_CMD_LED_DEFAULT 0x2 /* enum */ 3696 3697 /* MC_CMD_SET_ID_LED_OUT msgresponse */ 3698 #define MC_CMD_SET_ID_LED_OUT_LEN 0 3699 3700 3701 /***********************************/ 3702 /* MC_CMD_SET_MAC 3703 * Set MAC configuration. Locks required: None. Return code: 0, EINVAL 3704 */ 3705 #define MC_CMD_SET_MAC 0x2c 3706 #undef MC_CMD_0x2c_PRIVILEGE_CTG 3707 3708 #define MC_CMD_0x2c_PRIVILEGE_CTG SRIOV_CTG_GENERAL 3709 3710 /* MC_CMD_SET_MAC_IN msgrequest */ 3711 #define MC_CMD_SET_MAC_IN_LEN 28 3712 /* The MTU is the MTU programmed directly into the XMAC/GMAC (inclusive of 3713 * EtherII, VLAN, bug16011 padding). 3714 */ 3715 #define MC_CMD_SET_MAC_IN_MTU_OFST 0 3716 #define MC_CMD_SET_MAC_IN_MTU_LEN 4 3717 #define MC_CMD_SET_MAC_IN_DRAIN_OFST 4 3718 #define MC_CMD_SET_MAC_IN_DRAIN_LEN 4 3719 #define MC_CMD_SET_MAC_IN_ADDR_OFST 8 3720 #define MC_CMD_SET_MAC_IN_ADDR_LEN 8 3721 #define MC_CMD_SET_MAC_IN_ADDR_LO_OFST 8 3722 #define MC_CMD_SET_MAC_IN_ADDR_HI_OFST 12 3723 #define MC_CMD_SET_MAC_IN_REJECT_OFST 16 3724 #define MC_CMD_SET_MAC_IN_REJECT_LEN 4 3725 #define MC_CMD_SET_MAC_IN_REJECT_UNCST_LBN 0 3726 #define MC_CMD_SET_MAC_IN_REJECT_UNCST_WIDTH 1 3727 #define MC_CMD_SET_MAC_IN_REJECT_BRDCST_LBN 1 3728 #define MC_CMD_SET_MAC_IN_REJECT_BRDCST_WIDTH 1 3729 #define MC_CMD_SET_MAC_IN_FCNTL_OFST 20 3730 #define MC_CMD_SET_MAC_IN_FCNTL_LEN 4 3731 /* enum: Flow control is off. */ 3732 #define MC_CMD_FCNTL_OFF 0x0 3733 /* enum: Respond to flow control. */ 3734 #define MC_CMD_FCNTL_RESPOND 0x1 3735 /* enum: Respond to and Issue flow control. */ 3736 #define MC_CMD_FCNTL_BIDIR 0x2 3737 /* enum: Auto neg flow control. */ 3738 #define MC_CMD_FCNTL_AUTO 0x3 3739 /* enum: Priority flow control (eftest builds only). */ 3740 #define MC_CMD_FCNTL_QBB 0x4 3741 /* enum: Issue flow control. */ 3742 #define MC_CMD_FCNTL_GENERATE 0x5 3743 #define MC_CMD_SET_MAC_IN_FLAGS_OFST 24 3744 #define MC_CMD_SET_MAC_IN_FLAGS_LEN 4 3745 #define MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_LBN 0 3746 #define MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_WIDTH 1 3747 3748 /* MC_CMD_SET_MAC_EXT_IN msgrequest */ 3749 #define MC_CMD_SET_MAC_EXT_IN_LEN 32 3750 /* The MTU is the MTU programmed directly into the XMAC/GMAC (inclusive of 3751 * EtherII, VLAN, bug16011 padding). 3752 */ 3753 #define MC_CMD_SET_MAC_EXT_IN_MTU_OFST 0 3754 #define MC_CMD_SET_MAC_EXT_IN_MTU_LEN 4 3755 #define MC_CMD_SET_MAC_EXT_IN_DRAIN_OFST 4 3756 #define MC_CMD_SET_MAC_EXT_IN_DRAIN_LEN 4 3757 #define MC_CMD_SET_MAC_EXT_IN_ADDR_OFST 8 3758 #define MC_CMD_SET_MAC_EXT_IN_ADDR_LEN 8 3759 #define MC_CMD_SET_MAC_EXT_IN_ADDR_LO_OFST 8 3760 #define MC_CMD_SET_MAC_EXT_IN_ADDR_HI_OFST 12 3761 #define MC_CMD_SET_MAC_EXT_IN_REJECT_OFST 16 3762 #define MC_CMD_SET_MAC_EXT_IN_REJECT_LEN 4 3763 #define MC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_LBN 0 3764 #define MC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_WIDTH 1 3765 #define MC_CMD_SET_MAC_EXT_IN_REJECT_BRDCST_LBN 1 3766 #define MC_CMD_SET_MAC_EXT_IN_REJECT_BRDCST_WIDTH 1 3767 #define MC_CMD_SET_MAC_EXT_IN_FCNTL_OFST 20 3768 #define MC_CMD_SET_MAC_EXT_IN_FCNTL_LEN 4 3769 /* enum: Flow control is off. */ 3770 /* MC_CMD_FCNTL_OFF 0x0 */ 3771 /* enum: Respond to flow control. */ 3772 /* MC_CMD_FCNTL_RESPOND 0x1 */ 3773 /* enum: Respond to and Issue flow control. */ 3774 /* MC_CMD_FCNTL_BIDIR 0x2 */ 3775 /* enum: Auto neg flow control. */ 3776 /* MC_CMD_FCNTL_AUTO 0x3 */ 3777 /* enum: Priority flow control (eftest builds only). */ 3778 /* MC_CMD_FCNTL_QBB 0x4 */ 3779 /* enum: Issue flow control. */ 3780 /* MC_CMD_FCNTL_GENERATE 0x5 */ 3781 #define MC_CMD_SET_MAC_EXT_IN_FLAGS_OFST 24 3782 #define MC_CMD_SET_MAC_EXT_IN_FLAGS_LEN 4 3783 #define MC_CMD_SET_MAC_EXT_IN_FLAG_INCLUDE_FCS_LBN 0 3784 #define MC_CMD_SET_MAC_EXT_IN_FLAG_INCLUDE_FCS_WIDTH 1 3785 /* Select which parameters to configure. A parameter will only be modified if 3786 * the corresponding control flag is set. If SET_MAC_ENHANCED is not set in 3787 * capabilities then this field is ignored (and all flags are assumed to be 3788 * set). 3789 */ 3790 #define MC_CMD_SET_MAC_EXT_IN_CONTROL_OFST 28 3791 #define MC_CMD_SET_MAC_EXT_IN_CONTROL_LEN 4 3792 #define MC_CMD_SET_MAC_EXT_IN_CFG_MTU_LBN 0 3793 #define MC_CMD_SET_MAC_EXT_IN_CFG_MTU_WIDTH 1 3794 #define MC_CMD_SET_MAC_EXT_IN_CFG_DRAIN_LBN 1 3795 #define MC_CMD_SET_MAC_EXT_IN_CFG_DRAIN_WIDTH 1 3796 #define MC_CMD_SET_MAC_EXT_IN_CFG_REJECT_LBN 2 3797 #define MC_CMD_SET_MAC_EXT_IN_CFG_REJECT_WIDTH 1 3798 #define MC_CMD_SET_MAC_EXT_IN_CFG_FCNTL_LBN 3 3799 #define MC_CMD_SET_MAC_EXT_IN_CFG_FCNTL_WIDTH 1 3800 #define MC_CMD_SET_MAC_EXT_IN_CFG_FCS_LBN 4 3801 #define MC_CMD_SET_MAC_EXT_IN_CFG_FCS_WIDTH 1 3802 3803 /* MC_CMD_SET_MAC_OUT msgresponse */ 3804 #define MC_CMD_SET_MAC_OUT_LEN 0 3805 3806 /* MC_CMD_SET_MAC_V2_OUT msgresponse */ 3807 #define MC_CMD_SET_MAC_V2_OUT_LEN 4 3808 /* MTU as configured after processing the request. See comment at 3809 * MC_CMD_SET_MAC_IN/MTU. To query MTU without doing any changes, set CONTROL 3810 * to 0. 3811 */ 3812 #define MC_CMD_SET_MAC_V2_OUT_MTU_OFST 0 3813 #define MC_CMD_SET_MAC_V2_OUT_MTU_LEN 4 3814 3815 3816 /***********************************/ 3817 /* MC_CMD_PHY_STATS 3818 * Get generic PHY statistics. This call returns the statistics for a generic 3819 * PHY in a sparse array (indexed by the enumerate). Each value is represented 3820 * by a 32bit number. If the DMA_ADDR is 0, then no DMA is performed, and the 3821 * statistics may be read from the message response. If DMA_ADDR != 0, then the 3822 * statistics are dmad to that (page-aligned location). Locks required: None. 3823 * Returns: 0, ETIME 3824 */ 3825 #define MC_CMD_PHY_STATS 0x2d 3826 #undef MC_CMD_0x2d_PRIVILEGE_CTG 3827 3828 #define MC_CMD_0x2d_PRIVILEGE_CTG SRIOV_CTG_LINK 3829 3830 /* MC_CMD_PHY_STATS_IN msgrequest */ 3831 #define MC_CMD_PHY_STATS_IN_LEN 8 3832 /* ??? */ 3833 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_OFST 0 3834 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_LEN 8 3835 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_OFST 0 3836 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_HI_OFST 4 3837 3838 /* MC_CMD_PHY_STATS_OUT_DMA msgresponse */ 3839 #define MC_CMD_PHY_STATS_OUT_DMA_LEN 0 3840 3841 /* MC_CMD_PHY_STATS_OUT_NO_DMA msgresponse */ 3842 #define MC_CMD_PHY_STATS_OUT_NO_DMA_LEN (((MC_CMD_PHY_NSTATS*32))>>3) 3843 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_OFST 0 3844 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_LEN 4 3845 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_PHY_NSTATS 3846 /* enum: OUI. */ 3847 #define MC_CMD_OUI 0x0 3848 /* enum: PMA-PMD Link Up. */ 3849 #define MC_CMD_PMA_PMD_LINK_UP 0x1 3850 /* enum: PMA-PMD RX Fault. */ 3851 #define MC_CMD_PMA_PMD_RX_FAULT 0x2 3852 /* enum: PMA-PMD TX Fault. */ 3853 #define MC_CMD_PMA_PMD_TX_FAULT 0x3 3854 /* enum: PMA-PMD Signal */ 3855 #define MC_CMD_PMA_PMD_SIGNAL 0x4 3856 /* enum: PMA-PMD SNR A. */ 3857 #define MC_CMD_PMA_PMD_SNR_A 0x5 3858 /* enum: PMA-PMD SNR B. */ 3859 #define MC_CMD_PMA_PMD_SNR_B 0x6 3860 /* enum: PMA-PMD SNR C. */ 3861 #define MC_CMD_PMA_PMD_SNR_C 0x7 3862 /* enum: PMA-PMD SNR D. */ 3863 #define MC_CMD_PMA_PMD_SNR_D 0x8 3864 /* enum: PCS Link Up. */ 3865 #define MC_CMD_PCS_LINK_UP 0x9 3866 /* enum: PCS RX Fault. */ 3867 #define MC_CMD_PCS_RX_FAULT 0xa 3868 /* enum: PCS TX Fault. */ 3869 #define MC_CMD_PCS_TX_FAULT 0xb 3870 /* enum: PCS BER. */ 3871 #define MC_CMD_PCS_BER 0xc 3872 /* enum: PCS Block Errors. */ 3873 #define MC_CMD_PCS_BLOCK_ERRORS 0xd 3874 /* enum: PhyXS Link Up. */ 3875 #define MC_CMD_PHYXS_LINK_UP 0xe 3876 /* enum: PhyXS RX Fault. */ 3877 #define MC_CMD_PHYXS_RX_FAULT 0xf 3878 /* enum: PhyXS TX Fault. */ 3879 #define MC_CMD_PHYXS_TX_FAULT 0x10 3880 /* enum: PhyXS Align. */ 3881 #define MC_CMD_PHYXS_ALIGN 0x11 3882 /* enum: PhyXS Sync. */ 3883 #define MC_CMD_PHYXS_SYNC 0x12 3884 /* enum: AN link-up. */ 3885 #define MC_CMD_AN_LINK_UP 0x13 3886 /* enum: AN Complete. */ 3887 #define MC_CMD_AN_COMPLETE 0x14 3888 /* enum: AN 10GBaseT Status. */ 3889 #define MC_CMD_AN_10GBT_STATUS 0x15 3890 /* enum: Clause 22 Link-Up. */ 3891 #define MC_CMD_CL22_LINK_UP 0x16 3892 /* enum: (Last entry) */ 3893 #define MC_CMD_PHY_NSTATS 0x17 3894 3895 3896 /***********************************/ 3897 /* MC_CMD_MAC_STATS 3898 * Get generic MAC statistics. This call returns unified statistics maintained 3899 * by the MC as it switches between the GMAC and XMAC. The MC will write out 3900 * all supported stats. The driver should zero initialise the buffer to 3901 * guarantee consistent results. If the DMA_ADDR is 0, then no DMA is 3902 * performed, and the statistics may be read from the message response. If 3903 * DMA_ADDR != 0, then the statistics are dmad to that (page-aligned location). 3904 * Locks required: None. The PERIODIC_CLEAR option is not used and now has no 3905 * effect. Returns: 0, ETIME 3906 */ 3907 #define MC_CMD_MAC_STATS 0x2e 3908 #undef MC_CMD_0x2e_PRIVILEGE_CTG 3909 3910 #define MC_CMD_0x2e_PRIVILEGE_CTG SRIOV_CTG_GENERAL 3911 3912 /* MC_CMD_MAC_STATS_IN msgrequest */ 3913 #define MC_CMD_MAC_STATS_IN_LEN 20 3914 /* ??? */ 3915 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_OFST 0 3916 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_LEN 8 3917 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_OFST 0 3918 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_OFST 4 3919 #define MC_CMD_MAC_STATS_IN_CMD_OFST 8 3920 #define MC_CMD_MAC_STATS_IN_CMD_LEN 4 3921 #define MC_CMD_MAC_STATS_IN_DMA_LBN 0 3922 #define MC_CMD_MAC_STATS_IN_DMA_WIDTH 1 3923 #define MC_CMD_MAC_STATS_IN_CLEAR_LBN 1 3924 #define MC_CMD_MAC_STATS_IN_CLEAR_WIDTH 1 3925 #define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_LBN 2 3926 #define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_WIDTH 1 3927 #define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_LBN 3 3928 #define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_WIDTH 1 3929 #define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_LBN 4 3930 #define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_WIDTH 1 3931 #define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_LBN 5 3932 #define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_WIDTH 1 3933 #define MC_CMD_MAC_STATS_IN_PERIOD_MS_LBN 16 3934 #define MC_CMD_MAC_STATS_IN_PERIOD_MS_WIDTH 16 3935 /* DMA length. Should be set to MAC_STATS_NUM_STATS * sizeof(uint64_t), as 3936 * returned by MC_CMD_GET_CAPABILITIES_V4_OUT. For legacy firmware not 3937 * supporting MC_CMD_GET_CAPABILITIES_V4_OUT, DMA_LEN should be set to 3938 * MC_CMD_MAC_NSTATS * sizeof(uint64_t) 3939 */ 3940 #define MC_CMD_MAC_STATS_IN_DMA_LEN_OFST 12 3941 #define MC_CMD_MAC_STATS_IN_DMA_LEN_LEN 4 3942 /* port id so vadapter stats can be provided */ 3943 #define MC_CMD_MAC_STATS_IN_PORT_ID_OFST 16 3944 #define MC_CMD_MAC_STATS_IN_PORT_ID_LEN 4 3945 3946 /* MC_CMD_MAC_STATS_OUT_DMA msgresponse */ 3947 #define MC_CMD_MAC_STATS_OUT_DMA_LEN 0 3948 3949 /* MC_CMD_MAC_STATS_OUT_NO_DMA msgresponse */ 3950 #define MC_CMD_MAC_STATS_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS*64))>>3) 3951 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_OFST 0 3952 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LEN 8 3953 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_OFST 0 3954 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_OFST 4 3955 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS 3956 #define MC_CMD_MAC_GENERATION_START 0x0 /* enum */ 3957 #define MC_CMD_MAC_DMABUF_START 0x1 /* enum */ 3958 #define MC_CMD_MAC_TX_PKTS 0x1 /* enum */ 3959 #define MC_CMD_MAC_TX_PAUSE_PKTS 0x2 /* enum */ 3960 #define MC_CMD_MAC_TX_CONTROL_PKTS 0x3 /* enum */ 3961 #define MC_CMD_MAC_TX_UNICAST_PKTS 0x4 /* enum */ 3962 #define MC_CMD_MAC_TX_MULTICAST_PKTS 0x5 /* enum */ 3963 #define MC_CMD_MAC_TX_BROADCAST_PKTS 0x6 /* enum */ 3964 #define MC_CMD_MAC_TX_BYTES 0x7 /* enum */ 3965 #define MC_CMD_MAC_TX_BAD_BYTES 0x8 /* enum */ 3966 #define MC_CMD_MAC_TX_LT64_PKTS 0x9 /* enum */ 3967 #define MC_CMD_MAC_TX_64_PKTS 0xa /* enum */ 3968 #define MC_CMD_MAC_TX_65_TO_127_PKTS 0xb /* enum */ 3969 #define MC_CMD_MAC_TX_128_TO_255_PKTS 0xc /* enum */ 3970 #define MC_CMD_MAC_TX_256_TO_511_PKTS 0xd /* enum */ 3971 #define MC_CMD_MAC_TX_512_TO_1023_PKTS 0xe /* enum */ 3972 #define MC_CMD_MAC_TX_1024_TO_15XX_PKTS 0xf /* enum */ 3973 #define MC_CMD_MAC_TX_15XX_TO_JUMBO_PKTS 0x10 /* enum */ 3974 #define MC_CMD_MAC_TX_GTJUMBO_PKTS 0x11 /* enum */ 3975 #define MC_CMD_MAC_TX_BAD_FCS_PKTS 0x12 /* enum */ 3976 #define MC_CMD_MAC_TX_SINGLE_COLLISION_PKTS 0x13 /* enum */ 3977 #define MC_CMD_MAC_TX_MULTIPLE_COLLISION_PKTS 0x14 /* enum */ 3978 #define MC_CMD_MAC_TX_EXCESSIVE_COLLISION_PKTS 0x15 /* enum */ 3979 #define MC_CMD_MAC_TX_LATE_COLLISION_PKTS 0x16 /* enum */ 3980 #define MC_CMD_MAC_TX_DEFERRED_PKTS 0x17 /* enum */ 3981 #define MC_CMD_MAC_TX_EXCESSIVE_DEFERRED_PKTS 0x18 /* enum */ 3982 #define MC_CMD_MAC_TX_NON_TCPUDP_PKTS 0x19 /* enum */ 3983 #define MC_CMD_MAC_TX_MAC_SRC_ERR_PKTS 0x1a /* enum */ 3984 #define MC_CMD_MAC_TX_IP_SRC_ERR_PKTS 0x1b /* enum */ 3985 #define MC_CMD_MAC_RX_PKTS 0x1c /* enum */ 3986 #define MC_CMD_MAC_RX_PAUSE_PKTS 0x1d /* enum */ 3987 #define MC_CMD_MAC_RX_GOOD_PKTS 0x1e /* enum */ 3988 #define MC_CMD_MAC_RX_CONTROL_PKTS 0x1f /* enum */ 3989 #define MC_CMD_MAC_RX_UNICAST_PKTS 0x20 /* enum */ 3990 #define MC_CMD_MAC_RX_MULTICAST_PKTS 0x21 /* enum */ 3991 #define MC_CMD_MAC_RX_BROADCAST_PKTS 0x22 /* enum */ 3992 #define MC_CMD_MAC_RX_BYTES 0x23 /* enum */ 3993 #define MC_CMD_MAC_RX_BAD_BYTES 0x24 /* enum */ 3994 #define MC_CMD_MAC_RX_64_PKTS 0x25 /* enum */ 3995 #define MC_CMD_MAC_RX_65_TO_127_PKTS 0x26 /* enum */ 3996 #define MC_CMD_MAC_RX_128_TO_255_PKTS 0x27 /* enum */ 3997 #define MC_CMD_MAC_RX_256_TO_511_PKTS 0x28 /* enum */ 3998 #define MC_CMD_MAC_RX_512_TO_1023_PKTS 0x29 /* enum */ 3999 #define MC_CMD_MAC_RX_1024_TO_15XX_PKTS 0x2a /* enum */ 4000 #define MC_CMD_MAC_RX_15XX_TO_JUMBO_PKTS 0x2b /* enum */ 4001 #define MC_CMD_MAC_RX_GTJUMBO_PKTS 0x2c /* enum */ 4002 #define MC_CMD_MAC_RX_UNDERSIZE_PKTS 0x2d /* enum */ 4003 #define MC_CMD_MAC_RX_BAD_FCS_PKTS 0x2e /* enum */ 4004 #define MC_CMD_MAC_RX_OVERFLOW_PKTS 0x2f /* enum */ 4005 #define MC_CMD_MAC_RX_FALSE_CARRIER_PKTS 0x30 /* enum */ 4006 #define MC_CMD_MAC_RX_SYMBOL_ERROR_PKTS 0x31 /* enum */ 4007 #define MC_CMD_MAC_RX_ALIGN_ERROR_PKTS 0x32 /* enum */ 4008 #define MC_CMD_MAC_RX_LENGTH_ERROR_PKTS 0x33 /* enum */ 4009 #define MC_CMD_MAC_RX_INTERNAL_ERROR_PKTS 0x34 /* enum */ 4010 #define MC_CMD_MAC_RX_JABBER_PKTS 0x35 /* enum */ 4011 #define MC_CMD_MAC_RX_NODESC_DROPS 0x36 /* enum */ 4012 #define MC_CMD_MAC_RX_LANES01_CHAR_ERR 0x37 /* enum */ 4013 #define MC_CMD_MAC_RX_LANES23_CHAR_ERR 0x38 /* enum */ 4014 #define MC_CMD_MAC_RX_LANES01_DISP_ERR 0x39 /* enum */ 4015 #define MC_CMD_MAC_RX_LANES23_DISP_ERR 0x3a /* enum */ 4016 #define MC_CMD_MAC_RX_MATCH_FAULT 0x3b /* enum */ 4017 /* enum: PM trunc_bb_overflow counter. Valid for EF10 with PM_AND_RXDP_COUNTERS 4018 * capability only. 4019 */ 4020 #define MC_CMD_MAC_PM_TRUNC_BB_OVERFLOW 0x3c 4021 /* enum: PM discard_bb_overflow counter. Valid for EF10 with 4022 * PM_AND_RXDP_COUNTERS capability only. 4023 */ 4024 #define MC_CMD_MAC_PM_DISCARD_BB_OVERFLOW 0x3d 4025 /* enum: PM trunc_vfifo_full counter. Valid for EF10 with PM_AND_RXDP_COUNTERS 4026 * capability only. 4027 */ 4028 #define MC_CMD_MAC_PM_TRUNC_VFIFO_FULL 0x3e 4029 /* enum: PM discard_vfifo_full counter. Valid for EF10 with 4030 * PM_AND_RXDP_COUNTERS capability only. 4031 */ 4032 #define MC_CMD_MAC_PM_DISCARD_VFIFO_FULL 0x3f 4033 /* enum: PM trunc_qbb counter. Valid for EF10 with PM_AND_RXDP_COUNTERS 4034 * capability only. 4035 */ 4036 #define MC_CMD_MAC_PM_TRUNC_QBB 0x40 4037 /* enum: PM discard_qbb counter. Valid for EF10 with PM_AND_RXDP_COUNTERS 4038 * capability only. 4039 */ 4040 #define MC_CMD_MAC_PM_DISCARD_QBB 0x41 4041 /* enum: PM discard_mapping counter. Valid for EF10 with PM_AND_RXDP_COUNTERS 4042 * capability only. 4043 */ 4044 #define MC_CMD_MAC_PM_DISCARD_MAPPING 0x42 4045 /* enum: RXDP counter: Number of packets dropped due to the queue being 4046 * disabled. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only. 4047 */ 4048 #define MC_CMD_MAC_RXDP_Q_DISABLED_PKTS 0x43 4049 /* enum: RXDP counter: Number of packets dropped by the DICPU. Valid for EF10 4050 * with PM_AND_RXDP_COUNTERS capability only. 4051 */ 4052 #define MC_CMD_MAC_RXDP_DI_DROPPED_PKTS 0x45 4053 /* enum: RXDP counter: Number of non-host packets. Valid for EF10 with 4054 * PM_AND_RXDP_COUNTERS capability only. 4055 */ 4056 #define MC_CMD_MAC_RXDP_STREAMING_PKTS 0x46 4057 /* enum: RXDP counter: Number of times an hlb descriptor fetch was performed. 4058 * Valid for EF10 with PM_AND_RXDP_COUNTERS capability only. 4059 */ 4060 #define MC_CMD_MAC_RXDP_HLB_FETCH_CONDITIONS 0x47 4061 /* enum: RXDP counter: Number of times the DPCPU waited for an existing 4062 * descriptor fetch. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only. 4063 */ 4064 #define MC_CMD_MAC_RXDP_HLB_WAIT_CONDITIONS 0x48 4065 #define MC_CMD_MAC_VADAPTER_RX_DMABUF_START 0x4c /* enum */ 4066 #define MC_CMD_MAC_VADAPTER_RX_UNICAST_PACKETS 0x4c /* enum */ 4067 #define MC_CMD_MAC_VADAPTER_RX_UNICAST_BYTES 0x4d /* enum */ 4068 #define MC_CMD_MAC_VADAPTER_RX_MULTICAST_PACKETS 0x4e /* enum */ 4069 #define MC_CMD_MAC_VADAPTER_RX_MULTICAST_BYTES 0x4f /* enum */ 4070 #define MC_CMD_MAC_VADAPTER_RX_BROADCAST_PACKETS 0x50 /* enum */ 4071 #define MC_CMD_MAC_VADAPTER_RX_BROADCAST_BYTES 0x51 /* enum */ 4072 #define MC_CMD_MAC_VADAPTER_RX_BAD_PACKETS 0x52 /* enum */ 4073 #define MC_CMD_MAC_VADAPTER_RX_BAD_BYTES 0x53 /* enum */ 4074 #define MC_CMD_MAC_VADAPTER_RX_OVERFLOW 0x54 /* enum */ 4075 #define MC_CMD_MAC_VADAPTER_TX_DMABUF_START 0x57 /* enum */ 4076 #define MC_CMD_MAC_VADAPTER_TX_UNICAST_PACKETS 0x57 /* enum */ 4077 #define MC_CMD_MAC_VADAPTER_TX_UNICAST_BYTES 0x58 /* enum */ 4078 #define MC_CMD_MAC_VADAPTER_TX_MULTICAST_PACKETS 0x59 /* enum */ 4079 #define MC_CMD_MAC_VADAPTER_TX_MULTICAST_BYTES 0x5a /* enum */ 4080 #define MC_CMD_MAC_VADAPTER_TX_BROADCAST_PACKETS 0x5b /* enum */ 4081 #define MC_CMD_MAC_VADAPTER_TX_BROADCAST_BYTES 0x5c /* enum */ 4082 #define MC_CMD_MAC_VADAPTER_TX_BAD_PACKETS 0x5d /* enum */ 4083 #define MC_CMD_MAC_VADAPTER_TX_BAD_BYTES 0x5e /* enum */ 4084 #define MC_CMD_MAC_VADAPTER_TX_OVERFLOW 0x5f /* enum */ 4085 /* enum: Start of GMAC stats buffer space, for Siena only. */ 4086 #define MC_CMD_GMAC_DMABUF_START 0x40 4087 /* enum: End of GMAC stats buffer space, for Siena only. */ 4088 #define MC_CMD_GMAC_DMABUF_END 0x5f 4089 /* enum: GENERATION_END value, used together with GENERATION_START to verify 4090 * consistency of DMAd data. For legacy firmware / drivers without extended 4091 * stats (more precisely, when DMA_LEN == MC_CMD_MAC_NSTATS * 4092 * sizeof(uint64_t)), this entry holds the GENERATION_END value. Otherwise, 4093 * this value is invalid/ reserved and GENERATION_END is written as the last 4094 * 64-bit word of the DMA buffer (at DMA_LEN - sizeof(uint64_t)). Note that 4095 * this is consistent with the legacy behaviour, in the sense that entry 96 is 4096 * the last 64-bit word in the buffer when DMA_LEN == MC_CMD_MAC_NSTATS * 4097 * sizeof(uint64_t). See SF-109306-TC, Section 9.2 for details. 4098 */ 4099 #define MC_CMD_MAC_GENERATION_END 0x60 4100 #define MC_CMD_MAC_NSTATS 0x61 /* enum */ 4101 4102 /* MC_CMD_MAC_STATS_V2_OUT_DMA msgresponse */ 4103 #define MC_CMD_MAC_STATS_V2_OUT_DMA_LEN 0 4104 4105 /* MC_CMD_MAC_STATS_V2_OUT_NO_DMA msgresponse */ 4106 #define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS_V2*64))>>3) 4107 #define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_OFST 0 4108 #define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LEN 8 4109 #define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LO_OFST 0 4110 #define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_HI_OFST 4 4111 #define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS_V2 4112 /* enum: Start of FEC stats buffer space, Medford2 and up */ 4113 #define MC_CMD_MAC_FEC_DMABUF_START 0x61 4114 /* enum: Number of uncorrected FEC codewords on link (RS-FEC only for Medford2) 4115 */ 4116 #define MC_CMD_MAC_FEC_UNCORRECTED_ERRORS 0x61 4117 /* enum: Number of corrected FEC codewords on link (RS-FEC only for Medford2) 4118 */ 4119 #define MC_CMD_MAC_FEC_CORRECTED_ERRORS 0x62 4120 /* enum: Number of corrected 10-bit symbol errors, lane 0 (RS-FEC only) */ 4121 #define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE0 0x63 4122 /* enum: Number of corrected 10-bit symbol errors, lane 1 (RS-FEC only) */ 4123 #define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE1 0x64 4124 /* enum: Number of corrected 10-bit symbol errors, lane 2 (RS-FEC only) */ 4125 #define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE2 0x65 4126 /* enum: Number of corrected 10-bit symbol errors, lane 3 (RS-FEC only) */ 4127 #define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE3 0x66 4128 /* enum: This includes the final GENERATION_END */ 4129 #define MC_CMD_MAC_NSTATS_V2 0x68 4130 /* Other enum values, see field(s): */ 4131 /* MC_CMD_MAC_STATS_OUT_NO_DMA/STATISTICS */ 4132 4133 4134 /***********************************/ 4135 /* MC_CMD_SRIOV 4136 * to be documented 4137 */ 4138 #define MC_CMD_SRIOV 0x30 4139 4140 /* MC_CMD_SRIOV_IN msgrequest */ 4141 #define MC_CMD_SRIOV_IN_LEN 12 4142 #define MC_CMD_SRIOV_IN_ENABLE_OFST 0 4143 #define MC_CMD_SRIOV_IN_ENABLE_LEN 4 4144 #define MC_CMD_SRIOV_IN_VI_BASE_OFST 4 4145 #define MC_CMD_SRIOV_IN_VI_BASE_LEN 4 4146 #define MC_CMD_SRIOV_IN_VF_COUNT_OFST 8 4147 #define MC_CMD_SRIOV_IN_VF_COUNT_LEN 4 4148 4149 /* MC_CMD_SRIOV_OUT msgresponse */ 4150 #define MC_CMD_SRIOV_OUT_LEN 8 4151 #define MC_CMD_SRIOV_OUT_VI_SCALE_OFST 0 4152 #define MC_CMD_SRIOV_OUT_VI_SCALE_LEN 4 4153 #define MC_CMD_SRIOV_OUT_VF_TOTAL_OFST 4 4154 #define MC_CMD_SRIOV_OUT_VF_TOTAL_LEN 4 4155 4156 /* MC_CMD_MEMCPY_RECORD_TYPEDEF structuredef */ 4157 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LEN 32 4158 /* this is only used for the first record */ 4159 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_OFST 0 4160 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_LEN 4 4161 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_LBN 0 4162 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_WIDTH 32 4163 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_OFST 4 4164 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_LEN 4 4165 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_LBN 32 4166 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_WIDTH 32 4167 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_OFST 8 4168 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LEN 8 4169 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LO_OFST 8 4170 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_HI_OFST 12 4171 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LBN 64 4172 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_WIDTH 64 4173 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_OFST 16 4174 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_LEN 4 4175 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_RID_INLINE 0x100 /* enum */ 4176 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_LBN 128 4177 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_WIDTH 32 4178 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_OFST 20 4179 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LEN 8 4180 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LO_OFST 20 4181 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_HI_OFST 24 4182 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LBN 160 4183 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_WIDTH 64 4184 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_OFST 28 4185 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_LEN 4 4186 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_LBN 224 4187 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_WIDTH 32 4188 4189 4190 /***********************************/ 4191 /* MC_CMD_MEMCPY 4192 * DMA write data into (Rid,Addr), either by dma reading (Rid,Addr), or by data 4193 * embedded directly in the command. 4194 * 4195 * A common pattern is for a client to use generation counts to signal a dma 4196 * update of a datastructure. To facilitate this, this MCDI operation can 4197 * contain multiple requests which are executed in strict order. Requests take 4198 * the form of duplicating the entire MCDI request continuously (including the 4199 * requests record, which is ignored in all but the first structure) 4200 * 4201 * The source data can either come from a DMA from the host, or it can be 4202 * embedded within the request directly, thereby eliminating a DMA read. To 4203 * indicate this, the client sets FROM_RID=%RID_INLINE, ADDR_HI=0, and 4204 * ADDR_LO=offset, and inserts the data at %offset from the start of the 4205 * payload. It's the callers responsibility to ensure that the embedded data 4206 * doesn't overlap the records. 4207 * 4208 * Returns: 0, EINVAL (invalid RID) 4209 */ 4210 #define MC_CMD_MEMCPY 0x31 4211 4212 /* MC_CMD_MEMCPY_IN msgrequest */ 4213 #define MC_CMD_MEMCPY_IN_LENMIN 32 4214 #define MC_CMD_MEMCPY_IN_LENMAX 224 4215 #define MC_CMD_MEMCPY_IN_LEN(num) (0+32*(num)) 4216 /* see MC_CMD_MEMCPY_RECORD_TYPEDEF */ 4217 #define MC_CMD_MEMCPY_IN_RECORD_OFST 0 4218 #define MC_CMD_MEMCPY_IN_RECORD_LEN 32 4219 #define MC_CMD_MEMCPY_IN_RECORD_MINNUM 1 4220 #define MC_CMD_MEMCPY_IN_RECORD_MAXNUM 7 4221 4222 /* MC_CMD_MEMCPY_OUT msgresponse */ 4223 #define MC_CMD_MEMCPY_OUT_LEN 0 4224 4225 4226 /***********************************/ 4227 /* MC_CMD_WOL_FILTER_SET 4228 * Set a WoL filter. 4229 */ 4230 #define MC_CMD_WOL_FILTER_SET 0x32 4231 #undef MC_CMD_0x32_PRIVILEGE_CTG 4232 4233 #define MC_CMD_0x32_PRIVILEGE_CTG SRIOV_CTG_LINK 4234 4235 /* MC_CMD_WOL_FILTER_SET_IN msgrequest */ 4236 #define MC_CMD_WOL_FILTER_SET_IN_LEN 192 4237 #define MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 4238 #define MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 4239 #define MC_CMD_FILTER_MODE_SIMPLE 0x0 /* enum */ 4240 #define MC_CMD_FILTER_MODE_STRUCTURED 0xffffffff /* enum */ 4241 /* A type value of 1 is unused. */ 4242 #define MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 4243 #define MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 4244 /* enum: Magic */ 4245 #define MC_CMD_WOL_TYPE_MAGIC 0x0 4246 /* enum: MS Windows Magic */ 4247 #define MC_CMD_WOL_TYPE_WIN_MAGIC 0x2 4248 /* enum: IPv4 Syn */ 4249 #define MC_CMD_WOL_TYPE_IPV4_SYN 0x3 4250 /* enum: IPv6 Syn */ 4251 #define MC_CMD_WOL_TYPE_IPV6_SYN 0x4 4252 /* enum: Bitmap */ 4253 #define MC_CMD_WOL_TYPE_BITMAP 0x5 4254 /* enum: Link */ 4255 #define MC_CMD_WOL_TYPE_LINK 0x6 4256 /* enum: (Above this for future use) */ 4257 #define MC_CMD_WOL_TYPE_MAX 0x7 4258 #define MC_CMD_WOL_FILTER_SET_IN_DATA_OFST 8 4259 #define MC_CMD_WOL_FILTER_SET_IN_DATA_LEN 4 4260 #define MC_CMD_WOL_FILTER_SET_IN_DATA_NUM 46 4261 4262 /* MC_CMD_WOL_FILTER_SET_IN_MAGIC msgrequest */ 4263 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_LEN 16 4264 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 4265 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */ 4266 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 4267 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */ 4268 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_OFST 8 4269 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LEN 8 4270 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LO_OFST 8 4271 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_HI_OFST 12 4272 4273 /* MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN msgrequest */ 4274 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_LEN 20 4275 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 4276 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */ 4277 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 4278 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */ 4279 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_IP_OFST 8 4280 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_IP_LEN 4 4281 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_IP_OFST 12 4282 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_IP_LEN 4 4283 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_OFST 16 4284 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_LEN 2 4285 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_OFST 18 4286 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_LEN 2 4287 4288 /* MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN msgrequest */ 4289 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_LEN 44 4290 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 4291 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */ 4292 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 4293 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */ 4294 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_OFST 8 4295 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_LEN 16 4296 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_OFST 24 4297 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_LEN 16 4298 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_OFST 40 4299 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_LEN 2 4300 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_OFST 42 4301 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_LEN 2 4302 4303 /* MC_CMD_WOL_FILTER_SET_IN_BITMAP msgrequest */ 4304 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN 187 4305 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 4306 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */ 4307 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 4308 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */ 4309 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_OFST 8 4310 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_LEN 48 4311 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_OFST 56 4312 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_LEN 128 4313 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_OFST 184 4314 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_LEN 1 4315 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_OFST 185 4316 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_LEN 1 4317 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_OFST 186 4318 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_LEN 1 4319 4320 /* MC_CMD_WOL_FILTER_SET_IN_LINK msgrequest */ 4321 #define MC_CMD_WOL_FILTER_SET_IN_LINK_LEN 12 4322 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 4323 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */ 4324 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 4325 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */ 4326 #define MC_CMD_WOL_FILTER_SET_IN_LINK_MASK_OFST 8 4327 #define MC_CMD_WOL_FILTER_SET_IN_LINK_MASK_LEN 4 4328 #define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_LBN 0 4329 #define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_WIDTH 1 4330 #define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_LBN 1 4331 #define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_WIDTH 1 4332 4333 /* MC_CMD_WOL_FILTER_SET_OUT msgresponse */ 4334 #define MC_CMD_WOL_FILTER_SET_OUT_LEN 4 4335 #define MC_CMD_WOL_FILTER_SET_OUT_FILTER_ID_OFST 0 4336 #define MC_CMD_WOL_FILTER_SET_OUT_FILTER_ID_LEN 4 4337 4338 4339 /***********************************/ 4340 /* MC_CMD_WOL_FILTER_REMOVE 4341 * Remove a WoL filter. Locks required: None. Returns: 0, EINVAL, ENOSYS 4342 */ 4343 #define MC_CMD_WOL_FILTER_REMOVE 0x33 4344 #undef MC_CMD_0x33_PRIVILEGE_CTG 4345 4346 #define MC_CMD_0x33_PRIVILEGE_CTG SRIOV_CTG_LINK 4347 4348 /* MC_CMD_WOL_FILTER_REMOVE_IN msgrequest */ 4349 #define MC_CMD_WOL_FILTER_REMOVE_IN_LEN 4 4350 #define MC_CMD_WOL_FILTER_REMOVE_IN_FILTER_ID_OFST 0 4351 #define MC_CMD_WOL_FILTER_REMOVE_IN_FILTER_ID_LEN 4 4352 4353 /* MC_CMD_WOL_FILTER_REMOVE_OUT msgresponse */ 4354 #define MC_CMD_WOL_FILTER_REMOVE_OUT_LEN 0 4355 4356 4357 /***********************************/ 4358 /* MC_CMD_WOL_FILTER_RESET 4359 * Reset (i.e. remove all) WoL filters. Locks required: None. Returns: 0, 4360 * ENOSYS 4361 */ 4362 #define MC_CMD_WOL_FILTER_RESET 0x34 4363 #undef MC_CMD_0x34_PRIVILEGE_CTG 4364 4365 #define MC_CMD_0x34_PRIVILEGE_CTG SRIOV_CTG_LINK 4366 4367 /* MC_CMD_WOL_FILTER_RESET_IN msgrequest */ 4368 #define MC_CMD_WOL_FILTER_RESET_IN_LEN 4 4369 #define MC_CMD_WOL_FILTER_RESET_IN_MASK_OFST 0 4370 #define MC_CMD_WOL_FILTER_RESET_IN_MASK_LEN 4 4371 #define MC_CMD_WOL_FILTER_RESET_IN_WAKE_FILTERS 0x1 /* enum */ 4372 #define MC_CMD_WOL_FILTER_RESET_IN_LIGHTSOUT_OFFLOADS 0x2 /* enum */ 4373 4374 /* MC_CMD_WOL_FILTER_RESET_OUT msgresponse */ 4375 #define MC_CMD_WOL_FILTER_RESET_OUT_LEN 0 4376 4377 4378 /***********************************/ 4379 /* MC_CMD_SET_MCAST_HASH 4380 * Set the MCAST hash value without otherwise reconfiguring the MAC 4381 */ 4382 #define MC_CMD_SET_MCAST_HASH 0x35 4383 4384 /* MC_CMD_SET_MCAST_HASH_IN msgrequest */ 4385 #define MC_CMD_SET_MCAST_HASH_IN_LEN 32 4386 #define MC_CMD_SET_MCAST_HASH_IN_HASH0_OFST 0 4387 #define MC_CMD_SET_MCAST_HASH_IN_HASH0_LEN 16 4388 #define MC_CMD_SET_MCAST_HASH_IN_HASH1_OFST 16 4389 #define MC_CMD_SET_MCAST_HASH_IN_HASH1_LEN 16 4390 4391 /* MC_CMD_SET_MCAST_HASH_OUT msgresponse */ 4392 #define MC_CMD_SET_MCAST_HASH_OUT_LEN 0 4393 4394 4395 /***********************************/ 4396 /* MC_CMD_NVRAM_TYPES 4397 * Return bitfield indicating available types of virtual NVRAM partitions. 4398 * Locks required: none. Returns: 0 4399 */ 4400 #define MC_CMD_NVRAM_TYPES 0x36 4401 #undef MC_CMD_0x36_PRIVILEGE_CTG 4402 4403 #define MC_CMD_0x36_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4404 4405 /* MC_CMD_NVRAM_TYPES_IN msgrequest */ 4406 #define MC_CMD_NVRAM_TYPES_IN_LEN 0 4407 4408 /* MC_CMD_NVRAM_TYPES_OUT msgresponse */ 4409 #define MC_CMD_NVRAM_TYPES_OUT_LEN 4 4410 /* Bit mask of supported types. */ 4411 #define MC_CMD_NVRAM_TYPES_OUT_TYPES_OFST 0 4412 #define MC_CMD_NVRAM_TYPES_OUT_TYPES_LEN 4 4413 /* enum: Disabled callisto. */ 4414 #define MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO 0x0 4415 /* enum: MC firmware. */ 4416 #define MC_CMD_NVRAM_TYPE_MC_FW 0x1 4417 /* enum: MC backup firmware. */ 4418 #define MC_CMD_NVRAM_TYPE_MC_FW_BACKUP 0x2 4419 /* enum: Static configuration Port0. */ 4420 #define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0 0x3 4421 /* enum: Static configuration Port1. */ 4422 #define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1 0x4 4423 /* enum: Dynamic configuration Port0. */ 4424 #define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0 0x5 4425 /* enum: Dynamic configuration Port1. */ 4426 #define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1 0x6 4427 /* enum: Expansion Rom. */ 4428 #define MC_CMD_NVRAM_TYPE_EXP_ROM 0x7 4429 /* enum: Expansion Rom Configuration Port0. */ 4430 #define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0 0x8 4431 /* enum: Expansion Rom Configuration Port1. */ 4432 #define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1 0x9 4433 /* enum: Phy Configuration Port0. */ 4434 #define MC_CMD_NVRAM_TYPE_PHY_PORT0 0xa 4435 /* enum: Phy Configuration Port1. */ 4436 #define MC_CMD_NVRAM_TYPE_PHY_PORT1 0xb 4437 /* enum: Log. */ 4438 #define MC_CMD_NVRAM_TYPE_LOG 0xc 4439 /* enum: FPGA image. */ 4440 #define MC_CMD_NVRAM_TYPE_FPGA 0xd 4441 /* enum: FPGA backup image */ 4442 #define MC_CMD_NVRAM_TYPE_FPGA_BACKUP 0xe 4443 /* enum: FC firmware. */ 4444 #define MC_CMD_NVRAM_TYPE_FC_FW 0xf 4445 /* enum: FC backup firmware. */ 4446 #define MC_CMD_NVRAM_TYPE_FC_FW_BACKUP 0x10 4447 /* enum: CPLD image. */ 4448 #define MC_CMD_NVRAM_TYPE_CPLD 0x11 4449 /* enum: Licensing information. */ 4450 #define MC_CMD_NVRAM_TYPE_LICENSE 0x12 4451 /* enum: FC Log. */ 4452 #define MC_CMD_NVRAM_TYPE_FC_LOG 0x13 4453 /* enum: Additional flash on FPGA. */ 4454 #define MC_CMD_NVRAM_TYPE_FC_EXTRA 0x14 4455 4456 4457 /***********************************/ 4458 /* MC_CMD_NVRAM_INFO 4459 * Read info about a virtual NVRAM partition. Locks required: none. Returns: 0, 4460 * EINVAL (bad type). 4461 */ 4462 #define MC_CMD_NVRAM_INFO 0x37 4463 #undef MC_CMD_0x37_PRIVILEGE_CTG 4464 4465 #define MC_CMD_0x37_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4466 4467 /* MC_CMD_NVRAM_INFO_IN msgrequest */ 4468 #define MC_CMD_NVRAM_INFO_IN_LEN 4 4469 #define MC_CMD_NVRAM_INFO_IN_TYPE_OFST 0 4470 #define MC_CMD_NVRAM_INFO_IN_TYPE_LEN 4 4471 /* Enum values, see field(s): */ 4472 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 4473 4474 /* MC_CMD_NVRAM_INFO_OUT msgresponse */ 4475 #define MC_CMD_NVRAM_INFO_OUT_LEN 24 4476 #define MC_CMD_NVRAM_INFO_OUT_TYPE_OFST 0 4477 #define MC_CMD_NVRAM_INFO_OUT_TYPE_LEN 4 4478 /* Enum values, see field(s): */ 4479 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 4480 #define MC_CMD_NVRAM_INFO_OUT_SIZE_OFST 4 4481 #define MC_CMD_NVRAM_INFO_OUT_SIZE_LEN 4 4482 #define MC_CMD_NVRAM_INFO_OUT_ERASESIZE_OFST 8 4483 #define MC_CMD_NVRAM_INFO_OUT_ERASESIZE_LEN 4 4484 #define MC_CMD_NVRAM_INFO_OUT_FLAGS_OFST 12 4485 #define MC_CMD_NVRAM_INFO_OUT_FLAGS_LEN 4 4486 #define MC_CMD_NVRAM_INFO_OUT_PROTECTED_LBN 0 4487 #define MC_CMD_NVRAM_INFO_OUT_PROTECTED_WIDTH 1 4488 #define MC_CMD_NVRAM_INFO_OUT_TLV_LBN 1 4489 #define MC_CMD_NVRAM_INFO_OUT_TLV_WIDTH 1 4490 #define MC_CMD_NVRAM_INFO_OUT_READ_ONLY_LBN 5 4491 #define MC_CMD_NVRAM_INFO_OUT_READ_ONLY_WIDTH 1 4492 #define MC_CMD_NVRAM_INFO_OUT_CMAC_LBN 6 4493 #define MC_CMD_NVRAM_INFO_OUT_CMAC_WIDTH 1 4494 #define MC_CMD_NVRAM_INFO_OUT_A_B_LBN 7 4495 #define MC_CMD_NVRAM_INFO_OUT_A_B_WIDTH 1 4496 #define MC_CMD_NVRAM_INFO_OUT_PHYSDEV_OFST 16 4497 #define MC_CMD_NVRAM_INFO_OUT_PHYSDEV_LEN 4 4498 #define MC_CMD_NVRAM_INFO_OUT_PHYSADDR_OFST 20 4499 #define MC_CMD_NVRAM_INFO_OUT_PHYSADDR_LEN 4 4500 4501 /* MC_CMD_NVRAM_INFO_V2_OUT msgresponse */ 4502 #define MC_CMD_NVRAM_INFO_V2_OUT_LEN 28 4503 #define MC_CMD_NVRAM_INFO_V2_OUT_TYPE_OFST 0 4504 #define MC_CMD_NVRAM_INFO_V2_OUT_TYPE_LEN 4 4505 /* Enum values, see field(s): */ 4506 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 4507 #define MC_CMD_NVRAM_INFO_V2_OUT_SIZE_OFST 4 4508 #define MC_CMD_NVRAM_INFO_V2_OUT_SIZE_LEN 4 4509 #define MC_CMD_NVRAM_INFO_V2_OUT_ERASESIZE_OFST 8 4510 #define MC_CMD_NVRAM_INFO_V2_OUT_ERASESIZE_LEN 4 4511 #define MC_CMD_NVRAM_INFO_V2_OUT_FLAGS_OFST 12 4512 #define MC_CMD_NVRAM_INFO_V2_OUT_FLAGS_LEN 4 4513 #define MC_CMD_NVRAM_INFO_V2_OUT_PROTECTED_LBN 0 4514 #define MC_CMD_NVRAM_INFO_V2_OUT_PROTECTED_WIDTH 1 4515 #define MC_CMD_NVRAM_INFO_V2_OUT_TLV_LBN 1 4516 #define MC_CMD_NVRAM_INFO_V2_OUT_TLV_WIDTH 1 4517 #define MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_LBN 5 4518 #define MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_WIDTH 1 4519 #define MC_CMD_NVRAM_INFO_V2_OUT_A_B_LBN 7 4520 #define MC_CMD_NVRAM_INFO_V2_OUT_A_B_WIDTH 1 4521 #define MC_CMD_NVRAM_INFO_V2_OUT_PHYSDEV_OFST 16 4522 #define MC_CMD_NVRAM_INFO_V2_OUT_PHYSDEV_LEN 4 4523 #define MC_CMD_NVRAM_INFO_V2_OUT_PHYSADDR_OFST 20 4524 #define MC_CMD_NVRAM_INFO_V2_OUT_PHYSADDR_LEN 4 4525 /* Writes must be multiples of this size. Added to support the MUM on Sorrento. 4526 */ 4527 #define MC_CMD_NVRAM_INFO_V2_OUT_WRITESIZE_OFST 24 4528 #define MC_CMD_NVRAM_INFO_V2_OUT_WRITESIZE_LEN 4 4529 4530 4531 /***********************************/ 4532 /* MC_CMD_NVRAM_UPDATE_START 4533 * Start a group of update operations on a virtual NVRAM partition. Locks 4534 * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad type), EACCES (if 4535 * PHY_LOCK required and not held). 4536 */ 4537 #define MC_CMD_NVRAM_UPDATE_START 0x38 4538 #undef MC_CMD_0x38_PRIVILEGE_CTG 4539 4540 #define MC_CMD_0x38_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4541 4542 /* MC_CMD_NVRAM_UPDATE_START_IN msgrequest: Legacy NVRAM_UPDATE_START request. 4543 * Use NVRAM_UPDATE_START_V2_IN in new code 4544 */ 4545 #define MC_CMD_NVRAM_UPDATE_START_IN_LEN 4 4546 #define MC_CMD_NVRAM_UPDATE_START_IN_TYPE_OFST 0 4547 #define MC_CMD_NVRAM_UPDATE_START_IN_TYPE_LEN 4 4548 /* Enum values, see field(s): */ 4549 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 4550 4551 /* MC_CMD_NVRAM_UPDATE_START_V2_IN msgrequest: Extended NVRAM_UPDATE_START 4552 * request with additional flags indicating version of command in use. See 4553 * MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT for details of extended functionality. Use 4554 * paired up with NVRAM_UPDATE_FINISH_V2_IN. 4555 */ 4556 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_LEN 8 4557 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_TYPE_OFST 0 4558 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_TYPE_LEN 4 4559 /* Enum values, see field(s): */ 4560 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 4561 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAGS_OFST 4 4562 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAGS_LEN 4 4563 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAG_REPORT_VERIFY_RESULT_LBN 0 4564 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAG_REPORT_VERIFY_RESULT_WIDTH 1 4565 4566 /* MC_CMD_NVRAM_UPDATE_START_OUT msgresponse */ 4567 #define MC_CMD_NVRAM_UPDATE_START_OUT_LEN 0 4568 4569 4570 /***********************************/ 4571 /* MC_CMD_NVRAM_READ 4572 * Read data from a virtual NVRAM partition. Locks required: PHY_LOCK if 4573 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if 4574 * PHY_LOCK required and not held) 4575 */ 4576 #define MC_CMD_NVRAM_READ 0x39 4577 #undef MC_CMD_0x39_PRIVILEGE_CTG 4578 4579 #define MC_CMD_0x39_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4580 4581 /* MC_CMD_NVRAM_READ_IN msgrequest */ 4582 #define MC_CMD_NVRAM_READ_IN_LEN 12 4583 #define MC_CMD_NVRAM_READ_IN_TYPE_OFST 0 4584 #define MC_CMD_NVRAM_READ_IN_TYPE_LEN 4 4585 /* Enum values, see field(s): */ 4586 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 4587 #define MC_CMD_NVRAM_READ_IN_OFFSET_OFST 4 4588 #define MC_CMD_NVRAM_READ_IN_OFFSET_LEN 4 4589 /* amount to read in bytes */ 4590 #define MC_CMD_NVRAM_READ_IN_LENGTH_OFST 8 4591 #define MC_CMD_NVRAM_READ_IN_LENGTH_LEN 4 4592 4593 /* MC_CMD_NVRAM_READ_IN_V2 msgrequest */ 4594 #define MC_CMD_NVRAM_READ_IN_V2_LEN 16 4595 #define MC_CMD_NVRAM_READ_IN_V2_TYPE_OFST 0 4596 #define MC_CMD_NVRAM_READ_IN_V2_TYPE_LEN 4 4597 /* Enum values, see field(s): */ 4598 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 4599 #define MC_CMD_NVRAM_READ_IN_V2_OFFSET_OFST 4 4600 #define MC_CMD_NVRAM_READ_IN_V2_OFFSET_LEN 4 4601 /* amount to read in bytes */ 4602 #define MC_CMD_NVRAM_READ_IN_V2_LENGTH_OFST 8 4603 #define MC_CMD_NVRAM_READ_IN_V2_LENGTH_LEN 4 4604 /* Optional control info. If a partition is stored with an A/B versioning 4605 * scheme (i.e. in more than one physical partition in NVRAM) the host can set 4606 * this to control which underlying physical partition is used to read data 4607 * from. This allows it to perform a read-modify-write-verify with the write 4608 * lock continuously held by calling NVRAM_UPDATE_START, reading the old 4609 * contents using MODE=TARGET_CURRENT, overwriting the old partition and then 4610 * verifying by reading with MODE=TARGET_BACKUP. 4611 */ 4612 #define MC_CMD_NVRAM_READ_IN_V2_MODE_OFST 12 4613 #define MC_CMD_NVRAM_READ_IN_V2_MODE_LEN 4 4614 /* enum: Same as omitting MODE: caller sees data in current partition unless it 4615 * holds the write lock in which case it sees data in the partition it is 4616 * updating. 4617 */ 4618 #define MC_CMD_NVRAM_READ_IN_V2_DEFAULT 0x0 4619 /* enum: Read from the current partition of an A/B pair, even if holding the 4620 * write lock. 4621 */ 4622 #define MC_CMD_NVRAM_READ_IN_V2_TARGET_CURRENT 0x1 4623 /* enum: Read from the non-current (i.e. to be updated) partition of an A/B 4624 * pair 4625 */ 4626 #define MC_CMD_NVRAM_READ_IN_V2_TARGET_BACKUP 0x2 4627 4628 /* MC_CMD_NVRAM_READ_OUT msgresponse */ 4629 #define MC_CMD_NVRAM_READ_OUT_LENMIN 1 4630 #define MC_CMD_NVRAM_READ_OUT_LENMAX 252 4631 #define MC_CMD_NVRAM_READ_OUT_LEN(num) (0+1*(num)) 4632 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_OFST 0 4633 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_LEN 1 4634 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MINNUM 1 4635 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MAXNUM 252 4636 4637 4638 /***********************************/ 4639 /* MC_CMD_NVRAM_WRITE 4640 * Write data to a virtual NVRAM partition. Locks required: PHY_LOCK if 4641 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if 4642 * PHY_LOCK required and not held) 4643 */ 4644 #define MC_CMD_NVRAM_WRITE 0x3a 4645 #undef MC_CMD_0x3a_PRIVILEGE_CTG 4646 4647 #define MC_CMD_0x3a_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4648 4649 /* MC_CMD_NVRAM_WRITE_IN msgrequest */ 4650 #define MC_CMD_NVRAM_WRITE_IN_LENMIN 13 4651 #define MC_CMD_NVRAM_WRITE_IN_LENMAX 252 4652 #define MC_CMD_NVRAM_WRITE_IN_LEN(num) (12+1*(num)) 4653 #define MC_CMD_NVRAM_WRITE_IN_TYPE_OFST 0 4654 #define MC_CMD_NVRAM_WRITE_IN_TYPE_LEN 4 4655 /* Enum values, see field(s): */ 4656 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 4657 #define MC_CMD_NVRAM_WRITE_IN_OFFSET_OFST 4 4658 #define MC_CMD_NVRAM_WRITE_IN_OFFSET_LEN 4 4659 #define MC_CMD_NVRAM_WRITE_IN_LENGTH_OFST 8 4660 #define MC_CMD_NVRAM_WRITE_IN_LENGTH_LEN 4 4661 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_OFST 12 4662 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_LEN 1 4663 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MINNUM 1 4664 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MAXNUM 240 4665 4666 /* MC_CMD_NVRAM_WRITE_OUT msgresponse */ 4667 #define MC_CMD_NVRAM_WRITE_OUT_LEN 0 4668 4669 4670 /***********************************/ 4671 /* MC_CMD_NVRAM_ERASE 4672 * Erase sector(s) from a virtual NVRAM partition. Locks required: PHY_LOCK if 4673 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if 4674 * PHY_LOCK required and not held) 4675 */ 4676 #define MC_CMD_NVRAM_ERASE 0x3b 4677 #undef MC_CMD_0x3b_PRIVILEGE_CTG 4678 4679 #define MC_CMD_0x3b_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4680 4681 /* MC_CMD_NVRAM_ERASE_IN msgrequest */ 4682 #define MC_CMD_NVRAM_ERASE_IN_LEN 12 4683 #define MC_CMD_NVRAM_ERASE_IN_TYPE_OFST 0 4684 #define MC_CMD_NVRAM_ERASE_IN_TYPE_LEN 4 4685 /* Enum values, see field(s): */ 4686 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 4687 #define MC_CMD_NVRAM_ERASE_IN_OFFSET_OFST 4 4688 #define MC_CMD_NVRAM_ERASE_IN_OFFSET_LEN 4 4689 #define MC_CMD_NVRAM_ERASE_IN_LENGTH_OFST 8 4690 #define MC_CMD_NVRAM_ERASE_IN_LENGTH_LEN 4 4691 4692 /* MC_CMD_NVRAM_ERASE_OUT msgresponse */ 4693 #define MC_CMD_NVRAM_ERASE_OUT_LEN 0 4694 4695 4696 /***********************************/ 4697 /* MC_CMD_NVRAM_UPDATE_FINISH 4698 * Finish a group of update operations on a virtual NVRAM partition. Locks 4699 * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad 4700 * type/offset/length), EACCES (if PHY_LOCK required and not held) 4701 */ 4702 #define MC_CMD_NVRAM_UPDATE_FINISH 0x3c 4703 #undef MC_CMD_0x3c_PRIVILEGE_CTG 4704 4705 #define MC_CMD_0x3c_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4706 4707 /* MC_CMD_NVRAM_UPDATE_FINISH_IN msgrequest: Legacy NVRAM_UPDATE_FINISH 4708 * request. Use NVRAM_UPDATE_FINISH_V2_IN in new code 4709 */ 4710 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_LEN 8 4711 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_TYPE_OFST 0 4712 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_TYPE_LEN 4 4713 /* Enum values, see field(s): */ 4714 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 4715 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_REBOOT_OFST 4 4716 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_REBOOT_LEN 4 4717 4718 /* MC_CMD_NVRAM_UPDATE_FINISH_V2_IN msgrequest: Extended NVRAM_UPDATE_FINISH 4719 * request with additional flags indicating version of NVRAM_UPDATE commands in 4720 * use. See MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT for details of extended 4721 * functionality. Use paired up with NVRAM_UPDATE_START_V2_IN. 4722 */ 4723 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_LEN 12 4724 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_TYPE_OFST 0 4725 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_TYPE_LEN 4 4726 /* Enum values, see field(s): */ 4727 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 4728 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_REBOOT_OFST 4 4729 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_REBOOT_LEN 4 4730 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAGS_OFST 8 4731 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAGS_LEN 4 4732 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_REPORT_VERIFY_RESULT_LBN 0 4733 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_REPORT_VERIFY_RESULT_WIDTH 1 4734 4735 /* MC_CMD_NVRAM_UPDATE_FINISH_OUT msgresponse: Legacy NVRAM_UPDATE_FINISH 4736 * response. Use NVRAM_UPDATE_FINISH_V2_OUT in new code 4737 */ 4738 #define MC_CMD_NVRAM_UPDATE_FINISH_OUT_LEN 0 4739 4740 /* MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT msgresponse: 4741 * 4742 * Extended NVRAM_UPDATE_FINISH response that communicates the result of secure 4743 * firmware validation where applicable back to the host. 4744 * 4745 * Medford only: For signed firmware images, such as those for medford, the MC 4746 * firmware verifies the signature before marking the firmware image as valid. 4747 * This process takes a few seconds to complete. So is likely to take more than 4748 * the MCDI timeout. Hence signature verification is initiated when 4749 * MC_CMD_NVRAM_UPDATE_FINISH_V2_IN is received by the firmware, however, the 4750 * MCDI command is run in a background MCDI processing thread. This response 4751 * payload includes the results of the signature verification. Note that the 4752 * per-partition nvram lock in firmware is only released after the verification 4753 * has completed. 4754 */ 4755 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_LEN 4 4756 /* Result of nvram update completion processing */ 4757 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_RESULT_CODE_OFST 0 4758 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_RESULT_CODE_LEN 4 4759 /* enum: Invalid return code; only non-zero values are defined. Defined as 4760 * unknown for backwards compatibility with NVRAM_UPDATE_FINISH_OUT. 4761 */ 4762 #define MC_CMD_NVRAM_VERIFY_RC_UNKNOWN 0x0 4763 /* enum: Verify succeeded without any errors. */ 4764 #define MC_CMD_NVRAM_VERIFY_RC_SUCCESS 0x1 4765 /* enum: CMS format verification failed due to an internal error. */ 4766 #define MC_CMD_NVRAM_VERIFY_RC_CMS_CHECK_FAILED 0x2 4767 /* enum: Invalid CMS format in image metadata. */ 4768 #define MC_CMD_NVRAM_VERIFY_RC_INVALID_CMS_FORMAT 0x3 4769 /* enum: Message digest verification failed due to an internal error. */ 4770 #define MC_CMD_NVRAM_VERIFY_RC_MESSAGE_DIGEST_CHECK_FAILED 0x4 4771 /* enum: Error in message digest calculated over the reflash-header, payload 4772 * and reflash-trailer. 4773 */ 4774 #define MC_CMD_NVRAM_VERIFY_RC_BAD_MESSAGE_DIGEST 0x5 4775 /* enum: Signature verification failed due to an internal error. */ 4776 #define MC_CMD_NVRAM_VERIFY_RC_SIGNATURE_CHECK_FAILED 0x6 4777 /* enum: There are no valid signatures in the image. */ 4778 #define MC_CMD_NVRAM_VERIFY_RC_NO_VALID_SIGNATURES 0x7 4779 /* enum: Trusted approvers verification failed due to an internal error. */ 4780 #define MC_CMD_NVRAM_VERIFY_RC_TRUSTED_APPROVERS_CHECK_FAILED 0x8 4781 /* enum: The Trusted approver's list is empty. */ 4782 #define MC_CMD_NVRAM_VERIFY_RC_NO_TRUSTED_APPROVERS 0x9 4783 /* enum: Signature chain verification failed due to an internal error. */ 4784 #define MC_CMD_NVRAM_VERIFY_RC_SIGNATURE_CHAIN_CHECK_FAILED 0xa 4785 /* enum: The signers of the signatures in the image are not listed in the 4786 * Trusted approver's list. 4787 */ 4788 #define MC_CMD_NVRAM_VERIFY_RC_NO_SIGNATURE_MATCH 0xb 4789 /* enum: The image contains a test-signed certificate, but the adapter accepts 4790 * only production signed images. 4791 */ 4792 #define MC_CMD_NVRAM_VERIFY_RC_REJECT_TEST_SIGNED 0xc 4793 /* enum: The image has a lower security level than the current firmware. */ 4794 #define MC_CMD_NVRAM_VERIFY_RC_SECURITY_LEVEL_DOWNGRADE 0xd 4795 4796 4797 /***********************************/ 4798 /* MC_CMD_REBOOT 4799 * Reboot the MC. 4800 * 4801 * The AFTER_ASSERTION flag is intended to be used when the driver notices an 4802 * assertion failure (at which point it is expected to perform a complete tear 4803 * down and reinitialise), to allow both ports to reset the MC once in an 4804 * atomic fashion. 4805 * 4806 * Production mc firmwares are generally compiled with REBOOT_ON_ASSERT=1, 4807 * which means that they will automatically reboot out of the assertion 4808 * handler, so this is in practise an optional operation. It is still 4809 * recommended that drivers execute this to support custom firmwares with 4810 * REBOOT_ON_ASSERT=0. 4811 * 4812 * Locks required: NONE Returns: Nothing. You get back a response with ERR=1, 4813 * DATALEN=0 4814 */ 4815 #define MC_CMD_REBOOT 0x3d 4816 #undef MC_CMD_0x3d_PRIVILEGE_CTG 4817 4818 #define MC_CMD_0x3d_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4819 4820 /* MC_CMD_REBOOT_IN msgrequest */ 4821 #define MC_CMD_REBOOT_IN_LEN 4 4822 #define MC_CMD_REBOOT_IN_FLAGS_OFST 0 4823 #define MC_CMD_REBOOT_IN_FLAGS_LEN 4 4824 #define MC_CMD_REBOOT_FLAGS_AFTER_ASSERTION 0x1 /* enum */ 4825 4826 /* MC_CMD_REBOOT_OUT msgresponse */ 4827 #define MC_CMD_REBOOT_OUT_LEN 0 4828 4829 4830 /***********************************/ 4831 /* MC_CMD_SCHEDINFO 4832 * Request scheduler info. Locks required: NONE. Returns: An array of 4833 * (timeslice,maximum overrun), one for each thread, in ascending order of 4834 * thread address. 4835 */ 4836 #define MC_CMD_SCHEDINFO 0x3e 4837 #undef MC_CMD_0x3e_PRIVILEGE_CTG 4838 4839 #define MC_CMD_0x3e_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4840 4841 /* MC_CMD_SCHEDINFO_IN msgrequest */ 4842 #define MC_CMD_SCHEDINFO_IN_LEN 0 4843 4844 /* MC_CMD_SCHEDINFO_OUT msgresponse */ 4845 #define MC_CMD_SCHEDINFO_OUT_LENMIN 4 4846 #define MC_CMD_SCHEDINFO_OUT_LENMAX 252 4847 #define MC_CMD_SCHEDINFO_OUT_LEN(num) (0+4*(num)) 4848 #define MC_CMD_SCHEDINFO_OUT_DATA_OFST 0 4849 #define MC_CMD_SCHEDINFO_OUT_DATA_LEN 4 4850 #define MC_CMD_SCHEDINFO_OUT_DATA_MINNUM 1 4851 #define MC_CMD_SCHEDINFO_OUT_DATA_MAXNUM 63 4852 4853 4854 /***********************************/ 4855 /* MC_CMD_REBOOT_MODE 4856 * Set the mode for the next MC reboot. Locks required: NONE. Sets the reboot 4857 * mode to the specified value. Returns the old mode. 4858 */ 4859 #define MC_CMD_REBOOT_MODE 0x3f 4860 #undef MC_CMD_0x3f_PRIVILEGE_CTG 4861 4862 #define MC_CMD_0x3f_PRIVILEGE_CTG SRIOV_CTG_INSECURE 4863 4864 /* MC_CMD_REBOOT_MODE_IN msgrequest */ 4865 #define MC_CMD_REBOOT_MODE_IN_LEN 4 4866 #define MC_CMD_REBOOT_MODE_IN_VALUE_OFST 0 4867 #define MC_CMD_REBOOT_MODE_IN_VALUE_LEN 4 4868 /* enum: Normal. */ 4869 #define MC_CMD_REBOOT_MODE_NORMAL 0x0 4870 /* enum: Power-on Reset. */ 4871 #define MC_CMD_REBOOT_MODE_POR 0x2 4872 /* enum: Snapper. */ 4873 #define MC_CMD_REBOOT_MODE_SNAPPER 0x3 4874 /* enum: snapper fake POR */ 4875 #define MC_CMD_REBOOT_MODE_SNAPPER_POR 0x4 4876 #define MC_CMD_REBOOT_MODE_IN_FAKE_LBN 7 4877 #define MC_CMD_REBOOT_MODE_IN_FAKE_WIDTH 1 4878 4879 /* MC_CMD_REBOOT_MODE_OUT msgresponse */ 4880 #define MC_CMD_REBOOT_MODE_OUT_LEN 4 4881 #define MC_CMD_REBOOT_MODE_OUT_VALUE_OFST 0 4882 #define MC_CMD_REBOOT_MODE_OUT_VALUE_LEN 4 4883 4884 4885 /***********************************/ 4886 /* MC_CMD_SENSOR_INFO 4887 * Returns information about every available sensor. 4888 * 4889 * Each sensor has a single (16bit) value, and a corresponding state. The 4890 * mapping between value and state is nominally determined by the MC, but may 4891 * be implemented using up to 2 ranges per sensor. 4892 * 4893 * This call returns a mask (32bit) of the sensors that are supported by this 4894 * platform, then an array of sensor information structures, in order of sensor 4895 * type (but without gaps for unimplemented sensors). Each structure defines 4896 * the ranges for the corresponding sensor. An unused range is indicated by 4897 * equal limit values. If one range is used, a value outside that range results 4898 * in STATE_FATAL. If two ranges are used, a value outside the second range 4899 * results in STATE_FATAL while a value outside the first and inside the second 4900 * range results in STATE_WARNING. 4901 * 4902 * Sensor masks and sensor information arrays are organised into pages. For 4903 * backward compatibility, older host software can only use sensors in page 0. 4904 * Bit 32 in the sensor mask was previously unused, and is no reserved for use 4905 * as the next page flag. 4906 * 4907 * If the request does not contain a PAGE value then firmware will only return 4908 * page 0 of sensor information, with bit 31 in the sensor mask cleared. 4909 * 4910 * If the request contains a PAGE value then firmware responds with the sensor 4911 * mask and sensor information array for that page of sensors. In this case bit 4912 * 31 in the mask is set if another page exists. 4913 * 4914 * Locks required: None Returns: 0 4915 */ 4916 #define MC_CMD_SENSOR_INFO 0x41 4917 #undef MC_CMD_0x41_PRIVILEGE_CTG 4918 4919 #define MC_CMD_0x41_PRIVILEGE_CTG SRIOV_CTG_GENERAL 4920 4921 /* MC_CMD_SENSOR_INFO_IN msgrequest */ 4922 #define MC_CMD_SENSOR_INFO_IN_LEN 0 4923 4924 /* MC_CMD_SENSOR_INFO_EXT_IN msgrequest */ 4925 #define MC_CMD_SENSOR_INFO_EXT_IN_LEN 4 4926 /* Which page of sensors to report. 4927 * 4928 * Page 0 contains sensors 0 to 30 (sensor 31 is the next page bit). 4929 * 4930 * Page 1 contains sensors 32 to 62 (sensor 63 is the next page bit). etc. 4931 */ 4932 #define MC_CMD_SENSOR_INFO_EXT_IN_PAGE_OFST 0 4933 #define MC_CMD_SENSOR_INFO_EXT_IN_PAGE_LEN 4 4934 4935 /* MC_CMD_SENSOR_INFO_OUT msgresponse */ 4936 #define MC_CMD_SENSOR_INFO_OUT_LENMIN 4 4937 #define MC_CMD_SENSOR_INFO_OUT_LENMAX 252 4938 #define MC_CMD_SENSOR_INFO_OUT_LEN(num) (4+8*(num)) 4939 #define MC_CMD_SENSOR_INFO_OUT_MASK_OFST 0 4940 #define MC_CMD_SENSOR_INFO_OUT_MASK_LEN 4 4941 /* enum: Controller temperature: degC */ 4942 #define MC_CMD_SENSOR_CONTROLLER_TEMP 0x0 4943 /* enum: Phy common temperature: degC */ 4944 #define MC_CMD_SENSOR_PHY_COMMON_TEMP 0x1 4945 /* enum: Controller cooling: bool */ 4946 #define MC_CMD_SENSOR_CONTROLLER_COOLING 0x2 4947 /* enum: Phy 0 temperature: degC */ 4948 #define MC_CMD_SENSOR_PHY0_TEMP 0x3 4949 /* enum: Phy 0 cooling: bool */ 4950 #define MC_CMD_SENSOR_PHY0_COOLING 0x4 4951 /* enum: Phy 1 temperature: degC */ 4952 #define MC_CMD_SENSOR_PHY1_TEMP 0x5 4953 /* enum: Phy 1 cooling: bool */ 4954 #define MC_CMD_SENSOR_PHY1_COOLING 0x6 4955 /* enum: 1.0v power: mV */ 4956 #define MC_CMD_SENSOR_IN_1V0 0x7 4957 /* enum: 1.2v power: mV */ 4958 #define MC_CMD_SENSOR_IN_1V2 0x8 4959 /* enum: 1.8v power: mV */ 4960 #define MC_CMD_SENSOR_IN_1V8 0x9 4961 /* enum: 2.5v power: mV */ 4962 #define MC_CMD_SENSOR_IN_2V5 0xa 4963 /* enum: 3.3v power: mV */ 4964 #define MC_CMD_SENSOR_IN_3V3 0xb 4965 /* enum: 12v power: mV */ 4966 #define MC_CMD_SENSOR_IN_12V0 0xc 4967 /* enum: 1.2v analogue power: mV */ 4968 #define MC_CMD_SENSOR_IN_1V2A 0xd 4969 /* enum: reference voltage: mV */ 4970 #define MC_CMD_SENSOR_IN_VREF 0xe 4971 /* enum: AOE FPGA power: mV */ 4972 #define MC_CMD_SENSOR_OUT_VAOE 0xf 4973 /* enum: AOE FPGA temperature: degC */ 4974 #define MC_CMD_SENSOR_AOE_TEMP 0x10 4975 /* enum: AOE FPGA PSU temperature: degC */ 4976 #define MC_CMD_SENSOR_PSU_AOE_TEMP 0x11 4977 /* enum: AOE PSU temperature: degC */ 4978 #define MC_CMD_SENSOR_PSU_TEMP 0x12 4979 /* enum: Fan 0 speed: RPM */ 4980 #define MC_CMD_SENSOR_FAN_0 0x13 4981 /* enum: Fan 1 speed: RPM */ 4982 #define MC_CMD_SENSOR_FAN_1 0x14 4983 /* enum: Fan 2 speed: RPM */ 4984 #define MC_CMD_SENSOR_FAN_2 0x15 4985 /* enum: Fan 3 speed: RPM */ 4986 #define MC_CMD_SENSOR_FAN_3 0x16 4987 /* enum: Fan 4 speed: RPM */ 4988 #define MC_CMD_SENSOR_FAN_4 0x17 4989 /* enum: AOE FPGA input power: mV */ 4990 #define MC_CMD_SENSOR_IN_VAOE 0x18 4991 /* enum: AOE FPGA current: mA */ 4992 #define MC_CMD_SENSOR_OUT_IAOE 0x19 4993 /* enum: AOE FPGA input current: mA */ 4994 #define MC_CMD_SENSOR_IN_IAOE 0x1a 4995 /* enum: NIC power consumption: W */ 4996 #define MC_CMD_SENSOR_NIC_POWER 0x1b 4997 /* enum: 0.9v power voltage: mV */ 4998 #define MC_CMD_SENSOR_IN_0V9 0x1c 4999 /* enum: 0.9v power current: mA */ 5000 #define MC_CMD_SENSOR_IN_I0V9 0x1d 5001 /* enum: 1.2v power current: mA */ 5002 #define MC_CMD_SENSOR_IN_I1V2 0x1e 5003 /* enum: Not a sensor: reserved for the next page flag */ 5004 #define MC_CMD_SENSOR_PAGE0_NEXT 0x1f 5005 /* enum: 0.9v power voltage (at ADC): mV */ 5006 #define MC_CMD_SENSOR_IN_0V9_ADC 0x20 5007 /* enum: Controller temperature 2: degC */ 5008 #define MC_CMD_SENSOR_CONTROLLER_2_TEMP 0x21 5009 /* enum: Voltage regulator internal temperature: degC */ 5010 #define MC_CMD_SENSOR_VREG_INTERNAL_TEMP 0x22 5011 /* enum: 0.9V voltage regulator temperature: degC */ 5012 #define MC_CMD_SENSOR_VREG_0V9_TEMP 0x23 5013 /* enum: 1.2V voltage regulator temperature: degC */ 5014 #define MC_CMD_SENSOR_VREG_1V2_TEMP 0x24 5015 /* enum: controller internal temperature sensor voltage (internal ADC): mV */ 5016 #define MC_CMD_SENSOR_CONTROLLER_VPTAT 0x25 5017 /* enum: controller internal temperature (internal ADC): degC */ 5018 #define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP 0x26 5019 /* enum: controller internal temperature sensor voltage (external ADC): mV */ 5020 #define MC_CMD_SENSOR_CONTROLLER_VPTAT_EXTADC 0x27 5021 /* enum: controller internal temperature (external ADC): degC */ 5022 #define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP_EXTADC 0x28 5023 /* enum: ambient temperature: degC */ 5024 #define MC_CMD_SENSOR_AMBIENT_TEMP 0x29 5025 /* enum: air flow: bool */ 5026 #define MC_CMD_SENSOR_AIRFLOW 0x2a 5027 /* enum: voltage between VSS08D and VSS08D at CSR: mV */ 5028 #define MC_CMD_SENSOR_VDD08D_VSS08D_CSR 0x2b 5029 /* enum: voltage between VSS08D and VSS08D at CSR (external ADC): mV */ 5030 #define MC_CMD_SENSOR_VDD08D_VSS08D_CSR_EXTADC 0x2c 5031 /* enum: Hotpoint temperature: degC */ 5032 #define MC_CMD_SENSOR_HOTPOINT_TEMP 0x2d 5033 /* enum: Port 0 PHY power switch over-current: bool */ 5034 #define MC_CMD_SENSOR_PHY_POWER_PORT0 0x2e 5035 /* enum: Port 1 PHY power switch over-current: bool */ 5036 #define MC_CMD_SENSOR_PHY_POWER_PORT1 0x2f 5037 /* enum: Mop-up microcontroller reference voltage (millivolts) */ 5038 #define MC_CMD_SENSOR_MUM_VCC 0x30 5039 /* enum: 0.9v power phase A voltage: mV */ 5040 #define MC_CMD_SENSOR_IN_0V9_A 0x31 5041 /* enum: 0.9v power phase A current: mA */ 5042 #define MC_CMD_SENSOR_IN_I0V9_A 0x32 5043 /* enum: 0.9V voltage regulator phase A temperature: degC */ 5044 #define MC_CMD_SENSOR_VREG_0V9_A_TEMP 0x33 5045 /* enum: 0.9v power phase B voltage: mV */ 5046 #define MC_CMD_SENSOR_IN_0V9_B 0x34 5047 /* enum: 0.9v power phase B current: mA */ 5048 #define MC_CMD_SENSOR_IN_I0V9_B 0x35 5049 /* enum: 0.9V voltage regulator phase B temperature: degC */ 5050 #define MC_CMD_SENSOR_VREG_0V9_B_TEMP 0x36 5051 /* enum: CCOM AVREG 1v2 supply (interval ADC): mV */ 5052 #define MC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY 0x37 5053 /* enum: CCOM AVREG 1v2 supply (external ADC): mV */ 5054 #define MC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY_EXTADC 0x38 5055 /* enum: CCOM AVREG 1v8 supply (interval ADC): mV */ 5056 #define MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY 0x39 5057 /* enum: CCOM AVREG 1v8 supply (external ADC): mV */ 5058 #define MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY_EXTADC 0x3a 5059 /* enum: CCOM RTS temperature: degC */ 5060 #define MC_CMD_SENSOR_CONTROLLER_RTS 0x3b 5061 /* enum: Not a sensor: reserved for the next page flag */ 5062 #define MC_CMD_SENSOR_PAGE1_NEXT 0x3f 5063 /* enum: controller internal temperature sensor voltage on master core 5064 * (internal ADC): mV 5065 */ 5066 #define MC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT 0x40 5067 /* enum: controller internal temperature on master core (internal ADC): degC */ 5068 #define MC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP 0x41 5069 /* enum: controller internal temperature sensor voltage on master core 5070 * (external ADC): mV 5071 */ 5072 #define MC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT_EXTADC 0x42 5073 /* enum: controller internal temperature on master core (external ADC): degC */ 5074 #define MC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC 0x43 5075 /* enum: controller internal temperature on slave core sensor voltage (internal 5076 * ADC): mV 5077 */ 5078 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT 0x44 5079 /* enum: controller internal temperature on slave core (internal ADC): degC */ 5080 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP 0x45 5081 /* enum: controller internal temperature on slave core sensor voltage (external 5082 * ADC): mV 5083 */ 5084 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT_EXTADC 0x46 5085 /* enum: controller internal temperature on slave core (external ADC): degC */ 5086 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC 0x47 5087 /* enum: Voltage supplied to the SODIMMs from their power supply: mV */ 5088 #define MC_CMD_SENSOR_SODIMM_VOUT 0x49 5089 /* enum: Temperature of SODIMM 0 (if installed): degC */ 5090 #define MC_CMD_SENSOR_SODIMM_0_TEMP 0x4a 5091 /* enum: Temperature of SODIMM 1 (if installed): degC */ 5092 #define MC_CMD_SENSOR_SODIMM_1_TEMP 0x4b 5093 /* enum: Voltage supplied to the QSFP #0 from their power supply: mV */ 5094 #define MC_CMD_SENSOR_PHY0_VCC 0x4c 5095 /* enum: Voltage supplied to the QSFP #1 from their power supply: mV */ 5096 #define MC_CMD_SENSOR_PHY1_VCC 0x4d 5097 /* enum: Controller die temperature (TDIODE): degC */ 5098 #define MC_CMD_SENSOR_CONTROLLER_TDIODE_TEMP 0x4e 5099 /* enum: Board temperature (front): degC */ 5100 #define MC_CMD_SENSOR_BOARD_FRONT_TEMP 0x4f 5101 /* enum: Board temperature (back): degC */ 5102 #define MC_CMD_SENSOR_BOARD_BACK_TEMP 0x50 5103 /* enum: 1.8v power current: mA */ 5104 #define MC_CMD_SENSOR_IN_I1V8 0x51 5105 /* enum: 2.5v power current: mA */ 5106 #define MC_CMD_SENSOR_IN_I2V5 0x52 5107 /* enum: 3.3v power current: mA */ 5108 #define MC_CMD_SENSOR_IN_I3V3 0x53 5109 /* enum: 12v power current: mA */ 5110 #define MC_CMD_SENSOR_IN_I12V0 0x54 5111 /* enum: Not a sensor: reserved for the next page flag */ 5112 #define MC_CMD_SENSOR_PAGE2_NEXT 0x5f 5113 /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */ 5114 #define MC_CMD_SENSOR_ENTRY_OFST 4 5115 #define MC_CMD_SENSOR_ENTRY_LEN 8 5116 #define MC_CMD_SENSOR_ENTRY_LO_OFST 4 5117 #define MC_CMD_SENSOR_ENTRY_HI_OFST 8 5118 #define MC_CMD_SENSOR_ENTRY_MINNUM 0 5119 #define MC_CMD_SENSOR_ENTRY_MAXNUM 31 5120 5121 /* MC_CMD_SENSOR_INFO_EXT_OUT msgresponse */ 5122 #define MC_CMD_SENSOR_INFO_EXT_OUT_LENMIN 4 5123 #define MC_CMD_SENSOR_INFO_EXT_OUT_LENMAX 252 5124 #define MC_CMD_SENSOR_INFO_EXT_OUT_LEN(num) (4+8*(num)) 5125 #define MC_CMD_SENSOR_INFO_EXT_OUT_MASK_OFST 0 5126 #define MC_CMD_SENSOR_INFO_EXT_OUT_MASK_LEN 4 5127 /* Enum values, see field(s): */ 5128 /* MC_CMD_SENSOR_INFO_OUT */ 5129 #define MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_LBN 31 5130 #define MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_WIDTH 1 5131 /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */ 5132 /* MC_CMD_SENSOR_ENTRY_OFST 4 */ 5133 /* MC_CMD_SENSOR_ENTRY_LEN 8 */ 5134 /* MC_CMD_SENSOR_ENTRY_LO_OFST 4 */ 5135 /* MC_CMD_SENSOR_ENTRY_HI_OFST 8 */ 5136 /* MC_CMD_SENSOR_ENTRY_MINNUM 0 */ 5137 /* MC_CMD_SENSOR_ENTRY_MAXNUM 31 */ 5138 5139 /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF structuredef */ 5140 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_LEN 8 5141 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_OFST 0 5142 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LEN 2 5143 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LBN 0 5144 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_WIDTH 16 5145 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_OFST 2 5146 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LEN 2 5147 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LBN 16 5148 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_WIDTH 16 5149 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_OFST 4 5150 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LEN 2 5151 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LBN 32 5152 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_WIDTH 16 5153 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_OFST 6 5154 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LEN 2 5155 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LBN 48 5156 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_WIDTH 16 5157 5158 5159 /***********************************/ 5160 /* MC_CMD_READ_SENSORS 5161 * Returns the current reading from each sensor. DMAs an array of sensor 5162 * readings, in order of sensor type (but without gaps for unimplemented 5163 * sensors), into host memory. Each array element is a 5164 * MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF dword. 5165 * 5166 * If the request does not contain the LENGTH field then only sensors 0 to 30 5167 * are reported, to avoid DMA buffer overflow in older host software. If the 5168 * sensor reading require more space than the LENGTH allows, then return 5169 * EINVAL. 5170 * 5171 * The MC will send a SENSOREVT event every time any sensor changes state. The 5172 * driver is responsible for ensuring that it doesn't miss any events. The 5173 * board will function normally if all sensors are in STATE_OK or 5174 * STATE_WARNING. Otherwise the board should not be expected to function. 5175 */ 5176 #define MC_CMD_READ_SENSORS 0x42 5177 #undef MC_CMD_0x42_PRIVILEGE_CTG 5178 5179 #define MC_CMD_0x42_PRIVILEGE_CTG SRIOV_CTG_GENERAL 5180 5181 /* MC_CMD_READ_SENSORS_IN msgrequest */ 5182 #define MC_CMD_READ_SENSORS_IN_LEN 8 5183 /* DMA address of host buffer for sensor readings (must be 4Kbyte aligned). */ 5184 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_OFST 0 5185 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LEN 8 5186 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_OFST 0 5187 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_OFST 4 5188 5189 /* MC_CMD_READ_SENSORS_EXT_IN msgrequest */ 5190 #define MC_CMD_READ_SENSORS_EXT_IN_LEN 12 5191 /* DMA address of host buffer for sensor readings (must be 4Kbyte aligned). */ 5192 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_OFST 0 5193 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LEN 8 5194 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_OFST 0 5195 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_HI_OFST 4 5196 /* Size in bytes of host buffer. */ 5197 #define MC_CMD_READ_SENSORS_EXT_IN_LENGTH_OFST 8 5198 #define MC_CMD_READ_SENSORS_EXT_IN_LENGTH_LEN 4 5199 5200 /* MC_CMD_READ_SENSORS_OUT msgresponse */ 5201 #define MC_CMD_READ_SENSORS_OUT_LEN 0 5202 5203 /* MC_CMD_READ_SENSORS_EXT_OUT msgresponse */ 5204 #define MC_CMD_READ_SENSORS_EXT_OUT_LEN 0 5205 5206 /* MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF structuredef */ 5207 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_LEN 4 5208 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_OFST 0 5209 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LEN 2 5210 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LBN 0 5211 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_WIDTH 16 5212 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_OFST 2 5213 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LEN 1 5214 /* enum: Ok. */ 5215 #define MC_CMD_SENSOR_STATE_OK 0x0 5216 /* enum: Breached warning threshold. */ 5217 #define MC_CMD_SENSOR_STATE_WARNING 0x1 5218 /* enum: Breached fatal threshold. */ 5219 #define MC_CMD_SENSOR_STATE_FATAL 0x2 5220 /* enum: Fault with sensor. */ 5221 #define MC_CMD_SENSOR_STATE_BROKEN 0x3 5222 /* enum: Sensor is working but does not currently have a reading. */ 5223 #define MC_CMD_SENSOR_STATE_NO_READING 0x4 5224 /* enum: Sensor initialisation failed. */ 5225 #define MC_CMD_SENSOR_STATE_INIT_FAILED 0x5 5226 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LBN 16 5227 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_WIDTH 8 5228 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_OFST 3 5229 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_LEN 1 5230 /* Enum values, see field(s): */ 5231 /* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */ 5232 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_LBN 24 5233 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_WIDTH 8 5234 5235 5236 /***********************************/ 5237 /* MC_CMD_GET_PHY_STATE 5238 * Report current state of PHY. A 'zombie' PHY is a PHY that has failed to boot 5239 * (e.g. due to missing or corrupted firmware). Locks required: None. Return 5240 * code: 0 5241 */ 5242 #define MC_CMD_GET_PHY_STATE 0x43 5243 #undef MC_CMD_0x43_PRIVILEGE_CTG 5244 5245 #define MC_CMD_0x43_PRIVILEGE_CTG SRIOV_CTG_GENERAL 5246 5247 /* MC_CMD_GET_PHY_STATE_IN msgrequest */ 5248 #define MC_CMD_GET_PHY_STATE_IN_LEN 0 5249 5250 /* MC_CMD_GET_PHY_STATE_OUT msgresponse */ 5251 #define MC_CMD_GET_PHY_STATE_OUT_LEN 4 5252 #define MC_CMD_GET_PHY_STATE_OUT_STATE_OFST 0 5253 #define MC_CMD_GET_PHY_STATE_OUT_STATE_LEN 4 5254 /* enum: Ok. */ 5255 #define MC_CMD_PHY_STATE_OK 0x1 5256 /* enum: Faulty. */ 5257 #define MC_CMD_PHY_STATE_ZOMBIE 0x2 5258 5259 5260 /***********************************/ 5261 /* MC_CMD_SETUP_8021QBB 5262 * 802.1Qbb control. 8 Tx queues that map to priorities 0 - 7. Use all 1s to 5263 * disable 802.Qbb for a given priority. 5264 */ 5265 #define MC_CMD_SETUP_8021QBB 0x44 5266 5267 /* MC_CMD_SETUP_8021QBB_IN msgrequest */ 5268 #define MC_CMD_SETUP_8021QBB_IN_LEN 32 5269 #define MC_CMD_SETUP_8021QBB_IN_TXQS_OFST 0 5270 #define MC_CMD_SETUP_8021QBB_IN_TXQS_LEN 32 5271 5272 /* MC_CMD_SETUP_8021QBB_OUT msgresponse */ 5273 #define MC_CMD_SETUP_8021QBB_OUT_LEN 0 5274 5275 5276 /***********************************/ 5277 /* MC_CMD_WOL_FILTER_GET 5278 * Retrieve ID of any WoL filters. Locks required: None. Returns: 0, ENOSYS 5279 */ 5280 #define MC_CMD_WOL_FILTER_GET 0x45 5281 #undef MC_CMD_0x45_PRIVILEGE_CTG 5282 5283 #define MC_CMD_0x45_PRIVILEGE_CTG SRIOV_CTG_LINK 5284 5285 /* MC_CMD_WOL_FILTER_GET_IN msgrequest */ 5286 #define MC_CMD_WOL_FILTER_GET_IN_LEN 0 5287 5288 /* MC_CMD_WOL_FILTER_GET_OUT msgresponse */ 5289 #define MC_CMD_WOL_FILTER_GET_OUT_LEN 4 5290 #define MC_CMD_WOL_FILTER_GET_OUT_FILTER_ID_OFST 0 5291 #define MC_CMD_WOL_FILTER_GET_OUT_FILTER_ID_LEN 4 5292 5293 5294 /***********************************/ 5295 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD 5296 * Add a protocol offload to NIC for lights-out state. Locks required: None. 5297 * Returns: 0, ENOSYS 5298 */ 5299 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD 0x46 5300 #undef MC_CMD_0x46_PRIVILEGE_CTG 5301 5302 #define MC_CMD_0x46_PRIVILEGE_CTG SRIOV_CTG_LINK 5303 5304 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN msgrequest */ 5305 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMIN 8 5306 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMAX 252 5307 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LEN(num) (4+4*(num)) 5308 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 5309 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4 5310 #define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_ARP 0x1 /* enum */ 5311 #define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_NS 0x2 /* enum */ 5312 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_OFST 4 5313 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_LEN 4 5314 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MINNUM 1 5315 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MAXNUM 62 5316 5317 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP msgrequest */ 5318 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_LEN 14 5319 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */ 5320 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4 */ 5321 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_OFST 4 5322 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_LEN 6 5323 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_IP_OFST 10 5324 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_IP_LEN 4 5325 5326 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS msgrequest */ 5327 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_LEN 42 5328 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */ 5329 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4 */ 5330 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_OFST 4 5331 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_LEN 6 5332 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_OFST 10 5333 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_LEN 16 5334 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_OFST 26 5335 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_LEN 16 5336 5337 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT msgresponse */ 5338 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_LEN 4 5339 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_FILTER_ID_OFST 0 5340 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_FILTER_ID_LEN 4 5341 5342 5343 /***********************************/ 5344 /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD 5345 * Remove a protocol offload from NIC for lights-out state. Locks required: 5346 * None. Returns: 0, ENOSYS 5347 */ 5348 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD 0x47 5349 #undef MC_CMD_0x47_PRIVILEGE_CTG 5350 5351 #define MC_CMD_0x47_PRIVILEGE_CTG SRIOV_CTG_LINK 5352 5353 /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN msgrequest */ 5354 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_LEN 8 5355 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 5356 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4 5357 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_FILTER_ID_OFST 4 5358 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_FILTER_ID_LEN 4 5359 5360 /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT msgresponse */ 5361 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT_LEN 0 5362 5363 5364 /***********************************/ 5365 /* MC_CMD_MAC_RESET_RESTORE 5366 * Restore MAC after block reset. Locks required: None. Returns: 0. 5367 */ 5368 #define MC_CMD_MAC_RESET_RESTORE 0x48 5369 5370 /* MC_CMD_MAC_RESET_RESTORE_IN msgrequest */ 5371 #define MC_CMD_MAC_RESET_RESTORE_IN_LEN 0 5372 5373 /* MC_CMD_MAC_RESET_RESTORE_OUT msgresponse */ 5374 #define MC_CMD_MAC_RESET_RESTORE_OUT_LEN 0 5375 5376 5377 /***********************************/ 5378 /* MC_CMD_TESTASSERT 5379 * Deliberately trigger an assert-detonation in the firmware for testing 5380 * purposes (i.e. to allow tests that the driver copes gracefully). Locks 5381 * required: None Returns: 0 5382 */ 5383 #define MC_CMD_TESTASSERT 0x49 5384 #undef MC_CMD_0x49_PRIVILEGE_CTG 5385 5386 #define MC_CMD_0x49_PRIVILEGE_CTG SRIOV_CTG_ADMIN 5387 5388 /* MC_CMD_TESTASSERT_IN msgrequest */ 5389 #define MC_CMD_TESTASSERT_IN_LEN 0 5390 5391 /* MC_CMD_TESTASSERT_OUT msgresponse */ 5392 #define MC_CMD_TESTASSERT_OUT_LEN 0 5393 5394 /* MC_CMD_TESTASSERT_V2_IN msgrequest */ 5395 #define MC_CMD_TESTASSERT_V2_IN_LEN 4 5396 /* How to provoke the assertion */ 5397 #define MC_CMD_TESTASSERT_V2_IN_TYPE_OFST 0 5398 #define MC_CMD_TESTASSERT_V2_IN_TYPE_LEN 4 5399 /* enum: Assert using the FAIL_ASSERTION_WITH_USEFUL_VALUES macro. Unless 5400 * you're testing firmware, this is what you want. 5401 */ 5402 #define MC_CMD_TESTASSERT_V2_IN_FAIL_ASSERTION_WITH_USEFUL_VALUES 0x0 5403 /* enum: Assert using assert(0); */ 5404 #define MC_CMD_TESTASSERT_V2_IN_ASSERT_FALSE 0x1 5405 /* enum: Deliberately trigger a watchdog */ 5406 #define MC_CMD_TESTASSERT_V2_IN_WATCHDOG 0x2 5407 /* enum: Deliberately trigger a trap by loading from an invalid address */ 5408 #define MC_CMD_TESTASSERT_V2_IN_LOAD_TRAP 0x3 5409 /* enum: Deliberately trigger a trap by storing to an invalid address */ 5410 #define MC_CMD_TESTASSERT_V2_IN_STORE_TRAP 0x4 5411 /* enum: Jump to an invalid address */ 5412 #define MC_CMD_TESTASSERT_V2_IN_JUMP_TRAP 0x5 5413 5414 /* MC_CMD_TESTASSERT_V2_OUT msgresponse */ 5415 #define MC_CMD_TESTASSERT_V2_OUT_LEN 0 5416 5417 5418 /***********************************/ 5419 /* MC_CMD_WORKAROUND 5420 * Enable/Disable a given workaround. The mcfw will return EINVAL if it doesn't 5421 * understand the given workaround number - which should not be treated as a 5422 * hard error by client code. This op does not imply any semantics about each 5423 * workaround, that's between the driver and the mcfw on a per-workaround 5424 * basis. Locks required: None. Returns: 0, EINVAL . 5425 */ 5426 #define MC_CMD_WORKAROUND 0x4a 5427 #undef MC_CMD_0x4a_PRIVILEGE_CTG 5428 5429 #define MC_CMD_0x4a_PRIVILEGE_CTG SRIOV_CTG_ADMIN 5430 5431 /* MC_CMD_WORKAROUND_IN msgrequest */ 5432 #define MC_CMD_WORKAROUND_IN_LEN 8 5433 /* The enums here must correspond with those in MC_CMD_GET_WORKAROUND. */ 5434 #define MC_CMD_WORKAROUND_IN_TYPE_OFST 0 5435 #define MC_CMD_WORKAROUND_IN_TYPE_LEN 4 5436 /* enum: Bug 17230 work around. */ 5437 #define MC_CMD_WORKAROUND_BUG17230 0x1 5438 /* enum: Bug 35388 work around (unsafe EVQ writes). */ 5439 #define MC_CMD_WORKAROUND_BUG35388 0x2 5440 /* enum: Bug35017 workaround (A64 tables must be identity map) */ 5441 #define MC_CMD_WORKAROUND_BUG35017 0x3 5442 /* enum: Bug 41750 present (MC_CMD_TRIGGER_INTERRUPT won't work) */ 5443 #define MC_CMD_WORKAROUND_BUG41750 0x4 5444 /* enum: Bug 42008 present (Interrupts can overtake associated events). Caution 5445 * - before adding code that queries this workaround, remember that there's 5446 * released Monza firmware that doesn't understand MC_CMD_WORKAROUND_BUG42008, 5447 * and will hence (incorrectly) report that the bug doesn't exist. 5448 */ 5449 #define MC_CMD_WORKAROUND_BUG42008 0x5 5450 /* enum: Bug 26807 features present in firmware (multicast filter chaining) 5451 * This feature cannot be turned on/off while there are any filters already 5452 * present. The behaviour in such case depends on the acting client's privilege 5453 * level. If the client has the admin privilege, then all functions that have 5454 * filters installed will be FLRed and the FLR_DONE flag will be set. Otherwise 5455 * the command will fail with MC_CMD_ERR_FILTERS_PRESENT. 5456 */ 5457 #define MC_CMD_WORKAROUND_BUG26807 0x6 5458 /* enum: Bug 61265 work around (broken EVQ TMR writes). */ 5459 #define MC_CMD_WORKAROUND_BUG61265 0x7 5460 /* 0 = disable the workaround indicated by TYPE; any non-zero value = enable 5461 * the workaround 5462 */ 5463 #define MC_CMD_WORKAROUND_IN_ENABLED_OFST 4 5464 #define MC_CMD_WORKAROUND_IN_ENABLED_LEN 4 5465 5466 /* MC_CMD_WORKAROUND_OUT msgresponse */ 5467 #define MC_CMD_WORKAROUND_OUT_LEN 0 5468 5469 /* MC_CMD_WORKAROUND_EXT_OUT msgresponse: This response format will be used 5470 * when (TYPE == MC_CMD_WORKAROUND_BUG26807) 5471 */ 5472 #define MC_CMD_WORKAROUND_EXT_OUT_LEN 4 5473 #define MC_CMD_WORKAROUND_EXT_OUT_FLAGS_OFST 0 5474 #define MC_CMD_WORKAROUND_EXT_OUT_FLAGS_LEN 4 5475 #define MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN 0 5476 #define MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_WIDTH 1 5477 5478 5479 /***********************************/ 5480 /* MC_CMD_GET_PHY_MEDIA_INFO 5481 * Read media-specific data from PHY (e.g. SFP/SFP+ module ID information for 5482 * SFP+ PHYs). The 'media type' can be found via GET_PHY_CFG 5483 * (GET_PHY_CFG_OUT_MEDIA_TYPE); the valid 'page number' input values, and the 5484 * output data, are interpreted on a per-type basis. For SFP+: PAGE=0 or 1 5485 * returns a 128-byte block read from module I2C address 0xA0 offset 0 or 0x80. 5486 * Anything else: currently undefined. Locks required: None. Return code: 0. 5487 */ 5488 #define MC_CMD_GET_PHY_MEDIA_INFO 0x4b 5489 #undef MC_CMD_0x4b_PRIVILEGE_CTG 5490 5491 #define MC_CMD_0x4b_PRIVILEGE_CTG SRIOV_CTG_ADMIN 5492 5493 /* MC_CMD_GET_PHY_MEDIA_INFO_IN msgrequest */ 5494 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_LEN 4 5495 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_PAGE_OFST 0 5496 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_PAGE_LEN 4 5497 5498 /* MC_CMD_GET_PHY_MEDIA_INFO_OUT msgresponse */ 5499 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMIN 5 5500 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMAX 252 5501 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LEN(num) (4+1*(num)) 5502 /* in bytes */ 5503 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATALEN_OFST 0 5504 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATALEN_LEN 4 5505 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_OFST 4 5506 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_LEN 1 5507 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MINNUM 1 5508 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MAXNUM 248 5509 5510 5511 /***********************************/ 5512 /* MC_CMD_NVRAM_TEST 5513 * Test a particular NVRAM partition for valid contents (where "valid" depends 5514 * on the type of partition). 5515 */ 5516 #define MC_CMD_NVRAM_TEST 0x4c 5517 #undef MC_CMD_0x4c_PRIVILEGE_CTG 5518 5519 #define MC_CMD_0x4c_PRIVILEGE_CTG SRIOV_CTG_ADMIN 5520 5521 /* MC_CMD_NVRAM_TEST_IN msgrequest */ 5522 #define MC_CMD_NVRAM_TEST_IN_LEN 4 5523 #define MC_CMD_NVRAM_TEST_IN_TYPE_OFST 0 5524 #define MC_CMD_NVRAM_TEST_IN_TYPE_LEN 4 5525 /* Enum values, see field(s): */ 5526 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 5527 5528 /* MC_CMD_NVRAM_TEST_OUT msgresponse */ 5529 #define MC_CMD_NVRAM_TEST_OUT_LEN 4 5530 #define MC_CMD_NVRAM_TEST_OUT_RESULT_OFST 0 5531 #define MC_CMD_NVRAM_TEST_OUT_RESULT_LEN 4 5532 /* enum: Passed. */ 5533 #define MC_CMD_NVRAM_TEST_PASS 0x0 5534 /* enum: Failed. */ 5535 #define MC_CMD_NVRAM_TEST_FAIL 0x1 5536 /* enum: Not supported. */ 5537 #define MC_CMD_NVRAM_TEST_NOTSUPP 0x2 5538 5539 5540 /***********************************/ 5541 /* MC_CMD_MRSFP_TWEAK 5542 * Read status and/or set parameters for the 'mrsfp' driver in mr_rusty builds. 5543 * I2C I/O expander bits are always read; if equaliser parameters are supplied, 5544 * they are configured first. Locks required: None. Return code: 0, EINVAL. 5545 */ 5546 #define MC_CMD_MRSFP_TWEAK 0x4d 5547 5548 /* MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG msgrequest */ 5549 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_LEN 16 5550 /* 0-6 low->high de-emph. */ 5551 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_LEVEL_OFST 0 5552 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_LEVEL_LEN 4 5553 /* 0-8 low->high ref.V */ 5554 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_DT_CFG_OFST 4 5555 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_DT_CFG_LEN 4 5556 /* 0-8 0-8 low->high boost */ 5557 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_BOOST_OFST 8 5558 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_BOOST_LEN 4 5559 /* 0-8 low->high ref.V */ 5560 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_DT_CFG_OFST 12 5561 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_DT_CFG_LEN 4 5562 5563 /* MC_CMD_MRSFP_TWEAK_IN_READ_ONLY msgrequest */ 5564 #define MC_CMD_MRSFP_TWEAK_IN_READ_ONLY_LEN 0 5565 5566 /* MC_CMD_MRSFP_TWEAK_OUT msgresponse */ 5567 #define MC_CMD_MRSFP_TWEAK_OUT_LEN 12 5568 /* input bits */ 5569 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_INPUTS_OFST 0 5570 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_INPUTS_LEN 4 5571 /* output bits */ 5572 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_OUTPUTS_OFST 4 5573 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_OUTPUTS_LEN 4 5574 /* direction */ 5575 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OFST 8 5576 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_LEN 4 5577 /* enum: Out. */ 5578 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OUT 0x0 5579 /* enum: In. */ 5580 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_IN 0x1 5581 5582 5583 /***********************************/ 5584 /* MC_CMD_SENSOR_SET_LIMS 5585 * Adjusts the sensor limits. This is a warranty-voiding operation. Returns: 5586 * ENOENT if the sensor specified does not exist, EINVAL if the limits are out 5587 * of range. 5588 */ 5589 #define MC_CMD_SENSOR_SET_LIMS 0x4e 5590 #undef MC_CMD_0x4e_PRIVILEGE_CTG 5591 5592 #define MC_CMD_0x4e_PRIVILEGE_CTG SRIOV_CTG_INSECURE 5593 5594 /* MC_CMD_SENSOR_SET_LIMS_IN msgrequest */ 5595 #define MC_CMD_SENSOR_SET_LIMS_IN_LEN 20 5596 #define MC_CMD_SENSOR_SET_LIMS_IN_SENSOR_OFST 0 5597 #define MC_CMD_SENSOR_SET_LIMS_IN_SENSOR_LEN 4 5598 /* Enum values, see field(s): */ 5599 /* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */ 5600 /* interpretation is is sensor-specific. */ 5601 #define MC_CMD_SENSOR_SET_LIMS_IN_LOW0_OFST 4 5602 #define MC_CMD_SENSOR_SET_LIMS_IN_LOW0_LEN 4 5603 /* interpretation is is sensor-specific. */ 5604 #define MC_CMD_SENSOR_SET_LIMS_IN_HI0_OFST 8 5605 #define MC_CMD_SENSOR_SET_LIMS_IN_HI0_LEN 4 5606 /* interpretation is is sensor-specific. */ 5607 #define MC_CMD_SENSOR_SET_LIMS_IN_LOW1_OFST 12 5608 #define MC_CMD_SENSOR_SET_LIMS_IN_LOW1_LEN 4 5609 /* interpretation is is sensor-specific. */ 5610 #define MC_CMD_SENSOR_SET_LIMS_IN_HI1_OFST 16 5611 #define MC_CMD_SENSOR_SET_LIMS_IN_HI1_LEN 4 5612 5613 /* MC_CMD_SENSOR_SET_LIMS_OUT msgresponse */ 5614 #define MC_CMD_SENSOR_SET_LIMS_OUT_LEN 0 5615 5616 5617 /***********************************/ 5618 /* MC_CMD_GET_RESOURCE_LIMITS 5619 */ 5620 #define MC_CMD_GET_RESOURCE_LIMITS 0x4f 5621 5622 /* MC_CMD_GET_RESOURCE_LIMITS_IN msgrequest */ 5623 #define MC_CMD_GET_RESOURCE_LIMITS_IN_LEN 0 5624 5625 /* MC_CMD_GET_RESOURCE_LIMITS_OUT msgresponse */ 5626 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_LEN 16 5627 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_BUFTBL_OFST 0 5628 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_BUFTBL_LEN 4 5629 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_EVQ_OFST 4 5630 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_EVQ_LEN 4 5631 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_RXQ_OFST 8 5632 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_RXQ_LEN 4 5633 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_TXQ_OFST 12 5634 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_TXQ_LEN 4 5635 5636 5637 /***********************************/ 5638 /* MC_CMD_NVRAM_PARTITIONS 5639 * Reads the list of available virtual NVRAM partition types. Locks required: 5640 * none. Returns: 0, EINVAL (bad type). 5641 */ 5642 #define MC_CMD_NVRAM_PARTITIONS 0x51 5643 #undef MC_CMD_0x51_PRIVILEGE_CTG 5644 5645 #define MC_CMD_0x51_PRIVILEGE_CTG SRIOV_CTG_ADMIN 5646 5647 /* MC_CMD_NVRAM_PARTITIONS_IN msgrequest */ 5648 #define MC_CMD_NVRAM_PARTITIONS_IN_LEN 0 5649 5650 /* MC_CMD_NVRAM_PARTITIONS_OUT msgresponse */ 5651 #define MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN 4 5652 #define MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX 252 5653 #define MC_CMD_NVRAM_PARTITIONS_OUT_LEN(num) (4+4*(num)) 5654 /* total number of partitions */ 5655 #define MC_CMD_NVRAM_PARTITIONS_OUT_NUM_PARTITIONS_OFST 0 5656 #define MC_CMD_NVRAM_PARTITIONS_OUT_NUM_PARTITIONS_LEN 4 5657 /* type ID code for each of NUM_PARTITIONS partitions */ 5658 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_OFST 4 5659 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_LEN 4 5660 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MINNUM 0 5661 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MAXNUM 62 5662 5663 5664 /***********************************/ 5665 /* MC_CMD_NVRAM_METADATA 5666 * Reads soft metadata for a virtual NVRAM partition type. Locks required: 5667 * none. Returns: 0, EINVAL (bad type). 5668 */ 5669 #define MC_CMD_NVRAM_METADATA 0x52 5670 #undef MC_CMD_0x52_PRIVILEGE_CTG 5671 5672 #define MC_CMD_0x52_PRIVILEGE_CTG SRIOV_CTG_ADMIN 5673 5674 /* MC_CMD_NVRAM_METADATA_IN msgrequest */ 5675 #define MC_CMD_NVRAM_METADATA_IN_LEN 4 5676 /* Partition type ID code */ 5677 #define MC_CMD_NVRAM_METADATA_IN_TYPE_OFST 0 5678 #define MC_CMD_NVRAM_METADATA_IN_TYPE_LEN 4 5679 5680 /* MC_CMD_NVRAM_METADATA_OUT msgresponse */ 5681 #define MC_CMD_NVRAM_METADATA_OUT_LENMIN 20 5682 #define MC_CMD_NVRAM_METADATA_OUT_LENMAX 252 5683 #define MC_CMD_NVRAM_METADATA_OUT_LEN(num) (20+1*(num)) 5684 /* Partition type ID code */ 5685 #define MC_CMD_NVRAM_METADATA_OUT_TYPE_OFST 0 5686 #define MC_CMD_NVRAM_METADATA_OUT_TYPE_LEN 4 5687 #define MC_CMD_NVRAM_METADATA_OUT_FLAGS_OFST 4 5688 #define MC_CMD_NVRAM_METADATA_OUT_FLAGS_LEN 4 5689 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN 0 5690 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_WIDTH 1 5691 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_LBN 1 5692 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_WIDTH 1 5693 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_LBN 2 5694 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_WIDTH 1 5695 /* Subtype ID code for content of this partition */ 5696 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_OFST 8 5697 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_LEN 4 5698 /* 1st component of W.X.Y.Z version number for content of this partition */ 5699 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_W_OFST 12 5700 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_W_LEN 2 5701 /* 2nd component of W.X.Y.Z version number for content of this partition */ 5702 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_X_OFST 14 5703 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_X_LEN 2 5704 /* 3rd component of W.X.Y.Z version number for content of this partition */ 5705 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Y_OFST 16 5706 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Y_LEN 2 5707 /* 4th component of W.X.Y.Z version number for content of this partition */ 5708 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Z_OFST 18 5709 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Z_LEN 2 5710 /* Zero-terminated string describing the content of this partition */ 5711 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_OFST 20 5712 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_LEN 1 5713 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MINNUM 0 5714 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MAXNUM 232 5715 5716 5717 /***********************************/ 5718 /* MC_CMD_GET_MAC_ADDRESSES 5719 * Returns the base MAC, count and stride for the requesting function 5720 */ 5721 #define MC_CMD_GET_MAC_ADDRESSES 0x55 5722 #undef MC_CMD_0x55_PRIVILEGE_CTG 5723 5724 #define MC_CMD_0x55_PRIVILEGE_CTG SRIOV_CTG_GENERAL 5725 5726 /* MC_CMD_GET_MAC_ADDRESSES_IN msgrequest */ 5727 #define MC_CMD_GET_MAC_ADDRESSES_IN_LEN 0 5728 5729 /* MC_CMD_GET_MAC_ADDRESSES_OUT msgresponse */ 5730 #define MC_CMD_GET_MAC_ADDRESSES_OUT_LEN 16 5731 /* Base MAC address */ 5732 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE_OFST 0 5733 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE_LEN 6 5734 /* Padding */ 5735 #define MC_CMD_GET_MAC_ADDRESSES_OUT_RESERVED_OFST 6 5736 #define MC_CMD_GET_MAC_ADDRESSES_OUT_RESERVED_LEN 2 5737 /* Number of allocated MAC addresses */ 5738 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_COUNT_OFST 8 5739 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_COUNT_LEN 4 5740 /* Spacing of allocated MAC addresses */ 5741 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_STRIDE_OFST 12 5742 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_STRIDE_LEN 4 5743 5744 5745 /***********************************/ 5746 /* MC_CMD_CLP 5747 * Perform a CLP related operation 5748 */ 5749 #define MC_CMD_CLP 0x56 5750 #undef MC_CMD_0x56_PRIVILEGE_CTG 5751 5752 #define MC_CMD_0x56_PRIVILEGE_CTG SRIOV_CTG_ADMIN 5753 5754 /* MC_CMD_CLP_IN msgrequest */ 5755 #define MC_CMD_CLP_IN_LEN 4 5756 /* Sub operation */ 5757 #define MC_CMD_CLP_IN_OP_OFST 0 5758 #define MC_CMD_CLP_IN_OP_LEN 4 5759 /* enum: Return to factory default settings */ 5760 #define MC_CMD_CLP_OP_DEFAULT 0x1 5761 /* enum: Set MAC address */ 5762 #define MC_CMD_CLP_OP_SET_MAC 0x2 5763 /* enum: Get MAC address */ 5764 #define MC_CMD_CLP_OP_GET_MAC 0x3 5765 /* enum: Set UEFI/GPXE boot mode */ 5766 #define MC_CMD_CLP_OP_SET_BOOT 0x4 5767 /* enum: Get UEFI/GPXE boot mode */ 5768 #define MC_CMD_CLP_OP_GET_BOOT 0x5 5769 5770 /* MC_CMD_CLP_OUT msgresponse */ 5771 #define MC_CMD_CLP_OUT_LEN 0 5772 5773 /* MC_CMD_CLP_IN_DEFAULT msgrequest */ 5774 #define MC_CMD_CLP_IN_DEFAULT_LEN 4 5775 /* MC_CMD_CLP_IN_OP_OFST 0 */ 5776 /* MC_CMD_CLP_IN_OP_LEN 4 */ 5777 5778 /* MC_CMD_CLP_OUT_DEFAULT msgresponse */ 5779 #define MC_CMD_CLP_OUT_DEFAULT_LEN 0 5780 5781 /* MC_CMD_CLP_IN_SET_MAC msgrequest */ 5782 #define MC_CMD_CLP_IN_SET_MAC_LEN 12 5783 /* MC_CMD_CLP_IN_OP_OFST 0 */ 5784 /* MC_CMD_CLP_IN_OP_LEN 4 */ 5785 /* MAC address assigned to port */ 5786 #define MC_CMD_CLP_IN_SET_MAC_ADDR_OFST 4 5787 #define MC_CMD_CLP_IN_SET_MAC_ADDR_LEN 6 5788 /* Padding */ 5789 #define MC_CMD_CLP_IN_SET_MAC_RESERVED_OFST 10 5790 #define MC_CMD_CLP_IN_SET_MAC_RESERVED_LEN 2 5791 5792 /* MC_CMD_CLP_OUT_SET_MAC msgresponse */ 5793 #define MC_CMD_CLP_OUT_SET_MAC_LEN 0 5794 5795 /* MC_CMD_CLP_IN_GET_MAC msgrequest */ 5796 #define MC_CMD_CLP_IN_GET_MAC_LEN 4 5797 /* MC_CMD_CLP_IN_OP_OFST 0 */ 5798 /* MC_CMD_CLP_IN_OP_LEN 4 */ 5799 5800 /* MC_CMD_CLP_OUT_GET_MAC msgresponse */ 5801 #define MC_CMD_CLP_OUT_GET_MAC_LEN 8 5802 /* MAC address assigned to port */ 5803 #define MC_CMD_CLP_OUT_GET_MAC_ADDR_OFST 0 5804 #define MC_CMD_CLP_OUT_GET_MAC_ADDR_LEN 6 5805 /* Padding */ 5806 #define MC_CMD_CLP_OUT_GET_MAC_RESERVED_OFST 6 5807 #define MC_CMD_CLP_OUT_GET_MAC_RESERVED_LEN 2 5808 5809 /* MC_CMD_CLP_IN_SET_BOOT msgrequest */ 5810 #define MC_CMD_CLP_IN_SET_BOOT_LEN 5 5811 /* MC_CMD_CLP_IN_OP_OFST 0 */ 5812 /* MC_CMD_CLP_IN_OP_LEN 4 */ 5813 /* Boot flag */ 5814 #define MC_CMD_CLP_IN_SET_BOOT_FLAG_OFST 4 5815 #define MC_CMD_CLP_IN_SET_BOOT_FLAG_LEN 1 5816 5817 /* MC_CMD_CLP_OUT_SET_BOOT msgresponse */ 5818 #define MC_CMD_CLP_OUT_SET_BOOT_LEN 0 5819 5820 /* MC_CMD_CLP_IN_GET_BOOT msgrequest */ 5821 #define MC_CMD_CLP_IN_GET_BOOT_LEN 4 5822 /* MC_CMD_CLP_IN_OP_OFST 0 */ 5823 /* MC_CMD_CLP_IN_OP_LEN 4 */ 5824 5825 /* MC_CMD_CLP_OUT_GET_BOOT msgresponse */ 5826 #define MC_CMD_CLP_OUT_GET_BOOT_LEN 4 5827 /* Boot flag */ 5828 #define MC_CMD_CLP_OUT_GET_BOOT_FLAG_OFST 0 5829 #define MC_CMD_CLP_OUT_GET_BOOT_FLAG_LEN 1 5830 /* Padding */ 5831 #define MC_CMD_CLP_OUT_GET_BOOT_RESERVED_OFST 1 5832 #define MC_CMD_CLP_OUT_GET_BOOT_RESERVED_LEN 3 5833 5834 5835 /***********************************/ 5836 /* MC_CMD_MUM 5837 * Perform a MUM operation 5838 */ 5839 #define MC_CMD_MUM 0x57 5840 #undef MC_CMD_0x57_PRIVILEGE_CTG 5841 5842 #define MC_CMD_0x57_PRIVILEGE_CTG SRIOV_CTG_INSECURE 5843 5844 /* MC_CMD_MUM_IN msgrequest */ 5845 #define MC_CMD_MUM_IN_LEN 4 5846 #define MC_CMD_MUM_IN_OP_HDR_OFST 0 5847 #define MC_CMD_MUM_IN_OP_HDR_LEN 4 5848 #define MC_CMD_MUM_IN_OP_LBN 0 5849 #define MC_CMD_MUM_IN_OP_WIDTH 8 5850 /* enum: NULL MCDI command to MUM */ 5851 #define MC_CMD_MUM_OP_NULL 0x1 5852 /* enum: Get MUM version */ 5853 #define MC_CMD_MUM_OP_GET_VERSION 0x2 5854 /* enum: Issue raw I2C command to MUM */ 5855 #define MC_CMD_MUM_OP_RAW_CMD 0x3 5856 /* enum: Read from registers on devices connected to MUM. */ 5857 #define MC_CMD_MUM_OP_READ 0x4 5858 /* enum: Write to registers on devices connected to MUM. */ 5859 #define MC_CMD_MUM_OP_WRITE 0x5 5860 /* enum: Control UART logging. */ 5861 #define MC_CMD_MUM_OP_LOG 0x6 5862 /* enum: Operations on MUM GPIO lines */ 5863 #define MC_CMD_MUM_OP_GPIO 0x7 5864 /* enum: Get sensor readings from MUM */ 5865 #define MC_CMD_MUM_OP_READ_SENSORS 0x8 5866 /* enum: Initiate clock programming on the MUM */ 5867 #define MC_CMD_MUM_OP_PROGRAM_CLOCKS 0x9 5868 /* enum: Initiate FPGA load from flash on the MUM */ 5869 #define MC_CMD_MUM_OP_FPGA_LOAD 0xa 5870 /* enum: Request sensor reading from MUM ADC resulting from earlier request via 5871 * MUM ATB 5872 */ 5873 #define MC_CMD_MUM_OP_READ_ATB_SENSOR 0xb 5874 /* enum: Send commands relating to the QSFP ports via the MUM for PHY 5875 * operations 5876 */ 5877 #define MC_CMD_MUM_OP_QSFP 0xc 5878 /* enum: Request discrete and SODIMM DDR info (type, size, speed grade, voltage 5879 * level) from MUM 5880 */ 5881 #define MC_CMD_MUM_OP_READ_DDR_INFO 0xd 5882 5883 /* MC_CMD_MUM_IN_NULL msgrequest */ 5884 #define MC_CMD_MUM_IN_NULL_LEN 4 5885 /* MUM cmd header */ 5886 #define MC_CMD_MUM_IN_CMD_OFST 0 5887 #define MC_CMD_MUM_IN_CMD_LEN 4 5888 5889 /* MC_CMD_MUM_IN_GET_VERSION msgrequest */ 5890 #define MC_CMD_MUM_IN_GET_VERSION_LEN 4 5891 /* MUM cmd header */ 5892 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 5893 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 5894 5895 /* MC_CMD_MUM_IN_READ msgrequest */ 5896 #define MC_CMD_MUM_IN_READ_LEN 16 5897 /* MUM cmd header */ 5898 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 5899 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 5900 /* ID of (device connected to MUM) to read from registers of */ 5901 #define MC_CMD_MUM_IN_READ_DEVICE_OFST 4 5902 #define MC_CMD_MUM_IN_READ_DEVICE_LEN 4 5903 /* enum: Hittite HMC1035 clock generator on Sorrento board */ 5904 #define MC_CMD_MUM_DEV_HITTITE 0x1 5905 /* enum: Hittite HMC1035 clock generator for NIC-side on Sorrento board */ 5906 #define MC_CMD_MUM_DEV_HITTITE_NIC 0x2 5907 /* 32-bit address to read from */ 5908 #define MC_CMD_MUM_IN_READ_ADDR_OFST 8 5909 #define MC_CMD_MUM_IN_READ_ADDR_LEN 4 5910 /* Number of words to read. */ 5911 #define MC_CMD_MUM_IN_READ_NUMWORDS_OFST 12 5912 #define MC_CMD_MUM_IN_READ_NUMWORDS_LEN 4 5913 5914 /* MC_CMD_MUM_IN_WRITE msgrequest */ 5915 #define MC_CMD_MUM_IN_WRITE_LENMIN 16 5916 #define MC_CMD_MUM_IN_WRITE_LENMAX 252 5917 #define MC_CMD_MUM_IN_WRITE_LEN(num) (12+4*(num)) 5918 /* MUM cmd header */ 5919 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 5920 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 5921 /* ID of (device connected to MUM) to write to registers of */ 5922 #define MC_CMD_MUM_IN_WRITE_DEVICE_OFST 4 5923 #define MC_CMD_MUM_IN_WRITE_DEVICE_LEN 4 5924 /* enum: Hittite HMC1035 clock generator on Sorrento board */ 5925 /* MC_CMD_MUM_DEV_HITTITE 0x1 */ 5926 /* 32-bit address to write to */ 5927 #define MC_CMD_MUM_IN_WRITE_ADDR_OFST 8 5928 #define MC_CMD_MUM_IN_WRITE_ADDR_LEN 4 5929 /* Words to write */ 5930 #define MC_CMD_MUM_IN_WRITE_BUFFER_OFST 12 5931 #define MC_CMD_MUM_IN_WRITE_BUFFER_LEN 4 5932 #define MC_CMD_MUM_IN_WRITE_BUFFER_MINNUM 1 5933 #define MC_CMD_MUM_IN_WRITE_BUFFER_MAXNUM 60 5934 5935 /* MC_CMD_MUM_IN_RAW_CMD msgrequest */ 5936 #define MC_CMD_MUM_IN_RAW_CMD_LENMIN 17 5937 #define MC_CMD_MUM_IN_RAW_CMD_LENMAX 252 5938 #define MC_CMD_MUM_IN_RAW_CMD_LEN(num) (16+1*(num)) 5939 /* MUM cmd header */ 5940 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 5941 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 5942 /* MUM I2C cmd code */ 5943 #define MC_CMD_MUM_IN_RAW_CMD_CMD_CODE_OFST 4 5944 #define MC_CMD_MUM_IN_RAW_CMD_CMD_CODE_LEN 4 5945 /* Number of bytes to write */ 5946 #define MC_CMD_MUM_IN_RAW_CMD_NUM_WRITE_OFST 8 5947 #define MC_CMD_MUM_IN_RAW_CMD_NUM_WRITE_LEN 4 5948 /* Number of bytes to read */ 5949 #define MC_CMD_MUM_IN_RAW_CMD_NUM_READ_OFST 12 5950 #define MC_CMD_MUM_IN_RAW_CMD_NUM_READ_LEN 4 5951 /* Bytes to write */ 5952 #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_OFST 16 5953 #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_LEN 1 5954 #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_MINNUM 1 5955 #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_MAXNUM 236 5956 5957 /* MC_CMD_MUM_IN_LOG msgrequest */ 5958 #define MC_CMD_MUM_IN_LOG_LEN 8 5959 /* MUM cmd header */ 5960 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 5961 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 5962 #define MC_CMD_MUM_IN_LOG_OP_OFST 4 5963 #define MC_CMD_MUM_IN_LOG_OP_LEN 4 5964 #define MC_CMD_MUM_IN_LOG_OP_UART 0x1 /* enum */ 5965 5966 /* MC_CMD_MUM_IN_LOG_OP_UART msgrequest */ 5967 #define MC_CMD_MUM_IN_LOG_OP_UART_LEN 12 5968 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 5969 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 5970 /* MC_CMD_MUM_IN_LOG_OP_OFST 4 */ 5971 /* MC_CMD_MUM_IN_LOG_OP_LEN 4 */ 5972 /* Enable/disable debug output to UART */ 5973 #define MC_CMD_MUM_IN_LOG_OP_UART_ENABLE_OFST 8 5974 #define MC_CMD_MUM_IN_LOG_OP_UART_ENABLE_LEN 4 5975 5976 /* MC_CMD_MUM_IN_GPIO msgrequest */ 5977 #define MC_CMD_MUM_IN_GPIO_LEN 8 5978 /* MUM cmd header */ 5979 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 5980 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 5981 #define MC_CMD_MUM_IN_GPIO_HDR_OFST 4 5982 #define MC_CMD_MUM_IN_GPIO_HDR_LEN 4 5983 #define MC_CMD_MUM_IN_GPIO_OPCODE_LBN 0 5984 #define MC_CMD_MUM_IN_GPIO_OPCODE_WIDTH 8 5985 #define MC_CMD_MUM_IN_GPIO_IN_READ 0x0 /* enum */ 5986 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE 0x1 /* enum */ 5987 #define MC_CMD_MUM_IN_GPIO_OUT_READ 0x2 /* enum */ 5988 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE 0x3 /* enum */ 5989 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ 0x4 /* enum */ 5990 #define MC_CMD_MUM_IN_GPIO_OP 0x5 /* enum */ 5991 5992 /* MC_CMD_MUM_IN_GPIO_IN_READ msgrequest */ 5993 #define MC_CMD_MUM_IN_GPIO_IN_READ_LEN 8 5994 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 5995 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 5996 #define MC_CMD_MUM_IN_GPIO_IN_READ_HDR_OFST 4 5997 #define MC_CMD_MUM_IN_GPIO_IN_READ_HDR_LEN 4 5998 5999 /* MC_CMD_MUM_IN_GPIO_OUT_WRITE msgrequest */ 6000 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_LEN 16 6001 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6002 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 6003 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_HDR_OFST 4 6004 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_HDR_LEN 4 6005 /* The first 32-bit word to be written to the GPIO OUT register. */ 6006 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK1_OFST 8 6007 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK1_LEN 4 6008 /* The second 32-bit word to be written to the GPIO OUT register. */ 6009 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK2_OFST 12 6010 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK2_LEN 4 6011 6012 /* MC_CMD_MUM_IN_GPIO_OUT_READ msgrequest */ 6013 #define MC_CMD_MUM_IN_GPIO_OUT_READ_LEN 8 6014 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6015 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 6016 #define MC_CMD_MUM_IN_GPIO_OUT_READ_HDR_OFST 4 6017 #define MC_CMD_MUM_IN_GPIO_OUT_READ_HDR_LEN 4 6018 6019 /* MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE msgrequest */ 6020 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_LEN 16 6021 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6022 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 6023 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_HDR_OFST 4 6024 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_HDR_LEN 4 6025 /* The first 32-bit word to be written to the GPIO OUT ENABLE register. */ 6026 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK1_OFST 8 6027 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK1_LEN 4 6028 /* The second 32-bit word to be written to the GPIO OUT ENABLE register. */ 6029 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK2_OFST 12 6030 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK2_LEN 4 6031 6032 /* MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ msgrequest */ 6033 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_LEN 8 6034 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6035 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 6036 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_HDR_OFST 4 6037 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_HDR_LEN 4 6038 6039 /* MC_CMD_MUM_IN_GPIO_OP msgrequest */ 6040 #define MC_CMD_MUM_IN_GPIO_OP_LEN 8 6041 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6042 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 6043 #define MC_CMD_MUM_IN_GPIO_OP_HDR_OFST 4 6044 #define MC_CMD_MUM_IN_GPIO_OP_HDR_LEN 4 6045 #define MC_CMD_MUM_IN_GPIO_OP_BITWISE_OP_LBN 8 6046 #define MC_CMD_MUM_IN_GPIO_OP_BITWISE_OP_WIDTH 8 6047 #define MC_CMD_MUM_IN_GPIO_OP_OUT_READ 0x0 /* enum */ 6048 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE 0x1 /* enum */ 6049 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG 0x2 /* enum */ 6050 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE 0x3 /* enum */ 6051 #define MC_CMD_MUM_IN_GPIO_OP_GPIO_NUMBER_LBN 16 6052 #define MC_CMD_MUM_IN_GPIO_OP_GPIO_NUMBER_WIDTH 8 6053 6054 /* MC_CMD_MUM_IN_GPIO_OP_OUT_READ msgrequest */ 6055 #define MC_CMD_MUM_IN_GPIO_OP_OUT_READ_LEN 8 6056 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6057 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 6058 #define MC_CMD_MUM_IN_GPIO_OP_OUT_READ_HDR_OFST 4 6059 #define MC_CMD_MUM_IN_GPIO_OP_OUT_READ_HDR_LEN 4 6060 6061 /* MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE msgrequest */ 6062 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_LEN 8 6063 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6064 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 6065 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_HDR_OFST 4 6066 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_HDR_LEN 4 6067 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_WRITEBIT_LBN 24 6068 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_WRITEBIT_WIDTH 8 6069 6070 /* MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG msgrequest */ 6071 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_LEN 8 6072 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6073 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 6074 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_HDR_OFST 4 6075 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_HDR_LEN 4 6076 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_CFG_LBN 24 6077 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_CFG_WIDTH 8 6078 6079 /* MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE msgrequest */ 6080 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_LEN 8 6081 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6082 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 6083 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_HDR_OFST 4 6084 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_HDR_LEN 4 6085 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_ENABLEBIT_LBN 24 6086 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_ENABLEBIT_WIDTH 8 6087 6088 /* MC_CMD_MUM_IN_READ_SENSORS msgrequest */ 6089 #define MC_CMD_MUM_IN_READ_SENSORS_LEN 8 6090 /* MUM cmd header */ 6091 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6092 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 6093 #define MC_CMD_MUM_IN_READ_SENSORS_PARAMS_OFST 4 6094 #define MC_CMD_MUM_IN_READ_SENSORS_PARAMS_LEN 4 6095 #define MC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_LBN 0 6096 #define MC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_WIDTH 8 6097 #define MC_CMD_MUM_IN_READ_SENSORS_NUM_SENSORS_LBN 8 6098 #define MC_CMD_MUM_IN_READ_SENSORS_NUM_SENSORS_WIDTH 8 6099 6100 /* MC_CMD_MUM_IN_PROGRAM_CLOCKS msgrequest */ 6101 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_LEN 12 6102 /* MUM cmd header */ 6103 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6104 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 6105 /* Bit-mask of clocks to be programmed */ 6106 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_MASK_OFST 4 6107 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_MASK_LEN 4 6108 #define MC_CMD_MUM_CLOCK_ID_FPGA 0x0 /* enum */ 6109 #define MC_CMD_MUM_CLOCK_ID_DDR 0x1 /* enum */ 6110 #define MC_CMD_MUM_CLOCK_ID_NIC 0x2 /* enum */ 6111 /* Control flags for clock programming */ 6112 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_FLAGS_OFST 8 6113 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_FLAGS_LEN 4 6114 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_LBN 0 6115 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_WIDTH 1 6116 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_NIC_FROM_FPGA_LBN 1 6117 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_NIC_FROM_FPGA_WIDTH 1 6118 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_REF_FROM_XO_LBN 2 6119 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_REF_FROM_XO_WIDTH 1 6120 6121 /* MC_CMD_MUM_IN_FPGA_LOAD msgrequest */ 6122 #define MC_CMD_MUM_IN_FPGA_LOAD_LEN 8 6123 /* MUM cmd header */ 6124 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6125 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 6126 /* Enable/Disable FPGA config from flash */ 6127 #define MC_CMD_MUM_IN_FPGA_LOAD_ENABLE_OFST 4 6128 #define MC_CMD_MUM_IN_FPGA_LOAD_ENABLE_LEN 4 6129 6130 /* MC_CMD_MUM_IN_READ_ATB_SENSOR msgrequest */ 6131 #define MC_CMD_MUM_IN_READ_ATB_SENSOR_LEN 4 6132 /* MUM cmd header */ 6133 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6134 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 6135 6136 /* MC_CMD_MUM_IN_QSFP msgrequest */ 6137 #define MC_CMD_MUM_IN_QSFP_LEN 12 6138 /* MUM cmd header */ 6139 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6140 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 6141 #define MC_CMD_MUM_IN_QSFP_HDR_OFST 4 6142 #define MC_CMD_MUM_IN_QSFP_HDR_LEN 4 6143 #define MC_CMD_MUM_IN_QSFP_OPCODE_LBN 0 6144 #define MC_CMD_MUM_IN_QSFP_OPCODE_WIDTH 4 6145 #define MC_CMD_MUM_IN_QSFP_INIT 0x0 /* enum */ 6146 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE 0x1 /* enum */ 6147 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP 0x2 /* enum */ 6148 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO 0x3 /* enum */ 6149 #define MC_CMD_MUM_IN_QSFP_FILL_STATS 0x4 /* enum */ 6150 #define MC_CMD_MUM_IN_QSFP_POLL_BIST 0x5 /* enum */ 6151 #define MC_CMD_MUM_IN_QSFP_IDX_OFST 8 6152 #define MC_CMD_MUM_IN_QSFP_IDX_LEN 4 6153 6154 /* MC_CMD_MUM_IN_QSFP_INIT msgrequest */ 6155 #define MC_CMD_MUM_IN_QSFP_INIT_LEN 16 6156 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6157 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 6158 #define MC_CMD_MUM_IN_QSFP_INIT_HDR_OFST 4 6159 #define MC_CMD_MUM_IN_QSFP_INIT_HDR_LEN 4 6160 #define MC_CMD_MUM_IN_QSFP_INIT_IDX_OFST 8 6161 #define MC_CMD_MUM_IN_QSFP_INIT_IDX_LEN 4 6162 #define MC_CMD_MUM_IN_QSFP_INIT_CAGE_OFST 12 6163 #define MC_CMD_MUM_IN_QSFP_INIT_CAGE_LEN 4 6164 6165 /* MC_CMD_MUM_IN_QSFP_RECONFIGURE msgrequest */ 6166 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_LEN 24 6167 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6168 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 6169 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_HDR_OFST 4 6170 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_HDR_LEN 4 6171 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_IDX_OFST 8 6172 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_IDX_LEN 4 6173 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_TX_DISABLE_OFST 12 6174 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_TX_DISABLE_LEN 4 6175 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LANES_OFST 16 6176 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LANES_LEN 4 6177 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LINK_SPEED_OFST 20 6178 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LINK_SPEED_LEN 4 6179 6180 /* MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP msgrequest */ 6181 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_LEN 12 6182 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6183 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 6184 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_HDR_OFST 4 6185 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_HDR_LEN 4 6186 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_IDX_OFST 8 6187 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_IDX_LEN 4 6188 6189 /* MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO msgrequest */ 6190 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_LEN 16 6191 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6192 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 6193 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_HDR_OFST 4 6194 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_HDR_LEN 4 6195 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_IDX_OFST 8 6196 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_IDX_LEN 4 6197 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_PAGE_OFST 12 6198 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_PAGE_LEN 4 6199 6200 /* MC_CMD_MUM_IN_QSFP_FILL_STATS msgrequest */ 6201 #define MC_CMD_MUM_IN_QSFP_FILL_STATS_LEN 12 6202 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6203 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 6204 #define MC_CMD_MUM_IN_QSFP_FILL_STATS_HDR_OFST 4 6205 #define MC_CMD_MUM_IN_QSFP_FILL_STATS_HDR_LEN 4 6206 #define MC_CMD_MUM_IN_QSFP_FILL_STATS_IDX_OFST 8 6207 #define MC_CMD_MUM_IN_QSFP_FILL_STATS_IDX_LEN 4 6208 6209 /* MC_CMD_MUM_IN_QSFP_POLL_BIST msgrequest */ 6210 #define MC_CMD_MUM_IN_QSFP_POLL_BIST_LEN 12 6211 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6212 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 6213 #define MC_CMD_MUM_IN_QSFP_POLL_BIST_HDR_OFST 4 6214 #define MC_CMD_MUM_IN_QSFP_POLL_BIST_HDR_LEN 4 6215 #define MC_CMD_MUM_IN_QSFP_POLL_BIST_IDX_OFST 8 6216 #define MC_CMD_MUM_IN_QSFP_POLL_BIST_IDX_LEN 4 6217 6218 /* MC_CMD_MUM_IN_READ_DDR_INFO msgrequest */ 6219 #define MC_CMD_MUM_IN_READ_DDR_INFO_LEN 4 6220 /* MUM cmd header */ 6221 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6222 /* MC_CMD_MUM_IN_CMD_LEN 4 */ 6223 6224 /* MC_CMD_MUM_OUT msgresponse */ 6225 #define MC_CMD_MUM_OUT_LEN 0 6226 6227 /* MC_CMD_MUM_OUT_NULL msgresponse */ 6228 #define MC_CMD_MUM_OUT_NULL_LEN 0 6229 6230 /* MC_CMD_MUM_OUT_GET_VERSION msgresponse */ 6231 #define MC_CMD_MUM_OUT_GET_VERSION_LEN 12 6232 #define MC_CMD_MUM_OUT_GET_VERSION_FIRMWARE_OFST 0 6233 #define MC_CMD_MUM_OUT_GET_VERSION_FIRMWARE_LEN 4 6234 #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_OFST 4 6235 #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LEN 8 6236 #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LO_OFST 4 6237 #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_HI_OFST 8 6238 6239 /* MC_CMD_MUM_OUT_RAW_CMD msgresponse */ 6240 #define MC_CMD_MUM_OUT_RAW_CMD_LENMIN 1 6241 #define MC_CMD_MUM_OUT_RAW_CMD_LENMAX 252 6242 #define MC_CMD_MUM_OUT_RAW_CMD_LEN(num) (0+1*(num)) 6243 /* returned data */ 6244 #define MC_CMD_MUM_OUT_RAW_CMD_DATA_OFST 0 6245 #define MC_CMD_MUM_OUT_RAW_CMD_DATA_LEN 1 6246 #define MC_CMD_MUM_OUT_RAW_CMD_DATA_MINNUM 1 6247 #define MC_CMD_MUM_OUT_RAW_CMD_DATA_MAXNUM 252 6248 6249 /* MC_CMD_MUM_OUT_READ msgresponse */ 6250 #define MC_CMD_MUM_OUT_READ_LENMIN 4 6251 #define MC_CMD_MUM_OUT_READ_LENMAX 252 6252 #define MC_CMD_MUM_OUT_READ_LEN(num) (0+4*(num)) 6253 #define MC_CMD_MUM_OUT_READ_BUFFER_OFST 0 6254 #define MC_CMD_MUM_OUT_READ_BUFFER_LEN 4 6255 #define MC_CMD_MUM_OUT_READ_BUFFER_MINNUM 1 6256 #define MC_CMD_MUM_OUT_READ_BUFFER_MAXNUM 63 6257 6258 /* MC_CMD_MUM_OUT_WRITE msgresponse */ 6259 #define MC_CMD_MUM_OUT_WRITE_LEN 0 6260 6261 /* MC_CMD_MUM_OUT_LOG msgresponse */ 6262 #define MC_CMD_MUM_OUT_LOG_LEN 0 6263 6264 /* MC_CMD_MUM_OUT_LOG_OP_UART msgresponse */ 6265 #define MC_CMD_MUM_OUT_LOG_OP_UART_LEN 0 6266 6267 /* MC_CMD_MUM_OUT_GPIO_IN_READ msgresponse */ 6268 #define MC_CMD_MUM_OUT_GPIO_IN_READ_LEN 8 6269 /* The first 32-bit word read from the GPIO IN register. */ 6270 #define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK1_OFST 0 6271 #define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK1_LEN 4 6272 /* The second 32-bit word read from the GPIO IN register. */ 6273 #define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK2_OFST 4 6274 #define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK2_LEN 4 6275 6276 /* MC_CMD_MUM_OUT_GPIO_OUT_WRITE msgresponse */ 6277 #define MC_CMD_MUM_OUT_GPIO_OUT_WRITE_LEN 0 6278 6279 /* MC_CMD_MUM_OUT_GPIO_OUT_READ msgresponse */ 6280 #define MC_CMD_MUM_OUT_GPIO_OUT_READ_LEN 8 6281 /* The first 32-bit word read from the GPIO OUT register. */ 6282 #define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK1_OFST 0 6283 #define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK1_LEN 4 6284 /* The second 32-bit word read from the GPIO OUT register. */ 6285 #define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK2_OFST 4 6286 #define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK2_LEN 4 6287 6288 /* MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_WRITE msgresponse */ 6289 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_WRITE_LEN 0 6290 6291 /* MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ msgresponse */ 6292 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_LEN 8 6293 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK1_OFST 0 6294 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK1_LEN 4 6295 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK2_OFST 4 6296 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK2_LEN 4 6297 6298 /* MC_CMD_MUM_OUT_GPIO_OP_OUT_READ msgresponse */ 6299 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_LEN 4 6300 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_BIT_READ_OFST 0 6301 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_BIT_READ_LEN 4 6302 6303 /* MC_CMD_MUM_OUT_GPIO_OP_OUT_WRITE msgresponse */ 6304 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_WRITE_LEN 0 6305 6306 /* MC_CMD_MUM_OUT_GPIO_OP_OUT_CONFIG msgresponse */ 6307 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_CONFIG_LEN 0 6308 6309 /* MC_CMD_MUM_OUT_GPIO_OP_OUT_ENABLE msgresponse */ 6310 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_ENABLE_LEN 0 6311 6312 /* MC_CMD_MUM_OUT_READ_SENSORS msgresponse */ 6313 #define MC_CMD_MUM_OUT_READ_SENSORS_LENMIN 4 6314 #define MC_CMD_MUM_OUT_READ_SENSORS_LENMAX 252 6315 #define MC_CMD_MUM_OUT_READ_SENSORS_LEN(num) (0+4*(num)) 6316 #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_OFST 0 6317 #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_LEN 4 6318 #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_MINNUM 1 6319 #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_MAXNUM 63 6320 #define MC_CMD_MUM_OUT_READ_SENSORS_READING_LBN 0 6321 #define MC_CMD_MUM_OUT_READ_SENSORS_READING_WIDTH 16 6322 #define MC_CMD_MUM_OUT_READ_SENSORS_STATE_LBN 16 6323 #define MC_CMD_MUM_OUT_READ_SENSORS_STATE_WIDTH 8 6324 #define MC_CMD_MUM_OUT_READ_SENSORS_TYPE_LBN 24 6325 #define MC_CMD_MUM_OUT_READ_SENSORS_TYPE_WIDTH 8 6326 6327 /* MC_CMD_MUM_OUT_PROGRAM_CLOCKS msgresponse */ 6328 #define MC_CMD_MUM_OUT_PROGRAM_CLOCKS_LEN 4 6329 #define MC_CMD_MUM_OUT_PROGRAM_CLOCKS_OK_MASK_OFST 0 6330 #define MC_CMD_MUM_OUT_PROGRAM_CLOCKS_OK_MASK_LEN 4 6331 6332 /* MC_CMD_MUM_OUT_FPGA_LOAD msgresponse */ 6333 #define MC_CMD_MUM_OUT_FPGA_LOAD_LEN 0 6334 6335 /* MC_CMD_MUM_OUT_READ_ATB_SENSOR msgresponse */ 6336 #define MC_CMD_MUM_OUT_READ_ATB_SENSOR_LEN 4 6337 #define MC_CMD_MUM_OUT_READ_ATB_SENSOR_RESULT_OFST 0 6338 #define MC_CMD_MUM_OUT_READ_ATB_SENSOR_RESULT_LEN 4 6339 6340 /* MC_CMD_MUM_OUT_QSFP_INIT msgresponse */ 6341 #define MC_CMD_MUM_OUT_QSFP_INIT_LEN 0 6342 6343 /* MC_CMD_MUM_OUT_QSFP_RECONFIGURE msgresponse */ 6344 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_LEN 8 6345 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LP_CAP_OFST 0 6346 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LP_CAP_LEN 4 6347 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_FLAGS_OFST 4 6348 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_FLAGS_LEN 4 6349 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_LBN 0 6350 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_WIDTH 1 6351 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_LBN 1 6352 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_WIDTH 1 6353 6354 /* MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP msgresponse */ 6355 #define MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_LEN 4 6356 #define MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_PORT_PHY_LP_CAP_OFST 0 6357 #define MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_PORT_PHY_LP_CAP_LEN 4 6358 6359 /* MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO msgresponse */ 6360 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LENMIN 5 6361 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LENMAX 252 6362 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LEN(num) (4+1*(num)) 6363 /* in bytes */ 6364 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATALEN_OFST 0 6365 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATALEN_LEN 4 6366 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_OFST 4 6367 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_LEN 1 6368 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_MINNUM 1 6369 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_MAXNUM 248 6370 6371 /* MC_CMD_MUM_OUT_QSFP_FILL_STATS msgresponse */ 6372 #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_LEN 8 6373 #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PMA_PMD_LINK_UP_OFST 0 6374 #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PMA_PMD_LINK_UP_LEN 4 6375 #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PCS_LINK_UP_OFST 4 6376 #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PCS_LINK_UP_LEN 4 6377 6378 /* MC_CMD_MUM_OUT_QSFP_POLL_BIST msgresponse */ 6379 #define MC_CMD_MUM_OUT_QSFP_POLL_BIST_LEN 4 6380 #define MC_CMD_MUM_OUT_QSFP_POLL_BIST_TEST_OFST 0 6381 #define MC_CMD_MUM_OUT_QSFP_POLL_BIST_TEST_LEN 4 6382 6383 /* MC_CMD_MUM_OUT_READ_DDR_INFO msgresponse */ 6384 #define MC_CMD_MUM_OUT_READ_DDR_INFO_LENMIN 24 6385 #define MC_CMD_MUM_OUT_READ_DDR_INFO_LENMAX 248 6386 #define MC_CMD_MUM_OUT_READ_DDR_INFO_LEN(num) (8+8*(num)) 6387 /* Discrete (soldered) DDR resistor strap info */ 6388 #define MC_CMD_MUM_OUT_READ_DDR_INFO_DISCRETE_DDR_INFO_OFST 0 6389 #define MC_CMD_MUM_OUT_READ_DDR_INFO_DISCRETE_DDR_INFO_LEN 4 6390 #define MC_CMD_MUM_OUT_READ_DDR_INFO_VRATIO_LBN 0 6391 #define MC_CMD_MUM_OUT_READ_DDR_INFO_VRATIO_WIDTH 16 6392 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED1_LBN 16 6393 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED1_WIDTH 16 6394 /* Number of SODIMM info records */ 6395 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_RECORDS_OFST 4 6396 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_RECORDS_LEN 4 6397 /* Array of SODIMM info records */ 6398 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_OFST 8 6399 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LEN 8 6400 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LO_OFST 8 6401 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_HI_OFST 12 6402 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MINNUM 2 6403 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MAXNUM 30 6404 #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK_ID_LBN 0 6405 #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK_ID_WIDTH 8 6406 /* enum: SODIMM bank 1 (Top SODIMM for Sorrento) */ 6407 #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK1 0x0 6408 /* enum: SODIMM bank 2 (Bottom SODDIMM for Sorrento) */ 6409 #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK2 0x1 6410 /* enum: Total number of SODIMM banks */ 6411 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_BANKS 0x2 6412 #define MC_CMD_MUM_OUT_READ_DDR_INFO_TYPE_LBN 8 6413 #define MC_CMD_MUM_OUT_READ_DDR_INFO_TYPE_WIDTH 8 6414 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RANK_LBN 16 6415 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RANK_WIDTH 4 6416 #define MC_CMD_MUM_OUT_READ_DDR_INFO_VOLTAGE_LBN 20 6417 #define MC_CMD_MUM_OUT_READ_DDR_INFO_VOLTAGE_WIDTH 4 6418 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NOT_POWERED 0x0 /* enum */ 6419 #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V25 0x1 /* enum */ 6420 #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V35 0x2 /* enum */ 6421 #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V5 0x3 /* enum */ 6422 /* enum: Values 5-15 are reserved for future usage */ 6423 #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V8 0x4 6424 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SIZE_LBN 24 6425 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SIZE_WIDTH 8 6426 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SPEED_LBN 32 6427 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SPEED_WIDTH 16 6428 #define MC_CMD_MUM_OUT_READ_DDR_INFO_STATE_LBN 48 6429 #define MC_CMD_MUM_OUT_READ_DDR_INFO_STATE_WIDTH 4 6430 /* enum: No module present */ 6431 #define MC_CMD_MUM_OUT_READ_DDR_INFO_ABSENT 0x0 6432 /* enum: Module present supported and powered on */ 6433 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_POWERED 0x1 6434 /* enum: Module present but bad type */ 6435 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_TYPE 0x2 6436 /* enum: Module present but incompatible voltage */ 6437 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_VOLTAGE 0x3 6438 /* enum: Module present but unknown SPD */ 6439 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_SPD 0x4 6440 /* enum: Module present but slot cannot support it */ 6441 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_SLOT 0x5 6442 /* enum: Modules may or may not be present, but cannot establish contact by I2C 6443 */ 6444 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NOT_REACHABLE 0x6 6445 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED2_LBN 52 6446 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED2_WIDTH 12 6447 6448 /* MC_CMD_RESOURCE_SPECIFIER enum */ 6449 /* enum: Any */ 6450 #define MC_CMD_RESOURCE_INSTANCE_ANY 0xffffffff 6451 /* enum: None */ 6452 #define MC_CMD_RESOURCE_INSTANCE_NONE 0xfffffffe 6453 6454 /* EVB_PORT_ID structuredef */ 6455 #define EVB_PORT_ID_LEN 4 6456 #define EVB_PORT_ID_PORT_ID_OFST 0 6457 #define EVB_PORT_ID_PORT_ID_LEN 4 6458 /* enum: An invalid port handle. */ 6459 #define EVB_PORT_ID_NULL 0x0 6460 /* enum: The port assigned to this function.. */ 6461 #define EVB_PORT_ID_ASSIGNED 0x1000000 6462 /* enum: External network port 0 */ 6463 #define EVB_PORT_ID_MAC0 0x2000000 6464 /* enum: External network port 1 */ 6465 #define EVB_PORT_ID_MAC1 0x2000001 6466 /* enum: External network port 2 */ 6467 #define EVB_PORT_ID_MAC2 0x2000002 6468 /* enum: External network port 3 */ 6469 #define EVB_PORT_ID_MAC3 0x2000003 6470 #define EVB_PORT_ID_PORT_ID_LBN 0 6471 #define EVB_PORT_ID_PORT_ID_WIDTH 32 6472 6473 /* EVB_VLAN_TAG structuredef */ 6474 #define EVB_VLAN_TAG_LEN 2 6475 /* The VLAN tag value */ 6476 #define EVB_VLAN_TAG_VLAN_ID_LBN 0 6477 #define EVB_VLAN_TAG_VLAN_ID_WIDTH 12 6478 #define EVB_VLAN_TAG_MODE_LBN 12 6479 #define EVB_VLAN_TAG_MODE_WIDTH 4 6480 /* enum: Insert the VLAN. */ 6481 #define EVB_VLAN_TAG_INSERT 0x0 6482 /* enum: Replace the VLAN if already present. */ 6483 #define EVB_VLAN_TAG_REPLACE 0x1 6484 6485 /* BUFTBL_ENTRY structuredef */ 6486 #define BUFTBL_ENTRY_LEN 12 6487 /* the owner ID */ 6488 #define BUFTBL_ENTRY_OID_OFST 0 6489 #define BUFTBL_ENTRY_OID_LEN 2 6490 #define BUFTBL_ENTRY_OID_LBN 0 6491 #define BUFTBL_ENTRY_OID_WIDTH 16 6492 /* the page parameter as one of ESE_DZ_SMC_PAGE_SIZE_ */ 6493 #define BUFTBL_ENTRY_PGSZ_OFST 2 6494 #define BUFTBL_ENTRY_PGSZ_LEN 2 6495 #define BUFTBL_ENTRY_PGSZ_LBN 16 6496 #define BUFTBL_ENTRY_PGSZ_WIDTH 16 6497 /* the raw 64-bit address field from the SMC, not adjusted for page size */ 6498 #define BUFTBL_ENTRY_RAWADDR_OFST 4 6499 #define BUFTBL_ENTRY_RAWADDR_LEN 8 6500 #define BUFTBL_ENTRY_RAWADDR_LO_OFST 4 6501 #define BUFTBL_ENTRY_RAWADDR_HI_OFST 8 6502 #define BUFTBL_ENTRY_RAWADDR_LBN 32 6503 #define BUFTBL_ENTRY_RAWADDR_WIDTH 64 6504 6505 /* NVRAM_PARTITION_TYPE structuredef */ 6506 #define NVRAM_PARTITION_TYPE_LEN 2 6507 #define NVRAM_PARTITION_TYPE_ID_OFST 0 6508 #define NVRAM_PARTITION_TYPE_ID_LEN 2 6509 /* enum: Primary MC firmware partition */ 6510 #define NVRAM_PARTITION_TYPE_MC_FIRMWARE 0x100 6511 /* enum: Secondary MC firmware partition */ 6512 #define NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP 0x200 6513 /* enum: Expansion ROM partition */ 6514 #define NVRAM_PARTITION_TYPE_EXPANSION_ROM 0x300 6515 /* enum: Static configuration TLV partition */ 6516 #define NVRAM_PARTITION_TYPE_STATIC_CONFIG 0x400 6517 /* enum: Dynamic configuration TLV partition */ 6518 #define NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG 0x500 6519 /* enum: Expansion ROM configuration data for port 0 */ 6520 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0 0x600 6521 /* enum: Synonym for EXPROM_CONFIG_PORT0 as used in pmap files */ 6522 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG 0x600 6523 /* enum: Expansion ROM configuration data for port 1 */ 6524 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1 0x601 6525 /* enum: Expansion ROM configuration data for port 2 */ 6526 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2 0x602 6527 /* enum: Expansion ROM configuration data for port 3 */ 6528 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3 0x603 6529 /* enum: Non-volatile log output partition */ 6530 #define NVRAM_PARTITION_TYPE_LOG 0x700 6531 /* enum: Non-volatile log output of second core on dual-core device */ 6532 #define NVRAM_PARTITION_TYPE_LOG_SLAVE 0x701 6533 /* enum: Device state dump output partition */ 6534 #define NVRAM_PARTITION_TYPE_DUMP 0x800 6535 /* enum: Application license key storage partition */ 6536 #define NVRAM_PARTITION_TYPE_LICENSE 0x900 6537 /* enum: Start of range used for PHY partitions (low 8 bits are the PHY ID) */ 6538 #define NVRAM_PARTITION_TYPE_PHY_MIN 0xa00 6539 /* enum: End of range used for PHY partitions (low 8 bits are the PHY ID) */ 6540 #define NVRAM_PARTITION_TYPE_PHY_MAX 0xaff 6541 /* enum: Primary FPGA partition */ 6542 #define NVRAM_PARTITION_TYPE_FPGA 0xb00 6543 /* enum: Secondary FPGA partition */ 6544 #define NVRAM_PARTITION_TYPE_FPGA_BACKUP 0xb01 6545 /* enum: FC firmware partition */ 6546 #define NVRAM_PARTITION_TYPE_FC_FIRMWARE 0xb02 6547 /* enum: FC License partition */ 6548 #define NVRAM_PARTITION_TYPE_FC_LICENSE 0xb03 6549 /* enum: Non-volatile log output partition for FC */ 6550 #define NVRAM_PARTITION_TYPE_FC_LOG 0xb04 6551 /* enum: MUM firmware partition */ 6552 #define NVRAM_PARTITION_TYPE_MUM_FIRMWARE 0xc00 6553 /* enum: SUC firmware partition (this is intentionally an alias of 6554 * MUM_FIRMWARE) 6555 */ 6556 #define NVRAM_PARTITION_TYPE_SUC_FIRMWARE 0xc00 6557 /* enum: MUM Non-volatile log output partition. */ 6558 #define NVRAM_PARTITION_TYPE_MUM_LOG 0xc01 6559 /* enum: MUM Application table partition. */ 6560 #define NVRAM_PARTITION_TYPE_MUM_APPTABLE 0xc02 6561 /* enum: MUM boot rom partition. */ 6562 #define NVRAM_PARTITION_TYPE_MUM_BOOT_ROM 0xc03 6563 /* enum: MUM production signatures & calibration rom partition. */ 6564 #define NVRAM_PARTITION_TYPE_MUM_PROD_ROM 0xc04 6565 /* enum: MUM user signatures & calibration rom partition. */ 6566 #define NVRAM_PARTITION_TYPE_MUM_USER_ROM 0xc05 6567 /* enum: MUM fuses and lockbits partition. */ 6568 #define NVRAM_PARTITION_TYPE_MUM_FUSELOCK 0xc06 6569 /* enum: UEFI expansion ROM if separate from PXE */ 6570 #define NVRAM_PARTITION_TYPE_EXPANSION_UEFI 0xd00 6571 /* enum: Used by the expansion ROM for logging */ 6572 #define NVRAM_PARTITION_TYPE_PXE_LOG 0x1000 6573 /* enum: Used for XIP code of shmbooted images */ 6574 #define NVRAM_PARTITION_TYPE_XIP_SCRATCH 0x1100 6575 /* enum: Spare partition 2 */ 6576 #define NVRAM_PARTITION_TYPE_SPARE_2 0x1200 6577 /* enum: Manufacturing partition. Used during manufacture to pass information 6578 * between XJTAG and Manftest. 6579 */ 6580 #define NVRAM_PARTITION_TYPE_MANUFACTURING 0x1300 6581 /* enum: Spare partition 4 */ 6582 #define NVRAM_PARTITION_TYPE_SPARE_4 0x1400 6583 /* enum: Spare partition 5 */ 6584 #define NVRAM_PARTITION_TYPE_SPARE_5 0x1500 6585 /* enum: Partition for reporting MC status. See mc_flash_layout.h 6586 * medford_mc_status_hdr_t for layout on Medford. 6587 */ 6588 #define NVRAM_PARTITION_TYPE_STATUS 0x1600 6589 /* enum: Spare partition 13 */ 6590 #define NVRAM_PARTITION_TYPE_SPARE_13 0x1700 6591 /* enum: Spare partition 14 */ 6592 #define NVRAM_PARTITION_TYPE_SPARE_14 0x1800 6593 /* enum: Spare partition 15 */ 6594 #define NVRAM_PARTITION_TYPE_SPARE_15 0x1900 6595 /* enum: Spare partition 16 */ 6596 #define NVRAM_PARTITION_TYPE_SPARE_16 0x1a00 6597 /* enum: Factory defaults for dynamic configuration */ 6598 #define NVRAM_PARTITION_TYPE_DYNCONFIG_DEFAULTS 0x1b00 6599 /* enum: Factory defaults for expansion ROM configuration */ 6600 #define NVRAM_PARTITION_TYPE_ROMCONFIG_DEFAULTS 0x1c00 6601 /* enum: Start of reserved value range (firmware may use for any purpose) */ 6602 #define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MIN 0xff00 6603 /* enum: End of reserved value range (firmware may use for any purpose) */ 6604 #define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MAX 0xfffd 6605 /* enum: Recovery partition map (provided if real map is missing or corrupt) */ 6606 #define NVRAM_PARTITION_TYPE_RECOVERY_MAP 0xfffe 6607 /* enum: Partition map (real map as stored in flash) */ 6608 #define NVRAM_PARTITION_TYPE_PARTITION_MAP 0xffff 6609 #define NVRAM_PARTITION_TYPE_ID_LBN 0 6610 #define NVRAM_PARTITION_TYPE_ID_WIDTH 16 6611 6612 /* LICENSED_APP_ID structuredef */ 6613 #define LICENSED_APP_ID_LEN 4 6614 #define LICENSED_APP_ID_ID_OFST 0 6615 #define LICENSED_APP_ID_ID_LEN 4 6616 /* enum: OpenOnload */ 6617 #define LICENSED_APP_ID_ONLOAD 0x1 6618 /* enum: PTP timestamping */ 6619 #define LICENSED_APP_ID_PTP 0x2 6620 /* enum: SolarCapture Pro */ 6621 #define LICENSED_APP_ID_SOLARCAPTURE_PRO 0x4 6622 /* enum: SolarSecure filter engine */ 6623 #define LICENSED_APP_ID_SOLARSECURE 0x8 6624 /* enum: Performance monitor */ 6625 #define LICENSED_APP_ID_PERF_MONITOR 0x10 6626 /* enum: SolarCapture Live */ 6627 #define LICENSED_APP_ID_SOLARCAPTURE_LIVE 0x20 6628 /* enum: Capture SolarSystem */ 6629 #define LICENSED_APP_ID_CAPTURE_SOLARSYSTEM 0x40 6630 /* enum: Network Access Control */ 6631 #define LICENSED_APP_ID_NETWORK_ACCESS_CONTROL 0x80 6632 /* enum: TCP Direct */ 6633 #define LICENSED_APP_ID_TCP_DIRECT 0x100 6634 /* enum: Low Latency */ 6635 #define LICENSED_APP_ID_LOW_LATENCY 0x200 6636 /* enum: SolarCapture Tap */ 6637 #define LICENSED_APP_ID_SOLARCAPTURE_TAP 0x400 6638 /* enum: Capture SolarSystem 40G */ 6639 #define LICENSED_APP_ID_CAPTURE_SOLARSYSTEM_40G 0x800 6640 /* enum: Capture SolarSystem 1G */ 6641 #define LICENSED_APP_ID_CAPTURE_SOLARSYSTEM_1G 0x1000 6642 #define LICENSED_APP_ID_ID_LBN 0 6643 #define LICENSED_APP_ID_ID_WIDTH 32 6644 6645 /* LICENSED_FEATURES structuredef */ 6646 #define LICENSED_FEATURES_LEN 8 6647 /* Bitmask of licensed firmware features */ 6648 #define LICENSED_FEATURES_MASK_OFST 0 6649 #define LICENSED_FEATURES_MASK_LEN 8 6650 #define LICENSED_FEATURES_MASK_LO_OFST 0 6651 #define LICENSED_FEATURES_MASK_HI_OFST 4 6652 #define LICENSED_FEATURES_RX_CUT_THROUGH_LBN 0 6653 #define LICENSED_FEATURES_RX_CUT_THROUGH_WIDTH 1 6654 #define LICENSED_FEATURES_PIO_LBN 1 6655 #define LICENSED_FEATURES_PIO_WIDTH 1 6656 #define LICENSED_FEATURES_EVQ_TIMER_LBN 2 6657 #define LICENSED_FEATURES_EVQ_TIMER_WIDTH 1 6658 #define LICENSED_FEATURES_CLOCK_LBN 3 6659 #define LICENSED_FEATURES_CLOCK_WIDTH 1 6660 #define LICENSED_FEATURES_RX_TIMESTAMPS_LBN 4 6661 #define LICENSED_FEATURES_RX_TIMESTAMPS_WIDTH 1 6662 #define LICENSED_FEATURES_TX_TIMESTAMPS_LBN 5 6663 #define LICENSED_FEATURES_TX_TIMESTAMPS_WIDTH 1 6664 #define LICENSED_FEATURES_RX_SNIFF_LBN 6 6665 #define LICENSED_FEATURES_RX_SNIFF_WIDTH 1 6666 #define LICENSED_FEATURES_TX_SNIFF_LBN 7 6667 #define LICENSED_FEATURES_TX_SNIFF_WIDTH 1 6668 #define LICENSED_FEATURES_PROXY_FILTER_OPS_LBN 8 6669 #define LICENSED_FEATURES_PROXY_FILTER_OPS_WIDTH 1 6670 #define LICENSED_FEATURES_EVENT_CUT_THROUGH_LBN 9 6671 #define LICENSED_FEATURES_EVENT_CUT_THROUGH_WIDTH 1 6672 #define LICENSED_FEATURES_MASK_LBN 0 6673 #define LICENSED_FEATURES_MASK_WIDTH 64 6674 6675 /* LICENSED_V3_APPS structuredef */ 6676 #define LICENSED_V3_APPS_LEN 8 6677 /* Bitmask of licensed applications */ 6678 #define LICENSED_V3_APPS_MASK_OFST 0 6679 #define LICENSED_V3_APPS_MASK_LEN 8 6680 #define LICENSED_V3_APPS_MASK_LO_OFST 0 6681 #define LICENSED_V3_APPS_MASK_HI_OFST 4 6682 #define LICENSED_V3_APPS_ONLOAD_LBN 0 6683 #define LICENSED_V3_APPS_ONLOAD_WIDTH 1 6684 #define LICENSED_V3_APPS_PTP_LBN 1 6685 #define LICENSED_V3_APPS_PTP_WIDTH 1 6686 #define LICENSED_V3_APPS_SOLARCAPTURE_PRO_LBN 2 6687 #define LICENSED_V3_APPS_SOLARCAPTURE_PRO_WIDTH 1 6688 #define LICENSED_V3_APPS_SOLARSECURE_LBN 3 6689 #define LICENSED_V3_APPS_SOLARSECURE_WIDTH 1 6690 #define LICENSED_V3_APPS_PERF_MONITOR_LBN 4 6691 #define LICENSED_V3_APPS_PERF_MONITOR_WIDTH 1 6692 #define LICENSED_V3_APPS_SOLARCAPTURE_LIVE_LBN 5 6693 #define LICENSED_V3_APPS_SOLARCAPTURE_LIVE_WIDTH 1 6694 #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_LBN 6 6695 #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_WIDTH 1 6696 #define LICENSED_V3_APPS_NETWORK_ACCESS_CONTROL_LBN 7 6697 #define LICENSED_V3_APPS_NETWORK_ACCESS_CONTROL_WIDTH 1 6698 #define LICENSED_V3_APPS_TCP_DIRECT_LBN 8 6699 #define LICENSED_V3_APPS_TCP_DIRECT_WIDTH 1 6700 #define LICENSED_V3_APPS_LOW_LATENCY_LBN 9 6701 #define LICENSED_V3_APPS_LOW_LATENCY_WIDTH 1 6702 #define LICENSED_V3_APPS_SOLARCAPTURE_TAP_LBN 10 6703 #define LICENSED_V3_APPS_SOLARCAPTURE_TAP_WIDTH 1 6704 #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_40G_LBN 11 6705 #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_40G_WIDTH 1 6706 #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_1G_LBN 12 6707 #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_1G_WIDTH 1 6708 #define LICENSED_V3_APPS_MASK_LBN 0 6709 #define LICENSED_V3_APPS_MASK_WIDTH 64 6710 6711 /* LICENSED_V3_FEATURES structuredef */ 6712 #define LICENSED_V3_FEATURES_LEN 8 6713 /* Bitmask of licensed firmware features */ 6714 #define LICENSED_V3_FEATURES_MASK_OFST 0 6715 #define LICENSED_V3_FEATURES_MASK_LEN 8 6716 #define LICENSED_V3_FEATURES_MASK_LO_OFST 0 6717 #define LICENSED_V3_FEATURES_MASK_HI_OFST 4 6718 #define LICENSED_V3_FEATURES_RX_CUT_THROUGH_LBN 0 6719 #define LICENSED_V3_FEATURES_RX_CUT_THROUGH_WIDTH 1 6720 #define LICENSED_V3_FEATURES_PIO_LBN 1 6721 #define LICENSED_V3_FEATURES_PIO_WIDTH 1 6722 #define LICENSED_V3_FEATURES_EVQ_TIMER_LBN 2 6723 #define LICENSED_V3_FEATURES_EVQ_TIMER_WIDTH 1 6724 #define LICENSED_V3_FEATURES_CLOCK_LBN 3 6725 #define LICENSED_V3_FEATURES_CLOCK_WIDTH 1 6726 #define LICENSED_V3_FEATURES_RX_TIMESTAMPS_LBN 4 6727 #define LICENSED_V3_FEATURES_RX_TIMESTAMPS_WIDTH 1 6728 #define LICENSED_V3_FEATURES_TX_TIMESTAMPS_LBN 5 6729 #define LICENSED_V3_FEATURES_TX_TIMESTAMPS_WIDTH 1 6730 #define LICENSED_V3_FEATURES_RX_SNIFF_LBN 6 6731 #define LICENSED_V3_FEATURES_RX_SNIFF_WIDTH 1 6732 #define LICENSED_V3_FEATURES_TX_SNIFF_LBN 7 6733 #define LICENSED_V3_FEATURES_TX_SNIFF_WIDTH 1 6734 #define LICENSED_V3_FEATURES_PROXY_FILTER_OPS_LBN 8 6735 #define LICENSED_V3_FEATURES_PROXY_FILTER_OPS_WIDTH 1 6736 #define LICENSED_V3_FEATURES_EVENT_CUT_THROUGH_LBN 9 6737 #define LICENSED_V3_FEATURES_EVENT_CUT_THROUGH_WIDTH 1 6738 #define LICENSED_V3_FEATURES_MASK_LBN 0 6739 #define LICENSED_V3_FEATURES_MASK_WIDTH 64 6740 6741 /* TX_TIMESTAMP_EVENT structuredef */ 6742 #define TX_TIMESTAMP_EVENT_LEN 6 6743 /* lower 16 bits of timestamp data */ 6744 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_OFST 0 6745 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_LEN 2 6746 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_LBN 0 6747 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_WIDTH 16 6748 /* Type of TX event, ordinary TX completion, low or high part of TX timestamp 6749 */ 6750 #define TX_TIMESTAMP_EVENT_TX_EV_TYPE_OFST 3 6751 #define TX_TIMESTAMP_EVENT_TX_EV_TYPE_LEN 1 6752 /* enum: This is a TX completion event, not a timestamp */ 6753 #define TX_TIMESTAMP_EVENT_TX_EV_COMPLETION 0x0 6754 /* enum: This is the low part of a TX timestamp event */ 6755 #define TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_LO 0x51 6756 /* enum: This is the high part of a TX timestamp event */ 6757 #define TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_HI 0x52 6758 #define TX_TIMESTAMP_EVENT_TX_EV_TYPE_LBN 24 6759 #define TX_TIMESTAMP_EVENT_TX_EV_TYPE_WIDTH 8 6760 /* upper 16 bits of timestamp data */ 6761 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_OFST 4 6762 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_LEN 2 6763 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_LBN 32 6764 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_WIDTH 16 6765 6766 /* RSS_MODE structuredef */ 6767 #define RSS_MODE_LEN 1 6768 /* The RSS mode for a particular packet type is a value from 0 - 15 which can 6769 * be considered as 4 bits selecting which fields are included in the hash. (A 6770 * value 0 effectively disables RSS spreading for the packet type.) The YAML 6771 * generation tools require this structure to be a whole number of bytes wide, 6772 * but only 4 bits are relevant. 6773 */ 6774 #define RSS_MODE_HASH_SELECTOR_OFST 0 6775 #define RSS_MODE_HASH_SELECTOR_LEN 1 6776 #define RSS_MODE_HASH_SRC_ADDR_LBN 0 6777 #define RSS_MODE_HASH_SRC_ADDR_WIDTH 1 6778 #define RSS_MODE_HASH_DST_ADDR_LBN 1 6779 #define RSS_MODE_HASH_DST_ADDR_WIDTH 1 6780 #define RSS_MODE_HASH_SRC_PORT_LBN 2 6781 #define RSS_MODE_HASH_SRC_PORT_WIDTH 1 6782 #define RSS_MODE_HASH_DST_PORT_LBN 3 6783 #define RSS_MODE_HASH_DST_PORT_WIDTH 1 6784 #define RSS_MODE_HASH_SELECTOR_LBN 0 6785 #define RSS_MODE_HASH_SELECTOR_WIDTH 8 6786 6787 /* CTPIO_STATS_MAP structuredef */ 6788 #define CTPIO_STATS_MAP_LEN 4 6789 /* The (function relative) VI number */ 6790 #define CTPIO_STATS_MAP_VI_OFST 0 6791 #define CTPIO_STATS_MAP_VI_LEN 2 6792 #define CTPIO_STATS_MAP_VI_LBN 0 6793 #define CTPIO_STATS_MAP_VI_WIDTH 16 6794 /* The target bucket for the VI */ 6795 #define CTPIO_STATS_MAP_BUCKET_OFST 2 6796 #define CTPIO_STATS_MAP_BUCKET_LEN 2 6797 #define CTPIO_STATS_MAP_BUCKET_LBN 16 6798 #define CTPIO_STATS_MAP_BUCKET_WIDTH 16 6799 6800 6801 /***********************************/ 6802 /* MC_CMD_READ_REGS 6803 * Get a dump of the MCPU registers 6804 */ 6805 #define MC_CMD_READ_REGS 0x50 6806 #undef MC_CMD_0x50_PRIVILEGE_CTG 6807 6808 #define MC_CMD_0x50_PRIVILEGE_CTG SRIOV_CTG_INSECURE 6809 6810 /* MC_CMD_READ_REGS_IN msgrequest */ 6811 #define MC_CMD_READ_REGS_IN_LEN 0 6812 6813 /* MC_CMD_READ_REGS_OUT msgresponse */ 6814 #define MC_CMD_READ_REGS_OUT_LEN 308 6815 /* Whether the corresponding register entry contains a valid value */ 6816 #define MC_CMD_READ_REGS_OUT_MASK_OFST 0 6817 #define MC_CMD_READ_REGS_OUT_MASK_LEN 16 6818 /* Same order as MIPS GDB (r0-r31, sr, lo, hi, bad, cause, 32 x float, fsr, 6819 * fir, fp) 6820 */ 6821 #define MC_CMD_READ_REGS_OUT_REGS_OFST 16 6822 #define MC_CMD_READ_REGS_OUT_REGS_LEN 4 6823 #define MC_CMD_READ_REGS_OUT_REGS_NUM 73 6824 6825 6826 /***********************************/ 6827 /* MC_CMD_INIT_EVQ 6828 * Set up an event queue according to the supplied parameters. The IN arguments 6829 * end with an address for each 4k of host memory required to back the EVQ. 6830 */ 6831 #define MC_CMD_INIT_EVQ 0x80 6832 #undef MC_CMD_0x80_PRIVILEGE_CTG 6833 6834 #define MC_CMD_0x80_PRIVILEGE_CTG SRIOV_CTG_GENERAL 6835 6836 /* MC_CMD_INIT_EVQ_IN msgrequest */ 6837 #define MC_CMD_INIT_EVQ_IN_LENMIN 44 6838 #define MC_CMD_INIT_EVQ_IN_LENMAX 548 6839 #define MC_CMD_INIT_EVQ_IN_LEN(num) (36+8*(num)) 6840 /* Size, in entries */ 6841 #define MC_CMD_INIT_EVQ_IN_SIZE_OFST 0 6842 #define MC_CMD_INIT_EVQ_IN_SIZE_LEN 4 6843 /* Desired instance. Must be set to a specific instance, which is a function 6844 * local queue index. 6845 */ 6846 #define MC_CMD_INIT_EVQ_IN_INSTANCE_OFST 4 6847 #define MC_CMD_INIT_EVQ_IN_INSTANCE_LEN 4 6848 /* The initial timer value. The load value is ignored if the timer mode is DIS. 6849 */ 6850 #define MC_CMD_INIT_EVQ_IN_TMR_LOAD_OFST 8 6851 #define MC_CMD_INIT_EVQ_IN_TMR_LOAD_LEN 4 6852 /* The reload value is ignored in one-shot modes */ 6853 #define MC_CMD_INIT_EVQ_IN_TMR_RELOAD_OFST 12 6854 #define MC_CMD_INIT_EVQ_IN_TMR_RELOAD_LEN 4 6855 /* tbd */ 6856 #define MC_CMD_INIT_EVQ_IN_FLAGS_OFST 16 6857 #define MC_CMD_INIT_EVQ_IN_FLAGS_LEN 4 6858 #define MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_LBN 0 6859 #define MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_WIDTH 1 6860 #define MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_LBN 1 6861 #define MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_WIDTH 1 6862 #define MC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_LBN 2 6863 #define MC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_WIDTH 1 6864 #define MC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_LBN 3 6865 #define MC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_WIDTH 1 6866 #define MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_LBN 4 6867 #define MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_WIDTH 1 6868 #define MC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_LBN 5 6869 #define MC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_WIDTH 1 6870 #define MC_CMD_INIT_EVQ_IN_FLAG_USE_TIMER_LBN 6 6871 #define MC_CMD_INIT_EVQ_IN_FLAG_USE_TIMER_WIDTH 1 6872 #define MC_CMD_INIT_EVQ_IN_TMR_MODE_OFST 20 6873 #define MC_CMD_INIT_EVQ_IN_TMR_MODE_LEN 4 6874 /* enum: Disabled */ 6875 #define MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS 0x0 6876 /* enum: Immediate */ 6877 #define MC_CMD_INIT_EVQ_IN_TMR_IMMED_START 0x1 6878 /* enum: Triggered */ 6879 #define MC_CMD_INIT_EVQ_IN_TMR_TRIG_START 0x2 6880 /* enum: Hold-off */ 6881 #define MC_CMD_INIT_EVQ_IN_TMR_INT_HLDOFF 0x3 6882 /* Target EVQ for wakeups if in wakeup mode. */ 6883 #define MC_CMD_INIT_EVQ_IN_TARGET_EVQ_OFST 24 6884 #define MC_CMD_INIT_EVQ_IN_TARGET_EVQ_LEN 4 6885 /* Target interrupt if in interrupting mode (note union with target EVQ). Use 6886 * MC_CMD_RESOURCE_INSTANCE_ANY unless a specific one required for test 6887 * purposes. 6888 */ 6889 #define MC_CMD_INIT_EVQ_IN_IRQ_NUM_OFST 24 6890 #define MC_CMD_INIT_EVQ_IN_IRQ_NUM_LEN 4 6891 /* Event Counter Mode. */ 6892 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_OFST 28 6893 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_LEN 4 6894 /* enum: Disabled */ 6895 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS 0x0 6896 /* enum: Disabled */ 6897 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_RX 0x1 6898 /* enum: Disabled */ 6899 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_TX 0x2 6900 /* enum: Disabled */ 6901 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_RXTX 0x3 6902 /* Event queue packet count threshold. */ 6903 #define MC_CMD_INIT_EVQ_IN_COUNT_THRSHLD_OFST 32 6904 #define MC_CMD_INIT_EVQ_IN_COUNT_THRSHLD_LEN 4 6905 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 6906 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_OFST 36 6907 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LEN 8 6908 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LO_OFST 36 6909 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_HI_OFST 40 6910 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MINNUM 1 6911 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MAXNUM 64 6912 6913 /* MC_CMD_INIT_EVQ_OUT msgresponse */ 6914 #define MC_CMD_INIT_EVQ_OUT_LEN 4 6915 /* Only valid if INTRFLAG was true */ 6916 #define MC_CMD_INIT_EVQ_OUT_IRQ_OFST 0 6917 #define MC_CMD_INIT_EVQ_OUT_IRQ_LEN 4 6918 6919 /* MC_CMD_INIT_EVQ_V2_IN msgrequest */ 6920 #define MC_CMD_INIT_EVQ_V2_IN_LENMIN 44 6921 #define MC_CMD_INIT_EVQ_V2_IN_LENMAX 548 6922 #define MC_CMD_INIT_EVQ_V2_IN_LEN(num) (36+8*(num)) 6923 /* Size, in entries */ 6924 #define MC_CMD_INIT_EVQ_V2_IN_SIZE_OFST 0 6925 #define MC_CMD_INIT_EVQ_V2_IN_SIZE_LEN 4 6926 /* Desired instance. Must be set to a specific instance, which is a function 6927 * local queue index. 6928 */ 6929 #define MC_CMD_INIT_EVQ_V2_IN_INSTANCE_OFST 4 6930 #define MC_CMD_INIT_EVQ_V2_IN_INSTANCE_LEN 4 6931 /* The initial timer value. The load value is ignored if the timer mode is DIS. 6932 */ 6933 #define MC_CMD_INIT_EVQ_V2_IN_TMR_LOAD_OFST 8 6934 #define MC_CMD_INIT_EVQ_V2_IN_TMR_LOAD_LEN 4 6935 /* The reload value is ignored in one-shot modes */ 6936 #define MC_CMD_INIT_EVQ_V2_IN_TMR_RELOAD_OFST 12 6937 #define MC_CMD_INIT_EVQ_V2_IN_TMR_RELOAD_LEN 4 6938 /* tbd */ 6939 #define MC_CMD_INIT_EVQ_V2_IN_FLAGS_OFST 16 6940 #define MC_CMD_INIT_EVQ_V2_IN_FLAGS_LEN 4 6941 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_INTERRUPTING_LBN 0 6942 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_INTERRUPTING_WIDTH 1 6943 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_RPTR_DOS_LBN 1 6944 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_RPTR_DOS_WIDTH 1 6945 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_INT_ARMD_LBN 2 6946 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_INT_ARMD_WIDTH 1 6947 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_CUT_THRU_LBN 3 6948 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_CUT_THRU_WIDTH 1 6949 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_RX_MERGE_LBN 4 6950 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_RX_MERGE_WIDTH 1 6951 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TX_MERGE_LBN 5 6952 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TX_MERGE_WIDTH 1 6953 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_USE_TIMER_LBN 6 6954 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_USE_TIMER_WIDTH 1 6955 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_LBN 7 6956 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_WIDTH 4 6957 /* enum: All initialisation flags specified by host. */ 6958 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_MANUAL 0x0 6959 /* enum: MEDFORD only. Certain initialisation flags specified by host may be 6960 * over-ridden by firmware based on licenses and firmware variant in order to 6961 * provide the lowest latency achievable. See 6962 * MC_CMD_INIT_EVQ_V2/MC_CMD_INIT_EVQ_V2_OUT/FLAGS for list of affected flags. 6963 */ 6964 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_LOW_LATENCY 0x1 6965 /* enum: MEDFORD only. Certain initialisation flags specified by host may be 6966 * over-ridden by firmware based on licenses and firmware variant in order to 6967 * provide the best throughput achievable. See 6968 * MC_CMD_INIT_EVQ_V2/MC_CMD_INIT_EVQ_V2_OUT/FLAGS for list of affected flags. 6969 */ 6970 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_THROUGHPUT 0x2 6971 /* enum: MEDFORD only. Certain initialisation flags may be over-ridden by 6972 * firmware based on licenses and firmware variant. See 6973 * MC_CMD_INIT_EVQ_V2/MC_CMD_INIT_EVQ_V2_OUT/FLAGS for list of affected flags. 6974 */ 6975 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_AUTO 0x3 6976 #define MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_OFST 20 6977 #define MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_LEN 4 6978 /* enum: Disabled */ 6979 #define MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_DIS 0x0 6980 /* enum: Immediate */ 6981 #define MC_CMD_INIT_EVQ_V2_IN_TMR_IMMED_START 0x1 6982 /* enum: Triggered */ 6983 #define MC_CMD_INIT_EVQ_V2_IN_TMR_TRIG_START 0x2 6984 /* enum: Hold-off */ 6985 #define MC_CMD_INIT_EVQ_V2_IN_TMR_INT_HLDOFF 0x3 6986 /* Target EVQ for wakeups if in wakeup mode. */ 6987 #define MC_CMD_INIT_EVQ_V2_IN_TARGET_EVQ_OFST 24 6988 #define MC_CMD_INIT_EVQ_V2_IN_TARGET_EVQ_LEN 4 6989 /* Target interrupt if in interrupting mode (note union with target EVQ). Use 6990 * MC_CMD_RESOURCE_INSTANCE_ANY unless a specific one required for test 6991 * purposes. 6992 */ 6993 #define MC_CMD_INIT_EVQ_V2_IN_IRQ_NUM_OFST 24 6994 #define MC_CMD_INIT_EVQ_V2_IN_IRQ_NUM_LEN 4 6995 /* Event Counter Mode. */ 6996 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_OFST 28 6997 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_LEN 4 6998 /* enum: Disabled */ 6999 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_DIS 0x0 7000 /* enum: Disabled */ 7001 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_RX 0x1 7002 /* enum: Disabled */ 7003 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_TX 0x2 7004 /* enum: Disabled */ 7005 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_RXTX 0x3 7006 /* Event queue packet count threshold. */ 7007 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_THRSHLD_OFST 32 7008 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_THRSHLD_LEN 4 7009 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 7010 #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_OFST 36 7011 #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_LEN 8 7012 #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_LO_OFST 36 7013 #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_HI_OFST 40 7014 #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_MINNUM 1 7015 #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_MAXNUM 64 7016 7017 /* MC_CMD_INIT_EVQ_V2_OUT msgresponse */ 7018 #define MC_CMD_INIT_EVQ_V2_OUT_LEN 8 7019 /* Only valid if INTRFLAG was true */ 7020 #define MC_CMD_INIT_EVQ_V2_OUT_IRQ_OFST 0 7021 #define MC_CMD_INIT_EVQ_V2_OUT_IRQ_LEN 4 7022 /* Actual configuration applied on the card */ 7023 #define MC_CMD_INIT_EVQ_V2_OUT_FLAGS_OFST 4 7024 #define MC_CMD_INIT_EVQ_V2_OUT_FLAGS_LEN 4 7025 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_CUT_THRU_LBN 0 7026 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_CUT_THRU_WIDTH 1 7027 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RX_MERGE_LBN 1 7028 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RX_MERGE_WIDTH 1 7029 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_TX_MERGE_LBN 2 7030 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_TX_MERGE_WIDTH 1 7031 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RXQ_FORCE_EV_MERGING_LBN 3 7032 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RXQ_FORCE_EV_MERGING_WIDTH 1 7033 7034 /* QUEUE_CRC_MODE structuredef */ 7035 #define QUEUE_CRC_MODE_LEN 1 7036 #define QUEUE_CRC_MODE_MODE_LBN 0 7037 #define QUEUE_CRC_MODE_MODE_WIDTH 4 7038 /* enum: No CRC. */ 7039 #define QUEUE_CRC_MODE_NONE 0x0 7040 /* enum: CRC Fiber channel over ethernet. */ 7041 #define QUEUE_CRC_MODE_FCOE 0x1 7042 /* enum: CRC (digest) iSCSI header only. */ 7043 #define QUEUE_CRC_MODE_ISCSI_HDR 0x2 7044 /* enum: CRC (digest) iSCSI header and payload. */ 7045 #define QUEUE_CRC_MODE_ISCSI 0x3 7046 /* enum: CRC Fiber channel over IP over ethernet. */ 7047 #define QUEUE_CRC_MODE_FCOIPOE 0x4 7048 /* enum: CRC MPA. */ 7049 #define QUEUE_CRC_MODE_MPA 0x5 7050 #define QUEUE_CRC_MODE_SPARE_LBN 4 7051 #define QUEUE_CRC_MODE_SPARE_WIDTH 4 7052 7053 7054 /***********************************/ 7055 /* MC_CMD_INIT_RXQ 7056 * set up a receive queue according to the supplied parameters. The IN 7057 * arguments end with an address for each 4k of host memory required to back 7058 * the RXQ. 7059 */ 7060 #define MC_CMD_INIT_RXQ 0x81 7061 #undef MC_CMD_0x81_PRIVILEGE_CTG 7062 7063 #define MC_CMD_0x81_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7064 7065 /* MC_CMD_INIT_RXQ_IN msgrequest: Legacy RXQ_INIT request. Use extended version 7066 * in new code. 7067 */ 7068 #define MC_CMD_INIT_RXQ_IN_LENMIN 36 7069 #define MC_CMD_INIT_RXQ_IN_LENMAX 252 7070 #define MC_CMD_INIT_RXQ_IN_LEN(num) (28+8*(num)) 7071 /* Size, in entries */ 7072 #define MC_CMD_INIT_RXQ_IN_SIZE_OFST 0 7073 #define MC_CMD_INIT_RXQ_IN_SIZE_LEN 4 7074 /* The EVQ to send events to. This is an index originally specified to INIT_EVQ 7075 */ 7076 #define MC_CMD_INIT_RXQ_IN_TARGET_EVQ_OFST 4 7077 #define MC_CMD_INIT_RXQ_IN_TARGET_EVQ_LEN 4 7078 /* The value to put in the event data. Check hardware spec. for valid range. */ 7079 #define MC_CMD_INIT_RXQ_IN_LABEL_OFST 8 7080 #define MC_CMD_INIT_RXQ_IN_LABEL_LEN 4 7081 /* Desired instance. Must be set to a specific instance, which is a function 7082 * local queue index. 7083 */ 7084 #define MC_CMD_INIT_RXQ_IN_INSTANCE_OFST 12 7085 #define MC_CMD_INIT_RXQ_IN_INSTANCE_LEN 4 7086 /* There will be more flags here. */ 7087 #define MC_CMD_INIT_RXQ_IN_FLAGS_OFST 16 7088 #define MC_CMD_INIT_RXQ_IN_FLAGS_LEN 4 7089 #define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_LBN 0 7090 #define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_WIDTH 1 7091 #define MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_LBN 1 7092 #define MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_WIDTH 1 7093 #define MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_LBN 2 7094 #define MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_WIDTH 1 7095 #define MC_CMD_INIT_RXQ_IN_CRC_MODE_LBN 3 7096 #define MC_CMD_INIT_RXQ_IN_CRC_MODE_WIDTH 4 7097 #define MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_LBN 7 7098 #define MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_WIDTH 1 7099 #define MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_LBN 8 7100 #define MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_WIDTH 1 7101 #define MC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_LBN 9 7102 #define MC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_WIDTH 1 7103 #define MC_CMD_INIT_RXQ_IN_UNUSED_LBN 10 7104 #define MC_CMD_INIT_RXQ_IN_UNUSED_WIDTH 1 7105 /* Owner ID to use if in buffer mode (zero if physical) */ 7106 #define MC_CMD_INIT_RXQ_IN_OWNER_ID_OFST 20 7107 #define MC_CMD_INIT_RXQ_IN_OWNER_ID_LEN 4 7108 /* The port ID associated with the v-adaptor which should contain this DMAQ. */ 7109 #define MC_CMD_INIT_RXQ_IN_PORT_ID_OFST 24 7110 #define MC_CMD_INIT_RXQ_IN_PORT_ID_LEN 4 7111 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 7112 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_OFST 28 7113 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LEN 8 7114 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LO_OFST 28 7115 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_HI_OFST 32 7116 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MINNUM 1 7117 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MAXNUM 28 7118 7119 /* MC_CMD_INIT_RXQ_EXT_IN msgrequest: Extended RXQ_INIT with additional mode 7120 * flags 7121 */ 7122 #define MC_CMD_INIT_RXQ_EXT_IN_LEN 544 7123 /* Size, in entries */ 7124 #define MC_CMD_INIT_RXQ_EXT_IN_SIZE_OFST 0 7125 #define MC_CMD_INIT_RXQ_EXT_IN_SIZE_LEN 4 7126 /* The EVQ to send events to. This is an index originally specified to INIT_EVQ 7127 */ 7128 #define MC_CMD_INIT_RXQ_EXT_IN_TARGET_EVQ_OFST 4 7129 #define MC_CMD_INIT_RXQ_EXT_IN_TARGET_EVQ_LEN 4 7130 /* The value to put in the event data. Check hardware spec. for valid range. */ 7131 #define MC_CMD_INIT_RXQ_EXT_IN_LABEL_OFST 8 7132 #define MC_CMD_INIT_RXQ_EXT_IN_LABEL_LEN 4 7133 /* Desired instance. Must be set to a specific instance, which is a function 7134 * local queue index. 7135 */ 7136 #define MC_CMD_INIT_RXQ_EXT_IN_INSTANCE_OFST 12 7137 #define MC_CMD_INIT_RXQ_EXT_IN_INSTANCE_LEN 4 7138 /* There will be more flags here. */ 7139 #define MC_CMD_INIT_RXQ_EXT_IN_FLAGS_OFST 16 7140 #define MC_CMD_INIT_RXQ_EXT_IN_FLAGS_LEN 4 7141 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_LBN 0 7142 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_WIDTH 1 7143 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT_LBN 1 7144 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT_WIDTH 1 7145 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_TIMESTAMP_LBN 2 7146 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_TIMESTAMP_WIDTH 1 7147 #define MC_CMD_INIT_RXQ_EXT_IN_CRC_MODE_LBN 3 7148 #define MC_CMD_INIT_RXQ_EXT_IN_CRC_MODE_WIDTH 4 7149 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_CHAIN_LBN 7 7150 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_CHAIN_WIDTH 1 7151 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_PREFIX_LBN 8 7152 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_PREFIX_WIDTH 1 7153 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER_LBN 9 7154 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER_WIDTH 1 7155 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_LBN 10 7156 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_WIDTH 4 7157 /* enum: One packet per descriptor (for normal networking) */ 7158 #define MC_CMD_INIT_RXQ_EXT_IN_SINGLE_PACKET 0x0 7159 /* enum: Pack multiple packets into large descriptors (for SolarCapture) */ 7160 #define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM 0x1 7161 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_LBN 14 7162 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_WIDTH 1 7163 #define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE_LBN 15 7164 #define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE_WIDTH 3 7165 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_1M 0x0 /* enum */ 7166 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_512K 0x1 /* enum */ 7167 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_256K 0x2 /* enum */ 7168 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_128K 0x3 /* enum */ 7169 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_64K 0x4 /* enum */ 7170 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES_LBN 18 7171 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 1 7172 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_FORCE_EV_MERGING_LBN 19 7173 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_FORCE_EV_MERGING_WIDTH 1 7174 /* Owner ID to use if in buffer mode (zero if physical) */ 7175 #define MC_CMD_INIT_RXQ_EXT_IN_OWNER_ID_OFST 20 7176 #define MC_CMD_INIT_RXQ_EXT_IN_OWNER_ID_LEN 4 7177 /* The port ID associated with the v-adaptor which should contain this DMAQ. */ 7178 #define MC_CMD_INIT_RXQ_EXT_IN_PORT_ID_OFST 24 7179 #define MC_CMD_INIT_RXQ_EXT_IN_PORT_ID_LEN 4 7180 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 7181 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_OFST 28 7182 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LEN 8 7183 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LO_OFST 28 7184 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_HI_OFST 32 7185 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_NUM 64 7186 /* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */ 7187 #define MC_CMD_INIT_RXQ_EXT_IN_SNAPSHOT_LENGTH_OFST 540 7188 #define MC_CMD_INIT_RXQ_EXT_IN_SNAPSHOT_LENGTH_LEN 4 7189 7190 /* MC_CMD_INIT_RXQ_OUT msgresponse */ 7191 #define MC_CMD_INIT_RXQ_OUT_LEN 0 7192 7193 /* MC_CMD_INIT_RXQ_EXT_OUT msgresponse */ 7194 #define MC_CMD_INIT_RXQ_EXT_OUT_LEN 0 7195 7196 7197 /***********************************/ 7198 /* MC_CMD_INIT_TXQ 7199 */ 7200 #define MC_CMD_INIT_TXQ 0x82 7201 #undef MC_CMD_0x82_PRIVILEGE_CTG 7202 7203 #define MC_CMD_0x82_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7204 7205 /* MC_CMD_INIT_TXQ_IN msgrequest: Legacy INIT_TXQ request. Use extended version 7206 * in new code. 7207 */ 7208 #define MC_CMD_INIT_TXQ_IN_LENMIN 36 7209 #define MC_CMD_INIT_TXQ_IN_LENMAX 252 7210 #define MC_CMD_INIT_TXQ_IN_LEN(num) (28+8*(num)) 7211 /* Size, in entries */ 7212 #define MC_CMD_INIT_TXQ_IN_SIZE_OFST 0 7213 #define MC_CMD_INIT_TXQ_IN_SIZE_LEN 4 7214 /* The EVQ to send events to. This is an index originally specified to 7215 * INIT_EVQ. 7216 */ 7217 #define MC_CMD_INIT_TXQ_IN_TARGET_EVQ_OFST 4 7218 #define MC_CMD_INIT_TXQ_IN_TARGET_EVQ_LEN 4 7219 /* The value to put in the event data. Check hardware spec. for valid range. */ 7220 #define MC_CMD_INIT_TXQ_IN_LABEL_OFST 8 7221 #define MC_CMD_INIT_TXQ_IN_LABEL_LEN 4 7222 /* Desired instance. Must be set to a specific instance, which is a function 7223 * local queue index. 7224 */ 7225 #define MC_CMD_INIT_TXQ_IN_INSTANCE_OFST 12 7226 #define MC_CMD_INIT_TXQ_IN_INSTANCE_LEN 4 7227 /* There will be more flags here. */ 7228 #define MC_CMD_INIT_TXQ_IN_FLAGS_OFST 16 7229 #define MC_CMD_INIT_TXQ_IN_FLAGS_LEN 4 7230 #define MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_LBN 0 7231 #define MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_WIDTH 1 7232 #define MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_LBN 1 7233 #define MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_WIDTH 1 7234 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_LBN 2 7235 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_WIDTH 1 7236 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_LBN 3 7237 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_WIDTH 1 7238 #define MC_CMD_INIT_TXQ_IN_CRC_MODE_LBN 4 7239 #define MC_CMD_INIT_TXQ_IN_CRC_MODE_WIDTH 4 7240 #define MC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_LBN 8 7241 #define MC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_WIDTH 1 7242 #define MC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_LBN 9 7243 #define MC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_WIDTH 1 7244 #define MC_CMD_INIT_TXQ_IN_FLAG_INNER_IP_CSUM_EN_LBN 10 7245 #define MC_CMD_INIT_TXQ_IN_FLAG_INNER_IP_CSUM_EN_WIDTH 1 7246 #define MC_CMD_INIT_TXQ_IN_FLAG_INNER_TCP_CSUM_EN_LBN 11 7247 #define MC_CMD_INIT_TXQ_IN_FLAG_INNER_TCP_CSUM_EN_WIDTH 1 7248 /* Owner ID to use if in buffer mode (zero if physical) */ 7249 #define MC_CMD_INIT_TXQ_IN_OWNER_ID_OFST 20 7250 #define MC_CMD_INIT_TXQ_IN_OWNER_ID_LEN 4 7251 /* The port ID associated with the v-adaptor which should contain this DMAQ. */ 7252 #define MC_CMD_INIT_TXQ_IN_PORT_ID_OFST 24 7253 #define MC_CMD_INIT_TXQ_IN_PORT_ID_LEN 4 7254 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 7255 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_OFST 28 7256 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LEN 8 7257 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LO_OFST 28 7258 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_HI_OFST 32 7259 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MINNUM 1 7260 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MAXNUM 28 7261 7262 /* MC_CMD_INIT_TXQ_EXT_IN msgrequest: Extended INIT_TXQ with additional mode 7263 * flags 7264 */ 7265 #define MC_CMD_INIT_TXQ_EXT_IN_LEN 544 7266 /* Size, in entries */ 7267 #define MC_CMD_INIT_TXQ_EXT_IN_SIZE_OFST 0 7268 #define MC_CMD_INIT_TXQ_EXT_IN_SIZE_LEN 4 7269 /* The EVQ to send events to. This is an index originally specified to 7270 * INIT_EVQ. 7271 */ 7272 #define MC_CMD_INIT_TXQ_EXT_IN_TARGET_EVQ_OFST 4 7273 #define MC_CMD_INIT_TXQ_EXT_IN_TARGET_EVQ_LEN 4 7274 /* The value to put in the event data. Check hardware spec. for valid range. */ 7275 #define MC_CMD_INIT_TXQ_EXT_IN_LABEL_OFST 8 7276 #define MC_CMD_INIT_TXQ_EXT_IN_LABEL_LEN 4 7277 /* Desired instance. Must be set to a specific instance, which is a function 7278 * local queue index. 7279 */ 7280 #define MC_CMD_INIT_TXQ_EXT_IN_INSTANCE_OFST 12 7281 #define MC_CMD_INIT_TXQ_EXT_IN_INSTANCE_LEN 4 7282 /* There will be more flags here. */ 7283 #define MC_CMD_INIT_TXQ_EXT_IN_FLAGS_OFST 16 7284 #define MC_CMD_INIT_TXQ_EXT_IN_FLAGS_LEN 4 7285 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_BUFF_MODE_LBN 0 7286 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_BUFF_MODE_WIDTH 1 7287 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_IP_CSUM_DIS_LBN 1 7288 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_IP_CSUM_DIS_WIDTH 1 7289 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_CSUM_DIS_LBN 2 7290 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_CSUM_DIS_WIDTH 1 7291 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_UDP_ONLY_LBN 3 7292 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_UDP_ONLY_WIDTH 1 7293 #define MC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_LBN 4 7294 #define MC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_WIDTH 4 7295 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TIMESTAMP_LBN 8 7296 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TIMESTAMP_WIDTH 1 7297 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_PACER_BYPASS_LBN 9 7298 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_PACER_BYPASS_WIDTH 1 7299 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN_LBN 10 7300 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN_WIDTH 1 7301 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN_LBN 11 7302 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN_WIDTH 1 7303 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TSOV2_EN_LBN 12 7304 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TSOV2_EN_WIDTH 1 7305 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_LBN 13 7306 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_WIDTH 1 7307 /* Owner ID to use if in buffer mode (zero if physical) */ 7308 #define MC_CMD_INIT_TXQ_EXT_IN_OWNER_ID_OFST 20 7309 #define MC_CMD_INIT_TXQ_EXT_IN_OWNER_ID_LEN 4 7310 /* The port ID associated with the v-adaptor which should contain this DMAQ. */ 7311 #define MC_CMD_INIT_TXQ_EXT_IN_PORT_ID_OFST 24 7312 #define MC_CMD_INIT_TXQ_EXT_IN_PORT_ID_LEN 4 7313 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 7314 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_OFST 28 7315 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LEN 8 7316 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LO_OFST 28 7317 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_HI_OFST 32 7318 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MINNUM 1 7319 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MAXNUM 64 7320 /* Flags related to Qbb flow control mode. */ 7321 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_FLAGS_OFST 540 7322 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_FLAGS_LEN 4 7323 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_ENABLE_LBN 0 7324 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_ENABLE_WIDTH 1 7325 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_PRIORITY_LBN 1 7326 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_PRIORITY_WIDTH 3 7327 7328 /* MC_CMD_INIT_TXQ_OUT msgresponse */ 7329 #define MC_CMD_INIT_TXQ_OUT_LEN 0 7330 7331 7332 /***********************************/ 7333 /* MC_CMD_FINI_EVQ 7334 * Teardown an EVQ. 7335 * 7336 * All DMAQs or EVQs that point to the EVQ to tear down must be torn down first 7337 * or the operation will fail with EBUSY 7338 */ 7339 #define MC_CMD_FINI_EVQ 0x83 7340 #undef MC_CMD_0x83_PRIVILEGE_CTG 7341 7342 #define MC_CMD_0x83_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7343 7344 /* MC_CMD_FINI_EVQ_IN msgrequest */ 7345 #define MC_CMD_FINI_EVQ_IN_LEN 4 7346 /* Instance of EVQ to destroy. Should be the same instance as that previously 7347 * passed to INIT_EVQ 7348 */ 7349 #define MC_CMD_FINI_EVQ_IN_INSTANCE_OFST 0 7350 #define MC_CMD_FINI_EVQ_IN_INSTANCE_LEN 4 7351 7352 /* MC_CMD_FINI_EVQ_OUT msgresponse */ 7353 #define MC_CMD_FINI_EVQ_OUT_LEN 0 7354 7355 7356 /***********************************/ 7357 /* MC_CMD_FINI_RXQ 7358 * Teardown a RXQ. 7359 */ 7360 #define MC_CMD_FINI_RXQ 0x84 7361 #undef MC_CMD_0x84_PRIVILEGE_CTG 7362 7363 #define MC_CMD_0x84_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7364 7365 /* MC_CMD_FINI_RXQ_IN msgrequest */ 7366 #define MC_CMD_FINI_RXQ_IN_LEN 4 7367 /* Instance of RXQ to destroy */ 7368 #define MC_CMD_FINI_RXQ_IN_INSTANCE_OFST 0 7369 #define MC_CMD_FINI_RXQ_IN_INSTANCE_LEN 4 7370 7371 /* MC_CMD_FINI_RXQ_OUT msgresponse */ 7372 #define MC_CMD_FINI_RXQ_OUT_LEN 0 7373 7374 7375 /***********************************/ 7376 /* MC_CMD_FINI_TXQ 7377 * Teardown a TXQ. 7378 */ 7379 #define MC_CMD_FINI_TXQ 0x85 7380 #undef MC_CMD_0x85_PRIVILEGE_CTG 7381 7382 #define MC_CMD_0x85_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7383 7384 /* MC_CMD_FINI_TXQ_IN msgrequest */ 7385 #define MC_CMD_FINI_TXQ_IN_LEN 4 7386 /* Instance of TXQ to destroy */ 7387 #define MC_CMD_FINI_TXQ_IN_INSTANCE_OFST 0 7388 #define MC_CMD_FINI_TXQ_IN_INSTANCE_LEN 4 7389 7390 /* MC_CMD_FINI_TXQ_OUT msgresponse */ 7391 #define MC_CMD_FINI_TXQ_OUT_LEN 0 7392 7393 7394 /***********************************/ 7395 /* MC_CMD_DRIVER_EVENT 7396 * Generate an event on an EVQ belonging to the function issuing the command. 7397 */ 7398 #define MC_CMD_DRIVER_EVENT 0x86 7399 #undef MC_CMD_0x86_PRIVILEGE_CTG 7400 7401 #define MC_CMD_0x86_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7402 7403 /* MC_CMD_DRIVER_EVENT_IN msgrequest */ 7404 #define MC_CMD_DRIVER_EVENT_IN_LEN 12 7405 /* Handle of target EVQ */ 7406 #define MC_CMD_DRIVER_EVENT_IN_EVQ_OFST 0 7407 #define MC_CMD_DRIVER_EVENT_IN_EVQ_LEN 4 7408 /* Bits 0 - 63 of event */ 7409 #define MC_CMD_DRIVER_EVENT_IN_DATA_OFST 4 7410 #define MC_CMD_DRIVER_EVENT_IN_DATA_LEN 8 7411 #define MC_CMD_DRIVER_EVENT_IN_DATA_LO_OFST 4 7412 #define MC_CMD_DRIVER_EVENT_IN_DATA_HI_OFST 8 7413 7414 /* MC_CMD_DRIVER_EVENT_OUT msgresponse */ 7415 #define MC_CMD_DRIVER_EVENT_OUT_LEN 0 7416 7417 7418 /***********************************/ 7419 /* MC_CMD_PROXY_CMD 7420 * Execute an arbitrary MCDI command on behalf of a different function, subject 7421 * to security restrictions. The command to be proxied follows immediately 7422 * afterward in the host buffer (or on the UART). This command supercedes 7423 * MC_CMD_SET_FUNC, which remains available for Siena but now deprecated. 7424 */ 7425 #define MC_CMD_PROXY_CMD 0x5b 7426 #undef MC_CMD_0x5b_PRIVILEGE_CTG 7427 7428 #define MC_CMD_0x5b_PRIVILEGE_CTG SRIOV_CTG_ADMIN 7429 7430 /* MC_CMD_PROXY_CMD_IN msgrequest */ 7431 #define MC_CMD_PROXY_CMD_IN_LEN 4 7432 /* The handle of the target function. */ 7433 #define MC_CMD_PROXY_CMD_IN_TARGET_OFST 0 7434 #define MC_CMD_PROXY_CMD_IN_TARGET_LEN 4 7435 #define MC_CMD_PROXY_CMD_IN_TARGET_PF_LBN 0 7436 #define MC_CMD_PROXY_CMD_IN_TARGET_PF_WIDTH 16 7437 #define MC_CMD_PROXY_CMD_IN_TARGET_VF_LBN 16 7438 #define MC_CMD_PROXY_CMD_IN_TARGET_VF_WIDTH 16 7439 #define MC_CMD_PROXY_CMD_IN_VF_NULL 0xffff /* enum */ 7440 7441 /* MC_CMD_PROXY_CMD_OUT msgresponse */ 7442 #define MC_CMD_PROXY_CMD_OUT_LEN 0 7443 7444 /* MC_PROXY_STATUS_BUFFER structuredef: Host memory status buffer used to 7445 * manage proxied requests 7446 */ 7447 #define MC_PROXY_STATUS_BUFFER_LEN 16 7448 /* Handle allocated by the firmware for this proxy transaction */ 7449 #define MC_PROXY_STATUS_BUFFER_HANDLE_OFST 0 7450 #define MC_PROXY_STATUS_BUFFER_HANDLE_LEN 4 7451 /* enum: An invalid handle. */ 7452 #define MC_PROXY_STATUS_BUFFER_HANDLE_INVALID 0x0 7453 #define MC_PROXY_STATUS_BUFFER_HANDLE_LBN 0 7454 #define MC_PROXY_STATUS_BUFFER_HANDLE_WIDTH 32 7455 /* The requesting physical function number */ 7456 #define MC_PROXY_STATUS_BUFFER_PF_OFST 4 7457 #define MC_PROXY_STATUS_BUFFER_PF_LEN 2 7458 #define MC_PROXY_STATUS_BUFFER_PF_LBN 32 7459 #define MC_PROXY_STATUS_BUFFER_PF_WIDTH 16 7460 /* The requesting virtual function number. Set to VF_NULL if the target is a 7461 * PF. 7462 */ 7463 #define MC_PROXY_STATUS_BUFFER_VF_OFST 6 7464 #define MC_PROXY_STATUS_BUFFER_VF_LEN 2 7465 #define MC_PROXY_STATUS_BUFFER_VF_LBN 48 7466 #define MC_PROXY_STATUS_BUFFER_VF_WIDTH 16 7467 /* The target function RID. */ 7468 #define MC_PROXY_STATUS_BUFFER_RID_OFST 8 7469 #define MC_PROXY_STATUS_BUFFER_RID_LEN 2 7470 #define MC_PROXY_STATUS_BUFFER_RID_LBN 64 7471 #define MC_PROXY_STATUS_BUFFER_RID_WIDTH 16 7472 /* The status of the proxy as described in MC_CMD_PROXY_COMPLETE. */ 7473 #define MC_PROXY_STATUS_BUFFER_STATUS_OFST 10 7474 #define MC_PROXY_STATUS_BUFFER_STATUS_LEN 2 7475 #define MC_PROXY_STATUS_BUFFER_STATUS_LBN 80 7476 #define MC_PROXY_STATUS_BUFFER_STATUS_WIDTH 16 7477 /* If a request is authorized rather than carried out by the host, this is the 7478 * elevated privilege mask granted to the requesting function. 7479 */ 7480 #define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_OFST 12 7481 #define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_LEN 4 7482 #define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_LBN 96 7483 #define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_WIDTH 32 7484 7485 7486 /***********************************/ 7487 /* MC_CMD_PROXY_CONFIGURE 7488 * Enable/disable authorization of MCDI requests from unprivileged functions by 7489 * a designated admin function 7490 */ 7491 #define MC_CMD_PROXY_CONFIGURE 0x58 7492 #undef MC_CMD_0x58_PRIVILEGE_CTG 7493 7494 #define MC_CMD_0x58_PRIVILEGE_CTG SRIOV_CTG_ADMIN 7495 7496 /* MC_CMD_PROXY_CONFIGURE_IN msgrequest */ 7497 #define MC_CMD_PROXY_CONFIGURE_IN_LEN 108 7498 #define MC_CMD_PROXY_CONFIGURE_IN_FLAGS_OFST 0 7499 #define MC_CMD_PROXY_CONFIGURE_IN_FLAGS_LEN 4 7500 #define MC_CMD_PROXY_CONFIGURE_IN_ENABLE_LBN 0 7501 #define MC_CMD_PROXY_CONFIGURE_IN_ENABLE_WIDTH 1 7502 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 7503 * of blocks, each of the size REQUEST_BLOCK_SIZE. 7504 */ 7505 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_OFST 4 7506 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LEN 8 7507 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LO_OFST 4 7508 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_HI_OFST 8 7509 /* Must be a power of 2 */ 7510 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BLOCK_SIZE_OFST 12 7511 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BLOCK_SIZE_LEN 4 7512 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 7513 * of blocks, each of the size REPLY_BLOCK_SIZE. 7514 */ 7515 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_OFST 16 7516 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LEN 8 7517 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LO_OFST 16 7518 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_HI_OFST 20 7519 /* Must be a power of 2 */ 7520 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BLOCK_SIZE_OFST 24 7521 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BLOCK_SIZE_LEN 4 7522 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 7523 * of blocks, each of the size STATUS_BLOCK_SIZE. This buffer is only needed if 7524 * host intends to complete proxied operations by using MC_CMD_PROXY_CMD. 7525 */ 7526 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_OFST 28 7527 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LEN 8 7528 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LO_OFST 28 7529 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_HI_OFST 32 7530 /* Must be a power of 2, or zero if this buffer is not provided */ 7531 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BLOCK_SIZE_OFST 36 7532 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BLOCK_SIZE_LEN 4 7533 /* Applies to all three buffers */ 7534 #define MC_CMD_PROXY_CONFIGURE_IN_NUM_BLOCKS_OFST 40 7535 #define MC_CMD_PROXY_CONFIGURE_IN_NUM_BLOCKS_LEN 4 7536 /* A bit mask defining which MCDI operations may be proxied */ 7537 #define MC_CMD_PROXY_CONFIGURE_IN_ALLOWED_MCDI_MASK_OFST 44 7538 #define MC_CMD_PROXY_CONFIGURE_IN_ALLOWED_MCDI_MASK_LEN 64 7539 7540 /* MC_CMD_PROXY_CONFIGURE_EXT_IN msgrequest */ 7541 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_LEN 112 7542 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_FLAGS_OFST 0 7543 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_FLAGS_LEN 4 7544 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_ENABLE_LBN 0 7545 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_ENABLE_WIDTH 1 7546 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 7547 * of blocks, each of the size REQUEST_BLOCK_SIZE. 7548 */ 7549 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_OFST 4 7550 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LEN 8 7551 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LO_OFST 4 7552 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_HI_OFST 8 7553 /* Must be a power of 2 */ 7554 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BLOCK_SIZE_OFST 12 7555 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BLOCK_SIZE_LEN 4 7556 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 7557 * of blocks, each of the size REPLY_BLOCK_SIZE. 7558 */ 7559 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_OFST 16 7560 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_LEN 8 7561 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_LO_OFST 16 7562 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_HI_OFST 20 7563 /* Must be a power of 2 */ 7564 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BLOCK_SIZE_OFST 24 7565 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BLOCK_SIZE_LEN 4 7566 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 7567 * of blocks, each of the size STATUS_BLOCK_SIZE. This buffer is only needed if 7568 * host intends to complete proxied operations by using MC_CMD_PROXY_CMD. 7569 */ 7570 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_OFST 28 7571 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_LEN 8 7572 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_LO_OFST 28 7573 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_HI_OFST 32 7574 /* Must be a power of 2, or zero if this buffer is not provided */ 7575 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BLOCK_SIZE_OFST 36 7576 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BLOCK_SIZE_LEN 4 7577 /* Applies to all three buffers */ 7578 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_NUM_BLOCKS_OFST 40 7579 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_NUM_BLOCKS_LEN 4 7580 /* A bit mask defining which MCDI operations may be proxied */ 7581 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_ALLOWED_MCDI_MASK_OFST 44 7582 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_ALLOWED_MCDI_MASK_LEN 64 7583 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_RESERVED_OFST 108 7584 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_RESERVED_LEN 4 7585 7586 /* MC_CMD_PROXY_CONFIGURE_OUT msgresponse */ 7587 #define MC_CMD_PROXY_CONFIGURE_OUT_LEN 0 7588 7589 7590 /***********************************/ 7591 /* MC_CMD_PROXY_COMPLETE 7592 * Tells FW that a requested proxy operation has either been completed (by 7593 * using MC_CMD_PROXY_CMD) or authorized/declined. May only be sent by the 7594 * function that enabled proxying/authorization (by using 7595 * MC_CMD_PROXY_CONFIGURE). 7596 */ 7597 #define MC_CMD_PROXY_COMPLETE 0x5f 7598 #undef MC_CMD_0x5f_PRIVILEGE_CTG 7599 7600 #define MC_CMD_0x5f_PRIVILEGE_CTG SRIOV_CTG_ADMIN 7601 7602 /* MC_CMD_PROXY_COMPLETE_IN msgrequest */ 7603 #define MC_CMD_PROXY_COMPLETE_IN_LEN 12 7604 #define MC_CMD_PROXY_COMPLETE_IN_BLOCK_INDEX_OFST 0 7605 #define MC_CMD_PROXY_COMPLETE_IN_BLOCK_INDEX_LEN 4 7606 #define MC_CMD_PROXY_COMPLETE_IN_STATUS_OFST 4 7607 #define MC_CMD_PROXY_COMPLETE_IN_STATUS_LEN 4 7608 /* enum: The operation has been completed by using MC_CMD_PROXY_CMD, the reply 7609 * is stored in the REPLY_BUFF. 7610 */ 7611 #define MC_CMD_PROXY_COMPLETE_IN_COMPLETE 0x0 7612 /* enum: The operation has been authorized. The originating function may now 7613 * try again. 7614 */ 7615 #define MC_CMD_PROXY_COMPLETE_IN_AUTHORIZED 0x1 7616 /* enum: The operation has been declined. */ 7617 #define MC_CMD_PROXY_COMPLETE_IN_DECLINED 0x2 7618 /* enum: The authorization failed because the relevant application did not 7619 * respond in time. 7620 */ 7621 #define MC_CMD_PROXY_COMPLETE_IN_TIMEDOUT 0x3 7622 #define MC_CMD_PROXY_COMPLETE_IN_HANDLE_OFST 8 7623 #define MC_CMD_PROXY_COMPLETE_IN_HANDLE_LEN 4 7624 7625 /* MC_CMD_PROXY_COMPLETE_OUT msgresponse */ 7626 #define MC_CMD_PROXY_COMPLETE_OUT_LEN 0 7627 7628 7629 /***********************************/ 7630 /* MC_CMD_ALLOC_BUFTBL_CHUNK 7631 * Allocate a set of buffer table entries using the specified owner ID. This 7632 * operation allocates the required buffer table entries (and fails if it 7633 * cannot do so). The buffer table entries will initially be zeroed. 7634 */ 7635 #define MC_CMD_ALLOC_BUFTBL_CHUNK 0x87 7636 #undef MC_CMD_0x87_PRIVILEGE_CTG 7637 7638 #define MC_CMD_0x87_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 7639 7640 /* MC_CMD_ALLOC_BUFTBL_CHUNK_IN msgrequest */ 7641 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_LEN 8 7642 /* Owner ID to use */ 7643 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_OWNER_OFST 0 7644 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_OWNER_LEN 4 7645 /* Size of buffer table pages to use, in bytes (note that only a few values are 7646 * legal on any specific hardware). 7647 */ 7648 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_PAGE_SIZE_OFST 4 7649 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_PAGE_SIZE_LEN 4 7650 7651 /* MC_CMD_ALLOC_BUFTBL_CHUNK_OUT msgresponse */ 7652 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_LEN 12 7653 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_HANDLE_OFST 0 7654 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_HANDLE_LEN 4 7655 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_NUMENTRIES_OFST 4 7656 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_NUMENTRIES_LEN 4 7657 /* Buffer table IDs for use in DMA descriptors. */ 7658 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_ID_OFST 8 7659 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_ID_LEN 4 7660 7661 7662 /***********************************/ 7663 /* MC_CMD_PROGRAM_BUFTBL_ENTRIES 7664 * Reprogram a set of buffer table entries in the specified chunk. 7665 */ 7666 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES 0x88 7667 #undef MC_CMD_0x88_PRIVILEGE_CTG 7668 7669 #define MC_CMD_0x88_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 7670 7671 /* MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN msgrequest */ 7672 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMIN 20 7673 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMAX 268 7674 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LEN(num) (12+8*(num)) 7675 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_HANDLE_OFST 0 7676 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_HANDLE_LEN 4 7677 /* ID */ 7678 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_FIRSTID_OFST 4 7679 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_FIRSTID_LEN 4 7680 /* Num entries */ 7681 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_NUMENTRIES_OFST 8 7682 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_NUMENTRIES_LEN 4 7683 /* Buffer table entry address */ 7684 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_OFST 12 7685 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LEN 8 7686 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LO_OFST 12 7687 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_HI_OFST 16 7688 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MINNUM 1 7689 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MAXNUM 32 7690 7691 /* MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT msgresponse */ 7692 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT_LEN 0 7693 7694 7695 /***********************************/ 7696 /* MC_CMD_FREE_BUFTBL_CHUNK 7697 */ 7698 #define MC_CMD_FREE_BUFTBL_CHUNK 0x89 7699 #undef MC_CMD_0x89_PRIVILEGE_CTG 7700 7701 #define MC_CMD_0x89_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 7702 7703 /* MC_CMD_FREE_BUFTBL_CHUNK_IN msgrequest */ 7704 #define MC_CMD_FREE_BUFTBL_CHUNK_IN_LEN 4 7705 #define MC_CMD_FREE_BUFTBL_CHUNK_IN_HANDLE_OFST 0 7706 #define MC_CMD_FREE_BUFTBL_CHUNK_IN_HANDLE_LEN 4 7707 7708 /* MC_CMD_FREE_BUFTBL_CHUNK_OUT msgresponse */ 7709 #define MC_CMD_FREE_BUFTBL_CHUNK_OUT_LEN 0 7710 7711 7712 /***********************************/ 7713 /* MC_CMD_FILTER_OP 7714 * Multiplexed MCDI call for filter operations 7715 */ 7716 #define MC_CMD_FILTER_OP 0x8a 7717 #undef MC_CMD_0x8a_PRIVILEGE_CTG 7718 7719 #define MC_CMD_0x8a_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7720 7721 /* MC_CMD_FILTER_OP_IN msgrequest */ 7722 #define MC_CMD_FILTER_OP_IN_LEN 108 7723 /* identifies the type of operation requested */ 7724 #define MC_CMD_FILTER_OP_IN_OP_OFST 0 7725 #define MC_CMD_FILTER_OP_IN_OP_LEN 4 7726 /* enum: single-recipient filter insert */ 7727 #define MC_CMD_FILTER_OP_IN_OP_INSERT 0x0 7728 /* enum: single-recipient filter remove */ 7729 #define MC_CMD_FILTER_OP_IN_OP_REMOVE 0x1 7730 /* enum: multi-recipient filter subscribe */ 7731 #define MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE 0x2 7732 /* enum: multi-recipient filter unsubscribe */ 7733 #define MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE 0x3 7734 /* enum: replace one recipient with another (warning - the filter handle may 7735 * change) 7736 */ 7737 #define MC_CMD_FILTER_OP_IN_OP_REPLACE 0x4 7738 /* filter handle (for remove / unsubscribe operations) */ 7739 #define MC_CMD_FILTER_OP_IN_HANDLE_OFST 4 7740 #define MC_CMD_FILTER_OP_IN_HANDLE_LEN 8 7741 #define MC_CMD_FILTER_OP_IN_HANDLE_LO_OFST 4 7742 #define MC_CMD_FILTER_OP_IN_HANDLE_HI_OFST 8 7743 /* The port ID associated with the v-adaptor which should contain this filter. 7744 */ 7745 #define MC_CMD_FILTER_OP_IN_PORT_ID_OFST 12 7746 #define MC_CMD_FILTER_OP_IN_PORT_ID_LEN 4 7747 /* fields to include in match criteria */ 7748 #define MC_CMD_FILTER_OP_IN_MATCH_FIELDS_OFST 16 7749 #define MC_CMD_FILTER_OP_IN_MATCH_FIELDS_LEN 4 7750 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_LBN 0 7751 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_WIDTH 1 7752 #define MC_CMD_FILTER_OP_IN_MATCH_DST_IP_LBN 1 7753 #define MC_CMD_FILTER_OP_IN_MATCH_DST_IP_WIDTH 1 7754 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_LBN 2 7755 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_WIDTH 1 7756 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_LBN 3 7757 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_WIDTH 1 7758 #define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_LBN 4 7759 #define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_WIDTH 1 7760 #define MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_LBN 5 7761 #define MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_WIDTH 1 7762 #define MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_LBN 6 7763 #define MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_WIDTH 1 7764 #define MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_LBN 7 7765 #define MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_WIDTH 1 7766 #define MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_LBN 8 7767 #define MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_WIDTH 1 7768 #define MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_LBN 9 7769 #define MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_WIDTH 1 7770 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_LBN 10 7771 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_WIDTH 1 7772 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_LBN 11 7773 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_WIDTH 1 7774 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN 30 7775 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1 7776 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN 31 7777 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1 7778 /* receive destination */ 7779 #define MC_CMD_FILTER_OP_IN_RX_DEST_OFST 20 7780 #define MC_CMD_FILTER_OP_IN_RX_DEST_LEN 4 7781 /* enum: drop packets */ 7782 #define MC_CMD_FILTER_OP_IN_RX_DEST_DROP 0x0 7783 /* enum: receive to host */ 7784 #define MC_CMD_FILTER_OP_IN_RX_DEST_HOST 0x1 7785 /* enum: receive to MC */ 7786 #define MC_CMD_FILTER_OP_IN_RX_DEST_MC 0x2 7787 /* enum: loop back to TXDP 0 */ 7788 #define MC_CMD_FILTER_OP_IN_RX_DEST_TX0 0x3 7789 /* enum: loop back to TXDP 1 */ 7790 #define MC_CMD_FILTER_OP_IN_RX_DEST_TX1 0x4 7791 /* receive queue handle (for multiple queue modes, this is the base queue) */ 7792 #define MC_CMD_FILTER_OP_IN_RX_QUEUE_OFST 24 7793 #define MC_CMD_FILTER_OP_IN_RX_QUEUE_LEN 4 7794 /* receive mode */ 7795 #define MC_CMD_FILTER_OP_IN_RX_MODE_OFST 28 7796 #define MC_CMD_FILTER_OP_IN_RX_MODE_LEN 4 7797 /* enum: receive to just the specified queue */ 7798 #define MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE 0x0 7799 /* enum: receive to multiple queues using RSS context */ 7800 #define MC_CMD_FILTER_OP_IN_RX_MODE_RSS 0x1 7801 /* enum: receive to multiple queues using .1p mapping */ 7802 #define MC_CMD_FILTER_OP_IN_RX_MODE_DOT1P_MAPPING 0x2 7803 /* enum: install a filter entry that will never match; for test purposes only 7804 */ 7805 #define MC_CMD_FILTER_OP_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000 7806 /* RSS context (for RX_MODE_RSS) or .1p mapping handle (for 7807 * RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or 7808 * MC_CMD_DOT1P_MAPPING_ALLOC. 7809 */ 7810 #define MC_CMD_FILTER_OP_IN_RX_CONTEXT_OFST 32 7811 #define MC_CMD_FILTER_OP_IN_RX_CONTEXT_LEN 4 7812 /* transmit domain (reserved; set to 0) */ 7813 #define MC_CMD_FILTER_OP_IN_TX_DOMAIN_OFST 36 7814 #define MC_CMD_FILTER_OP_IN_TX_DOMAIN_LEN 4 7815 /* transmit destination (either set the MAC and/or PM bits for explicit 7816 * control, or set this field to TX_DEST_DEFAULT for sensible default 7817 * behaviour) 7818 */ 7819 #define MC_CMD_FILTER_OP_IN_TX_DEST_OFST 40 7820 #define MC_CMD_FILTER_OP_IN_TX_DEST_LEN 4 7821 /* enum: request default behaviour (based on filter type) */ 7822 #define MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT 0xffffffff 7823 #define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_LBN 0 7824 #define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_WIDTH 1 7825 #define MC_CMD_FILTER_OP_IN_TX_DEST_PM_LBN 1 7826 #define MC_CMD_FILTER_OP_IN_TX_DEST_PM_WIDTH 1 7827 /* source MAC address to match (as bytes in network order) */ 7828 #define MC_CMD_FILTER_OP_IN_SRC_MAC_OFST 44 7829 #define MC_CMD_FILTER_OP_IN_SRC_MAC_LEN 6 7830 /* source port to match (as bytes in network order) */ 7831 #define MC_CMD_FILTER_OP_IN_SRC_PORT_OFST 50 7832 #define MC_CMD_FILTER_OP_IN_SRC_PORT_LEN 2 7833 /* destination MAC address to match (as bytes in network order) */ 7834 #define MC_CMD_FILTER_OP_IN_DST_MAC_OFST 52 7835 #define MC_CMD_FILTER_OP_IN_DST_MAC_LEN 6 7836 /* destination port to match (as bytes in network order) */ 7837 #define MC_CMD_FILTER_OP_IN_DST_PORT_OFST 58 7838 #define MC_CMD_FILTER_OP_IN_DST_PORT_LEN 2 7839 /* Ethernet type to match (as bytes in network order) */ 7840 #define MC_CMD_FILTER_OP_IN_ETHER_TYPE_OFST 60 7841 #define MC_CMD_FILTER_OP_IN_ETHER_TYPE_LEN 2 7842 /* Inner VLAN tag to match (as bytes in network order) */ 7843 #define MC_CMD_FILTER_OP_IN_INNER_VLAN_OFST 62 7844 #define MC_CMD_FILTER_OP_IN_INNER_VLAN_LEN 2 7845 /* Outer VLAN tag to match (as bytes in network order) */ 7846 #define MC_CMD_FILTER_OP_IN_OUTER_VLAN_OFST 64 7847 #define MC_CMD_FILTER_OP_IN_OUTER_VLAN_LEN 2 7848 /* IP protocol to match (in low byte; set high byte to 0) */ 7849 #define MC_CMD_FILTER_OP_IN_IP_PROTO_OFST 66 7850 #define MC_CMD_FILTER_OP_IN_IP_PROTO_LEN 2 7851 /* Firmware defined register 0 to match (reserved; set to 0) */ 7852 #define MC_CMD_FILTER_OP_IN_FWDEF0_OFST 68 7853 #define MC_CMD_FILTER_OP_IN_FWDEF0_LEN 4 7854 /* Firmware defined register 1 to match (reserved; set to 0) */ 7855 #define MC_CMD_FILTER_OP_IN_FWDEF1_OFST 72 7856 #define MC_CMD_FILTER_OP_IN_FWDEF1_LEN 4 7857 /* source IP address to match (as bytes in network order; set last 12 bytes to 7858 * 0 for IPv4 address) 7859 */ 7860 #define MC_CMD_FILTER_OP_IN_SRC_IP_OFST 76 7861 #define MC_CMD_FILTER_OP_IN_SRC_IP_LEN 16 7862 /* destination IP address to match (as bytes in network order; set last 12 7863 * bytes to 0 for IPv4 address) 7864 */ 7865 #define MC_CMD_FILTER_OP_IN_DST_IP_OFST 92 7866 #define MC_CMD_FILTER_OP_IN_DST_IP_LEN 16 7867 7868 /* MC_CMD_FILTER_OP_EXT_IN msgrequest: Extension to MC_CMD_FILTER_OP_IN to 7869 * include handling of VXLAN/NVGRE encapsulated frame filtering (which is 7870 * supported on Medford only). 7871 */ 7872 #define MC_CMD_FILTER_OP_EXT_IN_LEN 172 7873 /* identifies the type of operation requested */ 7874 #define MC_CMD_FILTER_OP_EXT_IN_OP_OFST 0 7875 #define MC_CMD_FILTER_OP_EXT_IN_OP_LEN 4 7876 /* Enum values, see field(s): */ 7877 /* MC_CMD_FILTER_OP_IN/OP */ 7878 /* filter handle (for remove / unsubscribe operations) */ 7879 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_OFST 4 7880 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LEN 8 7881 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LO_OFST 4 7882 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_HI_OFST 8 7883 /* The port ID associated with the v-adaptor which should contain this filter. 7884 */ 7885 #define MC_CMD_FILTER_OP_EXT_IN_PORT_ID_OFST 12 7886 #define MC_CMD_FILTER_OP_EXT_IN_PORT_ID_LEN 4 7887 /* fields to include in match criteria */ 7888 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_FIELDS_OFST 16 7889 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_FIELDS_LEN 4 7890 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_LBN 0 7891 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_WIDTH 1 7892 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_IP_LBN 1 7893 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_IP_WIDTH 1 7894 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_MAC_LBN 2 7895 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_MAC_WIDTH 1 7896 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_PORT_LBN 3 7897 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_PORT_WIDTH 1 7898 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_LBN 4 7899 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_WIDTH 1 7900 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_PORT_LBN 5 7901 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_PORT_WIDTH 1 7902 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_LBN 6 7903 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_WIDTH 1 7904 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_INNER_VLAN_LBN 7 7905 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_INNER_VLAN_WIDTH 1 7906 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_OUTER_VLAN_LBN 8 7907 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_OUTER_VLAN_WIDTH 1 7908 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_LBN 9 7909 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_WIDTH 1 7910 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_FWDEF0_LBN 10 7911 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_FWDEF0_WIDTH 1 7912 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_VNI_OR_VSID_LBN 11 7913 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_VNI_OR_VSID_WIDTH 1 7914 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_IP_LBN 12 7915 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_IP_WIDTH 1 7916 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_IP_LBN 13 7917 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_IP_WIDTH 1 7918 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_MAC_LBN 14 7919 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_MAC_WIDTH 1 7920 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_PORT_LBN 15 7921 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_PORT_WIDTH 1 7922 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_MAC_LBN 16 7923 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_MAC_WIDTH 1 7924 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_PORT_LBN 17 7925 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_PORT_WIDTH 1 7926 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ETHER_TYPE_LBN 18 7927 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ETHER_TYPE_WIDTH 1 7928 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_INNER_VLAN_LBN 19 7929 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_INNER_VLAN_WIDTH 1 7930 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_OUTER_VLAN_LBN 20 7931 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_OUTER_VLAN_WIDTH 1 7932 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_IP_PROTO_LBN 21 7933 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_IP_PROTO_WIDTH 1 7934 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF0_LBN 22 7935 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF0_WIDTH 1 7936 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF1_LBN 23 7937 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF1_WIDTH 1 7938 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_LBN 24 7939 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_WIDTH 1 7940 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_LBN 25 7941 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_WIDTH 1 7942 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_LBN 30 7943 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1 7944 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_LBN 31 7945 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1 7946 /* receive destination */ 7947 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_OFST 20 7948 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_LEN 4 7949 /* enum: drop packets */ 7950 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_DROP 0x0 7951 /* enum: receive to host */ 7952 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_HOST 0x1 7953 /* enum: receive to MC */ 7954 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_MC 0x2 7955 /* enum: loop back to TXDP 0 */ 7956 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_TX0 0x3 7957 /* enum: loop back to TXDP 1 */ 7958 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_TX1 0x4 7959 /* receive queue handle (for multiple queue modes, this is the base queue) */ 7960 #define MC_CMD_FILTER_OP_EXT_IN_RX_QUEUE_OFST 24 7961 #define MC_CMD_FILTER_OP_EXT_IN_RX_QUEUE_LEN 4 7962 /* receive mode */ 7963 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_OFST 28 7964 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_LEN 4 7965 /* enum: receive to just the specified queue */ 7966 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_SIMPLE 0x0 7967 /* enum: receive to multiple queues using RSS context */ 7968 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_RSS 0x1 7969 /* enum: receive to multiple queues using .1p mapping */ 7970 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_DOT1P_MAPPING 0x2 7971 /* enum: install a filter entry that will never match; for test purposes only 7972 */ 7973 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000 7974 /* RSS context (for RX_MODE_RSS) or .1p mapping handle (for 7975 * RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or 7976 * MC_CMD_DOT1P_MAPPING_ALLOC. 7977 */ 7978 #define MC_CMD_FILTER_OP_EXT_IN_RX_CONTEXT_OFST 32 7979 #define MC_CMD_FILTER_OP_EXT_IN_RX_CONTEXT_LEN 4 7980 /* transmit domain (reserved; set to 0) */ 7981 #define MC_CMD_FILTER_OP_EXT_IN_TX_DOMAIN_OFST 36 7982 #define MC_CMD_FILTER_OP_EXT_IN_TX_DOMAIN_LEN 4 7983 /* transmit destination (either set the MAC and/or PM bits for explicit 7984 * control, or set this field to TX_DEST_DEFAULT for sensible default 7985 * behaviour) 7986 */ 7987 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_OFST 40 7988 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_LEN 4 7989 /* enum: request default behaviour (based on filter type) */ 7990 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_DEFAULT 0xffffffff 7991 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_LBN 0 7992 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_WIDTH 1 7993 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_PM_LBN 1 7994 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_PM_WIDTH 1 7995 /* source MAC address to match (as bytes in network order) */ 7996 #define MC_CMD_FILTER_OP_EXT_IN_SRC_MAC_OFST 44 7997 #define MC_CMD_FILTER_OP_EXT_IN_SRC_MAC_LEN 6 7998 /* source port to match (as bytes in network order) */ 7999 #define MC_CMD_FILTER_OP_EXT_IN_SRC_PORT_OFST 50 8000 #define MC_CMD_FILTER_OP_EXT_IN_SRC_PORT_LEN 2 8001 /* destination MAC address to match (as bytes in network order) */ 8002 #define MC_CMD_FILTER_OP_EXT_IN_DST_MAC_OFST 52 8003 #define MC_CMD_FILTER_OP_EXT_IN_DST_MAC_LEN 6 8004 /* destination port to match (as bytes in network order) */ 8005 #define MC_CMD_FILTER_OP_EXT_IN_DST_PORT_OFST 58 8006 #define MC_CMD_FILTER_OP_EXT_IN_DST_PORT_LEN 2 8007 /* Ethernet type to match (as bytes in network order) */ 8008 #define MC_CMD_FILTER_OP_EXT_IN_ETHER_TYPE_OFST 60 8009 #define MC_CMD_FILTER_OP_EXT_IN_ETHER_TYPE_LEN 2 8010 /* Inner VLAN tag to match (as bytes in network order) */ 8011 #define MC_CMD_FILTER_OP_EXT_IN_INNER_VLAN_OFST 62 8012 #define MC_CMD_FILTER_OP_EXT_IN_INNER_VLAN_LEN 2 8013 /* Outer VLAN tag to match (as bytes in network order) */ 8014 #define MC_CMD_FILTER_OP_EXT_IN_OUTER_VLAN_OFST 64 8015 #define MC_CMD_FILTER_OP_EXT_IN_OUTER_VLAN_LEN 2 8016 /* IP protocol to match (in low byte; set high byte to 0) */ 8017 #define MC_CMD_FILTER_OP_EXT_IN_IP_PROTO_OFST 66 8018 #define MC_CMD_FILTER_OP_EXT_IN_IP_PROTO_LEN 2 8019 /* Firmware defined register 0 to match (reserved; set to 0) */ 8020 #define MC_CMD_FILTER_OP_EXT_IN_FWDEF0_OFST 68 8021 #define MC_CMD_FILTER_OP_EXT_IN_FWDEF0_LEN 4 8022 /* VNI (for VXLAN/Geneve, when IP protocol is UDP) or VSID (for NVGRE, when IP 8023 * protocol is GRE) to match (as bytes in network order; set last byte to 0 for 8024 * VXLAN/NVGRE, or 1 for Geneve) 8025 */ 8026 #define MC_CMD_FILTER_OP_EXT_IN_VNI_OR_VSID_OFST 72 8027 #define MC_CMD_FILTER_OP_EXT_IN_VNI_OR_VSID_LEN 4 8028 #define MC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_LBN 0 8029 #define MC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_WIDTH 24 8030 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_LBN 24 8031 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_WIDTH 8 8032 /* enum: Match VXLAN traffic with this VNI */ 8033 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_VXLAN 0x0 8034 /* enum: Match Geneve traffic with this VNI */ 8035 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_GENEVE 0x1 8036 /* enum: Reserved for experimental development use */ 8037 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_EXPERIMENTAL 0xfe 8038 #define MC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_LBN 0 8039 #define MC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_WIDTH 24 8040 #define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_LBN 24 8041 #define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_WIDTH 8 8042 /* enum: Match NVGRE traffic with this VSID */ 8043 #define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_NVGRE 0x0 8044 /* source IP address to match (as bytes in network order; set last 12 bytes to 8045 * 0 for IPv4 address) 8046 */ 8047 #define MC_CMD_FILTER_OP_EXT_IN_SRC_IP_OFST 76 8048 #define MC_CMD_FILTER_OP_EXT_IN_SRC_IP_LEN 16 8049 /* destination IP address to match (as bytes in network order; set last 12 8050 * bytes to 0 for IPv4 address) 8051 */ 8052 #define MC_CMD_FILTER_OP_EXT_IN_DST_IP_OFST 92 8053 #define MC_CMD_FILTER_OP_EXT_IN_DST_IP_LEN 16 8054 /* VXLAN/NVGRE inner frame source MAC address to match (as bytes in network 8055 * order) 8056 */ 8057 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_MAC_OFST 108 8058 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_MAC_LEN 6 8059 /* VXLAN/NVGRE inner frame source port to match (as bytes in network order) */ 8060 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_PORT_OFST 114 8061 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_PORT_LEN 2 8062 /* VXLAN/NVGRE inner frame destination MAC address to match (as bytes in 8063 * network order) 8064 */ 8065 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_MAC_OFST 116 8066 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_MAC_LEN 6 8067 /* VXLAN/NVGRE inner frame destination port to match (as bytes in network 8068 * order) 8069 */ 8070 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_PORT_OFST 122 8071 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_PORT_LEN 2 8072 /* VXLAN/NVGRE inner frame Ethernet type to match (as bytes in network order) 8073 */ 8074 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_ETHER_TYPE_OFST 124 8075 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_ETHER_TYPE_LEN 2 8076 /* VXLAN/NVGRE inner frame Inner VLAN tag to match (as bytes in network order) 8077 */ 8078 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_INNER_VLAN_OFST 126 8079 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_INNER_VLAN_LEN 2 8080 /* VXLAN/NVGRE inner frame Outer VLAN tag to match (as bytes in network order) 8081 */ 8082 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_OUTER_VLAN_OFST 128 8083 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_OUTER_VLAN_LEN 2 8084 /* VXLAN/NVGRE inner frame IP protocol to match (in low byte; set high byte to 8085 * 0) 8086 */ 8087 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_IP_PROTO_OFST 130 8088 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_IP_PROTO_LEN 2 8089 /* VXLAN/NVGRE inner frame Firmware defined register 0 to match (reserved; set 8090 * to 0) 8091 */ 8092 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF0_OFST 132 8093 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF0_LEN 4 8094 /* VXLAN/NVGRE inner frame Firmware defined register 1 to match (reserved; set 8095 * to 0) 8096 */ 8097 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF1_OFST 136 8098 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF1_LEN 4 8099 /* VXLAN/NVGRE inner frame source IP address to match (as bytes in network 8100 * order; set last 12 bytes to 0 for IPv4 address) 8101 */ 8102 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_IP_OFST 140 8103 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_IP_LEN 16 8104 /* VXLAN/NVGRE inner frame destination IP address to match (as bytes in network 8105 * order; set last 12 bytes to 0 for IPv4 address) 8106 */ 8107 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_IP_OFST 156 8108 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_IP_LEN 16 8109 8110 /* MC_CMD_FILTER_OP_OUT msgresponse */ 8111 #define MC_CMD_FILTER_OP_OUT_LEN 12 8112 /* identifies the type of operation requested */ 8113 #define MC_CMD_FILTER_OP_OUT_OP_OFST 0 8114 #define MC_CMD_FILTER_OP_OUT_OP_LEN 4 8115 /* Enum values, see field(s): */ 8116 /* MC_CMD_FILTER_OP_IN/OP */ 8117 /* Returned filter handle (for insert / subscribe operations). Note that these 8118 * handles should be considered opaque to the host, although a value of 8119 * 0xFFFFFFFF_FFFFFFFF is guaranteed never to be a valid handle. 8120 */ 8121 #define MC_CMD_FILTER_OP_OUT_HANDLE_OFST 4 8122 #define MC_CMD_FILTER_OP_OUT_HANDLE_LEN 8 8123 #define MC_CMD_FILTER_OP_OUT_HANDLE_LO_OFST 4 8124 #define MC_CMD_FILTER_OP_OUT_HANDLE_HI_OFST 8 8125 /* enum: guaranteed invalid filter handle (low 32 bits) */ 8126 #define MC_CMD_FILTER_OP_OUT_HANDLE_LO_INVALID 0xffffffff 8127 /* enum: guaranteed invalid filter handle (high 32 bits) */ 8128 #define MC_CMD_FILTER_OP_OUT_HANDLE_HI_INVALID 0xffffffff 8129 8130 /* MC_CMD_FILTER_OP_EXT_OUT msgresponse */ 8131 #define MC_CMD_FILTER_OP_EXT_OUT_LEN 12 8132 /* identifies the type of operation requested */ 8133 #define MC_CMD_FILTER_OP_EXT_OUT_OP_OFST 0 8134 #define MC_CMD_FILTER_OP_EXT_OUT_OP_LEN 4 8135 /* Enum values, see field(s): */ 8136 /* MC_CMD_FILTER_OP_EXT_IN/OP */ 8137 /* Returned filter handle (for insert / subscribe operations). Note that these 8138 * handles should be considered opaque to the host, although a value of 8139 * 0xFFFFFFFF_FFFFFFFF is guaranteed never to be a valid handle. 8140 */ 8141 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_OFST 4 8142 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LEN 8 8143 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LO_OFST 4 8144 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_HI_OFST 8 8145 /* Enum values, see field(s): */ 8146 /* MC_CMD_FILTER_OP_OUT/HANDLE */ 8147 8148 8149 /***********************************/ 8150 /* MC_CMD_GET_PARSER_DISP_INFO 8151 * Get information related to the parser-dispatcher subsystem 8152 */ 8153 #define MC_CMD_GET_PARSER_DISP_INFO 0xe4 8154 #undef MC_CMD_0xe4_PRIVILEGE_CTG 8155 8156 #define MC_CMD_0xe4_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8157 8158 /* MC_CMD_GET_PARSER_DISP_INFO_IN msgrequest */ 8159 #define MC_CMD_GET_PARSER_DISP_INFO_IN_LEN 4 8160 /* identifies the type of operation requested */ 8161 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_OFST 0 8162 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_LEN 4 8163 /* enum: read the list of supported RX filter matches */ 8164 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES 0x1 8165 /* enum: read flags indicating restrictions on filter insertion for the calling 8166 * client 8167 */ 8168 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_RESTRICTIONS 0x2 8169 /* enum: read properties relating to security rules (Medford-only; for use by 8170 * SolarSecure apps, not directly by drivers. See SF-114946-SW.) 8171 */ 8172 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SECURITY_RULE_INFO 0x3 8173 /* enum: read the list of supported RX filter matches for VXLAN/NVGRE 8174 * encapsulated frames, which follow a different match sequence to normal 8175 * frames (Medford only) 8176 */ 8177 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_ENCAP_RX_MATCHES 0x4 8178 8179 /* MC_CMD_GET_PARSER_DISP_INFO_OUT msgresponse */ 8180 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMIN 8 8181 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX 252 8182 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_LEN(num) (8+4*(num)) 8183 /* identifies the type of operation requested */ 8184 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_OP_OFST 0 8185 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_OP_LEN 4 8186 /* Enum values, see field(s): */ 8187 /* MC_CMD_GET_PARSER_DISP_INFO_IN/OP */ 8188 /* number of supported match types */ 8189 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_NUM_SUPPORTED_MATCHES_OFST 4 8190 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_NUM_SUPPORTED_MATCHES_LEN 4 8191 /* array of supported match types (valid MATCH_FIELDS values for 8192 * MC_CMD_FILTER_OP) sorted in decreasing priority order 8193 */ 8194 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_OFST 8 8195 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_LEN 4 8196 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MINNUM 0 8197 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM 61 8198 8199 /* MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT msgresponse */ 8200 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_LEN 8 8201 /* identifies the type of operation requested */ 8202 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_OP_OFST 0 8203 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_OP_LEN 4 8204 /* Enum values, see field(s): */ 8205 /* MC_CMD_GET_PARSER_DISP_INFO_IN/OP */ 8206 /* bitfield of filter insertion restrictions */ 8207 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_RESTRICTION_FLAGS_OFST 4 8208 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_RESTRICTION_FLAGS_LEN 4 8209 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_LBN 0 8210 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_WIDTH 1 8211 8212 /* MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT msgresponse: 8213 * GET_PARSER_DISP_INFO response format for OP_GET_SECURITY_RULE_INFO. 8214 * (Medford-only; for use by SolarSecure apps, not directly by drivers. See 8215 * SF-114946-SW.) NOTE - this message definition is provisional. It has not yet 8216 * been used in any released code and may change during development. This note 8217 * will be removed once it is regarded as stable. 8218 */ 8219 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_LEN 36 8220 /* identifies the type of operation requested */ 8221 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_OP_OFST 0 8222 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_OP_LEN 4 8223 /* Enum values, see field(s): */ 8224 /* MC_CMD_GET_PARSER_DISP_INFO_IN/OP */ 8225 /* a version number representing the set of rule lookups that are implemented 8226 * by the currently running firmware 8227 */ 8228 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_RULES_VERSION_OFST 4 8229 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_RULES_VERSION_LEN 4 8230 /* enum: implements lookup sequences described in SF-114946-SW draft C */ 8231 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_RULES_VERSION_SF_114946_SW_C 0x0 8232 /* the number of nodes in the subnet map */ 8233 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_MAP_NUM_NODES_OFST 8 8234 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_MAP_NUM_NODES_LEN 4 8235 /* the number of entries in one subnet map node */ 8236 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_MAP_NUM_ENTRIES_PER_NODE_OFST 12 8237 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_MAP_NUM_ENTRIES_PER_NODE_LEN 4 8238 /* minimum valid value for a subnet ID in a subnet map leaf */ 8239 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_ID_MIN_OFST 16 8240 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_ID_MIN_LEN 4 8241 /* maximum valid value for a subnet ID in a subnet map leaf */ 8242 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_ID_MAX_OFST 20 8243 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_ID_MAX_LEN 4 8244 /* the number of entries in the local and remote port range maps */ 8245 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_PORTRANGE_TREE_NUM_ENTRIES_OFST 24 8246 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_PORTRANGE_TREE_NUM_ENTRIES_LEN 4 8247 /* minimum valid value for a portrange ID in a port range map leaf */ 8248 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_PORTRANGE_ID_MIN_OFST 28 8249 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_PORTRANGE_ID_MIN_LEN 4 8250 /* maximum valid value for a portrange ID in a port range map leaf */ 8251 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_PORTRANGE_ID_MAX_OFST 32 8252 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_PORTRANGE_ID_MAX_LEN 4 8253 8254 8255 /***********************************/ 8256 /* MC_CMD_PARSER_DISP_RW 8257 * Direct read/write of parser-dispatcher state (DICPUs and LUE) for debugging. 8258 * Please note that this interface is only of use to debug tools which have 8259 * knowledge of firmware and hardware data structures; nothing here is intended 8260 * for use by normal driver code. Note that although this command is in the 8261 * Admin privilege group, in tamperproof adapters, only read operations are 8262 * permitted. 8263 */ 8264 #define MC_CMD_PARSER_DISP_RW 0xe5 8265 #undef MC_CMD_0xe5_PRIVILEGE_CTG 8266 8267 #define MC_CMD_0xe5_PRIVILEGE_CTG SRIOV_CTG_ADMIN 8268 8269 /* MC_CMD_PARSER_DISP_RW_IN msgrequest */ 8270 #define MC_CMD_PARSER_DISP_RW_IN_LEN 32 8271 /* identifies the target of the operation */ 8272 #define MC_CMD_PARSER_DISP_RW_IN_TARGET_OFST 0 8273 #define MC_CMD_PARSER_DISP_RW_IN_TARGET_LEN 4 8274 /* enum: RX dispatcher CPU */ 8275 #define MC_CMD_PARSER_DISP_RW_IN_RX_DICPU 0x0 8276 /* enum: TX dispatcher CPU */ 8277 #define MC_CMD_PARSER_DISP_RW_IN_TX_DICPU 0x1 8278 /* enum: Lookup engine (with original metadata format). Deprecated; used only 8279 * by cmdclient as a fallback for very old Huntington firmware, and not 8280 * supported in firmware beyond v6.4.0.1005. Use LUE_VERSIONED_METADATA 8281 * instead. 8282 */ 8283 #define MC_CMD_PARSER_DISP_RW_IN_LUE 0x2 8284 /* enum: Lookup engine (with requested metadata format) */ 8285 #define MC_CMD_PARSER_DISP_RW_IN_LUE_VERSIONED_METADATA 0x3 8286 /* enum: RX0 dispatcher CPU (alias for RX_DICPU; Medford has 2 RX DICPUs) */ 8287 #define MC_CMD_PARSER_DISP_RW_IN_RX0_DICPU 0x0 8288 /* enum: RX1 dispatcher CPU (only valid for Medford) */ 8289 #define MC_CMD_PARSER_DISP_RW_IN_RX1_DICPU 0x4 8290 /* enum: Miscellaneous other state (only valid for Medford) */ 8291 #define MC_CMD_PARSER_DISP_RW_IN_MISC_STATE 0x5 8292 /* identifies the type of operation requested */ 8293 #define MC_CMD_PARSER_DISP_RW_IN_OP_OFST 4 8294 #define MC_CMD_PARSER_DISP_RW_IN_OP_LEN 4 8295 /* enum: Read a word of DICPU DMEM or a LUE entry */ 8296 #define MC_CMD_PARSER_DISP_RW_IN_READ 0x0 8297 /* enum: Write a word of DICPU DMEM or a LUE entry. Not permitted on 8298 * tamperproof adapters. 8299 */ 8300 #define MC_CMD_PARSER_DISP_RW_IN_WRITE 0x1 8301 /* enum: Read-modify-write a word of DICPU DMEM (not valid for LUE). Not 8302 * permitted on tamperproof adapters. 8303 */ 8304 #define MC_CMD_PARSER_DISP_RW_IN_RMW 0x2 8305 /* data memory address (DICPU targets) or LUE index (LUE targets) */ 8306 #define MC_CMD_PARSER_DISP_RW_IN_ADDRESS_OFST 8 8307 #define MC_CMD_PARSER_DISP_RW_IN_ADDRESS_LEN 4 8308 /* selector (for MISC_STATE target) */ 8309 #define MC_CMD_PARSER_DISP_RW_IN_SELECTOR_OFST 8 8310 #define MC_CMD_PARSER_DISP_RW_IN_SELECTOR_LEN 4 8311 /* enum: Port to datapath mapping */ 8312 #define MC_CMD_PARSER_DISP_RW_IN_PORT_DP_MAPPING 0x1 8313 /* value to write (for DMEM writes) */ 8314 #define MC_CMD_PARSER_DISP_RW_IN_DMEM_WRITE_VALUE_OFST 12 8315 #define MC_CMD_PARSER_DISP_RW_IN_DMEM_WRITE_VALUE_LEN 4 8316 /* XOR value (for DMEM read-modify-writes: new = (old & mask) ^ value) */ 8317 #define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_XOR_VALUE_OFST 12 8318 #define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_XOR_VALUE_LEN 4 8319 /* AND mask (for DMEM read-modify-writes: new = (old & mask) ^ value) */ 8320 #define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_AND_MASK_OFST 16 8321 #define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_AND_MASK_LEN 4 8322 /* metadata format (for LUE reads using LUE_VERSIONED_METADATA) */ 8323 #define MC_CMD_PARSER_DISP_RW_IN_LUE_READ_METADATA_VERSION_OFST 12 8324 #define MC_CMD_PARSER_DISP_RW_IN_LUE_READ_METADATA_VERSION_LEN 4 8325 /* value to write (for LUE writes) */ 8326 #define MC_CMD_PARSER_DISP_RW_IN_LUE_WRITE_VALUE_OFST 12 8327 #define MC_CMD_PARSER_DISP_RW_IN_LUE_WRITE_VALUE_LEN 20 8328 8329 /* MC_CMD_PARSER_DISP_RW_OUT msgresponse */ 8330 #define MC_CMD_PARSER_DISP_RW_OUT_LEN 52 8331 /* value read (for DMEM reads) */ 8332 #define MC_CMD_PARSER_DISP_RW_OUT_DMEM_READ_VALUE_OFST 0 8333 #define MC_CMD_PARSER_DISP_RW_OUT_DMEM_READ_VALUE_LEN 4 8334 /* value read (for LUE reads) */ 8335 #define MC_CMD_PARSER_DISP_RW_OUT_LUE_READ_VALUE_OFST 0 8336 #define MC_CMD_PARSER_DISP_RW_OUT_LUE_READ_VALUE_LEN 20 8337 /* up to 8 32-bit words of additional soft state from the LUE manager (the 8338 * exact content is firmware-dependent and intended only for debug use) 8339 */ 8340 #define MC_CMD_PARSER_DISP_RW_OUT_LUE_MGR_STATE_OFST 20 8341 #define MC_CMD_PARSER_DISP_RW_OUT_LUE_MGR_STATE_LEN 32 8342 /* datapath(s) used for each port (for MISC_STATE PORT_DP_MAPPING selector) */ 8343 #define MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_OFST 0 8344 #define MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_LEN 4 8345 #define MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_NUM 4 8346 #define MC_CMD_PARSER_DISP_RW_OUT_DP0 0x1 /* enum */ 8347 #define MC_CMD_PARSER_DISP_RW_OUT_DP1 0x2 /* enum */ 8348 8349 8350 /***********************************/ 8351 /* MC_CMD_GET_PF_COUNT 8352 * Get number of PFs on the device. 8353 */ 8354 #define MC_CMD_GET_PF_COUNT 0xb6 8355 #undef MC_CMD_0xb6_PRIVILEGE_CTG 8356 8357 #define MC_CMD_0xb6_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8358 8359 /* MC_CMD_GET_PF_COUNT_IN msgrequest */ 8360 #define MC_CMD_GET_PF_COUNT_IN_LEN 0 8361 8362 /* MC_CMD_GET_PF_COUNT_OUT msgresponse */ 8363 #define MC_CMD_GET_PF_COUNT_OUT_LEN 1 8364 /* Identifies the number of PFs on the device. */ 8365 #define MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_OFST 0 8366 #define MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_LEN 1 8367 8368 8369 /***********************************/ 8370 /* MC_CMD_SET_PF_COUNT 8371 * Set number of PFs on the device. 8372 */ 8373 #define MC_CMD_SET_PF_COUNT 0xb7 8374 8375 /* MC_CMD_SET_PF_COUNT_IN msgrequest */ 8376 #define MC_CMD_SET_PF_COUNT_IN_LEN 4 8377 /* New number of PFs on the device. */ 8378 #define MC_CMD_SET_PF_COUNT_IN_PF_COUNT_OFST 0 8379 #define MC_CMD_SET_PF_COUNT_IN_PF_COUNT_LEN 4 8380 8381 /* MC_CMD_SET_PF_COUNT_OUT msgresponse */ 8382 #define MC_CMD_SET_PF_COUNT_OUT_LEN 0 8383 8384 8385 /***********************************/ 8386 /* MC_CMD_GET_PORT_ASSIGNMENT 8387 * Get port assignment for current PCI function. 8388 */ 8389 #define MC_CMD_GET_PORT_ASSIGNMENT 0xb8 8390 #undef MC_CMD_0xb8_PRIVILEGE_CTG 8391 8392 #define MC_CMD_0xb8_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8393 8394 /* MC_CMD_GET_PORT_ASSIGNMENT_IN msgrequest */ 8395 #define MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN 0 8396 8397 /* MC_CMD_GET_PORT_ASSIGNMENT_OUT msgresponse */ 8398 #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN 4 8399 /* Identifies the port assignment for this function. */ 8400 #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_PORT_OFST 0 8401 #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_PORT_LEN 4 8402 8403 8404 /***********************************/ 8405 /* MC_CMD_SET_PORT_ASSIGNMENT 8406 * Set port assignment for current PCI function. 8407 */ 8408 #define MC_CMD_SET_PORT_ASSIGNMENT 0xb9 8409 #undef MC_CMD_0xb9_PRIVILEGE_CTG 8410 8411 #define MC_CMD_0xb9_PRIVILEGE_CTG SRIOV_CTG_ADMIN 8412 8413 /* MC_CMD_SET_PORT_ASSIGNMENT_IN msgrequest */ 8414 #define MC_CMD_SET_PORT_ASSIGNMENT_IN_LEN 4 8415 /* Identifies the port assignment for this function. */ 8416 #define MC_CMD_SET_PORT_ASSIGNMENT_IN_PORT_OFST 0 8417 #define MC_CMD_SET_PORT_ASSIGNMENT_IN_PORT_LEN 4 8418 8419 /* MC_CMD_SET_PORT_ASSIGNMENT_OUT msgresponse */ 8420 #define MC_CMD_SET_PORT_ASSIGNMENT_OUT_LEN 0 8421 8422 8423 /***********************************/ 8424 /* MC_CMD_ALLOC_VIS 8425 * Allocate VIs for current PCI function. 8426 */ 8427 #define MC_CMD_ALLOC_VIS 0x8b 8428 #undef MC_CMD_0x8b_PRIVILEGE_CTG 8429 8430 #define MC_CMD_0x8b_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8431 8432 /* MC_CMD_ALLOC_VIS_IN msgrequest */ 8433 #define MC_CMD_ALLOC_VIS_IN_LEN 8 8434 /* The minimum number of VIs that is acceptable */ 8435 #define MC_CMD_ALLOC_VIS_IN_MIN_VI_COUNT_OFST 0 8436 #define MC_CMD_ALLOC_VIS_IN_MIN_VI_COUNT_LEN 4 8437 /* The maximum number of VIs that would be useful */ 8438 #define MC_CMD_ALLOC_VIS_IN_MAX_VI_COUNT_OFST 4 8439 #define MC_CMD_ALLOC_VIS_IN_MAX_VI_COUNT_LEN 4 8440 8441 /* MC_CMD_ALLOC_VIS_OUT msgresponse: Huntington-compatible VI_ALLOC request. 8442 * Use extended version in new code. 8443 */ 8444 #define MC_CMD_ALLOC_VIS_OUT_LEN 8 8445 /* The number of VIs allocated on this function */ 8446 #define MC_CMD_ALLOC_VIS_OUT_VI_COUNT_OFST 0 8447 #define MC_CMD_ALLOC_VIS_OUT_VI_COUNT_LEN 4 8448 /* The base absolute VI number allocated to this function. Required to 8449 * correctly interpret wakeup events. 8450 */ 8451 #define MC_CMD_ALLOC_VIS_OUT_VI_BASE_OFST 4 8452 #define MC_CMD_ALLOC_VIS_OUT_VI_BASE_LEN 4 8453 8454 /* MC_CMD_ALLOC_VIS_EXT_OUT msgresponse */ 8455 #define MC_CMD_ALLOC_VIS_EXT_OUT_LEN 12 8456 /* The number of VIs allocated on this function */ 8457 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_COUNT_OFST 0 8458 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_COUNT_LEN 4 8459 /* The base absolute VI number allocated to this function. Required to 8460 * correctly interpret wakeup events. 8461 */ 8462 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_BASE_OFST 4 8463 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_BASE_LEN 4 8464 /* Function's port vi_shift value (always 0 on Huntington) */ 8465 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_SHIFT_OFST 8 8466 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_SHIFT_LEN 4 8467 8468 8469 /***********************************/ 8470 /* MC_CMD_FREE_VIS 8471 * Free VIs for current PCI function. Any linked PIO buffers will be unlinked, 8472 * but not freed. 8473 */ 8474 #define MC_CMD_FREE_VIS 0x8c 8475 #undef MC_CMD_0x8c_PRIVILEGE_CTG 8476 8477 #define MC_CMD_0x8c_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8478 8479 /* MC_CMD_FREE_VIS_IN msgrequest */ 8480 #define MC_CMD_FREE_VIS_IN_LEN 0 8481 8482 /* MC_CMD_FREE_VIS_OUT msgresponse */ 8483 #define MC_CMD_FREE_VIS_OUT_LEN 0 8484 8485 8486 /***********************************/ 8487 /* MC_CMD_GET_SRIOV_CFG 8488 * Get SRIOV config for this PF. 8489 */ 8490 #define MC_CMD_GET_SRIOV_CFG 0xba 8491 #undef MC_CMD_0xba_PRIVILEGE_CTG 8492 8493 #define MC_CMD_0xba_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8494 8495 /* MC_CMD_GET_SRIOV_CFG_IN msgrequest */ 8496 #define MC_CMD_GET_SRIOV_CFG_IN_LEN 0 8497 8498 /* MC_CMD_GET_SRIOV_CFG_OUT msgresponse */ 8499 #define MC_CMD_GET_SRIOV_CFG_OUT_LEN 20 8500 /* Number of VFs currently enabled. */ 8501 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_CURRENT_OFST 0 8502 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_CURRENT_LEN 4 8503 /* Max number of VFs before sriov stride and offset may need to be changed. */ 8504 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_MAX_OFST 4 8505 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_MAX_LEN 4 8506 #define MC_CMD_GET_SRIOV_CFG_OUT_FLAGS_OFST 8 8507 #define MC_CMD_GET_SRIOV_CFG_OUT_FLAGS_LEN 4 8508 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_LBN 0 8509 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_WIDTH 1 8510 /* RID offset of first VF from PF. */ 8511 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_OFFSET_OFST 12 8512 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_OFFSET_LEN 4 8513 /* RID offset of each subsequent VF from the previous. */ 8514 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_STRIDE_OFST 16 8515 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_STRIDE_LEN 4 8516 8517 8518 /***********************************/ 8519 /* MC_CMD_SET_SRIOV_CFG 8520 * Set SRIOV config for this PF. 8521 */ 8522 #define MC_CMD_SET_SRIOV_CFG 0xbb 8523 #undef MC_CMD_0xbb_PRIVILEGE_CTG 8524 8525 #define MC_CMD_0xbb_PRIVILEGE_CTG SRIOV_CTG_ADMIN 8526 8527 /* MC_CMD_SET_SRIOV_CFG_IN msgrequest */ 8528 #define MC_CMD_SET_SRIOV_CFG_IN_LEN 20 8529 /* Number of VFs currently enabled. */ 8530 #define MC_CMD_SET_SRIOV_CFG_IN_VF_CURRENT_OFST 0 8531 #define MC_CMD_SET_SRIOV_CFG_IN_VF_CURRENT_LEN 4 8532 /* Max number of VFs before sriov stride and offset may need to be changed. */ 8533 #define MC_CMD_SET_SRIOV_CFG_IN_VF_MAX_OFST 4 8534 #define MC_CMD_SET_SRIOV_CFG_IN_VF_MAX_LEN 4 8535 #define MC_CMD_SET_SRIOV_CFG_IN_FLAGS_OFST 8 8536 #define MC_CMD_SET_SRIOV_CFG_IN_FLAGS_LEN 4 8537 #define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_LBN 0 8538 #define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_WIDTH 1 8539 /* RID offset of first VF from PF, or 0 for no change, or 8540 * MC_CMD_RESOURCE_INSTANCE_ANY to allow the system to allocate an offset. 8541 */ 8542 #define MC_CMD_SET_SRIOV_CFG_IN_VF_OFFSET_OFST 12 8543 #define MC_CMD_SET_SRIOV_CFG_IN_VF_OFFSET_LEN 4 8544 /* RID offset of each subsequent VF from the previous, 0 for no change, or 8545 * MC_CMD_RESOURCE_INSTANCE_ANY to allow the system to allocate a stride. 8546 */ 8547 #define MC_CMD_SET_SRIOV_CFG_IN_VF_STRIDE_OFST 16 8548 #define MC_CMD_SET_SRIOV_CFG_IN_VF_STRIDE_LEN 4 8549 8550 /* MC_CMD_SET_SRIOV_CFG_OUT msgresponse */ 8551 #define MC_CMD_SET_SRIOV_CFG_OUT_LEN 0 8552 8553 8554 /***********************************/ 8555 /* MC_CMD_GET_VI_ALLOC_INFO 8556 * Get information about number of VI's and base VI number allocated to this 8557 * function. 8558 */ 8559 #define MC_CMD_GET_VI_ALLOC_INFO 0x8d 8560 #undef MC_CMD_0x8d_PRIVILEGE_CTG 8561 8562 #define MC_CMD_0x8d_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8563 8564 /* MC_CMD_GET_VI_ALLOC_INFO_IN msgrequest */ 8565 #define MC_CMD_GET_VI_ALLOC_INFO_IN_LEN 0 8566 8567 /* MC_CMD_GET_VI_ALLOC_INFO_OUT msgresponse */ 8568 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_LEN 12 8569 /* The number of VIs allocated on this function */ 8570 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_COUNT_OFST 0 8571 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_COUNT_LEN 4 8572 /* The base absolute VI number allocated to this function. Required to 8573 * correctly interpret wakeup events. 8574 */ 8575 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_BASE_OFST 4 8576 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_BASE_LEN 4 8577 /* Function's port vi_shift value (always 0 on Huntington) */ 8578 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_SHIFT_OFST 8 8579 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_SHIFT_LEN 4 8580 8581 8582 /***********************************/ 8583 /* MC_CMD_DUMP_VI_STATE 8584 * For CmdClient use. Dump pertinent information on a specific absolute VI. 8585 */ 8586 #define MC_CMD_DUMP_VI_STATE 0x8e 8587 #undef MC_CMD_0x8e_PRIVILEGE_CTG 8588 8589 #define MC_CMD_0x8e_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8590 8591 /* MC_CMD_DUMP_VI_STATE_IN msgrequest */ 8592 #define MC_CMD_DUMP_VI_STATE_IN_LEN 4 8593 /* The VI number to query. */ 8594 #define MC_CMD_DUMP_VI_STATE_IN_VI_NUMBER_OFST 0 8595 #define MC_CMD_DUMP_VI_STATE_IN_VI_NUMBER_LEN 4 8596 8597 /* MC_CMD_DUMP_VI_STATE_OUT msgresponse */ 8598 #define MC_CMD_DUMP_VI_STATE_OUT_LEN 96 8599 /* The PF part of the function owning this VI. */ 8600 #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_OFST 0 8601 #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_LEN 2 8602 /* The VF part of the function owning this VI. */ 8603 #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_VF_OFST 2 8604 #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_VF_LEN 2 8605 /* Base of VIs allocated to this function. */ 8606 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_BASE_OFST 4 8607 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_BASE_LEN 2 8608 /* Count of VIs allocated to the owner function. */ 8609 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_COUNT_OFST 6 8610 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_COUNT_LEN 2 8611 /* Base interrupt vector allocated to this function. */ 8612 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_BASE_OFST 8 8613 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_BASE_LEN 2 8614 /* Number of interrupt vectors allocated to this function. */ 8615 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_COUNT_OFST 10 8616 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_COUNT_LEN 2 8617 /* Raw evq ptr table data. */ 8618 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_OFST 12 8619 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LEN 8 8620 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LO_OFST 12 8621 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_HI_OFST 16 8622 /* Raw evq timer table data. */ 8623 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_OFST 20 8624 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LEN 8 8625 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LO_OFST 20 8626 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_HI_OFST 24 8627 /* Combined metadata field. */ 8628 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_OFST 28 8629 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_LEN 4 8630 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_LBN 0 8631 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_WIDTH 16 8632 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_LBN 16 8633 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_WIDTH 8 8634 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_LBN 24 8635 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_WIDTH 8 8636 /* TXDPCPU raw table data for queue. */ 8637 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_OFST 32 8638 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LEN 8 8639 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LO_OFST 32 8640 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_HI_OFST 36 8641 /* TXDPCPU raw table data for queue. */ 8642 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_OFST 40 8643 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LEN 8 8644 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LO_OFST 40 8645 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_HI_OFST 44 8646 /* TXDPCPU raw table data for queue. */ 8647 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_OFST 48 8648 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LEN 8 8649 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LO_OFST 48 8650 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_HI_OFST 52 8651 /* Combined metadata field. */ 8652 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_OFST 56 8653 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LEN 8 8654 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LO_OFST 56 8655 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_HI_OFST 60 8656 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_LBN 0 8657 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_WIDTH 16 8658 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_LBN 16 8659 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_WIDTH 8 8660 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_LBN 24 8661 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_WIDTH 8 8662 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_LBN 32 8663 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_WIDTH 8 8664 #define MC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_LBN 40 8665 #define MC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_WIDTH 24 8666 /* RXDPCPU raw table data for queue. */ 8667 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_OFST 64 8668 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LEN 8 8669 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LO_OFST 64 8670 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_HI_OFST 68 8671 /* RXDPCPU raw table data for queue. */ 8672 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_OFST 72 8673 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LEN 8 8674 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LO_OFST 72 8675 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_HI_OFST 76 8676 /* Reserved, currently 0. */ 8677 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_OFST 80 8678 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LEN 8 8679 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LO_OFST 80 8680 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_HI_OFST 84 8681 /* Combined metadata field. */ 8682 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_OFST 88 8683 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LEN 8 8684 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LO_OFST 88 8685 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_HI_OFST 92 8686 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_LBN 0 8687 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_WIDTH 16 8688 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_LBN 16 8689 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_WIDTH 8 8690 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_LBN 24 8691 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_WIDTH 8 8692 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_LBN 32 8693 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_WIDTH 8 8694 8695 8696 /***********************************/ 8697 /* MC_CMD_ALLOC_PIOBUF 8698 * Allocate a push I/O buffer for later use with a tx queue. 8699 */ 8700 #define MC_CMD_ALLOC_PIOBUF 0x8f 8701 #undef MC_CMD_0x8f_PRIVILEGE_CTG 8702 8703 #define MC_CMD_0x8f_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 8704 8705 /* MC_CMD_ALLOC_PIOBUF_IN msgrequest */ 8706 #define MC_CMD_ALLOC_PIOBUF_IN_LEN 0 8707 8708 /* MC_CMD_ALLOC_PIOBUF_OUT msgresponse */ 8709 #define MC_CMD_ALLOC_PIOBUF_OUT_LEN 4 8710 /* Handle for allocated push I/O buffer. */ 8711 #define MC_CMD_ALLOC_PIOBUF_OUT_PIOBUF_HANDLE_OFST 0 8712 #define MC_CMD_ALLOC_PIOBUF_OUT_PIOBUF_HANDLE_LEN 4 8713 8714 8715 /***********************************/ 8716 /* MC_CMD_FREE_PIOBUF 8717 * Free a push I/O buffer. 8718 */ 8719 #define MC_CMD_FREE_PIOBUF 0x90 8720 #undef MC_CMD_0x90_PRIVILEGE_CTG 8721 8722 #define MC_CMD_0x90_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 8723 8724 /* MC_CMD_FREE_PIOBUF_IN msgrequest */ 8725 #define MC_CMD_FREE_PIOBUF_IN_LEN 4 8726 /* Handle for allocated push I/O buffer. */ 8727 #define MC_CMD_FREE_PIOBUF_IN_PIOBUF_HANDLE_OFST 0 8728 #define MC_CMD_FREE_PIOBUF_IN_PIOBUF_HANDLE_LEN 4 8729 8730 /* MC_CMD_FREE_PIOBUF_OUT msgresponse */ 8731 #define MC_CMD_FREE_PIOBUF_OUT_LEN 0 8732 8733 8734 /***********************************/ 8735 /* MC_CMD_GET_VI_TLP_PROCESSING 8736 * Get TLP steering and ordering information for a VI. 8737 */ 8738 #define MC_CMD_GET_VI_TLP_PROCESSING 0xb0 8739 #undef MC_CMD_0xb0_PRIVILEGE_CTG 8740 8741 #define MC_CMD_0xb0_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8742 8743 /* MC_CMD_GET_VI_TLP_PROCESSING_IN msgrequest */ 8744 #define MC_CMD_GET_VI_TLP_PROCESSING_IN_LEN 4 8745 /* VI number to get information for. */ 8746 #define MC_CMD_GET_VI_TLP_PROCESSING_IN_INSTANCE_OFST 0 8747 #define MC_CMD_GET_VI_TLP_PROCESSING_IN_INSTANCE_LEN 4 8748 8749 /* MC_CMD_GET_VI_TLP_PROCESSING_OUT msgresponse */ 8750 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_LEN 4 8751 /* Transaction processing steering hint 1 for use with the Rx Queue. */ 8752 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG1_RX_OFST 0 8753 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG1_RX_LEN 1 8754 /* Transaction processing steering hint 2 for use with the Ev Queue. */ 8755 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG2_EV_OFST 1 8756 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG2_EV_LEN 1 8757 /* Use Relaxed ordering model for TLPs on this VI. */ 8758 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_RELAXED_ORDERING_LBN 16 8759 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_RELAXED_ORDERING_WIDTH 1 8760 /* Use ID based ordering for TLPs on this VI. */ 8761 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_ID_BASED_ORDERING_LBN 17 8762 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_ID_BASED_ORDERING_WIDTH 1 8763 /* Set no snoop bit for TLPs on this VI. */ 8764 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_NO_SNOOP_LBN 18 8765 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_NO_SNOOP_WIDTH 1 8766 /* Enable TPH for TLPs on this VI. */ 8767 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_ON_LBN 19 8768 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_ON_WIDTH 1 8769 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_DATA_OFST 0 8770 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_DATA_LEN 4 8771 8772 8773 /***********************************/ 8774 /* MC_CMD_SET_VI_TLP_PROCESSING 8775 * Set TLP steering and ordering information for a VI. 8776 */ 8777 #define MC_CMD_SET_VI_TLP_PROCESSING 0xb1 8778 #undef MC_CMD_0xb1_PRIVILEGE_CTG 8779 8780 #define MC_CMD_0xb1_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8781 8782 /* MC_CMD_SET_VI_TLP_PROCESSING_IN msgrequest */ 8783 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_LEN 8 8784 /* VI number to set information for. */ 8785 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_INSTANCE_OFST 0 8786 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_INSTANCE_LEN 4 8787 /* Transaction processing steering hint 1 for use with the Rx Queue. */ 8788 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG1_RX_OFST 4 8789 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG1_RX_LEN 1 8790 /* Transaction processing steering hint 2 for use with the Ev Queue. */ 8791 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG2_EV_OFST 5 8792 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG2_EV_LEN 1 8793 /* Use Relaxed ordering model for TLPs on this VI. */ 8794 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_RELAXED_ORDERING_LBN 48 8795 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_RELAXED_ORDERING_WIDTH 1 8796 /* Use ID based ordering for TLPs on this VI. */ 8797 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_ID_BASED_ORDERING_LBN 49 8798 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_ID_BASED_ORDERING_WIDTH 1 8799 /* Set the no snoop bit for TLPs on this VI. */ 8800 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_NO_SNOOP_LBN 50 8801 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_NO_SNOOP_WIDTH 1 8802 /* Enable TPH for TLPs on this VI. */ 8803 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_ON_LBN 51 8804 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_ON_WIDTH 1 8805 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_DATA_OFST 4 8806 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_DATA_LEN 4 8807 8808 /* MC_CMD_SET_VI_TLP_PROCESSING_OUT msgresponse */ 8809 #define MC_CMD_SET_VI_TLP_PROCESSING_OUT_LEN 0 8810 8811 8812 /***********************************/ 8813 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS 8814 * Get global PCIe steering and transaction processing configuration. 8815 */ 8816 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS 0xbc 8817 #undef MC_CMD_0xbc_PRIVILEGE_CTG 8818 8819 #define MC_CMD_0xbc_PRIVILEGE_CTG SRIOV_CTG_ADMIN 8820 8821 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN msgrequest */ 8822 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_LEN 4 8823 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_OFST 0 8824 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_LEN 4 8825 /* enum: MISC. */ 8826 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_MISC 0x0 8827 /* enum: IDO. */ 8828 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_IDO 0x1 8829 /* enum: RO. */ 8830 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_RO 0x2 8831 /* enum: TPH Type. */ 8832 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_TPH_TYPE 0x3 8833 8834 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT msgresponse */ 8835 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_LEN 8 8836 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_GLOBAL_CATEGORY_OFST 0 8837 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_GLOBAL_CATEGORY_LEN 4 8838 /* Enum values, see field(s): */ 8839 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN/TLP_GLOBAL_CATEGORY */ 8840 /* Amalgamated TLP info word. */ 8841 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_WORD_OFST 4 8842 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_WORD_LEN 4 8843 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_LBN 0 8844 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_WIDTH 1 8845 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_LBN 1 8846 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_WIDTH 31 8847 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_LBN 0 8848 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_WIDTH 1 8849 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_LBN 1 8850 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_WIDTH 1 8851 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_EV_EN_LBN 2 8852 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_EV_EN_WIDTH 1 8853 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_LBN 3 8854 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_WIDTH 1 8855 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_LBN 4 8856 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_WIDTH 28 8857 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_LBN 0 8858 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_WIDTH 1 8859 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_LBN 1 8860 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_WIDTH 1 8861 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_LBN 2 8862 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_WIDTH 1 8863 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_LBN 3 8864 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_WIDTH 29 8865 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_LBN 0 8866 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_WIDTH 2 8867 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_DL_LBN 2 8868 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_DL_WIDTH 2 8869 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_LBN 4 8870 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_WIDTH 2 8871 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_EV_LBN 6 8872 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_EV_WIDTH 2 8873 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_LBN 8 8874 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_WIDTH 2 8875 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_LBN 9 8876 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_WIDTH 23 8877 8878 8879 /***********************************/ 8880 /* MC_CMD_SET_TLP_PROCESSING_GLOBALS 8881 * Set global PCIe steering and transaction processing configuration. 8882 */ 8883 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS 0xbd 8884 #undef MC_CMD_0xbd_PRIVILEGE_CTG 8885 8886 #define MC_CMD_0xbd_PRIVILEGE_CTG SRIOV_CTG_ADMIN 8887 8888 /* MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN msgrequest */ 8889 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_LEN 8 8890 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_OFST 0 8891 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_LEN 4 8892 /* Enum values, see field(s): */ 8893 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS/MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN/TLP_GLOBAL_CATEGORY */ 8894 /* Amalgamated TLP info word. */ 8895 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_WORD_OFST 4 8896 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_WORD_LEN 4 8897 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_LBN 0 8898 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_WIDTH 1 8899 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_LBN 0 8900 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_WIDTH 1 8901 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_LBN 1 8902 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_WIDTH 1 8903 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_EV_EN_LBN 2 8904 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_EV_EN_WIDTH 1 8905 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_RX_EN_LBN 3 8906 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_RX_EN_WIDTH 1 8907 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_LBN 0 8908 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_WIDTH 1 8909 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_LBN 1 8910 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_WIDTH 1 8911 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_DL_EN_LBN 2 8912 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_DL_EN_WIDTH 1 8913 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_LBN 0 8914 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_WIDTH 2 8915 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_DL_LBN 2 8916 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_DL_WIDTH 2 8917 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_LBN 4 8918 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_WIDTH 2 8919 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_EV_LBN 6 8920 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_EV_WIDTH 2 8921 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_LBN 8 8922 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_WIDTH 2 8923 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_LBN 10 8924 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_WIDTH 22 8925 8926 /* MC_CMD_SET_TLP_PROCESSING_GLOBALS_OUT msgresponse */ 8927 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_OUT_LEN 0 8928 8929 8930 /***********************************/ 8931 /* MC_CMD_SATELLITE_DOWNLOAD 8932 * Download a new set of images to the satellite CPUs from the host. 8933 */ 8934 #define MC_CMD_SATELLITE_DOWNLOAD 0x91 8935 #undef MC_CMD_0x91_PRIVILEGE_CTG 8936 8937 #define MC_CMD_0x91_PRIVILEGE_CTG SRIOV_CTG_ADMIN 8938 8939 /* MC_CMD_SATELLITE_DOWNLOAD_IN msgrequest: The reset requirements for the CPUs 8940 * are subtle, and so downloads must proceed in a number of phases. 8941 * 8942 * 1) PHASE_RESET with a target of TARGET_ALL and chunk ID/length of 0. 8943 * 8944 * 2) PHASE_IMEMS for each of the IMEM targets (target IDs 0-11). Each download 8945 * may consist of multiple chunks. The final chunk (with CHUNK_ID_LAST) should 8946 * be a checksum (a simple 32-bit sum) of the transferred data. An individual 8947 * download may be aborted using CHUNK_ID_ABORT. 8948 * 8949 * 3) PHASE_VECTORS for each of the vector table targets (target IDs 12-15), 8950 * similar to PHASE_IMEMS. 8951 * 8952 * 4) PHASE_READY with a target of TARGET_ALL and chunk ID/length of 0. 8953 * 8954 * After any error (a requested abort is not considered to be an error) the 8955 * sequence must be restarted from PHASE_RESET. 8956 */ 8957 #define MC_CMD_SATELLITE_DOWNLOAD_IN_LENMIN 20 8958 #define MC_CMD_SATELLITE_DOWNLOAD_IN_LENMAX 252 8959 #define MC_CMD_SATELLITE_DOWNLOAD_IN_LEN(num) (16+4*(num)) 8960 /* Download phase. (Note: the IDLE phase is used internally and is never valid 8961 * in a command from the host.) 8962 */ 8963 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_OFST 0 8964 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_LEN 4 8965 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_IDLE 0x0 /* enum */ 8966 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_RESET 0x1 /* enum */ 8967 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_IMEMS 0x2 /* enum */ 8968 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_VECTORS 0x3 /* enum */ 8969 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_READY 0x4 /* enum */ 8970 /* Target for download. (These match the blob numbers defined in 8971 * mc_flash_layout.h.) 8972 */ 8973 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_OFST 4 8974 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_LEN 4 8975 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 8976 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_TEXT 0x0 8977 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 8978 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_TEXT 0x1 8979 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 8980 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDP_TEXT 0x2 8981 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 8982 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDP_TEXT 0x3 8983 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 8984 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_LUT 0x4 8985 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 8986 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_LUT_CFG 0x5 8987 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 8988 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_LUT 0x6 8989 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 8990 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_LUT_CFG 0x7 8991 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 8992 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_PGM 0x8 8993 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 8994 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_SL_PGM 0x9 8995 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 8996 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_PGM 0xa 8997 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 8998 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_SL_PGM 0xb 8999 /* enum: Valid in phase 3 (PHASE_VECTORS) only */ 9000 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_VTBL0 0xc 9001 /* enum: Valid in phase 3 (PHASE_VECTORS) only */ 9002 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_VTBL0 0xd 9003 /* enum: Valid in phase 3 (PHASE_VECTORS) only */ 9004 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_VTBL1 0xe 9005 /* enum: Valid in phase 3 (PHASE_VECTORS) only */ 9006 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_VTBL1 0xf 9007 /* enum: Valid in phases 1 (PHASE_RESET) and 4 (PHASE_READY) only */ 9008 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_ALL 0xffffffff 9009 /* Chunk ID, or CHUNK_ID_LAST or CHUNK_ID_ABORT */ 9010 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_OFST 8 9011 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_LEN 4 9012 /* enum: Last chunk, containing checksum rather than data */ 9013 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_LAST 0xffffffff 9014 /* enum: Abort download of this item */ 9015 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_ABORT 0xfffffffe 9016 /* Length of this chunk in bytes */ 9017 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_LEN_OFST 12 9018 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_LEN_LEN 4 9019 /* Data for this chunk */ 9020 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_OFST 16 9021 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_LEN 4 9022 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_MINNUM 1 9023 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_MAXNUM 59 9024 9025 /* MC_CMD_SATELLITE_DOWNLOAD_OUT msgresponse */ 9026 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_LEN 8 9027 /* Same as MC_CMD_ERR field, but included as 0 in success cases */ 9028 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_RESULT_OFST 0 9029 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_RESULT_LEN 4 9030 /* Extra status information */ 9031 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_INFO_OFST 4 9032 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_INFO_LEN 4 9033 /* enum: Code download OK, completed. */ 9034 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_COMPLETE 0x0 9035 /* enum: Code download aborted as requested. */ 9036 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_ABORTED 0x1 9037 /* enum: Code download OK so far, send next chunk. */ 9038 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_NEXT_CHUNK 0x2 9039 /* enum: Download phases out of sequence */ 9040 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_PHASE 0x100 9041 /* enum: Bad target for this phase */ 9042 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_TARGET 0x101 9043 /* enum: Chunk ID out of sequence */ 9044 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHUNK_ID 0x200 9045 /* enum: Chunk length zero or too large */ 9046 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHUNK_LEN 0x201 9047 /* enum: Checksum was incorrect */ 9048 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHECKSUM 0x300 9049 9050 9051 /***********************************/ 9052 /* MC_CMD_GET_CAPABILITIES 9053 * Get device capabilities. 9054 * 9055 * This is supplementary to the MC_CMD_GET_BOARD_CFG command, and intended to 9056 * reference inherent device capabilities as opposed to current NVRAM config. 9057 */ 9058 #define MC_CMD_GET_CAPABILITIES 0xbe 9059 #undef MC_CMD_0xbe_PRIVILEGE_CTG 9060 9061 #define MC_CMD_0xbe_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9062 9063 /* MC_CMD_GET_CAPABILITIES_IN msgrequest */ 9064 #define MC_CMD_GET_CAPABILITIES_IN_LEN 0 9065 9066 /* MC_CMD_GET_CAPABILITIES_OUT msgresponse */ 9067 #define MC_CMD_GET_CAPABILITIES_OUT_LEN 20 9068 /* First word of flags. */ 9069 #define MC_CMD_GET_CAPABILITIES_OUT_FLAGS1_OFST 0 9070 #define MC_CMD_GET_CAPABILITIES_OUT_FLAGS1_LEN 4 9071 #define MC_CMD_GET_CAPABILITIES_OUT_VPORT_RECONFIGURE_LBN 3 9072 #define MC_CMD_GET_CAPABILITIES_OUT_VPORT_RECONFIGURE_WIDTH 1 9073 #define MC_CMD_GET_CAPABILITIES_OUT_TX_STRIPING_LBN 4 9074 #define MC_CMD_GET_CAPABILITIES_OUT_TX_STRIPING_WIDTH 1 9075 #define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_LBN 5 9076 #define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_WIDTH 1 9077 #define MC_CMD_GET_CAPABILITIES_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6 9078 #define MC_CMD_GET_CAPABILITIES_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1 9079 #define MC_CMD_GET_CAPABILITIES_OUT_DRV_ATTACH_PREBOOT_LBN 7 9080 #define MC_CMD_GET_CAPABILITIES_OUT_DRV_ATTACH_PREBOOT_WIDTH 1 9081 #define MC_CMD_GET_CAPABILITIES_OUT_RX_FORCE_EVENT_MERGING_LBN 8 9082 #define MC_CMD_GET_CAPABILITIES_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1 9083 #define MC_CMD_GET_CAPABILITIES_OUT_SET_MAC_ENHANCED_LBN 9 9084 #define MC_CMD_GET_CAPABILITIES_OUT_SET_MAC_ENHANCED_WIDTH 1 9085 #define MC_CMD_GET_CAPABILITIES_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10 9086 #define MC_CMD_GET_CAPABILITIES_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1 9087 #define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11 9088 #define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1 9089 #define MC_CMD_GET_CAPABILITIES_OUT_TX_MAC_SECURITY_FILTERING_LBN 12 9090 #define MC_CMD_GET_CAPABILITIES_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1 9091 #define MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_LBN 13 9092 #define MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_WIDTH 1 9093 #define MC_CMD_GET_CAPABILITIES_OUT_QBB_LBN 14 9094 #define MC_CMD_GET_CAPABILITIES_OUT_QBB_WIDTH 1 9095 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15 9096 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1 9097 #define MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_LBN 16 9098 #define MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_WIDTH 1 9099 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_LBN 17 9100 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_WIDTH 1 9101 #define MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_LBN 18 9102 #define MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_WIDTH 1 9103 #define MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_LBN 19 9104 #define MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_WIDTH 1 9105 #define MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_LBN 20 9106 #define MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_WIDTH 1 9107 #define MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN 21 9108 #define MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_WIDTH 1 9109 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_LBN 22 9110 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_WIDTH 1 9111 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN 23 9112 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_WIDTH 1 9113 #define MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_LBN 24 9114 #define MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_WIDTH 1 9115 #define MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN 25 9116 #define MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_WIDTH 1 9117 #define MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_LBN 26 9118 #define MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_WIDTH 1 9119 #define MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN 27 9120 #define MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1 9121 #define MC_CMD_GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER_LBN 28 9122 #define MC_CMD_GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER_WIDTH 1 9123 #define MC_CMD_GET_CAPABILITIES_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29 9124 #define MC_CMD_GET_CAPABILITIES_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1 9125 #define MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN 30 9126 #define MC_CMD_GET_CAPABILITIES_OUT_EVB_WIDTH 1 9127 #define MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN 31 9128 #define MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_WIDTH 1 9129 /* RxDPCPU firmware id. */ 9130 #define MC_CMD_GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID_OFST 4 9131 #define MC_CMD_GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID_LEN 2 9132 /* enum: Standard RXDP firmware */ 9133 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP 0x0 9134 /* enum: Low latency RXDP firmware */ 9135 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_LOW_LATENCY 0x1 9136 /* enum: Packed stream RXDP firmware */ 9137 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_PACKED_STREAM 0x2 9138 /* enum: Rules engine RXDP firmware */ 9139 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_RULES_ENGINE 0x5 9140 /* enum: BIST RXDP firmware */ 9141 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_BIST 0x10a 9142 /* enum: RXDP Test firmware image 1 */ 9143 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101 9144 /* enum: RXDP Test firmware image 2 */ 9145 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102 9146 /* enum: RXDP Test firmware image 3 */ 9147 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103 9148 /* enum: RXDP Test firmware image 4 */ 9149 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104 9150 /* enum: RXDP Test firmware image 5 */ 9151 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_BACKPRESSURE 0x105 9152 /* enum: RXDP Test firmware image 6 */ 9153 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106 9154 /* enum: RXDP Test firmware image 7 */ 9155 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107 9156 /* enum: RXDP Test firmware image 8 */ 9157 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_DISABLE_DL 0x108 9158 /* enum: RXDP Test firmware image 9 */ 9159 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b 9160 /* enum: RXDP Test firmware image 10 */ 9161 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_SLOW 0x10c 9162 /* TxDPCPU firmware id. */ 9163 #define MC_CMD_GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID_OFST 6 9164 #define MC_CMD_GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID_LEN 2 9165 /* enum: Standard TXDP firmware */ 9166 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP 0x0 9167 /* enum: Low latency TXDP firmware */ 9168 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_LOW_LATENCY 0x1 9169 /* enum: High packet rate TXDP firmware */ 9170 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_HIGH_PACKET_RATE 0x3 9171 /* enum: Rules engine TXDP firmware */ 9172 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_RULES_ENGINE 0x5 9173 /* enum: BIST TXDP firmware */ 9174 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_BIST 0x12d 9175 /* enum: TXDP Test firmware image 1 */ 9176 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_TSO_EDIT 0x101 9177 /* enum: TXDP Test firmware image 2 */ 9178 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102 9179 /* enum: TXDP CSR bus test firmware */ 9180 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_CSR 0x103 9181 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_OFST 8 9182 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_LEN 2 9183 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_LBN 0 9184 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_WIDTH 12 9185 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_LBN 12 9186 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4 9187 /* enum: reserved value - do not use (may indicate alternative interpretation 9188 * of REV field in future) 9189 */ 9190 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_RESERVED 0x0 9191 /* enum: Trivial RX PD firmware for early Huntington development (Huntington 9192 * development only) 9193 */ 9194 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1 9195 /* enum: RX PD firmware with approximately Siena-compatible behaviour 9196 * (Huntington development only) 9197 */ 9198 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2 9199 /* enum: Full featured RX PD production firmware */ 9200 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3 9201 /* enum: (deprecated original name for the FULL_FEATURED variant) */ 9202 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_VSWITCH 0x3 9203 /* enum: siena_compat variant RX PD firmware using PM rather than MAC 9204 * (Huntington development only) 9205 */ 9206 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 9207 /* enum: Low latency RX PD production firmware */ 9208 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5 9209 /* enum: Packed stream RX PD production firmware */ 9210 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6 9211 /* enum: RX PD firmware handling layer 2 only for high packet rate performance 9212 * tests (Medford development only) 9213 */ 9214 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7 9215 /* enum: Rules engine RX PD production firmware */ 9216 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8 9217 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 9218 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 9219 /* enum: RX PD firmware parsing but not filtering network overlay tunnel 9220 * encapsulations (Medford development only) 9221 */ 9222 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf 9223 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_OFST 10 9224 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_LEN 2 9225 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_LBN 0 9226 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_WIDTH 12 9227 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_LBN 12 9228 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4 9229 /* enum: reserved value - do not use (may indicate alternative interpretation 9230 * of REV field in future) 9231 */ 9232 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_RESERVED 0x0 9233 /* enum: Trivial TX PD firmware for early Huntington development (Huntington 9234 * development only) 9235 */ 9236 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1 9237 /* enum: TX PD firmware with approximately Siena-compatible behaviour 9238 * (Huntington development only) 9239 */ 9240 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2 9241 /* enum: Full featured TX PD production firmware */ 9242 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3 9243 /* enum: (deprecated original name for the FULL_FEATURED variant) */ 9244 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_VSWITCH 0x3 9245 /* enum: siena_compat variant TX PD firmware using PM rather than MAC 9246 * (Huntington development only) 9247 */ 9248 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 9249 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */ 9250 /* enum: TX PD firmware handling layer 2 only for high packet rate performance 9251 * tests (Medford development only) 9252 */ 9253 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7 9254 /* enum: Rules engine TX PD production firmware */ 9255 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8 9256 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 9257 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 9258 /* Hardware capabilities of NIC */ 9259 #define MC_CMD_GET_CAPABILITIES_OUT_HW_CAPABILITIES_OFST 12 9260 #define MC_CMD_GET_CAPABILITIES_OUT_HW_CAPABILITIES_LEN 4 9261 /* Licensed capabilities */ 9262 #define MC_CMD_GET_CAPABILITIES_OUT_LICENSE_CAPABILITIES_OFST 16 9263 #define MC_CMD_GET_CAPABILITIES_OUT_LICENSE_CAPABILITIES_LEN 4 9264 9265 /* MC_CMD_GET_CAPABILITIES_V2_IN msgrequest */ 9266 #define MC_CMD_GET_CAPABILITIES_V2_IN_LEN 0 9267 9268 /* MC_CMD_GET_CAPABILITIES_V2_OUT msgresponse */ 9269 #define MC_CMD_GET_CAPABILITIES_V2_OUT_LEN 72 9270 /* First word of flags. */ 9271 #define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS1_OFST 0 9272 #define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS1_LEN 4 9273 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VPORT_RECONFIGURE_LBN 3 9274 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VPORT_RECONFIGURE_WIDTH 1 9275 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_STRIPING_LBN 4 9276 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_STRIPING_WIDTH 1 9277 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_QUERY_LBN 5 9278 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_QUERY_WIDTH 1 9279 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6 9280 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1 9281 #define MC_CMD_GET_CAPABILITIES_V2_OUT_DRV_ATTACH_PREBOOT_LBN 7 9282 #define MC_CMD_GET_CAPABILITIES_V2_OUT_DRV_ATTACH_PREBOOT_WIDTH 1 9283 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_FORCE_EVENT_MERGING_LBN 8 9284 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1 9285 #define MC_CMD_GET_CAPABILITIES_V2_OUT_SET_MAC_ENHANCED_LBN 9 9286 #define MC_CMD_GET_CAPABILITIES_V2_OUT_SET_MAC_ENHANCED_WIDTH 1 9287 #define MC_CMD_GET_CAPABILITIES_V2_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10 9288 #define MC_CMD_GET_CAPABILITIES_V2_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1 9289 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11 9290 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1 9291 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_SECURITY_FILTERING_LBN 12 9292 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1 9293 #define MC_CMD_GET_CAPABILITIES_V2_OUT_ADDITIONAL_RSS_MODES_LBN 13 9294 #define MC_CMD_GET_CAPABILITIES_V2_OUT_ADDITIONAL_RSS_MODES_WIDTH 1 9295 #define MC_CMD_GET_CAPABILITIES_V2_OUT_QBB_LBN 14 9296 #define MC_CMD_GET_CAPABILITIES_V2_OUT_QBB_WIDTH 1 9297 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15 9298 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1 9299 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_RSS_LIMITED_LBN 16 9300 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_RSS_LIMITED_WIDTH 1 9301 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_LBN 17 9302 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_WIDTH 1 9303 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_INCLUDE_FCS_LBN 18 9304 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_INCLUDE_FCS_WIDTH 1 9305 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VLAN_INSERTION_LBN 19 9306 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VLAN_INSERTION_WIDTH 1 9307 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_VLAN_STRIPPING_LBN 20 9308 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_VLAN_STRIPPING_WIDTH 1 9309 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_LBN 21 9310 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_WIDTH 1 9311 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_0_LBN 22 9312 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_0_WIDTH 1 9313 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_14_LBN 23 9314 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_14_WIDTH 1 9315 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_TIMESTAMP_LBN 24 9316 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_TIMESTAMP_WIDTH 1 9317 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_BATCHING_LBN 25 9318 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_BATCHING_WIDTH 1 9319 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MCAST_FILTER_CHAINING_LBN 26 9320 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MCAST_FILTER_CHAINING_WIDTH 1 9321 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PM_AND_RXDP_COUNTERS_LBN 27 9322 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1 9323 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DISABLE_SCATTER_LBN 28 9324 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DISABLE_SCATTER_WIDTH 1 9325 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29 9326 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1 9327 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_LBN 30 9328 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_WIDTH 1 9329 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VXLAN_NVGRE_LBN 31 9330 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VXLAN_NVGRE_WIDTH 1 9331 /* RxDPCPU firmware id. */ 9332 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DPCPU_FW_ID_OFST 4 9333 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DPCPU_FW_ID_LEN 2 9334 /* enum: Standard RXDP firmware */ 9335 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP 0x0 9336 /* enum: Low latency RXDP firmware */ 9337 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_LOW_LATENCY 0x1 9338 /* enum: Packed stream RXDP firmware */ 9339 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_PACKED_STREAM 0x2 9340 /* enum: Rules engine RXDP firmware */ 9341 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_RULES_ENGINE 0x5 9342 /* enum: BIST RXDP firmware */ 9343 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_BIST 0x10a 9344 /* enum: RXDP Test firmware image 1 */ 9345 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101 9346 /* enum: RXDP Test firmware image 2 */ 9347 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102 9348 /* enum: RXDP Test firmware image 3 */ 9349 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103 9350 /* enum: RXDP Test firmware image 4 */ 9351 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104 9352 /* enum: RXDP Test firmware image 5 */ 9353 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_BACKPRESSURE 0x105 9354 /* enum: RXDP Test firmware image 6 */ 9355 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106 9356 /* enum: RXDP Test firmware image 7 */ 9357 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107 9358 /* enum: RXDP Test firmware image 8 */ 9359 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_DISABLE_DL 0x108 9360 /* enum: RXDP Test firmware image 9 */ 9361 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b 9362 /* enum: RXDP Test firmware image 10 */ 9363 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_SLOW 0x10c 9364 /* TxDPCPU firmware id. */ 9365 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DPCPU_FW_ID_OFST 6 9366 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DPCPU_FW_ID_LEN 2 9367 /* enum: Standard TXDP firmware */ 9368 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP 0x0 9369 /* enum: Low latency TXDP firmware */ 9370 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_LOW_LATENCY 0x1 9371 /* enum: High packet rate TXDP firmware */ 9372 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_HIGH_PACKET_RATE 0x3 9373 /* enum: Rules engine TXDP firmware */ 9374 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_RULES_ENGINE 0x5 9375 /* enum: BIST TXDP firmware */ 9376 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_BIST 0x12d 9377 /* enum: TXDP Test firmware image 1 */ 9378 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_TSO_EDIT 0x101 9379 /* enum: TXDP Test firmware image 2 */ 9380 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102 9381 /* enum: TXDP CSR bus test firmware */ 9382 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_CSR 0x103 9383 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_OFST 8 9384 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_LEN 2 9385 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_REV_LBN 0 9386 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_REV_WIDTH 12 9387 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_TYPE_LBN 12 9388 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4 9389 /* enum: reserved value - do not use (may indicate alternative interpretation 9390 * of REV field in future) 9391 */ 9392 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_RESERVED 0x0 9393 /* enum: Trivial RX PD firmware for early Huntington development (Huntington 9394 * development only) 9395 */ 9396 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1 9397 /* enum: RX PD firmware with approximately Siena-compatible behaviour 9398 * (Huntington development only) 9399 */ 9400 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2 9401 /* enum: Full featured RX PD production firmware */ 9402 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3 9403 /* enum: (deprecated original name for the FULL_FEATURED variant) */ 9404 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_VSWITCH 0x3 9405 /* enum: siena_compat variant RX PD firmware using PM rather than MAC 9406 * (Huntington development only) 9407 */ 9408 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 9409 /* enum: Low latency RX PD production firmware */ 9410 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5 9411 /* enum: Packed stream RX PD production firmware */ 9412 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6 9413 /* enum: RX PD firmware handling layer 2 only for high packet rate performance 9414 * tests (Medford development only) 9415 */ 9416 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7 9417 /* enum: Rules engine RX PD production firmware */ 9418 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8 9419 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 9420 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 9421 /* enum: RX PD firmware parsing but not filtering network overlay tunnel 9422 * encapsulations (Medford development only) 9423 */ 9424 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf 9425 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_OFST 10 9426 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_LEN 2 9427 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_REV_LBN 0 9428 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_REV_WIDTH 12 9429 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_TYPE_LBN 12 9430 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4 9431 /* enum: reserved value - do not use (may indicate alternative interpretation 9432 * of REV field in future) 9433 */ 9434 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_RESERVED 0x0 9435 /* enum: Trivial TX PD firmware for early Huntington development (Huntington 9436 * development only) 9437 */ 9438 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1 9439 /* enum: TX PD firmware with approximately Siena-compatible behaviour 9440 * (Huntington development only) 9441 */ 9442 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2 9443 /* enum: Full featured TX PD production firmware */ 9444 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3 9445 /* enum: (deprecated original name for the FULL_FEATURED variant) */ 9446 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_VSWITCH 0x3 9447 /* enum: siena_compat variant TX PD firmware using PM rather than MAC 9448 * (Huntington development only) 9449 */ 9450 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 9451 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */ 9452 /* enum: TX PD firmware handling layer 2 only for high packet rate performance 9453 * tests (Medford development only) 9454 */ 9455 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7 9456 /* enum: Rules engine TX PD production firmware */ 9457 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8 9458 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 9459 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 9460 /* Hardware capabilities of NIC */ 9461 #define MC_CMD_GET_CAPABILITIES_V2_OUT_HW_CAPABILITIES_OFST 12 9462 #define MC_CMD_GET_CAPABILITIES_V2_OUT_HW_CAPABILITIES_LEN 4 9463 /* Licensed capabilities */ 9464 #define MC_CMD_GET_CAPABILITIES_V2_OUT_LICENSE_CAPABILITIES_OFST 16 9465 #define MC_CMD_GET_CAPABILITIES_V2_OUT_LICENSE_CAPABILITIES_LEN 4 9466 /* Second word of flags. Not present on older firmware (check the length). */ 9467 #define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS2_OFST 20 9468 #define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS2_LEN 4 9469 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN 0 9470 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_WIDTH 1 9471 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_ENCAP_LBN 1 9472 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_ENCAP_WIDTH 1 9473 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVQ_TIMER_CTRL_LBN 2 9474 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVQ_TIMER_CTRL_WIDTH 1 9475 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVENT_CUT_THROUGH_LBN 3 9476 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVENT_CUT_THROUGH_WIDTH 1 9477 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_CUT_THROUGH_LBN 4 9478 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_CUT_THROUGH_WIDTH 1 9479 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VFIFO_ULL_MODE_LBN 5 9480 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VFIFO_ULL_MODE_WIDTH 1 9481 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6 9482 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1 9483 #define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_LBN 7 9484 #define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_WIDTH 1 9485 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_TIMESTAMPING_LBN 8 9486 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_TIMESTAMPING_WIDTH 1 9487 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TIMESTAMP_LBN 9 9488 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TIMESTAMP_WIDTH 1 9489 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_SNIFF_LBN 10 9490 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_SNIFF_WIDTH 1 9491 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_SNIFF_LBN 11 9492 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_SNIFF_WIDTH 1 9493 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12 9494 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1 9495 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_BACKGROUND_LBN 13 9496 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_BACKGROUND_WIDTH 1 9497 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_DB_RETURN_LBN 14 9498 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_DB_RETURN_WIDTH 1 9499 /* Number of FATSOv2 contexts per datapath supported by this NIC. Not present 9500 * on older firmware (check the length). 9501 */ 9502 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24 9503 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2 9504 /* One byte per PF containing the number of the external port assigned to this 9505 * PF, indexed by PF number. Special values indicate that a PF is either not 9506 * present or not assigned. 9507 */ 9508 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26 9509 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1 9510 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16 9511 /* enum: The caller is not permitted to access information on this PF. */ 9512 #define MC_CMD_GET_CAPABILITIES_V2_OUT_ACCESS_NOT_PERMITTED 0xff 9513 /* enum: PF does not exist. */ 9514 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_PRESENT 0xfe 9515 /* enum: PF does exist but is not assigned to any external port. */ 9516 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_ASSIGNED 0xfd 9517 /* enum: This value indicates that PF is assigned, but it cannot be expressed 9518 * in this field. It is intended for a possible future situation where a more 9519 * complex scheme of PFs to ports mapping is being used. The future driver 9520 * should look for a new field supporting the new scheme. The current/old 9521 * driver should treat this value as PF_NOT_ASSIGNED. 9522 */ 9523 #define MC_CMD_GET_CAPABILITIES_V2_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc 9524 /* One byte per PF containing the number of its VFs, indexed by PF number. A 9525 * special value indicates that a PF is not present. 9526 */ 9527 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VFS_PER_PF_OFST 42 9528 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VFS_PER_PF_LEN 1 9529 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VFS_PER_PF_NUM 16 9530 /* enum: The caller is not permitted to access information on this PF. */ 9531 /* MC_CMD_GET_CAPABILITIES_V2_OUT_ACCESS_NOT_PERMITTED 0xff */ 9532 /* enum: PF does not exist. */ 9533 /* MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_PRESENT 0xfe */ 9534 /* Number of VIs available for each external port */ 9535 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_OFST 58 9536 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_LEN 2 9537 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_NUM 4 9538 /* Size of RX descriptor cache expressed as binary logarithm The actual size 9539 * equals (2 ^ RX_DESC_CACHE_SIZE) 9540 */ 9541 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DESC_CACHE_SIZE_OFST 66 9542 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DESC_CACHE_SIZE_LEN 1 9543 /* Size of TX descriptor cache expressed as binary logarithm The actual size 9544 * equals (2 ^ TX_DESC_CACHE_SIZE) 9545 */ 9546 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DESC_CACHE_SIZE_OFST 67 9547 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DESC_CACHE_SIZE_LEN 1 9548 /* Total number of available PIO buffers */ 9549 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_PIO_BUFFS_OFST 68 9550 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_PIO_BUFFS_LEN 2 9551 /* Size of a single PIO buffer */ 9552 #define MC_CMD_GET_CAPABILITIES_V2_OUT_SIZE_PIO_BUFF_OFST 70 9553 #define MC_CMD_GET_CAPABILITIES_V2_OUT_SIZE_PIO_BUFF_LEN 2 9554 9555 /* MC_CMD_GET_CAPABILITIES_V3_OUT msgresponse */ 9556 #define MC_CMD_GET_CAPABILITIES_V3_OUT_LEN 76 9557 /* First word of flags. */ 9558 #define MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS1_OFST 0 9559 #define MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS1_LEN 4 9560 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VPORT_RECONFIGURE_LBN 3 9561 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VPORT_RECONFIGURE_WIDTH 1 9562 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_STRIPING_LBN 4 9563 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_STRIPING_WIDTH 1 9564 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_QUERY_LBN 5 9565 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_QUERY_WIDTH 1 9566 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6 9567 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1 9568 #define MC_CMD_GET_CAPABILITIES_V3_OUT_DRV_ATTACH_PREBOOT_LBN 7 9569 #define MC_CMD_GET_CAPABILITIES_V3_OUT_DRV_ATTACH_PREBOOT_WIDTH 1 9570 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_FORCE_EVENT_MERGING_LBN 8 9571 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1 9572 #define MC_CMD_GET_CAPABILITIES_V3_OUT_SET_MAC_ENHANCED_LBN 9 9573 #define MC_CMD_GET_CAPABILITIES_V3_OUT_SET_MAC_ENHANCED_WIDTH 1 9574 #define MC_CMD_GET_CAPABILITIES_V3_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10 9575 #define MC_CMD_GET_CAPABILITIES_V3_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1 9576 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11 9577 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1 9578 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_SECURITY_FILTERING_LBN 12 9579 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1 9580 #define MC_CMD_GET_CAPABILITIES_V3_OUT_ADDITIONAL_RSS_MODES_LBN 13 9581 #define MC_CMD_GET_CAPABILITIES_V3_OUT_ADDITIONAL_RSS_MODES_WIDTH 1 9582 #define MC_CMD_GET_CAPABILITIES_V3_OUT_QBB_LBN 14 9583 #define MC_CMD_GET_CAPABILITIES_V3_OUT_QBB_WIDTH 1 9584 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15 9585 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1 9586 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_RSS_LIMITED_LBN 16 9587 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_RSS_LIMITED_WIDTH 1 9588 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_LBN 17 9589 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_WIDTH 1 9590 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_INCLUDE_FCS_LBN 18 9591 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_INCLUDE_FCS_WIDTH 1 9592 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VLAN_INSERTION_LBN 19 9593 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VLAN_INSERTION_WIDTH 1 9594 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_VLAN_STRIPPING_LBN 20 9595 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_VLAN_STRIPPING_WIDTH 1 9596 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_LBN 21 9597 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_WIDTH 1 9598 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_0_LBN 22 9599 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_0_WIDTH 1 9600 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_14_LBN 23 9601 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_14_WIDTH 1 9602 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_TIMESTAMP_LBN 24 9603 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_TIMESTAMP_WIDTH 1 9604 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_BATCHING_LBN 25 9605 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_BATCHING_WIDTH 1 9606 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MCAST_FILTER_CHAINING_LBN 26 9607 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MCAST_FILTER_CHAINING_WIDTH 1 9608 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PM_AND_RXDP_COUNTERS_LBN 27 9609 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1 9610 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DISABLE_SCATTER_LBN 28 9611 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DISABLE_SCATTER_WIDTH 1 9612 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29 9613 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1 9614 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_LBN 30 9615 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_WIDTH 1 9616 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VXLAN_NVGRE_LBN 31 9617 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VXLAN_NVGRE_WIDTH 1 9618 /* RxDPCPU firmware id. */ 9619 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DPCPU_FW_ID_OFST 4 9620 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DPCPU_FW_ID_LEN 2 9621 /* enum: Standard RXDP firmware */ 9622 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP 0x0 9623 /* enum: Low latency RXDP firmware */ 9624 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_LOW_LATENCY 0x1 9625 /* enum: Packed stream RXDP firmware */ 9626 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_PACKED_STREAM 0x2 9627 /* enum: Rules engine RXDP firmware */ 9628 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_RULES_ENGINE 0x5 9629 /* enum: BIST RXDP firmware */ 9630 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_BIST 0x10a 9631 /* enum: RXDP Test firmware image 1 */ 9632 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101 9633 /* enum: RXDP Test firmware image 2 */ 9634 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102 9635 /* enum: RXDP Test firmware image 3 */ 9636 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103 9637 /* enum: RXDP Test firmware image 4 */ 9638 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104 9639 /* enum: RXDP Test firmware image 5 */ 9640 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_BACKPRESSURE 0x105 9641 /* enum: RXDP Test firmware image 6 */ 9642 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106 9643 /* enum: RXDP Test firmware image 7 */ 9644 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107 9645 /* enum: RXDP Test firmware image 8 */ 9646 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_DISABLE_DL 0x108 9647 /* enum: RXDP Test firmware image 9 */ 9648 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b 9649 /* enum: RXDP Test firmware image 10 */ 9650 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_SLOW 0x10c 9651 /* TxDPCPU firmware id. */ 9652 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_DPCPU_FW_ID_OFST 6 9653 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_DPCPU_FW_ID_LEN 2 9654 /* enum: Standard TXDP firmware */ 9655 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP 0x0 9656 /* enum: Low latency TXDP firmware */ 9657 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_LOW_LATENCY 0x1 9658 /* enum: High packet rate TXDP firmware */ 9659 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_HIGH_PACKET_RATE 0x3 9660 /* enum: Rules engine TXDP firmware */ 9661 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_RULES_ENGINE 0x5 9662 /* enum: BIST TXDP firmware */ 9663 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_BIST 0x12d 9664 /* enum: TXDP Test firmware image 1 */ 9665 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_TSO_EDIT 0x101 9666 /* enum: TXDP Test firmware image 2 */ 9667 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102 9668 /* enum: TXDP CSR bus test firmware */ 9669 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_CSR 0x103 9670 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_OFST 8 9671 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_LEN 2 9672 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_REV_LBN 0 9673 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_REV_WIDTH 12 9674 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_TYPE_LBN 12 9675 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4 9676 /* enum: reserved value - do not use (may indicate alternative interpretation 9677 * of REV field in future) 9678 */ 9679 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_RESERVED 0x0 9680 /* enum: Trivial RX PD firmware for early Huntington development (Huntington 9681 * development only) 9682 */ 9683 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1 9684 /* enum: RX PD firmware with approximately Siena-compatible behaviour 9685 * (Huntington development only) 9686 */ 9687 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2 9688 /* enum: Full featured RX PD production firmware */ 9689 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3 9690 /* enum: (deprecated original name for the FULL_FEATURED variant) */ 9691 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_VSWITCH 0x3 9692 /* enum: siena_compat variant RX PD firmware using PM rather than MAC 9693 * (Huntington development only) 9694 */ 9695 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 9696 /* enum: Low latency RX PD production firmware */ 9697 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5 9698 /* enum: Packed stream RX PD production firmware */ 9699 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6 9700 /* enum: RX PD firmware handling layer 2 only for high packet rate performance 9701 * tests (Medford development only) 9702 */ 9703 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7 9704 /* enum: Rules engine RX PD production firmware */ 9705 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8 9706 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 9707 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 9708 /* enum: RX PD firmware parsing but not filtering network overlay tunnel 9709 * encapsulations (Medford development only) 9710 */ 9711 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf 9712 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_OFST 10 9713 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_LEN 2 9714 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_REV_LBN 0 9715 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_REV_WIDTH 12 9716 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_TYPE_LBN 12 9717 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4 9718 /* enum: reserved value - do not use (may indicate alternative interpretation 9719 * of REV field in future) 9720 */ 9721 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_RESERVED 0x0 9722 /* enum: Trivial TX PD firmware for early Huntington development (Huntington 9723 * development only) 9724 */ 9725 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1 9726 /* enum: TX PD firmware with approximately Siena-compatible behaviour 9727 * (Huntington development only) 9728 */ 9729 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2 9730 /* enum: Full featured TX PD production firmware */ 9731 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3 9732 /* enum: (deprecated original name for the FULL_FEATURED variant) */ 9733 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_VSWITCH 0x3 9734 /* enum: siena_compat variant TX PD firmware using PM rather than MAC 9735 * (Huntington development only) 9736 */ 9737 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 9738 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */ 9739 /* enum: TX PD firmware handling layer 2 only for high packet rate performance 9740 * tests (Medford development only) 9741 */ 9742 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7 9743 /* enum: Rules engine TX PD production firmware */ 9744 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8 9745 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 9746 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 9747 /* Hardware capabilities of NIC */ 9748 #define MC_CMD_GET_CAPABILITIES_V3_OUT_HW_CAPABILITIES_OFST 12 9749 #define MC_CMD_GET_CAPABILITIES_V3_OUT_HW_CAPABILITIES_LEN 4 9750 /* Licensed capabilities */ 9751 #define MC_CMD_GET_CAPABILITIES_V3_OUT_LICENSE_CAPABILITIES_OFST 16 9752 #define MC_CMD_GET_CAPABILITIES_V3_OUT_LICENSE_CAPABILITIES_LEN 4 9753 /* Second word of flags. Not present on older firmware (check the length). */ 9754 #define MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS2_OFST 20 9755 #define MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS2_LEN 4 9756 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_LBN 0 9757 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_WIDTH 1 9758 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_ENCAP_LBN 1 9759 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_ENCAP_WIDTH 1 9760 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVQ_TIMER_CTRL_LBN 2 9761 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVQ_TIMER_CTRL_WIDTH 1 9762 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVENT_CUT_THROUGH_LBN 3 9763 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVENT_CUT_THROUGH_WIDTH 1 9764 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_CUT_THROUGH_LBN 4 9765 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_CUT_THROUGH_WIDTH 1 9766 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VFIFO_ULL_MODE_LBN 5 9767 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VFIFO_ULL_MODE_WIDTH 1 9768 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6 9769 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1 9770 #define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_V2_LBN 7 9771 #define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_V2_WIDTH 1 9772 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_TIMESTAMPING_LBN 8 9773 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_TIMESTAMPING_WIDTH 1 9774 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TIMESTAMP_LBN 9 9775 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TIMESTAMP_WIDTH 1 9776 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_SNIFF_LBN 10 9777 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_SNIFF_WIDTH 1 9778 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_SNIFF_LBN 11 9779 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_SNIFF_WIDTH 1 9780 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12 9781 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1 9782 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_BACKGROUND_LBN 13 9783 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_BACKGROUND_WIDTH 1 9784 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_DB_RETURN_LBN 14 9785 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_DB_RETURN_WIDTH 1 9786 /* Number of FATSOv2 contexts per datapath supported by this NIC. Not present 9787 * on older firmware (check the length). 9788 */ 9789 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24 9790 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2 9791 /* One byte per PF containing the number of the external port assigned to this 9792 * PF, indexed by PF number. Special values indicate that a PF is either not 9793 * present or not assigned. 9794 */ 9795 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26 9796 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1 9797 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16 9798 /* enum: The caller is not permitted to access information on this PF. */ 9799 #define MC_CMD_GET_CAPABILITIES_V3_OUT_ACCESS_NOT_PERMITTED 0xff 9800 /* enum: PF does not exist. */ 9801 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_PRESENT 0xfe 9802 /* enum: PF does exist but is not assigned to any external port. */ 9803 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_ASSIGNED 0xfd 9804 /* enum: This value indicates that PF is assigned, but it cannot be expressed 9805 * in this field. It is intended for a possible future situation where a more 9806 * complex scheme of PFs to ports mapping is being used. The future driver 9807 * should look for a new field supporting the new scheme. The current/old 9808 * driver should treat this value as PF_NOT_ASSIGNED. 9809 */ 9810 #define MC_CMD_GET_CAPABILITIES_V3_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc 9811 /* One byte per PF containing the number of its VFs, indexed by PF number. A 9812 * special value indicates that a PF is not present. 9813 */ 9814 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VFS_PER_PF_OFST 42 9815 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VFS_PER_PF_LEN 1 9816 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VFS_PER_PF_NUM 16 9817 /* enum: The caller is not permitted to access information on this PF. */ 9818 /* MC_CMD_GET_CAPABILITIES_V3_OUT_ACCESS_NOT_PERMITTED 0xff */ 9819 /* enum: PF does not exist. */ 9820 /* MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_PRESENT 0xfe */ 9821 /* Number of VIs available for each external port */ 9822 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VIS_PER_PORT_OFST 58 9823 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VIS_PER_PORT_LEN 2 9824 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VIS_PER_PORT_NUM 4 9825 /* Size of RX descriptor cache expressed as binary logarithm The actual size 9826 * equals (2 ^ RX_DESC_CACHE_SIZE) 9827 */ 9828 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DESC_CACHE_SIZE_OFST 66 9829 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DESC_CACHE_SIZE_LEN 1 9830 /* Size of TX descriptor cache expressed as binary logarithm The actual size 9831 * equals (2 ^ TX_DESC_CACHE_SIZE) 9832 */ 9833 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_DESC_CACHE_SIZE_OFST 67 9834 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_DESC_CACHE_SIZE_LEN 1 9835 /* Total number of available PIO buffers */ 9836 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_PIO_BUFFS_OFST 68 9837 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_PIO_BUFFS_LEN 2 9838 /* Size of a single PIO buffer */ 9839 #define MC_CMD_GET_CAPABILITIES_V3_OUT_SIZE_PIO_BUFF_OFST 70 9840 #define MC_CMD_GET_CAPABILITIES_V3_OUT_SIZE_PIO_BUFF_LEN 2 9841 /* On chips later than Medford the amount of address space assigned to each VI 9842 * is configurable. This is a global setting that the driver must query to 9843 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available 9844 * with 8k VI windows. 9845 */ 9846 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_OFST 72 9847 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_LEN 1 9848 /* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k. 9849 * CTPIO is not mapped. 9850 */ 9851 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_8K 0x0 9852 /* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */ 9853 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_16K 0x1 9854 /* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */ 9855 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_64K 0x2 9856 /* Number of vFIFOs per adapter that can be used for VFIFO Stuffing 9857 * (SF-115995-SW) in the present configuration of firmware and port mode. 9858 */ 9859 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 73 9860 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1 9861 /* Number of buffers per adapter that can be used for VFIFO Stuffing 9862 * (SF-115995-SW) in the present configuration of firmware and port mode. 9863 */ 9864 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 74 9865 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 2 9866 9867 /* MC_CMD_GET_CAPABILITIES_V4_OUT msgresponse */ 9868 #define MC_CMD_GET_CAPABILITIES_V4_OUT_LEN 78 9869 /* First word of flags. */ 9870 #define MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS1_OFST 0 9871 #define MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS1_LEN 4 9872 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VPORT_RECONFIGURE_LBN 3 9873 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VPORT_RECONFIGURE_WIDTH 1 9874 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_STRIPING_LBN 4 9875 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_STRIPING_WIDTH 1 9876 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_QUERY_LBN 5 9877 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_QUERY_WIDTH 1 9878 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6 9879 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1 9880 #define MC_CMD_GET_CAPABILITIES_V4_OUT_DRV_ATTACH_PREBOOT_LBN 7 9881 #define MC_CMD_GET_CAPABILITIES_V4_OUT_DRV_ATTACH_PREBOOT_WIDTH 1 9882 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_FORCE_EVENT_MERGING_LBN 8 9883 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1 9884 #define MC_CMD_GET_CAPABILITIES_V4_OUT_SET_MAC_ENHANCED_LBN 9 9885 #define MC_CMD_GET_CAPABILITIES_V4_OUT_SET_MAC_ENHANCED_WIDTH 1 9886 #define MC_CMD_GET_CAPABILITIES_V4_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10 9887 #define MC_CMD_GET_CAPABILITIES_V4_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1 9888 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11 9889 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1 9890 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_SECURITY_FILTERING_LBN 12 9891 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1 9892 #define MC_CMD_GET_CAPABILITIES_V4_OUT_ADDITIONAL_RSS_MODES_LBN 13 9893 #define MC_CMD_GET_CAPABILITIES_V4_OUT_ADDITIONAL_RSS_MODES_WIDTH 1 9894 #define MC_CMD_GET_CAPABILITIES_V4_OUT_QBB_LBN 14 9895 #define MC_CMD_GET_CAPABILITIES_V4_OUT_QBB_WIDTH 1 9896 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15 9897 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1 9898 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_RSS_LIMITED_LBN 16 9899 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_RSS_LIMITED_WIDTH 1 9900 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_LBN 17 9901 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_WIDTH 1 9902 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_INCLUDE_FCS_LBN 18 9903 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_INCLUDE_FCS_WIDTH 1 9904 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VLAN_INSERTION_LBN 19 9905 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VLAN_INSERTION_WIDTH 1 9906 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_VLAN_STRIPPING_LBN 20 9907 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_VLAN_STRIPPING_WIDTH 1 9908 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_LBN 21 9909 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_WIDTH 1 9910 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_0_LBN 22 9911 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_0_WIDTH 1 9912 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_14_LBN 23 9913 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_14_WIDTH 1 9914 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_TIMESTAMP_LBN 24 9915 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_TIMESTAMP_WIDTH 1 9916 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_BATCHING_LBN 25 9917 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_BATCHING_WIDTH 1 9918 #define MC_CMD_GET_CAPABILITIES_V4_OUT_MCAST_FILTER_CHAINING_LBN 26 9919 #define MC_CMD_GET_CAPABILITIES_V4_OUT_MCAST_FILTER_CHAINING_WIDTH 1 9920 #define MC_CMD_GET_CAPABILITIES_V4_OUT_PM_AND_RXDP_COUNTERS_LBN 27 9921 #define MC_CMD_GET_CAPABILITIES_V4_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1 9922 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DISABLE_SCATTER_LBN 28 9923 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DISABLE_SCATTER_WIDTH 1 9924 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29 9925 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1 9926 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_LBN 30 9927 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_WIDTH 1 9928 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VXLAN_NVGRE_LBN 31 9929 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VXLAN_NVGRE_WIDTH 1 9930 /* RxDPCPU firmware id. */ 9931 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DPCPU_FW_ID_OFST 4 9932 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DPCPU_FW_ID_LEN 2 9933 /* enum: Standard RXDP firmware */ 9934 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP 0x0 9935 /* enum: Low latency RXDP firmware */ 9936 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_LOW_LATENCY 0x1 9937 /* enum: Packed stream RXDP firmware */ 9938 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_PACKED_STREAM 0x2 9939 /* enum: Rules engine RXDP firmware */ 9940 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_RULES_ENGINE 0x5 9941 /* enum: BIST RXDP firmware */ 9942 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_BIST 0x10a 9943 /* enum: RXDP Test firmware image 1 */ 9944 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101 9945 /* enum: RXDP Test firmware image 2 */ 9946 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102 9947 /* enum: RXDP Test firmware image 3 */ 9948 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103 9949 /* enum: RXDP Test firmware image 4 */ 9950 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104 9951 /* enum: RXDP Test firmware image 5 */ 9952 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_BACKPRESSURE 0x105 9953 /* enum: RXDP Test firmware image 6 */ 9954 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106 9955 /* enum: RXDP Test firmware image 7 */ 9956 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107 9957 /* enum: RXDP Test firmware image 8 */ 9958 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_DISABLE_DL 0x108 9959 /* enum: RXDP Test firmware image 9 */ 9960 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b 9961 /* enum: RXDP Test firmware image 10 */ 9962 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_SLOW 0x10c 9963 /* TxDPCPU firmware id. */ 9964 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_DPCPU_FW_ID_OFST 6 9965 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_DPCPU_FW_ID_LEN 2 9966 /* enum: Standard TXDP firmware */ 9967 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP 0x0 9968 /* enum: Low latency TXDP firmware */ 9969 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_LOW_LATENCY 0x1 9970 /* enum: High packet rate TXDP firmware */ 9971 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_HIGH_PACKET_RATE 0x3 9972 /* enum: Rules engine TXDP firmware */ 9973 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_RULES_ENGINE 0x5 9974 /* enum: BIST TXDP firmware */ 9975 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_BIST 0x12d 9976 /* enum: TXDP Test firmware image 1 */ 9977 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_TEST_FW_TSO_EDIT 0x101 9978 /* enum: TXDP Test firmware image 2 */ 9979 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102 9980 /* enum: TXDP CSR bus test firmware */ 9981 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_TEST_FW_CSR 0x103 9982 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_OFST 8 9983 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_LEN 2 9984 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_REV_LBN 0 9985 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_REV_WIDTH 12 9986 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_TYPE_LBN 12 9987 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4 9988 /* enum: reserved value - do not use (may indicate alternative interpretation 9989 * of REV field in future) 9990 */ 9991 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_RESERVED 0x0 9992 /* enum: Trivial RX PD firmware for early Huntington development (Huntington 9993 * development only) 9994 */ 9995 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1 9996 /* enum: RX PD firmware with approximately Siena-compatible behaviour 9997 * (Huntington development only) 9998 */ 9999 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2 10000 /* enum: Full featured RX PD production firmware */ 10001 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3 10002 /* enum: (deprecated original name for the FULL_FEATURED variant) */ 10003 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_VSWITCH 0x3 10004 /* enum: siena_compat variant RX PD firmware using PM rather than MAC 10005 * (Huntington development only) 10006 */ 10007 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 10008 /* enum: Low latency RX PD production firmware */ 10009 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5 10010 /* enum: Packed stream RX PD production firmware */ 10011 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6 10012 /* enum: RX PD firmware handling layer 2 only for high packet rate performance 10013 * tests (Medford development only) 10014 */ 10015 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7 10016 /* enum: Rules engine RX PD production firmware */ 10017 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8 10018 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 10019 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 10020 /* enum: RX PD firmware parsing but not filtering network overlay tunnel 10021 * encapsulations (Medford development only) 10022 */ 10023 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf 10024 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_OFST 10 10025 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_LEN 2 10026 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_REV_LBN 0 10027 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_REV_WIDTH 12 10028 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_TYPE_LBN 12 10029 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4 10030 /* enum: reserved value - do not use (may indicate alternative interpretation 10031 * of REV field in future) 10032 */ 10033 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_RESERVED 0x0 10034 /* enum: Trivial TX PD firmware for early Huntington development (Huntington 10035 * development only) 10036 */ 10037 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1 10038 /* enum: TX PD firmware with approximately Siena-compatible behaviour 10039 * (Huntington development only) 10040 */ 10041 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2 10042 /* enum: Full featured TX PD production firmware */ 10043 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3 10044 /* enum: (deprecated original name for the FULL_FEATURED variant) */ 10045 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_VSWITCH 0x3 10046 /* enum: siena_compat variant TX PD firmware using PM rather than MAC 10047 * (Huntington development only) 10048 */ 10049 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 10050 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */ 10051 /* enum: TX PD firmware handling layer 2 only for high packet rate performance 10052 * tests (Medford development only) 10053 */ 10054 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7 10055 /* enum: Rules engine TX PD production firmware */ 10056 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8 10057 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 10058 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 10059 /* Hardware capabilities of NIC */ 10060 #define MC_CMD_GET_CAPABILITIES_V4_OUT_HW_CAPABILITIES_OFST 12 10061 #define MC_CMD_GET_CAPABILITIES_V4_OUT_HW_CAPABILITIES_LEN 4 10062 /* Licensed capabilities */ 10063 #define MC_CMD_GET_CAPABILITIES_V4_OUT_LICENSE_CAPABILITIES_OFST 16 10064 #define MC_CMD_GET_CAPABILITIES_V4_OUT_LICENSE_CAPABILITIES_LEN 4 10065 /* Second word of flags. Not present on older firmware (check the length). */ 10066 #define MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS2_OFST 20 10067 #define MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS2_LEN 4 10068 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_LBN 0 10069 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_WIDTH 1 10070 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_ENCAP_LBN 1 10071 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_ENCAP_WIDTH 1 10072 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EVQ_TIMER_CTRL_LBN 2 10073 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EVQ_TIMER_CTRL_WIDTH 1 10074 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EVENT_CUT_THROUGH_LBN 3 10075 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EVENT_CUT_THROUGH_WIDTH 1 10076 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_CUT_THROUGH_LBN 4 10077 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_CUT_THROUGH_WIDTH 1 10078 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VFIFO_ULL_MODE_LBN 5 10079 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VFIFO_ULL_MODE_WIDTH 1 10080 #define MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6 10081 #define MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1 10082 #define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_EVQ_V2_LBN 7 10083 #define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_EVQ_V2_WIDTH 1 10084 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_TIMESTAMPING_LBN 8 10085 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_TIMESTAMPING_WIDTH 1 10086 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TIMESTAMP_LBN 9 10087 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TIMESTAMP_WIDTH 1 10088 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_SNIFF_LBN 10 10089 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_SNIFF_WIDTH 1 10090 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_SNIFF_LBN 11 10091 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_SNIFF_WIDTH 1 10092 #define MC_CMD_GET_CAPABILITIES_V4_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12 10093 #define MC_CMD_GET_CAPABILITIES_V4_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1 10094 #define MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_BACKGROUND_LBN 13 10095 #define MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_BACKGROUND_WIDTH 1 10096 #define MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_DB_RETURN_LBN 14 10097 #define MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_DB_RETURN_WIDTH 1 10098 /* Number of FATSOv2 contexts per datapath supported by this NIC. Not present 10099 * on older firmware (check the length). 10100 */ 10101 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24 10102 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2 10103 /* One byte per PF containing the number of the external port assigned to this 10104 * PF, indexed by PF number. Special values indicate that a PF is either not 10105 * present or not assigned. 10106 */ 10107 #define MC_CMD_GET_CAPABILITIES_V4_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26 10108 #define MC_CMD_GET_CAPABILITIES_V4_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1 10109 #define MC_CMD_GET_CAPABILITIES_V4_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16 10110 /* enum: The caller is not permitted to access information on this PF. */ 10111 #define MC_CMD_GET_CAPABILITIES_V4_OUT_ACCESS_NOT_PERMITTED 0xff 10112 /* enum: PF does not exist. */ 10113 #define MC_CMD_GET_CAPABILITIES_V4_OUT_PF_NOT_PRESENT 0xfe 10114 /* enum: PF does exist but is not assigned to any external port. */ 10115 #define MC_CMD_GET_CAPABILITIES_V4_OUT_PF_NOT_ASSIGNED 0xfd 10116 /* enum: This value indicates that PF is assigned, but it cannot be expressed 10117 * in this field. It is intended for a possible future situation where a more 10118 * complex scheme of PFs to ports mapping is being used. The future driver 10119 * should look for a new field supporting the new scheme. The current/old 10120 * driver should treat this value as PF_NOT_ASSIGNED. 10121 */ 10122 #define MC_CMD_GET_CAPABILITIES_V4_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc 10123 /* One byte per PF containing the number of its VFs, indexed by PF number. A 10124 * special value indicates that a PF is not present. 10125 */ 10126 #define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VFS_PER_PF_OFST 42 10127 #define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VFS_PER_PF_LEN 1 10128 #define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VFS_PER_PF_NUM 16 10129 /* enum: The caller is not permitted to access information on this PF. */ 10130 /* MC_CMD_GET_CAPABILITIES_V4_OUT_ACCESS_NOT_PERMITTED 0xff */ 10131 /* enum: PF does not exist. */ 10132 /* MC_CMD_GET_CAPABILITIES_V4_OUT_PF_NOT_PRESENT 0xfe */ 10133 /* Number of VIs available for each external port */ 10134 #define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VIS_PER_PORT_OFST 58 10135 #define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VIS_PER_PORT_LEN 2 10136 #define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VIS_PER_PORT_NUM 4 10137 /* Size of RX descriptor cache expressed as binary logarithm The actual size 10138 * equals (2 ^ RX_DESC_CACHE_SIZE) 10139 */ 10140 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DESC_CACHE_SIZE_OFST 66 10141 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DESC_CACHE_SIZE_LEN 1 10142 /* Size of TX descriptor cache expressed as binary logarithm The actual size 10143 * equals (2 ^ TX_DESC_CACHE_SIZE) 10144 */ 10145 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_DESC_CACHE_SIZE_OFST 67 10146 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_DESC_CACHE_SIZE_LEN 1 10147 /* Total number of available PIO buffers */ 10148 #define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_PIO_BUFFS_OFST 68 10149 #define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_PIO_BUFFS_LEN 2 10150 /* Size of a single PIO buffer */ 10151 #define MC_CMD_GET_CAPABILITIES_V4_OUT_SIZE_PIO_BUFF_OFST 70 10152 #define MC_CMD_GET_CAPABILITIES_V4_OUT_SIZE_PIO_BUFF_LEN 2 10153 /* On chips later than Medford the amount of address space assigned to each VI 10154 * is configurable. This is a global setting that the driver must query to 10155 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available 10156 * with 8k VI windows. 10157 */ 10158 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_OFST 72 10159 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_LEN 1 10160 /* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k. 10161 * CTPIO is not mapped. 10162 */ 10163 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_8K 0x0 10164 /* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */ 10165 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_16K 0x1 10166 /* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */ 10167 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_64K 0x2 10168 /* Number of vFIFOs per adapter that can be used for VFIFO Stuffing 10169 * (SF-115995-SW) in the present configuration of firmware and port mode. 10170 */ 10171 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 73 10172 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1 10173 /* Number of buffers per adapter that can be used for VFIFO Stuffing 10174 * (SF-115995-SW) in the present configuration of firmware and port mode. 10175 */ 10176 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 74 10177 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 2 10178 /* Entry count in the MAC stats array, including the final GENERATION_END 10179 * entry. For MAC stats DMA, drivers should allocate a buffer large enough to 10180 * hold at least this many 64-bit stats values, if they wish to receive all 10181 * available stats. If the buffer is shorter than MAC_STATS_NUM_STATS * 8, the 10182 * stats array returned will be truncated. 10183 */ 10184 #define MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS_OFST 76 10185 #define MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS_LEN 2 10186 10187 10188 /***********************************/ 10189 /* MC_CMD_V2_EXTN 10190 * Encapsulation for a v2 extended command 10191 */ 10192 #define MC_CMD_V2_EXTN 0x7f 10193 10194 /* MC_CMD_V2_EXTN_IN msgrequest */ 10195 #define MC_CMD_V2_EXTN_IN_LEN 4 10196 /* the extended command number */ 10197 #define MC_CMD_V2_EXTN_IN_EXTENDED_CMD_LBN 0 10198 #define MC_CMD_V2_EXTN_IN_EXTENDED_CMD_WIDTH 15 10199 #define MC_CMD_V2_EXTN_IN_UNUSED_LBN 15 10200 #define MC_CMD_V2_EXTN_IN_UNUSED_WIDTH 1 10201 /* the actual length of the encapsulated command (which is not in the v1 10202 * header) 10203 */ 10204 #define MC_CMD_V2_EXTN_IN_ACTUAL_LEN_LBN 16 10205 #define MC_CMD_V2_EXTN_IN_ACTUAL_LEN_WIDTH 10 10206 #define MC_CMD_V2_EXTN_IN_UNUSED2_LBN 26 10207 #define MC_CMD_V2_EXTN_IN_UNUSED2_WIDTH 2 10208 /* Type of command/response */ 10209 #define MC_CMD_V2_EXTN_IN_MESSAGE_TYPE_LBN 28 10210 #define MC_CMD_V2_EXTN_IN_MESSAGE_TYPE_WIDTH 4 10211 /* enum: MCDI command directed to or response originating from the MC. */ 10212 #define MC_CMD_V2_EXTN_IN_MCDI_MESSAGE_TYPE_MC 0x0 10213 /* enum: MCDI command directed to a TSA controller. MCDI responses of this type 10214 * are not defined. 10215 */ 10216 #define MC_CMD_V2_EXTN_IN_MCDI_MESSAGE_TYPE_TSA 0x1 10217 10218 10219 /***********************************/ 10220 /* MC_CMD_TCM_BUCKET_ALLOC 10221 * Allocate a pacer bucket (for qau rp or a snapper test) 10222 */ 10223 #define MC_CMD_TCM_BUCKET_ALLOC 0xb2 10224 #undef MC_CMD_0xb2_PRIVILEGE_CTG 10225 10226 #define MC_CMD_0xb2_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10227 10228 /* MC_CMD_TCM_BUCKET_ALLOC_IN msgrequest */ 10229 #define MC_CMD_TCM_BUCKET_ALLOC_IN_LEN 0 10230 10231 /* MC_CMD_TCM_BUCKET_ALLOC_OUT msgresponse */ 10232 #define MC_CMD_TCM_BUCKET_ALLOC_OUT_LEN 4 10233 /* the bucket id */ 10234 #define MC_CMD_TCM_BUCKET_ALLOC_OUT_BUCKET_OFST 0 10235 #define MC_CMD_TCM_BUCKET_ALLOC_OUT_BUCKET_LEN 4 10236 10237 10238 /***********************************/ 10239 /* MC_CMD_TCM_BUCKET_FREE 10240 * Free a pacer bucket 10241 */ 10242 #define MC_CMD_TCM_BUCKET_FREE 0xb3 10243 #undef MC_CMD_0xb3_PRIVILEGE_CTG 10244 10245 #define MC_CMD_0xb3_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10246 10247 /* MC_CMD_TCM_BUCKET_FREE_IN msgrequest */ 10248 #define MC_CMD_TCM_BUCKET_FREE_IN_LEN 4 10249 /* the bucket id */ 10250 #define MC_CMD_TCM_BUCKET_FREE_IN_BUCKET_OFST 0 10251 #define MC_CMD_TCM_BUCKET_FREE_IN_BUCKET_LEN 4 10252 10253 /* MC_CMD_TCM_BUCKET_FREE_OUT msgresponse */ 10254 #define MC_CMD_TCM_BUCKET_FREE_OUT_LEN 0 10255 10256 10257 /***********************************/ 10258 /* MC_CMD_TCM_BUCKET_INIT 10259 * Initialise pacer bucket with a given rate 10260 */ 10261 #define MC_CMD_TCM_BUCKET_INIT 0xb4 10262 #undef MC_CMD_0xb4_PRIVILEGE_CTG 10263 10264 #define MC_CMD_0xb4_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10265 10266 /* MC_CMD_TCM_BUCKET_INIT_IN msgrequest */ 10267 #define MC_CMD_TCM_BUCKET_INIT_IN_LEN 8 10268 /* the bucket id */ 10269 #define MC_CMD_TCM_BUCKET_INIT_IN_BUCKET_OFST 0 10270 #define MC_CMD_TCM_BUCKET_INIT_IN_BUCKET_LEN 4 10271 /* the rate in mbps */ 10272 #define MC_CMD_TCM_BUCKET_INIT_IN_RATE_OFST 4 10273 #define MC_CMD_TCM_BUCKET_INIT_IN_RATE_LEN 4 10274 10275 /* MC_CMD_TCM_BUCKET_INIT_EXT_IN msgrequest */ 10276 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_LEN 12 10277 /* the bucket id */ 10278 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_BUCKET_OFST 0 10279 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_BUCKET_LEN 4 10280 /* the rate in mbps */ 10281 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_RATE_OFST 4 10282 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_RATE_LEN 4 10283 /* the desired maximum fill level */ 10284 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_MAX_FILL_OFST 8 10285 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_MAX_FILL_LEN 4 10286 10287 /* MC_CMD_TCM_BUCKET_INIT_OUT msgresponse */ 10288 #define MC_CMD_TCM_BUCKET_INIT_OUT_LEN 0 10289 10290 10291 /***********************************/ 10292 /* MC_CMD_TCM_TXQ_INIT 10293 * Initialise txq in pacer with given options or set options 10294 */ 10295 #define MC_CMD_TCM_TXQ_INIT 0xb5 10296 #undef MC_CMD_0xb5_PRIVILEGE_CTG 10297 10298 #define MC_CMD_0xb5_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10299 10300 /* MC_CMD_TCM_TXQ_INIT_IN msgrequest */ 10301 #define MC_CMD_TCM_TXQ_INIT_IN_LEN 28 10302 /* the txq id */ 10303 #define MC_CMD_TCM_TXQ_INIT_IN_QID_OFST 0 10304 #define MC_CMD_TCM_TXQ_INIT_IN_QID_LEN 4 10305 /* the static priority associated with the txq */ 10306 #define MC_CMD_TCM_TXQ_INIT_IN_LABEL_OFST 4 10307 #define MC_CMD_TCM_TXQ_INIT_IN_LABEL_LEN 4 10308 /* bitmask of the priority queues this txq is inserted into when inserted. */ 10309 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAGS_OFST 8 10310 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAGS_LEN 4 10311 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_GUARANTEED_LBN 0 10312 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_GUARANTEED_WIDTH 1 10313 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_NORMAL_LBN 1 10314 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_NORMAL_WIDTH 1 10315 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_LOW_LBN 2 10316 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_LOW_WIDTH 1 10317 /* the reaction point (RP) bucket */ 10318 #define MC_CMD_TCM_TXQ_INIT_IN_RP_BKT_OFST 12 10319 #define MC_CMD_TCM_TXQ_INIT_IN_RP_BKT_LEN 4 10320 /* an already reserved bucket (typically set to bucket associated with outer 10321 * vswitch) 10322 */ 10323 #define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT1_OFST 16 10324 #define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT1_LEN 4 10325 /* an already reserved bucket (typically set to bucket associated with inner 10326 * vswitch) 10327 */ 10328 #define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT2_OFST 20 10329 #define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT2_LEN 4 10330 /* the min bucket (typically for ETS/minimum bandwidth) */ 10331 #define MC_CMD_TCM_TXQ_INIT_IN_MIN_BKT_OFST 24 10332 #define MC_CMD_TCM_TXQ_INIT_IN_MIN_BKT_LEN 4 10333 10334 /* MC_CMD_TCM_TXQ_INIT_EXT_IN msgrequest */ 10335 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_LEN 32 10336 /* the txq id */ 10337 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_QID_OFST 0 10338 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_QID_LEN 4 10339 /* the static priority associated with the txq */ 10340 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_NORMAL_OFST 4 10341 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_NORMAL_LEN 4 10342 /* bitmask of the priority queues this txq is inserted into when inserted. */ 10343 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAGS_OFST 8 10344 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAGS_LEN 4 10345 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_GUARANTEED_LBN 0 10346 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_GUARANTEED_WIDTH 1 10347 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_NORMAL_LBN 1 10348 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_NORMAL_WIDTH 1 10349 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_LOW_LBN 2 10350 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_LOW_WIDTH 1 10351 /* the reaction point (RP) bucket */ 10352 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_RP_BKT_OFST 12 10353 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_RP_BKT_LEN 4 10354 /* an already reserved bucket (typically set to bucket associated with outer 10355 * vswitch) 10356 */ 10357 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT1_OFST 16 10358 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT1_LEN 4 10359 /* an already reserved bucket (typically set to bucket associated with inner 10360 * vswitch) 10361 */ 10362 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT2_OFST 20 10363 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT2_LEN 4 10364 /* the min bucket (typically for ETS/minimum bandwidth) */ 10365 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MIN_BKT_OFST 24 10366 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MIN_BKT_LEN 4 10367 /* the static priority associated with the txq */ 10368 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_GUARANTEED_OFST 28 10369 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_GUARANTEED_LEN 4 10370 10371 /* MC_CMD_TCM_TXQ_INIT_OUT msgresponse */ 10372 #define MC_CMD_TCM_TXQ_INIT_OUT_LEN 0 10373 10374 10375 /***********************************/ 10376 /* MC_CMD_LINK_PIOBUF 10377 * Link a push I/O buffer to a TxQ 10378 */ 10379 #define MC_CMD_LINK_PIOBUF 0x92 10380 #undef MC_CMD_0x92_PRIVILEGE_CTG 10381 10382 #define MC_CMD_0x92_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 10383 10384 /* MC_CMD_LINK_PIOBUF_IN msgrequest */ 10385 #define MC_CMD_LINK_PIOBUF_IN_LEN 8 10386 /* Handle for allocated push I/O buffer. */ 10387 #define MC_CMD_LINK_PIOBUF_IN_PIOBUF_HANDLE_OFST 0 10388 #define MC_CMD_LINK_PIOBUF_IN_PIOBUF_HANDLE_LEN 4 10389 /* Function Local Instance (VI) number. */ 10390 #define MC_CMD_LINK_PIOBUF_IN_TXQ_INSTANCE_OFST 4 10391 #define MC_CMD_LINK_PIOBUF_IN_TXQ_INSTANCE_LEN 4 10392 10393 /* MC_CMD_LINK_PIOBUF_OUT msgresponse */ 10394 #define MC_CMD_LINK_PIOBUF_OUT_LEN 0 10395 10396 10397 /***********************************/ 10398 /* MC_CMD_UNLINK_PIOBUF 10399 * Unlink a push I/O buffer from a TxQ 10400 */ 10401 #define MC_CMD_UNLINK_PIOBUF 0x93 10402 #undef MC_CMD_0x93_PRIVILEGE_CTG 10403 10404 #define MC_CMD_0x93_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 10405 10406 /* MC_CMD_UNLINK_PIOBUF_IN msgrequest */ 10407 #define MC_CMD_UNLINK_PIOBUF_IN_LEN 4 10408 /* Function Local Instance (VI) number. */ 10409 #define MC_CMD_UNLINK_PIOBUF_IN_TXQ_INSTANCE_OFST 0 10410 #define MC_CMD_UNLINK_PIOBUF_IN_TXQ_INSTANCE_LEN 4 10411 10412 /* MC_CMD_UNLINK_PIOBUF_OUT msgresponse */ 10413 #define MC_CMD_UNLINK_PIOBUF_OUT_LEN 0 10414 10415 10416 /***********************************/ 10417 /* MC_CMD_VSWITCH_ALLOC 10418 * allocate and initialise a v-switch. 10419 */ 10420 #define MC_CMD_VSWITCH_ALLOC 0x94 10421 #undef MC_CMD_0x94_PRIVILEGE_CTG 10422 10423 #define MC_CMD_0x94_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10424 10425 /* MC_CMD_VSWITCH_ALLOC_IN msgrequest */ 10426 #define MC_CMD_VSWITCH_ALLOC_IN_LEN 16 10427 /* The port to connect to the v-switch's upstream port. */ 10428 #define MC_CMD_VSWITCH_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 10429 #define MC_CMD_VSWITCH_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4 10430 /* The type of v-switch to create. */ 10431 #define MC_CMD_VSWITCH_ALLOC_IN_TYPE_OFST 4 10432 #define MC_CMD_VSWITCH_ALLOC_IN_TYPE_LEN 4 10433 /* enum: VLAN */ 10434 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VLAN 0x1 10435 /* enum: VEB */ 10436 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEB 0x2 10437 /* enum: VEPA (obsolete) */ 10438 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEPA 0x3 10439 /* enum: MUX */ 10440 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_MUX 0x4 10441 /* enum: Snapper specific; semantics TBD */ 10442 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_TEST 0x5 10443 /* Flags controlling v-port creation */ 10444 #define MC_CMD_VSWITCH_ALLOC_IN_FLAGS_OFST 8 10445 #define MC_CMD_VSWITCH_ALLOC_IN_FLAGS_LEN 4 10446 #define MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_LBN 0 10447 #define MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_WIDTH 1 10448 /* The number of VLAN tags to allow for attached v-ports. For VLAN aggregators, 10449 * this must be one or greated, and the attached v-ports must have exactly this 10450 * number of tags. For other v-switch types, this must be zero of greater, and 10451 * is an upper limit on the number of VLAN tags for attached v-ports. An error 10452 * will be returned if existing configuration means we can't support attached 10453 * v-ports with this number of tags. 10454 */ 10455 #define MC_CMD_VSWITCH_ALLOC_IN_NUM_VLAN_TAGS_OFST 12 10456 #define MC_CMD_VSWITCH_ALLOC_IN_NUM_VLAN_TAGS_LEN 4 10457 10458 /* MC_CMD_VSWITCH_ALLOC_OUT msgresponse */ 10459 #define MC_CMD_VSWITCH_ALLOC_OUT_LEN 0 10460 10461 10462 /***********************************/ 10463 /* MC_CMD_VSWITCH_FREE 10464 * de-allocate a v-switch. 10465 */ 10466 #define MC_CMD_VSWITCH_FREE 0x95 10467 #undef MC_CMD_0x95_PRIVILEGE_CTG 10468 10469 #define MC_CMD_0x95_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10470 10471 /* MC_CMD_VSWITCH_FREE_IN msgrequest */ 10472 #define MC_CMD_VSWITCH_FREE_IN_LEN 4 10473 /* The port to which the v-switch is connected. */ 10474 #define MC_CMD_VSWITCH_FREE_IN_UPSTREAM_PORT_ID_OFST 0 10475 #define MC_CMD_VSWITCH_FREE_IN_UPSTREAM_PORT_ID_LEN 4 10476 10477 /* MC_CMD_VSWITCH_FREE_OUT msgresponse */ 10478 #define MC_CMD_VSWITCH_FREE_OUT_LEN 0 10479 10480 10481 /***********************************/ 10482 /* MC_CMD_VSWITCH_QUERY 10483 * read some config of v-switch. For now this command is an empty placeholder. 10484 * It may be used to check if a v-switch is connected to a given EVB port (if 10485 * not, then the command returns ENOENT). 10486 */ 10487 #define MC_CMD_VSWITCH_QUERY 0x63 10488 #undef MC_CMD_0x63_PRIVILEGE_CTG 10489 10490 #define MC_CMD_0x63_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10491 10492 /* MC_CMD_VSWITCH_QUERY_IN msgrequest */ 10493 #define MC_CMD_VSWITCH_QUERY_IN_LEN 4 10494 /* The port to which the v-switch is connected. */ 10495 #define MC_CMD_VSWITCH_QUERY_IN_UPSTREAM_PORT_ID_OFST 0 10496 #define MC_CMD_VSWITCH_QUERY_IN_UPSTREAM_PORT_ID_LEN 4 10497 10498 /* MC_CMD_VSWITCH_QUERY_OUT msgresponse */ 10499 #define MC_CMD_VSWITCH_QUERY_OUT_LEN 0 10500 10501 10502 /***********************************/ 10503 /* MC_CMD_VPORT_ALLOC 10504 * allocate a v-port. 10505 */ 10506 #define MC_CMD_VPORT_ALLOC 0x96 10507 #undef MC_CMD_0x96_PRIVILEGE_CTG 10508 10509 #define MC_CMD_0x96_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10510 10511 /* MC_CMD_VPORT_ALLOC_IN msgrequest */ 10512 #define MC_CMD_VPORT_ALLOC_IN_LEN 20 10513 /* The port to which the v-switch is connected. */ 10514 #define MC_CMD_VPORT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 10515 #define MC_CMD_VPORT_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4 10516 /* The type of the new v-port. */ 10517 #define MC_CMD_VPORT_ALLOC_IN_TYPE_OFST 4 10518 #define MC_CMD_VPORT_ALLOC_IN_TYPE_LEN 4 10519 /* enum: VLAN (obsolete) */ 10520 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VLAN 0x1 10521 /* enum: VEB (obsolete) */ 10522 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEB 0x2 10523 /* enum: VEPA (obsolete) */ 10524 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEPA 0x3 10525 /* enum: A normal v-port receives packets which match a specified MAC and/or 10526 * VLAN. 10527 */ 10528 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_NORMAL 0x4 10529 /* enum: An expansion v-port packets traffic which don't match any other 10530 * v-port. 10531 */ 10532 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_EXPANSION 0x5 10533 /* enum: An test v-port receives packets which match any filters installed by 10534 * its downstream components. 10535 */ 10536 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_TEST 0x6 10537 /* Flags controlling v-port creation */ 10538 #define MC_CMD_VPORT_ALLOC_IN_FLAGS_OFST 8 10539 #define MC_CMD_VPORT_ALLOC_IN_FLAGS_LEN 4 10540 #define MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_LBN 0 10541 #define MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_WIDTH 1 10542 #define MC_CMD_VPORT_ALLOC_IN_FLAG_VLAN_RESTRICT_LBN 1 10543 #define MC_CMD_VPORT_ALLOC_IN_FLAG_VLAN_RESTRICT_WIDTH 1 10544 /* The number of VLAN tags to insert/remove. An error will be returned if 10545 * incompatible with the number of VLAN tags specified for the upstream 10546 * v-switch. 10547 */ 10548 #define MC_CMD_VPORT_ALLOC_IN_NUM_VLAN_TAGS_OFST 12 10549 #define MC_CMD_VPORT_ALLOC_IN_NUM_VLAN_TAGS_LEN 4 10550 /* The actual VLAN tags to insert/remove */ 10551 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAGS_OFST 16 10552 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAGS_LEN 4 10553 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_LBN 0 10554 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_WIDTH 16 10555 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_LBN 16 10556 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_WIDTH 16 10557 10558 /* MC_CMD_VPORT_ALLOC_OUT msgresponse */ 10559 #define MC_CMD_VPORT_ALLOC_OUT_LEN 4 10560 /* The handle of the new v-port */ 10561 #define MC_CMD_VPORT_ALLOC_OUT_VPORT_ID_OFST 0 10562 #define MC_CMD_VPORT_ALLOC_OUT_VPORT_ID_LEN 4 10563 10564 10565 /***********************************/ 10566 /* MC_CMD_VPORT_FREE 10567 * de-allocate a v-port. 10568 */ 10569 #define MC_CMD_VPORT_FREE 0x97 10570 #undef MC_CMD_0x97_PRIVILEGE_CTG 10571 10572 #define MC_CMD_0x97_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10573 10574 /* MC_CMD_VPORT_FREE_IN msgrequest */ 10575 #define MC_CMD_VPORT_FREE_IN_LEN 4 10576 /* The handle of the v-port */ 10577 #define MC_CMD_VPORT_FREE_IN_VPORT_ID_OFST 0 10578 #define MC_CMD_VPORT_FREE_IN_VPORT_ID_LEN 4 10579 10580 /* MC_CMD_VPORT_FREE_OUT msgresponse */ 10581 #define MC_CMD_VPORT_FREE_OUT_LEN 0 10582 10583 10584 /***********************************/ 10585 /* MC_CMD_VADAPTOR_ALLOC 10586 * allocate a v-adaptor. 10587 */ 10588 #define MC_CMD_VADAPTOR_ALLOC 0x98 10589 #undef MC_CMD_0x98_PRIVILEGE_CTG 10590 10591 #define MC_CMD_0x98_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10592 10593 /* MC_CMD_VADAPTOR_ALLOC_IN msgrequest */ 10594 #define MC_CMD_VADAPTOR_ALLOC_IN_LEN 30 10595 /* The port to connect to the v-adaptor's port. */ 10596 #define MC_CMD_VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 10597 #define MC_CMD_VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4 10598 /* Flags controlling v-adaptor creation */ 10599 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAGS_OFST 8 10600 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAGS_LEN 4 10601 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_LBN 0 10602 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_WIDTH 1 10603 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 1 10604 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1 10605 /* The number of VLAN tags to strip on receive */ 10606 #define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLANS_OFST 12 10607 #define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLANS_LEN 4 10608 /* The number of VLAN tags to transparently insert/remove. */ 10609 #define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLAN_TAGS_OFST 16 10610 #define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLAN_TAGS_LEN 4 10611 /* The actual VLAN tags to insert/remove */ 10612 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAGS_OFST 20 10613 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAGS_LEN 4 10614 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_0_LBN 0 10615 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_0_WIDTH 16 10616 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_1_LBN 16 10617 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_1_WIDTH 16 10618 /* The MAC address to assign to this v-adaptor */ 10619 #define MC_CMD_VADAPTOR_ALLOC_IN_MACADDR_OFST 24 10620 #define MC_CMD_VADAPTOR_ALLOC_IN_MACADDR_LEN 6 10621 /* enum: Derive the MAC address from the upstream port */ 10622 #define MC_CMD_VADAPTOR_ALLOC_IN_AUTO_MAC 0x0 10623 10624 /* MC_CMD_VADAPTOR_ALLOC_OUT msgresponse */ 10625 #define MC_CMD_VADAPTOR_ALLOC_OUT_LEN 0 10626 10627 10628 /***********************************/ 10629 /* MC_CMD_VADAPTOR_FREE 10630 * de-allocate a v-adaptor. 10631 */ 10632 #define MC_CMD_VADAPTOR_FREE 0x99 10633 #undef MC_CMD_0x99_PRIVILEGE_CTG 10634 10635 #define MC_CMD_0x99_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10636 10637 /* MC_CMD_VADAPTOR_FREE_IN msgrequest */ 10638 #define MC_CMD_VADAPTOR_FREE_IN_LEN 4 10639 /* The port to which the v-adaptor is connected. */ 10640 #define MC_CMD_VADAPTOR_FREE_IN_UPSTREAM_PORT_ID_OFST 0 10641 #define MC_CMD_VADAPTOR_FREE_IN_UPSTREAM_PORT_ID_LEN 4 10642 10643 /* MC_CMD_VADAPTOR_FREE_OUT msgresponse */ 10644 #define MC_CMD_VADAPTOR_FREE_OUT_LEN 0 10645 10646 10647 /***********************************/ 10648 /* MC_CMD_VADAPTOR_SET_MAC 10649 * assign a new MAC address to a v-adaptor. 10650 */ 10651 #define MC_CMD_VADAPTOR_SET_MAC 0x5d 10652 #undef MC_CMD_0x5d_PRIVILEGE_CTG 10653 10654 #define MC_CMD_0x5d_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10655 10656 /* MC_CMD_VADAPTOR_SET_MAC_IN msgrequest */ 10657 #define MC_CMD_VADAPTOR_SET_MAC_IN_LEN 10 10658 /* The port to which the v-adaptor is connected. */ 10659 #define MC_CMD_VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID_OFST 0 10660 #define MC_CMD_VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID_LEN 4 10661 /* The new MAC address to assign to this v-adaptor */ 10662 #define MC_CMD_VADAPTOR_SET_MAC_IN_MACADDR_OFST 4 10663 #define MC_CMD_VADAPTOR_SET_MAC_IN_MACADDR_LEN 6 10664 10665 /* MC_CMD_VADAPTOR_SET_MAC_OUT msgresponse */ 10666 #define MC_CMD_VADAPTOR_SET_MAC_OUT_LEN 0 10667 10668 10669 /***********************************/ 10670 /* MC_CMD_VADAPTOR_GET_MAC 10671 * read the MAC address assigned to a v-adaptor. 10672 */ 10673 #define MC_CMD_VADAPTOR_GET_MAC 0x5e 10674 #undef MC_CMD_0x5e_PRIVILEGE_CTG 10675 10676 #define MC_CMD_0x5e_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10677 10678 /* MC_CMD_VADAPTOR_GET_MAC_IN msgrequest */ 10679 #define MC_CMD_VADAPTOR_GET_MAC_IN_LEN 4 10680 /* The port to which the v-adaptor is connected. */ 10681 #define MC_CMD_VADAPTOR_GET_MAC_IN_UPSTREAM_PORT_ID_OFST 0 10682 #define MC_CMD_VADAPTOR_GET_MAC_IN_UPSTREAM_PORT_ID_LEN 4 10683 10684 /* MC_CMD_VADAPTOR_GET_MAC_OUT msgresponse */ 10685 #define MC_CMD_VADAPTOR_GET_MAC_OUT_LEN 6 10686 /* The MAC address assigned to this v-adaptor */ 10687 #define MC_CMD_VADAPTOR_GET_MAC_OUT_MACADDR_OFST 0 10688 #define MC_CMD_VADAPTOR_GET_MAC_OUT_MACADDR_LEN 6 10689 10690 10691 /***********************************/ 10692 /* MC_CMD_VADAPTOR_QUERY 10693 * read some config of v-adaptor. 10694 */ 10695 #define MC_CMD_VADAPTOR_QUERY 0x61 10696 #undef MC_CMD_0x61_PRIVILEGE_CTG 10697 10698 #define MC_CMD_0x61_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10699 10700 /* MC_CMD_VADAPTOR_QUERY_IN msgrequest */ 10701 #define MC_CMD_VADAPTOR_QUERY_IN_LEN 4 10702 /* The port to which the v-adaptor is connected. */ 10703 #define MC_CMD_VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID_OFST 0 10704 #define MC_CMD_VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID_LEN 4 10705 10706 /* MC_CMD_VADAPTOR_QUERY_OUT msgresponse */ 10707 #define MC_CMD_VADAPTOR_QUERY_OUT_LEN 12 10708 /* The EVB port flags as defined at MC_CMD_VPORT_ALLOC. */ 10709 #define MC_CMD_VADAPTOR_QUERY_OUT_PORT_FLAGS_OFST 0 10710 #define MC_CMD_VADAPTOR_QUERY_OUT_PORT_FLAGS_LEN 4 10711 /* The v-adaptor flags as defined at MC_CMD_VADAPTOR_ALLOC. */ 10712 #define MC_CMD_VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS_OFST 4 10713 #define MC_CMD_VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS_LEN 4 10714 /* The number of VLAN tags that may still be added */ 10715 #define MC_CMD_VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_OFST 8 10716 #define MC_CMD_VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_LEN 4 10717 10718 10719 /***********************************/ 10720 /* MC_CMD_EVB_PORT_ASSIGN 10721 * assign a port to a PCI function. 10722 */ 10723 #define MC_CMD_EVB_PORT_ASSIGN 0x9a 10724 #undef MC_CMD_0x9a_PRIVILEGE_CTG 10725 10726 #define MC_CMD_0x9a_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10727 10728 /* MC_CMD_EVB_PORT_ASSIGN_IN msgrequest */ 10729 #define MC_CMD_EVB_PORT_ASSIGN_IN_LEN 8 10730 /* The port to assign. */ 10731 #define MC_CMD_EVB_PORT_ASSIGN_IN_PORT_ID_OFST 0 10732 #define MC_CMD_EVB_PORT_ASSIGN_IN_PORT_ID_LEN 4 10733 /* The target function to modify. */ 10734 #define MC_CMD_EVB_PORT_ASSIGN_IN_FUNCTION_OFST 4 10735 #define MC_CMD_EVB_PORT_ASSIGN_IN_FUNCTION_LEN 4 10736 #define MC_CMD_EVB_PORT_ASSIGN_IN_PF_LBN 0 10737 #define MC_CMD_EVB_PORT_ASSIGN_IN_PF_WIDTH 16 10738 #define MC_CMD_EVB_PORT_ASSIGN_IN_VF_LBN 16 10739 #define MC_CMD_EVB_PORT_ASSIGN_IN_VF_WIDTH 16 10740 10741 /* MC_CMD_EVB_PORT_ASSIGN_OUT msgresponse */ 10742 #define MC_CMD_EVB_PORT_ASSIGN_OUT_LEN 0 10743 10744 10745 /***********************************/ 10746 /* MC_CMD_RDWR_A64_REGIONS 10747 * Assign the 64 bit region addresses. 10748 */ 10749 #define MC_CMD_RDWR_A64_REGIONS 0x9b 10750 #undef MC_CMD_0x9b_PRIVILEGE_CTG 10751 10752 #define MC_CMD_0x9b_PRIVILEGE_CTG SRIOV_CTG_ADMIN 10753 10754 /* MC_CMD_RDWR_A64_REGIONS_IN msgrequest */ 10755 #define MC_CMD_RDWR_A64_REGIONS_IN_LEN 17 10756 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION0_OFST 0 10757 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION0_LEN 4 10758 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION1_OFST 4 10759 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION1_LEN 4 10760 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION2_OFST 8 10761 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION2_LEN 4 10762 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION3_OFST 12 10763 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION3_LEN 4 10764 /* Write enable bits 0-3, set to write, clear to read. */ 10765 #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_LBN 128 10766 #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_WIDTH 4 10767 #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_BYTE_OFST 16 10768 #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_BYTE_LEN 1 10769 10770 /* MC_CMD_RDWR_A64_REGIONS_OUT msgresponse: This data always included 10771 * regardless of state of write bits in the request. 10772 */ 10773 #define MC_CMD_RDWR_A64_REGIONS_OUT_LEN 16 10774 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION0_OFST 0 10775 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION0_LEN 4 10776 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION1_OFST 4 10777 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION1_LEN 4 10778 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION2_OFST 8 10779 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION2_LEN 4 10780 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION3_OFST 12 10781 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION3_LEN 4 10782 10783 10784 /***********************************/ 10785 /* MC_CMD_ONLOAD_STACK_ALLOC 10786 * Allocate an Onload stack ID. 10787 */ 10788 #define MC_CMD_ONLOAD_STACK_ALLOC 0x9c 10789 #undef MC_CMD_0x9c_PRIVILEGE_CTG 10790 10791 #define MC_CMD_0x9c_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 10792 10793 /* MC_CMD_ONLOAD_STACK_ALLOC_IN msgrequest */ 10794 #define MC_CMD_ONLOAD_STACK_ALLOC_IN_LEN 4 10795 /* The handle of the owning upstream port */ 10796 #define MC_CMD_ONLOAD_STACK_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 10797 #define MC_CMD_ONLOAD_STACK_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4 10798 10799 /* MC_CMD_ONLOAD_STACK_ALLOC_OUT msgresponse */ 10800 #define MC_CMD_ONLOAD_STACK_ALLOC_OUT_LEN 4 10801 /* The handle of the new Onload stack */ 10802 #define MC_CMD_ONLOAD_STACK_ALLOC_OUT_ONLOAD_STACK_ID_OFST 0 10803 #define MC_CMD_ONLOAD_STACK_ALLOC_OUT_ONLOAD_STACK_ID_LEN 4 10804 10805 10806 /***********************************/ 10807 /* MC_CMD_ONLOAD_STACK_FREE 10808 * Free an Onload stack ID. 10809 */ 10810 #define MC_CMD_ONLOAD_STACK_FREE 0x9d 10811 #undef MC_CMD_0x9d_PRIVILEGE_CTG 10812 10813 #define MC_CMD_0x9d_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 10814 10815 /* MC_CMD_ONLOAD_STACK_FREE_IN msgrequest */ 10816 #define MC_CMD_ONLOAD_STACK_FREE_IN_LEN 4 10817 /* The handle of the Onload stack */ 10818 #define MC_CMD_ONLOAD_STACK_FREE_IN_ONLOAD_STACK_ID_OFST 0 10819 #define MC_CMD_ONLOAD_STACK_FREE_IN_ONLOAD_STACK_ID_LEN 4 10820 10821 /* MC_CMD_ONLOAD_STACK_FREE_OUT msgresponse */ 10822 #define MC_CMD_ONLOAD_STACK_FREE_OUT_LEN 0 10823 10824 10825 /***********************************/ 10826 /* MC_CMD_RSS_CONTEXT_ALLOC 10827 * Allocate an RSS context. 10828 */ 10829 #define MC_CMD_RSS_CONTEXT_ALLOC 0x9e 10830 #undef MC_CMD_0x9e_PRIVILEGE_CTG 10831 10832 #define MC_CMD_0x9e_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10833 10834 /* MC_CMD_RSS_CONTEXT_ALLOC_IN msgrequest */ 10835 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN 12 10836 /* The handle of the owning upstream port */ 10837 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 10838 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4 10839 /* The type of context to allocate */ 10840 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_OFST 4 10841 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_LEN 4 10842 /* enum: Allocate a context for exclusive use. The key and indirection table 10843 * must be explicitly configured. 10844 */ 10845 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE 0x0 10846 /* enum: Allocate a context for shared use; this will spread across a range of 10847 * queues, but the key and indirection table are pre-configured and may not be 10848 * changed. For this mode, NUM_QUEUES must 2, 4, 8, 16, 32 or 64. 10849 */ 10850 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED 0x1 10851 /* Number of queues spanned by this context, in the range 1-64; valid offsets 10852 * in the indirection table will be in the range 0 to NUM_QUEUES-1. 10853 */ 10854 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_NUM_QUEUES_OFST 8 10855 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_NUM_QUEUES_LEN 4 10856 10857 /* MC_CMD_RSS_CONTEXT_ALLOC_OUT msgresponse */ 10858 #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN 4 10859 /* The handle of the new RSS context. This should be considered opaque to the 10860 * host, although a value of 0xFFFFFFFF is guaranteed never to be a valid 10861 * handle. 10862 */ 10863 #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_OFST 0 10864 #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_LEN 4 10865 /* enum: guaranteed invalid RSS context handle value */ 10866 #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_INVALID 0xffffffff 10867 10868 10869 /***********************************/ 10870 /* MC_CMD_RSS_CONTEXT_FREE 10871 * Free an RSS context. 10872 */ 10873 #define MC_CMD_RSS_CONTEXT_FREE 0x9f 10874 #undef MC_CMD_0x9f_PRIVILEGE_CTG 10875 10876 #define MC_CMD_0x9f_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10877 10878 /* MC_CMD_RSS_CONTEXT_FREE_IN msgrequest */ 10879 #define MC_CMD_RSS_CONTEXT_FREE_IN_LEN 4 10880 /* The handle of the RSS context */ 10881 #define MC_CMD_RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID_OFST 0 10882 #define MC_CMD_RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID_LEN 4 10883 10884 /* MC_CMD_RSS_CONTEXT_FREE_OUT msgresponse */ 10885 #define MC_CMD_RSS_CONTEXT_FREE_OUT_LEN 0 10886 10887 10888 /***********************************/ 10889 /* MC_CMD_RSS_CONTEXT_SET_KEY 10890 * Set the Toeplitz hash key for an RSS context. 10891 */ 10892 #define MC_CMD_RSS_CONTEXT_SET_KEY 0xa0 10893 #undef MC_CMD_0xa0_PRIVILEGE_CTG 10894 10895 #define MC_CMD_0xa0_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10896 10897 /* MC_CMD_RSS_CONTEXT_SET_KEY_IN msgrequest */ 10898 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN 44 10899 /* The handle of the RSS context */ 10900 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID_OFST 0 10901 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID_LEN 4 10902 /* The 40-byte Toeplitz hash key (TBD endianness issues?) */ 10903 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_OFST 4 10904 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN 40 10905 10906 /* MC_CMD_RSS_CONTEXT_SET_KEY_OUT msgresponse */ 10907 #define MC_CMD_RSS_CONTEXT_SET_KEY_OUT_LEN 0 10908 10909 10910 /***********************************/ 10911 /* MC_CMD_RSS_CONTEXT_GET_KEY 10912 * Get the Toeplitz hash key for an RSS context. 10913 */ 10914 #define MC_CMD_RSS_CONTEXT_GET_KEY 0xa1 10915 #undef MC_CMD_0xa1_PRIVILEGE_CTG 10916 10917 #define MC_CMD_0xa1_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10918 10919 /* MC_CMD_RSS_CONTEXT_GET_KEY_IN msgrequest */ 10920 #define MC_CMD_RSS_CONTEXT_GET_KEY_IN_LEN 4 10921 /* The handle of the RSS context */ 10922 #define MC_CMD_RSS_CONTEXT_GET_KEY_IN_RSS_CONTEXT_ID_OFST 0 10923 #define MC_CMD_RSS_CONTEXT_GET_KEY_IN_RSS_CONTEXT_ID_LEN 4 10924 10925 /* MC_CMD_RSS_CONTEXT_GET_KEY_OUT msgresponse */ 10926 #define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_LEN 44 10927 /* The 40-byte Toeplitz hash key (TBD endianness issues?) */ 10928 #define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY_OFST 4 10929 #define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY_LEN 40 10930 10931 10932 /***********************************/ 10933 /* MC_CMD_RSS_CONTEXT_SET_TABLE 10934 * Set the indirection table for an RSS context. 10935 */ 10936 #define MC_CMD_RSS_CONTEXT_SET_TABLE 0xa2 10937 #undef MC_CMD_0xa2_PRIVILEGE_CTG 10938 10939 #define MC_CMD_0xa2_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10940 10941 /* MC_CMD_RSS_CONTEXT_SET_TABLE_IN msgrequest */ 10942 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN 132 10943 /* The handle of the RSS context */ 10944 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID_OFST 0 10945 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID_LEN 4 10946 /* The 128-byte indirection table (1 byte per entry) */ 10947 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_OFST 4 10948 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN 128 10949 10950 /* MC_CMD_RSS_CONTEXT_SET_TABLE_OUT msgresponse */ 10951 #define MC_CMD_RSS_CONTEXT_SET_TABLE_OUT_LEN 0 10952 10953 10954 /***********************************/ 10955 /* MC_CMD_RSS_CONTEXT_GET_TABLE 10956 * Get the indirection table for an RSS context. 10957 */ 10958 #define MC_CMD_RSS_CONTEXT_GET_TABLE 0xa3 10959 #undef MC_CMD_0xa3_PRIVILEGE_CTG 10960 10961 #define MC_CMD_0xa3_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10962 10963 /* MC_CMD_RSS_CONTEXT_GET_TABLE_IN msgrequest */ 10964 #define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_LEN 4 10965 /* The handle of the RSS context */ 10966 #define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_RSS_CONTEXT_ID_OFST 0 10967 #define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_RSS_CONTEXT_ID_LEN 4 10968 10969 /* MC_CMD_RSS_CONTEXT_GET_TABLE_OUT msgresponse */ 10970 #define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_LEN 132 10971 /* The 128-byte indirection table (1 byte per entry) */ 10972 #define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_OFST 4 10973 #define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_LEN 128 10974 10975 10976 /***********************************/ 10977 /* MC_CMD_RSS_CONTEXT_SET_FLAGS 10978 * Set various control flags for an RSS context. 10979 */ 10980 #define MC_CMD_RSS_CONTEXT_SET_FLAGS 0xe1 10981 #undef MC_CMD_0xe1_PRIVILEGE_CTG 10982 10983 #define MC_CMD_0xe1_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10984 10985 /* MC_CMD_RSS_CONTEXT_SET_FLAGS_IN msgrequest */ 10986 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_LEN 8 10987 /* The handle of the RSS context */ 10988 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID_OFST 0 10989 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID_LEN 4 10990 /* Hash control flags. The _EN bits are always supported, but new modes are 10991 * available when ADDITIONAL_RSS_MODES is reported by MC_CMD_GET_CAPABILITIES: 10992 * in this case, the MODE fields may be set to non-zero values, and will take 10993 * effect regardless of the settings of the _EN flags. See the RSS_MODE 10994 * structure for the meaning of the mode bits. Drivers must check the 10995 * capability before trying to set any _MODE fields, as older firmware will 10996 * reject any attempt to set the FLAGS field to a value > 0xff with EINVAL. In 10997 * the case where all the _MODE flags are zero, the _EN flags take effect, 10998 * providing backward compatibility for existing drivers. (Setting all _MODE 10999 * *and* all _EN flags to zero is valid, to disable RSS spreading for that 11000 * particular packet type.) 11001 */ 11002 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_FLAGS_OFST 4 11003 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_FLAGS_LEN 4 11004 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_LBN 0 11005 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_WIDTH 1 11006 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_LBN 1 11007 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_WIDTH 1 11008 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_LBN 2 11009 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_WIDTH 1 11010 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_LBN 3 11011 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_WIDTH 1 11012 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_LBN 4 11013 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_WIDTH 4 11014 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_LBN 8 11015 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_WIDTH 4 11016 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE_LBN 12 11017 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE_WIDTH 4 11018 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_LBN 16 11019 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_WIDTH 4 11020 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_LBN 20 11021 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_WIDTH 4 11022 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE_LBN 24 11023 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE_WIDTH 4 11024 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_LBN 28 11025 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_WIDTH 4 11026 11027 /* MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT msgresponse */ 11028 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT_LEN 0 11029 11030 11031 /***********************************/ 11032 /* MC_CMD_RSS_CONTEXT_GET_FLAGS 11033 * Get various control flags for an RSS context. 11034 */ 11035 #define MC_CMD_RSS_CONTEXT_GET_FLAGS 0xe2 11036 #undef MC_CMD_0xe2_PRIVILEGE_CTG 11037 11038 #define MC_CMD_0xe2_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11039 11040 /* MC_CMD_RSS_CONTEXT_GET_FLAGS_IN msgrequest */ 11041 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_LEN 4 11042 /* The handle of the RSS context */ 11043 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_RSS_CONTEXT_ID_OFST 0 11044 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_RSS_CONTEXT_ID_LEN 4 11045 11046 /* MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT msgresponse */ 11047 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN 8 11048 /* Hash control flags. If all _MODE bits are zero (which will always be true 11049 * for older firmware which does not report the ADDITIONAL_RSS_MODES 11050 * capability), the _EN bits report the state. If any _MODE bits are non-zero 11051 * (which will only be true when the firmware reports ADDITIONAL_RSS_MODES) 11052 * then the _EN bits should be disregarded, although the _MODE flags are 11053 * guaranteed to be consistent with the _EN flags for a freshly-allocated RSS 11054 * context and in the case where the _EN flags were used in the SET. This 11055 * provides backward compatibility: old drivers will not be attempting to 11056 * derive any meaning from the _MODE bits (and can never set them to any value 11057 * not representable by the _EN bits); new drivers can always determine the 11058 * mode by looking only at the _MODE bits; the value returned by a GET can 11059 * always be used for a SET regardless of old/new driver vs. old/new firmware. 11060 */ 11061 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_OFST 4 11062 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_LEN 4 11063 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_LBN 0 11064 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_WIDTH 1 11065 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_LBN 1 11066 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_WIDTH 1 11067 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_LBN 2 11068 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_WIDTH 1 11069 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_LBN 3 11070 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_WIDTH 1 11071 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_LBN 4 11072 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_WIDTH 4 11073 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_LBN 8 11074 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_WIDTH 4 11075 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_LBN 12 11076 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_WIDTH 4 11077 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_LBN 16 11078 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_WIDTH 4 11079 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_LBN 20 11080 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_WIDTH 4 11081 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_LBN 24 11082 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_WIDTH 4 11083 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_LBN 28 11084 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_WIDTH 4 11085 11086 11087 /***********************************/ 11088 /* MC_CMD_DOT1P_MAPPING_ALLOC 11089 * Allocate a .1p mapping. 11090 */ 11091 #define MC_CMD_DOT1P_MAPPING_ALLOC 0xa4 11092 #undef MC_CMD_0xa4_PRIVILEGE_CTG 11093 11094 #define MC_CMD_0xa4_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11095 11096 /* MC_CMD_DOT1P_MAPPING_ALLOC_IN msgrequest */ 11097 #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_LEN 8 11098 /* The handle of the owning upstream port */ 11099 #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 11100 #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4 11101 /* Number of queues spanned by this mapping, in the range 1-64; valid fixed 11102 * offsets in the mapping table will be in the range 0 to NUM_QUEUES-1, and 11103 * referenced RSS contexts must span no more than this number. 11104 */ 11105 #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_NUM_QUEUES_OFST 4 11106 #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_NUM_QUEUES_LEN 4 11107 11108 /* MC_CMD_DOT1P_MAPPING_ALLOC_OUT msgresponse */ 11109 #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_LEN 4 11110 /* The handle of the new .1p mapping. This should be considered opaque to the 11111 * host, although a value of 0xFFFFFFFF is guaranteed never to be a valid 11112 * handle. 11113 */ 11114 #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_OFST 0 11115 #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_LEN 4 11116 /* enum: guaranteed invalid .1p mapping handle value */ 11117 #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_INVALID 0xffffffff 11118 11119 11120 /***********************************/ 11121 /* MC_CMD_DOT1P_MAPPING_FREE 11122 * Free a .1p mapping. 11123 */ 11124 #define MC_CMD_DOT1P_MAPPING_FREE 0xa5 11125 #undef MC_CMD_0xa5_PRIVILEGE_CTG 11126 11127 #define MC_CMD_0xa5_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11128 11129 /* MC_CMD_DOT1P_MAPPING_FREE_IN msgrequest */ 11130 #define MC_CMD_DOT1P_MAPPING_FREE_IN_LEN 4 11131 /* The handle of the .1p mapping */ 11132 #define MC_CMD_DOT1P_MAPPING_FREE_IN_DOT1P_MAPPING_ID_OFST 0 11133 #define MC_CMD_DOT1P_MAPPING_FREE_IN_DOT1P_MAPPING_ID_LEN 4 11134 11135 /* MC_CMD_DOT1P_MAPPING_FREE_OUT msgresponse */ 11136 #define MC_CMD_DOT1P_MAPPING_FREE_OUT_LEN 0 11137 11138 11139 /***********************************/ 11140 /* MC_CMD_DOT1P_MAPPING_SET_TABLE 11141 * Set the mapping table for a .1p mapping. 11142 */ 11143 #define MC_CMD_DOT1P_MAPPING_SET_TABLE 0xa6 11144 #undef MC_CMD_0xa6_PRIVILEGE_CTG 11145 11146 #define MC_CMD_0xa6_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11147 11148 /* MC_CMD_DOT1P_MAPPING_SET_TABLE_IN msgrequest */ 11149 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_LEN 36 11150 /* The handle of the .1p mapping */ 11151 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_DOT1P_MAPPING_ID_OFST 0 11152 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_DOT1P_MAPPING_ID_LEN 4 11153 /* Per-priority mappings (1 32-bit word per entry - an offset or RSS context 11154 * handle) 11155 */ 11156 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_MAPPING_TABLE_OFST 4 11157 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_MAPPING_TABLE_LEN 32 11158 11159 /* MC_CMD_DOT1P_MAPPING_SET_TABLE_OUT msgresponse */ 11160 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_OUT_LEN 0 11161 11162 11163 /***********************************/ 11164 /* MC_CMD_DOT1P_MAPPING_GET_TABLE 11165 * Get the mapping table for a .1p mapping. 11166 */ 11167 #define MC_CMD_DOT1P_MAPPING_GET_TABLE 0xa7 11168 #undef MC_CMD_0xa7_PRIVILEGE_CTG 11169 11170 #define MC_CMD_0xa7_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11171 11172 /* MC_CMD_DOT1P_MAPPING_GET_TABLE_IN msgrequest */ 11173 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_IN_LEN 4 11174 /* The handle of the .1p mapping */ 11175 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_IN_DOT1P_MAPPING_ID_OFST 0 11176 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_IN_DOT1P_MAPPING_ID_LEN 4 11177 11178 /* MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT msgresponse */ 11179 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_LEN 36 11180 /* Per-priority mappings (1 32-bit word per entry - an offset or RSS context 11181 * handle) 11182 */ 11183 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_MAPPING_TABLE_OFST 4 11184 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_MAPPING_TABLE_LEN 32 11185 11186 11187 /***********************************/ 11188 /* MC_CMD_GET_VECTOR_CFG 11189 * Get Interrupt Vector config for this PF. 11190 */ 11191 #define MC_CMD_GET_VECTOR_CFG 0xbf 11192 #undef MC_CMD_0xbf_PRIVILEGE_CTG 11193 11194 #define MC_CMD_0xbf_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11195 11196 /* MC_CMD_GET_VECTOR_CFG_IN msgrequest */ 11197 #define MC_CMD_GET_VECTOR_CFG_IN_LEN 0 11198 11199 /* MC_CMD_GET_VECTOR_CFG_OUT msgresponse */ 11200 #define MC_CMD_GET_VECTOR_CFG_OUT_LEN 12 11201 /* Base absolute interrupt vector number. */ 11202 #define MC_CMD_GET_VECTOR_CFG_OUT_VEC_BASE_OFST 0 11203 #define MC_CMD_GET_VECTOR_CFG_OUT_VEC_BASE_LEN 4 11204 /* Number of interrupt vectors allocate to this PF. */ 11205 #define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_PF_OFST 4 11206 #define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_PF_LEN 4 11207 /* Number of interrupt vectors to allocate per VF. */ 11208 #define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_VF_OFST 8 11209 #define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_VF_LEN 4 11210 11211 11212 /***********************************/ 11213 /* MC_CMD_SET_VECTOR_CFG 11214 * Set Interrupt Vector config for this PF. 11215 */ 11216 #define MC_CMD_SET_VECTOR_CFG 0xc0 11217 #undef MC_CMD_0xc0_PRIVILEGE_CTG 11218 11219 #define MC_CMD_0xc0_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11220 11221 /* MC_CMD_SET_VECTOR_CFG_IN msgrequest */ 11222 #define MC_CMD_SET_VECTOR_CFG_IN_LEN 12 11223 /* Base absolute interrupt vector number, or MC_CMD_RESOURCE_INSTANCE_ANY to 11224 * let the system find a suitable base. 11225 */ 11226 #define MC_CMD_SET_VECTOR_CFG_IN_VEC_BASE_OFST 0 11227 #define MC_CMD_SET_VECTOR_CFG_IN_VEC_BASE_LEN 4 11228 /* Number of interrupt vectors allocate to this PF. */ 11229 #define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_PF_OFST 4 11230 #define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_PF_LEN 4 11231 /* Number of interrupt vectors to allocate per VF. */ 11232 #define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_VF_OFST 8 11233 #define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_VF_LEN 4 11234 11235 /* MC_CMD_SET_VECTOR_CFG_OUT msgresponse */ 11236 #define MC_CMD_SET_VECTOR_CFG_OUT_LEN 0 11237 11238 11239 /***********************************/ 11240 /* MC_CMD_VPORT_ADD_MAC_ADDRESS 11241 * Add a MAC address to a v-port 11242 */ 11243 #define MC_CMD_VPORT_ADD_MAC_ADDRESS 0xa8 11244 #undef MC_CMD_0xa8_PRIVILEGE_CTG 11245 11246 #define MC_CMD_0xa8_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11247 11248 /* MC_CMD_VPORT_ADD_MAC_ADDRESS_IN msgrequest */ 11249 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN 10 11250 /* The handle of the v-port */ 11251 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID_OFST 0 11252 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID_LEN 4 11253 /* MAC address to add */ 11254 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_MACADDR_OFST 4 11255 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_MACADDR_LEN 6 11256 11257 /* MC_CMD_VPORT_ADD_MAC_ADDRESS_OUT msgresponse */ 11258 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_OUT_LEN 0 11259 11260 11261 /***********************************/ 11262 /* MC_CMD_VPORT_DEL_MAC_ADDRESS 11263 * Delete a MAC address from a v-port 11264 */ 11265 #define MC_CMD_VPORT_DEL_MAC_ADDRESS 0xa9 11266 #undef MC_CMD_0xa9_PRIVILEGE_CTG 11267 11268 #define MC_CMD_0xa9_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11269 11270 /* MC_CMD_VPORT_DEL_MAC_ADDRESS_IN msgrequest */ 11271 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN 10 11272 /* The handle of the v-port */ 11273 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID_OFST 0 11274 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID_LEN 4 11275 /* MAC address to add */ 11276 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_MACADDR_OFST 4 11277 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_MACADDR_LEN 6 11278 11279 /* MC_CMD_VPORT_DEL_MAC_ADDRESS_OUT msgresponse */ 11280 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_OUT_LEN 0 11281 11282 11283 /***********************************/ 11284 /* MC_CMD_VPORT_GET_MAC_ADDRESSES 11285 * Delete a MAC address from a v-port 11286 */ 11287 #define MC_CMD_VPORT_GET_MAC_ADDRESSES 0xaa 11288 #undef MC_CMD_0xaa_PRIVILEGE_CTG 11289 11290 #define MC_CMD_0xaa_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11291 11292 /* MC_CMD_VPORT_GET_MAC_ADDRESSES_IN msgrequest */ 11293 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN 4 11294 /* The handle of the v-port */ 11295 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID_OFST 0 11296 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID_LEN 4 11297 11298 /* MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT msgresponse */ 11299 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN 4 11300 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX 250 11301 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LEN(num) (4+6*(num)) 11302 /* The number of MAC addresses returned */ 11303 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT_OFST 0 11304 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT_LEN 4 11305 /* Array of MAC addresses */ 11306 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_OFST 4 11307 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_LEN 6 11308 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MINNUM 0 11309 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MAXNUM 41 11310 11311 11312 /***********************************/ 11313 /* MC_CMD_VPORT_RECONFIGURE 11314 * Replace VLAN tags and/or MAC addresses of an existing v-port. If the v-port 11315 * has already been passed to another function (v-port's user), then that 11316 * function will be reset before applying the changes. 11317 */ 11318 #define MC_CMD_VPORT_RECONFIGURE 0xeb 11319 #undef MC_CMD_0xeb_PRIVILEGE_CTG 11320 11321 #define MC_CMD_0xeb_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11322 11323 /* MC_CMD_VPORT_RECONFIGURE_IN msgrequest */ 11324 #define MC_CMD_VPORT_RECONFIGURE_IN_LEN 44 11325 /* The handle of the v-port */ 11326 #define MC_CMD_VPORT_RECONFIGURE_IN_VPORT_ID_OFST 0 11327 #define MC_CMD_VPORT_RECONFIGURE_IN_VPORT_ID_LEN 4 11328 /* Flags requesting what should be changed. */ 11329 #define MC_CMD_VPORT_RECONFIGURE_IN_FLAGS_OFST 4 11330 #define MC_CMD_VPORT_RECONFIGURE_IN_FLAGS_LEN 4 11331 #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_VLAN_TAGS_LBN 0 11332 #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_VLAN_TAGS_WIDTH 1 11333 #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_MACADDRS_LBN 1 11334 #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_MACADDRS_WIDTH 1 11335 /* The number of VLAN tags to insert/remove. An error will be returned if 11336 * incompatible with the number of VLAN tags specified for the upstream 11337 * v-switch. 11338 */ 11339 #define MC_CMD_VPORT_RECONFIGURE_IN_NUM_VLAN_TAGS_OFST 8 11340 #define MC_CMD_VPORT_RECONFIGURE_IN_NUM_VLAN_TAGS_LEN 4 11341 /* The actual VLAN tags to insert/remove */ 11342 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAGS_OFST 12 11343 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAGS_LEN 4 11344 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_0_LBN 0 11345 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_0_WIDTH 16 11346 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_1_LBN 16 11347 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_1_WIDTH 16 11348 /* The number of MAC addresses to add */ 11349 #define MC_CMD_VPORT_RECONFIGURE_IN_NUM_MACADDRS_OFST 16 11350 #define MC_CMD_VPORT_RECONFIGURE_IN_NUM_MACADDRS_LEN 4 11351 /* MAC addresses to add */ 11352 #define MC_CMD_VPORT_RECONFIGURE_IN_MACADDRS_OFST 20 11353 #define MC_CMD_VPORT_RECONFIGURE_IN_MACADDRS_LEN 6 11354 #define MC_CMD_VPORT_RECONFIGURE_IN_MACADDRS_NUM 4 11355 11356 /* MC_CMD_VPORT_RECONFIGURE_OUT msgresponse */ 11357 #define MC_CMD_VPORT_RECONFIGURE_OUT_LEN 4 11358 #define MC_CMD_VPORT_RECONFIGURE_OUT_FLAGS_OFST 0 11359 #define MC_CMD_VPORT_RECONFIGURE_OUT_FLAGS_LEN 4 11360 #define MC_CMD_VPORT_RECONFIGURE_OUT_RESET_DONE_LBN 0 11361 #define MC_CMD_VPORT_RECONFIGURE_OUT_RESET_DONE_WIDTH 1 11362 11363 11364 /***********************************/ 11365 /* MC_CMD_EVB_PORT_QUERY 11366 * read some config of v-port. 11367 */ 11368 #define MC_CMD_EVB_PORT_QUERY 0x62 11369 #undef MC_CMD_0x62_PRIVILEGE_CTG 11370 11371 #define MC_CMD_0x62_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11372 11373 /* MC_CMD_EVB_PORT_QUERY_IN msgrequest */ 11374 #define MC_CMD_EVB_PORT_QUERY_IN_LEN 4 11375 /* The handle of the v-port */ 11376 #define MC_CMD_EVB_PORT_QUERY_IN_PORT_ID_OFST 0 11377 #define MC_CMD_EVB_PORT_QUERY_IN_PORT_ID_LEN 4 11378 11379 /* MC_CMD_EVB_PORT_QUERY_OUT msgresponse */ 11380 #define MC_CMD_EVB_PORT_QUERY_OUT_LEN 8 11381 /* The EVB port flags as defined at MC_CMD_VPORT_ALLOC. */ 11382 #define MC_CMD_EVB_PORT_QUERY_OUT_PORT_FLAGS_OFST 0 11383 #define MC_CMD_EVB_PORT_QUERY_OUT_PORT_FLAGS_LEN 4 11384 /* The number of VLAN tags that may be used on a v-adaptor connected to this 11385 * EVB port. 11386 */ 11387 #define MC_CMD_EVB_PORT_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_OFST 4 11388 #define MC_CMD_EVB_PORT_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_LEN 4 11389 11390 11391 /***********************************/ 11392 /* MC_CMD_DUMP_BUFTBL_ENTRIES 11393 * Dump buffer table entries, mainly for command client debug use. Dumps 11394 * absolute entries, and does not use chunk handles. All entries must be in 11395 * range, and used for q page mapping, Although the latter restriction may be 11396 * lifted in future. 11397 */ 11398 #define MC_CMD_DUMP_BUFTBL_ENTRIES 0xab 11399 #undef MC_CMD_0xab_PRIVILEGE_CTG 11400 11401 #define MC_CMD_0xab_PRIVILEGE_CTG SRIOV_CTG_INSECURE 11402 11403 /* MC_CMD_DUMP_BUFTBL_ENTRIES_IN msgrequest */ 11404 #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_LEN 8 11405 /* Index of the first buffer table entry. */ 11406 #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_FIRSTID_OFST 0 11407 #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_FIRSTID_LEN 4 11408 /* Number of buffer table entries to dump. */ 11409 #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_NUMENTRIES_OFST 4 11410 #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_NUMENTRIES_LEN 4 11411 11412 /* MC_CMD_DUMP_BUFTBL_ENTRIES_OUT msgresponse */ 11413 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LENMIN 12 11414 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LENMAX 252 11415 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LEN(num) (0+12*(num)) 11416 /* Raw buffer table entries, layed out as BUFTBL_ENTRY. */ 11417 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_OFST 0 11418 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_LEN 12 11419 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_MINNUM 1 11420 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_MAXNUM 21 11421 11422 11423 /***********************************/ 11424 /* MC_CMD_SET_RXDP_CONFIG 11425 * Set global RXDP configuration settings 11426 */ 11427 #define MC_CMD_SET_RXDP_CONFIG 0xc1 11428 #undef MC_CMD_0xc1_PRIVILEGE_CTG 11429 11430 #define MC_CMD_0xc1_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11431 11432 /* MC_CMD_SET_RXDP_CONFIG_IN msgrequest */ 11433 #define MC_CMD_SET_RXDP_CONFIG_IN_LEN 4 11434 #define MC_CMD_SET_RXDP_CONFIG_IN_DATA_OFST 0 11435 #define MC_CMD_SET_RXDP_CONFIG_IN_DATA_LEN 4 11436 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_LBN 0 11437 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_WIDTH 1 11438 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_LEN_LBN 1 11439 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_LEN_WIDTH 2 11440 /* enum: pad to 64 bytes */ 11441 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_64 0x0 11442 /* enum: pad to 128 bytes (Medford only) */ 11443 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_128 0x1 11444 /* enum: pad to 256 bytes (Medford only) */ 11445 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_256 0x2 11446 11447 /* MC_CMD_SET_RXDP_CONFIG_OUT msgresponse */ 11448 #define MC_CMD_SET_RXDP_CONFIG_OUT_LEN 0 11449 11450 11451 /***********************************/ 11452 /* MC_CMD_GET_RXDP_CONFIG 11453 * Get global RXDP configuration settings 11454 */ 11455 #define MC_CMD_GET_RXDP_CONFIG 0xc2 11456 #undef MC_CMD_0xc2_PRIVILEGE_CTG 11457 11458 #define MC_CMD_0xc2_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11459 11460 /* MC_CMD_GET_RXDP_CONFIG_IN msgrequest */ 11461 #define MC_CMD_GET_RXDP_CONFIG_IN_LEN 0 11462 11463 /* MC_CMD_GET_RXDP_CONFIG_OUT msgresponse */ 11464 #define MC_CMD_GET_RXDP_CONFIG_OUT_LEN 4 11465 #define MC_CMD_GET_RXDP_CONFIG_OUT_DATA_OFST 0 11466 #define MC_CMD_GET_RXDP_CONFIG_OUT_DATA_LEN 4 11467 #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_LBN 0 11468 #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_WIDTH 1 11469 #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_LEN_LBN 1 11470 #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_LEN_WIDTH 2 11471 /* Enum values, see field(s): */ 11472 /* MC_CMD_SET_RXDP_CONFIG/MC_CMD_SET_RXDP_CONFIG_IN/PAD_HOST_LEN */ 11473 11474 11475 /***********************************/ 11476 /* MC_CMD_GET_CLOCK 11477 * Return the system and PDCPU clock frequencies. 11478 */ 11479 #define MC_CMD_GET_CLOCK 0xac 11480 #undef MC_CMD_0xac_PRIVILEGE_CTG 11481 11482 #define MC_CMD_0xac_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11483 11484 /* MC_CMD_GET_CLOCK_IN msgrequest */ 11485 #define MC_CMD_GET_CLOCK_IN_LEN 0 11486 11487 /* MC_CMD_GET_CLOCK_OUT msgresponse */ 11488 #define MC_CMD_GET_CLOCK_OUT_LEN 8 11489 /* System frequency, MHz */ 11490 #define MC_CMD_GET_CLOCK_OUT_SYS_FREQ_OFST 0 11491 #define MC_CMD_GET_CLOCK_OUT_SYS_FREQ_LEN 4 11492 /* DPCPU frequency, MHz */ 11493 #define MC_CMD_GET_CLOCK_OUT_DPCPU_FREQ_OFST 4 11494 #define MC_CMD_GET_CLOCK_OUT_DPCPU_FREQ_LEN 4 11495 11496 11497 /***********************************/ 11498 /* MC_CMD_SET_CLOCK 11499 * Control the system and DPCPU clock frequencies. Changes are lost reboot. 11500 */ 11501 #define MC_CMD_SET_CLOCK 0xad 11502 #undef MC_CMD_0xad_PRIVILEGE_CTG 11503 11504 #define MC_CMD_0xad_PRIVILEGE_CTG SRIOV_CTG_INSECURE 11505 11506 /* MC_CMD_SET_CLOCK_IN msgrequest */ 11507 #define MC_CMD_SET_CLOCK_IN_LEN 28 11508 /* Requested frequency in MHz for system clock domain */ 11509 #define MC_CMD_SET_CLOCK_IN_SYS_FREQ_OFST 0 11510 #define MC_CMD_SET_CLOCK_IN_SYS_FREQ_LEN 4 11511 /* enum: Leave the system clock domain frequency unchanged */ 11512 #define MC_CMD_SET_CLOCK_IN_SYS_DOMAIN_DONT_CHANGE 0x0 11513 /* Requested frequency in MHz for inter-core clock domain */ 11514 #define MC_CMD_SET_CLOCK_IN_ICORE_FREQ_OFST 4 11515 #define MC_CMD_SET_CLOCK_IN_ICORE_FREQ_LEN 4 11516 /* enum: Leave the inter-core clock domain frequency unchanged */ 11517 #define MC_CMD_SET_CLOCK_IN_ICORE_DOMAIN_DONT_CHANGE 0x0 11518 /* Requested frequency in MHz for DPCPU clock domain */ 11519 #define MC_CMD_SET_CLOCK_IN_DPCPU_FREQ_OFST 8 11520 #define MC_CMD_SET_CLOCK_IN_DPCPU_FREQ_LEN 4 11521 /* enum: Leave the DPCPU clock domain frequency unchanged */ 11522 #define MC_CMD_SET_CLOCK_IN_DPCPU_DOMAIN_DONT_CHANGE 0x0 11523 /* Requested frequency in MHz for PCS clock domain */ 11524 #define MC_CMD_SET_CLOCK_IN_PCS_FREQ_OFST 12 11525 #define MC_CMD_SET_CLOCK_IN_PCS_FREQ_LEN 4 11526 /* enum: Leave the PCS clock domain frequency unchanged */ 11527 #define MC_CMD_SET_CLOCK_IN_PCS_DOMAIN_DONT_CHANGE 0x0 11528 /* Requested frequency in MHz for MC clock domain */ 11529 #define MC_CMD_SET_CLOCK_IN_MC_FREQ_OFST 16 11530 #define MC_CMD_SET_CLOCK_IN_MC_FREQ_LEN 4 11531 /* enum: Leave the MC clock domain frequency unchanged */ 11532 #define MC_CMD_SET_CLOCK_IN_MC_DOMAIN_DONT_CHANGE 0x0 11533 /* Requested frequency in MHz for rmon clock domain */ 11534 #define MC_CMD_SET_CLOCK_IN_RMON_FREQ_OFST 20 11535 #define MC_CMD_SET_CLOCK_IN_RMON_FREQ_LEN 4 11536 /* enum: Leave the rmon clock domain frequency unchanged */ 11537 #define MC_CMD_SET_CLOCK_IN_RMON_DOMAIN_DONT_CHANGE 0x0 11538 /* Requested frequency in MHz for vswitch clock domain */ 11539 #define MC_CMD_SET_CLOCK_IN_VSWITCH_FREQ_OFST 24 11540 #define MC_CMD_SET_CLOCK_IN_VSWITCH_FREQ_LEN 4 11541 /* enum: Leave the vswitch clock domain frequency unchanged */ 11542 #define MC_CMD_SET_CLOCK_IN_VSWITCH_DOMAIN_DONT_CHANGE 0x0 11543 11544 /* MC_CMD_SET_CLOCK_OUT msgresponse */ 11545 #define MC_CMD_SET_CLOCK_OUT_LEN 28 11546 /* Resulting system frequency in MHz */ 11547 #define MC_CMD_SET_CLOCK_OUT_SYS_FREQ_OFST 0 11548 #define MC_CMD_SET_CLOCK_OUT_SYS_FREQ_LEN 4 11549 /* enum: The system clock domain doesn't exist */ 11550 #define MC_CMD_SET_CLOCK_OUT_SYS_DOMAIN_UNSUPPORTED 0x0 11551 /* Resulting inter-core frequency in MHz */ 11552 #define MC_CMD_SET_CLOCK_OUT_ICORE_FREQ_OFST 4 11553 #define MC_CMD_SET_CLOCK_OUT_ICORE_FREQ_LEN 4 11554 /* enum: The inter-core clock domain doesn't exist / isn't used */ 11555 #define MC_CMD_SET_CLOCK_OUT_ICORE_DOMAIN_UNSUPPORTED 0x0 11556 /* Resulting DPCPU frequency in MHz */ 11557 #define MC_CMD_SET_CLOCK_OUT_DPCPU_FREQ_OFST 8 11558 #define MC_CMD_SET_CLOCK_OUT_DPCPU_FREQ_LEN 4 11559 /* enum: The dpcpu clock domain doesn't exist */ 11560 #define MC_CMD_SET_CLOCK_OUT_DPCPU_DOMAIN_UNSUPPORTED 0x0 11561 /* Resulting PCS frequency in MHz */ 11562 #define MC_CMD_SET_CLOCK_OUT_PCS_FREQ_OFST 12 11563 #define MC_CMD_SET_CLOCK_OUT_PCS_FREQ_LEN 4 11564 /* enum: The PCS clock domain doesn't exist / isn't controlled */ 11565 #define MC_CMD_SET_CLOCK_OUT_PCS_DOMAIN_UNSUPPORTED 0x0 11566 /* Resulting MC frequency in MHz */ 11567 #define MC_CMD_SET_CLOCK_OUT_MC_FREQ_OFST 16 11568 #define MC_CMD_SET_CLOCK_OUT_MC_FREQ_LEN 4 11569 /* enum: The MC clock domain doesn't exist / isn't controlled */ 11570 #define MC_CMD_SET_CLOCK_OUT_MC_DOMAIN_UNSUPPORTED 0x0 11571 /* Resulting rmon frequency in MHz */ 11572 #define MC_CMD_SET_CLOCK_OUT_RMON_FREQ_OFST 20 11573 #define MC_CMD_SET_CLOCK_OUT_RMON_FREQ_LEN 4 11574 /* enum: The rmon clock domain doesn't exist / isn't controlled */ 11575 #define MC_CMD_SET_CLOCK_OUT_RMON_DOMAIN_UNSUPPORTED 0x0 11576 /* Resulting vswitch frequency in MHz */ 11577 #define MC_CMD_SET_CLOCK_OUT_VSWITCH_FREQ_OFST 24 11578 #define MC_CMD_SET_CLOCK_OUT_VSWITCH_FREQ_LEN 4 11579 /* enum: The vswitch clock domain doesn't exist / isn't controlled */ 11580 #define MC_CMD_SET_CLOCK_OUT_VSWITCH_DOMAIN_UNSUPPORTED 0x0 11581 11582 11583 /***********************************/ 11584 /* MC_CMD_DPCPU_RPC 11585 * Send an arbitrary DPCPU message. 11586 */ 11587 #define MC_CMD_DPCPU_RPC 0xae 11588 #undef MC_CMD_0xae_PRIVILEGE_CTG 11589 11590 #define MC_CMD_0xae_PRIVILEGE_CTG SRIOV_CTG_INSECURE 11591 11592 /* MC_CMD_DPCPU_RPC_IN msgrequest */ 11593 #define MC_CMD_DPCPU_RPC_IN_LEN 36 11594 #define MC_CMD_DPCPU_RPC_IN_CPU_OFST 0 11595 #define MC_CMD_DPCPU_RPC_IN_CPU_LEN 4 11596 /* enum: RxDPCPU0 */ 11597 #define MC_CMD_DPCPU_RPC_IN_DPCPU_RX0 0x0 11598 /* enum: TxDPCPU0 */ 11599 #define MC_CMD_DPCPU_RPC_IN_DPCPU_TX0 0x1 11600 /* enum: TxDPCPU1 */ 11601 #define MC_CMD_DPCPU_RPC_IN_DPCPU_TX1 0x2 11602 /* enum: RxDPCPU1 (Medford only) */ 11603 #define MC_CMD_DPCPU_RPC_IN_DPCPU_RX1 0x3 11604 /* enum: RxDPCPU (will be for the calling function; for now, just an alias of 11605 * DPCPU_RX0) 11606 */ 11607 #define MC_CMD_DPCPU_RPC_IN_DPCPU_RX 0x80 11608 /* enum: TxDPCPU (will be for the calling function; for now, just an alias of 11609 * DPCPU_TX0) 11610 */ 11611 #define MC_CMD_DPCPU_RPC_IN_DPCPU_TX 0x81 11612 /* First 8 bits [39:32] of DATA are consumed by MC-DPCPU protocol and must be 11613 * initialised to zero 11614 */ 11615 #define MC_CMD_DPCPU_RPC_IN_DATA_OFST 4 11616 #define MC_CMD_DPCPU_RPC_IN_DATA_LEN 32 11617 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_CMDNUM_LBN 8 11618 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_CMDNUM_WIDTH 8 11619 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_READ 0x6 /* enum */ 11620 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_WRITE 0x7 /* enum */ 11621 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_SELF_TEST 0xc /* enum */ 11622 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_CSR_ACCESS 0xe /* enum */ 11623 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_READ 0x46 /* enum */ 11624 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_WRITE 0x47 /* enum */ 11625 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_SELF_TEST 0x4a /* enum */ 11626 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_CSR_ACCESS 0x4c /* enum */ 11627 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_SET_MC_REPLAY_CNTXT 0x4d /* enum */ 11628 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_OBJID_LBN 16 11629 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_OBJID_WIDTH 16 11630 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_ADDR_LBN 16 11631 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_ADDR_WIDTH 16 11632 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_COUNT_LBN 48 11633 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_COUNT_WIDTH 16 11634 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_INFO_LBN 16 11635 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_INFO_WIDTH 240 11636 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_LBN 16 11637 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_WIDTH 16 11638 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_STOP_RETURN_RESULT 0x0 /* enum */ 11639 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_READ 0x1 /* enum */ 11640 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_WRITE 0x2 /* enum */ 11641 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_WRITE_READ 0x3 /* enum */ 11642 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_PIPELINED_READ 0x4 /* enum */ 11643 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_START_DELAY_LBN 48 11644 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_START_DELAY_WIDTH 16 11645 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_RPT_COUNT_LBN 64 11646 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_RPT_COUNT_WIDTH 16 11647 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_GAP_DELAY_LBN 80 11648 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_GAP_DELAY_WIDTH 16 11649 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_LBN 16 11650 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_WIDTH 16 11651 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_CUT_THROUGH 0x1 /* enum */ 11652 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_STORE_FORWARD 0x2 /* enum */ 11653 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_STORE_FORWARD_FIRST 0x3 /* enum */ 11654 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_CNTXT_LBN 64 11655 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_CNTXT_WIDTH 16 11656 #define MC_CMD_DPCPU_RPC_IN_WDATA_OFST 12 11657 #define MC_CMD_DPCPU_RPC_IN_WDATA_LEN 24 11658 /* Register data to write. Only valid in write/write-read. */ 11659 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_DATA_OFST 16 11660 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_DATA_LEN 4 11661 /* Register address. */ 11662 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_ADDRESS_OFST 20 11663 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_ADDRESS_LEN 4 11664 11665 /* MC_CMD_DPCPU_RPC_OUT msgresponse */ 11666 #define MC_CMD_DPCPU_RPC_OUT_LEN 36 11667 #define MC_CMD_DPCPU_RPC_OUT_RC_OFST 0 11668 #define MC_CMD_DPCPU_RPC_OUT_RC_LEN 4 11669 /* DATA */ 11670 #define MC_CMD_DPCPU_RPC_OUT_DATA_OFST 4 11671 #define MC_CMD_DPCPU_RPC_OUT_DATA_LEN 32 11672 #define MC_CMD_DPCPU_RPC_OUT_HDR_CMD_RESP_ERRCODE_LBN 32 11673 #define MC_CMD_DPCPU_RPC_OUT_HDR_CMD_RESP_ERRCODE_WIDTH 16 11674 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_COUNT_LBN 48 11675 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_COUNT_WIDTH 16 11676 #define MC_CMD_DPCPU_RPC_OUT_RDATA_OFST 12 11677 #define MC_CMD_DPCPU_RPC_OUT_RDATA_LEN 24 11678 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_1_OFST 12 11679 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_1_LEN 4 11680 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_2_OFST 16 11681 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_2_LEN 4 11682 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_3_OFST 20 11683 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_3_LEN 4 11684 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_4_OFST 24 11685 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_4_LEN 4 11686 11687 11688 /***********************************/ 11689 /* MC_CMD_TRIGGER_INTERRUPT 11690 * Trigger an interrupt by prodding the BIU. 11691 */ 11692 #define MC_CMD_TRIGGER_INTERRUPT 0xe3 11693 #undef MC_CMD_0xe3_PRIVILEGE_CTG 11694 11695 #define MC_CMD_0xe3_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11696 11697 /* MC_CMD_TRIGGER_INTERRUPT_IN msgrequest */ 11698 #define MC_CMD_TRIGGER_INTERRUPT_IN_LEN 4 11699 /* Interrupt level relative to base for function. */ 11700 #define MC_CMD_TRIGGER_INTERRUPT_IN_INTR_LEVEL_OFST 0 11701 #define MC_CMD_TRIGGER_INTERRUPT_IN_INTR_LEVEL_LEN 4 11702 11703 /* MC_CMD_TRIGGER_INTERRUPT_OUT msgresponse */ 11704 #define MC_CMD_TRIGGER_INTERRUPT_OUT_LEN 0 11705 11706 11707 /***********************************/ 11708 /* MC_CMD_SHMBOOT_OP 11709 * Special operations to support (for now) shmboot. 11710 */ 11711 #define MC_CMD_SHMBOOT_OP 0xe6 11712 #undef MC_CMD_0xe6_PRIVILEGE_CTG 11713 11714 #define MC_CMD_0xe6_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11715 11716 /* MC_CMD_SHMBOOT_OP_IN msgrequest */ 11717 #define MC_CMD_SHMBOOT_OP_IN_LEN 4 11718 /* Identifies the operation to perform */ 11719 #define MC_CMD_SHMBOOT_OP_IN_SHMBOOT_OP_OFST 0 11720 #define MC_CMD_SHMBOOT_OP_IN_SHMBOOT_OP_LEN 4 11721 /* enum: Copy slave_data section to the slave core. (Greenport only) */ 11722 #define MC_CMD_SHMBOOT_OP_IN_PUSH_SLAVE_DATA 0x0 11723 11724 /* MC_CMD_SHMBOOT_OP_OUT msgresponse */ 11725 #define MC_CMD_SHMBOOT_OP_OUT_LEN 0 11726 11727 11728 /***********************************/ 11729 /* MC_CMD_CAP_BLK_READ 11730 * Read multiple 64bit words from capture block memory 11731 */ 11732 #define MC_CMD_CAP_BLK_READ 0xe7 11733 #undef MC_CMD_0xe7_PRIVILEGE_CTG 11734 11735 #define MC_CMD_0xe7_PRIVILEGE_CTG SRIOV_CTG_INSECURE 11736 11737 /* MC_CMD_CAP_BLK_READ_IN msgrequest */ 11738 #define MC_CMD_CAP_BLK_READ_IN_LEN 12 11739 #define MC_CMD_CAP_BLK_READ_IN_CAP_REG_OFST 0 11740 #define MC_CMD_CAP_BLK_READ_IN_CAP_REG_LEN 4 11741 #define MC_CMD_CAP_BLK_READ_IN_ADDR_OFST 4 11742 #define MC_CMD_CAP_BLK_READ_IN_ADDR_LEN 4 11743 #define MC_CMD_CAP_BLK_READ_IN_COUNT_OFST 8 11744 #define MC_CMD_CAP_BLK_READ_IN_COUNT_LEN 4 11745 11746 /* MC_CMD_CAP_BLK_READ_OUT msgresponse */ 11747 #define MC_CMD_CAP_BLK_READ_OUT_LENMIN 8 11748 #define MC_CMD_CAP_BLK_READ_OUT_LENMAX 248 11749 #define MC_CMD_CAP_BLK_READ_OUT_LEN(num) (0+8*(num)) 11750 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_OFST 0 11751 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LEN 8 11752 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LO_OFST 0 11753 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_HI_OFST 4 11754 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_MINNUM 1 11755 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_MAXNUM 31 11756 11757 11758 /***********************************/ 11759 /* MC_CMD_DUMP_DO 11760 * Take a dump of the DUT state 11761 */ 11762 #define MC_CMD_DUMP_DO 0xe8 11763 #undef MC_CMD_0xe8_PRIVILEGE_CTG 11764 11765 #define MC_CMD_0xe8_PRIVILEGE_CTG SRIOV_CTG_INSECURE 11766 11767 /* MC_CMD_DUMP_DO_IN msgrequest */ 11768 #define MC_CMD_DUMP_DO_IN_LEN 52 11769 #define MC_CMD_DUMP_DO_IN_PADDING_OFST 0 11770 #define MC_CMD_DUMP_DO_IN_PADDING_LEN 4 11771 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_OFST 4 11772 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_LEN 4 11773 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM 0x0 /* enum */ 11774 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_DEFAULT 0x1 /* enum */ 11775 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_TYPE_OFST 8 11776 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_TYPE_LEN 4 11777 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_NVRAM 0x1 /* enum */ 11778 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_HOST_MEMORY 0x2 /* enum */ 11779 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_HOST_MEMORY_MLI 0x3 /* enum */ 11780 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_UART 0x4 /* enum */ 11781 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 12 11782 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_LEN 4 11783 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_OFST 16 11784 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_LEN 4 11785 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 12 11786 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_LEN 4 11787 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 16 11788 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_LEN 4 11789 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 12 11790 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_LEN 4 11791 #define MC_CMD_DUMP_DO_IN_HOST_MEMORY_MLI_PAGE_SIZE 0x1000 /* enum */ 11792 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 16 11793 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_LEN 4 11794 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 20 11795 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_LEN 4 11796 #define MC_CMD_DUMP_DO_IN_HOST_MEMORY_MLI_MAX_DEPTH 0x2 /* enum */ 11797 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_OFST 12 11798 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_LEN 4 11799 /* enum: The uart port this command was received over (if using a uart 11800 * transport) 11801 */ 11802 #define MC_CMD_DUMP_DO_IN_UART_PORT_SRC 0xff 11803 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_SIZE_OFST 24 11804 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_SIZE_LEN 4 11805 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_OFST 28 11806 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_LEN 4 11807 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM 0x0 /* enum */ 11808 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_NVRAM_DUMP_PARTITION 0x1 /* enum */ 11809 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_TYPE_OFST 32 11810 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_TYPE_LEN 4 11811 /* Enum values, see field(s): */ 11812 /* MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */ 11813 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 36 11814 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_LEN 4 11815 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_OFST 40 11816 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_LEN 4 11817 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 36 11818 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_LEN 4 11819 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 40 11820 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_LEN 4 11821 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 36 11822 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_LEN 4 11823 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 40 11824 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_LEN 4 11825 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 44 11826 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_LEN 4 11827 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_UART_PORT_OFST 36 11828 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_UART_PORT_LEN 4 11829 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_SIZE_OFST 48 11830 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_SIZE_LEN 4 11831 11832 /* MC_CMD_DUMP_DO_OUT msgresponse */ 11833 #define MC_CMD_DUMP_DO_OUT_LEN 4 11834 #define MC_CMD_DUMP_DO_OUT_DUMPFILE_SIZE_OFST 0 11835 #define MC_CMD_DUMP_DO_OUT_DUMPFILE_SIZE_LEN 4 11836 11837 11838 /***********************************/ 11839 /* MC_CMD_DUMP_CONFIGURE_UNSOLICITED 11840 * Configure unsolicited dumps 11841 */ 11842 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED 0xe9 11843 #undef MC_CMD_0xe9_PRIVILEGE_CTG 11844 11845 #define MC_CMD_0xe9_PRIVILEGE_CTG SRIOV_CTG_INSECURE 11846 11847 /* MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN msgrequest */ 11848 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_LEN 52 11849 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_ENABLE_OFST 0 11850 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_ENABLE_LEN 4 11851 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_OFST 4 11852 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_LEN 4 11853 /* Enum values, see field(s): */ 11854 /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC */ 11855 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_TYPE_OFST 8 11856 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_TYPE_LEN 4 11857 /* Enum values, see field(s): */ 11858 /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */ 11859 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 12 11860 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_LEN 4 11861 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_OFST 16 11862 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_LEN 4 11863 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 12 11864 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_LEN 4 11865 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 16 11866 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_LEN 4 11867 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 12 11868 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_LEN 4 11869 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 16 11870 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_LEN 4 11871 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 20 11872 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_LEN 4 11873 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_OFST 12 11874 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_LEN 4 11875 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_SIZE_OFST 24 11876 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_SIZE_LEN 4 11877 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_OFST 28 11878 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_LEN 4 11879 /* Enum values, see field(s): */ 11880 /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPFILE_DST */ 11881 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_TYPE_OFST 32 11882 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_TYPE_LEN 4 11883 /* Enum values, see field(s): */ 11884 /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */ 11885 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 36 11886 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_LEN 4 11887 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_OFST 40 11888 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_LEN 4 11889 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 36 11890 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_LEN 4 11891 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 40 11892 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_LEN 4 11893 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 36 11894 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_LEN 4 11895 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 40 11896 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_LEN 4 11897 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 44 11898 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_LEN 4 11899 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_UART_PORT_OFST 36 11900 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_UART_PORT_LEN 4 11901 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_SIZE_OFST 48 11902 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_SIZE_LEN 4 11903 11904 11905 /***********************************/ 11906 /* MC_CMD_SET_PSU 11907 * Adjusts power supply parameters. This is a warranty-voiding operation. 11908 * Returns: ENOENT if the parameter or rail specified does not exist, EINVAL if 11909 * the parameter is out of range. 11910 */ 11911 #define MC_CMD_SET_PSU 0xea 11912 #undef MC_CMD_0xea_PRIVILEGE_CTG 11913 11914 #define MC_CMD_0xea_PRIVILEGE_CTG SRIOV_CTG_INSECURE 11915 11916 /* MC_CMD_SET_PSU_IN msgrequest */ 11917 #define MC_CMD_SET_PSU_IN_LEN 12 11918 #define MC_CMD_SET_PSU_IN_PARAM_OFST 0 11919 #define MC_CMD_SET_PSU_IN_PARAM_LEN 4 11920 #define MC_CMD_SET_PSU_IN_PARAM_SUPPLY_VOLTAGE 0x0 /* enum */ 11921 #define MC_CMD_SET_PSU_IN_RAIL_OFST 4 11922 #define MC_CMD_SET_PSU_IN_RAIL_LEN 4 11923 #define MC_CMD_SET_PSU_IN_RAIL_0V9 0x0 /* enum */ 11924 #define MC_CMD_SET_PSU_IN_RAIL_1V2 0x1 /* enum */ 11925 /* desired value, eg voltage in mV */ 11926 #define MC_CMD_SET_PSU_IN_VALUE_OFST 8 11927 #define MC_CMD_SET_PSU_IN_VALUE_LEN 4 11928 11929 /* MC_CMD_SET_PSU_OUT msgresponse */ 11930 #define MC_CMD_SET_PSU_OUT_LEN 0 11931 11932 11933 /***********************************/ 11934 /* MC_CMD_GET_FUNCTION_INFO 11935 * Get function information. PF and VF number. 11936 */ 11937 #define MC_CMD_GET_FUNCTION_INFO 0xec 11938 #undef MC_CMD_0xec_PRIVILEGE_CTG 11939 11940 #define MC_CMD_0xec_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11941 11942 /* MC_CMD_GET_FUNCTION_INFO_IN msgrequest */ 11943 #define MC_CMD_GET_FUNCTION_INFO_IN_LEN 0 11944 11945 /* MC_CMD_GET_FUNCTION_INFO_OUT msgresponse */ 11946 #define MC_CMD_GET_FUNCTION_INFO_OUT_LEN 8 11947 #define MC_CMD_GET_FUNCTION_INFO_OUT_PF_OFST 0 11948 #define MC_CMD_GET_FUNCTION_INFO_OUT_PF_LEN 4 11949 #define MC_CMD_GET_FUNCTION_INFO_OUT_VF_OFST 4 11950 #define MC_CMD_GET_FUNCTION_INFO_OUT_VF_LEN 4 11951 11952 11953 /***********************************/ 11954 /* MC_CMD_ENABLE_OFFLINE_BIST 11955 * Enters offline BIST mode. All queues are torn down, chip enters quiescent 11956 * mode, calling function gets exclusive MCDI ownership. The only way out is 11957 * reboot. 11958 */ 11959 #define MC_CMD_ENABLE_OFFLINE_BIST 0xed 11960 #undef MC_CMD_0xed_PRIVILEGE_CTG 11961 11962 #define MC_CMD_0xed_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11963 11964 /* MC_CMD_ENABLE_OFFLINE_BIST_IN msgrequest */ 11965 #define MC_CMD_ENABLE_OFFLINE_BIST_IN_LEN 0 11966 11967 /* MC_CMD_ENABLE_OFFLINE_BIST_OUT msgresponse */ 11968 #define MC_CMD_ENABLE_OFFLINE_BIST_OUT_LEN 0 11969 11970 11971 /***********************************/ 11972 /* MC_CMD_UART_SEND_DATA 11973 * Send checksummed[sic] block of data over the uart. Response is a placeholder 11974 * should we wish to make this reliable; currently requests are fire-and- 11975 * forget. 11976 */ 11977 #define MC_CMD_UART_SEND_DATA 0xee 11978 #undef MC_CMD_0xee_PRIVILEGE_CTG 11979 11980 #define MC_CMD_0xee_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11981 11982 /* MC_CMD_UART_SEND_DATA_OUT msgrequest */ 11983 #define MC_CMD_UART_SEND_DATA_OUT_LENMIN 16 11984 #define MC_CMD_UART_SEND_DATA_OUT_LENMAX 252 11985 #define MC_CMD_UART_SEND_DATA_OUT_LEN(num) (16+1*(num)) 11986 /* CRC32 over OFFSET, LENGTH, RESERVED, DATA */ 11987 #define MC_CMD_UART_SEND_DATA_OUT_CHECKSUM_OFST 0 11988 #define MC_CMD_UART_SEND_DATA_OUT_CHECKSUM_LEN 4 11989 /* Offset at which to write the data */ 11990 #define MC_CMD_UART_SEND_DATA_OUT_OFFSET_OFST 4 11991 #define MC_CMD_UART_SEND_DATA_OUT_OFFSET_LEN 4 11992 /* Length of data */ 11993 #define MC_CMD_UART_SEND_DATA_OUT_LENGTH_OFST 8 11994 #define MC_CMD_UART_SEND_DATA_OUT_LENGTH_LEN 4 11995 /* Reserved for future use */ 11996 #define MC_CMD_UART_SEND_DATA_OUT_RESERVED_OFST 12 11997 #define MC_CMD_UART_SEND_DATA_OUT_RESERVED_LEN 4 11998 #define MC_CMD_UART_SEND_DATA_OUT_DATA_OFST 16 11999 #define MC_CMD_UART_SEND_DATA_OUT_DATA_LEN 1 12000 #define MC_CMD_UART_SEND_DATA_OUT_DATA_MINNUM 0 12001 #define MC_CMD_UART_SEND_DATA_OUT_DATA_MAXNUM 236 12002 12003 /* MC_CMD_UART_SEND_DATA_IN msgresponse */ 12004 #define MC_CMD_UART_SEND_DATA_IN_LEN 0 12005 12006 12007 /***********************************/ 12008 /* MC_CMD_UART_RECV_DATA 12009 * Request checksummed[sic] block of data over the uart. Only a placeholder, 12010 * subject to change and not currently implemented. 12011 */ 12012 #define MC_CMD_UART_RECV_DATA 0xef 12013 #undef MC_CMD_0xef_PRIVILEGE_CTG 12014 12015 #define MC_CMD_0xef_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12016 12017 /* MC_CMD_UART_RECV_DATA_OUT msgrequest */ 12018 #define MC_CMD_UART_RECV_DATA_OUT_LEN 16 12019 /* CRC32 over OFFSET, LENGTH, RESERVED */ 12020 #define MC_CMD_UART_RECV_DATA_OUT_CHECKSUM_OFST 0 12021 #define MC_CMD_UART_RECV_DATA_OUT_CHECKSUM_LEN 4 12022 /* Offset from which to read the data */ 12023 #define MC_CMD_UART_RECV_DATA_OUT_OFFSET_OFST 4 12024 #define MC_CMD_UART_RECV_DATA_OUT_OFFSET_LEN 4 12025 /* Length of data */ 12026 #define MC_CMD_UART_RECV_DATA_OUT_LENGTH_OFST 8 12027 #define MC_CMD_UART_RECV_DATA_OUT_LENGTH_LEN 4 12028 /* Reserved for future use */ 12029 #define MC_CMD_UART_RECV_DATA_OUT_RESERVED_OFST 12 12030 #define MC_CMD_UART_RECV_DATA_OUT_RESERVED_LEN 4 12031 12032 /* MC_CMD_UART_RECV_DATA_IN msgresponse */ 12033 #define MC_CMD_UART_RECV_DATA_IN_LENMIN 16 12034 #define MC_CMD_UART_RECV_DATA_IN_LENMAX 252 12035 #define MC_CMD_UART_RECV_DATA_IN_LEN(num) (16+1*(num)) 12036 /* CRC32 over RESERVED1, RESERVED2, RESERVED3, DATA */ 12037 #define MC_CMD_UART_RECV_DATA_IN_CHECKSUM_OFST 0 12038 #define MC_CMD_UART_RECV_DATA_IN_CHECKSUM_LEN 4 12039 /* Offset at which to write the data */ 12040 #define MC_CMD_UART_RECV_DATA_IN_RESERVED1_OFST 4 12041 #define MC_CMD_UART_RECV_DATA_IN_RESERVED1_LEN 4 12042 /* Length of data */ 12043 #define MC_CMD_UART_RECV_DATA_IN_RESERVED2_OFST 8 12044 #define MC_CMD_UART_RECV_DATA_IN_RESERVED2_LEN 4 12045 /* Reserved for future use */ 12046 #define MC_CMD_UART_RECV_DATA_IN_RESERVED3_OFST 12 12047 #define MC_CMD_UART_RECV_DATA_IN_RESERVED3_LEN 4 12048 #define MC_CMD_UART_RECV_DATA_IN_DATA_OFST 16 12049 #define MC_CMD_UART_RECV_DATA_IN_DATA_LEN 1 12050 #define MC_CMD_UART_RECV_DATA_IN_DATA_MINNUM 0 12051 #define MC_CMD_UART_RECV_DATA_IN_DATA_MAXNUM 236 12052 12053 12054 /***********************************/ 12055 /* MC_CMD_READ_FUSES 12056 * Read data programmed into the device One-Time-Programmable (OTP) Fuses 12057 */ 12058 #define MC_CMD_READ_FUSES 0xf0 12059 #undef MC_CMD_0xf0_PRIVILEGE_CTG 12060 12061 #define MC_CMD_0xf0_PRIVILEGE_CTG SRIOV_CTG_INSECURE 12062 12063 /* MC_CMD_READ_FUSES_IN msgrequest */ 12064 #define MC_CMD_READ_FUSES_IN_LEN 8 12065 /* Offset in OTP to read */ 12066 #define MC_CMD_READ_FUSES_IN_OFFSET_OFST 0 12067 #define MC_CMD_READ_FUSES_IN_OFFSET_LEN 4 12068 /* Length of data to read in bytes */ 12069 #define MC_CMD_READ_FUSES_IN_LENGTH_OFST 4 12070 #define MC_CMD_READ_FUSES_IN_LENGTH_LEN 4 12071 12072 /* MC_CMD_READ_FUSES_OUT msgresponse */ 12073 #define MC_CMD_READ_FUSES_OUT_LENMIN 4 12074 #define MC_CMD_READ_FUSES_OUT_LENMAX 252 12075 #define MC_CMD_READ_FUSES_OUT_LEN(num) (4+1*(num)) 12076 /* Length of returned OTP data in bytes */ 12077 #define MC_CMD_READ_FUSES_OUT_LENGTH_OFST 0 12078 #define MC_CMD_READ_FUSES_OUT_LENGTH_LEN 4 12079 /* Returned data */ 12080 #define MC_CMD_READ_FUSES_OUT_DATA_OFST 4 12081 #define MC_CMD_READ_FUSES_OUT_DATA_LEN 1 12082 #define MC_CMD_READ_FUSES_OUT_DATA_MINNUM 0 12083 #define MC_CMD_READ_FUSES_OUT_DATA_MAXNUM 248 12084 12085 12086 /***********************************/ 12087 /* MC_CMD_KR_TUNE 12088 * Get or set KR Serdes RXEQ and TX Driver settings 12089 */ 12090 #define MC_CMD_KR_TUNE 0xf1 12091 #undef MC_CMD_0xf1_PRIVILEGE_CTG 12092 12093 #define MC_CMD_0xf1_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12094 12095 /* MC_CMD_KR_TUNE_IN msgrequest */ 12096 #define MC_CMD_KR_TUNE_IN_LENMIN 4 12097 #define MC_CMD_KR_TUNE_IN_LENMAX 252 12098 #define MC_CMD_KR_TUNE_IN_LEN(num) (4+4*(num)) 12099 /* Requested operation */ 12100 #define MC_CMD_KR_TUNE_IN_KR_TUNE_OP_OFST 0 12101 #define MC_CMD_KR_TUNE_IN_KR_TUNE_OP_LEN 1 12102 /* enum: Get current RXEQ settings */ 12103 #define MC_CMD_KR_TUNE_IN_RXEQ_GET 0x0 12104 /* enum: Override RXEQ settings */ 12105 #define MC_CMD_KR_TUNE_IN_RXEQ_SET 0x1 12106 /* enum: Get current TX Driver settings */ 12107 #define MC_CMD_KR_TUNE_IN_TXEQ_GET 0x2 12108 /* enum: Override TX Driver settings */ 12109 #define MC_CMD_KR_TUNE_IN_TXEQ_SET 0x3 12110 /* enum: Force KR Serdes reset / recalibration */ 12111 #define MC_CMD_KR_TUNE_IN_RECAL 0x4 12112 /* enum: Start KR Serdes Eye diagram plot on a given lane. Lane must have valid 12113 * signal. 12114 */ 12115 #define MC_CMD_KR_TUNE_IN_START_EYE_PLOT 0x5 12116 /* enum: Poll KR Serdes Eye diagram plot. Returns one row of BER data. The 12117 * caller should call this command repeatedly after starting eye plot, until no 12118 * more data is returned. 12119 */ 12120 #define MC_CMD_KR_TUNE_IN_POLL_EYE_PLOT 0x6 12121 /* enum: Read Figure Of Merit (eye quality, higher is better). */ 12122 #define MC_CMD_KR_TUNE_IN_READ_FOM 0x7 12123 /* Align the arguments to 32 bits */ 12124 #define MC_CMD_KR_TUNE_IN_KR_TUNE_RSVD_OFST 1 12125 #define MC_CMD_KR_TUNE_IN_KR_TUNE_RSVD_LEN 3 12126 /* Arguments specific to the operation */ 12127 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_OFST 4 12128 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_LEN 4 12129 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_MINNUM 0 12130 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_MAXNUM 62 12131 12132 /* MC_CMD_KR_TUNE_OUT msgresponse */ 12133 #define MC_CMD_KR_TUNE_OUT_LEN 0 12134 12135 /* MC_CMD_KR_TUNE_RXEQ_GET_IN msgrequest */ 12136 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_LEN 4 12137 /* Requested operation */ 12138 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_OP_OFST 0 12139 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_OP_LEN 1 12140 /* Align the arguments to 32 bits */ 12141 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_RSVD_OFST 1 12142 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_RSVD_LEN 3 12143 12144 /* MC_CMD_KR_TUNE_RXEQ_GET_OUT msgresponse */ 12145 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LENMIN 4 12146 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LENMAX 252 12147 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LEN(num) (0+4*(num)) 12148 /* RXEQ Parameter */ 12149 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_OFST 0 12150 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LEN 4 12151 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_MINNUM 1 12152 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_MAXNUM 63 12153 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_LBN 0 12154 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_WIDTH 8 12155 /* enum: Attenuation (0-15, Huntington) */ 12156 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_ATT 0x0 12157 /* enum: CTLE Boost (0-15, Huntington) */ 12158 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_BOOST 0x1 12159 /* enum: Edge DFE Tap1 (Huntington - 0 - max negative, 64 - zero, 127 - max 12160 * positive, Medford - 0-31) 12161 */ 12162 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP1 0x2 12163 /* enum: Edge DFE Tap2 (Huntington - 0 - max negative, 32 - zero, 63 - max 12164 * positive, Medford - 0-31) 12165 */ 12166 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP2 0x3 12167 /* enum: Edge DFE Tap3 (Huntington - 0 - max negative, 32 - zero, 63 - max 12168 * positive, Medford - 0-16) 12169 */ 12170 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP3 0x4 12171 /* enum: Edge DFE Tap4 (Huntington - 0 - max negative, 32 - zero, 63 - max 12172 * positive, Medford - 0-16) 12173 */ 12174 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP4 0x5 12175 /* enum: Edge DFE Tap5 (Huntington - 0 - max negative, 32 - zero, 63 - max 12176 * positive, Medford - 0-16) 12177 */ 12178 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP5 0x6 12179 /* enum: Edge DFE DLEV (0-128 for Medford) */ 12180 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_DLEV 0x7 12181 /* enum: Variable Gain Amplifier (0-15, Medford) */ 12182 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_VGA 0x8 12183 /* enum: CTLE EQ Capacitor (0-15, Medford) */ 12184 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_EQC 0x9 12185 /* enum: CTLE EQ Resistor (0-7, Medford) */ 12186 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_EQRES 0xa 12187 /* enum: CTLE gain (0-31, Medford2) */ 12188 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_GAIN 0xb 12189 /* enum: CTLE pole (0-31, Medford2) */ 12190 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_POLE 0xc 12191 /* enum: CTLE peaking (0-31, Medford2) */ 12192 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_PEAK 0xd 12193 /* enum: DFE Tap1 - even path (Medford2 - 0-63, sign-magnitude (-31 - +31)) */ 12194 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP1_EVEN 0xe 12195 /* enum: DFE Tap1 - odd path (Medford2 - 0-63, sign-magnitude (-31 - +31)) */ 12196 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP1_ODD 0xf 12197 /* enum: DFE Tap2 (Medford2 - 0-63, sign-magnitude (-31 - +31)) */ 12198 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP2 0x10 12199 /* enum: DFE Tap3 (Medford2 - 0-63, sign-magnitude (-31 - +31)) */ 12200 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP3 0x11 12201 /* enum: DFE Tap4 (Medford2 - 0-63, sign-magnitude (-31 - +31)) */ 12202 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP4 0x12 12203 /* enum: DFE Tap5 (Medford2 - 0-63, sign-magnitude (-31 - +31)) */ 12204 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP5 0x13 12205 /* enum: DFE Tap6 (Medford2 - 0-63, sign-magnitude (-31 - +31)) */ 12206 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP6 0x14 12207 /* enum: DFE Tap7 (Medford2 - 0-63, sign-magnitude (-31 - +31)) */ 12208 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP7 0x15 12209 /* enum: DFE Tap8 (Medford2 - 0-63, sign-magnitude (-31 - +31)) */ 12210 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP8 0x16 12211 /* enum: DFE Tap9 (Medford2 - 0-63, sign-magnitude (-31 - +31)) */ 12212 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP9 0x17 12213 /* enum: DFE Tap10 (Medford2 - 0-63, sign-magnitude (-31 - +31)) */ 12214 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP10 0x18 12215 /* enum: DFE Tap11 (Medford2 - 0-63, sign-magnitude (-31 - +31)) */ 12216 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP11 0x19 12217 /* enum: DFE Tap12 (Medford2 - 0-63, sign-magnitude (-31 - +31)) */ 12218 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP12 0x1a 12219 /* enum: I/Q clk offset (Medford2 - 0-5, sign-magnitude (-5 - +5)) */ 12220 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_IQ_OFF 0x1b 12221 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_LBN 8 12222 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_WIDTH 3 12223 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */ 12224 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_1 0x1 /* enum */ 12225 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_2 0x2 /* enum */ 12226 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_3 0x3 /* enum */ 12227 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_ALL 0x4 /* enum */ 12228 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_LBN 11 12229 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_WIDTH 1 12230 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_RESERVED_LBN 12 12231 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_RESERVED_WIDTH 4 12232 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_INITIAL_LBN 16 12233 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_INITIAL_WIDTH 8 12234 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_LBN 24 12235 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8 12236 12237 /* MC_CMD_KR_TUNE_RXEQ_SET_IN msgrequest */ 12238 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_LENMIN 8 12239 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_LENMAX 252 12240 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_LEN(num) (4+4*(num)) 12241 /* Requested operation */ 12242 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_OP_OFST 0 12243 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_OP_LEN 1 12244 /* Align the arguments to 32 bits */ 12245 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_RSVD_OFST 1 12246 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_RSVD_LEN 3 12247 /* RXEQ Parameter */ 12248 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_OFST 4 12249 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LEN 4 12250 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_MINNUM 1 12251 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_MAXNUM 62 12252 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_ID_LBN 0 12253 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_ID_WIDTH 8 12254 /* Enum values, see field(s): */ 12255 /* MC_CMD_KR_TUNE_RXEQ_GET_OUT/PARAM_ID */ 12256 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LANE_LBN 8 12257 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LANE_WIDTH 3 12258 /* Enum values, see field(s): */ 12259 /* MC_CMD_KR_TUNE_RXEQ_GET_OUT/PARAM_LANE */ 12260 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_LBN 11 12261 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_WIDTH 1 12262 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED_LBN 12 12263 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED_WIDTH 4 12264 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_INITIAL_LBN 16 12265 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_INITIAL_WIDTH 8 12266 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED2_LBN 24 12267 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED2_WIDTH 8 12268 12269 /* MC_CMD_KR_TUNE_RXEQ_SET_OUT msgresponse */ 12270 #define MC_CMD_KR_TUNE_RXEQ_SET_OUT_LEN 0 12271 12272 /* MC_CMD_KR_TUNE_TXEQ_GET_IN msgrequest */ 12273 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_LEN 4 12274 /* Requested operation */ 12275 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_OP_OFST 0 12276 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_OP_LEN 1 12277 /* Align the arguments to 32 bits */ 12278 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_RSVD_OFST 1 12279 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_RSVD_LEN 3 12280 12281 /* MC_CMD_KR_TUNE_TXEQ_GET_OUT msgresponse */ 12282 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LENMIN 4 12283 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LENMAX 252 12284 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LEN(num) (0+4*(num)) 12285 /* TXEQ Parameter */ 12286 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_OFST 0 12287 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LEN 4 12288 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_MINNUM 1 12289 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_MAXNUM 63 12290 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_LBN 0 12291 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_WIDTH 8 12292 /* enum: TX Amplitude (Huntington, Medford, Medford2) */ 12293 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV 0x0 12294 /* enum: De-Emphasis Tap1 Magnitude (0-7) (Huntington) */ 12295 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_MODE 0x1 12296 /* enum: De-Emphasis Tap1 Fine */ 12297 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_DTLEV 0x2 12298 /* enum: De-Emphasis Tap2 Magnitude (0-6) (Huntington) */ 12299 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_D2 0x3 12300 /* enum: De-Emphasis Tap2 Fine (Huntington) */ 12301 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_D2TLEV 0x4 12302 /* enum: Pre-Emphasis Magnitude (Huntington) */ 12303 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_E 0x5 12304 /* enum: Pre-Emphasis Fine (Huntington) */ 12305 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_ETLEV 0x6 12306 /* enum: TX Slew Rate Coarse control (Huntington) */ 12307 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_PREDRV_DLY 0x7 12308 /* enum: TX Slew Rate Fine control (Huntington) */ 12309 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_SR_SET 0x8 12310 /* enum: TX Termination Impedance control (Huntington) */ 12311 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_RT_SET 0x9 12312 /* enum: TX Amplitude Fine control (Medford) */ 12313 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV_FINE 0xa 12314 /* enum: Pre-shoot Tap (Medford, Medford2) */ 12315 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_ADV 0xb 12316 /* enum: De-emphasis Tap (Medford, Medford2) */ 12317 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_DLY 0xc 12318 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LANE_LBN 8 12319 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LANE_WIDTH 3 12320 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_0 0x0 /* enum */ 12321 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_1 0x1 /* enum */ 12322 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_2 0x2 /* enum */ 12323 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_3 0x3 /* enum */ 12324 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_ALL 0x4 /* enum */ 12325 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED_LBN 11 12326 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED_WIDTH 5 12327 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_INITIAL_LBN 16 12328 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_INITIAL_WIDTH 8 12329 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED2_LBN 24 12330 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED2_WIDTH 8 12331 12332 /* MC_CMD_KR_TUNE_TXEQ_SET_IN msgrequest */ 12333 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_LENMIN 8 12334 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_LENMAX 252 12335 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_LEN(num) (4+4*(num)) 12336 /* Requested operation */ 12337 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_OP_OFST 0 12338 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_OP_LEN 1 12339 /* Align the arguments to 32 bits */ 12340 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_RSVD_OFST 1 12341 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_RSVD_LEN 3 12342 /* TXEQ Parameter */ 12343 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_OFST 4 12344 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LEN 4 12345 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_MINNUM 1 12346 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_MAXNUM 62 12347 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_ID_LBN 0 12348 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_ID_WIDTH 8 12349 /* Enum values, see field(s): */ 12350 /* MC_CMD_KR_TUNE_TXEQ_GET_OUT/PARAM_ID */ 12351 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LANE_LBN 8 12352 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LANE_WIDTH 3 12353 /* Enum values, see field(s): */ 12354 /* MC_CMD_KR_TUNE_TXEQ_GET_OUT/PARAM_LANE */ 12355 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED_LBN 11 12356 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED_WIDTH 5 12357 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_INITIAL_LBN 16 12358 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_INITIAL_WIDTH 8 12359 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED2_LBN 24 12360 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED2_WIDTH 8 12361 12362 /* MC_CMD_KR_TUNE_TXEQ_SET_OUT msgresponse */ 12363 #define MC_CMD_KR_TUNE_TXEQ_SET_OUT_LEN 0 12364 12365 /* MC_CMD_KR_TUNE_RECAL_IN msgrequest */ 12366 #define MC_CMD_KR_TUNE_RECAL_IN_LEN 4 12367 /* Requested operation */ 12368 #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_OP_OFST 0 12369 #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_OP_LEN 1 12370 /* Align the arguments to 32 bits */ 12371 #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_RSVD_OFST 1 12372 #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_RSVD_LEN 3 12373 12374 /* MC_CMD_KR_TUNE_RECAL_OUT msgresponse */ 12375 #define MC_CMD_KR_TUNE_RECAL_OUT_LEN 0 12376 12377 /* MC_CMD_KR_TUNE_START_EYE_PLOT_IN msgrequest */ 12378 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_LEN 8 12379 /* Requested operation */ 12380 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_OP_OFST 0 12381 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_OP_LEN 1 12382 /* Align the arguments to 32 bits */ 12383 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_RSVD_OFST 1 12384 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_RSVD_LEN 3 12385 /* Port-relative lane to scan eye on */ 12386 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_LANE_OFST 4 12387 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_LANE_LEN 4 12388 12389 /* MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN msgrequest */ 12390 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LEN 12 12391 /* Requested operation */ 12392 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_KR_TUNE_OP_OFST 0 12393 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_KR_TUNE_OP_LEN 1 12394 /* Align the arguments to 32 bits */ 12395 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_KR_TUNE_RSVD_OFST 1 12396 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_KR_TUNE_RSVD_LEN 3 12397 /* Port-relative lane to scan eye on */ 12398 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_OFST 4 12399 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_LEN 4 12400 /* Scan duration / cycle count */ 12401 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_BER_OFST 8 12402 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_BER_LEN 4 12403 12404 /* MC_CMD_KR_TUNE_START_EYE_PLOT_OUT msgresponse */ 12405 #define MC_CMD_KR_TUNE_START_EYE_PLOT_OUT_LEN 0 12406 12407 /* MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN msgrequest */ 12408 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_LEN 4 12409 /* Requested operation */ 12410 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_OP_OFST 0 12411 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_OP_LEN 1 12412 /* Align the arguments to 32 bits */ 12413 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_RSVD_OFST 1 12414 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_RSVD_LEN 3 12415 12416 /* MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT msgresponse */ 12417 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LENMIN 0 12418 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LENMAX 252 12419 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LEN(num) (0+2*(num)) 12420 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_OFST 0 12421 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_LEN 2 12422 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MINNUM 0 12423 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MAXNUM 126 12424 12425 /* MC_CMD_KR_TUNE_READ_FOM_IN msgrequest */ 12426 #define MC_CMD_KR_TUNE_READ_FOM_IN_LEN 8 12427 /* Requested operation */ 12428 #define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_OP_OFST 0 12429 #define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_OP_LEN 1 12430 /* Align the arguments to 32 bits */ 12431 #define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_RSVD_OFST 1 12432 #define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_RSVD_LEN 3 12433 #define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_OFST 4 12434 #define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_LEN 4 12435 12436 /* MC_CMD_KR_TUNE_READ_FOM_OUT msgresponse */ 12437 #define MC_CMD_KR_TUNE_READ_FOM_OUT_LEN 4 12438 #define MC_CMD_KR_TUNE_READ_FOM_OUT_FOM_OFST 0 12439 #define MC_CMD_KR_TUNE_READ_FOM_OUT_FOM_LEN 4 12440 12441 12442 /***********************************/ 12443 /* MC_CMD_PCIE_TUNE 12444 * Get or set PCIE Serdes RXEQ and TX Driver settings 12445 */ 12446 #define MC_CMD_PCIE_TUNE 0xf2 12447 #undef MC_CMD_0xf2_PRIVILEGE_CTG 12448 12449 #define MC_CMD_0xf2_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12450 12451 /* MC_CMD_PCIE_TUNE_IN msgrequest */ 12452 #define MC_CMD_PCIE_TUNE_IN_LENMIN 4 12453 #define MC_CMD_PCIE_TUNE_IN_LENMAX 252 12454 #define MC_CMD_PCIE_TUNE_IN_LEN(num) (4+4*(num)) 12455 /* Requested operation */ 12456 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_OP_OFST 0 12457 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_OP_LEN 1 12458 /* enum: Get current RXEQ settings */ 12459 #define MC_CMD_PCIE_TUNE_IN_RXEQ_GET 0x0 12460 /* enum: Override RXEQ settings */ 12461 #define MC_CMD_PCIE_TUNE_IN_RXEQ_SET 0x1 12462 /* enum: Get current TX Driver settings */ 12463 #define MC_CMD_PCIE_TUNE_IN_TXEQ_GET 0x2 12464 /* enum: Override TX Driver settings */ 12465 #define MC_CMD_PCIE_TUNE_IN_TXEQ_SET 0x3 12466 /* enum: Start PCIe Serdes Eye diagram plot on a given lane. */ 12467 #define MC_CMD_PCIE_TUNE_IN_START_EYE_PLOT 0x5 12468 /* enum: Poll PCIe Serdes Eye diagram plot. Returns one row of BER data. The 12469 * caller should call this command repeatedly after starting eye plot, until no 12470 * more data is returned. 12471 */ 12472 #define MC_CMD_PCIE_TUNE_IN_POLL_EYE_PLOT 0x6 12473 /* enum: Enable the SERDES BIST and set it to generate a 200MHz square wave */ 12474 #define MC_CMD_PCIE_TUNE_IN_BIST_SQUARE_WAVE 0x7 12475 /* Align the arguments to 32 bits */ 12476 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_RSVD_OFST 1 12477 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_RSVD_LEN 3 12478 /* Arguments specific to the operation */ 12479 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_OFST 4 12480 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_LEN 4 12481 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_MINNUM 0 12482 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_MAXNUM 62 12483 12484 /* MC_CMD_PCIE_TUNE_OUT msgresponse */ 12485 #define MC_CMD_PCIE_TUNE_OUT_LEN 0 12486 12487 /* MC_CMD_PCIE_TUNE_RXEQ_GET_IN msgrequest */ 12488 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_LEN 4 12489 /* Requested operation */ 12490 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_OP_OFST 0 12491 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_OP_LEN 1 12492 /* Align the arguments to 32 bits */ 12493 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_RSVD_OFST 1 12494 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_RSVD_LEN 3 12495 12496 /* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT msgresponse */ 12497 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LENMIN 4 12498 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LENMAX 252 12499 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LEN(num) (0+4*(num)) 12500 /* RXEQ Parameter */ 12501 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_OFST 0 12502 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LEN 4 12503 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_MINNUM 1 12504 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_MAXNUM 63 12505 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_ID_LBN 0 12506 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_ID_WIDTH 8 12507 /* enum: Attenuation (0-15) */ 12508 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_ATT 0x0 12509 /* enum: CTLE Boost (0-15) */ 12510 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_BOOST 0x1 12511 /* enum: DFE Tap1 (0 - max negative, 64 - zero, 127 - max positive) */ 12512 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP1 0x2 12513 /* enum: DFE Tap2 (0 - max negative, 32 - zero, 63 - max positive) */ 12514 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP2 0x3 12515 /* enum: DFE Tap3 (0 - max negative, 32 - zero, 63 - max positive) */ 12516 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP3 0x4 12517 /* enum: DFE Tap4 (0 - max negative, 32 - zero, 63 - max positive) */ 12518 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP4 0x5 12519 /* enum: DFE Tap5 (0 - max negative, 32 - zero, 63 - max positive) */ 12520 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP5 0x6 12521 /* enum: DFE DLev */ 12522 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_DLEV 0x7 12523 /* enum: Figure of Merit */ 12524 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_FOM 0x8 12525 /* enum: CTLE EQ Capacitor (HF Gain) */ 12526 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_CTLE_EQC 0x9 12527 /* enum: CTLE EQ Resistor (DC Gain) */ 12528 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_CTLE_EQRES 0xa 12529 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_LBN 8 12530 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_WIDTH 5 12531 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */ 12532 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_1 0x1 /* enum */ 12533 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_2 0x2 /* enum */ 12534 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_3 0x3 /* enum */ 12535 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_4 0x4 /* enum */ 12536 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_5 0x5 /* enum */ 12537 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_6 0x6 /* enum */ 12538 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_7 0x7 /* enum */ 12539 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_8 0x8 /* enum */ 12540 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_9 0x9 /* enum */ 12541 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_10 0xa /* enum */ 12542 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_11 0xb /* enum */ 12543 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_12 0xc /* enum */ 12544 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_13 0xd /* enum */ 12545 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_14 0xe /* enum */ 12546 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_15 0xf /* enum */ 12547 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_ALL 0x10 /* enum */ 12548 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_LBN 13 12549 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_WIDTH 1 12550 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_LBN 14 12551 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_WIDTH 10 12552 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_LBN 24 12553 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8 12554 12555 /* MC_CMD_PCIE_TUNE_RXEQ_SET_IN msgrequest */ 12556 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LENMIN 8 12557 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LENMAX 252 12558 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LEN(num) (4+4*(num)) 12559 /* Requested operation */ 12560 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_OP_OFST 0 12561 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_OP_LEN 1 12562 /* Align the arguments to 32 bits */ 12563 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_RSVD_OFST 1 12564 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_RSVD_LEN 3 12565 /* RXEQ Parameter */ 12566 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_OFST 4 12567 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LEN 4 12568 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_MINNUM 1 12569 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_MAXNUM 62 12570 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_ID_LBN 0 12571 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_ID_WIDTH 8 12572 /* Enum values, see field(s): */ 12573 /* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_ID */ 12574 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LANE_LBN 8 12575 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LANE_WIDTH 5 12576 /* Enum values, see field(s): */ 12577 /* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_LANE */ 12578 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_LBN 13 12579 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_WIDTH 1 12580 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED_LBN 14 12581 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED_WIDTH 2 12582 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_INITIAL_LBN 16 12583 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_INITIAL_WIDTH 8 12584 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED2_LBN 24 12585 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED2_WIDTH 8 12586 12587 /* MC_CMD_PCIE_TUNE_RXEQ_SET_OUT msgresponse */ 12588 #define MC_CMD_PCIE_TUNE_RXEQ_SET_OUT_LEN 0 12589 12590 /* MC_CMD_PCIE_TUNE_TXEQ_GET_IN msgrequest */ 12591 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_LEN 4 12592 /* Requested operation */ 12593 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_OP_OFST 0 12594 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_OP_LEN 1 12595 /* Align the arguments to 32 bits */ 12596 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_RSVD_OFST 1 12597 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_RSVD_LEN 3 12598 12599 /* MC_CMD_PCIE_TUNE_TXEQ_GET_OUT msgresponse */ 12600 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LENMIN 4 12601 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LENMAX 252 12602 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LEN(num) (0+4*(num)) 12603 /* RXEQ Parameter */ 12604 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_OFST 0 12605 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LEN 4 12606 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_MINNUM 1 12607 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_MAXNUM 63 12608 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_ID_LBN 0 12609 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_ID_WIDTH 8 12610 /* enum: TxMargin (PIPE) */ 12611 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_TXMARGIN 0x0 12612 /* enum: TxSwing (PIPE) */ 12613 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_TXSWING 0x1 12614 /* enum: De-emphasis coefficient C(-1) (PIPE) */ 12615 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_CM1 0x2 12616 /* enum: De-emphasis coefficient C(0) (PIPE) */ 12617 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_C0 0x3 12618 /* enum: De-emphasis coefficient C(+1) (PIPE) */ 12619 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_CP1 0x4 12620 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LANE_LBN 8 12621 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LANE_WIDTH 4 12622 /* Enum values, see field(s): */ 12623 /* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_LANE */ 12624 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_RESERVED_LBN 12 12625 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_RESERVED_WIDTH 12 12626 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_CURRENT_LBN 24 12627 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8 12628 12629 /* MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN msgrequest */ 12630 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_LEN 8 12631 /* Requested operation */ 12632 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_OP_OFST 0 12633 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_OP_LEN 1 12634 /* Align the arguments to 32 bits */ 12635 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_RSVD_OFST 1 12636 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_RSVD_LEN 3 12637 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_LANE_OFST 4 12638 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_LANE_LEN 4 12639 12640 /* MC_CMD_PCIE_TUNE_START_EYE_PLOT_OUT msgresponse */ 12641 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_OUT_LEN 0 12642 12643 /* MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN msgrequest */ 12644 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_LEN 4 12645 /* Requested operation */ 12646 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_OP_OFST 0 12647 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_OP_LEN 1 12648 /* Align the arguments to 32 bits */ 12649 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_RSVD_OFST 1 12650 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_RSVD_LEN 3 12651 12652 /* MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT msgresponse */ 12653 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LENMIN 0 12654 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LENMAX 252 12655 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LEN(num) (0+2*(num)) 12656 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_OFST 0 12657 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_LEN 2 12658 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MINNUM 0 12659 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MAXNUM 126 12660 12661 /* MC_CMD_PCIE_TUNE_BIST_SQUARE_WAVE_IN msgrequest */ 12662 #define MC_CMD_PCIE_TUNE_BIST_SQUARE_WAVE_IN_LEN 0 12663 12664 /* MC_CMD_PCIE_TUNE_BIST_SQUARE_WAVE_OUT msgrequest */ 12665 #define MC_CMD_PCIE_TUNE_BIST_SQUARE_WAVE_OUT_LEN 0 12666 12667 12668 /***********************************/ 12669 /* MC_CMD_LICENSING 12670 * Operations on the NVRAM_PARTITION_TYPE_LICENSE application license partition 12671 * - not used for V3 licensing 12672 */ 12673 #define MC_CMD_LICENSING 0xf3 12674 #undef MC_CMD_0xf3_PRIVILEGE_CTG 12675 12676 #define MC_CMD_0xf3_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12677 12678 /* MC_CMD_LICENSING_IN msgrequest */ 12679 #define MC_CMD_LICENSING_IN_LEN 4 12680 /* identifies the type of operation requested */ 12681 #define MC_CMD_LICENSING_IN_OP_OFST 0 12682 #define MC_CMD_LICENSING_IN_OP_LEN 4 12683 /* enum: re-read and apply licenses after a license key partition update; note 12684 * that this operation returns a zero-length response 12685 */ 12686 #define MC_CMD_LICENSING_IN_OP_UPDATE_LICENSE 0x0 12687 /* enum: report counts of installed licenses */ 12688 #define MC_CMD_LICENSING_IN_OP_GET_KEY_STATS 0x1 12689 12690 /* MC_CMD_LICENSING_OUT msgresponse */ 12691 #define MC_CMD_LICENSING_OUT_LEN 28 12692 /* count of application keys which are valid */ 12693 #define MC_CMD_LICENSING_OUT_VALID_APP_KEYS_OFST 0 12694 #define MC_CMD_LICENSING_OUT_VALID_APP_KEYS_LEN 4 12695 /* sum of UNVERIFIABLE_APP_KEYS + WRONG_NODE_APP_KEYS (for compatibility with 12696 * MC_CMD_FC_OP_LICENSE) 12697 */ 12698 #define MC_CMD_LICENSING_OUT_INVALID_APP_KEYS_OFST 4 12699 #define MC_CMD_LICENSING_OUT_INVALID_APP_KEYS_LEN 4 12700 /* count of application keys which are invalid due to being blacklisted */ 12701 #define MC_CMD_LICENSING_OUT_BLACKLISTED_APP_KEYS_OFST 8 12702 #define MC_CMD_LICENSING_OUT_BLACKLISTED_APP_KEYS_LEN 4 12703 /* count of application keys which are invalid due to being unverifiable */ 12704 #define MC_CMD_LICENSING_OUT_UNVERIFIABLE_APP_KEYS_OFST 12 12705 #define MC_CMD_LICENSING_OUT_UNVERIFIABLE_APP_KEYS_LEN 4 12706 /* count of application keys which are invalid due to being for the wrong node 12707 */ 12708 #define MC_CMD_LICENSING_OUT_WRONG_NODE_APP_KEYS_OFST 16 12709 #define MC_CMD_LICENSING_OUT_WRONG_NODE_APP_KEYS_LEN 4 12710 /* licensing state (for diagnostics; the exact meaning of the bits in this 12711 * field are private to the firmware) 12712 */ 12713 #define MC_CMD_LICENSING_OUT_LICENSING_STATE_OFST 20 12714 #define MC_CMD_LICENSING_OUT_LICENSING_STATE_LEN 4 12715 /* licensing subsystem self-test report (for manftest) */ 12716 #define MC_CMD_LICENSING_OUT_LICENSING_SELF_TEST_OFST 24 12717 #define MC_CMD_LICENSING_OUT_LICENSING_SELF_TEST_LEN 4 12718 /* enum: licensing subsystem self-test failed */ 12719 #define MC_CMD_LICENSING_OUT_SELF_TEST_FAIL 0x0 12720 /* enum: licensing subsystem self-test passed */ 12721 #define MC_CMD_LICENSING_OUT_SELF_TEST_PASS 0x1 12722 12723 12724 /***********************************/ 12725 /* MC_CMD_LICENSING_V3 12726 * Operations on the NVRAM_PARTITION_TYPE_LICENSE application license partition 12727 * - V3 licensing (Medford) 12728 */ 12729 #define MC_CMD_LICENSING_V3 0xd0 12730 #undef MC_CMD_0xd0_PRIVILEGE_CTG 12731 12732 #define MC_CMD_0xd0_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12733 12734 /* MC_CMD_LICENSING_V3_IN msgrequest */ 12735 #define MC_CMD_LICENSING_V3_IN_LEN 4 12736 /* identifies the type of operation requested */ 12737 #define MC_CMD_LICENSING_V3_IN_OP_OFST 0 12738 #define MC_CMD_LICENSING_V3_IN_OP_LEN 4 12739 /* enum: re-read and apply licenses after a license key partition update; note 12740 * that this operation returns a zero-length response 12741 */ 12742 #define MC_CMD_LICENSING_V3_IN_OP_UPDATE_LICENSE 0x0 12743 /* enum: report counts of installed licenses Returns EAGAIN if license 12744 * processing (updating) has been started but not yet completed. 12745 */ 12746 #define MC_CMD_LICENSING_V3_IN_OP_REPORT_LICENSE 0x1 12747 12748 /* MC_CMD_LICENSING_V3_OUT msgresponse */ 12749 #define MC_CMD_LICENSING_V3_OUT_LEN 88 12750 /* count of keys which are valid */ 12751 #define MC_CMD_LICENSING_V3_OUT_VALID_KEYS_OFST 0 12752 #define MC_CMD_LICENSING_V3_OUT_VALID_KEYS_LEN 4 12753 /* sum of UNVERIFIABLE_KEYS + WRONG_NODE_KEYS (for compatibility with 12754 * MC_CMD_FC_OP_LICENSE) 12755 */ 12756 #define MC_CMD_LICENSING_V3_OUT_INVALID_KEYS_OFST 4 12757 #define MC_CMD_LICENSING_V3_OUT_INVALID_KEYS_LEN 4 12758 /* count of keys which are invalid due to being unverifiable */ 12759 #define MC_CMD_LICENSING_V3_OUT_UNVERIFIABLE_KEYS_OFST 8 12760 #define MC_CMD_LICENSING_V3_OUT_UNVERIFIABLE_KEYS_LEN 4 12761 /* count of keys which are invalid due to being for the wrong node */ 12762 #define MC_CMD_LICENSING_V3_OUT_WRONG_NODE_KEYS_OFST 12 12763 #define MC_CMD_LICENSING_V3_OUT_WRONG_NODE_KEYS_LEN 4 12764 /* licensing state (for diagnostics; the exact meaning of the bits in this 12765 * field are private to the firmware) 12766 */ 12767 #define MC_CMD_LICENSING_V3_OUT_LICENSING_STATE_OFST 16 12768 #define MC_CMD_LICENSING_V3_OUT_LICENSING_STATE_LEN 4 12769 /* licensing subsystem self-test report (for manftest) */ 12770 #define MC_CMD_LICENSING_V3_OUT_LICENSING_SELF_TEST_OFST 20 12771 #define MC_CMD_LICENSING_V3_OUT_LICENSING_SELF_TEST_LEN 4 12772 /* enum: licensing subsystem self-test failed */ 12773 #define MC_CMD_LICENSING_V3_OUT_SELF_TEST_FAIL 0x0 12774 /* enum: licensing subsystem self-test passed */ 12775 #define MC_CMD_LICENSING_V3_OUT_SELF_TEST_PASS 0x1 12776 /* bitmask of licensed applications */ 12777 #define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_OFST 24 12778 #define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LEN 8 12779 #define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LO_OFST 24 12780 #define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_HI_OFST 28 12781 /* reserved for future use */ 12782 #define MC_CMD_LICENSING_V3_OUT_RESERVED_0_OFST 32 12783 #define MC_CMD_LICENSING_V3_OUT_RESERVED_0_LEN 24 12784 /* bitmask of licensed features */ 12785 #define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_OFST 56 12786 #define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LEN 8 12787 #define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LO_OFST 56 12788 #define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_HI_OFST 60 12789 /* reserved for future use */ 12790 #define MC_CMD_LICENSING_V3_OUT_RESERVED_1_OFST 64 12791 #define MC_CMD_LICENSING_V3_OUT_RESERVED_1_LEN 24 12792 12793 12794 /***********************************/ 12795 /* MC_CMD_LICENSING_GET_ID_V3 12796 * Get ID and type from the NVRAM_PARTITION_TYPE_LICENSE application license 12797 * partition - V3 licensing (Medford) 12798 */ 12799 #define MC_CMD_LICENSING_GET_ID_V3 0xd1 12800 #undef MC_CMD_0xd1_PRIVILEGE_CTG 12801 12802 #define MC_CMD_0xd1_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12803 12804 /* MC_CMD_LICENSING_GET_ID_V3_IN msgrequest */ 12805 #define MC_CMD_LICENSING_GET_ID_V3_IN_LEN 0 12806 12807 /* MC_CMD_LICENSING_GET_ID_V3_OUT msgresponse */ 12808 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LENMIN 8 12809 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LENMAX 252 12810 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LEN(num) (8+1*(num)) 12811 /* type of license (eg 3) */ 12812 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_TYPE_OFST 0 12813 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_TYPE_LEN 4 12814 /* length of the license ID (in bytes) */ 12815 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_LENGTH_OFST 4 12816 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_LENGTH_LEN 4 12817 /* the unique license ID of the adapter */ 12818 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_OFST 8 12819 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_LEN 1 12820 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_MINNUM 0 12821 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_MAXNUM 244 12822 12823 12824 /***********************************/ 12825 /* MC_CMD_MC2MC_PROXY 12826 * Execute an arbitrary MCDI command on the slave MC of a dual-core device. 12827 * This will fail on a single-core system. 12828 */ 12829 #define MC_CMD_MC2MC_PROXY 0xf4 12830 #undef MC_CMD_0xf4_PRIVILEGE_CTG 12831 12832 #define MC_CMD_0xf4_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12833 12834 /* MC_CMD_MC2MC_PROXY_IN msgrequest */ 12835 #define MC_CMD_MC2MC_PROXY_IN_LEN 0 12836 12837 /* MC_CMD_MC2MC_PROXY_OUT msgresponse */ 12838 #define MC_CMD_MC2MC_PROXY_OUT_LEN 0 12839 12840 12841 /***********************************/ 12842 /* MC_CMD_GET_LICENSED_APP_STATE 12843 * Query the state of an individual licensed application. (Note that the actual 12844 * state may be invalidated by the MC_CMD_LICENSING OP_UPDATE_LICENSE operation 12845 * or a reboot of the MC.) Not used for V3 licensing 12846 */ 12847 #define MC_CMD_GET_LICENSED_APP_STATE 0xf5 12848 #undef MC_CMD_0xf5_PRIVILEGE_CTG 12849 12850 #define MC_CMD_0xf5_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12851 12852 /* MC_CMD_GET_LICENSED_APP_STATE_IN msgrequest */ 12853 #define MC_CMD_GET_LICENSED_APP_STATE_IN_LEN 4 12854 /* application ID to query (LICENSED_APP_ID_xxx) */ 12855 #define MC_CMD_GET_LICENSED_APP_STATE_IN_APP_ID_OFST 0 12856 #define MC_CMD_GET_LICENSED_APP_STATE_IN_APP_ID_LEN 4 12857 12858 /* MC_CMD_GET_LICENSED_APP_STATE_OUT msgresponse */ 12859 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_LEN 4 12860 /* state of this application */ 12861 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_STATE_OFST 0 12862 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_STATE_LEN 4 12863 /* enum: no (or invalid) license is present for the application */ 12864 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_NOT_LICENSED 0x0 12865 /* enum: a valid license is present for the application */ 12866 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_LICENSED 0x1 12867 12868 12869 /***********************************/ 12870 /* MC_CMD_GET_LICENSED_V3_APP_STATE 12871 * Query the state of an individual licensed application. (Note that the actual 12872 * state may be invalidated by the MC_CMD_LICENSING_V3 OP_UPDATE_LICENSE 12873 * operation or a reboot of the MC.) Used for V3 licensing (Medford) 12874 */ 12875 #define MC_CMD_GET_LICENSED_V3_APP_STATE 0xd2 12876 #undef MC_CMD_0xd2_PRIVILEGE_CTG 12877 12878 #define MC_CMD_0xd2_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12879 12880 /* MC_CMD_GET_LICENSED_V3_APP_STATE_IN msgrequest */ 12881 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_LEN 8 12882 /* application ID to query (LICENSED_V3_APPS_xxx) expressed as a single bit 12883 * mask 12884 */ 12885 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_OFST 0 12886 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LEN 8 12887 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LO_OFST 0 12888 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_HI_OFST 4 12889 12890 /* MC_CMD_GET_LICENSED_V3_APP_STATE_OUT msgresponse */ 12891 #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_LEN 4 12892 /* state of this application */ 12893 #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_STATE_OFST 0 12894 #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_STATE_LEN 4 12895 /* enum: no (or invalid) license is present for the application */ 12896 #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_NOT_LICENSED 0x0 12897 /* enum: a valid license is present for the application */ 12898 #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_LICENSED 0x1 12899 12900 12901 /***********************************/ 12902 /* MC_CMD_GET_LICENSED_V3_FEATURE_STATES 12903 * Query the state of an one or more licensed features. (Note that the actual 12904 * state may be invalidated by the MC_CMD_LICENSING_V3 OP_UPDATE_LICENSE 12905 * operation or a reboot of the MC.) Used for V3 licensing (Medford) 12906 */ 12907 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES 0xd3 12908 #undef MC_CMD_0xd3_PRIVILEGE_CTG 12909 12910 #define MC_CMD_0xd3_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12911 12912 /* MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN msgrequest */ 12913 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_LEN 8 12914 /* features to query (LICENSED_V3_FEATURES_xxx) expressed as a mask with one or 12915 * more bits set 12916 */ 12917 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_OFST 0 12918 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LEN 8 12919 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LO_OFST 0 12920 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_HI_OFST 4 12921 12922 /* MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT msgresponse */ 12923 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_LEN 8 12924 /* states of these features - bit set for licensed, clear for not licensed */ 12925 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_OFST 0 12926 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LEN 8 12927 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LO_OFST 0 12928 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_HI_OFST 4 12929 12930 12931 /***********************************/ 12932 /* MC_CMD_LICENSED_APP_OP 12933 * Perform an action for an individual licensed application - not used for V3 12934 * licensing. 12935 */ 12936 #define MC_CMD_LICENSED_APP_OP 0xf6 12937 #undef MC_CMD_0xf6_PRIVILEGE_CTG 12938 12939 #define MC_CMD_0xf6_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12940 12941 /* MC_CMD_LICENSED_APP_OP_IN msgrequest */ 12942 #define MC_CMD_LICENSED_APP_OP_IN_LENMIN 8 12943 #define MC_CMD_LICENSED_APP_OP_IN_LENMAX 252 12944 #define MC_CMD_LICENSED_APP_OP_IN_LEN(num) (8+4*(num)) 12945 /* application ID */ 12946 #define MC_CMD_LICENSED_APP_OP_IN_APP_ID_OFST 0 12947 #define MC_CMD_LICENSED_APP_OP_IN_APP_ID_LEN 4 12948 /* the type of operation requested */ 12949 #define MC_CMD_LICENSED_APP_OP_IN_OP_OFST 4 12950 #define MC_CMD_LICENSED_APP_OP_IN_OP_LEN 4 12951 /* enum: validate application */ 12952 #define MC_CMD_LICENSED_APP_OP_IN_OP_VALIDATE 0x0 12953 /* enum: mask application */ 12954 #define MC_CMD_LICENSED_APP_OP_IN_OP_MASK 0x1 12955 /* arguments specific to this particular operation */ 12956 #define MC_CMD_LICENSED_APP_OP_IN_ARGS_OFST 8 12957 #define MC_CMD_LICENSED_APP_OP_IN_ARGS_LEN 4 12958 #define MC_CMD_LICENSED_APP_OP_IN_ARGS_MINNUM 0 12959 #define MC_CMD_LICENSED_APP_OP_IN_ARGS_MAXNUM 61 12960 12961 /* MC_CMD_LICENSED_APP_OP_OUT msgresponse */ 12962 #define MC_CMD_LICENSED_APP_OP_OUT_LENMIN 0 12963 #define MC_CMD_LICENSED_APP_OP_OUT_LENMAX 252 12964 #define MC_CMD_LICENSED_APP_OP_OUT_LEN(num) (0+4*(num)) 12965 /* result specific to this particular operation */ 12966 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_OFST 0 12967 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_LEN 4 12968 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_MINNUM 0 12969 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_MAXNUM 63 12970 12971 /* MC_CMD_LICENSED_APP_OP_VALIDATE_IN msgrequest */ 12972 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_LEN 72 12973 /* application ID */ 12974 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_APP_ID_OFST 0 12975 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_APP_ID_LEN 4 12976 /* the type of operation requested */ 12977 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_OP_OFST 4 12978 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_OP_LEN 4 12979 /* validation challenge */ 12980 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_CHALLENGE_OFST 8 12981 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_CHALLENGE_LEN 64 12982 12983 /* MC_CMD_LICENSED_APP_OP_VALIDATE_OUT msgresponse */ 12984 #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_LEN 68 12985 /* feature expiry (time_t) */ 12986 #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_EXPIRY_OFST 0 12987 #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_EXPIRY_LEN 4 12988 /* validation response */ 12989 #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_RESPONSE_OFST 4 12990 #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_RESPONSE_LEN 64 12991 12992 /* MC_CMD_LICENSED_APP_OP_MASK_IN msgrequest */ 12993 #define MC_CMD_LICENSED_APP_OP_MASK_IN_LEN 12 12994 /* application ID */ 12995 #define MC_CMD_LICENSED_APP_OP_MASK_IN_APP_ID_OFST 0 12996 #define MC_CMD_LICENSED_APP_OP_MASK_IN_APP_ID_LEN 4 12997 /* the type of operation requested */ 12998 #define MC_CMD_LICENSED_APP_OP_MASK_IN_OP_OFST 4 12999 #define MC_CMD_LICENSED_APP_OP_MASK_IN_OP_LEN 4 13000 /* flag */ 13001 #define MC_CMD_LICENSED_APP_OP_MASK_IN_FLAG_OFST 8 13002 #define MC_CMD_LICENSED_APP_OP_MASK_IN_FLAG_LEN 4 13003 13004 /* MC_CMD_LICENSED_APP_OP_MASK_OUT msgresponse */ 13005 #define MC_CMD_LICENSED_APP_OP_MASK_OUT_LEN 0 13006 13007 13008 /***********************************/ 13009 /* MC_CMD_LICENSED_V3_VALIDATE_APP 13010 * Perform validation for an individual licensed application - V3 licensing 13011 * (Medford) 13012 */ 13013 #define MC_CMD_LICENSED_V3_VALIDATE_APP 0xd4 13014 #undef MC_CMD_0xd4_PRIVILEGE_CTG 13015 13016 #define MC_CMD_0xd4_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13017 13018 /* MC_CMD_LICENSED_V3_VALIDATE_APP_IN msgrequest */ 13019 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_LEN 56 13020 /* challenge for validation (384 bits) */ 13021 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_CHALLENGE_OFST 0 13022 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_CHALLENGE_LEN 48 13023 /* application ID expressed as a single bit mask */ 13024 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_OFST 48 13025 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LEN 8 13026 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LO_OFST 48 13027 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_HI_OFST 52 13028 13029 /* MC_CMD_LICENSED_V3_VALIDATE_APP_OUT msgresponse */ 13030 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_LEN 116 13031 /* validation response to challenge in the form of ECDSA signature consisting 13032 * of two 384-bit integers, r and s, in big-endian order. The signature signs a 13033 * SHA-384 digest of a message constructed from the concatenation of the input 13034 * message and the remaining fields of this output message, e.g. challenge[48 13035 * bytes] ... expiry_time[4 bytes] ... 13036 */ 13037 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_RESPONSE_OFST 0 13038 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_RESPONSE_LEN 96 13039 /* application expiry time */ 13040 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_TIME_OFST 96 13041 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_TIME_LEN 4 13042 /* application expiry units */ 13043 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNITS_OFST 100 13044 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNITS_LEN 4 13045 /* enum: expiry units are accounting units */ 13046 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNIT_ACC 0x0 13047 /* enum: expiry units are calendar days */ 13048 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNIT_DAYS 0x1 13049 /* base MAC address of the NIC stored in NVRAM (note that this is a constant 13050 * value for a given NIC regardless which function is calling, effectively this 13051 * is PF0 base MAC address) 13052 */ 13053 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_BASE_MACADDR_OFST 104 13054 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_BASE_MACADDR_LEN 6 13055 /* MAC address of v-adaptor associated with the client. If no such v-adapator 13056 * exists, then the field is filled with 0xFF. 13057 */ 13058 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_VADAPTOR_MACADDR_OFST 110 13059 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_VADAPTOR_MACADDR_LEN 6 13060 13061 13062 /***********************************/ 13063 /* MC_CMD_LICENSED_V3_MASK_FEATURES 13064 * Mask features - V3 licensing (Medford) 13065 */ 13066 #define MC_CMD_LICENSED_V3_MASK_FEATURES 0xd5 13067 #undef MC_CMD_0xd5_PRIVILEGE_CTG 13068 13069 #define MC_CMD_0xd5_PRIVILEGE_CTG SRIOV_CTG_ADMIN 13070 13071 /* MC_CMD_LICENSED_V3_MASK_FEATURES_IN msgrequest */ 13072 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_LEN 12 13073 /* mask to be applied to features to be changed */ 13074 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_OFST 0 13075 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LEN 8 13076 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LO_OFST 0 13077 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_HI_OFST 4 13078 /* whether to turn on or turn off the masked features */ 13079 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_FLAG_OFST 8 13080 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_FLAG_LEN 4 13081 /* enum: turn the features off */ 13082 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_OFF 0x0 13083 /* enum: turn the features back on */ 13084 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_ON 0x1 13085 13086 /* MC_CMD_LICENSED_V3_MASK_FEATURES_OUT msgresponse */ 13087 #define MC_CMD_LICENSED_V3_MASK_FEATURES_OUT_LEN 0 13088 13089 13090 /***********************************/ 13091 /* MC_CMD_LICENSING_V3_TEMPORARY 13092 * Perform operations to support installation of a single temporary license in 13093 * the adapter, in addition to those found in the licensing partition. See 13094 * SF-116124-SW for an overview of how this could be used. The license is 13095 * stored in MC persistent data and so will survive a MC reboot, but will be 13096 * erased when the adapter is power cycled 13097 */ 13098 #define MC_CMD_LICENSING_V3_TEMPORARY 0xd6 13099 #undef MC_CMD_0xd6_PRIVILEGE_CTG 13100 13101 #define MC_CMD_0xd6_PRIVILEGE_CTG SRIOV_CTG_ADMIN 13102 13103 /* MC_CMD_LICENSING_V3_TEMPORARY_IN msgrequest */ 13104 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_LEN 4 13105 /* operation code */ 13106 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_OP_OFST 0 13107 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_OP_LEN 4 13108 /* enum: install a new license, overwriting any existing temporary license. 13109 * This is an asynchronous operation owing to the time taken to validate an 13110 * ECDSA license 13111 */ 13112 #define MC_CMD_LICENSING_V3_TEMPORARY_SET 0x0 13113 /* enum: clear the license immediately rather than waiting for the next power 13114 * cycle 13115 */ 13116 #define MC_CMD_LICENSING_V3_TEMPORARY_CLEAR 0x1 13117 /* enum: get the status of the asynchronous MC_CMD_LICENSING_V3_TEMPORARY_SET 13118 * operation 13119 */ 13120 #define MC_CMD_LICENSING_V3_TEMPORARY_STATUS 0x2 13121 13122 /* MC_CMD_LICENSING_V3_TEMPORARY_IN_SET msgrequest */ 13123 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_LEN 164 13124 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_OP_OFST 0 13125 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_OP_LEN 4 13126 /* ECDSA license and signature */ 13127 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_LICENSE_OFST 4 13128 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_LICENSE_LEN 160 13129 13130 /* MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR msgrequest */ 13131 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR_LEN 4 13132 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR_OP_OFST 0 13133 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR_OP_LEN 4 13134 13135 /* MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS msgrequest */ 13136 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS_LEN 4 13137 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS_OP_OFST 0 13138 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS_OP_LEN 4 13139 13140 /* MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS msgresponse */ 13141 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LEN 12 13142 /* status code */ 13143 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_STATUS_OFST 0 13144 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_STATUS_LEN 4 13145 /* enum: finished validating and installing license */ 13146 #define MC_CMD_LICENSING_V3_TEMPORARY_STATUS_OK 0x0 13147 /* enum: license validation and installation in progress */ 13148 #define MC_CMD_LICENSING_V3_TEMPORARY_STATUS_IN_PROGRESS 0x1 13149 /* enum: licensing error. More specific error messages are not provided to 13150 * avoid exposing details of the licensing system to the client 13151 */ 13152 #define MC_CMD_LICENSING_V3_TEMPORARY_STATUS_ERROR 0x2 13153 /* bitmask of licensed features */ 13154 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_OFST 4 13155 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_LEN 8 13156 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_LO_OFST 4 13157 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_HI_OFST 8 13158 13159 13160 /***********************************/ 13161 /* MC_CMD_SET_PORT_SNIFF_CONFIG 13162 * Configure RX port sniffing for the physical port associated with the calling 13163 * function. Only a privileged function may change the port sniffing 13164 * configuration. A copy of all traffic delivered to the host (non-promiscuous 13165 * mode) or all traffic arriving at the port (promiscuous mode) may be 13166 * delivered to a specific queue, or a set of queues with RSS. 13167 */ 13168 #define MC_CMD_SET_PORT_SNIFF_CONFIG 0xf7 13169 #undef MC_CMD_0xf7_PRIVILEGE_CTG 13170 13171 #define MC_CMD_0xf7_PRIVILEGE_CTG SRIOV_CTG_ADMIN 13172 13173 /* MC_CMD_SET_PORT_SNIFF_CONFIG_IN msgrequest */ 13174 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_LEN 16 13175 /* configuration flags */ 13176 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_FLAGS_OFST 0 13177 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_FLAGS_LEN 4 13178 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_ENABLE_LBN 0 13179 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_ENABLE_WIDTH 1 13180 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_PROMISCUOUS_LBN 1 13181 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_PROMISCUOUS_WIDTH 1 13182 /* receive queue handle (for RSS mode, this is the base queue) */ 13183 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_QUEUE_OFST 4 13184 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_QUEUE_LEN 4 13185 /* receive mode */ 13186 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_OFST 8 13187 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_LEN 4 13188 /* enum: receive to just the specified queue */ 13189 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_SIMPLE 0x0 13190 /* enum: receive to multiple queues using RSS context */ 13191 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_RSS 0x1 13192 /* RSS context (for RX_MODE_RSS) as returned by MC_CMD_RSS_CONTEXT_ALLOC. Note 13193 * that these handles should be considered opaque to the host, although a value 13194 * of 0xFFFFFFFF is guaranteed never to be a valid handle. 13195 */ 13196 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_OFST 12 13197 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_LEN 4 13198 13199 /* MC_CMD_SET_PORT_SNIFF_CONFIG_OUT msgresponse */ 13200 #define MC_CMD_SET_PORT_SNIFF_CONFIG_OUT_LEN 0 13201 13202 13203 /***********************************/ 13204 /* MC_CMD_GET_PORT_SNIFF_CONFIG 13205 * Obtain the current RX port sniffing configuration for the physical port 13206 * associated with the calling function. Only a privileged function may read 13207 * the configuration. 13208 */ 13209 #define MC_CMD_GET_PORT_SNIFF_CONFIG 0xf8 13210 #undef MC_CMD_0xf8_PRIVILEGE_CTG 13211 13212 #define MC_CMD_0xf8_PRIVILEGE_CTG SRIOV_CTG_ADMIN 13213 13214 /* MC_CMD_GET_PORT_SNIFF_CONFIG_IN msgrequest */ 13215 #define MC_CMD_GET_PORT_SNIFF_CONFIG_IN_LEN 0 13216 13217 /* MC_CMD_GET_PORT_SNIFF_CONFIG_OUT msgresponse */ 13218 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_LEN 16 13219 /* configuration flags */ 13220 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_FLAGS_OFST 0 13221 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_FLAGS_LEN 4 13222 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_ENABLE_LBN 0 13223 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_ENABLE_WIDTH 1 13224 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_PROMISCUOUS_LBN 1 13225 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_PROMISCUOUS_WIDTH 1 13226 /* receiving queue handle (for RSS mode, this is the base queue) */ 13227 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_OFST 4 13228 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_LEN 4 13229 /* receive mode */ 13230 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_OFST 8 13231 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_LEN 4 13232 /* enum: receiving to just the specified queue */ 13233 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_SIMPLE 0x0 13234 /* enum: receiving to multiple queues using RSS context */ 13235 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_RSS 0x1 13236 /* RSS context (for RX_MODE_RSS) */ 13237 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_OFST 12 13238 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_LEN 4 13239 13240 13241 /***********************************/ 13242 /* MC_CMD_SET_PARSER_DISP_CONFIG 13243 * Change configuration related to the parser-dispatcher subsystem. 13244 */ 13245 #define MC_CMD_SET_PARSER_DISP_CONFIG 0xf9 13246 #undef MC_CMD_0xf9_PRIVILEGE_CTG 13247 13248 #define MC_CMD_0xf9_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13249 13250 /* MC_CMD_SET_PARSER_DISP_CONFIG_IN msgrequest */ 13251 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LENMIN 12 13252 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LENMAX 252 13253 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LEN(num) (8+4*(num)) 13254 /* the type of configuration setting to change */ 13255 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_TYPE_OFST 0 13256 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_TYPE_LEN 4 13257 /* enum: Per-TXQ enable for multicast UDP destination lookup for possible 13258 * internal loopback. (ENTITY is a queue handle, VALUE is a single boolean.) 13259 */ 13260 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_TXQ_MCAST_UDP_DST_LOOKUP_EN 0x0 13261 /* enum: Per-v-adaptor enable for suppression of self-transmissions on the 13262 * internal loopback path. (ENTITY is an EVB_PORT_ID, VALUE is a single 13263 * boolean.) 13264 */ 13265 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VADAPTOR_SUPPRESS_SELF_TX 0x1 13266 /* handle for the entity to update: queue handle, EVB port ID, etc. depending 13267 * on the type of configuration setting being changed 13268 */ 13269 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_ENTITY_OFST 4 13270 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_ENTITY_LEN 4 13271 /* new value: the details depend on the type of configuration setting being 13272 * changed 13273 */ 13274 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_OFST 8 13275 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_LEN 4 13276 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_MINNUM 1 13277 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_MAXNUM 61 13278 13279 /* MC_CMD_SET_PARSER_DISP_CONFIG_OUT msgresponse */ 13280 #define MC_CMD_SET_PARSER_DISP_CONFIG_OUT_LEN 0 13281 13282 13283 /***********************************/ 13284 /* MC_CMD_GET_PARSER_DISP_CONFIG 13285 * Read configuration related to the parser-dispatcher subsystem. 13286 */ 13287 #define MC_CMD_GET_PARSER_DISP_CONFIG 0xfa 13288 #undef MC_CMD_0xfa_PRIVILEGE_CTG 13289 13290 #define MC_CMD_0xfa_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13291 13292 /* MC_CMD_GET_PARSER_DISP_CONFIG_IN msgrequest */ 13293 #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_LEN 8 13294 /* the type of configuration setting to read */ 13295 #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_TYPE_OFST 0 13296 #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_TYPE_LEN 4 13297 /* Enum values, see field(s): */ 13298 /* MC_CMD_SET_PARSER_DISP_CONFIG/MC_CMD_SET_PARSER_DISP_CONFIG_IN/TYPE */ 13299 /* handle for the entity to query: queue handle, EVB port ID, etc. depending on 13300 * the type of configuration setting being read 13301 */ 13302 #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_ENTITY_OFST 4 13303 #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_ENTITY_LEN 4 13304 13305 /* MC_CMD_GET_PARSER_DISP_CONFIG_OUT msgresponse */ 13306 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LENMIN 4 13307 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LENMAX 252 13308 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LEN(num) (0+4*(num)) 13309 /* current value: the details depend on the type of configuration setting being 13310 * read 13311 */ 13312 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_OFST 0 13313 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_LEN 4 13314 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_MINNUM 1 13315 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_MAXNUM 63 13316 13317 13318 /***********************************/ 13319 /* MC_CMD_SET_TX_PORT_SNIFF_CONFIG 13320 * Configure TX port sniffing for the physical port associated with the calling 13321 * function. Only a privileged function may change the port sniffing 13322 * configuration. A copy of all traffic transmitted through the port may be 13323 * delivered to a specific queue, or a set of queues with RSS. Note that these 13324 * packets are delivered with transmit timestamps in the packet prefix, not 13325 * receive timestamps, so it is likely that the queue(s) will need to be 13326 * dedicated as TX sniff receivers. 13327 */ 13328 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG 0xfb 13329 #undef MC_CMD_0xfb_PRIVILEGE_CTG 13330 13331 #define MC_CMD_0xfb_PRIVILEGE_CTG SRIOV_CTG_ADMIN 13332 13333 /* MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN msgrequest */ 13334 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_LEN 16 13335 /* configuration flags */ 13336 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_FLAGS_OFST 0 13337 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_FLAGS_LEN 4 13338 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_ENABLE_LBN 0 13339 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_ENABLE_WIDTH 1 13340 /* receive queue handle (for RSS mode, this is the base queue) */ 13341 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_QUEUE_OFST 4 13342 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_QUEUE_LEN 4 13343 /* receive mode */ 13344 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_OFST 8 13345 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_LEN 4 13346 /* enum: receive to just the specified queue */ 13347 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_SIMPLE 0x0 13348 /* enum: receive to multiple queues using RSS context */ 13349 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_RSS 0x1 13350 /* RSS context (for RX_MODE_RSS) as returned by MC_CMD_RSS_CONTEXT_ALLOC. Note 13351 * that these handles should be considered opaque to the host, although a value 13352 * of 0xFFFFFFFF is guaranteed never to be a valid handle. 13353 */ 13354 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_OFST 12 13355 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_LEN 4 13356 13357 /* MC_CMD_SET_TX_PORT_SNIFF_CONFIG_OUT msgresponse */ 13358 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_OUT_LEN 0 13359 13360 13361 /***********************************/ 13362 /* MC_CMD_GET_TX_PORT_SNIFF_CONFIG 13363 * Obtain the current TX port sniffing configuration for the physical port 13364 * associated with the calling function. Only a privileged function may read 13365 * the configuration. 13366 */ 13367 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG 0xfc 13368 #undef MC_CMD_0xfc_PRIVILEGE_CTG 13369 13370 #define MC_CMD_0xfc_PRIVILEGE_CTG SRIOV_CTG_ADMIN 13371 13372 /* MC_CMD_GET_TX_PORT_SNIFF_CONFIG_IN msgrequest */ 13373 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_IN_LEN 0 13374 13375 /* MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT msgresponse */ 13376 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_LEN 16 13377 /* configuration flags */ 13378 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_FLAGS_OFST 0 13379 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_FLAGS_LEN 4 13380 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_ENABLE_LBN 0 13381 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_ENABLE_WIDTH 1 13382 /* receiving queue handle (for RSS mode, this is the base queue) */ 13383 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_OFST 4 13384 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_LEN 4 13385 /* receive mode */ 13386 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_OFST 8 13387 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_LEN 4 13388 /* enum: receiving to just the specified queue */ 13389 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_SIMPLE 0x0 13390 /* enum: receiving to multiple queues using RSS context */ 13391 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_RSS 0x1 13392 /* RSS context (for RX_MODE_RSS) */ 13393 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_OFST 12 13394 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_LEN 4 13395 13396 13397 /***********************************/ 13398 /* MC_CMD_RMON_STATS_RX_ERRORS 13399 * Per queue rx error stats. 13400 */ 13401 #define MC_CMD_RMON_STATS_RX_ERRORS 0xfe 13402 #undef MC_CMD_0xfe_PRIVILEGE_CTG 13403 13404 #define MC_CMD_0xfe_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13405 13406 /* MC_CMD_RMON_STATS_RX_ERRORS_IN msgrequest */ 13407 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_LEN 8 13408 /* The rx queue to get stats for. */ 13409 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_RX_QUEUE_OFST 0 13410 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_RX_QUEUE_LEN 4 13411 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_FLAGS_OFST 4 13412 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_FLAGS_LEN 4 13413 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_RST_LBN 0 13414 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_RST_WIDTH 1 13415 13416 /* MC_CMD_RMON_STATS_RX_ERRORS_OUT msgresponse */ 13417 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_LEN 16 13418 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_CRC_ERRORS_OFST 0 13419 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_CRC_ERRORS_LEN 4 13420 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_TRUNC_ERRORS_OFST 4 13421 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_TRUNC_ERRORS_LEN 4 13422 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_NO_DESC_DROPS_OFST 8 13423 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_NO_DESC_DROPS_LEN 4 13424 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_ABORT_OFST 12 13425 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_ABORT_LEN 4 13426 13427 13428 /***********************************/ 13429 /* MC_CMD_GET_PCIE_RESOURCE_INFO 13430 * Find out about available PCIE resources 13431 */ 13432 #define MC_CMD_GET_PCIE_RESOURCE_INFO 0xfd 13433 #undef MC_CMD_0xfd_PRIVILEGE_CTG 13434 13435 #define MC_CMD_0xfd_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13436 13437 /* MC_CMD_GET_PCIE_RESOURCE_INFO_IN msgrequest */ 13438 #define MC_CMD_GET_PCIE_RESOURCE_INFO_IN_LEN 0 13439 13440 /* MC_CMD_GET_PCIE_RESOURCE_INFO_OUT msgresponse */ 13441 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_LEN 28 13442 /* The maximum number of PFs the device can expose */ 13443 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PFS_OFST 0 13444 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PFS_LEN 4 13445 /* The maximum number of VFs the device can expose in total */ 13446 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VFS_OFST 4 13447 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VFS_LEN 4 13448 /* The maximum number of MSI-X vectors the device can provide in total */ 13449 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VECTORS_OFST 8 13450 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VECTORS_LEN 4 13451 /* the number of MSI-X vectors the device will allocate by default to each PF 13452 */ 13453 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_PF_VECTORS_OFST 12 13454 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_PF_VECTORS_LEN 4 13455 /* the number of MSI-X vectors the device will allocate by default to each VF 13456 */ 13457 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_VF_VECTORS_OFST 16 13458 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_VF_VECTORS_LEN 4 13459 /* the maximum number of MSI-X vectors the device can allocate to any one PF */ 13460 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PF_VECTORS_OFST 20 13461 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PF_VECTORS_LEN 4 13462 /* the maximum number of MSI-X vectors the device can allocate to any one VF */ 13463 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VF_VECTORS_OFST 24 13464 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VF_VECTORS_LEN 4 13465 13466 13467 /***********************************/ 13468 /* MC_CMD_GET_PORT_MODES 13469 * Find out about available port modes 13470 */ 13471 #define MC_CMD_GET_PORT_MODES 0xff 13472 #undef MC_CMD_0xff_PRIVILEGE_CTG 13473 13474 #define MC_CMD_0xff_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13475 13476 /* MC_CMD_GET_PORT_MODES_IN msgrequest */ 13477 #define MC_CMD_GET_PORT_MODES_IN_LEN 0 13478 13479 /* MC_CMD_GET_PORT_MODES_OUT msgresponse */ 13480 #define MC_CMD_GET_PORT_MODES_OUT_LEN 12 13481 /* Bitmask of port modes available on the board (indexed by TLV_PORT_MODE_*) */ 13482 #define MC_CMD_GET_PORT_MODES_OUT_MODES_OFST 0 13483 #define MC_CMD_GET_PORT_MODES_OUT_MODES_LEN 4 13484 /* Default (canonical) board mode */ 13485 #define MC_CMD_GET_PORT_MODES_OUT_DEFAULT_MODE_OFST 4 13486 #define MC_CMD_GET_PORT_MODES_OUT_DEFAULT_MODE_LEN 4 13487 /* Current board mode */ 13488 #define MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST 8 13489 #define MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_LEN 4 13490 13491 13492 /***********************************/ 13493 /* MC_CMD_READ_ATB 13494 * Sample voltages on the ATB 13495 */ 13496 #define MC_CMD_READ_ATB 0x100 13497 #undef MC_CMD_0x100_PRIVILEGE_CTG 13498 13499 #define MC_CMD_0x100_PRIVILEGE_CTG SRIOV_CTG_INSECURE 13500 13501 /* MC_CMD_READ_ATB_IN msgrequest */ 13502 #define MC_CMD_READ_ATB_IN_LEN 16 13503 #define MC_CMD_READ_ATB_IN_SIGNAL_BUS_OFST 0 13504 #define MC_CMD_READ_ATB_IN_SIGNAL_BUS_LEN 4 13505 #define MC_CMD_READ_ATB_IN_BUS_CCOM 0x0 /* enum */ 13506 #define MC_CMD_READ_ATB_IN_BUS_CKR 0x1 /* enum */ 13507 #define MC_CMD_READ_ATB_IN_BUS_CPCIE 0x8 /* enum */ 13508 #define MC_CMD_READ_ATB_IN_SIGNAL_EN_BITNO_OFST 4 13509 #define MC_CMD_READ_ATB_IN_SIGNAL_EN_BITNO_LEN 4 13510 #define MC_CMD_READ_ATB_IN_SIGNAL_SEL_OFST 8 13511 #define MC_CMD_READ_ATB_IN_SIGNAL_SEL_LEN 4 13512 #define MC_CMD_READ_ATB_IN_SETTLING_TIME_US_OFST 12 13513 #define MC_CMD_READ_ATB_IN_SETTLING_TIME_US_LEN 4 13514 13515 /* MC_CMD_READ_ATB_OUT msgresponse */ 13516 #define MC_CMD_READ_ATB_OUT_LEN 4 13517 #define MC_CMD_READ_ATB_OUT_SAMPLE_MV_OFST 0 13518 #define MC_CMD_READ_ATB_OUT_SAMPLE_MV_LEN 4 13519 13520 13521 /***********************************/ 13522 /* MC_CMD_GET_WORKAROUNDS 13523 * Read the list of all implemented and all currently enabled workarounds. The 13524 * enums here must correspond with those in MC_CMD_WORKAROUND. 13525 */ 13526 #define MC_CMD_GET_WORKAROUNDS 0x59 13527 #undef MC_CMD_0x59_PRIVILEGE_CTG 13528 13529 #define MC_CMD_0x59_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13530 13531 /* MC_CMD_GET_WORKAROUNDS_OUT msgresponse */ 13532 #define MC_CMD_GET_WORKAROUNDS_OUT_LEN 8 13533 /* Each workaround is represented by a single bit according to the enums below. 13534 */ 13535 #define MC_CMD_GET_WORKAROUNDS_OUT_IMPLEMENTED_OFST 0 13536 #define MC_CMD_GET_WORKAROUNDS_OUT_IMPLEMENTED_LEN 4 13537 #define MC_CMD_GET_WORKAROUNDS_OUT_ENABLED_OFST 4 13538 #define MC_CMD_GET_WORKAROUNDS_OUT_ENABLED_LEN 4 13539 /* enum: Bug 17230 work around. */ 13540 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG17230 0x2 13541 /* enum: Bug 35388 work around (unsafe EVQ writes). */ 13542 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG35388 0x4 13543 /* enum: Bug35017 workaround (A64 tables must be identity map) */ 13544 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG35017 0x8 13545 /* enum: Bug 41750 present (MC_CMD_TRIGGER_INTERRUPT won't work) */ 13546 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG41750 0x10 13547 /* enum: Bug 42008 present (Interrupts can overtake associated events). Caution 13548 * - before adding code that queries this workaround, remember that there's 13549 * released Monza firmware that doesn't understand MC_CMD_WORKAROUND_BUG42008, 13550 * and will hence (incorrectly) report that the bug doesn't exist. 13551 */ 13552 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG42008 0x20 13553 /* enum: Bug 26807 features present in firmware (multicast filter chaining) */ 13554 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG26807 0x40 13555 /* enum: Bug 61265 work around (broken EVQ TMR writes). */ 13556 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG61265 0x80 13557 13558 13559 /***********************************/ 13560 /* MC_CMD_PRIVILEGE_MASK 13561 * Read/set privileges of an arbitrary PCIe function 13562 */ 13563 #define MC_CMD_PRIVILEGE_MASK 0x5a 13564 #undef MC_CMD_0x5a_PRIVILEGE_CTG 13565 13566 #define MC_CMD_0x5a_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13567 13568 /* MC_CMD_PRIVILEGE_MASK_IN msgrequest */ 13569 #define MC_CMD_PRIVILEGE_MASK_IN_LEN 8 13570 /* The target function to have its mask read or set e.g. PF 0 = 0xFFFF0000, VF 13571 * 1,3 = 0x00030001 13572 */ 13573 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_OFST 0 13574 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_LEN 4 13575 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_PF_LBN 0 13576 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_PF_WIDTH 16 13577 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_VF_LBN 16 13578 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_VF_WIDTH 16 13579 #define MC_CMD_PRIVILEGE_MASK_IN_VF_NULL 0xffff /* enum */ 13580 /* New privilege mask to be set. The mask will only be changed if the MSB is 13581 * set to 1. 13582 */ 13583 #define MC_CMD_PRIVILEGE_MASK_IN_NEW_MASK_OFST 4 13584 #define MC_CMD_PRIVILEGE_MASK_IN_NEW_MASK_LEN 4 13585 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN 0x1 /* enum */ 13586 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_LINK 0x2 /* enum */ 13587 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ONLOAD 0x4 /* enum */ 13588 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_PTP 0x8 /* enum */ 13589 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE_FILTERS 0x10 /* enum */ 13590 /* enum: Deprecated. Equivalent to MAC_SPOOFING_TX combined with CHANGE_MAC. */ 13591 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING 0x20 13592 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_UNICAST 0x40 /* enum */ 13593 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_MULTICAST 0x80 /* enum */ 13594 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_BROADCAST 0x100 /* enum */ 13595 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ALL_MULTICAST 0x200 /* enum */ 13596 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_PROMISCUOUS 0x400 /* enum */ 13597 /* enum: Allows to set the TX packets' source MAC address to any arbitrary MAC 13598 * adress. 13599 */ 13600 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING_TX 0x800 13601 /* enum: Privilege that allows a Function to change the MAC address configured 13602 * in its associated vAdapter/vPort. 13603 */ 13604 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_CHANGE_MAC 0x1000 13605 /* enum: Privilege that allows a Function to install filters that specify VLANs 13606 * that are not in the permit list for the associated vPort. This privilege is 13607 * primarily to support ESX where vPorts are created that restrict traffic to 13608 * only a set of permitted VLANs. See the vPort flag FLAG_VLAN_RESTRICT. 13609 */ 13610 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_UNRESTRICTED_VLAN 0x2000 13611 /* enum: Privilege for insecure commands. Commands that belong to this group 13612 * are not permitted on secure adapters regardless of the privilege mask. 13613 */ 13614 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE 0x4000 13615 /* enum: Set this bit to indicate that a new privilege mask is to be set, 13616 * otherwise the command will only read the existing mask. 13617 */ 13618 #define MC_CMD_PRIVILEGE_MASK_IN_DO_CHANGE 0x80000000 13619 13620 /* MC_CMD_PRIVILEGE_MASK_OUT msgresponse */ 13621 #define MC_CMD_PRIVILEGE_MASK_OUT_LEN 4 13622 /* For an admin function, always all the privileges are reported. */ 13623 #define MC_CMD_PRIVILEGE_MASK_OUT_OLD_MASK_OFST 0 13624 #define MC_CMD_PRIVILEGE_MASK_OUT_OLD_MASK_LEN 4 13625 13626 13627 /***********************************/ 13628 /* MC_CMD_LINK_STATE_MODE 13629 * Read/set link state mode of a VF 13630 */ 13631 #define MC_CMD_LINK_STATE_MODE 0x5c 13632 #undef MC_CMD_0x5c_PRIVILEGE_CTG 13633 13634 #define MC_CMD_0x5c_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13635 13636 /* MC_CMD_LINK_STATE_MODE_IN msgrequest */ 13637 #define MC_CMD_LINK_STATE_MODE_IN_LEN 8 13638 /* The target function to have its link state mode read or set, must be a VF 13639 * e.g. VF 1,3 = 0x00030001 13640 */ 13641 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_OFST 0 13642 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_LEN 4 13643 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_LBN 0 13644 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_WIDTH 16 13645 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_VF_LBN 16 13646 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_VF_WIDTH 16 13647 /* New link state mode to be set */ 13648 #define MC_CMD_LINK_STATE_MODE_IN_NEW_MODE_OFST 4 13649 #define MC_CMD_LINK_STATE_MODE_IN_NEW_MODE_LEN 4 13650 #define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_AUTO 0x0 /* enum */ 13651 #define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_UP 0x1 /* enum */ 13652 #define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_DOWN 0x2 /* enum */ 13653 /* enum: Use this value to just read the existing setting without modifying it. 13654 */ 13655 #define MC_CMD_LINK_STATE_MODE_IN_DO_NOT_CHANGE 0xffffffff 13656 13657 /* MC_CMD_LINK_STATE_MODE_OUT msgresponse */ 13658 #define MC_CMD_LINK_STATE_MODE_OUT_LEN 4 13659 #define MC_CMD_LINK_STATE_MODE_OUT_OLD_MODE_OFST 0 13660 #define MC_CMD_LINK_STATE_MODE_OUT_OLD_MODE_LEN 4 13661 13662 13663 /***********************************/ 13664 /* MC_CMD_GET_SNAPSHOT_LENGTH 13665 * Obtain the current range of allowable values for the SNAPSHOT_LENGTH 13666 * parameter to MC_CMD_INIT_RXQ. 13667 */ 13668 #define MC_CMD_GET_SNAPSHOT_LENGTH 0x101 13669 #undef MC_CMD_0x101_PRIVILEGE_CTG 13670 13671 #define MC_CMD_0x101_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13672 13673 /* MC_CMD_GET_SNAPSHOT_LENGTH_IN msgrequest */ 13674 #define MC_CMD_GET_SNAPSHOT_LENGTH_IN_LEN 0 13675 13676 /* MC_CMD_GET_SNAPSHOT_LENGTH_OUT msgresponse */ 13677 #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_LEN 8 13678 /* Minimum acceptable snapshot length. */ 13679 #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MIN_OFST 0 13680 #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MIN_LEN 4 13681 /* Maximum acceptable snapshot length. */ 13682 #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MAX_OFST 4 13683 #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MAX_LEN 4 13684 13685 13686 /***********************************/ 13687 /* MC_CMD_FUSE_DIAGS 13688 * Additional fuse diagnostics 13689 */ 13690 #define MC_CMD_FUSE_DIAGS 0x102 13691 #undef MC_CMD_0x102_PRIVILEGE_CTG 13692 13693 #define MC_CMD_0x102_PRIVILEGE_CTG SRIOV_CTG_INSECURE 13694 13695 /* MC_CMD_FUSE_DIAGS_IN msgrequest */ 13696 #define MC_CMD_FUSE_DIAGS_IN_LEN 0 13697 13698 /* MC_CMD_FUSE_DIAGS_OUT msgresponse */ 13699 #define MC_CMD_FUSE_DIAGS_OUT_LEN 48 13700 /* Total number of mismatched bits between pairs in area 0 */ 13701 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_MISMATCH_BITS_OFST 0 13702 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_MISMATCH_BITS_LEN 4 13703 /* Total number of unexpectedly clear (set in B but not A) bits in area 0 */ 13704 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_A_BAD_BITS_OFST 4 13705 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_A_BAD_BITS_LEN 4 13706 /* Total number of unexpectedly clear (set in A but not B) bits in area 0 */ 13707 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_B_BAD_BITS_OFST 8 13708 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_B_BAD_BITS_LEN 4 13709 /* Checksum of data after logical OR of pairs in area 0 */ 13710 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_CHECKSUM_OFST 12 13711 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_CHECKSUM_LEN 4 13712 /* Total number of mismatched bits between pairs in area 1 */ 13713 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_MISMATCH_BITS_OFST 16 13714 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_MISMATCH_BITS_LEN 4 13715 /* Total number of unexpectedly clear (set in B but not A) bits in area 1 */ 13716 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_A_BAD_BITS_OFST 20 13717 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_A_BAD_BITS_LEN 4 13718 /* Total number of unexpectedly clear (set in A but not B) bits in area 1 */ 13719 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_B_BAD_BITS_OFST 24 13720 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_B_BAD_BITS_LEN 4 13721 /* Checksum of data after logical OR of pairs in area 1 */ 13722 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_CHECKSUM_OFST 28 13723 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_CHECKSUM_LEN 4 13724 /* Total number of mismatched bits between pairs in area 2 */ 13725 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_MISMATCH_BITS_OFST 32 13726 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_MISMATCH_BITS_LEN 4 13727 /* Total number of unexpectedly clear (set in B but not A) bits in area 2 */ 13728 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_A_BAD_BITS_OFST 36 13729 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_A_BAD_BITS_LEN 4 13730 /* Total number of unexpectedly clear (set in A but not B) bits in area 2 */ 13731 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_B_BAD_BITS_OFST 40 13732 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_B_BAD_BITS_LEN 4 13733 /* Checksum of data after logical OR of pairs in area 2 */ 13734 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_CHECKSUM_OFST 44 13735 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_CHECKSUM_LEN 4 13736 13737 13738 /***********************************/ 13739 /* MC_CMD_PRIVILEGE_MODIFY 13740 * Modify the privileges of a set of PCIe functions. Note that this operation 13741 * only effects non-admin functions unless the admin privilege itself is 13742 * included in one of the masks provided. 13743 */ 13744 #define MC_CMD_PRIVILEGE_MODIFY 0x60 13745 #undef MC_CMD_0x60_PRIVILEGE_CTG 13746 13747 #define MC_CMD_0x60_PRIVILEGE_CTG SRIOV_CTG_ADMIN 13748 13749 /* MC_CMD_PRIVILEGE_MODIFY_IN msgrequest */ 13750 #define MC_CMD_PRIVILEGE_MODIFY_IN_LEN 16 13751 /* The groups of functions to have their privilege masks modified. */ 13752 #define MC_CMD_PRIVILEGE_MODIFY_IN_FN_GROUP_OFST 0 13753 #define MC_CMD_PRIVILEGE_MODIFY_IN_FN_GROUP_LEN 4 13754 #define MC_CMD_PRIVILEGE_MODIFY_IN_NONE 0x0 /* enum */ 13755 #define MC_CMD_PRIVILEGE_MODIFY_IN_ALL 0x1 /* enum */ 13756 #define MC_CMD_PRIVILEGE_MODIFY_IN_PFS_ONLY 0x2 /* enum */ 13757 #define MC_CMD_PRIVILEGE_MODIFY_IN_VFS_ONLY 0x3 /* enum */ 13758 #define MC_CMD_PRIVILEGE_MODIFY_IN_VFS_OF_PF 0x4 /* enum */ 13759 #define MC_CMD_PRIVILEGE_MODIFY_IN_ONE 0x5 /* enum */ 13760 /* For VFS_OF_PF specify the PF, for ONE specify the target function */ 13761 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_OFST 4 13762 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_LEN 4 13763 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_PF_LBN 0 13764 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_PF_WIDTH 16 13765 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_VF_LBN 16 13766 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_VF_WIDTH 16 13767 /* Privileges to be added to the target functions. For privilege definitions 13768 * refer to the command MC_CMD_PRIVILEGE_MASK 13769 */ 13770 #define MC_CMD_PRIVILEGE_MODIFY_IN_ADD_MASK_OFST 8 13771 #define MC_CMD_PRIVILEGE_MODIFY_IN_ADD_MASK_LEN 4 13772 /* Privileges to be removed from the target functions. For privilege 13773 * definitions refer to the command MC_CMD_PRIVILEGE_MASK 13774 */ 13775 #define MC_CMD_PRIVILEGE_MODIFY_IN_REMOVE_MASK_OFST 12 13776 #define MC_CMD_PRIVILEGE_MODIFY_IN_REMOVE_MASK_LEN 4 13777 13778 /* MC_CMD_PRIVILEGE_MODIFY_OUT msgresponse */ 13779 #define MC_CMD_PRIVILEGE_MODIFY_OUT_LEN 0 13780 13781 13782 /***********************************/ 13783 /* MC_CMD_XPM_READ_BYTES 13784 * Read XPM memory 13785 */ 13786 #define MC_CMD_XPM_READ_BYTES 0x103 13787 #undef MC_CMD_0x103_PRIVILEGE_CTG 13788 13789 #define MC_CMD_0x103_PRIVILEGE_CTG SRIOV_CTG_ADMIN 13790 13791 /* MC_CMD_XPM_READ_BYTES_IN msgrequest */ 13792 #define MC_CMD_XPM_READ_BYTES_IN_LEN 8 13793 /* Start address (byte) */ 13794 #define MC_CMD_XPM_READ_BYTES_IN_ADDR_OFST 0 13795 #define MC_CMD_XPM_READ_BYTES_IN_ADDR_LEN 4 13796 /* Count (bytes) */ 13797 #define MC_CMD_XPM_READ_BYTES_IN_COUNT_OFST 4 13798 #define MC_CMD_XPM_READ_BYTES_IN_COUNT_LEN 4 13799 13800 /* MC_CMD_XPM_READ_BYTES_OUT msgresponse */ 13801 #define MC_CMD_XPM_READ_BYTES_OUT_LENMIN 0 13802 #define MC_CMD_XPM_READ_BYTES_OUT_LENMAX 252 13803 #define MC_CMD_XPM_READ_BYTES_OUT_LEN(num) (0+1*(num)) 13804 /* Data */ 13805 #define MC_CMD_XPM_READ_BYTES_OUT_DATA_OFST 0 13806 #define MC_CMD_XPM_READ_BYTES_OUT_DATA_LEN 1 13807 #define MC_CMD_XPM_READ_BYTES_OUT_DATA_MINNUM 0 13808 #define MC_CMD_XPM_READ_BYTES_OUT_DATA_MAXNUM 252 13809 13810 13811 /***********************************/ 13812 /* MC_CMD_XPM_WRITE_BYTES 13813 * Write XPM memory 13814 */ 13815 #define MC_CMD_XPM_WRITE_BYTES 0x104 13816 #undef MC_CMD_0x104_PRIVILEGE_CTG 13817 13818 #define MC_CMD_0x104_PRIVILEGE_CTG SRIOV_CTG_INSECURE 13819 13820 /* MC_CMD_XPM_WRITE_BYTES_IN msgrequest */ 13821 #define MC_CMD_XPM_WRITE_BYTES_IN_LENMIN 8 13822 #define MC_CMD_XPM_WRITE_BYTES_IN_LENMAX 252 13823 #define MC_CMD_XPM_WRITE_BYTES_IN_LEN(num) (8+1*(num)) 13824 /* Start address (byte) */ 13825 #define MC_CMD_XPM_WRITE_BYTES_IN_ADDR_OFST 0 13826 #define MC_CMD_XPM_WRITE_BYTES_IN_ADDR_LEN 4 13827 /* Count (bytes) */ 13828 #define MC_CMD_XPM_WRITE_BYTES_IN_COUNT_OFST 4 13829 #define MC_CMD_XPM_WRITE_BYTES_IN_COUNT_LEN 4 13830 /* Data */ 13831 #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_OFST 8 13832 #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_LEN 1 13833 #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_MINNUM 0 13834 #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_MAXNUM 244 13835 13836 /* MC_CMD_XPM_WRITE_BYTES_OUT msgresponse */ 13837 #define MC_CMD_XPM_WRITE_BYTES_OUT_LEN 0 13838 13839 13840 /***********************************/ 13841 /* MC_CMD_XPM_READ_SECTOR 13842 * Read XPM sector 13843 */ 13844 #define MC_CMD_XPM_READ_SECTOR 0x105 13845 #undef MC_CMD_0x105_PRIVILEGE_CTG 13846 13847 #define MC_CMD_0x105_PRIVILEGE_CTG SRIOV_CTG_INSECURE 13848 13849 /* MC_CMD_XPM_READ_SECTOR_IN msgrequest */ 13850 #define MC_CMD_XPM_READ_SECTOR_IN_LEN 8 13851 /* Sector index */ 13852 #define MC_CMD_XPM_READ_SECTOR_IN_INDEX_OFST 0 13853 #define MC_CMD_XPM_READ_SECTOR_IN_INDEX_LEN 4 13854 /* Sector size */ 13855 #define MC_CMD_XPM_READ_SECTOR_IN_SIZE_OFST 4 13856 #define MC_CMD_XPM_READ_SECTOR_IN_SIZE_LEN 4 13857 13858 /* MC_CMD_XPM_READ_SECTOR_OUT msgresponse */ 13859 #define MC_CMD_XPM_READ_SECTOR_OUT_LENMIN 4 13860 #define MC_CMD_XPM_READ_SECTOR_OUT_LENMAX 36 13861 #define MC_CMD_XPM_READ_SECTOR_OUT_LEN(num) (4+1*(num)) 13862 /* Sector type */ 13863 #define MC_CMD_XPM_READ_SECTOR_OUT_TYPE_OFST 0 13864 #define MC_CMD_XPM_READ_SECTOR_OUT_TYPE_LEN 4 13865 #define MC_CMD_XPM_READ_SECTOR_OUT_BLANK 0x0 /* enum */ 13866 #define MC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_KEY_128 0x1 /* enum */ 13867 #define MC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_KEY_256 0x2 /* enum */ 13868 #define MC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_DATA 0x3 /* enum */ 13869 #define MC_CMD_XPM_READ_SECTOR_OUT_INVALID 0xff /* enum */ 13870 /* Sector data */ 13871 #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_OFST 4 13872 #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_LEN 1 13873 #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_MINNUM 0 13874 #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_MAXNUM 32 13875 13876 13877 /***********************************/ 13878 /* MC_CMD_XPM_WRITE_SECTOR 13879 * Write XPM sector 13880 */ 13881 #define MC_CMD_XPM_WRITE_SECTOR 0x106 13882 #undef MC_CMD_0x106_PRIVILEGE_CTG 13883 13884 #define MC_CMD_0x106_PRIVILEGE_CTG SRIOV_CTG_INSECURE 13885 13886 /* MC_CMD_XPM_WRITE_SECTOR_IN msgrequest */ 13887 #define MC_CMD_XPM_WRITE_SECTOR_IN_LENMIN 12 13888 #define MC_CMD_XPM_WRITE_SECTOR_IN_LENMAX 44 13889 #define MC_CMD_XPM_WRITE_SECTOR_IN_LEN(num) (12+1*(num)) 13890 /* If writing fails due to an uncorrectable error, try up to RETRIES following 13891 * sectors (or until no more space available). If 0, only one write attempt is 13892 * made. Note that uncorrectable errors are unlikely, thanks to XPM self-repair 13893 * mechanism. 13894 */ 13895 #define MC_CMD_XPM_WRITE_SECTOR_IN_RETRIES_OFST 0 13896 #define MC_CMD_XPM_WRITE_SECTOR_IN_RETRIES_LEN 1 13897 #define MC_CMD_XPM_WRITE_SECTOR_IN_RESERVED_OFST 1 13898 #define MC_CMD_XPM_WRITE_SECTOR_IN_RESERVED_LEN 3 13899 /* Sector type */ 13900 #define MC_CMD_XPM_WRITE_SECTOR_IN_TYPE_OFST 4 13901 #define MC_CMD_XPM_WRITE_SECTOR_IN_TYPE_LEN 4 13902 /* Enum values, see field(s): */ 13903 /* MC_CMD_XPM_READ_SECTOR/MC_CMD_XPM_READ_SECTOR_OUT/TYPE */ 13904 /* Sector size */ 13905 #define MC_CMD_XPM_WRITE_SECTOR_IN_SIZE_OFST 8 13906 #define MC_CMD_XPM_WRITE_SECTOR_IN_SIZE_LEN 4 13907 /* Sector data */ 13908 #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_OFST 12 13909 #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_LEN 1 13910 #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_MINNUM 0 13911 #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_MAXNUM 32 13912 13913 /* MC_CMD_XPM_WRITE_SECTOR_OUT msgresponse */ 13914 #define MC_CMD_XPM_WRITE_SECTOR_OUT_LEN 4 13915 /* New sector index */ 13916 #define MC_CMD_XPM_WRITE_SECTOR_OUT_INDEX_OFST 0 13917 #define MC_CMD_XPM_WRITE_SECTOR_OUT_INDEX_LEN 4 13918 13919 13920 /***********************************/ 13921 /* MC_CMD_XPM_INVALIDATE_SECTOR 13922 * Invalidate XPM sector 13923 */ 13924 #define MC_CMD_XPM_INVALIDATE_SECTOR 0x107 13925 #undef MC_CMD_0x107_PRIVILEGE_CTG 13926 13927 #define MC_CMD_0x107_PRIVILEGE_CTG SRIOV_CTG_INSECURE 13928 13929 /* MC_CMD_XPM_INVALIDATE_SECTOR_IN msgrequest */ 13930 #define MC_CMD_XPM_INVALIDATE_SECTOR_IN_LEN 4 13931 /* Sector index */ 13932 #define MC_CMD_XPM_INVALIDATE_SECTOR_IN_INDEX_OFST 0 13933 #define MC_CMD_XPM_INVALIDATE_SECTOR_IN_INDEX_LEN 4 13934 13935 /* MC_CMD_XPM_INVALIDATE_SECTOR_OUT msgresponse */ 13936 #define MC_CMD_XPM_INVALIDATE_SECTOR_OUT_LEN 0 13937 13938 13939 /***********************************/ 13940 /* MC_CMD_XPM_BLANK_CHECK 13941 * Blank-check XPM memory and report bad locations 13942 */ 13943 #define MC_CMD_XPM_BLANK_CHECK 0x108 13944 #undef MC_CMD_0x108_PRIVILEGE_CTG 13945 13946 #define MC_CMD_0x108_PRIVILEGE_CTG SRIOV_CTG_INSECURE 13947 13948 /* MC_CMD_XPM_BLANK_CHECK_IN msgrequest */ 13949 #define MC_CMD_XPM_BLANK_CHECK_IN_LEN 8 13950 /* Start address (byte) */ 13951 #define MC_CMD_XPM_BLANK_CHECK_IN_ADDR_OFST 0 13952 #define MC_CMD_XPM_BLANK_CHECK_IN_ADDR_LEN 4 13953 /* Count (bytes) */ 13954 #define MC_CMD_XPM_BLANK_CHECK_IN_COUNT_OFST 4 13955 #define MC_CMD_XPM_BLANK_CHECK_IN_COUNT_LEN 4 13956 13957 /* MC_CMD_XPM_BLANK_CHECK_OUT msgresponse */ 13958 #define MC_CMD_XPM_BLANK_CHECK_OUT_LENMIN 4 13959 #define MC_CMD_XPM_BLANK_CHECK_OUT_LENMAX 252 13960 #define MC_CMD_XPM_BLANK_CHECK_OUT_LEN(num) (4+2*(num)) 13961 /* Total number of bad (non-blank) locations */ 13962 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_COUNT_OFST 0 13963 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_COUNT_LEN 4 13964 /* Addresses of bad locations (may be less than BAD_COUNT, if all cannot fit 13965 * into MCDI response) 13966 */ 13967 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_OFST 4 13968 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_LEN 2 13969 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_MINNUM 0 13970 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_MAXNUM 124 13971 13972 13973 /***********************************/ 13974 /* MC_CMD_XPM_REPAIR 13975 * Blank-check and repair XPM memory 13976 */ 13977 #define MC_CMD_XPM_REPAIR 0x109 13978 #undef MC_CMD_0x109_PRIVILEGE_CTG 13979 13980 #define MC_CMD_0x109_PRIVILEGE_CTG SRIOV_CTG_INSECURE 13981 13982 /* MC_CMD_XPM_REPAIR_IN msgrequest */ 13983 #define MC_CMD_XPM_REPAIR_IN_LEN 8 13984 /* Start address (byte) */ 13985 #define MC_CMD_XPM_REPAIR_IN_ADDR_OFST 0 13986 #define MC_CMD_XPM_REPAIR_IN_ADDR_LEN 4 13987 /* Count (bytes) */ 13988 #define MC_CMD_XPM_REPAIR_IN_COUNT_OFST 4 13989 #define MC_CMD_XPM_REPAIR_IN_COUNT_LEN 4 13990 13991 /* MC_CMD_XPM_REPAIR_OUT msgresponse */ 13992 #define MC_CMD_XPM_REPAIR_OUT_LEN 0 13993 13994 13995 /***********************************/ 13996 /* MC_CMD_XPM_DECODER_TEST 13997 * Test XPM memory address decoders for gross manufacturing defects. Can only 13998 * be performed on an unprogrammed part. 13999 */ 14000 #define MC_CMD_XPM_DECODER_TEST 0x10a 14001 #undef MC_CMD_0x10a_PRIVILEGE_CTG 14002 14003 #define MC_CMD_0x10a_PRIVILEGE_CTG SRIOV_CTG_INSECURE 14004 14005 /* MC_CMD_XPM_DECODER_TEST_IN msgrequest */ 14006 #define MC_CMD_XPM_DECODER_TEST_IN_LEN 0 14007 14008 /* MC_CMD_XPM_DECODER_TEST_OUT msgresponse */ 14009 #define MC_CMD_XPM_DECODER_TEST_OUT_LEN 0 14010 14011 14012 /***********************************/ 14013 /* MC_CMD_XPM_WRITE_TEST 14014 * XPM memory write test. Test XPM write logic for gross manufacturing defects 14015 * by writing to a dedicated test row. There are 16 locations in the test row 14016 * and the test can only be performed on locations that have not been 14017 * previously used (i.e. can be run at most 16 times). The test will pick the 14018 * first available location to use, or fail with ENOSPC if none left. 14019 */ 14020 #define MC_CMD_XPM_WRITE_TEST 0x10b 14021 #undef MC_CMD_0x10b_PRIVILEGE_CTG 14022 14023 #define MC_CMD_0x10b_PRIVILEGE_CTG SRIOV_CTG_INSECURE 14024 14025 /* MC_CMD_XPM_WRITE_TEST_IN msgrequest */ 14026 #define MC_CMD_XPM_WRITE_TEST_IN_LEN 0 14027 14028 /* MC_CMD_XPM_WRITE_TEST_OUT msgresponse */ 14029 #define MC_CMD_XPM_WRITE_TEST_OUT_LEN 0 14030 14031 14032 /***********************************/ 14033 /* MC_CMD_EXEC_SIGNED 14034 * Check the CMAC of the contents of IMEM and DMEM against the value supplied 14035 * and if correct begin execution from the start of IMEM. The caller supplies a 14036 * key ID, the length of IMEM and DMEM to validate and the expected CMAC. CMAC 14037 * computation runs from the start of IMEM, and from the start of DMEM + 16k, 14038 * to match flash booting. The command will respond with EINVAL if the CMAC 14039 * does match, otherwise it will respond with success before it jumps to IMEM. 14040 */ 14041 #define MC_CMD_EXEC_SIGNED 0x10c 14042 #undef MC_CMD_0x10c_PRIVILEGE_CTG 14043 14044 #define MC_CMD_0x10c_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14045 14046 /* MC_CMD_EXEC_SIGNED_IN msgrequest */ 14047 #define MC_CMD_EXEC_SIGNED_IN_LEN 28 14048 /* the length of code to include in the CMAC */ 14049 #define MC_CMD_EXEC_SIGNED_IN_CODELEN_OFST 0 14050 #define MC_CMD_EXEC_SIGNED_IN_CODELEN_LEN 4 14051 /* the length of date to include in the CMAC */ 14052 #define MC_CMD_EXEC_SIGNED_IN_DATALEN_OFST 4 14053 #define MC_CMD_EXEC_SIGNED_IN_DATALEN_LEN 4 14054 /* the XPM sector containing the key to use */ 14055 #define MC_CMD_EXEC_SIGNED_IN_KEYSECTOR_OFST 8 14056 #define MC_CMD_EXEC_SIGNED_IN_KEYSECTOR_LEN 4 14057 /* the expected CMAC value */ 14058 #define MC_CMD_EXEC_SIGNED_IN_CMAC_OFST 12 14059 #define MC_CMD_EXEC_SIGNED_IN_CMAC_LEN 16 14060 14061 /* MC_CMD_EXEC_SIGNED_OUT msgresponse */ 14062 #define MC_CMD_EXEC_SIGNED_OUT_LEN 0 14063 14064 14065 /***********************************/ 14066 /* MC_CMD_PREPARE_SIGNED 14067 * Prepare to upload a signed image. This will scrub the specified length of 14068 * the data region, which must be at least as large as the DATALEN supplied to 14069 * MC_CMD_EXEC_SIGNED. 14070 */ 14071 #define MC_CMD_PREPARE_SIGNED 0x10d 14072 #undef MC_CMD_0x10d_PRIVILEGE_CTG 14073 14074 #define MC_CMD_0x10d_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14075 14076 /* MC_CMD_PREPARE_SIGNED_IN msgrequest */ 14077 #define MC_CMD_PREPARE_SIGNED_IN_LEN 4 14078 /* the length of data area to clear */ 14079 #define MC_CMD_PREPARE_SIGNED_IN_DATALEN_OFST 0 14080 #define MC_CMD_PREPARE_SIGNED_IN_DATALEN_LEN 4 14081 14082 /* MC_CMD_PREPARE_SIGNED_OUT msgresponse */ 14083 #define MC_CMD_PREPARE_SIGNED_OUT_LEN 0 14084 14085 14086 /***********************************/ 14087 /* MC_CMD_SET_SECURITY_RULE 14088 * Set blacklist and/or whitelist action for a particular match criteria. 14089 * (Medford-only; for use by SolarSecure apps, not directly by drivers. See 14090 * SF-114946-SW.) NOTE - this message definition is provisional. It has not yet 14091 * been used in any released code and may change during development. This note 14092 * will be removed once it is regarded as stable. 14093 */ 14094 #define MC_CMD_SET_SECURITY_RULE 0x10f 14095 #undef MC_CMD_0x10f_PRIVILEGE_CTG 14096 14097 #define MC_CMD_0x10f_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14098 14099 /* MC_CMD_SET_SECURITY_RULE_IN msgrequest */ 14100 #define MC_CMD_SET_SECURITY_RULE_IN_LEN 92 14101 /* fields to include in match criteria */ 14102 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_FIELDS_OFST 0 14103 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_FIELDS_LEN 4 14104 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_IP_LBN 0 14105 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_IP_WIDTH 1 14106 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_IP_LBN 1 14107 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_IP_WIDTH 1 14108 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_MAC_LBN 2 14109 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_MAC_WIDTH 1 14110 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_PORT_LBN 3 14111 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_PORT_WIDTH 1 14112 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_MAC_LBN 4 14113 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_MAC_WIDTH 1 14114 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_PORT_LBN 5 14115 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_PORT_WIDTH 1 14116 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_ETHER_TYPE_LBN 6 14117 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_ETHER_TYPE_WIDTH 1 14118 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_INNER_VLAN_LBN 7 14119 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_INNER_VLAN_WIDTH 1 14120 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_OUTER_VLAN_LBN 8 14121 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_OUTER_VLAN_WIDTH 1 14122 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_IP_PROTO_LBN 9 14123 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_IP_PROTO_WIDTH 1 14124 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_PHYSICAL_PORT_LBN 10 14125 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_PHYSICAL_PORT_WIDTH 1 14126 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_RESERVED_LBN 11 14127 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_RESERVED_WIDTH 1 14128 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_SUBNET_ID_LBN 12 14129 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_SUBNET_ID_WIDTH 1 14130 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_PORTRANGE_ID_LBN 13 14131 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_PORTRANGE_ID_WIDTH 1 14132 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_PORTRANGE_ID_LBN 14 14133 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_PORTRANGE_ID_WIDTH 1 14134 /* remote MAC address to match (as bytes in network order) */ 14135 #define MC_CMD_SET_SECURITY_RULE_IN_REMOTE_MAC_OFST 4 14136 #define MC_CMD_SET_SECURITY_RULE_IN_REMOTE_MAC_LEN 6 14137 /* remote port to match (as bytes in network order) */ 14138 #define MC_CMD_SET_SECURITY_RULE_IN_REMOTE_PORT_OFST 10 14139 #define MC_CMD_SET_SECURITY_RULE_IN_REMOTE_PORT_LEN 2 14140 /* local MAC address to match (as bytes in network order) */ 14141 #define MC_CMD_SET_SECURITY_RULE_IN_LOCAL_MAC_OFST 12 14142 #define MC_CMD_SET_SECURITY_RULE_IN_LOCAL_MAC_LEN 6 14143 /* local port to match (as bytes in network order) */ 14144 #define MC_CMD_SET_SECURITY_RULE_IN_LOCAL_PORT_OFST 18 14145 #define MC_CMD_SET_SECURITY_RULE_IN_LOCAL_PORT_LEN 2 14146 /* Ethernet type to match (as bytes in network order) */ 14147 #define MC_CMD_SET_SECURITY_RULE_IN_ETHER_TYPE_OFST 20 14148 #define MC_CMD_SET_SECURITY_RULE_IN_ETHER_TYPE_LEN 2 14149 /* Inner VLAN tag to match (as bytes in network order) */ 14150 #define MC_CMD_SET_SECURITY_RULE_IN_INNER_VLAN_OFST 22 14151 #define MC_CMD_SET_SECURITY_RULE_IN_INNER_VLAN_LEN 2 14152 /* Outer VLAN tag to match (as bytes in network order) */ 14153 #define MC_CMD_SET_SECURITY_RULE_IN_OUTER_VLAN_OFST 24 14154 #define MC_CMD_SET_SECURITY_RULE_IN_OUTER_VLAN_LEN 2 14155 /* IP protocol to match (in low byte; set high byte to 0) */ 14156 #define MC_CMD_SET_SECURITY_RULE_IN_IP_PROTO_OFST 26 14157 #define MC_CMD_SET_SECURITY_RULE_IN_IP_PROTO_LEN 2 14158 /* Physical port to match (as little-endian 32-bit value) */ 14159 #define MC_CMD_SET_SECURITY_RULE_IN_PHYSICAL_PORT_OFST 28 14160 #define MC_CMD_SET_SECURITY_RULE_IN_PHYSICAL_PORT_LEN 4 14161 /* Reserved; set to 0 */ 14162 #define MC_CMD_SET_SECURITY_RULE_IN_RESERVED_OFST 32 14163 #define MC_CMD_SET_SECURITY_RULE_IN_RESERVED_LEN 4 14164 /* remote IP address to match (as bytes in network order; set last 12 bytes to 14165 * 0 for IPv4 address) 14166 */ 14167 #define MC_CMD_SET_SECURITY_RULE_IN_REMOTE_IP_OFST 36 14168 #define MC_CMD_SET_SECURITY_RULE_IN_REMOTE_IP_LEN 16 14169 /* local IP address to match (as bytes in network order; set last 12 bytes to 0 14170 * for IPv4 address) 14171 */ 14172 #define MC_CMD_SET_SECURITY_RULE_IN_LOCAL_IP_OFST 52 14173 #define MC_CMD_SET_SECURITY_RULE_IN_LOCAL_IP_LEN 16 14174 /* remote subnet ID to match (as little-endian 32-bit value); note that remote 14175 * subnets are matched by mapping the remote IP address to a "subnet ID" via a 14176 * data structure which must already have been configured using 14177 * MC_CMD_SUBNET_MAP_SET_NODE appropriately 14178 */ 14179 #define MC_CMD_SET_SECURITY_RULE_IN_REMOTE_SUBNET_ID_OFST 68 14180 #define MC_CMD_SET_SECURITY_RULE_IN_REMOTE_SUBNET_ID_LEN 4 14181 /* remote portrange ID to match (as little-endian 32-bit value); note that 14182 * remote port ranges are matched by mapping the remote port to a "portrange 14183 * ID" via a data structure which must already have been configured using 14184 * MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE 14185 */ 14186 #define MC_CMD_SET_SECURITY_RULE_IN_REMOTE_PORTRANGE_ID_OFST 72 14187 #define MC_CMD_SET_SECURITY_RULE_IN_REMOTE_PORTRANGE_ID_LEN 4 14188 /* local portrange ID to match (as little-endian 32-bit value); note that local 14189 * port ranges are matched by mapping the local port to a "portrange ID" via a 14190 * data structure which must already have been configured using 14191 * MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE 14192 */ 14193 #define MC_CMD_SET_SECURITY_RULE_IN_LOCAL_PORTRANGE_ID_OFST 76 14194 #define MC_CMD_SET_SECURITY_RULE_IN_LOCAL_PORTRANGE_ID_LEN 4 14195 /* set the action for transmitted packets matching this rule */ 14196 #define MC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_OFST 80 14197 #define MC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_LEN 4 14198 /* enum: make no decision */ 14199 #define MC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_NONE 0x0 14200 /* enum: decide to accept the packet */ 14201 #define MC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_WHITELIST 0x1 14202 /* enum: decide to drop the packet */ 14203 #define MC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_BLACKLIST 0x2 14204 /* enum: inform the TSA controller about some sample of packets matching this 14205 * rule (via MC_CMD_TSA_INFO_IN_PKT_SAMPLE messages); may be bitwise-ORed with 14206 * either the WHITELIST or BLACKLIST action 14207 */ 14208 #define MC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_SAMPLE 0x4 14209 /* enum: do not change the current TX action */ 14210 #define MC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_UNCHANGED 0xffffffff 14211 /* set the action for received packets matching this rule */ 14212 #define MC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_OFST 84 14213 #define MC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_LEN 4 14214 /* enum: make no decision */ 14215 #define MC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_NONE 0x0 14216 /* enum: decide to accept the packet */ 14217 #define MC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_WHITELIST 0x1 14218 /* enum: decide to drop the packet */ 14219 #define MC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_BLACKLIST 0x2 14220 /* enum: inform the TSA controller about some sample of packets matching this 14221 * rule (via MC_CMD_TSA_INFO_IN_PKT_SAMPLE messages); may be bitwise-ORed with 14222 * either the WHITELIST or BLACKLIST action 14223 */ 14224 #define MC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_SAMPLE 0x4 14225 /* enum: do not change the current RX action */ 14226 #define MC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_UNCHANGED 0xffffffff 14227 /* counter ID to associate with this rule; IDs are allocated using 14228 * MC_CMD_SECURITY_RULE_COUNTER_ALLOC 14229 */ 14230 #define MC_CMD_SET_SECURITY_RULE_IN_COUNTER_ID_OFST 88 14231 #define MC_CMD_SET_SECURITY_RULE_IN_COUNTER_ID_LEN 4 14232 /* enum: special value for the null counter ID */ 14233 #define MC_CMD_SET_SECURITY_RULE_IN_COUNTER_ID_NONE 0x0 14234 /* enum: special value to tell the MC to allocate an available counter */ 14235 #define MC_CMD_SET_SECURITY_RULE_IN_COUNTER_ID_SW_AUTO 0xeeeeeeee 14236 /* enum: special value to request use of hardware counter (Medford2 only) */ 14237 #define MC_CMD_SET_SECURITY_RULE_IN_COUNTER_ID_HW 0xffffffff 14238 14239 /* MC_CMD_SET_SECURITY_RULE_OUT msgresponse */ 14240 #define MC_CMD_SET_SECURITY_RULE_OUT_LEN 32 14241 /* new reference count for uses of counter ID */ 14242 #define MC_CMD_SET_SECURITY_RULE_OUT_COUNTER_REFCNT_OFST 0 14243 #define MC_CMD_SET_SECURITY_RULE_OUT_COUNTER_REFCNT_LEN 4 14244 /* constructed match bits for this rule (as a tracing aid only) */ 14245 #define MC_CMD_SET_SECURITY_RULE_OUT_LUE_MATCH_BITS_OFST 4 14246 #define MC_CMD_SET_SECURITY_RULE_OUT_LUE_MATCH_BITS_LEN 12 14247 /* constructed discriminator bits for this rule (as a tracing aid only) */ 14248 #define MC_CMD_SET_SECURITY_RULE_OUT_LUE_DISCRIMINATOR_OFST 16 14249 #define MC_CMD_SET_SECURITY_RULE_OUT_LUE_DISCRIMINATOR_LEN 4 14250 /* base location for probes for this rule (as a tracing aid only) */ 14251 #define MC_CMD_SET_SECURITY_RULE_OUT_LUE_PROBE_BASE_OFST 20 14252 #define MC_CMD_SET_SECURITY_RULE_OUT_LUE_PROBE_BASE_LEN 4 14253 /* step for probes for this rule (as a tracing aid only) */ 14254 #define MC_CMD_SET_SECURITY_RULE_OUT_LUE_PROBE_STEP_OFST 24 14255 #define MC_CMD_SET_SECURITY_RULE_OUT_LUE_PROBE_STEP_LEN 4 14256 /* ID for reading back the counter */ 14257 #define MC_CMD_SET_SECURITY_RULE_OUT_COUNTER_ID_OFST 28 14258 #define MC_CMD_SET_SECURITY_RULE_OUT_COUNTER_ID_LEN 4 14259 14260 14261 /***********************************/ 14262 /* MC_CMD_RESET_SECURITY_RULES 14263 * Reset all blacklist and whitelist actions for a particular physical port, or 14264 * all ports. (Medford-only; for use by SolarSecure apps, not directly by 14265 * drivers. See SF-114946-SW.) NOTE - this message definition is provisional. 14266 * It has not yet been used in any released code and may change during 14267 * development. This note will be removed once it is regarded as stable. 14268 */ 14269 #define MC_CMD_RESET_SECURITY_RULES 0x110 14270 #undef MC_CMD_0x110_PRIVILEGE_CTG 14271 14272 #define MC_CMD_0x110_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14273 14274 /* MC_CMD_RESET_SECURITY_RULES_IN msgrequest */ 14275 #define MC_CMD_RESET_SECURITY_RULES_IN_LEN 4 14276 /* index of physical port to reset (or ALL_PHYSICAL_PORTS to reset all) */ 14277 #define MC_CMD_RESET_SECURITY_RULES_IN_PHYSICAL_PORT_OFST 0 14278 #define MC_CMD_RESET_SECURITY_RULES_IN_PHYSICAL_PORT_LEN 4 14279 /* enum: special value to reset all physical ports */ 14280 #define MC_CMD_RESET_SECURITY_RULES_IN_ALL_PHYSICAL_PORTS 0xffffffff 14281 14282 /* MC_CMD_RESET_SECURITY_RULES_OUT msgresponse */ 14283 #define MC_CMD_RESET_SECURITY_RULES_OUT_LEN 0 14284 14285 14286 /***********************************/ 14287 /* MC_CMD_GET_SECURITY_RULESET_VERSION 14288 * Return a large hash value representing a "version" of the complete set of 14289 * currently active blacklist / whitelist rules and associated data structures. 14290 * (Medford-only; for use by SolarSecure apps, not directly by drivers. See 14291 * SF-114946-SW.) NOTE - this message definition is provisional. It has not yet 14292 * been used in any released code and may change during development. This note 14293 * will be removed once it is regarded as stable. 14294 */ 14295 #define MC_CMD_GET_SECURITY_RULESET_VERSION 0x111 14296 #undef MC_CMD_0x111_PRIVILEGE_CTG 14297 14298 #define MC_CMD_0x111_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14299 14300 /* MC_CMD_GET_SECURITY_RULESET_VERSION_IN msgrequest */ 14301 #define MC_CMD_GET_SECURITY_RULESET_VERSION_IN_LEN 0 14302 14303 /* MC_CMD_GET_SECURITY_RULESET_VERSION_OUT msgresponse */ 14304 #define MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_LENMIN 1 14305 #define MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_LENMAX 252 14306 #define MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_LEN(num) (0+1*(num)) 14307 /* Opaque hash value; length may vary depending on the hash scheme used */ 14308 #define MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_VERSION_OFST 0 14309 #define MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_VERSION_LEN 1 14310 #define MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_VERSION_MINNUM 1 14311 #define MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_VERSION_MAXNUM 252 14312 14313 14314 /***********************************/ 14315 /* MC_CMD_SECURITY_RULE_COUNTER_ALLOC 14316 * Allocate counters for use with blacklist / whitelist rules. (Medford-only; 14317 * for use by SolarSecure apps, not directly by drivers. See SF-114946-SW.) 14318 * NOTE - this message definition is provisional. It has not yet been used in 14319 * any released code and may change during development. This note will be 14320 * removed once it is regarded as stable. 14321 */ 14322 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC 0x112 14323 #undef MC_CMD_0x112_PRIVILEGE_CTG 14324 14325 #define MC_CMD_0x112_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14326 14327 /* MC_CMD_SECURITY_RULE_COUNTER_ALLOC_IN msgrequest */ 14328 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_IN_LEN 4 14329 /* the number of new counter IDs to request */ 14330 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_IN_NUM_COUNTERS_OFST 0 14331 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_IN_NUM_COUNTERS_LEN 4 14332 14333 /* MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT msgresponse */ 14334 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_LENMIN 4 14335 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_LENMAX 252 14336 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_LEN(num) (4+4*(num)) 14337 /* the number of new counter IDs allocated (may be less than the number 14338 * requested if resources are unavailable) 14339 */ 14340 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_NUM_COUNTERS_OFST 0 14341 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_NUM_COUNTERS_LEN 4 14342 /* new counter ID(s) */ 14343 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_COUNTER_ID_OFST 4 14344 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_COUNTER_ID_LEN 4 14345 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_COUNTER_ID_MINNUM 0 14346 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_COUNTER_ID_MAXNUM 62 14347 14348 14349 /***********************************/ 14350 /* MC_CMD_SECURITY_RULE_COUNTER_FREE 14351 * Allocate counters for use with blacklist / whitelist rules. (Medford-only; 14352 * for use by SolarSecure apps, not directly by drivers. See SF-114946-SW.) 14353 * NOTE - this message definition is provisional. It has not yet been used in 14354 * any released code and may change during development. This note will be 14355 * removed once it is regarded as stable. 14356 */ 14357 #define MC_CMD_SECURITY_RULE_COUNTER_FREE 0x113 14358 #undef MC_CMD_0x113_PRIVILEGE_CTG 14359 14360 #define MC_CMD_0x113_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14361 14362 /* MC_CMD_SECURITY_RULE_COUNTER_FREE_IN msgrequest */ 14363 #define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_LENMIN 4 14364 #define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_LENMAX 252 14365 #define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_LEN(num) (4+4*(num)) 14366 /* the number of counter IDs to free */ 14367 #define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_NUM_COUNTERS_OFST 0 14368 #define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_NUM_COUNTERS_LEN 4 14369 /* the counter ID(s) to free */ 14370 #define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_COUNTER_ID_OFST 4 14371 #define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_COUNTER_ID_LEN 4 14372 #define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_COUNTER_ID_MINNUM 0 14373 #define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_COUNTER_ID_MAXNUM 62 14374 14375 /* MC_CMD_SECURITY_RULE_COUNTER_FREE_OUT msgresponse */ 14376 #define MC_CMD_SECURITY_RULE_COUNTER_FREE_OUT_LEN 0 14377 14378 14379 /***********************************/ 14380 /* MC_CMD_SUBNET_MAP_SET_NODE 14381 * Atomically update a trie node in the map of subnets to subnet IDs. The 14382 * constants in the descriptions of the fields of this message may be retrieved 14383 * by the GET_SECURITY_RULE_INFO op of MC_CMD_GET_PARSER_DISP_INFO. (Medford- 14384 * only; for use by SolarSecure apps, not directly by drivers. See 14385 * SF-114946-SW.) NOTE - this message definition is provisional. It has not yet 14386 * been used in any released code and may change during development. This note 14387 * will be removed once it is regarded as stable. 14388 */ 14389 #define MC_CMD_SUBNET_MAP_SET_NODE 0x114 14390 #undef MC_CMD_0x114_PRIVILEGE_CTG 14391 14392 #define MC_CMD_0x114_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14393 14394 /* MC_CMD_SUBNET_MAP_SET_NODE_IN msgrequest */ 14395 #define MC_CMD_SUBNET_MAP_SET_NODE_IN_LENMIN 6 14396 #define MC_CMD_SUBNET_MAP_SET_NODE_IN_LENMAX 252 14397 #define MC_CMD_SUBNET_MAP_SET_NODE_IN_LEN(num) (4+2*(num)) 14398 /* node to update in the range 0 .. SUBNET_MAP_NUM_NODES-1 */ 14399 #define MC_CMD_SUBNET_MAP_SET_NODE_IN_NODE_ID_OFST 0 14400 #define MC_CMD_SUBNET_MAP_SET_NODE_IN_NODE_ID_LEN 4 14401 /* SUBNET_MAP_NUM_ENTRIES_PER_NODE new entries; each entry is either a pointer 14402 * to the next node, expressed as an offset in the trie memory (i.e. node ID 14403 * multiplied by SUBNET_MAP_NUM_ENTRIES_PER_NODE), or a leaf value in the range 14404 * SUBNET_ID_MIN .. SUBNET_ID_MAX 14405 */ 14406 #define MC_CMD_SUBNET_MAP_SET_NODE_IN_ENTRY_OFST 4 14407 #define MC_CMD_SUBNET_MAP_SET_NODE_IN_ENTRY_LEN 2 14408 #define MC_CMD_SUBNET_MAP_SET_NODE_IN_ENTRY_MINNUM 1 14409 #define MC_CMD_SUBNET_MAP_SET_NODE_IN_ENTRY_MAXNUM 124 14410 14411 /* MC_CMD_SUBNET_MAP_SET_NODE_OUT msgresponse */ 14412 #define MC_CMD_SUBNET_MAP_SET_NODE_OUT_LEN 0 14413 14414 /* PORTRANGE_TREE_ENTRY structuredef */ 14415 #define PORTRANGE_TREE_ENTRY_LEN 4 14416 /* key for branch nodes (<= key takes left branch, > key takes right branch), 14417 * or magic value for leaf nodes 14418 */ 14419 #define PORTRANGE_TREE_ENTRY_BRANCH_KEY_OFST 0 14420 #define PORTRANGE_TREE_ENTRY_BRANCH_KEY_LEN 2 14421 #define PORTRANGE_TREE_ENTRY_LEAF_NODE_KEY 0xffff /* enum */ 14422 #define PORTRANGE_TREE_ENTRY_BRANCH_KEY_LBN 0 14423 #define PORTRANGE_TREE_ENTRY_BRANCH_KEY_WIDTH 16 14424 /* final portrange ID for leaf nodes (don't care for branch nodes) */ 14425 #define PORTRANGE_TREE_ENTRY_LEAF_PORTRANGE_ID_OFST 2 14426 #define PORTRANGE_TREE_ENTRY_LEAF_PORTRANGE_ID_LEN 2 14427 #define PORTRANGE_TREE_ENTRY_LEAF_PORTRANGE_ID_LBN 16 14428 #define PORTRANGE_TREE_ENTRY_LEAF_PORTRANGE_ID_WIDTH 16 14429 14430 14431 /***********************************/ 14432 /* MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE 14433 * Atomically update the entire tree mapping remote port ranges to portrange 14434 * IDs. The constants in the descriptions of the fields of this message may be 14435 * retrieved by the GET_SECURITY_RULE_INFO op of MC_CMD_GET_PARSER_DISP_INFO. 14436 * (Medford-only; for use by SolarSecure apps, not directly by drivers. See 14437 * SF-114946-SW.) NOTE - this message definition is provisional. It has not yet 14438 * been used in any released code and may change during development. This note 14439 * will be removed once it is regarded as stable. 14440 */ 14441 #define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE 0x115 14442 #undef MC_CMD_0x115_PRIVILEGE_CTG 14443 14444 #define MC_CMD_0x115_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14445 14446 /* MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN msgrequest */ 14447 #define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN_LENMIN 4 14448 #define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN_LENMAX 252 14449 #define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN_LEN(num) (0+4*(num)) 14450 /* PORTRANGE_TREE_NUM_ENTRIES new entries, each laid out as a 14451 * PORTRANGE_TREE_ENTRY 14452 */ 14453 #define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_OFST 0 14454 #define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_LEN 4 14455 #define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_MINNUM 1 14456 #define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_MAXNUM 63 14457 14458 /* MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_OUT msgresponse */ 14459 #define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_OUT_LEN 0 14460 14461 14462 /***********************************/ 14463 /* MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE 14464 * Atomically update the entire tree mapping remote port ranges to portrange 14465 * IDs. The constants in the descriptions of the fields of this message may be 14466 * retrieved by the GET_SECURITY_RULE_INFO op of MC_CMD_GET_PARSER_DISP_INFO. 14467 * (Medford-only; for use by SolarSecure apps, not directly by drivers. See 14468 * SF-114946-SW.) NOTE - this message definition is provisional. It has not yet 14469 * been used in any released code and may change during development. This note 14470 * will be removed once it is regarded as stable. 14471 */ 14472 #define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE 0x116 14473 #undef MC_CMD_0x116_PRIVILEGE_CTG 14474 14475 #define MC_CMD_0x116_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14476 14477 /* MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN msgrequest */ 14478 #define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN_LENMIN 4 14479 #define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN_LENMAX 252 14480 #define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN_LEN(num) (0+4*(num)) 14481 /* PORTRANGE_TREE_NUM_ENTRIES new entries, each laid out as a 14482 * PORTRANGE_TREE_ENTRY 14483 */ 14484 #define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_OFST 0 14485 #define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_LEN 4 14486 #define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_MINNUM 1 14487 #define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_MAXNUM 63 14488 14489 /* MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_OUT msgresponse */ 14490 #define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_OUT_LEN 0 14491 14492 /* TUNNEL_ENCAP_UDP_PORT_ENTRY structuredef */ 14493 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_LEN 4 14494 /* UDP port (the standard ports are named below but any port may be used) */ 14495 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_OFST 0 14496 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_LEN 2 14497 /* enum: the IANA allocated UDP port for VXLAN */ 14498 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_IANA_VXLAN_UDP_PORT 0x12b5 14499 /* enum: the IANA allocated UDP port for Geneve */ 14500 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_IANA_GENEVE_UDP_PORT 0x17c1 14501 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_LBN 0 14502 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_WIDTH 16 14503 /* tunnel encapsulation protocol (only those named below are supported) */ 14504 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_OFST 2 14505 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_LEN 2 14506 /* enum: This port will be used for VXLAN on both IPv4 and IPv6 */ 14507 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_VXLAN 0x0 14508 /* enum: This port will be used for Geneve on both IPv4 and IPv6 */ 14509 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_GENEVE 0x1 14510 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_LBN 16 14511 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_WIDTH 16 14512 14513 14514 /***********************************/ 14515 /* MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS 14516 * Configure UDP ports for tunnel encapsulation hardware acceleration. The 14517 * parser-dispatcher will attempt to parse traffic on these ports as tunnel 14518 * encapsulation PDUs and filter them using the tunnel encapsulation filter 14519 * chain rather than the standard filter chain. Note that this command can 14520 * cause all functions to see a reset. (Available on Medford only.) 14521 */ 14522 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS 0x117 14523 #undef MC_CMD_0x117_PRIVILEGE_CTG 14524 14525 #define MC_CMD_0x117_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14526 14527 /* MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN msgrequest */ 14528 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMIN 4 14529 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMAX 68 14530 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LEN(num) (4+4*(num)) 14531 /* Flags */ 14532 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_OFST 0 14533 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_LEN 2 14534 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING_LBN 0 14535 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING_WIDTH 1 14536 /* The number of entries in the ENTRIES array */ 14537 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_OFST 2 14538 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_LEN 2 14539 /* Entries defining the UDP port to protocol mapping, each laid out as a 14540 * TUNNEL_ENCAP_UDP_PORT_ENTRY 14541 */ 14542 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_OFST 4 14543 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_LEN 4 14544 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MINNUM 0 14545 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MAXNUM 16 14546 14547 /* MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT msgresponse */ 14548 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_LEN 2 14549 /* Flags */ 14550 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_FLAGS_OFST 0 14551 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_FLAGS_LEN 2 14552 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_LBN 0 14553 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_WIDTH 1 14554 14555 14556 /***********************************/ 14557 /* MC_CMD_RX_BALANCING 14558 * Configure a port upconverter to distribute the packets on both RX engines. 14559 * Packets are distributed based on a table with the destination vFIFO. The 14560 * index of the table is a hash of source and destination of IPV4 and VLAN 14561 * priority. 14562 */ 14563 #define MC_CMD_RX_BALANCING 0x118 14564 #undef MC_CMD_0x118_PRIVILEGE_CTG 14565 14566 #define MC_CMD_0x118_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14567 14568 /* MC_CMD_RX_BALANCING_IN msgrequest */ 14569 #define MC_CMD_RX_BALANCING_IN_LEN 16 14570 /* The RX port whose upconverter table will be modified */ 14571 #define MC_CMD_RX_BALANCING_IN_PORT_OFST 0 14572 #define MC_CMD_RX_BALANCING_IN_PORT_LEN 4 14573 /* The VLAN priority associated to the table index and vFIFO */ 14574 #define MC_CMD_RX_BALANCING_IN_PRIORITY_OFST 4 14575 #define MC_CMD_RX_BALANCING_IN_PRIORITY_LEN 4 14576 /* The resulting bit of SRC^DST for indexing the table */ 14577 #define MC_CMD_RX_BALANCING_IN_SRC_DST_OFST 8 14578 #define MC_CMD_RX_BALANCING_IN_SRC_DST_LEN 4 14579 /* The RX engine to which the vFIFO in the table entry will point to */ 14580 #define MC_CMD_RX_BALANCING_IN_ENG_OFST 12 14581 #define MC_CMD_RX_BALANCING_IN_ENG_LEN 4 14582 14583 /* MC_CMD_RX_BALANCING_OUT msgresponse */ 14584 #define MC_CMD_RX_BALANCING_OUT_LEN 0 14585 14586 14587 /***********************************/ 14588 /* MC_CMD_TSA_BIND 14589 * TSAN - TSAC binding communication protocol. Refer to SF-115479-TC for more 14590 * info in respect to the binding protocol. This MCDI command is only available 14591 * over a TLS secure connection between the TSAN and TSAC, and is not available 14592 * to host software. Note- The messages definitions that do comprise this MCDI 14593 * command deemed as provisional. This MCDI command has not yet been used in 14594 * any released code and may change during development. This note will be 14595 * removed once it is regarded as stable. 14596 */ 14597 #define MC_CMD_TSA_BIND 0x119 14598 #undef MC_CMD_0x119_PRIVILEGE_CTG 14599 14600 #define MC_CMD_0x119_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14601 14602 /* MC_CMD_TSA_BIND_IN msgrequest: Protocol operation code */ 14603 #define MC_CMD_TSA_BIND_IN_LEN 4 14604 #define MC_CMD_TSA_BIND_IN_OP_OFST 0 14605 #define MC_CMD_TSA_BIND_IN_OP_LEN 4 14606 /* enum: Retrieve the TSAN ID from a TSAN. TSAN ID is a unique identifier for 14607 * the network adapter. More specifically, TSAN ID equals the MAC address of 14608 * the network adapter. TSAN ID is used as part of the TSAN authentication 14609 * protocol. Refer to SF-114946-SW for more information. 14610 */ 14611 #define MC_CMD_TSA_BIND_OP_GET_ID 0x1 14612 /* enum: Get a binding ticket from the TSAN. The binding ticket is used as part 14613 * of the binding procedure to authorize the binding of an adapter to a TSAID. 14614 * Refer to SF-114946-SW for more information. 14615 */ 14616 #define MC_CMD_TSA_BIND_OP_GET_TICKET 0x2 14617 /* enum: Opcode associated with the propagation of a private key that TSAN uses 14618 * as part of post-binding authentication procedure. More specifically, TSAN 14619 * uses this key for a signing operation. TSAC uses the counterpart public key 14620 * to verify the signature. Note - The post-binding authentication occurs when 14621 * the TSAN-TSAC connection terminates and TSAN tries to reconnect. Refer to 14622 * SF-114946-SW for more information. 14623 */ 14624 #define MC_CMD_TSA_BIND_OP_SET_KEY 0x3 14625 /* enum: Request an unbinding operation. Note- TSAN clears the binding ticket 14626 * from the Nvram section. Deprecated. Use MC_CMD_TSA_BIND_OP_UNBIND_EXT opcode 14627 * as indicated below. 14628 */ 14629 #define MC_CMD_TSA_BIND_OP_UNBIND 0x4 14630 /* enum: Opcode associated with the propagation of the unbinding ticket data 14631 * blob. The latest SF-115479-TC spec requires a more secure unbinding 14632 * procedure based on unbinding ticket. Note- The previous unbind operation 14633 * based on MC_CMD_TSA_BIND_OP_UNBIND remains in place but now deprecated. 14634 */ 14635 #define MC_CMD_TSA_BIND_OP_UNBIND_EXT 0x5 14636 /* enum: Opcode associated with the propagation of the unbinding secret token. 14637 * TSAN persists the unbinding secret token. Refer to SF-115479-TC for more 14638 * information. 14639 */ 14640 #define MC_CMD_TSA_BIND_OP_SET_UNBINDTOKEN 0x6 14641 /* enum: Request a decommissioning operation. This is to force unbinding the 14642 * adapter. Note- This type of operation comes handy when keys other attributes 14643 * get corrupted at the database level on the controller side and not able to 14644 * unbind the adapter as part of a normal unbind procedure. Note- Refer to 14645 * SF-115479-TC for more information. 14646 */ 14647 #define MC_CMD_TSA_BIND_OP_DECOMMISSION 0x7 14648 /* enum: Request a certificate. */ 14649 #define MC_CMD_TSA_BIND_OP_GET_CERTIFICATE 0x8 14650 14651 /* MC_CMD_TSA_BIND_IN_GET_ID msgrequest */ 14652 #define MC_CMD_TSA_BIND_IN_GET_ID_LEN 20 14653 /* The operation requested. */ 14654 #define MC_CMD_TSA_BIND_IN_GET_ID_OP_OFST 0 14655 #define MC_CMD_TSA_BIND_IN_GET_ID_OP_LEN 4 14656 /* Cryptographic nonce that TSAC generates and sends to TSAN. TSAC generates 14657 * the nonce every time as part of the TSAN post-binding authentication 14658 * procedure when the TSAN-TSAC connection terminates and TSAN does need to re- 14659 * connect to the TSAC. Refer to SF-114946-SW for more information. 14660 */ 14661 #define MC_CMD_TSA_BIND_IN_GET_ID_NONCE_OFST 4 14662 #define MC_CMD_TSA_BIND_IN_GET_ID_NONCE_LEN 16 14663 14664 /* MC_CMD_TSA_BIND_IN_GET_TICKET msgrequest */ 14665 #define MC_CMD_TSA_BIND_IN_GET_TICKET_LEN 4 14666 /* The operation requested. */ 14667 #define MC_CMD_TSA_BIND_IN_GET_TICKET_OP_OFST 0 14668 #define MC_CMD_TSA_BIND_IN_GET_TICKET_OP_LEN 4 14669 14670 /* MC_CMD_TSA_BIND_IN_SET_KEY msgrequest */ 14671 #define MC_CMD_TSA_BIND_IN_SET_KEY_LENMIN 5 14672 #define MC_CMD_TSA_BIND_IN_SET_KEY_LENMAX 252 14673 #define MC_CMD_TSA_BIND_IN_SET_KEY_LEN(num) (4+1*(num)) 14674 /* The operation requested. */ 14675 #define MC_CMD_TSA_BIND_IN_SET_KEY_OP_OFST 0 14676 #define MC_CMD_TSA_BIND_IN_SET_KEY_OP_LEN 4 14677 /* This data blob contains the private key generated by the TSAC. TSAN uses 14678 * this key for a signing operation. Note- This private key is used in 14679 * conjunction with the post-binding TSAN authentication procedure that occurs 14680 * when the TSAN-TSAC connection terminates and TSAN tries to reconnect. Refer 14681 * to SF-114946-SW for more information. 14682 */ 14683 #define MC_CMD_TSA_BIND_IN_SET_KEY_DATKEY_OFST 4 14684 #define MC_CMD_TSA_BIND_IN_SET_KEY_DATKEY_LEN 1 14685 #define MC_CMD_TSA_BIND_IN_SET_KEY_DATKEY_MINNUM 1 14686 #define MC_CMD_TSA_BIND_IN_SET_KEY_DATKEY_MAXNUM 248 14687 14688 /* MC_CMD_TSA_BIND_IN_UNBIND msgrequest: Asks for the un-binding procedure 14689 * Deprecated. Use MC_CMD_TSA_BIND_IN_UNBIND_EXT msgrequest as indicated below. 14690 */ 14691 #define MC_CMD_TSA_BIND_IN_UNBIND_LEN 10 14692 /* The operation requested. */ 14693 #define MC_CMD_TSA_BIND_IN_UNBIND_OP_OFST 0 14694 #define MC_CMD_TSA_BIND_IN_UNBIND_OP_LEN 4 14695 /* TSAN unique identifier for the network adapter */ 14696 #define MC_CMD_TSA_BIND_IN_UNBIND_TSANID_OFST 4 14697 #define MC_CMD_TSA_BIND_IN_UNBIND_TSANID_LEN 6 14698 14699 /* MC_CMD_TSA_BIND_IN_UNBIND_EXT msgrequest: Asks for the un-binding procedure 14700 */ 14701 #define MC_CMD_TSA_BIND_IN_UNBIND_EXT_LENMIN 93 14702 #define MC_CMD_TSA_BIND_IN_UNBIND_EXT_LENMAX 252 14703 #define MC_CMD_TSA_BIND_IN_UNBIND_EXT_LEN(num) (92+1*(num)) 14704 /* The operation requested. */ 14705 #define MC_CMD_TSA_BIND_IN_UNBIND_EXT_OP_OFST 0 14706 #define MC_CMD_TSA_BIND_IN_UNBIND_EXT_OP_LEN 4 14707 /* TSAN unique identifier for the network adapter */ 14708 #define MC_CMD_TSA_BIND_IN_UNBIND_EXT_TSANID_OFST 4 14709 #define MC_CMD_TSA_BIND_IN_UNBIND_EXT_TSANID_LEN 6 14710 /* Align the arguments to 32 bits */ 14711 #define MC_CMD_TSA_BIND_IN_UNBIND_EXT_TSANID_RSVD_OFST 10 14712 #define MC_CMD_TSA_BIND_IN_UNBIND_EXT_TSANID_RSVD_LEN 2 14713 /* This attribute identifies the TSA infrastructure domain. The length of the 14714 * TSAID attribute is limited to 64 bytes. This is how TSA SDK defines the max 14715 * length. Note- The TSAID is the Organizational Unit Name filed as part of the 14716 * root and server certificates. 14717 */ 14718 #define MC_CMD_TSA_BIND_IN_UNBIND_EXT_TSAID_OFST 12 14719 #define MC_CMD_TSA_BIND_IN_UNBIND_EXT_TSAID_LEN 1 14720 #define MC_CMD_TSA_BIND_IN_UNBIND_EXT_TSAID_NUM 64 14721 /* Unbinding secret token. The adapter validates this unbinding token by 14722 * comparing it against the one stored on the adapter as part of the 14723 * MC_CMD_TSA_BIND_IN_SET_UNBINDTOKEN msgrequest. Refer to SF-115479-TC for 14724 * more information. 14725 */ 14726 #define MC_CMD_TSA_BIND_IN_UNBIND_EXT_UNBINDTOKEN_OFST 76 14727 #define MC_CMD_TSA_BIND_IN_UNBIND_EXT_UNBINDTOKEN_LEN 16 14728 /* This is the signature of the above mentioned fields- TSANID, TSAID and 14729 * UNBINDTOKEN. As per current requirements, the SIG opaque data blob contains 14730 * ECDSA ECC-384 based signature. The ECC curve is secp384r1. The signature is 14731 * also ASN-1 encoded. Note- The signature is verified based on the public key 14732 * stored into the root certificate that is provisioned on the adapter side. 14733 * This key is known as the PUKtsaid. Refer to SF-115479-TC for more 14734 * information. 14735 */ 14736 #define MC_CMD_TSA_BIND_IN_UNBIND_EXT_SIG_OFST 92 14737 #define MC_CMD_TSA_BIND_IN_UNBIND_EXT_SIG_LEN 1 14738 #define MC_CMD_TSA_BIND_IN_UNBIND_EXT_SIG_MINNUM 1 14739 #define MC_CMD_TSA_BIND_IN_UNBIND_EXT_SIG_MAXNUM 160 14740 14741 /* MC_CMD_TSA_BIND_IN_SET_UNBINDTOKEN msgrequest */ 14742 #define MC_CMD_TSA_BIND_IN_SET_UNBINDTOKEN_LEN 20 14743 /* The operation requested. */ 14744 #define MC_CMD_TSA_BIND_IN_SET_UNBINDTOKEN_OP_OFST 0 14745 #define MC_CMD_TSA_BIND_IN_SET_UNBINDTOKEN_OP_LEN 4 14746 /* Unbinding secret token. TSAN persists the unbinding secret token. Refer to 14747 * SF-115479-TC for more information. 14748 */ 14749 #define MC_CMD_TSA_BIND_IN_SET_UNBINDTOKEN_UNBINDTOKEN_OFST 4 14750 #define MC_CMD_TSA_BIND_IN_SET_UNBINDTOKEN_UNBINDTOKEN_LEN 16 14751 /* enum: There are situations when the binding process does not complete 14752 * successfully due to key, other attributes corruption at the database level 14753 * (Controller). Adapter can't connect to the controller anymore. To recover, 14754 * make usage of the decommission command that forces the adapter into 14755 * unbinding state. 14756 */ 14757 #define MC_CMD_TSA_BIND_IN_SET_UNBINDTOKEN_ADAPTER_BINDING_FAILURE 0x1 14758 14759 /* MC_CMD_TSA_BIND_IN_DECOMMISSION msgrequest: Asks for the decommissioning 14760 * procedure 14761 */ 14762 #define MC_CMD_TSA_BIND_IN_DECOMMISSION_LENMIN 109 14763 #define MC_CMD_TSA_BIND_IN_DECOMMISSION_LENMAX 252 14764 #define MC_CMD_TSA_BIND_IN_DECOMMISSION_LEN(num) (108+1*(num)) 14765 /* This is the signature of the above mentioned fields- TSAID, USER and REASON. 14766 * As per current requirements, the SIG opaque data blob contains ECDSA ECC-384 14767 * based signature. The ECC curve is secp384r1. The signature is also ASN-1 14768 * encoded . Note- The signature is verified based on the public key stored 14769 * into the root certificate that is provisioned on the adapter side. This key 14770 * is known as the PUKtsaid. Refer to SF-115479-TC for more information. 14771 */ 14772 #define MC_CMD_TSA_BIND_IN_DECOMMISSION_SIG_OFST 108 14773 #define MC_CMD_TSA_BIND_IN_DECOMMISSION_SIG_LEN 1 14774 #define MC_CMD_TSA_BIND_IN_DECOMMISSION_SIG_MINNUM 1 14775 #define MC_CMD_TSA_BIND_IN_DECOMMISSION_SIG_MAXNUM 144 14776 /* The operation requested. */ 14777 #define MC_CMD_TSA_BIND_IN_DECOMMISSION_OP_OFST 0 14778 #define MC_CMD_TSA_BIND_IN_DECOMMISSION_OP_LEN 4 14779 /* This attribute identifies the TSA infrastructure domain. The length of the 14780 * TSAID attribute is limited to 64 bytes. This is how TSA SDK defines the max 14781 * length. Note- The TSAID is the Organizational Unit Name filed as part of the 14782 * root and server certificates. 14783 */ 14784 #define MC_CMD_TSA_BIND_IN_DECOMMISSION_TSAID_OFST 4 14785 #define MC_CMD_TSA_BIND_IN_DECOMMISSION_TSAID_LEN 1 14786 #define MC_CMD_TSA_BIND_IN_DECOMMISSION_TSAID_NUM 64 14787 /* User ID that comes, as an example, from the Controller. Note- The 33 byte 14788 * length of this attribute is max length of the linux user name plus null 14789 * character. 14790 */ 14791 #define MC_CMD_TSA_BIND_IN_DECOMMISSION_USER_OFST 68 14792 #define MC_CMD_TSA_BIND_IN_DECOMMISSION_USER_LEN 1 14793 #define MC_CMD_TSA_BIND_IN_DECOMMISSION_USER_NUM 33 14794 /* Align the arguments to 32 bits */ 14795 #define MC_CMD_TSA_BIND_IN_DECOMMISSION_USER_RSVD_OFST 101 14796 #define MC_CMD_TSA_BIND_IN_DECOMMISSION_USER_RSVD_LEN 3 14797 /* Reason of why decommissioning happens Note- The list of reasons, defined as 14798 * part of the enumeration below, can be extended. 14799 */ 14800 #define MC_CMD_TSA_BIND_IN_DECOMMISSION_REASON_OFST 104 14801 #define MC_CMD_TSA_BIND_IN_DECOMMISSION_REASON_LEN 4 14802 14803 /* MC_CMD_TSA_BIND_IN_GET_CERTIFICATE msgrequest: Request a certificate. */ 14804 #define MC_CMD_TSA_BIND_IN_GET_CERTIFICATE_LEN 8 14805 /* The operation requested, must be MC_CMD_TSA_BIND_OP_GET_CERTIFICATE. */ 14806 #define MC_CMD_TSA_BIND_IN_GET_CERTIFICATE_OP_OFST 0 14807 #define MC_CMD_TSA_BIND_IN_GET_CERTIFICATE_OP_LEN 4 14808 /* Type of the certificate to be retrieved. */ 14809 #define MC_CMD_TSA_BIND_IN_GET_CERTIFICATE_TYPE_OFST 4 14810 #define MC_CMD_TSA_BIND_IN_GET_CERTIFICATE_TYPE_LEN 4 14811 #define MC_CMD_TSA_BIND_IN_GET_CERTIFICATE_UNUSED 0x0 /* enum */ 14812 /* enum: Adapter Authentication Certificate (AAC). The AAC is used by the 14813 * controller to verify the authenticity of the adapter. 14814 */ 14815 #define MC_CMD_TSA_BIND_IN_GET_CERTIFICATE_AAC 0x1 14816 /* enum: Adapter Authentication Signing Certificate (AASC). The AASC is used by 14817 * the controller to verify the validity of AAC. 14818 */ 14819 #define MC_CMD_TSA_BIND_IN_GET_CERTIFICATE_AASC 0x2 14820 14821 /* MC_CMD_TSA_BIND_OUT_GET_ID msgresponse */ 14822 #define MC_CMD_TSA_BIND_OUT_GET_ID_LENMIN 15 14823 #define MC_CMD_TSA_BIND_OUT_GET_ID_LENMAX 252 14824 #define MC_CMD_TSA_BIND_OUT_GET_ID_LEN(num) (14+1*(num)) 14825 /* The protocol operation code MC_CMD_TSA_BIND_OP_GET_ID that is sent back to 14826 * the caller. 14827 */ 14828 #define MC_CMD_TSA_BIND_OUT_GET_ID_OP_OFST 0 14829 #define MC_CMD_TSA_BIND_OUT_GET_ID_OP_LEN 4 14830 /* Rules engine type. Note- The rules engine type allows TSAC to further 14831 * identify the connected endpoint (e.g. TSAN, NIC Emulator) type and take the 14832 * proper action accordingly. As an example, TSAC uses the rules engine type to 14833 * select the SF key that differs in the case of TSAN vs. NIC Emulator. 14834 */ 14835 #define MC_CMD_TSA_BIND_OUT_GET_ID_RULE_ENGINE_OFST 4 14836 #define MC_CMD_TSA_BIND_OUT_GET_ID_RULE_ENGINE_LEN 4 14837 /* enum: Hardware rules engine. */ 14838 #define MC_CMD_TSA_BIND_OUT_GET_ID_RULE_ENGINE_TSAN 0x1 14839 /* enum: Nic emulator rules engine. */ 14840 #define MC_CMD_TSA_BIND_OUT_GET_ID_RULE_ENGINE_NEMU 0x2 14841 /* enum: SSFE. */ 14842 #define MC_CMD_TSA_BIND_OUT_GET_ID_RULE_ENGINE_SSFE 0x3 14843 /* TSAN unique identifier for the network adapter */ 14844 #define MC_CMD_TSA_BIND_OUT_GET_ID_TSANID_OFST 8 14845 #define MC_CMD_TSA_BIND_OUT_GET_ID_TSANID_LEN 6 14846 /* The signature data blob. The signature is computed against the message 14847 * formed by TSAN ID concatenated with the NONCE value. Refer to SF-115479-TC 14848 * for more information also in respect to the private keys that are used to 14849 * sign the message based on TSAN pre/post-binding authentication procedure. 14850 */ 14851 #define MC_CMD_TSA_BIND_OUT_GET_ID_SIG_OFST 14 14852 #define MC_CMD_TSA_BIND_OUT_GET_ID_SIG_LEN 1 14853 #define MC_CMD_TSA_BIND_OUT_GET_ID_SIG_MINNUM 1 14854 #define MC_CMD_TSA_BIND_OUT_GET_ID_SIG_MAXNUM 238 14855 14856 /* MC_CMD_TSA_BIND_OUT_GET_TICKET msgresponse */ 14857 #define MC_CMD_TSA_BIND_OUT_GET_TICKET_LENMIN 5 14858 #define MC_CMD_TSA_BIND_OUT_GET_TICKET_LENMAX 252 14859 #define MC_CMD_TSA_BIND_OUT_GET_TICKET_LEN(num) (4+1*(num)) 14860 /* The protocol operation code MC_CMD_TSA_BIND_OP_GET_TICKET that is sent back 14861 * to the caller. 14862 */ 14863 #define MC_CMD_TSA_BIND_OUT_GET_TICKET_OP_OFST 0 14864 #define MC_CMD_TSA_BIND_OUT_GET_TICKET_OP_LEN 4 14865 /* The ticket represents the data blob construct that TSAN sends to TSAC as 14866 * part of the binding protocol. From the TSAN perspective the ticket is an 14867 * opaque construct. For more info refer to SF-115479-TC. 14868 */ 14869 #define MC_CMD_TSA_BIND_OUT_GET_TICKET_TICKET_OFST 4 14870 #define MC_CMD_TSA_BIND_OUT_GET_TICKET_TICKET_LEN 1 14871 #define MC_CMD_TSA_BIND_OUT_GET_TICKET_TICKET_MINNUM 1 14872 #define MC_CMD_TSA_BIND_OUT_GET_TICKET_TICKET_MAXNUM 248 14873 14874 /* MC_CMD_TSA_BIND_OUT_SET_KEY msgresponse */ 14875 #define MC_CMD_TSA_BIND_OUT_SET_KEY_LEN 4 14876 /* The protocol operation code MC_CMD_TSA_BIND_OP_SET_KEY that is sent back to 14877 * the caller. 14878 */ 14879 #define MC_CMD_TSA_BIND_OUT_SET_KEY_OP_OFST 0 14880 #define MC_CMD_TSA_BIND_OUT_SET_KEY_OP_LEN 4 14881 14882 /* MC_CMD_TSA_BIND_OUT_UNBIND msgresponse: Response to insecure unbind request. 14883 */ 14884 #define MC_CMD_TSA_BIND_OUT_UNBIND_LEN 8 14885 /* Same as MC_CMD_ERR field, but included as 0 in success cases */ 14886 #define MC_CMD_TSA_BIND_OUT_UNBIND_RESULT_OFST 0 14887 #define MC_CMD_TSA_BIND_OUT_UNBIND_RESULT_LEN 4 14888 /* Extra status information */ 14889 #define MC_CMD_TSA_BIND_OUT_UNBIND_INFO_OFST 4 14890 #define MC_CMD_TSA_BIND_OUT_UNBIND_INFO_LEN 4 14891 /* enum: Unbind successful. */ 14892 #define MC_CMD_TSA_BIND_OUT_UNBIND_OK_UNBOUND 0x0 14893 /* enum: TSANID mismatch */ 14894 #define MC_CMD_TSA_BIND_OUT_UNBIND_ERR_BAD_TSANID 0x1 14895 /* enum: Unable to remove the binding ticket from persistent storage. */ 14896 #define MC_CMD_TSA_BIND_OUT_UNBIND_ERR_REMOVE_TICKET 0x2 14897 /* enum: TSAN is not bound to a binding ticket. */ 14898 #define MC_CMD_TSA_BIND_OUT_UNBIND_ERR_NOT_BOUND 0x3 14899 14900 /* MC_CMD_TSA_BIND_OUT_UNBIND_EXT msgresponse: Response to secure unbind 14901 * request. (Note! This has same fields as insecure unbind response but is a 14902 * response to a different command.) 14903 */ 14904 #define MC_CMD_TSA_BIND_OUT_UNBIND_EXT_LEN 8 14905 /* Same as MC_CMD_ERR field, but included as 0 in success cases */ 14906 #define MC_CMD_TSA_BIND_OUT_UNBIND_EXT_RESULT_OFST 0 14907 #define MC_CMD_TSA_BIND_OUT_UNBIND_EXT_RESULT_LEN 4 14908 /* Extra status information */ 14909 #define MC_CMD_TSA_BIND_OUT_UNBIND_EXT_INFO_OFST 4 14910 #define MC_CMD_TSA_BIND_OUT_UNBIND_EXT_INFO_LEN 4 14911 /* enum: Unbind successful. */ 14912 #define MC_CMD_TSA_BIND_OUT_UNBIND_EXT_OK_UNBOUND 0x0 14913 /* enum: TSANID mismatch */ 14914 #define MC_CMD_TSA_BIND_OUT_UNBIND_EXT_ERR_BAD_TSANID 0x1 14915 /* enum: Unable to remove the binding ticket from persistent storage. */ 14916 #define MC_CMD_TSA_BIND_OUT_UNBIND_EXT_ERR_REMOVE_TICKET 0x2 14917 /* enum: TSAN is not bound to a binding ticket. */ 14918 #define MC_CMD_TSA_BIND_OUT_UNBIND_EXT_ERR_NOT_BOUND 0x3 14919 /* enum: Invalid unbind token */ 14920 #define MC_CMD_TSA_BIND_OUT_UNBIND_EXT_ERR_BAD_TOKEN 0x4 14921 /* enum: Invalid signature */ 14922 #define MC_CMD_TSA_BIND_OUT_UNBIND_EXT_ERR_BAD_SIGNATURE 0x5 14923 14924 /* MC_CMD_TSA_BIND_OUT_SET_UNBINDTOKEN msgresponse */ 14925 #define MC_CMD_TSA_BIND_OUT_SET_UNBINDTOKEN_LEN 4 14926 /* The protocol operation code MC_CMD_TSA_BIND_OP_SET_UNBINDTOKEN that is sent 14927 * back to the caller. 14928 */ 14929 #define MC_CMD_TSA_BIND_OUT_SET_UNBINDTOKEN_OP_OFST 0 14930 #define MC_CMD_TSA_BIND_OUT_SET_UNBINDTOKEN_OP_LEN 4 14931 14932 /* MC_CMD_TSA_BIND_OUT_DECOMMISSION msgresponse */ 14933 #define MC_CMD_TSA_BIND_OUT_DECOMMISSION_LEN 4 14934 /* The protocol operation code MC_CMD_TSA_BIND_OP_DECOMMISSION that is sent 14935 * back to the caller. 14936 */ 14937 #define MC_CMD_TSA_BIND_OUT_DECOMMISSION_OP_OFST 0 14938 #define MC_CMD_TSA_BIND_OUT_DECOMMISSION_OP_LEN 4 14939 14940 /* MC_CMD_TSA_BIND_OUT_GET_CERTIFICATE msgresponse */ 14941 #define MC_CMD_TSA_BIND_OUT_GET_CERTIFICATE_LENMIN 9 14942 #define MC_CMD_TSA_BIND_OUT_GET_CERTIFICATE_LENMAX 252 14943 #define MC_CMD_TSA_BIND_OUT_GET_CERTIFICATE_LEN(num) (8+1*(num)) 14944 /* The protocol operation code MC_CMD_TSA_BIND_OP_GET_CERTIFICATE that is sent 14945 * back to the caller. 14946 */ 14947 #define MC_CMD_TSA_BIND_OUT_GET_CERTIFICATE_OP_OFST 0 14948 #define MC_CMD_TSA_BIND_OUT_GET_CERTIFICATE_OP_LEN 4 14949 /* Type of the certificate. */ 14950 #define MC_CMD_TSA_BIND_OUT_GET_CERTIFICATE_TYPE_OFST 4 14951 #define MC_CMD_TSA_BIND_OUT_GET_CERTIFICATE_TYPE_LEN 4 14952 /* Enum values, see field(s): */ 14953 /* MC_CMD_TSA_BIND_IN_GET_CERTIFICATE/TYPE */ 14954 /* The certificate data. */ 14955 #define MC_CMD_TSA_BIND_OUT_GET_CERTIFICATE_DATA_OFST 8 14956 #define MC_CMD_TSA_BIND_OUT_GET_CERTIFICATE_DATA_LEN 1 14957 #define MC_CMD_TSA_BIND_OUT_GET_CERTIFICATE_DATA_MINNUM 1 14958 #define MC_CMD_TSA_BIND_OUT_GET_CERTIFICATE_DATA_MAXNUM 244 14959 14960 14961 /***********************************/ 14962 /* MC_CMD_MANAGE_SECURITY_RULESET_CACHE 14963 * Manage the persistent NVRAM cache of security rules created with 14964 * MC_CMD_SET_SECURITY_RULE. Note that the cache is not automatically updated 14965 * as rules are added or removed; the active ruleset must be explicitly 14966 * committed to the cache. The cache may also be explicitly invalidated, 14967 * without affecting the currently active ruleset. When the cache is valid, it 14968 * will be loaded at power on or MC reboot, instead of the default ruleset. 14969 * Rollback of the currently active ruleset to the cached version (when it is 14970 * valid) is also supported. (Medford-only; for use by SolarSecure apps, not 14971 * directly by drivers. See SF-114946-SW.) NOTE - this message definition is 14972 * provisional. It has not yet been used in any released code and may change 14973 * during development. This note will be removed once it is regarded as stable. 14974 */ 14975 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE 0x11a 14976 #undef MC_CMD_0x11a_PRIVILEGE_CTG 14977 14978 #define MC_CMD_0x11a_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14979 14980 /* MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN msgrequest */ 14981 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_LEN 4 14982 /* the operation to perform */ 14983 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_OP_OFST 0 14984 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_OP_LEN 4 14985 /* enum: reports the ruleset version that is cached in persistent storage but 14986 * performs no other action 14987 */ 14988 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_OP_GET_CACHED_VERSION 0x0 14989 /* enum: rolls back the active state to the cached version. (May fail with 14990 * ENOENT if there is no valid cached version.) 14991 */ 14992 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_OP_ROLLBACK 0x1 14993 /* enum: commits the active state to the persistent cache */ 14994 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_OP_COMMIT 0x2 14995 /* enum: invalidates the persistent cache without affecting the active state */ 14996 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_OP_INVALIDATE 0x3 14997 14998 /* MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT msgresponse */ 14999 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_LENMIN 5 15000 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_LENMAX 252 15001 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_LEN(num) (4+1*(num)) 15002 /* indicates whether the persistent cache is valid (after completion of the 15003 * requested operation in the case of rollback, commit, or invalidate) 15004 */ 15005 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_STATE_OFST 0 15006 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_STATE_LEN 4 15007 /* enum: persistent cache is invalid (the VERSION field will be empty in this 15008 * case) 15009 */ 15010 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_STATE_INVALID 0x0 15011 /* enum: persistent cache is valid */ 15012 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_STATE_VALID 0x1 15013 /* cached ruleset version (after completion of the requested operation, in the 15014 * case of rollback, commit, or invalidate) as an opaque hash value in the same 15015 * form as MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_VERSION 15016 */ 15017 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_VERSION_OFST 4 15018 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_VERSION_LEN 1 15019 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_VERSION_MINNUM 1 15020 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_VERSION_MAXNUM 248 15021 15022 15023 /***********************************/ 15024 /* MC_CMD_NVRAM_PRIVATE_APPEND 15025 * Append a single TLV to the MC_USAGE_TLV partition. Returns MC_CMD_ERR_EEXIST 15026 * if the tag is already present. 15027 */ 15028 #define MC_CMD_NVRAM_PRIVATE_APPEND 0x11c 15029 #undef MC_CMD_0x11c_PRIVILEGE_CTG 15030 15031 #define MC_CMD_0x11c_PRIVILEGE_CTG SRIOV_CTG_ADMIN 15032 15033 /* MC_CMD_NVRAM_PRIVATE_APPEND_IN msgrequest */ 15034 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_LENMIN 9 15035 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_LENMAX 252 15036 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_LEN(num) (8+1*(num)) 15037 /* The tag to be appended */ 15038 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_TAG_OFST 0 15039 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_TAG_LEN 4 15040 /* The length of the data */ 15041 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_LENGTH_OFST 4 15042 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_LENGTH_LEN 4 15043 /* The data to be contained in the TLV structure */ 15044 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_OFST 8 15045 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_LEN 1 15046 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_MINNUM 1 15047 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_MAXNUM 244 15048 15049 /* MC_CMD_NVRAM_PRIVATE_APPEND_OUT msgresponse */ 15050 #define MC_CMD_NVRAM_PRIVATE_APPEND_OUT_LEN 0 15051 15052 15053 /***********************************/ 15054 /* MC_CMD_XPM_VERIFY_CONTENTS 15055 * Verify that the contents of the XPM memory is correct (Medford only). This 15056 * is used during manufacture to check that the XPM memory has been programmed 15057 * correctly at ATE. 15058 */ 15059 #define MC_CMD_XPM_VERIFY_CONTENTS 0x11b 15060 #undef MC_CMD_0x11b_PRIVILEGE_CTG 15061 15062 #define MC_CMD_0x11b_PRIVILEGE_CTG SRIOV_CTG_ADMIN 15063 15064 /* MC_CMD_XPM_VERIFY_CONTENTS_IN msgrequest */ 15065 #define MC_CMD_XPM_VERIFY_CONTENTS_IN_LEN 4 15066 /* Data type to be checked */ 15067 #define MC_CMD_XPM_VERIFY_CONTENTS_IN_DATA_TYPE_OFST 0 15068 #define MC_CMD_XPM_VERIFY_CONTENTS_IN_DATA_TYPE_LEN 4 15069 15070 /* MC_CMD_XPM_VERIFY_CONTENTS_OUT msgresponse */ 15071 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_LENMIN 12 15072 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_LENMAX 252 15073 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_LEN(num) (12+1*(num)) 15074 /* Number of sectors found (test builds only) */ 15075 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_NUM_SECTORS_OFST 0 15076 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_NUM_SECTORS_LEN 4 15077 /* Number of bytes found (test builds only) */ 15078 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_NUM_BYTES_OFST 4 15079 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_NUM_BYTES_LEN 4 15080 /* Length of signature */ 15081 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIG_LENGTH_OFST 8 15082 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIG_LENGTH_LEN 4 15083 /* Signature */ 15084 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_OFST 12 15085 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_LEN 1 15086 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_MINNUM 0 15087 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_MAXNUM 240 15088 15089 15090 /***********************************/ 15091 /* MC_CMD_SET_EVQ_TMR 15092 * Update the timer load, timer reload and timer mode values for a given EVQ. 15093 * The requested timer values (in TMR_LOAD_REQ_NS and TMR_RELOAD_REQ_NS) will 15094 * be rounded up to the granularity supported by the hardware, then truncated 15095 * to the range supported by the hardware. The resulting value after the 15096 * rounding and truncation will be returned to the caller (in TMR_LOAD_ACT_NS 15097 * and TMR_RELOAD_ACT_NS). 15098 */ 15099 #define MC_CMD_SET_EVQ_TMR 0x120 15100 #undef MC_CMD_0x120_PRIVILEGE_CTG 15101 15102 #define MC_CMD_0x120_PRIVILEGE_CTG SRIOV_CTG_GENERAL 15103 15104 /* MC_CMD_SET_EVQ_TMR_IN msgrequest */ 15105 #define MC_CMD_SET_EVQ_TMR_IN_LEN 16 15106 /* Function-relative queue instance */ 15107 #define MC_CMD_SET_EVQ_TMR_IN_INSTANCE_OFST 0 15108 #define MC_CMD_SET_EVQ_TMR_IN_INSTANCE_LEN 4 15109 /* Requested value for timer load (in nanoseconds) */ 15110 #define MC_CMD_SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS_OFST 4 15111 #define MC_CMD_SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS_LEN 4 15112 /* Requested value for timer reload (in nanoseconds) */ 15113 #define MC_CMD_SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS_OFST 8 15114 #define MC_CMD_SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS_LEN 4 15115 /* Timer mode. Meanings as per EVQ_TMR_REG.TC_TIMER_VAL */ 15116 #define MC_CMD_SET_EVQ_TMR_IN_TMR_MODE_OFST 12 15117 #define MC_CMD_SET_EVQ_TMR_IN_TMR_MODE_LEN 4 15118 #define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_DIS 0x0 /* enum */ 15119 #define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_IMMED_START 0x1 /* enum */ 15120 #define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_TRIG_START 0x2 /* enum */ 15121 #define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_INT_HLDOFF 0x3 /* enum */ 15122 15123 /* MC_CMD_SET_EVQ_TMR_OUT msgresponse */ 15124 #define MC_CMD_SET_EVQ_TMR_OUT_LEN 8 15125 /* Actual value for timer load (in nanoseconds) */ 15126 #define MC_CMD_SET_EVQ_TMR_OUT_TMR_LOAD_ACT_NS_OFST 0 15127 #define MC_CMD_SET_EVQ_TMR_OUT_TMR_LOAD_ACT_NS_LEN 4 15128 /* Actual value for timer reload (in nanoseconds) */ 15129 #define MC_CMD_SET_EVQ_TMR_OUT_TMR_RELOAD_ACT_NS_OFST 4 15130 #define MC_CMD_SET_EVQ_TMR_OUT_TMR_RELOAD_ACT_NS_LEN 4 15131 15132 15133 /***********************************/ 15134 /* MC_CMD_GET_EVQ_TMR_PROPERTIES 15135 * Query properties about the event queue timers. 15136 */ 15137 #define MC_CMD_GET_EVQ_TMR_PROPERTIES 0x122 15138 #undef MC_CMD_0x122_PRIVILEGE_CTG 15139 15140 #define MC_CMD_0x122_PRIVILEGE_CTG SRIOV_CTG_GENERAL 15141 15142 /* MC_CMD_GET_EVQ_TMR_PROPERTIES_IN msgrequest */ 15143 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_IN_LEN 0 15144 15145 /* MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT msgresponse */ 15146 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN 36 15147 /* Reserved for future use. */ 15148 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_FLAGS_OFST 0 15149 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_FLAGS_LEN 4 15150 /* For timers updated via writes to EVQ_TMR_REG, this is the time interval (in 15151 * nanoseconds) for each increment of the timer load/reload count. The 15152 * requested duration of a timer is this value multiplied by the timer 15153 * load/reload count. 15154 */ 15155 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_NS_PER_COUNT_OFST 4 15156 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_NS_PER_COUNT_LEN 4 15157 /* For timers updated via writes to EVQ_TMR_REG, this is the maximum value 15158 * allowed for timer load/reload counts. 15159 */ 15160 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_MAX_COUNT_OFST 8 15161 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_MAX_COUNT_LEN 4 15162 /* For timers updated via writes to EVQ_TMR_REG, timer load/reload counts not a 15163 * multiple of this step size will be rounded in an implementation defined 15164 * manner. 15165 */ 15166 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_STEP_OFST 12 15167 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_STEP_LEN 4 15168 /* Maximum timer duration (in nanoseconds) for timers updated via MCDI. Only 15169 * meaningful if MC_CMD_SET_EVQ_TMR is implemented. 15170 */ 15171 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_MAX_NS_OFST 16 15172 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_MAX_NS_LEN 4 15173 /* Timer durations requested via MCDI that are not a multiple of this step size 15174 * will be rounded up. Only meaningful if MC_CMD_SET_EVQ_TMR is implemented. 15175 */ 15176 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_STEP_NS_OFST 20 15177 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_STEP_NS_LEN 4 15178 /* For timers updated using the bug35388 workaround, this is the time interval 15179 * (in nanoseconds) for each increment of the timer load/reload count. The 15180 * requested duration of a timer is this value multiplied by the timer 15181 * load/reload count. This field is only meaningful if the bug35388 workaround 15182 * is enabled. 15183 */ 15184 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_NS_PER_COUNT_OFST 24 15185 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_NS_PER_COUNT_LEN 4 15186 /* For timers updated using the bug35388 workaround, this is the maximum value 15187 * allowed for timer load/reload counts. This field is only meaningful if the 15188 * bug35388 workaround is enabled. 15189 */ 15190 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_MAX_COUNT_OFST 28 15191 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_MAX_COUNT_LEN 4 15192 /* For timers updated using the bug35388 workaround, timer load/reload counts 15193 * not a multiple of this step size will be rounded in an implementation 15194 * defined manner. This field is only meaningful if the bug35388 workaround is 15195 * enabled. 15196 */ 15197 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_STEP_OFST 32 15198 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_STEP_LEN 4 15199 15200 15201 /***********************************/ 15202 /* MC_CMD_ALLOCATE_TX_VFIFO_CP 15203 * When we use the TX_vFIFO_ULL mode, we can allocate common pools using the 15204 * non used switch buffers. 15205 */ 15206 #define MC_CMD_ALLOCATE_TX_VFIFO_CP 0x11d 15207 #undef MC_CMD_0x11d_PRIVILEGE_CTG 15208 15209 #define MC_CMD_0x11d_PRIVILEGE_CTG SRIOV_CTG_ADMIN 15210 15211 /* MC_CMD_ALLOCATE_TX_VFIFO_CP_IN msgrequest */ 15212 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_LEN 20 15213 /* Desired instance. Must be set to a specific instance, which is a function 15214 * local queue index. 15215 */ 15216 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_INSTANCE_OFST 0 15217 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_INSTANCE_LEN 4 15218 /* Will the common pool be used as TX_vFIFO_ULL (1) */ 15219 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_MODE_OFST 4 15220 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_MODE_LEN 4 15221 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_ENABLED 0x1 /* enum */ 15222 /* enum: Using this interface without TX_vFIFO_ULL is not supported for now */ 15223 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_DISABLED 0x0 15224 /* Number of buffers to reserve for the common pool */ 15225 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_SIZE_OFST 8 15226 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_SIZE_LEN 4 15227 /* TX datapath to which the Common Pool is connected to. */ 15228 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_INGRESS_OFST 12 15229 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_INGRESS_LEN 4 15230 /* enum: Extracts information from function */ 15231 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_USE_FUNCTION_VALUE -0x1 15232 /* Network port or RX Engine to which the common pool connects. */ 15233 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_EGRESS_OFST 16 15234 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_EGRESS_LEN 4 15235 /* enum: Extracts information from function */ 15236 /* MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_USE_FUNCTION_VALUE -0x1 */ 15237 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT0 0x0 /* enum */ 15238 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT1 0x1 /* enum */ 15239 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT2 0x2 /* enum */ 15240 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT3 0x3 /* enum */ 15241 /* enum: To enable Switch loopback with Rx engine 0 */ 15242 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_RX_ENGINE0 0x4 15243 /* enum: To enable Switch loopback with Rx engine 1 */ 15244 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_RX_ENGINE1 0x5 15245 15246 /* MC_CMD_ALLOCATE_TX_VFIFO_CP_OUT msgresponse */ 15247 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_OUT_LEN 4 15248 /* ID of the common pool allocated */ 15249 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_OUT_CP_ID_OFST 0 15250 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_OUT_CP_ID_LEN 4 15251 15252 15253 /***********************************/ 15254 /* MC_CMD_ALLOCATE_TX_VFIFO_VFIFO 15255 * When we use the TX_vFIFO_ULL mode, we can allocate vFIFOs using the 15256 * previously allocated common pools. 15257 */ 15258 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO 0x11e 15259 #undef MC_CMD_0x11e_PRIVILEGE_CTG 15260 15261 #define MC_CMD_0x11e_PRIVILEGE_CTG SRIOV_CTG_ADMIN 15262 15263 /* MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN msgrequest */ 15264 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_LEN 20 15265 /* Common pool previously allocated to which the new vFIFO will be associated 15266 */ 15267 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_CP_OFST 0 15268 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_CP_LEN 4 15269 /* Port or RX engine to associate the vFIFO egress */ 15270 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_EGRESS_OFST 4 15271 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_EGRESS_LEN 4 15272 /* enum: Extracts information from common pool */ 15273 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_USE_CP_VALUE -0x1 15274 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT0 0x0 /* enum */ 15275 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT1 0x1 /* enum */ 15276 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT2 0x2 /* enum */ 15277 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT3 0x3 /* enum */ 15278 /* enum: To enable Switch loopback with Rx engine 0 */ 15279 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_RX_ENGINE0 0x4 15280 /* enum: To enable Switch loopback with Rx engine 1 */ 15281 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_RX_ENGINE1 0x5 15282 /* Minimum number of buffers that the pool must have */ 15283 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_SIZE_OFST 8 15284 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_SIZE_LEN 4 15285 /* enum: Do not check the space available */ 15286 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_NO_MINIMUM 0x0 15287 /* Will the vFIFO be used as TX_vFIFO_ULL */ 15288 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_MODE_OFST 12 15289 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_MODE_LEN 4 15290 /* Network priority of the vFIFO,if applicable */ 15291 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PRIORITY_OFST 16 15292 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PRIORITY_LEN 4 15293 /* enum: Search for the lowest unused priority */ 15294 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_LOWEST_AVAILABLE -0x1 15295 15296 /* MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT msgresponse */ 15297 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_LEN 8 15298 /* Short vFIFO ID */ 15299 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_VID_OFST 0 15300 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_VID_LEN 4 15301 /* Network priority of the vFIFO */ 15302 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_PRIORITY_OFST 4 15303 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_PRIORITY_LEN 4 15304 15305 15306 /***********************************/ 15307 /* MC_CMD_TEARDOWN_TX_VFIFO_VF 15308 * This interface clears the configuration of the given vFIFO and leaves it 15309 * ready to be re-used. 15310 */ 15311 #define MC_CMD_TEARDOWN_TX_VFIFO_VF 0x11f 15312 #undef MC_CMD_0x11f_PRIVILEGE_CTG 15313 15314 #define MC_CMD_0x11f_PRIVILEGE_CTG SRIOV_CTG_ADMIN 15315 15316 /* MC_CMD_TEARDOWN_TX_VFIFO_VF_IN msgrequest */ 15317 #define MC_CMD_TEARDOWN_TX_VFIFO_VF_IN_LEN 4 15318 /* Short vFIFO ID */ 15319 #define MC_CMD_TEARDOWN_TX_VFIFO_VF_IN_VFIFO_OFST 0 15320 #define MC_CMD_TEARDOWN_TX_VFIFO_VF_IN_VFIFO_LEN 4 15321 15322 /* MC_CMD_TEARDOWN_TX_VFIFO_VF_OUT msgresponse */ 15323 #define MC_CMD_TEARDOWN_TX_VFIFO_VF_OUT_LEN 0 15324 15325 15326 /***********************************/ 15327 /* MC_CMD_DEALLOCATE_TX_VFIFO_CP 15328 * This interface clears the configuration of the given common pool and leaves 15329 * it ready to be re-used. 15330 */ 15331 #define MC_CMD_DEALLOCATE_TX_VFIFO_CP 0x121 15332 #undef MC_CMD_0x121_PRIVILEGE_CTG 15333 15334 #define MC_CMD_0x121_PRIVILEGE_CTG SRIOV_CTG_ADMIN 15335 15336 /* MC_CMD_DEALLOCATE_TX_VFIFO_CP_IN msgrequest */ 15337 #define MC_CMD_DEALLOCATE_TX_VFIFO_CP_IN_LEN 4 15338 /* Common pool ID given when pool allocated */ 15339 #define MC_CMD_DEALLOCATE_TX_VFIFO_CP_IN_POOL_ID_OFST 0 15340 #define MC_CMD_DEALLOCATE_TX_VFIFO_CP_IN_POOL_ID_LEN 4 15341 15342 /* MC_CMD_DEALLOCATE_TX_VFIFO_CP_OUT msgresponse */ 15343 #define MC_CMD_DEALLOCATE_TX_VFIFO_CP_OUT_LEN 0 15344 15345 15346 /***********************************/ 15347 /* MC_CMD_REKEY 15348 * This request causes the NIC to generate a new per-NIC key and program it 15349 * into the write-once memory. During the process all flash partitions that are 15350 * protected with a CMAC are verified with the old per-NIC key and then signed 15351 * with the new per-NIC key. If the NIC has already reached its rekey limit the 15352 * REKEY op will return MC_CMD_ERR_ERANGE. The REKEY op may block until 15353 * completion or it may return 0 and continue processing, therefore the caller 15354 * must poll at least once to confirm that the rekeying has completed. The POLL 15355 * operation returns MC_CMD_ERR_EBUSY if the rekey process is still running 15356 * otherwise it will return the result of the last completed rekey operation, 15357 * or 0 if there has not been a previous rekey. 15358 */ 15359 #define MC_CMD_REKEY 0x123 15360 #undef MC_CMD_0x123_PRIVILEGE_CTG 15361 15362 #define MC_CMD_0x123_PRIVILEGE_CTG SRIOV_CTG_ADMIN 15363 15364 /* MC_CMD_REKEY_IN msgrequest */ 15365 #define MC_CMD_REKEY_IN_LEN 4 15366 /* the type of operation requested */ 15367 #define MC_CMD_REKEY_IN_OP_OFST 0 15368 #define MC_CMD_REKEY_IN_OP_LEN 4 15369 /* enum: Start the rekeying operation */ 15370 #define MC_CMD_REKEY_IN_OP_REKEY 0x0 15371 /* enum: Poll for completion of the rekeying operation */ 15372 #define MC_CMD_REKEY_IN_OP_POLL 0x1 15373 15374 /* MC_CMD_REKEY_OUT msgresponse */ 15375 #define MC_CMD_REKEY_OUT_LEN 0 15376 15377 15378 /***********************************/ 15379 /* MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS 15380 * This interface allows the host to find out how many common pool buffers are 15381 * not yet assigned. 15382 */ 15383 #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS 0x124 15384 #undef MC_CMD_0x124_PRIVILEGE_CTG 15385 15386 #define MC_CMD_0x124_PRIVILEGE_CTG SRIOV_CTG_ADMIN 15387 15388 /* MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_IN msgrequest */ 15389 #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_IN_LEN 0 15390 15391 /* MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT msgresponse */ 15392 #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_LEN 8 15393 /* Available buffers for the ENG to NET vFIFOs. */ 15394 #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_NET_OFST 0 15395 #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_NET_LEN 4 15396 /* Available buffers for the ENG to ENG and NET to ENG vFIFOs. */ 15397 #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_ENG_OFST 4 15398 #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_ENG_LEN 4 15399 15400 15401 /***********************************/ 15402 /* MC_CMD_SET_SECURITY_FUSES 15403 * Change the security level of the adapter by setting bits in the write-once 15404 * memory. The firmware maps each flag in the message to a set of one or more 15405 * hardware-defined or software-defined bits and sets these bits in the write- 15406 * once memory. For Medford the hardware-defined bits are defined in 15407 * SF-112079-PS 5.3, the software-defined bits are defined in xpm.h. Returns 0 15408 * if all of the required bits were set and returns MC_CMD_ERR_EIO if any of 15409 * the required bits were not set. 15410 */ 15411 #define MC_CMD_SET_SECURITY_FUSES 0x126 15412 #undef MC_CMD_0x126_PRIVILEGE_CTG 15413 15414 #define MC_CMD_0x126_PRIVILEGE_CTG SRIOV_CTG_ADMIN 15415 15416 /* MC_CMD_SET_SECURITY_FUSES_IN msgrequest */ 15417 #define MC_CMD_SET_SECURITY_FUSES_IN_LEN 4 15418 /* Flags specifying what type of security features are being set */ 15419 #define MC_CMD_SET_SECURITY_FUSES_IN_FLAGS_OFST 0 15420 #define MC_CMD_SET_SECURITY_FUSES_IN_FLAGS_LEN 4 15421 #define MC_CMD_SET_SECURITY_FUSES_IN_SECURE_BOOT_LBN 0 15422 #define MC_CMD_SET_SECURITY_FUSES_IN_SECURE_BOOT_WIDTH 1 15423 #define MC_CMD_SET_SECURITY_FUSES_IN_REJECT_TEST_SIGNED_LBN 1 15424 #define MC_CMD_SET_SECURITY_FUSES_IN_REJECT_TEST_SIGNED_WIDTH 1 15425 #define MC_CMD_SET_SECURITY_FUSES_IN_SOFT_CONFIG_LBN 31 15426 #define MC_CMD_SET_SECURITY_FUSES_IN_SOFT_CONFIG_WIDTH 1 15427 15428 /* MC_CMD_SET_SECURITY_FUSES_OUT msgresponse */ 15429 #define MC_CMD_SET_SECURITY_FUSES_OUT_LEN 0 15430 15431 /* MC_CMD_SET_SECURITY_FUSES_V2_OUT msgresponse */ 15432 #define MC_CMD_SET_SECURITY_FUSES_V2_OUT_LEN 4 15433 /* Flags specifying which security features are enforced on the NIC after the 15434 * flags in the request have been applied. See 15435 * MC_CMD_SET_SECURITY_FUSES_IN/FLAGS for flag definitions. 15436 */ 15437 #define MC_CMD_SET_SECURITY_FUSES_V2_OUT_FLAGS_OFST 0 15438 #define MC_CMD_SET_SECURITY_FUSES_V2_OUT_FLAGS_LEN 4 15439 15440 15441 /***********************************/ 15442 /* MC_CMD_TSA_INFO 15443 * Messages sent from TSA adapter to TSA controller. This command is only valid 15444 * when the MCDI header has MESSAGE_TYPE set to MCDI_MESSAGE_TYPE_TSA. This 15445 * command is not sent by the driver to the MC; it is sent from the MC to a TSA 15446 * controller, being treated more like an alert message rather than a command; 15447 * hence the MC does not expect a response in return. Doxbox reference 15448 * SF-117371-SW 15449 */ 15450 #define MC_CMD_TSA_INFO 0x127 15451 #undef MC_CMD_0x127_PRIVILEGE_CTG 15452 15453 #define MC_CMD_0x127_PRIVILEGE_CTG SRIOV_CTG_ADMIN 15454 15455 /* MC_CMD_TSA_INFO_IN msgrequest */ 15456 #define MC_CMD_TSA_INFO_IN_LEN 4 15457 #define MC_CMD_TSA_INFO_IN_OP_HDR_OFST 0 15458 #define MC_CMD_TSA_INFO_IN_OP_HDR_LEN 4 15459 #define MC_CMD_TSA_INFO_IN_OP_LBN 0 15460 #define MC_CMD_TSA_INFO_IN_OP_WIDTH 16 15461 /* enum: Information about recently discovered local IP address of the adapter 15462 */ 15463 #define MC_CMD_TSA_INFO_OP_LOCAL_IP 0x1 15464 /* enum: Information about a sampled packet that either - did not match any 15465 * black/white-list filters and was allowed by the default filter or - did not 15466 * match any black/white-list filters and was denied by the default filter 15467 */ 15468 #define MC_CMD_TSA_INFO_OP_PKT_SAMPLE 0x2 15469 15470 /* MC_CMD_TSA_INFO_IN_LOCAL_IP msgrequest: 15471 * 15472 * The TSA controller maintains a list of IP addresses valid for each port of a 15473 * TSA adapter. The TSA controller requires information from the adapter 15474 * inorder to learn new IP addresses assigned to a physical port and to 15475 * identify those that are no longer assigned to the physical port. For this 15476 * purpose, the TSA adapter snoops ARP replies, gratuitous ARP requests and ARP 15477 * probe packets seen on each physical port. This definition describes the 15478 * format of the notification message sent from a TSA adapter to a TSA 15479 * controller related to any information related to a change in IP address 15480 * assignment for a port. Doxbox reference SF-117371. 15481 * 15482 * There may be a possibility of combining multiple notifications in a single 15483 * message in future. When that happens, a new flag can be defined using the 15484 * reserved bits to describe the extended format of this notification. 15485 */ 15486 #define MC_CMD_TSA_INFO_IN_LOCAL_IP_LEN 18 15487 #define MC_CMD_TSA_INFO_IN_LOCAL_IP_OP_HDR_OFST 0 15488 #define MC_CMD_TSA_INFO_IN_LOCAL_IP_OP_HDR_LEN 4 15489 /* Additional metadata describing the IP address information such as source of 15490 * information retrieval, type of IP address, physical port number. 15491 */ 15492 #define MC_CMD_TSA_INFO_IN_LOCAL_IP_META_OFST 4 15493 #define MC_CMD_TSA_INFO_IN_LOCAL_IP_META_LEN 4 15494 #define MC_CMD_TSA_INFO_IN_LOCAL_IP_META_PORT_INDEX_LBN 0 15495 #define MC_CMD_TSA_INFO_IN_LOCAL_IP_META_PORT_INDEX_WIDTH 8 15496 #define MC_CMD_TSA_INFO_IN_LOCAL_IP_RESERVED_LBN 8 15497 #define MC_CMD_TSA_INFO_IN_LOCAL_IP_RESERVED_WIDTH 8 15498 #define MC_CMD_TSA_INFO_IN_LOCAL_IP_META_REASON_LBN 16 15499 #define MC_CMD_TSA_INFO_IN_LOCAL_IP_META_REASON_WIDTH 8 15500 /* enum: ARP reply sent out of the physical port */ 15501 #define MC_CMD_TSA_INFO_IP_REASON_TX_ARP 0x0 15502 /* enum: ARP probe packet received on the physical port */ 15503 #define MC_CMD_TSA_INFO_IP_REASON_RX_ARP_PROBE 0x1 15504 /* enum: Gratuitous ARP packet received on the physical port */ 15505 #define MC_CMD_TSA_INFO_IP_REASON_RX_GRATUITOUS_ARP 0x2 15506 /* enum: DHCP ACK packet received on the physical port */ 15507 #define MC_CMD_TSA_INFO_IP_REASON_RX_DHCP_ACK 0x3 15508 #define MC_CMD_TSA_INFO_IN_LOCAL_IP_META_IPV4_LBN 24 15509 #define MC_CMD_TSA_INFO_IN_LOCAL_IP_META_IPV4_WIDTH 1 15510 #define MC_CMD_TSA_INFO_IN_LOCAL_IP_RESERVED1_LBN 25 15511 #define MC_CMD_TSA_INFO_IN_LOCAL_IP_RESERVED1_WIDTH 7 15512 /* IPV4 address retrieved from the sampled packets. This field is relevant only 15513 * when META_IPV4 is set to 1. 15514 */ 15515 #define MC_CMD_TSA_INFO_IN_LOCAL_IP_IPV4_ADDR_OFST 8 15516 #define MC_CMD_TSA_INFO_IN_LOCAL_IP_IPV4_ADDR_LEN 4 15517 /* Target MAC address retrieved from the sampled packet. */ 15518 #define MC_CMD_TSA_INFO_IN_LOCAL_IP_MAC_ADDR_OFST 12 15519 #define MC_CMD_TSA_INFO_IN_LOCAL_IP_MAC_ADDR_LEN 1 15520 #define MC_CMD_TSA_INFO_IN_LOCAL_IP_MAC_ADDR_NUM 6 15521 15522 /* MC_CMD_TSA_INFO_IN_PKT_SAMPLE msgrequest: 15523 * 15524 * It is desireable for the TSA controller to learn the traffic pattern of 15525 * packets seen at the network port being monitored. In order to learn about 15526 * the traffic pattern, the TSA controller may want to sample packets seen at 15527 * the network port. Based on the packet samples that the TSA controller 15528 * receives from the adapter, the controller may choose to configure additional 15529 * black-list or white-list rules to allow or block packets as required. 15530 * 15531 * Although the entire sampled packet as seen on the network port is available 15532 * to the MC the length of sampled packet sent to controller is restricted by 15533 * MCDI payload size. Besides, the TSA controller does not require the entire 15534 * packet to make decisions about filter updates. Hence the packet sample being 15535 * passed to the controller is truncated to 128 bytes. This length is large 15536 * enough to hold the ethernet header, IP header and maximum length of 15537 * supported L4 protocol headers (IPv4 only, but can hold IPv6 header too, if 15538 * required in future). 15539 * 15540 * The intention is that any future changes to this message format that are not 15541 * backwards compatible will be defined with a new operation code. 15542 */ 15543 #define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_LEN 136 15544 #define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_OP_HDR_OFST 0 15545 #define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_OP_HDR_LEN 4 15546 /* Additional metadata describing the sampled packet */ 15547 #define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_OFST 4 15548 #define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_LEN 4 15549 #define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_PORT_INDEX_LBN 0 15550 #define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_PORT_INDEX_WIDTH 8 15551 #define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_DIRECTION_LBN 8 15552 #define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_DIRECTION_WIDTH 1 15553 #define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_RESERVED_LBN 9 15554 #define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_RESERVED_WIDTH 7 15555 #define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_ACTION_MASK_LBN 16 15556 #define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_ACTION_MASK_WIDTH 4 15557 #define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_ACTION_ALLOW_LBN 16 15558 #define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_ACTION_ALLOW_WIDTH 1 15559 #define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_ACTION_DENY_LBN 17 15560 #define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_ACTION_DENY_WIDTH 1 15561 #define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_ACTION_COUNT_LBN 18 15562 #define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_ACTION_COUNT_WIDTH 1 15563 /* 128-byte raw prefix of the sampled packet which includes the ethernet 15564 * header, IP header and L4 protocol header (only IPv4 supported initially). 15565 * This provides the controller enough information about the packet sample to 15566 * report traffic patterns seen on a network port and to make decisions 15567 * concerning rule-set updates. 15568 */ 15569 #define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_PACKET_DATA_OFST 8 15570 #define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_PACKET_DATA_LEN 1 15571 #define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_PACKET_DATA_NUM 128 15572 15573 /* MC_CMD_TSA_INFO_OUT msgresponse */ 15574 #define MC_CMD_TSA_INFO_OUT_LEN 0 15575 15576 15577 /***********************************/ 15578 /* MC_CMD_HOST_INFO 15579 * Commands to appply or retrieve host-related information from an adapter. 15580 * Doxbox reference SF-117371-SW 15581 */ 15582 #define MC_CMD_HOST_INFO 0x128 15583 #undef MC_CMD_0x128_PRIVILEGE_CTG 15584 15585 #define MC_CMD_0x128_PRIVILEGE_CTG SRIOV_CTG_ADMIN 15586 15587 /* MC_CMD_HOST_INFO_IN msgrequest */ 15588 #define MC_CMD_HOST_INFO_IN_LEN 4 15589 /* sub-operation code info */ 15590 #define MC_CMD_HOST_INFO_IN_OP_HDR_OFST 0 15591 #define MC_CMD_HOST_INFO_IN_OP_HDR_LEN 4 15592 #define MC_CMD_HOST_INFO_IN_OP_LBN 0 15593 #define MC_CMD_HOST_INFO_IN_OP_WIDTH 16 15594 /* enum: Read a 16-byte unique host identifier from the adapter. This UUID 15595 * helps to identify the host that an adapter is plugged into. This identifier 15596 * is ideally the system UUID retrieved and set by the UEFI driver. If the UEFI 15597 * driver is unable to extract the system UUID, it would still set a random 15598 * 16-byte value into each supported SF adapter plugged into it. Host UUIDs may 15599 * change if the system is power-cycled, however, they persist across adapter 15600 * resets. If the host UUID was not set on an adapter, due to an unsupported 15601 * version of UEFI driver, then this command returns an error. Doxbox reference 15602 * - SF-117371-SW section 'Host UUID'. 15603 */ 15604 #define MC_CMD_HOST_INFO_OP_GET_UUID 0x0 15605 /* enum: Set a 16-byte unique host identifier on the adapter to identify the 15606 * host that the adapter is plugged into. See MC_CMD_HOST_INFO_OP_GET_UUID for 15607 * further details. 15608 */ 15609 #define MC_CMD_HOST_INFO_OP_SET_UUID 0x1 15610 15611 /* MC_CMD_HOST_INFO_IN_GET_UUID msgrequest */ 15612 #define MC_CMD_HOST_INFO_IN_GET_UUID_LEN 4 15613 /* sub-operation code info */ 15614 #define MC_CMD_HOST_INFO_IN_GET_UUID_OP_HDR_OFST 0 15615 #define MC_CMD_HOST_INFO_IN_GET_UUID_OP_HDR_LEN 4 15616 15617 /* MC_CMD_HOST_INFO_OUT_GET_UUID msgresponse */ 15618 #define MC_CMD_HOST_INFO_OUT_GET_UUID_LEN 16 15619 /* 16-byte host UUID read out of the adapter. See MC_CMD_HOST_INFO_OP_GET_UUID 15620 * for further details. 15621 */ 15622 #define MC_CMD_HOST_INFO_OUT_GET_UUID_HOST_UUID_OFST 0 15623 #define MC_CMD_HOST_INFO_OUT_GET_UUID_HOST_UUID_LEN 1 15624 #define MC_CMD_HOST_INFO_OUT_GET_UUID_HOST_UUID_NUM 16 15625 15626 /* MC_CMD_HOST_INFO_IN_SET_UUID msgrequest */ 15627 #define MC_CMD_HOST_INFO_IN_SET_UUID_LEN 20 15628 /* sub-operation code info */ 15629 #define MC_CMD_HOST_INFO_IN_SET_UUID_OP_HDR_OFST 0 15630 #define MC_CMD_HOST_INFO_IN_SET_UUID_OP_HDR_LEN 4 15631 /* 16-byte host UUID set on the adapter. See MC_CMD_HOST_INFO_OP_GET_UUID for 15632 * further details. 15633 */ 15634 #define MC_CMD_HOST_INFO_IN_SET_UUID_HOST_UUID_OFST 4 15635 #define MC_CMD_HOST_INFO_IN_SET_UUID_HOST_UUID_LEN 1 15636 #define MC_CMD_HOST_INFO_IN_SET_UUID_HOST_UUID_NUM 16 15637 15638 /* MC_CMD_HOST_INFO_OUT_SET_UUID msgresponse */ 15639 #define MC_CMD_HOST_INFO_OUT_SET_UUID_LEN 0 15640 15641 15642 /***********************************/ 15643 /* MC_CMD_TSAN_INFO 15644 * Get TSA adapter information. TSA controllers query each TSA adapter to learn 15645 * some configuration parameters of each adapter. Doxbox reference SF-117371-SW 15646 * section 'Adapter Information' 15647 */ 15648 #define MC_CMD_TSAN_INFO 0x129 15649 #undef MC_CMD_0x129_PRIVILEGE_CTG 15650 15651 #define MC_CMD_0x129_PRIVILEGE_CTG SRIOV_CTG_ADMIN 15652 15653 /* MC_CMD_TSAN_INFO_IN msgrequest */ 15654 #define MC_CMD_TSAN_INFO_IN_LEN 4 15655 /* sub-operation code info */ 15656 #define MC_CMD_TSAN_INFO_IN_OP_HDR_OFST 0 15657 #define MC_CMD_TSAN_INFO_IN_OP_HDR_LEN 4 15658 #define MC_CMD_TSAN_INFO_IN_OP_LBN 0 15659 #define MC_CMD_TSAN_INFO_IN_OP_WIDTH 16 15660 /* enum: Read configuration parameters and IDs that uniquely identify an 15661 * adapter. The parameters include - host identification, adapter 15662 * identification string and number of physical ports on the adapter. 15663 */ 15664 #define MC_CMD_TSAN_INFO_OP_GET_CFG 0x0 15665 15666 /* MC_CMD_TSAN_INFO_IN_GET_CFG msgrequest */ 15667 #define MC_CMD_TSAN_INFO_IN_GET_CFG_LEN 4 15668 /* sub-operation code info */ 15669 #define MC_CMD_TSAN_INFO_IN_GET_CFG_OP_HDR_OFST 0 15670 #define MC_CMD_TSAN_INFO_IN_GET_CFG_OP_HDR_LEN 4 15671 15672 /* MC_CMD_TSAN_INFO_OUT_GET_CFG msgresponse */ 15673 #define MC_CMD_TSAN_INFO_OUT_GET_CFG_LEN 26 15674 /* Information about the configuration parameters returned in this response. */ 15675 #define MC_CMD_TSAN_INFO_OUT_GET_CFG_CONFIG_WORD_OFST 0 15676 #define MC_CMD_TSAN_INFO_OUT_GET_CFG_CONFIG_WORD_LEN 4 15677 #define MC_CMD_TSAN_INFO_OUT_GET_CFG_CAP_FLAGS_LBN 0 15678 #define MC_CMD_TSAN_INFO_OUT_GET_CFG_CAP_FLAGS_WIDTH 16 15679 #define MC_CMD_TSAN_INFO_OUT_GET_CFG_FLAG_HOST_UUID_VALID_LBN 0 15680 #define MC_CMD_TSAN_INFO_OUT_GET_CFG_FLAG_HOST_UUID_VALID_WIDTH 1 15681 #define MC_CMD_TSAN_INFO_OUT_GET_CFG_NUM_PORTS_LBN 16 15682 #define MC_CMD_TSAN_INFO_OUT_GET_CFG_NUM_PORTS_WIDTH 8 15683 /* 16-byte host UUID read out of the adapter. See MC_CMD_HOST_INFO_OP_GET_UUID 15684 * for further details. 15685 */ 15686 #define MC_CMD_TSAN_INFO_OUT_GET_CFG_HOST_UUID_OFST 4 15687 #define MC_CMD_TSAN_INFO_OUT_GET_CFG_HOST_UUID_LEN 1 15688 #define MC_CMD_TSAN_INFO_OUT_GET_CFG_HOST_UUID_NUM 16 15689 /* A unique identifier per adapter. The base MAC address of the card is used 15690 * for this purpose. 15691 */ 15692 #define MC_CMD_TSAN_INFO_OUT_GET_CFG_GUID_OFST 20 15693 #define MC_CMD_TSAN_INFO_OUT_GET_CFG_GUID_LEN 1 15694 #define MC_CMD_TSAN_INFO_OUT_GET_CFG_GUID_NUM 6 15695 15696 15697 /***********************************/ 15698 /* MC_CMD_TSA_STATISTICS 15699 * TSA adapter statistics operations. 15700 */ 15701 #define MC_CMD_TSA_STATISTICS 0x130 15702 #undef MC_CMD_0x130_PRIVILEGE_CTG 15703 15704 #define MC_CMD_0x130_PRIVILEGE_CTG SRIOV_CTG_ADMIN 15705 15706 /* MC_CMD_TSA_STATISTICS_IN msgrequest */ 15707 #define MC_CMD_TSA_STATISTICS_IN_LEN 4 15708 /* TSA statistics sub-operation code */ 15709 #define MC_CMD_TSA_STATISTICS_IN_OP_CODE_OFST 0 15710 #define MC_CMD_TSA_STATISTICS_IN_OP_CODE_LEN 4 15711 /* enum: Get the configuration parameters that describe the TSA statistics 15712 * layout on the adapter. 15713 */ 15714 #define MC_CMD_TSA_STATISTICS_OP_GET_CONFIG 0x0 15715 /* enum: Read and/or clear TSA statistics counters. */ 15716 #define MC_CMD_TSA_STATISTICS_OP_READ_CLEAR 0x1 15717 15718 /* MC_CMD_TSA_STATISTICS_IN_GET_CONFIG msgrequest */ 15719 #define MC_CMD_TSA_STATISTICS_IN_GET_CONFIG_LEN 4 15720 /* TSA statistics sub-operation code */ 15721 #define MC_CMD_TSA_STATISTICS_IN_GET_CONFIG_OP_CODE_OFST 0 15722 #define MC_CMD_TSA_STATISTICS_IN_GET_CONFIG_OP_CODE_LEN 4 15723 15724 /* MC_CMD_TSA_STATISTICS_OUT_GET_CONFIG msgresponse */ 15725 #define MC_CMD_TSA_STATISTICS_OUT_GET_CONFIG_LEN 8 15726 /* Maximum number of TSA statistics counters in each direction of dataflow 15727 * supported on the card. Note that the statistics counters are always 15728 * allocated in pairs, i.e. a counter ID is associated with one Tx and one Rx 15729 * counter. 15730 */ 15731 #define MC_CMD_TSA_STATISTICS_OUT_GET_CONFIG_MAX_STATS_OFST 0 15732 #define MC_CMD_TSA_STATISTICS_OUT_GET_CONFIG_MAX_STATS_LEN 4 15733 /* Width of each statistics counter (represented in bits). This gives an 15734 * indication of wrap point to the user. 15735 */ 15736 #define MC_CMD_TSA_STATISTICS_OUT_GET_CONFIG_STATS_WIDTH_OFST 4 15737 #define MC_CMD_TSA_STATISTICS_OUT_GET_CONFIG_STATS_WIDTH_LEN 4 15738 15739 /* MC_CMD_TSA_STATISTICS_IN_READ_CLEAR msgrequest */ 15740 #define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_LENMIN 20 15741 #define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_LENMAX 252 15742 #define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_LEN(num) (16+4*(num)) 15743 /* TSA statistics sub-operation code */ 15744 #define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_OP_CODE_OFST 0 15745 #define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_OP_CODE_LEN 4 15746 /* Parameters describing the statistics operation */ 15747 #define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_FLAGS_OFST 4 15748 #define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_FLAGS_LEN 4 15749 #define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_READ_LBN 0 15750 #define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_READ_WIDTH 1 15751 #define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_CLEAR_LBN 1 15752 #define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_CLEAR_WIDTH 1 15753 /* Counter ID list specification type */ 15754 #define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_MODE_OFST 8 15755 #define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_MODE_LEN 4 15756 /* enum: The statistics counters are specified as an unordered list of 15757 * individual counter ID. 15758 */ 15759 #define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_LIST 0x0 15760 /* enum: The statistics counters are specified as a range of consecutive 15761 * counter IDs. 15762 */ 15763 #define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_RANGE 0x1 15764 /* Number of statistics counters */ 15765 #define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_NUM_STATS_OFST 12 15766 #define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_NUM_STATS_LEN 4 15767 /* Counter IDs to be read/cleared. When mode is set to LIST, this entry holds a 15768 * list of counter IDs to be operated on. When mode is set to RANGE, this entry 15769 * holds a single counter ID representing the start of the range of counter IDs 15770 * to be operated on. 15771 */ 15772 #define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_COUNTER_ID_OFST 16 15773 #define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_COUNTER_ID_LEN 4 15774 #define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_COUNTER_ID_MINNUM 1 15775 #define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_COUNTER_ID_MAXNUM 59 15776 15777 /* MC_CMD_TSA_STATISTICS_OUT_READ_CLEAR msgresponse */ 15778 #define MC_CMD_TSA_STATISTICS_OUT_READ_CLEAR_LENMIN 24 15779 #define MC_CMD_TSA_STATISTICS_OUT_READ_CLEAR_LENMAX 248 15780 #define MC_CMD_TSA_STATISTICS_OUT_READ_CLEAR_LEN(num) (8+16*(num)) 15781 /* Number of statistics counters returned in this response */ 15782 #define MC_CMD_TSA_STATISTICS_OUT_READ_CLEAR_NUM_STATS_OFST 0 15783 #define MC_CMD_TSA_STATISTICS_OUT_READ_CLEAR_NUM_STATS_LEN 4 15784 /* MC_TSA_STATISTICS_ENTRY Note that this field is expected to start at a 15785 * 64-bit aligned offset 15786 */ 15787 #define MC_CMD_TSA_STATISTICS_OUT_READ_CLEAR_STATS_COUNTERS_OFST 8 15788 #define MC_CMD_TSA_STATISTICS_OUT_READ_CLEAR_STATS_COUNTERS_LEN 16 15789 #define MC_CMD_TSA_STATISTICS_OUT_READ_CLEAR_STATS_COUNTERS_MINNUM 1 15790 #define MC_CMD_TSA_STATISTICS_OUT_READ_CLEAR_STATS_COUNTERS_MAXNUM 15 15791 15792 /* MC_TSA_STATISTICS_ENTRY structuredef */ 15793 #define MC_TSA_STATISTICS_ENTRY_LEN 16 15794 /* Tx statistics counter */ 15795 #define MC_TSA_STATISTICS_ENTRY_TX_STAT_OFST 0 15796 #define MC_TSA_STATISTICS_ENTRY_TX_STAT_LEN 8 15797 #define MC_TSA_STATISTICS_ENTRY_TX_STAT_LO_OFST 0 15798 #define MC_TSA_STATISTICS_ENTRY_TX_STAT_HI_OFST 4 15799 #define MC_TSA_STATISTICS_ENTRY_TX_STAT_LBN 0 15800 #define MC_TSA_STATISTICS_ENTRY_TX_STAT_WIDTH 64 15801 /* Rx statistics counter */ 15802 #define MC_TSA_STATISTICS_ENTRY_RX_STAT_OFST 8 15803 #define MC_TSA_STATISTICS_ENTRY_RX_STAT_LEN 8 15804 #define MC_TSA_STATISTICS_ENTRY_RX_STAT_LO_OFST 8 15805 #define MC_TSA_STATISTICS_ENTRY_RX_STAT_HI_OFST 12 15806 #define MC_TSA_STATISTICS_ENTRY_RX_STAT_LBN 64 15807 #define MC_TSA_STATISTICS_ENTRY_RX_STAT_WIDTH 64 15808 15809 15810 /***********************************/ 15811 /* MC_CMD_ERASE_INITIAL_NIC_SECRET 15812 * This request causes the NIC to find the initial NIC secret (programmed 15813 * during ATE) in XPM memory and if and only if the NIC has already been 15814 * rekeyed with MC_CMD_REKEY, erase it. This is used by manftest after 15815 * installing TSA binding certificates. See SF-117631-TC. 15816 */ 15817 #define MC_CMD_ERASE_INITIAL_NIC_SECRET 0x131 15818 #undef MC_CMD_0x131_PRIVILEGE_CTG 15819 15820 #define MC_CMD_0x131_PRIVILEGE_CTG SRIOV_CTG_ADMIN 15821 15822 /* MC_CMD_ERASE_INITIAL_NIC_SECRET_IN msgrequest */ 15823 #define MC_CMD_ERASE_INITIAL_NIC_SECRET_IN_LEN 0 15824 15825 /* MC_CMD_ERASE_INITIAL_NIC_SECRET_OUT msgresponse */ 15826 #define MC_CMD_ERASE_INITIAL_NIC_SECRET_OUT_LEN 0 15827 15828 15829 /***********************************/ 15830 /* MC_CMD_TSA_CONFIG 15831 * TSA adapter configuration operations. This command is used to prepare the 15832 * NIC for TSA binding. 15833 */ 15834 #define MC_CMD_TSA_CONFIG 0x64 15835 #undef MC_CMD_0x64_PRIVILEGE_CTG 15836 15837 #define MC_CMD_0x64_PRIVILEGE_CTG SRIOV_CTG_ADMIN 15838 15839 /* MC_CMD_TSA_CONFIG_IN msgrequest */ 15840 #define MC_CMD_TSA_CONFIG_IN_LEN 4 15841 /* TSA configuration sub-operation code */ 15842 #define MC_CMD_TSA_CONFIG_IN_OP_OFST 0 15843 #define MC_CMD_TSA_CONFIG_IN_OP_LEN 4 15844 /* enum: Append a single item to the tsa_config partition. Items will be 15845 * encrypted unless they are declared as non-sensitive. Returns 15846 * MC_CMD_ERR_EEXIST if the tag is already present. 15847 */ 15848 #define MC_CMD_TSA_CONFIG_OP_APPEND 0x1 15849 /* enum: Reset the tsa_config partition to a clean state. */ 15850 #define MC_CMD_TSA_CONFIG_OP_RESET 0x2 15851 /* enum: Read back a configured item from tsa_config partition. Returns 15852 * MC_CMD_ERR_ENOENT if the item doesn't exist, or MC_CMD_ERR_EPERM if the item 15853 * is declared as sensitive (i.e. is encrypted). 15854 */ 15855 #define MC_CMD_TSA_CONFIG_OP_READ 0x3 15856 15857 /* MC_CMD_TSA_CONFIG_IN_APPEND msgrequest */ 15858 #define MC_CMD_TSA_CONFIG_IN_APPEND_LENMIN 12 15859 #define MC_CMD_TSA_CONFIG_IN_APPEND_LENMAX 252 15860 #define MC_CMD_TSA_CONFIG_IN_APPEND_LEN(num) (12+1*(num)) 15861 /* TSA configuration sub-operation code. The value shall be 15862 * MC_CMD_TSA_CONFIG_OP_APPEND. 15863 */ 15864 #define MC_CMD_TSA_CONFIG_IN_APPEND_OP_OFST 0 15865 #define MC_CMD_TSA_CONFIG_IN_APPEND_OP_LEN 4 15866 /* The tag to be appended */ 15867 #define MC_CMD_TSA_CONFIG_IN_APPEND_TAG_OFST 4 15868 #define MC_CMD_TSA_CONFIG_IN_APPEND_TAG_LEN 4 15869 /* The length of the data in bytes */ 15870 #define MC_CMD_TSA_CONFIG_IN_APPEND_LENGTH_OFST 8 15871 #define MC_CMD_TSA_CONFIG_IN_APPEND_LENGTH_LEN 4 15872 /* The item data */ 15873 #define MC_CMD_TSA_CONFIG_IN_APPEND_DATA_OFST 12 15874 #define MC_CMD_TSA_CONFIG_IN_APPEND_DATA_LEN 1 15875 #define MC_CMD_TSA_CONFIG_IN_APPEND_DATA_MINNUM 0 15876 #define MC_CMD_TSA_CONFIG_IN_APPEND_DATA_MAXNUM 240 15877 15878 /* MC_CMD_TSA_CONFIG_OUT_APPEND msgresponse */ 15879 #define MC_CMD_TSA_CONFIG_OUT_APPEND_LEN 0 15880 15881 /* MC_CMD_TSA_CONFIG_IN_RESET msgrequest */ 15882 #define MC_CMD_TSA_CONFIG_IN_RESET_LEN 4 15883 /* TSA configuration sub-operation code. The value shall be 15884 * MC_CMD_TSA_CONFIG_OP_RESET. 15885 */ 15886 #define MC_CMD_TSA_CONFIG_IN_RESET_OP_OFST 0 15887 #define MC_CMD_TSA_CONFIG_IN_RESET_OP_LEN 4 15888 15889 /* MC_CMD_TSA_CONFIG_OUT_RESET msgresponse */ 15890 #define MC_CMD_TSA_CONFIG_OUT_RESET_LEN 0 15891 15892 /* MC_CMD_TSA_CONFIG_IN_READ msgrequest */ 15893 #define MC_CMD_TSA_CONFIG_IN_READ_LEN 8 15894 /* TSA configuration sub-operation code. The value shall be 15895 * MC_CMD_TSA_CONFIG_OP_READ. 15896 */ 15897 #define MC_CMD_TSA_CONFIG_IN_READ_OP_OFST 0 15898 #define MC_CMD_TSA_CONFIG_IN_READ_OP_LEN 4 15899 /* The tag to be read */ 15900 #define MC_CMD_TSA_CONFIG_IN_READ_TAG_OFST 4 15901 #define MC_CMD_TSA_CONFIG_IN_READ_TAG_LEN 4 15902 15903 /* MC_CMD_TSA_CONFIG_OUT_READ msgresponse */ 15904 #define MC_CMD_TSA_CONFIG_OUT_READ_LENMIN 8 15905 #define MC_CMD_TSA_CONFIG_OUT_READ_LENMAX 252 15906 #define MC_CMD_TSA_CONFIG_OUT_READ_LEN(num) (8+1*(num)) 15907 /* The tag that was read */ 15908 #define MC_CMD_TSA_CONFIG_OUT_READ_TAG_OFST 0 15909 #define MC_CMD_TSA_CONFIG_OUT_READ_TAG_LEN 4 15910 /* The length of the data in bytes */ 15911 #define MC_CMD_TSA_CONFIG_OUT_READ_LENGTH_OFST 4 15912 #define MC_CMD_TSA_CONFIG_OUT_READ_LENGTH_LEN 4 15913 /* The data of the item. */ 15914 #define MC_CMD_TSA_CONFIG_OUT_READ_DATA_OFST 8 15915 #define MC_CMD_TSA_CONFIG_OUT_READ_DATA_LEN 1 15916 #define MC_CMD_TSA_CONFIG_OUT_READ_DATA_MINNUM 0 15917 #define MC_CMD_TSA_CONFIG_OUT_READ_DATA_MAXNUM 244 15918 15919 /* MC_TSA_IPV4_ITEM structuredef */ 15920 #define MC_TSA_IPV4_ITEM_LEN 8 15921 /* Additional metadata describing the IP address information such as the 15922 * physical port number the address is being used on. Unused space in this 15923 * field is reserved for future expansion. 15924 */ 15925 #define MC_TSA_IPV4_ITEM_IPV4_ADDR_META_OFST 0 15926 #define MC_TSA_IPV4_ITEM_IPV4_ADDR_META_LEN 4 15927 #define MC_TSA_IPV4_ITEM_PORT_IDX_LBN 0 15928 #define MC_TSA_IPV4_ITEM_PORT_IDX_WIDTH 8 15929 #define MC_TSA_IPV4_ITEM_IPV4_ADDR_META_LBN 0 15930 #define MC_TSA_IPV4_ITEM_IPV4_ADDR_META_WIDTH 32 15931 /* The IPv4 address in little endian byte order. */ 15932 #define MC_TSA_IPV4_ITEM_IPV4_ADDR_OFST 4 15933 #define MC_TSA_IPV4_ITEM_IPV4_ADDR_LEN 4 15934 #define MC_TSA_IPV4_ITEM_IPV4_ADDR_LBN 32 15935 #define MC_TSA_IPV4_ITEM_IPV4_ADDR_WIDTH 32 15936 15937 15938 /***********************************/ 15939 /* MC_CMD_TSA_IPADDR 15940 * TSA operations relating to the monitoring and expiry of local IP addresses 15941 * discovered by the controller. These commands are sent from a TSA controller 15942 * to a TSA adapter. 15943 */ 15944 #define MC_CMD_TSA_IPADDR 0x65 15945 #undef MC_CMD_0x65_PRIVILEGE_CTG 15946 15947 #define MC_CMD_0x65_PRIVILEGE_CTG SRIOV_CTG_ADMIN 15948 15949 /* MC_CMD_TSA_IPADDR_IN msgrequest */ 15950 #define MC_CMD_TSA_IPADDR_IN_LEN 4 15951 /* Header containing information to identify which sub-operation of this 15952 * command to perform. The header contains a 16-bit op-code. Unused space in 15953 * this field is reserved for future expansion. 15954 */ 15955 #define MC_CMD_TSA_IPADDR_IN_OP_HDR_OFST 0 15956 #define MC_CMD_TSA_IPADDR_IN_OP_HDR_LEN 4 15957 #define MC_CMD_TSA_IPADDR_IN_OP_LBN 0 15958 #define MC_CMD_TSA_IPADDR_IN_OP_WIDTH 16 15959 /* enum: Request that the adapter verifies that the IPv4 addresses supplied are 15960 * still in use by the host by sending ARP probes to the host. The MC does not 15961 * wait for a response to the probes and sends an MCDI response to the 15962 * controller once the probes have been sent to the host. The response to the 15963 * probes (if there are any) will be forwarded to the controller using 15964 * MC_CMD_TSA_INFO alerts. 15965 */ 15966 #define MC_CMD_TSA_IPADDR_OP_VALIDATE_IPV4 0x1 15967 /* enum: Notify the adapter that one or more IPv4 addresses are no longer valid 15968 * for the host of the adapter. The adapter should remove the IPv4 addresses 15969 * from its local cache. 15970 */ 15971 #define MC_CMD_TSA_IPADDR_OP_REMOVE_IPV4 0x2 15972 15973 /* MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4 msgrequest */ 15974 #define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_LENMIN 16 15975 #define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_LENMAX 248 15976 #define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_LEN(num) (8+8*(num)) 15977 /* Header containing information to identify which sub-operation of this 15978 * command to perform. The header contains a 16-bit op-code. Unused space in 15979 * this field is reserved for future expansion. 15980 */ 15981 #define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_OP_HDR_OFST 0 15982 #define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_OP_HDR_LEN 4 15983 #define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_OP_LBN 0 15984 #define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_OP_WIDTH 16 15985 /* Number of IPv4 addresses to validate. */ 15986 #define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_NUM_ITEMS_OFST 4 15987 #define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_NUM_ITEMS_LEN 4 15988 /* The IPv4 addresses to validate, in struct MC_TSA_IPV4_ITEM format. */ 15989 #define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_OFST 8 15990 #define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_LEN 8 15991 #define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_LO_OFST 8 15992 #define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_HI_OFST 12 15993 #define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_MINNUM 1 15994 #define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_IPV4_ITEM_MAXNUM 30 15995 15996 /* MC_CMD_TSA_IPADDR_OUT_VALIDATE_IPV4 msgresponse */ 15997 #define MC_CMD_TSA_IPADDR_OUT_VALIDATE_IPV4_LEN 0 15998 15999 /* MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4 msgrequest */ 16000 #define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_LENMIN 16 16001 #define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_LENMAX 248 16002 #define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_LEN(num) (8+8*(num)) 16003 /* Header containing information to identify which sub-operation of this 16004 * command to perform. The header contains a 16-bit op-code. Unused space in 16005 * this field is reserved for future expansion. 16006 */ 16007 #define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_OP_HDR_OFST 0 16008 #define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_OP_HDR_LEN 4 16009 #define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_OP_LBN 0 16010 #define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_OP_WIDTH 16 16011 /* Number of IPv4 addresses to remove. */ 16012 #define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_NUM_ITEMS_OFST 4 16013 #define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_NUM_ITEMS_LEN 4 16014 /* The IPv4 addresses that have expired, in struct MC_TSA_IPV4_ITEM format. */ 16015 #define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_OFST 8 16016 #define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_LEN 8 16017 #define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_LO_OFST 8 16018 #define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_HI_OFST 12 16019 #define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_MINNUM 1 16020 #define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_IPV4_ITEM_MAXNUM 30 16021 16022 /* MC_CMD_TSA_IPADDR_OUT_REMOVE_IPV4 msgresponse */ 16023 #define MC_CMD_TSA_IPADDR_OUT_REMOVE_IPV4_LEN 0 16024 16025 16026 /***********************************/ 16027 /* MC_CMD_SECURE_NIC_INFO 16028 * Get secure NIC information. While many of the features reported by these 16029 * commands are related to TSA, they must be supported in firmware where TSA is 16030 * disabled. 16031 */ 16032 #define MC_CMD_SECURE_NIC_INFO 0x132 16033 #undef MC_CMD_0x132_PRIVILEGE_CTG 16034 16035 #define MC_CMD_0x132_PRIVILEGE_CTG SRIOV_CTG_ADMIN 16036 16037 /* MC_CMD_SECURE_NIC_INFO_IN msgrequest */ 16038 #define MC_CMD_SECURE_NIC_INFO_IN_LEN 4 16039 /* sub-operation code info */ 16040 #define MC_CMD_SECURE_NIC_INFO_IN_OP_HDR_OFST 0 16041 #define MC_CMD_SECURE_NIC_INFO_IN_OP_HDR_LEN 4 16042 #define MC_CMD_SECURE_NIC_INFO_IN_OP_LBN 0 16043 #define MC_CMD_SECURE_NIC_INFO_IN_OP_WIDTH 16 16044 /* enum: Get the status of various security settings, all signed along with a 16045 * challenge chosen by the host. 16046 */ 16047 #define MC_CMD_SECURE_NIC_INFO_OP_STATUS 0x0 16048 16049 /* MC_CMD_SECURE_NIC_INFO_IN_STATUS msgrequest */ 16050 #define MC_CMD_SECURE_NIC_INFO_IN_STATUS_LEN 24 16051 /* sub-operation code, must be MC_CMD_SECURE_NIC_INFO_OP_STATUS */ 16052 #define MC_CMD_SECURE_NIC_INFO_IN_STATUS_OP_HDR_OFST 0 16053 #define MC_CMD_SECURE_NIC_INFO_IN_STATUS_OP_HDR_LEN 4 16054 /* Type of key to be used to sign response. */ 16055 #define MC_CMD_SECURE_NIC_INFO_IN_STATUS_KEY_TYPE_OFST 4 16056 #define MC_CMD_SECURE_NIC_INFO_IN_STATUS_KEY_TYPE_LEN 4 16057 #define MC_CMD_SECURE_NIC_INFO_IN_STATUS_UNUSED 0x0 /* enum */ 16058 /* enum: Solarflare adapter authentication key, installed by Manftest. */ 16059 #define MC_CMD_SECURE_NIC_INFO_IN_STATUS_SF_ADAPTER_AUTH 0x1 16060 /* enum: TSA binding key, installed after adapter is bound to a TSA controller. 16061 * This is not supported in firmware which does not support TSA. 16062 */ 16063 #define MC_CMD_SECURE_NIC_INFO_IN_STATUS_TSA_BINDING 0x2 16064 /* enum: Customer adapter authentication key. Installed by the customer in the 16065 * field, but otherwise similar to the Solarflare adapter authentication key. 16066 */ 16067 #define MC_CMD_SECURE_NIC_INFO_IN_STATUS_CUSTOMER_ADAPTER_AUTH 0x3 16068 /* Random challenge generated by the host. */ 16069 #define MC_CMD_SECURE_NIC_INFO_IN_STATUS_CHALLENGE_OFST 8 16070 #define MC_CMD_SECURE_NIC_INFO_IN_STATUS_CHALLENGE_LEN 16 16071 16072 /* MC_CMD_SECURE_NIC_INFO_OUT_STATUS msgresponse */ 16073 #define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_LEN 420 16074 /* Length of the signature in MSG_SIGNATURE. */ 16075 #define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_MSG_SIGNATURE_LEN_OFST 0 16076 #define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_MSG_SIGNATURE_LEN_LEN 4 16077 /* Signature over the message, starting at MESSAGE_TYPE and continuing to the 16078 * end of the MCDI response, allowing the message format to be extended. The 16079 * signature uses ECDSA 384 encoding in ASN.1 format. It has variable length, 16080 * with a maximum of 384 bytes. 16081 */ 16082 #define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_MSG_SIGNATURE_OFST 4 16083 #define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_MSG_SIGNATURE_LEN 384 16084 /* Enum value indicating the type of response. This protects against chosen 16085 * message attacks. The enum values are random rather than sequential to make 16086 * it unlikely that values will be reused should other commands in a different 16087 * namespace need to create signed messages. 16088 */ 16089 #define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_MESSAGE_TYPE_OFST 388 16090 #define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_MESSAGE_TYPE_LEN 4 16091 /* enum: Message type value for the response to a 16092 * MC_CMD_SECURE_NIC_INFO_IN_STATUS message. 16093 */ 16094 #define MC_CMD_SECURE_NIC_INFO_STATUS 0xdb4 16095 /* The challenge provided by the host in the MC_CMD_SECURE_NIC_INFO_IN_STATUS 16096 * message 16097 */ 16098 #define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_CHALLENGE_OFST 392 16099 #define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_CHALLENGE_LEN 16 16100 /* The first 32 bits of XPM memory, which include security and flag bits, die 16101 * ID and chip ID revision. The meaning of these bits is defined in 16102 * mc/include/mc/xpm.h in the firmwaresrc repository. 16103 */ 16104 #define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_XPM_STATUS_BITS_OFST 408 16105 #define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_XPM_STATUS_BITS_LEN 4 16106 #define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_FIRMWARE_VERSION_A_OFST 412 16107 #define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_FIRMWARE_VERSION_A_LEN 2 16108 #define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_FIRMWARE_VERSION_B_OFST 414 16109 #define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_FIRMWARE_VERSION_B_LEN 2 16110 #define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_FIRMWARE_VERSION_C_OFST 416 16111 #define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_FIRMWARE_VERSION_C_LEN 2 16112 #define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_FIRMWARE_VERSION_D_OFST 418 16113 #define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_FIRMWARE_VERSION_D_LEN 2 16114 16115 16116 /***********************************/ 16117 /* MC_CMD_TSA_TEST 16118 * A simple ping-pong command just to test the adapter<>controller MCDI 16119 * communication channel. This command makes not changes to the TSA adapter's 16120 * internal state. It is used by the controller just to verify that the MCDI 16121 * communication channel is working fine. This command takes no additonal 16122 * parameters in request or response. 16123 */ 16124 #define MC_CMD_TSA_TEST 0x125 16125 #undef MC_CMD_0x125_PRIVILEGE_CTG 16126 16127 #define MC_CMD_0x125_PRIVILEGE_CTG SRIOV_CTG_ADMIN 16128 16129 /* MC_CMD_TSA_TEST_IN msgrequest */ 16130 #define MC_CMD_TSA_TEST_IN_LEN 0 16131 16132 /* MC_CMD_TSA_TEST_OUT msgresponse */ 16133 #define MC_CMD_TSA_TEST_OUT_LEN 0 16134 16135 16136 /***********************************/ 16137 /* MC_CMD_TSA_RULESET_OVERRIDE 16138 * Override TSA ruleset that is currently active on the adapter. This operation 16139 * does not modify the ruleset itself. This operation provides a mechanism to 16140 * apply an allow-all or deny-all operation on all packets, thereby completely 16141 * ignoring the rule-set configured on the adapter. The main purpose of this 16142 * operation is to provide a deterministic state to the TSA firewall during 16143 * rule-set transitions. 16144 */ 16145 #define MC_CMD_TSA_RULESET_OVERRIDE 0x12a 16146 #undef MC_CMD_0x12a_PRIVILEGE_CTG 16147 16148 #define MC_CMD_0x12a_PRIVILEGE_CTG SRIOV_CTG_ADMIN 16149 16150 /* MC_CMD_TSA_RULESET_OVERRIDE_IN msgrequest */ 16151 #define MC_CMD_TSA_RULESET_OVERRIDE_IN_LEN 4 16152 /* The override state to apply. */ 16153 #define MC_CMD_TSA_RULESET_OVERRIDE_IN_STATE_OFST 0 16154 #define MC_CMD_TSA_RULESET_OVERRIDE_IN_STATE_LEN 4 16155 /* enum: No override in place - the existing ruleset is in operation. */ 16156 #define MC_CMD_TSA_RULESET_OVERRIDE_NONE 0x0 16157 /* enum: Block all packets seen on all datapath channel except those packets 16158 * required for basic configuration of the TSA NIC such as ARPs and TSA- 16159 * communication traffic. Such exceptional traffic is handled differently 16160 * compared to TSA rulesets. 16161 */ 16162 #define MC_CMD_TSA_RULESET_OVERRIDE_BLOCK 0x1 16163 /* enum: Allow all packets through all datapath channel. The TSA adapter 16164 * behaves like a normal NIC without any firewalls. 16165 */ 16166 #define MC_CMD_TSA_RULESET_OVERRIDE_ALLOW 0x2 16167 16168 /* MC_CMD_TSA_RULESET_OVERRIDE_OUT msgresponse */ 16169 #define MC_CMD_TSA_RULESET_OVERRIDE_OUT_LEN 0 16170 16171 16172 /***********************************/ 16173 /* MC_CMD_TSAC_REQUEST 16174 * Generic command to send requests from a TSA controller to a TSA adapter. 16175 * Specific usage is determined by the TYPE field. 16176 */ 16177 #define MC_CMD_TSAC_REQUEST 0x12b 16178 #undef MC_CMD_0x12b_PRIVILEGE_CTG 16179 16180 #define MC_CMD_0x12b_PRIVILEGE_CTG SRIOV_CTG_ADMIN 16181 16182 /* MC_CMD_TSAC_REQUEST_IN msgrequest */ 16183 #define MC_CMD_TSAC_REQUEST_IN_LEN 4 16184 /* The type of request from the controller. */ 16185 #define MC_CMD_TSAC_REQUEST_IN_TYPE_OFST 0 16186 #define MC_CMD_TSAC_REQUEST_IN_TYPE_LEN 4 16187 /* enum: Request the adapter to resend localIP information from it's cache. The 16188 * command does not return any IP address information; IP addresses are sent as 16189 * TSA notifications as descibed in MC_CMD_TSA_INFO_IN_LOCAL_IP. 16190 */ 16191 #define MC_CMD_TSAC_REQUEST_LOCALIP 0x0 16192 16193 /* MC_CMD_TSAC_REQUEST_OUT msgresponse */ 16194 #define MC_CMD_TSAC_REQUEST_OUT_LEN 0 16195 16196 16197 /***********************************/ 16198 /* MC_CMD_SUC_VERSION 16199 * Get the version of the SUC 16200 */ 16201 #define MC_CMD_SUC_VERSION 0x134 16202 #undef MC_CMD_0x134_PRIVILEGE_CTG 16203 16204 #define MC_CMD_0x134_PRIVILEGE_CTG SRIOV_CTG_ADMIN 16205 16206 /* MC_CMD_SUC_VERSION_IN msgrequest */ 16207 #define MC_CMD_SUC_VERSION_IN_LEN 0 16208 16209 /* MC_CMD_SUC_VERSION_OUT msgresponse */ 16210 #define MC_CMD_SUC_VERSION_OUT_LEN 24 16211 /* The SUC firmware version as four numbers - a.b.c.d */ 16212 #define MC_CMD_SUC_VERSION_OUT_VERSION_OFST 0 16213 #define MC_CMD_SUC_VERSION_OUT_VERSION_LEN 4 16214 #define MC_CMD_SUC_VERSION_OUT_VERSION_NUM 4 16215 /* The date, in seconds since the Unix epoch, when the firmware image was 16216 * built. 16217 */ 16218 #define MC_CMD_SUC_VERSION_OUT_BUILD_DATE_OFST 16 16219 #define MC_CMD_SUC_VERSION_OUT_BUILD_DATE_LEN 4 16220 /* The ID of the SUC chip. This is specific to the platform but typically 16221 * indicates family, memory sizes etc. See SF-116728-SW for further details. 16222 */ 16223 #define MC_CMD_SUC_VERSION_OUT_CHIP_ID_OFST 20 16224 #define MC_CMD_SUC_VERSION_OUT_CHIP_ID_LEN 4 16225 16226 16227 /***********************************/ 16228 /* MC_CMD_SUC_MANFTEST 16229 * Operations to support manftest on SUC based systems. 16230 */ 16231 #define MC_CMD_SUC_MANFTEST 0x135 16232 #undef MC_CMD_0x135_PRIVILEGE_CTG 16233 16234 #define MC_CMD_0x135_PRIVILEGE_CTG SRIOV_CTG_ADMIN 16235 16236 /* MC_CMD_SUC_MANFTEST_IN msgrequest */ 16237 #define MC_CMD_SUC_MANFTEST_IN_LEN 4 16238 /* The manftest operation to be performed. */ 16239 #define MC_CMD_SUC_MANFTEST_IN_OP_OFST 0 16240 #define MC_CMD_SUC_MANFTEST_IN_OP_LEN 4 16241 /* enum: Read serial number and use count. */ 16242 #define MC_CMD_SUC_MANFTEST_WEAROUT_READ 0x0 16243 /* enum: Update use count on wearout adapter. */ 16244 #define MC_CMD_SUC_MANFTEST_WEAROUT_UPDATE 0x1 16245 /* enum: Start an ADC calibration. */ 16246 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_START 0x2 16247 /* enum: Read the status of an ADC calibration. */ 16248 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS 0x3 16249 /* enum: Read the results of an ADC calibration. */ 16250 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_RESULT 0x4 16251 /* enum: Read the PCIe configuration. */ 16252 #define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_READ 0x5 16253 /* enum: Write the PCIe configuration. */ 16254 #define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_WRITE 0x6 16255 16256 /* MC_CMD_SUC_MANFTEST_OUT msgresponse */ 16257 #define MC_CMD_SUC_MANFTEST_OUT_LEN 0 16258 16259 /* MC_CMD_SUC_MANFTEST_WEAROUT_READ_IN msgrequest */ 16260 #define MC_CMD_SUC_MANFTEST_WEAROUT_READ_IN_LEN 4 16261 /* The manftest operation to be performed. This must be 16262 * MC_CMD_SUC_MANFTEST_WEAROUT_READ. 16263 */ 16264 #define MC_CMD_SUC_MANFTEST_WEAROUT_READ_IN_OP_OFST 0 16265 #define MC_CMD_SUC_MANFTEST_WEAROUT_READ_IN_OP_LEN 4 16266 16267 /* MC_CMD_SUC_MANFTEST_WEAROUT_READ_OUT msgresponse */ 16268 #define MC_CMD_SUC_MANFTEST_WEAROUT_READ_OUT_LEN 20 16269 /* The serial number of the wearout adapter, see SF-112717-PR for format. */ 16270 #define MC_CMD_SUC_MANFTEST_WEAROUT_READ_OUT_SERIAL_NUMBER_OFST 0 16271 #define MC_CMD_SUC_MANFTEST_WEAROUT_READ_OUT_SERIAL_NUMBER_LEN 16 16272 /* The use count of the wearout adapter. */ 16273 #define MC_CMD_SUC_MANFTEST_WEAROUT_READ_OUT_USE_COUNT_OFST 16 16274 #define MC_CMD_SUC_MANFTEST_WEAROUT_READ_OUT_USE_COUNT_LEN 4 16275 16276 /* MC_CMD_SUC_MANFTEST_WEAROUT_UPDATE_IN msgrequest */ 16277 #define MC_CMD_SUC_MANFTEST_WEAROUT_UPDATE_IN_LEN 4 16278 /* The manftest operation to be performed. This must be 16279 * MC_CMD_SUC_MANFTEST_WEAROUT_UPDATE. 16280 */ 16281 #define MC_CMD_SUC_MANFTEST_WEAROUT_UPDATE_IN_OP_OFST 0 16282 #define MC_CMD_SUC_MANFTEST_WEAROUT_UPDATE_IN_OP_LEN 4 16283 16284 /* MC_CMD_SUC_MANFTEST_WEAROUT_UPDATE_OUT msgresponse */ 16285 #define MC_CMD_SUC_MANFTEST_WEAROUT_UPDATE_OUT_LEN 0 16286 16287 /* MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_START_IN msgrequest */ 16288 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_START_IN_LEN 4 16289 /* The manftest operation to be performed. This must be 16290 * MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_START. 16291 */ 16292 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_START_IN_OP_OFST 0 16293 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_START_IN_OP_LEN 4 16294 16295 /* MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_START_OUT msgresponse */ 16296 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_START_OUT_LEN 0 16297 16298 /* MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_IN msgrequest */ 16299 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_IN_LEN 4 16300 /* The manftest operation to be performed. This must be 16301 * MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS. 16302 */ 16303 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_IN_OP_OFST 0 16304 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_IN_OP_LEN 4 16305 16306 /* MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT msgresponse */ 16307 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT_LEN 4 16308 /* The combined status of the calibration operation. */ 16309 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT_FLAGS_OFST 0 16310 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT_FLAGS_LEN 4 16311 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT_CALIBRATING_LBN 0 16312 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT_CALIBRATING_WIDTH 1 16313 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT_FAILED_LBN 1 16314 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT_FAILED_WIDTH 1 16315 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT_RESULT_LBN 2 16316 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT_RESULT_WIDTH 4 16317 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT_INDEX_LBN 6 16318 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT_INDEX_WIDTH 2 16319 16320 /* MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_RESULT_IN msgrequest */ 16321 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_RESULT_IN_LEN 4 16322 /* The manftest operation to be performed. This must be 16323 * MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_RESULT. 16324 */ 16325 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_RESULT_IN_OP_OFST 0 16326 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_RESULT_IN_OP_LEN 4 16327 16328 /* MC_CMD_SUC_WEAROUT_ADC_CALIBRATE_RESULT_OUT msgresponse */ 16329 #define MC_CMD_SUC_WEAROUT_ADC_CALIBRATE_RESULT_OUT_LEN 12 16330 /* The set of calibration results. */ 16331 #define MC_CMD_SUC_WEAROUT_ADC_CALIBRATE_RESULT_OUT_VALUE_OFST 0 16332 #define MC_CMD_SUC_WEAROUT_ADC_CALIBRATE_RESULT_OUT_VALUE_LEN 4 16333 #define MC_CMD_SUC_WEAROUT_ADC_CALIBRATE_RESULT_OUT_VALUE_NUM 3 16334 16335 /* MC_CMD_SUC_MANFTEST_CONFIG_PCIE_READ_IN msgrequest */ 16336 #define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_READ_IN_LEN 4 16337 /* The manftest operation to be performed. This must be 16338 * MC_CMD_SUC_MANFTEST_CONFIG_PCIE_READ. 16339 */ 16340 #define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_READ_IN_OP_OFST 0 16341 #define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_READ_IN_OP_LEN 4 16342 16343 /* MC_CMD_SUC_WEAROUT_CONFIG_PCIE_READ_OUT msgresponse */ 16344 #define MC_CMD_SUC_WEAROUT_CONFIG_PCIE_READ_OUT_LEN 4 16345 /* The PCIe vendor ID. */ 16346 #define MC_CMD_SUC_WEAROUT_CONFIG_PCIE_READ_OUT_VENDOR_ID_OFST 0 16347 #define MC_CMD_SUC_WEAROUT_CONFIG_PCIE_READ_OUT_VENDOR_ID_LEN 2 16348 /* The PCIe device ID. */ 16349 #define MC_CMD_SUC_WEAROUT_CONFIG_PCIE_READ_OUT_DEVICE_ID_OFST 2 16350 #define MC_CMD_SUC_WEAROUT_CONFIG_PCIE_READ_OUT_DEVICE_ID_LEN 2 16351 16352 /* MC_CMD_SUC_MANFTEST_CONFIG_PCIE_WRITE_IN msgrequest */ 16353 #define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_WRITE_IN_LEN 8 16354 /* The manftest operation to be performed. This must be 16355 * MC_CMD_SUC_MANFTEST_CONFIG_PCIE_WRITE. 16356 */ 16357 #define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_WRITE_IN_OP_OFST 0 16358 #define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_WRITE_IN_OP_LEN 4 16359 /* The PCIe vendor ID. */ 16360 #define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_WRITE_IN_VENDOR_ID_OFST 4 16361 #define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_WRITE_IN_VENDOR_ID_LEN 2 16362 /* The PCIe device ID. */ 16363 #define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_WRITE_IN_DEVICE_ID_OFST 6 16364 #define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_WRITE_IN_DEVICE_ID_LEN 2 16365 16366 /* MC_CMD_SUC_MANFTEST_CONFIG_PCIE_WRITE_OUT msgresponse */ 16367 #define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_WRITE_OUT_LEN 0 16368 16369 #endif /* _SIENA_MC_DRIVER_PCOL_H */ 16370