1 /*- 2 * Copyright 2008-2013 Solarflare Communications Inc. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #ifndef _SIENA_MC_DRIVER_PCOL_H 29 #define _SIENA_MC_DRIVER_PCOL_H 30 31 32 /* Values to be written into FMCR_CZ_RESET_STATE_REG to control boot. */ 33 /* Power-on reset state */ 34 #define MC_FW_STATE_POR (1) 35 /* If this is set in MC_RESET_STATE_REG then it should be 36 * possible to jump into IMEM without loading code from flash. */ 37 #define MC_FW_WARM_BOOT_OK (2) 38 /* The MC main image has started to boot. */ 39 #define MC_FW_STATE_BOOTING (4) 40 /* The Scheduler has started. */ 41 #define MC_FW_STATE_SCHED (8) 42 /* If this is set in MC_RESET_STATE_REG then it should be 43 * possible to jump into IMEM without loading code from flash. 44 * Unlike a warm boot, assume DMEM has been reloaded, so that 45 * the MC persistent data must be reinitialised. */ 46 #define MC_FW_TEPID_BOOT_OK (16) 47 /* We have entered the main firmware via recovery mode. This 48 * means that MC persistent data must be reinitialised, but that 49 * we shouldn't touch PCIe config. */ 50 #define MC_FW_RECOVERY_MODE_PCIE_INIT_OK (32) 51 /* BIST state has been initialized */ 52 #define MC_FW_BIST_INIT_OK (128) 53 54 /* Siena MC shared memmory offsets */ 55 /* The 'doorbell' addresses are hard-wired to alert the MC when written */ 56 #define MC_SMEM_P0_DOORBELL_OFST 0x000 57 #define MC_SMEM_P1_DOORBELL_OFST 0x004 58 /* The rest of these are firmware-defined */ 59 #define MC_SMEM_P0_PDU_OFST 0x008 60 #define MC_SMEM_P1_PDU_OFST 0x108 61 #define MC_SMEM_PDU_LEN 0x100 62 #define MC_SMEM_P0_PTP_TIME_OFST 0x7f0 63 #define MC_SMEM_P0_STATUS_OFST 0x7f8 64 #define MC_SMEM_P1_STATUS_OFST 0x7fc 65 66 /* Values to be written to the per-port status dword in shared 67 * memory on reboot and assert */ 68 #define MC_STATUS_DWORD_REBOOT (0xb007b007) 69 #define MC_STATUS_DWORD_ASSERT (0xdeaddead) 70 71 /* Check whether an mcfw version (in host order) belongs to a bootloader */ 72 #define MC_FW_VERSION_IS_BOOTLOADER(_v) (((_v) >> 16) == 0xb007) 73 74 /* The current version of the MCDI protocol. 75 * 76 * Note that the ROM burnt into the card only talks V0, so at the very 77 * least every driver must support version 0 and MCDI_PCOL_VERSION 78 */ 79 #ifdef WITH_MCDI_V2 80 #define MCDI_PCOL_VERSION 2 81 #else 82 #define MCDI_PCOL_VERSION 1 83 #endif 84 85 /* Unused commands: 0x23, 0x27, 0x30, 0x31 */ 86 87 /* MCDI version 1 88 * 89 * Each MCDI request starts with an MCDI_HEADER, which is a 32bit 90 * structure, filled in by the client. 91 * 92 * 0 7 8 16 20 22 23 24 31 93 * | CODE | R | LEN | SEQ | Rsvd | E | R | XFLAGS | 94 * | | | 95 * | | \--- Response 96 * | \------- Error 97 * \------------------------------ Resync (always set) 98 * 99 * The client writes it's request into MC shared memory, and rings the 100 * doorbell. Each request is completed by either by the MC writting 101 * back into shared memory, or by writting out an event. 102 * 103 * All MCDI commands support completion by shared memory response. Each 104 * request may also contain additional data (accounted for by HEADER.LEN), 105 * and some response's may also contain additional data (again, accounted 106 * for by HEADER.LEN). 107 * 108 * Some MCDI commands support completion by event, in which any associated 109 * response data is included in the event. 110 * 111 * The protocol requires one response to be delivered for every request, a 112 * request should not be sent unless the response for the previous request 113 * has been received (either by polling shared memory, or by receiving 114 * an event). 115 */ 116 117 /** Request/Response structure */ 118 #define MCDI_HEADER_OFST 0 119 #define MCDI_HEADER_CODE_LBN 0 120 #define MCDI_HEADER_CODE_WIDTH 7 121 #define MCDI_HEADER_RESYNC_LBN 7 122 #define MCDI_HEADER_RESYNC_WIDTH 1 123 #define MCDI_HEADER_DATALEN_LBN 8 124 #define MCDI_HEADER_DATALEN_WIDTH 8 125 #define MCDI_HEADER_SEQ_LBN 16 126 #define MCDI_HEADER_SEQ_WIDTH 4 127 #define MCDI_HEADER_RSVD_LBN 20 128 #define MCDI_HEADER_RSVD_WIDTH 1 129 #define MCDI_HEADER_NOT_EPOCH_LBN 21 130 #define MCDI_HEADER_NOT_EPOCH_WIDTH 1 131 #define MCDI_HEADER_ERROR_LBN 22 132 #define MCDI_HEADER_ERROR_WIDTH 1 133 #define MCDI_HEADER_RESPONSE_LBN 23 134 #define MCDI_HEADER_RESPONSE_WIDTH 1 135 #define MCDI_HEADER_XFLAGS_LBN 24 136 #define MCDI_HEADER_XFLAGS_WIDTH 8 137 /* Request response using event */ 138 #define MCDI_HEADER_XFLAGS_EVREQ 0x01 139 140 /* Maximum number of payload bytes */ 141 #define MCDI_CTL_SDU_LEN_MAX_V1 0xfc 142 #define MCDI_CTL_SDU_LEN_MAX_V2 0x400 143 144 #ifdef WITH_MCDI_V2 145 #define MCDI_CTL_SDU_LEN_MAX MCDI_CTL_SDU_LEN_MAX_V2 146 #else 147 #define MCDI_CTL_SDU_LEN_MAX MCDI_CTL_SDU_LEN_MAX_V1 148 #endif 149 150 151 /* The MC can generate events for two reasons: 152 * - To complete a shared memory request if XFLAGS_EVREQ was set 153 * - As a notification (link state, i2c event), controlled 154 * via MC_CMD_LOG_CTRL 155 * 156 * Both events share a common structure: 157 * 158 * 0 32 33 36 44 52 60 159 * | Data | Cont | Level | Src | Code | Rsvd | 160 * | 161 * \ There is another event pending in this notification 162 * 163 * If Code==CMDDONE, then the fields are further interpreted as: 164 * 165 * - LEVEL==INFO Command succeeded 166 * - LEVEL==ERR Command failed 167 * 168 * 0 8 16 24 32 169 * | Seq | Datalen | Errno | Rsvd | 170 * 171 * These fields are taken directly out of the standard MCDI header, i.e., 172 * LEVEL==ERR, Datalen == 0 => Reboot 173 * 174 * Events can be squirted out of the UART (using LOG_CTRL) without a 175 * MCDI header. An event can be distinguished from a MCDI response by 176 * examining the first byte which is 0xc0. This corresponds to the 177 * non-existent MCDI command MC_CMD_DEBUG_LOG. 178 * 179 * 0 7 8 180 * | command | Resync | = 0xc0 181 * 182 * Since the event is written in big-endian byte order, this works 183 * providing bits 56-63 of the event are 0xc0. 184 * 185 * 56 60 63 186 * | Rsvd | Code | = 0xc0 187 * 188 * Which means for convenience the event code is 0xc for all MC 189 * generated events. 190 */ 191 #define FSE_AZ_EV_CODE_MCDI_EVRESPONSE 0xc 192 193 194 /* Operation not permitted. */ 195 #define MC_CMD_ERR_EPERM 1 196 /* Non-existent command target */ 197 #define MC_CMD_ERR_ENOENT 2 198 /* assert() has killed the MC */ 199 #define MC_CMD_ERR_EINTR 4 200 /* I/O failure */ 201 #define MC_CMD_ERR_EIO 5 202 /* Already exists */ 203 #define MC_CMD_ERR_EEXIST 6 204 /* Try again */ 205 #define MC_CMD_ERR_EAGAIN 11 206 /* Out of memory */ 207 #define MC_CMD_ERR_ENOMEM 12 208 /* Caller does not hold required locks */ 209 #define MC_CMD_ERR_EACCES 13 210 /* Resource is currently unavailable (e.g. lock contention) */ 211 #define MC_CMD_ERR_EBUSY 16 212 /* No such device */ 213 #define MC_CMD_ERR_ENODEV 19 214 /* Invalid argument to target */ 215 #define MC_CMD_ERR_EINVAL 22 216 /* Broken pipe */ 217 #define MC_CMD_ERR_EPIPE 32 218 /* Read-only */ 219 #define MC_CMD_ERR_EROFS 30 220 /* Out of range */ 221 #define MC_CMD_ERR_ERANGE 34 222 /* Non-recursive resource is already acquired */ 223 #define MC_CMD_ERR_EDEADLK 35 224 /* Operation not implemented */ 225 #define MC_CMD_ERR_ENOSYS 38 226 /* Operation timed out */ 227 #define MC_CMD_ERR_ETIME 62 228 /* Link has been severed */ 229 #define MC_CMD_ERR_ENOLINK 67 230 /* Protocol error */ 231 #define MC_CMD_ERR_EPROTO 71 232 /* Operation not supported */ 233 #define MC_CMD_ERR_ENOTSUP 95 234 /* Address not available */ 235 #define MC_CMD_ERR_EADDRNOTAVAIL 99 236 /* Not connected */ 237 #define MC_CMD_ERR_ENOTCONN 107 238 /* Operation already in progress */ 239 #define MC_CMD_ERR_EALREADY 114 240 241 /* Resource allocation failed. */ 242 #define MC_CMD_ERR_ALLOC_FAIL 0x1000 243 /* V-adaptor not found. */ 244 #define MC_CMD_ERR_NO_VADAPTOR 0x1001 245 /* EVB port not found. */ 246 #define MC_CMD_ERR_NO_EVB_PORT 0x1002 247 /* V-switch not found. */ 248 #define MC_CMD_ERR_NO_VSWITCH 0x1003 249 /* Too many VLAN tags. */ 250 #define MC_CMD_ERR_VLAN_LIMIT 0x1004 251 /* Bad PCI function number. */ 252 #define MC_CMD_ERR_BAD_PCI_FUNC 0x1005 253 /* Invalid VLAN mode. */ 254 #define MC_CMD_ERR_BAD_VLAN_MODE 0x1006 255 /* Invalid v-switch type. */ 256 #define MC_CMD_ERR_BAD_VSWITCH_TYPE 0x1007 257 /* Invalid v-port type. */ 258 #define MC_CMD_ERR_BAD_VPORT_TYPE 0x1008 259 /* MAC address exists. */ 260 #define MC_CMD_ERR_MAC_EXIST 0x1009 261 /* Slave core not present */ 262 #define MC_CMD_ERR_SLAVE_NOT_PRESENT 0x100a 263 /* The datapath is disabled. */ 264 #define MC_CMD_ERR_DATAPATH_DISABLED 0x100b 265 /* The requesting client is not a function */ 266 #define MC_CMD_ERR_CLIENT_NOT_FN 0x100c 267 /* The requested operation might require the 268 command to be passed between MCs, and the 269 transport doesn't support that. Should 270 only ever been seen over the UART. */ 271 #define MC_CMD_ERR_TRANSPORT_NOPROXY 0x100d 272 /* VLAN tag(s) exists */ 273 #define MC_CMD_ERR_VLAN_EXIST 0x100e 274 /* No MAC address assigned to an EVB port */ 275 #define MC_CMD_ERR_NO_MAC_ADDR 0x100f 276 /* Notifies the driver that the request has been relayed 277 * to an admin function for authorization. The driver should 278 * wait for a PROXY_RESPONSE event and then resend its request. 279 * This error code is followed by a 32-bit handle that 280 * helps matching it with the respective PROXY_RESPONSE event. */ 281 #define MC_CMD_ERR_PROXY_PENDING 0x1010 282 #define MC_CMD_ERR_PROXY_PENDING_HANDLE_OFST 4 283 /* The request cannot be passed for authorization because 284 * another request from the same function is currently being 285 * authorized. The drvier should try again later. */ 286 #define MC_CMD_ERR_PROXY_INPROGRESS 0x1011 287 /* Returned by MC_CMD_PROXY_COMPLETE if the caller is not the function 288 * that has enabled proxying or BLOCK_INDEX points to a function that 289 * doesn't await an authorization. */ 290 #define MC_CMD_ERR_PROXY_UNEXPECTED 0x1012 291 /* This code is currently only used internally in FW. Its meaning is that 292 * an operation failed due to lack of SR-IOV privilege. 293 * Normally it is translated to EPERM by send_cmd_err(), 294 * but it may also be used to trigger some special mechanism 295 * for handling such case, e.g. to relay the failed request 296 * to a designated admin function for authorization. */ 297 #define MC_CMD_ERR_NO_PRIVILEGE 0x1013 298 /* Workaround 26807 could not be turned on/off because some functions 299 * have already installed filters. See the comment at 300 * MC_CMD_WORKAROUND_BUG26807. */ 301 #define MC_CMD_ERR_FILTERS_PRESENT 0x1014 302 /* The clock whose frequency you've attempted to set set 303 * doesn't exist on this NIC */ 304 #define MC_CMD_ERR_NO_CLOCK 0x1015 305 306 #define MC_CMD_ERR_CODE_OFST 0 307 308 /* We define 8 "escape" commands to allow 309 for command number space extension */ 310 311 #define MC_CMD_CMD_SPACE_ESCAPE_0 0x78 312 #define MC_CMD_CMD_SPACE_ESCAPE_1 0x79 313 #define MC_CMD_CMD_SPACE_ESCAPE_2 0x7A 314 #define MC_CMD_CMD_SPACE_ESCAPE_3 0x7B 315 #define MC_CMD_CMD_SPACE_ESCAPE_4 0x7C 316 #define MC_CMD_CMD_SPACE_ESCAPE_5 0x7D 317 #define MC_CMD_CMD_SPACE_ESCAPE_6 0x7E 318 #define MC_CMD_CMD_SPACE_ESCAPE_7 0x7F 319 320 /* Vectors in the boot ROM */ 321 /* Point to the copycode entry point. */ 322 #define SIENA_MC_BOOTROM_COPYCODE_VEC (0x800 - 3 * 0x4) 323 #define HUNT_MC_BOOTROM_COPYCODE_VEC (0x8000 - 3 * 0x4) 324 #define MEDFORD_MC_BOOTROM_COPYCODE_VEC (0x10000 - 3 * 0x4) 325 /* Points to the recovery mode entry point. */ 326 #define SIENA_MC_BOOTROM_NOFLASH_VEC (0x800 - 2 * 0x4) 327 #define HUNT_MC_BOOTROM_NOFLASH_VEC (0x8000 - 2 * 0x4) 328 #define MEDFORD_MC_BOOTROM_NOFLASH_VEC (0x10000 - 2 * 0x4) 329 330 /* The command set exported by the boot ROM (MCDI v0) */ 331 #define MC_CMD_GET_VERSION_V0_SUPPORTED_FUNCS { \ 332 (1 << MC_CMD_READ32) | \ 333 (1 << MC_CMD_WRITE32) | \ 334 (1 << MC_CMD_COPYCODE) | \ 335 (1 << MC_CMD_GET_VERSION), \ 336 0, 0, 0 } 337 338 #define MC_CMD_SENSOR_INFO_OUT_OFFSET_OFST(_x) \ 339 (MC_CMD_SENSOR_ENTRY_OFST + (_x)) 340 341 #define MC_CMD_DBI_WRITE_IN_ADDRESS_OFST(n) \ 342 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \ 343 MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST + \ 344 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN) 345 346 #define MC_CMD_DBI_WRITE_IN_BYTE_MASK_OFST(n) \ 347 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \ 348 MC_CMD_DBIWROP_TYPEDEF_BYTE_MASK_OFST + \ 349 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN) 350 351 #define MC_CMD_DBI_WRITE_IN_VALUE_OFST(n) \ 352 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \ 353 MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST + \ 354 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN) 355 356 /* This may be ORed with an EVB_PORT_ID_xxx constant to pass a non-default 357 * stack ID (which must be in the range 1-255) along with an EVB port ID. 358 */ 359 #define EVB_STACK_ID(n) (((n) & 0xff) << 16) 360 361 362 #ifdef WITH_MCDI_V2 363 364 /* Version 2 adds an optional argument to error returns: the errno value 365 * may be followed by the (0-based) number of the first argument that 366 * could not be processed. 367 */ 368 #define MC_CMD_ERR_ARG_OFST 4 369 370 /* No space */ 371 #define MC_CMD_ERR_ENOSPC 28 372 373 #endif 374 375 /* MCDI_EVENT structuredef */ 376 #define MCDI_EVENT_LEN 8 377 #define MCDI_EVENT_CONT_LBN 32 378 #define MCDI_EVENT_CONT_WIDTH 1 379 #define MCDI_EVENT_LEVEL_LBN 33 380 #define MCDI_EVENT_LEVEL_WIDTH 3 381 /* enum: Info. */ 382 #define MCDI_EVENT_LEVEL_INFO 0x0 383 /* enum: Warning. */ 384 #define MCDI_EVENT_LEVEL_WARN 0x1 385 /* enum: Error. */ 386 #define MCDI_EVENT_LEVEL_ERR 0x2 387 /* enum: Fatal. */ 388 #define MCDI_EVENT_LEVEL_FATAL 0x3 389 #define MCDI_EVENT_DATA_OFST 0 390 #define MCDI_EVENT_CMDDONE_SEQ_LBN 0 391 #define MCDI_EVENT_CMDDONE_SEQ_WIDTH 8 392 #define MCDI_EVENT_CMDDONE_DATALEN_LBN 8 393 #define MCDI_EVENT_CMDDONE_DATALEN_WIDTH 8 394 #define MCDI_EVENT_CMDDONE_ERRNO_LBN 16 395 #define MCDI_EVENT_CMDDONE_ERRNO_WIDTH 8 396 #define MCDI_EVENT_LINKCHANGE_LP_CAP_LBN 0 397 #define MCDI_EVENT_LINKCHANGE_LP_CAP_WIDTH 16 398 #define MCDI_EVENT_LINKCHANGE_SPEED_LBN 16 399 #define MCDI_EVENT_LINKCHANGE_SPEED_WIDTH 4 400 /* enum: 100Mbs */ 401 #define MCDI_EVENT_LINKCHANGE_SPEED_100M 0x1 402 /* enum: 1Gbs */ 403 #define MCDI_EVENT_LINKCHANGE_SPEED_1G 0x2 404 /* enum: 10Gbs */ 405 #define MCDI_EVENT_LINKCHANGE_SPEED_10G 0x3 406 /* enum: 40Gbs */ 407 #define MCDI_EVENT_LINKCHANGE_SPEED_40G 0x4 408 #define MCDI_EVENT_LINKCHANGE_FCNTL_LBN 20 409 #define MCDI_EVENT_LINKCHANGE_FCNTL_WIDTH 4 410 #define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_LBN 24 411 #define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_WIDTH 8 412 #define MCDI_EVENT_SENSOREVT_MONITOR_LBN 0 413 #define MCDI_EVENT_SENSOREVT_MONITOR_WIDTH 8 414 #define MCDI_EVENT_SENSOREVT_STATE_LBN 8 415 #define MCDI_EVENT_SENSOREVT_STATE_WIDTH 8 416 #define MCDI_EVENT_SENSOREVT_VALUE_LBN 16 417 #define MCDI_EVENT_SENSOREVT_VALUE_WIDTH 16 418 #define MCDI_EVENT_FWALERT_DATA_LBN 8 419 #define MCDI_EVENT_FWALERT_DATA_WIDTH 24 420 #define MCDI_EVENT_FWALERT_REASON_LBN 0 421 #define MCDI_EVENT_FWALERT_REASON_WIDTH 8 422 /* enum: SRAM Access. */ 423 #define MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS 0x1 424 #define MCDI_EVENT_FLR_VF_LBN 0 425 #define MCDI_EVENT_FLR_VF_WIDTH 8 426 #define MCDI_EVENT_TX_ERR_TXQ_LBN 0 427 #define MCDI_EVENT_TX_ERR_TXQ_WIDTH 12 428 #define MCDI_EVENT_TX_ERR_TYPE_LBN 12 429 #define MCDI_EVENT_TX_ERR_TYPE_WIDTH 4 430 /* enum: Descriptor loader reported failure */ 431 #define MCDI_EVENT_TX_ERR_DL_FAIL 0x1 432 /* enum: Descriptor ring empty and no EOP seen for packet */ 433 #define MCDI_EVENT_TX_ERR_NO_EOP 0x2 434 /* enum: Overlength packet */ 435 #define MCDI_EVENT_TX_ERR_2BIG 0x3 436 /* enum: Malformed option descriptor */ 437 #define MCDI_EVENT_TX_BAD_OPTDESC 0x5 438 /* enum: Option descriptor part way through a packet */ 439 #define MCDI_EVENT_TX_OPT_IN_PKT 0x8 440 /* enum: DMA or PIO data access error */ 441 #define MCDI_EVENT_TX_ERR_BAD_DMA_OR_PIO 0x9 442 #define MCDI_EVENT_TX_ERR_INFO_LBN 16 443 #define MCDI_EVENT_TX_ERR_INFO_WIDTH 16 444 #define MCDI_EVENT_TX_FLUSH_TO_DRIVER_LBN 12 445 #define MCDI_EVENT_TX_FLUSH_TO_DRIVER_WIDTH 1 446 #define MCDI_EVENT_TX_FLUSH_TXQ_LBN 0 447 #define MCDI_EVENT_TX_FLUSH_TXQ_WIDTH 12 448 #define MCDI_EVENT_PTP_ERR_TYPE_LBN 0 449 #define MCDI_EVENT_PTP_ERR_TYPE_WIDTH 8 450 /* enum: PLL lost lock */ 451 #define MCDI_EVENT_PTP_ERR_PLL_LOST 0x1 452 /* enum: Filter overflow (PDMA) */ 453 #define MCDI_EVENT_PTP_ERR_FILTER 0x2 454 /* enum: FIFO overflow (FPGA) */ 455 #define MCDI_EVENT_PTP_ERR_FIFO 0x3 456 /* enum: Merge queue overflow */ 457 #define MCDI_EVENT_PTP_ERR_QUEUE 0x4 458 #define MCDI_EVENT_AOE_ERR_TYPE_LBN 0 459 #define MCDI_EVENT_AOE_ERR_TYPE_WIDTH 8 460 /* enum: AOE failed to load - no valid image? */ 461 #define MCDI_EVENT_AOE_NO_LOAD 0x1 462 /* enum: AOE FC reported an exception */ 463 #define MCDI_EVENT_AOE_FC_ASSERT 0x2 464 /* enum: AOE FC watchdogged */ 465 #define MCDI_EVENT_AOE_FC_WATCHDOG 0x3 466 /* enum: AOE FC failed to start */ 467 #define MCDI_EVENT_AOE_FC_NO_START 0x4 468 /* enum: Generic AOE fault - likely to have been reported via other means too 469 * but intended for use by aoex driver. 470 */ 471 #define MCDI_EVENT_AOE_FAULT 0x5 472 /* enum: Results of reprogramming the CPLD (status in AOE_ERR_DATA) */ 473 #define MCDI_EVENT_AOE_CPLD_REPROGRAMMED 0x6 474 /* enum: AOE loaded successfully */ 475 #define MCDI_EVENT_AOE_LOAD 0x7 476 /* enum: AOE DMA operation completed (LSB of HOST_HANDLE in AOE_ERR_DATA) */ 477 #define MCDI_EVENT_AOE_DMA 0x8 478 /* enum: AOE byteblaster connected/disconnected (Connection status in 479 * AOE_ERR_DATA) 480 */ 481 #define MCDI_EVENT_AOE_BYTEBLASTER 0x9 482 /* enum: DDR ECC status update */ 483 #define MCDI_EVENT_AOE_DDR_ECC_STATUS 0xa 484 /* enum: PTP status update */ 485 #define MCDI_EVENT_AOE_PTP_STATUS 0xb 486 #define MCDI_EVENT_AOE_ERR_DATA_LBN 8 487 #define MCDI_EVENT_AOE_ERR_DATA_WIDTH 8 488 #define MCDI_EVENT_RX_ERR_RXQ_LBN 0 489 #define MCDI_EVENT_RX_ERR_RXQ_WIDTH 12 490 #define MCDI_EVENT_RX_ERR_TYPE_LBN 12 491 #define MCDI_EVENT_RX_ERR_TYPE_WIDTH 4 492 #define MCDI_EVENT_RX_ERR_INFO_LBN 16 493 #define MCDI_EVENT_RX_ERR_INFO_WIDTH 16 494 #define MCDI_EVENT_RX_FLUSH_TO_DRIVER_LBN 12 495 #define MCDI_EVENT_RX_FLUSH_TO_DRIVER_WIDTH 1 496 #define MCDI_EVENT_RX_FLUSH_RXQ_LBN 0 497 #define MCDI_EVENT_RX_FLUSH_RXQ_WIDTH 12 498 #define MCDI_EVENT_MC_REBOOT_COUNT_LBN 0 499 #define MCDI_EVENT_MC_REBOOT_COUNT_WIDTH 16 500 #define MCDI_EVENT_MUM_ERR_TYPE_LBN 0 501 #define MCDI_EVENT_MUM_ERR_TYPE_WIDTH 8 502 /* enum: MUM failed to load - no valid image? */ 503 #define MCDI_EVENT_MUM_NO_LOAD 0x1 504 /* enum: MUM f/w reported an exception */ 505 #define MCDI_EVENT_MUM_ASSERT 0x2 506 /* enum: MUM not kicking watchdog */ 507 #define MCDI_EVENT_MUM_WATCHDOG 0x3 508 #define MCDI_EVENT_MUM_ERR_DATA_LBN 8 509 #define MCDI_EVENT_MUM_ERR_DATA_WIDTH 8 510 #define MCDI_EVENT_DATA_LBN 0 511 #define MCDI_EVENT_DATA_WIDTH 32 512 #define MCDI_EVENT_SRC_LBN 36 513 #define MCDI_EVENT_SRC_WIDTH 8 514 #define MCDI_EVENT_EV_CODE_LBN 60 515 #define MCDI_EVENT_EV_CODE_WIDTH 4 516 #define MCDI_EVENT_CODE_LBN 44 517 #define MCDI_EVENT_CODE_WIDTH 8 518 /* enum: Event generated by host software */ 519 #define MCDI_EVENT_SW_EVENT 0x0 520 /* enum: Bad assert. */ 521 #define MCDI_EVENT_CODE_BADSSERT 0x1 522 /* enum: PM Notice. */ 523 #define MCDI_EVENT_CODE_PMNOTICE 0x2 524 /* enum: Command done. */ 525 #define MCDI_EVENT_CODE_CMDDONE 0x3 526 /* enum: Link change. */ 527 #define MCDI_EVENT_CODE_LINKCHANGE 0x4 528 /* enum: Sensor Event. */ 529 #define MCDI_EVENT_CODE_SENSOREVT 0x5 530 /* enum: Schedule error. */ 531 #define MCDI_EVENT_CODE_SCHEDERR 0x6 532 /* enum: Reboot. */ 533 #define MCDI_EVENT_CODE_REBOOT 0x7 534 /* enum: Mac stats DMA. */ 535 #define MCDI_EVENT_CODE_MAC_STATS_DMA 0x8 536 /* enum: Firmware alert. */ 537 #define MCDI_EVENT_CODE_FWALERT 0x9 538 /* enum: Function level reset. */ 539 #define MCDI_EVENT_CODE_FLR 0xa 540 /* enum: Transmit error */ 541 #define MCDI_EVENT_CODE_TX_ERR 0xb 542 /* enum: Tx flush has completed */ 543 #define MCDI_EVENT_CODE_TX_FLUSH 0xc 544 /* enum: PTP packet received timestamp */ 545 #define MCDI_EVENT_CODE_PTP_RX 0xd 546 /* enum: PTP NIC failure */ 547 #define MCDI_EVENT_CODE_PTP_FAULT 0xe 548 /* enum: PTP PPS event */ 549 #define MCDI_EVENT_CODE_PTP_PPS 0xf 550 /* enum: Rx flush has completed */ 551 #define MCDI_EVENT_CODE_RX_FLUSH 0x10 552 /* enum: Receive error */ 553 #define MCDI_EVENT_CODE_RX_ERR 0x11 554 /* enum: AOE fault */ 555 #define MCDI_EVENT_CODE_AOE 0x12 556 /* enum: Network port calibration failed (VCAL). */ 557 #define MCDI_EVENT_CODE_VCAL_FAIL 0x13 558 /* enum: HW PPS event */ 559 #define MCDI_EVENT_CODE_HW_PPS 0x14 560 /* enum: The MC has rebooted (huntington and later, siena uses CODE_REBOOT and 561 * a different format) 562 */ 563 #define MCDI_EVENT_CODE_MC_REBOOT 0x15 564 /* enum: the MC has detected a parity error */ 565 #define MCDI_EVENT_CODE_PAR_ERR 0x16 566 /* enum: the MC has detected a correctable error */ 567 #define MCDI_EVENT_CODE_ECC_CORR_ERR 0x17 568 /* enum: the MC has detected an uncorrectable error */ 569 #define MCDI_EVENT_CODE_ECC_FATAL_ERR 0x18 570 /* enum: The MC has entered offline BIST mode */ 571 #define MCDI_EVENT_CODE_MC_BIST 0x19 572 /* enum: PTP tick event providing current NIC time */ 573 #define MCDI_EVENT_CODE_PTP_TIME 0x1a 574 /* enum: MUM fault */ 575 #define MCDI_EVENT_CODE_MUM 0x1b 576 /* enum: notify the designated PF of a new authorization request */ 577 #define MCDI_EVENT_CODE_PROXY_REQUEST 0x1c 578 /* enum: notify a function that awaits an authorization that its request has 579 * been processed and it may now resend the command 580 */ 581 #define MCDI_EVENT_CODE_PROXY_RESPONSE 0x1d 582 /* enum: Artificial event generated by host and posted via MC for test 583 * purposes. 584 */ 585 #define MCDI_EVENT_CODE_TESTGEN 0xfa 586 #define MCDI_EVENT_CMDDONE_DATA_OFST 0 587 #define MCDI_EVENT_CMDDONE_DATA_LBN 0 588 #define MCDI_EVENT_CMDDONE_DATA_WIDTH 32 589 #define MCDI_EVENT_LINKCHANGE_DATA_OFST 0 590 #define MCDI_EVENT_LINKCHANGE_DATA_LBN 0 591 #define MCDI_EVENT_LINKCHANGE_DATA_WIDTH 32 592 #define MCDI_EVENT_SENSOREVT_DATA_OFST 0 593 #define MCDI_EVENT_SENSOREVT_DATA_LBN 0 594 #define MCDI_EVENT_SENSOREVT_DATA_WIDTH 32 595 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_OFST 0 596 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_LBN 0 597 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_WIDTH 32 598 #define MCDI_EVENT_TX_ERR_DATA_OFST 0 599 #define MCDI_EVENT_TX_ERR_DATA_LBN 0 600 #define MCDI_EVENT_TX_ERR_DATA_WIDTH 32 601 /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the seconds field of 602 * timestamp 603 */ 604 #define MCDI_EVENT_PTP_SECONDS_OFST 0 605 #define MCDI_EVENT_PTP_SECONDS_LBN 0 606 #define MCDI_EVENT_PTP_SECONDS_WIDTH 32 607 /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the major field of 608 * timestamp 609 */ 610 #define MCDI_EVENT_PTP_MAJOR_OFST 0 611 #define MCDI_EVENT_PTP_MAJOR_LBN 0 612 #define MCDI_EVENT_PTP_MAJOR_WIDTH 32 613 /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the nanoseconds field 614 * of timestamp 615 */ 616 #define MCDI_EVENT_PTP_NANOSECONDS_OFST 0 617 #define MCDI_EVENT_PTP_NANOSECONDS_LBN 0 618 #define MCDI_EVENT_PTP_NANOSECONDS_WIDTH 32 619 /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the minor field of 620 * timestamp 621 */ 622 #define MCDI_EVENT_PTP_MINOR_OFST 0 623 #define MCDI_EVENT_PTP_MINOR_LBN 0 624 #define MCDI_EVENT_PTP_MINOR_WIDTH 32 625 /* For CODE_PTP_RX events, the lowest four bytes of sourceUUID from PTP packet 626 */ 627 #define MCDI_EVENT_PTP_UUID_OFST 0 628 #define MCDI_EVENT_PTP_UUID_LBN 0 629 #define MCDI_EVENT_PTP_UUID_WIDTH 32 630 #define MCDI_EVENT_RX_ERR_DATA_OFST 0 631 #define MCDI_EVENT_RX_ERR_DATA_LBN 0 632 #define MCDI_EVENT_RX_ERR_DATA_WIDTH 32 633 #define MCDI_EVENT_PAR_ERR_DATA_OFST 0 634 #define MCDI_EVENT_PAR_ERR_DATA_LBN 0 635 #define MCDI_EVENT_PAR_ERR_DATA_WIDTH 32 636 #define MCDI_EVENT_ECC_CORR_ERR_DATA_OFST 0 637 #define MCDI_EVENT_ECC_CORR_ERR_DATA_LBN 0 638 #define MCDI_EVENT_ECC_CORR_ERR_DATA_WIDTH 32 639 #define MCDI_EVENT_ECC_FATAL_ERR_DATA_OFST 0 640 #define MCDI_EVENT_ECC_FATAL_ERR_DATA_LBN 0 641 #define MCDI_EVENT_ECC_FATAL_ERR_DATA_WIDTH 32 642 /* For CODE_PTP_TIME events, the major value of the PTP clock */ 643 #define MCDI_EVENT_PTP_TIME_MAJOR_OFST 0 644 #define MCDI_EVENT_PTP_TIME_MAJOR_LBN 0 645 #define MCDI_EVENT_PTP_TIME_MAJOR_WIDTH 32 646 /* For CODE_PTP_TIME events, bits 19-26 of the minor value of the PTP clock */ 647 #define MCDI_EVENT_PTP_TIME_MINOR_26_19_LBN 36 648 #define MCDI_EVENT_PTP_TIME_MINOR_26_19_WIDTH 8 649 /* For CODE_PTP_TIME events where report sync status is enabled, indicates 650 * whether the NIC clock has ever been set 651 */ 652 #define MCDI_EVENT_PTP_TIME_NIC_CLOCK_VALID_LBN 36 653 #define MCDI_EVENT_PTP_TIME_NIC_CLOCK_VALID_WIDTH 1 654 /* For CODE_PTP_TIME events where report sync status is enabled, indicates 655 * whether the NIC and System clocks are in sync 656 */ 657 #define MCDI_EVENT_PTP_TIME_HOST_NIC_IN_SYNC_LBN 37 658 #define MCDI_EVENT_PTP_TIME_HOST_NIC_IN_SYNC_WIDTH 1 659 /* For CODE_PTP_TIME events where report sync status is enabled, bits 21-26 of 660 * the minor value of the PTP clock 661 */ 662 #define MCDI_EVENT_PTP_TIME_MINOR_26_21_LBN 38 663 #define MCDI_EVENT_PTP_TIME_MINOR_26_21_WIDTH 6 664 #define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_OFST 0 665 #define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_LBN 0 666 #define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_WIDTH 32 667 #define MCDI_EVENT_PROXY_RESPONSE_HANDLE_OFST 0 668 #define MCDI_EVENT_PROXY_RESPONSE_HANDLE_LBN 0 669 #define MCDI_EVENT_PROXY_RESPONSE_HANDLE_WIDTH 32 670 /* Zero means that the request has been completed or authorized, and the driver 671 * should resend it. A non-zero value means that the authorization has been 672 * denied, and gives the reason. Typically it will be EPERM. 673 */ 674 #define MCDI_EVENT_PROXY_RESPONSE_RC_LBN 36 675 #define MCDI_EVENT_PROXY_RESPONSE_RC_WIDTH 8 676 677 /* FCDI_EVENT structuredef */ 678 #define FCDI_EVENT_LEN 8 679 #define FCDI_EVENT_CONT_LBN 32 680 #define FCDI_EVENT_CONT_WIDTH 1 681 #define FCDI_EVENT_LEVEL_LBN 33 682 #define FCDI_EVENT_LEVEL_WIDTH 3 683 /* enum: Info. */ 684 #define FCDI_EVENT_LEVEL_INFO 0x0 685 /* enum: Warning. */ 686 #define FCDI_EVENT_LEVEL_WARN 0x1 687 /* enum: Error. */ 688 #define FCDI_EVENT_LEVEL_ERR 0x2 689 /* enum: Fatal. */ 690 #define FCDI_EVENT_LEVEL_FATAL 0x3 691 #define FCDI_EVENT_DATA_OFST 0 692 #define FCDI_EVENT_LINK_STATE_STATUS_LBN 0 693 #define FCDI_EVENT_LINK_STATE_STATUS_WIDTH 1 694 #define FCDI_EVENT_LINK_DOWN 0x0 /* enum */ 695 #define FCDI_EVENT_LINK_UP 0x1 /* enum */ 696 #define FCDI_EVENT_DATA_LBN 0 697 #define FCDI_EVENT_DATA_WIDTH 32 698 #define FCDI_EVENT_SRC_LBN 36 699 #define FCDI_EVENT_SRC_WIDTH 8 700 #define FCDI_EVENT_EV_CODE_LBN 60 701 #define FCDI_EVENT_EV_CODE_WIDTH 4 702 #define FCDI_EVENT_CODE_LBN 44 703 #define FCDI_EVENT_CODE_WIDTH 8 704 /* enum: The FC was rebooted. */ 705 #define FCDI_EVENT_CODE_REBOOT 0x1 706 /* enum: Bad assert. */ 707 #define FCDI_EVENT_CODE_ASSERT 0x2 708 /* enum: DDR3 test result. */ 709 #define FCDI_EVENT_CODE_DDR_TEST_RESULT 0x3 710 /* enum: Link status. */ 711 #define FCDI_EVENT_CODE_LINK_STATE 0x4 712 /* enum: A timed read is ready to be serviced. */ 713 #define FCDI_EVENT_CODE_TIMED_READ 0x5 714 /* enum: One or more PPS IN events */ 715 #define FCDI_EVENT_CODE_PPS_IN 0x6 716 /* enum: Tick event from PTP clock */ 717 #define FCDI_EVENT_CODE_PTP_TICK 0x7 718 /* enum: ECC error counters */ 719 #define FCDI_EVENT_CODE_DDR_ECC_STATUS 0x8 720 /* enum: Current status of PTP */ 721 #define FCDI_EVENT_CODE_PTP_STATUS 0x9 722 /* enum: Port id config to map MC-FC port idx */ 723 #define FCDI_EVENT_CODE_PORT_CONFIG 0xa 724 #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_OFST 0 725 #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_LBN 0 726 #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_WIDTH 32 727 #define FCDI_EVENT_ASSERT_TYPE_LBN 36 728 #define FCDI_EVENT_ASSERT_TYPE_WIDTH 8 729 #define FCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_LBN 36 730 #define FCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_WIDTH 8 731 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_OFST 0 732 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_LBN 0 733 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_WIDTH 32 734 #define FCDI_EVENT_LINK_STATE_DATA_OFST 0 735 #define FCDI_EVENT_LINK_STATE_DATA_LBN 0 736 #define FCDI_EVENT_LINK_STATE_DATA_WIDTH 32 737 #define FCDI_EVENT_PTP_STATE_OFST 0 738 #define FCDI_EVENT_PTP_UNDEFINED 0x0 /* enum */ 739 #define FCDI_EVENT_PTP_SETUP_FAILED 0x1 /* enum */ 740 #define FCDI_EVENT_PTP_OPERATIONAL 0x2 /* enum */ 741 #define FCDI_EVENT_PTP_STATE_LBN 0 742 #define FCDI_EVENT_PTP_STATE_WIDTH 32 743 #define FCDI_EVENT_DDR_ECC_STATUS_BANK_ID_LBN 36 744 #define FCDI_EVENT_DDR_ECC_STATUS_BANK_ID_WIDTH 8 745 #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_OFST 0 746 #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_LBN 0 747 #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_WIDTH 32 748 /* Index of MC port being referred to */ 749 #define FCDI_EVENT_PORT_CONFIG_SRC_LBN 36 750 #define FCDI_EVENT_PORT_CONFIG_SRC_WIDTH 8 751 /* FC Port index that matches the MC port index in SRC */ 752 #define FCDI_EVENT_PORT_CONFIG_DATA_OFST 0 753 #define FCDI_EVENT_PORT_CONFIG_DATA_LBN 0 754 #define FCDI_EVENT_PORT_CONFIG_DATA_WIDTH 32 755 756 /* FCDI_EXTENDED_EVENT_PPS structuredef: Extended FCDI event to send PPS events 757 * to the MC. Note that this structure | is overlayed over a normal FCDI event 758 * such that bits 32-63 containing | event code, level, source etc remain the 759 * same. In this case the data | field of the header is defined to be the 760 * number of timestamps 761 */ 762 #define FCDI_EXTENDED_EVENT_PPS_LENMIN 16 763 #define FCDI_EXTENDED_EVENT_PPS_LENMAX 248 764 #define FCDI_EXTENDED_EVENT_PPS_LEN(num) (8+8*(num)) 765 /* Number of timestamps following */ 766 #define FCDI_EXTENDED_EVENT_PPS_COUNT_OFST 0 767 #define FCDI_EXTENDED_EVENT_PPS_COUNT_LBN 0 768 #define FCDI_EXTENDED_EVENT_PPS_COUNT_WIDTH 32 769 /* Seconds field of a timestamp record */ 770 #define FCDI_EXTENDED_EVENT_PPS_SECONDS_OFST 8 771 #define FCDI_EXTENDED_EVENT_PPS_SECONDS_LBN 64 772 #define FCDI_EXTENDED_EVENT_PPS_SECONDS_WIDTH 32 773 /* Nanoseconds field of a timestamp record */ 774 #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_OFST 12 775 #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_LBN 96 776 #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_WIDTH 32 777 /* Timestamp records comprising the event */ 778 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_OFST 8 779 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LEN 8 780 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LO_OFST 8 781 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_HI_OFST 12 782 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MINNUM 1 783 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MAXNUM 30 784 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LBN 64 785 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_WIDTH 64 786 787 /* MUM_EVENT structuredef */ 788 #define MUM_EVENT_LEN 8 789 #define MUM_EVENT_CONT_LBN 32 790 #define MUM_EVENT_CONT_WIDTH 1 791 #define MUM_EVENT_LEVEL_LBN 33 792 #define MUM_EVENT_LEVEL_WIDTH 3 793 /* enum: Info. */ 794 #define MUM_EVENT_LEVEL_INFO 0x0 795 /* enum: Warning. */ 796 #define MUM_EVENT_LEVEL_WARN 0x1 797 /* enum: Error. */ 798 #define MUM_EVENT_LEVEL_ERR 0x2 799 /* enum: Fatal. */ 800 #define MUM_EVENT_LEVEL_FATAL 0x3 801 #define MUM_EVENT_DATA_OFST 0 802 #define MUM_EVENT_SENSOR_ID_LBN 0 803 #define MUM_EVENT_SENSOR_ID_WIDTH 8 804 /* Enum values, see field(s): */ 805 /* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */ 806 #define MUM_EVENT_SENSOR_STATE_LBN 8 807 #define MUM_EVENT_SENSOR_STATE_WIDTH 8 808 #define MUM_EVENT_PORT_PHY_READY_LBN 0 809 #define MUM_EVENT_PORT_PHY_READY_WIDTH 1 810 #define MUM_EVENT_PORT_PHY_LINK_UP_LBN 1 811 #define MUM_EVENT_PORT_PHY_LINK_UP_WIDTH 1 812 #define MUM_EVENT_PORT_PHY_TX_LOL_LBN 2 813 #define MUM_EVENT_PORT_PHY_TX_LOL_WIDTH 1 814 #define MUM_EVENT_PORT_PHY_RX_LOL_LBN 3 815 #define MUM_EVENT_PORT_PHY_RX_LOL_WIDTH 1 816 #define MUM_EVENT_PORT_PHY_TX_LOS_LBN 4 817 #define MUM_EVENT_PORT_PHY_TX_LOS_WIDTH 1 818 #define MUM_EVENT_PORT_PHY_RX_LOS_LBN 5 819 #define MUM_EVENT_PORT_PHY_RX_LOS_WIDTH 1 820 #define MUM_EVENT_PORT_PHY_TX_FAULT_LBN 6 821 #define MUM_EVENT_PORT_PHY_TX_FAULT_WIDTH 1 822 #define MUM_EVENT_DATA_LBN 0 823 #define MUM_EVENT_DATA_WIDTH 32 824 #define MUM_EVENT_SRC_LBN 36 825 #define MUM_EVENT_SRC_WIDTH 8 826 #define MUM_EVENT_EV_CODE_LBN 60 827 #define MUM_EVENT_EV_CODE_WIDTH 4 828 #define MUM_EVENT_CODE_LBN 44 829 #define MUM_EVENT_CODE_WIDTH 8 830 /* enum: The MUM was rebooted. */ 831 #define MUM_EVENT_CODE_REBOOT 0x1 832 /* enum: Bad assert. */ 833 #define MUM_EVENT_CODE_ASSERT 0x2 834 /* enum: Sensor failure. */ 835 #define MUM_EVENT_CODE_SENSOR 0x3 836 /* enum: Link fault has been asserted, or has cleared. */ 837 #define MUM_EVENT_CODE_QSFP_LASI_INTERRUPT 0x4 838 #define MUM_EVENT_SENSOR_DATA_OFST 0 839 #define MUM_EVENT_SENSOR_DATA_LBN 0 840 #define MUM_EVENT_SENSOR_DATA_WIDTH 32 841 #define MUM_EVENT_PORT_PHY_FLAGS_OFST 0 842 #define MUM_EVENT_PORT_PHY_FLAGS_LBN 0 843 #define MUM_EVENT_PORT_PHY_FLAGS_WIDTH 32 844 #define MUM_EVENT_PORT_PHY_COPPER_LEN_OFST 0 845 #define MUM_EVENT_PORT_PHY_COPPER_LEN_LBN 0 846 #define MUM_EVENT_PORT_PHY_COPPER_LEN_WIDTH 32 847 #define MUM_EVENT_PORT_PHY_CAPS_OFST 0 848 #define MUM_EVENT_PORT_PHY_CAPS_LBN 0 849 #define MUM_EVENT_PORT_PHY_CAPS_WIDTH 32 850 #define MUM_EVENT_PORT_PHY_TECH_OFST 0 851 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_UNKNOWN 0x0 /* enum */ 852 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_OPTICAL 0x1 /* enum */ 853 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_PASSIVE 0x2 /* enum */ 854 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_PASSIVE_EQUALIZED 0x3 /* enum */ 855 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_ACTIVE_LIMITING 0x4 /* enum */ 856 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_ACTIVE_LINEAR 0x5 /* enum */ 857 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_BASE_T 0x6 /* enum */ 858 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_LOOPBACK_PASSIVE 0x7 /* enum */ 859 #define MUM_EVENT_PORT_PHY_TECH_LBN 0 860 #define MUM_EVENT_PORT_PHY_TECH_WIDTH 32 861 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_LBN 36 862 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_WIDTH 4 863 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_FLAGS 0x0 /* enum */ 864 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_COPPER_LEN 0x1 /* enum */ 865 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_CAPS 0x2 /* enum */ 866 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_TECH 0x3 /* enum */ 867 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_MAX 0x4 /* enum */ 868 #define MUM_EVENT_PORT_PHY_SRC_PORT_NO_LBN 40 869 #define MUM_EVENT_PORT_PHY_SRC_PORT_NO_WIDTH 4 870 871 872 /***********************************/ 873 /* MC_CMD_READ32 874 * Read multiple 32byte words from MC memory. 875 */ 876 #define MC_CMD_READ32 0x1 877 #undef MC_CMD_0x1_PRIVILEGE_CTG 878 879 #define MC_CMD_0x1_PRIVILEGE_CTG SRIOV_CTG_ADMIN 880 881 /* MC_CMD_READ32_IN msgrequest */ 882 #define MC_CMD_READ32_IN_LEN 8 883 #define MC_CMD_READ32_IN_ADDR_OFST 0 884 #define MC_CMD_READ32_IN_NUMWORDS_OFST 4 885 886 /* MC_CMD_READ32_OUT msgresponse */ 887 #define MC_CMD_READ32_OUT_LENMIN 4 888 #define MC_CMD_READ32_OUT_LENMAX 252 889 #define MC_CMD_READ32_OUT_LEN(num) (0+4*(num)) 890 #define MC_CMD_READ32_OUT_BUFFER_OFST 0 891 #define MC_CMD_READ32_OUT_BUFFER_LEN 4 892 #define MC_CMD_READ32_OUT_BUFFER_MINNUM 1 893 #define MC_CMD_READ32_OUT_BUFFER_MAXNUM 63 894 895 896 /***********************************/ 897 /* MC_CMD_WRITE32 898 * Write multiple 32byte words to MC memory. 899 */ 900 #define MC_CMD_WRITE32 0x2 901 #undef MC_CMD_0x2_PRIVILEGE_CTG 902 903 #define MC_CMD_0x2_PRIVILEGE_CTG SRIOV_CTG_ADMIN 904 905 /* MC_CMD_WRITE32_IN msgrequest */ 906 #define MC_CMD_WRITE32_IN_LENMIN 8 907 #define MC_CMD_WRITE32_IN_LENMAX 252 908 #define MC_CMD_WRITE32_IN_LEN(num) (4+4*(num)) 909 #define MC_CMD_WRITE32_IN_ADDR_OFST 0 910 #define MC_CMD_WRITE32_IN_BUFFER_OFST 4 911 #define MC_CMD_WRITE32_IN_BUFFER_LEN 4 912 #define MC_CMD_WRITE32_IN_BUFFER_MINNUM 1 913 #define MC_CMD_WRITE32_IN_BUFFER_MAXNUM 62 914 915 /* MC_CMD_WRITE32_OUT msgresponse */ 916 #define MC_CMD_WRITE32_OUT_LEN 0 917 918 919 /***********************************/ 920 /* MC_CMD_COPYCODE 921 * Copy MC code between two locations and jump. 922 */ 923 #define MC_CMD_COPYCODE 0x3 924 #undef MC_CMD_0x3_PRIVILEGE_CTG 925 926 #define MC_CMD_0x3_PRIVILEGE_CTG SRIOV_CTG_ADMIN 927 928 /* MC_CMD_COPYCODE_IN msgrequest */ 929 #define MC_CMD_COPYCODE_IN_LEN 16 930 /* Source address 931 * 932 * The main image should be entered via a copy of a single word from and to a 933 * magic address, which controls various aspects of the boot. The magic address 934 * is a bitfield, with each bit as documented below. 935 */ 936 #define MC_CMD_COPYCODE_IN_SRC_ADDR_OFST 0 937 /* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT (see below) */ 938 #define MC_CMD_COPYCODE_HUNT_NO_MAGIC_ADDR 0x10000 939 /* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT and 940 * BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED (see below) 941 */ 942 #define MC_CMD_COPYCODE_HUNT_NO_DATAPATH_MAGIC_ADDR 0x1d0d0 943 /* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT, 944 * BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED and BOOT_MAGIC_IGNORE_CONFIG (see 945 * below) 946 */ 947 #define MC_CMD_COPYCODE_HUNT_IGNORE_CONFIG_MAGIC_ADDR 0x1badc 948 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_LBN 17 949 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_WIDTH 1 950 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_LBN 2 951 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_WIDTH 1 952 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_LBN 3 953 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_WIDTH 1 954 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_LBN 4 955 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_WIDTH 1 956 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_LBN 5 957 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_WIDTH 1 958 /* Destination address */ 959 #define MC_CMD_COPYCODE_IN_DEST_ADDR_OFST 4 960 #define MC_CMD_COPYCODE_IN_NUMWORDS_OFST 8 961 /* Address of where to jump after copy. */ 962 #define MC_CMD_COPYCODE_IN_JUMP_OFST 12 963 /* enum: Control should return to the caller rather than jumping */ 964 #define MC_CMD_COPYCODE_JUMP_NONE 0x1 965 966 /* MC_CMD_COPYCODE_OUT msgresponse */ 967 #define MC_CMD_COPYCODE_OUT_LEN 0 968 969 970 /***********************************/ 971 /* MC_CMD_SET_FUNC 972 * Select function for function-specific commands. 973 */ 974 #define MC_CMD_SET_FUNC 0x4 975 #undef MC_CMD_0x4_PRIVILEGE_CTG 976 977 #define MC_CMD_0x4_PRIVILEGE_CTG SRIOV_CTG_ADMIN 978 979 /* MC_CMD_SET_FUNC_IN msgrequest */ 980 #define MC_CMD_SET_FUNC_IN_LEN 4 981 /* Set function */ 982 #define MC_CMD_SET_FUNC_IN_FUNC_OFST 0 983 984 /* MC_CMD_SET_FUNC_OUT msgresponse */ 985 #define MC_CMD_SET_FUNC_OUT_LEN 0 986 987 988 /***********************************/ 989 /* MC_CMD_GET_BOOT_STATUS 990 * Get the instruction address from which the MC booted. 991 */ 992 #define MC_CMD_GET_BOOT_STATUS 0x5 993 #undef MC_CMD_0x5_PRIVILEGE_CTG 994 995 #define MC_CMD_0x5_PRIVILEGE_CTG SRIOV_CTG_ADMIN 996 997 /* MC_CMD_GET_BOOT_STATUS_IN msgrequest */ 998 #define MC_CMD_GET_BOOT_STATUS_IN_LEN 0 999 1000 /* MC_CMD_GET_BOOT_STATUS_OUT msgresponse */ 1001 #define MC_CMD_GET_BOOT_STATUS_OUT_LEN 8 1002 /* ?? */ 1003 #define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_OFST 0 1004 /* enum: indicates that the MC wasn't flash booted */ 1005 #define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_NULL 0xdeadbeef 1006 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_OFST 4 1007 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_LBN 0 1008 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_WIDTH 1 1009 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_LBN 1 1010 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_WIDTH 1 1011 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_LBN 2 1012 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_WIDTH 1 1013 1014 1015 /***********************************/ 1016 /* MC_CMD_GET_ASSERTS 1017 * Get (and optionally clear) the current assertion status. Only 1018 * OUT.GLOBAL_FLAGS is guaranteed to exist in the completion payload. The other 1019 * fields will only be present if OUT.GLOBAL_FLAGS != NO_FAILS 1020 */ 1021 #define MC_CMD_GET_ASSERTS 0x6 1022 #undef MC_CMD_0x6_PRIVILEGE_CTG 1023 1024 #define MC_CMD_0x6_PRIVILEGE_CTG SRIOV_CTG_ADMIN 1025 1026 /* MC_CMD_GET_ASSERTS_IN msgrequest */ 1027 #define MC_CMD_GET_ASSERTS_IN_LEN 4 1028 /* Set to clear assertion */ 1029 #define MC_CMD_GET_ASSERTS_IN_CLEAR_OFST 0 1030 1031 /* MC_CMD_GET_ASSERTS_OUT msgresponse */ 1032 #define MC_CMD_GET_ASSERTS_OUT_LEN 140 1033 /* Assertion status flag. */ 1034 #define MC_CMD_GET_ASSERTS_OUT_GLOBAL_FLAGS_OFST 0 1035 /* enum: No assertions have failed. */ 1036 #define MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1 1037 /* enum: A system-level assertion has failed. */ 1038 #define MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2 1039 /* enum: A thread-level assertion has failed. */ 1040 #define MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3 1041 /* enum: The system was reset by the watchdog. */ 1042 #define MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4 1043 /* enum: An illegal address trap stopped the system (huntington and later) */ 1044 #define MC_CMD_GET_ASSERTS_FLAGS_ADDR_TRAP 0x5 1045 /* Failing PC value */ 1046 #define MC_CMD_GET_ASSERTS_OUT_SAVED_PC_OFFS_OFST 4 1047 /* Saved GP regs */ 1048 #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_OFST 8 1049 #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_LEN 4 1050 #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_NUM 31 1051 /* enum: A magic value hinting that the value in this register at the time of 1052 * the failure has likely been lost. 1053 */ 1054 #define MC_CMD_GET_ASSERTS_REG_NO_DATA 0xda7a1057 1055 /* Failing thread address */ 1056 #define MC_CMD_GET_ASSERTS_OUT_THREAD_OFFS_OFST 132 1057 #define MC_CMD_GET_ASSERTS_OUT_RESERVED_OFST 136 1058 1059 1060 /***********************************/ 1061 /* MC_CMD_LOG_CTRL 1062 * Configure the output stream for log events such as link state changes, 1063 * sensor notifications and MCDI completions 1064 */ 1065 #define MC_CMD_LOG_CTRL 0x7 1066 #undef MC_CMD_0x7_PRIVILEGE_CTG 1067 1068 #define MC_CMD_0x7_PRIVILEGE_CTG SRIOV_CTG_GENERAL 1069 1070 /* MC_CMD_LOG_CTRL_IN msgrequest */ 1071 #define MC_CMD_LOG_CTRL_IN_LEN 8 1072 /* Log destination */ 1073 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_OFST 0 1074 /* enum: UART. */ 1075 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_UART 0x1 1076 /* enum: Event queue. */ 1077 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ 0x2 1078 /* Legacy argument. Must be zero. */ 1079 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ_OFST 4 1080 1081 /* MC_CMD_LOG_CTRL_OUT msgresponse */ 1082 #define MC_CMD_LOG_CTRL_OUT_LEN 0 1083 1084 1085 /***********************************/ 1086 /* MC_CMD_GET_VERSION 1087 * Get version information about the MC firmware. 1088 */ 1089 #define MC_CMD_GET_VERSION 0x8 1090 #undef MC_CMD_0x8_PRIVILEGE_CTG 1091 1092 #define MC_CMD_0x8_PRIVILEGE_CTG SRIOV_CTG_GENERAL 1093 1094 /* MC_CMD_GET_VERSION_IN msgrequest */ 1095 #define MC_CMD_GET_VERSION_IN_LEN 0 1096 1097 /* MC_CMD_GET_VERSION_EXT_IN msgrequest: Asks for the extended version */ 1098 #define MC_CMD_GET_VERSION_EXT_IN_LEN 4 1099 /* placeholder, set to 0 */ 1100 #define MC_CMD_GET_VERSION_EXT_IN_EXT_FLAGS_OFST 0 1101 1102 /* MC_CMD_GET_VERSION_V0_OUT msgresponse: deprecated version format */ 1103 #define MC_CMD_GET_VERSION_V0_OUT_LEN 4 1104 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 1105 /* enum: Reserved version number to indicate "any" version. */ 1106 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_ANY 0xffffffff 1107 /* enum: Bootrom version value for Siena. */ 1108 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_SIENA_BOOTROM 0xb0070000 1109 /* enum: Bootrom version value for Huntington. */ 1110 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_HUNT_BOOTROM 0xb0070001 1111 1112 /* MC_CMD_GET_VERSION_OUT msgresponse */ 1113 #define MC_CMD_GET_VERSION_OUT_LEN 32 1114 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */ 1115 /* Enum values, see field(s): */ 1116 /* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */ 1117 #define MC_CMD_GET_VERSION_OUT_PCOL_OFST 4 1118 /* 128bit mask of functions supported by the current firmware */ 1119 #define MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_OFST 8 1120 #define MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_LEN 16 1121 #define MC_CMD_GET_VERSION_OUT_VERSION_OFST 24 1122 #define MC_CMD_GET_VERSION_OUT_VERSION_LEN 8 1123 #define MC_CMD_GET_VERSION_OUT_VERSION_LO_OFST 24 1124 #define MC_CMD_GET_VERSION_OUT_VERSION_HI_OFST 28 1125 1126 /* MC_CMD_GET_VERSION_EXT_OUT msgresponse */ 1127 #define MC_CMD_GET_VERSION_EXT_OUT_LEN 48 1128 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */ 1129 /* Enum values, see field(s): */ 1130 /* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */ 1131 #define MC_CMD_GET_VERSION_EXT_OUT_PCOL_OFST 4 1132 /* 128bit mask of functions supported by the current firmware */ 1133 #define MC_CMD_GET_VERSION_EXT_OUT_SUPPORTED_FUNCS_OFST 8 1134 #define MC_CMD_GET_VERSION_EXT_OUT_SUPPORTED_FUNCS_LEN 16 1135 #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_OFST 24 1136 #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LEN 8 1137 #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LO_OFST 24 1138 #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_HI_OFST 28 1139 /* extra info */ 1140 #define MC_CMD_GET_VERSION_EXT_OUT_EXTRA_OFST 32 1141 #define MC_CMD_GET_VERSION_EXT_OUT_EXTRA_LEN 16 1142 1143 1144 /***********************************/ 1145 /* MC_CMD_FC 1146 * Perform an FC operation 1147 */ 1148 #define MC_CMD_FC 0x9 1149 1150 /* MC_CMD_FC_IN msgrequest */ 1151 #define MC_CMD_FC_IN_LEN 4 1152 #define MC_CMD_FC_IN_OP_HDR_OFST 0 1153 #define MC_CMD_FC_IN_OP_LBN 0 1154 #define MC_CMD_FC_IN_OP_WIDTH 8 1155 /* enum: NULL MCDI command to FC. */ 1156 #define MC_CMD_FC_OP_NULL 0x1 1157 /* enum: Unused opcode */ 1158 #define MC_CMD_FC_OP_UNUSED 0x2 1159 /* enum: MAC driver commands */ 1160 #define MC_CMD_FC_OP_MAC 0x3 1161 /* enum: Read FC memory */ 1162 #define MC_CMD_FC_OP_READ32 0x4 1163 /* enum: Write to FC memory */ 1164 #define MC_CMD_FC_OP_WRITE32 0x5 1165 /* enum: Read FC memory */ 1166 #define MC_CMD_FC_OP_TRC_READ 0x6 1167 /* enum: Write to FC memory */ 1168 #define MC_CMD_FC_OP_TRC_WRITE 0x7 1169 /* enum: FC firmware Version */ 1170 #define MC_CMD_FC_OP_GET_VERSION 0x8 1171 /* enum: Read FC memory */ 1172 #define MC_CMD_FC_OP_TRC_RX_READ 0x9 1173 /* enum: Write to FC memory */ 1174 #define MC_CMD_FC_OP_TRC_RX_WRITE 0xa 1175 /* enum: SFP parameters */ 1176 #define MC_CMD_FC_OP_SFP 0xb 1177 /* enum: DDR3 test */ 1178 #define MC_CMD_FC_OP_DDR_TEST 0xc 1179 /* enum: Get Crash context from FC */ 1180 #define MC_CMD_FC_OP_GET_ASSERT 0xd 1181 /* enum: Get FPGA Build registers */ 1182 #define MC_CMD_FC_OP_FPGA_BUILD 0xe 1183 /* enum: Read map support commands */ 1184 #define MC_CMD_FC_OP_READ_MAP 0xf 1185 /* enum: FC Capabilities */ 1186 #define MC_CMD_FC_OP_CAPABILITIES 0x10 1187 /* enum: FC Global flags */ 1188 #define MC_CMD_FC_OP_GLOBAL_FLAGS 0x11 1189 /* enum: FC IO using relative addressing modes */ 1190 #define MC_CMD_FC_OP_IO_REL 0x12 1191 /* enum: FPGA link information */ 1192 #define MC_CMD_FC_OP_UHLINK 0x13 1193 /* enum: Configure loopbacks and link on FPGA ports */ 1194 #define MC_CMD_FC_OP_SET_LINK 0x14 1195 /* enum: Licensing operations relating to AOE */ 1196 #define MC_CMD_FC_OP_LICENSE 0x15 1197 /* enum: Startup information to the FC */ 1198 #define MC_CMD_FC_OP_STARTUP 0x16 1199 /* enum: Configure a DMA read */ 1200 #define MC_CMD_FC_OP_DMA 0x17 1201 /* enum: Configure a timed read */ 1202 #define MC_CMD_FC_OP_TIMED_READ 0x18 1203 /* enum: Control UART logging */ 1204 #define MC_CMD_FC_OP_LOG 0x19 1205 /* enum: Get the value of a given clock_id */ 1206 #define MC_CMD_FC_OP_CLOCK 0x1a 1207 /* enum: DDR3/QDR3 parameters */ 1208 #define MC_CMD_FC_OP_DDR 0x1b 1209 /* enum: PTP and timestamp control */ 1210 #define MC_CMD_FC_OP_TIMESTAMP 0x1c 1211 /* enum: Commands for SPI Flash interface */ 1212 #define MC_CMD_FC_OP_SPI 0x1d 1213 /* enum: Commands for diagnostic components */ 1214 #define MC_CMD_FC_OP_DIAG 0x1e 1215 /* enum: External AOE port. */ 1216 #define MC_CMD_FC_IN_PORT_EXT_OFST 0x0 1217 /* enum: Internal AOE port. */ 1218 #define MC_CMD_FC_IN_PORT_INT_OFST 0x40 1219 1220 /* MC_CMD_FC_IN_NULL msgrequest */ 1221 #define MC_CMD_FC_IN_NULL_LEN 4 1222 #define MC_CMD_FC_IN_CMD_OFST 0 1223 1224 /* MC_CMD_FC_IN_PHY msgrequest */ 1225 #define MC_CMD_FC_IN_PHY_LEN 5 1226 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1227 /* FC PHY driver operation code */ 1228 #define MC_CMD_FC_IN_PHY_OP_OFST 4 1229 #define MC_CMD_FC_IN_PHY_OP_LEN 1 1230 /* enum: PHY init handler */ 1231 #define MC_CMD_FC_OP_PHY_OP_INIT 0x1 1232 /* enum: PHY reconfigure handler */ 1233 #define MC_CMD_FC_OP_PHY_OP_RECONFIGURE 0x2 1234 /* enum: PHY reboot handler */ 1235 #define MC_CMD_FC_OP_PHY_OP_REBOOT 0x3 1236 /* enum: PHY get_supported_cap handler */ 1237 #define MC_CMD_FC_OP_PHY_OP_GET_SUPPORTED_CAP 0x4 1238 /* enum: PHY get_config handler */ 1239 #define MC_CMD_FC_OP_PHY_OP_GET_CONFIG 0x5 1240 /* enum: PHY get_media_info handler */ 1241 #define MC_CMD_FC_OP_PHY_OP_GET_MEDIA_INFO 0x6 1242 /* enum: PHY set_led handler */ 1243 #define MC_CMD_FC_OP_PHY_OP_SET_LED 0x7 1244 /* enum: PHY lasi_interrupt handler */ 1245 #define MC_CMD_FC_OP_PHY_OP_LASI_INTERRUPT 0x8 1246 /* enum: PHY check_link handler */ 1247 #define MC_CMD_FC_OP_PHY_OP_CHECK_LINK 0x9 1248 /* enum: PHY fill_stats handler */ 1249 #define MC_CMD_FC_OP_PHY_OP_FILL_STATS 0xa 1250 /* enum: PHY bpx_link_state_changed handler */ 1251 #define MC_CMD_FC_OP_PHY_OP_BPX_LINK_STATE_CHANGED 0xb 1252 /* enum: PHY get_state handler */ 1253 #define MC_CMD_FC_OP_PHY_OP_GET_STATE 0xc 1254 /* enum: PHY start_bist handler */ 1255 #define MC_CMD_FC_OP_PHY_OP_START_BIST 0xd 1256 /* enum: PHY poll_bist handler */ 1257 #define MC_CMD_FC_OP_PHY_OP_POLL_BIST 0xe 1258 /* enum: PHY nvram_test handler */ 1259 #define MC_CMD_FC_OP_PHY_OP_NVRAM_TEST 0xf 1260 /* enum: PHY relinquish handler */ 1261 #define MC_CMD_FC_OP_PHY_OP_RELINQUISH_SPI 0x10 1262 /* enum: PHY read connection from FC - may be not required */ 1263 #define MC_CMD_FC_OP_PHY_OP_GET_CONNECTION 0x11 1264 /* enum: PHY read flags from FC - may be not required */ 1265 #define MC_CMD_FC_OP_PHY_OP_GET_FLAGS 0x12 1266 1267 /* MC_CMD_FC_IN_PHY_INIT msgrequest */ 1268 #define MC_CMD_FC_IN_PHY_INIT_LEN 4 1269 #define MC_CMD_FC_IN_PHY_CMD_OFST 0 1270 1271 /* MC_CMD_FC_IN_MAC msgrequest */ 1272 #define MC_CMD_FC_IN_MAC_LEN 8 1273 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1274 #define MC_CMD_FC_IN_MAC_HEADER_OFST 4 1275 #define MC_CMD_FC_IN_MAC_OP_LBN 0 1276 #define MC_CMD_FC_IN_MAC_OP_WIDTH 8 1277 /* enum: MAC reconfigure handler */ 1278 #define MC_CMD_FC_OP_MAC_OP_RECONFIGURE 0x1 1279 /* enum: MAC Set command - same as MC_CMD_SET_MAC */ 1280 #define MC_CMD_FC_OP_MAC_OP_SET_LINK 0x2 1281 /* enum: MAC statistics */ 1282 #define MC_CMD_FC_OP_MAC_OP_GET_STATS 0x3 1283 /* enum: MAC RX statistics */ 1284 #define MC_CMD_FC_OP_MAC_OP_GET_RX_STATS 0x6 1285 /* enum: MAC TX statistics */ 1286 #define MC_CMD_FC_OP_MAC_OP_GET_TX_STATS 0x7 1287 /* enum: MAC Read status */ 1288 #define MC_CMD_FC_OP_MAC_OP_READ_STATUS 0x8 1289 #define MC_CMD_FC_IN_MAC_PORT_TYPE_LBN 8 1290 #define MC_CMD_FC_IN_MAC_PORT_TYPE_WIDTH 8 1291 /* enum: External FPGA port. */ 1292 #define MC_CMD_FC_PORT_EXT 0x0 1293 /* enum: Internal Siena-facing FPGA ports. */ 1294 #define MC_CMD_FC_PORT_INT 0x1 1295 #define MC_CMD_FC_IN_MAC_PORT_IDX_LBN 16 1296 #define MC_CMD_FC_IN_MAC_PORT_IDX_WIDTH 8 1297 #define MC_CMD_FC_IN_MAC_CMD_FORMAT_LBN 24 1298 #define MC_CMD_FC_IN_MAC_CMD_FORMAT_WIDTH 8 1299 /* enum: Default FC command format; the fields PORT_TYPE and PORT_IDX are 1300 * irrelevant. Port number is derived from pci_fn; passed in FC header. 1301 */ 1302 #define MC_CMD_FC_OP_MAC_CMD_FORMAT_DEFAULT 0x0 1303 /* enum: Override default port number. Port number determined by fields 1304 * PORT_TYPE and PORT_IDX. 1305 */ 1306 #define MC_CMD_FC_OP_MAC_CMD_FORMAT_PORT_OVERRIDE 0x1 1307 1308 /* MC_CMD_FC_IN_MAC_RECONFIGURE msgrequest */ 1309 #define MC_CMD_FC_IN_MAC_RECONFIGURE_LEN 8 1310 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1311 /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ 1312 1313 /* MC_CMD_FC_IN_MAC_SET_LINK msgrequest */ 1314 #define MC_CMD_FC_IN_MAC_SET_LINK_LEN 32 1315 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1316 /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ 1317 /* MTU size */ 1318 #define MC_CMD_FC_IN_MAC_SET_LINK_MTU_OFST 8 1319 /* Drain Tx FIFO */ 1320 #define MC_CMD_FC_IN_MAC_SET_LINK_DRAIN_OFST 12 1321 #define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_OFST 16 1322 #define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_LEN 8 1323 #define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_LO_OFST 16 1324 #define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_HI_OFST 20 1325 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_OFST 24 1326 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_UNICAST_LBN 0 1327 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_UNICAST_WIDTH 1 1328 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_BRDCAST_LBN 1 1329 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_BRDCAST_WIDTH 1 1330 #define MC_CMD_FC_IN_MAC_SET_LINK_FCNTL_OFST 28 1331 1332 /* MC_CMD_FC_IN_MAC_READ_STATUS msgrequest */ 1333 #define MC_CMD_FC_IN_MAC_READ_STATUS_LEN 8 1334 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1335 /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ 1336 1337 /* MC_CMD_FC_IN_MAC_GET_RX_STATS msgrequest */ 1338 #define MC_CMD_FC_IN_MAC_GET_RX_STATS_LEN 8 1339 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1340 /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ 1341 1342 /* MC_CMD_FC_IN_MAC_GET_TX_STATS msgrequest */ 1343 #define MC_CMD_FC_IN_MAC_GET_TX_STATS_LEN 8 1344 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1345 /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ 1346 1347 /* MC_CMD_FC_IN_MAC_GET_STATS msgrequest */ 1348 #define MC_CMD_FC_IN_MAC_GET_STATS_LEN 20 1349 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1350 /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ 1351 /* MC Statistics index */ 1352 #define MC_CMD_FC_IN_MAC_GET_STATS_STATS_INDEX_OFST 8 1353 #define MC_CMD_FC_IN_MAC_GET_STATS_FLAGS_OFST 12 1354 #define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_ALL_LBN 0 1355 #define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_ALL_WIDTH 1 1356 #define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_LBN 1 1357 #define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_WIDTH 1 1358 #define MC_CMD_FC_IN_MAC_GET_STATS_UPDATE_LBN 2 1359 #define MC_CMD_FC_IN_MAC_GET_STATS_UPDATE_WIDTH 1 1360 /* Number of statistics to read */ 1361 #define MC_CMD_FC_IN_MAC_GET_STATS_NUM_OFST 16 1362 #define MC_CMD_FC_MAC_NSTATS_PER_BLOCK 0x1e /* enum */ 1363 #define MC_CMD_FC_MAC_NBYTES_PER_STAT 0x8 /* enum */ 1364 1365 /* MC_CMD_FC_IN_READ32 msgrequest */ 1366 #define MC_CMD_FC_IN_READ32_LEN 16 1367 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1368 #define MC_CMD_FC_IN_READ32_ADDR_HI_OFST 4 1369 #define MC_CMD_FC_IN_READ32_ADDR_LO_OFST 8 1370 #define MC_CMD_FC_IN_READ32_NUMWORDS_OFST 12 1371 1372 /* MC_CMD_FC_IN_WRITE32 msgrequest */ 1373 #define MC_CMD_FC_IN_WRITE32_LENMIN 16 1374 #define MC_CMD_FC_IN_WRITE32_LENMAX 252 1375 #define MC_CMD_FC_IN_WRITE32_LEN(num) (12+4*(num)) 1376 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1377 #define MC_CMD_FC_IN_WRITE32_ADDR_HI_OFST 4 1378 #define MC_CMD_FC_IN_WRITE32_ADDR_LO_OFST 8 1379 #define MC_CMD_FC_IN_WRITE32_BUFFER_OFST 12 1380 #define MC_CMD_FC_IN_WRITE32_BUFFER_LEN 4 1381 #define MC_CMD_FC_IN_WRITE32_BUFFER_MINNUM 1 1382 #define MC_CMD_FC_IN_WRITE32_BUFFER_MAXNUM 60 1383 1384 /* MC_CMD_FC_IN_TRC_READ msgrequest */ 1385 #define MC_CMD_FC_IN_TRC_READ_LEN 12 1386 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1387 #define MC_CMD_FC_IN_TRC_READ_TRC_OFST 4 1388 #define MC_CMD_FC_IN_TRC_READ_CHANNEL_OFST 8 1389 1390 /* MC_CMD_FC_IN_TRC_WRITE msgrequest */ 1391 #define MC_CMD_FC_IN_TRC_WRITE_LEN 28 1392 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1393 #define MC_CMD_FC_IN_TRC_WRITE_TRC_OFST 4 1394 #define MC_CMD_FC_IN_TRC_WRITE_CHANNEL_OFST 8 1395 #define MC_CMD_FC_IN_TRC_WRITE_DATA_OFST 12 1396 #define MC_CMD_FC_IN_TRC_WRITE_DATA_LEN 4 1397 #define MC_CMD_FC_IN_TRC_WRITE_DATA_NUM 4 1398 1399 /* MC_CMD_FC_IN_GET_VERSION msgrequest */ 1400 #define MC_CMD_FC_IN_GET_VERSION_LEN 4 1401 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1402 1403 /* MC_CMD_FC_IN_TRC_RX_READ msgrequest */ 1404 #define MC_CMD_FC_IN_TRC_RX_READ_LEN 12 1405 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1406 #define MC_CMD_FC_IN_TRC_RX_READ_TRC_OFST 4 1407 #define MC_CMD_FC_IN_TRC_RX_READ_CHANNEL_OFST 8 1408 1409 /* MC_CMD_FC_IN_TRC_RX_WRITE msgrequest */ 1410 #define MC_CMD_FC_IN_TRC_RX_WRITE_LEN 20 1411 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1412 #define MC_CMD_FC_IN_TRC_RX_WRITE_TRC_OFST 4 1413 #define MC_CMD_FC_IN_TRC_RX_WRITE_CHANNEL_OFST 8 1414 #define MC_CMD_FC_IN_TRC_RX_WRITE_DATA_OFST 12 1415 #define MC_CMD_FC_IN_TRC_RX_WRITE_DATA_LEN 4 1416 #define MC_CMD_FC_IN_TRC_RX_WRITE_DATA_NUM 2 1417 1418 /* MC_CMD_FC_IN_SFP msgrequest */ 1419 #define MC_CMD_FC_IN_SFP_LEN 28 1420 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1421 /* Link speed is 100, 1000, 10000, 40000 */ 1422 #define MC_CMD_FC_IN_SFP_SPEED_OFST 4 1423 /* Length of copper cable - zero when not relevant (e.g. if cable is fibre) */ 1424 #define MC_CMD_FC_IN_SFP_COPPER_LEN_OFST 8 1425 /* Not relevant for cards with QSFP modules. For older cards, true if module is 1426 * a dual speed SFP+ module. 1427 */ 1428 #define MC_CMD_FC_IN_SFP_DUAL_SPEED_OFST 12 1429 /* True if an SFP Module is present (other fields valid when true) */ 1430 #define MC_CMD_FC_IN_SFP_PRESENT_OFST 16 1431 /* The type of the SFP+ Module. For later cards with QSFP modules, this field 1432 * is unused and the type is communicated by other means. 1433 */ 1434 #define MC_CMD_FC_IN_SFP_TYPE_OFST 20 1435 /* Capabilities corresponding to 1 bits. */ 1436 #define MC_CMD_FC_IN_SFP_CAPS_OFST 24 1437 1438 /* MC_CMD_FC_IN_DDR_TEST msgrequest */ 1439 #define MC_CMD_FC_IN_DDR_TEST_LEN 8 1440 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1441 #define MC_CMD_FC_IN_DDR_TEST_HEADER_OFST 4 1442 #define MC_CMD_FC_IN_DDR_TEST_OP_LBN 0 1443 #define MC_CMD_FC_IN_DDR_TEST_OP_WIDTH 8 1444 /* enum: DRAM Test Start */ 1445 #define MC_CMD_FC_OP_DDR_TEST_START 0x1 1446 /* enum: DRAM Test Poll */ 1447 #define MC_CMD_FC_OP_DDR_TEST_POLL 0x2 1448 1449 /* MC_CMD_FC_IN_DDR_TEST_START msgrequest */ 1450 #define MC_CMD_FC_IN_DDR_TEST_START_LEN 12 1451 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1452 /* MC_CMD_FC_IN_DDR_TEST_HEADER_OFST 4 */ 1453 #define MC_CMD_FC_IN_DDR_TEST_START_MASK_OFST 8 1454 #define MC_CMD_FC_IN_DDR_TEST_START_T0_LBN 0 1455 #define MC_CMD_FC_IN_DDR_TEST_START_T0_WIDTH 1 1456 #define MC_CMD_FC_IN_DDR_TEST_START_T1_LBN 1 1457 #define MC_CMD_FC_IN_DDR_TEST_START_T1_WIDTH 1 1458 #define MC_CMD_FC_IN_DDR_TEST_START_B0_LBN 2 1459 #define MC_CMD_FC_IN_DDR_TEST_START_B0_WIDTH 1 1460 #define MC_CMD_FC_IN_DDR_TEST_START_B1_LBN 3 1461 #define MC_CMD_FC_IN_DDR_TEST_START_B1_WIDTH 1 1462 1463 /* MC_CMD_FC_IN_DDR_TEST_POLL msgrequest */ 1464 #define MC_CMD_FC_IN_DDR_TEST_POLL_LEN 12 1465 #define MC_CMD_FC_IN_DDR_TEST_CMD_OFST 0 1466 /* MC_CMD_FC_IN_DDR_TEST_HEADER_OFST 4 */ 1467 /* Clear previous test result and prepare for restarting DDR test */ 1468 #define MC_CMD_FC_IN_DDR_TEST_POLL_CLEAR_RESULT_FOR_DDR_TEST_OFST 8 1469 1470 /* MC_CMD_FC_IN_GET_ASSERT msgrequest */ 1471 #define MC_CMD_FC_IN_GET_ASSERT_LEN 4 1472 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1473 1474 /* MC_CMD_FC_IN_FPGA_BUILD msgrequest */ 1475 #define MC_CMD_FC_IN_FPGA_BUILD_LEN 8 1476 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1477 /* FPGA build info operation code */ 1478 #define MC_CMD_FC_IN_FPGA_BUILD_OP_OFST 4 1479 /* enum: Get the build registers */ 1480 #define MC_CMD_FC_IN_FPGA_BUILD_BUILD 0x1 1481 /* enum: Get the services registers */ 1482 #define MC_CMD_FC_IN_FPGA_BUILD_SERVICES 0x2 1483 /* enum: Get the BSP version */ 1484 #define MC_CMD_FC_IN_FPGA_BUILD_BSP_VERSION 0x3 1485 /* enum: Get build register for V2 (SFA974X) */ 1486 #define MC_CMD_FC_IN_FPGA_BUILD_BUILD_V2 0x4 1487 /* enum: GEt the services register for V2 (SFA974X) */ 1488 #define MC_CMD_FC_IN_FPGA_BUILD_SERVICES_V2 0x5 1489 1490 /* MC_CMD_FC_IN_READ_MAP msgrequest */ 1491 #define MC_CMD_FC_IN_READ_MAP_LEN 8 1492 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1493 #define MC_CMD_FC_IN_READ_MAP_HEADER_OFST 4 1494 #define MC_CMD_FC_IN_READ_MAP_OP_LBN 0 1495 #define MC_CMD_FC_IN_READ_MAP_OP_WIDTH 8 1496 /* enum: Get the number of map regions */ 1497 #define MC_CMD_FC_OP_READ_MAP_COUNT 0x1 1498 /* enum: Get the specified map */ 1499 #define MC_CMD_FC_OP_READ_MAP_INDEX 0x2 1500 1501 /* MC_CMD_FC_IN_READ_MAP_COUNT msgrequest */ 1502 #define MC_CMD_FC_IN_READ_MAP_COUNT_LEN 8 1503 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1504 /* MC_CMD_FC_IN_READ_MAP_HEADER_OFST 4 */ 1505 1506 /* MC_CMD_FC_IN_READ_MAP_INDEX msgrequest */ 1507 #define MC_CMD_FC_IN_READ_MAP_INDEX_LEN 12 1508 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1509 /* MC_CMD_FC_IN_READ_MAP_HEADER_OFST 4 */ 1510 #define MC_CMD_FC_IN_MAP_INDEX_OFST 8 1511 1512 /* MC_CMD_FC_IN_CAPABILITIES msgrequest */ 1513 #define MC_CMD_FC_IN_CAPABILITIES_LEN 4 1514 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1515 1516 /* MC_CMD_FC_IN_GLOBAL_FLAGS msgrequest */ 1517 #define MC_CMD_FC_IN_GLOBAL_FLAGS_LEN 8 1518 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1519 #define MC_CMD_FC_IN_GLOBAL_FLAGS_FLAGS_OFST 4 1520 #define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_CABLE_PLUGGED_IN_LBN 0 1521 #define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_CABLE_PLUGGED_IN_WIDTH 1 1522 #define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_LINK_MONITORING_LBN 1 1523 #define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_LINK_MONITORING_WIDTH 1 1524 #define MC_CMD_FC_IN_GLOBAL_FLAGS_DFE_ENABLE_LBN 2 1525 #define MC_CMD_FC_IN_GLOBAL_FLAGS_DFE_ENABLE_WIDTH 1 1526 #define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_EYE_ENABLE_LBN 3 1527 #define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_EYE_ENABLE_WIDTH 1 1528 #define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_TUNING_ENABLE_LBN 4 1529 #define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_TUNING_ENABLE_WIDTH 1 1530 #define MC_CMD_FC_IN_GLOBAL_FLAGS_OFFCAL_ENABLE_LBN 5 1531 #define MC_CMD_FC_IN_GLOBAL_FLAGS_OFFCAL_ENABLE_WIDTH 1 1532 1533 /* MC_CMD_FC_IN_IO_REL msgrequest */ 1534 #define MC_CMD_FC_IN_IO_REL_LEN 8 1535 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1536 #define MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 1537 #define MC_CMD_FC_IN_IO_REL_OP_LBN 0 1538 #define MC_CMD_FC_IN_IO_REL_OP_WIDTH 8 1539 /* enum: Get the base address that the FC applies to relative commands */ 1540 #define MC_CMD_FC_IN_IO_REL_GET_ADDR 0x1 1541 /* enum: Read data */ 1542 #define MC_CMD_FC_IN_IO_REL_READ32 0x2 1543 /* enum: Write data */ 1544 #define MC_CMD_FC_IN_IO_REL_WRITE32 0x3 1545 #define MC_CMD_FC_IN_IO_REL_COMP_TYPE_LBN 8 1546 #define MC_CMD_FC_IN_IO_REL_COMP_TYPE_WIDTH 8 1547 /* enum: Application address space */ 1548 #define MC_CMD_FC_COMP_TYPE_APP_ADDR_SPACE 0x1 1549 /* enum: Flash address space */ 1550 #define MC_CMD_FC_COMP_TYPE_FLASH 0x2 1551 1552 /* MC_CMD_FC_IN_IO_REL_GET_ADDR msgrequest */ 1553 #define MC_CMD_FC_IN_IO_REL_GET_ADDR_LEN 8 1554 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1555 /* MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 */ 1556 1557 /* MC_CMD_FC_IN_IO_REL_READ32 msgrequest */ 1558 #define MC_CMD_FC_IN_IO_REL_READ32_LEN 20 1559 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1560 /* MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 */ 1561 #define MC_CMD_FC_IN_IO_REL_READ32_ADDR_HI_OFST 8 1562 #define MC_CMD_FC_IN_IO_REL_READ32_ADDR_LO_OFST 12 1563 #define MC_CMD_FC_IN_IO_REL_READ32_NUMWORDS_OFST 16 1564 1565 /* MC_CMD_FC_IN_IO_REL_WRITE32 msgrequest */ 1566 #define MC_CMD_FC_IN_IO_REL_WRITE32_LENMIN 20 1567 #define MC_CMD_FC_IN_IO_REL_WRITE32_LENMAX 252 1568 #define MC_CMD_FC_IN_IO_REL_WRITE32_LEN(num) (16+4*(num)) 1569 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1570 /* MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 */ 1571 #define MC_CMD_FC_IN_IO_REL_WRITE32_ADDR_HI_OFST 8 1572 #define MC_CMD_FC_IN_IO_REL_WRITE32_ADDR_LO_OFST 12 1573 #define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_OFST 16 1574 #define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_LEN 4 1575 #define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_MINNUM 1 1576 #define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_MAXNUM 59 1577 1578 /* MC_CMD_FC_IN_UHLINK msgrequest */ 1579 #define MC_CMD_FC_IN_UHLINK_LEN 8 1580 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1581 #define MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 1582 #define MC_CMD_FC_IN_UHLINK_OP_LBN 0 1583 #define MC_CMD_FC_IN_UHLINK_OP_WIDTH 8 1584 /* enum: Get PHY configuration info */ 1585 #define MC_CMD_FC_OP_UHLINK_PHY 0x1 1586 /* enum: Get MAC configuration info */ 1587 #define MC_CMD_FC_OP_UHLINK_MAC 0x2 1588 /* enum: Get Rx eye table */ 1589 #define MC_CMD_FC_OP_UHLINK_RX_EYE 0x3 1590 /* enum: Get Rx eye plot */ 1591 #define MC_CMD_FC_OP_UHLINK_DUMP_RX_EYE_PLOT 0x4 1592 /* enum: Get Rx eye plot */ 1593 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT 0x5 1594 /* enum: Retune Rx settings */ 1595 #define MC_CMD_FC_OP_UHLINK_RX_TUNE 0x6 1596 /* enum: Set loopback mode on fpga port */ 1597 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET 0x7 1598 /* enum: Get loopback mode config state on fpga port */ 1599 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_GET 0x8 1600 #define MC_CMD_FC_IN_UHLINK_PORT_TYPE_LBN 8 1601 #define MC_CMD_FC_IN_UHLINK_PORT_TYPE_WIDTH 8 1602 #define MC_CMD_FC_IN_UHLINK_PORT_IDX_LBN 16 1603 #define MC_CMD_FC_IN_UHLINK_PORT_IDX_WIDTH 8 1604 #define MC_CMD_FC_IN_UHLINK_CMD_FORMAT_LBN 24 1605 #define MC_CMD_FC_IN_UHLINK_CMD_FORMAT_WIDTH 8 1606 /* enum: Default FC command format; the fields PORT_TYPE and PORT_IDX are 1607 * irrelevant. Port number is derived from pci_fn; passed in FC header. 1608 */ 1609 #define MC_CMD_FC_OP_UHLINK_CMD_FORMAT_DEFAULT 0x0 1610 /* enum: Override default port number. Port number determined by fields 1611 * PORT_TYPE and PORT_IDX. 1612 */ 1613 #define MC_CMD_FC_OP_UHLINK_CMD_FORMAT_PORT_OVERRIDE 0x1 1614 1615 /* MC_CMD_FC_OP_UHLINK_PHY msgrequest */ 1616 #define MC_CMD_FC_OP_UHLINK_PHY_LEN 8 1617 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1618 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 1619 1620 /* MC_CMD_FC_OP_UHLINK_MAC msgrequest */ 1621 #define MC_CMD_FC_OP_UHLINK_MAC_LEN 8 1622 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1623 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 1624 1625 /* MC_CMD_FC_OP_UHLINK_RX_EYE msgrequest */ 1626 #define MC_CMD_FC_OP_UHLINK_RX_EYE_LEN 12 1627 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1628 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 1629 #define MC_CMD_FC_OP_UHLINK_RX_EYE_INDEX_OFST 8 1630 #define MC_CMD_FC_UHLINK_RX_EYE_PER_BLOCK 0x30 /* enum */ 1631 1632 /* MC_CMD_FC_OP_UHLINK_DUMP_RX_EYE_PLOT msgrequest */ 1633 #define MC_CMD_FC_OP_UHLINK_DUMP_RX_EYE_PLOT_LEN 8 1634 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1635 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 1636 1637 /* MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT msgrequest */ 1638 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_LEN 20 1639 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1640 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 1641 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_DC_GAIN_OFST 8 1642 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_EQ_CONTROL_OFST 12 1643 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_INDEX_OFST 16 1644 #define MC_CMD_FC_UHLINK_RX_EYE_PLOT_ROWS_PER_BLOCK 0x1e /* enum */ 1645 1646 /* MC_CMD_FC_OP_UHLINK_RX_TUNE msgrequest */ 1647 #define MC_CMD_FC_OP_UHLINK_RX_TUNE_LEN 8 1648 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1649 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 1650 1651 /* MC_CMD_FC_OP_UHLINK_LOOPBACK_SET msgrequest */ 1652 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET_LEN 16 1653 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1654 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 1655 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET_TYPE_OFST 8 1656 #define MC_CMD_FC_UHLINK_LOOPBACK_TYPE_PCS_SERIAL 0x0 /* enum */ 1657 #define MC_CMD_FC_UHLINK_LOOPBACK_TYPE_PMA_PRE_CDR 0x1 /* enum */ 1658 #define MC_CMD_FC_UHLINK_LOOPBACK_TYPE_PMA_POST_CDR 0x2 /* enum */ 1659 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET_STATE_OFST 12 1660 #define MC_CMD_FC_UHLINK_LOOPBACK_STATE_OFF 0x0 /* enum */ 1661 #define MC_CMD_FC_UHLINK_LOOPBACK_STATE_ON 0x1 /* enum */ 1662 1663 /* MC_CMD_FC_OP_UHLINK_LOOPBACK_GET msgrequest */ 1664 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_GET_LEN 12 1665 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1666 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 1667 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_GET_TYPE_OFST 8 1668 1669 /* MC_CMD_FC_IN_SET_LINK msgrequest */ 1670 #define MC_CMD_FC_IN_SET_LINK_LEN 16 1671 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1672 /* See MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */ 1673 #define MC_CMD_FC_IN_SET_LINK_MODE_OFST 4 1674 #define MC_CMD_FC_IN_SET_LINK_SPEED_OFST 8 1675 #define MC_CMD_FC_IN_SET_LINK_FLAGS_OFST 12 1676 #define MC_CMD_FC_IN_SET_LINK_LOWPOWER_LBN 0 1677 #define MC_CMD_FC_IN_SET_LINK_LOWPOWER_WIDTH 1 1678 #define MC_CMD_FC_IN_SET_LINK_POWEROFF_LBN 1 1679 #define MC_CMD_FC_IN_SET_LINK_POWEROFF_WIDTH 1 1680 #define MC_CMD_FC_IN_SET_LINK_TXDIS_LBN 2 1681 #define MC_CMD_FC_IN_SET_LINK_TXDIS_WIDTH 1 1682 1683 /* MC_CMD_FC_IN_LICENSE msgrequest */ 1684 #define MC_CMD_FC_IN_LICENSE_LEN 8 1685 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1686 #define MC_CMD_FC_IN_LICENSE_OP_OFST 4 1687 #define MC_CMD_FC_IN_LICENSE_UPDATE_LICENSE 0x0 /* enum */ 1688 #define MC_CMD_FC_IN_LICENSE_GET_KEY_STATS 0x1 /* enum */ 1689 1690 /* MC_CMD_FC_IN_STARTUP msgrequest */ 1691 #define MC_CMD_FC_IN_STARTUP_LEN 40 1692 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1693 #define MC_CMD_FC_IN_STARTUP_BASE_OFST 4 1694 #define MC_CMD_FC_IN_STARTUP_LENGTH_OFST 8 1695 /* Length of identifier */ 1696 #define MC_CMD_FC_IN_STARTUP_IDLENGTH_OFST 12 1697 /* Identifier for AOE FPGA */ 1698 #define MC_CMD_FC_IN_STARTUP_ID_OFST 16 1699 #define MC_CMD_FC_IN_STARTUP_ID_LEN 1 1700 #define MC_CMD_FC_IN_STARTUP_ID_NUM 24 1701 1702 /* MC_CMD_FC_IN_DMA msgrequest */ 1703 #define MC_CMD_FC_IN_DMA_LEN 8 1704 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1705 #define MC_CMD_FC_IN_DMA_OP_OFST 4 1706 #define MC_CMD_FC_IN_DMA_STOP 0x0 /* enum */ 1707 #define MC_CMD_FC_IN_DMA_READ 0x1 /* enum */ 1708 1709 /* MC_CMD_FC_IN_DMA_STOP msgrequest */ 1710 #define MC_CMD_FC_IN_DMA_STOP_LEN 12 1711 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1712 /* MC_CMD_FC_IN_DMA_OP_OFST 4 */ 1713 /* FC supplied handle */ 1714 #define MC_CMD_FC_IN_DMA_STOP_FC_HANDLE_OFST 8 1715 1716 /* MC_CMD_FC_IN_DMA_READ msgrequest */ 1717 #define MC_CMD_FC_IN_DMA_READ_LEN 16 1718 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1719 /* MC_CMD_FC_IN_DMA_OP_OFST 4 */ 1720 #define MC_CMD_FC_IN_DMA_READ_OFFSET_OFST 8 1721 #define MC_CMD_FC_IN_DMA_READ_LENGTH_OFST 12 1722 1723 /* MC_CMD_FC_IN_TIMED_READ msgrequest */ 1724 #define MC_CMD_FC_IN_TIMED_READ_LEN 8 1725 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1726 #define MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 1727 #define MC_CMD_FC_IN_TIMED_READ_SET 0x0 /* enum */ 1728 #define MC_CMD_FC_IN_TIMED_READ_GET 0x1 /* enum */ 1729 #define MC_CMD_FC_IN_TIMED_READ_CLEAR 0x2 /* enum */ 1730 1731 /* MC_CMD_FC_IN_TIMED_READ_SET msgrequest */ 1732 #define MC_CMD_FC_IN_TIMED_READ_SET_LEN 52 1733 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1734 /* MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 */ 1735 /* Host supplied handle (unique) */ 1736 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_HANDLE_OFST 8 1737 /* Address into which to transfer data in host */ 1738 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_OFST 12 1739 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_LEN 8 1740 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_LO_OFST 12 1741 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_HI_OFST 16 1742 /* AOE address from which to transfer data */ 1743 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_OFST 20 1744 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_LEN 8 1745 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_LO_OFST 20 1746 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_HI_OFST 24 1747 /* Length of AOE transfer (total) */ 1748 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_LENGTH_OFST 28 1749 /* Length of host transfer (total) */ 1750 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_LENGTH_OFST 32 1751 /* Offset back from aoe_address to apply operation to */ 1752 #define MC_CMD_FC_IN_TIMED_READ_SET_OFFSET_OFST 36 1753 /* Data to apply at offset */ 1754 #define MC_CMD_FC_IN_TIMED_READ_SET_DATA_OFST 40 1755 #define MC_CMD_FC_IN_TIMED_READ_SET_FLAGS_OFST 44 1756 #define MC_CMD_FC_IN_TIMED_READ_SET_INDIRECT_LBN 0 1757 #define MC_CMD_FC_IN_TIMED_READ_SET_INDIRECT_WIDTH 1 1758 #define MC_CMD_FC_IN_TIMED_READ_SET_DOUBLE_LBN 1 1759 #define MC_CMD_FC_IN_TIMED_READ_SET_DOUBLE_WIDTH 1 1760 #define MC_CMD_FC_IN_TIMED_READ_SET_EVENT_LBN 2 1761 #define MC_CMD_FC_IN_TIMED_READ_SET_EVENT_WIDTH 1 1762 #define MC_CMD_FC_IN_TIMED_READ_SET_PREREAD_LBN 3 1763 #define MC_CMD_FC_IN_TIMED_READ_SET_PREREAD_WIDTH 2 1764 #define MC_CMD_FC_IN_TIMED_READ_SET_NONE 0x0 /* enum */ 1765 #define MC_CMD_FC_IN_TIMED_READ_SET_READ 0x1 /* enum */ 1766 #define MC_CMD_FC_IN_TIMED_READ_SET_WRITE 0x2 /* enum */ 1767 #define MC_CMD_FC_IN_TIMED_READ_SET_READWRITE 0x3 /* enum */ 1768 /* Period at which reads are performed (100ms units) */ 1769 #define MC_CMD_FC_IN_TIMED_READ_SET_PERIOD_OFST 48 1770 1771 /* MC_CMD_FC_IN_TIMED_READ_GET msgrequest */ 1772 #define MC_CMD_FC_IN_TIMED_READ_GET_LEN 12 1773 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1774 /* MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 */ 1775 /* FC supplied handle */ 1776 #define MC_CMD_FC_IN_TIMED_READ_GET_FC_HANDLE_OFST 8 1777 1778 /* MC_CMD_FC_IN_TIMED_READ_CLEAR msgrequest */ 1779 #define MC_CMD_FC_IN_TIMED_READ_CLEAR_LEN 12 1780 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1781 /* MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 */ 1782 /* FC supplied handle */ 1783 #define MC_CMD_FC_IN_TIMED_READ_CLEAR_FC_HANDLE_OFST 8 1784 1785 /* MC_CMD_FC_IN_LOG msgrequest */ 1786 #define MC_CMD_FC_IN_LOG_LEN 8 1787 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1788 #define MC_CMD_FC_IN_LOG_OP_OFST 4 1789 #define MC_CMD_FC_IN_LOG_ADDR_RANGE 0x0 /* enum */ 1790 #define MC_CMD_FC_IN_LOG_JTAG_UART 0x1 /* enum */ 1791 1792 /* MC_CMD_FC_IN_LOG_ADDR_RANGE msgrequest */ 1793 #define MC_CMD_FC_IN_LOG_ADDR_RANGE_LEN 20 1794 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1795 /* MC_CMD_FC_IN_LOG_OP_OFST 4 */ 1796 /* Partition offset into flash */ 1797 #define MC_CMD_FC_IN_LOG_ADDR_RANGE_OFFSET_OFST 8 1798 /* Partition length */ 1799 #define MC_CMD_FC_IN_LOG_ADDR_RANGE_LENGTH_OFST 12 1800 /* Partition erase size */ 1801 #define MC_CMD_FC_IN_LOG_ADDR_RANGE_ERASE_SIZE_OFST 16 1802 1803 /* MC_CMD_FC_IN_LOG_JTAG_UART msgrequest */ 1804 #define MC_CMD_FC_IN_LOG_JTAG_UART_LEN 12 1805 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1806 /* MC_CMD_FC_IN_LOG_OP_OFST 4 */ 1807 /* Enable/disable printing to JTAG UART */ 1808 #define MC_CMD_FC_IN_LOG_JTAG_UART_ENABLE_OFST 8 1809 1810 /* MC_CMD_FC_IN_CLOCK msgrequest */ 1811 #define MC_CMD_FC_IN_CLOCK_LEN 12 1812 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1813 #define MC_CMD_FC_IN_CLOCK_OP_OFST 4 1814 #define MC_CMD_FC_IN_CLOCK_GET_TIME 0x0 /* enum */ 1815 #define MC_CMD_FC_IN_CLOCK_SET_TIME 0x1 /* enum */ 1816 /* Perform a clock operation */ 1817 #define MC_CMD_FC_IN_CLOCK_ID_OFST 8 1818 #define MC_CMD_FC_IN_CLOCK_STATS 0x0 /* enum */ 1819 #define MC_CMD_FC_IN_CLOCK_MAC 0x1 /* enum */ 1820 1821 /* MC_CMD_FC_IN_CLOCK_GET_TIME msgrequest */ 1822 #define MC_CMD_FC_IN_CLOCK_GET_TIME_LEN 12 1823 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1824 /* MC_CMD_FC_IN_CLOCK_OP_OFST 4 */ 1825 /* Retrieve the clock value of the specified clock */ 1826 /* MC_CMD_FC_IN_CLOCK_ID_OFST 8 */ 1827 1828 /* MC_CMD_FC_IN_CLOCK_SET_TIME msgrequest */ 1829 #define MC_CMD_FC_IN_CLOCK_SET_TIME_LEN 24 1830 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1831 /* MC_CMD_FC_IN_CLOCK_OP_OFST 4 */ 1832 /* MC_CMD_FC_IN_CLOCK_ID_OFST 8 */ 1833 #define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_OFST 12 1834 #define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LEN 8 1835 #define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LO_OFST 12 1836 #define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_HI_OFST 16 1837 /* Set the clock value of the specified clock */ 1838 #define MC_CMD_FC_IN_CLOCK_SET_TIME_NANOSECONDS_OFST 20 1839 1840 /* MC_CMD_FC_IN_DDR msgrequest */ 1841 #define MC_CMD_FC_IN_DDR_LEN 12 1842 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1843 #define MC_CMD_FC_IN_DDR_OP_OFST 4 1844 #define MC_CMD_FC_IN_DDR_SET_SPD 0x0 /* enum */ 1845 #define MC_CMD_FC_IN_DDR_GET_STATUS 0x1 /* enum */ 1846 #define MC_CMD_FC_IN_DDR_SET_INFO 0x2 /* enum */ 1847 #define MC_CMD_FC_IN_DDR_BANK_OFST 8 1848 #define MC_CMD_FC_IN_DDR_BANK_B0 0x0 /* enum */ 1849 #define MC_CMD_FC_IN_DDR_BANK_B1 0x1 /* enum */ 1850 #define MC_CMD_FC_IN_DDR_BANK_T0 0x2 /* enum */ 1851 #define MC_CMD_FC_IN_DDR_BANK_T1 0x3 /* enum */ 1852 #define MC_CMD_FC_IN_DDR_NUM_BANKS 0x4 /* enum */ 1853 1854 /* MC_CMD_FC_IN_DDR_SET_SPD msgrequest */ 1855 #define MC_CMD_FC_IN_DDR_SET_SPD_LEN 148 1856 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1857 /* MC_CMD_FC_IN_DDR_OP_OFST 4 */ 1858 /* Affected bank */ 1859 /* MC_CMD_FC_IN_DDR_BANK_OFST 8 */ 1860 /* Flags */ 1861 #define MC_CMD_FC_IN_DDR_FLAGS_OFST 12 1862 #define MC_CMD_FC_IN_DDR_SET_SPD_ACTIVE 0x1 /* enum */ 1863 /* 128-byte page of serial presence detect data read from module's EEPROM */ 1864 #define MC_CMD_FC_IN_DDR_SPD_OFST 16 1865 #define MC_CMD_FC_IN_DDR_SPD_LEN 1 1866 #define MC_CMD_FC_IN_DDR_SPD_NUM 128 1867 /* Page index of the spd data copied into MC_CMD_FC_IN_DDR_SPD */ 1868 #define MC_CMD_FC_IN_DDR_SPD_PAGE_ID_OFST 144 1869 1870 /* MC_CMD_FC_IN_DDR_SET_INFO msgrequest */ 1871 #define MC_CMD_FC_IN_DDR_SET_INFO_LEN 16 1872 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1873 /* MC_CMD_FC_IN_DDR_OP_OFST 4 */ 1874 /* Affected bank */ 1875 /* MC_CMD_FC_IN_DDR_BANK_OFST 8 */ 1876 /* Size of DDR */ 1877 #define MC_CMD_FC_IN_DDR_SIZE_OFST 12 1878 1879 /* MC_CMD_FC_IN_DDR_GET_STATUS msgrequest */ 1880 #define MC_CMD_FC_IN_DDR_GET_STATUS_LEN 12 1881 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1882 /* MC_CMD_FC_IN_DDR_OP_OFST 4 */ 1883 /* Affected bank */ 1884 /* MC_CMD_FC_IN_DDR_BANK_OFST 8 */ 1885 1886 /* MC_CMD_FC_IN_TIMESTAMP msgrequest */ 1887 #define MC_CMD_FC_IN_TIMESTAMP_LEN 8 1888 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1889 /* FC timestamp operation code */ 1890 #define MC_CMD_FC_IN_TIMESTAMP_OP_OFST 4 1891 /* enum: Read transmit timestamp(s) */ 1892 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT 0x0 1893 /* enum: Read snapshot timestamps */ 1894 #define MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT 0x1 1895 /* enum: Clear all transmit timestamps */ 1896 #define MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT 0x2 1897 1898 /* MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT msgrequest */ 1899 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_LEN 28 1900 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1901 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_OP_OFST 4 1902 /* Control filtering of the returned timestamp and sequence number specified 1903 * here 1904 */ 1905 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_FILTER_OFST 8 1906 /* enum: Return most recent timestamp. No filtering */ 1907 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_LATEST 0x0 1908 /* enum: Match timestamp against the PTP clock ID, port number and sequence 1909 * number specified 1910 */ 1911 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_MATCH 0x1 1912 /* Clock identity of PTP packet for which timestamp required */ 1913 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_OFST 12 1914 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_LEN 8 1915 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_LO_OFST 12 1916 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_HI_OFST 16 1917 /* Port number of PTP packet for which timestamp required */ 1918 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_PORT_NUM_OFST 20 1919 /* Sequence number of PTP packet for which timestamp required */ 1920 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_SEQ_NUM_OFST 24 1921 1922 /* MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT msgrequest */ 1923 #define MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT_LEN 8 1924 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1925 #define MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT_OP_OFST 4 1926 1927 /* MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT msgrequest */ 1928 #define MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT_LEN 8 1929 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1930 #define MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT_OP_OFST 4 1931 1932 /* MC_CMD_FC_IN_SPI msgrequest */ 1933 #define MC_CMD_FC_IN_SPI_LEN 8 1934 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1935 /* Basic commands for SPI Flash. */ 1936 #define MC_CMD_FC_IN_SPI_OP_OFST 4 1937 /* enum: SPI Flash read */ 1938 #define MC_CMD_FC_IN_SPI_READ 0x0 1939 /* enum: SPI Flash write */ 1940 #define MC_CMD_FC_IN_SPI_WRITE 0x1 1941 /* enum: SPI Flash erase */ 1942 #define MC_CMD_FC_IN_SPI_ERASE 0x2 1943 1944 /* MC_CMD_FC_IN_SPI_READ msgrequest */ 1945 #define MC_CMD_FC_IN_SPI_READ_LEN 16 1946 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1947 #define MC_CMD_FC_IN_SPI_READ_OP_OFST 4 1948 #define MC_CMD_FC_IN_SPI_READ_ADDR_OFST 8 1949 #define MC_CMD_FC_IN_SPI_READ_NUMBYTES_OFST 12 1950 1951 /* MC_CMD_FC_IN_SPI_WRITE msgrequest */ 1952 #define MC_CMD_FC_IN_SPI_WRITE_LENMIN 16 1953 #define MC_CMD_FC_IN_SPI_WRITE_LENMAX 252 1954 #define MC_CMD_FC_IN_SPI_WRITE_LEN(num) (12+4*(num)) 1955 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1956 #define MC_CMD_FC_IN_SPI_WRITE_OP_OFST 4 1957 #define MC_CMD_FC_IN_SPI_WRITE_ADDR_OFST 8 1958 #define MC_CMD_FC_IN_SPI_WRITE_BUFFER_OFST 12 1959 #define MC_CMD_FC_IN_SPI_WRITE_BUFFER_LEN 4 1960 #define MC_CMD_FC_IN_SPI_WRITE_BUFFER_MINNUM 1 1961 #define MC_CMD_FC_IN_SPI_WRITE_BUFFER_MAXNUM 60 1962 1963 /* MC_CMD_FC_IN_SPI_ERASE msgrequest */ 1964 #define MC_CMD_FC_IN_SPI_ERASE_LEN 16 1965 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1966 #define MC_CMD_FC_IN_SPI_ERASE_OP_OFST 4 1967 #define MC_CMD_FC_IN_SPI_ERASE_ADDR_OFST 8 1968 #define MC_CMD_FC_IN_SPI_ERASE_NUMBYTES_OFST 12 1969 1970 /* MC_CMD_FC_IN_DIAG msgrequest */ 1971 #define MC_CMD_FC_IN_DIAG_LEN 8 1972 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1973 /* Operation code indicating component type */ 1974 #define MC_CMD_FC_IN_DIAG_OP_OFST 4 1975 /* enum: Power noise generator. */ 1976 #define MC_CMD_FC_IN_DIAG_POWER_NOISE 0x0 1977 /* enum: DDR soak test component. */ 1978 #define MC_CMD_FC_IN_DIAG_DDR_SOAK 0x1 1979 /* enum: Diagnostics datapath control component. */ 1980 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL 0x2 1981 1982 /* MC_CMD_FC_IN_DIAG_POWER_NOISE msgrequest */ 1983 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_LEN 12 1984 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1985 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_OP_OFST 4 1986 /* Sub-opcode describing the operation to be carried out */ 1987 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_SUB_OP_OFST 8 1988 /* enum: Read the configuration (the 32-bit values in each of the clock enable 1989 * count and toggle count registers) 1990 */ 1991 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG 0x0 1992 /* enum: Write a new configuration to the clock enable count and toggle count 1993 * registers 1994 */ 1995 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG 0x1 1996 1997 /* MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG msgrequest */ 1998 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_LEN 12 1999 /* MC_CMD_FC_IN_CMD_OFST 0 */ 2000 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_OP_OFST 4 2001 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_SUB_OP_OFST 8 2002 2003 /* MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG msgrequest */ 2004 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_LEN 20 2005 /* MC_CMD_FC_IN_CMD_OFST 0 */ 2006 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_OP_OFST 4 2007 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_SUB_OP_OFST 8 2008 /* The 32-bit value to be written to the toggle count register */ 2009 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_TOGGLE_COUNT_OFST 12 2010 /* The 32-bit value to be written to the clock enable count register */ 2011 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_CLKEN_COUNT_OFST 16 2012 2013 /* MC_CMD_FC_IN_DIAG_DDR_SOAK msgrequest */ 2014 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_LEN 12 2015 /* MC_CMD_FC_IN_CMD_OFST 0 */ 2016 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_OP_OFST 4 2017 /* Sub-opcode describing the operation to be carried out */ 2018 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_SUB_OP_OFST 8 2019 /* enum: Starts DDR soak test on selected banks */ 2020 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START 0x0 2021 /* enum: Read status of DDR soak test */ 2022 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT 0x1 2023 /* enum: Stop test */ 2024 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP 0x2 2025 /* enum: Set or clear bit that triggers fake errors. These cause subsequent 2026 * tests to fail until the bit is cleared. 2027 */ 2028 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR 0x3 2029 2030 /* MC_CMD_FC_IN_DIAG_DDR_SOAK_START msgrequest */ 2031 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_LEN 24 2032 /* MC_CMD_FC_IN_CMD_OFST 0 */ 2033 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_OP_OFST 4 2034 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_SUB_OP_OFST 8 2035 /* Mask of DDR banks to be tested */ 2036 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_BANK_MASK_OFST 12 2037 /* Pattern to use in the soak test */ 2038 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_TEST_PATTERN_OFST 16 2039 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_ZEROS 0x0 /* enum */ 2040 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_ONES 0x1 /* enum */ 2041 /* Either multiple automatic tests until a STOP command is issued, or one 2042 * single test 2043 */ 2044 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_TEST_TYPE_OFST 20 2045 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_ONGOING_TEST 0x0 /* enum */ 2046 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_SINGLE_TEST 0x1 /* enum */ 2047 2048 /* MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT msgrequest */ 2049 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_LEN 16 2050 /* MC_CMD_FC_IN_CMD_OFST 0 */ 2051 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_OP_OFST 4 2052 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_SUB_OP_OFST 8 2053 /* DDR bank to read status from */ 2054 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_BANK_ID_OFST 12 2055 #define MC_CMD_FC_DDR_BANK0 0x0 /* enum */ 2056 #define MC_CMD_FC_DDR_BANK1 0x1 /* enum */ 2057 #define MC_CMD_FC_DDR_BANK2 0x2 /* enum */ 2058 #define MC_CMD_FC_DDR_BANK3 0x3 /* enum */ 2059 #define MC_CMD_FC_DDR_AOEMEM_MAX_BANKS 0x4 /* enum */ 2060 2061 /* MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP msgrequest */ 2062 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_LEN 16 2063 /* MC_CMD_FC_IN_CMD_OFST 0 */ 2064 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_OP_OFST 4 2065 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_SUB_OP_OFST 8 2066 /* Mask of DDR banks to be tested */ 2067 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_BANK_MASK_OFST 12 2068 2069 /* MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR msgrequest */ 2070 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_LEN 20 2071 /* MC_CMD_FC_IN_CMD_OFST 0 */ 2072 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_OP_OFST 4 2073 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_SUB_OP_OFST 8 2074 /* Mask of DDR banks to set/clear error flag on */ 2075 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_BANK_MASK_OFST 12 2076 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_FLAG_ACTION_OFST 16 2077 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_CLEAR 0x0 /* enum */ 2078 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_SET 0x1 /* enum */ 2079 2080 /* MC_CMD_FC_IN_DIAG_DATAPATH_CTRL msgrequest */ 2081 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_LEN 12 2082 /* MC_CMD_FC_IN_CMD_OFST 0 */ 2083 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_OP_OFST 4 2084 /* Sub-opcode describing the operation to be carried out */ 2085 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SUB_OP_OFST 8 2086 /* enum: Set a known datapath configuration */ 2087 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE 0x0 2088 /* enum: Apply raw config to datapath control registers */ 2089 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG 0x1 2090 2091 /* MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE msgrequest */ 2092 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_LEN 16 2093 /* MC_CMD_FC_IN_CMD_OFST 0 */ 2094 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_OP_OFST 4 2095 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_SUB_OP_OFST 8 2096 /* Datapath configuration identifier */ 2097 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_MODE_OFST 12 2098 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_PASSTHROUGH 0x0 /* enum */ 2099 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_SNAKE 0x1 /* enum */ 2100 2101 /* MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG msgrequest */ 2102 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_LEN 24 2103 /* MC_CMD_FC_IN_CMD_OFST 0 */ 2104 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_OP_OFST 4 2105 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_SUB_OP_OFST 8 2106 /* Value to write into control register 1 */ 2107 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL1_OFST 12 2108 /* Value to write into control register 2 */ 2109 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL2_OFST 16 2110 /* Value to write into control register 3 */ 2111 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL3_OFST 20 2112 2113 /* MC_CMD_FC_OUT msgresponse */ 2114 #define MC_CMD_FC_OUT_LEN 0 2115 2116 /* MC_CMD_FC_OUT_NULL msgresponse */ 2117 #define MC_CMD_FC_OUT_NULL_LEN 0 2118 2119 /* MC_CMD_FC_OUT_READ32 msgresponse */ 2120 #define MC_CMD_FC_OUT_READ32_LENMIN 4 2121 #define MC_CMD_FC_OUT_READ32_LENMAX 252 2122 #define MC_CMD_FC_OUT_READ32_LEN(num) (0+4*(num)) 2123 #define MC_CMD_FC_OUT_READ32_BUFFER_OFST 0 2124 #define MC_CMD_FC_OUT_READ32_BUFFER_LEN 4 2125 #define MC_CMD_FC_OUT_READ32_BUFFER_MINNUM 1 2126 #define MC_CMD_FC_OUT_READ32_BUFFER_MAXNUM 63 2127 2128 /* MC_CMD_FC_OUT_WRITE32 msgresponse */ 2129 #define MC_CMD_FC_OUT_WRITE32_LEN 0 2130 2131 /* MC_CMD_FC_OUT_TRC_READ msgresponse */ 2132 #define MC_CMD_FC_OUT_TRC_READ_LEN 16 2133 #define MC_CMD_FC_OUT_TRC_READ_DATA_OFST 0 2134 #define MC_CMD_FC_OUT_TRC_READ_DATA_LEN 4 2135 #define MC_CMD_FC_OUT_TRC_READ_DATA_NUM 4 2136 2137 /* MC_CMD_FC_OUT_TRC_WRITE msgresponse */ 2138 #define MC_CMD_FC_OUT_TRC_WRITE_LEN 0 2139 2140 /* MC_CMD_FC_OUT_GET_VERSION msgresponse */ 2141 #define MC_CMD_FC_OUT_GET_VERSION_LEN 12 2142 #define MC_CMD_FC_OUT_GET_VERSION_FIRMWARE_OFST 0 2143 #define MC_CMD_FC_OUT_GET_VERSION_VERSION_OFST 4 2144 #define MC_CMD_FC_OUT_GET_VERSION_VERSION_LEN 8 2145 #define MC_CMD_FC_OUT_GET_VERSION_VERSION_LO_OFST 4 2146 #define MC_CMD_FC_OUT_GET_VERSION_VERSION_HI_OFST 8 2147 2148 /* MC_CMD_FC_OUT_TRC_RX_READ msgresponse */ 2149 #define MC_CMD_FC_OUT_TRC_RX_READ_LEN 8 2150 #define MC_CMD_FC_OUT_TRC_RX_READ_DATA_OFST 0 2151 #define MC_CMD_FC_OUT_TRC_RX_READ_DATA_LEN 4 2152 #define MC_CMD_FC_OUT_TRC_RX_READ_DATA_NUM 2 2153 2154 /* MC_CMD_FC_OUT_TRC_RX_WRITE msgresponse */ 2155 #define MC_CMD_FC_OUT_TRC_RX_WRITE_LEN 0 2156 2157 /* MC_CMD_FC_OUT_MAC_RECONFIGURE msgresponse */ 2158 #define MC_CMD_FC_OUT_MAC_RECONFIGURE_LEN 0 2159 2160 /* MC_CMD_FC_OUT_MAC_SET_LINK msgresponse */ 2161 #define MC_CMD_FC_OUT_MAC_SET_LINK_LEN 0 2162 2163 /* MC_CMD_FC_OUT_MAC_READ_STATUS msgresponse */ 2164 #define MC_CMD_FC_OUT_MAC_READ_STATUS_LEN 4 2165 #define MC_CMD_FC_OUT_MAC_READ_STATUS_STATUS_OFST 0 2166 2167 /* MC_CMD_FC_OUT_MAC_GET_RX_STATS msgresponse */ 2168 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_LEN ((((0-1+(64*MC_CMD_FC_MAC_RX_NSTATS))+1))>>3) 2169 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_OFST 0 2170 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_LEN 8 2171 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_LO_OFST 0 2172 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_HI_OFST 4 2173 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_NUM MC_CMD_FC_MAC_RX_NSTATS 2174 #define MC_CMD_FC_MAC_RX_STATS_OCTETS 0x0 /* enum */ 2175 #define MC_CMD_FC_MAC_RX_OCTETS_OK 0x1 /* enum */ 2176 #define MC_CMD_FC_MAC_RX_ALIGNMENT_ERRORS 0x2 /* enum */ 2177 #define MC_CMD_FC_MAC_RX_PAUSE_MAC_CTRL_FRAMES 0x3 /* enum */ 2178 #define MC_CMD_FC_MAC_RX_FRAMES_OK 0x4 /* enum */ 2179 #define MC_CMD_FC_MAC_RX_CRC_ERRORS 0x5 /* enum */ 2180 #define MC_CMD_FC_MAC_RX_VLAN_OK 0x6 /* enum */ 2181 #define MC_CMD_FC_MAC_RX_ERRORS 0x7 /* enum */ 2182 #define MC_CMD_FC_MAC_RX_UCAST_PKTS 0x8 /* enum */ 2183 #define MC_CMD_FC_MAC_RX_MULTICAST_PKTS 0x9 /* enum */ 2184 #define MC_CMD_FC_MAC_RX_BROADCAST_PKTS 0xa /* enum */ 2185 #define MC_CMD_FC_MAC_RX_STATS_DROP_EVENTS 0xb /* enum */ 2186 #define MC_CMD_FC_MAC_RX_STATS_PKTS 0xc /* enum */ 2187 #define MC_CMD_FC_MAC_RX_STATS_UNDERSIZE_PKTS 0xd /* enum */ 2188 #define MC_CMD_FC_MAC_RX_STATS_PKTS_64 0xe /* enum */ 2189 #define MC_CMD_FC_MAC_RX_STATS_PKTS_65_127 0xf /* enum */ 2190 #define MC_CMD_FC_MAC_RX_STATS_PKTS_128_255 0x10 /* enum */ 2191 #define MC_CMD_FC_MAC_RX_STATS_PKTS_256_511 0x11 /* enum */ 2192 #define MC_CMD_FC_MAC_RX_STATS_PKTS_512_1023 0x12 /* enum */ 2193 #define MC_CMD_FC_MAC_RX_STATS_PKTS_1024_1518 0x13 /* enum */ 2194 #define MC_CMD_FC_MAC_RX_STATS_PKTS_1519_MAX 0x14 /* enum */ 2195 #define MC_CMD_FC_MAC_RX_STATS_OVERSIZE_PKTS 0x15 /* enum */ 2196 #define MC_CMD_FC_MAC_RX_STATS_JABBERS 0x16 /* enum */ 2197 #define MC_CMD_FC_MAC_RX_STATS_FRAGMENTS 0x17 /* enum */ 2198 #define MC_CMD_FC_MAC_RX_MAC_CONTROL_FRAMES 0x18 /* enum */ 2199 /* enum: (Last entry) */ 2200 #define MC_CMD_FC_MAC_RX_NSTATS 0x19 2201 2202 /* MC_CMD_FC_OUT_MAC_GET_TX_STATS msgresponse */ 2203 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_LEN ((((0-1+(64*MC_CMD_FC_MAC_TX_NSTATS))+1))>>3) 2204 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_OFST 0 2205 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_LEN 8 2206 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_LO_OFST 0 2207 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_HI_OFST 4 2208 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_NUM MC_CMD_FC_MAC_TX_NSTATS 2209 #define MC_CMD_FC_MAC_TX_STATS_OCTETS 0x0 /* enum */ 2210 #define MC_CMD_FC_MAC_TX_OCTETS_OK 0x1 /* enum */ 2211 #define MC_CMD_FC_MAC_TX_ALIGNMENT_ERRORS 0x2 /* enum */ 2212 #define MC_CMD_FC_MAC_TX_PAUSE_MAC_CTRL_FRAMES 0x3 /* enum */ 2213 #define MC_CMD_FC_MAC_TX_FRAMES_OK 0x4 /* enum */ 2214 #define MC_CMD_FC_MAC_TX_CRC_ERRORS 0x5 /* enum */ 2215 #define MC_CMD_FC_MAC_TX_VLAN_OK 0x6 /* enum */ 2216 #define MC_CMD_FC_MAC_TX_ERRORS 0x7 /* enum */ 2217 #define MC_CMD_FC_MAC_TX_UCAST_PKTS 0x8 /* enum */ 2218 #define MC_CMD_FC_MAC_TX_MULTICAST_PKTS 0x9 /* enum */ 2219 #define MC_CMD_FC_MAC_TX_BROADCAST_PKTS 0xa /* enum */ 2220 #define MC_CMD_FC_MAC_TX_STATS_DROP_EVENTS 0xb /* enum */ 2221 #define MC_CMD_FC_MAC_TX_STATS_PKTS 0xc /* enum */ 2222 #define MC_CMD_FC_MAC_TX_STATS_UNDERSIZE_PKTS 0xd /* enum */ 2223 #define MC_CMD_FC_MAC_TX_STATS_PKTS_64 0xe /* enum */ 2224 #define MC_CMD_FC_MAC_TX_STATS_PKTS_65_127 0xf /* enum */ 2225 #define MC_CMD_FC_MAC_TX_STATS_PKTS_128_255 0x10 /* enum */ 2226 #define MC_CMD_FC_MAC_TX_STATS_PKTS_256_511 0x11 /* enum */ 2227 #define MC_CMD_FC_MAC_TX_STATS_PKTS_512_1023 0x12 /* enum */ 2228 #define MC_CMD_FC_MAC_TX_STATS_PKTS_1024_1518 0x13 /* enum */ 2229 #define MC_CMD_FC_MAC_TX_STATS_PKTS_1519_TX_MTU 0x14 /* enum */ 2230 #define MC_CMD_FC_MAC_TX_MAC_CONTROL_FRAMES 0x15 /* enum */ 2231 /* enum: (Last entry) */ 2232 #define MC_CMD_FC_MAC_TX_NSTATS 0x16 2233 2234 /* MC_CMD_FC_OUT_MAC_GET_STATS msgresponse */ 2235 #define MC_CMD_FC_OUT_MAC_GET_STATS_LEN ((((0-1+(64*MC_CMD_FC_MAC_NSTATS_PER_BLOCK))+1))>>3) 2236 /* MAC Statistics */ 2237 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_OFST 0 2238 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_LEN 8 2239 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_LO_OFST 0 2240 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_HI_OFST 4 2241 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_NUM MC_CMD_FC_MAC_NSTATS_PER_BLOCK 2242 2243 /* MC_CMD_FC_OUT_MAC msgresponse */ 2244 #define MC_CMD_FC_OUT_MAC_LEN 0 2245 2246 /* MC_CMD_FC_OUT_SFP msgresponse */ 2247 #define MC_CMD_FC_OUT_SFP_LEN 0 2248 2249 /* MC_CMD_FC_OUT_DDR_TEST_START msgresponse */ 2250 #define MC_CMD_FC_OUT_DDR_TEST_START_LEN 0 2251 2252 /* MC_CMD_FC_OUT_DDR_TEST_POLL msgresponse */ 2253 #define MC_CMD_FC_OUT_DDR_TEST_POLL_LEN 8 2254 #define MC_CMD_FC_OUT_DDR_TEST_POLL_STATUS_OFST 0 2255 #define MC_CMD_FC_OUT_DDR_TEST_POLL_CODE_LBN 0 2256 #define MC_CMD_FC_OUT_DDR_TEST_POLL_CODE_WIDTH 8 2257 /* enum: Test not yet initiated */ 2258 #define MC_CMD_FC_OP_DDR_TEST_NONE 0x0 2259 /* enum: Test is in progress */ 2260 #define MC_CMD_FC_OP_DDR_TEST_INPROGRESS 0x1 2261 /* enum: Timed completed */ 2262 #define MC_CMD_FC_OP_DDR_TEST_SUCCESS 0x2 2263 /* enum: Test did not complete in specified time */ 2264 #define MC_CMD_FC_OP_DDR_TEST_TIMER_EXPIRED 0x3 2265 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T0_LBN 11 2266 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T0_WIDTH 1 2267 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T1_LBN 10 2268 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T1_WIDTH 1 2269 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B0_LBN 9 2270 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B0_WIDTH 1 2271 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B1_LBN 8 2272 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B1_WIDTH 1 2273 /* Test result from FPGA */ 2274 #define MC_CMD_FC_OUT_DDR_TEST_POLL_RESULT_OFST 4 2275 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T0_LBN 31 2276 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T0_WIDTH 1 2277 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T1_LBN 30 2278 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T1_WIDTH 1 2279 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B0_LBN 29 2280 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B0_WIDTH 1 2281 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B1_LBN 28 2282 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B1_WIDTH 1 2283 #define MC_CMD_FC_OUT_DDR_TEST_POLL_T0_LBN 15 2284 #define MC_CMD_FC_OUT_DDR_TEST_POLL_T0_WIDTH 5 2285 #define MC_CMD_FC_OUT_DDR_TEST_POLL_T1_LBN 10 2286 #define MC_CMD_FC_OUT_DDR_TEST_POLL_T1_WIDTH 5 2287 #define MC_CMD_FC_OUT_DDR_TEST_POLL_B0_LBN 5 2288 #define MC_CMD_FC_OUT_DDR_TEST_POLL_B0_WIDTH 5 2289 #define MC_CMD_FC_OUT_DDR_TEST_POLL_B1_LBN 0 2290 #define MC_CMD_FC_OUT_DDR_TEST_POLL_B1_WIDTH 5 2291 #define MC_CMD_FC_OUT_DDR_TEST_POLL_TEST_COMPLETE 0x0 /* enum */ 2292 #define MC_CMD_FC_OUT_DDR_TEST_POLL_TEST_FAIL 0x1 /* enum */ 2293 #define MC_CMD_FC_OUT_DDR_TEST_POLL_TEST_PASS 0x2 /* enum */ 2294 #define MC_CMD_FC_OUT_DDR_TEST_POLL_CAL_FAIL 0x3 /* enum */ 2295 #define MC_CMD_FC_OUT_DDR_TEST_POLL_CAL_SUCCESS 0x4 /* enum */ 2296 2297 /* MC_CMD_FC_OUT_DDR_TEST msgresponse */ 2298 #define MC_CMD_FC_OUT_DDR_TEST_LEN 0 2299 2300 /* MC_CMD_FC_OUT_GET_ASSERT msgresponse */ 2301 #define MC_CMD_FC_OUT_GET_ASSERT_LEN 144 2302 /* Assertion status flag. */ 2303 #define MC_CMD_FC_OUT_GET_ASSERT_GLOBAL_FLAGS_OFST 0 2304 #define MC_CMD_FC_OUT_GET_ASSERT_STATE_LBN 8 2305 #define MC_CMD_FC_OUT_GET_ASSERT_STATE_WIDTH 8 2306 /* enum: No crash data available */ 2307 #define MC_CMD_FC_GET_ASSERT_FLAGS_STATE_CLEAR 0x0 2308 /* enum: New crash data available */ 2309 #define MC_CMD_FC_GET_ASSERT_FLAGS_STATE_NEW 0x1 2310 /* enum: Crash data has been sent */ 2311 #define MC_CMD_FC_GET_ASSERT_FLAGS_STATE_NOTIFIED 0x2 2312 #define MC_CMD_FC_OUT_GET_ASSERT_TYPE_LBN 0 2313 #define MC_CMD_FC_OUT_GET_ASSERT_TYPE_WIDTH 8 2314 /* enum: No crash has been recorded. */ 2315 #define MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_NONE 0x0 2316 /* enum: Crash due to exception. */ 2317 #define MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_EXCEPTION 0x1 2318 /* enum: Crash due to assertion. */ 2319 #define MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_ASSERTION 0x2 2320 /* Failing PC value */ 2321 #define MC_CMD_FC_OUT_GET_ASSERT_SAVED_PC_OFFS_OFST 4 2322 /* Saved GP regs */ 2323 #define MC_CMD_FC_OUT_GET_ASSERT_GP_REGS_OFFS_OFST 8 2324 #define MC_CMD_FC_OUT_GET_ASSERT_GP_REGS_OFFS_LEN 4 2325 #define MC_CMD_FC_OUT_GET_ASSERT_GP_REGS_OFFS_NUM 31 2326 /* Exception Type */ 2327 #define MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_TYPE_OFFS_OFST 132 2328 /* Instruction at which exception occurred */ 2329 #define MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_PC_ADDR_OFFS_OFST 136 2330 /* BAD Address that triggered address-based exception */ 2331 #define MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_BAD_ADDR_OFFS_OFST 140 2332 2333 /* MC_CMD_FC_OUT_FPGA_BUILD msgresponse */ 2334 #define MC_CMD_FC_OUT_FPGA_BUILD_LEN 32 2335 #define MC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_INFO_OFST 0 2336 #define MC_CMD_FC_OUT_FPGA_BUILD_IS_APPLICATION_LBN 31 2337 #define MC_CMD_FC_OUT_FPGA_BUILD_IS_APPLICATION_WIDTH 1 2338 #define MC_CMD_FC_OUT_FPGA_BUILD_IS_LICENSED_LBN 30 2339 #define MC_CMD_FC_OUT_FPGA_BUILD_IS_LICENSED_WIDTH 1 2340 #define MC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_ID_LBN 16 2341 #define MC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_ID_WIDTH 14 2342 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MAJOR_LBN 12 2343 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MAJOR_WIDTH 4 2344 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MINOR_LBN 4 2345 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MINOR_WIDTH 8 2346 #define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_NUM_LBN 0 2347 #define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_NUM_WIDTH 4 2348 /* Build timestamp (seconds since epoch) */ 2349 #define MC_CMD_FC_OUT_FPGA_BUILD_TIMESTAMP_OFST 4 2350 #define MC_CMD_FC_OUT_FPGA_BUILD_PARAMETERS_OFST 8 2351 #define MC_CMD_FC_OUT_FPGA_BUILD_FPGA_TYPE_LBN 0 2352 #define MC_CMD_FC_OUT_FPGA_BUILD_FPGA_TYPE_WIDTH 8 2353 #define MC_CMD_FC_FPGA_TYPE_A7 0xa7 /* enum */ 2354 #define MC_CMD_FC_FPGA_TYPE_A5 0xa5 /* enum */ 2355 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED1_LBN 8 2356 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED1_WIDTH 10 2357 #define MC_CMD_FC_OUT_FPGA_BUILD_PTP_ENABLED_LBN 18 2358 #define MC_CMD_FC_OUT_FPGA_BUILD_PTP_ENABLED_WIDTH 1 2359 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM1_RLDRAM_DEF_LBN 19 2360 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM1_RLDRAM_DEF_WIDTH 1 2361 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM2_RLDRAM_DEF_LBN 20 2362 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM2_RLDRAM_DEF_WIDTH 1 2363 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM3_RLDRAM_DEF_LBN 21 2364 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM3_RLDRAM_DEF_WIDTH 1 2365 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM4_RLDRAM_DEF_LBN 22 2366 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM4_RLDRAM_DEF_WIDTH 1 2367 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T0_DDR3_DEF_LBN 23 2368 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T0_DDR3_DEF_WIDTH 1 2369 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_DDR3_DEF_LBN 24 2370 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_DDR3_DEF_WIDTH 1 2371 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B0_DDR3_DEF_LBN 25 2372 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B0_DDR3_DEF_WIDTH 1 2373 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B1_DDR3_DEF_LBN 26 2374 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B1_DDR3_DEF_WIDTH 1 2375 #define MC_CMD_FC_OUT_FPGA_BUILD_DDR3_ECC_ENABLED_LBN 27 2376 #define MC_CMD_FC_OUT_FPGA_BUILD_DDR3_ECC_ENABLED_WIDTH 1 2377 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_QDR_DEF_LBN 28 2378 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_QDR_DEF_WIDTH 1 2379 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED2_LBN 29 2380 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED2_WIDTH 2 2381 #define MC_CMD_FC_OUT_FPGA_BUILD_CRC_APPEND_LBN 31 2382 #define MC_CMD_FC_OUT_FPGA_BUILD_CRC_APPEND_WIDTH 1 2383 #define MC_CMD_FC_OUT_FPGA_BUILD_IDENTIFIER_OFST 12 2384 #define MC_CMD_FC_OUT_FPGA_BUILD_CHANGESET_LBN 0 2385 #define MC_CMD_FC_OUT_FPGA_BUILD_CHANGESET_WIDTH 16 2386 #define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_FLAG_LBN 16 2387 #define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_FLAG_WIDTH 1 2388 #define MC_CMD_FC_FPGA_BUILD_FLAG_INTERNAL 0x0 /* enum */ 2389 #define MC_CMD_FC_FPGA_BUILD_FLAG_RELEASE 0x1 /* enum */ 2390 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED3_LBN 17 2391 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED3_WIDTH 15 2392 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_HI_OFST 16 2393 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MINOR_LBN 0 2394 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MINOR_WIDTH 16 2395 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MAJOR_LBN 16 2396 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MAJOR_WIDTH 16 2397 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_LO_OFST 20 2398 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_BUILD_LBN 0 2399 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_BUILD_WIDTH 16 2400 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MICRO_LBN 16 2401 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MICRO_WIDTH 16 2402 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_OFST 16 2403 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_LEN 8 2404 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_LO_OFST 16 2405 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_HI_OFST 20 2406 #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_LO_OFST 24 2407 #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HI_OFST 28 2408 #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HIGH_LBN 0 2409 #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HIGH_WIDTH 16 2410 2411 /* MC_CMD_FC_OUT_FPGA_BUILD_V2 msgresponse */ 2412 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_LEN 32 2413 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_INFO_OFST 0 2414 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_APPLICATION_LBN 31 2415 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_APPLICATION_WIDTH 1 2416 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_LICENSED_LBN 30 2417 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_LICENSED_WIDTH 1 2418 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_ID_LBN 16 2419 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_ID_WIDTH 14 2420 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MAJOR_LBN 12 2421 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MAJOR_WIDTH 4 2422 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MINOR_LBN 4 2423 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MINOR_WIDTH 8 2424 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_NUM_LBN 0 2425 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_NUM_WIDTH 4 2426 /* Build timestamp (seconds since epoch) */ 2427 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_TIMESTAMP_OFST 4 2428 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_PARAMETERS_OFST 8 2429 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_PMA_PASSTHROUGH_LBN 31 2430 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_PMA_PASSTHROUGH_WIDTH 1 2431 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_QDR_DEF_LBN 29 2432 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_QDR_DEF_WIDTH 1 2433 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_QDR_DEF_LBN 28 2434 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_QDR_DEF_WIDTH 1 2435 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DDR3_ECC_ENABLED_LBN 27 2436 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DDR3_ECC_ENABLED_WIDTH 1 2437 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_DDR3_DEF_LBN 26 2438 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_DDR3_DEF_WIDTH 1 2439 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_DDR3_DEF_LBN 25 2440 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_DDR3_DEF_WIDTH 1 2441 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_TO_DDR3_DEF_LBN 24 2442 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_TO_DDR3_DEF_WIDTH 1 2443 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_T0_DDR3_DEF_LBN 23 2444 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_T0_DDR3_DEF_WIDTH 1 2445 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_RLDRAM_DEF_LBN 22 2446 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_RLDRAM_DEF_WIDTH 1 2447 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_RLDRAM_DEF_LBN 21 2448 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_RLDRAM_DEF_WIDTH 1 2449 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_RLDRAM_DEF_LBN 20 2450 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_RLDRAM_DEF_WIDTH 1 2451 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_RLDRAM_DEF_LBN 19 2452 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_RLDRAM_DEF_WIDTH 1 2453 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_LBN 18 2454 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_WIDTH 1 2455 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_10G 0x0 /* enum */ 2456 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_40G 0x1 /* enum */ 2457 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_LBN 17 2458 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_WIDTH 1 2459 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_10G 0x0 /* enum */ 2460 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_40G 0x1 /* enum */ 2461 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_LBN 16 2462 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_WIDTH 1 2463 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_10G 0x0 /* enum */ 2464 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_40G 0x1 /* enum */ 2465 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP7_DEF_LBN 15 2466 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP7_DEF_WIDTH 1 2467 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP6_DEF_LBN 14 2468 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP6_DEF_WIDTH 1 2469 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP5_DEF_LBN 13 2470 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP5_DEF_WIDTH 1 2471 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_DEF_LBN 12 2472 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_DEF_WIDTH 1 2473 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP3_DEF_LBN 11 2474 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP3_DEF_WIDTH 1 2475 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP2_DEF_LBN 10 2476 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP2_DEF_WIDTH 1 2477 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP1_DEF_LBN 9 2478 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP1_DEF_WIDTH 1 2479 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_DEF_LBN 8 2480 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_DEF_WIDTH 1 2481 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC3_DEF_LBN 7 2482 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC3_DEF_WIDTH 1 2483 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC2_DEF_LBN 6 2484 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC2_DEF_WIDTH 1 2485 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC1_DEF_LBN 5 2486 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC1_DEF_WIDTH 1 2487 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_DEF_LBN 4 2488 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_DEF_WIDTH 1 2489 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_FPGA_TYPE_LBN 0 2490 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_FPGA_TYPE_WIDTH 4 2491 #define MC_CMD_FC_FPGA_V2_TYPE_A3 0x0 /* enum */ 2492 #define MC_CMD_FC_FPGA_V2_TYPE_A4 0x1 /* enum */ 2493 #define MC_CMD_FC_FPGA_V2_TYPE_A5 0x2 /* enum */ 2494 #define MC_CMD_FC_FPGA_V2_TYPE_A7 0x3 /* enum */ 2495 #define MC_CMD_FC_FPGA_V2_TYPE_D3 0x8 /* enum */ 2496 #define MC_CMD_FC_FPGA_V2_TYPE_D4 0x9 /* enum */ 2497 #define MC_CMD_FC_FPGA_V2_TYPE_D5 0xa /* enum */ 2498 #define MC_CMD_FC_FPGA_V2_TYPE_D7 0xb /* enum */ 2499 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_IDENTIFIER_OFST 12 2500 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_CHANGESET_LBN 0 2501 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_CHANGESET_WIDTH 16 2502 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_FLAG_LBN 16 2503 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_FLAG_WIDTH 1 2504 /* MC_CMD_FC_FPGA_BUILD_FLAG_INTERNAL 0x0 */ 2505 /* MC_CMD_FC_FPGA_BUILD_FLAG_RELEASE 0x1 */ 2506 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_HI_OFST 16 2507 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MINOR_LBN 0 2508 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MINOR_WIDTH 16 2509 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MAJOR_LBN 16 2510 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MAJOR_WIDTH 16 2511 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_LO_OFST 20 2512 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_BUILD_LBN 0 2513 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_BUILD_WIDTH 16 2514 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MICRO_LBN 16 2515 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MICRO_WIDTH 16 2516 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_LO_OFST 24 2517 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HI_OFST 28 2518 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HIGH_LBN 0 2519 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HIGH_WIDTH 16 2520 2521 /* MC_CMD_FC_OUT_FPGA_SERVICES msgresponse */ 2522 #define MC_CMD_FC_OUT_FPGA_SERVICES_LEN 32 2523 #define MC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_INFO_OFST 0 2524 #define MC_CMD_FC_OUT_FPGA_SERVICES_IS_APPLICATION_LBN 31 2525 #define MC_CMD_FC_OUT_FPGA_SERVICES_IS_APPLICATION_WIDTH 1 2526 #define MC_CMD_FC_OUT_FPGA_SERVICES_IS_LICENSED_LBN 30 2527 #define MC_CMD_FC_OUT_FPGA_SERVICES_IS_LICENSED_WIDTH 1 2528 #define MC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_ID_LBN 16 2529 #define MC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_ID_WIDTH 14 2530 #define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MAJOR_LBN 12 2531 #define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MAJOR_WIDTH 4 2532 #define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MINOR_LBN 4 2533 #define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MINOR_WIDTH 8 2534 #define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_NUM_LBN 0 2535 #define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_NUM_WIDTH 4 2536 /* Build timestamp (seconds since epoch) */ 2537 #define MC_CMD_FC_OUT_FPGA_SERVICES_TIMESTAMP_OFST 4 2538 #define MC_CMD_FC_OUT_FPGA_SERVICES_PARAMETERS_OFST 8 2539 #define MC_CMD_FC_OUT_FPGA_SERVICES_FC_FLASH_BOOTED_LBN 8 2540 #define MC_CMD_FC_OUT_FPGA_SERVICES_FC_FLASH_BOOTED_WIDTH 1 2541 #define MC_CMD_FC_OUT_FPGA_SERVICES_NIC0_DEF_LBN 27 2542 #define MC_CMD_FC_OUT_FPGA_SERVICES_NIC0_DEF_WIDTH 1 2543 #define MC_CMD_FC_OUT_FPGA_SERVICES_NIC1_DEF_LBN 28 2544 #define MC_CMD_FC_OUT_FPGA_SERVICES_NIC1_DEF_WIDTH 1 2545 #define MC_CMD_FC_OUT_FPGA_SERVICES_SFP0_DEF_LBN 29 2546 #define MC_CMD_FC_OUT_FPGA_SERVICES_SFP0_DEF_WIDTH 1 2547 #define MC_CMD_FC_OUT_FPGA_SERVICES_SFP1_DEF_LBN 30 2548 #define MC_CMD_FC_OUT_FPGA_SERVICES_SFP1_DEF_WIDTH 1 2549 #define MC_CMD_FC_OUT_FPGA_SERVICES_RESERVED_LBN 31 2550 #define MC_CMD_FC_OUT_FPGA_SERVICES_RESERVED_WIDTH 1 2551 #define MC_CMD_FC_OUT_FPGA_SERVICES_IDENTIFIER_OFST 12 2552 #define MC_CMD_FC_OUT_FPGA_SERVICES_CHANGESET_LBN 0 2553 #define MC_CMD_FC_OUT_FPGA_SERVICES_CHANGESET_WIDTH 16 2554 #define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_FLAG_LBN 16 2555 #define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_FLAG_WIDTH 1 2556 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_OFST 16 2557 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_WIDTH_LBN 0 2558 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_WIDTH_WIDTH 16 2559 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_COUNT_LBN 16 2560 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_COUNT_WIDTH 16 2561 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_OFST 20 2562 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_WIDTH_LBN 0 2563 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_WIDTH_WIDTH 16 2564 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_COUNT_LBN 16 2565 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_COUNT_WIDTH 16 2566 #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_LO_OFST 24 2567 #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HI_OFST 28 2568 #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HIGH_LBN 0 2569 #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HIGH_WIDTH 16 2570 2571 /* MC_CMD_FC_OUT_FPGA_SERVICES_V2 msgresponse */ 2572 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_LEN 32 2573 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_INFO_OFST 0 2574 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_APPLICATION_LBN 31 2575 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_APPLICATION_WIDTH 1 2576 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_LICENSED_LBN 30 2577 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_LICENSED_WIDTH 1 2578 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_ID_LBN 16 2579 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_ID_WIDTH 14 2580 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MAJOR_LBN 12 2581 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MAJOR_WIDTH 4 2582 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MINOR_LBN 4 2583 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MINOR_WIDTH 8 2584 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_NUM_LBN 0 2585 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_NUM_WIDTH 4 2586 /* Build timestamp (seconds since epoch) */ 2587 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_TIMESTAMP_OFST 4 2588 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_PARAMETERS_OFST 8 2589 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_PTP_ENABLED_LBN 0 2590 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_PTP_ENABLED_WIDTH 1 2591 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_FC_FLASH_BOOTED_LBN 8 2592 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_FC_FLASH_BOOTED_WIDTH 1 2593 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IDENTIFIER_OFST 12 2594 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_CHANGESET_LBN 0 2595 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_CHANGESET_WIDTH 16 2596 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_FLAG_LBN 16 2597 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_FLAG_WIDTH 1 2598 /* MC_CMD_FC_FPGA_BUILD_FLAG_INTERNAL 0x0 */ 2599 /* MC_CMD_FC_FPGA_BUILD_FLAG_RELEASE 0x1 */ 2600 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_LO_OFST 24 2601 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HI_OFST 28 2602 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HIGH_LBN 0 2603 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HIGH_WIDTH 16 2604 2605 /* MC_CMD_FC_OUT_BSP_VERSION msgresponse */ 2606 #define MC_CMD_FC_OUT_BSP_VERSION_LEN 4 2607 /* Qsys system ID */ 2608 #define MC_CMD_FC_OUT_BSP_VERSION_SYSID_OFST 0 2609 #define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MAJOR_LBN 12 2610 #define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MAJOR_WIDTH 4 2611 #define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MINOR_LBN 4 2612 #define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MINOR_WIDTH 8 2613 #define MC_CMD_FC_OUT_BSP_VERSION_BUILD_NUM_LBN 0 2614 #define MC_CMD_FC_OUT_BSP_VERSION_BUILD_NUM_WIDTH 4 2615 2616 /* MC_CMD_FC_OUT_READ_MAP_COUNT msgresponse */ 2617 #define MC_CMD_FC_OUT_READ_MAP_COUNT_LEN 4 2618 /* Number of maps */ 2619 #define MC_CMD_FC_OUT_READ_MAP_COUNT_NUM_MAPS_OFST 0 2620 2621 /* MC_CMD_FC_OUT_READ_MAP_INDEX msgresponse */ 2622 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN 164 2623 /* Index of the map */ 2624 #define MC_CMD_FC_OUT_READ_MAP_INDEX_INDEX_OFST 0 2625 /* Options for the map */ 2626 #define MC_CMD_FC_OUT_READ_MAP_INDEX_OPTIONS_OFST 4 2627 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_8 0x0 /* enum */ 2628 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_16 0x1 /* enum */ 2629 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_32 0x2 /* enum */ 2630 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_64 0x3 /* enum */ 2631 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_MASK 0x3 /* enum */ 2632 #define MC_CMD_FC_OUT_READ_MAP_INDEX_PATH_FC 0x4 /* enum */ 2633 #define MC_CMD_FC_OUT_READ_MAP_INDEX_PATH_MEM 0x8 /* enum */ 2634 #define MC_CMD_FC_OUT_READ_MAP_INDEX_PERM_READ 0x10 /* enum */ 2635 #define MC_CMD_FC_OUT_READ_MAP_INDEX_PERM_WRITE 0x20 /* enum */ 2636 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_FREE 0x0 /* enum */ 2637 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_LICENSED 0x40 /* enum */ 2638 /* Address of start of map */ 2639 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_OFST 8 2640 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_LEN 8 2641 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_LO_OFST 8 2642 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_HI_OFST 12 2643 /* Length of address map */ 2644 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_OFST 16 2645 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_LEN 8 2646 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_LO_OFST 16 2647 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_HI_OFST 20 2648 /* Component information field */ 2649 #define MC_CMD_FC_OUT_READ_MAP_INDEX_COMP_INFO_OFST 24 2650 /* License expiry data for map */ 2651 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_OFST 28 2652 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_LEN 8 2653 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_LO_OFST 28 2654 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_HI_OFST 32 2655 /* Name of the component */ 2656 #define MC_CMD_FC_OUT_READ_MAP_INDEX_NAME_OFST 36 2657 #define MC_CMD_FC_OUT_READ_MAP_INDEX_NAME_LEN 1 2658 #define MC_CMD_FC_OUT_READ_MAP_INDEX_NAME_NUM 128 2659 2660 /* MC_CMD_FC_OUT_READ_MAP msgresponse */ 2661 #define MC_CMD_FC_OUT_READ_MAP_LEN 0 2662 2663 /* MC_CMD_FC_OUT_CAPABILITIES msgresponse */ 2664 #define MC_CMD_FC_OUT_CAPABILITIES_LEN 8 2665 /* Number of internal ports */ 2666 #define MC_CMD_FC_OUT_CAPABILITIES_INTERNAL_OFST 0 2667 /* Number of external ports */ 2668 #define MC_CMD_FC_OUT_CAPABILITIES_EXTERNAL_OFST 4 2669 2670 /* MC_CMD_FC_OUT_GLOBAL_FLAGS msgresponse */ 2671 #define MC_CMD_FC_OUT_GLOBAL_FLAGS_LEN 4 2672 #define MC_CMD_FC_OUT_GLOBAL_FLAGS_FLAGS_OFST 0 2673 2674 /* MC_CMD_FC_OUT_IO_REL msgresponse */ 2675 #define MC_CMD_FC_OUT_IO_REL_LEN 0 2676 2677 /* MC_CMD_FC_OUT_IO_REL_GET_ADDR msgresponse */ 2678 #define MC_CMD_FC_OUT_IO_REL_GET_ADDR_LEN 8 2679 #define MC_CMD_FC_OUT_IO_REL_GET_ADDR_ADDR_HI_OFST 0 2680 #define MC_CMD_FC_OUT_IO_REL_GET_ADDR_ADDR_LO_OFST 4 2681 2682 /* MC_CMD_FC_OUT_IO_REL_READ32 msgresponse */ 2683 #define MC_CMD_FC_OUT_IO_REL_READ32_LENMIN 4 2684 #define MC_CMD_FC_OUT_IO_REL_READ32_LENMAX 252 2685 #define MC_CMD_FC_OUT_IO_REL_READ32_LEN(num) (0+4*(num)) 2686 #define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_OFST 0 2687 #define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_LEN 4 2688 #define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_MINNUM 1 2689 #define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_MAXNUM 63 2690 2691 /* MC_CMD_FC_OUT_IO_REL_WRITE32 msgresponse */ 2692 #define MC_CMD_FC_OUT_IO_REL_WRITE32_LEN 0 2693 2694 /* MC_CMD_FC_OUT_UHLINK_PHY msgresponse */ 2695 #define MC_CMD_FC_OUT_UHLINK_PHY_LEN 48 2696 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_SETTINGS_0_OFST 0 2697 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_VOD_LBN 0 2698 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_VOD_WIDTH 16 2699 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_1STPOSTTAP_LBN 16 2700 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_1STPOSTTAP_WIDTH 16 2701 /* Transceiver Transmit settings */ 2702 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_SETTINGS_1_OFST 4 2703 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_PRETAP_LBN 0 2704 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_PRETAP_WIDTH 16 2705 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_2NDPOSTTAP_LBN 16 2706 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_2NDPOSTTAP_WIDTH 16 2707 /* Transceiver Receive settings */ 2708 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_SETTINGS_OFST 8 2709 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_DC_GAIN_LBN 0 2710 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_DC_GAIN_WIDTH 16 2711 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_EQ_CONTROL_LBN 16 2712 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_EQ_CONTROL_WIDTH 16 2713 /* Rx eye opening */ 2714 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_OFST 12 2715 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_WIDTH_LBN 0 2716 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_WIDTH_WIDTH 16 2717 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_HEIGHT_LBN 16 2718 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_HEIGHT_WIDTH 16 2719 /* PCS status word */ 2720 #define MC_CMD_FC_OUT_UHLINK_PHY_PCS_STATUS_OFST 16 2721 /* Link status word */ 2722 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_WORD_OFST 20 2723 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_LBN 0 2724 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_WIDTH 1 2725 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_CONFIGURED_LBN 1 2726 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_CONFIGURED_WIDTH 1 2727 /* Current SFp parameters applied */ 2728 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_PARAMS_OFST 24 2729 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_PARAMS_LEN 20 2730 /* Link speed is 100, 1000, 10000 */ 2731 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_SPEED_OFST 24 2732 /* Length of copper cable - zero when not relevant */ 2733 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_COPPER_LEN_OFST 28 2734 /* True if a dual speed SFP+ module */ 2735 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_DUAL_SPEED_OFST 32 2736 /* True if an SFP Module is present (other fields valid when true) */ 2737 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_PRESENT_OFST 36 2738 /* The type of the SFP+ Module */ 2739 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_TYPE_OFST 40 2740 /* PHY config flags */ 2741 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_OFST 44 2742 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_DFE_LBN 0 2743 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_DFE_WIDTH 1 2744 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_AEQ_LBN 1 2745 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_AEQ_WIDTH 1 2746 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_RX_TUNING_LBN 2 2747 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_RX_TUNING_WIDTH 1 2748 2749 /* MC_CMD_FC_OUT_UHLINK_MAC msgresponse */ 2750 #define MC_CMD_FC_OUT_UHLINK_MAC_LEN 20 2751 /* MAC configuration applied */ 2752 #define MC_CMD_FC_OUT_UHLINK_MAC_CONFIG_OFST 0 2753 /* MTU size */ 2754 #define MC_CMD_FC_OUT_UHLINK_MAC_MTU_OFST 4 2755 /* IF Mode status */ 2756 #define MC_CMD_FC_OUT_UHLINK_MAC_IF_STATUS_OFST 8 2757 /* MAC address configured */ 2758 #define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_OFST 12 2759 #define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_LEN 8 2760 #define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_LO_OFST 12 2761 #define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_HI_OFST 16 2762 2763 /* MC_CMD_FC_OUT_UHLINK_RX_EYE msgresponse */ 2764 #define MC_CMD_FC_OUT_UHLINK_RX_EYE_LEN ((((0-1+(32*MC_CMD_FC_UHLINK_RX_EYE_PER_BLOCK))+1))>>3) 2765 /* Rx Eye measurements */ 2766 #define MC_CMD_FC_OUT_UHLINK_RX_EYE_RX_EYE_OFST 0 2767 #define MC_CMD_FC_OUT_UHLINK_RX_EYE_RX_EYE_LEN 4 2768 #define MC_CMD_FC_OUT_UHLINK_RX_EYE_RX_EYE_NUM MC_CMD_FC_UHLINK_RX_EYE_PER_BLOCK 2769 2770 /* MC_CMD_FC_OUT_UHLINK_DUMP_RX_EYE_PLOT msgresponse */ 2771 #define MC_CMD_FC_OUT_UHLINK_DUMP_RX_EYE_PLOT_LEN 0 2772 2773 /* MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT msgresponse */ 2774 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_LEN ((((32-1+(64*MC_CMD_FC_UHLINK_RX_EYE_PLOT_ROWS_PER_BLOCK))+1))>>3) 2775 /* Has the eye plot dump completed and data returned is valid? */ 2776 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_VALID_OFST 0 2777 /* Rx Eye binary plot */ 2778 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_OFST 4 2779 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_LEN 8 2780 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_LO_OFST 4 2781 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_HI_OFST 8 2782 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_NUM MC_CMD_FC_UHLINK_RX_EYE_PLOT_ROWS_PER_BLOCK 2783 2784 /* MC_CMD_FC_OUT_UHLINK_RX_TUNE msgresponse */ 2785 #define MC_CMD_FC_OUT_UHLINK_RX_TUNE_LEN 0 2786 2787 /* MC_CMD_FC_OUT_UHLINK_LOOPBACK_SET msgresponse */ 2788 #define MC_CMD_FC_OUT_UHLINK_LOOPBACK_SET_LEN 0 2789 2790 /* MC_CMD_FC_OUT_UHLINK_LOOPBACK_GET msgresponse */ 2791 #define MC_CMD_FC_OUT_UHLINK_LOOPBACK_GET_LEN 4 2792 #define MC_CMD_FC_OUT_UHLINK_LOOPBACK_GET_STATE_OFST 0 2793 2794 /* MC_CMD_FC_OUT_UHLINK msgresponse */ 2795 #define MC_CMD_FC_OUT_UHLINK_LEN 0 2796 2797 /* MC_CMD_FC_OUT_SET_LINK msgresponse */ 2798 #define MC_CMD_FC_OUT_SET_LINK_LEN 0 2799 2800 /* MC_CMD_FC_OUT_LICENSE msgresponse */ 2801 #define MC_CMD_FC_OUT_LICENSE_LEN 12 2802 /* Count of valid keys */ 2803 #define MC_CMD_FC_OUT_LICENSE_VALID_KEYS_OFST 0 2804 /* Count of invalid keys */ 2805 #define MC_CMD_FC_OUT_LICENSE_INVALID_KEYS_OFST 4 2806 /* Count of blacklisted keys */ 2807 #define MC_CMD_FC_OUT_LICENSE_BLACKLISTED_KEYS_OFST 8 2808 2809 /* MC_CMD_FC_OUT_STARTUP msgresponse */ 2810 #define MC_CMD_FC_OUT_STARTUP_LEN 4 2811 /* Capabilities of the FPGA/FC */ 2812 #define MC_CMD_FC_OUT_STARTUP_CAPABILITIES_OFST 0 2813 #define MC_CMD_FC_OUT_STARTUP_CAN_ACCESS_FLASH_LBN 0 2814 #define MC_CMD_FC_OUT_STARTUP_CAN_ACCESS_FLASH_WIDTH 1 2815 2816 /* MC_CMD_FC_OUT_DMA_READ msgresponse */ 2817 #define MC_CMD_FC_OUT_DMA_READ_LENMIN 1 2818 #define MC_CMD_FC_OUT_DMA_READ_LENMAX 252 2819 #define MC_CMD_FC_OUT_DMA_READ_LEN(num) (0+1*(num)) 2820 /* The data read */ 2821 #define MC_CMD_FC_OUT_DMA_READ_DATA_OFST 0 2822 #define MC_CMD_FC_OUT_DMA_READ_DATA_LEN 1 2823 #define MC_CMD_FC_OUT_DMA_READ_DATA_MINNUM 1 2824 #define MC_CMD_FC_OUT_DMA_READ_DATA_MAXNUM 252 2825 2826 /* MC_CMD_FC_OUT_TIMED_READ_SET msgresponse */ 2827 #define MC_CMD_FC_OUT_TIMED_READ_SET_LEN 4 2828 /* Timer handle */ 2829 #define MC_CMD_FC_OUT_TIMED_READ_SET_FC_HANDLE_OFST 0 2830 2831 /* MC_CMD_FC_OUT_TIMED_READ_GET msgresponse */ 2832 #define MC_CMD_FC_OUT_TIMED_READ_GET_LEN 52 2833 /* Host supplied handle (unique) */ 2834 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_HANDLE_OFST 0 2835 /* Address into which to transfer data in host */ 2836 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_OFST 4 2837 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_LEN 8 2838 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_LO_OFST 4 2839 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_HI_OFST 8 2840 /* AOE address from which to transfer data */ 2841 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_OFST 12 2842 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_LEN 8 2843 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_LO_OFST 12 2844 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_HI_OFST 16 2845 /* Length of AOE transfer (total) */ 2846 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_LENGTH_OFST 20 2847 /* Length of host transfer (total) */ 2848 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_LENGTH_OFST 24 2849 /* See FLAGS entry for MC_CMD_FC_IN_TIMED_READ_SET */ 2850 #define MC_CMD_FC_OUT_TIMED_READ_GET_FLAGS_OFST 28 2851 #define MC_CMD_FC_OUT_TIMED_READ_GET_PERIOD_OFST 32 2852 /* When active, start read time */ 2853 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_OFST 36 2854 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_LEN 8 2855 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_LO_OFST 36 2856 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_HI_OFST 40 2857 /* When active, end read time */ 2858 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_OFST 44 2859 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_LEN 8 2860 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_LO_OFST 44 2861 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_HI_OFST 48 2862 2863 /* MC_CMD_FC_OUT_LOG_ADDR_RANGE msgresponse */ 2864 #define MC_CMD_FC_OUT_LOG_ADDR_RANGE_LEN 0 2865 2866 /* MC_CMD_FC_OUT_LOG msgresponse */ 2867 #define MC_CMD_FC_OUT_LOG_LEN 0 2868 2869 /* MC_CMD_FC_OUT_CLOCK_GET_TIME msgresponse */ 2870 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_LEN 24 2871 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_CLOCK_ID_OFST 0 2872 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_OFST 4 2873 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_LEN 8 2874 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_LO_OFST 4 2875 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_HI_OFST 8 2876 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_NANOSECONDS_OFST 12 2877 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_RANGE_OFST 16 2878 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_PRECISION_OFST 20 2879 2880 /* MC_CMD_FC_OUT_CLOCK_SET_TIME msgresponse */ 2881 #define MC_CMD_FC_OUT_CLOCK_SET_TIME_LEN 0 2882 2883 /* MC_CMD_FC_OUT_DDR_SET_SPD msgresponse */ 2884 #define MC_CMD_FC_OUT_DDR_SET_SPD_LEN 0 2885 2886 /* MC_CMD_FC_OUT_DDR_SET_INFO msgresponse */ 2887 #define MC_CMD_FC_OUT_DDR_SET_INFO_LEN 0 2888 2889 /* MC_CMD_FC_OUT_DDR_GET_STATUS msgresponse */ 2890 #define MC_CMD_FC_OUT_DDR_GET_STATUS_LEN 4 2891 #define MC_CMD_FC_OUT_DDR_GET_STATUS_FLAGS_OFST 0 2892 #define MC_CMD_FC_OUT_DDR_GET_STATUS_READY_LBN 0 2893 #define MC_CMD_FC_OUT_DDR_GET_STATUS_READY_WIDTH 1 2894 #define MC_CMD_FC_OUT_DDR_GET_STATUS_CALIBRATED_LBN 1 2895 #define MC_CMD_FC_OUT_DDR_GET_STATUS_CALIBRATED_WIDTH 1 2896 2897 /* MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT msgresponse */ 2898 #define MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_LEN 8 2899 #define MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_SECONDS_OFST 0 2900 #define MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_NANOSECONDS_OFST 4 2901 2902 /* MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT msgresponse */ 2903 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LENMIN 8 2904 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LENMAX 248 2905 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LEN(num) (0+8*(num)) 2906 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_SECONDS_OFST 0 2907 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_NANOSECONDS_OFST 4 2908 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_OFST 0 2909 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_LEN 8 2910 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_LO_OFST 0 2911 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_HI_OFST 4 2912 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_MINNUM 0 2913 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_MAXNUM 31 2914 2915 /* MC_CMD_FC_OUT_SPI_READ msgresponse */ 2916 #define MC_CMD_FC_OUT_SPI_READ_LENMIN 4 2917 #define MC_CMD_FC_OUT_SPI_READ_LENMAX 252 2918 #define MC_CMD_FC_OUT_SPI_READ_LEN(num) (0+4*(num)) 2919 #define MC_CMD_FC_OUT_SPI_READ_BUFFER_OFST 0 2920 #define MC_CMD_FC_OUT_SPI_READ_BUFFER_LEN 4 2921 #define MC_CMD_FC_OUT_SPI_READ_BUFFER_MINNUM 1 2922 #define MC_CMD_FC_OUT_SPI_READ_BUFFER_MAXNUM 63 2923 2924 /* MC_CMD_FC_OUT_SPI_WRITE msgresponse */ 2925 #define MC_CMD_FC_OUT_SPI_WRITE_LEN 0 2926 2927 /* MC_CMD_FC_OUT_SPI_ERASE msgresponse */ 2928 #define MC_CMD_FC_OUT_SPI_ERASE_LEN 0 2929 2930 /* MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG msgresponse */ 2931 #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_LEN 8 2932 /* The 32-bit value read from the toggle count register */ 2933 #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_TOGGLE_COUNT_OFST 0 2934 /* The 32-bit value read from the clock enable count register */ 2935 #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_CLKEN_COUNT_OFST 4 2936 2937 /* MC_CMD_FC_OUT_DIAG_POWER_NOISE_WRITE_CONFIG msgresponse */ 2938 #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_WRITE_CONFIG_LEN 0 2939 2940 /* MC_CMD_FC_OUT_DIAG_DDR_SOAK_START msgresponse */ 2941 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_START_LEN 0 2942 2943 /* MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT msgresponse */ 2944 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_LEN 8 2945 /* DDR soak test status word; bits [4:0] are relevant. */ 2946 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_STATUS_OFST 0 2947 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PASSED_LBN 0 2948 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PASSED_WIDTH 1 2949 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_FAILED_LBN 1 2950 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_FAILED_WIDTH 1 2951 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_COMPLETED_LBN 2 2952 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_COMPLETED_WIDTH 1 2953 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_TIMEOUT_LBN 3 2954 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_TIMEOUT_WIDTH 1 2955 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PNF_LBN 4 2956 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PNF_WIDTH 1 2957 /* DDR soak test error count */ 2958 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_ERR_COUNT_OFST 4 2959 2960 /* MC_CMD_FC_OUT_DIAG_DDR_SOAK_STOP msgresponse */ 2961 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_STOP_LEN 0 2962 2963 /* MC_CMD_FC_OUT_DIAG_DDR_SOAK_ERROR msgresponse */ 2964 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_ERROR_LEN 0 2965 2966 /* MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_SET_MODE msgresponse */ 2967 #define MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_SET_MODE_LEN 0 2968 2969 /* MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_RAW_CONFIG msgresponse */ 2970 #define MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_RAW_CONFIG_LEN 0 2971 2972 2973 /***********************************/ 2974 /* MC_CMD_AOE 2975 * AOE operations on MC 2976 */ 2977 #define MC_CMD_AOE 0xa 2978 2979 /* MC_CMD_AOE_IN msgrequest */ 2980 #define MC_CMD_AOE_IN_LEN 4 2981 #define MC_CMD_AOE_IN_OP_HDR_OFST 0 2982 #define MC_CMD_AOE_IN_OP_LBN 0 2983 #define MC_CMD_AOE_IN_OP_WIDTH 8 2984 /* enum: FPGA and CPLD information */ 2985 #define MC_CMD_AOE_OP_INFO 0x1 2986 /* enum: Currents and voltages read from MCP3424s; DEBUG */ 2987 #define MC_CMD_AOE_OP_CURRENTS 0x2 2988 /* enum: Temperatures at locations around the PCB; DEBUG */ 2989 #define MC_CMD_AOE_OP_TEMPERATURES 0x3 2990 /* enum: Set CPLD to idle */ 2991 #define MC_CMD_AOE_OP_CPLD_IDLE 0x4 2992 /* enum: Read from CPLD register */ 2993 #define MC_CMD_AOE_OP_CPLD_READ 0x5 2994 /* enum: Write to CPLD register */ 2995 #define MC_CMD_AOE_OP_CPLD_WRITE 0x6 2996 /* enum: Execute CPLD instruction */ 2997 #define MC_CMD_AOE_OP_CPLD_INSTRUCTION 0x7 2998 /* enum: Reprogram the CPLD on the AOE device */ 2999 #define MC_CMD_AOE_OP_CPLD_REPROGRAM 0x8 3000 /* enum: AOE power control */ 3001 #define MC_CMD_AOE_OP_POWER 0x9 3002 /* enum: AOE image loading */ 3003 #define MC_CMD_AOE_OP_LOAD 0xa 3004 /* enum: Fan monitoring */ 3005 #define MC_CMD_AOE_OP_FAN_CONTROL 0xb 3006 /* enum: Fan failures since last reset */ 3007 #define MC_CMD_AOE_OP_FAN_FAILURES 0xc 3008 /* enum: Get generic AOE MAC statistics */ 3009 #define MC_CMD_AOE_OP_MAC_STATS 0xd 3010 /* enum: Retrieve PHY specific information */ 3011 #define MC_CMD_AOE_OP_GET_PHY_MEDIA_INFO 0xe 3012 /* enum: Write a number of JTAG primitive commands, return will give data */ 3013 #define MC_CMD_AOE_OP_JTAG_WRITE 0xf 3014 /* enum: Control access to the FPGA via the Siena JTAG Chain */ 3015 #define MC_CMD_AOE_OP_FPGA_ACCESS 0x10 3016 /* enum: Set the MTU offset between Siena and AOE MACs */ 3017 #define MC_CMD_AOE_OP_SET_MTU_OFFSET 0x11 3018 /* enum: How link state is handled */ 3019 #define MC_CMD_AOE_OP_LINK_STATE 0x12 3020 /* enum: How Siena MAC statistics are reported (deprecated - use 3021 * MC_CMD_AOE_OP_ASIC_STATS) 3022 */ 3023 #define MC_CMD_AOE_OP_SIENA_STATS 0x13 3024 /* enum: How native ASIC MAC statistics are reported - replaces the deprecated 3025 * command MC_CMD_AOE_OP_SIENA_STATS 3026 */ 3027 #define MC_CMD_AOE_OP_ASIC_STATS 0x13 3028 /* enum: DDR memory information */ 3029 #define MC_CMD_AOE_OP_DDR 0x14 3030 /* enum: FC control */ 3031 #define MC_CMD_AOE_OP_FC 0x15 3032 /* enum: DDR ECC status reads */ 3033 #define MC_CMD_AOE_OP_DDR_ECC_STATUS 0x16 3034 /* enum: Commands for MC-SPI Master emulation */ 3035 #define MC_CMD_AOE_OP_MC_SPI_MASTER 0x17 3036 /* enum: Commands for FC boot control */ 3037 #define MC_CMD_AOE_OP_FC_BOOT 0x18 3038 3039 /* MC_CMD_AOE_OUT msgresponse */ 3040 #define MC_CMD_AOE_OUT_LEN 0 3041 3042 /* MC_CMD_AOE_IN_INFO msgrequest */ 3043 #define MC_CMD_AOE_IN_INFO_LEN 4 3044 #define MC_CMD_AOE_IN_CMD_OFST 0 3045 3046 /* MC_CMD_AOE_IN_CURRENTS msgrequest */ 3047 #define MC_CMD_AOE_IN_CURRENTS_LEN 4 3048 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3049 3050 /* MC_CMD_AOE_IN_TEMPERATURES msgrequest */ 3051 #define MC_CMD_AOE_IN_TEMPERATURES_LEN 4 3052 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3053 3054 /* MC_CMD_AOE_IN_CPLD_IDLE msgrequest */ 3055 #define MC_CMD_AOE_IN_CPLD_IDLE_LEN 4 3056 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3057 3058 /* MC_CMD_AOE_IN_CPLD_READ msgrequest */ 3059 #define MC_CMD_AOE_IN_CPLD_READ_LEN 12 3060 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3061 #define MC_CMD_AOE_IN_CPLD_READ_REGISTER_OFST 4 3062 #define MC_CMD_AOE_IN_CPLD_READ_WIDTH_OFST 8 3063 3064 /* MC_CMD_AOE_IN_CPLD_WRITE msgrequest */ 3065 #define MC_CMD_AOE_IN_CPLD_WRITE_LEN 16 3066 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3067 #define MC_CMD_AOE_IN_CPLD_WRITE_REGISTER_OFST 4 3068 #define MC_CMD_AOE_IN_CPLD_WRITE_WIDTH_OFST 8 3069 #define MC_CMD_AOE_IN_CPLD_WRITE_VALUE_OFST 12 3070 3071 /* MC_CMD_AOE_IN_CPLD_INSTRUCTION msgrequest */ 3072 #define MC_CMD_AOE_IN_CPLD_INSTRUCTION_LEN 8 3073 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3074 #define MC_CMD_AOE_IN_CPLD_INSTRUCTION_INSTRUCTION_OFST 4 3075 3076 /* MC_CMD_AOE_IN_CPLD_REPROGRAM msgrequest */ 3077 #define MC_CMD_AOE_IN_CPLD_REPROGRAM_LEN 8 3078 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3079 #define MC_CMD_AOE_IN_CPLD_REPROGRAM_OP_OFST 4 3080 /* enum: Reprogram CPLD, poll for completion */ 3081 #define MC_CMD_AOE_IN_CPLD_REPROGRAM_REPROGRAM 0x1 3082 /* enum: Reprogram CPLD, send event on completion */ 3083 #define MC_CMD_AOE_IN_CPLD_REPROGRAM_REPROGRAM_EVENT 0x3 3084 /* enum: Get status of reprogramming operation */ 3085 #define MC_CMD_AOE_IN_CPLD_REPROGRAM_STATUS 0x4 3086 3087 /* MC_CMD_AOE_IN_POWER msgrequest */ 3088 #define MC_CMD_AOE_IN_POWER_LEN 8 3089 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3090 /* Turn on or off AOE power */ 3091 #define MC_CMD_AOE_IN_POWER_OP_OFST 4 3092 /* enum: Turn off FPGA power */ 3093 #define MC_CMD_AOE_IN_POWER_OFF 0x0 3094 /* enum: Turn on FPGA power */ 3095 #define MC_CMD_AOE_IN_POWER_ON 0x1 3096 /* enum: Clear peak power measurement */ 3097 #define MC_CMD_AOE_IN_POWER_CLEAR 0x2 3098 /* enum: Show current power in sensors output */ 3099 #define MC_CMD_AOE_IN_POWER_SHOW_CURRENT 0x3 3100 /* enum: Show peak power in sensors output */ 3101 #define MC_CMD_AOE_IN_POWER_SHOW_PEAK 0x4 3102 /* enum: Show current DDR current */ 3103 #define MC_CMD_AOE_IN_POWER_DDR_LAST 0x5 3104 /* enum: Show peak DDR current */ 3105 #define MC_CMD_AOE_IN_POWER_DDR_PEAK 0x6 3106 /* enum: Clear peak DDR current */ 3107 #define MC_CMD_AOE_IN_POWER_DDR_CLEAR 0x7 3108 3109 /* MC_CMD_AOE_IN_LOAD msgrequest */ 3110 #define MC_CMD_AOE_IN_LOAD_LEN 8 3111 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3112 /* Image to be loaded (0 - main or 1 - diagnostic) to load in normal sequence 3113 */ 3114 #define MC_CMD_AOE_IN_LOAD_IMAGE_OFST 4 3115 3116 /* MC_CMD_AOE_IN_FAN_CONTROL msgrequest */ 3117 #define MC_CMD_AOE_IN_FAN_CONTROL_LEN 8 3118 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3119 /* If non zero report measured fan RPM rather than nominal */ 3120 #define MC_CMD_AOE_IN_FAN_CONTROL_REAL_RPM_OFST 4 3121 3122 /* MC_CMD_AOE_IN_FAN_FAILURES msgrequest */ 3123 #define MC_CMD_AOE_IN_FAN_FAILURES_LEN 4 3124 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3125 3126 /* MC_CMD_AOE_IN_MAC_STATS msgrequest */ 3127 #define MC_CMD_AOE_IN_MAC_STATS_LEN 24 3128 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3129 /* AOE port */ 3130 #define MC_CMD_AOE_IN_MAC_STATS_PORT_OFST 4 3131 /* Host memory address for statistics */ 3132 #define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_OFST 8 3133 #define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_LEN 8 3134 #define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_LO_OFST 8 3135 #define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_HI_OFST 12 3136 #define MC_CMD_AOE_IN_MAC_STATS_CMD_OFST 16 3137 #define MC_CMD_AOE_IN_MAC_STATS_DMA_LBN 0 3138 #define MC_CMD_AOE_IN_MAC_STATS_DMA_WIDTH 1 3139 #define MC_CMD_AOE_IN_MAC_STATS_CLEAR_LBN 1 3140 #define MC_CMD_AOE_IN_MAC_STATS_CLEAR_WIDTH 1 3141 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CHANGE_LBN 2 3142 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CHANGE_WIDTH 1 3143 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_ENABLE_LBN 3 3144 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_ENABLE_WIDTH 1 3145 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CLEAR_LBN 4 3146 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CLEAR_WIDTH 1 3147 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_NOEVENT_LBN 5 3148 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_NOEVENT_WIDTH 1 3149 #define MC_CMD_AOE_IN_MAC_STATS_PERIOD_MS_LBN 16 3150 #define MC_CMD_AOE_IN_MAC_STATS_PERIOD_MS_WIDTH 16 3151 /* Length of DMA data (optional) */ 3152 #define MC_CMD_AOE_IN_MAC_STATS_DMA_LEN_OFST 20 3153 3154 /* MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO msgrequest */ 3155 #define MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_LEN 12 3156 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3157 /* AOE port */ 3158 #define MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_PORT_OFST 4 3159 #define MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_PAGE_OFST 8 3160 3161 /* MC_CMD_AOE_IN_JTAG_WRITE msgrequest */ 3162 #define MC_CMD_AOE_IN_JTAG_WRITE_LENMIN 12 3163 #define MC_CMD_AOE_IN_JTAG_WRITE_LENMAX 252 3164 #define MC_CMD_AOE_IN_JTAG_WRITE_LEN(num) (8+4*(num)) 3165 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3166 #define MC_CMD_AOE_IN_JTAG_WRITE_DATALEN_OFST 4 3167 #define MC_CMD_AOE_IN_JTAG_WRITE_DATA_OFST 8 3168 #define MC_CMD_AOE_IN_JTAG_WRITE_DATA_LEN 4 3169 #define MC_CMD_AOE_IN_JTAG_WRITE_DATA_MINNUM 1 3170 #define MC_CMD_AOE_IN_JTAG_WRITE_DATA_MAXNUM 61 3171 3172 /* MC_CMD_AOE_IN_FPGA_ACCESS msgrequest */ 3173 #define MC_CMD_AOE_IN_FPGA_ACCESS_LEN 8 3174 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3175 /* Enable or disable access */ 3176 #define MC_CMD_AOE_IN_FPGA_ACCESS_OP_OFST 4 3177 /* enum: Enable access */ 3178 #define MC_CMD_AOE_IN_FPGA_ACCESS_ENABLE 0x1 3179 /* enum: Disable access */ 3180 #define MC_CMD_AOE_IN_FPGA_ACCESS_DISABLE 0x2 3181 3182 /* MC_CMD_AOE_IN_SET_MTU_OFFSET msgrequest */ 3183 #define MC_CMD_AOE_IN_SET_MTU_OFFSET_LEN 12 3184 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3185 /* AOE port - when not ALL_EXTERNAL or ALL_INTERNAL specifies port number */ 3186 #define MC_CMD_AOE_IN_SET_MTU_OFFSET_PORT_OFST 4 3187 /* enum: Apply to all external ports */ 3188 #define MC_CMD_AOE_IN_SET_MTU_OFFSET_ALL_EXTERNAL 0x8000 3189 /* enum: Apply to all internal ports */ 3190 #define MC_CMD_AOE_IN_SET_MTU_OFFSET_ALL_INTERNAL 0x4000 3191 /* The MTU offset to be applied to the external ports */ 3192 #define MC_CMD_AOE_IN_SET_MTU_OFFSET_OFFSET_OFST 8 3193 3194 /* MC_CMD_AOE_IN_LINK_STATE msgrequest */ 3195 #define MC_CMD_AOE_IN_LINK_STATE_LEN 8 3196 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3197 #define MC_CMD_AOE_IN_LINK_STATE_MODE_OFST 4 3198 #define MC_CMD_AOE_IN_LINK_STATE_CONFIG_MODE_LBN 0 3199 #define MC_CMD_AOE_IN_LINK_STATE_CONFIG_MODE_WIDTH 8 3200 /* enum: AOE and associated external port */ 3201 #define MC_CMD_AOE_IN_LINK_STATE_SIMPLE_SEPARATE 0x0 3202 /* enum: AOE and OR of all external ports */ 3203 #define MC_CMD_AOE_IN_LINK_STATE_SIMPLE_COMBINED 0x1 3204 /* enum: Individual ports */ 3205 #define MC_CMD_AOE_IN_LINK_STATE_DIAGNOSTIC 0x2 3206 /* enum: Configure link state mode on given AOE port */ 3207 #define MC_CMD_AOE_IN_LINK_STATE_CUSTOM 0x3 3208 #define MC_CMD_AOE_IN_LINK_STATE_OPERATION_LBN 8 3209 #define MC_CMD_AOE_IN_LINK_STATE_OPERATION_WIDTH 8 3210 /* enum: No-op */ 3211 #define MC_CMD_AOE_IN_LINK_STATE_OP_NONE 0x0 3212 /* enum: logical OR of all SFP ports link status */ 3213 #define MC_CMD_AOE_IN_LINK_STATE_OP_OR 0x1 3214 /* enum: logical AND of all SFP ports link status */ 3215 #define MC_CMD_AOE_IN_LINK_STATE_OP_AND 0x2 3216 #define MC_CMD_AOE_IN_LINK_STATE_SFP_MASK_LBN 16 3217 #define MC_CMD_AOE_IN_LINK_STATE_SFP_MASK_WIDTH 16 3218 3219 /* MC_CMD_AOE_IN_SIENA_STATS msgrequest */ 3220 #define MC_CMD_AOE_IN_SIENA_STATS_LEN 8 3221 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3222 /* How MAC statistics are reported */ 3223 #define MC_CMD_AOE_IN_SIENA_STATS_MODE_OFST 4 3224 /* enum: Statistics from Siena (default) */ 3225 #define MC_CMD_AOE_IN_SIENA_STATS_STATS_SIENA 0x0 3226 /* enum: Statistics from AOE external ports */ 3227 #define MC_CMD_AOE_IN_SIENA_STATS_STATS_AOE 0x1 3228 3229 /* MC_CMD_AOE_IN_ASIC_STATS msgrequest */ 3230 #define MC_CMD_AOE_IN_ASIC_STATS_LEN 8 3231 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3232 /* How MAC statistics are reported */ 3233 #define MC_CMD_AOE_IN_ASIC_STATS_MODE_OFST 4 3234 /* enum: Statistics from the ASIC (default) */ 3235 #define MC_CMD_AOE_IN_ASIC_STATS_STATS_ASIC 0x0 3236 /* enum: Statistics from AOE external ports */ 3237 #define MC_CMD_AOE_IN_ASIC_STATS_STATS_AOE 0x1 3238 3239 /* MC_CMD_AOE_IN_DDR msgrequest */ 3240 #define MC_CMD_AOE_IN_DDR_LEN 12 3241 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3242 #define MC_CMD_AOE_IN_DDR_BANK_OFST 4 3243 /* Enum values, see field(s): */ 3244 /* MC_CMD_FC/MC_CMD_FC_IN_DDR/MC_CMD_FC_IN_DDR_BANK */ 3245 /* Page index of SPD data */ 3246 #define MC_CMD_AOE_IN_DDR_SPD_PAGE_ID_OFST 8 3247 3248 /* MC_CMD_AOE_IN_FC msgrequest */ 3249 #define MC_CMD_AOE_IN_FC_LEN 4 3250 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3251 3252 /* MC_CMD_AOE_IN_DDR_ECC_STATUS msgrequest */ 3253 #define MC_CMD_AOE_IN_DDR_ECC_STATUS_LEN 8 3254 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3255 #define MC_CMD_AOE_IN_DDR_ECC_STATUS_BANK_OFST 4 3256 /* Enum values, see field(s): */ 3257 /* MC_CMD_FC/MC_CMD_FC_IN_DDR/MC_CMD_FC_IN_DDR_BANK */ 3258 3259 /* MC_CMD_AOE_IN_MC_SPI_MASTER msgrequest */ 3260 #define MC_CMD_AOE_IN_MC_SPI_MASTER_LEN 8 3261 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3262 /* Basic commands for MC SPI Master emulation. */ 3263 #define MC_CMD_AOE_IN_MC_SPI_MASTER_OP_OFST 4 3264 /* enum: MC SPI read */ 3265 #define MC_CMD_AOE_IN_MC_SPI_MASTER_READ 0x0 3266 /* enum: MC SPI write */ 3267 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE 0x1 3268 3269 /* MC_CMD_AOE_IN_MC_SPI_MASTER_READ msgrequest */ 3270 #define MC_CMD_AOE_IN_MC_SPI_MASTER_READ_LEN 12 3271 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3272 #define MC_CMD_AOE_IN_MC_SPI_MASTER_READ_OP_OFST 4 3273 #define MC_CMD_AOE_IN_MC_SPI_MASTER_READ_OFFSET_OFST 8 3274 3275 /* MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE msgrequest */ 3276 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_LEN 16 3277 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3278 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_OP_OFST 4 3279 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_OFFSET_OFST 8 3280 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_DATA_OFST 12 3281 3282 /* MC_CMD_AOE_IN_FC_BOOT msgrequest */ 3283 #define MC_CMD_AOE_IN_FC_BOOT_LEN 8 3284 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3285 /* FC boot control flags */ 3286 #define MC_CMD_AOE_IN_FC_BOOT_CONTROL_OFST 4 3287 #define MC_CMD_AOE_IN_FC_BOOT_CONTROL_BOOT_ENABLE_LBN 0 3288 #define MC_CMD_AOE_IN_FC_BOOT_CONTROL_BOOT_ENABLE_WIDTH 1 3289 3290 /* MC_CMD_AOE_OUT_INFO msgresponse */ 3291 #define MC_CMD_AOE_OUT_INFO_LEN 44 3292 /* JTAG IDCODE of CPLD */ 3293 #define MC_CMD_AOE_OUT_INFO_CPLD_IDCODE_OFST 0 3294 /* Version of CPLD */ 3295 #define MC_CMD_AOE_OUT_INFO_CPLD_VERSION_OFST 4 3296 /* JTAG IDCODE of FPGA */ 3297 #define MC_CMD_AOE_OUT_INFO_FPGA_IDCODE_OFST 8 3298 /* JTAG USERCODE of FPGA */ 3299 #define MC_CMD_AOE_OUT_INFO_FPGA_VERSION_OFST 12 3300 /* FPGA type - read from CPLD straps */ 3301 #define MC_CMD_AOE_OUT_INFO_FPGA_TYPE_OFST 16 3302 #define MC_CMD_AOE_OUT_INFO_FPGA_TYPE_A5_C2 0x1 /* enum */ 3303 #define MC_CMD_AOE_OUT_INFO_FPGA_TYPE_A7_C2 0x2 /* enum */ 3304 /* FPGA state (debug) */ 3305 #define MC_CMD_AOE_OUT_INFO_FPGA_STATE_OFST 20 3306 /* FPGA image - partition from which loaded */ 3307 #define MC_CMD_AOE_OUT_INFO_FPGA_IMAGE_OFST 24 3308 /* FC state */ 3309 #define MC_CMD_AOE_OUT_INFO_FC_STATE_OFST 28 3310 /* enum: Set if watchdog working */ 3311 #define MC_CMD_AOE_OUT_INFO_WATCHDOG 0x1 3312 /* enum: Set if MC-FC communications working */ 3313 #define MC_CMD_AOE_OUT_INFO_COMMS 0x2 3314 /* Random pieces of information */ 3315 #define MC_CMD_AOE_OUT_INFO_FLAGS_OFST 32 3316 /* enum: Power to FPGA supplied by PEG connector, not PCIe bus */ 3317 #define MC_CMD_AOE_OUT_INFO_PEG_POWER 0x1 3318 /* enum: CPLD apparently good */ 3319 #define MC_CMD_AOE_OUT_INFO_CPLD_GOOD 0x2 3320 /* enum: FPGA working normally */ 3321 #define MC_CMD_AOE_OUT_INFO_FPGA_GOOD 0x4 3322 /* enum: FPGA is powered */ 3323 #define MC_CMD_AOE_OUT_INFO_FPGA_POWER 0x8 3324 /* enum: Board has incompatible SODIMMs fitted */ 3325 #define MC_CMD_AOE_OUT_INFO_BAD_SODIMM 0x10 3326 /* enum: Board has ByteBlaster connected */ 3327 #define MC_CMD_AOE_OUT_INFO_HAS_BYTEBLASTER 0x20 3328 /* enum: FPGA Boot flash has an invalid header. */ 3329 #define MC_CMD_AOE_OUT_INFO_FPGA_BAD_BOOT_HDR 0x40 3330 /* enum: FPGA Application flash is accessible. */ 3331 #define MC_CMD_AOE_OUT_INFO_FPGA_APP_FLASH_GOOD 0x80 3332 /* Revision of Modena and Sorrento boards. Sorrento can be R1_2 or R1_3. */ 3333 #define MC_CMD_AOE_OUT_INFO_BOARD_REVISION_OFST 36 3334 #define MC_CMD_AOE_OUT_INFO_UNKNOWN 0x0 /* enum */ 3335 #define MC_CMD_AOE_OUT_INFO_R1_0 0x10 /* enum */ 3336 #define MC_CMD_AOE_OUT_INFO_R1_1 0x11 /* enum */ 3337 #define MC_CMD_AOE_OUT_INFO_R1_2 0x12 /* enum */ 3338 #define MC_CMD_AOE_OUT_INFO_R1_3 0x13 /* enum */ 3339 /* Result of FC booting - not valid while a ByteBlaster is connected. */ 3340 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_RESULT_OFST 40 3341 /* enum: No error */ 3342 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_NO_ERROR 0x0 3343 /* enum: Bad address set in CPLD */ 3344 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_ADDRESS 0x1 3345 /* enum: Bad header */ 3346 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_MAGIC 0x2 3347 /* enum: Bad text section details */ 3348 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_TEXT 0x3 3349 /* enum: Bad checksum */ 3350 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_CHECKSUM 0x4 3351 /* enum: Bad BSP */ 3352 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_BSP 0x5 3353 /* enum: FC application loaded and execution attempted */ 3354 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_APP_EXECUTE 0x80 3355 /* enum: FC application Started */ 3356 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_APP_STARTED 0x81 3357 /* enum: No bootrom in FPGA */ 3358 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_NO_BOOTROM 0xff 3359 3360 /* MC_CMD_AOE_OUT_CURRENTS msgresponse */ 3361 #define MC_CMD_AOE_OUT_CURRENTS_LEN 68 3362 /* Set of currents and voltages (mA or mV as appropriate) */ 3363 #define MC_CMD_AOE_OUT_CURRENTS_VALUES_OFST 0 3364 #define MC_CMD_AOE_OUT_CURRENTS_VALUES_LEN 4 3365 #define MC_CMD_AOE_OUT_CURRENTS_VALUES_NUM 17 3366 #define MC_CMD_AOE_OUT_CURRENTS_I_2V5 0x0 /* enum */ 3367 #define MC_CMD_AOE_OUT_CURRENTS_I_1V8 0x1 /* enum */ 3368 #define MC_CMD_AOE_OUT_CURRENTS_I_GXB 0x2 /* enum */ 3369 #define MC_CMD_AOE_OUT_CURRENTS_I_PGM 0x3 /* enum */ 3370 #define MC_CMD_AOE_OUT_CURRENTS_I_XCVR 0x4 /* enum */ 3371 #define MC_CMD_AOE_OUT_CURRENTS_I_1V5 0x5 /* enum */ 3372 #define MC_CMD_AOE_OUT_CURRENTS_V_3V3 0x6 /* enum */ 3373 #define MC_CMD_AOE_OUT_CURRENTS_V_1V5 0x7 /* enum */ 3374 #define MC_CMD_AOE_OUT_CURRENTS_I_IN 0x8 /* enum */ 3375 #define MC_CMD_AOE_OUT_CURRENTS_I_OUT 0x9 /* enum */ 3376 #define MC_CMD_AOE_OUT_CURRENTS_V_IN 0xa /* enum */ 3377 #define MC_CMD_AOE_OUT_CURRENTS_I_OUT_DDR1 0xb /* enum */ 3378 #define MC_CMD_AOE_OUT_CURRENTS_V_OUT_DDR1 0xc /* enum */ 3379 #define MC_CMD_AOE_OUT_CURRENTS_I_OUT_DDR2 0xd /* enum */ 3380 #define MC_CMD_AOE_OUT_CURRENTS_V_OUT_DDR2 0xe /* enum */ 3381 #define MC_CMD_AOE_OUT_CURRENTS_I_OUT_DDR3 0xf /* enum */ 3382 #define MC_CMD_AOE_OUT_CURRENTS_V_OUT_DDR3 0x10 /* enum */ 3383 3384 /* MC_CMD_AOE_OUT_TEMPERATURES msgresponse */ 3385 #define MC_CMD_AOE_OUT_TEMPERATURES_LEN 40 3386 /* Set of temperatures */ 3387 #define MC_CMD_AOE_OUT_TEMPERATURES_VALUES_OFST 0 3388 #define MC_CMD_AOE_OUT_TEMPERATURES_VALUES_LEN 4 3389 #define MC_CMD_AOE_OUT_TEMPERATURES_VALUES_NUM 10 3390 /* enum: The first set of enum values are for Modena code. */ 3391 #define MC_CMD_AOE_OUT_TEMPERATURES_MAIN_0 0x0 3392 #define MC_CMD_AOE_OUT_TEMPERATURES_MAIN_1 0x1 /* enum */ 3393 #define MC_CMD_AOE_OUT_TEMPERATURES_IND_0 0x2 /* enum */ 3394 #define MC_CMD_AOE_OUT_TEMPERATURES_IND_1 0x3 /* enum */ 3395 #define MC_CMD_AOE_OUT_TEMPERATURES_VCCIO1 0x4 /* enum */ 3396 #define MC_CMD_AOE_OUT_TEMPERATURES_VCCIO2 0x5 /* enum */ 3397 #define MC_CMD_AOE_OUT_TEMPERATURES_VCCIO3 0x6 /* enum */ 3398 #define MC_CMD_AOE_OUT_TEMPERATURES_PSU 0x7 /* enum */ 3399 #define MC_CMD_AOE_OUT_TEMPERATURES_FPGA 0x8 /* enum */ 3400 #define MC_CMD_AOE_OUT_TEMPERATURES_SIENA 0x9 /* enum */ 3401 /* enum: The second set of enum values are for Sorrento code. */ 3402 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_MAIN_0 0x0 3403 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_MAIN_1 0x1 /* enum */ 3404 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_IND_0 0x2 /* enum */ 3405 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_IND_1 0x3 /* enum */ 3406 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_SODIMM_0 0x4 /* enum */ 3407 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_SODIMM_1 0x5 /* enum */ 3408 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_FPGA 0x6 /* enum */ 3409 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_PHY0 0x7 /* enum */ 3410 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_PHY1 0x8 /* enum */ 3411 3412 /* MC_CMD_AOE_OUT_CPLD_READ msgresponse */ 3413 #define MC_CMD_AOE_OUT_CPLD_READ_LEN 4 3414 /* The value read from the CPLD */ 3415 #define MC_CMD_AOE_OUT_CPLD_READ_VALUE_OFST 0 3416 3417 /* MC_CMD_AOE_OUT_FAN_FAILURES msgresponse */ 3418 #define MC_CMD_AOE_OUT_FAN_FAILURES_LENMIN 4 3419 #define MC_CMD_AOE_OUT_FAN_FAILURES_LENMAX 252 3420 #define MC_CMD_AOE_OUT_FAN_FAILURES_LEN(num) (0+4*(num)) 3421 /* Failure counts for each fan */ 3422 #define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_OFST 0 3423 #define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_LEN 4 3424 #define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_MINNUM 1 3425 #define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_MAXNUM 63 3426 3427 /* MC_CMD_AOE_OUT_CPLD_REPROGRAM msgresponse */ 3428 #define MC_CMD_AOE_OUT_CPLD_REPROGRAM_LEN 4 3429 /* Results of status command (only) */ 3430 #define MC_CMD_AOE_OUT_CPLD_REPROGRAM_STATUS_OFST 0 3431 3432 /* MC_CMD_AOE_OUT_POWER_OFF msgresponse */ 3433 #define MC_CMD_AOE_OUT_POWER_OFF_LEN 0 3434 3435 /* MC_CMD_AOE_OUT_POWER_ON msgresponse */ 3436 #define MC_CMD_AOE_OUT_POWER_ON_LEN 0 3437 3438 /* MC_CMD_AOE_OUT_LOAD msgresponse */ 3439 #define MC_CMD_AOE_OUT_LOAD_LEN 0 3440 3441 /* MC_CMD_AOE_OUT_MAC_STATS_DMA msgresponse */ 3442 #define MC_CMD_AOE_OUT_MAC_STATS_DMA_LEN 0 3443 3444 /* MC_CMD_AOE_OUT_MAC_STATS_NO_DMA msgresponse: See MC_CMD_MAC_STATS_OUT_NO_DMA 3445 * for details 3446 */ 3447 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_LEN (((MC_CMD_MAC_NSTATS*64))>>3) 3448 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_OFST 0 3449 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_LEN 8 3450 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_LO_OFST 0 3451 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_HI_OFST 4 3452 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS 3453 3454 /* MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO msgresponse */ 3455 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LENMIN 5 3456 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LENMAX 252 3457 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LEN(num) (4+1*(num)) 3458 /* in bytes */ 3459 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATALEN_OFST 0 3460 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_OFST 4 3461 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_LEN 1 3462 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_MINNUM 1 3463 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_MAXNUM 248 3464 3465 /* MC_CMD_AOE_OUT_JTAG_WRITE msgresponse */ 3466 #define MC_CMD_AOE_OUT_JTAG_WRITE_LENMIN 12 3467 #define MC_CMD_AOE_OUT_JTAG_WRITE_LENMAX 252 3468 #define MC_CMD_AOE_OUT_JTAG_WRITE_LEN(num) (8+4*(num)) 3469 /* Used to align the in and out data blocks so the MC can re-use the cmd */ 3470 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATALEN_OFST 0 3471 /* out bytes */ 3472 #define MC_CMD_AOE_OUT_JTAG_WRITE_PAD_OFST 4 3473 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_OFST 8 3474 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_LEN 4 3475 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_MINNUM 1 3476 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_MAXNUM 61 3477 3478 /* MC_CMD_AOE_OUT_FPGA_ACCESS msgresponse */ 3479 #define MC_CMD_AOE_OUT_FPGA_ACCESS_LEN 0 3480 3481 /* MC_CMD_AOE_OUT_DDR msgresponse */ 3482 #define MC_CMD_AOE_OUT_DDR_LENMIN 17 3483 #define MC_CMD_AOE_OUT_DDR_LENMAX 252 3484 #define MC_CMD_AOE_OUT_DDR_LEN(num) (16+1*(num)) 3485 /* Information on the module. */ 3486 #define MC_CMD_AOE_OUT_DDR_FLAGS_OFST 0 3487 #define MC_CMD_AOE_OUT_DDR_PRESENT_LBN 0 3488 #define MC_CMD_AOE_OUT_DDR_PRESENT_WIDTH 1 3489 #define MC_CMD_AOE_OUT_DDR_POWERED_LBN 1 3490 #define MC_CMD_AOE_OUT_DDR_POWERED_WIDTH 1 3491 #define MC_CMD_AOE_OUT_DDR_OPERATIONAL_LBN 2 3492 #define MC_CMD_AOE_OUT_DDR_OPERATIONAL_WIDTH 1 3493 #define MC_CMD_AOE_OUT_DDR_NOT_REACHABLE_LBN 3 3494 #define MC_CMD_AOE_OUT_DDR_NOT_REACHABLE_WIDTH 1 3495 /* Memory size, in MB. */ 3496 #define MC_CMD_AOE_OUT_DDR_CAPACITY_OFST 4 3497 /* The memory type, as reported from SPD information */ 3498 #define MC_CMD_AOE_OUT_DDR_TYPE_OFST 8 3499 /* Nominal voltage of the module (as applied) */ 3500 #define MC_CMD_AOE_OUT_DDR_VOLTAGE_OFST 12 3501 /* SPD data read from the module */ 3502 #define MC_CMD_AOE_OUT_DDR_SPD_OFST 16 3503 #define MC_CMD_AOE_OUT_DDR_SPD_LEN 1 3504 #define MC_CMD_AOE_OUT_DDR_SPD_MINNUM 1 3505 #define MC_CMD_AOE_OUT_DDR_SPD_MAXNUM 236 3506 3507 /* MC_CMD_AOE_OUT_SET_MTU_OFFSET msgresponse */ 3508 #define MC_CMD_AOE_OUT_SET_MTU_OFFSET_LEN 0 3509 3510 /* MC_CMD_AOE_OUT_LINK_STATE msgresponse */ 3511 #define MC_CMD_AOE_OUT_LINK_STATE_LEN 0 3512 3513 /* MC_CMD_AOE_OUT_SIENA_STATS msgresponse */ 3514 #define MC_CMD_AOE_OUT_SIENA_STATS_LEN 0 3515 3516 /* MC_CMD_AOE_OUT_ASIC_STATS msgresponse */ 3517 #define MC_CMD_AOE_OUT_ASIC_STATS_LEN 0 3518 3519 /* MC_CMD_AOE_OUT_FC msgresponse */ 3520 #define MC_CMD_AOE_OUT_FC_LEN 0 3521 3522 /* MC_CMD_AOE_OUT_DDR_ECC_STATUS msgresponse */ 3523 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_LEN 8 3524 /* Flags describing status info on the module. */ 3525 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_FLAGS_OFST 0 3526 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_VALID_LBN 0 3527 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_VALID_WIDTH 1 3528 /* DDR ECC status on the module. */ 3529 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_STATUS_OFST 4 3530 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_LBN 0 3531 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_WIDTH 1 3532 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_LBN 1 3533 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_WIDTH 1 3534 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_LBN 2 3535 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_WIDTH 1 3536 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_COUNT_LBN 8 3537 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_COUNT_WIDTH 8 3538 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_COUNT_LBN 16 3539 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_COUNT_WIDTH 8 3540 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_COUNT_LBN 24 3541 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_COUNT_WIDTH 8 3542 3543 /* MC_CMD_AOE_OUT_MC_SPI_MASTER_READ msgresponse */ 3544 #define MC_CMD_AOE_OUT_MC_SPI_MASTER_READ_LEN 4 3545 #define MC_CMD_AOE_OUT_MC_SPI_MASTER_READ_DATA_OFST 0 3546 3547 /* MC_CMD_AOE_OUT_MC_SPI_MASTER_WRITE msgresponse */ 3548 #define MC_CMD_AOE_OUT_MC_SPI_MASTER_WRITE_LEN 0 3549 3550 /* MC_CMD_AOE_OUT_MC_SPI_MASTER msgresponse */ 3551 #define MC_CMD_AOE_OUT_MC_SPI_MASTER_LEN 0 3552 3553 /* MC_CMD_AOE_OUT_FC_BOOT msgresponse */ 3554 #define MC_CMD_AOE_OUT_FC_BOOT_LEN 0 3555 3556 3557 /***********************************/ 3558 /* MC_CMD_PTP 3559 * Perform PTP operation 3560 */ 3561 #define MC_CMD_PTP 0xb 3562 #undef MC_CMD_0xb_PRIVILEGE_CTG 3563 3564 #define MC_CMD_0xb_PRIVILEGE_CTG SRIOV_CTG_GENERAL 3565 3566 /* MC_CMD_PTP_IN msgrequest */ 3567 #define MC_CMD_PTP_IN_LEN 1 3568 /* PTP operation code */ 3569 #define MC_CMD_PTP_IN_OP_OFST 0 3570 #define MC_CMD_PTP_IN_OP_LEN 1 3571 /* enum: Enable PTP packet timestamping operation. */ 3572 #define MC_CMD_PTP_OP_ENABLE 0x1 3573 /* enum: Disable PTP packet timestamping operation. */ 3574 #define MC_CMD_PTP_OP_DISABLE 0x2 3575 /* enum: Send a PTP packet. */ 3576 #define MC_CMD_PTP_OP_TRANSMIT 0x3 3577 /* enum: Read the current NIC time. */ 3578 #define MC_CMD_PTP_OP_READ_NIC_TIME 0x4 3579 /* enum: Get the current PTP status. */ 3580 #define MC_CMD_PTP_OP_STATUS 0x5 3581 /* enum: Adjust the PTP NIC's time. */ 3582 #define MC_CMD_PTP_OP_ADJUST 0x6 3583 /* enum: Synchronize host and NIC time. */ 3584 #define MC_CMD_PTP_OP_SYNCHRONIZE 0x7 3585 /* enum: Basic manufacturing tests. */ 3586 #define MC_CMD_PTP_OP_MANFTEST_BASIC 0x8 3587 /* enum: Packet based manufacturing tests. */ 3588 #define MC_CMD_PTP_OP_MANFTEST_PACKET 0x9 3589 /* enum: Reset some of the PTP related statistics */ 3590 #define MC_CMD_PTP_OP_RESET_STATS 0xa 3591 /* enum: Debug operations to MC. */ 3592 #define MC_CMD_PTP_OP_DEBUG 0xb 3593 /* enum: Read an FPGA register */ 3594 #define MC_CMD_PTP_OP_FPGAREAD 0xc 3595 /* enum: Write an FPGA register */ 3596 #define MC_CMD_PTP_OP_FPGAWRITE 0xd 3597 /* enum: Apply an offset to the NIC clock */ 3598 #define MC_CMD_PTP_OP_CLOCK_OFFSET_ADJUST 0xe 3599 /* enum: Change Apply an offset to the NIC clock */ 3600 #define MC_CMD_PTP_OP_CLOCK_FREQ_ADJUST 0xf 3601 /* enum: Set the MC packet filter VLAN tags for received PTP packets */ 3602 #define MC_CMD_PTP_OP_RX_SET_VLAN_FILTER 0x10 3603 /* enum: Set the MC packet filter UUID for received PTP packets */ 3604 #define MC_CMD_PTP_OP_RX_SET_UUID_FILTER 0x11 3605 /* enum: Set the MC packet filter Domain for received PTP packets */ 3606 #define MC_CMD_PTP_OP_RX_SET_DOMAIN_FILTER 0x12 3607 /* enum: Set the clock source */ 3608 #define MC_CMD_PTP_OP_SET_CLK_SRC 0x13 3609 /* enum: Reset value of Timer Reg. */ 3610 #define MC_CMD_PTP_OP_RST_CLK 0x14 3611 /* enum: Enable the forwarding of PPS events to the host */ 3612 #define MC_CMD_PTP_OP_PPS_ENABLE 0x15 3613 /* enum: Get the time format used by this NIC for PTP operations */ 3614 #define MC_CMD_PTP_OP_GET_TIME_FORMAT 0x16 3615 /* enum: Get the clock attributes. NOTE- extended version of 3616 * MC_CMD_PTP_OP_GET_TIME_FORMAT 3617 */ 3618 #define MC_CMD_PTP_OP_GET_ATTRIBUTES 0x16 3619 /* enum: Get corrections that should be applied to the various different 3620 * timestamps 3621 */ 3622 #define MC_CMD_PTP_OP_GET_TIMESTAMP_CORRECTIONS 0x17 3623 /* enum: Subscribe to receive periodic time events indicating the current NIC 3624 * time 3625 */ 3626 #define MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE 0x18 3627 /* enum: Unsubscribe to stop receiving time events */ 3628 #define MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE 0x19 3629 /* enum: PPS based manfacturing tests. Requires PPS output to be looped to PPS 3630 * input on the same NIC. 3631 */ 3632 #define MC_CMD_PTP_OP_MANFTEST_PPS 0x1a 3633 /* enum: Set the PTP sync status. Status is used by firmware to report to event 3634 * subscribers. 3635 */ 3636 #define MC_CMD_PTP_OP_SET_SYNC_STATUS 0x1b 3637 /* enum: Above this for future use. */ 3638 #define MC_CMD_PTP_OP_MAX 0x1c 3639 3640 /* MC_CMD_PTP_IN_ENABLE msgrequest */ 3641 #define MC_CMD_PTP_IN_ENABLE_LEN 16 3642 #define MC_CMD_PTP_IN_CMD_OFST 0 3643 #define MC_CMD_PTP_IN_PERIPH_ID_OFST 4 3644 /* Event queue for PTP events */ 3645 #define MC_CMD_PTP_IN_ENABLE_QUEUE_OFST 8 3646 /* PTP timestamping mode */ 3647 #define MC_CMD_PTP_IN_ENABLE_MODE_OFST 12 3648 /* enum: PTP, version 1 */ 3649 #define MC_CMD_PTP_MODE_V1 0x0 3650 /* enum: PTP, version 1, with VLAN headers - deprecated */ 3651 #define MC_CMD_PTP_MODE_V1_VLAN 0x1 3652 /* enum: PTP, version 2 */ 3653 #define MC_CMD_PTP_MODE_V2 0x2 3654 /* enum: PTP, version 2, with VLAN headers - deprecated */ 3655 #define MC_CMD_PTP_MODE_V2_VLAN 0x3 3656 /* enum: PTP, version 2, with improved UUID filtering */ 3657 #define MC_CMD_PTP_MODE_V2_ENHANCED 0x4 3658 /* enum: FCoE (seconds and microseconds) */ 3659 #define MC_CMD_PTP_MODE_FCOE 0x5 3660 3661 /* MC_CMD_PTP_IN_DISABLE msgrequest */ 3662 #define MC_CMD_PTP_IN_DISABLE_LEN 8 3663 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3664 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3665 3666 /* MC_CMD_PTP_IN_TRANSMIT msgrequest */ 3667 #define MC_CMD_PTP_IN_TRANSMIT_LENMIN 13 3668 #define MC_CMD_PTP_IN_TRANSMIT_LENMAX 252 3669 #define MC_CMD_PTP_IN_TRANSMIT_LEN(num) (12+1*(num)) 3670 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3671 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3672 /* Transmit packet length */ 3673 #define MC_CMD_PTP_IN_TRANSMIT_LENGTH_OFST 8 3674 /* Transmit packet data */ 3675 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_OFST 12 3676 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_LEN 1 3677 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_MINNUM 1 3678 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_MAXNUM 240 3679 3680 /* MC_CMD_PTP_IN_READ_NIC_TIME msgrequest */ 3681 #define MC_CMD_PTP_IN_READ_NIC_TIME_LEN 8 3682 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3683 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3684 3685 /* MC_CMD_PTP_IN_STATUS msgrequest */ 3686 #define MC_CMD_PTP_IN_STATUS_LEN 8 3687 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3688 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3689 3690 /* MC_CMD_PTP_IN_ADJUST msgrequest */ 3691 #define MC_CMD_PTP_IN_ADJUST_LEN 24 3692 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3693 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3694 /* Frequency adjustment 40 bit fixed point ns */ 3695 #define MC_CMD_PTP_IN_ADJUST_FREQ_OFST 8 3696 #define MC_CMD_PTP_IN_ADJUST_FREQ_LEN 8 3697 #define MC_CMD_PTP_IN_ADJUST_FREQ_LO_OFST 8 3698 #define MC_CMD_PTP_IN_ADJUST_FREQ_HI_OFST 12 3699 /* enum: Number of fractional bits in frequency adjustment */ 3700 #define MC_CMD_PTP_IN_ADJUST_BITS 0x28 3701 /* Time adjustment in seconds */ 3702 #define MC_CMD_PTP_IN_ADJUST_SECONDS_OFST 16 3703 /* Time adjustment major value */ 3704 #define MC_CMD_PTP_IN_ADJUST_MAJOR_OFST 16 3705 /* Time adjustment in nanoseconds */ 3706 #define MC_CMD_PTP_IN_ADJUST_NANOSECONDS_OFST 20 3707 /* Time adjustment minor value */ 3708 #define MC_CMD_PTP_IN_ADJUST_MINOR_OFST 20 3709 3710 /* MC_CMD_PTP_IN_SYNCHRONIZE msgrequest */ 3711 #define MC_CMD_PTP_IN_SYNCHRONIZE_LEN 20 3712 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3713 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3714 /* Number of time readings to capture */ 3715 #define MC_CMD_PTP_IN_SYNCHRONIZE_NUMTIMESETS_OFST 8 3716 /* Host address in which to write "synchronization started" indication (64 3717 * bits) 3718 */ 3719 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_OFST 12 3720 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LEN 8 3721 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LO_OFST 12 3722 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_HI_OFST 16 3723 3724 /* MC_CMD_PTP_IN_MANFTEST_BASIC msgrequest */ 3725 #define MC_CMD_PTP_IN_MANFTEST_BASIC_LEN 8 3726 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3727 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3728 3729 /* MC_CMD_PTP_IN_MANFTEST_PACKET msgrequest */ 3730 #define MC_CMD_PTP_IN_MANFTEST_PACKET_LEN 12 3731 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3732 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3733 /* Enable or disable packet testing */ 3734 #define MC_CMD_PTP_IN_MANFTEST_PACKET_TEST_ENABLE_OFST 8 3735 3736 /* MC_CMD_PTP_IN_RESET_STATS msgrequest */ 3737 #define MC_CMD_PTP_IN_RESET_STATS_LEN 8 3738 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3739 /* Reset PTP statistics */ 3740 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3741 3742 /* MC_CMD_PTP_IN_DEBUG msgrequest */ 3743 #define MC_CMD_PTP_IN_DEBUG_LEN 12 3744 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3745 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3746 /* Debug operations */ 3747 #define MC_CMD_PTP_IN_DEBUG_DEBUG_PARAM_OFST 8 3748 3749 /* MC_CMD_PTP_IN_FPGAREAD msgrequest */ 3750 #define MC_CMD_PTP_IN_FPGAREAD_LEN 16 3751 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3752 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3753 #define MC_CMD_PTP_IN_FPGAREAD_ADDR_OFST 8 3754 #define MC_CMD_PTP_IN_FPGAREAD_NUMBYTES_OFST 12 3755 3756 /* MC_CMD_PTP_IN_FPGAWRITE msgrequest */ 3757 #define MC_CMD_PTP_IN_FPGAWRITE_LENMIN 13 3758 #define MC_CMD_PTP_IN_FPGAWRITE_LENMAX 252 3759 #define MC_CMD_PTP_IN_FPGAWRITE_LEN(num) (12+1*(num)) 3760 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3761 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3762 #define MC_CMD_PTP_IN_FPGAWRITE_ADDR_OFST 8 3763 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_OFST 12 3764 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_LEN 1 3765 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MINNUM 1 3766 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MAXNUM 240 3767 3768 /* MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST msgrequest */ 3769 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_LEN 16 3770 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3771 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3772 /* Time adjustment in seconds */ 3773 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_SECONDS_OFST 8 3774 /* Time adjustment major value */ 3775 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MAJOR_OFST 8 3776 /* Time adjustment in nanoseconds */ 3777 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_NANOSECONDS_OFST 12 3778 /* Time adjustment minor value */ 3779 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MINOR_OFST 12 3780 3781 /* MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST msgrequest */ 3782 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_LEN 16 3783 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3784 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3785 /* Frequency adjustment 40 bit fixed point ns */ 3786 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_OFST 8 3787 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LEN 8 3788 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LO_OFST 8 3789 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_HI_OFST 12 3790 /* enum: Number of fractional bits in frequency adjustment */ 3791 /* MC_CMD_PTP_IN_ADJUST_BITS 0x28 */ 3792 3793 /* MC_CMD_PTP_IN_RX_SET_VLAN_FILTER msgrequest */ 3794 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_LEN 24 3795 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3796 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3797 /* Number of VLAN tags, 0 if not VLAN */ 3798 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_NUM_VLAN_TAGS_OFST 8 3799 /* Set of VLAN tags to filter against */ 3800 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_OFST 12 3801 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_LEN 4 3802 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_NUM 3 3803 3804 /* MC_CMD_PTP_IN_RX_SET_UUID_FILTER msgrequest */ 3805 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_LEN 20 3806 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3807 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3808 /* 1 to enable UUID filtering, 0 to disable */ 3809 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_ENABLE_OFST 8 3810 /* UUID to filter against */ 3811 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_OFST 12 3812 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LEN 8 3813 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LO_OFST 12 3814 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_HI_OFST 16 3815 3816 /* MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER msgrequest */ 3817 #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_LEN 16 3818 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3819 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3820 /* 1 to enable Domain filtering, 0 to disable */ 3821 #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_ENABLE_OFST 8 3822 /* Domain number to filter against */ 3823 #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_DOMAIN_OFST 12 3824 3825 /* MC_CMD_PTP_IN_SET_CLK_SRC msgrequest */ 3826 #define MC_CMD_PTP_IN_SET_CLK_SRC_LEN 12 3827 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3828 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3829 /* Set the clock source. */ 3830 #define MC_CMD_PTP_IN_SET_CLK_SRC_CLK_OFST 8 3831 /* enum: Internal. */ 3832 #define MC_CMD_PTP_CLK_SRC_INTERNAL 0x0 3833 /* enum: External. */ 3834 #define MC_CMD_PTP_CLK_SRC_EXTERNAL 0x1 3835 3836 /* MC_CMD_PTP_IN_RST_CLK msgrequest */ 3837 #define MC_CMD_PTP_IN_RST_CLK_LEN 8 3838 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3839 /* Reset value of Timer Reg. */ 3840 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3841 3842 /* MC_CMD_PTP_IN_PPS_ENABLE msgrequest */ 3843 #define MC_CMD_PTP_IN_PPS_ENABLE_LEN 12 3844 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3845 /* Enable or disable */ 3846 #define MC_CMD_PTP_IN_PPS_ENABLE_OP_OFST 4 3847 /* enum: Enable */ 3848 #define MC_CMD_PTP_ENABLE_PPS 0x0 3849 /* enum: Disable */ 3850 #define MC_CMD_PTP_DISABLE_PPS 0x1 3851 /* Queue id to send events back */ 3852 #define MC_CMD_PTP_IN_PPS_ENABLE_QUEUE_ID_OFST 8 3853 3854 /* MC_CMD_PTP_IN_GET_TIME_FORMAT msgrequest */ 3855 #define MC_CMD_PTP_IN_GET_TIME_FORMAT_LEN 8 3856 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3857 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3858 3859 /* MC_CMD_PTP_IN_GET_ATTRIBUTES msgrequest */ 3860 #define MC_CMD_PTP_IN_GET_ATTRIBUTES_LEN 8 3861 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3862 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3863 3864 /* MC_CMD_PTP_IN_GET_TIMESTAMP_CORRECTIONS msgrequest */ 3865 #define MC_CMD_PTP_IN_GET_TIMESTAMP_CORRECTIONS_LEN 8 3866 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3867 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3868 3869 /* MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE msgrequest */ 3870 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN 12 3871 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3872 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3873 /* Original field containing queue ID. Now extended to include flags. */ 3874 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_OFST 8 3875 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_LBN 0 3876 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_WIDTH 16 3877 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_REPORT_SYNC_STATUS_LBN 31 3878 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_REPORT_SYNC_STATUS_WIDTH 1 3879 3880 /* MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE msgrequest */ 3881 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN 16 3882 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3883 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3884 /* Unsubscribe options */ 3885 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL_OFST 8 3886 /* enum: Unsubscribe a single queue */ 3887 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE 0x0 3888 /* enum: Unsubscribe all queues */ 3889 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_ALL 0x1 3890 /* Event queue ID */ 3891 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE_OFST 12 3892 3893 /* MC_CMD_PTP_IN_MANFTEST_PPS msgrequest */ 3894 #define MC_CMD_PTP_IN_MANFTEST_PPS_LEN 12 3895 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3896 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3897 /* 1 to enable PPS test mode, 0 to disable and return result. */ 3898 #define MC_CMD_PTP_IN_MANFTEST_PPS_TEST_ENABLE_OFST 8 3899 3900 /* MC_CMD_PTP_IN_SET_SYNC_STATUS msgrequest */ 3901 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_LEN 24 3902 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3903 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3904 /* NIC - Host System Clock Synchronization status */ 3905 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_STATUS_OFST 8 3906 /* enum: Host System clock and NIC clock are not in sync */ 3907 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_NOT_IN_SYNC 0x0 3908 /* enum: Host System clock and NIC clock are synchronized */ 3909 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_IN_SYNC 0x1 3910 /* If synchronized, number of seconds until clocks should be considered to be 3911 * no longer in sync. 3912 */ 3913 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_TIMEOUT_OFST 12 3914 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED0_OFST 16 3915 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED1_OFST 20 3916 3917 /* MC_CMD_PTP_OUT msgresponse */ 3918 #define MC_CMD_PTP_OUT_LEN 0 3919 3920 /* MC_CMD_PTP_OUT_TRANSMIT msgresponse */ 3921 #define MC_CMD_PTP_OUT_TRANSMIT_LEN 8 3922 /* Value of seconds timestamp */ 3923 #define MC_CMD_PTP_OUT_TRANSMIT_SECONDS_OFST 0 3924 /* Timestamp major value */ 3925 #define MC_CMD_PTP_OUT_TRANSMIT_MAJOR_OFST 0 3926 /* Value of nanoseconds timestamp */ 3927 #define MC_CMD_PTP_OUT_TRANSMIT_NANOSECONDS_OFST 4 3928 /* Timestamp minor value */ 3929 #define MC_CMD_PTP_OUT_TRANSMIT_MINOR_OFST 4 3930 3931 /* MC_CMD_PTP_OUT_TIME_EVENT_SUBSCRIBE msgresponse */ 3932 #define MC_CMD_PTP_OUT_TIME_EVENT_SUBSCRIBE_LEN 0 3933 3934 /* MC_CMD_PTP_OUT_TIME_EVENT_UNSUBSCRIBE msgresponse */ 3935 #define MC_CMD_PTP_OUT_TIME_EVENT_UNSUBSCRIBE_LEN 0 3936 3937 /* MC_CMD_PTP_OUT_READ_NIC_TIME msgresponse */ 3938 #define MC_CMD_PTP_OUT_READ_NIC_TIME_LEN 8 3939 /* Value of seconds timestamp */ 3940 #define MC_CMD_PTP_OUT_READ_NIC_TIME_SECONDS_OFST 0 3941 /* Timestamp major value */ 3942 #define MC_CMD_PTP_OUT_READ_NIC_TIME_MAJOR_OFST 0 3943 /* Value of nanoseconds timestamp */ 3944 #define MC_CMD_PTP_OUT_READ_NIC_TIME_NANOSECONDS_OFST 4 3945 /* Timestamp minor value */ 3946 #define MC_CMD_PTP_OUT_READ_NIC_TIME_MINOR_OFST 4 3947 3948 /* MC_CMD_PTP_OUT_STATUS msgresponse */ 3949 #define MC_CMD_PTP_OUT_STATUS_LEN 64 3950 /* Frequency of NIC's hardware clock */ 3951 #define MC_CMD_PTP_OUT_STATUS_CLOCK_FREQ_OFST 0 3952 /* Number of packets transmitted and timestamped */ 3953 #define MC_CMD_PTP_OUT_STATUS_STATS_TX_OFST 4 3954 /* Number of packets received and timestamped */ 3955 #define MC_CMD_PTP_OUT_STATUS_STATS_RX_OFST 8 3956 /* Number of packets timestamped by the FPGA */ 3957 #define MC_CMD_PTP_OUT_STATUS_STATS_TS_OFST 12 3958 /* Number of packets filter matched */ 3959 #define MC_CMD_PTP_OUT_STATUS_STATS_FM_OFST 16 3960 /* Number of packets not filter matched */ 3961 #define MC_CMD_PTP_OUT_STATUS_STATS_NFM_OFST 20 3962 /* Number of PPS overflows (noise on input?) */ 3963 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFLOW_OFST 24 3964 /* Number of PPS bad periods */ 3965 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_BAD_OFST 28 3966 /* Minimum period of PPS pulse in nanoseconds */ 3967 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MIN_OFST 32 3968 /* Maximum period of PPS pulse in nanoseconds */ 3969 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MAX_OFST 36 3970 /* Last period of PPS pulse in nanoseconds */ 3971 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_LAST_OFST 40 3972 /* Mean period of PPS pulse in nanoseconds */ 3973 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MEAN_OFST 44 3974 /* Minimum offset of PPS pulse in nanoseconds (signed) */ 3975 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MIN_OFST 48 3976 /* Maximum offset of PPS pulse in nanoseconds (signed) */ 3977 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MAX_OFST 52 3978 /* Last offset of PPS pulse in nanoseconds (signed) */ 3979 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_LAST_OFST 56 3980 /* Mean offset of PPS pulse in nanoseconds (signed) */ 3981 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MEAN_OFST 60 3982 3983 /* MC_CMD_PTP_OUT_SYNCHRONIZE msgresponse */ 3984 #define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMIN 20 3985 #define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMAX 240 3986 #define MC_CMD_PTP_OUT_SYNCHRONIZE_LEN(num) (0+20*(num)) 3987 /* A set of host and NIC times */ 3988 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_OFST 0 3989 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_LEN 20 3990 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MINNUM 1 3991 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MAXNUM 12 3992 /* Host time immediately before NIC's hardware clock read */ 3993 #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTSTART_OFST 0 3994 /* Value of seconds timestamp */ 3995 #define MC_CMD_PTP_OUT_SYNCHRONIZE_SECONDS_OFST 4 3996 /* Timestamp major value */ 3997 #define MC_CMD_PTP_OUT_SYNCHRONIZE_MAJOR_OFST 4 3998 /* Value of nanoseconds timestamp */ 3999 #define MC_CMD_PTP_OUT_SYNCHRONIZE_NANOSECONDS_OFST 8 4000 /* Timestamp minor value */ 4001 #define MC_CMD_PTP_OUT_SYNCHRONIZE_MINOR_OFST 8 4002 /* Host time immediately after NIC's hardware clock read */ 4003 #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTEND_OFST 12 4004 /* Number of nanoseconds waited after reading NIC's hardware clock */ 4005 #define MC_CMD_PTP_OUT_SYNCHRONIZE_WAITNS_OFST 16 4006 4007 /* MC_CMD_PTP_OUT_MANFTEST_BASIC msgresponse */ 4008 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_LEN 8 4009 /* Results of testing */ 4010 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_RESULT_OFST 0 4011 /* enum: Successful test */ 4012 #define MC_CMD_PTP_MANF_SUCCESS 0x0 4013 /* enum: FPGA load failed */ 4014 #define MC_CMD_PTP_MANF_FPGA_LOAD 0x1 4015 /* enum: FPGA version invalid */ 4016 #define MC_CMD_PTP_MANF_FPGA_VERSION 0x2 4017 /* enum: FPGA registers incorrect */ 4018 #define MC_CMD_PTP_MANF_FPGA_REGISTERS 0x3 4019 /* enum: Oscillator possibly not working? */ 4020 #define MC_CMD_PTP_MANF_OSCILLATOR 0x4 4021 /* enum: Timestamps not increasing */ 4022 #define MC_CMD_PTP_MANF_TIMESTAMPS 0x5 4023 /* enum: Mismatched packet count */ 4024 #define MC_CMD_PTP_MANF_PACKET_COUNT 0x6 4025 /* enum: Mismatched packet count (Siena filter and FPGA) */ 4026 #define MC_CMD_PTP_MANF_FILTER_COUNT 0x7 4027 /* enum: Not enough packets to perform timestamp check */ 4028 #define MC_CMD_PTP_MANF_PACKET_ENOUGH 0x8 4029 /* enum: Timestamp trigger GPIO not working */ 4030 #define MC_CMD_PTP_MANF_GPIO_TRIGGER 0x9 4031 /* enum: Insufficient PPS events to perform checks */ 4032 #define MC_CMD_PTP_MANF_PPS_ENOUGH 0xa 4033 /* enum: PPS time event period not sufficiently close to 1s. */ 4034 #define MC_CMD_PTP_MANF_PPS_PERIOD 0xb 4035 /* enum: PPS time event nS reading not sufficiently close to zero. */ 4036 #define MC_CMD_PTP_MANF_PPS_NS 0xc 4037 /* enum: PTP peripheral registers incorrect */ 4038 #define MC_CMD_PTP_MANF_REGISTERS 0xd 4039 /* enum: Failed to read time from PTP peripheral */ 4040 #define MC_CMD_PTP_MANF_CLOCK_READ 0xe 4041 /* Presence of external oscillator */ 4042 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_EXTOSC_OFST 4 4043 4044 /* MC_CMD_PTP_OUT_MANFTEST_PACKET msgresponse */ 4045 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_LEN 12 4046 /* Results of testing */ 4047 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_RESULT_OFST 0 4048 /* Number of packets received by FPGA */ 4049 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FPGACOUNT_OFST 4 4050 /* Number of packets received by Siena filters */ 4051 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FILTERCOUNT_OFST 8 4052 4053 /* MC_CMD_PTP_OUT_FPGAREAD msgresponse */ 4054 #define MC_CMD_PTP_OUT_FPGAREAD_LENMIN 1 4055 #define MC_CMD_PTP_OUT_FPGAREAD_LENMAX 252 4056 #define MC_CMD_PTP_OUT_FPGAREAD_LEN(num) (0+1*(num)) 4057 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_OFST 0 4058 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_LEN 1 4059 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MINNUM 1 4060 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MAXNUM 252 4061 4062 /* MC_CMD_PTP_OUT_GET_TIME_FORMAT msgresponse */ 4063 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_LEN 4 4064 /* Time format required/used by for this NIC. Applies to all PTP MCDI 4065 * operations that pass times between the host and firmware. If this operation 4066 * is not supported (older firmware) a format of seconds and nanoseconds should 4067 * be assumed. 4068 */ 4069 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_FORMAT_OFST 0 4070 /* enum: Times are in seconds and nanoseconds */ 4071 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_NANOSECONDS 0x0 4072 /* enum: Major register has units of 16 second per tick, minor 8 ns per tick */ 4073 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_16SECONDS_8NANOSECONDS 0x1 4074 /* enum: Major register has units of seconds, minor 2^-27s per tick */ 4075 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_27FRACTION 0x2 4076 4077 /* MC_CMD_PTP_OUT_GET_ATTRIBUTES msgresponse */ 4078 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_LEN 24 4079 /* Time format required/used by for this NIC. Applies to all PTP MCDI 4080 * operations that pass times between the host and firmware. If this operation 4081 * is not supported (older firmware) a format of seconds and nanoseconds should 4082 * be assumed. 4083 */ 4084 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_TIME_FORMAT_OFST 0 4085 /* enum: Times are in seconds and nanoseconds */ 4086 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_NANOSECONDS 0x0 4087 /* enum: Major register has units of 16 second per tick, minor 8 ns per tick */ 4088 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_16SECONDS_8NANOSECONDS 0x1 4089 /* enum: Major register has units of seconds, minor 2^-27s per tick */ 4090 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_27FRACTION 0x2 4091 /* Minimum acceptable value for a corrected synchronization timeset. When 4092 * comparing host and NIC clock times, the MC returns a set of samples that 4093 * contain the host start and end time, the MC time when the host start was 4094 * detected and the time the MC waited between reading the time and detecting 4095 * the host end. The corrected sync window is the difference between the host 4096 * end and start times minus the time that the MC waited for host end. 4097 */ 4098 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SYNC_WINDOW_MIN_OFST 4 4099 /* Various PTP capabilities */ 4100 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_CAPABILITIES_OFST 8 4101 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_LBN 0 4102 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_WIDTH 1 4103 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED0_OFST 12 4104 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED1_OFST 16 4105 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED2_OFST 20 4106 4107 /* MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS msgresponse */ 4108 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_LEN 16 4109 /* Uncorrected error on PTP transmit timestamps in NIC clock format */ 4110 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_TRANSMIT_OFST 0 4111 /* Uncorrected error on PTP receive timestamps in NIC clock format */ 4112 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_RECEIVE_OFST 4 4113 /* Uncorrected error on PPS output in NIC clock format */ 4114 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_OUT_OFST 8 4115 /* Uncorrected error on PPS input in NIC clock format */ 4116 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_IN_OFST 12 4117 4118 /* MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2 msgresponse */ 4119 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_LEN 24 4120 /* Uncorrected error on PTP transmit timestamps in NIC clock format */ 4121 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_TX_OFST 0 4122 /* Uncorrected error on PTP receive timestamps in NIC clock format */ 4123 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_RX_OFST 4 4124 /* Uncorrected error on PPS output in NIC clock format */ 4125 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_OUT_OFST 8 4126 /* Uncorrected error on PPS input in NIC clock format */ 4127 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_IN_OFST 12 4128 /* Uncorrected error on non-PTP transmit timestamps in NIC clock format */ 4129 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_TX_OFST 16 4130 /* Uncorrected error on non-PTP receive timestamps in NIC clock format */ 4131 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_RX_OFST 20 4132 4133 /* MC_CMD_PTP_OUT_MANFTEST_PPS msgresponse */ 4134 #define MC_CMD_PTP_OUT_MANFTEST_PPS_LEN 4 4135 /* Results of testing */ 4136 #define MC_CMD_PTP_OUT_MANFTEST_PPS_TEST_RESULT_OFST 0 4137 /* Enum values, see field(s): */ 4138 /* MC_CMD_PTP_OUT_MANFTEST_BASIC/TEST_RESULT */ 4139 4140 /* MC_CMD_PTP_OUT_SET_SYNC_STATUS msgresponse */ 4141 #define MC_CMD_PTP_OUT_SET_SYNC_STATUS_LEN 0 4142 4143 4144 /***********************************/ 4145 /* MC_CMD_CSR_READ32 4146 * Read 32bit words from the indirect memory map. 4147 */ 4148 #define MC_CMD_CSR_READ32 0xc 4149 #undef MC_CMD_0xc_PRIVILEGE_CTG 4150 4151 #define MC_CMD_0xc_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4152 4153 /* MC_CMD_CSR_READ32_IN msgrequest */ 4154 #define MC_CMD_CSR_READ32_IN_LEN 12 4155 /* Address */ 4156 #define MC_CMD_CSR_READ32_IN_ADDR_OFST 0 4157 #define MC_CMD_CSR_READ32_IN_STEP_OFST 4 4158 #define MC_CMD_CSR_READ32_IN_NUMWORDS_OFST 8 4159 4160 /* MC_CMD_CSR_READ32_OUT msgresponse */ 4161 #define MC_CMD_CSR_READ32_OUT_LENMIN 4 4162 #define MC_CMD_CSR_READ32_OUT_LENMAX 252 4163 #define MC_CMD_CSR_READ32_OUT_LEN(num) (0+4*(num)) 4164 /* The last dword is the status, not a value read */ 4165 #define MC_CMD_CSR_READ32_OUT_BUFFER_OFST 0 4166 #define MC_CMD_CSR_READ32_OUT_BUFFER_LEN 4 4167 #define MC_CMD_CSR_READ32_OUT_BUFFER_MINNUM 1 4168 #define MC_CMD_CSR_READ32_OUT_BUFFER_MAXNUM 63 4169 4170 4171 /***********************************/ 4172 /* MC_CMD_CSR_WRITE32 4173 * Write 32bit dwords to the indirect memory map. 4174 */ 4175 #define MC_CMD_CSR_WRITE32 0xd 4176 #undef MC_CMD_0xd_PRIVILEGE_CTG 4177 4178 #define MC_CMD_0xd_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4179 4180 /* MC_CMD_CSR_WRITE32_IN msgrequest */ 4181 #define MC_CMD_CSR_WRITE32_IN_LENMIN 12 4182 #define MC_CMD_CSR_WRITE32_IN_LENMAX 252 4183 #define MC_CMD_CSR_WRITE32_IN_LEN(num) (8+4*(num)) 4184 /* Address */ 4185 #define MC_CMD_CSR_WRITE32_IN_ADDR_OFST 0 4186 #define MC_CMD_CSR_WRITE32_IN_STEP_OFST 4 4187 #define MC_CMD_CSR_WRITE32_IN_BUFFER_OFST 8 4188 #define MC_CMD_CSR_WRITE32_IN_BUFFER_LEN 4 4189 #define MC_CMD_CSR_WRITE32_IN_BUFFER_MINNUM 1 4190 #define MC_CMD_CSR_WRITE32_IN_BUFFER_MAXNUM 61 4191 4192 /* MC_CMD_CSR_WRITE32_OUT msgresponse */ 4193 #define MC_CMD_CSR_WRITE32_OUT_LEN 4 4194 #define MC_CMD_CSR_WRITE32_OUT_STATUS_OFST 0 4195 4196 4197 /***********************************/ 4198 /* MC_CMD_HP 4199 * These commands are used for HP related features. They are grouped under one 4200 * MCDI command to avoid creating too many MCDI commands. 4201 */ 4202 #define MC_CMD_HP 0x54 4203 #undef MC_CMD_0x54_PRIVILEGE_CTG 4204 4205 #define MC_CMD_0x54_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4206 4207 /* MC_CMD_HP_IN msgrequest */ 4208 #define MC_CMD_HP_IN_LEN 16 4209 /* HP OCSD sub-command. When address is not NULL, request activation of OCSD at 4210 * the specified address with the specified interval.When address is NULL, 4211 * INTERVAL is interpreted as a command: 0: stop OCSD / 1: Report OCSD current 4212 * state / 2: (debug) Show temperature reported by one of the supported 4213 * sensors. 4214 */ 4215 #define MC_CMD_HP_IN_SUBCMD_OFST 0 4216 /* enum: OCSD (Option Card Sensor Data) sub-command. */ 4217 #define MC_CMD_HP_IN_OCSD_SUBCMD 0x0 4218 /* enum: Last known valid HP sub-command. */ 4219 #define MC_CMD_HP_IN_LAST_SUBCMD 0x0 4220 /* The address to the array of sensor fields. (Or NULL to use a sub-command.) 4221 */ 4222 #define MC_CMD_HP_IN_OCSD_ADDR_OFST 4 4223 #define MC_CMD_HP_IN_OCSD_ADDR_LEN 8 4224 #define MC_CMD_HP_IN_OCSD_ADDR_LO_OFST 4 4225 #define MC_CMD_HP_IN_OCSD_ADDR_HI_OFST 8 4226 /* The requested update interval, in seconds. (Or the sub-command if ADDR is 4227 * NULL.) 4228 */ 4229 #define MC_CMD_HP_IN_OCSD_INTERVAL_OFST 12 4230 4231 /* MC_CMD_HP_OUT msgresponse */ 4232 #define MC_CMD_HP_OUT_LEN 4 4233 #define MC_CMD_HP_OUT_OCSD_STATUS_OFST 0 4234 /* enum: OCSD stopped for this card. */ 4235 #define MC_CMD_HP_OUT_OCSD_STOPPED 0x1 4236 /* enum: OCSD was successfully started with the address provided. */ 4237 #define MC_CMD_HP_OUT_OCSD_STARTED 0x2 4238 /* enum: OCSD was already started for this card. */ 4239 #define MC_CMD_HP_OUT_OCSD_ALREADY_STARTED 0x3 4240 4241 4242 /***********************************/ 4243 /* MC_CMD_STACKINFO 4244 * Get stack information. 4245 */ 4246 #define MC_CMD_STACKINFO 0xf 4247 #undef MC_CMD_0xf_PRIVILEGE_CTG 4248 4249 #define MC_CMD_0xf_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4250 4251 /* MC_CMD_STACKINFO_IN msgrequest */ 4252 #define MC_CMD_STACKINFO_IN_LEN 0 4253 4254 /* MC_CMD_STACKINFO_OUT msgresponse */ 4255 #define MC_CMD_STACKINFO_OUT_LENMIN 12 4256 #define MC_CMD_STACKINFO_OUT_LENMAX 252 4257 #define MC_CMD_STACKINFO_OUT_LEN(num) (0+12*(num)) 4258 /* (thread ptr, stack size, free space) for each thread in system */ 4259 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_OFST 0 4260 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_LEN 12 4261 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_MINNUM 1 4262 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_MAXNUM 21 4263 4264 4265 /***********************************/ 4266 /* MC_CMD_MDIO_READ 4267 * MDIO register read. 4268 */ 4269 #define MC_CMD_MDIO_READ 0x10 4270 #undef MC_CMD_0x10_PRIVILEGE_CTG 4271 4272 #define MC_CMD_0x10_PRIVILEGE_CTG SRIOV_CTG_GENERAL 4273 4274 /* MC_CMD_MDIO_READ_IN msgrequest */ 4275 #define MC_CMD_MDIO_READ_IN_LEN 16 4276 /* Bus number; there are two MDIO buses: one for the internal PHY, and one for 4277 * external devices. 4278 */ 4279 #define MC_CMD_MDIO_READ_IN_BUS_OFST 0 4280 /* enum: Internal. */ 4281 #define MC_CMD_MDIO_BUS_INTERNAL 0x0 4282 /* enum: External. */ 4283 #define MC_CMD_MDIO_BUS_EXTERNAL 0x1 4284 /* Port address */ 4285 #define MC_CMD_MDIO_READ_IN_PRTAD_OFST 4 4286 /* Device Address or clause 22. */ 4287 #define MC_CMD_MDIO_READ_IN_DEVAD_OFST 8 4288 /* enum: By default all the MCDI MDIO operations perform clause45 mode. If you 4289 * want to use clause22 then set DEVAD = MC_CMD_MDIO_CLAUSE22. 4290 */ 4291 #define MC_CMD_MDIO_CLAUSE22 0x20 4292 /* Address */ 4293 #define MC_CMD_MDIO_READ_IN_ADDR_OFST 12 4294 4295 /* MC_CMD_MDIO_READ_OUT msgresponse */ 4296 #define MC_CMD_MDIO_READ_OUT_LEN 8 4297 /* Value */ 4298 #define MC_CMD_MDIO_READ_OUT_VALUE_OFST 0 4299 /* Status the MDIO commands return the raw status bits from the MDIO block. A 4300 * "good" transaction should have the DONE bit set and all other bits clear. 4301 */ 4302 #define MC_CMD_MDIO_READ_OUT_STATUS_OFST 4 4303 /* enum: Good. */ 4304 #define MC_CMD_MDIO_STATUS_GOOD 0x8 4305 4306 4307 /***********************************/ 4308 /* MC_CMD_MDIO_WRITE 4309 * MDIO register write. 4310 */ 4311 #define MC_CMD_MDIO_WRITE 0x11 4312 #undef MC_CMD_0x11_PRIVILEGE_CTG 4313 4314 #define MC_CMD_0x11_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4315 4316 /* MC_CMD_MDIO_WRITE_IN msgrequest */ 4317 #define MC_CMD_MDIO_WRITE_IN_LEN 20 4318 /* Bus number; there are two MDIO buses: one for the internal PHY, and one for 4319 * external devices. 4320 */ 4321 #define MC_CMD_MDIO_WRITE_IN_BUS_OFST 0 4322 /* enum: Internal. */ 4323 /* MC_CMD_MDIO_BUS_INTERNAL 0x0 */ 4324 /* enum: External. */ 4325 /* MC_CMD_MDIO_BUS_EXTERNAL 0x1 */ 4326 /* Port address */ 4327 #define MC_CMD_MDIO_WRITE_IN_PRTAD_OFST 4 4328 /* Device Address or clause 22. */ 4329 #define MC_CMD_MDIO_WRITE_IN_DEVAD_OFST 8 4330 /* enum: By default all the MCDI MDIO operations perform clause45 mode. If you 4331 * want to use clause22 then set DEVAD = MC_CMD_MDIO_CLAUSE22. 4332 */ 4333 /* MC_CMD_MDIO_CLAUSE22 0x20 */ 4334 /* Address */ 4335 #define MC_CMD_MDIO_WRITE_IN_ADDR_OFST 12 4336 /* Value */ 4337 #define MC_CMD_MDIO_WRITE_IN_VALUE_OFST 16 4338 4339 /* MC_CMD_MDIO_WRITE_OUT msgresponse */ 4340 #define MC_CMD_MDIO_WRITE_OUT_LEN 4 4341 /* Status; the MDIO commands return the raw status bits from the MDIO block. A 4342 * "good" transaction should have the DONE bit set and all other bits clear. 4343 */ 4344 #define MC_CMD_MDIO_WRITE_OUT_STATUS_OFST 0 4345 /* enum: Good. */ 4346 /* MC_CMD_MDIO_STATUS_GOOD 0x8 */ 4347 4348 4349 /***********************************/ 4350 /* MC_CMD_DBI_WRITE 4351 * Write DBI register(s). 4352 */ 4353 #define MC_CMD_DBI_WRITE 0x12 4354 #undef MC_CMD_0x12_PRIVILEGE_CTG 4355 4356 #define MC_CMD_0x12_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4357 4358 /* MC_CMD_DBI_WRITE_IN msgrequest */ 4359 #define MC_CMD_DBI_WRITE_IN_LENMIN 12 4360 #define MC_CMD_DBI_WRITE_IN_LENMAX 252 4361 #define MC_CMD_DBI_WRITE_IN_LEN(num) (0+12*(num)) 4362 /* Each write op consists of an address (offset 0), byte enable/VF/CS2 (offset 4363 * 32) and value (offset 64). See MC_CMD_DBIWROP_TYPEDEF. 4364 */ 4365 #define MC_CMD_DBI_WRITE_IN_DBIWROP_OFST 0 4366 #define MC_CMD_DBI_WRITE_IN_DBIWROP_LEN 12 4367 #define MC_CMD_DBI_WRITE_IN_DBIWROP_MINNUM 1 4368 #define MC_CMD_DBI_WRITE_IN_DBIWROP_MAXNUM 21 4369 4370 /* MC_CMD_DBI_WRITE_OUT msgresponse */ 4371 #define MC_CMD_DBI_WRITE_OUT_LEN 0 4372 4373 /* MC_CMD_DBIWROP_TYPEDEF structuredef */ 4374 #define MC_CMD_DBIWROP_TYPEDEF_LEN 12 4375 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST 0 4376 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_LBN 0 4377 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_WIDTH 32 4378 #define MC_CMD_DBIWROP_TYPEDEF_PARMS_OFST 4 4379 #define MC_CMD_DBIWROP_TYPEDEF_VF_NUM_LBN 16 4380 #define MC_CMD_DBIWROP_TYPEDEF_VF_NUM_WIDTH 16 4381 #define MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_LBN 15 4382 #define MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_WIDTH 1 4383 #define MC_CMD_DBIWROP_TYPEDEF_CS2_LBN 14 4384 #define MC_CMD_DBIWROP_TYPEDEF_CS2_WIDTH 1 4385 #define MC_CMD_DBIWROP_TYPEDEF_PARMS_LBN 32 4386 #define MC_CMD_DBIWROP_TYPEDEF_PARMS_WIDTH 32 4387 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST 8 4388 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_LBN 64 4389 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_WIDTH 32 4390 4391 4392 /***********************************/ 4393 /* MC_CMD_PORT_READ32 4394 * Read a 32-bit register from the indirect port register map. The port to 4395 * access is implied by the Shared memory channel used. 4396 */ 4397 #define MC_CMD_PORT_READ32 0x14 4398 4399 /* MC_CMD_PORT_READ32_IN msgrequest */ 4400 #define MC_CMD_PORT_READ32_IN_LEN 4 4401 /* Address */ 4402 #define MC_CMD_PORT_READ32_IN_ADDR_OFST 0 4403 4404 /* MC_CMD_PORT_READ32_OUT msgresponse */ 4405 #define MC_CMD_PORT_READ32_OUT_LEN 8 4406 /* Value */ 4407 #define MC_CMD_PORT_READ32_OUT_VALUE_OFST 0 4408 /* Status */ 4409 #define MC_CMD_PORT_READ32_OUT_STATUS_OFST 4 4410 4411 4412 /***********************************/ 4413 /* MC_CMD_PORT_WRITE32 4414 * Write a 32-bit register to the indirect port register map. The port to 4415 * access is implied by the Shared memory channel used. 4416 */ 4417 #define MC_CMD_PORT_WRITE32 0x15 4418 4419 /* MC_CMD_PORT_WRITE32_IN msgrequest */ 4420 #define MC_CMD_PORT_WRITE32_IN_LEN 8 4421 /* Address */ 4422 #define MC_CMD_PORT_WRITE32_IN_ADDR_OFST 0 4423 /* Value */ 4424 #define MC_CMD_PORT_WRITE32_IN_VALUE_OFST 4 4425 4426 /* MC_CMD_PORT_WRITE32_OUT msgresponse */ 4427 #define MC_CMD_PORT_WRITE32_OUT_LEN 4 4428 /* Status */ 4429 #define MC_CMD_PORT_WRITE32_OUT_STATUS_OFST 0 4430 4431 4432 /***********************************/ 4433 /* MC_CMD_PORT_READ128 4434 * Read a 128-bit register from the indirect port register map. The port to 4435 * access is implied by the Shared memory channel used. 4436 */ 4437 #define MC_CMD_PORT_READ128 0x16 4438 4439 /* MC_CMD_PORT_READ128_IN msgrequest */ 4440 #define MC_CMD_PORT_READ128_IN_LEN 4 4441 /* Address */ 4442 #define MC_CMD_PORT_READ128_IN_ADDR_OFST 0 4443 4444 /* MC_CMD_PORT_READ128_OUT msgresponse */ 4445 #define MC_CMD_PORT_READ128_OUT_LEN 20 4446 /* Value */ 4447 #define MC_CMD_PORT_READ128_OUT_VALUE_OFST 0 4448 #define MC_CMD_PORT_READ128_OUT_VALUE_LEN 16 4449 /* Status */ 4450 #define MC_CMD_PORT_READ128_OUT_STATUS_OFST 16 4451 4452 4453 /***********************************/ 4454 /* MC_CMD_PORT_WRITE128 4455 * Write a 128-bit register to the indirect port register map. The port to 4456 * access is implied by the Shared memory channel used. 4457 */ 4458 #define MC_CMD_PORT_WRITE128 0x17 4459 4460 /* MC_CMD_PORT_WRITE128_IN msgrequest */ 4461 #define MC_CMD_PORT_WRITE128_IN_LEN 20 4462 /* Address */ 4463 #define MC_CMD_PORT_WRITE128_IN_ADDR_OFST 0 4464 /* Value */ 4465 #define MC_CMD_PORT_WRITE128_IN_VALUE_OFST 4 4466 #define MC_CMD_PORT_WRITE128_IN_VALUE_LEN 16 4467 4468 /* MC_CMD_PORT_WRITE128_OUT msgresponse */ 4469 #define MC_CMD_PORT_WRITE128_OUT_LEN 4 4470 /* Status */ 4471 #define MC_CMD_PORT_WRITE128_OUT_STATUS_OFST 0 4472 4473 /* MC_CMD_CAPABILITIES structuredef */ 4474 #define MC_CMD_CAPABILITIES_LEN 4 4475 /* Small buf table. */ 4476 #define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_LBN 0 4477 #define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_WIDTH 1 4478 /* Turbo mode (for Maranello). */ 4479 #define MC_CMD_CAPABILITIES_TURBO_LBN 1 4480 #define MC_CMD_CAPABILITIES_TURBO_WIDTH 1 4481 /* Turbo mode active (for Maranello). */ 4482 #define MC_CMD_CAPABILITIES_TURBO_ACTIVE_LBN 2 4483 #define MC_CMD_CAPABILITIES_TURBO_ACTIVE_WIDTH 1 4484 /* PTP offload. */ 4485 #define MC_CMD_CAPABILITIES_PTP_LBN 3 4486 #define MC_CMD_CAPABILITIES_PTP_WIDTH 1 4487 /* AOE mode. */ 4488 #define MC_CMD_CAPABILITIES_AOE_LBN 4 4489 #define MC_CMD_CAPABILITIES_AOE_WIDTH 1 4490 /* AOE mode active. */ 4491 #define MC_CMD_CAPABILITIES_AOE_ACTIVE_LBN 5 4492 #define MC_CMD_CAPABILITIES_AOE_ACTIVE_WIDTH 1 4493 /* AOE mode active. */ 4494 #define MC_CMD_CAPABILITIES_FC_ACTIVE_LBN 6 4495 #define MC_CMD_CAPABILITIES_FC_ACTIVE_WIDTH 1 4496 #define MC_CMD_CAPABILITIES_RESERVED_LBN 7 4497 #define MC_CMD_CAPABILITIES_RESERVED_WIDTH 25 4498 4499 4500 /***********************************/ 4501 /* MC_CMD_GET_BOARD_CFG 4502 * Returns the MC firmware configuration structure. 4503 */ 4504 #define MC_CMD_GET_BOARD_CFG 0x18 4505 #undef MC_CMD_0x18_PRIVILEGE_CTG 4506 4507 #define MC_CMD_0x18_PRIVILEGE_CTG SRIOV_CTG_GENERAL 4508 4509 /* MC_CMD_GET_BOARD_CFG_IN msgrequest */ 4510 #define MC_CMD_GET_BOARD_CFG_IN_LEN 0 4511 4512 /* MC_CMD_GET_BOARD_CFG_OUT msgresponse */ 4513 #define MC_CMD_GET_BOARD_CFG_OUT_LENMIN 96 4514 #define MC_CMD_GET_BOARD_CFG_OUT_LENMAX 136 4515 #define MC_CMD_GET_BOARD_CFG_OUT_LEN(num) (72+2*(num)) 4516 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_OFST 0 4517 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_OFST 4 4518 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_LEN 32 4519 /* See MC_CMD_CAPABILITIES */ 4520 #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT0_OFST 36 4521 /* See MC_CMD_CAPABILITIES */ 4522 #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT1_OFST 40 4523 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_OFST 44 4524 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_LEN 6 4525 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_OFST 50 4526 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_LEN 6 4527 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT0_OFST 56 4528 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT1_OFST 60 4529 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT0_OFST 64 4530 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT1_OFST 68 4531 /* This field contains a 16-bit value for each of the types of NVRAM area. The 4532 * values are defined in the firmware/mc/platform/.c file for a specific board 4533 * type, but otherwise have no meaning to the MC; they are used by the driver 4534 * to manage selection of appropriate firmware updates. 4535 */ 4536 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_OFST 72 4537 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_LEN 2 4538 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MINNUM 12 4539 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM 32 4540 4541 4542 /***********************************/ 4543 /* MC_CMD_DBI_READX 4544 * Read DBI register(s) -- extended functionality 4545 */ 4546 #define MC_CMD_DBI_READX 0x19 4547 #undef MC_CMD_0x19_PRIVILEGE_CTG 4548 4549 #define MC_CMD_0x19_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4550 4551 /* MC_CMD_DBI_READX_IN msgrequest */ 4552 #define MC_CMD_DBI_READX_IN_LENMIN 8 4553 #define MC_CMD_DBI_READX_IN_LENMAX 248 4554 #define MC_CMD_DBI_READX_IN_LEN(num) (0+8*(num)) 4555 /* Each Read op consists of an address (offset 0), VF/CS2) */ 4556 #define MC_CMD_DBI_READX_IN_DBIRDOP_OFST 0 4557 #define MC_CMD_DBI_READX_IN_DBIRDOP_LEN 8 4558 #define MC_CMD_DBI_READX_IN_DBIRDOP_LO_OFST 0 4559 #define MC_CMD_DBI_READX_IN_DBIRDOP_HI_OFST 4 4560 #define MC_CMD_DBI_READX_IN_DBIRDOP_MINNUM 1 4561 #define MC_CMD_DBI_READX_IN_DBIRDOP_MAXNUM 31 4562 4563 /* MC_CMD_DBI_READX_OUT msgresponse */ 4564 #define MC_CMD_DBI_READX_OUT_LENMIN 4 4565 #define MC_CMD_DBI_READX_OUT_LENMAX 252 4566 #define MC_CMD_DBI_READX_OUT_LEN(num) (0+4*(num)) 4567 /* Value */ 4568 #define MC_CMD_DBI_READX_OUT_VALUE_OFST 0 4569 #define MC_CMD_DBI_READX_OUT_VALUE_LEN 4 4570 #define MC_CMD_DBI_READX_OUT_VALUE_MINNUM 1 4571 #define MC_CMD_DBI_READX_OUT_VALUE_MAXNUM 63 4572 4573 /* MC_CMD_DBIRDOP_TYPEDEF structuredef */ 4574 #define MC_CMD_DBIRDOP_TYPEDEF_LEN 8 4575 #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_OFST 0 4576 #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_LBN 0 4577 #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_WIDTH 32 4578 #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_OFST 4 4579 #define MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_LBN 16 4580 #define MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_WIDTH 16 4581 #define MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_LBN 15 4582 #define MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_WIDTH 1 4583 #define MC_CMD_DBIRDOP_TYPEDEF_CS2_LBN 14 4584 #define MC_CMD_DBIRDOP_TYPEDEF_CS2_WIDTH 1 4585 #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_LBN 32 4586 #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_WIDTH 32 4587 4588 4589 /***********************************/ 4590 /* MC_CMD_SET_RAND_SEED 4591 * Set the 16byte seed for the MC pseudo-random generator. 4592 */ 4593 #define MC_CMD_SET_RAND_SEED 0x1a 4594 #undef MC_CMD_0x1a_PRIVILEGE_CTG 4595 4596 #define MC_CMD_0x1a_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4597 4598 /* MC_CMD_SET_RAND_SEED_IN msgrequest */ 4599 #define MC_CMD_SET_RAND_SEED_IN_LEN 16 4600 /* Seed value. */ 4601 #define MC_CMD_SET_RAND_SEED_IN_SEED_OFST 0 4602 #define MC_CMD_SET_RAND_SEED_IN_SEED_LEN 16 4603 4604 /* MC_CMD_SET_RAND_SEED_OUT msgresponse */ 4605 #define MC_CMD_SET_RAND_SEED_OUT_LEN 0 4606 4607 4608 /***********************************/ 4609 /* MC_CMD_LTSSM_HIST 4610 * Retrieve the history of the LTSSM, if the build supports it. 4611 */ 4612 #define MC_CMD_LTSSM_HIST 0x1b 4613 4614 /* MC_CMD_LTSSM_HIST_IN msgrequest */ 4615 #define MC_CMD_LTSSM_HIST_IN_LEN 0 4616 4617 /* MC_CMD_LTSSM_HIST_OUT msgresponse */ 4618 #define MC_CMD_LTSSM_HIST_OUT_LENMIN 0 4619 #define MC_CMD_LTSSM_HIST_OUT_LENMAX 252 4620 #define MC_CMD_LTSSM_HIST_OUT_LEN(num) (0+4*(num)) 4621 /* variable number of LTSSM values, as bytes. The history is read-to-clear. */ 4622 #define MC_CMD_LTSSM_HIST_OUT_DATA_OFST 0 4623 #define MC_CMD_LTSSM_HIST_OUT_DATA_LEN 4 4624 #define MC_CMD_LTSSM_HIST_OUT_DATA_MINNUM 0 4625 #define MC_CMD_LTSSM_HIST_OUT_DATA_MAXNUM 63 4626 4627 4628 /***********************************/ 4629 /* MC_CMD_DRV_ATTACH 4630 * Inform MCPU that this port is managed on the host (i.e. driver active). For 4631 * Huntington, also request the preferred datapath firmware to use if possible 4632 * (it may not be possible for this request to be fulfilled; the driver must 4633 * issue a subsequent MC_CMD_GET_CAPABILITIES command to determine which 4634 * features are actually available). The FIRMWARE_ID field is ignored by older 4635 * platforms. 4636 */ 4637 #define MC_CMD_DRV_ATTACH 0x1c 4638 #undef MC_CMD_0x1c_PRIVILEGE_CTG 4639 4640 #define MC_CMD_0x1c_PRIVILEGE_CTG SRIOV_CTG_GENERAL 4641 4642 /* MC_CMD_DRV_ATTACH_IN msgrequest */ 4643 #define MC_CMD_DRV_ATTACH_IN_LEN 12 4644 /* new state to set if UPDATE=1 */ 4645 #define MC_CMD_DRV_ATTACH_IN_NEW_STATE_OFST 0 4646 #define MC_CMD_DRV_ATTACH_LBN 0 4647 #define MC_CMD_DRV_ATTACH_WIDTH 1 4648 #define MC_CMD_DRV_PREBOOT_LBN 1 4649 #define MC_CMD_DRV_PREBOOT_WIDTH 1 4650 /* 1 to set new state, or 0 to just report the existing state */ 4651 #define MC_CMD_DRV_ATTACH_IN_UPDATE_OFST 4 4652 /* preferred datapath firmware (for Huntington; ignored for Siena) */ 4653 #define MC_CMD_DRV_ATTACH_IN_FIRMWARE_ID_OFST 8 4654 /* enum: Prefer to use full featured firmware */ 4655 #define MC_CMD_FW_FULL_FEATURED 0x0 4656 /* enum: Prefer to use firmware with fewer features but lower latency */ 4657 #define MC_CMD_FW_LOW_LATENCY 0x1 4658 /* enum: Prefer to use firmware for SolarCapture packed stream mode */ 4659 #define MC_CMD_FW_PACKED_STREAM 0x2 4660 /* enum: Prefer to use firmware with fewer features and simpler TX event 4661 * batching but higher TX packet rate 4662 */ 4663 #define MC_CMD_FW_HIGH_TX_RATE 0x3 4664 /* enum: Reserved value */ 4665 #define MC_CMD_FW_PACKED_STREAM_HASH_MODE_1 0x4 4666 /* enum: Only this option is allowed for non-admin functions */ 4667 #define MC_CMD_FW_DONT_CARE 0xffffffff 4668 4669 /* MC_CMD_DRV_ATTACH_OUT msgresponse */ 4670 #define MC_CMD_DRV_ATTACH_OUT_LEN 4 4671 /* previous or existing state, see the bitmask at NEW_STATE */ 4672 #define MC_CMD_DRV_ATTACH_OUT_OLD_STATE_OFST 0 4673 4674 /* MC_CMD_DRV_ATTACH_EXT_OUT msgresponse */ 4675 #define MC_CMD_DRV_ATTACH_EXT_OUT_LEN 8 4676 /* previous or existing state, see the bitmask at NEW_STATE */ 4677 #define MC_CMD_DRV_ATTACH_EXT_OUT_OLD_STATE_OFST 0 4678 /* Flags associated with this function */ 4679 #define MC_CMD_DRV_ATTACH_EXT_OUT_FUNC_FLAGS_OFST 4 4680 /* enum: Labels the lowest-numbered function visible to the OS */ 4681 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY 0x0 4682 /* enum: The function can control the link state of the physical port it is 4683 * bound to. 4684 */ 4685 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL 0x1 4686 /* enum: The function can perform privileged operations */ 4687 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TRUSTED 0x2 4688 /* enum: The function does not have an active port associated with it. The port 4689 * refers to the Sorrento external FPGA port. 4690 */ 4691 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_NO_ACTIVE_PORT 0x3 4692 4693 4694 /***********************************/ 4695 /* MC_CMD_SHMUART 4696 * Route UART output to circular buffer in shared memory instead. 4697 */ 4698 #define MC_CMD_SHMUART 0x1f 4699 4700 /* MC_CMD_SHMUART_IN msgrequest */ 4701 #define MC_CMD_SHMUART_IN_LEN 4 4702 /* ??? */ 4703 #define MC_CMD_SHMUART_IN_FLAG_OFST 0 4704 4705 /* MC_CMD_SHMUART_OUT msgresponse */ 4706 #define MC_CMD_SHMUART_OUT_LEN 0 4707 4708 4709 /***********************************/ 4710 /* MC_CMD_PORT_RESET 4711 * Generic per-port reset. There is no equivalent for per-board reset. Locks 4712 * required: None; Return code: 0, ETIME. NOTE: This command is deprecated - 4713 * use MC_CMD_ENTITY_RESET instead. 4714 */ 4715 #define MC_CMD_PORT_RESET 0x20 4716 #undef MC_CMD_0x20_PRIVILEGE_CTG 4717 4718 #define MC_CMD_0x20_PRIVILEGE_CTG SRIOV_CTG_GENERAL 4719 4720 /* MC_CMD_PORT_RESET_IN msgrequest */ 4721 #define MC_CMD_PORT_RESET_IN_LEN 0 4722 4723 /* MC_CMD_PORT_RESET_OUT msgresponse */ 4724 #define MC_CMD_PORT_RESET_OUT_LEN 0 4725 4726 4727 /***********************************/ 4728 /* MC_CMD_ENTITY_RESET 4729 * Generic per-resource reset. There is no equivalent for per-board reset. 4730 * Locks required: None; Return code: 0, ETIME. NOTE: This command is an 4731 * extended version of the deprecated MC_CMD_PORT_RESET with added fields. 4732 */ 4733 #define MC_CMD_ENTITY_RESET 0x20 4734 /* MC_CMD_0x20_PRIVILEGE_CTG SRIOV_CTG_GENERAL */ 4735 4736 /* MC_CMD_ENTITY_RESET_IN msgrequest */ 4737 #define MC_CMD_ENTITY_RESET_IN_LEN 4 4738 /* Optional flags field. Omitting this will perform a "legacy" reset action 4739 * (TBD). 4740 */ 4741 #define MC_CMD_ENTITY_RESET_IN_FLAG_OFST 0 4742 #define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_LBN 0 4743 #define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_WIDTH 1 4744 4745 /* MC_CMD_ENTITY_RESET_OUT msgresponse */ 4746 #define MC_CMD_ENTITY_RESET_OUT_LEN 0 4747 4748 4749 /***********************************/ 4750 /* MC_CMD_PCIE_CREDITS 4751 * Read instantaneous and minimum flow control thresholds. 4752 */ 4753 #define MC_CMD_PCIE_CREDITS 0x21 4754 4755 /* MC_CMD_PCIE_CREDITS_IN msgrequest */ 4756 #define MC_CMD_PCIE_CREDITS_IN_LEN 8 4757 /* poll period. 0 is disabled */ 4758 #define MC_CMD_PCIE_CREDITS_IN_POLL_PERIOD_OFST 0 4759 /* wipe statistics */ 4760 #define MC_CMD_PCIE_CREDITS_IN_WIPE_OFST 4 4761 4762 /* MC_CMD_PCIE_CREDITS_OUT msgresponse */ 4763 #define MC_CMD_PCIE_CREDITS_OUT_LEN 16 4764 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_OFST 0 4765 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_LEN 2 4766 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_OFST 2 4767 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_LEN 2 4768 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_OFST 4 4769 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_LEN 2 4770 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_OFST 6 4771 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_LEN 2 4772 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_OFST 8 4773 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_LEN 2 4774 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_OFST 10 4775 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_LEN 2 4776 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_OFST 12 4777 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_LEN 2 4778 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_OFST 14 4779 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_LEN 2 4780 4781 4782 /***********************************/ 4783 /* MC_CMD_RXD_MONITOR 4784 * Get histogram of RX queue fill level. 4785 */ 4786 #define MC_CMD_RXD_MONITOR 0x22 4787 4788 /* MC_CMD_RXD_MONITOR_IN msgrequest */ 4789 #define MC_CMD_RXD_MONITOR_IN_LEN 12 4790 #define MC_CMD_RXD_MONITOR_IN_QID_OFST 0 4791 #define MC_CMD_RXD_MONITOR_IN_POLL_PERIOD_OFST 4 4792 #define MC_CMD_RXD_MONITOR_IN_WIPE_OFST 8 4793 4794 /* MC_CMD_RXD_MONITOR_OUT msgresponse */ 4795 #define MC_CMD_RXD_MONITOR_OUT_LEN 80 4796 #define MC_CMD_RXD_MONITOR_OUT_QID_OFST 0 4797 #define MC_CMD_RXD_MONITOR_OUT_RING_FILL_OFST 4 4798 #define MC_CMD_RXD_MONITOR_OUT_CACHE_FILL_OFST 8 4799 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_1_OFST 12 4800 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_2_OFST 16 4801 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_4_OFST 20 4802 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_8_OFST 24 4803 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_16_OFST 28 4804 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_32_OFST 32 4805 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_64_OFST 36 4806 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_128_OFST 40 4807 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_256_OFST 44 4808 #define MC_CMD_RXD_MONITOR_OUT_RING_GE_256_OFST 48 4809 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_1_OFST 52 4810 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_2_OFST 56 4811 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_4_OFST 60 4812 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_8_OFST 64 4813 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_16_OFST 68 4814 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_32_OFST 72 4815 #define MC_CMD_RXD_MONITOR_OUT_CACHE_GE_32_OFST 76 4816 4817 4818 /***********************************/ 4819 /* MC_CMD_PUTS 4820 * Copy the given ASCII string out onto UART and/or out of the network port. 4821 */ 4822 #define MC_CMD_PUTS 0x23 4823 #undef MC_CMD_0x23_PRIVILEGE_CTG 4824 4825 #define MC_CMD_0x23_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4826 4827 /* MC_CMD_PUTS_IN msgrequest */ 4828 #define MC_CMD_PUTS_IN_LENMIN 13 4829 #define MC_CMD_PUTS_IN_LENMAX 252 4830 #define MC_CMD_PUTS_IN_LEN(num) (12+1*(num)) 4831 #define MC_CMD_PUTS_IN_DEST_OFST 0 4832 #define MC_CMD_PUTS_IN_UART_LBN 0 4833 #define MC_CMD_PUTS_IN_UART_WIDTH 1 4834 #define MC_CMD_PUTS_IN_PORT_LBN 1 4835 #define MC_CMD_PUTS_IN_PORT_WIDTH 1 4836 #define MC_CMD_PUTS_IN_DHOST_OFST 4 4837 #define MC_CMD_PUTS_IN_DHOST_LEN 6 4838 #define MC_CMD_PUTS_IN_STRING_OFST 12 4839 #define MC_CMD_PUTS_IN_STRING_LEN 1 4840 #define MC_CMD_PUTS_IN_STRING_MINNUM 1 4841 #define MC_CMD_PUTS_IN_STRING_MAXNUM 240 4842 4843 /* MC_CMD_PUTS_OUT msgresponse */ 4844 #define MC_CMD_PUTS_OUT_LEN 0 4845 4846 4847 /***********************************/ 4848 /* MC_CMD_GET_PHY_CFG 4849 * Report PHY configuration. This guarantees to succeed even if the PHY is in a 4850 * 'zombie' state. Locks required: None 4851 */ 4852 #define MC_CMD_GET_PHY_CFG 0x24 4853 #undef MC_CMD_0x24_PRIVILEGE_CTG 4854 4855 #define MC_CMD_0x24_PRIVILEGE_CTG SRIOV_CTG_GENERAL 4856 4857 /* MC_CMD_GET_PHY_CFG_IN msgrequest */ 4858 #define MC_CMD_GET_PHY_CFG_IN_LEN 0 4859 4860 /* MC_CMD_GET_PHY_CFG_OUT msgresponse */ 4861 #define MC_CMD_GET_PHY_CFG_OUT_LEN 72 4862 /* flags */ 4863 #define MC_CMD_GET_PHY_CFG_OUT_FLAGS_OFST 0 4864 #define MC_CMD_GET_PHY_CFG_OUT_PRESENT_LBN 0 4865 #define MC_CMD_GET_PHY_CFG_OUT_PRESENT_WIDTH 1 4866 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_LBN 1 4867 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_WIDTH 1 4868 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_LBN 2 4869 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_WIDTH 1 4870 #define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_LBN 3 4871 #define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_WIDTH 1 4872 #define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_LBN 4 4873 #define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_WIDTH 1 4874 #define MC_CMD_GET_PHY_CFG_OUT_TXDIS_LBN 5 4875 #define MC_CMD_GET_PHY_CFG_OUT_TXDIS_WIDTH 1 4876 #define MC_CMD_GET_PHY_CFG_OUT_BIST_LBN 6 4877 #define MC_CMD_GET_PHY_CFG_OUT_BIST_WIDTH 1 4878 /* ?? */ 4879 #define MC_CMD_GET_PHY_CFG_OUT_TYPE_OFST 4 4880 /* Bitmask of supported capabilities */ 4881 #define MC_CMD_GET_PHY_CFG_OUT_SUPPORTED_CAP_OFST 8 4882 #define MC_CMD_PHY_CAP_10HDX_LBN 1 4883 #define MC_CMD_PHY_CAP_10HDX_WIDTH 1 4884 #define MC_CMD_PHY_CAP_10FDX_LBN 2 4885 #define MC_CMD_PHY_CAP_10FDX_WIDTH 1 4886 #define MC_CMD_PHY_CAP_100HDX_LBN 3 4887 #define MC_CMD_PHY_CAP_100HDX_WIDTH 1 4888 #define MC_CMD_PHY_CAP_100FDX_LBN 4 4889 #define MC_CMD_PHY_CAP_100FDX_WIDTH 1 4890 #define MC_CMD_PHY_CAP_1000HDX_LBN 5 4891 #define MC_CMD_PHY_CAP_1000HDX_WIDTH 1 4892 #define MC_CMD_PHY_CAP_1000FDX_LBN 6 4893 #define MC_CMD_PHY_CAP_1000FDX_WIDTH 1 4894 #define MC_CMD_PHY_CAP_10000FDX_LBN 7 4895 #define MC_CMD_PHY_CAP_10000FDX_WIDTH 1 4896 #define MC_CMD_PHY_CAP_PAUSE_LBN 8 4897 #define MC_CMD_PHY_CAP_PAUSE_WIDTH 1 4898 #define MC_CMD_PHY_CAP_ASYM_LBN 9 4899 #define MC_CMD_PHY_CAP_ASYM_WIDTH 1 4900 #define MC_CMD_PHY_CAP_AN_LBN 10 4901 #define MC_CMD_PHY_CAP_AN_WIDTH 1 4902 #define MC_CMD_PHY_CAP_40000FDX_LBN 11 4903 #define MC_CMD_PHY_CAP_40000FDX_WIDTH 1 4904 #define MC_CMD_PHY_CAP_DDM_LBN 12 4905 #define MC_CMD_PHY_CAP_DDM_WIDTH 1 4906 /* ?? */ 4907 #define MC_CMD_GET_PHY_CFG_OUT_CHANNEL_OFST 12 4908 /* ?? */ 4909 #define MC_CMD_GET_PHY_CFG_OUT_PRT_OFST 16 4910 /* ?? */ 4911 #define MC_CMD_GET_PHY_CFG_OUT_STATS_MASK_OFST 20 4912 /* ?? */ 4913 #define MC_CMD_GET_PHY_CFG_OUT_NAME_OFST 24 4914 #define MC_CMD_GET_PHY_CFG_OUT_NAME_LEN 20 4915 /* ?? */ 4916 #define MC_CMD_GET_PHY_CFG_OUT_MEDIA_TYPE_OFST 44 4917 /* enum: Xaui. */ 4918 #define MC_CMD_MEDIA_XAUI 0x1 4919 /* enum: CX4. */ 4920 #define MC_CMD_MEDIA_CX4 0x2 4921 /* enum: KX4. */ 4922 #define MC_CMD_MEDIA_KX4 0x3 4923 /* enum: XFP Far. */ 4924 #define MC_CMD_MEDIA_XFP 0x4 4925 /* enum: SFP+. */ 4926 #define MC_CMD_MEDIA_SFP_PLUS 0x5 4927 /* enum: 10GBaseT. */ 4928 #define MC_CMD_MEDIA_BASE_T 0x6 4929 /* enum: QSFP+. */ 4930 #define MC_CMD_MEDIA_QSFP_PLUS 0x7 4931 #define MC_CMD_GET_PHY_CFG_OUT_MMD_MASK_OFST 48 4932 /* enum: Native clause 22 */ 4933 #define MC_CMD_MMD_CLAUSE22 0x0 4934 #define MC_CMD_MMD_CLAUSE45_PMAPMD 0x1 /* enum */ 4935 #define MC_CMD_MMD_CLAUSE45_WIS 0x2 /* enum */ 4936 #define MC_CMD_MMD_CLAUSE45_PCS 0x3 /* enum */ 4937 #define MC_CMD_MMD_CLAUSE45_PHYXS 0x4 /* enum */ 4938 #define MC_CMD_MMD_CLAUSE45_DTEXS 0x5 /* enum */ 4939 #define MC_CMD_MMD_CLAUSE45_TC 0x6 /* enum */ 4940 #define MC_CMD_MMD_CLAUSE45_AN 0x7 /* enum */ 4941 /* enum: Clause22 proxied over clause45 by PHY. */ 4942 #define MC_CMD_MMD_CLAUSE45_C22EXT 0x1d 4943 #define MC_CMD_MMD_CLAUSE45_VEND1 0x1e /* enum */ 4944 #define MC_CMD_MMD_CLAUSE45_VEND2 0x1f /* enum */ 4945 #define MC_CMD_GET_PHY_CFG_OUT_REVISION_OFST 52 4946 #define MC_CMD_GET_PHY_CFG_OUT_REVISION_LEN 20 4947 4948 4949 /***********************************/ 4950 /* MC_CMD_START_BIST 4951 * Start a BIST test on the PHY. Locks required: PHY_LOCK if doing a PHY BIST 4952 * Return code: 0, EINVAL, EACCES (if PHY_LOCK is not held) 4953 */ 4954 #define MC_CMD_START_BIST 0x25 4955 #undef MC_CMD_0x25_PRIVILEGE_CTG 4956 4957 #define MC_CMD_0x25_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4958 4959 /* MC_CMD_START_BIST_IN msgrequest */ 4960 #define MC_CMD_START_BIST_IN_LEN 4 4961 /* Type of test. */ 4962 #define MC_CMD_START_BIST_IN_TYPE_OFST 0 4963 /* enum: Run the PHY's short cable BIST. */ 4964 #define MC_CMD_PHY_BIST_CABLE_SHORT 0x1 4965 /* enum: Run the PHY's long cable BIST. */ 4966 #define MC_CMD_PHY_BIST_CABLE_LONG 0x2 4967 /* enum: Run BIST on the currently selected BPX Serdes (XAUI or XFI) . */ 4968 #define MC_CMD_BPX_SERDES_BIST 0x3 4969 /* enum: Run the MC loopback tests. */ 4970 #define MC_CMD_MC_LOOPBACK_BIST 0x4 4971 /* enum: Run the PHY's standard BIST. */ 4972 #define MC_CMD_PHY_BIST 0x5 4973 /* enum: Run MC RAM test. */ 4974 #define MC_CMD_MC_MEM_BIST 0x6 4975 /* enum: Run Port RAM test. */ 4976 #define MC_CMD_PORT_MEM_BIST 0x7 4977 /* enum: Run register test. */ 4978 #define MC_CMD_REG_BIST 0x8 4979 4980 /* MC_CMD_START_BIST_OUT msgresponse */ 4981 #define MC_CMD_START_BIST_OUT_LEN 0 4982 4983 4984 /***********************************/ 4985 /* MC_CMD_POLL_BIST 4986 * Poll for BIST completion. Returns a single status code, and optionally some 4987 * PHY specific bist output. The driver should only consume the BIST output 4988 * after validating OUTLEN and MC_CMD_GET_PHY_CFG.TYPE. If a driver can't 4989 * successfully parse the BIST output, it should still respect the pass/Fail in 4990 * OUT.RESULT. Locks required: PHY_LOCK if doing a PHY BIST. Return code: 0, 4991 * EACCES (if PHY_LOCK is not held). 4992 */ 4993 #define MC_CMD_POLL_BIST 0x26 4994 #undef MC_CMD_0x26_PRIVILEGE_CTG 4995 4996 #define MC_CMD_0x26_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4997 4998 /* MC_CMD_POLL_BIST_IN msgrequest */ 4999 #define MC_CMD_POLL_BIST_IN_LEN 0 5000 5001 /* MC_CMD_POLL_BIST_OUT msgresponse */ 5002 #define MC_CMD_POLL_BIST_OUT_LEN 8 5003 /* result */ 5004 #define MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 5005 /* enum: Running. */ 5006 #define MC_CMD_POLL_BIST_RUNNING 0x1 5007 /* enum: Passed. */ 5008 #define MC_CMD_POLL_BIST_PASSED 0x2 5009 /* enum: Failed. */ 5010 #define MC_CMD_POLL_BIST_FAILED 0x3 5011 /* enum: Timed-out. */ 5012 #define MC_CMD_POLL_BIST_TIMEOUT 0x4 5013 #define MC_CMD_POLL_BIST_OUT_PRIVATE_OFST 4 5014 5015 /* MC_CMD_POLL_BIST_OUT_SFT9001 msgresponse */ 5016 #define MC_CMD_POLL_BIST_OUT_SFT9001_LEN 36 5017 /* result */ 5018 /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */ 5019 /* Enum values, see field(s): */ 5020 /* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */ 5021 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A_OFST 4 5022 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B_OFST 8 5023 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C_OFST 12 5024 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D_OFST 16 5025 /* Status of each channel A */ 5026 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_A_OFST 20 5027 /* enum: Ok. */ 5028 #define MC_CMD_POLL_BIST_SFT9001_PAIR_OK 0x1 5029 /* enum: Open. */ 5030 #define MC_CMD_POLL_BIST_SFT9001_PAIR_OPEN 0x2 5031 /* enum: Intra-pair short. */ 5032 #define MC_CMD_POLL_BIST_SFT9001_INTRA_PAIR_SHORT 0x3 5033 /* enum: Inter-pair short. */ 5034 #define MC_CMD_POLL_BIST_SFT9001_INTER_PAIR_SHORT 0x4 5035 /* enum: Busy. */ 5036 #define MC_CMD_POLL_BIST_SFT9001_PAIR_BUSY 0x9 5037 /* Status of each channel B */ 5038 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_B_OFST 24 5039 /* Enum values, see field(s): */ 5040 /* CABLE_STATUS_A */ 5041 /* Status of each channel C */ 5042 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_C_OFST 28 5043 /* Enum values, see field(s): */ 5044 /* CABLE_STATUS_A */ 5045 /* Status of each channel D */ 5046 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_D_OFST 32 5047 /* Enum values, see field(s): */ 5048 /* CABLE_STATUS_A */ 5049 5050 /* MC_CMD_POLL_BIST_OUT_MRSFP msgresponse */ 5051 #define MC_CMD_POLL_BIST_OUT_MRSFP_LEN 8 5052 /* result */ 5053 /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */ 5054 /* Enum values, see field(s): */ 5055 /* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */ 5056 #define MC_CMD_POLL_BIST_OUT_MRSFP_TEST_OFST 4 5057 /* enum: Complete. */ 5058 #define MC_CMD_POLL_BIST_MRSFP_TEST_COMPLETE 0x0 5059 /* enum: Bus switch off I2C write. */ 5060 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_WRITE 0x1 5061 /* enum: Bus switch off I2C no access IO exp. */ 5062 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_IO_EXP 0x2 5063 /* enum: Bus switch off I2C no access module. */ 5064 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_MODULE 0x3 5065 /* enum: IO exp I2C configure. */ 5066 #define MC_CMD_POLL_BIST_MRSFP_TEST_IO_EXP_I2C_CONFIGURE 0x4 5067 /* enum: Bus switch I2C no cross talk. */ 5068 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_I2C_NO_CROSSTALK 0x5 5069 /* enum: Module presence. */ 5070 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_PRESENCE 0x6 5071 /* enum: Module ID I2C access. */ 5072 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_I2C_ACCESS 0x7 5073 /* enum: Module ID sane value. */ 5074 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_SANE_VALUE 0x8 5075 5076 /* MC_CMD_POLL_BIST_OUT_MEM msgresponse */ 5077 #define MC_CMD_POLL_BIST_OUT_MEM_LEN 36 5078 /* result */ 5079 /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */ 5080 /* Enum values, see field(s): */ 5081 /* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */ 5082 #define MC_CMD_POLL_BIST_OUT_MEM_TEST_OFST 4 5083 /* enum: Test has completed. */ 5084 #define MC_CMD_POLL_BIST_MEM_COMPLETE 0x0 5085 /* enum: RAM test - walk ones. */ 5086 #define MC_CMD_POLL_BIST_MEM_MEM_WALK_ONES 0x1 5087 /* enum: RAM test - walk zeros. */ 5088 #define MC_CMD_POLL_BIST_MEM_MEM_WALK_ZEROS 0x2 5089 /* enum: RAM test - walking inversions zeros/ones. */ 5090 #define MC_CMD_POLL_BIST_MEM_MEM_INV_ZERO_ONE 0x3 5091 /* enum: RAM test - walking inversions checkerboard. */ 5092 #define MC_CMD_POLL_BIST_MEM_MEM_INV_CHKBOARD 0x4 5093 /* enum: Register test - set / clear individual bits. */ 5094 #define MC_CMD_POLL_BIST_MEM_REG 0x5 5095 /* enum: ECC error detected. */ 5096 #define MC_CMD_POLL_BIST_MEM_ECC 0x6 5097 /* Failure address, only valid if result is POLL_BIST_FAILED */ 5098 #define MC_CMD_POLL_BIST_OUT_MEM_ADDR_OFST 8 5099 /* Bus or address space to which the failure address corresponds */ 5100 #define MC_CMD_POLL_BIST_OUT_MEM_BUS_OFST 12 5101 /* enum: MC MIPS bus. */ 5102 #define MC_CMD_POLL_BIST_MEM_BUS_MC 0x0 5103 /* enum: CSR IREG bus. */ 5104 #define MC_CMD_POLL_BIST_MEM_BUS_CSR 0x1 5105 /* enum: RX DPCPU bus. */ 5106 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_RX 0x2 5107 /* enum: TX0 DPCPU bus. */ 5108 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX0 0x3 5109 /* enum: TX1 DPCPU bus. */ 5110 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX1 0x4 5111 /* enum: RX DICPU bus. */ 5112 #define MC_CMD_POLL_BIST_MEM_BUS_DICPU_RX 0x5 5113 /* enum: TX DICPU bus. */ 5114 #define MC_CMD_POLL_BIST_MEM_BUS_DICPU_TX 0x6 5115 /* Pattern written to RAM / register */ 5116 #define MC_CMD_POLL_BIST_OUT_MEM_EXPECT_OFST 16 5117 /* Actual value read from RAM / register */ 5118 #define MC_CMD_POLL_BIST_OUT_MEM_ACTUAL_OFST 20 5119 /* ECC error mask */ 5120 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_OFST 24 5121 /* ECC parity error mask */ 5122 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_PARITY_OFST 28 5123 /* ECC fatal error mask */ 5124 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_FATAL_OFST 32 5125 5126 5127 /***********************************/ 5128 /* MC_CMD_FLUSH_RX_QUEUES 5129 * Flush receive queue(s). If SRIOV is enabled (via MC_CMD_SRIOV), then RXQ 5130 * flushes should be initiated via this MCDI operation, rather than via 5131 * directly writing FLUSH_CMD. 5132 * 5133 * The flush is completed (either done/fail) asynchronously (after this command 5134 * returns). The driver must still wait for flush done/failure events as usual. 5135 */ 5136 #define MC_CMD_FLUSH_RX_QUEUES 0x27 5137 5138 /* MC_CMD_FLUSH_RX_QUEUES_IN msgrequest */ 5139 #define MC_CMD_FLUSH_RX_QUEUES_IN_LENMIN 4 5140 #define MC_CMD_FLUSH_RX_QUEUES_IN_LENMAX 252 5141 #define MC_CMD_FLUSH_RX_QUEUES_IN_LEN(num) (0+4*(num)) 5142 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_OFST 0 5143 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_LEN 4 5144 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MINNUM 1 5145 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MAXNUM 63 5146 5147 /* MC_CMD_FLUSH_RX_QUEUES_OUT msgresponse */ 5148 #define MC_CMD_FLUSH_RX_QUEUES_OUT_LEN 0 5149 5150 5151 /***********************************/ 5152 /* MC_CMD_GET_LOOPBACK_MODES 5153 * Returns a bitmask of loopback modes available at each speed. 5154 */ 5155 #define MC_CMD_GET_LOOPBACK_MODES 0x28 5156 #undef MC_CMD_0x28_PRIVILEGE_CTG 5157 5158 #define MC_CMD_0x28_PRIVILEGE_CTG SRIOV_CTG_GENERAL 5159 5160 /* MC_CMD_GET_LOOPBACK_MODES_IN msgrequest */ 5161 #define MC_CMD_GET_LOOPBACK_MODES_IN_LEN 0 5162 5163 /* MC_CMD_GET_LOOPBACK_MODES_OUT msgresponse */ 5164 #define MC_CMD_GET_LOOPBACK_MODES_OUT_LEN 40 5165 /* Supported loopbacks. */ 5166 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_OFST 0 5167 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LEN 8 5168 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_OFST 0 5169 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_OFST 4 5170 /* enum: None. */ 5171 #define MC_CMD_LOOPBACK_NONE 0x0 5172 /* enum: Data. */ 5173 #define MC_CMD_LOOPBACK_DATA 0x1 5174 /* enum: GMAC. */ 5175 #define MC_CMD_LOOPBACK_GMAC 0x2 5176 /* enum: XGMII. */ 5177 #define MC_CMD_LOOPBACK_XGMII 0x3 5178 /* enum: XGXS. */ 5179 #define MC_CMD_LOOPBACK_XGXS 0x4 5180 /* enum: XAUI. */ 5181 #define MC_CMD_LOOPBACK_XAUI 0x5 5182 /* enum: GMII. */ 5183 #define MC_CMD_LOOPBACK_GMII 0x6 5184 /* enum: SGMII. */ 5185 #define MC_CMD_LOOPBACK_SGMII 0x7 5186 /* enum: XGBR. */ 5187 #define MC_CMD_LOOPBACK_XGBR 0x8 5188 /* enum: XFI. */ 5189 #define MC_CMD_LOOPBACK_XFI 0x9 5190 /* enum: XAUI Far. */ 5191 #define MC_CMD_LOOPBACK_XAUI_FAR 0xa 5192 /* enum: GMII Far. */ 5193 #define MC_CMD_LOOPBACK_GMII_FAR 0xb 5194 /* enum: SGMII Far. */ 5195 #define MC_CMD_LOOPBACK_SGMII_FAR 0xc 5196 /* enum: XFI Far. */ 5197 #define MC_CMD_LOOPBACK_XFI_FAR 0xd 5198 /* enum: GPhy. */ 5199 #define MC_CMD_LOOPBACK_GPHY 0xe 5200 /* enum: PhyXS. */ 5201 #define MC_CMD_LOOPBACK_PHYXS 0xf 5202 /* enum: PCS. */ 5203 #define MC_CMD_LOOPBACK_PCS 0x10 5204 /* enum: PMA-PMD. */ 5205 #define MC_CMD_LOOPBACK_PMAPMD 0x11 5206 /* enum: Cross-Port. */ 5207 #define MC_CMD_LOOPBACK_XPORT 0x12 5208 /* enum: XGMII-Wireside. */ 5209 #define MC_CMD_LOOPBACK_XGMII_WS 0x13 5210 /* enum: XAUI Wireside. */ 5211 #define MC_CMD_LOOPBACK_XAUI_WS 0x14 5212 /* enum: XAUI Wireside Far. */ 5213 #define MC_CMD_LOOPBACK_XAUI_WS_FAR 0x15 5214 /* enum: XAUI Wireside near. */ 5215 #define MC_CMD_LOOPBACK_XAUI_WS_NEAR 0x16 5216 /* enum: GMII Wireside. */ 5217 #define MC_CMD_LOOPBACK_GMII_WS 0x17 5218 /* enum: XFI Wireside. */ 5219 #define MC_CMD_LOOPBACK_XFI_WS 0x18 5220 /* enum: XFI Wireside Far. */ 5221 #define MC_CMD_LOOPBACK_XFI_WS_FAR 0x19 5222 /* enum: PhyXS Wireside. */ 5223 #define MC_CMD_LOOPBACK_PHYXS_WS 0x1a 5224 /* enum: PMA lanes MAC-Serdes. */ 5225 #define MC_CMD_LOOPBACK_PMA_INT 0x1b 5226 /* enum: KR Serdes Parallel (Encoder). */ 5227 #define MC_CMD_LOOPBACK_SD_NEAR 0x1c 5228 /* enum: KR Serdes Serial. */ 5229 #define MC_CMD_LOOPBACK_SD_FAR 0x1d 5230 /* enum: PMA lanes MAC-Serdes Wireside. */ 5231 #define MC_CMD_LOOPBACK_PMA_INT_WS 0x1e 5232 /* enum: KR Serdes Parallel Wireside (Full PCS). */ 5233 #define MC_CMD_LOOPBACK_SD_FEP2_WS 0x1f 5234 /* enum: KR Serdes Parallel Wireside (Sym Aligner to TX). */ 5235 #define MC_CMD_LOOPBACK_SD_FEP1_5_WS 0x20 5236 /* enum: KR Serdes Parallel Wireside (Deserializer to Serializer). */ 5237 #define MC_CMD_LOOPBACK_SD_FEP_WS 0x21 5238 /* enum: KR Serdes Serial Wireside. */ 5239 #define MC_CMD_LOOPBACK_SD_FES_WS 0x22 5240 /* enum: Near side of AOE Siena side port */ 5241 #define MC_CMD_LOOPBACK_AOE_INT_NEAR 0x23 5242 /* enum: Medford Wireside datapath loopback */ 5243 #define MC_CMD_LOOPBACK_DATA_WS 0x24 5244 /* enum: Force link up without setting up any physical loopback (snapper use 5245 * only) 5246 */ 5247 #define MC_CMD_LOOPBACK_FORCE_EXT_LINK 0x25 5248 /* Supported loopbacks. */ 5249 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_OFST 8 5250 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LEN 8 5251 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LO_OFST 8 5252 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_HI_OFST 12 5253 /* Enum values, see field(s): */ 5254 /* 100M */ 5255 /* Supported loopbacks. */ 5256 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_OFST 16 5257 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LEN 8 5258 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LO_OFST 16 5259 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_HI_OFST 20 5260 /* Enum values, see field(s): */ 5261 /* 100M */ 5262 /* Supported loopbacks. */ 5263 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_OFST 24 5264 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LEN 8 5265 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LO_OFST 24 5266 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_HI_OFST 28 5267 /* Enum values, see field(s): */ 5268 /* 100M */ 5269 /* Supported loopbacks. */ 5270 #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_OFST 32 5271 #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LEN 8 5272 #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LO_OFST 32 5273 #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_HI_OFST 36 5274 /* Enum values, see field(s): */ 5275 /* 100M */ 5276 5277 5278 /***********************************/ 5279 /* MC_CMD_GET_LINK 5280 * Read the unified MAC/PHY link state. Locks required: None Return code: 0, 5281 * ETIME. 5282 */ 5283 #define MC_CMD_GET_LINK 0x29 5284 #undef MC_CMD_0x29_PRIVILEGE_CTG 5285 5286 #define MC_CMD_0x29_PRIVILEGE_CTG SRIOV_CTG_GENERAL 5287 5288 /* MC_CMD_GET_LINK_IN msgrequest */ 5289 #define MC_CMD_GET_LINK_IN_LEN 0 5290 5291 /* MC_CMD_GET_LINK_OUT msgresponse */ 5292 #define MC_CMD_GET_LINK_OUT_LEN 28 5293 /* near-side advertised capabilities */ 5294 #define MC_CMD_GET_LINK_OUT_CAP_OFST 0 5295 /* link-partner advertised capabilities */ 5296 #define MC_CMD_GET_LINK_OUT_LP_CAP_OFST 4 5297 /* Autonegotiated speed in mbit/s. The link may still be down even if this 5298 * reads non-zero. 5299 */ 5300 #define MC_CMD_GET_LINK_OUT_LINK_SPEED_OFST 8 5301 /* Current loopback setting. */ 5302 #define MC_CMD_GET_LINK_OUT_LOOPBACK_MODE_OFST 12 5303 /* Enum values, see field(s): */ 5304 /* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */ 5305 #define MC_CMD_GET_LINK_OUT_FLAGS_OFST 16 5306 #define MC_CMD_GET_LINK_OUT_LINK_UP_LBN 0 5307 #define MC_CMD_GET_LINK_OUT_LINK_UP_WIDTH 1 5308 #define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_LBN 1 5309 #define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_WIDTH 1 5310 #define MC_CMD_GET_LINK_OUT_BPX_LINK_LBN 2 5311 #define MC_CMD_GET_LINK_OUT_BPX_LINK_WIDTH 1 5312 #define MC_CMD_GET_LINK_OUT_PHY_LINK_LBN 3 5313 #define MC_CMD_GET_LINK_OUT_PHY_LINK_WIDTH 1 5314 #define MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_LBN 6 5315 #define MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_WIDTH 1 5316 #define MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_LBN 7 5317 #define MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_WIDTH 1 5318 /* This returns the negotiated flow control value. */ 5319 #define MC_CMD_GET_LINK_OUT_FCNTL_OFST 20 5320 /* Enum values, see field(s): */ 5321 /* MC_CMD_SET_MAC/MC_CMD_SET_MAC_IN/FCNTL */ 5322 #define MC_CMD_GET_LINK_OUT_MAC_FAULT_OFST 24 5323 #define MC_CMD_MAC_FAULT_XGMII_LOCAL_LBN 0 5324 #define MC_CMD_MAC_FAULT_XGMII_LOCAL_WIDTH 1 5325 #define MC_CMD_MAC_FAULT_XGMII_REMOTE_LBN 1 5326 #define MC_CMD_MAC_FAULT_XGMII_REMOTE_WIDTH 1 5327 #define MC_CMD_MAC_FAULT_SGMII_REMOTE_LBN 2 5328 #define MC_CMD_MAC_FAULT_SGMII_REMOTE_WIDTH 1 5329 #define MC_CMD_MAC_FAULT_PENDING_RECONFIG_LBN 3 5330 #define MC_CMD_MAC_FAULT_PENDING_RECONFIG_WIDTH 1 5331 5332 5333 /***********************************/ 5334 /* MC_CMD_SET_LINK 5335 * Write the unified MAC/PHY link configuration. Locks required: None. Return 5336 * code: 0, EINVAL, ETIME 5337 */ 5338 #define MC_CMD_SET_LINK 0x2a 5339 #undef MC_CMD_0x2a_PRIVILEGE_CTG 5340 5341 #define MC_CMD_0x2a_PRIVILEGE_CTG SRIOV_CTG_LINK 5342 5343 /* MC_CMD_SET_LINK_IN msgrequest */ 5344 #define MC_CMD_SET_LINK_IN_LEN 16 5345 /* ??? */ 5346 #define MC_CMD_SET_LINK_IN_CAP_OFST 0 5347 /* Flags */ 5348 #define MC_CMD_SET_LINK_IN_FLAGS_OFST 4 5349 #define MC_CMD_SET_LINK_IN_LOWPOWER_LBN 0 5350 #define MC_CMD_SET_LINK_IN_LOWPOWER_WIDTH 1 5351 #define MC_CMD_SET_LINK_IN_POWEROFF_LBN 1 5352 #define MC_CMD_SET_LINK_IN_POWEROFF_WIDTH 1 5353 #define MC_CMD_SET_LINK_IN_TXDIS_LBN 2 5354 #define MC_CMD_SET_LINK_IN_TXDIS_WIDTH 1 5355 /* Loopback mode. */ 5356 #define MC_CMD_SET_LINK_IN_LOOPBACK_MODE_OFST 8 5357 /* Enum values, see field(s): */ 5358 /* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */ 5359 /* A loopback speed of "0" is supported, and means (choose any available 5360 * speed). 5361 */ 5362 #define MC_CMD_SET_LINK_IN_LOOPBACK_SPEED_OFST 12 5363 5364 /* MC_CMD_SET_LINK_OUT msgresponse */ 5365 #define MC_CMD_SET_LINK_OUT_LEN 0 5366 5367 5368 /***********************************/ 5369 /* MC_CMD_SET_ID_LED 5370 * Set identification LED state. Locks required: None. Return code: 0, EINVAL 5371 */ 5372 #define MC_CMD_SET_ID_LED 0x2b 5373 #undef MC_CMD_0x2b_PRIVILEGE_CTG 5374 5375 #define MC_CMD_0x2b_PRIVILEGE_CTG SRIOV_CTG_LINK 5376 5377 /* MC_CMD_SET_ID_LED_IN msgrequest */ 5378 #define MC_CMD_SET_ID_LED_IN_LEN 4 5379 /* Set LED state. */ 5380 #define MC_CMD_SET_ID_LED_IN_STATE_OFST 0 5381 #define MC_CMD_LED_OFF 0x0 /* enum */ 5382 #define MC_CMD_LED_ON 0x1 /* enum */ 5383 #define MC_CMD_LED_DEFAULT 0x2 /* enum */ 5384 5385 /* MC_CMD_SET_ID_LED_OUT msgresponse */ 5386 #define MC_CMD_SET_ID_LED_OUT_LEN 0 5387 5388 5389 /***********************************/ 5390 /* MC_CMD_SET_MAC 5391 * Set MAC configuration. Locks required: None. Return code: 0, EINVAL 5392 */ 5393 #define MC_CMD_SET_MAC 0x2c 5394 #undef MC_CMD_0x2c_PRIVILEGE_CTG 5395 5396 #define MC_CMD_0x2c_PRIVILEGE_CTG SRIOV_CTG_GENERAL 5397 5398 /* MC_CMD_SET_MAC_IN msgrequest */ 5399 #define MC_CMD_SET_MAC_IN_LEN 28 5400 /* The MTU is the MTU programmed directly into the XMAC/GMAC (inclusive of 5401 * EtherII, VLAN, bug16011 padding). 5402 */ 5403 #define MC_CMD_SET_MAC_IN_MTU_OFST 0 5404 #define MC_CMD_SET_MAC_IN_DRAIN_OFST 4 5405 #define MC_CMD_SET_MAC_IN_ADDR_OFST 8 5406 #define MC_CMD_SET_MAC_IN_ADDR_LEN 8 5407 #define MC_CMD_SET_MAC_IN_ADDR_LO_OFST 8 5408 #define MC_CMD_SET_MAC_IN_ADDR_HI_OFST 12 5409 #define MC_CMD_SET_MAC_IN_REJECT_OFST 16 5410 #define MC_CMD_SET_MAC_IN_REJECT_UNCST_LBN 0 5411 #define MC_CMD_SET_MAC_IN_REJECT_UNCST_WIDTH 1 5412 #define MC_CMD_SET_MAC_IN_REJECT_BRDCST_LBN 1 5413 #define MC_CMD_SET_MAC_IN_REJECT_BRDCST_WIDTH 1 5414 #define MC_CMD_SET_MAC_IN_FCNTL_OFST 20 5415 /* enum: Flow control is off. */ 5416 #define MC_CMD_FCNTL_OFF 0x0 5417 /* enum: Respond to flow control. */ 5418 #define MC_CMD_FCNTL_RESPOND 0x1 5419 /* enum: Respond to and Issue flow control. */ 5420 #define MC_CMD_FCNTL_BIDIR 0x2 5421 /* enum: Auto neg flow control. */ 5422 #define MC_CMD_FCNTL_AUTO 0x3 5423 /* enum: Priority flow control (eftest builds only). */ 5424 #define MC_CMD_FCNTL_QBB 0x4 5425 /* enum: Issue flow control. */ 5426 #define MC_CMD_FCNTL_GENERATE 0x5 5427 #define MC_CMD_SET_MAC_IN_FLAGS_OFST 24 5428 #define MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_LBN 0 5429 #define MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_WIDTH 1 5430 5431 /* MC_CMD_SET_MAC_EXT_IN msgrequest */ 5432 #define MC_CMD_SET_MAC_EXT_IN_LEN 32 5433 /* The MTU is the MTU programmed directly into the XMAC/GMAC (inclusive of 5434 * EtherII, VLAN, bug16011 padding). 5435 */ 5436 #define MC_CMD_SET_MAC_EXT_IN_MTU_OFST 0 5437 #define MC_CMD_SET_MAC_EXT_IN_DRAIN_OFST 4 5438 #define MC_CMD_SET_MAC_EXT_IN_ADDR_OFST 8 5439 #define MC_CMD_SET_MAC_EXT_IN_ADDR_LEN 8 5440 #define MC_CMD_SET_MAC_EXT_IN_ADDR_LO_OFST 8 5441 #define MC_CMD_SET_MAC_EXT_IN_ADDR_HI_OFST 12 5442 #define MC_CMD_SET_MAC_EXT_IN_REJECT_OFST 16 5443 #define MC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_LBN 0 5444 #define MC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_WIDTH 1 5445 #define MC_CMD_SET_MAC_EXT_IN_REJECT_BRDCST_LBN 1 5446 #define MC_CMD_SET_MAC_EXT_IN_REJECT_BRDCST_WIDTH 1 5447 #define MC_CMD_SET_MAC_EXT_IN_FCNTL_OFST 20 5448 /* enum: Flow control is off. */ 5449 /* MC_CMD_FCNTL_OFF 0x0 */ 5450 /* enum: Respond to flow control. */ 5451 /* MC_CMD_FCNTL_RESPOND 0x1 */ 5452 /* enum: Respond to and Issue flow control. */ 5453 /* MC_CMD_FCNTL_BIDIR 0x2 */ 5454 /* enum: Auto neg flow control. */ 5455 /* MC_CMD_FCNTL_AUTO 0x3 */ 5456 /* enum: Priority flow control (eftest builds only). */ 5457 /* MC_CMD_FCNTL_QBB 0x4 */ 5458 /* enum: Issue flow control. */ 5459 /* MC_CMD_FCNTL_GENERATE 0x5 */ 5460 #define MC_CMD_SET_MAC_EXT_IN_FLAGS_OFST 24 5461 #define MC_CMD_SET_MAC_EXT_IN_FLAG_INCLUDE_FCS_LBN 0 5462 #define MC_CMD_SET_MAC_EXT_IN_FLAG_INCLUDE_FCS_WIDTH 1 5463 /* Select which parameters to configure. A parameter will only be modified if 5464 * the corresponding control flag is set. If SET_MAC_ENHANCED is not set in 5465 * capabilities then this field is ignored (and all flags are assumed to be 5466 * set). 5467 */ 5468 #define MC_CMD_SET_MAC_EXT_IN_CONTROL_OFST 28 5469 #define MC_CMD_SET_MAC_EXT_IN_CFG_MTU_LBN 0 5470 #define MC_CMD_SET_MAC_EXT_IN_CFG_MTU_WIDTH 1 5471 #define MC_CMD_SET_MAC_EXT_IN_CFG_DRAIN_LBN 1 5472 #define MC_CMD_SET_MAC_EXT_IN_CFG_DRAIN_WIDTH 1 5473 #define MC_CMD_SET_MAC_EXT_IN_CFG_REJECT_LBN 2 5474 #define MC_CMD_SET_MAC_EXT_IN_CFG_REJECT_WIDTH 1 5475 #define MC_CMD_SET_MAC_EXT_IN_CFG_FCNTL_LBN 3 5476 #define MC_CMD_SET_MAC_EXT_IN_CFG_FCNTL_WIDTH 1 5477 #define MC_CMD_SET_MAC_EXT_IN_CFG_FCS_LBN 4 5478 #define MC_CMD_SET_MAC_EXT_IN_CFG_FCS_WIDTH 1 5479 5480 /* MC_CMD_SET_MAC_OUT msgresponse */ 5481 #define MC_CMD_SET_MAC_OUT_LEN 0 5482 5483 5484 /***********************************/ 5485 /* MC_CMD_PHY_STATS 5486 * Get generic PHY statistics. This call returns the statistics for a generic 5487 * PHY in a sparse array (indexed by the enumerate). Each value is represented 5488 * by a 32bit number. If the DMA_ADDR is 0, then no DMA is performed, and the 5489 * statistics may be read from the message response. If DMA_ADDR != 0, then the 5490 * statistics are dmad to that (page-aligned location). Locks required: None. 5491 * Returns: 0, ETIME 5492 */ 5493 #define MC_CMD_PHY_STATS 0x2d 5494 #undef MC_CMD_0x2d_PRIVILEGE_CTG 5495 5496 #define MC_CMD_0x2d_PRIVILEGE_CTG SRIOV_CTG_LINK 5497 5498 /* MC_CMD_PHY_STATS_IN msgrequest */ 5499 #define MC_CMD_PHY_STATS_IN_LEN 8 5500 /* ??? */ 5501 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_OFST 0 5502 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_LEN 8 5503 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_OFST 0 5504 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_HI_OFST 4 5505 5506 /* MC_CMD_PHY_STATS_OUT_DMA msgresponse */ 5507 #define MC_CMD_PHY_STATS_OUT_DMA_LEN 0 5508 5509 /* MC_CMD_PHY_STATS_OUT_NO_DMA msgresponse */ 5510 #define MC_CMD_PHY_STATS_OUT_NO_DMA_LEN (((MC_CMD_PHY_NSTATS*32))>>3) 5511 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_OFST 0 5512 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_LEN 4 5513 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_PHY_NSTATS 5514 /* enum: OUI. */ 5515 #define MC_CMD_OUI 0x0 5516 /* enum: PMA-PMD Link Up. */ 5517 #define MC_CMD_PMA_PMD_LINK_UP 0x1 5518 /* enum: PMA-PMD RX Fault. */ 5519 #define MC_CMD_PMA_PMD_RX_FAULT 0x2 5520 /* enum: PMA-PMD TX Fault. */ 5521 #define MC_CMD_PMA_PMD_TX_FAULT 0x3 5522 /* enum: PMA-PMD Signal */ 5523 #define MC_CMD_PMA_PMD_SIGNAL 0x4 5524 /* enum: PMA-PMD SNR A. */ 5525 #define MC_CMD_PMA_PMD_SNR_A 0x5 5526 /* enum: PMA-PMD SNR B. */ 5527 #define MC_CMD_PMA_PMD_SNR_B 0x6 5528 /* enum: PMA-PMD SNR C. */ 5529 #define MC_CMD_PMA_PMD_SNR_C 0x7 5530 /* enum: PMA-PMD SNR D. */ 5531 #define MC_CMD_PMA_PMD_SNR_D 0x8 5532 /* enum: PCS Link Up. */ 5533 #define MC_CMD_PCS_LINK_UP 0x9 5534 /* enum: PCS RX Fault. */ 5535 #define MC_CMD_PCS_RX_FAULT 0xa 5536 /* enum: PCS TX Fault. */ 5537 #define MC_CMD_PCS_TX_FAULT 0xb 5538 /* enum: PCS BER. */ 5539 #define MC_CMD_PCS_BER 0xc 5540 /* enum: PCS Block Errors. */ 5541 #define MC_CMD_PCS_BLOCK_ERRORS 0xd 5542 /* enum: PhyXS Link Up. */ 5543 #define MC_CMD_PHYXS_LINK_UP 0xe 5544 /* enum: PhyXS RX Fault. */ 5545 #define MC_CMD_PHYXS_RX_FAULT 0xf 5546 /* enum: PhyXS TX Fault. */ 5547 #define MC_CMD_PHYXS_TX_FAULT 0x10 5548 /* enum: PhyXS Align. */ 5549 #define MC_CMD_PHYXS_ALIGN 0x11 5550 /* enum: PhyXS Sync. */ 5551 #define MC_CMD_PHYXS_SYNC 0x12 5552 /* enum: AN link-up. */ 5553 #define MC_CMD_AN_LINK_UP 0x13 5554 /* enum: AN Complete. */ 5555 #define MC_CMD_AN_COMPLETE 0x14 5556 /* enum: AN 10GBaseT Status. */ 5557 #define MC_CMD_AN_10GBT_STATUS 0x15 5558 /* enum: Clause 22 Link-Up. */ 5559 #define MC_CMD_CL22_LINK_UP 0x16 5560 /* enum: (Last entry) */ 5561 #define MC_CMD_PHY_NSTATS 0x17 5562 5563 5564 /***********************************/ 5565 /* MC_CMD_MAC_STATS 5566 * Get generic MAC statistics. This call returns unified statistics maintained 5567 * by the MC as it switches between the GMAC and XMAC. The MC will write out 5568 * all supported stats. The driver should zero initialise the buffer to 5569 * guarantee consistent results. If the DMA_ADDR is 0, then no DMA is 5570 * performed, and the statistics may be read from the message response. If 5571 * DMA_ADDR != 0, then the statistics are dmad to that (page-aligned location). 5572 * Locks required: None. The PERIODIC_CLEAR option is not used and now has no 5573 * effect. Returns: 0, ETIME 5574 */ 5575 #define MC_CMD_MAC_STATS 0x2e 5576 #undef MC_CMD_0x2e_PRIVILEGE_CTG 5577 5578 #define MC_CMD_0x2e_PRIVILEGE_CTG SRIOV_CTG_GENERAL 5579 5580 /* MC_CMD_MAC_STATS_IN msgrequest */ 5581 #define MC_CMD_MAC_STATS_IN_LEN 20 5582 /* ??? */ 5583 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_OFST 0 5584 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_LEN 8 5585 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_OFST 0 5586 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_OFST 4 5587 #define MC_CMD_MAC_STATS_IN_CMD_OFST 8 5588 #define MC_CMD_MAC_STATS_IN_DMA_LBN 0 5589 #define MC_CMD_MAC_STATS_IN_DMA_WIDTH 1 5590 #define MC_CMD_MAC_STATS_IN_CLEAR_LBN 1 5591 #define MC_CMD_MAC_STATS_IN_CLEAR_WIDTH 1 5592 #define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_LBN 2 5593 #define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_WIDTH 1 5594 #define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_LBN 3 5595 #define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_WIDTH 1 5596 #define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_LBN 4 5597 #define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_WIDTH 1 5598 #define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_LBN 5 5599 #define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_WIDTH 1 5600 #define MC_CMD_MAC_STATS_IN_PERIOD_MS_LBN 16 5601 #define MC_CMD_MAC_STATS_IN_PERIOD_MS_WIDTH 16 5602 #define MC_CMD_MAC_STATS_IN_DMA_LEN_OFST 12 5603 /* port id so vadapter stats can be provided */ 5604 #define MC_CMD_MAC_STATS_IN_PORT_ID_OFST 16 5605 5606 /* MC_CMD_MAC_STATS_OUT_DMA msgresponse */ 5607 #define MC_CMD_MAC_STATS_OUT_DMA_LEN 0 5608 5609 /* MC_CMD_MAC_STATS_OUT_NO_DMA msgresponse */ 5610 #define MC_CMD_MAC_STATS_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS*64))>>3) 5611 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_OFST 0 5612 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LEN 8 5613 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_OFST 0 5614 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_OFST 4 5615 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS 5616 #define MC_CMD_MAC_GENERATION_START 0x0 /* enum */ 5617 #define MC_CMD_MAC_DMABUF_START 0x1 /* enum */ 5618 #define MC_CMD_MAC_TX_PKTS 0x1 /* enum */ 5619 #define MC_CMD_MAC_TX_PAUSE_PKTS 0x2 /* enum */ 5620 #define MC_CMD_MAC_TX_CONTROL_PKTS 0x3 /* enum */ 5621 #define MC_CMD_MAC_TX_UNICAST_PKTS 0x4 /* enum */ 5622 #define MC_CMD_MAC_TX_MULTICAST_PKTS 0x5 /* enum */ 5623 #define MC_CMD_MAC_TX_BROADCAST_PKTS 0x6 /* enum */ 5624 #define MC_CMD_MAC_TX_BYTES 0x7 /* enum */ 5625 #define MC_CMD_MAC_TX_BAD_BYTES 0x8 /* enum */ 5626 #define MC_CMD_MAC_TX_LT64_PKTS 0x9 /* enum */ 5627 #define MC_CMD_MAC_TX_64_PKTS 0xa /* enum */ 5628 #define MC_CMD_MAC_TX_65_TO_127_PKTS 0xb /* enum */ 5629 #define MC_CMD_MAC_TX_128_TO_255_PKTS 0xc /* enum */ 5630 #define MC_CMD_MAC_TX_256_TO_511_PKTS 0xd /* enum */ 5631 #define MC_CMD_MAC_TX_512_TO_1023_PKTS 0xe /* enum */ 5632 #define MC_CMD_MAC_TX_1024_TO_15XX_PKTS 0xf /* enum */ 5633 #define MC_CMD_MAC_TX_15XX_TO_JUMBO_PKTS 0x10 /* enum */ 5634 #define MC_CMD_MAC_TX_GTJUMBO_PKTS 0x11 /* enum */ 5635 #define MC_CMD_MAC_TX_BAD_FCS_PKTS 0x12 /* enum */ 5636 #define MC_CMD_MAC_TX_SINGLE_COLLISION_PKTS 0x13 /* enum */ 5637 #define MC_CMD_MAC_TX_MULTIPLE_COLLISION_PKTS 0x14 /* enum */ 5638 #define MC_CMD_MAC_TX_EXCESSIVE_COLLISION_PKTS 0x15 /* enum */ 5639 #define MC_CMD_MAC_TX_LATE_COLLISION_PKTS 0x16 /* enum */ 5640 #define MC_CMD_MAC_TX_DEFERRED_PKTS 0x17 /* enum */ 5641 #define MC_CMD_MAC_TX_EXCESSIVE_DEFERRED_PKTS 0x18 /* enum */ 5642 #define MC_CMD_MAC_TX_NON_TCPUDP_PKTS 0x19 /* enum */ 5643 #define MC_CMD_MAC_TX_MAC_SRC_ERR_PKTS 0x1a /* enum */ 5644 #define MC_CMD_MAC_TX_IP_SRC_ERR_PKTS 0x1b /* enum */ 5645 #define MC_CMD_MAC_RX_PKTS 0x1c /* enum */ 5646 #define MC_CMD_MAC_RX_PAUSE_PKTS 0x1d /* enum */ 5647 #define MC_CMD_MAC_RX_GOOD_PKTS 0x1e /* enum */ 5648 #define MC_CMD_MAC_RX_CONTROL_PKTS 0x1f /* enum */ 5649 #define MC_CMD_MAC_RX_UNICAST_PKTS 0x20 /* enum */ 5650 #define MC_CMD_MAC_RX_MULTICAST_PKTS 0x21 /* enum */ 5651 #define MC_CMD_MAC_RX_BROADCAST_PKTS 0x22 /* enum */ 5652 #define MC_CMD_MAC_RX_BYTES 0x23 /* enum */ 5653 #define MC_CMD_MAC_RX_BAD_BYTES 0x24 /* enum */ 5654 #define MC_CMD_MAC_RX_64_PKTS 0x25 /* enum */ 5655 #define MC_CMD_MAC_RX_65_TO_127_PKTS 0x26 /* enum */ 5656 #define MC_CMD_MAC_RX_128_TO_255_PKTS 0x27 /* enum */ 5657 #define MC_CMD_MAC_RX_256_TO_511_PKTS 0x28 /* enum */ 5658 #define MC_CMD_MAC_RX_512_TO_1023_PKTS 0x29 /* enum */ 5659 #define MC_CMD_MAC_RX_1024_TO_15XX_PKTS 0x2a /* enum */ 5660 #define MC_CMD_MAC_RX_15XX_TO_JUMBO_PKTS 0x2b /* enum */ 5661 #define MC_CMD_MAC_RX_GTJUMBO_PKTS 0x2c /* enum */ 5662 #define MC_CMD_MAC_RX_UNDERSIZE_PKTS 0x2d /* enum */ 5663 #define MC_CMD_MAC_RX_BAD_FCS_PKTS 0x2e /* enum */ 5664 #define MC_CMD_MAC_RX_OVERFLOW_PKTS 0x2f /* enum */ 5665 #define MC_CMD_MAC_RX_FALSE_CARRIER_PKTS 0x30 /* enum */ 5666 #define MC_CMD_MAC_RX_SYMBOL_ERROR_PKTS 0x31 /* enum */ 5667 #define MC_CMD_MAC_RX_ALIGN_ERROR_PKTS 0x32 /* enum */ 5668 #define MC_CMD_MAC_RX_LENGTH_ERROR_PKTS 0x33 /* enum */ 5669 #define MC_CMD_MAC_RX_INTERNAL_ERROR_PKTS 0x34 /* enum */ 5670 #define MC_CMD_MAC_RX_JABBER_PKTS 0x35 /* enum */ 5671 #define MC_CMD_MAC_RX_NODESC_DROPS 0x36 /* enum */ 5672 #define MC_CMD_MAC_RX_LANES01_CHAR_ERR 0x37 /* enum */ 5673 #define MC_CMD_MAC_RX_LANES23_CHAR_ERR 0x38 /* enum */ 5674 #define MC_CMD_MAC_RX_LANES01_DISP_ERR 0x39 /* enum */ 5675 #define MC_CMD_MAC_RX_LANES23_DISP_ERR 0x3a /* enum */ 5676 #define MC_CMD_MAC_RX_MATCH_FAULT 0x3b /* enum */ 5677 /* enum: PM trunc_bb_overflow counter. Valid for EF10 with PM_AND_RXDP_COUNTERS 5678 * capability only. 5679 */ 5680 #define MC_CMD_MAC_PM_TRUNC_BB_OVERFLOW 0x3c 5681 /* enum: PM discard_bb_overflow counter. Valid for EF10 with 5682 * PM_AND_RXDP_COUNTERS capability only. 5683 */ 5684 #define MC_CMD_MAC_PM_DISCARD_BB_OVERFLOW 0x3d 5685 /* enum: PM trunc_vfifo_full counter. Valid for EF10 with PM_AND_RXDP_COUNTERS 5686 * capability only. 5687 */ 5688 #define MC_CMD_MAC_PM_TRUNC_VFIFO_FULL 0x3e 5689 /* enum: PM discard_vfifo_full counter. Valid for EF10 with 5690 * PM_AND_RXDP_COUNTERS capability only. 5691 */ 5692 #define MC_CMD_MAC_PM_DISCARD_VFIFO_FULL 0x3f 5693 /* enum: PM trunc_qbb counter. Valid for EF10 with PM_AND_RXDP_COUNTERS 5694 * capability only. 5695 */ 5696 #define MC_CMD_MAC_PM_TRUNC_QBB 0x40 5697 /* enum: PM discard_qbb counter. Valid for EF10 with PM_AND_RXDP_COUNTERS 5698 * capability only. 5699 */ 5700 #define MC_CMD_MAC_PM_DISCARD_QBB 0x41 5701 /* enum: PM discard_mapping counter. Valid for EF10 with PM_AND_RXDP_COUNTERS 5702 * capability only. 5703 */ 5704 #define MC_CMD_MAC_PM_DISCARD_MAPPING 0x42 5705 /* enum: RXDP counter: Number of packets dropped due to the queue being 5706 * disabled. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only. 5707 */ 5708 #define MC_CMD_MAC_RXDP_Q_DISABLED_PKTS 0x43 5709 /* enum: RXDP counter: Number of packets dropped by the DICPU. Valid for EF10 5710 * with PM_AND_RXDP_COUNTERS capability only. 5711 */ 5712 #define MC_CMD_MAC_RXDP_DI_DROPPED_PKTS 0x45 5713 /* enum: RXDP counter: Number of non-host packets. Valid for EF10 with 5714 * PM_AND_RXDP_COUNTERS capability only. 5715 */ 5716 #define MC_CMD_MAC_RXDP_STREAMING_PKTS 0x46 5717 /* enum: RXDP counter: Number of times an hlb descriptor fetch was performed. 5718 * Valid for EF10 with PM_AND_RXDP_COUNTERS capability only. 5719 */ 5720 #define MC_CMD_MAC_RXDP_HLB_FETCH_CONDITIONS 0x47 5721 /* enum: RXDP counter: Number of times the DPCPU waited for an existing 5722 * descriptor fetch. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only. 5723 */ 5724 #define MC_CMD_MAC_RXDP_HLB_WAIT_CONDITIONS 0x48 5725 #define MC_CMD_MAC_VADAPTER_RX_DMABUF_START 0x4c /* enum */ 5726 #define MC_CMD_MAC_VADAPTER_RX_UNICAST_PACKETS 0x4c /* enum */ 5727 #define MC_CMD_MAC_VADAPTER_RX_UNICAST_BYTES 0x4d /* enum */ 5728 #define MC_CMD_MAC_VADAPTER_RX_MULTICAST_PACKETS 0x4e /* enum */ 5729 #define MC_CMD_MAC_VADAPTER_RX_MULTICAST_BYTES 0x4f /* enum */ 5730 #define MC_CMD_MAC_VADAPTER_RX_BROADCAST_PACKETS 0x50 /* enum */ 5731 #define MC_CMD_MAC_VADAPTER_RX_BROADCAST_BYTES 0x51 /* enum */ 5732 #define MC_CMD_MAC_VADAPTER_RX_BAD_PACKETS 0x52 /* enum */ 5733 #define MC_CMD_MAC_VADAPTER_RX_BAD_BYTES 0x53 /* enum */ 5734 #define MC_CMD_MAC_VADAPTER_RX_OVERFLOW 0x54 /* enum */ 5735 #define MC_CMD_MAC_VADAPTER_TX_DMABUF_START 0x57 /* enum */ 5736 #define MC_CMD_MAC_VADAPTER_TX_UNICAST_PACKETS 0x57 /* enum */ 5737 #define MC_CMD_MAC_VADAPTER_TX_UNICAST_BYTES 0x58 /* enum */ 5738 #define MC_CMD_MAC_VADAPTER_TX_MULTICAST_PACKETS 0x59 /* enum */ 5739 #define MC_CMD_MAC_VADAPTER_TX_MULTICAST_BYTES 0x5a /* enum */ 5740 #define MC_CMD_MAC_VADAPTER_TX_BROADCAST_PACKETS 0x5b /* enum */ 5741 #define MC_CMD_MAC_VADAPTER_TX_BROADCAST_BYTES 0x5c /* enum */ 5742 #define MC_CMD_MAC_VADAPTER_TX_BAD_PACKETS 0x5d /* enum */ 5743 #define MC_CMD_MAC_VADAPTER_TX_BAD_BYTES 0x5e /* enum */ 5744 #define MC_CMD_MAC_VADAPTER_TX_OVERFLOW 0x5f /* enum */ 5745 /* enum: Start of GMAC stats buffer space, for Siena only. */ 5746 #define MC_CMD_GMAC_DMABUF_START 0x40 5747 /* enum: End of GMAC stats buffer space, for Siena only. */ 5748 #define MC_CMD_GMAC_DMABUF_END 0x5f 5749 #define MC_CMD_MAC_GENERATION_END 0x60 /* enum */ 5750 #define MC_CMD_MAC_NSTATS 0x61 /* enum */ 5751 5752 5753 /***********************************/ 5754 /* MC_CMD_SRIOV 5755 * to be documented 5756 */ 5757 #define MC_CMD_SRIOV 0x30 5758 5759 /* MC_CMD_SRIOV_IN msgrequest */ 5760 #define MC_CMD_SRIOV_IN_LEN 12 5761 #define MC_CMD_SRIOV_IN_ENABLE_OFST 0 5762 #define MC_CMD_SRIOV_IN_VI_BASE_OFST 4 5763 #define MC_CMD_SRIOV_IN_VF_COUNT_OFST 8 5764 5765 /* MC_CMD_SRIOV_OUT msgresponse */ 5766 #define MC_CMD_SRIOV_OUT_LEN 8 5767 #define MC_CMD_SRIOV_OUT_VI_SCALE_OFST 0 5768 #define MC_CMD_SRIOV_OUT_VF_TOTAL_OFST 4 5769 5770 /* MC_CMD_MEMCPY_RECORD_TYPEDEF structuredef */ 5771 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LEN 32 5772 /* this is only used for the first record */ 5773 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_OFST 0 5774 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_LBN 0 5775 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_WIDTH 32 5776 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_OFST 4 5777 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_LBN 32 5778 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_WIDTH 32 5779 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_OFST 8 5780 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LEN 8 5781 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LO_OFST 8 5782 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_HI_OFST 12 5783 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LBN 64 5784 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_WIDTH 64 5785 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_OFST 16 5786 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_RID_INLINE 0x100 /* enum */ 5787 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_LBN 128 5788 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_WIDTH 32 5789 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_OFST 20 5790 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LEN 8 5791 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LO_OFST 20 5792 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_HI_OFST 24 5793 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LBN 160 5794 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_WIDTH 64 5795 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_OFST 28 5796 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_LBN 224 5797 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_WIDTH 32 5798 5799 5800 /***********************************/ 5801 /* MC_CMD_MEMCPY 5802 * DMA write data into (Rid,Addr), either by dma reading (Rid,Addr), or by data 5803 * embedded directly in the command. 5804 * 5805 * A common pattern is for a client to use generation counts to signal a dma 5806 * update of a datastructure. To facilitate this, this MCDI operation can 5807 * contain multiple requests which are executed in strict order. Requests take 5808 * the form of duplicating the entire MCDI request continuously (including the 5809 * requests record, which is ignored in all but the first structure) 5810 * 5811 * The source data can either come from a DMA from the host, or it can be 5812 * embedded within the request directly, thereby eliminating a DMA read. To 5813 * indicate this, the client sets FROM_RID=%RID_INLINE, ADDR_HI=0, and 5814 * ADDR_LO=offset, and inserts the data at %offset from the start of the 5815 * payload. It's the callers responsibility to ensure that the embedded data 5816 * doesn't overlap the records. 5817 * 5818 * Returns: 0, EINVAL (invalid RID) 5819 */ 5820 #define MC_CMD_MEMCPY 0x31 5821 5822 /* MC_CMD_MEMCPY_IN msgrequest */ 5823 #define MC_CMD_MEMCPY_IN_LENMIN 32 5824 #define MC_CMD_MEMCPY_IN_LENMAX 224 5825 #define MC_CMD_MEMCPY_IN_LEN(num) (0+32*(num)) 5826 /* see MC_CMD_MEMCPY_RECORD_TYPEDEF */ 5827 #define MC_CMD_MEMCPY_IN_RECORD_OFST 0 5828 #define MC_CMD_MEMCPY_IN_RECORD_LEN 32 5829 #define MC_CMD_MEMCPY_IN_RECORD_MINNUM 1 5830 #define MC_CMD_MEMCPY_IN_RECORD_MAXNUM 7 5831 5832 /* MC_CMD_MEMCPY_OUT msgresponse */ 5833 #define MC_CMD_MEMCPY_OUT_LEN 0 5834 5835 5836 /***********************************/ 5837 /* MC_CMD_WOL_FILTER_SET 5838 * Set a WoL filter. 5839 */ 5840 #define MC_CMD_WOL_FILTER_SET 0x32 5841 #undef MC_CMD_0x32_PRIVILEGE_CTG 5842 5843 #define MC_CMD_0x32_PRIVILEGE_CTG SRIOV_CTG_LINK 5844 5845 /* MC_CMD_WOL_FILTER_SET_IN msgrequest */ 5846 #define MC_CMD_WOL_FILTER_SET_IN_LEN 192 5847 #define MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 5848 #define MC_CMD_FILTER_MODE_SIMPLE 0x0 /* enum */ 5849 #define MC_CMD_FILTER_MODE_STRUCTURED 0xffffffff /* enum */ 5850 /* A type value of 1 is unused. */ 5851 #define MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 5852 /* enum: Magic */ 5853 #define MC_CMD_WOL_TYPE_MAGIC 0x0 5854 /* enum: MS Windows Magic */ 5855 #define MC_CMD_WOL_TYPE_WIN_MAGIC 0x2 5856 /* enum: IPv4 Syn */ 5857 #define MC_CMD_WOL_TYPE_IPV4_SYN 0x3 5858 /* enum: IPv6 Syn */ 5859 #define MC_CMD_WOL_TYPE_IPV6_SYN 0x4 5860 /* enum: Bitmap */ 5861 #define MC_CMD_WOL_TYPE_BITMAP 0x5 5862 /* enum: Link */ 5863 #define MC_CMD_WOL_TYPE_LINK 0x6 5864 /* enum: (Above this for future use) */ 5865 #define MC_CMD_WOL_TYPE_MAX 0x7 5866 #define MC_CMD_WOL_FILTER_SET_IN_DATA_OFST 8 5867 #define MC_CMD_WOL_FILTER_SET_IN_DATA_LEN 4 5868 #define MC_CMD_WOL_FILTER_SET_IN_DATA_NUM 46 5869 5870 /* MC_CMD_WOL_FILTER_SET_IN_MAGIC msgrequest */ 5871 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_LEN 16 5872 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 5873 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 5874 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_OFST 8 5875 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LEN 8 5876 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LO_OFST 8 5877 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_HI_OFST 12 5878 5879 /* MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN msgrequest */ 5880 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_LEN 20 5881 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 5882 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 5883 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_IP_OFST 8 5884 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_IP_OFST 12 5885 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_OFST 16 5886 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_LEN 2 5887 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_OFST 18 5888 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_LEN 2 5889 5890 /* MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN msgrequest */ 5891 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_LEN 44 5892 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 5893 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 5894 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_OFST 8 5895 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_LEN 16 5896 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_OFST 24 5897 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_LEN 16 5898 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_OFST 40 5899 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_LEN 2 5900 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_OFST 42 5901 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_LEN 2 5902 5903 /* MC_CMD_WOL_FILTER_SET_IN_BITMAP msgrequest */ 5904 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN 187 5905 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 5906 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 5907 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_OFST 8 5908 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_LEN 48 5909 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_OFST 56 5910 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_LEN 128 5911 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_OFST 184 5912 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_LEN 1 5913 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_OFST 185 5914 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_LEN 1 5915 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_OFST 186 5916 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_LEN 1 5917 5918 /* MC_CMD_WOL_FILTER_SET_IN_LINK msgrequest */ 5919 #define MC_CMD_WOL_FILTER_SET_IN_LINK_LEN 12 5920 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 5921 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 5922 #define MC_CMD_WOL_FILTER_SET_IN_LINK_MASK_OFST 8 5923 #define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_LBN 0 5924 #define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_WIDTH 1 5925 #define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_LBN 1 5926 #define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_WIDTH 1 5927 5928 /* MC_CMD_WOL_FILTER_SET_OUT msgresponse */ 5929 #define MC_CMD_WOL_FILTER_SET_OUT_LEN 4 5930 #define MC_CMD_WOL_FILTER_SET_OUT_FILTER_ID_OFST 0 5931 5932 5933 /***********************************/ 5934 /* MC_CMD_WOL_FILTER_REMOVE 5935 * Remove a WoL filter. Locks required: None. Returns: 0, EINVAL, ENOSYS 5936 */ 5937 #define MC_CMD_WOL_FILTER_REMOVE 0x33 5938 #undef MC_CMD_0x33_PRIVILEGE_CTG 5939 5940 #define MC_CMD_0x33_PRIVILEGE_CTG SRIOV_CTG_LINK 5941 5942 /* MC_CMD_WOL_FILTER_REMOVE_IN msgrequest */ 5943 #define MC_CMD_WOL_FILTER_REMOVE_IN_LEN 4 5944 #define MC_CMD_WOL_FILTER_REMOVE_IN_FILTER_ID_OFST 0 5945 5946 /* MC_CMD_WOL_FILTER_REMOVE_OUT msgresponse */ 5947 #define MC_CMD_WOL_FILTER_REMOVE_OUT_LEN 0 5948 5949 5950 /***********************************/ 5951 /* MC_CMD_WOL_FILTER_RESET 5952 * Reset (i.e. remove all) WoL filters. Locks required: None. Returns: 0, 5953 * ENOSYS 5954 */ 5955 #define MC_CMD_WOL_FILTER_RESET 0x34 5956 #undef MC_CMD_0x34_PRIVILEGE_CTG 5957 5958 #define MC_CMD_0x34_PRIVILEGE_CTG SRIOV_CTG_LINK 5959 5960 /* MC_CMD_WOL_FILTER_RESET_IN msgrequest */ 5961 #define MC_CMD_WOL_FILTER_RESET_IN_LEN 4 5962 #define MC_CMD_WOL_FILTER_RESET_IN_MASK_OFST 0 5963 #define MC_CMD_WOL_FILTER_RESET_IN_WAKE_FILTERS 0x1 /* enum */ 5964 #define MC_CMD_WOL_FILTER_RESET_IN_LIGHTSOUT_OFFLOADS 0x2 /* enum */ 5965 5966 /* MC_CMD_WOL_FILTER_RESET_OUT msgresponse */ 5967 #define MC_CMD_WOL_FILTER_RESET_OUT_LEN 0 5968 5969 5970 /***********************************/ 5971 /* MC_CMD_SET_MCAST_HASH 5972 * Set the MCAST hash value without otherwise reconfiguring the MAC 5973 */ 5974 #define MC_CMD_SET_MCAST_HASH 0x35 5975 5976 /* MC_CMD_SET_MCAST_HASH_IN msgrequest */ 5977 #define MC_CMD_SET_MCAST_HASH_IN_LEN 32 5978 #define MC_CMD_SET_MCAST_HASH_IN_HASH0_OFST 0 5979 #define MC_CMD_SET_MCAST_HASH_IN_HASH0_LEN 16 5980 #define MC_CMD_SET_MCAST_HASH_IN_HASH1_OFST 16 5981 #define MC_CMD_SET_MCAST_HASH_IN_HASH1_LEN 16 5982 5983 /* MC_CMD_SET_MCAST_HASH_OUT msgresponse */ 5984 #define MC_CMD_SET_MCAST_HASH_OUT_LEN 0 5985 5986 5987 /***********************************/ 5988 /* MC_CMD_NVRAM_TYPES 5989 * Return bitfield indicating available types of virtual NVRAM partitions. 5990 * Locks required: none. Returns: 0 5991 */ 5992 #define MC_CMD_NVRAM_TYPES 0x36 5993 #undef MC_CMD_0x36_PRIVILEGE_CTG 5994 5995 #define MC_CMD_0x36_PRIVILEGE_CTG SRIOV_CTG_ADMIN 5996 5997 /* MC_CMD_NVRAM_TYPES_IN msgrequest */ 5998 #define MC_CMD_NVRAM_TYPES_IN_LEN 0 5999 6000 /* MC_CMD_NVRAM_TYPES_OUT msgresponse */ 6001 #define MC_CMD_NVRAM_TYPES_OUT_LEN 4 6002 /* Bit mask of supported types. */ 6003 #define MC_CMD_NVRAM_TYPES_OUT_TYPES_OFST 0 6004 /* enum: Disabled callisto. */ 6005 #define MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO 0x0 6006 /* enum: MC firmware. */ 6007 #define MC_CMD_NVRAM_TYPE_MC_FW 0x1 6008 /* enum: MC backup firmware. */ 6009 #define MC_CMD_NVRAM_TYPE_MC_FW_BACKUP 0x2 6010 /* enum: Static configuration Port0. */ 6011 #define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0 0x3 6012 /* enum: Static configuration Port1. */ 6013 #define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1 0x4 6014 /* enum: Dynamic configuration Port0. */ 6015 #define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0 0x5 6016 /* enum: Dynamic configuration Port1. */ 6017 #define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1 0x6 6018 /* enum: Expansion Rom. */ 6019 #define MC_CMD_NVRAM_TYPE_EXP_ROM 0x7 6020 /* enum: Expansion Rom Configuration Port0. */ 6021 #define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0 0x8 6022 /* enum: Expansion Rom Configuration Port1. */ 6023 #define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1 0x9 6024 /* enum: Phy Configuration Port0. */ 6025 #define MC_CMD_NVRAM_TYPE_PHY_PORT0 0xa 6026 /* enum: Phy Configuration Port1. */ 6027 #define MC_CMD_NVRAM_TYPE_PHY_PORT1 0xb 6028 /* enum: Log. */ 6029 #define MC_CMD_NVRAM_TYPE_LOG 0xc 6030 /* enum: FPGA image. */ 6031 #define MC_CMD_NVRAM_TYPE_FPGA 0xd 6032 /* enum: FPGA backup image */ 6033 #define MC_CMD_NVRAM_TYPE_FPGA_BACKUP 0xe 6034 /* enum: FC firmware. */ 6035 #define MC_CMD_NVRAM_TYPE_FC_FW 0xf 6036 /* enum: FC backup firmware. */ 6037 #define MC_CMD_NVRAM_TYPE_FC_FW_BACKUP 0x10 6038 /* enum: CPLD image. */ 6039 #define MC_CMD_NVRAM_TYPE_CPLD 0x11 6040 /* enum: Licensing information. */ 6041 #define MC_CMD_NVRAM_TYPE_LICENSE 0x12 6042 /* enum: FC Log. */ 6043 #define MC_CMD_NVRAM_TYPE_FC_LOG 0x13 6044 /* enum: Additional flash on FPGA. */ 6045 #define MC_CMD_NVRAM_TYPE_FC_EXTRA 0x14 6046 6047 6048 /***********************************/ 6049 /* MC_CMD_NVRAM_INFO 6050 * Read info about a virtual NVRAM partition. Locks required: none. Returns: 0, 6051 * EINVAL (bad type). 6052 */ 6053 #define MC_CMD_NVRAM_INFO 0x37 6054 #undef MC_CMD_0x37_PRIVILEGE_CTG 6055 6056 #define MC_CMD_0x37_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6057 6058 /* MC_CMD_NVRAM_INFO_IN msgrequest */ 6059 #define MC_CMD_NVRAM_INFO_IN_LEN 4 6060 #define MC_CMD_NVRAM_INFO_IN_TYPE_OFST 0 6061 /* Enum values, see field(s): */ 6062 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 6063 6064 /* MC_CMD_NVRAM_INFO_OUT msgresponse */ 6065 #define MC_CMD_NVRAM_INFO_OUT_LEN 24 6066 #define MC_CMD_NVRAM_INFO_OUT_TYPE_OFST 0 6067 /* Enum values, see field(s): */ 6068 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 6069 #define MC_CMD_NVRAM_INFO_OUT_SIZE_OFST 4 6070 #define MC_CMD_NVRAM_INFO_OUT_ERASESIZE_OFST 8 6071 #define MC_CMD_NVRAM_INFO_OUT_FLAGS_OFST 12 6072 #define MC_CMD_NVRAM_INFO_OUT_PROTECTED_LBN 0 6073 #define MC_CMD_NVRAM_INFO_OUT_PROTECTED_WIDTH 1 6074 #define MC_CMD_NVRAM_INFO_OUT_TLV_LBN 1 6075 #define MC_CMD_NVRAM_INFO_OUT_TLV_WIDTH 1 6076 #define MC_CMD_NVRAM_INFO_OUT_A_B_LBN 7 6077 #define MC_CMD_NVRAM_INFO_OUT_A_B_WIDTH 1 6078 #define MC_CMD_NVRAM_INFO_OUT_PHYSDEV_OFST 16 6079 #define MC_CMD_NVRAM_INFO_OUT_PHYSADDR_OFST 20 6080 6081 /* MC_CMD_NVRAM_INFO_V2_OUT msgresponse */ 6082 #define MC_CMD_NVRAM_INFO_V2_OUT_LEN 28 6083 #define MC_CMD_NVRAM_INFO_V2_OUT_TYPE_OFST 0 6084 /* Enum values, see field(s): */ 6085 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 6086 #define MC_CMD_NVRAM_INFO_V2_OUT_SIZE_OFST 4 6087 #define MC_CMD_NVRAM_INFO_V2_OUT_ERASESIZE_OFST 8 6088 #define MC_CMD_NVRAM_INFO_V2_OUT_FLAGS_OFST 12 6089 #define MC_CMD_NVRAM_INFO_V2_OUT_PROTECTED_LBN 0 6090 #define MC_CMD_NVRAM_INFO_V2_OUT_PROTECTED_WIDTH 1 6091 #define MC_CMD_NVRAM_INFO_V2_OUT_TLV_LBN 1 6092 #define MC_CMD_NVRAM_INFO_V2_OUT_TLV_WIDTH 1 6093 #define MC_CMD_NVRAM_INFO_V2_OUT_A_B_LBN 7 6094 #define MC_CMD_NVRAM_INFO_V2_OUT_A_B_WIDTH 1 6095 #define MC_CMD_NVRAM_INFO_V2_OUT_PHYSDEV_OFST 16 6096 #define MC_CMD_NVRAM_INFO_V2_OUT_PHYSADDR_OFST 20 6097 /* Writes must be multiples of this size. Added to support the MUM on Sorrento. 6098 */ 6099 #define MC_CMD_NVRAM_INFO_V2_OUT_WRITESIZE_OFST 24 6100 6101 6102 /***********************************/ 6103 /* MC_CMD_NVRAM_UPDATE_START 6104 * Start a group of update operations on a virtual NVRAM partition. Locks 6105 * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad type), EACCES (if 6106 * PHY_LOCK required and not held). 6107 */ 6108 #define MC_CMD_NVRAM_UPDATE_START 0x38 6109 #undef MC_CMD_0x38_PRIVILEGE_CTG 6110 6111 #define MC_CMD_0x38_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6112 6113 /* MC_CMD_NVRAM_UPDATE_START_IN msgrequest */ 6114 #define MC_CMD_NVRAM_UPDATE_START_IN_LEN 4 6115 #define MC_CMD_NVRAM_UPDATE_START_IN_TYPE_OFST 0 6116 /* Enum values, see field(s): */ 6117 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 6118 6119 /* MC_CMD_NVRAM_UPDATE_START_OUT msgresponse */ 6120 #define MC_CMD_NVRAM_UPDATE_START_OUT_LEN 0 6121 6122 6123 /***********************************/ 6124 /* MC_CMD_NVRAM_READ 6125 * Read data from a virtual NVRAM partition. Locks required: PHY_LOCK if 6126 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if 6127 * PHY_LOCK required and not held) 6128 */ 6129 #define MC_CMD_NVRAM_READ 0x39 6130 #undef MC_CMD_0x39_PRIVILEGE_CTG 6131 6132 #define MC_CMD_0x39_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6133 6134 /* MC_CMD_NVRAM_READ_IN msgrequest */ 6135 #define MC_CMD_NVRAM_READ_IN_LEN 12 6136 #define MC_CMD_NVRAM_READ_IN_TYPE_OFST 0 6137 /* Enum values, see field(s): */ 6138 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 6139 #define MC_CMD_NVRAM_READ_IN_OFFSET_OFST 4 6140 /* amount to read in bytes */ 6141 #define MC_CMD_NVRAM_READ_IN_LENGTH_OFST 8 6142 6143 /* MC_CMD_NVRAM_READ_IN_V2 msgrequest */ 6144 #define MC_CMD_NVRAM_READ_IN_V2_LEN 16 6145 #define MC_CMD_NVRAM_READ_IN_V2_TYPE_OFST 0 6146 /* Enum values, see field(s): */ 6147 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 6148 #define MC_CMD_NVRAM_READ_IN_V2_OFFSET_OFST 4 6149 /* amount to read in bytes */ 6150 #define MC_CMD_NVRAM_READ_IN_V2_LENGTH_OFST 8 6151 /* Optional control info. If a partition is stored with an A/B versioning 6152 * scheme (i.e. in more than one physical partition in NVRAM) the host can set 6153 * this to control which underlying physical partition is used to read data 6154 * from. This allows it to perform a read-modify-write-verify with the write 6155 * lock continuously held by calling NVRAM_UPDATE_START, reading the old 6156 * contents using MODE=TARGET_CURRENT, overwriting the old partition and then 6157 * verifying by reading with MODE=TARGET_BACKUP. 6158 */ 6159 #define MC_CMD_NVRAM_READ_IN_V2_MODE_OFST 12 6160 /* enum: Same as omitting MODE: caller sees data in current partition unless it 6161 * holds the write lock in which case it sees data in the partition it is 6162 * updating. 6163 */ 6164 #define MC_CMD_NVRAM_READ_IN_V2_DEFAULT 0x0 6165 /* enum: Read from the current partition of an A/B pair, even if holding the 6166 * write lock. 6167 */ 6168 #define MC_CMD_NVRAM_READ_IN_V2_TARGET_CURRENT 0x1 6169 /* enum: Read from the non-current (i.e. to be updated) partition of an A/B 6170 * pair 6171 */ 6172 #define MC_CMD_NVRAM_READ_IN_V2_TARGET_BACKUP 0x2 6173 6174 /* MC_CMD_NVRAM_READ_OUT msgresponse */ 6175 #define MC_CMD_NVRAM_READ_OUT_LENMIN 1 6176 #define MC_CMD_NVRAM_READ_OUT_LENMAX 252 6177 #define MC_CMD_NVRAM_READ_OUT_LEN(num) (0+1*(num)) 6178 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_OFST 0 6179 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_LEN 1 6180 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MINNUM 1 6181 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MAXNUM 252 6182 6183 6184 /***********************************/ 6185 /* MC_CMD_NVRAM_WRITE 6186 * Write data to a virtual NVRAM partition. Locks required: PHY_LOCK if 6187 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if 6188 * PHY_LOCK required and not held) 6189 */ 6190 #define MC_CMD_NVRAM_WRITE 0x3a 6191 #undef MC_CMD_0x3a_PRIVILEGE_CTG 6192 6193 #define MC_CMD_0x3a_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6194 6195 /* MC_CMD_NVRAM_WRITE_IN msgrequest */ 6196 #define MC_CMD_NVRAM_WRITE_IN_LENMIN 13 6197 #define MC_CMD_NVRAM_WRITE_IN_LENMAX 252 6198 #define MC_CMD_NVRAM_WRITE_IN_LEN(num) (12+1*(num)) 6199 #define MC_CMD_NVRAM_WRITE_IN_TYPE_OFST 0 6200 /* Enum values, see field(s): */ 6201 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 6202 #define MC_CMD_NVRAM_WRITE_IN_OFFSET_OFST 4 6203 #define MC_CMD_NVRAM_WRITE_IN_LENGTH_OFST 8 6204 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_OFST 12 6205 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_LEN 1 6206 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MINNUM 1 6207 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MAXNUM 240 6208 6209 /* MC_CMD_NVRAM_WRITE_OUT msgresponse */ 6210 #define MC_CMD_NVRAM_WRITE_OUT_LEN 0 6211 6212 6213 /***********************************/ 6214 /* MC_CMD_NVRAM_ERASE 6215 * Erase sector(s) from a virtual NVRAM partition. Locks required: PHY_LOCK if 6216 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if 6217 * PHY_LOCK required and not held) 6218 */ 6219 #define MC_CMD_NVRAM_ERASE 0x3b 6220 #undef MC_CMD_0x3b_PRIVILEGE_CTG 6221 6222 #define MC_CMD_0x3b_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6223 6224 /* MC_CMD_NVRAM_ERASE_IN msgrequest */ 6225 #define MC_CMD_NVRAM_ERASE_IN_LEN 12 6226 #define MC_CMD_NVRAM_ERASE_IN_TYPE_OFST 0 6227 /* Enum values, see field(s): */ 6228 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 6229 #define MC_CMD_NVRAM_ERASE_IN_OFFSET_OFST 4 6230 #define MC_CMD_NVRAM_ERASE_IN_LENGTH_OFST 8 6231 6232 /* MC_CMD_NVRAM_ERASE_OUT msgresponse */ 6233 #define MC_CMD_NVRAM_ERASE_OUT_LEN 0 6234 6235 6236 /***********************************/ 6237 /* MC_CMD_NVRAM_UPDATE_FINISH 6238 * Finish a group of update operations on a virtual NVRAM partition. Locks 6239 * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad 6240 * type/offset/length), EACCES (if PHY_LOCK required and not held) 6241 */ 6242 #define MC_CMD_NVRAM_UPDATE_FINISH 0x3c 6243 #undef MC_CMD_0x3c_PRIVILEGE_CTG 6244 6245 #define MC_CMD_0x3c_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6246 6247 /* MC_CMD_NVRAM_UPDATE_FINISH_IN msgrequest */ 6248 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_LEN 8 6249 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_TYPE_OFST 0 6250 /* Enum values, see field(s): */ 6251 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 6252 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_REBOOT_OFST 4 6253 6254 /* MC_CMD_NVRAM_UPDATE_FINISH_OUT msgresponse */ 6255 #define MC_CMD_NVRAM_UPDATE_FINISH_OUT_LEN 0 6256 6257 6258 /***********************************/ 6259 /* MC_CMD_REBOOT 6260 * Reboot the MC. 6261 * 6262 * The AFTER_ASSERTION flag is intended to be used when the driver notices an 6263 * assertion failure (at which point it is expected to perform a complete tear 6264 * down and reinitialise), to allow both ports to reset the MC once in an 6265 * atomic fashion. 6266 * 6267 * Production mc firmwares are generally compiled with REBOOT_ON_ASSERT=1, 6268 * which means that they will automatically reboot out of the assertion 6269 * handler, so this is in practise an optional operation. It is still 6270 * recommended that drivers execute this to support custom firmwares with 6271 * REBOOT_ON_ASSERT=0. 6272 * 6273 * Locks required: NONE Returns: Nothing. You get back a response with ERR=1, 6274 * DATALEN=0 6275 */ 6276 #define MC_CMD_REBOOT 0x3d 6277 #undef MC_CMD_0x3d_PRIVILEGE_CTG 6278 6279 #define MC_CMD_0x3d_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6280 6281 /* MC_CMD_REBOOT_IN msgrequest */ 6282 #define MC_CMD_REBOOT_IN_LEN 4 6283 #define MC_CMD_REBOOT_IN_FLAGS_OFST 0 6284 #define MC_CMD_REBOOT_FLAGS_AFTER_ASSERTION 0x1 /* enum */ 6285 6286 /* MC_CMD_REBOOT_OUT msgresponse */ 6287 #define MC_CMD_REBOOT_OUT_LEN 0 6288 6289 6290 /***********************************/ 6291 /* MC_CMD_SCHEDINFO 6292 * Request scheduler info. Locks required: NONE. Returns: An array of 6293 * (timeslice,maximum overrun), one for each thread, in ascending order of 6294 * thread address. 6295 */ 6296 #define MC_CMD_SCHEDINFO 0x3e 6297 #undef MC_CMD_0x3e_PRIVILEGE_CTG 6298 6299 #define MC_CMD_0x3e_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6300 6301 /* MC_CMD_SCHEDINFO_IN msgrequest */ 6302 #define MC_CMD_SCHEDINFO_IN_LEN 0 6303 6304 /* MC_CMD_SCHEDINFO_OUT msgresponse */ 6305 #define MC_CMD_SCHEDINFO_OUT_LENMIN 4 6306 #define MC_CMD_SCHEDINFO_OUT_LENMAX 252 6307 #define MC_CMD_SCHEDINFO_OUT_LEN(num) (0+4*(num)) 6308 #define MC_CMD_SCHEDINFO_OUT_DATA_OFST 0 6309 #define MC_CMD_SCHEDINFO_OUT_DATA_LEN 4 6310 #define MC_CMD_SCHEDINFO_OUT_DATA_MINNUM 1 6311 #define MC_CMD_SCHEDINFO_OUT_DATA_MAXNUM 63 6312 6313 6314 /***********************************/ 6315 /* MC_CMD_REBOOT_MODE 6316 * Set the mode for the next MC reboot. Locks required: NONE. Sets the reboot 6317 * mode to the specified value. Returns the old mode. 6318 */ 6319 #define MC_CMD_REBOOT_MODE 0x3f 6320 #undef MC_CMD_0x3f_PRIVILEGE_CTG 6321 6322 #define MC_CMD_0x3f_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6323 6324 /* MC_CMD_REBOOT_MODE_IN msgrequest */ 6325 #define MC_CMD_REBOOT_MODE_IN_LEN 4 6326 #define MC_CMD_REBOOT_MODE_IN_VALUE_OFST 0 6327 /* enum: Normal. */ 6328 #define MC_CMD_REBOOT_MODE_NORMAL 0x0 6329 /* enum: Power-on Reset. */ 6330 #define MC_CMD_REBOOT_MODE_POR 0x2 6331 /* enum: Snapper. */ 6332 #define MC_CMD_REBOOT_MODE_SNAPPER 0x3 6333 /* enum: snapper fake POR */ 6334 #define MC_CMD_REBOOT_MODE_SNAPPER_POR 0x4 6335 #define MC_CMD_REBOOT_MODE_IN_FAKE_LBN 7 6336 #define MC_CMD_REBOOT_MODE_IN_FAKE_WIDTH 1 6337 6338 /* MC_CMD_REBOOT_MODE_OUT msgresponse */ 6339 #define MC_CMD_REBOOT_MODE_OUT_LEN 4 6340 #define MC_CMD_REBOOT_MODE_OUT_VALUE_OFST 0 6341 6342 6343 /***********************************/ 6344 /* MC_CMD_SENSOR_INFO 6345 * Returns information about every available sensor. 6346 * 6347 * Each sensor has a single (16bit) value, and a corresponding state. The 6348 * mapping between value and state is nominally determined by the MC, but may 6349 * be implemented using up to 2 ranges per sensor. 6350 * 6351 * This call returns a mask (32bit) of the sensors that are supported by this 6352 * platform, then an array of sensor information structures, in order of sensor 6353 * type (but without gaps for unimplemented sensors). Each structure defines 6354 * the ranges for the corresponding sensor. An unused range is indicated by 6355 * equal limit values. If one range is used, a value outside that range results 6356 * in STATE_FATAL. If two ranges are used, a value outside the second range 6357 * results in STATE_FATAL while a value outside the first and inside the second 6358 * range results in STATE_WARNING. 6359 * 6360 * Sensor masks and sensor information arrays are organised into pages. For 6361 * backward compatibility, older host software can only use sensors in page 0. 6362 * Bit 32 in the sensor mask was previously unused, and is no reserved for use 6363 * as the next page flag. 6364 * 6365 * If the request does not contain a PAGE value then firmware will only return 6366 * page 0 of sensor information, with bit 31 in the sensor mask cleared. 6367 * 6368 * If the request contains a PAGE value then firmware responds with the sensor 6369 * mask and sensor information array for that page of sensors. In this case bit 6370 * 31 in the mask is set if another page exists. 6371 * 6372 * Locks required: None Returns: 0 6373 */ 6374 #define MC_CMD_SENSOR_INFO 0x41 6375 #undef MC_CMD_0x41_PRIVILEGE_CTG 6376 6377 #define MC_CMD_0x41_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6378 6379 /* MC_CMD_SENSOR_INFO_IN msgrequest */ 6380 #define MC_CMD_SENSOR_INFO_IN_LEN 0 6381 6382 /* MC_CMD_SENSOR_INFO_EXT_IN msgrequest */ 6383 #define MC_CMD_SENSOR_INFO_EXT_IN_LEN 4 6384 /* Which page of sensors to report. 6385 * 6386 * Page 0 contains sensors 0 to 30 (sensor 31 is the next page bit). 6387 * 6388 * Page 1 contains sensors 32 to 62 (sensor 63 is the next page bit). etc. 6389 */ 6390 #define MC_CMD_SENSOR_INFO_EXT_IN_PAGE_OFST 0 6391 6392 /* MC_CMD_SENSOR_INFO_OUT msgresponse */ 6393 #define MC_CMD_SENSOR_INFO_OUT_LENMIN 4 6394 #define MC_CMD_SENSOR_INFO_OUT_LENMAX 252 6395 #define MC_CMD_SENSOR_INFO_OUT_LEN(num) (4+8*(num)) 6396 #define MC_CMD_SENSOR_INFO_OUT_MASK_OFST 0 6397 /* enum: Controller temperature: degC */ 6398 #define MC_CMD_SENSOR_CONTROLLER_TEMP 0x0 6399 /* enum: Phy common temperature: degC */ 6400 #define MC_CMD_SENSOR_PHY_COMMON_TEMP 0x1 6401 /* enum: Controller cooling: bool */ 6402 #define MC_CMD_SENSOR_CONTROLLER_COOLING 0x2 6403 /* enum: Phy 0 temperature: degC */ 6404 #define MC_CMD_SENSOR_PHY0_TEMP 0x3 6405 /* enum: Phy 0 cooling: bool */ 6406 #define MC_CMD_SENSOR_PHY0_COOLING 0x4 6407 /* enum: Phy 1 temperature: degC */ 6408 #define MC_CMD_SENSOR_PHY1_TEMP 0x5 6409 /* enum: Phy 1 cooling: bool */ 6410 #define MC_CMD_SENSOR_PHY1_COOLING 0x6 6411 /* enum: 1.0v power: mV */ 6412 #define MC_CMD_SENSOR_IN_1V0 0x7 6413 /* enum: 1.2v power: mV */ 6414 #define MC_CMD_SENSOR_IN_1V2 0x8 6415 /* enum: 1.8v power: mV */ 6416 #define MC_CMD_SENSOR_IN_1V8 0x9 6417 /* enum: 2.5v power: mV */ 6418 #define MC_CMD_SENSOR_IN_2V5 0xa 6419 /* enum: 3.3v power: mV */ 6420 #define MC_CMD_SENSOR_IN_3V3 0xb 6421 /* enum: 12v power: mV */ 6422 #define MC_CMD_SENSOR_IN_12V0 0xc 6423 /* enum: 1.2v analogue power: mV */ 6424 #define MC_CMD_SENSOR_IN_1V2A 0xd 6425 /* enum: reference voltage: mV */ 6426 #define MC_CMD_SENSOR_IN_VREF 0xe 6427 /* enum: AOE FPGA power: mV */ 6428 #define MC_CMD_SENSOR_OUT_VAOE 0xf 6429 /* enum: AOE FPGA temperature: degC */ 6430 #define MC_CMD_SENSOR_AOE_TEMP 0x10 6431 /* enum: AOE FPGA PSU temperature: degC */ 6432 #define MC_CMD_SENSOR_PSU_AOE_TEMP 0x11 6433 /* enum: AOE PSU temperature: degC */ 6434 #define MC_CMD_SENSOR_PSU_TEMP 0x12 6435 /* enum: Fan 0 speed: RPM */ 6436 #define MC_CMD_SENSOR_FAN_0 0x13 6437 /* enum: Fan 1 speed: RPM */ 6438 #define MC_CMD_SENSOR_FAN_1 0x14 6439 /* enum: Fan 2 speed: RPM */ 6440 #define MC_CMD_SENSOR_FAN_2 0x15 6441 /* enum: Fan 3 speed: RPM */ 6442 #define MC_CMD_SENSOR_FAN_3 0x16 6443 /* enum: Fan 4 speed: RPM */ 6444 #define MC_CMD_SENSOR_FAN_4 0x17 6445 /* enum: AOE FPGA input power: mV */ 6446 #define MC_CMD_SENSOR_IN_VAOE 0x18 6447 /* enum: AOE FPGA current: mA */ 6448 #define MC_CMD_SENSOR_OUT_IAOE 0x19 6449 /* enum: AOE FPGA input current: mA */ 6450 #define MC_CMD_SENSOR_IN_IAOE 0x1a 6451 /* enum: NIC power consumption: W */ 6452 #define MC_CMD_SENSOR_NIC_POWER 0x1b 6453 /* enum: 0.9v power voltage: mV */ 6454 #define MC_CMD_SENSOR_IN_0V9 0x1c 6455 /* enum: 0.9v power current: mA */ 6456 #define MC_CMD_SENSOR_IN_I0V9 0x1d 6457 /* enum: 1.2v power current: mA */ 6458 #define MC_CMD_SENSOR_IN_I1V2 0x1e 6459 /* enum: Not a sensor: reserved for the next page flag */ 6460 #define MC_CMD_SENSOR_PAGE0_NEXT 0x1f 6461 /* enum: 0.9v power voltage (at ADC): mV */ 6462 #define MC_CMD_SENSOR_IN_0V9_ADC 0x20 6463 /* enum: Controller temperature 2: degC */ 6464 #define MC_CMD_SENSOR_CONTROLLER_2_TEMP 0x21 6465 /* enum: Voltage regulator internal temperature: degC */ 6466 #define MC_CMD_SENSOR_VREG_INTERNAL_TEMP 0x22 6467 /* enum: 0.9V voltage regulator temperature: degC */ 6468 #define MC_CMD_SENSOR_VREG_0V9_TEMP 0x23 6469 /* enum: 1.2V voltage regulator temperature: degC */ 6470 #define MC_CMD_SENSOR_VREG_1V2_TEMP 0x24 6471 /* enum: controller internal temperature sensor voltage (internal ADC): mV */ 6472 #define MC_CMD_SENSOR_CONTROLLER_VPTAT 0x25 6473 /* enum: controller internal temperature (internal ADC): degC */ 6474 #define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP 0x26 6475 /* enum: controller internal temperature sensor voltage (external ADC): mV */ 6476 #define MC_CMD_SENSOR_CONTROLLER_VPTAT_EXTADC 0x27 6477 /* enum: controller internal temperature (external ADC): degC */ 6478 #define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP_EXTADC 0x28 6479 /* enum: ambient temperature: degC */ 6480 #define MC_CMD_SENSOR_AMBIENT_TEMP 0x29 6481 /* enum: air flow: bool */ 6482 #define MC_CMD_SENSOR_AIRFLOW 0x2a 6483 /* enum: voltage between VSS08D and VSS08D at CSR: mV */ 6484 #define MC_CMD_SENSOR_VDD08D_VSS08D_CSR 0x2b 6485 /* enum: voltage between VSS08D and VSS08D at CSR (external ADC): mV */ 6486 #define MC_CMD_SENSOR_VDD08D_VSS08D_CSR_EXTADC 0x2c 6487 /* enum: Hotpoint temperature: degC */ 6488 #define MC_CMD_SENSOR_HOTPOINT_TEMP 0x2d 6489 /* enum: Port 0 PHY power switch over-current: bool */ 6490 #define MC_CMD_SENSOR_PHY_POWER_PORT0 0x2e 6491 /* enum: Port 1 PHY power switch over-current: bool */ 6492 #define MC_CMD_SENSOR_PHY_POWER_PORT1 0x2f 6493 /* enum: Mop-up microcontroller reference voltage (millivolts) */ 6494 #define MC_CMD_SENSOR_MUM_VCC 0x30 6495 /* enum: 0.9v power phase A voltage: mV */ 6496 #define MC_CMD_SENSOR_IN_0V9_A 0x31 6497 /* enum: 0.9v power phase A current: mA */ 6498 #define MC_CMD_SENSOR_IN_I0V9_A 0x32 6499 /* enum: 0.9V voltage regulator phase A temperature: degC */ 6500 #define MC_CMD_SENSOR_VREG_0V9_A_TEMP 0x33 6501 /* enum: 0.9v power phase B voltage: mV */ 6502 #define MC_CMD_SENSOR_IN_0V9_B 0x34 6503 /* enum: 0.9v power phase B current: mA */ 6504 #define MC_CMD_SENSOR_IN_I0V9_B 0x35 6505 /* enum: 0.9V voltage regulator phase B temperature: degC */ 6506 #define MC_CMD_SENSOR_VREG_0V9_B_TEMP 0x36 6507 /* enum: CCOM AVREG 1v2 supply (interval ADC): mV */ 6508 #define MC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY 0x37 6509 /* enum: CCOM AVREG 1v2 supply (external ADC): mV */ 6510 #define MC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY_EXTADC 0x38 6511 /* enum: CCOM AVREG 1v8 supply (interval ADC): mV */ 6512 #define MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY 0x39 6513 /* enum: CCOM AVREG 1v8 supply (external ADC): mV */ 6514 #define MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY_EXTADC 0x3a 6515 /* enum: CCOM RTS temperature: degC */ 6516 #define MC_CMD_SENSOR_CONTROLLER_RTS 0x3b 6517 /* enum: Not a sensor: reserved for the next page flag */ 6518 #define MC_CMD_SENSOR_PAGE1_NEXT 0x3f 6519 /* enum: controller internal temperature sensor voltage on master core 6520 * (internal ADC): mV 6521 */ 6522 #define MC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT 0x40 6523 /* enum: controller internal temperature on master core (internal ADC): degC */ 6524 #define MC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP 0x41 6525 /* enum: controller internal temperature sensor voltage on master core 6526 * (external ADC): mV 6527 */ 6528 #define MC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT_EXTADC 0x42 6529 /* enum: controller internal temperature on master core (external ADC): degC */ 6530 #define MC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC 0x43 6531 /* enum: controller internal temperature on slave core sensor voltage (internal 6532 * ADC): mV 6533 */ 6534 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT 0x44 6535 /* enum: controller internal temperature on slave core (internal ADC): degC */ 6536 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP 0x45 6537 /* enum: controller internal temperature on slave core sensor voltage (external 6538 * ADC): mV 6539 */ 6540 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT_EXTADC 0x46 6541 /* enum: controller internal temperature on slave core (external ADC): degC */ 6542 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC 0x47 6543 /* enum: Voltage supplied to the SODIMMs from their power supply: mV */ 6544 #define MC_CMD_SENSOR_SODIMM_VOUT 0x49 6545 /* enum: Temperature of SODIMM 0 (if installed): degC */ 6546 #define MC_CMD_SENSOR_SODIMM_0_TEMP 0x4a 6547 /* enum: Temperature of SODIMM 1 (if installed): degC */ 6548 #define MC_CMD_SENSOR_SODIMM_1_TEMP 0x4b 6549 /* enum: Voltage supplied to the QSFP #0 from their power supply: mV */ 6550 #define MC_CMD_SENSOR_PHY0_VCC 0x4c 6551 /* enum: Voltage supplied to the QSFP #1 from their power supply: mV */ 6552 #define MC_CMD_SENSOR_PHY1_VCC 0x4d 6553 /* enum: Controller die temperature (TDIODE): degC */ 6554 #define MC_CMD_SENSOR_CONTROLLER_TDIODE_TEMP 0x4e 6555 /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */ 6556 #define MC_CMD_SENSOR_ENTRY_OFST 4 6557 #define MC_CMD_SENSOR_ENTRY_LEN 8 6558 #define MC_CMD_SENSOR_ENTRY_LO_OFST 4 6559 #define MC_CMD_SENSOR_ENTRY_HI_OFST 8 6560 #define MC_CMD_SENSOR_ENTRY_MINNUM 0 6561 #define MC_CMD_SENSOR_ENTRY_MAXNUM 31 6562 6563 /* MC_CMD_SENSOR_INFO_EXT_OUT msgresponse */ 6564 #define MC_CMD_SENSOR_INFO_EXT_OUT_LENMIN 4 6565 #define MC_CMD_SENSOR_INFO_EXT_OUT_LENMAX 252 6566 #define MC_CMD_SENSOR_INFO_EXT_OUT_LEN(num) (4+8*(num)) 6567 #define MC_CMD_SENSOR_INFO_EXT_OUT_MASK_OFST 0 6568 /* Enum values, see field(s): */ 6569 /* MC_CMD_SENSOR_INFO_OUT */ 6570 #define MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_LBN 31 6571 #define MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_WIDTH 1 6572 /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */ 6573 /* MC_CMD_SENSOR_ENTRY_OFST 4 */ 6574 /* MC_CMD_SENSOR_ENTRY_LEN 8 */ 6575 /* MC_CMD_SENSOR_ENTRY_LO_OFST 4 */ 6576 /* MC_CMD_SENSOR_ENTRY_HI_OFST 8 */ 6577 /* MC_CMD_SENSOR_ENTRY_MINNUM 0 */ 6578 /* MC_CMD_SENSOR_ENTRY_MAXNUM 31 */ 6579 6580 /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF structuredef */ 6581 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_LEN 8 6582 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_OFST 0 6583 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LEN 2 6584 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LBN 0 6585 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_WIDTH 16 6586 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_OFST 2 6587 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LEN 2 6588 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LBN 16 6589 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_WIDTH 16 6590 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_OFST 4 6591 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LEN 2 6592 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LBN 32 6593 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_WIDTH 16 6594 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_OFST 6 6595 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LEN 2 6596 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LBN 48 6597 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_WIDTH 16 6598 6599 6600 /***********************************/ 6601 /* MC_CMD_READ_SENSORS 6602 * Returns the current reading from each sensor. DMAs an array of sensor 6603 * readings, in order of sensor type (but without gaps for unimplemented 6604 * sensors), into host memory. Each array element is a 6605 * MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF dword. 6606 * 6607 * If the request does not contain the LENGTH field then only sensors 0 to 30 6608 * are reported, to avoid DMA buffer overflow in older host software. If the 6609 * sensor reading require more space than the LENGTH allows, then return 6610 * EINVAL. 6611 * 6612 * The MC will send a SENSOREVT event every time any sensor changes state. The 6613 * driver is responsible for ensuring that it doesn't miss any events. The 6614 * board will function normally if all sensors are in STATE_OK or 6615 * STATE_WARNING. Otherwise the board should not be expected to function. 6616 */ 6617 #define MC_CMD_READ_SENSORS 0x42 6618 #undef MC_CMD_0x42_PRIVILEGE_CTG 6619 6620 #define MC_CMD_0x42_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6621 6622 /* MC_CMD_READ_SENSORS_IN msgrequest */ 6623 #define MC_CMD_READ_SENSORS_IN_LEN 8 6624 /* DMA address of host buffer for sensor readings (must be 4Kbyte aligned). */ 6625 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_OFST 0 6626 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LEN 8 6627 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_OFST 0 6628 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_OFST 4 6629 6630 /* MC_CMD_READ_SENSORS_EXT_IN msgrequest */ 6631 #define MC_CMD_READ_SENSORS_EXT_IN_LEN 12 6632 /* DMA address of host buffer for sensor readings (must be 4Kbyte aligned). */ 6633 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_OFST 0 6634 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LEN 8 6635 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_OFST 0 6636 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_HI_OFST 4 6637 /* Size in bytes of host buffer. */ 6638 #define MC_CMD_READ_SENSORS_EXT_IN_LENGTH_OFST 8 6639 6640 /* MC_CMD_READ_SENSORS_OUT msgresponse */ 6641 #define MC_CMD_READ_SENSORS_OUT_LEN 0 6642 6643 /* MC_CMD_READ_SENSORS_EXT_OUT msgresponse */ 6644 #define MC_CMD_READ_SENSORS_EXT_OUT_LEN 0 6645 6646 /* MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF structuredef */ 6647 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_LEN 4 6648 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_OFST 0 6649 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LEN 2 6650 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LBN 0 6651 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_WIDTH 16 6652 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_OFST 2 6653 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LEN 1 6654 /* enum: Ok. */ 6655 #define MC_CMD_SENSOR_STATE_OK 0x0 6656 /* enum: Breached warning threshold. */ 6657 #define MC_CMD_SENSOR_STATE_WARNING 0x1 6658 /* enum: Breached fatal threshold. */ 6659 #define MC_CMD_SENSOR_STATE_FATAL 0x2 6660 /* enum: Fault with sensor. */ 6661 #define MC_CMD_SENSOR_STATE_BROKEN 0x3 6662 /* enum: Sensor is working but does not currently have a reading. */ 6663 #define MC_CMD_SENSOR_STATE_NO_READING 0x4 6664 /* enum: Sensor initialisation failed. */ 6665 #define MC_CMD_SENSOR_STATE_INIT_FAILED 0x5 6666 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LBN 16 6667 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_WIDTH 8 6668 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_OFST 3 6669 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_LEN 1 6670 /* Enum values, see field(s): */ 6671 /* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */ 6672 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_LBN 24 6673 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_WIDTH 8 6674 6675 6676 /***********************************/ 6677 /* MC_CMD_GET_PHY_STATE 6678 * Report current state of PHY. A 'zombie' PHY is a PHY that has failed to boot 6679 * (e.g. due to missing or corrupted firmware). Locks required: None. Return 6680 * code: 0 6681 */ 6682 #define MC_CMD_GET_PHY_STATE 0x43 6683 #undef MC_CMD_0x43_PRIVILEGE_CTG 6684 6685 #define MC_CMD_0x43_PRIVILEGE_CTG SRIOV_CTG_GENERAL 6686 6687 /* MC_CMD_GET_PHY_STATE_IN msgrequest */ 6688 #define MC_CMD_GET_PHY_STATE_IN_LEN 0 6689 6690 /* MC_CMD_GET_PHY_STATE_OUT msgresponse */ 6691 #define MC_CMD_GET_PHY_STATE_OUT_LEN 4 6692 #define MC_CMD_GET_PHY_STATE_OUT_STATE_OFST 0 6693 /* enum: Ok. */ 6694 #define MC_CMD_PHY_STATE_OK 0x1 6695 /* enum: Faulty. */ 6696 #define MC_CMD_PHY_STATE_ZOMBIE 0x2 6697 6698 6699 /***********************************/ 6700 /* MC_CMD_SETUP_8021QBB 6701 * 802.1Qbb control. 8 Tx queues that map to priorities 0 - 7. Use all 1s to 6702 * disable 802.Qbb for a given priority. 6703 */ 6704 #define MC_CMD_SETUP_8021QBB 0x44 6705 6706 /* MC_CMD_SETUP_8021QBB_IN msgrequest */ 6707 #define MC_CMD_SETUP_8021QBB_IN_LEN 32 6708 #define MC_CMD_SETUP_8021QBB_IN_TXQS_OFST 0 6709 #define MC_CMD_SETUP_8021QBB_IN_TXQS_LEN 32 6710 6711 /* MC_CMD_SETUP_8021QBB_OUT msgresponse */ 6712 #define MC_CMD_SETUP_8021QBB_OUT_LEN 0 6713 6714 6715 /***********************************/ 6716 /* MC_CMD_WOL_FILTER_GET 6717 * Retrieve ID of any WoL filters. Locks required: None. Returns: 0, ENOSYS 6718 */ 6719 #define MC_CMD_WOL_FILTER_GET 0x45 6720 #undef MC_CMD_0x45_PRIVILEGE_CTG 6721 6722 #define MC_CMD_0x45_PRIVILEGE_CTG SRIOV_CTG_LINK 6723 6724 /* MC_CMD_WOL_FILTER_GET_IN msgrequest */ 6725 #define MC_CMD_WOL_FILTER_GET_IN_LEN 0 6726 6727 /* MC_CMD_WOL_FILTER_GET_OUT msgresponse */ 6728 #define MC_CMD_WOL_FILTER_GET_OUT_LEN 4 6729 #define MC_CMD_WOL_FILTER_GET_OUT_FILTER_ID_OFST 0 6730 6731 6732 /***********************************/ 6733 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD 6734 * Add a protocol offload to NIC for lights-out state. Locks required: None. 6735 * Returns: 0, ENOSYS 6736 */ 6737 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD 0x46 6738 #undef MC_CMD_0x46_PRIVILEGE_CTG 6739 6740 #define MC_CMD_0x46_PRIVILEGE_CTG SRIOV_CTG_LINK 6741 6742 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN msgrequest */ 6743 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMIN 8 6744 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMAX 252 6745 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LEN(num) (4+4*(num)) 6746 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 6747 #define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_ARP 0x1 /* enum */ 6748 #define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_NS 0x2 /* enum */ 6749 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_OFST 4 6750 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_LEN 4 6751 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MINNUM 1 6752 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MAXNUM 62 6753 6754 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP msgrequest */ 6755 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_LEN 14 6756 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */ 6757 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_OFST 4 6758 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_LEN 6 6759 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_IP_OFST 10 6760 6761 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS msgrequest */ 6762 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_LEN 42 6763 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */ 6764 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_OFST 4 6765 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_LEN 6 6766 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_OFST 10 6767 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_LEN 16 6768 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_OFST 26 6769 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_LEN 16 6770 6771 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT msgresponse */ 6772 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_LEN 4 6773 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_FILTER_ID_OFST 0 6774 6775 6776 /***********************************/ 6777 /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD 6778 * Remove a protocol offload from NIC for lights-out state. Locks required: 6779 * None. Returns: 0, ENOSYS 6780 */ 6781 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD 0x47 6782 #undef MC_CMD_0x47_PRIVILEGE_CTG 6783 6784 #define MC_CMD_0x47_PRIVILEGE_CTG SRIOV_CTG_LINK 6785 6786 /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN msgrequest */ 6787 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_LEN 8 6788 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 6789 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_FILTER_ID_OFST 4 6790 6791 /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT msgresponse */ 6792 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT_LEN 0 6793 6794 6795 /***********************************/ 6796 /* MC_CMD_MAC_RESET_RESTORE 6797 * Restore MAC after block reset. Locks required: None. Returns: 0. 6798 */ 6799 #define MC_CMD_MAC_RESET_RESTORE 0x48 6800 6801 /* MC_CMD_MAC_RESET_RESTORE_IN msgrequest */ 6802 #define MC_CMD_MAC_RESET_RESTORE_IN_LEN 0 6803 6804 /* MC_CMD_MAC_RESET_RESTORE_OUT msgresponse */ 6805 #define MC_CMD_MAC_RESET_RESTORE_OUT_LEN 0 6806 6807 6808 /***********************************/ 6809 /* MC_CMD_TESTASSERT 6810 * Deliberately trigger an assert-detonation in the firmware for testing 6811 * purposes (i.e. to allow tests that the driver copes gracefully). Locks 6812 * required: None Returns: 0 6813 */ 6814 #define MC_CMD_TESTASSERT 0x49 6815 #undef MC_CMD_0x49_PRIVILEGE_CTG 6816 6817 #define MC_CMD_0x49_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6818 6819 /* MC_CMD_TESTASSERT_IN msgrequest */ 6820 #define MC_CMD_TESTASSERT_IN_LEN 0 6821 6822 /* MC_CMD_TESTASSERT_OUT msgresponse */ 6823 #define MC_CMD_TESTASSERT_OUT_LEN 0 6824 6825 6826 /***********************************/ 6827 /* MC_CMD_WORKAROUND 6828 * Enable/Disable a given workaround. The mcfw will return EINVAL if it doesn't 6829 * understand the given workaround number - which should not be treated as a 6830 * hard error by client code. This op does not imply any semantics about each 6831 * workaround, that's between the driver and the mcfw on a per-workaround 6832 * basis. Locks required: None. Returns: 0, EINVAL . 6833 */ 6834 #define MC_CMD_WORKAROUND 0x4a 6835 #undef MC_CMD_0x4a_PRIVILEGE_CTG 6836 6837 #define MC_CMD_0x4a_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6838 6839 /* MC_CMD_WORKAROUND_IN msgrequest */ 6840 #define MC_CMD_WORKAROUND_IN_LEN 8 6841 /* The enums here must correspond with those in MC_CMD_GET_WORKAROUND. */ 6842 #define MC_CMD_WORKAROUND_IN_TYPE_OFST 0 6843 /* enum: Bug 17230 work around. */ 6844 #define MC_CMD_WORKAROUND_BUG17230 0x1 6845 /* enum: Bug 35388 work around (unsafe EVQ writes). */ 6846 #define MC_CMD_WORKAROUND_BUG35388 0x2 6847 /* enum: Bug35017 workaround (A64 tables must be identity map) */ 6848 #define MC_CMD_WORKAROUND_BUG35017 0x3 6849 /* enum: Bug 41750 present (MC_CMD_TRIGGER_INTERRUPT won't work) */ 6850 #define MC_CMD_WORKAROUND_BUG41750 0x4 6851 /* enum: Bug 42008 present (Interrupts can overtake associated events). Caution 6852 * - before adding code that queries this workaround, remember that there's 6853 * released Monza firmware that doesn't understand MC_CMD_WORKAROUND_BUG42008, 6854 * and will hence (incorrectly) report that the bug doesn't exist. 6855 */ 6856 #define MC_CMD_WORKAROUND_BUG42008 0x5 6857 /* enum: Bug 26807 features present in firmware (multicast filter chaining) 6858 * This feature cannot be turned on/off while there are any filters already 6859 * present. The behaviour in such case depends on the acting client's privilege 6860 * level. If the client has the admin privilege, then all functions that have 6861 * filters installed will be FLRed and the FLR_DONE flag will be set. Otherwise 6862 * the command will fail with MC_CMD_ERR_FILTERS_PRESENT. 6863 */ 6864 #define MC_CMD_WORKAROUND_BUG26807 0x6 6865 /* 0 = disable the workaround indicated by TYPE; any non-zero value = enable 6866 * the workaround 6867 */ 6868 #define MC_CMD_WORKAROUND_IN_ENABLED_OFST 4 6869 6870 /* MC_CMD_WORKAROUND_OUT msgresponse */ 6871 #define MC_CMD_WORKAROUND_OUT_LEN 0 6872 6873 /* MC_CMD_WORKAROUND_EXT_OUT msgresponse: This response format will be used 6874 * when (TYPE == MC_CMD_WORKAROUND_BUG26807) 6875 */ 6876 #define MC_CMD_WORKAROUND_EXT_OUT_LEN 4 6877 #define MC_CMD_WORKAROUND_EXT_OUT_FLAGS_OFST 0 6878 #define MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN 0 6879 #define MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_WIDTH 1 6880 6881 6882 /***********************************/ 6883 /* MC_CMD_GET_PHY_MEDIA_INFO 6884 * Read media-specific data from PHY (e.g. SFP/SFP+ module ID information for 6885 * SFP+ PHYs). The 'media type' can be found via GET_PHY_CFG 6886 * (GET_PHY_CFG_OUT_MEDIA_TYPE); the valid 'page number' input values, and the 6887 * output data, are interpreted on a per-type basis. For SFP+: PAGE=0 or 1 6888 * returns a 128-byte block read from module I2C address 0xA0 offset 0 or 0x80. 6889 * Anything else: currently undefined. Locks required: None. Return code: 0. 6890 */ 6891 #define MC_CMD_GET_PHY_MEDIA_INFO 0x4b 6892 #undef MC_CMD_0x4b_PRIVILEGE_CTG 6893 6894 #define MC_CMD_0x4b_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6895 6896 /* MC_CMD_GET_PHY_MEDIA_INFO_IN msgrequest */ 6897 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_LEN 4 6898 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_PAGE_OFST 0 6899 6900 /* MC_CMD_GET_PHY_MEDIA_INFO_OUT msgresponse */ 6901 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMIN 5 6902 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMAX 252 6903 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LEN(num) (4+1*(num)) 6904 /* in bytes */ 6905 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATALEN_OFST 0 6906 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_OFST 4 6907 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_LEN 1 6908 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MINNUM 1 6909 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MAXNUM 248 6910 6911 6912 /***********************************/ 6913 /* MC_CMD_NVRAM_TEST 6914 * Test a particular NVRAM partition for valid contents (where "valid" depends 6915 * on the type of partition). 6916 */ 6917 #define MC_CMD_NVRAM_TEST 0x4c 6918 #undef MC_CMD_0x4c_PRIVILEGE_CTG 6919 6920 #define MC_CMD_0x4c_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6921 6922 /* MC_CMD_NVRAM_TEST_IN msgrequest */ 6923 #define MC_CMD_NVRAM_TEST_IN_LEN 4 6924 #define MC_CMD_NVRAM_TEST_IN_TYPE_OFST 0 6925 /* Enum values, see field(s): */ 6926 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 6927 6928 /* MC_CMD_NVRAM_TEST_OUT msgresponse */ 6929 #define MC_CMD_NVRAM_TEST_OUT_LEN 4 6930 #define MC_CMD_NVRAM_TEST_OUT_RESULT_OFST 0 6931 /* enum: Passed. */ 6932 #define MC_CMD_NVRAM_TEST_PASS 0x0 6933 /* enum: Failed. */ 6934 #define MC_CMD_NVRAM_TEST_FAIL 0x1 6935 /* enum: Not supported. */ 6936 #define MC_CMD_NVRAM_TEST_NOTSUPP 0x2 6937 6938 6939 /***********************************/ 6940 /* MC_CMD_MRSFP_TWEAK 6941 * Read status and/or set parameters for the 'mrsfp' driver in mr_rusty builds. 6942 * I2C I/O expander bits are always read; if equaliser parameters are supplied, 6943 * they are configured first. Locks required: None. Return code: 0, EINVAL. 6944 */ 6945 #define MC_CMD_MRSFP_TWEAK 0x4d 6946 6947 /* MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG msgrequest */ 6948 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_LEN 16 6949 /* 0-6 low->high de-emph. */ 6950 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_LEVEL_OFST 0 6951 /* 0-8 low->high ref.V */ 6952 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_DT_CFG_OFST 4 6953 /* 0-8 0-8 low->high boost */ 6954 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_BOOST_OFST 8 6955 /* 0-8 low->high ref.V */ 6956 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_DT_CFG_OFST 12 6957 6958 /* MC_CMD_MRSFP_TWEAK_IN_READ_ONLY msgrequest */ 6959 #define MC_CMD_MRSFP_TWEAK_IN_READ_ONLY_LEN 0 6960 6961 /* MC_CMD_MRSFP_TWEAK_OUT msgresponse */ 6962 #define MC_CMD_MRSFP_TWEAK_OUT_LEN 12 6963 /* input bits */ 6964 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_INPUTS_OFST 0 6965 /* output bits */ 6966 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_OUTPUTS_OFST 4 6967 /* direction */ 6968 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OFST 8 6969 /* enum: Out. */ 6970 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OUT 0x0 6971 /* enum: In. */ 6972 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_IN 0x1 6973 6974 6975 /***********************************/ 6976 /* MC_CMD_SENSOR_SET_LIMS 6977 * Adjusts the sensor limits. This is a warranty-voiding operation. Returns: 6978 * ENOENT if the sensor specified does not exist, EINVAL if the limits are out 6979 * of range. 6980 */ 6981 #define MC_CMD_SENSOR_SET_LIMS 0x4e 6982 #undef MC_CMD_0x4e_PRIVILEGE_CTG 6983 6984 #define MC_CMD_0x4e_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6985 6986 /* MC_CMD_SENSOR_SET_LIMS_IN msgrequest */ 6987 #define MC_CMD_SENSOR_SET_LIMS_IN_LEN 20 6988 #define MC_CMD_SENSOR_SET_LIMS_IN_SENSOR_OFST 0 6989 /* Enum values, see field(s): */ 6990 /* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */ 6991 /* interpretation is is sensor-specific. */ 6992 #define MC_CMD_SENSOR_SET_LIMS_IN_LOW0_OFST 4 6993 /* interpretation is is sensor-specific. */ 6994 #define MC_CMD_SENSOR_SET_LIMS_IN_HI0_OFST 8 6995 /* interpretation is is sensor-specific. */ 6996 #define MC_CMD_SENSOR_SET_LIMS_IN_LOW1_OFST 12 6997 /* interpretation is is sensor-specific. */ 6998 #define MC_CMD_SENSOR_SET_LIMS_IN_HI1_OFST 16 6999 7000 /* MC_CMD_SENSOR_SET_LIMS_OUT msgresponse */ 7001 #define MC_CMD_SENSOR_SET_LIMS_OUT_LEN 0 7002 7003 7004 /***********************************/ 7005 /* MC_CMD_GET_RESOURCE_LIMITS 7006 */ 7007 #define MC_CMD_GET_RESOURCE_LIMITS 0x4f 7008 7009 /* MC_CMD_GET_RESOURCE_LIMITS_IN msgrequest */ 7010 #define MC_CMD_GET_RESOURCE_LIMITS_IN_LEN 0 7011 7012 /* MC_CMD_GET_RESOURCE_LIMITS_OUT msgresponse */ 7013 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_LEN 16 7014 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_BUFTBL_OFST 0 7015 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_EVQ_OFST 4 7016 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_RXQ_OFST 8 7017 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_TXQ_OFST 12 7018 7019 7020 /***********************************/ 7021 /* MC_CMD_NVRAM_PARTITIONS 7022 * Reads the list of available virtual NVRAM partition types. Locks required: 7023 * none. Returns: 0, EINVAL (bad type). 7024 */ 7025 #define MC_CMD_NVRAM_PARTITIONS 0x51 7026 #undef MC_CMD_0x51_PRIVILEGE_CTG 7027 7028 #define MC_CMD_0x51_PRIVILEGE_CTG SRIOV_CTG_ADMIN 7029 7030 /* MC_CMD_NVRAM_PARTITIONS_IN msgrequest */ 7031 #define MC_CMD_NVRAM_PARTITIONS_IN_LEN 0 7032 7033 /* MC_CMD_NVRAM_PARTITIONS_OUT msgresponse */ 7034 #define MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN 4 7035 #define MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX 252 7036 #define MC_CMD_NVRAM_PARTITIONS_OUT_LEN(num) (4+4*(num)) 7037 /* total number of partitions */ 7038 #define MC_CMD_NVRAM_PARTITIONS_OUT_NUM_PARTITIONS_OFST 0 7039 /* type ID code for each of NUM_PARTITIONS partitions */ 7040 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_OFST 4 7041 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_LEN 4 7042 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MINNUM 0 7043 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MAXNUM 62 7044 7045 7046 /***********************************/ 7047 /* MC_CMD_NVRAM_METADATA 7048 * Reads soft metadata for a virtual NVRAM partition type. Locks required: 7049 * none. Returns: 0, EINVAL (bad type). 7050 */ 7051 #define MC_CMD_NVRAM_METADATA 0x52 7052 #undef MC_CMD_0x52_PRIVILEGE_CTG 7053 7054 #define MC_CMD_0x52_PRIVILEGE_CTG SRIOV_CTG_ADMIN 7055 7056 /* MC_CMD_NVRAM_METADATA_IN msgrequest */ 7057 #define MC_CMD_NVRAM_METADATA_IN_LEN 4 7058 /* Partition type ID code */ 7059 #define MC_CMD_NVRAM_METADATA_IN_TYPE_OFST 0 7060 7061 /* MC_CMD_NVRAM_METADATA_OUT msgresponse */ 7062 #define MC_CMD_NVRAM_METADATA_OUT_LENMIN 20 7063 #define MC_CMD_NVRAM_METADATA_OUT_LENMAX 252 7064 #define MC_CMD_NVRAM_METADATA_OUT_LEN(num) (20+1*(num)) 7065 /* Partition type ID code */ 7066 #define MC_CMD_NVRAM_METADATA_OUT_TYPE_OFST 0 7067 #define MC_CMD_NVRAM_METADATA_OUT_FLAGS_OFST 4 7068 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN 0 7069 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_WIDTH 1 7070 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_LBN 1 7071 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_WIDTH 1 7072 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_LBN 2 7073 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_WIDTH 1 7074 /* Subtype ID code for content of this partition */ 7075 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_OFST 8 7076 /* 1st component of W.X.Y.Z version number for content of this partition */ 7077 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_W_OFST 12 7078 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_W_LEN 2 7079 /* 2nd component of W.X.Y.Z version number for content of this partition */ 7080 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_X_OFST 14 7081 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_X_LEN 2 7082 /* 3rd component of W.X.Y.Z version number for content of this partition */ 7083 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Y_OFST 16 7084 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Y_LEN 2 7085 /* 4th component of W.X.Y.Z version number for content of this partition */ 7086 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Z_OFST 18 7087 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Z_LEN 2 7088 /* Zero-terminated string describing the content of this partition */ 7089 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_OFST 20 7090 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_LEN 1 7091 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MINNUM 0 7092 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MAXNUM 232 7093 7094 7095 /***********************************/ 7096 /* MC_CMD_GET_MAC_ADDRESSES 7097 * Returns the base MAC, count and stride for the requesting function 7098 */ 7099 #define MC_CMD_GET_MAC_ADDRESSES 0x55 7100 #undef MC_CMD_0x55_PRIVILEGE_CTG 7101 7102 #define MC_CMD_0x55_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7103 7104 /* MC_CMD_GET_MAC_ADDRESSES_IN msgrequest */ 7105 #define MC_CMD_GET_MAC_ADDRESSES_IN_LEN 0 7106 7107 /* MC_CMD_GET_MAC_ADDRESSES_OUT msgresponse */ 7108 #define MC_CMD_GET_MAC_ADDRESSES_OUT_LEN 16 7109 /* Base MAC address */ 7110 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE_OFST 0 7111 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE_LEN 6 7112 /* Padding */ 7113 #define MC_CMD_GET_MAC_ADDRESSES_OUT_RESERVED_OFST 6 7114 #define MC_CMD_GET_MAC_ADDRESSES_OUT_RESERVED_LEN 2 7115 /* Number of allocated MAC addresses */ 7116 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_COUNT_OFST 8 7117 /* Spacing of allocated MAC addresses */ 7118 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_STRIDE_OFST 12 7119 7120 7121 /***********************************/ 7122 /* MC_CMD_CLP 7123 * Perform a CLP related operation 7124 */ 7125 #define MC_CMD_CLP 0x56 7126 #undef MC_CMD_0x56_PRIVILEGE_CTG 7127 7128 #define MC_CMD_0x56_PRIVILEGE_CTG SRIOV_CTG_ADMIN 7129 7130 /* MC_CMD_CLP_IN msgrequest */ 7131 #define MC_CMD_CLP_IN_LEN 4 7132 /* Sub operation */ 7133 #define MC_CMD_CLP_IN_OP_OFST 0 7134 /* enum: Return to factory default settings */ 7135 #define MC_CMD_CLP_OP_DEFAULT 0x1 7136 /* enum: Set MAC address */ 7137 #define MC_CMD_CLP_OP_SET_MAC 0x2 7138 /* enum: Get MAC address */ 7139 #define MC_CMD_CLP_OP_GET_MAC 0x3 7140 /* enum: Set UEFI/GPXE boot mode */ 7141 #define MC_CMD_CLP_OP_SET_BOOT 0x4 7142 /* enum: Get UEFI/GPXE boot mode */ 7143 #define MC_CMD_CLP_OP_GET_BOOT 0x5 7144 7145 /* MC_CMD_CLP_OUT msgresponse */ 7146 #define MC_CMD_CLP_OUT_LEN 0 7147 7148 /* MC_CMD_CLP_IN_DEFAULT msgrequest */ 7149 #define MC_CMD_CLP_IN_DEFAULT_LEN 4 7150 /* MC_CMD_CLP_IN_OP_OFST 0 */ 7151 7152 /* MC_CMD_CLP_OUT_DEFAULT msgresponse */ 7153 #define MC_CMD_CLP_OUT_DEFAULT_LEN 0 7154 7155 /* MC_CMD_CLP_IN_SET_MAC msgrequest */ 7156 #define MC_CMD_CLP_IN_SET_MAC_LEN 12 7157 /* MC_CMD_CLP_IN_OP_OFST 0 */ 7158 /* MAC address assigned to port */ 7159 #define MC_CMD_CLP_IN_SET_MAC_ADDR_OFST 4 7160 #define MC_CMD_CLP_IN_SET_MAC_ADDR_LEN 6 7161 /* Padding */ 7162 #define MC_CMD_CLP_IN_SET_MAC_RESERVED_OFST 10 7163 #define MC_CMD_CLP_IN_SET_MAC_RESERVED_LEN 2 7164 7165 /* MC_CMD_CLP_OUT_SET_MAC msgresponse */ 7166 #define MC_CMD_CLP_OUT_SET_MAC_LEN 0 7167 7168 /* MC_CMD_CLP_IN_GET_MAC msgrequest */ 7169 #define MC_CMD_CLP_IN_GET_MAC_LEN 4 7170 /* MC_CMD_CLP_IN_OP_OFST 0 */ 7171 7172 /* MC_CMD_CLP_OUT_GET_MAC msgresponse */ 7173 #define MC_CMD_CLP_OUT_GET_MAC_LEN 8 7174 /* MAC address assigned to port */ 7175 #define MC_CMD_CLP_OUT_GET_MAC_ADDR_OFST 0 7176 #define MC_CMD_CLP_OUT_GET_MAC_ADDR_LEN 6 7177 /* Padding */ 7178 #define MC_CMD_CLP_OUT_GET_MAC_RESERVED_OFST 6 7179 #define MC_CMD_CLP_OUT_GET_MAC_RESERVED_LEN 2 7180 7181 /* MC_CMD_CLP_IN_SET_BOOT msgrequest */ 7182 #define MC_CMD_CLP_IN_SET_BOOT_LEN 5 7183 /* MC_CMD_CLP_IN_OP_OFST 0 */ 7184 /* Boot flag */ 7185 #define MC_CMD_CLP_IN_SET_BOOT_FLAG_OFST 4 7186 #define MC_CMD_CLP_IN_SET_BOOT_FLAG_LEN 1 7187 7188 /* MC_CMD_CLP_OUT_SET_BOOT msgresponse */ 7189 #define MC_CMD_CLP_OUT_SET_BOOT_LEN 0 7190 7191 /* MC_CMD_CLP_IN_GET_BOOT msgrequest */ 7192 #define MC_CMD_CLP_IN_GET_BOOT_LEN 4 7193 /* MC_CMD_CLP_IN_OP_OFST 0 */ 7194 7195 /* MC_CMD_CLP_OUT_GET_BOOT msgresponse */ 7196 #define MC_CMD_CLP_OUT_GET_BOOT_LEN 4 7197 /* Boot flag */ 7198 #define MC_CMD_CLP_OUT_GET_BOOT_FLAG_OFST 0 7199 #define MC_CMD_CLP_OUT_GET_BOOT_FLAG_LEN 1 7200 /* Padding */ 7201 #define MC_CMD_CLP_OUT_GET_BOOT_RESERVED_OFST 1 7202 #define MC_CMD_CLP_OUT_GET_BOOT_RESERVED_LEN 3 7203 7204 7205 /***********************************/ 7206 /* MC_CMD_MUM 7207 * Perform a MUM operation 7208 */ 7209 #define MC_CMD_MUM 0x57 7210 #undef MC_CMD_0x57_PRIVILEGE_CTG 7211 7212 #define MC_CMD_0x57_PRIVILEGE_CTG SRIOV_CTG_ADMIN 7213 7214 /* MC_CMD_MUM_IN msgrequest */ 7215 #define MC_CMD_MUM_IN_LEN 4 7216 #define MC_CMD_MUM_IN_OP_HDR_OFST 0 7217 #define MC_CMD_MUM_IN_OP_LBN 0 7218 #define MC_CMD_MUM_IN_OP_WIDTH 8 7219 /* enum: NULL MCDI command to MUM */ 7220 #define MC_CMD_MUM_OP_NULL 0x1 7221 /* enum: Get MUM version */ 7222 #define MC_CMD_MUM_OP_GET_VERSION 0x2 7223 /* enum: Issue raw I2C command to MUM */ 7224 #define MC_CMD_MUM_OP_RAW_CMD 0x3 7225 /* enum: Read from registers on devices connected to MUM. */ 7226 #define MC_CMD_MUM_OP_READ 0x4 7227 /* enum: Write to registers on devices connected to MUM. */ 7228 #define MC_CMD_MUM_OP_WRITE 0x5 7229 /* enum: Control UART logging. */ 7230 #define MC_CMD_MUM_OP_LOG 0x6 7231 /* enum: Operations on MUM GPIO lines */ 7232 #define MC_CMD_MUM_OP_GPIO 0x7 7233 /* enum: Get sensor readings from MUM */ 7234 #define MC_CMD_MUM_OP_READ_SENSORS 0x8 7235 /* enum: Initiate clock programming on the MUM */ 7236 #define MC_CMD_MUM_OP_PROGRAM_CLOCKS 0x9 7237 /* enum: Initiate FPGA load from flash on the MUM */ 7238 #define MC_CMD_MUM_OP_FPGA_LOAD 0xa 7239 /* enum: Request sensor reading from MUM ADC resulting from earlier request via 7240 * MUM ATB 7241 */ 7242 #define MC_CMD_MUM_OP_READ_ATB_SENSOR 0xb 7243 /* enum: Send commands relating to the QSFP ports via the MUM for PHY 7244 * operations 7245 */ 7246 #define MC_CMD_MUM_OP_QSFP 0xc 7247 /* enum: Request discrete and SODIMM DDR info (type, size, speed grade, voltage 7248 * level) from MUM 7249 */ 7250 #define MC_CMD_MUM_OP_READ_DDR_INFO 0xd 7251 7252 /* MC_CMD_MUM_IN_NULL msgrequest */ 7253 #define MC_CMD_MUM_IN_NULL_LEN 4 7254 /* MUM cmd header */ 7255 #define MC_CMD_MUM_IN_CMD_OFST 0 7256 7257 /* MC_CMD_MUM_IN_GET_VERSION msgrequest */ 7258 #define MC_CMD_MUM_IN_GET_VERSION_LEN 4 7259 /* MUM cmd header */ 7260 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7261 7262 /* MC_CMD_MUM_IN_READ msgrequest */ 7263 #define MC_CMD_MUM_IN_READ_LEN 16 7264 /* MUM cmd header */ 7265 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7266 /* ID of (device connected to MUM) to read from registers of */ 7267 #define MC_CMD_MUM_IN_READ_DEVICE_OFST 4 7268 /* enum: Hittite HMC1035 clock generator on Sorrento board */ 7269 #define MC_CMD_MUM_DEV_HITTITE 0x1 7270 /* enum: Hittite HMC1035 clock generator for NIC-side on Sorrento board */ 7271 #define MC_CMD_MUM_DEV_HITTITE_NIC 0x2 7272 /* 32-bit address to read from */ 7273 #define MC_CMD_MUM_IN_READ_ADDR_OFST 8 7274 /* Number of words to read. */ 7275 #define MC_CMD_MUM_IN_READ_NUMWORDS_OFST 12 7276 7277 /* MC_CMD_MUM_IN_WRITE msgrequest */ 7278 #define MC_CMD_MUM_IN_WRITE_LENMIN 16 7279 #define MC_CMD_MUM_IN_WRITE_LENMAX 252 7280 #define MC_CMD_MUM_IN_WRITE_LEN(num) (12+4*(num)) 7281 /* MUM cmd header */ 7282 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7283 /* ID of (device connected to MUM) to write to registers of */ 7284 #define MC_CMD_MUM_IN_WRITE_DEVICE_OFST 4 7285 /* enum: Hittite HMC1035 clock generator on Sorrento board */ 7286 /* MC_CMD_MUM_DEV_HITTITE 0x1 */ 7287 /* 32-bit address to write to */ 7288 #define MC_CMD_MUM_IN_WRITE_ADDR_OFST 8 7289 /* Words to write */ 7290 #define MC_CMD_MUM_IN_WRITE_BUFFER_OFST 12 7291 #define MC_CMD_MUM_IN_WRITE_BUFFER_LEN 4 7292 #define MC_CMD_MUM_IN_WRITE_BUFFER_MINNUM 1 7293 #define MC_CMD_MUM_IN_WRITE_BUFFER_MAXNUM 60 7294 7295 /* MC_CMD_MUM_IN_RAW_CMD msgrequest */ 7296 #define MC_CMD_MUM_IN_RAW_CMD_LENMIN 17 7297 #define MC_CMD_MUM_IN_RAW_CMD_LENMAX 252 7298 #define MC_CMD_MUM_IN_RAW_CMD_LEN(num) (16+1*(num)) 7299 /* MUM cmd header */ 7300 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7301 /* MUM I2C cmd code */ 7302 #define MC_CMD_MUM_IN_RAW_CMD_CMD_CODE_OFST 4 7303 /* Number of bytes to write */ 7304 #define MC_CMD_MUM_IN_RAW_CMD_NUM_WRITE_OFST 8 7305 /* Number of bytes to read */ 7306 #define MC_CMD_MUM_IN_RAW_CMD_NUM_READ_OFST 12 7307 /* Bytes to write */ 7308 #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_OFST 16 7309 #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_LEN 1 7310 #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_MINNUM 1 7311 #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_MAXNUM 236 7312 7313 /* MC_CMD_MUM_IN_LOG msgrequest */ 7314 #define MC_CMD_MUM_IN_LOG_LEN 8 7315 /* MUM cmd header */ 7316 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7317 #define MC_CMD_MUM_IN_LOG_OP_OFST 4 7318 #define MC_CMD_MUM_IN_LOG_OP_UART 0x1 /* enum */ 7319 7320 /* MC_CMD_MUM_IN_LOG_OP_UART msgrequest */ 7321 #define MC_CMD_MUM_IN_LOG_OP_UART_LEN 12 7322 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7323 /* MC_CMD_MUM_IN_LOG_OP_OFST 4 */ 7324 /* Enable/disable debug output to UART */ 7325 #define MC_CMD_MUM_IN_LOG_OP_UART_ENABLE_OFST 8 7326 7327 /* MC_CMD_MUM_IN_GPIO msgrequest */ 7328 #define MC_CMD_MUM_IN_GPIO_LEN 8 7329 /* MUM cmd header */ 7330 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7331 #define MC_CMD_MUM_IN_GPIO_HDR_OFST 4 7332 #define MC_CMD_MUM_IN_GPIO_OPCODE_LBN 0 7333 #define MC_CMD_MUM_IN_GPIO_OPCODE_WIDTH 8 7334 #define MC_CMD_MUM_IN_GPIO_IN_READ 0x0 /* enum */ 7335 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE 0x1 /* enum */ 7336 #define MC_CMD_MUM_IN_GPIO_OUT_READ 0x2 /* enum */ 7337 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE 0x3 /* enum */ 7338 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ 0x4 /* enum */ 7339 #define MC_CMD_MUM_IN_GPIO_OP 0x5 /* enum */ 7340 7341 /* MC_CMD_MUM_IN_GPIO_IN_READ msgrequest */ 7342 #define MC_CMD_MUM_IN_GPIO_IN_READ_LEN 8 7343 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7344 #define MC_CMD_MUM_IN_GPIO_IN_READ_HDR_OFST 4 7345 7346 /* MC_CMD_MUM_IN_GPIO_OUT_WRITE msgrequest */ 7347 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_LEN 16 7348 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7349 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_HDR_OFST 4 7350 /* The first 32-bit word to be written to the GPIO OUT register. */ 7351 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK1_OFST 8 7352 /* The second 32-bit word to be written to the GPIO OUT register. */ 7353 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK2_OFST 12 7354 7355 /* MC_CMD_MUM_IN_GPIO_OUT_READ msgrequest */ 7356 #define MC_CMD_MUM_IN_GPIO_OUT_READ_LEN 8 7357 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7358 #define MC_CMD_MUM_IN_GPIO_OUT_READ_HDR_OFST 4 7359 7360 /* MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE msgrequest */ 7361 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_LEN 16 7362 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7363 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_HDR_OFST 4 7364 /* The first 32-bit word to be written to the GPIO OUT ENABLE register. */ 7365 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK1_OFST 8 7366 /* The second 32-bit word to be written to the GPIO OUT ENABLE register. */ 7367 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK2_OFST 12 7368 7369 /* MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ msgrequest */ 7370 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_LEN 8 7371 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7372 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_HDR_OFST 4 7373 7374 /* MC_CMD_MUM_IN_GPIO_OP msgrequest */ 7375 #define MC_CMD_MUM_IN_GPIO_OP_LEN 8 7376 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7377 #define MC_CMD_MUM_IN_GPIO_OP_HDR_OFST 4 7378 #define MC_CMD_MUM_IN_GPIO_OP_BITWISE_OP_LBN 8 7379 #define MC_CMD_MUM_IN_GPIO_OP_BITWISE_OP_WIDTH 8 7380 #define MC_CMD_MUM_IN_GPIO_OP_OUT_READ 0x0 /* enum */ 7381 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE 0x1 /* enum */ 7382 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG 0x2 /* enum */ 7383 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE 0x3 /* enum */ 7384 #define MC_CMD_MUM_IN_GPIO_OP_GPIO_NUMBER_LBN 16 7385 #define MC_CMD_MUM_IN_GPIO_OP_GPIO_NUMBER_WIDTH 8 7386 7387 /* MC_CMD_MUM_IN_GPIO_OP_OUT_READ msgrequest */ 7388 #define MC_CMD_MUM_IN_GPIO_OP_OUT_READ_LEN 8 7389 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7390 #define MC_CMD_MUM_IN_GPIO_OP_OUT_READ_HDR_OFST 4 7391 7392 /* MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE msgrequest */ 7393 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_LEN 8 7394 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7395 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_HDR_OFST 4 7396 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_WRITEBIT_LBN 24 7397 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_WRITEBIT_WIDTH 8 7398 7399 /* MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG msgrequest */ 7400 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_LEN 8 7401 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7402 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_HDR_OFST 4 7403 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_CFG_LBN 24 7404 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_CFG_WIDTH 8 7405 7406 /* MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE msgrequest */ 7407 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_LEN 8 7408 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7409 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_HDR_OFST 4 7410 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_ENABLEBIT_LBN 24 7411 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_ENABLEBIT_WIDTH 8 7412 7413 /* MC_CMD_MUM_IN_READ_SENSORS msgrequest */ 7414 #define MC_CMD_MUM_IN_READ_SENSORS_LEN 8 7415 /* MUM cmd header */ 7416 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7417 #define MC_CMD_MUM_IN_READ_SENSORS_PARAMS_OFST 4 7418 #define MC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_LBN 0 7419 #define MC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_WIDTH 8 7420 #define MC_CMD_MUM_IN_READ_SENSORS_NUM_SENSORS_LBN 8 7421 #define MC_CMD_MUM_IN_READ_SENSORS_NUM_SENSORS_WIDTH 8 7422 7423 /* MC_CMD_MUM_IN_PROGRAM_CLOCKS msgrequest */ 7424 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_LEN 12 7425 /* MUM cmd header */ 7426 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7427 /* Bit-mask of clocks to be programmed */ 7428 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_MASK_OFST 4 7429 #define MC_CMD_MUM_CLOCK_ID_FPGA 0x0 /* enum */ 7430 #define MC_CMD_MUM_CLOCK_ID_DDR 0x1 /* enum */ 7431 #define MC_CMD_MUM_CLOCK_ID_NIC 0x2 /* enum */ 7432 /* Control flags for clock programming */ 7433 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_FLAGS_OFST 8 7434 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_LBN 0 7435 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_WIDTH 1 7436 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_NIC_FROM_FPGA_LBN 1 7437 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_NIC_FROM_FPGA_WIDTH 1 7438 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_REF_FROM_XO_LBN 2 7439 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_REF_FROM_XO_WIDTH 1 7440 7441 /* MC_CMD_MUM_IN_FPGA_LOAD msgrequest */ 7442 #define MC_CMD_MUM_IN_FPGA_LOAD_LEN 8 7443 /* MUM cmd header */ 7444 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7445 /* Enable/Disable FPGA config from flash */ 7446 #define MC_CMD_MUM_IN_FPGA_LOAD_ENABLE_OFST 4 7447 7448 /* MC_CMD_MUM_IN_READ_ATB_SENSOR msgrequest */ 7449 #define MC_CMD_MUM_IN_READ_ATB_SENSOR_LEN 4 7450 /* MUM cmd header */ 7451 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7452 7453 /* MC_CMD_MUM_IN_QSFP msgrequest */ 7454 #define MC_CMD_MUM_IN_QSFP_LEN 12 7455 /* MUM cmd header */ 7456 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7457 #define MC_CMD_MUM_IN_QSFP_HDR_OFST 4 7458 #define MC_CMD_MUM_IN_QSFP_OPCODE_LBN 0 7459 #define MC_CMD_MUM_IN_QSFP_OPCODE_WIDTH 4 7460 #define MC_CMD_MUM_IN_QSFP_INIT 0x0 /* enum */ 7461 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE 0x1 /* enum */ 7462 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP 0x2 /* enum */ 7463 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO 0x3 /* enum */ 7464 #define MC_CMD_MUM_IN_QSFP_FILL_STATS 0x4 /* enum */ 7465 #define MC_CMD_MUM_IN_QSFP_POLL_BIST 0x5 /* enum */ 7466 #define MC_CMD_MUM_IN_QSFP_IDX_OFST 8 7467 7468 /* MC_CMD_MUM_IN_QSFP_INIT msgrequest */ 7469 #define MC_CMD_MUM_IN_QSFP_INIT_LEN 16 7470 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7471 #define MC_CMD_MUM_IN_QSFP_INIT_HDR_OFST 4 7472 #define MC_CMD_MUM_IN_QSFP_INIT_IDX_OFST 8 7473 #define MC_CMD_MUM_IN_QSFP_INIT_CAGE_OFST 12 7474 7475 /* MC_CMD_MUM_IN_QSFP_RECONFIGURE msgrequest */ 7476 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_LEN 24 7477 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7478 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_HDR_OFST 4 7479 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_IDX_OFST 8 7480 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_TX_DISABLE_OFST 12 7481 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LANES_OFST 16 7482 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LINK_SPEED_OFST 20 7483 7484 /* MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP msgrequest */ 7485 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_LEN 12 7486 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7487 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_HDR_OFST 4 7488 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_IDX_OFST 8 7489 7490 /* MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO msgrequest */ 7491 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_LEN 16 7492 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7493 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_HDR_OFST 4 7494 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_IDX_OFST 8 7495 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_PAGE_OFST 12 7496 7497 /* MC_CMD_MUM_IN_QSFP_FILL_STATS msgrequest */ 7498 #define MC_CMD_MUM_IN_QSFP_FILL_STATS_LEN 12 7499 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7500 #define MC_CMD_MUM_IN_QSFP_FILL_STATS_HDR_OFST 4 7501 #define MC_CMD_MUM_IN_QSFP_FILL_STATS_IDX_OFST 8 7502 7503 /* MC_CMD_MUM_IN_QSFP_POLL_BIST msgrequest */ 7504 #define MC_CMD_MUM_IN_QSFP_POLL_BIST_LEN 12 7505 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7506 #define MC_CMD_MUM_IN_QSFP_POLL_BIST_HDR_OFST 4 7507 #define MC_CMD_MUM_IN_QSFP_POLL_BIST_IDX_OFST 8 7508 7509 /* MC_CMD_MUM_IN_READ_DDR_INFO msgrequest */ 7510 #define MC_CMD_MUM_IN_READ_DDR_INFO_LEN 4 7511 /* MUM cmd header */ 7512 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7513 7514 /* MC_CMD_MUM_OUT msgresponse */ 7515 #define MC_CMD_MUM_OUT_LEN 0 7516 7517 /* MC_CMD_MUM_OUT_NULL msgresponse */ 7518 #define MC_CMD_MUM_OUT_NULL_LEN 0 7519 7520 /* MC_CMD_MUM_OUT_GET_VERSION msgresponse */ 7521 #define MC_CMD_MUM_OUT_GET_VERSION_LEN 12 7522 #define MC_CMD_MUM_OUT_GET_VERSION_FIRMWARE_OFST 0 7523 #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_OFST 4 7524 #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LEN 8 7525 #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LO_OFST 4 7526 #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_HI_OFST 8 7527 7528 /* MC_CMD_MUM_OUT_RAW_CMD msgresponse */ 7529 #define MC_CMD_MUM_OUT_RAW_CMD_LENMIN 1 7530 #define MC_CMD_MUM_OUT_RAW_CMD_LENMAX 252 7531 #define MC_CMD_MUM_OUT_RAW_CMD_LEN(num) (0+1*(num)) 7532 /* returned data */ 7533 #define MC_CMD_MUM_OUT_RAW_CMD_DATA_OFST 0 7534 #define MC_CMD_MUM_OUT_RAW_CMD_DATA_LEN 1 7535 #define MC_CMD_MUM_OUT_RAW_CMD_DATA_MINNUM 1 7536 #define MC_CMD_MUM_OUT_RAW_CMD_DATA_MAXNUM 252 7537 7538 /* MC_CMD_MUM_OUT_READ msgresponse */ 7539 #define MC_CMD_MUM_OUT_READ_LENMIN 4 7540 #define MC_CMD_MUM_OUT_READ_LENMAX 252 7541 #define MC_CMD_MUM_OUT_READ_LEN(num) (0+4*(num)) 7542 #define MC_CMD_MUM_OUT_READ_BUFFER_OFST 0 7543 #define MC_CMD_MUM_OUT_READ_BUFFER_LEN 4 7544 #define MC_CMD_MUM_OUT_READ_BUFFER_MINNUM 1 7545 #define MC_CMD_MUM_OUT_READ_BUFFER_MAXNUM 63 7546 7547 /* MC_CMD_MUM_OUT_WRITE msgresponse */ 7548 #define MC_CMD_MUM_OUT_WRITE_LEN 0 7549 7550 /* MC_CMD_MUM_OUT_LOG msgresponse */ 7551 #define MC_CMD_MUM_OUT_LOG_LEN 0 7552 7553 /* MC_CMD_MUM_OUT_LOG_OP_UART msgresponse */ 7554 #define MC_CMD_MUM_OUT_LOG_OP_UART_LEN 0 7555 7556 /* MC_CMD_MUM_OUT_GPIO_IN_READ msgresponse */ 7557 #define MC_CMD_MUM_OUT_GPIO_IN_READ_LEN 8 7558 /* The first 32-bit word read from the GPIO IN register. */ 7559 #define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK1_OFST 0 7560 /* The second 32-bit word read from the GPIO IN register. */ 7561 #define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK2_OFST 4 7562 7563 /* MC_CMD_MUM_OUT_GPIO_OUT_WRITE msgresponse */ 7564 #define MC_CMD_MUM_OUT_GPIO_OUT_WRITE_LEN 0 7565 7566 /* MC_CMD_MUM_OUT_GPIO_OUT_READ msgresponse */ 7567 #define MC_CMD_MUM_OUT_GPIO_OUT_READ_LEN 8 7568 /* The first 32-bit word read from the GPIO OUT register. */ 7569 #define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK1_OFST 0 7570 /* The second 32-bit word read from the GPIO OUT register. */ 7571 #define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK2_OFST 4 7572 7573 /* MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_WRITE msgresponse */ 7574 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_WRITE_LEN 0 7575 7576 /* MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ msgresponse */ 7577 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_LEN 8 7578 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK1_OFST 0 7579 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK2_OFST 4 7580 7581 /* MC_CMD_MUM_OUT_GPIO_OP_OUT_READ msgresponse */ 7582 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_LEN 4 7583 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_BIT_READ_OFST 0 7584 7585 /* MC_CMD_MUM_OUT_GPIO_OP_OUT_WRITE msgresponse */ 7586 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_WRITE_LEN 0 7587 7588 /* MC_CMD_MUM_OUT_GPIO_OP_OUT_CONFIG msgresponse */ 7589 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_CONFIG_LEN 0 7590 7591 /* MC_CMD_MUM_OUT_GPIO_OP_OUT_ENABLE msgresponse */ 7592 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_ENABLE_LEN 0 7593 7594 /* MC_CMD_MUM_OUT_READ_SENSORS msgresponse */ 7595 #define MC_CMD_MUM_OUT_READ_SENSORS_LENMIN 4 7596 #define MC_CMD_MUM_OUT_READ_SENSORS_LENMAX 252 7597 #define MC_CMD_MUM_OUT_READ_SENSORS_LEN(num) (0+4*(num)) 7598 #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_OFST 0 7599 #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_LEN 4 7600 #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_MINNUM 1 7601 #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_MAXNUM 63 7602 #define MC_CMD_MUM_OUT_READ_SENSORS_READING_LBN 0 7603 #define MC_CMD_MUM_OUT_READ_SENSORS_READING_WIDTH 16 7604 #define MC_CMD_MUM_OUT_READ_SENSORS_STATE_LBN 16 7605 #define MC_CMD_MUM_OUT_READ_SENSORS_STATE_WIDTH 8 7606 #define MC_CMD_MUM_OUT_READ_SENSORS_TYPE_LBN 24 7607 #define MC_CMD_MUM_OUT_READ_SENSORS_TYPE_WIDTH 8 7608 7609 /* MC_CMD_MUM_OUT_PROGRAM_CLOCKS msgresponse */ 7610 #define MC_CMD_MUM_OUT_PROGRAM_CLOCKS_LEN 4 7611 #define MC_CMD_MUM_OUT_PROGRAM_CLOCKS_OK_MASK_OFST 0 7612 7613 /* MC_CMD_MUM_OUT_FPGA_LOAD msgresponse */ 7614 #define MC_CMD_MUM_OUT_FPGA_LOAD_LEN 0 7615 7616 /* MC_CMD_MUM_OUT_READ_ATB_SENSOR msgresponse */ 7617 #define MC_CMD_MUM_OUT_READ_ATB_SENSOR_LEN 4 7618 #define MC_CMD_MUM_OUT_READ_ATB_SENSOR_RESULT_OFST 0 7619 7620 /* MC_CMD_MUM_OUT_QSFP_INIT msgresponse */ 7621 #define MC_CMD_MUM_OUT_QSFP_INIT_LEN 0 7622 7623 /* MC_CMD_MUM_OUT_QSFP_RECONFIGURE msgresponse */ 7624 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_LEN 8 7625 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LP_CAP_OFST 0 7626 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_FLAGS_OFST 4 7627 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_LBN 0 7628 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_WIDTH 1 7629 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_LBN 1 7630 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_WIDTH 1 7631 7632 /* MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP msgresponse */ 7633 #define MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_LEN 4 7634 #define MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_PORT_PHY_LP_CAP_OFST 0 7635 7636 /* MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO msgresponse */ 7637 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LENMIN 5 7638 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LENMAX 252 7639 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LEN(num) (4+1*(num)) 7640 /* in bytes */ 7641 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATALEN_OFST 0 7642 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_OFST 4 7643 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_LEN 1 7644 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_MINNUM 1 7645 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_MAXNUM 248 7646 7647 /* MC_CMD_MUM_OUT_QSFP_FILL_STATS msgresponse */ 7648 #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_LEN 8 7649 #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PMA_PMD_LINK_UP_OFST 0 7650 #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PCS_LINK_UP_OFST 4 7651 7652 /* MC_CMD_MUM_OUT_QSFP_POLL_BIST msgresponse */ 7653 #define MC_CMD_MUM_OUT_QSFP_POLL_BIST_LEN 4 7654 #define MC_CMD_MUM_OUT_QSFP_POLL_BIST_TEST_OFST 0 7655 7656 /* MC_CMD_MUM_OUT_READ_DDR_INFO msgresponse */ 7657 #define MC_CMD_MUM_OUT_READ_DDR_INFO_LENMIN 24 7658 #define MC_CMD_MUM_OUT_READ_DDR_INFO_LENMAX 248 7659 #define MC_CMD_MUM_OUT_READ_DDR_INFO_LEN(num) (8+8*(num)) 7660 /* Discrete (soldered) DDR resistor strap info */ 7661 #define MC_CMD_MUM_OUT_READ_DDR_INFO_DISCRETE_DDR_INFO_OFST 0 7662 #define MC_CMD_MUM_OUT_READ_DDR_INFO_VRATIO_LBN 0 7663 #define MC_CMD_MUM_OUT_READ_DDR_INFO_VRATIO_WIDTH 16 7664 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED1_LBN 16 7665 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED1_WIDTH 16 7666 /* Number of SODIMM info records */ 7667 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_RECORDS_OFST 4 7668 /* Array of SODIMM info records */ 7669 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_OFST 8 7670 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LEN 8 7671 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LO_OFST 8 7672 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_HI_OFST 12 7673 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MINNUM 2 7674 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MAXNUM 30 7675 #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK_ID_LBN 0 7676 #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK_ID_WIDTH 8 7677 /* enum: SODIMM bank 1 (Top SODIMM for Sorrento) */ 7678 #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK1 0x0 7679 /* enum: SODIMM bank 2 (Bottom SODDIMM for Sorrento) */ 7680 #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK2 0x1 7681 /* enum: Total number of SODIMM banks */ 7682 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_BANKS 0x2 7683 #define MC_CMD_MUM_OUT_READ_DDR_INFO_TYPE_LBN 8 7684 #define MC_CMD_MUM_OUT_READ_DDR_INFO_TYPE_WIDTH 8 7685 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RANK_LBN 16 7686 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RANK_WIDTH 4 7687 #define MC_CMD_MUM_OUT_READ_DDR_INFO_VOLTAGE_LBN 20 7688 #define MC_CMD_MUM_OUT_READ_DDR_INFO_VOLTAGE_WIDTH 4 7689 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NOT_POWERED 0x0 /* enum */ 7690 #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V25 0x1 /* enum */ 7691 #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V35 0x2 /* enum */ 7692 #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V5 0x3 /* enum */ 7693 /* enum: Values 5-15 are reserved for future usage */ 7694 #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V8 0x4 7695 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SIZE_LBN 24 7696 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SIZE_WIDTH 8 7697 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SPEED_LBN 32 7698 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SPEED_WIDTH 16 7699 #define MC_CMD_MUM_OUT_READ_DDR_INFO_STATE_LBN 48 7700 #define MC_CMD_MUM_OUT_READ_DDR_INFO_STATE_WIDTH 4 7701 /* enum: No module present */ 7702 #define MC_CMD_MUM_OUT_READ_DDR_INFO_ABSENT 0x0 7703 /* enum: Module present supported and powered on */ 7704 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_POWERED 0x1 7705 /* enum: Module present but bad type */ 7706 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_TYPE 0x2 7707 /* enum: Module present but incompatible voltage */ 7708 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_VOLTAGE 0x3 7709 /* enum: Module present but unknown SPD */ 7710 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_SPD 0x4 7711 /* enum: Module present but slot cannot support it */ 7712 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_SLOT 0x5 7713 /* enum: Modules may or may not be present, but cannot establish contact by I2C 7714 */ 7715 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NOT_REACHABLE 0x6 7716 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED2_LBN 52 7717 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED2_WIDTH 12 7718 7719 /* MC_CMD_RESOURCE_SPECIFIER enum */ 7720 /* enum: Any */ 7721 #define MC_CMD_RESOURCE_INSTANCE_ANY 0xffffffff 7722 /* enum: None */ 7723 #define MC_CMD_RESOURCE_INSTANCE_NONE 0xfffffffe 7724 7725 /* EVB_PORT_ID structuredef */ 7726 #define EVB_PORT_ID_LEN 4 7727 #define EVB_PORT_ID_PORT_ID_OFST 0 7728 /* enum: An invalid port handle. */ 7729 #define EVB_PORT_ID_NULL 0x0 7730 /* enum: The port assigned to this function.. */ 7731 #define EVB_PORT_ID_ASSIGNED 0x1000000 7732 /* enum: External network port 0 */ 7733 #define EVB_PORT_ID_MAC0 0x2000000 7734 /* enum: External network port 1 */ 7735 #define EVB_PORT_ID_MAC1 0x2000001 7736 /* enum: External network port 2 */ 7737 #define EVB_PORT_ID_MAC2 0x2000002 7738 /* enum: External network port 3 */ 7739 #define EVB_PORT_ID_MAC3 0x2000003 7740 #define EVB_PORT_ID_PORT_ID_LBN 0 7741 #define EVB_PORT_ID_PORT_ID_WIDTH 32 7742 7743 /* EVB_VLAN_TAG structuredef */ 7744 #define EVB_VLAN_TAG_LEN 2 7745 /* The VLAN tag value */ 7746 #define EVB_VLAN_TAG_VLAN_ID_LBN 0 7747 #define EVB_VLAN_TAG_VLAN_ID_WIDTH 12 7748 #define EVB_VLAN_TAG_MODE_LBN 12 7749 #define EVB_VLAN_TAG_MODE_WIDTH 4 7750 /* enum: Insert the VLAN. */ 7751 #define EVB_VLAN_TAG_INSERT 0x0 7752 /* enum: Replace the VLAN if already present. */ 7753 #define EVB_VLAN_TAG_REPLACE 0x1 7754 7755 /* BUFTBL_ENTRY structuredef */ 7756 #define BUFTBL_ENTRY_LEN 12 7757 /* the owner ID */ 7758 #define BUFTBL_ENTRY_OID_OFST 0 7759 #define BUFTBL_ENTRY_OID_LEN 2 7760 #define BUFTBL_ENTRY_OID_LBN 0 7761 #define BUFTBL_ENTRY_OID_WIDTH 16 7762 /* the page parameter as one of ESE_DZ_SMC_PAGE_SIZE_ */ 7763 #define BUFTBL_ENTRY_PGSZ_OFST 2 7764 #define BUFTBL_ENTRY_PGSZ_LEN 2 7765 #define BUFTBL_ENTRY_PGSZ_LBN 16 7766 #define BUFTBL_ENTRY_PGSZ_WIDTH 16 7767 /* the raw 64-bit address field from the SMC, not adjusted for page size */ 7768 #define BUFTBL_ENTRY_RAWADDR_OFST 4 7769 #define BUFTBL_ENTRY_RAWADDR_LEN 8 7770 #define BUFTBL_ENTRY_RAWADDR_LO_OFST 4 7771 #define BUFTBL_ENTRY_RAWADDR_HI_OFST 8 7772 #define BUFTBL_ENTRY_RAWADDR_LBN 32 7773 #define BUFTBL_ENTRY_RAWADDR_WIDTH 64 7774 7775 /* NVRAM_PARTITION_TYPE structuredef */ 7776 #define NVRAM_PARTITION_TYPE_LEN 2 7777 #define NVRAM_PARTITION_TYPE_ID_OFST 0 7778 #define NVRAM_PARTITION_TYPE_ID_LEN 2 7779 /* enum: Primary MC firmware partition */ 7780 #define NVRAM_PARTITION_TYPE_MC_FIRMWARE 0x100 7781 /* enum: Secondary MC firmware partition */ 7782 #define NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP 0x200 7783 /* enum: Expansion ROM partition */ 7784 #define NVRAM_PARTITION_TYPE_EXPANSION_ROM 0x300 7785 /* enum: Static configuration TLV partition */ 7786 #define NVRAM_PARTITION_TYPE_STATIC_CONFIG 0x400 7787 /* enum: Dynamic configuration TLV partition */ 7788 #define NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG 0x500 7789 /* enum: Expansion ROM configuration data for port 0 */ 7790 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0 0x600 7791 /* enum: Synonym for EXPROM_CONFIG_PORT0 as used in pmap files */ 7792 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG 0x600 7793 /* enum: Expansion ROM configuration data for port 1 */ 7794 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1 0x601 7795 /* enum: Expansion ROM configuration data for port 2 */ 7796 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2 0x602 7797 /* enum: Expansion ROM configuration data for port 3 */ 7798 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3 0x603 7799 /* enum: Non-volatile log output partition */ 7800 #define NVRAM_PARTITION_TYPE_LOG 0x700 7801 /* enum: Non-volatile log output of second core on dual-core device */ 7802 #define NVRAM_PARTITION_TYPE_LOG_SLAVE 0x701 7803 /* enum: Device state dump output partition */ 7804 #define NVRAM_PARTITION_TYPE_DUMP 0x800 7805 /* enum: Application license key storage partition */ 7806 #define NVRAM_PARTITION_TYPE_LICENSE 0x900 7807 /* enum: Start of range used for PHY partitions (low 8 bits are the PHY ID) */ 7808 #define NVRAM_PARTITION_TYPE_PHY_MIN 0xa00 7809 /* enum: End of range used for PHY partitions (low 8 bits are the PHY ID) */ 7810 #define NVRAM_PARTITION_TYPE_PHY_MAX 0xaff 7811 /* enum: Primary FPGA partition */ 7812 #define NVRAM_PARTITION_TYPE_FPGA 0xb00 7813 /* enum: Secondary FPGA partition */ 7814 #define NVRAM_PARTITION_TYPE_FPGA_BACKUP 0xb01 7815 /* enum: FC firmware partition */ 7816 #define NVRAM_PARTITION_TYPE_FC_FIRMWARE 0xb02 7817 /* enum: FC License partition */ 7818 #define NVRAM_PARTITION_TYPE_FC_LICENSE 0xb03 7819 /* enum: Non-volatile log output partition for FC */ 7820 #define NVRAM_PARTITION_TYPE_FC_LOG 0xb04 7821 /* enum: MUM firmware partition */ 7822 #define NVRAM_PARTITION_TYPE_MUM_FIRMWARE 0xc00 7823 /* enum: MUM Non-volatile log output partition. */ 7824 #define NVRAM_PARTITION_TYPE_MUM_LOG 0xc01 7825 /* enum: MUM Application table partition. */ 7826 #define NVRAM_PARTITION_TYPE_MUM_APPTABLE 0xc02 7827 /* enum: MUM boot rom partition. */ 7828 #define NVRAM_PARTITION_TYPE_MUM_BOOT_ROM 0xc03 7829 /* enum: MUM production signatures & calibration rom partition. */ 7830 #define NVRAM_PARTITION_TYPE_MUM_PROD_ROM 0xc04 7831 /* enum: MUM user signatures & calibration rom partition. */ 7832 #define NVRAM_PARTITION_TYPE_MUM_USER_ROM 0xc05 7833 /* enum: MUM fuses and lockbits partition. */ 7834 #define NVRAM_PARTITION_TYPE_MUM_FUSELOCK 0xc06 7835 /* enum: UEFI expansion ROM if separate from PXE */ 7836 #define NVRAM_PARTITION_TYPE_EXPANSION_UEFI 0xd00 7837 /* enum: Spare partition 0 */ 7838 #define NVRAM_PARTITION_TYPE_SPARE_0 0x1000 7839 /* enum: Spare partition 1 */ 7840 #define NVRAM_PARTITION_TYPE_SPARE_1 0x1100 7841 /* enum: Spare partition 2 */ 7842 #define NVRAM_PARTITION_TYPE_SPARE_2 0x1200 7843 /* enum: Spare partition 3 */ 7844 #define NVRAM_PARTITION_TYPE_SPARE_3 0x1300 7845 /* enum: Spare partition 4 */ 7846 #define NVRAM_PARTITION_TYPE_SPARE_4 0x1400 7847 /* enum: Spare partition 5 */ 7848 #define NVRAM_PARTITION_TYPE_SPARE_5 0x1500 7849 /* enum: Start of reserved value range (firmware may use for any purpose) */ 7850 #define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MIN 0xff00 7851 /* enum: End of reserved value range (firmware may use for any purpose) */ 7852 #define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MAX 0xfffd 7853 /* enum: Recovery partition map (provided if real map is missing or corrupt) */ 7854 #define NVRAM_PARTITION_TYPE_RECOVERY_MAP 0xfffe 7855 /* enum: Partition map (real map as stored in flash) */ 7856 #define NVRAM_PARTITION_TYPE_PARTITION_MAP 0xffff 7857 #define NVRAM_PARTITION_TYPE_ID_LBN 0 7858 #define NVRAM_PARTITION_TYPE_ID_WIDTH 16 7859 7860 /* LICENSED_APP_ID structuredef */ 7861 #define LICENSED_APP_ID_LEN 4 7862 #define LICENSED_APP_ID_ID_OFST 0 7863 /* enum: OpenOnload */ 7864 #define LICENSED_APP_ID_ONLOAD 0x1 7865 /* enum: PTP timestamping */ 7866 #define LICENSED_APP_ID_PTP 0x2 7867 /* enum: SolarCapture Pro */ 7868 #define LICENSED_APP_ID_SOLARCAPTURE_PRO 0x4 7869 /* enum: SolarSecure filter engine */ 7870 #define LICENSED_APP_ID_SOLARSECURE 0x8 7871 /* enum: Performance monitor */ 7872 #define LICENSED_APP_ID_PERF_MONITOR 0x10 7873 /* enum: SolarCapture Live */ 7874 #define LICENSED_APP_ID_SOLARCAPTURE_LIVE 0x20 7875 /* enum: Capture SolarSystem */ 7876 #define LICENSED_APP_ID_CAPTURE_SOLARSYSTEM 0x40 7877 /* enum: Network Access Control */ 7878 #define LICENSED_APP_ID_NETWORK_ACCESS_CONTROL 0x80 7879 #define LICENSED_APP_ID_ID_LBN 0 7880 #define LICENSED_APP_ID_ID_WIDTH 32 7881 7882 /* LICENSED_FEATURES structuredef */ 7883 #define LICENSED_FEATURES_LEN 8 7884 /* Bitmask of licensed firmware features */ 7885 #define LICENSED_FEATURES_MASK_OFST 0 7886 #define LICENSED_FEATURES_MASK_LEN 8 7887 #define LICENSED_FEATURES_MASK_LO_OFST 0 7888 #define LICENSED_FEATURES_MASK_HI_OFST 4 7889 #define LICENSED_FEATURES_RX_CUT_THROUGH_LBN 0 7890 #define LICENSED_FEATURES_RX_CUT_THROUGH_WIDTH 1 7891 #define LICENSED_FEATURES_PIO_LBN 1 7892 #define LICENSED_FEATURES_PIO_WIDTH 1 7893 #define LICENSED_FEATURES_EVQ_TIMER_LBN 2 7894 #define LICENSED_FEATURES_EVQ_TIMER_WIDTH 1 7895 #define LICENSED_FEATURES_CLOCK_LBN 3 7896 #define LICENSED_FEATURES_CLOCK_WIDTH 1 7897 #define LICENSED_FEATURES_RX_TIMESTAMPS_LBN 4 7898 #define LICENSED_FEATURES_RX_TIMESTAMPS_WIDTH 1 7899 #define LICENSED_FEATURES_TX_TIMESTAMPS_LBN 5 7900 #define LICENSED_FEATURES_TX_TIMESTAMPS_WIDTH 1 7901 #define LICENSED_FEATURES_RX_SNIFF_LBN 6 7902 #define LICENSED_FEATURES_RX_SNIFF_WIDTH 1 7903 #define LICENSED_FEATURES_TX_SNIFF_LBN 7 7904 #define LICENSED_FEATURES_TX_SNIFF_WIDTH 1 7905 #define LICENSED_FEATURES_PROXY_FILTER_OPS_LBN 8 7906 #define LICENSED_FEATURES_PROXY_FILTER_OPS_WIDTH 1 7907 #define LICENSED_FEATURES_MASK_LBN 0 7908 #define LICENSED_FEATURES_MASK_WIDTH 64 7909 7910 /* LICENSED_V3_APPS structuredef */ 7911 #define LICENSED_V3_APPS_LEN 8 7912 /* Bitmask of licensed applications */ 7913 #define LICENSED_V3_APPS_MASK_OFST 0 7914 #define LICENSED_V3_APPS_MASK_LEN 8 7915 #define LICENSED_V3_APPS_MASK_LO_OFST 0 7916 #define LICENSED_V3_APPS_MASK_HI_OFST 4 7917 #define LICENSED_V3_APPS_ONLOAD_LBN 0 7918 #define LICENSED_V3_APPS_ONLOAD_WIDTH 1 7919 #define LICENSED_V3_APPS_PTP_LBN 1 7920 #define LICENSED_V3_APPS_PTP_WIDTH 1 7921 #define LICENSED_V3_APPS_SOLARCAPTURE_PRO_LBN 2 7922 #define LICENSED_V3_APPS_SOLARCAPTURE_PRO_WIDTH 1 7923 #define LICENSED_V3_APPS_SOLARSECURE_LBN 3 7924 #define LICENSED_V3_APPS_SOLARSECURE_WIDTH 1 7925 #define LICENSED_V3_APPS_PERF_MONITOR_LBN 4 7926 #define LICENSED_V3_APPS_PERF_MONITOR_WIDTH 1 7927 #define LICENSED_V3_APPS_SOLARCAPTURE_LIVE_LBN 5 7928 #define LICENSED_V3_APPS_SOLARCAPTURE_LIVE_WIDTH 1 7929 #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_LBN 6 7930 #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_WIDTH 1 7931 #define LICENSED_V3_APPS_NETWORK_ACCESS_CONTROL_LBN 7 7932 #define LICENSED_V3_APPS_NETWORK_ACCESS_CONTROL_WIDTH 1 7933 #define LICENSED_V3_APPS_MASK_LBN 0 7934 #define LICENSED_V3_APPS_MASK_WIDTH 64 7935 7936 /* LICENSED_V3_FEATURES structuredef */ 7937 #define LICENSED_V3_FEATURES_LEN 8 7938 /* Bitmask of licensed firmware features */ 7939 #define LICENSED_V3_FEATURES_MASK_OFST 0 7940 #define LICENSED_V3_FEATURES_MASK_LEN 8 7941 #define LICENSED_V3_FEATURES_MASK_LO_OFST 0 7942 #define LICENSED_V3_FEATURES_MASK_HI_OFST 4 7943 #define LICENSED_V3_FEATURES_RX_CUT_THROUGH_LBN 0 7944 #define LICENSED_V3_FEATURES_RX_CUT_THROUGH_WIDTH 1 7945 #define LICENSED_V3_FEATURES_PIO_LBN 1 7946 #define LICENSED_V3_FEATURES_PIO_WIDTH 1 7947 #define LICENSED_V3_FEATURES_EVQ_TIMER_LBN 2 7948 #define LICENSED_V3_FEATURES_EVQ_TIMER_WIDTH 1 7949 #define LICENSED_V3_FEATURES_CLOCK_LBN 3 7950 #define LICENSED_V3_FEATURES_CLOCK_WIDTH 1 7951 #define LICENSED_V3_FEATURES_RX_TIMESTAMPS_LBN 4 7952 #define LICENSED_V3_FEATURES_RX_TIMESTAMPS_WIDTH 1 7953 #define LICENSED_V3_FEATURES_TX_TIMESTAMPS_LBN 5 7954 #define LICENSED_V3_FEATURES_TX_TIMESTAMPS_WIDTH 1 7955 #define LICENSED_V3_FEATURES_RX_SNIFF_LBN 6 7956 #define LICENSED_V3_FEATURES_RX_SNIFF_WIDTH 1 7957 #define LICENSED_V3_FEATURES_TX_SNIFF_LBN 7 7958 #define LICENSED_V3_FEATURES_TX_SNIFF_WIDTH 1 7959 #define LICENSED_V3_FEATURES_PROXY_FILTER_OPS_LBN 8 7960 #define LICENSED_V3_FEATURES_PROXY_FILTER_OPS_WIDTH 1 7961 #define LICENSED_V3_FEATURES_MASK_LBN 0 7962 #define LICENSED_V3_FEATURES_MASK_WIDTH 64 7963 7964 /* TX_TIMESTAMP_EVENT structuredef */ 7965 #define TX_TIMESTAMP_EVENT_LEN 6 7966 /* lower 16 bits of timestamp data */ 7967 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_OFST 0 7968 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_LEN 2 7969 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_LBN 0 7970 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_WIDTH 16 7971 /* Type of TX event, ordinary TX completion, low or high part of TX timestamp 7972 */ 7973 #define TX_TIMESTAMP_EVENT_TX_EV_TYPE_OFST 3 7974 #define TX_TIMESTAMP_EVENT_TX_EV_TYPE_LEN 1 7975 /* enum: This is a TX completion event, not a timestamp */ 7976 #define TX_TIMESTAMP_EVENT_TX_EV_COMPLETION 0x0 7977 /* enum: This is the low part of a TX timestamp event */ 7978 #define TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_LO 0x51 7979 /* enum: This is the high part of a TX timestamp event */ 7980 #define TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_HI 0x52 7981 #define TX_TIMESTAMP_EVENT_TX_EV_TYPE_LBN 24 7982 #define TX_TIMESTAMP_EVENT_TX_EV_TYPE_WIDTH 8 7983 /* upper 16 bits of timestamp data */ 7984 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_OFST 4 7985 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_LEN 2 7986 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_LBN 32 7987 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_WIDTH 16 7988 7989 /* RSS_MODE structuredef */ 7990 #define RSS_MODE_LEN 1 7991 /* The RSS mode for a particular packet type is a value from 0 - 15 which can 7992 * be considered as 4 bits selecting which fields are included in the hash. (A 7993 * value 0 effectively disables RSS spreading for the packet type.) The YAML 7994 * generation tools require this structure to be a whole number of bytes wide, 7995 * but only 4 bits are relevant. 7996 */ 7997 #define RSS_MODE_HASH_SELECTOR_OFST 0 7998 #define RSS_MODE_HASH_SELECTOR_LEN 1 7999 #define RSS_MODE_HASH_SRC_ADDR_LBN 0 8000 #define RSS_MODE_HASH_SRC_ADDR_WIDTH 1 8001 #define RSS_MODE_HASH_DST_ADDR_LBN 1 8002 #define RSS_MODE_HASH_DST_ADDR_WIDTH 1 8003 #define RSS_MODE_HASH_SRC_PORT_LBN 2 8004 #define RSS_MODE_HASH_SRC_PORT_WIDTH 1 8005 #define RSS_MODE_HASH_DST_PORT_LBN 3 8006 #define RSS_MODE_HASH_DST_PORT_WIDTH 1 8007 #define RSS_MODE_HASH_SELECTOR_LBN 0 8008 #define RSS_MODE_HASH_SELECTOR_WIDTH 8 8009 8010 8011 /***********************************/ 8012 /* MC_CMD_READ_REGS 8013 * Get a dump of the MCPU registers 8014 */ 8015 #define MC_CMD_READ_REGS 0x50 8016 #undef MC_CMD_0x50_PRIVILEGE_CTG 8017 8018 #define MC_CMD_0x50_PRIVILEGE_CTG SRIOV_CTG_ADMIN 8019 8020 /* MC_CMD_READ_REGS_IN msgrequest */ 8021 #define MC_CMD_READ_REGS_IN_LEN 0 8022 8023 /* MC_CMD_READ_REGS_OUT msgresponse */ 8024 #define MC_CMD_READ_REGS_OUT_LEN 308 8025 /* Whether the corresponding register entry contains a valid value */ 8026 #define MC_CMD_READ_REGS_OUT_MASK_OFST 0 8027 #define MC_CMD_READ_REGS_OUT_MASK_LEN 16 8028 /* Same order as MIPS GDB (r0-r31, sr, lo, hi, bad, cause, 32 x float, fsr, 8029 * fir, fp) 8030 */ 8031 #define MC_CMD_READ_REGS_OUT_REGS_OFST 16 8032 #define MC_CMD_READ_REGS_OUT_REGS_LEN 4 8033 #define MC_CMD_READ_REGS_OUT_REGS_NUM 73 8034 8035 8036 /***********************************/ 8037 /* MC_CMD_INIT_EVQ 8038 * Set up an event queue according to the supplied parameters. The IN arguments 8039 * end with an address for each 4k of host memory required to back the EVQ. 8040 */ 8041 #define MC_CMD_INIT_EVQ 0x80 8042 #undef MC_CMD_0x80_PRIVILEGE_CTG 8043 8044 #define MC_CMD_0x80_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8045 8046 /* MC_CMD_INIT_EVQ_IN msgrequest */ 8047 #define MC_CMD_INIT_EVQ_IN_LENMIN 44 8048 #define MC_CMD_INIT_EVQ_IN_LENMAX 548 8049 #define MC_CMD_INIT_EVQ_IN_LEN(num) (36+8*(num)) 8050 /* Size, in entries */ 8051 #define MC_CMD_INIT_EVQ_IN_SIZE_OFST 0 8052 /* Desired instance. Must be set to a specific instance, which is a function 8053 * local queue index. 8054 */ 8055 #define MC_CMD_INIT_EVQ_IN_INSTANCE_OFST 4 8056 /* The initial timer value. The load value is ignored if the timer mode is DIS. 8057 */ 8058 #define MC_CMD_INIT_EVQ_IN_TMR_LOAD_OFST 8 8059 /* The reload value is ignored in one-shot modes */ 8060 #define MC_CMD_INIT_EVQ_IN_TMR_RELOAD_OFST 12 8061 /* tbd */ 8062 #define MC_CMD_INIT_EVQ_IN_FLAGS_OFST 16 8063 #define MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_LBN 0 8064 #define MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_WIDTH 1 8065 #define MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_LBN 1 8066 #define MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_WIDTH 1 8067 #define MC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_LBN 2 8068 #define MC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_WIDTH 1 8069 #define MC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_LBN 3 8070 #define MC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_WIDTH 1 8071 #define MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_LBN 4 8072 #define MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_WIDTH 1 8073 #define MC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_LBN 5 8074 #define MC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_WIDTH 1 8075 #define MC_CMD_INIT_EVQ_IN_TMR_MODE_OFST 20 8076 /* enum: Disabled */ 8077 #define MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS 0x0 8078 /* enum: Immediate */ 8079 #define MC_CMD_INIT_EVQ_IN_TMR_IMMED_START 0x1 8080 /* enum: Triggered */ 8081 #define MC_CMD_INIT_EVQ_IN_TMR_TRIG_START 0x2 8082 /* enum: Hold-off */ 8083 #define MC_CMD_INIT_EVQ_IN_TMR_INT_HLDOFF 0x3 8084 /* Target EVQ for wakeups if in wakeup mode. */ 8085 #define MC_CMD_INIT_EVQ_IN_TARGET_EVQ_OFST 24 8086 /* Target interrupt if in interrupting mode (note union with target EVQ). Use 8087 * MC_CMD_RESOURCE_INSTANCE_ANY unless a specific one required for test 8088 * purposes. 8089 */ 8090 #define MC_CMD_INIT_EVQ_IN_IRQ_NUM_OFST 24 8091 /* Event Counter Mode. */ 8092 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_OFST 28 8093 /* enum: Disabled */ 8094 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS 0x0 8095 /* enum: Disabled */ 8096 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_RX 0x1 8097 /* enum: Disabled */ 8098 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_TX 0x2 8099 /* enum: Disabled */ 8100 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_RXTX 0x3 8101 /* Event queue packet count threshold. */ 8102 #define MC_CMD_INIT_EVQ_IN_COUNT_THRSHLD_OFST 32 8103 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 8104 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_OFST 36 8105 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LEN 8 8106 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LO_OFST 36 8107 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_HI_OFST 40 8108 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MINNUM 1 8109 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MAXNUM 64 8110 8111 /* MC_CMD_INIT_EVQ_OUT msgresponse */ 8112 #define MC_CMD_INIT_EVQ_OUT_LEN 4 8113 /* Only valid if INTRFLAG was true */ 8114 #define MC_CMD_INIT_EVQ_OUT_IRQ_OFST 0 8115 8116 /* QUEUE_CRC_MODE structuredef */ 8117 #define QUEUE_CRC_MODE_LEN 1 8118 #define QUEUE_CRC_MODE_MODE_LBN 0 8119 #define QUEUE_CRC_MODE_MODE_WIDTH 4 8120 /* enum: No CRC. */ 8121 #define QUEUE_CRC_MODE_NONE 0x0 8122 /* enum: CRC Fiber channel over ethernet. */ 8123 #define QUEUE_CRC_MODE_FCOE 0x1 8124 /* enum: CRC (digest) iSCSI header only. */ 8125 #define QUEUE_CRC_MODE_ISCSI_HDR 0x2 8126 /* enum: CRC (digest) iSCSI header and payload. */ 8127 #define QUEUE_CRC_MODE_ISCSI 0x3 8128 /* enum: CRC Fiber channel over IP over ethernet. */ 8129 #define QUEUE_CRC_MODE_FCOIPOE 0x4 8130 /* enum: CRC MPA. */ 8131 #define QUEUE_CRC_MODE_MPA 0x5 8132 #define QUEUE_CRC_MODE_SPARE_LBN 4 8133 #define QUEUE_CRC_MODE_SPARE_WIDTH 4 8134 8135 8136 /***********************************/ 8137 /* MC_CMD_INIT_RXQ 8138 * set up a receive queue according to the supplied parameters. The IN 8139 * arguments end with an address for each 4k of host memory required to back 8140 * the RXQ. 8141 */ 8142 #define MC_CMD_INIT_RXQ 0x81 8143 #undef MC_CMD_0x81_PRIVILEGE_CTG 8144 8145 #define MC_CMD_0x81_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8146 8147 /* MC_CMD_INIT_RXQ_IN msgrequest: Legacy RXQ_INIT request. Use extended version 8148 * in new code. 8149 */ 8150 #define MC_CMD_INIT_RXQ_IN_LENMIN 36 8151 #define MC_CMD_INIT_RXQ_IN_LENMAX 252 8152 #define MC_CMD_INIT_RXQ_IN_LEN(num) (28+8*(num)) 8153 /* Size, in entries */ 8154 #define MC_CMD_INIT_RXQ_IN_SIZE_OFST 0 8155 /* The EVQ to send events to. This is an index originally specified to INIT_EVQ 8156 */ 8157 #define MC_CMD_INIT_RXQ_IN_TARGET_EVQ_OFST 4 8158 /* The value to put in the event data. Check hardware spec. for valid range. */ 8159 #define MC_CMD_INIT_RXQ_IN_LABEL_OFST 8 8160 /* Desired instance. Must be set to a specific instance, which is a function 8161 * local queue index. 8162 */ 8163 #define MC_CMD_INIT_RXQ_IN_INSTANCE_OFST 12 8164 /* There will be more flags here. */ 8165 #define MC_CMD_INIT_RXQ_IN_FLAGS_OFST 16 8166 #define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_LBN 0 8167 #define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_WIDTH 1 8168 #define MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_LBN 1 8169 #define MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_WIDTH 1 8170 #define MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_LBN 2 8171 #define MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_WIDTH 1 8172 #define MC_CMD_INIT_RXQ_IN_CRC_MODE_LBN 3 8173 #define MC_CMD_INIT_RXQ_IN_CRC_MODE_WIDTH 4 8174 #define MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_LBN 7 8175 #define MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_WIDTH 1 8176 #define MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_LBN 8 8177 #define MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_WIDTH 1 8178 #define MC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_LBN 9 8179 #define MC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_WIDTH 1 8180 #define MC_CMD_INIT_RXQ_IN_FLAG_FORCE_EV_MERGING_LBN 10 8181 #define MC_CMD_INIT_RXQ_IN_FLAG_FORCE_EV_MERGING_WIDTH 1 8182 /* Owner ID to use if in buffer mode (zero if physical) */ 8183 #define MC_CMD_INIT_RXQ_IN_OWNER_ID_OFST 20 8184 /* The port ID associated with the v-adaptor which should contain this DMAQ. */ 8185 #define MC_CMD_INIT_RXQ_IN_PORT_ID_OFST 24 8186 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 8187 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_OFST 28 8188 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LEN 8 8189 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LO_OFST 28 8190 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_HI_OFST 32 8191 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MINNUM 1 8192 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MAXNUM 28 8193 8194 /* MC_CMD_INIT_RXQ_EXT_IN msgrequest: Extended RXQ_INIT with additional mode 8195 * flags 8196 */ 8197 #define MC_CMD_INIT_RXQ_EXT_IN_LEN 544 8198 /* Size, in entries */ 8199 #define MC_CMD_INIT_RXQ_EXT_IN_SIZE_OFST 0 8200 /* The EVQ to send events to. This is an index originally specified to INIT_EVQ 8201 */ 8202 #define MC_CMD_INIT_RXQ_EXT_IN_TARGET_EVQ_OFST 4 8203 /* The value to put in the event data. Check hardware spec. for valid range. */ 8204 #define MC_CMD_INIT_RXQ_EXT_IN_LABEL_OFST 8 8205 /* Desired instance. Must be set to a specific instance, which is a function 8206 * local queue index. 8207 */ 8208 #define MC_CMD_INIT_RXQ_EXT_IN_INSTANCE_OFST 12 8209 /* There will be more flags here. */ 8210 #define MC_CMD_INIT_RXQ_EXT_IN_FLAGS_OFST 16 8211 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_LBN 0 8212 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_WIDTH 1 8213 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT_LBN 1 8214 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT_WIDTH 1 8215 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_TIMESTAMP_LBN 2 8216 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_TIMESTAMP_WIDTH 1 8217 #define MC_CMD_INIT_RXQ_EXT_IN_CRC_MODE_LBN 3 8218 #define MC_CMD_INIT_RXQ_EXT_IN_CRC_MODE_WIDTH 4 8219 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_CHAIN_LBN 7 8220 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_CHAIN_WIDTH 1 8221 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_PREFIX_LBN 8 8222 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_PREFIX_WIDTH 1 8223 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER_LBN 9 8224 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER_WIDTH 1 8225 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_LBN 10 8226 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_WIDTH 4 8227 /* enum: One packet per descriptor (for normal networking) */ 8228 #define MC_CMD_INIT_RXQ_EXT_IN_SINGLE_PACKET 0x0 8229 /* enum: Pack multiple packets into large descriptors (for SolarCapture) */ 8230 #define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM 0x1 8231 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_LBN 14 8232 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_WIDTH 1 8233 #define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE_LBN 15 8234 #define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE_WIDTH 3 8235 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_1M 0x0 /* enum */ 8236 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_512K 0x1 /* enum */ 8237 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_256K 0x2 /* enum */ 8238 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_128K 0x3 /* enum */ 8239 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_64K 0x4 /* enum */ 8240 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES_LBN 18 8241 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 1 8242 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_FORCE_EV_MERGING_LBN 19 8243 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_FORCE_EV_MERGING_WIDTH 1 8244 /* Owner ID to use if in buffer mode (zero if physical) */ 8245 #define MC_CMD_INIT_RXQ_EXT_IN_OWNER_ID_OFST 20 8246 /* The port ID associated with the v-adaptor which should contain this DMAQ. */ 8247 #define MC_CMD_INIT_RXQ_EXT_IN_PORT_ID_OFST 24 8248 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 8249 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_OFST 28 8250 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LEN 8 8251 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LO_OFST 28 8252 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_HI_OFST 32 8253 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_NUM 64 8254 /* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */ 8255 #define MC_CMD_INIT_RXQ_EXT_IN_SNAPSHOT_LENGTH_OFST 540 8256 8257 /* MC_CMD_INIT_RXQ_OUT msgresponse */ 8258 #define MC_CMD_INIT_RXQ_OUT_LEN 0 8259 8260 /* MC_CMD_INIT_RXQ_EXT_OUT msgresponse */ 8261 #define MC_CMD_INIT_RXQ_EXT_OUT_LEN 0 8262 8263 8264 /***********************************/ 8265 /* MC_CMD_INIT_TXQ 8266 */ 8267 #define MC_CMD_INIT_TXQ 0x82 8268 #undef MC_CMD_0x82_PRIVILEGE_CTG 8269 8270 #define MC_CMD_0x82_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8271 8272 /* MC_CMD_INIT_TXQ_IN msgrequest: Legacy INIT_TXQ request. Use extended version 8273 * in new code. 8274 */ 8275 #define MC_CMD_INIT_TXQ_IN_LENMIN 36 8276 #define MC_CMD_INIT_TXQ_IN_LENMAX 252 8277 #define MC_CMD_INIT_TXQ_IN_LEN(num) (28+8*(num)) 8278 /* Size, in entries */ 8279 #define MC_CMD_INIT_TXQ_IN_SIZE_OFST 0 8280 /* The EVQ to send events to. This is an index originally specified to 8281 * INIT_EVQ. 8282 */ 8283 #define MC_CMD_INIT_TXQ_IN_TARGET_EVQ_OFST 4 8284 /* The value to put in the event data. Check hardware spec. for valid range. */ 8285 #define MC_CMD_INIT_TXQ_IN_LABEL_OFST 8 8286 /* Desired instance. Must be set to a specific instance, which is a function 8287 * local queue index. 8288 */ 8289 #define MC_CMD_INIT_TXQ_IN_INSTANCE_OFST 12 8290 /* There will be more flags here. */ 8291 #define MC_CMD_INIT_TXQ_IN_FLAGS_OFST 16 8292 #define MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_LBN 0 8293 #define MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_WIDTH 1 8294 #define MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_LBN 1 8295 #define MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_WIDTH 1 8296 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_LBN 2 8297 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_WIDTH 1 8298 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_LBN 3 8299 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_WIDTH 1 8300 #define MC_CMD_INIT_TXQ_IN_CRC_MODE_LBN 4 8301 #define MC_CMD_INIT_TXQ_IN_CRC_MODE_WIDTH 4 8302 #define MC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_LBN 8 8303 #define MC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_WIDTH 1 8304 #define MC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_LBN 9 8305 #define MC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_WIDTH 1 8306 #define MC_CMD_INIT_TXQ_IN_FLAG_INNER_IP_CSUM_EN_LBN 10 8307 #define MC_CMD_INIT_TXQ_IN_FLAG_INNER_IP_CSUM_EN_WIDTH 1 8308 #define MC_CMD_INIT_TXQ_IN_FLAG_INNER_TCP_CSUM_EN_LBN 11 8309 #define MC_CMD_INIT_TXQ_IN_FLAG_INNER_TCP_CSUM_EN_WIDTH 1 8310 /* Owner ID to use if in buffer mode (zero if physical) */ 8311 #define MC_CMD_INIT_TXQ_IN_OWNER_ID_OFST 20 8312 /* The port ID associated with the v-adaptor which should contain this DMAQ. */ 8313 #define MC_CMD_INIT_TXQ_IN_PORT_ID_OFST 24 8314 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 8315 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_OFST 28 8316 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LEN 8 8317 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LO_OFST 28 8318 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_HI_OFST 32 8319 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MINNUM 1 8320 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MAXNUM 28 8321 8322 /* MC_CMD_INIT_TXQ_EXT_IN msgrequest: Extended INIT_TXQ with additional mode 8323 * flags 8324 */ 8325 #define MC_CMD_INIT_TXQ_EXT_IN_LEN 544 8326 /* Size, in entries */ 8327 #define MC_CMD_INIT_TXQ_EXT_IN_SIZE_OFST 0 8328 /* The EVQ to send events to. This is an index originally specified to 8329 * INIT_EVQ. 8330 */ 8331 #define MC_CMD_INIT_TXQ_EXT_IN_TARGET_EVQ_OFST 4 8332 /* The value to put in the event data. Check hardware spec. for valid range. */ 8333 #define MC_CMD_INIT_TXQ_EXT_IN_LABEL_OFST 8 8334 /* Desired instance. Must be set to a specific instance, which is a function 8335 * local queue index. 8336 */ 8337 #define MC_CMD_INIT_TXQ_EXT_IN_INSTANCE_OFST 12 8338 /* There will be more flags here. */ 8339 #define MC_CMD_INIT_TXQ_EXT_IN_FLAGS_OFST 16 8340 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_BUFF_MODE_LBN 0 8341 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_BUFF_MODE_WIDTH 1 8342 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_IP_CSUM_DIS_LBN 1 8343 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_IP_CSUM_DIS_WIDTH 1 8344 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_CSUM_DIS_LBN 2 8345 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_CSUM_DIS_WIDTH 1 8346 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_UDP_ONLY_LBN 3 8347 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_UDP_ONLY_WIDTH 1 8348 #define MC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_LBN 4 8349 #define MC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_WIDTH 4 8350 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TIMESTAMP_LBN 8 8351 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TIMESTAMP_WIDTH 1 8352 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_PACER_BYPASS_LBN 9 8353 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_PACER_BYPASS_WIDTH 1 8354 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN_LBN 10 8355 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN_WIDTH 1 8356 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN_LBN 11 8357 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN_WIDTH 1 8358 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TSOV2_EN_LBN 12 8359 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TSOV2_EN_WIDTH 1 8360 /* Owner ID to use if in buffer mode (zero if physical) */ 8361 #define MC_CMD_INIT_TXQ_EXT_IN_OWNER_ID_OFST 20 8362 /* The port ID associated with the v-adaptor which should contain this DMAQ. */ 8363 #define MC_CMD_INIT_TXQ_EXT_IN_PORT_ID_OFST 24 8364 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 8365 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_OFST 28 8366 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LEN 8 8367 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LO_OFST 28 8368 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_HI_OFST 32 8369 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MINNUM 1 8370 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MAXNUM 64 8371 /* Flags related to Qbb flow control mode. */ 8372 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_FLAGS_OFST 540 8373 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_ENABLE_LBN 0 8374 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_ENABLE_WIDTH 1 8375 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_PRIORITY_LBN 1 8376 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_PRIORITY_WIDTH 3 8377 8378 /* MC_CMD_INIT_TXQ_OUT msgresponse */ 8379 #define MC_CMD_INIT_TXQ_OUT_LEN 0 8380 8381 8382 /***********************************/ 8383 /* MC_CMD_FINI_EVQ 8384 * Teardown an EVQ. 8385 * 8386 * All DMAQs or EVQs that point to the EVQ to tear down must be torn down first 8387 * or the operation will fail with EBUSY 8388 */ 8389 #define MC_CMD_FINI_EVQ 0x83 8390 #undef MC_CMD_0x83_PRIVILEGE_CTG 8391 8392 #define MC_CMD_0x83_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8393 8394 /* MC_CMD_FINI_EVQ_IN msgrequest */ 8395 #define MC_CMD_FINI_EVQ_IN_LEN 4 8396 /* Instance of EVQ to destroy. Should be the same instance as that previously 8397 * passed to INIT_EVQ 8398 */ 8399 #define MC_CMD_FINI_EVQ_IN_INSTANCE_OFST 0 8400 8401 /* MC_CMD_FINI_EVQ_OUT msgresponse */ 8402 #define MC_CMD_FINI_EVQ_OUT_LEN 0 8403 8404 8405 /***********************************/ 8406 /* MC_CMD_FINI_RXQ 8407 * Teardown a RXQ. 8408 */ 8409 #define MC_CMD_FINI_RXQ 0x84 8410 #undef MC_CMD_0x84_PRIVILEGE_CTG 8411 8412 #define MC_CMD_0x84_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8413 8414 /* MC_CMD_FINI_RXQ_IN msgrequest */ 8415 #define MC_CMD_FINI_RXQ_IN_LEN 4 8416 /* Instance of RXQ to destroy */ 8417 #define MC_CMD_FINI_RXQ_IN_INSTANCE_OFST 0 8418 8419 /* MC_CMD_FINI_RXQ_OUT msgresponse */ 8420 #define MC_CMD_FINI_RXQ_OUT_LEN 0 8421 8422 8423 /***********************************/ 8424 /* MC_CMD_FINI_TXQ 8425 * Teardown a TXQ. 8426 */ 8427 #define MC_CMD_FINI_TXQ 0x85 8428 #undef MC_CMD_0x85_PRIVILEGE_CTG 8429 8430 #define MC_CMD_0x85_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8431 8432 /* MC_CMD_FINI_TXQ_IN msgrequest */ 8433 #define MC_CMD_FINI_TXQ_IN_LEN 4 8434 /* Instance of TXQ to destroy */ 8435 #define MC_CMD_FINI_TXQ_IN_INSTANCE_OFST 0 8436 8437 /* MC_CMD_FINI_TXQ_OUT msgresponse */ 8438 #define MC_CMD_FINI_TXQ_OUT_LEN 0 8439 8440 8441 /***********************************/ 8442 /* MC_CMD_DRIVER_EVENT 8443 * Generate an event on an EVQ belonging to the function issuing the command. 8444 */ 8445 #define MC_CMD_DRIVER_EVENT 0x86 8446 #undef MC_CMD_0x86_PRIVILEGE_CTG 8447 8448 #define MC_CMD_0x86_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8449 8450 /* MC_CMD_DRIVER_EVENT_IN msgrequest */ 8451 #define MC_CMD_DRIVER_EVENT_IN_LEN 12 8452 /* Handle of target EVQ */ 8453 #define MC_CMD_DRIVER_EVENT_IN_EVQ_OFST 0 8454 /* Bits 0 - 63 of event */ 8455 #define MC_CMD_DRIVER_EVENT_IN_DATA_OFST 4 8456 #define MC_CMD_DRIVER_EVENT_IN_DATA_LEN 8 8457 #define MC_CMD_DRIVER_EVENT_IN_DATA_LO_OFST 4 8458 #define MC_CMD_DRIVER_EVENT_IN_DATA_HI_OFST 8 8459 8460 /* MC_CMD_DRIVER_EVENT_OUT msgresponse */ 8461 #define MC_CMD_DRIVER_EVENT_OUT_LEN 0 8462 8463 8464 /***********************************/ 8465 /* MC_CMD_PROXY_CMD 8466 * Execute an arbitrary MCDI command on behalf of a different function, subject 8467 * to security restrictions. The command to be proxied follows immediately 8468 * afterward in the host buffer (or on the UART). This command supercedes 8469 * MC_CMD_SET_FUNC, which remains available for Siena but now deprecated. 8470 */ 8471 #define MC_CMD_PROXY_CMD 0x5b 8472 #undef MC_CMD_0x5b_PRIVILEGE_CTG 8473 8474 #define MC_CMD_0x5b_PRIVILEGE_CTG SRIOV_CTG_ADMIN 8475 8476 /* MC_CMD_PROXY_CMD_IN msgrequest */ 8477 #define MC_CMD_PROXY_CMD_IN_LEN 4 8478 /* The handle of the target function. */ 8479 #define MC_CMD_PROXY_CMD_IN_TARGET_OFST 0 8480 #define MC_CMD_PROXY_CMD_IN_TARGET_PF_LBN 0 8481 #define MC_CMD_PROXY_CMD_IN_TARGET_PF_WIDTH 16 8482 #define MC_CMD_PROXY_CMD_IN_TARGET_VF_LBN 16 8483 #define MC_CMD_PROXY_CMD_IN_TARGET_VF_WIDTH 16 8484 #define MC_CMD_PROXY_CMD_IN_VF_NULL 0xffff /* enum */ 8485 8486 /* MC_CMD_PROXY_CMD_OUT msgresponse */ 8487 #define MC_CMD_PROXY_CMD_OUT_LEN 0 8488 8489 /* MC_PROXY_STATUS_BUFFER structuredef: Host memory status buffer used to 8490 * manage proxied requests 8491 */ 8492 #define MC_PROXY_STATUS_BUFFER_LEN 16 8493 /* Handle allocated by the firmware for this proxy transaction */ 8494 #define MC_PROXY_STATUS_BUFFER_HANDLE_OFST 0 8495 /* enum: An invalid handle. */ 8496 #define MC_PROXY_STATUS_BUFFER_HANDLE_INVALID 0x0 8497 #define MC_PROXY_STATUS_BUFFER_HANDLE_LBN 0 8498 #define MC_PROXY_STATUS_BUFFER_HANDLE_WIDTH 32 8499 /* The requesting physical function number */ 8500 #define MC_PROXY_STATUS_BUFFER_PF_OFST 4 8501 #define MC_PROXY_STATUS_BUFFER_PF_LEN 2 8502 #define MC_PROXY_STATUS_BUFFER_PF_LBN 32 8503 #define MC_PROXY_STATUS_BUFFER_PF_WIDTH 16 8504 /* The requesting virtual function number. Set to VF_NULL if the target is a 8505 * PF. 8506 */ 8507 #define MC_PROXY_STATUS_BUFFER_VF_OFST 6 8508 #define MC_PROXY_STATUS_BUFFER_VF_LEN 2 8509 #define MC_PROXY_STATUS_BUFFER_VF_LBN 48 8510 #define MC_PROXY_STATUS_BUFFER_VF_WIDTH 16 8511 /* The target function RID. */ 8512 #define MC_PROXY_STATUS_BUFFER_RID_OFST 8 8513 #define MC_PROXY_STATUS_BUFFER_RID_LEN 2 8514 #define MC_PROXY_STATUS_BUFFER_RID_LBN 64 8515 #define MC_PROXY_STATUS_BUFFER_RID_WIDTH 16 8516 /* The status of the proxy as described in MC_CMD_PROXY_COMPLETE. */ 8517 #define MC_PROXY_STATUS_BUFFER_STATUS_OFST 10 8518 #define MC_PROXY_STATUS_BUFFER_STATUS_LEN 2 8519 #define MC_PROXY_STATUS_BUFFER_STATUS_LBN 80 8520 #define MC_PROXY_STATUS_BUFFER_STATUS_WIDTH 16 8521 /* If a request is authorized rather than carried out by the host, this is the 8522 * elevated privilege mask granted to the requesting function. 8523 */ 8524 #define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_OFST 12 8525 #define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_LBN 96 8526 #define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_WIDTH 32 8527 8528 8529 /***********************************/ 8530 /* MC_CMD_PROXY_CONFIGURE 8531 * Enable/disable authorization of MCDI requests from unprivileged functions by 8532 * a designated admin function 8533 */ 8534 #define MC_CMD_PROXY_CONFIGURE 0x58 8535 #undef MC_CMD_0x58_PRIVILEGE_CTG 8536 8537 #define MC_CMD_0x58_PRIVILEGE_CTG SRIOV_CTG_ADMIN 8538 8539 /* MC_CMD_PROXY_CONFIGURE_IN msgrequest */ 8540 #define MC_CMD_PROXY_CONFIGURE_IN_LEN 108 8541 #define MC_CMD_PROXY_CONFIGURE_IN_FLAGS_OFST 0 8542 #define MC_CMD_PROXY_CONFIGURE_IN_ENABLE_LBN 0 8543 #define MC_CMD_PROXY_CONFIGURE_IN_ENABLE_WIDTH 1 8544 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 8545 * of blocks, each of the size REQUEST_BLOCK_SIZE. 8546 */ 8547 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_OFST 4 8548 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LEN 8 8549 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LO_OFST 4 8550 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_HI_OFST 8 8551 /* Must be a power of 2 */ 8552 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BLOCK_SIZE_OFST 12 8553 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 8554 * of blocks, each of the size REPLY_BLOCK_SIZE. 8555 */ 8556 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_OFST 16 8557 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LEN 8 8558 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LO_OFST 16 8559 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_HI_OFST 20 8560 /* Must be a power of 2 */ 8561 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BLOCK_SIZE_OFST 24 8562 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 8563 * of blocks, each of the size STATUS_BLOCK_SIZE. This buffer is only needed if 8564 * host intends to complete proxied operations by using MC_CMD_PROXY_CMD. 8565 */ 8566 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_OFST 28 8567 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LEN 8 8568 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LO_OFST 28 8569 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_HI_OFST 32 8570 /* Must be a power of 2, or zero if this buffer is not provided */ 8571 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BLOCK_SIZE_OFST 36 8572 /* Applies to all three buffers */ 8573 #define MC_CMD_PROXY_CONFIGURE_IN_NUM_BLOCKS_OFST 40 8574 /* A bit mask defining which MCDI operations may be proxied */ 8575 #define MC_CMD_PROXY_CONFIGURE_IN_ALLOWED_MCDI_MASK_OFST 44 8576 #define MC_CMD_PROXY_CONFIGURE_IN_ALLOWED_MCDI_MASK_LEN 64 8577 8578 /* MC_CMD_PROXY_CONFIGURE_EXT_IN msgrequest */ 8579 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_LEN 112 8580 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_FLAGS_OFST 0 8581 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_ENABLE_LBN 0 8582 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_ENABLE_WIDTH 1 8583 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 8584 * of blocks, each of the size REQUEST_BLOCK_SIZE. 8585 */ 8586 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_OFST 4 8587 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LEN 8 8588 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LO_OFST 4 8589 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_HI_OFST 8 8590 /* Must be a power of 2 */ 8591 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BLOCK_SIZE_OFST 12 8592 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 8593 * of blocks, each of the size REPLY_BLOCK_SIZE. 8594 */ 8595 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_OFST 16 8596 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_LEN 8 8597 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_LO_OFST 16 8598 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_HI_OFST 20 8599 /* Must be a power of 2 */ 8600 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BLOCK_SIZE_OFST 24 8601 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 8602 * of blocks, each of the size STATUS_BLOCK_SIZE. This buffer is only needed if 8603 * host intends to complete proxied operations by using MC_CMD_PROXY_CMD. 8604 */ 8605 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_OFST 28 8606 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_LEN 8 8607 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_LO_OFST 28 8608 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_HI_OFST 32 8609 /* Must be a power of 2, or zero if this buffer is not provided */ 8610 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BLOCK_SIZE_OFST 36 8611 /* Applies to all three buffers */ 8612 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_NUM_BLOCKS_OFST 40 8613 /* A bit mask defining which MCDI operations may be proxied */ 8614 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_ALLOWED_MCDI_MASK_OFST 44 8615 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_ALLOWED_MCDI_MASK_LEN 64 8616 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_RESERVED_OFST 108 8617 8618 /* MC_CMD_PROXY_CONFIGURE_OUT msgresponse */ 8619 #define MC_CMD_PROXY_CONFIGURE_OUT_LEN 0 8620 8621 8622 /***********************************/ 8623 /* MC_CMD_PROXY_COMPLETE 8624 * Tells FW that a requested proxy operation has either been completed (by 8625 * using MC_CMD_PROXY_CMD) or authorized/declined. May only be sent by the 8626 * function that enabled proxying/authorization (by using 8627 * MC_CMD_PROXY_CONFIGURE). 8628 */ 8629 #define MC_CMD_PROXY_COMPLETE 0x5f 8630 #undef MC_CMD_0x5f_PRIVILEGE_CTG 8631 8632 #define MC_CMD_0x5f_PRIVILEGE_CTG SRIOV_CTG_ADMIN 8633 8634 /* MC_CMD_PROXY_COMPLETE_IN msgrequest */ 8635 #define MC_CMD_PROXY_COMPLETE_IN_LEN 12 8636 #define MC_CMD_PROXY_COMPLETE_IN_BLOCK_INDEX_OFST 0 8637 #define MC_CMD_PROXY_COMPLETE_IN_STATUS_OFST 4 8638 /* enum: The operation has been completed by using MC_CMD_PROXY_CMD, the reply 8639 * is stored in the REPLY_BUFF. 8640 */ 8641 #define MC_CMD_PROXY_COMPLETE_IN_COMPLETE 0x0 8642 /* enum: The operation has been authorized. The originating function may now 8643 * try again. 8644 */ 8645 #define MC_CMD_PROXY_COMPLETE_IN_AUTHORIZED 0x1 8646 /* enum: The operation has been declined. */ 8647 #define MC_CMD_PROXY_COMPLETE_IN_DECLINED 0x2 8648 /* enum: The authorization failed because the relevant application did not 8649 * respond in time. 8650 */ 8651 #define MC_CMD_PROXY_COMPLETE_IN_TIMEDOUT 0x3 8652 #define MC_CMD_PROXY_COMPLETE_IN_HANDLE_OFST 8 8653 8654 /* MC_CMD_PROXY_COMPLETE_OUT msgresponse */ 8655 #define MC_CMD_PROXY_COMPLETE_OUT_LEN 0 8656 8657 8658 /***********************************/ 8659 /* MC_CMD_ALLOC_BUFTBL_CHUNK 8660 * Allocate a set of buffer table entries using the specified owner ID. This 8661 * operation allocates the required buffer table entries (and fails if it 8662 * cannot do so). The buffer table entries will initially be zeroed. 8663 */ 8664 #define MC_CMD_ALLOC_BUFTBL_CHUNK 0x87 8665 #undef MC_CMD_0x87_PRIVILEGE_CTG 8666 8667 #define MC_CMD_0x87_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 8668 8669 /* MC_CMD_ALLOC_BUFTBL_CHUNK_IN msgrequest */ 8670 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_LEN 8 8671 /* Owner ID to use */ 8672 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_OWNER_OFST 0 8673 /* Size of buffer table pages to use, in bytes (note that only a few values are 8674 * legal on any specific hardware). 8675 */ 8676 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_PAGE_SIZE_OFST 4 8677 8678 /* MC_CMD_ALLOC_BUFTBL_CHUNK_OUT msgresponse */ 8679 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_LEN 12 8680 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_HANDLE_OFST 0 8681 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_NUMENTRIES_OFST 4 8682 /* Buffer table IDs for use in DMA descriptors. */ 8683 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_ID_OFST 8 8684 8685 8686 /***********************************/ 8687 /* MC_CMD_PROGRAM_BUFTBL_ENTRIES 8688 * Reprogram a set of buffer table entries in the specified chunk. 8689 */ 8690 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES 0x88 8691 #undef MC_CMD_0x88_PRIVILEGE_CTG 8692 8693 #define MC_CMD_0x88_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 8694 8695 /* MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN msgrequest */ 8696 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMIN 20 8697 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMAX 268 8698 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LEN(num) (12+8*(num)) 8699 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_HANDLE_OFST 0 8700 /* ID */ 8701 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_FIRSTID_OFST 4 8702 /* Num entries */ 8703 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_NUMENTRIES_OFST 8 8704 /* Buffer table entry address */ 8705 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_OFST 12 8706 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LEN 8 8707 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LO_OFST 12 8708 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_HI_OFST 16 8709 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MINNUM 1 8710 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MAXNUM 32 8711 8712 /* MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT msgresponse */ 8713 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT_LEN 0 8714 8715 8716 /***********************************/ 8717 /* MC_CMD_FREE_BUFTBL_CHUNK 8718 */ 8719 #define MC_CMD_FREE_BUFTBL_CHUNK 0x89 8720 #undef MC_CMD_0x89_PRIVILEGE_CTG 8721 8722 #define MC_CMD_0x89_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 8723 8724 /* MC_CMD_FREE_BUFTBL_CHUNK_IN msgrequest */ 8725 #define MC_CMD_FREE_BUFTBL_CHUNK_IN_LEN 4 8726 #define MC_CMD_FREE_BUFTBL_CHUNK_IN_HANDLE_OFST 0 8727 8728 /* MC_CMD_FREE_BUFTBL_CHUNK_OUT msgresponse */ 8729 #define MC_CMD_FREE_BUFTBL_CHUNK_OUT_LEN 0 8730 8731 /* PORT_CONFIG_ENTRY structuredef */ 8732 #define PORT_CONFIG_ENTRY_LEN 16 8733 /* External port number (label) */ 8734 #define PORT_CONFIG_ENTRY_EXT_NUMBER_OFST 0 8735 #define PORT_CONFIG_ENTRY_EXT_NUMBER_LEN 1 8736 #define PORT_CONFIG_ENTRY_EXT_NUMBER_LBN 0 8737 #define PORT_CONFIG_ENTRY_EXT_NUMBER_WIDTH 8 8738 /* Port core location */ 8739 #define PORT_CONFIG_ENTRY_CORE_OFST 1 8740 #define PORT_CONFIG_ENTRY_CORE_LEN 1 8741 #define PORT_CONFIG_ENTRY_STANDALONE 0x0 /* enum */ 8742 #define PORT_CONFIG_ENTRY_MASTER 0x1 /* enum */ 8743 #define PORT_CONFIG_ENTRY_SLAVE 0x2 /* enum */ 8744 #define PORT_CONFIG_ENTRY_CORE_LBN 8 8745 #define PORT_CONFIG_ENTRY_CORE_WIDTH 8 8746 /* Internal number (HW resource) relative to the core */ 8747 #define PORT_CONFIG_ENTRY_INT_NUMBER_OFST 2 8748 #define PORT_CONFIG_ENTRY_INT_NUMBER_LEN 1 8749 #define PORT_CONFIG_ENTRY_INT_NUMBER_LBN 16 8750 #define PORT_CONFIG_ENTRY_INT_NUMBER_WIDTH 8 8751 /* Reserved */ 8752 #define PORT_CONFIG_ENTRY_RSVD_OFST 3 8753 #define PORT_CONFIG_ENTRY_RSVD_LEN 1 8754 #define PORT_CONFIG_ENTRY_RSVD_LBN 24 8755 #define PORT_CONFIG_ENTRY_RSVD_WIDTH 8 8756 /* Bitmask of KR lanes used by the port */ 8757 #define PORT_CONFIG_ENTRY_LANES_OFST 4 8758 #define PORT_CONFIG_ENTRY_LANES_LBN 32 8759 #define PORT_CONFIG_ENTRY_LANES_WIDTH 32 8760 /* Port capabilities (MC_CMD_PHY_CAP_*) */ 8761 #define PORT_CONFIG_ENTRY_SUPPORTED_CAPS_OFST 8 8762 #define PORT_CONFIG_ENTRY_SUPPORTED_CAPS_LBN 64 8763 #define PORT_CONFIG_ENTRY_SUPPORTED_CAPS_WIDTH 32 8764 /* Reserved (align to 16 bytes) */ 8765 #define PORT_CONFIG_ENTRY_RSVD2_OFST 12 8766 #define PORT_CONFIG_ENTRY_RSVD2_LBN 96 8767 #define PORT_CONFIG_ENTRY_RSVD2_WIDTH 32 8768 8769 8770 /***********************************/ 8771 /* MC_CMD_FILTER_OP 8772 * Multiplexed MCDI call for filter operations 8773 */ 8774 #define MC_CMD_FILTER_OP 0x8a 8775 #undef MC_CMD_0x8a_PRIVILEGE_CTG 8776 8777 #define MC_CMD_0x8a_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8778 8779 /* MC_CMD_FILTER_OP_IN msgrequest */ 8780 #define MC_CMD_FILTER_OP_IN_LEN 108 8781 /* identifies the type of operation requested */ 8782 #define MC_CMD_FILTER_OP_IN_OP_OFST 0 8783 /* enum: single-recipient filter insert */ 8784 #define MC_CMD_FILTER_OP_IN_OP_INSERT 0x0 8785 /* enum: single-recipient filter remove */ 8786 #define MC_CMD_FILTER_OP_IN_OP_REMOVE 0x1 8787 /* enum: multi-recipient filter subscribe */ 8788 #define MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE 0x2 8789 /* enum: multi-recipient filter unsubscribe */ 8790 #define MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE 0x3 8791 /* enum: replace one recipient with another (warning - the filter handle may 8792 * change) 8793 */ 8794 #define MC_CMD_FILTER_OP_IN_OP_REPLACE 0x4 8795 /* filter handle (for remove / unsubscribe operations) */ 8796 #define MC_CMD_FILTER_OP_IN_HANDLE_OFST 4 8797 #define MC_CMD_FILTER_OP_IN_HANDLE_LEN 8 8798 #define MC_CMD_FILTER_OP_IN_HANDLE_LO_OFST 4 8799 #define MC_CMD_FILTER_OP_IN_HANDLE_HI_OFST 8 8800 /* The port ID associated with the v-adaptor which should contain this filter. 8801 */ 8802 #define MC_CMD_FILTER_OP_IN_PORT_ID_OFST 12 8803 /* fields to include in match criteria */ 8804 #define MC_CMD_FILTER_OP_IN_MATCH_FIELDS_OFST 16 8805 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_LBN 0 8806 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_WIDTH 1 8807 #define MC_CMD_FILTER_OP_IN_MATCH_DST_IP_LBN 1 8808 #define MC_CMD_FILTER_OP_IN_MATCH_DST_IP_WIDTH 1 8809 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_LBN 2 8810 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_WIDTH 1 8811 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_LBN 3 8812 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_WIDTH 1 8813 #define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_LBN 4 8814 #define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_WIDTH 1 8815 #define MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_LBN 5 8816 #define MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_WIDTH 1 8817 #define MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_LBN 6 8818 #define MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_WIDTH 1 8819 #define MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_LBN 7 8820 #define MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_WIDTH 1 8821 #define MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_LBN 8 8822 #define MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_WIDTH 1 8823 #define MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_LBN 9 8824 #define MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_WIDTH 1 8825 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_LBN 10 8826 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_WIDTH 1 8827 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_LBN 11 8828 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_WIDTH 1 8829 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN 30 8830 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1 8831 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN 31 8832 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1 8833 /* receive destination */ 8834 #define MC_CMD_FILTER_OP_IN_RX_DEST_OFST 20 8835 /* enum: drop packets */ 8836 #define MC_CMD_FILTER_OP_IN_RX_DEST_DROP 0x0 8837 /* enum: receive to host */ 8838 #define MC_CMD_FILTER_OP_IN_RX_DEST_HOST 0x1 8839 /* enum: receive to MC */ 8840 #define MC_CMD_FILTER_OP_IN_RX_DEST_MC 0x2 8841 /* enum: loop back to TXDP 0 */ 8842 #define MC_CMD_FILTER_OP_IN_RX_DEST_TX0 0x3 8843 /* enum: loop back to TXDP 1 */ 8844 #define MC_CMD_FILTER_OP_IN_RX_DEST_TX1 0x4 8845 /* receive queue handle (for multiple queue modes, this is the base queue) */ 8846 #define MC_CMD_FILTER_OP_IN_RX_QUEUE_OFST 24 8847 /* receive mode */ 8848 #define MC_CMD_FILTER_OP_IN_RX_MODE_OFST 28 8849 /* enum: receive to just the specified queue */ 8850 #define MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE 0x0 8851 /* enum: receive to multiple queues using RSS context */ 8852 #define MC_CMD_FILTER_OP_IN_RX_MODE_RSS 0x1 8853 /* enum: receive to multiple queues using .1p mapping */ 8854 #define MC_CMD_FILTER_OP_IN_RX_MODE_DOT1P_MAPPING 0x2 8855 /* enum: install a filter entry that will never match; for test purposes only 8856 */ 8857 #define MC_CMD_FILTER_OP_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000 8858 /* RSS context (for RX_MODE_RSS) or .1p mapping handle (for 8859 * RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or 8860 * MC_CMD_DOT1P_MAPPING_ALLOC. 8861 */ 8862 #define MC_CMD_FILTER_OP_IN_RX_CONTEXT_OFST 32 8863 /* transmit domain (reserved; set to 0) */ 8864 #define MC_CMD_FILTER_OP_IN_TX_DOMAIN_OFST 36 8865 /* transmit destination (either set the MAC and/or PM bits for explicit 8866 * control, or set this field to TX_DEST_DEFAULT for sensible default 8867 * behaviour) 8868 */ 8869 #define MC_CMD_FILTER_OP_IN_TX_DEST_OFST 40 8870 /* enum: request default behaviour (based on filter type) */ 8871 #define MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT 0xffffffff 8872 #define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_LBN 0 8873 #define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_WIDTH 1 8874 #define MC_CMD_FILTER_OP_IN_TX_DEST_PM_LBN 1 8875 #define MC_CMD_FILTER_OP_IN_TX_DEST_PM_WIDTH 1 8876 /* source MAC address to match (as bytes in network order) */ 8877 #define MC_CMD_FILTER_OP_IN_SRC_MAC_OFST 44 8878 #define MC_CMD_FILTER_OP_IN_SRC_MAC_LEN 6 8879 /* source port to match (as bytes in network order) */ 8880 #define MC_CMD_FILTER_OP_IN_SRC_PORT_OFST 50 8881 #define MC_CMD_FILTER_OP_IN_SRC_PORT_LEN 2 8882 /* destination MAC address to match (as bytes in network order) */ 8883 #define MC_CMD_FILTER_OP_IN_DST_MAC_OFST 52 8884 #define MC_CMD_FILTER_OP_IN_DST_MAC_LEN 6 8885 /* destination port to match (as bytes in network order) */ 8886 #define MC_CMD_FILTER_OP_IN_DST_PORT_OFST 58 8887 #define MC_CMD_FILTER_OP_IN_DST_PORT_LEN 2 8888 /* Ethernet type to match (as bytes in network order) */ 8889 #define MC_CMD_FILTER_OP_IN_ETHER_TYPE_OFST 60 8890 #define MC_CMD_FILTER_OP_IN_ETHER_TYPE_LEN 2 8891 /* Inner VLAN tag to match (as bytes in network order) */ 8892 #define MC_CMD_FILTER_OP_IN_INNER_VLAN_OFST 62 8893 #define MC_CMD_FILTER_OP_IN_INNER_VLAN_LEN 2 8894 /* Outer VLAN tag to match (as bytes in network order) */ 8895 #define MC_CMD_FILTER_OP_IN_OUTER_VLAN_OFST 64 8896 #define MC_CMD_FILTER_OP_IN_OUTER_VLAN_LEN 2 8897 /* IP protocol to match (in low byte; set high byte to 0) */ 8898 #define MC_CMD_FILTER_OP_IN_IP_PROTO_OFST 66 8899 #define MC_CMD_FILTER_OP_IN_IP_PROTO_LEN 2 8900 /* Firmware defined register 0 to match (reserved; set to 0) */ 8901 #define MC_CMD_FILTER_OP_IN_FWDEF0_OFST 68 8902 /* Firmware defined register 1 to match (reserved; set to 0) */ 8903 #define MC_CMD_FILTER_OP_IN_FWDEF1_OFST 72 8904 /* source IP address to match (as bytes in network order; set last 12 bytes to 8905 * 0 for IPv4 address) 8906 */ 8907 #define MC_CMD_FILTER_OP_IN_SRC_IP_OFST 76 8908 #define MC_CMD_FILTER_OP_IN_SRC_IP_LEN 16 8909 /* destination IP address to match (as bytes in network order; set last 12 8910 * bytes to 0 for IPv4 address) 8911 */ 8912 #define MC_CMD_FILTER_OP_IN_DST_IP_OFST 92 8913 #define MC_CMD_FILTER_OP_IN_DST_IP_LEN 16 8914 8915 /* MC_CMD_FILTER_OP_EXT_IN msgrequest: Extension to MC_CMD_FILTER_OP_IN to 8916 * include handling of VXLAN/NVGRE encapsulated frame filtering (which is 8917 * supported on Medford only). 8918 */ 8919 #define MC_CMD_FILTER_OP_EXT_IN_LEN 172 8920 /* identifies the type of operation requested */ 8921 #define MC_CMD_FILTER_OP_EXT_IN_OP_OFST 0 8922 /* Enum values, see field(s): */ 8923 /* MC_CMD_FILTER_OP_IN/OP */ 8924 /* filter handle (for remove / unsubscribe operations) */ 8925 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_OFST 4 8926 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LEN 8 8927 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LO_OFST 4 8928 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_HI_OFST 8 8929 /* The port ID associated with the v-adaptor which should contain this filter. 8930 */ 8931 #define MC_CMD_FILTER_OP_EXT_IN_PORT_ID_OFST 12 8932 /* fields to include in match criteria */ 8933 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_FIELDS_OFST 16 8934 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_LBN 0 8935 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_WIDTH 1 8936 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_IP_LBN 1 8937 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_IP_WIDTH 1 8938 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_MAC_LBN 2 8939 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_MAC_WIDTH 1 8940 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_PORT_LBN 3 8941 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_PORT_WIDTH 1 8942 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_LBN 4 8943 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_WIDTH 1 8944 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_PORT_LBN 5 8945 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_PORT_WIDTH 1 8946 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_LBN 6 8947 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_WIDTH 1 8948 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_INNER_VLAN_LBN 7 8949 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_INNER_VLAN_WIDTH 1 8950 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_OUTER_VLAN_LBN 8 8951 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_OUTER_VLAN_WIDTH 1 8952 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_LBN 9 8953 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_WIDTH 1 8954 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_FWDEF0_LBN 10 8955 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_FWDEF0_WIDTH 1 8956 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_VNI_OR_VSID_LBN 11 8957 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_VNI_OR_VSID_WIDTH 1 8958 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_IP_LBN 12 8959 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_IP_WIDTH 1 8960 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_IP_LBN 13 8961 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_IP_WIDTH 1 8962 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_MAC_LBN 14 8963 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_MAC_WIDTH 1 8964 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_PORT_LBN 15 8965 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_PORT_WIDTH 1 8966 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_MAC_LBN 16 8967 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_MAC_WIDTH 1 8968 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_PORT_LBN 17 8969 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_PORT_WIDTH 1 8970 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ETHER_TYPE_LBN 18 8971 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ETHER_TYPE_WIDTH 1 8972 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_INNER_VLAN_LBN 19 8973 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_INNER_VLAN_WIDTH 1 8974 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_OUTER_VLAN_LBN 20 8975 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_OUTER_VLAN_WIDTH 1 8976 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_IP_PROTO_LBN 21 8977 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_IP_PROTO_WIDTH 1 8978 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF0_LBN 22 8979 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF0_WIDTH 1 8980 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF1_LBN 23 8981 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF1_WIDTH 1 8982 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_LBN 24 8983 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_WIDTH 1 8984 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_LBN 25 8985 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_WIDTH 1 8986 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_LBN 30 8987 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1 8988 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_LBN 31 8989 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1 8990 /* receive destination */ 8991 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_OFST 20 8992 /* enum: drop packets */ 8993 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_DROP 0x0 8994 /* enum: receive to host */ 8995 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_HOST 0x1 8996 /* enum: receive to MC */ 8997 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_MC 0x2 8998 /* enum: loop back to TXDP 0 */ 8999 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_TX0 0x3 9000 /* enum: loop back to TXDP 1 */ 9001 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_TX1 0x4 9002 /* receive queue handle (for multiple queue modes, this is the base queue) */ 9003 #define MC_CMD_FILTER_OP_EXT_IN_RX_QUEUE_OFST 24 9004 /* receive mode */ 9005 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_OFST 28 9006 /* enum: receive to just the specified queue */ 9007 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_SIMPLE 0x0 9008 /* enum: receive to multiple queues using RSS context */ 9009 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_RSS 0x1 9010 /* enum: receive to multiple queues using .1p mapping */ 9011 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_DOT1P_MAPPING 0x2 9012 /* enum: install a filter entry that will never match; for test purposes only 9013 */ 9014 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000 9015 /* RSS context (for RX_MODE_RSS) or .1p mapping handle (for 9016 * RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or 9017 * MC_CMD_DOT1P_MAPPING_ALLOC. 9018 */ 9019 #define MC_CMD_FILTER_OP_EXT_IN_RX_CONTEXT_OFST 32 9020 /* transmit domain (reserved; set to 0) */ 9021 #define MC_CMD_FILTER_OP_EXT_IN_TX_DOMAIN_OFST 36 9022 /* transmit destination (either set the MAC and/or PM bits for explicit 9023 * control, or set this field to TX_DEST_DEFAULT for sensible default 9024 * behaviour) 9025 */ 9026 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_OFST 40 9027 /* enum: request default behaviour (based on filter type) */ 9028 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_DEFAULT 0xffffffff 9029 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_LBN 0 9030 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_WIDTH 1 9031 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_PM_LBN 1 9032 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_PM_WIDTH 1 9033 /* source MAC address to match (as bytes in network order) */ 9034 #define MC_CMD_FILTER_OP_EXT_IN_SRC_MAC_OFST 44 9035 #define MC_CMD_FILTER_OP_EXT_IN_SRC_MAC_LEN 6 9036 /* source port to match (as bytes in network order) */ 9037 #define MC_CMD_FILTER_OP_EXT_IN_SRC_PORT_OFST 50 9038 #define MC_CMD_FILTER_OP_EXT_IN_SRC_PORT_LEN 2 9039 /* destination MAC address to match (as bytes in network order) */ 9040 #define MC_CMD_FILTER_OP_EXT_IN_DST_MAC_OFST 52 9041 #define MC_CMD_FILTER_OP_EXT_IN_DST_MAC_LEN 6 9042 /* destination port to match (as bytes in network order) */ 9043 #define MC_CMD_FILTER_OP_EXT_IN_DST_PORT_OFST 58 9044 #define MC_CMD_FILTER_OP_EXT_IN_DST_PORT_LEN 2 9045 /* Ethernet type to match (as bytes in network order) */ 9046 #define MC_CMD_FILTER_OP_EXT_IN_ETHER_TYPE_OFST 60 9047 #define MC_CMD_FILTER_OP_EXT_IN_ETHER_TYPE_LEN 2 9048 /* Inner VLAN tag to match (as bytes in network order) */ 9049 #define MC_CMD_FILTER_OP_EXT_IN_INNER_VLAN_OFST 62 9050 #define MC_CMD_FILTER_OP_EXT_IN_INNER_VLAN_LEN 2 9051 /* Outer VLAN tag to match (as bytes in network order) */ 9052 #define MC_CMD_FILTER_OP_EXT_IN_OUTER_VLAN_OFST 64 9053 #define MC_CMD_FILTER_OP_EXT_IN_OUTER_VLAN_LEN 2 9054 /* IP protocol to match (in low byte; set high byte to 0) */ 9055 #define MC_CMD_FILTER_OP_EXT_IN_IP_PROTO_OFST 66 9056 #define MC_CMD_FILTER_OP_EXT_IN_IP_PROTO_LEN 2 9057 /* Firmware defined register 0 to match (reserved; set to 0) */ 9058 #define MC_CMD_FILTER_OP_EXT_IN_FWDEF0_OFST 68 9059 /* VNI (for VXLAN/Geneve, when IP protocol is UDP) or VSID (for NVGRE, when IP 9060 * protocol is GRE) to match (as bytes in network order; set last byte to 0 for 9061 * VXLAN/NVGRE, or 1 for Geneve) 9062 */ 9063 #define MC_CMD_FILTER_OP_EXT_IN_VNI_OR_VSID_OFST 72 9064 #define MC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_LBN 0 9065 #define MC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_WIDTH 24 9066 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_LBN 24 9067 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_WIDTH 8 9068 /* enum: Match VXLAN traffic with this VNI */ 9069 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_VXLAN 0x0 9070 /* enum: Match Geneve traffic with this VNI */ 9071 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_GENEVE 0x1 9072 /* enum: Reserved for experimental development use */ 9073 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_EXPERIMENTAL 0xfe 9074 #define MC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_LBN 0 9075 #define MC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_WIDTH 24 9076 #define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_LBN 24 9077 #define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_WIDTH 8 9078 /* enum: Match NVGRE traffic with this VSID */ 9079 #define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_NVGRE 0x0 9080 /* source IP address to match (as bytes in network order; set last 12 bytes to 9081 * 0 for IPv4 address) 9082 */ 9083 #define MC_CMD_FILTER_OP_EXT_IN_SRC_IP_OFST 76 9084 #define MC_CMD_FILTER_OP_EXT_IN_SRC_IP_LEN 16 9085 /* destination IP address to match (as bytes in network order; set last 12 9086 * bytes to 0 for IPv4 address) 9087 */ 9088 #define MC_CMD_FILTER_OP_EXT_IN_DST_IP_OFST 92 9089 #define MC_CMD_FILTER_OP_EXT_IN_DST_IP_LEN 16 9090 /* VXLAN/NVGRE inner frame source MAC address to match (as bytes in network 9091 * order) 9092 */ 9093 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_MAC_OFST 108 9094 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_MAC_LEN 6 9095 /* VXLAN/NVGRE inner frame source port to match (as bytes in network order) */ 9096 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_PORT_OFST 114 9097 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_PORT_LEN 2 9098 /* VXLAN/NVGRE inner frame destination MAC address to match (as bytes in 9099 * network order) 9100 */ 9101 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_MAC_OFST 116 9102 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_MAC_LEN 6 9103 /* VXLAN/NVGRE inner frame destination port to match (as bytes in network 9104 * order) 9105 */ 9106 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_PORT_OFST 122 9107 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_PORT_LEN 2 9108 /* VXLAN/NVGRE inner frame Ethernet type to match (as bytes in network order) 9109 */ 9110 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_ETHER_TYPE_OFST 124 9111 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_ETHER_TYPE_LEN 2 9112 /* VXLAN/NVGRE inner frame Inner VLAN tag to match (as bytes in network order) 9113 */ 9114 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_INNER_VLAN_OFST 126 9115 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_INNER_VLAN_LEN 2 9116 /* VXLAN/NVGRE inner frame Outer VLAN tag to match (as bytes in network order) 9117 */ 9118 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_OUTER_VLAN_OFST 128 9119 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_OUTER_VLAN_LEN 2 9120 /* VXLAN/NVGRE inner frame IP protocol to match (in low byte; set high byte to 9121 * 0) 9122 */ 9123 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_IP_PROTO_OFST 130 9124 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_IP_PROTO_LEN 2 9125 /* VXLAN/NVGRE inner frame Firmware defined register 0 to match (reserved; set 9126 * to 0) 9127 */ 9128 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF0_OFST 132 9129 /* VXLAN/NVGRE inner frame Firmware defined register 1 to match (reserved; set 9130 * to 0) 9131 */ 9132 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF1_OFST 136 9133 /* VXLAN/NVGRE inner frame source IP address to match (as bytes in network 9134 * order; set last 12 bytes to 0 for IPv4 address) 9135 */ 9136 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_IP_OFST 140 9137 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_IP_LEN 16 9138 /* VXLAN/NVGRE inner frame destination IP address to match (as bytes in network 9139 * order; set last 12 bytes to 0 for IPv4 address) 9140 */ 9141 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_IP_OFST 156 9142 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_IP_LEN 16 9143 9144 /* MC_CMD_FILTER_OP_OUT msgresponse */ 9145 #define MC_CMD_FILTER_OP_OUT_LEN 12 9146 /* identifies the type of operation requested */ 9147 #define MC_CMD_FILTER_OP_OUT_OP_OFST 0 9148 /* Enum values, see field(s): */ 9149 /* MC_CMD_FILTER_OP_IN/OP */ 9150 /* Returned filter handle (for insert / subscribe operations). Note that these 9151 * handles should be considered opaque to the host, although a value of 9152 * 0xFFFFFFFF_FFFFFFFF is guaranteed never to be a valid handle. 9153 */ 9154 #define MC_CMD_FILTER_OP_OUT_HANDLE_OFST 4 9155 #define MC_CMD_FILTER_OP_OUT_HANDLE_LEN 8 9156 #define MC_CMD_FILTER_OP_OUT_HANDLE_LO_OFST 4 9157 #define MC_CMD_FILTER_OP_OUT_HANDLE_HI_OFST 8 9158 /* enum: guaranteed invalid filter handle (low 32 bits) */ 9159 #define MC_CMD_FILTER_OP_OUT_HANDLE_LO_INVALID 0xffffffff 9160 /* enum: guaranteed invalid filter handle (high 32 bits) */ 9161 #define MC_CMD_FILTER_OP_OUT_HANDLE_HI_INVALID 0xffffffff 9162 9163 /* MC_CMD_FILTER_OP_EXT_OUT msgresponse */ 9164 #define MC_CMD_FILTER_OP_EXT_OUT_LEN 12 9165 /* identifies the type of operation requested */ 9166 #define MC_CMD_FILTER_OP_EXT_OUT_OP_OFST 0 9167 /* Enum values, see field(s): */ 9168 /* MC_CMD_FILTER_OP_EXT_IN/OP */ 9169 /* Returned filter handle (for insert / subscribe operations). Note that these 9170 * handles should be considered opaque to the host, although a value of 9171 * 0xFFFFFFFF_FFFFFFFF is guaranteed never to be a valid handle. 9172 */ 9173 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_OFST 4 9174 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LEN 8 9175 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LO_OFST 4 9176 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_HI_OFST 8 9177 /* Enum values, see field(s): */ 9178 /* MC_CMD_FILTER_OP_OUT/HANDLE */ 9179 9180 9181 /***********************************/ 9182 /* MC_CMD_GET_PARSER_DISP_INFO 9183 * Get information related to the parser-dispatcher subsystem 9184 */ 9185 #define MC_CMD_GET_PARSER_DISP_INFO 0xe4 9186 #undef MC_CMD_0xe4_PRIVILEGE_CTG 9187 9188 #define MC_CMD_0xe4_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9189 9190 /* MC_CMD_GET_PARSER_DISP_INFO_IN msgrequest */ 9191 #define MC_CMD_GET_PARSER_DISP_INFO_IN_LEN 4 9192 /* identifies the type of operation requested */ 9193 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_OFST 0 9194 /* enum: read the list of supported RX filter matches */ 9195 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES 0x1 9196 /* enum: read flags indicating restrictions on filter insertion for the calling 9197 * client 9198 */ 9199 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_RESTRICTIONS 0x2 9200 9201 /* MC_CMD_GET_PARSER_DISP_INFO_OUT msgresponse */ 9202 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMIN 8 9203 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX 252 9204 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_LEN(num) (8+4*(num)) 9205 /* identifies the type of operation requested */ 9206 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_OP_OFST 0 9207 /* Enum values, see field(s): */ 9208 /* MC_CMD_GET_PARSER_DISP_INFO_IN/OP */ 9209 /* number of supported match types */ 9210 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_NUM_SUPPORTED_MATCHES_OFST 4 9211 /* array of supported match types (valid MATCH_FIELDS values for 9212 * MC_CMD_FILTER_OP) sorted in decreasing priority order 9213 */ 9214 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_OFST 8 9215 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_LEN 4 9216 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MINNUM 0 9217 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM 61 9218 9219 /* MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT msgresponse */ 9220 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_LEN 8 9221 /* identifies the type of operation requested */ 9222 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_OP_OFST 0 9223 /* Enum values, see field(s): */ 9224 /* MC_CMD_GET_PARSER_DISP_INFO_IN/OP */ 9225 /* bitfield of filter insertion restrictions */ 9226 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_RESTRICTION_FLAGS_OFST 4 9227 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_LBN 0 9228 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_WIDTH 1 9229 9230 9231 /***********************************/ 9232 /* MC_CMD_PARSER_DISP_RW 9233 * Direct read/write of parser-dispatcher state (DICPUs and LUE) for debugging. 9234 * Please note that this interface is only of use to debug tools which have 9235 * knowledge of firmware and hardware data structures; nothing here is intended 9236 * for use by normal driver code. 9237 */ 9238 #define MC_CMD_PARSER_DISP_RW 0xe5 9239 #undef MC_CMD_0xe5_PRIVILEGE_CTG 9240 9241 #define MC_CMD_0xe5_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9242 9243 /* MC_CMD_PARSER_DISP_RW_IN msgrequest */ 9244 #define MC_CMD_PARSER_DISP_RW_IN_LEN 32 9245 /* identifies the target of the operation */ 9246 #define MC_CMD_PARSER_DISP_RW_IN_TARGET_OFST 0 9247 /* enum: RX dispatcher CPU */ 9248 #define MC_CMD_PARSER_DISP_RW_IN_RX_DICPU 0x0 9249 /* enum: TX dispatcher CPU */ 9250 #define MC_CMD_PARSER_DISP_RW_IN_TX_DICPU 0x1 9251 /* enum: Lookup engine (with original metadata format) */ 9252 #define MC_CMD_PARSER_DISP_RW_IN_LUE 0x2 9253 /* enum: Lookup engine (with requested metadata format) */ 9254 #define MC_CMD_PARSER_DISP_RW_IN_LUE_VERSIONED_METADATA 0x3 9255 /* enum: RX0 dispatcher CPU (alias for RX_DICPU; Medford has 2 RX DICPUs) */ 9256 #define MC_CMD_PARSER_DISP_RW_IN_RX0_DICPU 0x0 9257 /* enum: RX1 dispatcher CPU (only valid for Medford) */ 9258 #define MC_CMD_PARSER_DISP_RW_IN_RX1_DICPU 0x4 9259 /* enum: Miscellaneous other state (only valid for Medford) */ 9260 #define MC_CMD_PARSER_DISP_RW_IN_MISC_STATE 0x5 9261 /* identifies the type of operation requested */ 9262 #define MC_CMD_PARSER_DISP_RW_IN_OP_OFST 4 9263 /* enum: read a word of DICPU DMEM or a LUE entry */ 9264 #define MC_CMD_PARSER_DISP_RW_IN_READ 0x0 9265 /* enum: write a word of DICPU DMEM or a LUE entry */ 9266 #define MC_CMD_PARSER_DISP_RW_IN_WRITE 0x1 9267 /* enum: read-modify-write a word of DICPU DMEM (not valid for LUE) */ 9268 #define MC_CMD_PARSER_DISP_RW_IN_RMW 0x2 9269 /* data memory address (DICPU targets) or LUE index (LUE targets) */ 9270 #define MC_CMD_PARSER_DISP_RW_IN_ADDRESS_OFST 8 9271 /* selector (for MISC_STATE target) */ 9272 #define MC_CMD_PARSER_DISP_RW_IN_SELECTOR_OFST 8 9273 /* enum: Port to datapath mapping */ 9274 #define MC_CMD_PARSER_DISP_RW_IN_PORT_DP_MAPPING 0x1 9275 /* value to write (for DMEM writes) */ 9276 #define MC_CMD_PARSER_DISP_RW_IN_DMEM_WRITE_VALUE_OFST 12 9277 /* XOR value (for DMEM read-modify-writes: new = (old & mask) ^ value) */ 9278 #define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_XOR_VALUE_OFST 12 9279 /* AND mask (for DMEM read-modify-writes: new = (old & mask) ^ value) */ 9280 #define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_AND_MASK_OFST 16 9281 /* metadata format (for LUE reads using LUE_VERSIONED_METADATA) */ 9282 #define MC_CMD_PARSER_DISP_RW_IN_LUE_READ_METADATA_VERSION_OFST 12 9283 /* value to write (for LUE writes) */ 9284 #define MC_CMD_PARSER_DISP_RW_IN_LUE_WRITE_VALUE_OFST 12 9285 #define MC_CMD_PARSER_DISP_RW_IN_LUE_WRITE_VALUE_LEN 20 9286 9287 /* MC_CMD_PARSER_DISP_RW_OUT msgresponse */ 9288 #define MC_CMD_PARSER_DISP_RW_OUT_LEN 52 9289 /* value read (for DMEM reads) */ 9290 #define MC_CMD_PARSER_DISP_RW_OUT_DMEM_READ_VALUE_OFST 0 9291 /* value read (for LUE reads) */ 9292 #define MC_CMD_PARSER_DISP_RW_OUT_LUE_READ_VALUE_OFST 0 9293 #define MC_CMD_PARSER_DISP_RW_OUT_LUE_READ_VALUE_LEN 20 9294 /* up to 8 32-bit words of additional soft state from the LUE manager (the 9295 * exact content is firmware-dependent and intended only for debug use) 9296 */ 9297 #define MC_CMD_PARSER_DISP_RW_OUT_LUE_MGR_STATE_OFST 20 9298 #define MC_CMD_PARSER_DISP_RW_OUT_LUE_MGR_STATE_LEN 32 9299 /* datapath(s) used for each port (for MISC_STATE PORT_DP_MAPPING selector) */ 9300 #define MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_OFST 0 9301 #define MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_LEN 4 9302 #define MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_NUM 4 9303 #define MC_CMD_PARSER_DISP_RW_OUT_DP0 0x1 /* enum */ 9304 #define MC_CMD_PARSER_DISP_RW_OUT_DP1 0x2 /* enum */ 9305 9306 9307 /***********************************/ 9308 /* MC_CMD_GET_PF_COUNT 9309 * Get number of PFs on the device. 9310 */ 9311 #define MC_CMD_GET_PF_COUNT 0xb6 9312 #undef MC_CMD_0xb6_PRIVILEGE_CTG 9313 9314 #define MC_CMD_0xb6_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9315 9316 /* MC_CMD_GET_PF_COUNT_IN msgrequest */ 9317 #define MC_CMD_GET_PF_COUNT_IN_LEN 0 9318 9319 /* MC_CMD_GET_PF_COUNT_OUT msgresponse */ 9320 #define MC_CMD_GET_PF_COUNT_OUT_LEN 1 9321 /* Identifies the number of PFs on the device. */ 9322 #define MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_OFST 0 9323 #define MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_LEN 1 9324 9325 9326 /***********************************/ 9327 /* MC_CMD_SET_PF_COUNT 9328 * Set number of PFs on the device. 9329 */ 9330 #define MC_CMD_SET_PF_COUNT 0xb7 9331 9332 /* MC_CMD_SET_PF_COUNT_IN msgrequest */ 9333 #define MC_CMD_SET_PF_COUNT_IN_LEN 4 9334 /* New number of PFs on the device. */ 9335 #define MC_CMD_SET_PF_COUNT_IN_PF_COUNT_OFST 0 9336 9337 /* MC_CMD_SET_PF_COUNT_OUT msgresponse */ 9338 #define MC_CMD_SET_PF_COUNT_OUT_LEN 0 9339 9340 9341 /***********************************/ 9342 /* MC_CMD_GET_PORT_ASSIGNMENT 9343 * Get port assignment for current PCI function. 9344 */ 9345 #define MC_CMD_GET_PORT_ASSIGNMENT 0xb8 9346 #undef MC_CMD_0xb8_PRIVILEGE_CTG 9347 9348 #define MC_CMD_0xb8_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9349 9350 /* MC_CMD_GET_PORT_ASSIGNMENT_IN msgrequest */ 9351 #define MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN 0 9352 9353 /* MC_CMD_GET_PORT_ASSIGNMENT_OUT msgresponse */ 9354 #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN 4 9355 /* Identifies the port assignment for this function. */ 9356 #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_PORT_OFST 0 9357 9358 9359 /***********************************/ 9360 /* MC_CMD_SET_PORT_ASSIGNMENT 9361 * Set port assignment for current PCI function. 9362 */ 9363 #define MC_CMD_SET_PORT_ASSIGNMENT 0xb9 9364 #undef MC_CMD_0xb9_PRIVILEGE_CTG 9365 9366 #define MC_CMD_0xb9_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9367 9368 /* MC_CMD_SET_PORT_ASSIGNMENT_IN msgrequest */ 9369 #define MC_CMD_SET_PORT_ASSIGNMENT_IN_LEN 4 9370 /* Identifies the port assignment for this function. */ 9371 #define MC_CMD_SET_PORT_ASSIGNMENT_IN_PORT_OFST 0 9372 9373 /* MC_CMD_SET_PORT_ASSIGNMENT_OUT msgresponse */ 9374 #define MC_CMD_SET_PORT_ASSIGNMENT_OUT_LEN 0 9375 9376 9377 /***********************************/ 9378 /* MC_CMD_ALLOC_VIS 9379 * Allocate VIs for current PCI function. 9380 */ 9381 #define MC_CMD_ALLOC_VIS 0x8b 9382 #undef MC_CMD_0x8b_PRIVILEGE_CTG 9383 9384 #define MC_CMD_0x8b_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9385 9386 /* MC_CMD_ALLOC_VIS_IN msgrequest */ 9387 #define MC_CMD_ALLOC_VIS_IN_LEN 8 9388 /* The minimum number of VIs that is acceptable */ 9389 #define MC_CMD_ALLOC_VIS_IN_MIN_VI_COUNT_OFST 0 9390 /* The maximum number of VIs that would be useful */ 9391 #define MC_CMD_ALLOC_VIS_IN_MAX_VI_COUNT_OFST 4 9392 9393 /* MC_CMD_ALLOC_VIS_OUT msgresponse: Huntington-compatible VI_ALLOC request. 9394 * Use extended version in new code. 9395 */ 9396 #define MC_CMD_ALLOC_VIS_OUT_LEN 8 9397 /* The number of VIs allocated on this function */ 9398 #define MC_CMD_ALLOC_VIS_OUT_VI_COUNT_OFST 0 9399 /* The base absolute VI number allocated to this function. Required to 9400 * correctly interpret wakeup events. 9401 */ 9402 #define MC_CMD_ALLOC_VIS_OUT_VI_BASE_OFST 4 9403 9404 /* MC_CMD_ALLOC_VIS_EXT_OUT msgresponse */ 9405 #define MC_CMD_ALLOC_VIS_EXT_OUT_LEN 12 9406 /* The number of VIs allocated on this function */ 9407 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_COUNT_OFST 0 9408 /* The base absolute VI number allocated to this function. Required to 9409 * correctly interpret wakeup events. 9410 */ 9411 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_BASE_OFST 4 9412 /* Function's port vi_shift value (always 0 on Huntington) */ 9413 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_SHIFT_OFST 8 9414 9415 9416 /***********************************/ 9417 /* MC_CMD_FREE_VIS 9418 * Free VIs for current PCI function. Any linked PIO buffers will be unlinked, 9419 * but not freed. 9420 */ 9421 #define MC_CMD_FREE_VIS 0x8c 9422 #undef MC_CMD_0x8c_PRIVILEGE_CTG 9423 9424 #define MC_CMD_0x8c_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9425 9426 /* MC_CMD_FREE_VIS_IN msgrequest */ 9427 #define MC_CMD_FREE_VIS_IN_LEN 0 9428 9429 /* MC_CMD_FREE_VIS_OUT msgresponse */ 9430 #define MC_CMD_FREE_VIS_OUT_LEN 0 9431 9432 9433 /***********************************/ 9434 /* MC_CMD_GET_SRIOV_CFG 9435 * Get SRIOV config for this PF. 9436 */ 9437 #define MC_CMD_GET_SRIOV_CFG 0xba 9438 #undef MC_CMD_0xba_PRIVILEGE_CTG 9439 9440 #define MC_CMD_0xba_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9441 9442 /* MC_CMD_GET_SRIOV_CFG_IN msgrequest */ 9443 #define MC_CMD_GET_SRIOV_CFG_IN_LEN 0 9444 9445 /* MC_CMD_GET_SRIOV_CFG_OUT msgresponse */ 9446 #define MC_CMD_GET_SRIOV_CFG_OUT_LEN 20 9447 /* Number of VFs currently enabled. */ 9448 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_CURRENT_OFST 0 9449 /* Max number of VFs before sriov stride and offset may need to be changed. */ 9450 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_MAX_OFST 4 9451 #define MC_CMD_GET_SRIOV_CFG_OUT_FLAGS_OFST 8 9452 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_LBN 0 9453 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_WIDTH 1 9454 /* RID offset of first VF from PF. */ 9455 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_OFFSET_OFST 12 9456 /* RID offset of each subsequent VF from the previous. */ 9457 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_STRIDE_OFST 16 9458 9459 9460 /***********************************/ 9461 /* MC_CMD_SET_SRIOV_CFG 9462 * Set SRIOV config for this PF. 9463 */ 9464 #define MC_CMD_SET_SRIOV_CFG 0xbb 9465 #undef MC_CMD_0xbb_PRIVILEGE_CTG 9466 9467 #define MC_CMD_0xbb_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9468 9469 /* MC_CMD_SET_SRIOV_CFG_IN msgrequest */ 9470 #define MC_CMD_SET_SRIOV_CFG_IN_LEN 20 9471 /* Number of VFs currently enabled. */ 9472 #define MC_CMD_SET_SRIOV_CFG_IN_VF_CURRENT_OFST 0 9473 /* Max number of VFs before sriov stride and offset may need to be changed. */ 9474 #define MC_CMD_SET_SRIOV_CFG_IN_VF_MAX_OFST 4 9475 #define MC_CMD_SET_SRIOV_CFG_IN_FLAGS_OFST 8 9476 #define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_LBN 0 9477 #define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_WIDTH 1 9478 /* RID offset of first VF from PF, or 0 for no change, or 9479 * MC_CMD_RESOURCE_INSTANCE_ANY to allow the system to allocate an offset. 9480 */ 9481 #define MC_CMD_SET_SRIOV_CFG_IN_VF_OFFSET_OFST 12 9482 /* RID offset of each subsequent VF from the previous, 0 for no change, or 9483 * MC_CMD_RESOURCE_INSTANCE_ANY to allow the system to allocate a stride. 9484 */ 9485 #define MC_CMD_SET_SRIOV_CFG_IN_VF_STRIDE_OFST 16 9486 9487 /* MC_CMD_SET_SRIOV_CFG_OUT msgresponse */ 9488 #define MC_CMD_SET_SRIOV_CFG_OUT_LEN 0 9489 9490 9491 /***********************************/ 9492 /* MC_CMD_GET_VI_ALLOC_INFO 9493 * Get information about number of VI's and base VI number allocated to this 9494 * function. 9495 */ 9496 #define MC_CMD_GET_VI_ALLOC_INFO 0x8d 9497 #undef MC_CMD_0x8d_PRIVILEGE_CTG 9498 9499 #define MC_CMD_0x8d_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9500 9501 /* MC_CMD_GET_VI_ALLOC_INFO_IN msgrequest */ 9502 #define MC_CMD_GET_VI_ALLOC_INFO_IN_LEN 0 9503 9504 /* MC_CMD_GET_VI_ALLOC_INFO_OUT msgresponse */ 9505 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_LEN 12 9506 /* The number of VIs allocated on this function */ 9507 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_COUNT_OFST 0 9508 /* The base absolute VI number allocated to this function. Required to 9509 * correctly interpret wakeup events. 9510 */ 9511 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_BASE_OFST 4 9512 /* Function's port vi_shift value (always 0 on Huntington) */ 9513 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_SHIFT_OFST 8 9514 9515 9516 /***********************************/ 9517 /* MC_CMD_DUMP_VI_STATE 9518 * For CmdClient use. Dump pertinent information on a specific absolute VI. 9519 */ 9520 #define MC_CMD_DUMP_VI_STATE 0x8e 9521 #undef MC_CMD_0x8e_PRIVILEGE_CTG 9522 9523 #define MC_CMD_0x8e_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9524 9525 /* MC_CMD_DUMP_VI_STATE_IN msgrequest */ 9526 #define MC_CMD_DUMP_VI_STATE_IN_LEN 4 9527 /* The VI number to query. */ 9528 #define MC_CMD_DUMP_VI_STATE_IN_VI_NUMBER_OFST 0 9529 9530 /* MC_CMD_DUMP_VI_STATE_OUT msgresponse */ 9531 #define MC_CMD_DUMP_VI_STATE_OUT_LEN 96 9532 /* The PF part of the function owning this VI. */ 9533 #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_OFST 0 9534 #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_LEN 2 9535 /* The VF part of the function owning this VI. */ 9536 #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_VF_OFST 2 9537 #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_VF_LEN 2 9538 /* Base of VIs allocated to this function. */ 9539 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_BASE_OFST 4 9540 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_BASE_LEN 2 9541 /* Count of VIs allocated to the owner function. */ 9542 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_COUNT_OFST 6 9543 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_COUNT_LEN 2 9544 /* Base interrupt vector allocated to this function. */ 9545 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_BASE_OFST 8 9546 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_BASE_LEN 2 9547 /* Number of interrupt vectors allocated to this function. */ 9548 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_COUNT_OFST 10 9549 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_COUNT_LEN 2 9550 /* Raw evq ptr table data. */ 9551 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_OFST 12 9552 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LEN 8 9553 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LO_OFST 12 9554 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_HI_OFST 16 9555 /* Raw evq timer table data. */ 9556 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_OFST 20 9557 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LEN 8 9558 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LO_OFST 20 9559 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_HI_OFST 24 9560 /* Combined metadata field. */ 9561 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_OFST 28 9562 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_LBN 0 9563 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_WIDTH 16 9564 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_LBN 16 9565 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_WIDTH 8 9566 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_LBN 24 9567 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_WIDTH 8 9568 /* TXDPCPU raw table data for queue. */ 9569 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_OFST 32 9570 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LEN 8 9571 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LO_OFST 32 9572 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_HI_OFST 36 9573 /* TXDPCPU raw table data for queue. */ 9574 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_OFST 40 9575 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LEN 8 9576 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LO_OFST 40 9577 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_HI_OFST 44 9578 /* TXDPCPU raw table data for queue. */ 9579 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_OFST 48 9580 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LEN 8 9581 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LO_OFST 48 9582 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_HI_OFST 52 9583 /* Combined metadata field. */ 9584 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_OFST 56 9585 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LEN 8 9586 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LO_OFST 56 9587 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_HI_OFST 60 9588 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_LBN 0 9589 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_WIDTH 16 9590 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_LBN 16 9591 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_WIDTH 8 9592 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_LBN 24 9593 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_WIDTH 8 9594 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_LBN 32 9595 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_WIDTH 8 9596 #define MC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_LBN 40 9597 #define MC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_WIDTH 24 9598 /* RXDPCPU raw table data for queue. */ 9599 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_OFST 64 9600 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LEN 8 9601 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LO_OFST 64 9602 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_HI_OFST 68 9603 /* RXDPCPU raw table data for queue. */ 9604 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_OFST 72 9605 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LEN 8 9606 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LO_OFST 72 9607 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_HI_OFST 76 9608 /* Reserved, currently 0. */ 9609 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_OFST 80 9610 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LEN 8 9611 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LO_OFST 80 9612 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_HI_OFST 84 9613 /* Combined metadata field. */ 9614 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_OFST 88 9615 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LEN 8 9616 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LO_OFST 88 9617 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_HI_OFST 92 9618 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_LBN 0 9619 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_WIDTH 16 9620 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_LBN 16 9621 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_WIDTH 8 9622 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_LBN 24 9623 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_WIDTH 8 9624 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_LBN 32 9625 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_WIDTH 8 9626 9627 9628 /***********************************/ 9629 /* MC_CMD_ALLOC_PIOBUF 9630 * Allocate a push I/O buffer for later use with a tx queue. 9631 */ 9632 #define MC_CMD_ALLOC_PIOBUF 0x8f 9633 #undef MC_CMD_0x8f_PRIVILEGE_CTG 9634 9635 #define MC_CMD_0x8f_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 9636 9637 /* MC_CMD_ALLOC_PIOBUF_IN msgrequest */ 9638 #define MC_CMD_ALLOC_PIOBUF_IN_LEN 0 9639 9640 /* MC_CMD_ALLOC_PIOBUF_OUT msgresponse */ 9641 #define MC_CMD_ALLOC_PIOBUF_OUT_LEN 4 9642 /* Handle for allocated push I/O buffer. */ 9643 #define MC_CMD_ALLOC_PIOBUF_OUT_PIOBUF_HANDLE_OFST 0 9644 9645 9646 /***********************************/ 9647 /* MC_CMD_FREE_PIOBUF 9648 * Free a push I/O buffer. 9649 */ 9650 #define MC_CMD_FREE_PIOBUF 0x90 9651 #undef MC_CMD_0x90_PRIVILEGE_CTG 9652 9653 #define MC_CMD_0x90_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 9654 9655 /* MC_CMD_FREE_PIOBUF_IN msgrequest */ 9656 #define MC_CMD_FREE_PIOBUF_IN_LEN 4 9657 /* Handle for allocated push I/O buffer. */ 9658 #define MC_CMD_FREE_PIOBUF_IN_PIOBUF_HANDLE_OFST 0 9659 9660 /* MC_CMD_FREE_PIOBUF_OUT msgresponse */ 9661 #define MC_CMD_FREE_PIOBUF_OUT_LEN 0 9662 9663 9664 /***********************************/ 9665 /* MC_CMD_GET_VI_TLP_PROCESSING 9666 * Get TLP steering and ordering information for a VI. 9667 */ 9668 #define MC_CMD_GET_VI_TLP_PROCESSING 0xb0 9669 #undef MC_CMD_0xb0_PRIVILEGE_CTG 9670 9671 #define MC_CMD_0xb0_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9672 9673 /* MC_CMD_GET_VI_TLP_PROCESSING_IN msgrequest */ 9674 #define MC_CMD_GET_VI_TLP_PROCESSING_IN_LEN 4 9675 /* VI number to get information for. */ 9676 #define MC_CMD_GET_VI_TLP_PROCESSING_IN_INSTANCE_OFST 0 9677 9678 /* MC_CMD_GET_VI_TLP_PROCESSING_OUT msgresponse */ 9679 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_LEN 4 9680 /* Transaction processing steering hint 1 for use with the Rx Queue. */ 9681 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG1_RX_OFST 0 9682 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG1_RX_LEN 1 9683 /* Transaction processing steering hint 2 for use with the Ev Queue. */ 9684 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG2_EV_OFST 1 9685 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG2_EV_LEN 1 9686 /* Use Relaxed ordering model for TLPs on this VI. */ 9687 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_RELAXED_ORDERING_LBN 16 9688 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_RELAXED_ORDERING_WIDTH 1 9689 /* Use ID based ordering for TLPs on this VI. */ 9690 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_ID_BASED_ORDERING_LBN 17 9691 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_ID_BASED_ORDERING_WIDTH 1 9692 /* Set no snoop bit for TLPs on this VI. */ 9693 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_NO_SNOOP_LBN 18 9694 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_NO_SNOOP_WIDTH 1 9695 /* Enable TPH for TLPs on this VI. */ 9696 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_ON_LBN 19 9697 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_ON_WIDTH 1 9698 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_DATA_OFST 0 9699 9700 9701 /***********************************/ 9702 /* MC_CMD_SET_VI_TLP_PROCESSING 9703 * Set TLP steering and ordering information for a VI. 9704 */ 9705 #define MC_CMD_SET_VI_TLP_PROCESSING 0xb1 9706 #undef MC_CMD_0xb1_PRIVILEGE_CTG 9707 9708 #define MC_CMD_0xb1_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9709 9710 /* MC_CMD_SET_VI_TLP_PROCESSING_IN msgrequest */ 9711 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_LEN 8 9712 /* VI number to set information for. */ 9713 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_INSTANCE_OFST 0 9714 /* Transaction processing steering hint 1 for use with the Rx Queue. */ 9715 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG1_RX_OFST 4 9716 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG1_RX_LEN 1 9717 /* Transaction processing steering hint 2 for use with the Ev Queue. */ 9718 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG2_EV_OFST 5 9719 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG2_EV_LEN 1 9720 /* Use Relaxed ordering model for TLPs on this VI. */ 9721 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_RELAXED_ORDERING_LBN 48 9722 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_RELAXED_ORDERING_WIDTH 1 9723 /* Use ID based ordering for TLPs on this VI. */ 9724 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_ID_BASED_ORDERING_LBN 49 9725 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_ID_BASED_ORDERING_WIDTH 1 9726 /* Set the no snoop bit for TLPs on this VI. */ 9727 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_NO_SNOOP_LBN 50 9728 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_NO_SNOOP_WIDTH 1 9729 /* Enable TPH for TLPs on this VI. */ 9730 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_ON_LBN 51 9731 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_ON_WIDTH 1 9732 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_DATA_OFST 4 9733 9734 /* MC_CMD_SET_VI_TLP_PROCESSING_OUT msgresponse */ 9735 #define MC_CMD_SET_VI_TLP_PROCESSING_OUT_LEN 0 9736 9737 9738 /***********************************/ 9739 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS 9740 * Get global PCIe steering and transaction processing configuration. 9741 */ 9742 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS 0xbc 9743 #undef MC_CMD_0xbc_PRIVILEGE_CTG 9744 9745 #define MC_CMD_0xbc_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9746 9747 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN msgrequest */ 9748 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_LEN 4 9749 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_OFST 0 9750 /* enum: MISC. */ 9751 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_MISC 0x0 9752 /* enum: IDO. */ 9753 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_IDO 0x1 9754 /* enum: RO. */ 9755 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_RO 0x2 9756 /* enum: TPH Type. */ 9757 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_TPH_TYPE 0x3 9758 9759 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT msgresponse */ 9760 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_LEN 8 9761 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_GLOBAL_CATEGORY_OFST 0 9762 /* Enum values, see field(s): */ 9763 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN/TLP_GLOBAL_CATEGORY */ 9764 /* Amalgamated TLP info word. */ 9765 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_WORD_OFST 4 9766 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_LBN 0 9767 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_WIDTH 1 9768 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_LBN 1 9769 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_WIDTH 31 9770 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_LBN 0 9771 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_WIDTH 1 9772 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_LBN 1 9773 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_WIDTH 1 9774 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_EV_EN_LBN 2 9775 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_EV_EN_WIDTH 1 9776 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_LBN 3 9777 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_WIDTH 1 9778 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_LBN 4 9779 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_WIDTH 28 9780 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_LBN 0 9781 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_WIDTH 1 9782 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_LBN 1 9783 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_WIDTH 1 9784 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_LBN 2 9785 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_WIDTH 1 9786 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_LBN 3 9787 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_WIDTH 29 9788 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_LBN 0 9789 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_WIDTH 2 9790 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_DL_LBN 2 9791 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_DL_WIDTH 2 9792 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_LBN 4 9793 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_WIDTH 2 9794 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_EV_LBN 6 9795 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_EV_WIDTH 2 9796 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_LBN 8 9797 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_WIDTH 2 9798 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_LBN 9 9799 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_WIDTH 23 9800 9801 9802 /***********************************/ 9803 /* MC_CMD_SET_TLP_PROCESSING_GLOBALS 9804 * Set global PCIe steering and transaction processing configuration. 9805 */ 9806 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS 0xbd 9807 #undef MC_CMD_0xbd_PRIVILEGE_CTG 9808 9809 #define MC_CMD_0xbd_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9810 9811 /* MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN msgrequest */ 9812 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_LEN 8 9813 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_OFST 0 9814 /* Enum values, see field(s): */ 9815 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS/MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN/TLP_GLOBAL_CATEGORY */ 9816 /* Amalgamated TLP info word. */ 9817 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_WORD_OFST 4 9818 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_LBN 0 9819 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_WIDTH 1 9820 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_LBN 0 9821 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_WIDTH 1 9822 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_LBN 1 9823 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_WIDTH 1 9824 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_EV_EN_LBN 2 9825 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_EV_EN_WIDTH 1 9826 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_RX_EN_LBN 3 9827 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_RX_EN_WIDTH 1 9828 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_LBN 0 9829 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_WIDTH 1 9830 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_LBN 1 9831 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_WIDTH 1 9832 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_DL_EN_LBN 2 9833 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_DL_EN_WIDTH 1 9834 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_LBN 0 9835 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_WIDTH 2 9836 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_DL_LBN 2 9837 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_DL_WIDTH 2 9838 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_LBN 4 9839 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_WIDTH 2 9840 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_EV_LBN 6 9841 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_EV_WIDTH 2 9842 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_LBN 8 9843 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_WIDTH 2 9844 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_LBN 10 9845 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_WIDTH 22 9846 9847 /* MC_CMD_SET_TLP_PROCESSING_GLOBALS_OUT msgresponse */ 9848 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_OUT_LEN 0 9849 9850 9851 /***********************************/ 9852 /* MC_CMD_SATELLITE_DOWNLOAD 9853 * Download a new set of images to the satellite CPUs from the host. 9854 */ 9855 #define MC_CMD_SATELLITE_DOWNLOAD 0x91 9856 #undef MC_CMD_0x91_PRIVILEGE_CTG 9857 9858 #define MC_CMD_0x91_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9859 9860 /* MC_CMD_SATELLITE_DOWNLOAD_IN msgrequest: The reset requirements for the CPUs 9861 * are subtle, and so downloads must proceed in a number of phases. 9862 * 9863 * 1) PHASE_RESET with a target of TARGET_ALL and chunk ID/length of 0. 9864 * 9865 * 2) PHASE_IMEMS for each of the IMEM targets (target IDs 0-11). Each download 9866 * may consist of multiple chunks. The final chunk (with CHUNK_ID_LAST) should 9867 * be a checksum (a simple 32-bit sum) of the transferred data. An individual 9868 * download may be aborted using CHUNK_ID_ABORT. 9869 * 9870 * 3) PHASE_VECTORS for each of the vector table targets (target IDs 12-15), 9871 * similar to PHASE_IMEMS. 9872 * 9873 * 4) PHASE_READY with a target of TARGET_ALL and chunk ID/length of 0. 9874 * 9875 * After any error (a requested abort is not considered to be an error) the 9876 * sequence must be restarted from PHASE_RESET. 9877 */ 9878 #define MC_CMD_SATELLITE_DOWNLOAD_IN_LENMIN 20 9879 #define MC_CMD_SATELLITE_DOWNLOAD_IN_LENMAX 252 9880 #define MC_CMD_SATELLITE_DOWNLOAD_IN_LEN(num) (16+4*(num)) 9881 /* Download phase. (Note: the IDLE phase is used internally and is never valid 9882 * in a command from the host.) 9883 */ 9884 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_OFST 0 9885 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_IDLE 0x0 /* enum */ 9886 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_RESET 0x1 /* enum */ 9887 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_IMEMS 0x2 /* enum */ 9888 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_VECTORS 0x3 /* enum */ 9889 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_READY 0x4 /* enum */ 9890 /* Target for download. (These match the blob numbers defined in 9891 * mc_flash_layout.h.) 9892 */ 9893 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_OFST 4 9894 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 9895 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_TEXT 0x0 9896 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 9897 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_TEXT 0x1 9898 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 9899 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDP_TEXT 0x2 9900 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 9901 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDP_TEXT 0x3 9902 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 9903 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_LUT 0x4 9904 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 9905 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_LUT_CFG 0x5 9906 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 9907 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_LUT 0x6 9908 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 9909 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_LUT_CFG 0x7 9910 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 9911 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_PGM 0x8 9912 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 9913 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_SL_PGM 0x9 9914 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 9915 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_PGM 0xa 9916 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 9917 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_SL_PGM 0xb 9918 /* enum: Valid in phase 3 (PHASE_VECTORS) only */ 9919 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_VTBL0 0xc 9920 /* enum: Valid in phase 3 (PHASE_VECTORS) only */ 9921 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_VTBL0 0xd 9922 /* enum: Valid in phase 3 (PHASE_VECTORS) only */ 9923 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_VTBL1 0xe 9924 /* enum: Valid in phase 3 (PHASE_VECTORS) only */ 9925 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_VTBL1 0xf 9926 /* enum: Valid in phases 1 (PHASE_RESET) and 4 (PHASE_READY) only */ 9927 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_ALL 0xffffffff 9928 /* Chunk ID, or CHUNK_ID_LAST or CHUNK_ID_ABORT */ 9929 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_OFST 8 9930 /* enum: Last chunk, containing checksum rather than data */ 9931 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_LAST 0xffffffff 9932 /* enum: Abort download of this item */ 9933 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_ABORT 0xfffffffe 9934 /* Length of this chunk in bytes */ 9935 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_LEN_OFST 12 9936 /* Data for this chunk */ 9937 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_OFST 16 9938 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_LEN 4 9939 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_MINNUM 1 9940 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_MAXNUM 59 9941 9942 /* MC_CMD_SATELLITE_DOWNLOAD_OUT msgresponse */ 9943 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_LEN 8 9944 /* Same as MC_CMD_ERR field, but included as 0 in success cases */ 9945 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_RESULT_OFST 0 9946 /* Extra status information */ 9947 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_INFO_OFST 4 9948 /* enum: Code download OK, completed. */ 9949 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_COMPLETE 0x0 9950 /* enum: Code download aborted as requested. */ 9951 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_ABORTED 0x1 9952 /* enum: Code download OK so far, send next chunk. */ 9953 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_NEXT_CHUNK 0x2 9954 /* enum: Download phases out of sequence */ 9955 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_PHASE 0x100 9956 /* enum: Bad target for this phase */ 9957 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_TARGET 0x101 9958 /* enum: Chunk ID out of sequence */ 9959 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHUNK_ID 0x200 9960 /* enum: Chunk length zero or too large */ 9961 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHUNK_LEN 0x201 9962 /* enum: Checksum was incorrect */ 9963 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHECKSUM 0x300 9964 9965 9966 /***********************************/ 9967 /* MC_CMD_GET_CAPABILITIES 9968 * Get device capabilities. 9969 * 9970 * This is supplementary to the MC_CMD_GET_BOARD_CFG command, and intended to 9971 * reference inherent device capabilities as opposed to current NVRAM config. 9972 */ 9973 #define MC_CMD_GET_CAPABILITIES 0xbe 9974 #undef MC_CMD_0xbe_PRIVILEGE_CTG 9975 9976 #define MC_CMD_0xbe_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9977 9978 /* MC_CMD_GET_CAPABILITIES_IN msgrequest */ 9979 #define MC_CMD_GET_CAPABILITIES_IN_LEN 0 9980 9981 /* MC_CMD_GET_CAPABILITIES_OUT msgresponse */ 9982 #define MC_CMD_GET_CAPABILITIES_OUT_LEN 20 9983 /* First word of flags. */ 9984 #define MC_CMD_GET_CAPABILITIES_OUT_FLAGS1_OFST 0 9985 #define MC_CMD_GET_CAPABILITIES_OUT_VPORT_RECONFIGURE_LBN 3 9986 #define MC_CMD_GET_CAPABILITIES_OUT_VPORT_RECONFIGURE_WIDTH 1 9987 #define MC_CMD_GET_CAPABILITIES_OUT_TX_STRIPING_LBN 4 9988 #define MC_CMD_GET_CAPABILITIES_OUT_TX_STRIPING_WIDTH 1 9989 #define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_LBN 5 9990 #define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_WIDTH 1 9991 #define MC_CMD_GET_CAPABILITIES_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6 9992 #define MC_CMD_GET_CAPABILITIES_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1 9993 #define MC_CMD_GET_CAPABILITIES_OUT_DRV_ATTACH_PREBOOT_LBN 7 9994 #define MC_CMD_GET_CAPABILITIES_OUT_DRV_ATTACH_PREBOOT_WIDTH 1 9995 #define MC_CMD_GET_CAPABILITIES_OUT_RX_FORCE_EVENT_MERGING_LBN 8 9996 #define MC_CMD_GET_CAPABILITIES_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1 9997 #define MC_CMD_GET_CAPABILITIES_OUT_SET_MAC_ENHANCED_LBN 9 9998 #define MC_CMD_GET_CAPABILITIES_OUT_SET_MAC_ENHANCED_WIDTH 1 9999 #define MC_CMD_GET_CAPABILITIES_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10 10000 #define MC_CMD_GET_CAPABILITIES_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1 10001 #define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11 10002 #define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1 10003 #define MC_CMD_GET_CAPABILITIES_OUT_TX_MAC_SECURITY_FILTERING_LBN 12 10004 #define MC_CMD_GET_CAPABILITIES_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1 10005 #define MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_LBN 13 10006 #define MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_WIDTH 1 10007 #define MC_CMD_GET_CAPABILITIES_OUT_QBB_LBN 14 10008 #define MC_CMD_GET_CAPABILITIES_OUT_QBB_WIDTH 1 10009 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15 10010 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1 10011 #define MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_LBN 16 10012 #define MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_WIDTH 1 10013 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_LBN 17 10014 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_WIDTH 1 10015 #define MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_LBN 18 10016 #define MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_WIDTH 1 10017 #define MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_LBN 19 10018 #define MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_WIDTH 1 10019 #define MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_LBN 20 10020 #define MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_WIDTH 1 10021 #define MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN 21 10022 #define MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_WIDTH 1 10023 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_LBN 22 10024 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_WIDTH 1 10025 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN 23 10026 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_WIDTH 1 10027 #define MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_LBN 24 10028 #define MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_WIDTH 1 10029 #define MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN 25 10030 #define MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_WIDTH 1 10031 #define MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_LBN 26 10032 #define MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_WIDTH 1 10033 #define MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN 27 10034 #define MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1 10035 #define MC_CMD_GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER_LBN 28 10036 #define MC_CMD_GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER_WIDTH 1 10037 #define MC_CMD_GET_CAPABILITIES_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29 10038 #define MC_CMD_GET_CAPABILITIES_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1 10039 #define MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN 30 10040 #define MC_CMD_GET_CAPABILITIES_OUT_EVB_WIDTH 1 10041 #define MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN 31 10042 #define MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_WIDTH 1 10043 /* RxDPCPU firmware id. */ 10044 #define MC_CMD_GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID_OFST 4 10045 #define MC_CMD_GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID_LEN 2 10046 /* enum: Standard RXDP firmware */ 10047 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP 0x0 10048 /* enum: Low latency RXDP firmware */ 10049 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_LOW_LATENCY 0x1 10050 /* enum: Packed stream RXDP firmware */ 10051 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_PACKED_STREAM 0x2 10052 /* enum: BIST RXDP firmware */ 10053 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_BIST 0x10a 10054 /* enum: RXDP Test firmware image 1 */ 10055 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101 10056 /* enum: RXDP Test firmware image 2 */ 10057 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102 10058 /* enum: RXDP Test firmware image 3 */ 10059 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103 10060 /* enum: RXDP Test firmware image 4 */ 10061 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104 10062 /* enum: RXDP Test firmware image 5 */ 10063 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_BACKPRESSURE 0x105 10064 /* enum: RXDP Test firmware image 6 */ 10065 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106 10066 /* enum: RXDP Test firmware image 7 */ 10067 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107 10068 /* enum: RXDP Test firmware image 8 */ 10069 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_DISABLE_DL 0x108 10070 /* enum: RXDP Test firmware image 9 */ 10071 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b 10072 /* TxDPCPU firmware id. */ 10073 #define MC_CMD_GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID_OFST 6 10074 #define MC_CMD_GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID_LEN 2 10075 /* enum: Standard TXDP firmware */ 10076 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP 0x0 10077 /* enum: Low latency TXDP firmware */ 10078 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_LOW_LATENCY 0x1 10079 /* enum: High packet rate TXDP firmware */ 10080 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_HIGH_PACKET_RATE 0x3 10081 /* enum: BIST TXDP firmware */ 10082 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_BIST 0x12d 10083 /* enum: TXDP Test firmware image 1 */ 10084 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_TSO_EDIT 0x101 10085 /* enum: TXDP Test firmware image 2 */ 10086 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102 10087 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_OFST 8 10088 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_LEN 2 10089 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_LBN 0 10090 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_WIDTH 12 10091 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_LBN 12 10092 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4 10093 /* enum: reserved value - do not use (may indicate alternative interpretation 10094 * of REV field in future) 10095 */ 10096 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_RESERVED 0x0 10097 /* enum: Trivial RX PD firmware for early Huntington development (Huntington 10098 * development only) 10099 */ 10100 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1 10101 /* enum: RX PD firmware with approximately Siena-compatible behaviour 10102 * (Huntington development only) 10103 */ 10104 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2 10105 /* enum: Virtual switching (full feature) RX PD production firmware */ 10106 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_VSWITCH 0x3 10107 /* enum: siena_compat variant RX PD firmware using PM rather than MAC 10108 * (Huntington development only) 10109 */ 10110 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 10111 /* enum: Low latency RX PD production firmware */ 10112 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5 10113 /* enum: Packed stream RX PD production firmware */ 10114 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6 10115 /* enum: RX PD firmware handling layer 2 only for high packet rate performance 10116 * tests (Medford development only) 10117 */ 10118 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7 10119 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 10120 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 10121 /* enum: RX PD firmware parsing but not filtering network overlay tunnel 10122 * encapsulations (Medford development only) 10123 */ 10124 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf 10125 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_OFST 10 10126 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_LEN 2 10127 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_LBN 0 10128 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_WIDTH 12 10129 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_LBN 12 10130 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4 10131 /* enum: reserved value - do not use (may indicate alternative interpretation 10132 * of REV field in future) 10133 */ 10134 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_RESERVED 0x0 10135 /* enum: Trivial TX PD firmware for early Huntington development (Huntington 10136 * development only) 10137 */ 10138 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1 10139 /* enum: TX PD firmware with approximately Siena-compatible behaviour 10140 * (Huntington development only) 10141 */ 10142 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2 10143 /* enum: Virtual switching (full feature) TX PD production firmware */ 10144 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_VSWITCH 0x3 10145 /* enum: siena_compat variant TX PD firmware using PM rather than MAC 10146 * (Huntington development only) 10147 */ 10148 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 10149 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */ 10150 /* enum: TX PD firmware handling layer 2 only for high packet rate performance 10151 * tests (Medford development only) 10152 */ 10153 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7 10154 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 10155 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 10156 /* Hardware capabilities of NIC */ 10157 #define MC_CMD_GET_CAPABILITIES_OUT_HW_CAPABILITIES_OFST 12 10158 /* Licensed capabilities */ 10159 #define MC_CMD_GET_CAPABILITIES_OUT_LICENSE_CAPABILITIES_OFST 16 10160 10161 /* MC_CMD_GET_CAPABILITIES_V2_IN msgrequest */ 10162 #define MC_CMD_GET_CAPABILITIES_V2_IN_LEN 0 10163 10164 /* MC_CMD_GET_CAPABILITIES_V2_OUT msgresponse */ 10165 #define MC_CMD_GET_CAPABILITIES_V2_OUT_LEN 26 10166 /* First word of flags. */ 10167 #define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS1_OFST 0 10168 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VPORT_RECONFIGURE_LBN 3 10169 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VPORT_RECONFIGURE_WIDTH 1 10170 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_STRIPING_LBN 4 10171 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_STRIPING_WIDTH 1 10172 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_QUERY_LBN 5 10173 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_QUERY_WIDTH 1 10174 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6 10175 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1 10176 #define MC_CMD_GET_CAPABILITIES_V2_OUT_DRV_ATTACH_PREBOOT_LBN 7 10177 #define MC_CMD_GET_CAPABILITIES_V2_OUT_DRV_ATTACH_PREBOOT_WIDTH 1 10178 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_FORCE_EVENT_MERGING_LBN 8 10179 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1 10180 #define MC_CMD_GET_CAPABILITIES_V2_OUT_SET_MAC_ENHANCED_LBN 9 10181 #define MC_CMD_GET_CAPABILITIES_V2_OUT_SET_MAC_ENHANCED_WIDTH 1 10182 #define MC_CMD_GET_CAPABILITIES_V2_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10 10183 #define MC_CMD_GET_CAPABILITIES_V2_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1 10184 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11 10185 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1 10186 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_SECURITY_FILTERING_LBN 12 10187 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1 10188 #define MC_CMD_GET_CAPABILITIES_V2_OUT_ADDITIONAL_RSS_MODES_LBN 13 10189 #define MC_CMD_GET_CAPABILITIES_V2_OUT_ADDITIONAL_RSS_MODES_WIDTH 1 10190 #define MC_CMD_GET_CAPABILITIES_V2_OUT_QBB_LBN 14 10191 #define MC_CMD_GET_CAPABILITIES_V2_OUT_QBB_WIDTH 1 10192 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15 10193 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1 10194 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_RSS_LIMITED_LBN 16 10195 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_RSS_LIMITED_WIDTH 1 10196 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_LBN 17 10197 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_WIDTH 1 10198 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_INCLUDE_FCS_LBN 18 10199 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_INCLUDE_FCS_WIDTH 1 10200 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VLAN_INSERTION_LBN 19 10201 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VLAN_INSERTION_WIDTH 1 10202 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_VLAN_STRIPPING_LBN 20 10203 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_VLAN_STRIPPING_WIDTH 1 10204 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_LBN 21 10205 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_WIDTH 1 10206 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_0_LBN 22 10207 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_0_WIDTH 1 10208 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_14_LBN 23 10209 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_14_WIDTH 1 10210 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_TIMESTAMP_LBN 24 10211 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_TIMESTAMP_WIDTH 1 10212 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_BATCHING_LBN 25 10213 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_BATCHING_WIDTH 1 10214 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MCAST_FILTER_CHAINING_LBN 26 10215 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MCAST_FILTER_CHAINING_WIDTH 1 10216 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PM_AND_RXDP_COUNTERS_LBN 27 10217 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1 10218 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DISABLE_SCATTER_LBN 28 10219 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DISABLE_SCATTER_WIDTH 1 10220 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29 10221 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1 10222 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_LBN 30 10223 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_WIDTH 1 10224 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VXLAN_NVGRE_LBN 31 10225 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VXLAN_NVGRE_WIDTH 1 10226 /* RxDPCPU firmware id. */ 10227 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DPCPU_FW_ID_OFST 4 10228 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DPCPU_FW_ID_LEN 2 10229 /* enum: Standard RXDP firmware */ 10230 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP 0x0 10231 /* enum: Low latency RXDP firmware */ 10232 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_LOW_LATENCY 0x1 10233 /* enum: Packed stream RXDP firmware */ 10234 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_PACKED_STREAM 0x2 10235 /* enum: BIST RXDP firmware */ 10236 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_BIST 0x10a 10237 /* enum: RXDP Test firmware image 1 */ 10238 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101 10239 /* enum: RXDP Test firmware image 2 */ 10240 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102 10241 /* enum: RXDP Test firmware image 3 */ 10242 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103 10243 /* enum: RXDP Test firmware image 4 */ 10244 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104 10245 /* enum: RXDP Test firmware image 5 */ 10246 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_BACKPRESSURE 0x105 10247 /* enum: RXDP Test firmware image 6 */ 10248 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106 10249 /* enum: RXDP Test firmware image 7 */ 10250 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107 10251 /* enum: RXDP Test firmware image 8 */ 10252 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_DISABLE_DL 0x108 10253 /* enum: RXDP Test firmware image 9 */ 10254 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b 10255 /* TxDPCPU firmware id. */ 10256 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DPCPU_FW_ID_OFST 6 10257 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DPCPU_FW_ID_LEN 2 10258 /* enum: Standard TXDP firmware */ 10259 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP 0x0 10260 /* enum: Low latency TXDP firmware */ 10261 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_LOW_LATENCY 0x1 10262 /* enum: High packet rate TXDP firmware */ 10263 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_HIGH_PACKET_RATE 0x3 10264 /* enum: BIST TXDP firmware */ 10265 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_BIST 0x12d 10266 /* enum: TXDP Test firmware image 1 */ 10267 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_TSO_EDIT 0x101 10268 /* enum: TXDP Test firmware image 2 */ 10269 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102 10270 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_OFST 8 10271 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_LEN 2 10272 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_REV_LBN 0 10273 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_REV_WIDTH 12 10274 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_TYPE_LBN 12 10275 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4 10276 /* enum: reserved value - do not use (may indicate alternative interpretation 10277 * of REV field in future) 10278 */ 10279 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_RESERVED 0x0 10280 /* enum: Trivial RX PD firmware for early Huntington development (Huntington 10281 * development only) 10282 */ 10283 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1 10284 /* enum: RX PD firmware with approximately Siena-compatible behaviour 10285 * (Huntington development only) 10286 */ 10287 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2 10288 /* enum: Virtual switching (full feature) RX PD production firmware */ 10289 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_VSWITCH 0x3 10290 /* enum: siena_compat variant RX PD firmware using PM rather than MAC 10291 * (Huntington development only) 10292 */ 10293 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 10294 /* enum: Low latency RX PD production firmware */ 10295 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5 10296 /* enum: Packed stream RX PD production firmware */ 10297 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6 10298 /* enum: RX PD firmware handling layer 2 only for high packet rate performance 10299 * tests (Medford development only) 10300 */ 10301 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7 10302 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 10303 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 10304 /* enum: RX PD firmware parsing but not filtering network overlay tunnel 10305 * encapsulations (Medford development only) 10306 */ 10307 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf 10308 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_OFST 10 10309 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_LEN 2 10310 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_REV_LBN 0 10311 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_REV_WIDTH 12 10312 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_TYPE_LBN 12 10313 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4 10314 /* enum: reserved value - do not use (may indicate alternative interpretation 10315 * of REV field in future) 10316 */ 10317 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_RESERVED 0x0 10318 /* enum: Trivial TX PD firmware for early Huntington development (Huntington 10319 * development only) 10320 */ 10321 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1 10322 /* enum: TX PD firmware with approximately Siena-compatible behaviour 10323 * (Huntington development only) 10324 */ 10325 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2 10326 /* enum: Virtual switching (full feature) TX PD production firmware */ 10327 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_VSWITCH 0x3 10328 /* enum: siena_compat variant TX PD firmware using PM rather than MAC 10329 * (Huntington development only) 10330 */ 10331 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 10332 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */ 10333 /* enum: TX PD firmware handling layer 2 only for high packet rate performance 10334 * tests (Medford development only) 10335 */ 10336 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7 10337 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 10338 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 10339 /* Hardware capabilities of NIC */ 10340 #define MC_CMD_GET_CAPABILITIES_V2_OUT_HW_CAPABILITIES_OFST 12 10341 /* Licensed capabilities */ 10342 #define MC_CMD_GET_CAPABILITIES_V2_OUT_LICENSE_CAPABILITIES_OFST 16 10343 /* Second word of flags. Not present on older firmware (check the length). */ 10344 #define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS2_OFST 20 10345 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN 0 10346 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_WIDTH 1 10347 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_ENCAP_LBN 1 10348 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_ENCAP_WIDTH 1 10349 /* Number of FATSOv2 contexts per datapath supported by this NIC. Not present 10350 * on older firmware (check the length). 10351 */ 10352 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24 10353 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2 10354 10355 10356 /***********************************/ 10357 /* MC_CMD_V2_EXTN 10358 * Encapsulation for a v2 extended command 10359 */ 10360 #define MC_CMD_V2_EXTN 0x7f 10361 10362 /* MC_CMD_V2_EXTN_IN msgrequest */ 10363 #define MC_CMD_V2_EXTN_IN_LEN 4 10364 /* the extended command number */ 10365 #define MC_CMD_V2_EXTN_IN_EXTENDED_CMD_LBN 0 10366 #define MC_CMD_V2_EXTN_IN_EXTENDED_CMD_WIDTH 15 10367 #define MC_CMD_V2_EXTN_IN_UNUSED_LBN 15 10368 #define MC_CMD_V2_EXTN_IN_UNUSED_WIDTH 1 10369 /* the actual length of the encapsulated command (which is not in the v1 10370 * header) 10371 */ 10372 #define MC_CMD_V2_EXTN_IN_ACTUAL_LEN_LBN 16 10373 #define MC_CMD_V2_EXTN_IN_ACTUAL_LEN_WIDTH 10 10374 #define MC_CMD_V2_EXTN_IN_UNUSED2_LBN 26 10375 #define MC_CMD_V2_EXTN_IN_UNUSED2_WIDTH 6 10376 10377 10378 /***********************************/ 10379 /* MC_CMD_TCM_BUCKET_ALLOC 10380 * Allocate a pacer bucket (for qau rp or a snapper test) 10381 */ 10382 #define MC_CMD_TCM_BUCKET_ALLOC 0xb2 10383 #undef MC_CMD_0xb2_PRIVILEGE_CTG 10384 10385 #define MC_CMD_0xb2_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10386 10387 /* MC_CMD_TCM_BUCKET_ALLOC_IN msgrequest */ 10388 #define MC_CMD_TCM_BUCKET_ALLOC_IN_LEN 0 10389 10390 /* MC_CMD_TCM_BUCKET_ALLOC_OUT msgresponse */ 10391 #define MC_CMD_TCM_BUCKET_ALLOC_OUT_LEN 4 10392 /* the bucket id */ 10393 #define MC_CMD_TCM_BUCKET_ALLOC_OUT_BUCKET_OFST 0 10394 10395 10396 /***********************************/ 10397 /* MC_CMD_TCM_BUCKET_FREE 10398 * Free a pacer bucket 10399 */ 10400 #define MC_CMD_TCM_BUCKET_FREE 0xb3 10401 #undef MC_CMD_0xb3_PRIVILEGE_CTG 10402 10403 #define MC_CMD_0xb3_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10404 10405 /* MC_CMD_TCM_BUCKET_FREE_IN msgrequest */ 10406 #define MC_CMD_TCM_BUCKET_FREE_IN_LEN 4 10407 /* the bucket id */ 10408 #define MC_CMD_TCM_BUCKET_FREE_IN_BUCKET_OFST 0 10409 10410 /* MC_CMD_TCM_BUCKET_FREE_OUT msgresponse */ 10411 #define MC_CMD_TCM_BUCKET_FREE_OUT_LEN 0 10412 10413 10414 /***********************************/ 10415 /* MC_CMD_TCM_BUCKET_INIT 10416 * Initialise pacer bucket with a given rate 10417 */ 10418 #define MC_CMD_TCM_BUCKET_INIT 0xb4 10419 #undef MC_CMD_0xb4_PRIVILEGE_CTG 10420 10421 #define MC_CMD_0xb4_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10422 10423 /* MC_CMD_TCM_BUCKET_INIT_IN msgrequest */ 10424 #define MC_CMD_TCM_BUCKET_INIT_IN_LEN 8 10425 /* the bucket id */ 10426 #define MC_CMD_TCM_BUCKET_INIT_IN_BUCKET_OFST 0 10427 /* the rate in mbps */ 10428 #define MC_CMD_TCM_BUCKET_INIT_IN_RATE_OFST 4 10429 10430 /* MC_CMD_TCM_BUCKET_INIT_EXT_IN msgrequest */ 10431 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_LEN 12 10432 /* the bucket id */ 10433 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_BUCKET_OFST 0 10434 /* the rate in mbps */ 10435 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_RATE_OFST 4 10436 /* the desired maximum fill level */ 10437 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_MAX_FILL_OFST 8 10438 10439 /* MC_CMD_TCM_BUCKET_INIT_OUT msgresponse */ 10440 #define MC_CMD_TCM_BUCKET_INIT_OUT_LEN 0 10441 10442 10443 /***********************************/ 10444 /* MC_CMD_TCM_TXQ_INIT 10445 * Initialise txq in pacer with given options or set options 10446 */ 10447 #define MC_CMD_TCM_TXQ_INIT 0xb5 10448 #undef MC_CMD_0xb5_PRIVILEGE_CTG 10449 10450 #define MC_CMD_0xb5_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10451 10452 /* MC_CMD_TCM_TXQ_INIT_IN msgrequest */ 10453 #define MC_CMD_TCM_TXQ_INIT_IN_LEN 28 10454 /* the txq id */ 10455 #define MC_CMD_TCM_TXQ_INIT_IN_QID_OFST 0 10456 /* the static priority associated with the txq */ 10457 #define MC_CMD_TCM_TXQ_INIT_IN_LABEL_OFST 4 10458 /* bitmask of the priority queues this txq is inserted into when inserted. */ 10459 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAGS_OFST 8 10460 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_GUARANTEED_LBN 0 10461 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_GUARANTEED_WIDTH 1 10462 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_NORMAL_LBN 1 10463 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_NORMAL_WIDTH 1 10464 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_LOW_LBN 2 10465 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_LOW_WIDTH 1 10466 /* the reaction point (RP) bucket */ 10467 #define MC_CMD_TCM_TXQ_INIT_IN_RP_BKT_OFST 12 10468 /* an already reserved bucket (typically set to bucket associated with outer 10469 * vswitch) 10470 */ 10471 #define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT1_OFST 16 10472 /* an already reserved bucket (typically set to bucket associated with inner 10473 * vswitch) 10474 */ 10475 #define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT2_OFST 20 10476 /* the min bucket (typically for ETS/minimum bandwidth) */ 10477 #define MC_CMD_TCM_TXQ_INIT_IN_MIN_BKT_OFST 24 10478 10479 /* MC_CMD_TCM_TXQ_INIT_EXT_IN msgrequest */ 10480 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_LEN 32 10481 /* the txq id */ 10482 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_QID_OFST 0 10483 /* the static priority associated with the txq */ 10484 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_NORMAL_OFST 4 10485 /* bitmask of the priority queues this txq is inserted into when inserted. */ 10486 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAGS_OFST 8 10487 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_GUARANTEED_LBN 0 10488 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_GUARANTEED_WIDTH 1 10489 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_NORMAL_LBN 1 10490 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_NORMAL_WIDTH 1 10491 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_LOW_LBN 2 10492 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_LOW_WIDTH 1 10493 /* the reaction point (RP) bucket */ 10494 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_RP_BKT_OFST 12 10495 /* an already reserved bucket (typically set to bucket associated with outer 10496 * vswitch) 10497 */ 10498 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT1_OFST 16 10499 /* an already reserved bucket (typically set to bucket associated with inner 10500 * vswitch) 10501 */ 10502 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT2_OFST 20 10503 /* the min bucket (typically for ETS/minimum bandwidth) */ 10504 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MIN_BKT_OFST 24 10505 /* the static priority associated with the txq */ 10506 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_GUARANTEED_OFST 28 10507 10508 /* MC_CMD_TCM_TXQ_INIT_OUT msgresponse */ 10509 #define MC_CMD_TCM_TXQ_INIT_OUT_LEN 0 10510 10511 10512 /***********************************/ 10513 /* MC_CMD_LINK_PIOBUF 10514 * Link a push I/O buffer to a TxQ 10515 */ 10516 #define MC_CMD_LINK_PIOBUF 0x92 10517 #undef MC_CMD_0x92_PRIVILEGE_CTG 10518 10519 #define MC_CMD_0x92_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 10520 10521 /* MC_CMD_LINK_PIOBUF_IN msgrequest */ 10522 #define MC_CMD_LINK_PIOBUF_IN_LEN 8 10523 /* Handle for allocated push I/O buffer. */ 10524 #define MC_CMD_LINK_PIOBUF_IN_PIOBUF_HANDLE_OFST 0 10525 /* Function Local Instance (VI) number. */ 10526 #define MC_CMD_LINK_PIOBUF_IN_TXQ_INSTANCE_OFST 4 10527 10528 /* MC_CMD_LINK_PIOBUF_OUT msgresponse */ 10529 #define MC_CMD_LINK_PIOBUF_OUT_LEN 0 10530 10531 10532 /***********************************/ 10533 /* MC_CMD_UNLINK_PIOBUF 10534 * Unlink a push I/O buffer from a TxQ 10535 */ 10536 #define MC_CMD_UNLINK_PIOBUF 0x93 10537 #undef MC_CMD_0x93_PRIVILEGE_CTG 10538 10539 #define MC_CMD_0x93_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 10540 10541 /* MC_CMD_UNLINK_PIOBUF_IN msgrequest */ 10542 #define MC_CMD_UNLINK_PIOBUF_IN_LEN 4 10543 /* Function Local Instance (VI) number. */ 10544 #define MC_CMD_UNLINK_PIOBUF_IN_TXQ_INSTANCE_OFST 0 10545 10546 /* MC_CMD_UNLINK_PIOBUF_OUT msgresponse */ 10547 #define MC_CMD_UNLINK_PIOBUF_OUT_LEN 0 10548 10549 10550 /***********************************/ 10551 /* MC_CMD_VSWITCH_ALLOC 10552 * allocate and initialise a v-switch. 10553 */ 10554 #define MC_CMD_VSWITCH_ALLOC 0x94 10555 #undef MC_CMD_0x94_PRIVILEGE_CTG 10556 10557 #define MC_CMD_0x94_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10558 10559 /* MC_CMD_VSWITCH_ALLOC_IN msgrequest */ 10560 #define MC_CMD_VSWITCH_ALLOC_IN_LEN 16 10561 /* The port to connect to the v-switch's upstream port. */ 10562 #define MC_CMD_VSWITCH_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 10563 /* The type of v-switch to create. */ 10564 #define MC_CMD_VSWITCH_ALLOC_IN_TYPE_OFST 4 10565 /* enum: VLAN */ 10566 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VLAN 0x1 10567 /* enum: VEB */ 10568 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEB 0x2 10569 /* enum: VEPA (obsolete) */ 10570 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEPA 0x3 10571 /* enum: MUX */ 10572 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_MUX 0x4 10573 /* enum: Snapper specific; semantics TBD */ 10574 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_TEST 0x5 10575 /* Flags controlling v-port creation */ 10576 #define MC_CMD_VSWITCH_ALLOC_IN_FLAGS_OFST 8 10577 #define MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_LBN 0 10578 #define MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_WIDTH 1 10579 /* The number of VLAN tags to allow for attached v-ports. For VLAN aggregators, 10580 * this must be one or greated, and the attached v-ports must have exactly this 10581 * number of tags. For other v-switch types, this must be zero of greater, and 10582 * is an upper limit on the number of VLAN tags for attached v-ports. An error 10583 * will be returned if existing configuration means we can't support attached 10584 * v-ports with this number of tags. 10585 */ 10586 #define MC_CMD_VSWITCH_ALLOC_IN_NUM_VLAN_TAGS_OFST 12 10587 10588 /* MC_CMD_VSWITCH_ALLOC_OUT msgresponse */ 10589 #define MC_CMD_VSWITCH_ALLOC_OUT_LEN 0 10590 10591 10592 /***********************************/ 10593 /* MC_CMD_VSWITCH_FREE 10594 * de-allocate a v-switch. 10595 */ 10596 #define MC_CMD_VSWITCH_FREE 0x95 10597 #undef MC_CMD_0x95_PRIVILEGE_CTG 10598 10599 #define MC_CMD_0x95_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10600 10601 /* MC_CMD_VSWITCH_FREE_IN msgrequest */ 10602 #define MC_CMD_VSWITCH_FREE_IN_LEN 4 10603 /* The port to which the v-switch is connected. */ 10604 #define MC_CMD_VSWITCH_FREE_IN_UPSTREAM_PORT_ID_OFST 0 10605 10606 /* MC_CMD_VSWITCH_FREE_OUT msgresponse */ 10607 #define MC_CMD_VSWITCH_FREE_OUT_LEN 0 10608 10609 10610 /***********************************/ 10611 /* MC_CMD_VSWITCH_QUERY 10612 * read some config of v-switch. For now this command is an empty placeholder. 10613 * It may be used to check if a v-switch is connected to a given EVB port (if 10614 * not, then the command returns ENOENT). 10615 */ 10616 #define MC_CMD_VSWITCH_QUERY 0x63 10617 #undef MC_CMD_0x63_PRIVILEGE_CTG 10618 10619 #define MC_CMD_0x63_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10620 10621 /* MC_CMD_VSWITCH_QUERY_IN msgrequest */ 10622 #define MC_CMD_VSWITCH_QUERY_IN_LEN 4 10623 /* The port to which the v-switch is connected. */ 10624 #define MC_CMD_VSWITCH_QUERY_IN_UPSTREAM_PORT_ID_OFST 0 10625 10626 /* MC_CMD_VSWITCH_QUERY_OUT msgresponse */ 10627 #define MC_CMD_VSWITCH_QUERY_OUT_LEN 0 10628 10629 10630 /***********************************/ 10631 /* MC_CMD_VPORT_ALLOC 10632 * allocate a v-port. 10633 */ 10634 #define MC_CMD_VPORT_ALLOC 0x96 10635 #undef MC_CMD_0x96_PRIVILEGE_CTG 10636 10637 #define MC_CMD_0x96_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10638 10639 /* MC_CMD_VPORT_ALLOC_IN msgrequest */ 10640 #define MC_CMD_VPORT_ALLOC_IN_LEN 20 10641 /* The port to which the v-switch is connected. */ 10642 #define MC_CMD_VPORT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 10643 /* The type of the new v-port. */ 10644 #define MC_CMD_VPORT_ALLOC_IN_TYPE_OFST 4 10645 /* enum: VLAN (obsolete) */ 10646 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VLAN 0x1 10647 /* enum: VEB (obsolete) */ 10648 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEB 0x2 10649 /* enum: VEPA (obsolete) */ 10650 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEPA 0x3 10651 /* enum: A normal v-port receives packets which match a specified MAC and/or 10652 * VLAN. 10653 */ 10654 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_NORMAL 0x4 10655 /* enum: An expansion v-port packets traffic which don't match any other 10656 * v-port. 10657 */ 10658 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_EXPANSION 0x5 10659 /* enum: An test v-port receives packets which match any filters installed by 10660 * its downstream components. 10661 */ 10662 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_TEST 0x6 10663 /* Flags controlling v-port creation */ 10664 #define MC_CMD_VPORT_ALLOC_IN_FLAGS_OFST 8 10665 #define MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_LBN 0 10666 #define MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_WIDTH 1 10667 #define MC_CMD_VPORT_ALLOC_IN_FLAG_VLAN_RESTRICT_LBN 1 10668 #define MC_CMD_VPORT_ALLOC_IN_FLAG_VLAN_RESTRICT_WIDTH 1 10669 /* The number of VLAN tags to insert/remove. An error will be returned if 10670 * incompatible with the number of VLAN tags specified for the upstream 10671 * v-switch. 10672 */ 10673 #define MC_CMD_VPORT_ALLOC_IN_NUM_VLAN_TAGS_OFST 12 10674 /* The actual VLAN tags to insert/remove */ 10675 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAGS_OFST 16 10676 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_LBN 0 10677 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_WIDTH 16 10678 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_LBN 16 10679 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_WIDTH 16 10680 10681 /* MC_CMD_VPORT_ALLOC_OUT msgresponse */ 10682 #define MC_CMD_VPORT_ALLOC_OUT_LEN 4 10683 /* The handle of the new v-port */ 10684 #define MC_CMD_VPORT_ALLOC_OUT_VPORT_ID_OFST 0 10685 10686 10687 /***********************************/ 10688 /* MC_CMD_VPORT_FREE 10689 * de-allocate a v-port. 10690 */ 10691 #define MC_CMD_VPORT_FREE 0x97 10692 #undef MC_CMD_0x97_PRIVILEGE_CTG 10693 10694 #define MC_CMD_0x97_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10695 10696 /* MC_CMD_VPORT_FREE_IN msgrequest */ 10697 #define MC_CMD_VPORT_FREE_IN_LEN 4 10698 /* The handle of the v-port */ 10699 #define MC_CMD_VPORT_FREE_IN_VPORT_ID_OFST 0 10700 10701 /* MC_CMD_VPORT_FREE_OUT msgresponse */ 10702 #define MC_CMD_VPORT_FREE_OUT_LEN 0 10703 10704 10705 /***********************************/ 10706 /* MC_CMD_VADAPTOR_ALLOC 10707 * allocate a v-adaptor. 10708 */ 10709 #define MC_CMD_VADAPTOR_ALLOC 0x98 10710 #undef MC_CMD_0x98_PRIVILEGE_CTG 10711 10712 #define MC_CMD_0x98_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10713 10714 /* MC_CMD_VADAPTOR_ALLOC_IN msgrequest */ 10715 #define MC_CMD_VADAPTOR_ALLOC_IN_LEN 30 10716 /* The port to connect to the v-adaptor's port. */ 10717 #define MC_CMD_VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 10718 /* Flags controlling v-adaptor creation */ 10719 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAGS_OFST 8 10720 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_LBN 0 10721 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_WIDTH 1 10722 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 1 10723 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1 10724 /* The number of VLAN tags to strip on receive */ 10725 #define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLANS_OFST 12 10726 /* The number of VLAN tags to transparently insert/remove. */ 10727 #define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLAN_TAGS_OFST 16 10728 /* The actual VLAN tags to insert/remove */ 10729 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAGS_OFST 20 10730 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_0_LBN 0 10731 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_0_WIDTH 16 10732 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_1_LBN 16 10733 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_1_WIDTH 16 10734 /* The MAC address to assign to this v-adaptor */ 10735 #define MC_CMD_VADAPTOR_ALLOC_IN_MACADDR_OFST 24 10736 #define MC_CMD_VADAPTOR_ALLOC_IN_MACADDR_LEN 6 10737 /* enum: Derive the MAC address from the upstream port */ 10738 #define MC_CMD_VADAPTOR_ALLOC_IN_AUTO_MAC 0x0 10739 10740 /* MC_CMD_VADAPTOR_ALLOC_OUT msgresponse */ 10741 #define MC_CMD_VADAPTOR_ALLOC_OUT_LEN 0 10742 10743 10744 /***********************************/ 10745 /* MC_CMD_VADAPTOR_FREE 10746 * de-allocate a v-adaptor. 10747 */ 10748 #define MC_CMD_VADAPTOR_FREE 0x99 10749 #undef MC_CMD_0x99_PRIVILEGE_CTG 10750 10751 #define MC_CMD_0x99_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10752 10753 /* MC_CMD_VADAPTOR_FREE_IN msgrequest */ 10754 #define MC_CMD_VADAPTOR_FREE_IN_LEN 4 10755 /* The port to which the v-adaptor is connected. */ 10756 #define MC_CMD_VADAPTOR_FREE_IN_UPSTREAM_PORT_ID_OFST 0 10757 10758 /* MC_CMD_VADAPTOR_FREE_OUT msgresponse */ 10759 #define MC_CMD_VADAPTOR_FREE_OUT_LEN 0 10760 10761 10762 /***********************************/ 10763 /* MC_CMD_VADAPTOR_SET_MAC 10764 * assign a new MAC address to a v-adaptor. 10765 */ 10766 #define MC_CMD_VADAPTOR_SET_MAC 0x5d 10767 #undef MC_CMD_0x5d_PRIVILEGE_CTG 10768 10769 #define MC_CMD_0x5d_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10770 10771 /* MC_CMD_VADAPTOR_SET_MAC_IN msgrequest */ 10772 #define MC_CMD_VADAPTOR_SET_MAC_IN_LEN 10 10773 /* The port to which the v-adaptor is connected. */ 10774 #define MC_CMD_VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID_OFST 0 10775 /* The new MAC address to assign to this v-adaptor */ 10776 #define MC_CMD_VADAPTOR_SET_MAC_IN_MACADDR_OFST 4 10777 #define MC_CMD_VADAPTOR_SET_MAC_IN_MACADDR_LEN 6 10778 10779 /* MC_CMD_VADAPTOR_SET_MAC_OUT msgresponse */ 10780 #define MC_CMD_VADAPTOR_SET_MAC_OUT_LEN 0 10781 10782 10783 /***********************************/ 10784 /* MC_CMD_VADAPTOR_GET_MAC 10785 * read the MAC address assigned to a v-adaptor. 10786 */ 10787 #define MC_CMD_VADAPTOR_GET_MAC 0x5e 10788 #undef MC_CMD_0x5e_PRIVILEGE_CTG 10789 10790 #define MC_CMD_0x5e_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10791 10792 /* MC_CMD_VADAPTOR_GET_MAC_IN msgrequest */ 10793 #define MC_CMD_VADAPTOR_GET_MAC_IN_LEN 4 10794 /* The port to which the v-adaptor is connected. */ 10795 #define MC_CMD_VADAPTOR_GET_MAC_IN_UPSTREAM_PORT_ID_OFST 0 10796 10797 /* MC_CMD_VADAPTOR_GET_MAC_OUT msgresponse */ 10798 #define MC_CMD_VADAPTOR_GET_MAC_OUT_LEN 6 10799 /* The MAC address assigned to this v-adaptor */ 10800 #define MC_CMD_VADAPTOR_GET_MAC_OUT_MACADDR_OFST 0 10801 #define MC_CMD_VADAPTOR_GET_MAC_OUT_MACADDR_LEN 6 10802 10803 10804 /***********************************/ 10805 /* MC_CMD_VADAPTOR_QUERY 10806 * read some config of v-adaptor. 10807 */ 10808 #define MC_CMD_VADAPTOR_QUERY 0x61 10809 #undef MC_CMD_0x61_PRIVILEGE_CTG 10810 10811 #define MC_CMD_0x61_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10812 10813 /* MC_CMD_VADAPTOR_QUERY_IN msgrequest */ 10814 #define MC_CMD_VADAPTOR_QUERY_IN_LEN 4 10815 /* The port to which the v-adaptor is connected. */ 10816 #define MC_CMD_VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID_OFST 0 10817 10818 /* MC_CMD_VADAPTOR_QUERY_OUT msgresponse */ 10819 #define MC_CMD_VADAPTOR_QUERY_OUT_LEN 12 10820 /* The EVB port flags as defined at MC_CMD_VPORT_ALLOC. */ 10821 #define MC_CMD_VADAPTOR_QUERY_OUT_PORT_FLAGS_OFST 0 10822 /* The v-adaptor flags as defined at MC_CMD_VADAPTOR_ALLOC. */ 10823 #define MC_CMD_VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS_OFST 4 10824 /* The number of VLAN tags that may still be added */ 10825 #define MC_CMD_VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_OFST 8 10826 10827 10828 /***********************************/ 10829 /* MC_CMD_EVB_PORT_ASSIGN 10830 * assign a port to a PCI function. 10831 */ 10832 #define MC_CMD_EVB_PORT_ASSIGN 0x9a 10833 #undef MC_CMD_0x9a_PRIVILEGE_CTG 10834 10835 #define MC_CMD_0x9a_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10836 10837 /* MC_CMD_EVB_PORT_ASSIGN_IN msgrequest */ 10838 #define MC_CMD_EVB_PORT_ASSIGN_IN_LEN 8 10839 /* The port to assign. */ 10840 #define MC_CMD_EVB_PORT_ASSIGN_IN_PORT_ID_OFST 0 10841 /* The target function to modify. */ 10842 #define MC_CMD_EVB_PORT_ASSIGN_IN_FUNCTION_OFST 4 10843 #define MC_CMD_EVB_PORT_ASSIGN_IN_PF_LBN 0 10844 #define MC_CMD_EVB_PORT_ASSIGN_IN_PF_WIDTH 16 10845 #define MC_CMD_EVB_PORT_ASSIGN_IN_VF_LBN 16 10846 #define MC_CMD_EVB_PORT_ASSIGN_IN_VF_WIDTH 16 10847 10848 /* MC_CMD_EVB_PORT_ASSIGN_OUT msgresponse */ 10849 #define MC_CMD_EVB_PORT_ASSIGN_OUT_LEN 0 10850 10851 10852 /***********************************/ 10853 /* MC_CMD_RDWR_A64_REGIONS 10854 * Assign the 64 bit region addresses. 10855 */ 10856 #define MC_CMD_RDWR_A64_REGIONS 0x9b 10857 #undef MC_CMD_0x9b_PRIVILEGE_CTG 10858 10859 #define MC_CMD_0x9b_PRIVILEGE_CTG SRIOV_CTG_ADMIN 10860 10861 /* MC_CMD_RDWR_A64_REGIONS_IN msgrequest */ 10862 #define MC_CMD_RDWR_A64_REGIONS_IN_LEN 17 10863 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION0_OFST 0 10864 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION1_OFST 4 10865 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION2_OFST 8 10866 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION3_OFST 12 10867 /* Write enable bits 0-3, set to write, clear to read. */ 10868 #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_LBN 128 10869 #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_WIDTH 4 10870 #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_BYTE_OFST 16 10871 #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_BYTE_LEN 1 10872 10873 /* MC_CMD_RDWR_A64_REGIONS_OUT msgresponse: This data always included 10874 * regardless of state of write bits in the request. 10875 */ 10876 #define MC_CMD_RDWR_A64_REGIONS_OUT_LEN 16 10877 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION0_OFST 0 10878 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION1_OFST 4 10879 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION2_OFST 8 10880 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION3_OFST 12 10881 10882 10883 /***********************************/ 10884 /* MC_CMD_ONLOAD_STACK_ALLOC 10885 * Allocate an Onload stack ID. 10886 */ 10887 #define MC_CMD_ONLOAD_STACK_ALLOC 0x9c 10888 #undef MC_CMD_0x9c_PRIVILEGE_CTG 10889 10890 #define MC_CMD_0x9c_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 10891 10892 /* MC_CMD_ONLOAD_STACK_ALLOC_IN msgrequest */ 10893 #define MC_CMD_ONLOAD_STACK_ALLOC_IN_LEN 4 10894 /* The handle of the owning upstream port */ 10895 #define MC_CMD_ONLOAD_STACK_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 10896 10897 /* MC_CMD_ONLOAD_STACK_ALLOC_OUT msgresponse */ 10898 #define MC_CMD_ONLOAD_STACK_ALLOC_OUT_LEN 4 10899 /* The handle of the new Onload stack */ 10900 #define MC_CMD_ONLOAD_STACK_ALLOC_OUT_ONLOAD_STACK_ID_OFST 0 10901 10902 10903 /***********************************/ 10904 /* MC_CMD_ONLOAD_STACK_FREE 10905 * Free an Onload stack ID. 10906 */ 10907 #define MC_CMD_ONLOAD_STACK_FREE 0x9d 10908 #undef MC_CMD_0x9d_PRIVILEGE_CTG 10909 10910 #define MC_CMD_0x9d_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 10911 10912 /* MC_CMD_ONLOAD_STACK_FREE_IN msgrequest */ 10913 #define MC_CMD_ONLOAD_STACK_FREE_IN_LEN 4 10914 /* The handle of the Onload stack */ 10915 #define MC_CMD_ONLOAD_STACK_FREE_IN_ONLOAD_STACK_ID_OFST 0 10916 10917 /* MC_CMD_ONLOAD_STACK_FREE_OUT msgresponse */ 10918 #define MC_CMD_ONLOAD_STACK_FREE_OUT_LEN 0 10919 10920 10921 /***********************************/ 10922 /* MC_CMD_RSS_CONTEXT_ALLOC 10923 * Allocate an RSS context. 10924 */ 10925 #define MC_CMD_RSS_CONTEXT_ALLOC 0x9e 10926 #undef MC_CMD_0x9e_PRIVILEGE_CTG 10927 10928 #define MC_CMD_0x9e_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10929 10930 /* MC_CMD_RSS_CONTEXT_ALLOC_IN msgrequest */ 10931 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN 12 10932 /* The handle of the owning upstream port */ 10933 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 10934 /* The type of context to allocate */ 10935 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_OFST 4 10936 /* enum: Allocate a context for exclusive use. The key and indirection table 10937 * must be explicitly configured. 10938 */ 10939 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE 0x0 10940 /* enum: Allocate a context for shared use; this will spread across a range of 10941 * queues, but the key and indirection table are pre-configured and may not be 10942 * changed. For this mode, NUM_QUEUES must 2, 4, 8, 16, 32 or 64. 10943 */ 10944 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED 0x1 10945 /* Number of queues spanned by this context, in the range 1-64; valid offsets 10946 * in the indirection table will be in the range 0 to NUM_QUEUES-1. 10947 */ 10948 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_NUM_QUEUES_OFST 8 10949 10950 /* MC_CMD_RSS_CONTEXT_ALLOC_OUT msgresponse */ 10951 #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN 4 10952 /* The handle of the new RSS context. This should be considered opaque to the 10953 * host, although a value of 0xFFFFFFFF is guaranteed never to be a valid 10954 * handle. 10955 */ 10956 #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_OFST 0 10957 /* enum: guaranteed invalid RSS context handle value */ 10958 #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_INVALID 0xffffffff 10959 10960 10961 /***********************************/ 10962 /* MC_CMD_RSS_CONTEXT_FREE 10963 * Free an RSS context. 10964 */ 10965 #define MC_CMD_RSS_CONTEXT_FREE 0x9f 10966 #undef MC_CMD_0x9f_PRIVILEGE_CTG 10967 10968 #define MC_CMD_0x9f_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10969 10970 /* MC_CMD_RSS_CONTEXT_FREE_IN msgrequest */ 10971 #define MC_CMD_RSS_CONTEXT_FREE_IN_LEN 4 10972 /* The handle of the RSS context */ 10973 #define MC_CMD_RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID_OFST 0 10974 10975 /* MC_CMD_RSS_CONTEXT_FREE_OUT msgresponse */ 10976 #define MC_CMD_RSS_CONTEXT_FREE_OUT_LEN 0 10977 10978 10979 /***********************************/ 10980 /* MC_CMD_RSS_CONTEXT_SET_KEY 10981 * Set the Toeplitz hash key for an RSS context. 10982 */ 10983 #define MC_CMD_RSS_CONTEXT_SET_KEY 0xa0 10984 #undef MC_CMD_0xa0_PRIVILEGE_CTG 10985 10986 #define MC_CMD_0xa0_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10987 10988 /* MC_CMD_RSS_CONTEXT_SET_KEY_IN msgrequest */ 10989 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN 44 10990 /* The handle of the RSS context */ 10991 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID_OFST 0 10992 /* The 40-byte Toeplitz hash key (TBD endianness issues?) */ 10993 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_OFST 4 10994 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN 40 10995 10996 /* MC_CMD_RSS_CONTEXT_SET_KEY_OUT msgresponse */ 10997 #define MC_CMD_RSS_CONTEXT_SET_KEY_OUT_LEN 0 10998 10999 11000 /***********************************/ 11001 /* MC_CMD_RSS_CONTEXT_GET_KEY 11002 * Get the Toeplitz hash key for an RSS context. 11003 */ 11004 #define MC_CMD_RSS_CONTEXT_GET_KEY 0xa1 11005 #undef MC_CMD_0xa1_PRIVILEGE_CTG 11006 11007 #define MC_CMD_0xa1_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11008 11009 /* MC_CMD_RSS_CONTEXT_GET_KEY_IN msgrequest */ 11010 #define MC_CMD_RSS_CONTEXT_GET_KEY_IN_LEN 4 11011 /* The handle of the RSS context */ 11012 #define MC_CMD_RSS_CONTEXT_GET_KEY_IN_RSS_CONTEXT_ID_OFST 0 11013 11014 /* MC_CMD_RSS_CONTEXT_GET_KEY_OUT msgresponse */ 11015 #define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_LEN 44 11016 /* The 40-byte Toeplitz hash key (TBD endianness issues?) */ 11017 #define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY_OFST 4 11018 #define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY_LEN 40 11019 11020 11021 /***********************************/ 11022 /* MC_CMD_RSS_CONTEXT_SET_TABLE 11023 * Set the indirection table for an RSS context. 11024 */ 11025 #define MC_CMD_RSS_CONTEXT_SET_TABLE 0xa2 11026 #undef MC_CMD_0xa2_PRIVILEGE_CTG 11027 11028 #define MC_CMD_0xa2_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11029 11030 /* MC_CMD_RSS_CONTEXT_SET_TABLE_IN msgrequest */ 11031 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN 132 11032 /* The handle of the RSS context */ 11033 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID_OFST 0 11034 /* The 128-byte indirection table (1 byte per entry) */ 11035 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_OFST 4 11036 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN 128 11037 11038 /* MC_CMD_RSS_CONTEXT_SET_TABLE_OUT msgresponse */ 11039 #define MC_CMD_RSS_CONTEXT_SET_TABLE_OUT_LEN 0 11040 11041 11042 /***********************************/ 11043 /* MC_CMD_RSS_CONTEXT_GET_TABLE 11044 * Get the indirection table for an RSS context. 11045 */ 11046 #define MC_CMD_RSS_CONTEXT_GET_TABLE 0xa3 11047 #undef MC_CMD_0xa3_PRIVILEGE_CTG 11048 11049 #define MC_CMD_0xa3_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11050 11051 /* MC_CMD_RSS_CONTEXT_GET_TABLE_IN msgrequest */ 11052 #define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_LEN 4 11053 /* The handle of the RSS context */ 11054 #define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_RSS_CONTEXT_ID_OFST 0 11055 11056 /* MC_CMD_RSS_CONTEXT_GET_TABLE_OUT msgresponse */ 11057 #define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_LEN 132 11058 /* The 128-byte indirection table (1 byte per entry) */ 11059 #define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_OFST 4 11060 #define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_LEN 128 11061 11062 11063 /***********************************/ 11064 /* MC_CMD_RSS_CONTEXT_SET_FLAGS 11065 * Set various control flags for an RSS context. 11066 */ 11067 #define MC_CMD_RSS_CONTEXT_SET_FLAGS 0xe1 11068 #undef MC_CMD_0xe1_PRIVILEGE_CTG 11069 11070 #define MC_CMD_0xe1_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11071 11072 /* MC_CMD_RSS_CONTEXT_SET_FLAGS_IN msgrequest */ 11073 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_LEN 8 11074 /* The handle of the RSS context */ 11075 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID_OFST 0 11076 /* Hash control flags. The _EN bits are always supported, but new modes are 11077 * available when ADDITIONAL_RSS_MODES is reported by MC_CMD_GET_CAPABILITIES: 11078 * in this case, the MODE fields may be set to non-zero values, and will take 11079 * effect regardless of the settings of the _EN flags. See the RSS_MODE 11080 * structure for the meaning of the mode bits. Drivers must check the 11081 * capability before trying to set any _MODE fields, as older firmware will 11082 * reject any attempt to set the FLAGS field to a value > 0xff with EINVAL. In 11083 * the case where all the _MODE flags are zero, the _EN flags take effect, 11084 * providing backward compatibility for existing drivers. (Setting all _MODE 11085 * *and* all _EN flags to zero is valid, to disable RSS spreading for that 11086 * particular packet type.) 11087 */ 11088 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_FLAGS_OFST 4 11089 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_LBN 0 11090 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_WIDTH 1 11091 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_LBN 1 11092 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_WIDTH 1 11093 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_LBN 2 11094 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_WIDTH 1 11095 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_LBN 3 11096 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_WIDTH 1 11097 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_LBN 4 11098 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_WIDTH 4 11099 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_LBN 8 11100 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_WIDTH 4 11101 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE_LBN 12 11102 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE_WIDTH 4 11103 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_LBN 16 11104 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_WIDTH 4 11105 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_LBN 20 11106 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_WIDTH 4 11107 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE_LBN 24 11108 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE_WIDTH 4 11109 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_LBN 28 11110 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_WIDTH 4 11111 11112 /* MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT msgresponse */ 11113 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT_LEN 0 11114 11115 11116 /***********************************/ 11117 /* MC_CMD_RSS_CONTEXT_GET_FLAGS 11118 * Get various control flags for an RSS context. 11119 */ 11120 #define MC_CMD_RSS_CONTEXT_GET_FLAGS 0xe2 11121 #undef MC_CMD_0xe2_PRIVILEGE_CTG 11122 11123 #define MC_CMD_0xe2_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11124 11125 /* MC_CMD_RSS_CONTEXT_GET_FLAGS_IN msgrequest */ 11126 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_LEN 4 11127 /* The handle of the RSS context */ 11128 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_RSS_CONTEXT_ID_OFST 0 11129 11130 /* MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT msgresponse */ 11131 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN 8 11132 /* Hash control flags. If all _MODE bits are zero (which will always be true 11133 * for older firmware which does not report the ADDITIONAL_RSS_MODES 11134 * capability), the _EN bits report the state. If any _MODE bits are non-zero 11135 * (which will only be true when the firmware reports ADDITIONAL_RSS_MODES) 11136 * then the _EN bits should be disregarded, although the _MODE flags are 11137 * guaranteed to be consistent with the _EN flags for a freshly-allocated RSS 11138 * context and in the case where the _EN flags were used in the SET. This 11139 * provides backward compatibility: old drivers will not be attempting to 11140 * derive any meaning from the _MODE bits (and can never set them to any value 11141 * not representable by the _EN bits); new drivers can always determine the 11142 * mode by looking only at the _MODE bits; the value returned by a GET can 11143 * always be used for a SET regardless of old/new driver vs. old/new firmware. 11144 */ 11145 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_OFST 4 11146 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_LBN 0 11147 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_WIDTH 1 11148 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_LBN 1 11149 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_WIDTH 1 11150 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_LBN 2 11151 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_WIDTH 1 11152 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_LBN 3 11153 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_WIDTH 1 11154 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_LBN 4 11155 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_WIDTH 4 11156 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_LBN 8 11157 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_WIDTH 4 11158 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_LBN 12 11159 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_WIDTH 4 11160 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_LBN 16 11161 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_WIDTH 4 11162 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_LBN 20 11163 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_WIDTH 4 11164 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_LBN 24 11165 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_WIDTH 4 11166 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_LBN 28 11167 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_WIDTH 4 11168 11169 11170 /***********************************/ 11171 /* MC_CMD_DOT1P_MAPPING_ALLOC 11172 * Allocate a .1p mapping. 11173 */ 11174 #define MC_CMD_DOT1P_MAPPING_ALLOC 0xa4 11175 #undef MC_CMD_0xa4_PRIVILEGE_CTG 11176 11177 #define MC_CMD_0xa4_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11178 11179 /* MC_CMD_DOT1P_MAPPING_ALLOC_IN msgrequest */ 11180 #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_LEN 8 11181 /* The handle of the owning upstream port */ 11182 #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 11183 /* Number of queues spanned by this mapping, in the range 1-64; valid fixed 11184 * offsets in the mapping table will be in the range 0 to NUM_QUEUES-1, and 11185 * referenced RSS contexts must span no more than this number. 11186 */ 11187 #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_NUM_QUEUES_OFST 4 11188 11189 /* MC_CMD_DOT1P_MAPPING_ALLOC_OUT msgresponse */ 11190 #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_LEN 4 11191 /* The handle of the new .1p mapping. This should be considered opaque to the 11192 * host, although a value of 0xFFFFFFFF is guaranteed never to be a valid 11193 * handle. 11194 */ 11195 #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_OFST 0 11196 /* enum: guaranteed invalid .1p mapping handle value */ 11197 #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_INVALID 0xffffffff 11198 11199 11200 /***********************************/ 11201 /* MC_CMD_DOT1P_MAPPING_FREE 11202 * Free a .1p mapping. 11203 */ 11204 #define MC_CMD_DOT1P_MAPPING_FREE 0xa5 11205 #undef MC_CMD_0xa5_PRIVILEGE_CTG 11206 11207 #define MC_CMD_0xa5_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11208 11209 /* MC_CMD_DOT1P_MAPPING_FREE_IN msgrequest */ 11210 #define MC_CMD_DOT1P_MAPPING_FREE_IN_LEN 4 11211 /* The handle of the .1p mapping */ 11212 #define MC_CMD_DOT1P_MAPPING_FREE_IN_DOT1P_MAPPING_ID_OFST 0 11213 11214 /* MC_CMD_DOT1P_MAPPING_FREE_OUT msgresponse */ 11215 #define MC_CMD_DOT1P_MAPPING_FREE_OUT_LEN 0 11216 11217 11218 /***********************************/ 11219 /* MC_CMD_DOT1P_MAPPING_SET_TABLE 11220 * Set the mapping table for a .1p mapping. 11221 */ 11222 #define MC_CMD_DOT1P_MAPPING_SET_TABLE 0xa6 11223 #undef MC_CMD_0xa6_PRIVILEGE_CTG 11224 11225 #define MC_CMD_0xa6_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11226 11227 /* MC_CMD_DOT1P_MAPPING_SET_TABLE_IN msgrequest */ 11228 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_LEN 36 11229 /* The handle of the .1p mapping */ 11230 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_DOT1P_MAPPING_ID_OFST 0 11231 /* Per-priority mappings (1 32-bit word per entry - an offset or RSS context 11232 * handle) 11233 */ 11234 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_MAPPING_TABLE_OFST 4 11235 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_MAPPING_TABLE_LEN 32 11236 11237 /* MC_CMD_DOT1P_MAPPING_SET_TABLE_OUT msgresponse */ 11238 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_OUT_LEN 0 11239 11240 11241 /***********************************/ 11242 /* MC_CMD_DOT1P_MAPPING_GET_TABLE 11243 * Get the mapping table for a .1p mapping. 11244 */ 11245 #define MC_CMD_DOT1P_MAPPING_GET_TABLE 0xa7 11246 #undef MC_CMD_0xa7_PRIVILEGE_CTG 11247 11248 #define MC_CMD_0xa7_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11249 11250 /* MC_CMD_DOT1P_MAPPING_GET_TABLE_IN msgrequest */ 11251 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_IN_LEN 4 11252 /* The handle of the .1p mapping */ 11253 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_IN_DOT1P_MAPPING_ID_OFST 0 11254 11255 /* MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT msgresponse */ 11256 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_LEN 36 11257 /* Per-priority mappings (1 32-bit word per entry - an offset or RSS context 11258 * handle) 11259 */ 11260 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_MAPPING_TABLE_OFST 4 11261 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_MAPPING_TABLE_LEN 32 11262 11263 11264 /***********************************/ 11265 /* MC_CMD_GET_VECTOR_CFG 11266 * Get Interrupt Vector config for this PF. 11267 */ 11268 #define MC_CMD_GET_VECTOR_CFG 0xbf 11269 #undef MC_CMD_0xbf_PRIVILEGE_CTG 11270 11271 #define MC_CMD_0xbf_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11272 11273 /* MC_CMD_GET_VECTOR_CFG_IN msgrequest */ 11274 #define MC_CMD_GET_VECTOR_CFG_IN_LEN 0 11275 11276 /* MC_CMD_GET_VECTOR_CFG_OUT msgresponse */ 11277 #define MC_CMD_GET_VECTOR_CFG_OUT_LEN 12 11278 /* Base absolute interrupt vector number. */ 11279 #define MC_CMD_GET_VECTOR_CFG_OUT_VEC_BASE_OFST 0 11280 /* Number of interrupt vectors allocate to this PF. */ 11281 #define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_PF_OFST 4 11282 /* Number of interrupt vectors to allocate per VF. */ 11283 #define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_VF_OFST 8 11284 11285 11286 /***********************************/ 11287 /* MC_CMD_SET_VECTOR_CFG 11288 * Set Interrupt Vector config for this PF. 11289 */ 11290 #define MC_CMD_SET_VECTOR_CFG 0xc0 11291 #undef MC_CMD_0xc0_PRIVILEGE_CTG 11292 11293 #define MC_CMD_0xc0_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11294 11295 /* MC_CMD_SET_VECTOR_CFG_IN msgrequest */ 11296 #define MC_CMD_SET_VECTOR_CFG_IN_LEN 12 11297 /* Base absolute interrupt vector number, or MC_CMD_RESOURCE_INSTANCE_ANY to 11298 * let the system find a suitable base. 11299 */ 11300 #define MC_CMD_SET_VECTOR_CFG_IN_VEC_BASE_OFST 0 11301 /* Number of interrupt vectors allocate to this PF. */ 11302 #define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_PF_OFST 4 11303 /* Number of interrupt vectors to allocate per VF. */ 11304 #define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_VF_OFST 8 11305 11306 /* MC_CMD_SET_VECTOR_CFG_OUT msgresponse */ 11307 #define MC_CMD_SET_VECTOR_CFG_OUT_LEN 0 11308 11309 11310 /***********************************/ 11311 /* MC_CMD_VPORT_ADD_MAC_ADDRESS 11312 * Add a MAC address to a v-port 11313 */ 11314 #define MC_CMD_VPORT_ADD_MAC_ADDRESS 0xa8 11315 #undef MC_CMD_0xa8_PRIVILEGE_CTG 11316 11317 #define MC_CMD_0xa8_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11318 11319 /* MC_CMD_VPORT_ADD_MAC_ADDRESS_IN msgrequest */ 11320 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN 10 11321 /* The handle of the v-port */ 11322 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID_OFST 0 11323 /* MAC address to add */ 11324 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_MACADDR_OFST 4 11325 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_MACADDR_LEN 6 11326 11327 /* MC_CMD_VPORT_ADD_MAC_ADDRESS_OUT msgresponse */ 11328 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_OUT_LEN 0 11329 11330 11331 /***********************************/ 11332 /* MC_CMD_VPORT_DEL_MAC_ADDRESS 11333 * Delete a MAC address from a v-port 11334 */ 11335 #define MC_CMD_VPORT_DEL_MAC_ADDRESS 0xa9 11336 #undef MC_CMD_0xa9_PRIVILEGE_CTG 11337 11338 #define MC_CMD_0xa9_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11339 11340 /* MC_CMD_VPORT_DEL_MAC_ADDRESS_IN msgrequest */ 11341 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN 10 11342 /* The handle of the v-port */ 11343 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID_OFST 0 11344 /* MAC address to add */ 11345 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_MACADDR_OFST 4 11346 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_MACADDR_LEN 6 11347 11348 /* MC_CMD_VPORT_DEL_MAC_ADDRESS_OUT msgresponse */ 11349 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_OUT_LEN 0 11350 11351 11352 /***********************************/ 11353 /* MC_CMD_VPORT_GET_MAC_ADDRESSES 11354 * Delete a MAC address from a v-port 11355 */ 11356 #define MC_CMD_VPORT_GET_MAC_ADDRESSES 0xaa 11357 #undef MC_CMD_0xaa_PRIVILEGE_CTG 11358 11359 #define MC_CMD_0xaa_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11360 11361 /* MC_CMD_VPORT_GET_MAC_ADDRESSES_IN msgrequest */ 11362 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN 4 11363 /* The handle of the v-port */ 11364 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID_OFST 0 11365 11366 /* MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT msgresponse */ 11367 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN 4 11368 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX 250 11369 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LEN(num) (4+6*(num)) 11370 /* The number of MAC addresses returned */ 11371 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT_OFST 0 11372 /* Array of MAC addresses */ 11373 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_OFST 4 11374 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_LEN 6 11375 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MINNUM 0 11376 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MAXNUM 41 11377 11378 11379 /***********************************/ 11380 /* MC_CMD_VPORT_RECONFIGURE 11381 * Replace VLAN tags and/or MAC addresses of an existing v-port. If the v-port 11382 * has already been passed to another function (v-port's user), then that 11383 * function will be reset before applying the changes. 11384 */ 11385 #define MC_CMD_VPORT_RECONFIGURE 0xeb 11386 #undef MC_CMD_0xeb_PRIVILEGE_CTG 11387 11388 #define MC_CMD_0xeb_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11389 11390 /* MC_CMD_VPORT_RECONFIGURE_IN msgrequest */ 11391 #define MC_CMD_VPORT_RECONFIGURE_IN_LEN 44 11392 /* The handle of the v-port */ 11393 #define MC_CMD_VPORT_RECONFIGURE_IN_VPORT_ID_OFST 0 11394 /* Flags requesting what should be changed. */ 11395 #define MC_CMD_VPORT_RECONFIGURE_IN_FLAGS_OFST 4 11396 #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_VLAN_TAGS_LBN 0 11397 #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_VLAN_TAGS_WIDTH 1 11398 #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_MACADDRS_LBN 1 11399 #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_MACADDRS_WIDTH 1 11400 /* The number of VLAN tags to insert/remove. An error will be returned if 11401 * incompatible with the number of VLAN tags specified for the upstream 11402 * v-switch. 11403 */ 11404 #define MC_CMD_VPORT_RECONFIGURE_IN_NUM_VLAN_TAGS_OFST 8 11405 /* The actual VLAN tags to insert/remove */ 11406 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAGS_OFST 12 11407 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_0_LBN 0 11408 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_0_WIDTH 16 11409 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_1_LBN 16 11410 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_1_WIDTH 16 11411 /* The number of MAC addresses to add */ 11412 #define MC_CMD_VPORT_RECONFIGURE_IN_NUM_MACADDRS_OFST 16 11413 /* MAC addresses to add */ 11414 #define MC_CMD_VPORT_RECONFIGURE_IN_MACADDRS_OFST 20 11415 #define MC_CMD_VPORT_RECONFIGURE_IN_MACADDRS_LEN 6 11416 #define MC_CMD_VPORT_RECONFIGURE_IN_MACADDRS_NUM 4 11417 11418 /* MC_CMD_VPORT_RECONFIGURE_OUT msgresponse */ 11419 #define MC_CMD_VPORT_RECONFIGURE_OUT_LEN 4 11420 #define MC_CMD_VPORT_RECONFIGURE_OUT_FLAGS_OFST 0 11421 #define MC_CMD_VPORT_RECONFIGURE_OUT_RESET_DONE_LBN 0 11422 #define MC_CMD_VPORT_RECONFIGURE_OUT_RESET_DONE_WIDTH 1 11423 11424 11425 /***********************************/ 11426 /* MC_CMD_EVB_PORT_QUERY 11427 * read some config of v-port. 11428 */ 11429 #define MC_CMD_EVB_PORT_QUERY 0x62 11430 #undef MC_CMD_0x62_PRIVILEGE_CTG 11431 11432 #define MC_CMD_0x62_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11433 11434 /* MC_CMD_EVB_PORT_QUERY_IN msgrequest */ 11435 #define MC_CMD_EVB_PORT_QUERY_IN_LEN 4 11436 /* The handle of the v-port */ 11437 #define MC_CMD_EVB_PORT_QUERY_IN_PORT_ID_OFST 0 11438 11439 /* MC_CMD_EVB_PORT_QUERY_OUT msgresponse */ 11440 #define MC_CMD_EVB_PORT_QUERY_OUT_LEN 8 11441 /* The EVB port flags as defined at MC_CMD_VPORT_ALLOC. */ 11442 #define MC_CMD_EVB_PORT_QUERY_OUT_PORT_FLAGS_OFST 0 11443 /* The number of VLAN tags that may be used on a v-adaptor connected to this 11444 * EVB port. 11445 */ 11446 #define MC_CMD_EVB_PORT_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_OFST 4 11447 11448 11449 /***********************************/ 11450 /* MC_CMD_DUMP_BUFTBL_ENTRIES 11451 * Dump buffer table entries, mainly for command client debug use. Dumps 11452 * absolute entries, and does not use chunk handles. All entries must be in 11453 * range, and used for q page mapping, Although the latter restriction may be 11454 * lifted in future. 11455 */ 11456 #define MC_CMD_DUMP_BUFTBL_ENTRIES 0xab 11457 #undef MC_CMD_0xab_PRIVILEGE_CTG 11458 11459 #define MC_CMD_0xab_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11460 11461 /* MC_CMD_DUMP_BUFTBL_ENTRIES_IN msgrequest */ 11462 #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_LEN 8 11463 /* Index of the first buffer table entry. */ 11464 #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_FIRSTID_OFST 0 11465 /* Number of buffer table entries to dump. */ 11466 #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_NUMENTRIES_OFST 4 11467 11468 /* MC_CMD_DUMP_BUFTBL_ENTRIES_OUT msgresponse */ 11469 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LENMIN 12 11470 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LENMAX 252 11471 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LEN(num) (0+12*(num)) 11472 /* Raw buffer table entries, layed out as BUFTBL_ENTRY. */ 11473 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_OFST 0 11474 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_LEN 12 11475 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_MINNUM 1 11476 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_MAXNUM 21 11477 11478 11479 /***********************************/ 11480 /* MC_CMD_SET_RXDP_CONFIG 11481 * Set global RXDP configuration settings 11482 */ 11483 #define MC_CMD_SET_RXDP_CONFIG 0xc1 11484 #undef MC_CMD_0xc1_PRIVILEGE_CTG 11485 11486 #define MC_CMD_0xc1_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11487 11488 /* MC_CMD_SET_RXDP_CONFIG_IN msgrequest */ 11489 #define MC_CMD_SET_RXDP_CONFIG_IN_LEN 4 11490 #define MC_CMD_SET_RXDP_CONFIG_IN_DATA_OFST 0 11491 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_LBN 0 11492 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_WIDTH 1 11493 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_LEN_LBN 1 11494 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_LEN_WIDTH 2 11495 /* enum: pad to 64 bytes */ 11496 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_64 0x0 11497 /* enum: pad to 128 bytes (Medford only) */ 11498 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_128 0x1 11499 /* enum: pad to 256 bytes (Medford only) */ 11500 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_256 0x2 11501 11502 /* MC_CMD_SET_RXDP_CONFIG_OUT msgresponse */ 11503 #define MC_CMD_SET_RXDP_CONFIG_OUT_LEN 0 11504 11505 11506 /***********************************/ 11507 /* MC_CMD_GET_RXDP_CONFIG 11508 * Get global RXDP configuration settings 11509 */ 11510 #define MC_CMD_GET_RXDP_CONFIG 0xc2 11511 #undef MC_CMD_0xc2_PRIVILEGE_CTG 11512 11513 #define MC_CMD_0xc2_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11514 11515 /* MC_CMD_GET_RXDP_CONFIG_IN msgrequest */ 11516 #define MC_CMD_GET_RXDP_CONFIG_IN_LEN 0 11517 11518 /* MC_CMD_GET_RXDP_CONFIG_OUT msgresponse */ 11519 #define MC_CMD_GET_RXDP_CONFIG_OUT_LEN 4 11520 #define MC_CMD_GET_RXDP_CONFIG_OUT_DATA_OFST 0 11521 #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_LBN 0 11522 #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_WIDTH 1 11523 #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_LEN_LBN 1 11524 #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_LEN_WIDTH 2 11525 /* Enum values, see field(s): */ 11526 /* MC_CMD_SET_RXDP_CONFIG/MC_CMD_SET_RXDP_CONFIG_IN/PAD_HOST_LEN */ 11527 11528 11529 /***********************************/ 11530 /* MC_CMD_GET_CLOCK 11531 * Return the system and PDCPU clock frequencies. 11532 */ 11533 #define MC_CMD_GET_CLOCK 0xac 11534 #undef MC_CMD_0xac_PRIVILEGE_CTG 11535 11536 #define MC_CMD_0xac_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11537 11538 /* MC_CMD_GET_CLOCK_IN msgrequest */ 11539 #define MC_CMD_GET_CLOCK_IN_LEN 0 11540 11541 /* MC_CMD_GET_CLOCK_OUT msgresponse */ 11542 #define MC_CMD_GET_CLOCK_OUT_LEN 8 11543 /* System frequency, MHz */ 11544 #define MC_CMD_GET_CLOCK_OUT_SYS_FREQ_OFST 0 11545 /* DPCPU frequency, MHz */ 11546 #define MC_CMD_GET_CLOCK_OUT_DPCPU_FREQ_OFST 4 11547 11548 11549 /***********************************/ 11550 /* MC_CMD_SET_CLOCK 11551 * Control the system and DPCPU clock frequencies. Changes are lost reboot. 11552 */ 11553 #define MC_CMD_SET_CLOCK 0xad 11554 #undef MC_CMD_0xad_PRIVILEGE_CTG 11555 11556 #define MC_CMD_0xad_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11557 11558 /* MC_CMD_SET_CLOCK_IN msgrequest */ 11559 #define MC_CMD_SET_CLOCK_IN_LEN 28 11560 /* Requested frequency in MHz for system clock domain */ 11561 #define MC_CMD_SET_CLOCK_IN_SYS_FREQ_OFST 0 11562 /* enum: Leave the system clock domain frequency unchanged */ 11563 #define MC_CMD_SET_CLOCK_IN_SYS_DOMAIN_DONT_CHANGE 0x0 11564 /* Requested frequency in MHz for inter-core clock domain */ 11565 #define MC_CMD_SET_CLOCK_IN_ICORE_FREQ_OFST 4 11566 /* enum: Leave the inter-core clock domain frequency unchanged */ 11567 #define MC_CMD_SET_CLOCK_IN_ICORE_DOMAIN_DONT_CHANGE 0x0 11568 /* Requested frequency in MHz for DPCPU clock domain */ 11569 #define MC_CMD_SET_CLOCK_IN_DPCPU_FREQ_OFST 8 11570 /* enum: Leave the DPCPU clock domain frequency unchanged */ 11571 #define MC_CMD_SET_CLOCK_IN_DPCPU_DOMAIN_DONT_CHANGE 0x0 11572 /* Requested frequency in MHz for PCS clock domain */ 11573 #define MC_CMD_SET_CLOCK_IN_PCS_FREQ_OFST 12 11574 /* enum: Leave the PCS clock domain frequency unchanged */ 11575 #define MC_CMD_SET_CLOCK_IN_PCS_DOMAIN_DONT_CHANGE 0x0 11576 /* Requested frequency in MHz for MC clock domain */ 11577 #define MC_CMD_SET_CLOCK_IN_MC_FREQ_OFST 16 11578 /* enum: Leave the MC clock domain frequency unchanged */ 11579 #define MC_CMD_SET_CLOCK_IN_MC_DOMAIN_DONT_CHANGE 0x0 11580 /* Requested frequency in MHz for rmon clock domain */ 11581 #define MC_CMD_SET_CLOCK_IN_RMON_FREQ_OFST 20 11582 /* enum: Leave the rmon clock domain frequency unchanged */ 11583 #define MC_CMD_SET_CLOCK_IN_RMON_DOMAIN_DONT_CHANGE 0x0 11584 /* Requested frequency in MHz for vswitch clock domain */ 11585 #define MC_CMD_SET_CLOCK_IN_VSWITCH_FREQ_OFST 24 11586 /* enum: Leave the vswitch clock domain frequency unchanged */ 11587 #define MC_CMD_SET_CLOCK_IN_VSWITCH_DOMAIN_DONT_CHANGE 0x0 11588 11589 /* MC_CMD_SET_CLOCK_OUT msgresponse */ 11590 #define MC_CMD_SET_CLOCK_OUT_LEN 28 11591 /* Resulting system frequency in MHz */ 11592 #define MC_CMD_SET_CLOCK_OUT_SYS_FREQ_OFST 0 11593 /* enum: The system clock domain doesn't exist */ 11594 #define MC_CMD_SET_CLOCK_OUT_SYS_DOMAIN_UNSUPPORTED 0x0 11595 /* Resulting inter-core frequency in MHz */ 11596 #define MC_CMD_SET_CLOCK_OUT_ICORE_FREQ_OFST 4 11597 /* enum: The inter-core clock domain doesn't exist / isn't used */ 11598 #define MC_CMD_SET_CLOCK_OUT_ICORE_DOMAIN_UNSUPPORTED 0x0 11599 /* Resulting DPCPU frequency in MHz */ 11600 #define MC_CMD_SET_CLOCK_OUT_DPCPU_FREQ_OFST 8 11601 /* enum: The dpcpu clock domain doesn't exist */ 11602 #define MC_CMD_SET_CLOCK_OUT_DPCPU_DOMAIN_UNSUPPORTED 0x0 11603 /* Resulting PCS frequency in MHz */ 11604 #define MC_CMD_SET_CLOCK_OUT_PCS_FREQ_OFST 12 11605 /* enum: The PCS clock domain doesn't exist / isn't controlled */ 11606 #define MC_CMD_SET_CLOCK_OUT_PCS_DOMAIN_UNSUPPORTED 0x0 11607 /* Resulting MC frequency in MHz */ 11608 #define MC_CMD_SET_CLOCK_OUT_MC_FREQ_OFST 16 11609 /* enum: The MC clock domain doesn't exist / isn't controlled */ 11610 #define MC_CMD_SET_CLOCK_OUT_MC_DOMAIN_UNSUPPORTED 0x0 11611 /* Resulting rmon frequency in MHz */ 11612 #define MC_CMD_SET_CLOCK_OUT_RMON_FREQ_OFST 20 11613 /* enum: The rmon clock domain doesn't exist / isn't controlled */ 11614 #define MC_CMD_SET_CLOCK_OUT_RMON_DOMAIN_UNSUPPORTED 0x0 11615 /* Resulting vswitch frequency in MHz */ 11616 #define MC_CMD_SET_CLOCK_OUT_VSWITCH_FREQ_OFST 24 11617 /* enum: The vswitch clock domain doesn't exist / isn't controlled */ 11618 #define MC_CMD_SET_CLOCK_OUT_VSWITCH_DOMAIN_UNSUPPORTED 0x0 11619 11620 11621 /***********************************/ 11622 /* MC_CMD_DPCPU_RPC 11623 * Send an arbitrary DPCPU message. 11624 */ 11625 #define MC_CMD_DPCPU_RPC 0xae 11626 #undef MC_CMD_0xae_PRIVILEGE_CTG 11627 11628 #define MC_CMD_0xae_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11629 11630 /* MC_CMD_DPCPU_RPC_IN msgrequest */ 11631 #define MC_CMD_DPCPU_RPC_IN_LEN 36 11632 #define MC_CMD_DPCPU_RPC_IN_CPU_OFST 0 11633 /* enum: RxDPCPU0 */ 11634 #define MC_CMD_DPCPU_RPC_IN_DPCPU_RX0 0x0 11635 /* enum: TxDPCPU0 */ 11636 #define MC_CMD_DPCPU_RPC_IN_DPCPU_TX0 0x1 11637 /* enum: TxDPCPU1 */ 11638 #define MC_CMD_DPCPU_RPC_IN_DPCPU_TX1 0x2 11639 /* enum: RxDPCPU1 (Medford only) */ 11640 #define MC_CMD_DPCPU_RPC_IN_DPCPU_RX1 0x3 11641 /* enum: RxDPCPU (will be for the calling function; for now, just an alias of 11642 * DPCPU_RX0) 11643 */ 11644 #define MC_CMD_DPCPU_RPC_IN_DPCPU_RX 0x80 11645 /* enum: TxDPCPU (will be for the calling function; for now, just an alias of 11646 * DPCPU_TX0) 11647 */ 11648 #define MC_CMD_DPCPU_RPC_IN_DPCPU_TX 0x81 11649 /* First 8 bits [39:32] of DATA are consumed by MC-DPCPU protocol and must be 11650 * initialised to zero 11651 */ 11652 #define MC_CMD_DPCPU_RPC_IN_DATA_OFST 4 11653 #define MC_CMD_DPCPU_RPC_IN_DATA_LEN 32 11654 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_CMDNUM_LBN 8 11655 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_CMDNUM_WIDTH 8 11656 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_READ 0x6 /* enum */ 11657 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_WRITE 0x7 /* enum */ 11658 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_SELF_TEST 0xc /* enum */ 11659 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_CSR_ACCESS 0xe /* enum */ 11660 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_READ 0x46 /* enum */ 11661 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_WRITE 0x47 /* enum */ 11662 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_SELF_TEST 0x4a /* enum */ 11663 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_CSR_ACCESS 0x4c /* enum */ 11664 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_SET_MC_REPLAY_CNTXT 0x4d /* enum */ 11665 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_OBJID_LBN 16 11666 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_OBJID_WIDTH 16 11667 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_ADDR_LBN 16 11668 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_ADDR_WIDTH 16 11669 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_COUNT_LBN 48 11670 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_COUNT_WIDTH 16 11671 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_INFO_LBN 16 11672 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_INFO_WIDTH 240 11673 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_LBN 16 11674 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_WIDTH 16 11675 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_STOP_RETURN_RESULT 0x0 /* enum */ 11676 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_READ 0x1 /* enum */ 11677 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_WRITE 0x2 /* enum */ 11678 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_WRITE_READ 0x3 /* enum */ 11679 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_PIPELINED_READ 0x4 /* enum */ 11680 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_START_DELAY_LBN 48 11681 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_START_DELAY_WIDTH 16 11682 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_RPT_COUNT_LBN 64 11683 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_RPT_COUNT_WIDTH 16 11684 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_GAP_DELAY_LBN 80 11685 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_GAP_DELAY_WIDTH 16 11686 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_LBN 16 11687 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_WIDTH 16 11688 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_CUT_THROUGH 0x1 /* enum */ 11689 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_STORE_FORWARD 0x2 /* enum */ 11690 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_STORE_FORWARD_FIRST 0x3 /* enum */ 11691 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_CNTXT_LBN 64 11692 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_CNTXT_WIDTH 16 11693 #define MC_CMD_DPCPU_RPC_IN_WDATA_OFST 12 11694 #define MC_CMD_DPCPU_RPC_IN_WDATA_LEN 24 11695 /* Register data to write. Only valid in write/write-read. */ 11696 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_DATA_OFST 16 11697 /* Register address. */ 11698 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_ADDRESS_OFST 20 11699 11700 /* MC_CMD_DPCPU_RPC_OUT msgresponse */ 11701 #define MC_CMD_DPCPU_RPC_OUT_LEN 36 11702 #define MC_CMD_DPCPU_RPC_OUT_RC_OFST 0 11703 /* DATA */ 11704 #define MC_CMD_DPCPU_RPC_OUT_DATA_OFST 4 11705 #define MC_CMD_DPCPU_RPC_OUT_DATA_LEN 32 11706 #define MC_CMD_DPCPU_RPC_OUT_HDR_CMD_RESP_ERRCODE_LBN 32 11707 #define MC_CMD_DPCPU_RPC_OUT_HDR_CMD_RESP_ERRCODE_WIDTH 16 11708 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_COUNT_LBN 48 11709 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_COUNT_WIDTH 16 11710 #define MC_CMD_DPCPU_RPC_OUT_RDATA_OFST 12 11711 #define MC_CMD_DPCPU_RPC_OUT_RDATA_LEN 24 11712 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_1_OFST 12 11713 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_2_OFST 16 11714 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_3_OFST 20 11715 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_4_OFST 24 11716 11717 11718 /***********************************/ 11719 /* MC_CMD_TRIGGER_INTERRUPT 11720 * Trigger an interrupt by prodding the BIU. 11721 */ 11722 #define MC_CMD_TRIGGER_INTERRUPT 0xe3 11723 #undef MC_CMD_0xe3_PRIVILEGE_CTG 11724 11725 #define MC_CMD_0xe3_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11726 11727 /* MC_CMD_TRIGGER_INTERRUPT_IN msgrequest */ 11728 #define MC_CMD_TRIGGER_INTERRUPT_IN_LEN 4 11729 /* Interrupt level relative to base for function. */ 11730 #define MC_CMD_TRIGGER_INTERRUPT_IN_INTR_LEVEL_OFST 0 11731 11732 /* MC_CMD_TRIGGER_INTERRUPT_OUT msgresponse */ 11733 #define MC_CMD_TRIGGER_INTERRUPT_OUT_LEN 0 11734 11735 11736 /***********************************/ 11737 /* MC_CMD_SHMBOOT_OP 11738 * Special operations to support (for now) shmboot. 11739 */ 11740 #define MC_CMD_SHMBOOT_OP 0xe6 11741 #undef MC_CMD_0xe6_PRIVILEGE_CTG 11742 11743 #define MC_CMD_0xe6_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11744 11745 /* MC_CMD_SHMBOOT_OP_IN msgrequest */ 11746 #define MC_CMD_SHMBOOT_OP_IN_LEN 4 11747 /* Identifies the operation to perform */ 11748 #define MC_CMD_SHMBOOT_OP_IN_SHMBOOT_OP_OFST 0 11749 /* enum: Copy slave_data section to the slave core. (Greenport only) */ 11750 #define MC_CMD_SHMBOOT_OP_IN_PUSH_SLAVE_DATA 0x0 11751 11752 /* MC_CMD_SHMBOOT_OP_OUT msgresponse */ 11753 #define MC_CMD_SHMBOOT_OP_OUT_LEN 0 11754 11755 11756 /***********************************/ 11757 /* MC_CMD_CAP_BLK_READ 11758 * Read multiple 64bit words from capture block memory 11759 */ 11760 #define MC_CMD_CAP_BLK_READ 0xe7 11761 #undef MC_CMD_0xe7_PRIVILEGE_CTG 11762 11763 #define MC_CMD_0xe7_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11764 11765 /* MC_CMD_CAP_BLK_READ_IN msgrequest */ 11766 #define MC_CMD_CAP_BLK_READ_IN_LEN 12 11767 #define MC_CMD_CAP_BLK_READ_IN_CAP_REG_OFST 0 11768 #define MC_CMD_CAP_BLK_READ_IN_ADDR_OFST 4 11769 #define MC_CMD_CAP_BLK_READ_IN_COUNT_OFST 8 11770 11771 /* MC_CMD_CAP_BLK_READ_OUT msgresponse */ 11772 #define MC_CMD_CAP_BLK_READ_OUT_LENMIN 8 11773 #define MC_CMD_CAP_BLK_READ_OUT_LENMAX 248 11774 #define MC_CMD_CAP_BLK_READ_OUT_LEN(num) (0+8*(num)) 11775 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_OFST 0 11776 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LEN 8 11777 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LO_OFST 0 11778 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_HI_OFST 4 11779 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_MINNUM 1 11780 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_MAXNUM 31 11781 11782 11783 /***********************************/ 11784 /* MC_CMD_DUMP_DO 11785 * Take a dump of the DUT state 11786 */ 11787 #define MC_CMD_DUMP_DO 0xe8 11788 #undef MC_CMD_0xe8_PRIVILEGE_CTG 11789 11790 #define MC_CMD_0xe8_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11791 11792 /* MC_CMD_DUMP_DO_IN msgrequest */ 11793 #define MC_CMD_DUMP_DO_IN_LEN 52 11794 #define MC_CMD_DUMP_DO_IN_PADDING_OFST 0 11795 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_OFST 4 11796 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM 0x0 /* enum */ 11797 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_DEFAULT 0x1 /* enum */ 11798 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_TYPE_OFST 8 11799 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_NVRAM 0x1 /* enum */ 11800 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_HOST_MEMORY 0x2 /* enum */ 11801 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_HOST_MEMORY_MLI 0x3 /* enum */ 11802 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_UART 0x4 /* enum */ 11803 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 12 11804 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_OFST 16 11805 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 12 11806 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 16 11807 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 12 11808 #define MC_CMD_DUMP_DO_IN_HOST_MEMORY_MLI_PAGE_SIZE 0x1000 /* enum */ 11809 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 16 11810 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 20 11811 #define MC_CMD_DUMP_DO_IN_HOST_MEMORY_MLI_MAX_DEPTH 0x2 /* enum */ 11812 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_OFST 12 11813 /* enum: The uart port this command was received over (if using a uart 11814 * transport) 11815 */ 11816 #define MC_CMD_DUMP_DO_IN_UART_PORT_SRC 0xff 11817 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_SIZE_OFST 24 11818 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_OFST 28 11819 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM 0x0 /* enum */ 11820 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_NVRAM_DUMP_PARTITION 0x1 /* enum */ 11821 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_TYPE_OFST 32 11822 /* Enum values, see field(s): */ 11823 /* MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */ 11824 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 36 11825 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_OFST 40 11826 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 36 11827 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 40 11828 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 36 11829 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 40 11830 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 44 11831 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_UART_PORT_OFST 36 11832 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_SIZE_OFST 48 11833 11834 /* MC_CMD_DUMP_DO_OUT msgresponse */ 11835 #define MC_CMD_DUMP_DO_OUT_LEN 4 11836 #define MC_CMD_DUMP_DO_OUT_DUMPFILE_SIZE_OFST 0 11837 11838 11839 /***********************************/ 11840 /* MC_CMD_DUMP_CONFIGURE_UNSOLICITED 11841 * Configure unsolicited dumps 11842 */ 11843 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED 0xe9 11844 #undef MC_CMD_0xe9_PRIVILEGE_CTG 11845 11846 #define MC_CMD_0xe9_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11847 11848 /* MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN msgrequest */ 11849 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_LEN 52 11850 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_ENABLE_OFST 0 11851 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_OFST 4 11852 /* Enum values, see field(s): */ 11853 /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC */ 11854 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_TYPE_OFST 8 11855 /* Enum values, see field(s): */ 11856 /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */ 11857 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 12 11858 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_OFST 16 11859 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 12 11860 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 16 11861 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 12 11862 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 16 11863 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 20 11864 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_OFST 12 11865 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_SIZE_OFST 24 11866 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_OFST 28 11867 /* Enum values, see field(s): */ 11868 /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPFILE_DST */ 11869 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_TYPE_OFST 32 11870 /* Enum values, see field(s): */ 11871 /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */ 11872 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 36 11873 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_OFST 40 11874 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 36 11875 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 40 11876 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 36 11877 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 40 11878 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 44 11879 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_UART_PORT_OFST 36 11880 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_SIZE_OFST 48 11881 11882 11883 /***********************************/ 11884 /* MC_CMD_SET_PSU 11885 * Adjusts power supply parameters. This is a warranty-voiding operation. 11886 * Returns: ENOENT if the parameter or rail specified does not exist, EINVAL if 11887 * the parameter is out of range. 11888 */ 11889 #define MC_CMD_SET_PSU 0xea 11890 #undef MC_CMD_0xea_PRIVILEGE_CTG 11891 11892 #define MC_CMD_0xea_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11893 11894 /* MC_CMD_SET_PSU_IN msgrequest */ 11895 #define MC_CMD_SET_PSU_IN_LEN 12 11896 #define MC_CMD_SET_PSU_IN_PARAM_OFST 0 11897 #define MC_CMD_SET_PSU_IN_PARAM_SUPPLY_VOLTAGE 0x0 /* enum */ 11898 #define MC_CMD_SET_PSU_IN_RAIL_OFST 4 11899 #define MC_CMD_SET_PSU_IN_RAIL_0V9 0x0 /* enum */ 11900 #define MC_CMD_SET_PSU_IN_RAIL_1V2 0x1 /* enum */ 11901 /* desired value, eg voltage in mV */ 11902 #define MC_CMD_SET_PSU_IN_VALUE_OFST 8 11903 11904 /* MC_CMD_SET_PSU_OUT msgresponse */ 11905 #define MC_CMD_SET_PSU_OUT_LEN 0 11906 11907 11908 /***********************************/ 11909 /* MC_CMD_GET_FUNCTION_INFO 11910 * Get function information. PF and VF number. 11911 */ 11912 #define MC_CMD_GET_FUNCTION_INFO 0xec 11913 #undef MC_CMD_0xec_PRIVILEGE_CTG 11914 11915 #define MC_CMD_0xec_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11916 11917 /* MC_CMD_GET_FUNCTION_INFO_IN msgrequest */ 11918 #define MC_CMD_GET_FUNCTION_INFO_IN_LEN 0 11919 11920 /* MC_CMD_GET_FUNCTION_INFO_OUT msgresponse */ 11921 #define MC_CMD_GET_FUNCTION_INFO_OUT_LEN 8 11922 #define MC_CMD_GET_FUNCTION_INFO_OUT_PF_OFST 0 11923 #define MC_CMD_GET_FUNCTION_INFO_OUT_VF_OFST 4 11924 11925 11926 /***********************************/ 11927 /* MC_CMD_ENABLE_OFFLINE_BIST 11928 * Enters offline BIST mode. All queues are torn down, chip enters quiescent 11929 * mode, calling function gets exclusive MCDI ownership. The only way out is 11930 * reboot. 11931 */ 11932 #define MC_CMD_ENABLE_OFFLINE_BIST 0xed 11933 #undef MC_CMD_0xed_PRIVILEGE_CTG 11934 11935 #define MC_CMD_0xed_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11936 11937 /* MC_CMD_ENABLE_OFFLINE_BIST_IN msgrequest */ 11938 #define MC_CMD_ENABLE_OFFLINE_BIST_IN_LEN 0 11939 11940 /* MC_CMD_ENABLE_OFFLINE_BIST_OUT msgresponse */ 11941 #define MC_CMD_ENABLE_OFFLINE_BIST_OUT_LEN 0 11942 11943 11944 /***********************************/ 11945 /* MC_CMD_UART_SEND_DATA 11946 * Send checksummed[sic] block of data over the uart. Response is a placeholder 11947 * should we wish to make this reliable; currently requests are fire-and- 11948 * forget. 11949 */ 11950 #define MC_CMD_UART_SEND_DATA 0xee 11951 #undef MC_CMD_0xee_PRIVILEGE_CTG 11952 11953 #define MC_CMD_0xee_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11954 11955 /* MC_CMD_UART_SEND_DATA_OUT msgrequest */ 11956 #define MC_CMD_UART_SEND_DATA_OUT_LENMIN 16 11957 #define MC_CMD_UART_SEND_DATA_OUT_LENMAX 252 11958 #define MC_CMD_UART_SEND_DATA_OUT_LEN(num) (16+1*(num)) 11959 /* CRC32 over OFFSET, LENGTH, RESERVED, DATA */ 11960 #define MC_CMD_UART_SEND_DATA_OUT_CHECKSUM_OFST 0 11961 /* Offset at which to write the data */ 11962 #define MC_CMD_UART_SEND_DATA_OUT_OFFSET_OFST 4 11963 /* Length of data */ 11964 #define MC_CMD_UART_SEND_DATA_OUT_LENGTH_OFST 8 11965 /* Reserved for future use */ 11966 #define MC_CMD_UART_SEND_DATA_OUT_RESERVED_OFST 12 11967 #define MC_CMD_UART_SEND_DATA_OUT_DATA_OFST 16 11968 #define MC_CMD_UART_SEND_DATA_OUT_DATA_LEN 1 11969 #define MC_CMD_UART_SEND_DATA_OUT_DATA_MINNUM 0 11970 #define MC_CMD_UART_SEND_DATA_OUT_DATA_MAXNUM 236 11971 11972 /* MC_CMD_UART_SEND_DATA_IN msgresponse */ 11973 #define MC_CMD_UART_SEND_DATA_IN_LEN 0 11974 11975 11976 /***********************************/ 11977 /* MC_CMD_UART_RECV_DATA 11978 * Request checksummed[sic] block of data over the uart. Only a placeholder, 11979 * subject to change and not currently implemented. 11980 */ 11981 #define MC_CMD_UART_RECV_DATA 0xef 11982 #undef MC_CMD_0xef_PRIVILEGE_CTG 11983 11984 #define MC_CMD_0xef_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11985 11986 /* MC_CMD_UART_RECV_DATA_OUT msgrequest */ 11987 #define MC_CMD_UART_RECV_DATA_OUT_LEN 16 11988 /* CRC32 over OFFSET, LENGTH, RESERVED */ 11989 #define MC_CMD_UART_RECV_DATA_OUT_CHECKSUM_OFST 0 11990 /* Offset from which to read the data */ 11991 #define MC_CMD_UART_RECV_DATA_OUT_OFFSET_OFST 4 11992 /* Length of data */ 11993 #define MC_CMD_UART_RECV_DATA_OUT_LENGTH_OFST 8 11994 /* Reserved for future use */ 11995 #define MC_CMD_UART_RECV_DATA_OUT_RESERVED_OFST 12 11996 11997 /* MC_CMD_UART_RECV_DATA_IN msgresponse */ 11998 #define MC_CMD_UART_RECV_DATA_IN_LENMIN 16 11999 #define MC_CMD_UART_RECV_DATA_IN_LENMAX 252 12000 #define MC_CMD_UART_RECV_DATA_IN_LEN(num) (16+1*(num)) 12001 /* CRC32 over RESERVED1, RESERVED2, RESERVED3, DATA */ 12002 #define MC_CMD_UART_RECV_DATA_IN_CHECKSUM_OFST 0 12003 /* Offset at which to write the data */ 12004 #define MC_CMD_UART_RECV_DATA_IN_RESERVED1_OFST 4 12005 /* Length of data */ 12006 #define MC_CMD_UART_RECV_DATA_IN_RESERVED2_OFST 8 12007 /* Reserved for future use */ 12008 #define MC_CMD_UART_RECV_DATA_IN_RESERVED3_OFST 12 12009 #define MC_CMD_UART_RECV_DATA_IN_DATA_OFST 16 12010 #define MC_CMD_UART_RECV_DATA_IN_DATA_LEN 1 12011 #define MC_CMD_UART_RECV_DATA_IN_DATA_MINNUM 0 12012 #define MC_CMD_UART_RECV_DATA_IN_DATA_MAXNUM 236 12013 12014 12015 /***********************************/ 12016 /* MC_CMD_READ_FUSES 12017 * Read data programmed into the device One-Time-Programmable (OTP) Fuses 12018 */ 12019 #define MC_CMD_READ_FUSES 0xf0 12020 #undef MC_CMD_0xf0_PRIVILEGE_CTG 12021 12022 #define MC_CMD_0xf0_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12023 12024 /* MC_CMD_READ_FUSES_IN msgrequest */ 12025 #define MC_CMD_READ_FUSES_IN_LEN 8 12026 /* Offset in OTP to read */ 12027 #define MC_CMD_READ_FUSES_IN_OFFSET_OFST 0 12028 /* Length of data to read in bytes */ 12029 #define MC_CMD_READ_FUSES_IN_LENGTH_OFST 4 12030 12031 /* MC_CMD_READ_FUSES_OUT msgresponse */ 12032 #define MC_CMD_READ_FUSES_OUT_LENMIN 4 12033 #define MC_CMD_READ_FUSES_OUT_LENMAX 252 12034 #define MC_CMD_READ_FUSES_OUT_LEN(num) (4+1*(num)) 12035 /* Length of returned OTP data in bytes */ 12036 #define MC_CMD_READ_FUSES_OUT_LENGTH_OFST 0 12037 /* Returned data */ 12038 #define MC_CMD_READ_FUSES_OUT_DATA_OFST 4 12039 #define MC_CMD_READ_FUSES_OUT_DATA_LEN 1 12040 #define MC_CMD_READ_FUSES_OUT_DATA_MINNUM 0 12041 #define MC_CMD_READ_FUSES_OUT_DATA_MAXNUM 248 12042 12043 12044 /***********************************/ 12045 /* MC_CMD_KR_TUNE 12046 * Get or set KR Serdes RXEQ and TX Driver settings 12047 */ 12048 #define MC_CMD_KR_TUNE 0xf1 12049 #undef MC_CMD_0xf1_PRIVILEGE_CTG 12050 12051 #define MC_CMD_0xf1_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12052 12053 /* MC_CMD_KR_TUNE_IN msgrequest */ 12054 #define MC_CMD_KR_TUNE_IN_LENMIN 4 12055 #define MC_CMD_KR_TUNE_IN_LENMAX 252 12056 #define MC_CMD_KR_TUNE_IN_LEN(num) (4+4*(num)) 12057 /* Requested operation */ 12058 #define MC_CMD_KR_TUNE_IN_KR_TUNE_OP_OFST 0 12059 #define MC_CMD_KR_TUNE_IN_KR_TUNE_OP_LEN 1 12060 /* enum: Get current RXEQ settings */ 12061 #define MC_CMD_KR_TUNE_IN_RXEQ_GET 0x0 12062 /* enum: Override RXEQ settings */ 12063 #define MC_CMD_KR_TUNE_IN_RXEQ_SET 0x1 12064 /* enum: Get current TX Driver settings */ 12065 #define MC_CMD_KR_TUNE_IN_TXEQ_GET 0x2 12066 /* enum: Override TX Driver settings */ 12067 #define MC_CMD_KR_TUNE_IN_TXEQ_SET 0x3 12068 /* enum: Force KR Serdes reset / recalibration */ 12069 #define MC_CMD_KR_TUNE_IN_RECAL 0x4 12070 /* enum: Start KR Serdes Eye diagram plot on a given lane. Lane must have valid 12071 * signal. 12072 */ 12073 #define MC_CMD_KR_TUNE_IN_START_EYE_PLOT 0x5 12074 /* enum: Poll KR Serdes Eye diagram plot. Returns one row of BER data. The 12075 * caller should call this command repeatedly after starting eye plot, until no 12076 * more data is returned. 12077 */ 12078 #define MC_CMD_KR_TUNE_IN_POLL_EYE_PLOT 0x6 12079 /* enum: Read Figure Of Merit (eye quality, higher is better). */ 12080 #define MC_CMD_KR_TUNE_IN_READ_FOM 0x7 12081 /* Align the arguments to 32 bits */ 12082 #define MC_CMD_KR_TUNE_IN_KR_TUNE_RSVD_OFST 1 12083 #define MC_CMD_KR_TUNE_IN_KR_TUNE_RSVD_LEN 3 12084 /* Arguments specific to the operation */ 12085 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_OFST 4 12086 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_LEN 4 12087 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_MINNUM 0 12088 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_MAXNUM 62 12089 12090 /* MC_CMD_KR_TUNE_OUT msgresponse */ 12091 #define MC_CMD_KR_TUNE_OUT_LEN 0 12092 12093 /* MC_CMD_KR_TUNE_RXEQ_GET_IN msgrequest */ 12094 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_LEN 4 12095 /* Requested operation */ 12096 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_OP_OFST 0 12097 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_OP_LEN 1 12098 /* Align the arguments to 32 bits */ 12099 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_RSVD_OFST 1 12100 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_RSVD_LEN 3 12101 12102 /* MC_CMD_KR_TUNE_RXEQ_GET_OUT msgresponse */ 12103 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LENMIN 4 12104 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LENMAX 252 12105 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LEN(num) (0+4*(num)) 12106 /* RXEQ Parameter */ 12107 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_OFST 0 12108 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LEN 4 12109 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_MINNUM 1 12110 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_MAXNUM 63 12111 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_LBN 0 12112 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_WIDTH 8 12113 /* enum: Attenuation (0-15, Huntington) */ 12114 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_ATT 0x0 12115 /* enum: CTLE Boost (0-15, Huntington) */ 12116 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_BOOST 0x1 12117 /* enum: Edge DFE Tap1 (Huntington - 0 - max negative, 64 - zero, 127 - max 12118 * positive, Medford - 0-31) 12119 */ 12120 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP1 0x2 12121 /* enum: Edge DFE Tap2 (Huntington - 0 - max negative, 32 - zero, 63 - max 12122 * positive, Medford - 0-31) 12123 */ 12124 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP2 0x3 12125 /* enum: Edge DFE Tap3 (Huntington - 0 - max negative, 32 - zero, 63 - max 12126 * positive, Medford - 0-16) 12127 */ 12128 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP3 0x4 12129 /* enum: Edge DFE Tap4 (Huntington - 0 - max negative, 32 - zero, 63 - max 12130 * positive, Medford - 0-16) 12131 */ 12132 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP4 0x5 12133 /* enum: Edge DFE Tap5 (Huntington - 0 - max negative, 32 - zero, 63 - max 12134 * positive, Medford - 0-16) 12135 */ 12136 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP5 0x6 12137 /* enum: Edge DFE DLEV (0-128 for Medford) */ 12138 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_DLEV 0x7 12139 /* enum: Variable Gain Amplifier (0-15, Medford) */ 12140 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_VGA 0x8 12141 /* enum: CTLE EQ Capacitor (0-15, Medford) */ 12142 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_EQC 0x9 12143 /* enum: CTLE EQ Resistor (0-7, Medford) */ 12144 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_EQRES 0xa 12145 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_LBN 8 12146 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_WIDTH 3 12147 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */ 12148 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_1 0x1 /* enum */ 12149 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_2 0x2 /* enum */ 12150 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_3 0x3 /* enum */ 12151 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_ALL 0x4 /* enum */ 12152 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_LBN 11 12153 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_WIDTH 1 12154 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_RESERVED_LBN 12 12155 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_RESERVED_WIDTH 4 12156 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_INITIAL_LBN 16 12157 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_INITIAL_WIDTH 8 12158 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_LBN 24 12159 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8 12160 12161 /* MC_CMD_KR_TUNE_RXEQ_SET_IN msgrequest */ 12162 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_LENMIN 8 12163 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_LENMAX 252 12164 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_LEN(num) (4+4*(num)) 12165 /* Requested operation */ 12166 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_OP_OFST 0 12167 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_OP_LEN 1 12168 /* Align the arguments to 32 bits */ 12169 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_RSVD_OFST 1 12170 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_RSVD_LEN 3 12171 /* RXEQ Parameter */ 12172 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_OFST 4 12173 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LEN 4 12174 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_MINNUM 1 12175 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_MAXNUM 62 12176 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_ID_LBN 0 12177 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_ID_WIDTH 8 12178 /* Enum values, see field(s): */ 12179 /* MC_CMD_KR_TUNE_RXEQ_GET_OUT/PARAM_ID */ 12180 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LANE_LBN 8 12181 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LANE_WIDTH 3 12182 /* Enum values, see field(s): */ 12183 /* MC_CMD_KR_TUNE_RXEQ_GET_OUT/PARAM_LANE */ 12184 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_LBN 11 12185 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_WIDTH 1 12186 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED_LBN 12 12187 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED_WIDTH 4 12188 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_INITIAL_LBN 16 12189 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_INITIAL_WIDTH 8 12190 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED2_LBN 24 12191 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED2_WIDTH 8 12192 12193 /* MC_CMD_KR_TUNE_RXEQ_SET_OUT msgresponse */ 12194 #define MC_CMD_KR_TUNE_RXEQ_SET_OUT_LEN 0 12195 12196 /* MC_CMD_KR_TUNE_TXEQ_GET_IN msgrequest */ 12197 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_LEN 4 12198 /* Requested operation */ 12199 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_OP_OFST 0 12200 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_OP_LEN 1 12201 /* Align the arguments to 32 bits */ 12202 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_RSVD_OFST 1 12203 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_RSVD_LEN 3 12204 12205 /* MC_CMD_KR_TUNE_TXEQ_GET_OUT msgresponse */ 12206 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LENMIN 4 12207 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LENMAX 252 12208 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LEN(num) (0+4*(num)) 12209 /* TXEQ Parameter */ 12210 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_OFST 0 12211 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LEN 4 12212 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_MINNUM 1 12213 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_MAXNUM 63 12214 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_LBN 0 12215 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_WIDTH 8 12216 /* enum: TX Amplitude (Huntington, Medford) */ 12217 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV 0x0 12218 /* enum: De-Emphasis Tap1 Magnitude (0-7) (Huntington) */ 12219 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_MODE 0x1 12220 /* enum: De-Emphasis Tap1 Fine */ 12221 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_DTLEV 0x2 12222 /* enum: De-Emphasis Tap2 Magnitude (0-6) (Huntington) */ 12223 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_D2 0x3 12224 /* enum: De-Emphasis Tap2 Fine (Huntington) */ 12225 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_D2TLEV 0x4 12226 /* enum: Pre-Emphasis Magnitude (Huntington) */ 12227 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_E 0x5 12228 /* enum: Pre-Emphasis Fine (Huntington) */ 12229 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_ETLEV 0x6 12230 /* enum: TX Slew Rate Coarse control (Huntington) */ 12231 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_PREDRV_DLY 0x7 12232 /* enum: TX Slew Rate Fine control (Huntington) */ 12233 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_SR_SET 0x8 12234 /* enum: TX Termination Impedance control (Huntington) */ 12235 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_RT_SET 0x9 12236 /* enum: TX Amplitude Fine control (Medford) */ 12237 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV_FINE 0xa 12238 /* enum: Pre-shoot Tap (Medford) */ 12239 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_ADV 0xb 12240 /* enum: De-emphasis Tap (Medford) */ 12241 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_DLY 0xc 12242 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LANE_LBN 8 12243 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LANE_WIDTH 3 12244 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_0 0x0 /* enum */ 12245 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_1 0x1 /* enum */ 12246 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_2 0x2 /* enum */ 12247 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_3 0x3 /* enum */ 12248 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_ALL 0x4 /* enum */ 12249 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED_LBN 11 12250 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED_WIDTH 5 12251 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_INITIAL_LBN 16 12252 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_INITIAL_WIDTH 8 12253 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED2_LBN 24 12254 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED2_WIDTH 8 12255 12256 /* MC_CMD_KR_TUNE_TXEQ_SET_IN msgrequest */ 12257 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_LENMIN 8 12258 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_LENMAX 252 12259 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_LEN(num) (4+4*(num)) 12260 /* Requested operation */ 12261 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_OP_OFST 0 12262 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_OP_LEN 1 12263 /* Align the arguments to 32 bits */ 12264 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_RSVD_OFST 1 12265 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_RSVD_LEN 3 12266 /* TXEQ Parameter */ 12267 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_OFST 4 12268 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LEN 4 12269 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_MINNUM 1 12270 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_MAXNUM 62 12271 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_ID_LBN 0 12272 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_ID_WIDTH 8 12273 /* Enum values, see field(s): */ 12274 /* MC_CMD_KR_TUNE_TXEQ_GET_OUT/PARAM_ID */ 12275 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LANE_LBN 8 12276 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LANE_WIDTH 3 12277 /* Enum values, see field(s): */ 12278 /* MC_CMD_KR_TUNE_TXEQ_GET_OUT/PARAM_LANE */ 12279 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED_LBN 11 12280 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED_WIDTH 5 12281 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_INITIAL_LBN 16 12282 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_INITIAL_WIDTH 8 12283 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED2_LBN 24 12284 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED2_WIDTH 8 12285 12286 /* MC_CMD_KR_TUNE_TXEQ_SET_OUT msgresponse */ 12287 #define MC_CMD_KR_TUNE_TXEQ_SET_OUT_LEN 0 12288 12289 /* MC_CMD_KR_TUNE_RECAL_IN msgrequest */ 12290 #define MC_CMD_KR_TUNE_RECAL_IN_LEN 4 12291 /* Requested operation */ 12292 #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_OP_OFST 0 12293 #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_OP_LEN 1 12294 /* Align the arguments to 32 bits */ 12295 #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_RSVD_OFST 1 12296 #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_RSVD_LEN 3 12297 12298 /* MC_CMD_KR_TUNE_RECAL_OUT msgresponse */ 12299 #define MC_CMD_KR_TUNE_RECAL_OUT_LEN 0 12300 12301 /* MC_CMD_KR_TUNE_START_EYE_PLOT_IN msgrequest */ 12302 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_LEN 8 12303 /* Requested operation */ 12304 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_OP_OFST 0 12305 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_OP_LEN 1 12306 /* Align the arguments to 32 bits */ 12307 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_RSVD_OFST 1 12308 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_RSVD_LEN 3 12309 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_LANE_OFST 4 12310 12311 /* MC_CMD_KR_TUNE_START_EYE_PLOT_OUT msgresponse */ 12312 #define MC_CMD_KR_TUNE_START_EYE_PLOT_OUT_LEN 0 12313 12314 /* MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN msgrequest */ 12315 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_LEN 4 12316 /* Requested operation */ 12317 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_OP_OFST 0 12318 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_OP_LEN 1 12319 /* Align the arguments to 32 bits */ 12320 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_RSVD_OFST 1 12321 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_RSVD_LEN 3 12322 12323 /* MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT msgresponse */ 12324 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LENMIN 0 12325 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LENMAX 252 12326 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LEN(num) (0+2*(num)) 12327 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_OFST 0 12328 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_LEN 2 12329 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MINNUM 0 12330 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MAXNUM 126 12331 12332 /* MC_CMD_KR_TUNE_READ_FOM_IN msgrequest */ 12333 #define MC_CMD_KR_TUNE_READ_FOM_IN_LEN 8 12334 /* Requested operation */ 12335 #define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_OP_OFST 0 12336 #define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_OP_LEN 1 12337 /* Align the arguments to 32 bits */ 12338 #define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_RSVD_OFST 1 12339 #define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_RSVD_LEN 3 12340 #define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_OFST 4 12341 12342 /* MC_CMD_KR_TUNE_READ_FOM_OUT msgresponse */ 12343 #define MC_CMD_KR_TUNE_READ_FOM_OUT_LEN 4 12344 #define MC_CMD_KR_TUNE_READ_FOM_OUT_FOM_OFST 0 12345 12346 12347 /***********************************/ 12348 /* MC_CMD_PCIE_TUNE 12349 * Get or set PCIE Serdes RXEQ and TX Driver settings 12350 */ 12351 #define MC_CMD_PCIE_TUNE 0xf2 12352 #undef MC_CMD_0xf2_PRIVILEGE_CTG 12353 12354 #define MC_CMD_0xf2_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12355 12356 /* MC_CMD_PCIE_TUNE_IN msgrequest */ 12357 #define MC_CMD_PCIE_TUNE_IN_LENMIN 4 12358 #define MC_CMD_PCIE_TUNE_IN_LENMAX 252 12359 #define MC_CMD_PCIE_TUNE_IN_LEN(num) (4+4*(num)) 12360 /* Requested operation */ 12361 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_OP_OFST 0 12362 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_OP_LEN 1 12363 /* enum: Get current RXEQ settings */ 12364 #define MC_CMD_PCIE_TUNE_IN_RXEQ_GET 0x0 12365 /* enum: Override RXEQ settings */ 12366 #define MC_CMD_PCIE_TUNE_IN_RXEQ_SET 0x1 12367 /* enum: Get current TX Driver settings */ 12368 #define MC_CMD_PCIE_TUNE_IN_TXEQ_GET 0x2 12369 /* enum: Override TX Driver settings */ 12370 #define MC_CMD_PCIE_TUNE_IN_TXEQ_SET 0x3 12371 /* enum: Start PCIe Serdes Eye diagram plot on a given lane. */ 12372 #define MC_CMD_PCIE_TUNE_IN_START_EYE_PLOT 0x5 12373 /* enum: Poll PCIe Serdes Eye diagram plot. Returns one row of BER data. The 12374 * caller should call this command repeatedly after starting eye plot, until no 12375 * more data is returned. 12376 */ 12377 #define MC_CMD_PCIE_TUNE_IN_POLL_EYE_PLOT 0x6 12378 /* Align the arguments to 32 bits */ 12379 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_RSVD_OFST 1 12380 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_RSVD_LEN 3 12381 /* Arguments specific to the operation */ 12382 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_OFST 4 12383 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_LEN 4 12384 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_MINNUM 0 12385 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_MAXNUM 62 12386 12387 /* MC_CMD_PCIE_TUNE_OUT msgresponse */ 12388 #define MC_CMD_PCIE_TUNE_OUT_LEN 0 12389 12390 /* MC_CMD_PCIE_TUNE_RXEQ_GET_IN msgrequest */ 12391 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_LEN 4 12392 /* Requested operation */ 12393 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_OP_OFST 0 12394 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_OP_LEN 1 12395 /* Align the arguments to 32 bits */ 12396 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_RSVD_OFST 1 12397 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_RSVD_LEN 3 12398 12399 /* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT msgresponse */ 12400 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LENMIN 4 12401 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LENMAX 252 12402 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LEN(num) (0+4*(num)) 12403 /* RXEQ Parameter */ 12404 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_OFST 0 12405 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LEN 4 12406 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_MINNUM 1 12407 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_MAXNUM 63 12408 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_ID_LBN 0 12409 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_ID_WIDTH 8 12410 /* enum: Attenuation (0-15) */ 12411 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_ATT 0x0 12412 /* enum: CTLE Boost (0-15) */ 12413 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_BOOST 0x1 12414 /* enum: DFE Tap1 (0 - max negative, 64 - zero, 127 - max positive) */ 12415 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP1 0x2 12416 /* enum: DFE Tap2 (0 - max negative, 32 - zero, 63 - max positive) */ 12417 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP2 0x3 12418 /* enum: DFE Tap3 (0 - max negative, 32 - zero, 63 - max positive) */ 12419 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP3 0x4 12420 /* enum: DFE Tap4 (0 - max negative, 32 - zero, 63 - max positive) */ 12421 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP4 0x5 12422 /* enum: DFE Tap5 (0 - max negative, 32 - zero, 63 - max positive) */ 12423 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP5 0x6 12424 /* enum: DFE DLev */ 12425 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_DLEV 0x7 12426 /* enum: Figure of Merit */ 12427 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_FOM 0x8 12428 /* enum: CTLE EQ Capacitor (HF Gain) */ 12429 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_CTLE_EQC 0x9 12430 /* enum: CTLE EQ Resistor (DC Gain) */ 12431 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_CTLE_EQRES 0xa 12432 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_LBN 8 12433 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_WIDTH 5 12434 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */ 12435 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_1 0x1 /* enum */ 12436 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_2 0x2 /* enum */ 12437 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_3 0x3 /* enum */ 12438 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_4 0x4 /* enum */ 12439 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_5 0x5 /* enum */ 12440 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_6 0x6 /* enum */ 12441 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_7 0x7 /* enum */ 12442 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_8 0x8 /* enum */ 12443 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_9 0x9 /* enum */ 12444 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_10 0xa /* enum */ 12445 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_11 0xb /* enum */ 12446 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_12 0xc /* enum */ 12447 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_13 0xd /* enum */ 12448 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_14 0xe /* enum */ 12449 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_15 0xf /* enum */ 12450 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_ALL 0x10 /* enum */ 12451 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_LBN 13 12452 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_WIDTH 1 12453 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_LBN 14 12454 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_WIDTH 10 12455 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_LBN 24 12456 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8 12457 12458 /* MC_CMD_PCIE_TUNE_RXEQ_SET_IN msgrequest */ 12459 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LENMIN 8 12460 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LENMAX 252 12461 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LEN(num) (4+4*(num)) 12462 /* Requested operation */ 12463 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_OP_OFST 0 12464 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_OP_LEN 1 12465 /* Align the arguments to 32 bits */ 12466 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_RSVD_OFST 1 12467 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_RSVD_LEN 3 12468 /* RXEQ Parameter */ 12469 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_OFST 4 12470 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LEN 4 12471 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_MINNUM 1 12472 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_MAXNUM 62 12473 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_ID_LBN 0 12474 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_ID_WIDTH 8 12475 /* Enum values, see field(s): */ 12476 /* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_ID */ 12477 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LANE_LBN 8 12478 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LANE_WIDTH 5 12479 /* Enum values, see field(s): */ 12480 /* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_LANE */ 12481 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_LBN 13 12482 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_WIDTH 1 12483 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED_LBN 14 12484 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED_WIDTH 2 12485 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_INITIAL_LBN 16 12486 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_INITIAL_WIDTH 8 12487 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED2_LBN 24 12488 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED2_WIDTH 8 12489 12490 /* MC_CMD_PCIE_TUNE_RXEQ_SET_OUT msgresponse */ 12491 #define MC_CMD_PCIE_TUNE_RXEQ_SET_OUT_LEN 0 12492 12493 /* MC_CMD_PCIE_TUNE_TXEQ_GET_IN msgrequest */ 12494 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_LEN 4 12495 /* Requested operation */ 12496 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_OP_OFST 0 12497 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_OP_LEN 1 12498 /* Align the arguments to 32 bits */ 12499 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_RSVD_OFST 1 12500 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_RSVD_LEN 3 12501 12502 /* MC_CMD_PCIE_TUNE_TXEQ_GET_OUT msgresponse */ 12503 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LENMIN 4 12504 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LENMAX 252 12505 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LEN(num) (0+4*(num)) 12506 /* RXEQ Parameter */ 12507 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_OFST 0 12508 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LEN 4 12509 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_MINNUM 1 12510 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_MAXNUM 63 12511 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_ID_LBN 0 12512 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_ID_WIDTH 8 12513 /* enum: TxMargin (PIPE) */ 12514 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_TXMARGIN 0x0 12515 /* enum: TxSwing (PIPE) */ 12516 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_TXSWING 0x1 12517 /* enum: De-emphasis coefficient C(-1) (PIPE) */ 12518 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_CM1 0x2 12519 /* enum: De-emphasis coefficient C(0) (PIPE) */ 12520 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_C0 0x3 12521 /* enum: De-emphasis coefficient C(+1) (PIPE) */ 12522 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_CP1 0x4 12523 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LANE_LBN 8 12524 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LANE_WIDTH 4 12525 /* Enum values, see field(s): */ 12526 /* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_LANE */ 12527 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_RESERVED_LBN 12 12528 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_RESERVED_WIDTH 12 12529 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_CURRENT_LBN 24 12530 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8 12531 12532 /* MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN msgrequest */ 12533 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_LEN 8 12534 /* Requested operation */ 12535 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_OP_OFST 0 12536 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_OP_LEN 1 12537 /* Align the arguments to 32 bits */ 12538 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_RSVD_OFST 1 12539 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_RSVD_LEN 3 12540 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_LANE_OFST 4 12541 12542 /* MC_CMD_PCIE_TUNE_START_EYE_PLOT_OUT msgresponse */ 12543 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_OUT_LEN 0 12544 12545 /* MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN msgrequest */ 12546 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_LEN 4 12547 /* Requested operation */ 12548 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_OP_OFST 0 12549 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_OP_LEN 1 12550 /* Align the arguments to 32 bits */ 12551 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_RSVD_OFST 1 12552 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_RSVD_LEN 3 12553 12554 /* MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT msgresponse */ 12555 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LENMIN 0 12556 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LENMAX 252 12557 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LEN(num) (0+2*(num)) 12558 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_OFST 0 12559 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_LEN 2 12560 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MINNUM 0 12561 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MAXNUM 126 12562 12563 12564 /***********************************/ 12565 /* MC_CMD_LICENSING 12566 * Operations on the NVRAM_PARTITION_TYPE_LICENSE application license partition 12567 * - not used for V3 licensing 12568 */ 12569 #define MC_CMD_LICENSING 0xf3 12570 #undef MC_CMD_0xf3_PRIVILEGE_CTG 12571 12572 #define MC_CMD_0xf3_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12573 12574 /* MC_CMD_LICENSING_IN msgrequest */ 12575 #define MC_CMD_LICENSING_IN_LEN 4 12576 /* identifies the type of operation requested */ 12577 #define MC_CMD_LICENSING_IN_OP_OFST 0 12578 /* enum: re-read and apply licenses after a license key partition update; note 12579 * that this operation returns a zero-length response 12580 */ 12581 #define MC_CMD_LICENSING_IN_OP_UPDATE_LICENSE 0x0 12582 /* enum: report counts of installed licenses */ 12583 #define MC_CMD_LICENSING_IN_OP_GET_KEY_STATS 0x1 12584 12585 /* MC_CMD_LICENSING_OUT msgresponse */ 12586 #define MC_CMD_LICENSING_OUT_LEN 28 12587 /* count of application keys which are valid */ 12588 #define MC_CMD_LICENSING_OUT_VALID_APP_KEYS_OFST 0 12589 /* sum of UNVERIFIABLE_APP_KEYS + WRONG_NODE_APP_KEYS (for compatibility with 12590 * MC_CMD_FC_OP_LICENSE) 12591 */ 12592 #define MC_CMD_LICENSING_OUT_INVALID_APP_KEYS_OFST 4 12593 /* count of application keys which are invalid due to being blacklisted */ 12594 #define MC_CMD_LICENSING_OUT_BLACKLISTED_APP_KEYS_OFST 8 12595 /* count of application keys which are invalid due to being unverifiable */ 12596 #define MC_CMD_LICENSING_OUT_UNVERIFIABLE_APP_KEYS_OFST 12 12597 /* count of application keys which are invalid due to being for the wrong node 12598 */ 12599 #define MC_CMD_LICENSING_OUT_WRONG_NODE_APP_KEYS_OFST 16 12600 /* licensing state (for diagnostics; the exact meaning of the bits in this 12601 * field are private to the firmware) 12602 */ 12603 #define MC_CMD_LICENSING_OUT_LICENSING_STATE_OFST 20 12604 /* licensing subsystem self-test report (for manftest) */ 12605 #define MC_CMD_LICENSING_OUT_LICENSING_SELF_TEST_OFST 24 12606 /* enum: licensing subsystem self-test failed */ 12607 #define MC_CMD_LICENSING_OUT_SELF_TEST_FAIL 0x0 12608 /* enum: licensing subsystem self-test passed */ 12609 #define MC_CMD_LICENSING_OUT_SELF_TEST_PASS 0x1 12610 12611 12612 /***********************************/ 12613 /* MC_CMD_LICENSING_V3 12614 * Operations on the NVRAM_PARTITION_TYPE_LICENSE application license partition 12615 * - V3 licensing (Medford) 12616 */ 12617 #define MC_CMD_LICENSING_V3 0xd0 12618 #undef MC_CMD_0xd0_PRIVILEGE_CTG 12619 12620 #define MC_CMD_0xd0_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12621 12622 /* MC_CMD_LICENSING_V3_IN msgrequest */ 12623 #define MC_CMD_LICENSING_V3_IN_LEN 4 12624 /* identifies the type of operation requested */ 12625 #define MC_CMD_LICENSING_V3_IN_OP_OFST 0 12626 /* enum: re-read and apply licenses after a license key partition update; note 12627 * that this operation returns a zero-length response 12628 */ 12629 #define MC_CMD_LICENSING_V3_IN_OP_UPDATE_LICENSE 0x0 12630 /* enum: report counts of installed licenses */ 12631 #define MC_CMD_LICENSING_V3_IN_OP_REPORT_LICENSE 0x1 12632 12633 /* MC_CMD_LICENSING_V3_OUT msgresponse */ 12634 #define MC_CMD_LICENSING_V3_OUT_LEN 88 12635 /* count of keys which are valid */ 12636 #define MC_CMD_LICENSING_V3_OUT_VALID_KEYS_OFST 0 12637 /* sum of UNVERIFIABLE_KEYS + WRONG_NODE_KEYS (for compatibility with 12638 * MC_CMD_FC_OP_LICENSE) 12639 */ 12640 #define MC_CMD_LICENSING_V3_OUT_INVALID_KEYS_OFST 4 12641 /* count of keys which are invalid due to being unverifiable */ 12642 #define MC_CMD_LICENSING_V3_OUT_UNVERIFIABLE_KEYS_OFST 8 12643 /* count of keys which are invalid due to being for the wrong node */ 12644 #define MC_CMD_LICENSING_V3_OUT_WRONG_NODE_KEYS_OFST 12 12645 /* licensing state (for diagnostics; the exact meaning of the bits in this 12646 * field are private to the firmware) 12647 */ 12648 #define MC_CMD_LICENSING_V3_OUT_LICENSING_STATE_OFST 16 12649 /* licensing subsystem self-test report (for manftest) */ 12650 #define MC_CMD_LICENSING_V3_OUT_LICENSING_SELF_TEST_OFST 20 12651 /* enum: licensing subsystem self-test failed */ 12652 #define MC_CMD_LICENSING_V3_OUT_SELF_TEST_FAIL 0x0 12653 /* enum: licensing subsystem self-test passed */ 12654 #define MC_CMD_LICENSING_V3_OUT_SELF_TEST_PASS 0x1 12655 /* bitmask of licensed applications */ 12656 #define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_OFST 24 12657 #define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LEN 8 12658 #define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LO_OFST 24 12659 #define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_HI_OFST 28 12660 /* reserved for future use */ 12661 #define MC_CMD_LICENSING_V3_OUT_RESERVED_0_OFST 32 12662 #define MC_CMD_LICENSING_V3_OUT_RESERVED_0_LEN 24 12663 /* bitmask of licensed features */ 12664 #define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_OFST 56 12665 #define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LEN 8 12666 #define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LO_OFST 56 12667 #define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_HI_OFST 60 12668 /* reserved for future use */ 12669 #define MC_CMD_LICENSING_V3_OUT_RESERVED_1_OFST 64 12670 #define MC_CMD_LICENSING_V3_OUT_RESERVED_1_LEN 24 12671 12672 12673 /***********************************/ 12674 /* MC_CMD_LICENSING_GET_ID_V3 12675 * Get ID and type from the NVRAM_PARTITION_TYPE_LICENSE application license 12676 * partition - V3 licensing (Medford) 12677 */ 12678 #define MC_CMD_LICENSING_GET_ID_V3 0xd1 12679 #undef MC_CMD_0xd1_PRIVILEGE_CTG 12680 12681 #define MC_CMD_0xd1_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12682 12683 /* MC_CMD_LICENSING_GET_ID_V3_IN msgrequest */ 12684 #define MC_CMD_LICENSING_GET_ID_V3_IN_LEN 0 12685 12686 /* MC_CMD_LICENSING_GET_ID_V3_OUT msgresponse */ 12687 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LENMIN 8 12688 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LENMAX 252 12689 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LEN(num) (8+1*(num)) 12690 /* type of license (eg 3) */ 12691 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_TYPE_OFST 0 12692 /* length of the license ID (in bytes) */ 12693 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_LENGTH_OFST 4 12694 /* the unique license ID of the adapter */ 12695 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_OFST 8 12696 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_LEN 1 12697 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_MINNUM 0 12698 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_MAXNUM 244 12699 12700 12701 /***********************************/ 12702 /* MC_CMD_MC2MC_PROXY 12703 * Execute an arbitrary MCDI command on the slave MC of a dual-core device. 12704 * This will fail on a single-core system. 12705 */ 12706 #define MC_CMD_MC2MC_PROXY 0xf4 12707 #undef MC_CMD_0xf4_PRIVILEGE_CTG 12708 12709 #define MC_CMD_0xf4_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12710 12711 /* MC_CMD_MC2MC_PROXY_IN msgrequest */ 12712 #define MC_CMD_MC2MC_PROXY_IN_LEN 0 12713 12714 /* MC_CMD_MC2MC_PROXY_OUT msgresponse */ 12715 #define MC_CMD_MC2MC_PROXY_OUT_LEN 0 12716 12717 12718 /***********************************/ 12719 /* MC_CMD_GET_LICENSED_APP_STATE 12720 * Query the state of an individual licensed application. (Note that the actual 12721 * state may be invalidated by the MC_CMD_LICENSING OP_UPDATE_LICENSE operation 12722 * or a reboot of the MC.) Not used for V3 licensing 12723 */ 12724 #define MC_CMD_GET_LICENSED_APP_STATE 0xf5 12725 #undef MC_CMD_0xf5_PRIVILEGE_CTG 12726 12727 #define MC_CMD_0xf5_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12728 12729 /* MC_CMD_GET_LICENSED_APP_STATE_IN msgrequest */ 12730 #define MC_CMD_GET_LICENSED_APP_STATE_IN_LEN 4 12731 /* application ID to query (LICENSED_APP_ID_xxx) */ 12732 #define MC_CMD_GET_LICENSED_APP_STATE_IN_APP_ID_OFST 0 12733 12734 /* MC_CMD_GET_LICENSED_APP_STATE_OUT msgresponse */ 12735 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_LEN 4 12736 /* state of this application */ 12737 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_STATE_OFST 0 12738 /* enum: no (or invalid) license is present for the application */ 12739 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_NOT_LICENSED 0x0 12740 /* enum: a valid license is present for the application */ 12741 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_LICENSED 0x1 12742 12743 12744 /***********************************/ 12745 /* MC_CMD_GET_LICENSED_V3_APP_STATE 12746 * Query the state of an individual licensed application. (Note that the actual 12747 * state may be invalidated by the MC_CMD_LICENSING_V3 OP_UPDATE_LICENSE 12748 * operation or a reboot of the MC.) Used for V3 licensing (Medford) 12749 */ 12750 #define MC_CMD_GET_LICENSED_V3_APP_STATE 0xd2 12751 #undef MC_CMD_0xd2_PRIVILEGE_CTG 12752 12753 #define MC_CMD_0xd2_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12754 12755 /* MC_CMD_GET_LICENSED_V3_APP_STATE_IN msgrequest */ 12756 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_LEN 8 12757 /* application ID to query (LICENSED_V3_APPS_xxx) expressed as a single bit 12758 * mask 12759 */ 12760 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_OFST 0 12761 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LEN 8 12762 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LO_OFST 0 12763 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_HI_OFST 4 12764 12765 /* MC_CMD_GET_LICENSED_V3_APP_STATE_OUT msgresponse */ 12766 #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_LEN 4 12767 /* state of this application */ 12768 #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_STATE_OFST 0 12769 /* enum: no (or invalid) license is present for the application */ 12770 #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_NOT_LICENSED 0x0 12771 /* enum: a valid license is present for the application */ 12772 #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_LICENSED 0x1 12773 12774 12775 /***********************************/ 12776 /* MC_CMD_GET_LICENSED_V3_FEATURE_STATES 12777 * Query the state of an one or more licensed features. (Note that the actual 12778 * state may be invalidated by the MC_CMD_LICENSING_V3 OP_UPDATE_LICENSE 12779 * operation or a reboot of the MC.) Used for V3 licensing (Medford) 12780 */ 12781 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES 0xd3 12782 #undef MC_CMD_0xd3_PRIVILEGE_CTG 12783 12784 #define MC_CMD_0xd3_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12785 12786 /* MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN msgrequest */ 12787 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_LEN 8 12788 /* features to query (LICENSED_V3_FEATURES_xxx) expressed as a mask with one or 12789 * more bits set 12790 */ 12791 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_OFST 0 12792 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LEN 8 12793 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LO_OFST 0 12794 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_HI_OFST 4 12795 12796 /* MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT msgresponse */ 12797 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_LEN 8 12798 /* states of these features - bit set for licensed, clear for not licensed */ 12799 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_OFST 0 12800 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LEN 8 12801 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LO_OFST 0 12802 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_HI_OFST 4 12803 12804 12805 /***********************************/ 12806 /* MC_CMD_LICENSED_APP_OP 12807 * Perform an action for an individual licensed application - not used for V3 12808 * licensing. 12809 */ 12810 #define MC_CMD_LICENSED_APP_OP 0xf6 12811 #undef MC_CMD_0xf6_PRIVILEGE_CTG 12812 12813 #define MC_CMD_0xf6_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12814 12815 /* MC_CMD_LICENSED_APP_OP_IN msgrequest */ 12816 #define MC_CMD_LICENSED_APP_OP_IN_LENMIN 8 12817 #define MC_CMD_LICENSED_APP_OP_IN_LENMAX 252 12818 #define MC_CMD_LICENSED_APP_OP_IN_LEN(num) (8+4*(num)) 12819 /* application ID */ 12820 #define MC_CMD_LICENSED_APP_OP_IN_APP_ID_OFST 0 12821 /* the type of operation requested */ 12822 #define MC_CMD_LICENSED_APP_OP_IN_OP_OFST 4 12823 /* enum: validate application */ 12824 #define MC_CMD_LICENSED_APP_OP_IN_OP_VALIDATE 0x0 12825 /* enum: mask application */ 12826 #define MC_CMD_LICENSED_APP_OP_IN_OP_MASK 0x1 12827 /* arguments specific to this particular operation */ 12828 #define MC_CMD_LICENSED_APP_OP_IN_ARGS_OFST 8 12829 #define MC_CMD_LICENSED_APP_OP_IN_ARGS_LEN 4 12830 #define MC_CMD_LICENSED_APP_OP_IN_ARGS_MINNUM 0 12831 #define MC_CMD_LICENSED_APP_OP_IN_ARGS_MAXNUM 61 12832 12833 /* MC_CMD_LICENSED_APP_OP_OUT msgresponse */ 12834 #define MC_CMD_LICENSED_APP_OP_OUT_LENMIN 0 12835 #define MC_CMD_LICENSED_APP_OP_OUT_LENMAX 252 12836 #define MC_CMD_LICENSED_APP_OP_OUT_LEN(num) (0+4*(num)) 12837 /* result specific to this particular operation */ 12838 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_OFST 0 12839 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_LEN 4 12840 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_MINNUM 0 12841 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_MAXNUM 63 12842 12843 /* MC_CMD_LICENSED_APP_OP_VALIDATE_IN msgrequest */ 12844 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_LEN 72 12845 /* application ID */ 12846 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_APP_ID_OFST 0 12847 /* the type of operation requested */ 12848 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_OP_OFST 4 12849 /* validation challenge */ 12850 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_CHALLENGE_OFST 8 12851 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_CHALLENGE_LEN 64 12852 12853 /* MC_CMD_LICENSED_APP_OP_VALIDATE_OUT msgresponse */ 12854 #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_LEN 68 12855 /* feature expiry (time_t) */ 12856 #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_EXPIRY_OFST 0 12857 /* validation response */ 12858 #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_RESPONSE_OFST 4 12859 #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_RESPONSE_LEN 64 12860 12861 /* MC_CMD_LICENSED_APP_OP_MASK_IN msgrequest */ 12862 #define MC_CMD_LICENSED_APP_OP_MASK_IN_LEN 12 12863 /* application ID */ 12864 #define MC_CMD_LICENSED_APP_OP_MASK_IN_APP_ID_OFST 0 12865 /* the type of operation requested */ 12866 #define MC_CMD_LICENSED_APP_OP_MASK_IN_OP_OFST 4 12867 /* flag */ 12868 #define MC_CMD_LICENSED_APP_OP_MASK_IN_FLAG_OFST 8 12869 12870 /* MC_CMD_LICENSED_APP_OP_MASK_OUT msgresponse */ 12871 #define MC_CMD_LICENSED_APP_OP_MASK_OUT_LEN 0 12872 12873 12874 /***********************************/ 12875 /* MC_CMD_LICENSED_V3_VALIDATE_APP 12876 * Perform validation for an individual licensed application - V3 licensing 12877 * (Medford) 12878 */ 12879 #define MC_CMD_LICENSED_V3_VALIDATE_APP 0xd4 12880 #undef MC_CMD_0xd4_PRIVILEGE_CTG 12881 12882 #define MC_CMD_0xd4_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12883 12884 /* MC_CMD_LICENSED_V3_VALIDATE_APP_IN msgrequest */ 12885 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_LEN 72 12886 /* application ID expressed as a single bit mask */ 12887 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_OFST 0 12888 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LEN 8 12889 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LO_OFST 0 12890 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_HI_OFST 4 12891 /* challenge for validation */ 12892 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_CHALLENGE_OFST 8 12893 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_CHALLENGE_LEN 64 12894 12895 /* MC_CMD_LICENSED_V3_VALIDATE_APP_OUT msgresponse */ 12896 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_LEN 72 12897 /* application expiry time */ 12898 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_TIME_OFST 0 12899 /* application expiry units */ 12900 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNITS_OFST 4 12901 /* enum: expiry units are accounting units */ 12902 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNIT_ACC 0x0 12903 /* enum: expiry units are calendar days */ 12904 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNIT_DAYS 0x1 12905 /* validation response to challenge */ 12906 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_RESPONSE_OFST 8 12907 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_RESPONSE_LEN 64 12908 12909 12910 /***********************************/ 12911 /* MC_CMD_LICENSED_V3_MASK_FEATURES 12912 * Mask features - V3 licensing (Medford) 12913 */ 12914 #define MC_CMD_LICENSED_V3_MASK_FEATURES 0xd5 12915 #undef MC_CMD_0xd5_PRIVILEGE_CTG 12916 12917 #define MC_CMD_0xd5_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12918 12919 /* MC_CMD_LICENSED_V3_MASK_FEATURES_IN msgrequest */ 12920 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_LEN 12 12921 /* mask to be applied to features to be changed */ 12922 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_OFST 0 12923 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LEN 8 12924 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LO_OFST 0 12925 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_HI_OFST 4 12926 /* whether to turn on or turn off the masked features */ 12927 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_FLAG_OFST 8 12928 /* enum: turn the features off */ 12929 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_OFF 0x0 12930 /* enum: turn the features back on */ 12931 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_ON 0x1 12932 12933 /* MC_CMD_LICENSED_V3_MASK_FEATURES_OUT msgresponse */ 12934 #define MC_CMD_LICENSED_V3_MASK_FEATURES_OUT_LEN 0 12935 12936 12937 /***********************************/ 12938 /* MC_CMD_SET_PORT_SNIFF_CONFIG 12939 * Configure RX port sniffing for the physical port associated with the calling 12940 * function. Only a privileged function may change the port sniffing 12941 * configuration. A copy of all traffic delivered to the host (non-promiscuous 12942 * mode) or all traffic arriving at the port (promiscuous mode) may be 12943 * delivered to a specific queue, or a set of queues with RSS. 12944 */ 12945 #define MC_CMD_SET_PORT_SNIFF_CONFIG 0xf7 12946 #undef MC_CMD_0xf7_PRIVILEGE_CTG 12947 12948 #define MC_CMD_0xf7_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12949 12950 /* MC_CMD_SET_PORT_SNIFF_CONFIG_IN msgrequest */ 12951 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_LEN 16 12952 /* configuration flags */ 12953 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_FLAGS_OFST 0 12954 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_ENABLE_LBN 0 12955 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_ENABLE_WIDTH 1 12956 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_PROMISCUOUS_LBN 1 12957 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_PROMISCUOUS_WIDTH 1 12958 /* receive queue handle (for RSS mode, this is the base queue) */ 12959 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_QUEUE_OFST 4 12960 /* receive mode */ 12961 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_OFST 8 12962 /* enum: receive to just the specified queue */ 12963 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_SIMPLE 0x0 12964 /* enum: receive to multiple queues using RSS context */ 12965 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_RSS 0x1 12966 /* RSS context (for RX_MODE_RSS) as returned by MC_CMD_RSS_CONTEXT_ALLOC. Note 12967 * that these handles should be considered opaque to the host, although a value 12968 * of 0xFFFFFFFF is guaranteed never to be a valid handle. 12969 */ 12970 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_OFST 12 12971 12972 /* MC_CMD_SET_PORT_SNIFF_CONFIG_OUT msgresponse */ 12973 #define MC_CMD_SET_PORT_SNIFF_CONFIG_OUT_LEN 0 12974 12975 12976 /***********************************/ 12977 /* MC_CMD_GET_PORT_SNIFF_CONFIG 12978 * Obtain the current RX port sniffing configuration for the physical port 12979 * associated with the calling function. Only a privileged function may read 12980 * the configuration. 12981 */ 12982 #define MC_CMD_GET_PORT_SNIFF_CONFIG 0xf8 12983 #undef MC_CMD_0xf8_PRIVILEGE_CTG 12984 12985 #define MC_CMD_0xf8_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12986 12987 /* MC_CMD_GET_PORT_SNIFF_CONFIG_IN msgrequest */ 12988 #define MC_CMD_GET_PORT_SNIFF_CONFIG_IN_LEN 0 12989 12990 /* MC_CMD_GET_PORT_SNIFF_CONFIG_OUT msgresponse */ 12991 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_LEN 16 12992 /* configuration flags */ 12993 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_FLAGS_OFST 0 12994 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_ENABLE_LBN 0 12995 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_ENABLE_WIDTH 1 12996 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_PROMISCUOUS_LBN 1 12997 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_PROMISCUOUS_WIDTH 1 12998 /* receiving queue handle (for RSS mode, this is the base queue) */ 12999 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_OFST 4 13000 /* receive mode */ 13001 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_OFST 8 13002 /* enum: receiving to just the specified queue */ 13003 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_SIMPLE 0x0 13004 /* enum: receiving to multiple queues using RSS context */ 13005 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_RSS 0x1 13006 /* RSS context (for RX_MODE_RSS) */ 13007 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_OFST 12 13008 13009 13010 /***********************************/ 13011 /* MC_CMD_SET_PARSER_DISP_CONFIG 13012 * Change configuration related to the parser-dispatcher subsystem. 13013 */ 13014 #define MC_CMD_SET_PARSER_DISP_CONFIG 0xf9 13015 #undef MC_CMD_0xf9_PRIVILEGE_CTG 13016 13017 #define MC_CMD_0xf9_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13018 13019 /* MC_CMD_SET_PARSER_DISP_CONFIG_IN msgrequest */ 13020 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LENMIN 12 13021 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LENMAX 252 13022 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LEN(num) (8+4*(num)) 13023 /* the type of configuration setting to change */ 13024 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_TYPE_OFST 0 13025 /* enum: Per-TXQ enable for multicast UDP destination lookup for possible 13026 * internal loopback. (ENTITY is a queue handle, VALUE is a single boolean.) 13027 */ 13028 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_TXQ_MCAST_UDP_DST_LOOKUP_EN 0x0 13029 /* enum: Per-v-adaptor enable for suppression of self-transmissions on the 13030 * internal loopback path. (ENTITY is an EVB_PORT_ID, VALUE is a single 13031 * boolean.) 13032 */ 13033 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VADAPTOR_SUPPRESS_SELF_TX 0x1 13034 /* handle for the entity to update: queue handle, EVB port ID, etc. depending 13035 * on the type of configuration setting being changed 13036 */ 13037 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_ENTITY_OFST 4 13038 /* new value: the details depend on the type of configuration setting being 13039 * changed 13040 */ 13041 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_OFST 8 13042 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_LEN 4 13043 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_MINNUM 1 13044 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_MAXNUM 61 13045 13046 /* MC_CMD_SET_PARSER_DISP_CONFIG_OUT msgresponse */ 13047 #define MC_CMD_SET_PARSER_DISP_CONFIG_OUT_LEN 0 13048 13049 13050 /***********************************/ 13051 /* MC_CMD_GET_PARSER_DISP_CONFIG 13052 * Read configuration related to the parser-dispatcher subsystem. 13053 */ 13054 #define MC_CMD_GET_PARSER_DISP_CONFIG 0xfa 13055 #undef MC_CMD_0xfa_PRIVILEGE_CTG 13056 13057 #define MC_CMD_0xfa_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13058 13059 /* MC_CMD_GET_PARSER_DISP_CONFIG_IN msgrequest */ 13060 #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_LEN 8 13061 /* the type of configuration setting to read */ 13062 #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_TYPE_OFST 0 13063 /* Enum values, see field(s): */ 13064 /* MC_CMD_SET_PARSER_DISP_CONFIG/MC_CMD_SET_PARSER_DISP_CONFIG_IN/TYPE */ 13065 /* handle for the entity to query: queue handle, EVB port ID, etc. depending on 13066 * the type of configuration setting being read 13067 */ 13068 #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_ENTITY_OFST 4 13069 13070 /* MC_CMD_GET_PARSER_DISP_CONFIG_OUT msgresponse */ 13071 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LENMIN 4 13072 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LENMAX 252 13073 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LEN(num) (0+4*(num)) 13074 /* current value: the details depend on the type of configuration setting being 13075 * read 13076 */ 13077 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_OFST 0 13078 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_LEN 4 13079 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_MINNUM 1 13080 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_MAXNUM 63 13081 13082 13083 /***********************************/ 13084 /* MC_CMD_SET_TX_PORT_SNIFF_CONFIG 13085 * Configure TX port sniffing for the physical port associated with the calling 13086 * function. Only a privileged function may change the port sniffing 13087 * configuration. A copy of all traffic transmitted through the port may be 13088 * delivered to a specific queue, or a set of queues with RSS. Note that these 13089 * packets are delivered with transmit timestamps in the packet prefix, not 13090 * receive timestamps, so it is likely that the queue(s) will need to be 13091 * dedicated as TX sniff receivers. 13092 */ 13093 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG 0xfb 13094 #undef MC_CMD_0xfb_PRIVILEGE_CTG 13095 13096 #define MC_CMD_0xfb_PRIVILEGE_CTG SRIOV_CTG_ADMIN 13097 13098 /* MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN msgrequest */ 13099 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_LEN 16 13100 /* configuration flags */ 13101 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_FLAGS_OFST 0 13102 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_ENABLE_LBN 0 13103 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_ENABLE_WIDTH 1 13104 /* receive queue handle (for RSS mode, this is the base queue) */ 13105 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_QUEUE_OFST 4 13106 /* receive mode */ 13107 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_OFST 8 13108 /* enum: receive to just the specified queue */ 13109 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_SIMPLE 0x0 13110 /* enum: receive to multiple queues using RSS context */ 13111 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_RSS 0x1 13112 /* RSS context (for RX_MODE_RSS) as returned by MC_CMD_RSS_CONTEXT_ALLOC. Note 13113 * that these handles should be considered opaque to the host, although a value 13114 * of 0xFFFFFFFF is guaranteed never to be a valid handle. 13115 */ 13116 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_OFST 12 13117 13118 /* MC_CMD_SET_TX_PORT_SNIFF_CONFIG_OUT msgresponse */ 13119 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_OUT_LEN 0 13120 13121 13122 /***********************************/ 13123 /* MC_CMD_GET_TX_PORT_SNIFF_CONFIG 13124 * Obtain the current TX port sniffing configuration for the physical port 13125 * associated with the calling function. Only a privileged function may read 13126 * the configuration. 13127 */ 13128 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG 0xfc 13129 #undef MC_CMD_0xfc_PRIVILEGE_CTG 13130 13131 #define MC_CMD_0xfc_PRIVILEGE_CTG SRIOV_CTG_ADMIN 13132 13133 /* MC_CMD_GET_TX_PORT_SNIFF_CONFIG_IN msgrequest */ 13134 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_IN_LEN 0 13135 13136 /* MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT msgresponse */ 13137 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_LEN 16 13138 /* configuration flags */ 13139 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_FLAGS_OFST 0 13140 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_ENABLE_LBN 0 13141 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_ENABLE_WIDTH 1 13142 /* receiving queue handle (for RSS mode, this is the base queue) */ 13143 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_OFST 4 13144 /* receive mode */ 13145 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_OFST 8 13146 /* enum: receiving to just the specified queue */ 13147 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_SIMPLE 0x0 13148 /* enum: receiving to multiple queues using RSS context */ 13149 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_RSS 0x1 13150 /* RSS context (for RX_MODE_RSS) */ 13151 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_OFST 12 13152 13153 13154 /***********************************/ 13155 /* MC_CMD_RMON_STATS_RX_ERRORS 13156 * Per queue rx error stats. 13157 */ 13158 #define MC_CMD_RMON_STATS_RX_ERRORS 0xfe 13159 #undef MC_CMD_0xfe_PRIVILEGE_CTG 13160 13161 #define MC_CMD_0xfe_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13162 13163 /* MC_CMD_RMON_STATS_RX_ERRORS_IN msgrequest */ 13164 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_LEN 8 13165 /* The rx queue to get stats for. */ 13166 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_RX_QUEUE_OFST 0 13167 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_FLAGS_OFST 4 13168 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_RST_LBN 0 13169 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_RST_WIDTH 1 13170 13171 /* MC_CMD_RMON_STATS_RX_ERRORS_OUT msgresponse */ 13172 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_LEN 16 13173 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_CRC_ERRORS_OFST 0 13174 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_TRUNC_ERRORS_OFST 4 13175 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_NO_DESC_DROPS_OFST 8 13176 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_ABORT_OFST 12 13177 13178 13179 /***********************************/ 13180 /* MC_CMD_GET_PCIE_RESOURCE_INFO 13181 * Find out about available PCIE resources 13182 */ 13183 #define MC_CMD_GET_PCIE_RESOURCE_INFO 0xfd 13184 13185 /* MC_CMD_GET_PCIE_RESOURCE_INFO_IN msgrequest */ 13186 #define MC_CMD_GET_PCIE_RESOURCE_INFO_IN_LEN 0 13187 13188 /* MC_CMD_GET_PCIE_RESOURCE_INFO_OUT msgresponse */ 13189 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_LEN 28 13190 /* The maximum number of PFs the device can expose */ 13191 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PFS_OFST 0 13192 /* The maximum number of VFs the device can expose in total */ 13193 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VFS_OFST 4 13194 /* The maximum number of MSI-X vectors the device can provide in total */ 13195 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VECTORS_OFST 8 13196 /* the number of MSI-X vectors the device will allocate by default to each PF 13197 */ 13198 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_PF_VECTORS_OFST 12 13199 /* the number of MSI-X vectors the device will allocate by default to each VF 13200 */ 13201 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_VF_VECTORS_OFST 16 13202 /* the maximum number of MSI-X vectors the device can allocate to any one PF */ 13203 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PF_VECTORS_OFST 20 13204 /* the maximum number of MSI-X vectors the device can allocate to any one VF */ 13205 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VF_VECTORS_OFST 24 13206 13207 13208 /***********************************/ 13209 /* MC_CMD_GET_PORT_MODES 13210 * Find out about available port modes 13211 */ 13212 #define MC_CMD_GET_PORT_MODES 0xff 13213 #undef MC_CMD_0xff_PRIVILEGE_CTG 13214 13215 #define MC_CMD_0xff_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13216 13217 /* MC_CMD_GET_PORT_MODES_IN msgrequest */ 13218 #define MC_CMD_GET_PORT_MODES_IN_LEN 0 13219 13220 /* MC_CMD_GET_PORT_MODES_OUT msgresponse */ 13221 #define MC_CMD_GET_PORT_MODES_OUT_LEN 12 13222 /* Bitmask of port modes available on the board (indexed by TLV_PORT_MODE_*) */ 13223 #define MC_CMD_GET_PORT_MODES_OUT_MODES_OFST 0 13224 /* Default (canonical) board mode */ 13225 #define MC_CMD_GET_PORT_MODES_OUT_DEFAULT_MODE_OFST 4 13226 /* Current board mode */ 13227 #define MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST 8 13228 13229 13230 /***********************************/ 13231 /* MC_CMD_READ_ATB 13232 * Sample voltages on the ATB 13233 */ 13234 #define MC_CMD_READ_ATB 0x100 13235 #undef MC_CMD_0x100_PRIVILEGE_CTG 13236 13237 #define MC_CMD_0x100_PRIVILEGE_CTG SRIOV_CTG_ADMIN 13238 13239 /* MC_CMD_READ_ATB_IN msgrequest */ 13240 #define MC_CMD_READ_ATB_IN_LEN 16 13241 #define MC_CMD_READ_ATB_IN_SIGNAL_BUS_OFST 0 13242 #define MC_CMD_READ_ATB_IN_BUS_CCOM 0x0 /* enum */ 13243 #define MC_CMD_READ_ATB_IN_BUS_CKR 0x1 /* enum */ 13244 #define MC_CMD_READ_ATB_IN_BUS_CPCIE 0x8 /* enum */ 13245 #define MC_CMD_READ_ATB_IN_SIGNAL_EN_BITNO_OFST 4 13246 #define MC_CMD_READ_ATB_IN_SIGNAL_SEL_OFST 8 13247 #define MC_CMD_READ_ATB_IN_SETTLING_TIME_US_OFST 12 13248 13249 /* MC_CMD_READ_ATB_OUT msgresponse */ 13250 #define MC_CMD_READ_ATB_OUT_LEN 4 13251 #define MC_CMD_READ_ATB_OUT_SAMPLE_MV_OFST 0 13252 13253 13254 /***********************************/ 13255 /* MC_CMD_GET_WORKAROUNDS 13256 * Read the list of all implemented and all currently enabled workarounds. The 13257 * enums here must correspond with those in MC_CMD_WORKAROUND. 13258 */ 13259 #define MC_CMD_GET_WORKAROUNDS 0x59 13260 #undef MC_CMD_0x59_PRIVILEGE_CTG 13261 13262 #define MC_CMD_0x59_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13263 13264 /* MC_CMD_GET_WORKAROUNDS_OUT msgresponse */ 13265 #define MC_CMD_GET_WORKAROUNDS_OUT_LEN 8 13266 /* Each workaround is represented by a single bit according to the enums below. 13267 */ 13268 #define MC_CMD_GET_WORKAROUNDS_OUT_IMPLEMENTED_OFST 0 13269 #define MC_CMD_GET_WORKAROUNDS_OUT_ENABLED_OFST 4 13270 /* enum: Bug 17230 work around. */ 13271 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG17230 0x2 13272 /* enum: Bug 35388 work around (unsafe EVQ writes). */ 13273 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG35388 0x4 13274 /* enum: Bug35017 workaround (A64 tables must be identity map) */ 13275 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG35017 0x8 13276 /* enum: Bug 41750 present (MC_CMD_TRIGGER_INTERRUPT won't work) */ 13277 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG41750 0x10 13278 /* enum: Bug 42008 present (Interrupts can overtake associated events). Caution 13279 * - before adding code that queries this workaround, remember that there's 13280 * released Monza firmware that doesn't understand MC_CMD_WORKAROUND_BUG42008, 13281 * and will hence (incorrectly) report that the bug doesn't exist. 13282 */ 13283 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG42008 0x20 13284 /* enum: Bug 26807 features present in firmware (multicast filter chaining) */ 13285 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG26807 0x40 13286 13287 13288 /***********************************/ 13289 /* MC_CMD_PRIVILEGE_MASK 13290 * Read/set privileges of an arbitrary PCIe function 13291 */ 13292 #define MC_CMD_PRIVILEGE_MASK 0x5a 13293 #undef MC_CMD_0x5a_PRIVILEGE_CTG 13294 13295 #define MC_CMD_0x5a_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13296 13297 /* MC_CMD_PRIVILEGE_MASK_IN msgrequest */ 13298 #define MC_CMD_PRIVILEGE_MASK_IN_LEN 8 13299 /* The target function to have its mask read or set e.g. PF 0 = 0xFFFF0000, VF 13300 * 1,3 = 0x00030001 13301 */ 13302 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_OFST 0 13303 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_PF_LBN 0 13304 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_PF_WIDTH 16 13305 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_VF_LBN 16 13306 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_VF_WIDTH 16 13307 #define MC_CMD_PRIVILEGE_MASK_IN_VF_NULL 0xffff /* enum */ 13308 /* New privilege mask to be set. The mask will only be changed if the MSB is 13309 * set to 1. 13310 */ 13311 #define MC_CMD_PRIVILEGE_MASK_IN_NEW_MASK_OFST 4 13312 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN 0x1 /* enum */ 13313 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_LINK 0x2 /* enum */ 13314 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ONLOAD 0x4 /* enum */ 13315 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_PTP 0x8 /* enum */ 13316 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE_FILTERS 0x10 /* enum */ 13317 /* enum: Deprecated. Equivalent to MAC_SPOOFING_TX combined with CHANGE_MAC. */ 13318 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING 0x20 13319 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_UNICAST 0x40 /* enum */ 13320 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_MULTICAST 0x80 /* enum */ 13321 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_BROADCAST 0x100 /* enum */ 13322 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ALL_MULTICAST 0x200 /* enum */ 13323 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_PROMISCUOUS 0x400 /* enum */ 13324 /* enum: Allows to set the TX packets' source MAC address to any arbitrary MAC 13325 * adress. 13326 */ 13327 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING_TX 0x800 13328 /* enum: Privilege that allows a Function to change the MAC address configured 13329 * in its associated vAdapter/vPort. 13330 */ 13331 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_CHANGE_MAC 0x1000 13332 /* enum: Privilege that allows a Function to install filters that specify VLANs 13333 * that are not in the permit list for the associated vPort. This privilege is 13334 * primarily to support ESX where vPorts are created that restrict traffic to 13335 * only a set of permitted VLANs. See the vPort flag FLAG_VLAN_RESTRICT. 13336 */ 13337 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_UNRESTRICTED_VLAN 0x2000 13338 /* enum: Set this bit to indicate that a new privilege mask is to be set, 13339 * otherwise the command will only read the existing mask. 13340 */ 13341 #define MC_CMD_PRIVILEGE_MASK_IN_DO_CHANGE 0x80000000 13342 13343 /* MC_CMD_PRIVILEGE_MASK_OUT msgresponse */ 13344 #define MC_CMD_PRIVILEGE_MASK_OUT_LEN 4 13345 /* For an admin function, always all the privileges are reported. */ 13346 #define MC_CMD_PRIVILEGE_MASK_OUT_OLD_MASK_OFST 0 13347 13348 13349 /***********************************/ 13350 /* MC_CMD_LINK_STATE_MODE 13351 * Read/set link state mode of a VF 13352 */ 13353 #define MC_CMD_LINK_STATE_MODE 0x5c 13354 #undef MC_CMD_0x5c_PRIVILEGE_CTG 13355 13356 #define MC_CMD_0x5c_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13357 13358 /* MC_CMD_LINK_STATE_MODE_IN msgrequest */ 13359 #define MC_CMD_LINK_STATE_MODE_IN_LEN 8 13360 /* The target function to have its link state mode read or set, must be a VF 13361 * e.g. VF 1,3 = 0x00030001 13362 */ 13363 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_OFST 0 13364 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_LBN 0 13365 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_WIDTH 16 13366 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_VF_LBN 16 13367 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_VF_WIDTH 16 13368 /* New link state mode to be set */ 13369 #define MC_CMD_LINK_STATE_MODE_IN_NEW_MODE_OFST 4 13370 #define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_AUTO 0x0 /* enum */ 13371 #define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_UP 0x1 /* enum */ 13372 #define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_DOWN 0x2 /* enum */ 13373 /* enum: Use this value to just read the existing setting without modifying it. 13374 */ 13375 #define MC_CMD_LINK_STATE_MODE_IN_DO_NOT_CHANGE 0xffffffff 13376 13377 /* MC_CMD_LINK_STATE_MODE_OUT msgresponse */ 13378 #define MC_CMD_LINK_STATE_MODE_OUT_LEN 4 13379 #define MC_CMD_LINK_STATE_MODE_OUT_OLD_MODE_OFST 0 13380 13381 13382 /***********************************/ 13383 /* MC_CMD_GET_SNAPSHOT_LENGTH 13384 * Obtain the curent range of allowable values for the SNAPSHOT_LENGTH 13385 * parameter to MC_CMD_INIT_RXQ. 13386 */ 13387 #define MC_CMD_GET_SNAPSHOT_LENGTH 0x101 13388 #undef MC_CMD_0x101_PRIVILEGE_CTG 13389 13390 #define MC_CMD_0x101_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13391 13392 /* MC_CMD_GET_SNAPSHOT_LENGTH_IN msgrequest */ 13393 #define MC_CMD_GET_SNAPSHOT_LENGTH_IN_LEN 0 13394 13395 /* MC_CMD_GET_SNAPSHOT_LENGTH_OUT msgresponse */ 13396 #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_LEN 8 13397 /* Minimum acceptable snapshot length. */ 13398 #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MIN_OFST 0 13399 /* Maximum acceptable snapshot length. */ 13400 #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MAX_OFST 4 13401 13402 13403 /***********************************/ 13404 /* MC_CMD_FUSE_DIAGS 13405 * Additional fuse diagnostics 13406 */ 13407 #define MC_CMD_FUSE_DIAGS 0x102 13408 #undef MC_CMD_0x102_PRIVILEGE_CTG 13409 13410 #define MC_CMD_0x102_PRIVILEGE_CTG SRIOV_CTG_ADMIN 13411 13412 /* MC_CMD_FUSE_DIAGS_IN msgrequest */ 13413 #define MC_CMD_FUSE_DIAGS_IN_LEN 0 13414 13415 /* MC_CMD_FUSE_DIAGS_OUT msgresponse */ 13416 #define MC_CMD_FUSE_DIAGS_OUT_LEN 48 13417 /* Total number of mismatched bits between pairs in area 0 */ 13418 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_MISMATCH_BITS_OFST 0 13419 /* Total number of unexpectedly clear (set in B but not A) bits in area 0 */ 13420 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_A_BAD_BITS_OFST 4 13421 /* Total number of unexpectedly clear (set in A but not B) bits in area 0 */ 13422 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_B_BAD_BITS_OFST 8 13423 /* Checksum of data after logical OR of pairs in area 0 */ 13424 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_CHECKSUM_OFST 12 13425 /* Total number of mismatched bits between pairs in area 1 */ 13426 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_MISMATCH_BITS_OFST 16 13427 /* Total number of unexpectedly clear (set in B but not A) bits in area 1 */ 13428 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_A_BAD_BITS_OFST 20 13429 /* Total number of unexpectedly clear (set in A but not B) bits in area 1 */ 13430 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_B_BAD_BITS_OFST 24 13431 /* Checksum of data after logical OR of pairs in area 1 */ 13432 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_CHECKSUM_OFST 28 13433 /* Total number of mismatched bits between pairs in area 2 */ 13434 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_MISMATCH_BITS_OFST 32 13435 /* Total number of unexpectedly clear (set in B but not A) bits in area 2 */ 13436 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_A_BAD_BITS_OFST 36 13437 /* Total number of unexpectedly clear (set in A but not B) bits in area 2 */ 13438 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_B_BAD_BITS_OFST 40 13439 /* Checksum of data after logical OR of pairs in area 2 */ 13440 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_CHECKSUM_OFST 44 13441 13442 13443 /***********************************/ 13444 /* MC_CMD_PRIVILEGE_MODIFY 13445 * Modify the privileges of a set of PCIe functions. Note that this operation 13446 * only effects non-admin functions unless the admin privilege itself is 13447 * included in one of the masks provided. 13448 */ 13449 #define MC_CMD_PRIVILEGE_MODIFY 0x60 13450 #undef MC_CMD_0x60_PRIVILEGE_CTG 13451 13452 #define MC_CMD_0x60_PRIVILEGE_CTG SRIOV_CTG_ADMIN 13453 13454 /* MC_CMD_PRIVILEGE_MODIFY_IN msgrequest */ 13455 #define MC_CMD_PRIVILEGE_MODIFY_IN_LEN 16 13456 /* The groups of functions to have their privilege masks modified. */ 13457 #define MC_CMD_PRIVILEGE_MODIFY_IN_FN_GROUP_OFST 0 13458 #define MC_CMD_PRIVILEGE_MODIFY_IN_NONE 0x0 /* enum */ 13459 #define MC_CMD_PRIVILEGE_MODIFY_IN_ALL 0x1 /* enum */ 13460 #define MC_CMD_PRIVILEGE_MODIFY_IN_PFS_ONLY 0x2 /* enum */ 13461 #define MC_CMD_PRIVILEGE_MODIFY_IN_VFS_ONLY 0x3 /* enum */ 13462 #define MC_CMD_PRIVILEGE_MODIFY_IN_VFS_OF_PF 0x4 /* enum */ 13463 #define MC_CMD_PRIVILEGE_MODIFY_IN_ONE 0x5 /* enum */ 13464 /* For VFS_OF_PF specify the PF, for ONE specify the target function */ 13465 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_OFST 4 13466 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_PF_LBN 0 13467 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_PF_WIDTH 16 13468 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_VF_LBN 16 13469 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_VF_WIDTH 16 13470 /* Privileges to be added to the target functions. For privilege definitions 13471 * refer to the command MC_CMD_PRIVILEGE_MASK 13472 */ 13473 #define MC_CMD_PRIVILEGE_MODIFY_IN_ADD_MASK_OFST 8 13474 /* Privileges to be removed from the target functions. For privilege 13475 * definitions refer to the command MC_CMD_PRIVILEGE_MASK 13476 */ 13477 #define MC_CMD_PRIVILEGE_MODIFY_IN_REMOVE_MASK_OFST 12 13478 13479 /* MC_CMD_PRIVILEGE_MODIFY_OUT msgresponse */ 13480 #define MC_CMD_PRIVILEGE_MODIFY_OUT_LEN 0 13481 13482 13483 /***********************************/ 13484 /* MC_CMD_XPM_READ_BYTES 13485 * Read XPM memory 13486 */ 13487 #define MC_CMD_XPM_READ_BYTES 0x103 13488 #undef MC_CMD_0x103_PRIVILEGE_CTG 13489 13490 #define MC_CMD_0x103_PRIVILEGE_CTG SRIOV_CTG_ADMIN 13491 13492 /* MC_CMD_XPM_READ_BYTES_IN msgrequest */ 13493 #define MC_CMD_XPM_READ_BYTES_IN_LEN 8 13494 /* Start address (byte) */ 13495 #define MC_CMD_XPM_READ_BYTES_IN_ADDR_OFST 0 13496 /* Count (bytes) */ 13497 #define MC_CMD_XPM_READ_BYTES_IN_COUNT_OFST 4 13498 13499 /* MC_CMD_XPM_READ_BYTES_OUT msgresponse */ 13500 #define MC_CMD_XPM_READ_BYTES_OUT_LENMIN 0 13501 #define MC_CMD_XPM_READ_BYTES_OUT_LENMAX 252 13502 #define MC_CMD_XPM_READ_BYTES_OUT_LEN(num) (0+1*(num)) 13503 /* Data */ 13504 #define MC_CMD_XPM_READ_BYTES_OUT_DATA_OFST 0 13505 #define MC_CMD_XPM_READ_BYTES_OUT_DATA_LEN 1 13506 #define MC_CMD_XPM_READ_BYTES_OUT_DATA_MINNUM 0 13507 #define MC_CMD_XPM_READ_BYTES_OUT_DATA_MAXNUM 252 13508 13509 13510 /***********************************/ 13511 /* MC_CMD_XPM_WRITE_BYTES 13512 * Write XPM memory 13513 */ 13514 #define MC_CMD_XPM_WRITE_BYTES 0x104 13515 #undef MC_CMD_0x104_PRIVILEGE_CTG 13516 13517 #define MC_CMD_0x104_PRIVILEGE_CTG SRIOV_CTG_ADMIN 13518 13519 /* MC_CMD_XPM_WRITE_BYTES_IN msgrequest */ 13520 #define MC_CMD_XPM_WRITE_BYTES_IN_LENMIN 8 13521 #define MC_CMD_XPM_WRITE_BYTES_IN_LENMAX 252 13522 #define MC_CMD_XPM_WRITE_BYTES_IN_LEN(num) (8+1*(num)) 13523 /* Start address (byte) */ 13524 #define MC_CMD_XPM_WRITE_BYTES_IN_ADDR_OFST 0 13525 /* Count (bytes) */ 13526 #define MC_CMD_XPM_WRITE_BYTES_IN_COUNT_OFST 4 13527 /* Data */ 13528 #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_OFST 8 13529 #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_LEN 1 13530 #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_MINNUM 0 13531 #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_MAXNUM 244 13532 13533 /* MC_CMD_XPM_WRITE_BYTES_OUT msgresponse */ 13534 #define MC_CMD_XPM_WRITE_BYTES_OUT_LEN 0 13535 13536 13537 /***********************************/ 13538 /* MC_CMD_XPM_READ_SECTOR 13539 * Read XPM sector 13540 */ 13541 #define MC_CMD_XPM_READ_SECTOR 0x105 13542 #undef MC_CMD_0x105_PRIVILEGE_CTG 13543 13544 #define MC_CMD_0x105_PRIVILEGE_CTG SRIOV_CTG_ADMIN 13545 13546 /* MC_CMD_XPM_READ_SECTOR_IN msgrequest */ 13547 #define MC_CMD_XPM_READ_SECTOR_IN_LEN 8 13548 /* Sector index */ 13549 #define MC_CMD_XPM_READ_SECTOR_IN_INDEX_OFST 0 13550 /* Sector size */ 13551 #define MC_CMD_XPM_READ_SECTOR_IN_SIZE_OFST 4 13552 13553 /* MC_CMD_XPM_READ_SECTOR_OUT msgresponse */ 13554 #define MC_CMD_XPM_READ_SECTOR_OUT_LENMIN 4 13555 #define MC_CMD_XPM_READ_SECTOR_OUT_LENMAX 36 13556 #define MC_CMD_XPM_READ_SECTOR_OUT_LEN(num) (4+1*(num)) 13557 /* Sector type */ 13558 #define MC_CMD_XPM_READ_SECTOR_OUT_TYPE_OFST 0 13559 #define MC_CMD_XPM_READ_SECTOR_OUT_BLANK 0x0 /* enum */ 13560 #define MC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_KEY_128 0x1 /* enum */ 13561 #define MC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_KEY_256 0x2 /* enum */ 13562 #define MC_CMD_XPM_READ_SECTOR_OUT_INVALID 0xff /* enum */ 13563 /* Sector data */ 13564 #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_OFST 4 13565 #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_LEN 1 13566 #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_MINNUM 0 13567 #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_MAXNUM 32 13568 13569 13570 /***********************************/ 13571 /* MC_CMD_XPM_WRITE_SECTOR 13572 * Write XPM sector 13573 */ 13574 #define MC_CMD_XPM_WRITE_SECTOR 0x106 13575 #undef MC_CMD_0x106_PRIVILEGE_CTG 13576 13577 #define MC_CMD_0x106_PRIVILEGE_CTG SRIOV_CTG_ADMIN 13578 13579 /* MC_CMD_XPM_WRITE_SECTOR_IN msgrequest */ 13580 #define MC_CMD_XPM_WRITE_SECTOR_IN_LENMIN 12 13581 #define MC_CMD_XPM_WRITE_SECTOR_IN_LENMAX 44 13582 #define MC_CMD_XPM_WRITE_SECTOR_IN_LEN(num) (12+1*(num)) 13583 /* If writing fails due to an uncorrectable error, try up to RETRIES following 13584 * sectors (or until no more space available). If 0, only one write attempt is 13585 * made. Note that uncorrectable errors are unlikely, thanks to XPM self-repair 13586 * mechanism. 13587 */ 13588 #define MC_CMD_XPM_WRITE_SECTOR_IN_RETRIES_OFST 0 13589 #define MC_CMD_XPM_WRITE_SECTOR_IN_RETRIES_LEN 1 13590 #define MC_CMD_XPM_WRITE_SECTOR_IN_RESERVED_OFST 1 13591 #define MC_CMD_XPM_WRITE_SECTOR_IN_RESERVED_LEN 3 13592 /* Sector type */ 13593 #define MC_CMD_XPM_WRITE_SECTOR_IN_TYPE_OFST 4 13594 /* Enum values, see field(s): */ 13595 /* MC_CMD_XPM_READ_SECTOR/MC_CMD_XPM_READ_SECTOR_OUT/TYPE */ 13596 /* Sector size */ 13597 #define MC_CMD_XPM_WRITE_SECTOR_IN_SIZE_OFST 8 13598 /* Sector data */ 13599 #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_OFST 12 13600 #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_LEN 1 13601 #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_MINNUM 0 13602 #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_MAXNUM 32 13603 13604 /* MC_CMD_XPM_WRITE_SECTOR_OUT msgresponse */ 13605 #define MC_CMD_XPM_WRITE_SECTOR_OUT_LEN 4 13606 /* New sector index */ 13607 #define MC_CMD_XPM_WRITE_SECTOR_OUT_INDEX_OFST 0 13608 13609 13610 /***********************************/ 13611 /* MC_CMD_XPM_INVALIDATE_SECTOR 13612 * Invalidate XPM sector 13613 */ 13614 #define MC_CMD_XPM_INVALIDATE_SECTOR 0x107 13615 #undef MC_CMD_0x107_PRIVILEGE_CTG 13616 13617 #define MC_CMD_0x107_PRIVILEGE_CTG SRIOV_CTG_ADMIN 13618 13619 /* MC_CMD_XPM_INVALIDATE_SECTOR_IN msgrequest */ 13620 #define MC_CMD_XPM_INVALIDATE_SECTOR_IN_LEN 4 13621 /* Sector index */ 13622 #define MC_CMD_XPM_INVALIDATE_SECTOR_IN_INDEX_OFST 0 13623 13624 /* MC_CMD_XPM_INVALIDATE_SECTOR_OUT msgresponse */ 13625 #define MC_CMD_XPM_INVALIDATE_SECTOR_OUT_LEN 0 13626 13627 13628 /***********************************/ 13629 /* MC_CMD_XPM_BLANK_CHECK 13630 * Blank-check XPM memory and report bad locations 13631 */ 13632 #define MC_CMD_XPM_BLANK_CHECK 0x108 13633 #undef MC_CMD_0x108_PRIVILEGE_CTG 13634 13635 #define MC_CMD_0x108_PRIVILEGE_CTG SRIOV_CTG_ADMIN 13636 13637 /* MC_CMD_XPM_BLANK_CHECK_IN msgrequest */ 13638 #define MC_CMD_XPM_BLANK_CHECK_IN_LEN 8 13639 /* Start address (byte) */ 13640 #define MC_CMD_XPM_BLANK_CHECK_IN_ADDR_OFST 0 13641 /* Count (bytes) */ 13642 #define MC_CMD_XPM_BLANK_CHECK_IN_COUNT_OFST 4 13643 13644 /* MC_CMD_XPM_BLANK_CHECK_OUT msgresponse */ 13645 #define MC_CMD_XPM_BLANK_CHECK_OUT_LENMIN 4 13646 #define MC_CMD_XPM_BLANK_CHECK_OUT_LENMAX 252 13647 #define MC_CMD_XPM_BLANK_CHECK_OUT_LEN(num) (4+2*(num)) 13648 /* Total number of bad (non-blank) locations */ 13649 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_COUNT_OFST 0 13650 /* Addresses of bad locations (may be less than BAD_COUNT, if all cannot fit 13651 * into MCDI response) 13652 */ 13653 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_OFST 4 13654 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_LEN 2 13655 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_MINNUM 0 13656 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_MAXNUM 124 13657 13658 13659 /***********************************/ 13660 /* MC_CMD_XPM_REPAIR 13661 * Blank-check and repair XPM memory 13662 */ 13663 #define MC_CMD_XPM_REPAIR 0x109 13664 #undef MC_CMD_0x109_PRIVILEGE_CTG 13665 13666 #define MC_CMD_0x109_PRIVILEGE_CTG SRIOV_CTG_ADMIN 13667 13668 /* MC_CMD_XPM_REPAIR_IN msgrequest */ 13669 #define MC_CMD_XPM_REPAIR_IN_LEN 8 13670 /* Start address (byte) */ 13671 #define MC_CMD_XPM_REPAIR_IN_ADDR_OFST 0 13672 /* Count (bytes) */ 13673 #define MC_CMD_XPM_REPAIR_IN_COUNT_OFST 4 13674 13675 /* MC_CMD_XPM_REPAIR_OUT msgresponse */ 13676 #define MC_CMD_XPM_REPAIR_OUT_LEN 0 13677 13678 13679 /***********************************/ 13680 /* MC_CMD_XPM_DECODER_TEST 13681 * Test XPM memory address decoders for gross manufacturing defects. Can only 13682 * be performed on an unprogrammed part. 13683 */ 13684 #define MC_CMD_XPM_DECODER_TEST 0x10a 13685 #undef MC_CMD_0x10a_PRIVILEGE_CTG 13686 13687 #define MC_CMD_0x10a_PRIVILEGE_CTG SRIOV_CTG_ADMIN 13688 13689 /* MC_CMD_XPM_DECODER_TEST_IN msgrequest */ 13690 #define MC_CMD_XPM_DECODER_TEST_IN_LEN 0 13691 13692 /* MC_CMD_XPM_DECODER_TEST_OUT msgresponse */ 13693 #define MC_CMD_XPM_DECODER_TEST_OUT_LEN 0 13694 13695 13696 /***********************************/ 13697 /* MC_CMD_XPM_WRITE_TEST 13698 * XPM memory write test. Test XPM write logic for gross manufacturing defects 13699 * by writing to a dedicated test row. There are 16 locations in the test row 13700 * and the test can only be performed on locations that have not been 13701 * previously used (i.e. can be run at most 16 times). The test will pick the 13702 * first available location to use, or fail with ENOSPC if none left. 13703 */ 13704 #define MC_CMD_XPM_WRITE_TEST 0x10b 13705 #undef MC_CMD_0x10b_PRIVILEGE_CTG 13706 13707 #define MC_CMD_0x10b_PRIVILEGE_CTG SRIOV_CTG_ADMIN 13708 13709 /* MC_CMD_XPM_WRITE_TEST_IN msgrequest */ 13710 #define MC_CMD_XPM_WRITE_TEST_IN_LEN 0 13711 13712 /* MC_CMD_XPM_WRITE_TEST_OUT msgresponse */ 13713 #define MC_CMD_XPM_WRITE_TEST_OUT_LEN 0 13714 13715 13716 /***********************************/ 13717 /* MC_CMD_EXEC_SIGNED 13718 * Check the CMAC of the contents of IMEM and DMEM against the value supplied 13719 * and if correct begin execution from the start of IMEM. The caller supplies a 13720 * key ID, the length of IMEM and DMEM to validate and the expected CMAC. CMAC 13721 * computation runs from the start of IMEM, and from the start of DMEM + 16k, 13722 * to match flash booting. The command will respond with EINVAL if the CMAC 13723 * does match, otherwise it will respond with success before it jumps to IMEM. 13724 */ 13725 #define MC_CMD_EXEC_SIGNED 0x10c 13726 #undef MC_CMD_0x10c_PRIVILEGE_CTG 13727 13728 #define MC_CMD_0x10c_PRIVILEGE_CTG SRIOV_CTG_ADMIN 13729 13730 /* MC_CMD_EXEC_SIGNED_IN msgrequest */ 13731 #define MC_CMD_EXEC_SIGNED_IN_LEN 28 13732 /* the length of code to include in the CMAC */ 13733 #define MC_CMD_EXEC_SIGNED_IN_CODELEN_OFST 0 13734 /* the length of date to include in the CMAC */ 13735 #define MC_CMD_EXEC_SIGNED_IN_DATALEN_OFST 4 13736 /* the XPM sector containing the key to use */ 13737 #define MC_CMD_EXEC_SIGNED_IN_KEYSECTOR_OFST 8 13738 /* the expected CMAC value */ 13739 #define MC_CMD_EXEC_SIGNED_IN_CMAC_OFST 12 13740 #define MC_CMD_EXEC_SIGNED_IN_CMAC_LEN 16 13741 13742 /* MC_CMD_EXEC_SIGNED_OUT msgresponse */ 13743 #define MC_CMD_EXEC_SIGNED_OUT_LEN 0 13744 13745 13746 /***********************************/ 13747 /* MC_CMD_PREPARE_SIGNED 13748 * Prepare to upload a signed image. This will scrub the specified length of 13749 * the data region, which must be at least as large as the DATALEN supplied to 13750 * MC_CMD_EXEC_SIGNED. 13751 */ 13752 #define MC_CMD_PREPARE_SIGNED 0x10d 13753 #undef MC_CMD_0x10d_PRIVILEGE_CTG 13754 13755 #define MC_CMD_0x10d_PRIVILEGE_CTG SRIOV_CTG_ADMIN 13756 13757 /* MC_CMD_PREPARE_SIGNED_IN msgrequest */ 13758 #define MC_CMD_PREPARE_SIGNED_IN_LEN 4 13759 /* the length of data area to clear */ 13760 #define MC_CMD_PREPARE_SIGNED_IN_DATALEN_OFST 0 13761 13762 /* MC_CMD_PREPARE_SIGNED_OUT msgresponse */ 13763 #define MC_CMD_PREPARE_SIGNED_OUT_LEN 0 13764 13765 #endif /* _SIENA_MC_DRIVER_PCOL_H */ 13766