1 /*- 2 * Copyright 2008-2011 Solarflare Communications Inc. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #ifndef _SIENA_MC_DRIVER_PCOL_H 29 #define _SIENA_MC_DRIVER_PCOL_H 30 31 32 /* Values to be written into FMCR_CZ_RESET_STATE_REG to control boot. */ 33 /* Power-on reset state */ 34 #define MC_FW_STATE_POR (1) 35 /* If this is set in MC_RESET_STATE_REG then it should be 36 * possible to jump into IMEM without loading code from flash. */ 37 #define MC_FW_WARM_BOOT_OK (2) 38 /* The MC main image has started to boot. */ 39 #define MC_FW_STATE_BOOTING (4) 40 /* The Scheduler has started. */ 41 #define MC_FW_STATE_SCHED (8) 42 43 /* Values to be written to the per-port status dword in shared 44 * memory on reboot and assert */ 45 #define MC_STATUS_DWORD_REBOOT (0xb007b007) 46 #define MC_STATUS_DWORD_ASSERT (0xdeaddead) 47 48 /* The current version of the MCDI protocol. 49 * 50 * Note that the ROM burnt into the card only talks V0, so at the very 51 * least every driver must support version 0 and MCDI_PCOL_VERSION 52 */ 53 #ifdef WITH_MCDI_V2 54 #define MCDI_PCOL_VERSION 2 55 #else 56 #define MCDI_PCOL_VERSION 1 57 #endif 58 59 /* Unused commands: 0x23, 0x27, 0x30, 0x31 */ 60 61 /* Unused commands: 0x23, 0x27, 0x30, 0x31 */ 62 63 /** 64 * MCDI version 1 65 * 66 * Each MCDI request starts with an MCDI_HEADER, which is a 32byte 67 * structure, filled in by the client. 68 * 69 * 0 7 8 16 20 22 23 24 31 70 * | CODE | R | LEN | SEQ | Rsvd | E | R | XFLAGS | 71 * | | | 72 * | | \--- Response 73 * | \------- Error 74 * \------------------------------ Resync (always set) 75 * 76 * The client writes it's request into MC shared memory, and rings the 77 * doorbell. Each request is completed by either by the MC writting 78 * back into shared memory, or by writting out an event. 79 * 80 * All MCDI commands support completion by shared memory response. Each 81 * request may also contain additional data (accounted for by HEADER.LEN), 82 * and some response's may also contain additional data (again, accounted 83 * for by HEADER.LEN). 84 * 85 * Some MCDI commands support completion by event, in which any associated 86 * response data is included in the event. 87 * 88 * The protocol requires one response to be delivered for every request, a 89 * request should not be sent unless the response for the previous request 90 * has been received (either by polling shared memory, or by receiving 91 * an event). 92 */ 93 94 /** Request/Response structure */ 95 #define MCDI_HEADER_OFST 0 96 #define MCDI_HEADER_CODE_LBN 0 97 #define MCDI_HEADER_CODE_WIDTH 7 98 #define MCDI_HEADER_RESYNC_LBN 7 99 #define MCDI_HEADER_RESYNC_WIDTH 1 100 #define MCDI_HEADER_DATALEN_LBN 8 101 #define MCDI_HEADER_DATALEN_WIDTH 8 102 #define MCDI_HEADER_SEQ_LBN 16 103 #define MCDI_HEADER_RSVD_LBN 20 104 #define MCDI_HEADER_RSVD_WIDTH 2 105 #define MCDI_HEADER_SEQ_WIDTH 4 106 #define MCDI_HEADER_ERROR_LBN 22 107 #define MCDI_HEADER_ERROR_WIDTH 1 108 #define MCDI_HEADER_RESPONSE_LBN 23 109 #define MCDI_HEADER_RESPONSE_WIDTH 1 110 #define MCDI_HEADER_XFLAGS_LBN 24 111 #define MCDI_HEADER_XFLAGS_WIDTH 8 112 /* Request response using event */ 113 #define MCDI_HEADER_XFLAGS_EVREQ 0x01 114 115 /* Maximum number of payload bytes */ 116 #if MCDI_PCOL_VERSION == 1 117 #define MCDI_CTL_SDU_LEN_MAX 0xfc 118 #elif MCDI_PCOL_VERSION == 2 119 #define MCDI_CTL_SDU_LEN_MAX 0x400 120 #endif 121 122 /* The MC can generate events for two reasons: 123 * - To complete a shared memory request if XFLAGS_EVREQ was set 124 * - As a notification (link state, i2c event), controlled 125 * via MC_CMD_LOG_CTRL 126 * 127 * Both events share a common structure: 128 * 129 * 0 32 33 36 44 52 60 130 * | Data | Cont | Level | Src | Code | Rsvd | 131 * | 132 * \ There is another event pending in this notification 133 * 134 * If Code==CMDDONE, then the fields are further interpreted as: 135 * 136 * - LEVEL==INFO Command succeded 137 * - LEVEL==ERR Command failed 138 * 139 * 0 8 16 24 32 140 * | Seq | Datalen | Errno | Rsvd | 141 * 142 * These fields are taken directly out of the standard MCDI header, i.e., 143 * LEVEL==ERR, Datalen == 0 => Reboot 144 * 145 * Events can be squirted out of the UART (using LOG_CTRL) without a 146 * MCDI header. An event can be distinguished from a MCDI response by 147 * examining the first byte which is 0xc0. This corresponds to the 148 * non-existent MCDI command MC_CMD_DEBUG_LOG. 149 * 150 * 0 7 8 151 * | command | Resync | = 0xc0 152 * 153 * Since the event is written in big-endian byte order, this works 154 * providing bits 56-63 of the event are 0xc0. 155 * 156 * 56 60 63 157 * | Rsvd | Code | = 0xc0 158 * 159 * Which means for convenience the event code is 0xc for all MC 160 * generated events. 161 */ 162 #define FSE_AZ_EV_CODE_MCDI_EVRESPONSE 0xc 163 164 165 /* Non-existent command target */ 166 #define MC_CMD_ERR_ENOENT 2 167 /* assert() has killed the MC */ 168 #define MC_CMD_ERR_EINTR 4 169 /* Caller does not hold required locks */ 170 #define MC_CMD_ERR_EACCES 13 171 /* Resource is currently unavailable (e.g. lock contention) */ 172 #define MC_CMD_ERR_EBUSY 16 173 /* Invalid argument to target */ 174 #define MC_CMD_ERR_EINVAL 22 175 /* Non-recursive resource is already acquired */ 176 #define MC_CMD_ERR_EDEADLK 35 177 /* Operation not implemented */ 178 #define MC_CMD_ERR_ENOSYS 38 179 /* Operation timed out */ 180 #define MC_CMD_ERR_ETIME 62 181 182 #define MC_CMD_ERR_CODE_OFST 0 183 184 /* We define 8 "escape" commands to allow 185 for command number space extension */ 186 187 #define MC_CMD_CMD_SPACE_ESCAPE_0 0x78 188 #define MC_CMD_CMD_SPACE_ESCAPE_1 0x79 189 #define MC_CMD_CMD_SPACE_ESCAPE_2 0x7A 190 #define MC_CMD_CMD_SPACE_ESCAPE_3 0x7B 191 #define MC_CMD_CMD_SPACE_ESCAPE_4 0x7C 192 #define MC_CMD_CMD_SPACE_ESCAPE_5 0x7D 193 #define MC_CMD_CMD_SPACE_ESCAPE_6 0x7E 194 #define MC_CMD_CMD_SPACE_ESCAPE_7 0x7F 195 196 /* Vectors in the boot ROM */ 197 /* Point to the copycode entry point. */ 198 #define MC_BOOTROM_COPYCODE_VEC (0x7f4) 199 /* Points to the recovery mode entry point. */ 200 #define MC_BOOTROM_NOFLASH_VEC (0x7f8) 201 202 /* The command set exported by the boot ROM (MCDI v0) */ 203 #define MC_CMD_GET_VERSION_V0_SUPPORTED_FUNCS { \ 204 (1 << MC_CMD_READ32) | \ 205 (1 << MC_CMD_WRITE32) | \ 206 (1 << MC_CMD_COPYCODE) | \ 207 (1 << MC_CMD_GET_VERSION), \ 208 0, 0, 0 } 209 210 #define MC_CMD_SENSOR_INFO_OUT_OFFSET_OFST(_x) \ 211 (MC_CMD_SENSOR_ENTRY_OFST + (_x)) 212 213 #define MC_CMD_DBI_WRITE_IN_ADDRESS_OFST(n) ( \ 214 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST+ \ 215 MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST)+ \ 216 ((n)*MC_CMD_DBIWROP_TYPEDEF_LEN)) 217 218 #define MC_CMD_DBI_WRITE_IN_BYTE_MASK_OFST(n) ( \ 219 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST+ \ 220 MC_CMD_DBIWROP_TYPEDEF_BYTE_MASK_OFST)+ \ 221 ((n)*MC_CMD_DBIWROP_TYPEDEF_LEN)) 222 223 #define MC_CMD_DBI_WRITE_IN_VALUE_OFST(n) ( \ 224 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST+ \ 225 MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST)+ \ 226 ((n)*MC_CMD_DBIWROP_TYPEDEF_LEN)) 227 228 229 #ifdef WITH_MCDI_V2 230 231 /* Version 2 adds an optional argument to error returns: the errno value 232 * may be followed by the (0-based) number of the first argument that 233 * could not be processed. 234 */ 235 #define MC_CMD_ERR_ARG_OFST 4 236 237 /* Try again */ 238 #define MC_CMD_ERR_EAGAIN 11 239 /* No space */ 240 #define MC_CMD_ERR_ENOSPC 28 241 242 #endif 243 244 /* MCDI_EVENT structuredef */ 245 #define MCDI_EVENT_LEN 8 246 #define MCDI_EVENT_CONT_LBN 32 247 #define MCDI_EVENT_CONT_WIDTH 1 248 #define MCDI_EVENT_LEVEL_LBN 33 249 #define MCDI_EVENT_LEVEL_WIDTH 3 250 #define MCDI_EVENT_LEVEL_INFO 0x0 /* enum */ 251 #define MCDI_EVENT_LEVEL_WARN 0x1 /* enum */ 252 #define MCDI_EVENT_LEVEL_ERR 0x2 /* enum */ 253 #define MCDI_EVENT_LEVEL_FATAL 0x3 /* enum */ 254 #define MCDI_EVENT_DATA_OFST 0 255 #define MCDI_EVENT_CMDDONE_SEQ_LBN 0 256 #define MCDI_EVENT_CMDDONE_SEQ_WIDTH 8 257 #define MCDI_EVENT_CMDDONE_DATALEN_LBN 8 258 #define MCDI_EVENT_CMDDONE_DATALEN_WIDTH 8 259 #define MCDI_EVENT_CMDDONE_ERRNO_LBN 16 260 #define MCDI_EVENT_CMDDONE_ERRNO_WIDTH 8 261 #define MCDI_EVENT_LINKCHANGE_LP_CAP_LBN 0 262 #define MCDI_EVENT_LINKCHANGE_LP_CAP_WIDTH 16 263 #define MCDI_EVENT_LINKCHANGE_SPEED_LBN 16 264 #define MCDI_EVENT_LINKCHANGE_SPEED_WIDTH 4 265 #define MCDI_EVENT_LINKCHANGE_SPEED_100M 0x1 /* enum */ 266 #define MCDI_EVENT_LINKCHANGE_SPEED_1G 0x2 /* enum */ 267 #define MCDI_EVENT_LINKCHANGE_SPEED_10G 0x3 /* enum */ 268 #define MCDI_EVENT_LINKCHANGE_FCNTL_LBN 20 269 #define MCDI_EVENT_LINKCHANGE_FCNTL_WIDTH 4 270 #define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_LBN 24 271 #define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_WIDTH 8 272 #define MCDI_EVENT_SENSOREVT_MONITOR_LBN 0 273 #define MCDI_EVENT_SENSOREVT_MONITOR_WIDTH 8 274 #define MCDI_EVENT_SENSOREVT_STATE_LBN 8 275 #define MCDI_EVENT_SENSOREVT_STATE_WIDTH 8 276 #define MCDI_EVENT_SENSOREVT_VALUE_LBN 16 277 #define MCDI_EVENT_SENSOREVT_VALUE_WIDTH 16 278 #define MCDI_EVENT_FWALERT_DATA_LBN 8 279 #define MCDI_EVENT_FWALERT_DATA_WIDTH 24 280 #define MCDI_EVENT_FWALERT_REASON_LBN 0 281 #define MCDI_EVENT_FWALERT_REASON_WIDTH 8 282 #define MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS 0x1 /* enum */ 283 #define MCDI_EVENT_FLR_VF_LBN 0 284 #define MCDI_EVENT_FLR_VF_WIDTH 8 285 #define MCDI_EVENT_TX_ERR_TXQ_LBN 0 286 #define MCDI_EVENT_TX_ERR_TXQ_WIDTH 12 287 #define MCDI_EVENT_TX_ERR_TYPE_LBN 12 288 #define MCDI_EVENT_TX_ERR_TYPE_WIDTH 4 289 #define MCDI_EVENT_TX_ERR_DL_FAIL 0x1 /* enum */ 290 #define MCDI_EVENT_TX_ERR_NO_EOP 0x2 /* enum */ 291 #define MCDI_EVENT_TX_ERR_2BIG 0x3 /* enum */ 292 #define MCDI_EVENT_TX_ERR_INFO_LBN 16 293 #define MCDI_EVENT_TX_ERR_INFO_WIDTH 16 294 #define MCDI_EVENT_TX_FLUSH_TXQ_LBN 0 295 #define MCDI_EVENT_TX_FLUSH_TXQ_WIDTH 12 296 #define MCDI_EVENT_DATA_LBN 0 297 #define MCDI_EVENT_DATA_WIDTH 32 298 #define MCDI_EVENT_SRC_LBN 36 299 #define MCDI_EVENT_SRC_WIDTH 8 300 #define MCDI_EVENT_EV_CODE_LBN 60 301 #define MCDI_EVENT_EV_CODE_WIDTH 4 302 #define MCDI_EVENT_CODE_LBN 44 303 #define MCDI_EVENT_CODE_WIDTH 8 304 #define MCDI_EVENT_CODE_BADSSERT 0x1 /* enum */ 305 #define MCDI_EVENT_CODE_PMNOTICE 0x2 /* enum */ 306 #define MCDI_EVENT_CODE_CMDDONE 0x3 /* enum */ 307 #define MCDI_EVENT_CODE_LINKCHANGE 0x4 /* enum */ 308 #define MCDI_EVENT_CODE_SENSOREVT 0x5 /* enum */ 309 #define MCDI_EVENT_CODE_SCHEDERR 0x6 /* enum */ 310 #define MCDI_EVENT_CODE_REBOOT 0x7 /* enum */ 311 #define MCDI_EVENT_CODE_MAC_STATS_DMA 0x8 /* enum */ 312 #define MCDI_EVENT_CODE_FWALERT 0x9 /* enum */ 313 #define MCDI_EVENT_CODE_FLR 0xa /* enum */ 314 #define MCDI_EVENT_CODE_TX_ERR 0xb /* enum */ 315 #define MCDI_EVENT_CODE_TX_FLUSH 0xc /* enum */ 316 #define MCDI_EVENT_CMDDONE_DATA_OFST 0 317 #define MCDI_EVENT_CMDDONE_DATA_LBN 0 318 #define MCDI_EVENT_CMDDONE_DATA_WIDTH 32 319 #define MCDI_EVENT_LINKCHANGE_DATA_OFST 0 320 #define MCDI_EVENT_LINKCHANGE_DATA_LBN 0 321 #define MCDI_EVENT_LINKCHANGE_DATA_WIDTH 32 322 #define MCDI_EVENT_SENSOREVT_DATA_OFST 0 323 #define MCDI_EVENT_SENSOREVT_DATA_LBN 0 324 #define MCDI_EVENT_SENSOREVT_DATA_WIDTH 32 325 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_OFST 0 326 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_LBN 0 327 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_WIDTH 32 328 #define MCDI_EVENT_TX_ERR_DATA_OFST 0 329 #define MCDI_EVENT_TX_ERR_DATA_LBN 0 330 #define MCDI_EVENT_TX_ERR_DATA_WIDTH 32 331 332 333 /***********************************/ 334 /* MC_CMD_READ32 335 * Read multiple 32byte words from MC memory. 336 */ 337 #define MC_CMD_READ32 0x1 338 339 /* MC_CMD_READ32_IN msgrequest */ 340 #define MC_CMD_READ32_IN_LEN 8 341 #define MC_CMD_READ32_IN_ADDR_OFST 0 342 #define MC_CMD_READ32_IN_NUMWORDS_OFST 4 343 344 /* MC_CMD_READ32_OUT msgresponse */ 345 #define MC_CMD_READ32_OUT_LENMIN 4 346 #define MC_CMD_READ32_OUT_LENMAX 252 347 #define MC_CMD_READ32_OUT_LEN(num) (0+4*(num)) 348 #define MC_CMD_READ32_OUT_BUFFER_OFST 0 349 #define MC_CMD_READ32_OUT_BUFFER_LEN 4 350 #define MC_CMD_READ32_OUT_BUFFER_MINNUM 1 351 #define MC_CMD_READ32_OUT_BUFFER_MAXNUM 63 352 353 354 /***********************************/ 355 /* MC_CMD_WRITE32 356 * Write multiple 32byte words to MC memory. 357 */ 358 #define MC_CMD_WRITE32 0x2 359 360 /* MC_CMD_WRITE32_IN msgrequest */ 361 #define MC_CMD_WRITE32_IN_LENMIN 8 362 #define MC_CMD_WRITE32_IN_LENMAX 252 363 #define MC_CMD_WRITE32_IN_LEN(num) (4+4*(num)) 364 #define MC_CMD_WRITE32_IN_ADDR_OFST 0 365 #define MC_CMD_WRITE32_IN_BUFFER_OFST 4 366 #define MC_CMD_WRITE32_IN_BUFFER_LEN 4 367 #define MC_CMD_WRITE32_IN_BUFFER_MINNUM 1 368 #define MC_CMD_WRITE32_IN_BUFFER_MAXNUM 62 369 370 /* MC_CMD_WRITE32_OUT msgresponse */ 371 #define MC_CMD_WRITE32_OUT_LEN 0 372 373 374 /***********************************/ 375 /* MC_CMD_COPYCODE 376 * Copy MC code between two locations and jump. 377 */ 378 #define MC_CMD_COPYCODE 0x3 379 380 /* MC_CMD_COPYCODE_IN msgrequest */ 381 #define MC_CMD_COPYCODE_IN_LEN 16 382 #define MC_CMD_COPYCODE_IN_SRC_ADDR_OFST 0 383 #define MC_CMD_COPYCODE_IN_DEST_ADDR_OFST 4 384 #define MC_CMD_COPYCODE_IN_NUMWORDS_OFST 8 385 #define MC_CMD_COPYCODE_IN_JUMP_OFST 12 386 #define MC_CMD_COPYCODE_JUMP_NONE 0x1 /* enum */ 387 388 /* MC_CMD_COPYCODE_OUT msgresponse */ 389 #define MC_CMD_COPYCODE_OUT_LEN 0 390 391 392 /***********************************/ 393 /* MC_CMD_SET_FUNC 394 */ 395 #define MC_CMD_SET_FUNC 0x4 396 397 /* MC_CMD_SET_FUNC_IN msgrequest */ 398 #define MC_CMD_SET_FUNC_IN_LEN 4 399 #define MC_CMD_SET_FUNC_IN_FUNC_OFST 0 400 401 /* MC_CMD_SET_FUNC_OUT msgresponse */ 402 #define MC_CMD_SET_FUNC_OUT_LEN 0 403 404 405 /***********************************/ 406 /* MC_CMD_GET_BOOT_STATUS 407 */ 408 #define MC_CMD_GET_BOOT_STATUS 0x5 409 410 /* MC_CMD_GET_BOOT_STATUS_IN msgrequest */ 411 #define MC_CMD_GET_BOOT_STATUS_IN_LEN 0 412 413 /* MC_CMD_GET_BOOT_STATUS_OUT msgresponse */ 414 #define MC_CMD_GET_BOOT_STATUS_OUT_LEN 8 415 #define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_OFST 0 416 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_OFST 4 417 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_LBN 0 418 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_WIDTH 1 419 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_LBN 1 420 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_WIDTH 1 421 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_LBN 2 422 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_WIDTH 1 423 424 425 /***********************************/ 426 /* MC_CMD_GET_ASSERTS 427 * Get and clear any assertion status. 428 */ 429 #define MC_CMD_GET_ASSERTS 0x6 430 431 /* MC_CMD_GET_ASSERTS_IN msgrequest */ 432 #define MC_CMD_GET_ASSERTS_IN_LEN 4 433 #define MC_CMD_GET_ASSERTS_IN_CLEAR_OFST 0 434 435 /* MC_CMD_GET_ASSERTS_OUT msgresponse */ 436 #define MC_CMD_GET_ASSERTS_OUT_LEN 140 437 #define MC_CMD_GET_ASSERTS_OUT_GLOBAL_FLAGS_OFST 0 438 #define MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1 /* enum */ 439 #define MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2 /* enum */ 440 #define MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3 /* enum */ 441 #define MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4 /* enum */ 442 #define MC_CMD_GET_ASSERTS_OUT_SAVED_PC_OFFS_OFST 4 443 #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_OFST 8 444 #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_LEN 4 445 #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_NUM 31 446 #define MC_CMD_GET_ASSERTS_OUT_THREAD_OFFS_OFST 132 447 #define MC_CMD_GET_ASSERTS_OUT_RESERVED_OFST 136 448 449 450 /***********************************/ 451 /* MC_CMD_LOG_CTRL 452 * Configure the output stream for various events and messages. 453 */ 454 #define MC_CMD_LOG_CTRL 0x7 455 456 /* MC_CMD_LOG_CTRL_IN msgrequest */ 457 #define MC_CMD_LOG_CTRL_IN_LEN 8 458 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_OFST 0 459 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_UART 0x1 /* enum */ 460 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ 0x2 /* enum */ 461 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ_OFST 4 462 463 /* MC_CMD_LOG_CTRL_OUT msgresponse */ 464 #define MC_CMD_LOG_CTRL_OUT_LEN 0 465 466 467 /***********************************/ 468 /* MC_CMD_GET_VERSION 469 * Get version information about the MC firmware. 470 */ 471 #define MC_CMD_GET_VERSION 0x8 472 473 /* MC_CMD_GET_VERSION_IN msgrequest */ 474 #define MC_CMD_GET_VERSION_IN_LEN 0 475 476 /* MC_CMD_GET_VERSION_V0_OUT msgresponse */ 477 #define MC_CMD_GET_VERSION_V0_OUT_LEN 4 478 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 479 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_ANY 0xffffffff /* enum */ 480 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_BOOTROM 0xb0070000 /* enum */ 481 482 /* MC_CMD_GET_VERSION_OUT msgresponse */ 483 #define MC_CMD_GET_VERSION_OUT_LEN 32 484 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */ 485 /* Enum values, see field(s): */ 486 /* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */ 487 #define MC_CMD_GET_VERSION_OUT_PCOL_OFST 4 488 #define MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_OFST 8 489 #define MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_LEN 16 490 #define MC_CMD_GET_VERSION_OUT_VERSION_OFST 24 491 #define MC_CMD_GET_VERSION_OUT_VERSION_LEN 8 492 #define MC_CMD_GET_VERSION_OUT_VERSION_LO_OFST 24 493 #define MC_CMD_GET_VERSION_OUT_VERSION_HI_OFST 28 494 495 496 /***********************************/ 497 /* MC_CMD_CSR_READ32 498 * Read 32bit words from the indirect memory map. 499 */ 500 #define MC_CMD_CSR_READ32 0xc 501 502 /* MC_CMD_CSR_READ32_IN msgrequest */ 503 #define MC_CMD_CSR_READ32_IN_LEN 12 504 #define MC_CMD_CSR_READ32_IN_ADDR_OFST 0 505 #define MC_CMD_CSR_READ32_IN_STEP_OFST 4 506 #define MC_CMD_CSR_READ32_IN_NUMWORDS_OFST 8 507 508 /* MC_CMD_CSR_READ32_OUT msgresponse */ 509 #define MC_CMD_CSR_READ32_OUT_LENMIN 4 510 #define MC_CMD_CSR_READ32_OUT_LENMAX 252 511 #define MC_CMD_CSR_READ32_OUT_LEN(num) (0+4*(num)) 512 #define MC_CMD_CSR_READ32_OUT_BUFFER_OFST 0 513 #define MC_CMD_CSR_READ32_OUT_BUFFER_LEN 4 514 #define MC_CMD_CSR_READ32_OUT_BUFFER_MINNUM 1 515 #define MC_CMD_CSR_READ32_OUT_BUFFER_MAXNUM 63 516 517 518 /***********************************/ 519 /* MC_CMD_CSR_WRITE32 520 * Write 32bit dwords to the indirect memory map. 521 */ 522 #define MC_CMD_CSR_WRITE32 0xd 523 524 /* MC_CMD_CSR_WRITE32_IN msgrequest */ 525 #define MC_CMD_CSR_WRITE32_IN_LENMIN 12 526 #define MC_CMD_CSR_WRITE32_IN_LENMAX 252 527 #define MC_CMD_CSR_WRITE32_IN_LEN(num) (8+4*(num)) 528 #define MC_CMD_CSR_WRITE32_IN_ADDR_OFST 0 529 #define MC_CMD_CSR_WRITE32_IN_STEP_OFST 4 530 #define MC_CMD_CSR_WRITE32_IN_BUFFER_OFST 8 531 #define MC_CMD_CSR_WRITE32_IN_BUFFER_LEN 4 532 #define MC_CMD_CSR_WRITE32_IN_BUFFER_MINNUM 1 533 #define MC_CMD_CSR_WRITE32_IN_BUFFER_MAXNUM 61 534 535 /* MC_CMD_CSR_WRITE32_OUT msgresponse */ 536 #define MC_CMD_CSR_WRITE32_OUT_LEN 4 537 #define MC_CMD_CSR_WRITE32_OUT_STATUS_OFST 0 538 539 540 /***********************************/ 541 /* MC_CMD_STACKINFO 542 * Get stack information. 543 */ 544 #define MC_CMD_STACKINFO 0xf 545 546 /* MC_CMD_STACKINFO_IN msgrequest */ 547 #define MC_CMD_STACKINFO_IN_LEN 0 548 549 /* MC_CMD_STACKINFO_OUT msgresponse */ 550 #define MC_CMD_STACKINFO_OUT_LENMIN 12 551 #define MC_CMD_STACKINFO_OUT_LENMAX 252 552 #define MC_CMD_STACKINFO_OUT_LEN(num) (0+12*(num)) 553 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_OFST 0 554 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_LEN 12 555 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_MINNUM 1 556 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_MAXNUM 21 557 558 559 /***********************************/ 560 /* MC_CMD_MDIO_READ 561 * MDIO register read. 562 */ 563 #define MC_CMD_MDIO_READ 0x10 564 565 /* MC_CMD_MDIO_READ_IN msgrequest */ 566 #define MC_CMD_MDIO_READ_IN_LEN 16 567 #define MC_CMD_MDIO_READ_IN_BUS_OFST 0 568 #define MC_CMD_MDIO_BUS_INTERNAL 0x0 /* enum */ 569 #define MC_CMD_MDIO_BUS_EXTERNAL 0x1 /* enum */ 570 #define MC_CMD_MDIO_READ_IN_PRTAD_OFST 4 571 #define MC_CMD_MDIO_READ_IN_DEVAD_OFST 8 572 #define MC_CMD_MDIO_CLAUSE22 0x20 /* enum */ 573 #define MC_CMD_MDIO_READ_IN_ADDR_OFST 12 574 575 /* MC_CMD_MDIO_READ_OUT msgresponse */ 576 #define MC_CMD_MDIO_READ_OUT_LEN 8 577 #define MC_CMD_MDIO_READ_OUT_VALUE_OFST 0 578 #define MC_CMD_MDIO_READ_OUT_STATUS_OFST 4 579 #define MC_CMD_MDIO_STATUS_GOOD 0x8 /* enum */ 580 581 582 /***********************************/ 583 /* MC_CMD_MDIO_WRITE 584 * MDIO register write. 585 */ 586 #define MC_CMD_MDIO_WRITE 0x11 587 588 /* MC_CMD_MDIO_WRITE_IN msgrequest */ 589 #define MC_CMD_MDIO_WRITE_IN_LEN 20 590 #define MC_CMD_MDIO_WRITE_IN_BUS_OFST 0 591 /* MC_CMD_MDIO_BUS_INTERNAL 0x0 */ 592 /* MC_CMD_MDIO_BUS_EXTERNAL 0x1 */ 593 #define MC_CMD_MDIO_WRITE_IN_PRTAD_OFST 4 594 #define MC_CMD_MDIO_WRITE_IN_DEVAD_OFST 8 595 /* MC_CMD_MDIO_CLAUSE22 0x20 */ 596 #define MC_CMD_MDIO_WRITE_IN_ADDR_OFST 12 597 #define MC_CMD_MDIO_WRITE_IN_VALUE_OFST 16 598 599 /* MC_CMD_MDIO_WRITE_OUT msgresponse */ 600 #define MC_CMD_MDIO_WRITE_OUT_LEN 4 601 #define MC_CMD_MDIO_WRITE_OUT_STATUS_OFST 0 602 /* MC_CMD_MDIO_STATUS_GOOD 0x8 */ 603 604 605 /***********************************/ 606 /* MC_CMD_DBI_WRITE 607 * Write DBI register(s). 608 */ 609 #define MC_CMD_DBI_WRITE 0x12 610 611 /* MC_CMD_DBI_WRITE_IN msgrequest */ 612 #define MC_CMD_DBI_WRITE_IN_LENMIN 12 613 #define MC_CMD_DBI_WRITE_IN_LENMAX 252 614 #define MC_CMD_DBI_WRITE_IN_LEN(num) (0+12*(num)) 615 #define MC_CMD_DBI_WRITE_IN_DBIWROP_OFST 0 616 #define MC_CMD_DBI_WRITE_IN_DBIWROP_LEN 12 617 #define MC_CMD_DBI_WRITE_IN_DBIWROP_MINNUM 1 618 #define MC_CMD_DBI_WRITE_IN_DBIWROP_MAXNUM 21 619 620 /* MC_CMD_DBI_WRITE_OUT msgresponse */ 621 #define MC_CMD_DBI_WRITE_OUT_LEN 0 622 623 /* MC_CMD_DBIWROP_TYPEDEF structuredef */ 624 #define MC_CMD_DBIWROP_TYPEDEF_LEN 12 625 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST 0 626 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_LBN 0 627 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_WIDTH 32 628 #define MC_CMD_DBIWROP_TYPEDEF_BYTE_MASK_OFST 4 629 #define MC_CMD_DBIWROP_TYPEDEF_BYTE_MASK_LBN 32 630 #define MC_CMD_DBIWROP_TYPEDEF_BYTE_MASK_WIDTH 32 631 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST 8 632 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_LBN 64 633 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_WIDTH 32 634 635 636 /***********************************/ 637 /* MC_CMD_PORT_READ32 638 * Read a 32-bit register from the indirect port register map. 639 */ 640 #define MC_CMD_PORT_READ32 0x14 641 642 /* MC_CMD_PORT_READ32_IN msgrequest */ 643 #define MC_CMD_PORT_READ32_IN_LEN 4 644 #define MC_CMD_PORT_READ32_IN_ADDR_OFST 0 645 646 /* MC_CMD_PORT_READ32_OUT msgresponse */ 647 #define MC_CMD_PORT_READ32_OUT_LEN 8 648 #define MC_CMD_PORT_READ32_OUT_VALUE_OFST 0 649 #define MC_CMD_PORT_READ32_OUT_STATUS_OFST 4 650 651 652 /***********************************/ 653 /* MC_CMD_PORT_WRITE32 654 * Write a 32-bit register to the indirect port register map. 655 */ 656 #define MC_CMD_PORT_WRITE32 0x15 657 658 /* MC_CMD_PORT_WRITE32_IN msgrequest */ 659 #define MC_CMD_PORT_WRITE32_IN_LEN 8 660 #define MC_CMD_PORT_WRITE32_IN_ADDR_OFST 0 661 #define MC_CMD_PORT_WRITE32_IN_VALUE_OFST 4 662 663 /* MC_CMD_PORT_WRITE32_OUT msgresponse */ 664 #define MC_CMD_PORT_WRITE32_OUT_LEN 4 665 #define MC_CMD_PORT_WRITE32_OUT_STATUS_OFST 0 666 667 668 /***********************************/ 669 /* MC_CMD_PORT_READ128 670 * Read a 128-bit register from the indirect port register map. 671 */ 672 #define MC_CMD_PORT_READ128 0x16 673 674 /* MC_CMD_PORT_READ128_IN msgrequest */ 675 #define MC_CMD_PORT_READ128_IN_LEN 4 676 #define MC_CMD_PORT_READ128_IN_ADDR_OFST 0 677 678 /* MC_CMD_PORT_READ128_OUT msgresponse */ 679 #define MC_CMD_PORT_READ128_OUT_LEN 20 680 #define MC_CMD_PORT_READ128_OUT_VALUE_OFST 0 681 #define MC_CMD_PORT_READ128_OUT_VALUE_LEN 16 682 #define MC_CMD_PORT_READ128_OUT_STATUS_OFST 16 683 684 685 /***********************************/ 686 /* MC_CMD_PORT_WRITE128 687 * Write a 128-bit register to the indirect port register map. 688 */ 689 #define MC_CMD_PORT_WRITE128 0x17 690 691 /* MC_CMD_PORT_WRITE128_IN msgrequest */ 692 #define MC_CMD_PORT_WRITE128_IN_LEN 20 693 #define MC_CMD_PORT_WRITE128_IN_ADDR_OFST 0 694 #define MC_CMD_PORT_WRITE128_IN_VALUE_OFST 4 695 #define MC_CMD_PORT_WRITE128_IN_VALUE_LEN 16 696 697 /* MC_CMD_PORT_WRITE128_OUT msgresponse */ 698 #define MC_CMD_PORT_WRITE128_OUT_LEN 4 699 #define MC_CMD_PORT_WRITE128_OUT_STATUS_OFST 0 700 701 702 /***********************************/ 703 /* MC_CMD_GET_BOARD_CFG 704 * Returns the MC firmware configuration structure. 705 */ 706 #define MC_CMD_GET_BOARD_CFG 0x18 707 708 /* MC_CMD_GET_BOARD_CFG_IN msgrequest */ 709 #define MC_CMD_GET_BOARD_CFG_IN_LEN 0 710 711 /* MC_CMD_GET_BOARD_CFG_OUT msgresponse */ 712 #define MC_CMD_GET_BOARD_CFG_OUT_LEN 96 713 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_OFST 0 714 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_OFST 4 715 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_LEN 32 716 #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT0_OFST 36 717 #define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_LBN 0x0 /* enum */ 718 #define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_WIDTH 0x1 /* enum */ 719 #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT1_OFST 40 720 /* Enum values, see field(s): */ 721 /* CAPABILITIES_PORT0 */ 722 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_OFST 44 723 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_LEN 6 724 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_OFST 50 725 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_LEN 6 726 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT0_OFST 56 727 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT1_OFST 60 728 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT0_OFST 64 729 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT1_OFST 68 730 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_OFST 72 731 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_LEN 2 732 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_NUM 12 733 734 735 /***********************************/ 736 /* MC_CMD_DBI_READX 737 * Read DBI register(s). 738 */ 739 #define MC_CMD_DBI_READX 0x19 740 741 /* MC_CMD_DBI_READX_IN msgrequest */ 742 #define MC_CMD_DBI_READX_IN_LENMIN 8 743 #define MC_CMD_DBI_READX_IN_LENMAX 248 744 #define MC_CMD_DBI_READX_IN_LEN(num) (0+8*(num)) 745 #define MC_CMD_DBI_READX_IN_DBIRDOP_OFST 0 746 #define MC_CMD_DBI_READX_IN_DBIRDOP_LEN 8 747 #define MC_CMD_DBI_READX_IN_DBIRDOP_LO_OFST 0 748 #define MC_CMD_DBI_READX_IN_DBIRDOP_HI_OFST 4 749 #define MC_CMD_DBI_READX_IN_DBIRDOP_MINNUM 1 750 #define MC_CMD_DBI_READX_IN_DBIRDOP_MAXNUM 31 751 752 /* MC_CMD_DBI_READX_OUT msgresponse */ 753 #define MC_CMD_DBI_READX_OUT_LENMIN 4 754 #define MC_CMD_DBI_READX_OUT_LENMAX 252 755 #define MC_CMD_DBI_READX_OUT_LEN(num) (0+4*(num)) 756 #define MC_CMD_DBI_READX_OUT_VALUE_OFST 0 757 #define MC_CMD_DBI_READX_OUT_VALUE_LEN 4 758 #define MC_CMD_DBI_READX_OUT_VALUE_MINNUM 1 759 #define MC_CMD_DBI_READX_OUT_VALUE_MAXNUM 63 760 761 762 /***********************************/ 763 /* MC_CMD_SET_RAND_SEED 764 * Set the 16byte seed for the MC psuedo-random generator. 765 */ 766 #define MC_CMD_SET_RAND_SEED 0x1a 767 768 /* MC_CMD_SET_RAND_SEED_IN msgrequest */ 769 #define MC_CMD_SET_RAND_SEED_IN_LEN 16 770 #define MC_CMD_SET_RAND_SEED_IN_SEED_OFST 0 771 #define MC_CMD_SET_RAND_SEED_IN_SEED_LEN 16 772 773 /* MC_CMD_SET_RAND_SEED_OUT msgresponse */ 774 #define MC_CMD_SET_RAND_SEED_OUT_LEN 0 775 776 777 /***********************************/ 778 /* MC_CMD_LTSSM_HIST 779 * Retrieve the history of the PCIE LTSSM. 780 */ 781 #define MC_CMD_LTSSM_HIST 0x1b 782 783 /* MC_CMD_LTSSM_HIST_IN msgrequest */ 784 #define MC_CMD_LTSSM_HIST_IN_LEN 0 785 786 /* MC_CMD_LTSSM_HIST_OUT msgresponse */ 787 #define MC_CMD_LTSSM_HIST_OUT_LENMIN 0 788 #define MC_CMD_LTSSM_HIST_OUT_LENMAX 252 789 #define MC_CMD_LTSSM_HIST_OUT_LEN(num) (0+4*(num)) 790 #define MC_CMD_LTSSM_HIST_OUT_DATA_OFST 0 791 #define MC_CMD_LTSSM_HIST_OUT_DATA_LEN 4 792 #define MC_CMD_LTSSM_HIST_OUT_DATA_MINNUM 0 793 #define MC_CMD_LTSSM_HIST_OUT_DATA_MAXNUM 63 794 795 796 /***********************************/ 797 /* MC_CMD_DRV_ATTACH 798 * Inform MCPU that this port is managed on the host. 799 */ 800 #define MC_CMD_DRV_ATTACH 0x1c 801 802 /* MC_CMD_DRV_ATTACH_IN msgrequest */ 803 #define MC_CMD_DRV_ATTACH_IN_LEN 8 804 #define MC_CMD_DRV_ATTACH_IN_NEW_STATE_OFST 0 805 #define MC_CMD_DRV_ATTACH_IN_UPDATE_OFST 4 806 807 /* MC_CMD_DRV_ATTACH_OUT msgresponse */ 808 #define MC_CMD_DRV_ATTACH_OUT_LEN 4 809 #define MC_CMD_DRV_ATTACH_OUT_OLD_STATE_OFST 0 810 811 812 /***********************************/ 813 /* MC_CMD_NCSI_PROD 814 * Trigger an NC-SI event. 815 */ 816 #define MC_CMD_NCSI_PROD 0x1d 817 818 /* MC_CMD_NCSI_PROD_IN msgrequest */ 819 #define MC_CMD_NCSI_PROD_IN_LEN 4 820 #define MC_CMD_NCSI_PROD_IN_EVENTS_OFST 0 821 #define MC_CMD_NCSI_PROD_LINKCHANGE 0x0 /* enum */ 822 #define MC_CMD_NCSI_PROD_RESET 0x1 /* enum */ 823 #define MC_CMD_NCSI_PROD_DRVATTACH 0x2 /* enum */ 824 #define MC_CMD_NCSI_PROD_IN_LINKCHANGE_LBN 0 825 #define MC_CMD_NCSI_PROD_IN_LINKCHANGE_WIDTH 1 826 #define MC_CMD_NCSI_PROD_IN_RESET_LBN 1 827 #define MC_CMD_NCSI_PROD_IN_RESET_WIDTH 1 828 #define MC_CMD_NCSI_PROD_IN_DRVATTACH_LBN 2 829 #define MC_CMD_NCSI_PROD_IN_DRVATTACH_WIDTH 1 830 831 /* MC_CMD_NCSI_PROD_OUT msgresponse */ 832 #define MC_CMD_NCSI_PROD_OUT_LEN 0 833 834 835 /***********************************/ 836 /* MC_CMD_SHMUART 837 * Route UART output to circular buffer in shared memory instead. 838 */ 839 #define MC_CMD_SHMUART 0x1f 840 841 /* MC_CMD_SHMUART_IN msgrequest */ 842 #define MC_CMD_SHMUART_IN_LEN 4 843 #define MC_CMD_SHMUART_IN_FLAG_OFST 0 844 845 /* MC_CMD_SHMUART_OUT msgresponse */ 846 #define MC_CMD_SHMUART_OUT_LEN 0 847 848 849 /***********************************/ 850 /* MC_CMD_PORT_RESET 851 * Generic per-port reset. 852 */ 853 #define MC_CMD_PORT_RESET 0x20 854 855 /* MC_CMD_PORT_RESET_IN msgrequest */ 856 #define MC_CMD_PORT_RESET_IN_LEN 0 857 858 /* MC_CMD_PORT_RESET_OUT msgresponse */ 859 #define MC_CMD_PORT_RESET_OUT_LEN 0 860 861 862 /***********************************/ 863 /* MC_CMD_PCIE_CREDITS 864 * Read instantaneous and minimum flow control thresholds. 865 */ 866 #define MC_CMD_PCIE_CREDITS 0x21 867 868 /* MC_CMD_PCIE_CREDITS_IN msgrequest */ 869 #define MC_CMD_PCIE_CREDITS_IN_LEN 8 870 #define MC_CMD_PCIE_CREDITS_IN_POLL_PERIOD_OFST 0 871 #define MC_CMD_PCIE_CREDITS_IN_WIPE_OFST 4 872 873 /* MC_CMD_PCIE_CREDITS_OUT msgresponse */ 874 #define MC_CMD_PCIE_CREDITS_OUT_LEN 16 875 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_OFST 0 876 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_LEN 2 877 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_OFST 2 878 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_LEN 2 879 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_OFST 4 880 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_LEN 2 881 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_OFST 6 882 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_LEN 2 883 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_OFST 8 884 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_LEN 2 885 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_OFST 10 886 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_LEN 2 887 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_OFST 12 888 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_LEN 2 889 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_OFST 14 890 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_LEN 2 891 892 893 /***********************************/ 894 /* MC_CMD_RXD_MONITOR 895 * Get histogram of RX queue fill level. 896 */ 897 #define MC_CMD_RXD_MONITOR 0x22 898 899 /* MC_CMD_RXD_MONITOR_IN msgrequest */ 900 #define MC_CMD_RXD_MONITOR_IN_LEN 12 901 #define MC_CMD_RXD_MONITOR_IN_QID_OFST 0 902 #define MC_CMD_RXD_MONITOR_IN_POLL_PERIOD_OFST 4 903 #define MC_CMD_RXD_MONITOR_IN_WIPE_OFST 8 904 905 /* MC_CMD_RXD_MONITOR_OUT msgresponse */ 906 #define MC_CMD_RXD_MONITOR_OUT_LEN 80 907 #define MC_CMD_RXD_MONITOR_OUT_QID_OFST 0 908 #define MC_CMD_RXD_MONITOR_OUT_RING_FILL_OFST 4 909 #define MC_CMD_RXD_MONITOR_OUT_CACHE_FILL_OFST 8 910 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_1_OFST 12 911 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_2_OFST 16 912 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_4_OFST 20 913 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_8_OFST 24 914 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_16_OFST 28 915 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_32_OFST 32 916 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_64_OFST 36 917 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_128_OFST 40 918 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_256_OFST 44 919 #define MC_CMD_RXD_MONITOR_OUT_RING_GE_256_OFST 48 920 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_1_OFST 52 921 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_2_OFST 56 922 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_4_OFST 60 923 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_8_OFST 64 924 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_16_OFST 68 925 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_32_OFST 72 926 #define MC_CMD_RXD_MONITOR_OUT_CACHE_GE_32_OFST 76 927 928 929 /***********************************/ 930 /* MC_CMD_PUTS 931 * puts(3) implementation over MCDI 932 */ 933 #define MC_CMD_PUTS 0x23 934 935 /* MC_CMD_PUTS_IN msgrequest */ 936 #define MC_CMD_PUTS_IN_LENMIN 13 937 #define MC_CMD_PUTS_IN_LENMAX 255 938 #define MC_CMD_PUTS_IN_LEN(num) (12+1*(num)) 939 #define MC_CMD_PUTS_IN_DEST_OFST 0 940 #define MC_CMD_PUTS_IN_UART_LBN 0 941 #define MC_CMD_PUTS_IN_UART_WIDTH 1 942 #define MC_CMD_PUTS_IN_PORT_LBN 1 943 #define MC_CMD_PUTS_IN_PORT_WIDTH 1 944 #define MC_CMD_PUTS_IN_DHOST_OFST 4 945 #define MC_CMD_PUTS_IN_DHOST_LEN 6 946 #define MC_CMD_PUTS_IN_STRING_OFST 12 947 #define MC_CMD_PUTS_IN_STRING_LEN 1 948 #define MC_CMD_PUTS_IN_STRING_MINNUM 1 949 #define MC_CMD_PUTS_IN_STRING_MAXNUM 243 950 951 /* MC_CMD_PUTS_OUT msgresponse */ 952 #define MC_CMD_PUTS_OUT_LEN 0 953 954 955 /***********************************/ 956 /* MC_CMD_GET_PHY_CFG 957 * Report PHY configuration. 958 */ 959 #define MC_CMD_GET_PHY_CFG 0x24 960 961 /* MC_CMD_GET_PHY_CFG_IN msgrequest */ 962 #define MC_CMD_GET_PHY_CFG_IN_LEN 0 963 964 /* MC_CMD_GET_PHY_CFG_OUT msgresponse */ 965 #define MC_CMD_GET_PHY_CFG_OUT_LEN 72 966 #define MC_CMD_GET_PHY_CFG_OUT_FLAGS_OFST 0 967 #define MC_CMD_GET_PHY_CFG_OUT_PRESENT_LBN 0 968 #define MC_CMD_GET_PHY_CFG_OUT_PRESENT_WIDTH 1 969 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_LBN 1 970 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_WIDTH 1 971 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_LBN 2 972 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_WIDTH 1 973 #define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_LBN 3 974 #define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_WIDTH 1 975 #define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_LBN 4 976 #define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_WIDTH 1 977 #define MC_CMD_GET_PHY_CFG_OUT_TXDIS_LBN 5 978 #define MC_CMD_GET_PHY_CFG_OUT_TXDIS_WIDTH 1 979 #define MC_CMD_GET_PHY_CFG_OUT_BIST_LBN 6 980 #define MC_CMD_GET_PHY_CFG_OUT_BIST_WIDTH 1 981 #define MC_CMD_GET_PHY_CFG_OUT_TYPE_OFST 4 982 #define MC_CMD_GET_PHY_CFG_OUT_SUPPORTED_CAP_OFST 8 983 #define MC_CMD_PHY_CAP_10HDX_LBN 1 984 #define MC_CMD_PHY_CAP_10HDX_WIDTH 1 985 #define MC_CMD_PHY_CAP_10FDX_LBN 2 986 #define MC_CMD_PHY_CAP_10FDX_WIDTH 1 987 #define MC_CMD_PHY_CAP_100HDX_LBN 3 988 #define MC_CMD_PHY_CAP_100HDX_WIDTH 1 989 #define MC_CMD_PHY_CAP_100FDX_LBN 4 990 #define MC_CMD_PHY_CAP_100FDX_WIDTH 1 991 #define MC_CMD_PHY_CAP_1000HDX_LBN 5 992 #define MC_CMD_PHY_CAP_1000HDX_WIDTH 1 993 #define MC_CMD_PHY_CAP_1000FDX_LBN 6 994 #define MC_CMD_PHY_CAP_1000FDX_WIDTH 1 995 #define MC_CMD_PHY_CAP_10000FDX_LBN 7 996 #define MC_CMD_PHY_CAP_10000FDX_WIDTH 1 997 #define MC_CMD_PHY_CAP_PAUSE_LBN 8 998 #define MC_CMD_PHY_CAP_PAUSE_WIDTH 1 999 #define MC_CMD_PHY_CAP_ASYM_LBN 9 1000 #define MC_CMD_PHY_CAP_ASYM_WIDTH 1 1001 #define MC_CMD_PHY_CAP_AN_LBN 10 1002 #define MC_CMD_PHY_CAP_AN_WIDTH 1 1003 #define MC_CMD_GET_PHY_CFG_OUT_CHANNEL_OFST 12 1004 #define MC_CMD_GET_PHY_CFG_OUT_PRT_OFST 16 1005 #define MC_CMD_GET_PHY_CFG_OUT_STATS_MASK_OFST 20 1006 #define MC_CMD_GET_PHY_CFG_OUT_NAME_OFST 24 1007 #define MC_CMD_GET_PHY_CFG_OUT_NAME_LEN 20 1008 #define MC_CMD_GET_PHY_CFG_OUT_MEDIA_TYPE_OFST 44 1009 #define MC_CMD_MEDIA_XAUI 0x1 /* enum */ 1010 #define MC_CMD_MEDIA_CX4 0x2 /* enum */ 1011 #define MC_CMD_MEDIA_KX4 0x3 /* enum */ 1012 #define MC_CMD_MEDIA_XFP 0x4 /* enum */ 1013 #define MC_CMD_MEDIA_SFP_PLUS 0x5 /* enum */ 1014 #define MC_CMD_MEDIA_BASE_T 0x6 /* enum */ 1015 #define MC_CMD_GET_PHY_CFG_OUT_MMD_MASK_OFST 48 1016 #define MC_CMD_MMD_CLAUSE22 0x0 /* enum */ 1017 #define MC_CMD_MMD_CLAUSE45_PMAPMD 0x1 /* enum */ 1018 #define MC_CMD_MMD_CLAUSE45_WIS 0x2 /* enum */ 1019 #define MC_CMD_MMD_CLAUSE45_PCS 0x3 /* enum */ 1020 #define MC_CMD_MMD_CLAUSE45_PHYXS 0x4 /* enum */ 1021 #define MC_CMD_MMD_CLAUSE45_DTEXS 0x5 /* enum */ 1022 #define MC_CMD_MMD_CLAUSE45_TC 0x6 /* enum */ 1023 #define MC_CMD_MMD_CLAUSE45_AN 0x7 /* enum */ 1024 #define MC_CMD_MMD_CLAUSE45_C22EXT 0x1d /* enum */ 1025 #define MC_CMD_MMD_CLAUSE45_VEND1 0x1e /* enum */ 1026 #define MC_CMD_MMD_CLAUSE45_VEND2 0x1f /* enum */ 1027 #define MC_CMD_GET_PHY_CFG_OUT_REVISION_OFST 52 1028 #define MC_CMD_GET_PHY_CFG_OUT_REVISION_LEN 20 1029 1030 1031 /***********************************/ 1032 /* MC_CMD_START_BIST 1033 * Start a BIST test on the PHY. 1034 */ 1035 #define MC_CMD_START_BIST 0x25 1036 1037 /* MC_CMD_START_BIST_IN msgrequest */ 1038 #define MC_CMD_START_BIST_IN_LEN 4 1039 #define MC_CMD_START_BIST_IN_TYPE_OFST 0 1040 #define MC_CMD_PHY_BIST_CABLE_SHORT 0x1 /* enum */ 1041 #define MC_CMD_PHY_BIST_CABLE_LONG 0x2 /* enum */ 1042 #define MC_CMD_BPX_SERDES_BIST 0x3 /* enum */ 1043 #define MC_CMD_MC_LOOPBACK_BIST 0x4 /* enum */ 1044 #define MC_CMD_PHY_BIST 0x5 /* enum */ 1045 1046 /* MC_CMD_START_BIST_OUT msgresponse */ 1047 #define MC_CMD_START_BIST_OUT_LEN 0 1048 1049 1050 /***********************************/ 1051 /* MC_CMD_POLL_BIST 1052 * Poll for BIST completion. 1053 */ 1054 #define MC_CMD_POLL_BIST 0x26 1055 1056 /* MC_CMD_POLL_BIST_IN msgrequest */ 1057 #define MC_CMD_POLL_BIST_IN_LEN 0 1058 1059 /* MC_CMD_POLL_BIST_OUT msgresponse */ 1060 #define MC_CMD_POLL_BIST_OUT_LEN 8 1061 #define MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 1062 #define MC_CMD_POLL_BIST_RUNNING 0x1 /* enum */ 1063 #define MC_CMD_POLL_BIST_PASSED 0x2 /* enum */ 1064 #define MC_CMD_POLL_BIST_FAILED 0x3 /* enum */ 1065 #define MC_CMD_POLL_BIST_TIMEOUT 0x4 /* enum */ 1066 #define MC_CMD_POLL_BIST_OUT_PRIVATE_OFST 4 1067 1068 /* MC_CMD_POLL_BIST_OUT_SFT9001 msgresponse */ 1069 #define MC_CMD_POLL_BIST_OUT_SFT9001_LEN 36 1070 /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */ 1071 /* Enum values, see field(s): */ 1072 /* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */ 1073 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A_OFST 4 1074 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B_OFST 8 1075 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C_OFST 12 1076 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D_OFST 16 1077 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_A_OFST 20 1078 #define MC_CMD_POLL_BIST_SFT9001_PAIR_OK 0x1 /* enum */ 1079 #define MC_CMD_POLL_BIST_SFT9001_PAIR_OPEN 0x2 /* enum */ 1080 #define MC_CMD_POLL_BIST_SFT9001_INTRA_PAIR_SHORT 0x3 /* enum */ 1081 #define MC_CMD_POLL_BIST_SFT9001_INTER_PAIR_SHORT 0x4 /* enum */ 1082 #define MC_CMD_POLL_BIST_SFT9001_PAIR_BUSY 0x9 /* enum */ 1083 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_B_OFST 24 1084 /* Enum values, see field(s): */ 1085 /* CABLE_STATUS_A */ 1086 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_C_OFST 28 1087 /* Enum values, see field(s): */ 1088 /* CABLE_STATUS_A */ 1089 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_D_OFST 32 1090 /* Enum values, see field(s): */ 1091 /* CABLE_STATUS_A */ 1092 1093 /* MC_CMD_POLL_BIST_OUT_MRSFP msgresponse */ 1094 #define MC_CMD_POLL_BIST_OUT_MRSFP_LEN 8 1095 /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */ 1096 /* Enum values, see field(s): */ 1097 /* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */ 1098 #define MC_CMD_POLL_BIST_OUT_MRSFP_TEST_OFST 4 1099 #define MC_CMD_POLL_BIST_MRSFP_TEST_COMPLETE 0x0 /* enum */ 1100 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_WRITE 0x1 /* enum */ 1101 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_IO_EXP 0x2 /* enum */ 1102 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_MODULE 0x3 /* enum */ 1103 #define MC_CMD_POLL_BIST_MRSFP_TEST_IO_EXP_I2C_CONFIGURE 0x4 /* enum */ 1104 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_I2C_NO_CROSSTALK 0x5 /* enum */ 1105 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_PRESENCE 0x6 /* enum */ 1106 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_I2C_ACCESS 0x7 /* enum */ 1107 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_SANE_VALUE 0x8 /* enum */ 1108 1109 1110 /***********************************/ 1111 /* MC_CMD_FLUSH_RX_QUEUES 1112 * Flush receive queue(s). 1113 */ 1114 #define MC_CMD_FLUSH_RX_QUEUES 0x27 1115 1116 /* MC_CMD_FLUSH_RX_QUEUES_IN msgrequest */ 1117 #define MC_CMD_FLUSH_RX_QUEUES_IN_LENMIN 4 1118 #define MC_CMD_FLUSH_RX_QUEUES_IN_LENMAX 252 1119 #define MC_CMD_FLUSH_RX_QUEUES_IN_LEN(num) (0+4*(num)) 1120 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_OFST 0 1121 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_LEN 4 1122 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MINNUM 1 1123 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MAXNUM 63 1124 1125 /* MC_CMD_FLUSH_RX_QUEUES_OUT msgresponse */ 1126 #define MC_CMD_FLUSH_RX_QUEUES_OUT_LEN 0 1127 1128 1129 /***********************************/ 1130 /* MC_CMD_GET_LOOPBACK_MODES 1131 * Get port's loopback modes. 1132 */ 1133 #define MC_CMD_GET_LOOPBACK_MODES 0x28 1134 1135 /* MC_CMD_GET_LOOPBACK_MODES_IN msgrequest */ 1136 #define MC_CMD_GET_LOOPBACK_MODES_IN_LEN 0 1137 1138 /* MC_CMD_GET_LOOPBACK_MODES_OUT msgresponse */ 1139 #define MC_CMD_GET_LOOPBACK_MODES_OUT_LEN 32 1140 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_OFST 0 1141 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LEN 8 1142 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_OFST 0 1143 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_OFST 4 1144 #define MC_CMD_LOOPBACK_NONE 0x0 /* enum */ 1145 #define MC_CMD_LOOPBACK_DATA 0x1 /* enum */ 1146 #define MC_CMD_LOOPBACK_GMAC 0x2 /* enum */ 1147 #define MC_CMD_LOOPBACK_XGMII 0x3 /* enum */ 1148 #define MC_CMD_LOOPBACK_XGXS 0x4 /* enum */ 1149 #define MC_CMD_LOOPBACK_XAUI 0x5 /* enum */ 1150 #define MC_CMD_LOOPBACK_GMII 0x6 /* enum */ 1151 #define MC_CMD_LOOPBACK_SGMII 0x7 /* enum */ 1152 #define MC_CMD_LOOPBACK_XGBR 0x8 /* enum */ 1153 #define MC_CMD_LOOPBACK_XFI 0x9 /* enum */ 1154 #define MC_CMD_LOOPBACK_XAUI_FAR 0xa /* enum */ 1155 #define MC_CMD_LOOPBACK_GMII_FAR 0xb /* enum */ 1156 #define MC_CMD_LOOPBACK_SGMII_FAR 0xc /* enum */ 1157 #define MC_CMD_LOOPBACK_XFI_FAR 0xd /* enum */ 1158 #define MC_CMD_LOOPBACK_GPHY 0xe /* enum */ 1159 #define MC_CMD_LOOPBACK_PHYXS 0xf /* enum */ 1160 #define MC_CMD_LOOPBACK_PCS 0x10 /* enum */ 1161 #define MC_CMD_LOOPBACK_PMAPMD 0x11 /* enum */ 1162 #define MC_CMD_LOOPBACK_XPORT 0x12 /* enum */ 1163 #define MC_CMD_LOOPBACK_XGMII_WS 0x13 /* enum */ 1164 #define MC_CMD_LOOPBACK_XAUI_WS 0x14 /* enum */ 1165 #define MC_CMD_LOOPBACK_XAUI_WS_FAR 0x15 /* enum */ 1166 #define MC_CMD_LOOPBACK_XAUI_WS_NEAR 0x16 /* enum */ 1167 #define MC_CMD_LOOPBACK_GMII_WS 0x17 /* enum */ 1168 #define MC_CMD_LOOPBACK_XFI_WS 0x18 /* enum */ 1169 #define MC_CMD_LOOPBACK_XFI_WS_FAR 0x19 /* enum */ 1170 #define MC_CMD_LOOPBACK_PHYXS_WS 0x1a /* enum */ 1171 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_OFST 8 1172 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LEN 8 1173 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LO_OFST 8 1174 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_HI_OFST 12 1175 /* Enum values, see field(s): */ 1176 /* 100M */ 1177 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_OFST 16 1178 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LEN 8 1179 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LO_OFST 16 1180 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_HI_OFST 20 1181 /* Enum values, see field(s): */ 1182 /* 100M */ 1183 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_OFST 24 1184 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LEN 8 1185 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LO_OFST 24 1186 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_HI_OFST 28 1187 /* Enum values, see field(s): */ 1188 /* 100M */ 1189 1190 1191 /***********************************/ 1192 /* MC_CMD_GET_LINK 1193 * Read the unified MAC/PHY link state. 1194 */ 1195 #define MC_CMD_GET_LINK 0x29 1196 1197 /* MC_CMD_GET_LINK_IN msgrequest */ 1198 #define MC_CMD_GET_LINK_IN_LEN 0 1199 1200 /* MC_CMD_GET_LINK_OUT msgresponse */ 1201 #define MC_CMD_GET_LINK_OUT_LEN 28 1202 #define MC_CMD_GET_LINK_OUT_CAP_OFST 0 1203 #define MC_CMD_GET_LINK_OUT_LP_CAP_OFST 4 1204 #define MC_CMD_GET_LINK_OUT_LINK_SPEED_OFST 8 1205 #define MC_CMD_GET_LINK_OUT_LOOPBACK_MODE_OFST 12 1206 /* Enum values, see field(s): */ 1207 /* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */ 1208 #define MC_CMD_GET_LINK_OUT_FLAGS_OFST 16 1209 #define MC_CMD_GET_LINK_OUT_LINK_UP_LBN 0 1210 #define MC_CMD_GET_LINK_OUT_LINK_UP_WIDTH 1 1211 #define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_LBN 1 1212 #define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_WIDTH 1 1213 #define MC_CMD_GET_LINK_OUT_BPX_LINK_LBN 2 1214 #define MC_CMD_GET_LINK_OUT_BPX_LINK_WIDTH 1 1215 #define MC_CMD_GET_LINK_OUT_PHY_LINK_LBN 3 1216 #define MC_CMD_GET_LINK_OUT_PHY_LINK_WIDTH 1 1217 #define MC_CMD_GET_LINK_OUT_FCNTL_OFST 20 1218 #define MC_CMD_FCNTL_OFF 0x0 /* enum */ 1219 #define MC_CMD_FCNTL_RESPOND 0x1 /* enum */ 1220 #define MC_CMD_FCNTL_BIDIR 0x2 /* enum */ 1221 #define MC_CMD_GET_LINK_OUT_MAC_FAULT_OFST 24 1222 #define MC_CMD_MAC_FAULT_XGMII_LOCAL_LBN 0 1223 #define MC_CMD_MAC_FAULT_XGMII_LOCAL_WIDTH 1 1224 #define MC_CMD_MAC_FAULT_XGMII_REMOTE_LBN 1 1225 #define MC_CMD_MAC_FAULT_XGMII_REMOTE_WIDTH 1 1226 #define MC_CMD_MAC_FAULT_SGMII_REMOTE_LBN 2 1227 #define MC_CMD_MAC_FAULT_SGMII_REMOTE_WIDTH 1 1228 #define MC_CMD_MAC_FAULT_PENDING_RECONFIG_LBN 3 1229 #define MC_CMD_MAC_FAULT_PENDING_RECONFIG_WIDTH 1 1230 1231 1232 /***********************************/ 1233 /* MC_CMD_SET_LINK 1234 * Write the unified MAC/PHY link configuration. 1235 */ 1236 #define MC_CMD_SET_LINK 0x2a 1237 1238 /* MC_CMD_SET_LINK_IN msgrequest */ 1239 #define MC_CMD_SET_LINK_IN_LEN 16 1240 #define MC_CMD_SET_LINK_IN_CAP_OFST 0 1241 #define MC_CMD_SET_LINK_IN_FLAGS_OFST 4 1242 #define MC_CMD_SET_LINK_IN_LOWPOWER_LBN 0 1243 #define MC_CMD_SET_LINK_IN_LOWPOWER_WIDTH 1 1244 #define MC_CMD_SET_LINK_IN_POWEROFF_LBN 1 1245 #define MC_CMD_SET_LINK_IN_POWEROFF_WIDTH 1 1246 #define MC_CMD_SET_LINK_IN_TXDIS_LBN 2 1247 #define MC_CMD_SET_LINK_IN_TXDIS_WIDTH 1 1248 #define MC_CMD_SET_LINK_IN_LOOPBACK_MODE_OFST 8 1249 /* Enum values, see field(s): */ 1250 /* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */ 1251 #define MC_CMD_SET_LINK_IN_LOOPBACK_SPEED_OFST 12 1252 1253 /* MC_CMD_SET_LINK_OUT msgresponse */ 1254 #define MC_CMD_SET_LINK_OUT_LEN 0 1255 1256 1257 /***********************************/ 1258 /* MC_CMD_SET_ID_LED 1259 * Set indentification LED state. 1260 */ 1261 #define MC_CMD_SET_ID_LED 0x2b 1262 1263 /* MC_CMD_SET_ID_LED_IN msgrequest */ 1264 #define MC_CMD_SET_ID_LED_IN_LEN 4 1265 #define MC_CMD_SET_ID_LED_IN_STATE_OFST 0 1266 #define MC_CMD_LED_OFF 0x0 /* enum */ 1267 #define MC_CMD_LED_ON 0x1 /* enum */ 1268 #define MC_CMD_LED_DEFAULT 0x2 /* enum */ 1269 1270 /* MC_CMD_SET_ID_LED_OUT msgresponse */ 1271 #define MC_CMD_SET_ID_LED_OUT_LEN 0 1272 1273 1274 /***********************************/ 1275 /* MC_CMD_SET_MAC 1276 * Set MAC configuration. 1277 */ 1278 #define MC_CMD_SET_MAC 0x2c 1279 1280 /* MC_CMD_SET_MAC_IN msgrequest */ 1281 #define MC_CMD_SET_MAC_IN_LEN 24 1282 #define MC_CMD_SET_MAC_IN_MTU_OFST 0 1283 #define MC_CMD_SET_MAC_IN_DRAIN_OFST 4 1284 #define MC_CMD_SET_MAC_IN_ADDR_OFST 8 1285 #define MC_CMD_SET_MAC_IN_ADDR_LEN 8 1286 #define MC_CMD_SET_MAC_IN_ADDR_LO_OFST 8 1287 #define MC_CMD_SET_MAC_IN_ADDR_HI_OFST 12 1288 #define MC_CMD_SET_MAC_IN_REJECT_OFST 16 1289 #define MC_CMD_SET_MAC_IN_REJECT_UNCST_LBN 0 1290 #define MC_CMD_SET_MAC_IN_REJECT_UNCST_WIDTH 1 1291 #define MC_CMD_SET_MAC_IN_REJECT_BRDCST_LBN 1 1292 #define MC_CMD_SET_MAC_IN_REJECT_BRDCST_WIDTH 1 1293 #define MC_CMD_SET_MAC_IN_FCNTL_OFST 20 1294 /* MC_CMD_FCNTL_OFF 0x0 */ 1295 /* MC_CMD_FCNTL_RESPOND 0x1 */ 1296 /* MC_CMD_FCNTL_BIDIR 0x2 */ 1297 #define MC_CMD_FCNTL_AUTO 0x3 /* enum */ 1298 1299 /* MC_CMD_SET_MAC_OUT msgresponse */ 1300 #define MC_CMD_SET_MAC_OUT_LEN 0 1301 1302 1303 /***********************************/ 1304 /* MC_CMD_PHY_STATS 1305 * Get generic PHY statistics. 1306 */ 1307 #define MC_CMD_PHY_STATS 0x2d 1308 1309 /* MC_CMD_PHY_STATS_IN msgrequest */ 1310 #define MC_CMD_PHY_STATS_IN_LEN 8 1311 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_OFST 0 1312 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_LEN 8 1313 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_OFST 0 1314 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_HI_OFST 4 1315 1316 /* MC_CMD_PHY_STATS_OUT_DMA msgresponse */ 1317 #define MC_CMD_PHY_STATS_OUT_DMA_LEN 0 1318 1319 /* MC_CMD_PHY_STATS_OUT_NO_DMA msgresponse */ 1320 #define MC_CMD_PHY_STATS_OUT_NO_DMA_LEN (((MC_CMD_PHY_NSTATS*32))>>3) 1321 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_OFST 0 1322 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_LEN 4 1323 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_PHY_NSTATS 1324 #define MC_CMD_OUI 0x0 /* enum */ 1325 #define MC_CMD_PMA_PMD_LINK_UP 0x1 /* enum */ 1326 #define MC_CMD_PMA_PMD_RX_FAULT 0x2 /* enum */ 1327 #define MC_CMD_PMA_PMD_TX_FAULT 0x3 /* enum */ 1328 #define MC_CMD_PMA_PMD_SIGNAL 0x4 /* enum */ 1329 #define MC_CMD_PMA_PMD_SNR_A 0x5 /* enum */ 1330 #define MC_CMD_PMA_PMD_SNR_B 0x6 /* enum */ 1331 #define MC_CMD_PMA_PMD_SNR_C 0x7 /* enum */ 1332 #define MC_CMD_PMA_PMD_SNR_D 0x8 /* enum */ 1333 #define MC_CMD_PCS_LINK_UP 0x9 /* enum */ 1334 #define MC_CMD_PCS_RX_FAULT 0xa /* enum */ 1335 #define MC_CMD_PCS_TX_FAULT 0xb /* enum */ 1336 #define MC_CMD_PCS_BER 0xc /* enum */ 1337 #define MC_CMD_PCS_BLOCK_ERRORS 0xd /* enum */ 1338 #define MC_CMD_PHYXS_LINK_UP 0xe /* enum */ 1339 #define MC_CMD_PHYXS_RX_FAULT 0xf /* enum */ 1340 #define MC_CMD_PHYXS_TX_FAULT 0x10 /* enum */ 1341 #define MC_CMD_PHYXS_ALIGN 0x11 /* enum */ 1342 #define MC_CMD_PHYXS_SYNC 0x12 /* enum */ 1343 #define MC_CMD_AN_LINK_UP 0x13 /* enum */ 1344 #define MC_CMD_AN_COMPLETE 0x14 /* enum */ 1345 #define MC_CMD_AN_10GBT_STATUS 0x15 /* enum */ 1346 #define MC_CMD_CL22_LINK_UP 0x16 /* enum */ 1347 #define MC_CMD_PHY_NSTATS 0x17 /* enum */ 1348 1349 1350 /***********************************/ 1351 /* MC_CMD_MAC_STATS 1352 * Get generic MAC statistics. 1353 */ 1354 #define MC_CMD_MAC_STATS 0x2e 1355 1356 /* MC_CMD_MAC_STATS_IN msgrequest */ 1357 #define MC_CMD_MAC_STATS_IN_LEN 16 1358 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_OFST 0 1359 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_LEN 8 1360 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_OFST 0 1361 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_OFST 4 1362 #define MC_CMD_MAC_STATS_IN_CMD_OFST 8 1363 #define MC_CMD_MAC_STATS_IN_DMA_LBN 0 1364 #define MC_CMD_MAC_STATS_IN_DMA_WIDTH 1 1365 #define MC_CMD_MAC_STATS_IN_CLEAR_LBN 1 1366 #define MC_CMD_MAC_STATS_IN_CLEAR_WIDTH 1 1367 #define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_LBN 2 1368 #define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_WIDTH 1 1369 #define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_LBN 3 1370 #define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_WIDTH 1 1371 #define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_LBN 4 1372 #define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_WIDTH 1 1373 #define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_LBN 5 1374 #define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_WIDTH 1 1375 #define MC_CMD_MAC_STATS_IN_PERIOD_MS_LBN 16 1376 #define MC_CMD_MAC_STATS_IN_PERIOD_MS_WIDTH 16 1377 #define MC_CMD_MAC_STATS_IN_DMA_LEN_OFST 12 1378 1379 /* MC_CMD_MAC_STATS_OUT_DMA msgresponse */ 1380 #define MC_CMD_MAC_STATS_OUT_DMA_LEN 0 1381 1382 /* MC_CMD_MAC_STATS_OUT_NO_DMA msgresponse */ 1383 #define MC_CMD_MAC_STATS_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS*64))>>3) 1384 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_OFST 0 1385 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LEN 8 1386 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_OFST 0 1387 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_OFST 4 1388 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS 1389 #define MC_CMD_MAC_GENERATION_START 0x0 /* enum */ 1390 #define MC_CMD_MAC_TX_PKTS 0x1 /* enum */ 1391 #define MC_CMD_MAC_TX_PAUSE_PKTS 0x2 /* enum */ 1392 #define MC_CMD_MAC_TX_CONTROL_PKTS 0x3 /* enum */ 1393 #define MC_CMD_MAC_TX_UNICAST_PKTS 0x4 /* enum */ 1394 #define MC_CMD_MAC_TX_MULTICAST_PKTS 0x5 /* enum */ 1395 #define MC_CMD_MAC_TX_BROADCAST_PKTS 0x6 /* enum */ 1396 #define MC_CMD_MAC_TX_BYTES 0x7 /* enum */ 1397 #define MC_CMD_MAC_TX_BAD_BYTES 0x8 /* enum */ 1398 #define MC_CMD_MAC_TX_LT64_PKTS 0x9 /* enum */ 1399 #define MC_CMD_MAC_TX_64_PKTS 0xa /* enum */ 1400 #define MC_CMD_MAC_TX_65_TO_127_PKTS 0xb /* enum */ 1401 #define MC_CMD_MAC_TX_128_TO_255_PKTS 0xc /* enum */ 1402 #define MC_CMD_MAC_TX_256_TO_511_PKTS 0xd /* enum */ 1403 #define MC_CMD_MAC_TX_512_TO_1023_PKTS 0xe /* enum */ 1404 #define MC_CMD_MAC_TX_1024_TO_15XX_PKTS 0xf /* enum */ 1405 #define MC_CMD_MAC_TX_15XX_TO_JUMBO_PKTS 0x10 /* enum */ 1406 #define MC_CMD_MAC_TX_GTJUMBO_PKTS 0x11 /* enum */ 1407 #define MC_CMD_MAC_TX_BAD_FCS_PKTS 0x12 /* enum */ 1408 #define MC_CMD_MAC_TX_SINGLE_COLLISION_PKTS 0x13 /* enum */ 1409 #define MC_CMD_MAC_TX_MULTIPLE_COLLISION_PKTS 0x14 /* enum */ 1410 #define MC_CMD_MAC_TX_EXCESSIVE_COLLISION_PKTS 0x15 /* enum */ 1411 #define MC_CMD_MAC_TX_LATE_COLLISION_PKTS 0x16 /* enum */ 1412 #define MC_CMD_MAC_TX_DEFERRED_PKTS 0x17 /* enum */ 1413 #define MC_CMD_MAC_TX_EXCESSIVE_DEFERRED_PKTS 0x18 /* enum */ 1414 #define MC_CMD_MAC_TX_NON_TCPUDP_PKTS 0x19 /* enum */ 1415 #define MC_CMD_MAC_TX_MAC_SRC_ERR_PKTS 0x1a /* enum */ 1416 #define MC_CMD_MAC_TX_IP_SRC_ERR_PKTS 0x1b /* enum */ 1417 #define MC_CMD_MAC_RX_PKTS 0x1c /* enum */ 1418 #define MC_CMD_MAC_RX_PAUSE_PKTS 0x1d /* enum */ 1419 #define MC_CMD_MAC_RX_GOOD_PKTS 0x1e /* enum */ 1420 #define MC_CMD_MAC_RX_CONTROL_PKTS 0x1f /* enum */ 1421 #define MC_CMD_MAC_RX_UNICAST_PKTS 0x20 /* enum */ 1422 #define MC_CMD_MAC_RX_MULTICAST_PKTS 0x21 /* enum */ 1423 #define MC_CMD_MAC_RX_BROADCAST_PKTS 0x22 /* enum */ 1424 #define MC_CMD_MAC_RX_BYTES 0x23 /* enum */ 1425 #define MC_CMD_MAC_RX_BAD_BYTES 0x24 /* enum */ 1426 #define MC_CMD_MAC_RX_64_PKTS 0x25 /* enum */ 1427 #define MC_CMD_MAC_RX_65_TO_127_PKTS 0x26 /* enum */ 1428 #define MC_CMD_MAC_RX_128_TO_255_PKTS 0x27 /* enum */ 1429 #define MC_CMD_MAC_RX_256_TO_511_PKTS 0x28 /* enum */ 1430 #define MC_CMD_MAC_RX_512_TO_1023_PKTS 0x29 /* enum */ 1431 #define MC_CMD_MAC_RX_1024_TO_15XX_PKTS 0x2a /* enum */ 1432 #define MC_CMD_MAC_RX_15XX_TO_JUMBO_PKTS 0x2b /* enum */ 1433 #define MC_CMD_MAC_RX_GTJUMBO_PKTS 0x2c /* enum */ 1434 #define MC_CMD_MAC_RX_UNDERSIZE_PKTS 0x2d /* enum */ 1435 #define MC_CMD_MAC_RX_BAD_FCS_PKTS 0x2e /* enum */ 1436 #define MC_CMD_MAC_RX_OVERFLOW_PKTS 0x2f /* enum */ 1437 #define MC_CMD_MAC_RX_FALSE_CARRIER_PKTS 0x30 /* enum */ 1438 #define MC_CMD_MAC_RX_SYMBOL_ERROR_PKTS 0x31 /* enum */ 1439 #define MC_CMD_MAC_RX_ALIGN_ERROR_PKTS 0x32 /* enum */ 1440 #define MC_CMD_MAC_RX_LENGTH_ERROR_PKTS 0x33 /* enum */ 1441 #define MC_CMD_MAC_RX_INTERNAL_ERROR_PKTS 0x34 /* enum */ 1442 #define MC_CMD_MAC_RX_JABBER_PKTS 0x35 /* enum */ 1443 #define MC_CMD_MAC_RX_NODESC_DROPS 0x36 /* enum */ 1444 #define MC_CMD_MAC_RX_LANES01_CHAR_ERR 0x37 /* enum */ 1445 #define MC_CMD_MAC_RX_LANES23_CHAR_ERR 0x38 /* enum */ 1446 #define MC_CMD_MAC_RX_LANES01_DISP_ERR 0x39 /* enum */ 1447 #define MC_CMD_MAC_RX_LANES23_DISP_ERR 0x3a /* enum */ 1448 #define MC_CMD_MAC_RX_MATCH_FAULT 0x3b /* enum */ 1449 #define MC_CMD_GMAC_DMABUF_START 0x40 /* enum */ 1450 #define MC_CMD_GMAC_DMABUF_END 0x5f /* enum */ 1451 #define MC_CMD_MAC_GENERATION_END 0x60 /* enum */ 1452 #define MC_CMD_MAC_NSTATS 0x61 /* enum */ 1453 1454 1455 /***********************************/ 1456 /* MC_CMD_SRIOV 1457 * to be documented 1458 */ 1459 #define MC_CMD_SRIOV 0x30 1460 1461 /* MC_CMD_SRIOV_IN msgrequest */ 1462 #define MC_CMD_SRIOV_IN_LEN 12 1463 #define MC_CMD_SRIOV_IN_ENABLE_OFST 0 1464 #define MC_CMD_SRIOV_IN_VI_BASE_OFST 4 1465 #define MC_CMD_SRIOV_IN_VF_COUNT_OFST 8 1466 1467 /* MC_CMD_SRIOV_OUT msgresponse */ 1468 #define MC_CMD_SRIOV_OUT_LEN 8 1469 #define MC_CMD_SRIOV_OUT_VI_SCALE_OFST 0 1470 #define MC_CMD_SRIOV_OUT_VF_TOTAL_OFST 4 1471 1472 /* MC_CMD_MEMCPY_RECORD_TYPEDEF structuredef */ 1473 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LEN 32 1474 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_OFST 0 1475 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_LBN 0 1476 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_WIDTH 32 1477 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_OFST 4 1478 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_LBN 32 1479 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_WIDTH 32 1480 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_OFST 8 1481 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LEN 8 1482 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LO_OFST 8 1483 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_HI_OFST 12 1484 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LBN 64 1485 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_WIDTH 64 1486 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_OFST 16 1487 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_RID_INLINE 0x100 /* enum */ 1488 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_LBN 128 1489 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_WIDTH 32 1490 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_OFST 20 1491 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LEN 8 1492 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LO_OFST 20 1493 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_HI_OFST 24 1494 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LBN 160 1495 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_WIDTH 64 1496 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_OFST 28 1497 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_LBN 224 1498 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_WIDTH 32 1499 1500 1501 /***********************************/ 1502 /* MC_CMD_MEMCPY 1503 * Perform memory copy operation. 1504 */ 1505 #define MC_CMD_MEMCPY 0x31 1506 1507 /* MC_CMD_MEMCPY_IN msgrequest */ 1508 #define MC_CMD_MEMCPY_IN_LENMIN 32 1509 #define MC_CMD_MEMCPY_IN_LENMAX 224 1510 #define MC_CMD_MEMCPY_IN_LEN(num) (0+32*(num)) 1511 #define MC_CMD_MEMCPY_IN_RECORD_OFST 0 1512 #define MC_CMD_MEMCPY_IN_RECORD_LEN 32 1513 #define MC_CMD_MEMCPY_IN_RECORD_MINNUM 1 1514 #define MC_CMD_MEMCPY_IN_RECORD_MAXNUM 7 1515 1516 /* MC_CMD_MEMCPY_OUT msgresponse */ 1517 #define MC_CMD_MEMCPY_OUT_LEN 0 1518 1519 1520 /***********************************/ 1521 /* MC_CMD_WOL_FILTER_SET 1522 * Set a WoL filter. 1523 */ 1524 #define MC_CMD_WOL_FILTER_SET 0x32 1525 1526 /* MC_CMD_WOL_FILTER_SET_IN msgrequest */ 1527 #define MC_CMD_WOL_FILTER_SET_IN_LEN 192 1528 #define MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 1529 #define MC_CMD_FILTER_MODE_SIMPLE 0x0 /* enum */ 1530 #define MC_CMD_FILTER_MODE_STRUCTURED 0xffffffff /* enum */ 1531 #define MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 1532 #define MC_CMD_WOL_TYPE_MAGIC 0x0 /* enum */ 1533 #define MC_CMD_WOL_TYPE_WIN_MAGIC 0x2 /* enum */ 1534 #define MC_CMD_WOL_TYPE_IPV4_SYN 0x3 /* enum */ 1535 #define MC_CMD_WOL_TYPE_IPV6_SYN 0x4 /* enum */ 1536 #define MC_CMD_WOL_TYPE_BITMAP 0x5 /* enum */ 1537 #define MC_CMD_WOL_TYPE_LINK 0x6 /* enum */ 1538 #define MC_CMD_WOL_TYPE_MAX 0x7 /* enum */ 1539 #define MC_CMD_WOL_FILTER_SET_IN_DATA_OFST 8 1540 #define MC_CMD_WOL_FILTER_SET_IN_DATA_LEN 4 1541 #define MC_CMD_WOL_FILTER_SET_IN_DATA_NUM 46 1542 1543 /* MC_CMD_WOL_FILTER_SET_IN_MAGIC msgrequest */ 1544 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_LEN 16 1545 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 1546 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 1547 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_OFST 8 1548 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LEN 8 1549 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LO_OFST 8 1550 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_HI_OFST 12 1551 1552 /* MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN msgrequest */ 1553 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_LEN 20 1554 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 1555 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 1556 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_IP_OFST 8 1557 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_IP_OFST 12 1558 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_OFST 16 1559 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_LEN 2 1560 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_OFST 18 1561 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_LEN 2 1562 1563 /* MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN msgrequest */ 1564 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_LEN 44 1565 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 1566 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 1567 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_OFST 8 1568 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_LEN 16 1569 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_OFST 24 1570 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_LEN 16 1571 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_OFST 40 1572 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_LEN 2 1573 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_OFST 42 1574 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_LEN 2 1575 1576 /* MC_CMD_WOL_FILTER_SET_IN_BITMAP msgrequest */ 1577 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN 187 1578 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 1579 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 1580 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_OFST 8 1581 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_LEN 48 1582 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_OFST 56 1583 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_LEN 128 1584 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_OFST 184 1585 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_LEN 1 1586 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_OFST 185 1587 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_LEN 1 1588 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_OFST 186 1589 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_LEN 1 1590 1591 /* MC_CMD_WOL_FILTER_SET_IN_LINK msgrequest */ 1592 #define MC_CMD_WOL_FILTER_SET_IN_LINK_LEN 12 1593 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 1594 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 1595 #define MC_CMD_WOL_FILTER_SET_IN_LINK_MASK_OFST 8 1596 #define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_LBN 0 1597 #define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_WIDTH 1 1598 #define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_LBN 1 1599 #define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_WIDTH 1 1600 1601 /* MC_CMD_WOL_FILTER_SET_OUT msgresponse */ 1602 #define MC_CMD_WOL_FILTER_SET_OUT_LEN 4 1603 #define MC_CMD_WOL_FILTER_SET_OUT_FILTER_ID_OFST 0 1604 1605 1606 /***********************************/ 1607 /* MC_CMD_WOL_FILTER_REMOVE 1608 * Remove a WoL filter. 1609 */ 1610 #define MC_CMD_WOL_FILTER_REMOVE 0x33 1611 1612 /* MC_CMD_WOL_FILTER_REMOVE_IN msgrequest */ 1613 #define MC_CMD_WOL_FILTER_REMOVE_IN_LEN 4 1614 #define MC_CMD_WOL_FILTER_REMOVE_IN_FILTER_ID_OFST 0 1615 1616 /* MC_CMD_WOL_FILTER_REMOVE_OUT msgresponse */ 1617 #define MC_CMD_WOL_FILTER_REMOVE_OUT_LEN 0 1618 1619 1620 /***********************************/ 1621 /* MC_CMD_WOL_FILTER_RESET 1622 * Reset (i.e. remove all) WoL filters. 1623 */ 1624 #define MC_CMD_WOL_FILTER_RESET 0x34 1625 1626 /* MC_CMD_WOL_FILTER_RESET_IN msgrequest */ 1627 #define MC_CMD_WOL_FILTER_RESET_IN_LEN 4 1628 #define MC_CMD_WOL_FILTER_RESET_IN_MASK_OFST 0 1629 #define MC_CMD_WOL_FILTER_RESET_IN_WAKE_FILTERS 0x1 /* enum */ 1630 #define MC_CMD_WOL_FILTER_RESET_IN_LIGHTSOUT_OFFLOADS 0x2 /* enum */ 1631 1632 /* MC_CMD_WOL_FILTER_RESET_OUT msgresponse */ 1633 #define MC_CMD_WOL_FILTER_RESET_OUT_LEN 0 1634 1635 1636 /***********************************/ 1637 /* MC_CMD_SET_MCAST_HASH 1638 * Set the MCASH hash value. 1639 */ 1640 #define MC_CMD_SET_MCAST_HASH 0x35 1641 1642 /* MC_CMD_SET_MCAST_HASH_IN msgrequest */ 1643 #define MC_CMD_SET_MCAST_HASH_IN_LEN 32 1644 #define MC_CMD_SET_MCAST_HASH_IN_HASH0_OFST 0 1645 #define MC_CMD_SET_MCAST_HASH_IN_HASH0_LEN 16 1646 #define MC_CMD_SET_MCAST_HASH_IN_HASH1_OFST 16 1647 #define MC_CMD_SET_MCAST_HASH_IN_HASH1_LEN 16 1648 1649 /* MC_CMD_SET_MCAST_HASH_OUT msgresponse */ 1650 #define MC_CMD_SET_MCAST_HASH_OUT_LEN 0 1651 1652 1653 /***********************************/ 1654 /* MC_CMD_NVRAM_TYPES 1655 * Get virtual NVRAM partitions information. 1656 */ 1657 #define MC_CMD_NVRAM_TYPES 0x36 1658 1659 /* MC_CMD_NVRAM_TYPES_IN msgrequest */ 1660 #define MC_CMD_NVRAM_TYPES_IN_LEN 0 1661 1662 /* MC_CMD_NVRAM_TYPES_OUT msgresponse */ 1663 #define MC_CMD_NVRAM_TYPES_OUT_LEN 4 1664 #define MC_CMD_NVRAM_TYPES_OUT_TYPES_OFST 0 1665 #define MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO 0x0 /* enum */ 1666 #define MC_CMD_NVRAM_TYPE_MC_FW 0x1 /* enum */ 1667 #define MC_CMD_NVRAM_TYPE_MC_FW_BACKUP 0x2 /* enum */ 1668 #define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0 0x3 /* enum */ 1669 #define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1 0x4 /* enum */ 1670 #define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0 0x5 /* enum */ 1671 #define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1 0x6 /* enum */ 1672 #define MC_CMD_NVRAM_TYPE_EXP_ROM 0x7 /* enum */ 1673 #define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0 0x8 /* enum */ 1674 #define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1 0x9 /* enum */ 1675 #define MC_CMD_NVRAM_TYPE_PHY_PORT0 0xa /* enum */ 1676 #define MC_CMD_NVRAM_TYPE_PHY_PORT1 0xb /* enum */ 1677 #define MC_CMD_NVRAM_TYPE_LOG 0xc /* enum */ 1678 1679 1680 /***********************************/ 1681 /* MC_CMD_NVRAM_INFO 1682 * Read info about a virtual NVRAM partition. 1683 */ 1684 #define MC_CMD_NVRAM_INFO 0x37 1685 1686 /* MC_CMD_NVRAM_INFO_IN msgrequest */ 1687 #define MC_CMD_NVRAM_INFO_IN_LEN 4 1688 #define MC_CMD_NVRAM_INFO_IN_TYPE_OFST 0 1689 /* Enum values, see field(s): */ 1690 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 1691 1692 /* MC_CMD_NVRAM_INFO_OUT msgresponse */ 1693 #define MC_CMD_NVRAM_INFO_OUT_LEN 24 1694 #define MC_CMD_NVRAM_INFO_OUT_TYPE_OFST 0 1695 /* Enum values, see field(s): */ 1696 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 1697 #define MC_CMD_NVRAM_INFO_OUT_SIZE_OFST 4 1698 #define MC_CMD_NVRAM_INFO_OUT_ERASESIZE_OFST 8 1699 #define MC_CMD_NVRAM_INFO_OUT_FLAGS_OFST 12 1700 #define MC_CMD_NVRAM_INFO_OUT_PROTECTED_LBN 0 1701 #define MC_CMD_NVRAM_INFO_OUT_PROTECTED_WIDTH 1 1702 #define MC_CMD_NVRAM_INFO_OUT_PHYSDEV_OFST 16 1703 #define MC_CMD_NVRAM_INFO_OUT_PHYSADDR_OFST 20 1704 1705 1706 /***********************************/ 1707 /* MC_CMD_NVRAM_UPDATE_START 1708 * Start a group of update operations on a virtual NVRAM partition. 1709 */ 1710 #define MC_CMD_NVRAM_UPDATE_START 0x38 1711 1712 /* MC_CMD_NVRAM_UPDATE_START_IN msgrequest */ 1713 #define MC_CMD_NVRAM_UPDATE_START_IN_LEN 4 1714 #define MC_CMD_NVRAM_UPDATE_START_IN_TYPE_OFST 0 1715 /* Enum values, see field(s): */ 1716 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 1717 1718 /* MC_CMD_NVRAM_UPDATE_START_OUT msgresponse */ 1719 #define MC_CMD_NVRAM_UPDATE_START_OUT_LEN 0 1720 1721 1722 /***********************************/ 1723 /* MC_CMD_NVRAM_READ 1724 * Read data from a virtual NVRAM partition. 1725 */ 1726 #define MC_CMD_NVRAM_READ 0x39 1727 1728 /* MC_CMD_NVRAM_READ_IN msgrequest */ 1729 #define MC_CMD_NVRAM_READ_IN_LEN 12 1730 #define MC_CMD_NVRAM_READ_IN_TYPE_OFST 0 1731 /* Enum values, see field(s): */ 1732 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 1733 #define MC_CMD_NVRAM_READ_IN_OFFSET_OFST 4 1734 #define MC_CMD_NVRAM_READ_IN_LENGTH_OFST 8 1735 1736 /* MC_CMD_NVRAM_READ_OUT msgresponse */ 1737 #define MC_CMD_NVRAM_READ_OUT_LENMIN 1 1738 #define MC_CMD_NVRAM_READ_OUT_LENMAX 255 1739 #define MC_CMD_NVRAM_READ_OUT_LEN(num) (0+1*(num)) 1740 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_OFST 0 1741 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_LEN 1 1742 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MINNUM 1 1743 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MAXNUM 255 1744 1745 1746 /***********************************/ 1747 /* MC_CMD_NVRAM_WRITE 1748 * Write data to a virtual NVRAM partition. 1749 */ 1750 #define MC_CMD_NVRAM_WRITE 0x3a 1751 1752 /* MC_CMD_NVRAM_WRITE_IN msgrequest */ 1753 #define MC_CMD_NVRAM_WRITE_IN_LENMIN 13 1754 #define MC_CMD_NVRAM_WRITE_IN_LENMAX 255 1755 #define MC_CMD_NVRAM_WRITE_IN_LEN(num) (12+1*(num)) 1756 #define MC_CMD_NVRAM_WRITE_IN_TYPE_OFST 0 1757 /* Enum values, see field(s): */ 1758 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 1759 #define MC_CMD_NVRAM_WRITE_IN_OFFSET_OFST 4 1760 #define MC_CMD_NVRAM_WRITE_IN_LENGTH_OFST 8 1761 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_OFST 12 1762 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_LEN 1 1763 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MINNUM 1 1764 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MAXNUM 243 1765 1766 /* MC_CMD_NVRAM_WRITE_OUT msgresponse */ 1767 #define MC_CMD_NVRAM_WRITE_OUT_LEN 0 1768 1769 1770 /***********************************/ 1771 /* MC_CMD_NVRAM_ERASE 1772 * Erase sector(s) from a virtual NVRAM partition. 1773 */ 1774 #define MC_CMD_NVRAM_ERASE 0x3b 1775 1776 /* MC_CMD_NVRAM_ERASE_IN msgrequest */ 1777 #define MC_CMD_NVRAM_ERASE_IN_LEN 12 1778 #define MC_CMD_NVRAM_ERASE_IN_TYPE_OFST 0 1779 /* Enum values, see field(s): */ 1780 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 1781 #define MC_CMD_NVRAM_ERASE_IN_OFFSET_OFST 4 1782 #define MC_CMD_NVRAM_ERASE_IN_LENGTH_OFST 8 1783 1784 /* MC_CMD_NVRAM_ERASE_OUT msgresponse */ 1785 #define MC_CMD_NVRAM_ERASE_OUT_LEN 0 1786 1787 1788 /***********************************/ 1789 /* MC_CMD_NVRAM_UPDATE_FINISH 1790 * Finish a group of update operations on a virtual NVRAM partition. 1791 */ 1792 #define MC_CMD_NVRAM_UPDATE_FINISH 0x3c 1793 1794 /* MC_CMD_NVRAM_UPDATE_FINISH_IN msgrequest */ 1795 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_LEN 8 1796 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_TYPE_OFST 0 1797 /* Enum values, see field(s): */ 1798 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 1799 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_REBOOT_OFST 4 1800 1801 /* MC_CMD_NVRAM_UPDATE_FINISH_OUT msgresponse */ 1802 #define MC_CMD_NVRAM_UPDATE_FINISH_OUT_LEN 0 1803 1804 1805 /***********************************/ 1806 /* MC_CMD_REBOOT 1807 * Reboot the MC. 1808 */ 1809 #define MC_CMD_REBOOT 0x3d 1810 1811 /* MC_CMD_REBOOT_IN msgrequest */ 1812 #define MC_CMD_REBOOT_IN_LEN 4 1813 #define MC_CMD_REBOOT_IN_FLAGS_OFST 0 1814 #define MC_CMD_REBOOT_FLAGS_AFTER_ASSERTION 0x1 /* enum */ 1815 1816 /* MC_CMD_REBOOT_OUT msgresponse */ 1817 #define MC_CMD_REBOOT_OUT_LEN 0 1818 1819 1820 /***********************************/ 1821 /* MC_CMD_SCHEDINFO 1822 * Request scheduler info. 1823 */ 1824 #define MC_CMD_SCHEDINFO 0x3e 1825 1826 /* MC_CMD_SCHEDINFO_IN msgrequest */ 1827 #define MC_CMD_SCHEDINFO_IN_LEN 0 1828 1829 /* MC_CMD_SCHEDINFO_OUT msgresponse */ 1830 #define MC_CMD_SCHEDINFO_OUT_LENMIN 4 1831 #define MC_CMD_SCHEDINFO_OUT_LENMAX 252 1832 #define MC_CMD_SCHEDINFO_OUT_LEN(num) (0+4*(num)) 1833 #define MC_CMD_SCHEDINFO_OUT_DATA_OFST 0 1834 #define MC_CMD_SCHEDINFO_OUT_DATA_LEN 4 1835 #define MC_CMD_SCHEDINFO_OUT_DATA_MINNUM 1 1836 #define MC_CMD_SCHEDINFO_OUT_DATA_MAXNUM 63 1837 1838 1839 /***********************************/ 1840 /* MC_CMD_REBOOT_MODE 1841 */ 1842 #define MC_CMD_REBOOT_MODE 0x3f 1843 1844 /* MC_CMD_REBOOT_MODE_IN msgrequest */ 1845 #define MC_CMD_REBOOT_MODE_IN_LEN 4 1846 #define MC_CMD_REBOOT_MODE_IN_VALUE_OFST 0 1847 #define MC_CMD_REBOOT_MODE_NORMAL 0x0 /* enum */ 1848 #define MC_CMD_REBOOT_MODE_SNAPPER 0x3 /* enum */ 1849 1850 /* MC_CMD_REBOOT_MODE_OUT msgresponse */ 1851 #define MC_CMD_REBOOT_MODE_OUT_LEN 4 1852 #define MC_CMD_REBOOT_MODE_OUT_VALUE_OFST 0 1853 1854 1855 /***********************************/ 1856 /* MC_CMD_SENSOR_INFO 1857 * Returns information about every available sensor. 1858 */ 1859 #define MC_CMD_SENSOR_INFO 0x41 1860 1861 /* MC_CMD_SENSOR_INFO_IN msgrequest */ 1862 #define MC_CMD_SENSOR_INFO_IN_LEN 0 1863 1864 /* MC_CMD_SENSOR_INFO_OUT msgresponse */ 1865 #define MC_CMD_SENSOR_INFO_OUT_LENMIN 12 1866 #define MC_CMD_SENSOR_INFO_OUT_LENMAX 252 1867 #define MC_CMD_SENSOR_INFO_OUT_LEN(num) (4+8*(num)) 1868 #define MC_CMD_SENSOR_INFO_OUT_MASK_OFST 0 1869 #define MC_CMD_SENSOR_CONTROLLER_TEMP 0x0 /* enum */ 1870 #define MC_CMD_SENSOR_PHY_COMMON_TEMP 0x1 /* enum */ 1871 #define MC_CMD_SENSOR_CONTROLLER_COOLING 0x2 /* enum */ 1872 #define MC_CMD_SENSOR_PHY0_TEMP 0x3 /* enum */ 1873 #define MC_CMD_SENSOR_PHY0_COOLING 0x4 /* enum */ 1874 #define MC_CMD_SENSOR_PHY1_TEMP 0x5 /* enum */ 1875 #define MC_CMD_SENSOR_PHY1_COOLING 0x6 /* enum */ 1876 #define MC_CMD_SENSOR_IN_1V0 0x7 /* enum */ 1877 #define MC_CMD_SENSOR_IN_1V2 0x8 /* enum */ 1878 #define MC_CMD_SENSOR_IN_1V8 0x9 /* enum */ 1879 #define MC_CMD_SENSOR_IN_2V5 0xa /* enum */ 1880 #define MC_CMD_SENSOR_IN_3V3 0xb /* enum */ 1881 #define MC_CMD_SENSOR_IN_12V0 0xc /* enum */ 1882 #define MC_CMD_SENSOR_ENTRY_OFST 4 1883 #define MC_CMD_SENSOR_ENTRY_LEN 8 1884 #define MC_CMD_SENSOR_ENTRY_LO_OFST 4 1885 #define MC_CMD_SENSOR_ENTRY_HI_OFST 8 1886 #define MC_CMD_SENSOR_ENTRY_MINNUM 1 1887 #define MC_CMD_SENSOR_ENTRY_MAXNUM 31 1888 1889 /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF structuredef */ 1890 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_LEN 8 1891 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_OFST 0 1892 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LEN 2 1893 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LBN 0 1894 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_WIDTH 16 1895 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_OFST 2 1896 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LEN 2 1897 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LBN 16 1898 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_WIDTH 16 1899 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_OFST 4 1900 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LEN 2 1901 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LBN 32 1902 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_WIDTH 16 1903 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_OFST 6 1904 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LEN 2 1905 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LBN 48 1906 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_WIDTH 16 1907 1908 1909 /***********************************/ 1910 /* MC_CMD_READ_SENSORS 1911 * Returns the current reading from each sensor. 1912 */ 1913 #define MC_CMD_READ_SENSORS 0x42 1914 1915 /* MC_CMD_READ_SENSORS_IN msgrequest */ 1916 #define MC_CMD_READ_SENSORS_IN_LEN 8 1917 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_OFST 0 1918 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LEN 8 1919 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_OFST 0 1920 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_OFST 4 1921 1922 /* MC_CMD_READ_SENSORS_OUT msgresponse */ 1923 #define MC_CMD_READ_SENSORS_OUT_LEN 0 1924 1925 /* MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF structuredef */ 1926 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_LEN 3 1927 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_OFST 0 1928 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LEN 2 1929 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LBN 0 1930 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_WIDTH 16 1931 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_OFST 2 1932 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LEN 1 1933 #define MC_CMD_SENSOR_STATE_OK 0x0 /* enum */ 1934 #define MC_CMD_SENSOR_STATE_WARNING 0x1 /* enum */ 1935 #define MC_CMD_SENSOR_STATE_FATAL 0x2 /* enum */ 1936 #define MC_CMD_SENSOR_STATE_BROKEN 0x3 /* enum */ 1937 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LBN 16 1938 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_WIDTH 8 1939 1940 1941 /***********************************/ 1942 /* MC_CMD_GET_PHY_STATE 1943 * Report current state of PHY. 1944 */ 1945 #define MC_CMD_GET_PHY_STATE 0x43 1946 1947 /* MC_CMD_GET_PHY_STATE_IN msgrequest */ 1948 #define MC_CMD_GET_PHY_STATE_IN_LEN 0 1949 1950 /* MC_CMD_GET_PHY_STATE_OUT msgresponse */ 1951 #define MC_CMD_GET_PHY_STATE_OUT_LEN 4 1952 #define MC_CMD_GET_PHY_STATE_OUT_STATE_OFST 0 1953 #define MC_CMD_PHY_STATE_OK 0x1 /* enum */ 1954 #define MC_CMD_PHY_STATE_ZOMBIE 0x2 /* enum */ 1955 1956 1957 /***********************************/ 1958 /* MC_CMD_SETUP_8021QBB 1959 * 802.1Qbb control. 1960 */ 1961 #define MC_CMD_SETUP_8021QBB 0x44 1962 1963 /* MC_CMD_SETUP_8021QBB_IN msgrequest */ 1964 #define MC_CMD_SETUP_8021QBB_IN_LEN 32 1965 #define MC_CMD_SETUP_8021QBB_IN_TXQS_OFST 0 1966 #define MC_CMD_SETUP_8021QBB_IN_TXQS_LEN 32 1967 1968 /* MC_CMD_SETUP_8021QBB_OUT msgresponse */ 1969 #define MC_CMD_SETUP_8021QBB_OUT_LEN 0 1970 1971 1972 /***********************************/ 1973 /* MC_CMD_WOL_FILTER_GET 1974 * Retrieve ID of any WoL filters. 1975 */ 1976 #define MC_CMD_WOL_FILTER_GET 0x45 1977 1978 /* MC_CMD_WOL_FILTER_GET_IN msgrequest */ 1979 #define MC_CMD_WOL_FILTER_GET_IN_LEN 0 1980 1981 /* MC_CMD_WOL_FILTER_GET_OUT msgresponse */ 1982 #define MC_CMD_WOL_FILTER_GET_OUT_LEN 4 1983 #define MC_CMD_WOL_FILTER_GET_OUT_FILTER_ID_OFST 0 1984 1985 1986 /***********************************/ 1987 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD 1988 * Add a protocol offload to NIC for lights-out state. 1989 */ 1990 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD 0x46 1991 1992 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN msgrequest */ 1993 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMIN 8 1994 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMAX 252 1995 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LEN(num) (4+4*(num)) 1996 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 1997 #define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_ARP 0x1 /* enum */ 1998 #define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_NS 0x2 /* enum */ 1999 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_OFST 4 2000 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_LEN 4 2001 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MINNUM 1 2002 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MAXNUM 62 2003 2004 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP msgrequest */ 2005 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_LEN 14 2006 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */ 2007 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_OFST 4 2008 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_LEN 6 2009 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_IP_OFST 10 2010 2011 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS msgrequest */ 2012 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_LEN 42 2013 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */ 2014 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_OFST 4 2015 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_LEN 6 2016 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_OFST 10 2017 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_LEN 16 2018 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_OFST 26 2019 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_LEN 16 2020 2021 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT msgresponse */ 2022 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_LEN 4 2023 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_FILTER_ID_OFST 0 2024 2025 2026 /***********************************/ 2027 /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD 2028 * Remove a protocol offload from NIC for lights-out state. 2029 */ 2030 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD 0x47 2031 2032 /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN msgrequest */ 2033 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_LEN 8 2034 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 2035 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_FILTER_ID_OFST 4 2036 2037 /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT msgresponse */ 2038 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT_LEN 0 2039 2040 2041 /***********************************/ 2042 /* MC_CMD_MAC_RESET_RESTORE 2043 * Restore MAC after block reset. 2044 */ 2045 #define MC_CMD_MAC_RESET_RESTORE 0x48 2046 2047 /* MC_CMD_MAC_RESET_RESTORE_IN msgrequest */ 2048 #define MC_CMD_MAC_RESET_RESTORE_IN_LEN 0 2049 2050 /* MC_CMD_MAC_RESET_RESTORE_OUT msgresponse */ 2051 #define MC_CMD_MAC_RESET_RESTORE_OUT_LEN 0 2052 2053 2054 /***********************************/ 2055 /* MC_CMD_TESTASSERT 2056 */ 2057 #define MC_CMD_TESTASSERT 0x49 2058 2059 /* MC_CMD_TESTASSERT_IN msgrequest */ 2060 #define MC_CMD_TESTASSERT_IN_LEN 0 2061 2062 /* MC_CMD_TESTASSERT_OUT msgresponse */ 2063 #define MC_CMD_TESTASSERT_OUT_LEN 0 2064 2065 2066 /***********************************/ 2067 /* MC_CMD_WORKAROUND 2068 * Enable/Disable a given workaround. 2069 */ 2070 #define MC_CMD_WORKAROUND 0x4a 2071 2072 /* MC_CMD_WORKAROUND_IN msgrequest */ 2073 #define MC_CMD_WORKAROUND_IN_LEN 8 2074 #define MC_CMD_WORKAROUND_IN_TYPE_OFST 0 2075 #define MC_CMD_WORKAROUND_BUG17230 0x1 /* enum */ 2076 #define MC_CMD_WORKAROUND_IN_ENABLED_OFST 4 2077 2078 /* MC_CMD_WORKAROUND_OUT msgresponse */ 2079 #define MC_CMD_WORKAROUND_OUT_LEN 0 2080 2081 2082 /***********************************/ 2083 /* MC_CMD_GET_PHY_MEDIA_INFO 2084 * Read media-specific data from PHY. 2085 */ 2086 #define MC_CMD_GET_PHY_MEDIA_INFO 0x4b 2087 2088 /* MC_CMD_GET_PHY_MEDIA_INFO_IN msgrequest */ 2089 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_LEN 4 2090 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_PAGE_OFST 0 2091 2092 /* MC_CMD_GET_PHY_MEDIA_INFO_OUT msgresponse */ 2093 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMIN 5 2094 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMAX 255 2095 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LEN(num) (4+1*(num)) 2096 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATALEN_OFST 0 2097 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_OFST 4 2098 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_LEN 1 2099 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MINNUM 1 2100 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MAXNUM 251 2101 2102 2103 /***********************************/ 2104 /* MC_CMD_NVRAM_TEST 2105 * Test a particular NVRAM partition. 2106 */ 2107 #define MC_CMD_NVRAM_TEST 0x4c 2108 2109 /* MC_CMD_NVRAM_TEST_IN msgrequest */ 2110 #define MC_CMD_NVRAM_TEST_IN_LEN 4 2111 #define MC_CMD_NVRAM_TEST_IN_TYPE_OFST 0 2112 /* Enum values, see field(s): */ 2113 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 2114 2115 /* MC_CMD_NVRAM_TEST_OUT msgresponse */ 2116 #define MC_CMD_NVRAM_TEST_OUT_LEN 4 2117 #define MC_CMD_NVRAM_TEST_OUT_RESULT_OFST 0 2118 #define MC_CMD_NVRAM_TEST_PASS 0x0 /* enum */ 2119 #define MC_CMD_NVRAM_TEST_FAIL 0x1 /* enum */ 2120 #define MC_CMD_NVRAM_TEST_NOTSUPP 0x2 /* enum */ 2121 2122 2123 /***********************************/ 2124 /* MC_CMD_MRSFP_TWEAK 2125 * Read status and/or set parameters for the 'mrsfp' driver. 2126 */ 2127 #define MC_CMD_MRSFP_TWEAK 0x4d 2128 2129 /* MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG msgrequest */ 2130 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_LEN 16 2131 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_LEVEL_OFST 0 2132 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_DT_CFG_OFST 4 2133 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_BOOST_OFST 8 2134 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_DT_CFG_OFST 12 2135 2136 /* MC_CMD_MRSFP_TWEAK_IN_READ_ONLY msgrequest */ 2137 #define MC_CMD_MRSFP_TWEAK_IN_READ_ONLY_LEN 0 2138 2139 /* MC_CMD_MRSFP_TWEAK_OUT msgresponse */ 2140 #define MC_CMD_MRSFP_TWEAK_OUT_LEN 12 2141 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_INPUTS_OFST 0 2142 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_OUTPUTS_OFST 4 2143 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OFST 8 2144 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OUT 0x0 /* enum */ 2145 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_IN 0x1 /* enum */ 2146 2147 2148 /***********************************/ 2149 /* MC_CMD_SENSOR_SET_LIMS 2150 * Adjusts the sensor limits. 2151 */ 2152 #define MC_CMD_SENSOR_SET_LIMS 0x4e 2153 2154 /* MC_CMD_SENSOR_SET_LIMS_IN msgrequest */ 2155 #define MC_CMD_SENSOR_SET_LIMS_IN_LEN 20 2156 #define MC_CMD_SENSOR_SET_LIMS_IN_SENSOR_OFST 0 2157 /* Enum values, see field(s): */ 2158 /* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */ 2159 #define MC_CMD_SENSOR_SET_LIMS_IN_LOW0_OFST 4 2160 #define MC_CMD_SENSOR_SET_LIMS_IN_HI0_OFST 8 2161 #define MC_CMD_SENSOR_SET_LIMS_IN_LOW1_OFST 12 2162 #define MC_CMD_SENSOR_SET_LIMS_IN_HI1_OFST 16 2163 2164 /* MC_CMD_SENSOR_SET_LIMS_OUT msgresponse */ 2165 #define MC_CMD_SENSOR_SET_LIMS_OUT_LEN 0 2166 2167 2168 /***********************************/ 2169 /* MC_CMD_GET_RESOURCE_LIMITS 2170 */ 2171 #define MC_CMD_GET_RESOURCE_LIMITS 0x4f 2172 2173 /* MC_CMD_GET_RESOURCE_LIMITS_IN msgrequest */ 2174 #define MC_CMD_GET_RESOURCE_LIMITS_IN_LEN 0 2175 2176 /* MC_CMD_GET_RESOURCE_LIMITS_OUT msgresponse */ 2177 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_LEN 16 2178 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_BUFTBL_OFST 0 2179 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_EVQ_OFST 4 2180 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_RXQ_OFST 8 2181 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_TXQ_OFST 12 2182 2183 /* MC_CMD_RESOURCE_SPECIFIER enum */ 2184 #define MC_CMD_RESOURCE_INSTANCE_ANY 0xffffffff /* enum */ 2185 #define MC_CMD_RESOURCE_INSTANCE_NONE 0xfffffffe /* enum */ 2186 2187 2188 /***********************************/ 2189 /* MC_CMD_INIT_EVQ 2190 */ 2191 #define MC_CMD_INIT_EVQ 0x50 2192 2193 /* MC_CMD_INIT_EVQ_IN msgrequest */ 2194 #define MC_CMD_INIT_EVQ_IN_LENMIN 36 2195 #define MC_CMD_INIT_EVQ_IN_LENMAX 540 2196 #define MC_CMD_INIT_EVQ_IN_LEN(num) (28+8*(num)) 2197 #define MC_CMD_INIT_EVQ_IN_SIZE_OFST 0 2198 #define MC_CMD_INIT_EVQ_IN_INSTANCE_OFST 4 2199 #define MC_CMD_INIT_EVQ_IN_TMR_LOAD_OFST 8 2200 #define MC_CMD_INIT_EVQ_IN_TMR_RELOAD_OFST 12 2201 #define MC_CMD_INIT_EVQ_IN_FLAGS_OFST 16 2202 #define MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_LBN 0 2203 #define MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_WIDTH 1 2204 #define MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_LBN 1 2205 #define MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_WIDTH 1 2206 #define MC_CMD_INIT_EVQ_IN_TMR_MODE_OFST 20 2207 #define MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS 0x0 /* enum */ 2208 #define MC_CMD_INIT_EVQ_IN_TMR_IMMED_START 0x1 /* enum */ 2209 #define MC_CMD_INIT_EVQ_IN_TMR_TRIG_START 0x2 /* enum */ 2210 #define MC_CMD_INIT_EVQ_IN_TMR_INT_HLDOFF 0x3 /* enum */ 2211 #define MC_CMD_INIT_EVQ_IN_TARGET_EVQ_OFST 24 2212 #define MC_CMD_INIT_EVQ_IN_IRQ_NUM_OFST 24 2213 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_OFST 28 2214 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LEN 8 2215 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LO_OFST 28 2216 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_HI_OFST 32 2217 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MINNUM 1 2218 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MAXNUM 64 2219 2220 /* MC_CMD_INIT_EVQ_OUT msgresponse */ 2221 #define MC_CMD_INIT_EVQ_OUT_LEN 4 2222 #define MC_CMD_INIT_EVQ_OUT_IRQ_OFST 0 2223 2224 /* QUEUE_CRC_MODE structuredef */ 2225 #define QUEUE_CRC_MODE_LEN 1 2226 #define QUEUE_CRC_MODE_MODE_LBN 0 2227 #define QUEUE_CRC_MODE_MODE_WIDTH 4 2228 #define QUEUE_CRC_MODE_NONE 0x0 /* enum */ 2229 #define QUEUE_CRC_MODE_FCOE 0x1 /* enum */ 2230 #define QUEUE_CRC_MODE_ISCSI_HDR 0x2 /* enum */ 2231 #define QUEUE_CRC_MODE_ISCSI 0x3 /* enum */ 2232 #define QUEUE_CRC_MODE_FCOIPOE 0x4 /* enum */ 2233 #define QUEUE_CRC_MODE_MPA 0x5 /* enum */ 2234 #define QUEUE_CRC_MODE_SPARE_LBN 4 2235 #define QUEUE_CRC_MODE_SPARE_WIDTH 4 2236 2237 2238 /***********************************/ 2239 /* MC_CMD_INIT_RXQ 2240 */ 2241 #define MC_CMD_INIT_RXQ 0x51 2242 2243 /* MC_CMD_INIT_RXQ_IN msgrequest */ 2244 #define MC_CMD_INIT_RXQ_IN_LENMIN 32 2245 #define MC_CMD_INIT_RXQ_IN_LENMAX 248 2246 #define MC_CMD_INIT_RXQ_IN_LEN(num) (24+8*(num)) 2247 #define MC_CMD_INIT_RXQ_IN_SIZE_OFST 0 2248 #define MC_CMD_INIT_RXQ_IN_TARGET_EVQ_OFST 4 2249 #define MC_CMD_INIT_RXQ_IN_LABEL_OFST 8 2250 #define MC_CMD_INIT_RXQ_IN_INSTANCE_OFST 12 2251 #define MC_CMD_INIT_RXQ_IN_FLAGS_OFST 16 2252 #define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_LBN 0 2253 #define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_WIDTH 1 2254 #define MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_LBN 1 2255 #define MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_WIDTH 1 2256 #define MC_CMD_INIT_RXQ_IN_FLAG_PKT_EDIT_LBN 2 2257 #define MC_CMD_INIT_RXQ_IN_FLAG_PKT_EDIT_WIDTH 1 2258 #define MC_CMD_INIT_RXQ_IN_CRC_MODE_LBN 3 2259 #define MC_CMD_INIT_RXQ_IN_CRC_MODE_WIDTH 4 2260 #define MC_CMD_INIT_RXQ_IN_OWNER_ID_OFST 20 2261 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_OFST 24 2262 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LEN 8 2263 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LO_OFST 24 2264 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_HI_OFST 28 2265 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MINNUM 1 2266 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MAXNUM 28 2267 2268 /* MC_CMD_INIT_RXQ_OUT msgresponse */ 2269 #define MC_CMD_INIT_RXQ_OUT_LEN 0 2270 2271 2272 /***********************************/ 2273 /* MC_CMD_INIT_TXQ 2274 */ 2275 #define MC_CMD_INIT_TXQ 0x52 2276 2277 /* MC_CMD_INIT_TXQ_IN msgrequest */ 2278 #define MC_CMD_INIT_TXQ_IN_LENMIN 32 2279 #define MC_CMD_INIT_TXQ_IN_LENMAX 248 2280 #define MC_CMD_INIT_TXQ_IN_LEN(num) (24+8*(num)) 2281 #define MC_CMD_INIT_TXQ_IN_SIZE_OFST 0 2282 #define MC_CMD_INIT_TXQ_IN_TARGET_EVQ_OFST 4 2283 #define MC_CMD_INIT_TXQ_IN_LABEL_OFST 8 2284 #define MC_CMD_INIT_TXQ_IN_INSTANCE_OFST 12 2285 #define MC_CMD_INIT_TXQ_IN_FLAGS_OFST 16 2286 #define MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_LBN 0 2287 #define MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_WIDTH 1 2288 #define MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_LBN 1 2289 #define MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_WIDTH 1 2290 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_LBN 2 2291 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_WIDTH 1 2292 #define MC_CMD_INIT_TXQ_IN_CRC_MODE_LBN 4 2293 #define MC_CMD_INIT_TXQ_IN_CRC_MODE_WIDTH 4 2294 #define MC_CMD_INIT_TXQ_IN_OWNER_ID_OFST 20 2295 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_OFST 24 2296 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LEN 8 2297 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LO_OFST 24 2298 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_HI_OFST 28 2299 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MINNUM 1 2300 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MAXNUM 28 2301 2302 /* MC_CMD_INIT_TXQ_OUT msgresponse */ 2303 #define MC_CMD_INIT_TXQ_OUT_LEN 0 2304 2305 2306 /***********************************/ 2307 /* MC_CMD_FINI_EVQ 2308 */ 2309 #define MC_CMD_FINI_EVQ 0x55 2310 2311 /* MC_CMD_FINI_EVQ_IN msgrequest */ 2312 #define MC_CMD_FINI_EVQ_IN_LEN 4 2313 #define MC_CMD_FINI_EVQ_IN_INSTANCE_OFST 0 2314 2315 /* MC_CMD_FINI_EVQ_OUT msgresponse */ 2316 #define MC_CMD_FINI_EVQ_OUT_LEN 0 2317 2318 2319 /***********************************/ 2320 /* MC_CMD_FINI_RXQ 2321 */ 2322 #define MC_CMD_FINI_RXQ 0x56 2323 2324 /* MC_CMD_FINI_RXQ_IN msgrequest */ 2325 #define MC_CMD_FINI_RXQ_IN_LEN 4 2326 #define MC_CMD_FINI_RXQ_IN_INSTANCE_OFST 0 2327 2328 /* MC_CMD_FINI_RXQ_OUT msgresponse */ 2329 #define MC_CMD_FINI_RXQ_OUT_LEN 0 2330 2331 2332 /***********************************/ 2333 /* MC_CMD_FINI_TXQ 2334 */ 2335 #define MC_CMD_FINI_TXQ 0x57 2336 2337 /* MC_CMD_FINI_TXQ_IN msgrequest */ 2338 #define MC_CMD_FINI_TXQ_IN_LEN 4 2339 #define MC_CMD_FINI_TXQ_IN_INSTANCE_OFST 0 2340 2341 /* MC_CMD_FINI_TXQ_OUT msgresponse */ 2342 #define MC_CMD_FINI_TXQ_OUT_LEN 0 2343 2344 2345 /***********************************/ 2346 /* MC_CMD_DRIVER_EVENT 2347 */ 2348 #define MC_CMD_DRIVER_EVENT 0x5a 2349 2350 /* MC_CMD_DRIVER_EVENT_IN msgrequest */ 2351 #define MC_CMD_DRIVER_EVENT_IN_LEN 12 2352 #define MC_CMD_DRIVER_EVENT_IN_EVQ_OFST 0 2353 #define MC_CMD_DRIVER_EVENT_IN_DATA_OFST 4 2354 #define MC_CMD_DRIVER_EVENT_IN_DATA_LEN 8 2355 #define MC_CMD_DRIVER_EVENT_IN_DATA_LO_OFST 4 2356 #define MC_CMD_DRIVER_EVENT_IN_DATA_HI_OFST 8 2357 2358 2359 /***********************************/ 2360 /* MC_CMD_PROXY_CMD 2361 */ 2362 #define MC_CMD_PROXY_CMD 0x5b 2363 2364 /* MC_CMD_PROXY_CMD_IN msgrequest */ 2365 #define MC_CMD_PROXY_CMD_IN_LEN 4 2366 #define MC_CMD_PROXY_CMD_IN_TARGET_OFST 0 2367 2368 2369 /***********************************/ 2370 /* MC_CMD_ALLOC_OWNER_IDS 2371 */ 2372 #define MC_CMD_ALLOC_OWNER_IDS 0x54 2373 2374 /* MC_CMD_ALLOC_OWNER_IDS_IN msgrequest */ 2375 #define MC_CMD_ALLOC_OWNER_IDS_IN_LEN 4 2376 #define MC_CMD_ALLOC_OWNER_IDS_IN_NIDS_OFST 0 2377 2378 /* MC_CMD_ALLOC_OWNER_IDS_OUT msgresponse */ 2379 #define MC_CMD_ALLOC_OWNER_IDS_OUT_LEN 12 2380 #define MC_CMD_ALLOC_OWNER_IDS_OUT_HANDLE_OFST 0 2381 #define MC_CMD_ALLOC_OWNER_IDS_OUT_NIDS_OFST 4 2382 #define MC_CMD_ALLOC_OWNER_IDS_OUT_BASE_OFST 8 2383 2384 2385 /***********************************/ 2386 /* MC_CMD_FREE_OWNER_IDS 2387 */ 2388 #define MC_CMD_FREE_OWNER_IDS 0x59 2389 2390 /* MC_CMD_FREE_OWNER_IDS_IN msgrequest */ 2391 #define MC_CMD_FREE_OWNER_IDS_IN_LEN 4 2392 #define MC_CMD_FREE_OWNER_IDS_IN_HANDLE_OFST 0 2393 2394 /* MC_CMD_FREE_OWNER_IDS_OUT msgresponse */ 2395 #define MC_CMD_FREE_OWNER_IDS_OUT_LEN 0 2396 2397 2398 /***********************************/ 2399 /* MC_CMD_ALLOC_BUFTBL_CHUNK 2400 */ 2401 #define MC_CMD_ALLOC_BUFTBL_CHUNK 0x5c 2402 2403 /* MC_CMD_ALLOC_BUFTBL_CHUNK_IN msgrequest */ 2404 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_LEN 8 2405 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_OWNER_OFST 0 2406 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_PAGE_SIZE_OFST 4 2407 2408 /* MC_CMD_ALLOC_BUFTBL_CHUNK_OUT msgresponse */ 2409 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_LEN 12 2410 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_HANDLE_OFST 0 2411 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_NUMENTRIES_OFST 4 2412 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_ID_OFST 8 2413 2414 2415 /***********************************/ 2416 /* MC_CMD_PROGRAM_BUFTBL_ENTRIES 2417 */ 2418 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES 0x5d 2419 2420 /* MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN msgrequest */ 2421 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMIN 20 2422 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMAX 252 2423 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LEN(num) (12+8*(num)) 2424 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_HANDLE_OFST 0 2425 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_FIRSTID_OFST 4 2426 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_NUMENTRIES_OFST 8 2427 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_OFST 12 2428 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LEN 8 2429 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LO_OFST 12 2430 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_HI_OFST 16 2431 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MINNUM 1 2432 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MAXNUM 30 2433 2434 /* MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT msgresponse */ 2435 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT_LEN 0 2436 2437 2438 /***********************************/ 2439 /* MC_CMD_FREE_BUFTBL_CHUNK 2440 */ 2441 #define MC_CMD_FREE_BUFTBL_CHUNK 0x5e 2442 2443 /* MC_CMD_FREE_BUFTBL_CHUNK_IN msgrequest */ 2444 #define MC_CMD_FREE_BUFTBL_CHUNK_IN_LEN 4 2445 #define MC_CMD_FREE_BUFTBL_CHUNK_IN_HANDLE_OFST 0 2446 2447 /* MC_CMD_FREE_BUFTBL_CHUNK_OUT msgresponse */ 2448 #define MC_CMD_FREE_BUFTBL_CHUNK_OUT_LEN 0 2449 2450 2451 /***********************************/ 2452 /* MC_CMD_GET_PF_COUNT 2453 */ 2454 #define MC_CMD_GET_PF_COUNT 0x60 2455 2456 /* MC_CMD_GET_PF_COUNT_IN msgrequest */ 2457 #define MC_CMD_GET_PF_COUNT_IN_LEN 0 2458 2459 /* MC_CMD_GET_PF_COUNT_OUT msgresponse */ 2460 #define MC_CMD_GET_PF_COUNT_OUT_LEN 1 2461 #define MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_OFST 0 2462 #define MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_LEN 1 2463 2464 2465 /***********************************/ 2466 /* MC_CMD_FILTER_OP 2467 */ 2468 #define MC_CMD_FILTER_OP 0x61 2469 2470 /* MC_CMD_FILTER_OP_IN msgrequest */ 2471 #define MC_CMD_FILTER_OP_IN_LEN 100 2472 #define MC_CMD_FILTER_OP_IN_OP_OFST 0 2473 #define MC_CMD_FILTER_OP_IN_OP_INSERT 0x0 /* enum */ 2474 #define MC_CMD_FILTER_OP_IN_OP_REMOVE 0x1 /* enum */ 2475 #define MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE 0x2 /* enum */ 2476 #define MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE 0x3 /* enum */ 2477 #define MC_CMD_FILTER_OP_IN_HANDLE_OFST 4 2478 #define MC_CMD_FILTER_OP_IN_MATCH_FIELDS_OFST 8 2479 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_LBN 0 2480 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_WIDTH 1 2481 #define MC_CMD_FILTER_OP_IN_MATCH_DST_IP_LBN 1 2482 #define MC_CMD_FILTER_OP_IN_MATCH_DST_IP_WIDTH 1 2483 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_LBN 2 2484 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_WIDTH 1 2485 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_LBN 3 2486 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_WIDTH 1 2487 #define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_LBN 4 2488 #define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_WIDTH 1 2489 #define MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_LBN 5 2490 #define MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_WIDTH 1 2491 #define MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_LBN 6 2492 #define MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_WIDTH 1 2493 #define MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_LBN 7 2494 #define MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_WIDTH 1 2495 #define MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_LBN 8 2496 #define MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_WIDTH 1 2497 #define MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_LBN 9 2498 #define MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_WIDTH 1 2499 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_LBN 10 2500 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_WIDTH 1 2501 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_LBN 11 2502 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_WIDTH 1 2503 #define MC_CMD_FILTER_OP_IN_RX_DEST_OFST 12 2504 #define MC_CMD_FILTER_OP_IN_RX_DEST_DROP 0x0 /* enum */ 2505 #define MC_CMD_FILTER_OP_IN_RX_DEST_HOST 0x1 /* enum */ 2506 #define MC_CMD_FILTER_OP_IN_RX_DEST_MC 0x2 /* enum */ 2507 #define MC_CMD_FILTER_OP_IN_RX_DEST_TX0 0x3 /* enum */ 2508 #define MC_CMD_FILTER_OP_IN_RX_DEST_TX1 0x4 /* enum */ 2509 #define MC_CMD_FILTER_OP_IN_RX_QUEUE_OFST 16 2510 #define MC_CMD_FILTER_OP_IN_RX_FLAGS_OFST 20 2511 #define MC_CMD_FILTER_OP_IN_RX_FLAG_RSS_LBN 0 2512 #define MC_CMD_FILTER_OP_IN_RX_FLAG_RSS_WIDTH 1 2513 #define MC_CMD_FILTER_OP_IN_RSS_CONTEXT_OFST 24 2514 #define MC_CMD_FILTER_OP_IN_TX_DOMAIN_OFST 28 2515 #define MC_CMD_FILTER_OP_IN_TX_DEST_OFST 32 2516 #define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_LBN 0 2517 #define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_WIDTH 1 2518 #define MC_CMD_FILTER_OP_IN_TX_DEST_PM_LBN 1 2519 #define MC_CMD_FILTER_OP_IN_TX_DEST_PM_WIDTH 1 2520 #define MC_CMD_FILTER_OP_IN_SRC_MAC_OFST 36 2521 #define MC_CMD_FILTER_OP_IN_SRC_MAC_LEN 6 2522 #define MC_CMD_FILTER_OP_IN_SRC_PORT_OFST 42 2523 #define MC_CMD_FILTER_OP_IN_SRC_PORT_LEN 2 2524 #define MC_CMD_FILTER_OP_IN_DST_MAC_OFST 44 2525 #define MC_CMD_FILTER_OP_IN_DST_MAC_LEN 6 2526 #define MC_CMD_FILTER_OP_IN_DST_PORT_OFST 50 2527 #define MC_CMD_FILTER_OP_IN_DST_PORT_LEN 2 2528 #define MC_CMD_FILTER_OP_IN_ETHER_TYPE_OFST 52 2529 #define MC_CMD_FILTER_OP_IN_ETHER_TYPE_LEN 2 2530 #define MC_CMD_FILTER_OP_IN_INNER_VLAN_OFST 54 2531 #define MC_CMD_FILTER_OP_IN_INNER_VLAN_LEN 2 2532 #define MC_CMD_FILTER_OP_IN_OUTER_VLAN_OFST 56 2533 #define MC_CMD_FILTER_OP_IN_OUTER_VLAN_LEN 2 2534 #define MC_CMD_FILTER_OP_IN_IP_PROTO_OFST 58 2535 #define MC_CMD_FILTER_OP_IN_IP_PROTO_LEN 2 2536 #define MC_CMD_FILTER_OP_IN_FWDEF0_OFST 60 2537 #define MC_CMD_FILTER_OP_IN_FWDEF1_OFST 64 2538 #define MC_CMD_FILTER_OP_IN_SRC_IP_OFST 68 2539 #define MC_CMD_FILTER_OP_IN_SRC_IP_LEN 16 2540 #define MC_CMD_FILTER_OP_IN_DST_IP_OFST 84 2541 #define MC_CMD_FILTER_OP_IN_DST_IP_LEN 16 2542 2543 /* MC_CMD_FILTER_OP_OUT msgresponse */ 2544 #define MC_CMD_FILTER_OP_OUT_LEN 8 2545 #define MC_CMD_FILTER_OP_OUT_OP_OFST 0 2546 #define MC_CMD_FILTER_OP_OUT_OP_INSERT 0x0 /* enum */ 2547 #define MC_CMD_FILTER_OP_OUT_OP_REMOVE 0x1 /* enum */ 2548 #define MC_CMD_FILTER_OP_OUT_OP_SUBSCRIBE 0x2 /* enum */ 2549 #define MC_CMD_FILTER_OP_OUT_OP_UNSUBSCRIBE 0x3 /* enum */ 2550 #define MC_CMD_FILTER_OP_OUT_HANDLE_OFST 4 2551 2552 2553 /***********************************/ 2554 /* MC_CMD_SET_PF_COUNT 2555 */ 2556 #define MC_CMD_SET_PF_COUNT 0x62 2557 2558 /* MC_CMD_SET_PF_COUNT_IN msgrequest */ 2559 #define MC_CMD_SET_PF_COUNT_IN_LEN 4 2560 #define MC_CMD_SET_PF_COUNT_IN_PF_COUNT_OFST 0 2561 2562 /* MC_CMD_SET_PF_COUNT_OUT msgresponse */ 2563 #define MC_CMD_SET_PF_COUNT_OUT_LEN 0 2564 2565 2566 /***********************************/ 2567 /* MC_CMD_GET_PORT_ASSIGNMENT 2568 */ 2569 #define MC_CMD_GET_PORT_ASSIGNMENT 0x63 2570 2571 /* MC_CMD_GET_PORT_ASSIGNMENT_IN msgrequest */ 2572 #define MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN 0 2573 2574 /* MC_CMD_GET_PORT_ASSIGNMENT_OUT msgresponse */ 2575 #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN 4 2576 #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_PORT_OFST 0 2577 2578 2579 /***********************************/ 2580 /* MC_CMD_SET_PORT_ASSIGNMENT 2581 */ 2582 #define MC_CMD_SET_PORT_ASSIGNMENT 0x64 2583 2584 /* MC_CMD_SET_PORT_ASSIGNMENT_IN msgrequest */ 2585 #define MC_CMD_SET_PORT_ASSIGNMENT_IN_LEN 4 2586 #define MC_CMD_SET_PORT_ASSIGNMENT_IN_PORT_OFST 0 2587 2588 /* MC_CMD_SET_PORT_ASSIGNMENT_OUT msgresponse */ 2589 #define MC_CMD_SET_PORT_ASSIGNMENT_OUT_LEN 0 2590 2591 2592 /***********************************/ 2593 /* MC_CMD_ALLOC_VIS 2594 */ 2595 #define MC_CMD_ALLOC_VIS 0x65 2596 2597 /* MC_CMD_ALLOC_VIS_IN msgrequest */ 2598 #define MC_CMD_ALLOC_VIS_IN_LEN 4 2599 #define MC_CMD_ALLOC_VIS_IN_VI_COUNT_OFST 0 2600 2601 /* MC_CMD_ALLOC_VIS_OUT msgresponse */ 2602 #define MC_CMD_ALLOC_VIS_OUT_LEN 0 2603 2604 2605 /***********************************/ 2606 /* MC_CMD_FREE_VIS 2607 */ 2608 #define MC_CMD_FREE_VIS 0x66 2609 2610 /* MC_CMD_FREE_VIS_IN msgrequest */ 2611 #define MC_CMD_FREE_VIS_IN_LEN 0 2612 2613 /* MC_CMD_FREE_VIS_OUT msgresponse */ 2614 #define MC_CMD_FREE_VIS_OUT_LEN 0 2615 2616 2617 /***********************************/ 2618 /* MC_CMD_GET_SRIOV_CFG 2619 */ 2620 #define MC_CMD_GET_SRIOV_CFG 0x67 2621 2622 /* MC_CMD_GET_SRIOV_CFG_IN msgrequest */ 2623 #define MC_CMD_GET_SRIOV_CFG_IN_LEN 0 2624 2625 /* MC_CMD_GET_SRIOV_CFG_OUT msgresponse */ 2626 #define MC_CMD_GET_SRIOV_CFG_OUT_LEN 20 2627 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_CURRENT_OFST 0 2628 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_MAX_OFST 4 2629 #define MC_CMD_GET_SRIOV_CFG_OUT_FLAGS_OFST 8 2630 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_LBN 0 2631 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_WIDTH 1 2632 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_OFFSET_OFST 12 2633 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_STRIDE_OFST 16 2634 2635 2636 /***********************************/ 2637 /* MC_CMD_SET_SRIOV_CFG 2638 */ 2639 #define MC_CMD_SET_SRIOV_CFG 0x68 2640 2641 /* MC_CMD_SET_SRIOV_CFG_IN msgrequest */ 2642 #define MC_CMD_SET_SRIOV_CFG_IN_LEN 20 2643 #define MC_CMD_SET_SRIOV_CFG_IN_VF_CURRENT_OFST 0 2644 #define MC_CMD_SET_SRIOV_CFG_IN_VF_MAX_OFST 4 2645 #define MC_CMD_SET_SRIOV_CFG_IN_FLAGS_OFST 8 2646 #define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_LBN 0 2647 #define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_WIDTH 1 2648 #define MC_CMD_SET_SRIOV_CFG_IN_VF_OFFSET_OFST 12 2649 #define MC_CMD_SET_SRIOV_CFG_IN_VF_STRIDE_OFST 16 2650 2651 /* MC_CMD_SET_SRIOV_CFG_OUT msgresponse */ 2652 #define MC_CMD_SET_SRIOV_CFG_OUT_LEN 0 2653 2654 2655 /***********************************/ 2656 /* MC_CMD_GET_VI_COUNT 2657 */ 2658 #define MC_CMD_GET_VI_COUNT 0x69 2659 2660 /* MC_CMD_GET_VI_COUNT_IN msgrequest */ 2661 #define MC_CMD_GET_VI_COUNT_IN_LEN 0 2662 2663 /* MC_CMD_GET_VI_COUNT_OUT msgresponse */ 2664 #define MC_CMD_GET_VI_COUNT_OUT_LEN 4 2665 #define MC_CMD_GET_VI_COUNT_OUT_VI_COUNT_OFST 0 2666 2667 2668 /***********************************/ 2669 /* MC_CMD_GET_VECTOR_CFG 2670 */ 2671 #define MC_CMD_GET_VECTOR_CFG 0x70 2672 2673 /* MC_CMD_GET_VECTOR_CFG_IN msgrequest */ 2674 #define MC_CMD_GET_VECTOR_CFG_IN_LEN 0 2675 2676 /* MC_CMD_GET_VECTOR_CFG_OUT msgresponse */ 2677 #define MC_CMD_GET_VECTOR_CFG_OUT_LEN 12 2678 #define MC_CMD_GET_VECTOR_CFG_OUT_VEC_BASE_OFST 0 2679 #define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_PF_OFST 4 2680 #define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_VF_OFST 8 2681 2682 2683 /***********************************/ 2684 /* MC_CMD_SET_VECTOR_CFG 2685 */ 2686 #define MC_CMD_SET_VECTOR_CFG 0x71 2687 2688 /* MC_CMD_SET_VECTOR_CFG_IN msgrequest */ 2689 #define MC_CMD_SET_VECTOR_CFG_IN_LEN 12 2690 #define MC_CMD_SET_VECTOR_CFG_IN_VEC_BASE_OFST 0 2691 #define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_PF_OFST 4 2692 #define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_VF_OFST 8 2693 2694 /* MC_CMD_SET_VECTOR_CFG_OUT msgresponse */ 2695 #define MC_CMD_SET_VECTOR_CFG_OUT_LEN 0 2696 2697 2698 /***********************************/ 2699 /* MC_CMD_ALLOC_PIOBUF 2700 */ 2701 #define MC_CMD_ALLOC_PIOBUF 0x72 2702 2703 /* MC_CMD_ALLOC_PIOBUF_IN msgrequest */ 2704 #define MC_CMD_ALLOC_PIOBUF_IN_LEN 0 2705 2706 /* MC_CMD_ALLOC_PIOBUF_OUT msgresponse */ 2707 #define MC_CMD_ALLOC_PIOBUF_OUT_LEN 4 2708 #define MC_CMD_ALLOC_PIOBUF_OUT_PIOBUF_HANDLE_OFST 0 2709 2710 2711 /***********************************/ 2712 /* MC_CMD_FREE_PIOBUF 2713 */ 2714 #define MC_CMD_FREE_PIOBUF 0x73 2715 2716 /* MC_CMD_FREE_PIOBUF_IN msgrequest */ 2717 #define MC_CMD_FREE_PIOBUF_IN_LEN 4 2718 #define MC_CMD_FREE_PIOBUF_IN_PIOBUF_HANDLE_OFST 0 2719 2720 /* MC_CMD_FREE_PIOBUF_OUT msgresponse */ 2721 #define MC_CMD_FREE_PIOBUF_OUT_LEN 0 2722 2723 2724 /***********************************/ 2725 /* MC_CMD_V2_EXTN 2726 */ 2727 #define MC_CMD_V2_EXTN 0x7f 2728 2729 /* MC_CMD_V2_EXTN_IN msgrequest */ 2730 #define MC_CMD_V2_EXTN_IN_LEN 4 2731 #define MC_CMD_V2_EXTN_IN_EXTENDED_CMD_LBN 0 2732 #define MC_CMD_V2_EXTN_IN_EXTENDED_CMD_WIDTH 15 2733 #define MC_CMD_V2_EXTN_IN_UNUSED_LBN 15 2734 #define MC_CMD_V2_EXTN_IN_UNUSED_WIDTH 1 2735 #define MC_CMD_V2_EXTN_IN_ACTUAL_LEN_LBN 16 2736 #define MC_CMD_V2_EXTN_IN_ACTUAL_LEN_WIDTH 10 2737 #define MC_CMD_V2_EXTN_IN_UNUSED2_LBN 26 2738 #define MC_CMD_V2_EXTN_IN_UNUSED2_WIDTH 6 2739 2740 2741 /***********************************/ 2742 /* MC_CMD_TCM_BUCKET_ALLOC 2743 */ 2744 #define MC_CMD_TCM_BUCKET_ALLOC 0x80 2745 2746 /* MC_CMD_TCM_BUCKET_ALLOC_IN msgrequest */ 2747 #define MC_CMD_TCM_BUCKET_ALLOC_IN_LEN 0 2748 2749 /* MC_CMD_TCM_BUCKET_ALLOC_OUT msgresponse */ 2750 #define MC_CMD_TCM_BUCKET_ALLOC_OUT_LEN 4 2751 #define MC_CMD_TCM_BUCKET_ALLOC_OUT_BUCKET_OFST 0 2752 2753 2754 /***********************************/ 2755 /* MC_CMD_TCM_BUCKET_FREE 2756 */ 2757 #define MC_CMD_TCM_BUCKET_FREE 0x81 2758 2759 /* MC_CMD_TCM_BUCKET_FREE_IN msgrequest */ 2760 #define MC_CMD_TCM_BUCKET_FREE_IN_LEN 4 2761 #define MC_CMD_TCM_BUCKET_FREE_IN_BUCKET_OFST 0 2762 2763 /* MC_CMD_TCM_BUCKET_FREE_OUT msgresponse */ 2764 #define MC_CMD_TCM_BUCKET_FREE_OUT_LEN 0 2765 2766 2767 /***********************************/ 2768 /* MC_CMD_TCM_TXQ_INIT 2769 */ 2770 #define MC_CMD_TCM_TXQ_INIT 0x82 2771 2772 /* MC_CMD_TCM_TXQ_INIT_IN msgrequest */ 2773 #define MC_CMD_TCM_TXQ_INIT_IN_LEN 28 2774 #define MC_CMD_TCM_TXQ_INIT_IN_QID_OFST 0 2775 #define MC_CMD_TCM_TXQ_INIT_IN_LABEL_OFST 4 2776 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAGS_OFST 8 2777 #define MC_CMD_TCM_TXQ_INIT_IN_RP_BKT_OFST 12 2778 #define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT1_OFST 16 2779 #define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT2_OFST 20 2780 #define MC_CMD_TCM_TXQ_INIT_IN_MIN_BKT_OFST 24 2781 2782 /* MC_CMD_TCM_TXQ_INIT_OUT msgresponse */ 2783 #define MC_CMD_TCM_TXQ_INIT_OUT_LEN 0 2784 2785 #endif /* _SIENA_MC_DRIVER_PCOL_H */ 2786