1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright 2008-2013 Solarflare Communications Inc. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 */ 29 30 #ifndef _SIENA_MC_DRIVER_PCOL_H 31 #define _SIENA_MC_DRIVER_PCOL_H 32 33 34 /* Values to be written into FMCR_CZ_RESET_STATE_REG to control boot. */ 35 /* Power-on reset state */ 36 #define MC_FW_STATE_POR (1) 37 /* If this is set in MC_RESET_STATE_REG then it should be 38 * possible to jump into IMEM without loading code from flash. */ 39 #define MC_FW_WARM_BOOT_OK (2) 40 /* The MC main image has started to boot. */ 41 #define MC_FW_STATE_BOOTING (4) 42 /* The Scheduler has started. */ 43 #define MC_FW_STATE_SCHED (8) 44 /* If this is set in MC_RESET_STATE_REG then it should be 45 * possible to jump into IMEM without loading code from flash. 46 * Unlike a warm boot, assume DMEM has been reloaded, so that 47 * the MC persistent data must be reinitialised. */ 48 #define MC_FW_TEPID_BOOT_OK (16) 49 /* We have entered the main firmware via recovery mode. This 50 * means that MC persistent data must be reinitialised, but that 51 * we shouldn't touch PCIe config. */ 52 #define MC_FW_RECOVERY_MODE_PCIE_INIT_OK (32) 53 /* BIST state has been initialized */ 54 #define MC_FW_BIST_INIT_OK (128) 55 56 /* Siena MC shared memmory offsets */ 57 /* The 'doorbell' addresses are hard-wired to alert the MC when written */ 58 #define MC_SMEM_P0_DOORBELL_OFST 0x000 59 #define MC_SMEM_P1_DOORBELL_OFST 0x004 60 /* The rest of these are firmware-defined */ 61 #define MC_SMEM_P0_PDU_OFST 0x008 62 #define MC_SMEM_P1_PDU_OFST 0x108 63 #define MC_SMEM_PDU_LEN 0x100 64 #define MC_SMEM_P0_PTP_TIME_OFST 0x7f0 65 #define MC_SMEM_P0_STATUS_OFST 0x7f8 66 #define MC_SMEM_P1_STATUS_OFST 0x7fc 67 68 /* Values to be written to the per-port status dword in shared 69 * memory on reboot and assert */ 70 #define MC_STATUS_DWORD_REBOOT (0xb007b007) 71 #define MC_STATUS_DWORD_ASSERT (0xdeaddead) 72 73 /* Check whether an mcfw version (in host order) belongs to a bootloader */ 74 #define MC_FW_VERSION_IS_BOOTLOADER(_v) (((_v) >> 16) == 0xb007) 75 76 /* The current version of the MCDI protocol. 77 * 78 * Note that the ROM burnt into the card only talks V0, so at the very 79 * least every driver must support version 0 and MCDI_PCOL_VERSION 80 */ 81 #ifdef WITH_MCDI_V2 82 #define MCDI_PCOL_VERSION 2 83 #else 84 #define MCDI_PCOL_VERSION 1 85 #endif 86 87 /* Unused commands: 0x23, 0x27, 0x30, 0x31 */ 88 89 /* MCDI version 1 90 * 91 * Each MCDI request starts with an MCDI_HEADER, which is a 32bit 92 * structure, filled in by the client. 93 * 94 * 0 7 8 16 20 22 23 24 31 95 * | CODE | R | LEN | SEQ | Rsvd | E | R | XFLAGS | 96 * | | | 97 * | | \--- Response 98 * | \------- Error 99 * \------------------------------ Resync (always set) 100 * 101 * The client writes it's request into MC shared memory, and rings the 102 * doorbell. Each request is completed by either by the MC writting 103 * back into shared memory, or by writting out an event. 104 * 105 * All MCDI commands support completion by shared memory response. Each 106 * request may also contain additional data (accounted for by HEADER.LEN), 107 * and some response's may also contain additional data (again, accounted 108 * for by HEADER.LEN). 109 * 110 * Some MCDI commands support completion by event, in which any associated 111 * response data is included in the event. 112 * 113 * The protocol requires one response to be delivered for every request, a 114 * request should not be sent unless the response for the previous request 115 * has been received (either by polling shared memory, or by receiving 116 * an event). 117 */ 118 119 /** Request/Response structure */ 120 #define MCDI_HEADER_OFST 0 121 #define MCDI_HEADER_CODE_LBN 0 122 #define MCDI_HEADER_CODE_WIDTH 7 123 #define MCDI_HEADER_RESYNC_LBN 7 124 #define MCDI_HEADER_RESYNC_WIDTH 1 125 #define MCDI_HEADER_DATALEN_LBN 8 126 #define MCDI_HEADER_DATALEN_WIDTH 8 127 #define MCDI_HEADER_SEQ_LBN 16 128 #define MCDI_HEADER_SEQ_WIDTH 4 129 #define MCDI_HEADER_RSVD_LBN 20 130 #define MCDI_HEADER_RSVD_WIDTH 1 131 #define MCDI_HEADER_NOT_EPOCH_LBN 21 132 #define MCDI_HEADER_NOT_EPOCH_WIDTH 1 133 #define MCDI_HEADER_ERROR_LBN 22 134 #define MCDI_HEADER_ERROR_WIDTH 1 135 #define MCDI_HEADER_RESPONSE_LBN 23 136 #define MCDI_HEADER_RESPONSE_WIDTH 1 137 #define MCDI_HEADER_XFLAGS_LBN 24 138 #define MCDI_HEADER_XFLAGS_WIDTH 8 139 /* Request response using event */ 140 #define MCDI_HEADER_XFLAGS_EVREQ 0x01 141 /* Request (and signal) early doorbell return */ 142 #define MCDI_HEADER_XFLAGS_DBRET 0x02 143 144 /* Maximum number of payload bytes */ 145 #define MCDI_CTL_SDU_LEN_MAX_V1 0xfc 146 #define MCDI_CTL_SDU_LEN_MAX_V2 0x400 147 148 #ifdef WITH_MCDI_V2 149 #define MCDI_CTL_SDU_LEN_MAX MCDI_CTL_SDU_LEN_MAX_V2 150 #else 151 #define MCDI_CTL_SDU_LEN_MAX MCDI_CTL_SDU_LEN_MAX_V1 152 #endif 153 154 155 /* The MC can generate events for two reasons: 156 * - To advance a shared memory request if XFLAGS_EVREQ was set 157 * - As a notification (link state, i2c event), controlled 158 * via MC_CMD_LOG_CTRL 159 * 160 * Both events share a common structure: 161 * 162 * 0 32 33 36 44 52 60 163 * | Data | Cont | Level | Src | Code | Rsvd | 164 * | 165 * \ There is another event pending in this notification 166 * 167 * If Code==CMDDONE, then the fields are further interpreted as: 168 * 169 * - LEVEL==INFO Command succeeded 170 * - LEVEL==ERR Command failed 171 * 172 * 0 8 16 24 32 173 * | Seq | Datalen | Errno | Rsvd | 174 * 175 * These fields are taken directly out of the standard MCDI header, i.e., 176 * LEVEL==ERR, Datalen == 0 => Reboot 177 * 178 * Events can be squirted out of the UART (using LOG_CTRL) without a 179 * MCDI header. An event can be distinguished from a MCDI response by 180 * examining the first byte which is 0xc0. This corresponds to the 181 * non-existent MCDI command MC_CMD_DEBUG_LOG. 182 * 183 * 0 7 8 184 * | command | Resync | = 0xc0 185 * 186 * Since the event is written in big-endian byte order, this works 187 * providing bits 56-63 of the event are 0xc0. 188 * 189 * 56 60 63 190 * | Rsvd | Code | = 0xc0 191 * 192 * Which means for convenience the event code is 0xc for all MC 193 * generated events. 194 */ 195 #define FSE_AZ_EV_CODE_MCDI_EVRESPONSE 0xc 196 197 198 /* Operation not permitted. */ 199 #define MC_CMD_ERR_EPERM 1 200 /* Non-existent command target */ 201 #define MC_CMD_ERR_ENOENT 2 202 /* assert() has killed the MC */ 203 #define MC_CMD_ERR_EINTR 4 204 /* I/O failure */ 205 #define MC_CMD_ERR_EIO 5 206 /* Already exists */ 207 #define MC_CMD_ERR_EEXIST 6 208 /* Try again */ 209 #define MC_CMD_ERR_EAGAIN 11 210 /* Out of memory */ 211 #define MC_CMD_ERR_ENOMEM 12 212 /* Caller does not hold required locks */ 213 #define MC_CMD_ERR_EACCES 13 214 /* Resource is currently unavailable (e.g. lock contention) */ 215 #define MC_CMD_ERR_EBUSY 16 216 /* No such device */ 217 #define MC_CMD_ERR_ENODEV 19 218 /* Invalid argument to target */ 219 #define MC_CMD_ERR_EINVAL 22 220 /* Broken pipe */ 221 #define MC_CMD_ERR_EPIPE 32 222 /* Read-only */ 223 #define MC_CMD_ERR_EROFS 30 224 /* Out of range */ 225 #define MC_CMD_ERR_ERANGE 34 226 /* Non-recursive resource is already acquired */ 227 #define MC_CMD_ERR_EDEADLK 35 228 /* Operation not implemented */ 229 #define MC_CMD_ERR_ENOSYS 38 230 /* Operation timed out */ 231 #define MC_CMD_ERR_ETIME 62 232 /* Link has been severed */ 233 #define MC_CMD_ERR_ENOLINK 67 234 /* Protocol error */ 235 #define MC_CMD_ERR_EPROTO 71 236 /* Operation not supported */ 237 #define MC_CMD_ERR_ENOTSUP 95 238 /* Address not available */ 239 #define MC_CMD_ERR_EADDRNOTAVAIL 99 240 /* Not connected */ 241 #define MC_CMD_ERR_ENOTCONN 107 242 /* Operation already in progress */ 243 #define MC_CMD_ERR_EALREADY 114 244 245 /* Resource allocation failed. */ 246 #define MC_CMD_ERR_ALLOC_FAIL 0x1000 247 /* V-adaptor not found. */ 248 #define MC_CMD_ERR_NO_VADAPTOR 0x1001 249 /* EVB port not found. */ 250 #define MC_CMD_ERR_NO_EVB_PORT 0x1002 251 /* V-switch not found. */ 252 #define MC_CMD_ERR_NO_VSWITCH 0x1003 253 /* Too many VLAN tags. */ 254 #define MC_CMD_ERR_VLAN_LIMIT 0x1004 255 /* Bad PCI function number. */ 256 #define MC_CMD_ERR_BAD_PCI_FUNC 0x1005 257 /* Invalid VLAN mode. */ 258 #define MC_CMD_ERR_BAD_VLAN_MODE 0x1006 259 /* Invalid v-switch type. */ 260 #define MC_CMD_ERR_BAD_VSWITCH_TYPE 0x1007 261 /* Invalid v-port type. */ 262 #define MC_CMD_ERR_BAD_VPORT_TYPE 0x1008 263 /* MAC address exists. */ 264 #define MC_CMD_ERR_MAC_EXIST 0x1009 265 /* Slave core not present */ 266 #define MC_CMD_ERR_SLAVE_NOT_PRESENT 0x100a 267 /* The datapath is disabled. */ 268 #define MC_CMD_ERR_DATAPATH_DISABLED 0x100b 269 /* The requesting client is not a function */ 270 #define MC_CMD_ERR_CLIENT_NOT_FN 0x100c 271 /* The requested operation might require the 272 command to be passed between MCs, and the 273 transport doesn't support that. Should 274 only ever been seen over the UART. */ 275 #define MC_CMD_ERR_TRANSPORT_NOPROXY 0x100d 276 /* VLAN tag(s) exists */ 277 #define MC_CMD_ERR_VLAN_EXIST 0x100e 278 /* No MAC address assigned to an EVB port */ 279 #define MC_CMD_ERR_NO_MAC_ADDR 0x100f 280 /* Notifies the driver that the request has been relayed 281 * to an admin function for authorization. The driver should 282 * wait for a PROXY_RESPONSE event and then resend its request. 283 * This error code is followed by a 32-bit handle that 284 * helps matching it with the respective PROXY_RESPONSE event. */ 285 #define MC_CMD_ERR_PROXY_PENDING 0x1010 286 #define MC_CMD_ERR_PROXY_PENDING_HANDLE_OFST 4 287 /* The request cannot be passed for authorization because 288 * another request from the same function is currently being 289 * authorized. The drvier should try again later. */ 290 #define MC_CMD_ERR_PROXY_INPROGRESS 0x1011 291 /* Returned by MC_CMD_PROXY_COMPLETE if the caller is not the function 292 * that has enabled proxying or BLOCK_INDEX points to a function that 293 * doesn't await an authorization. */ 294 #define MC_CMD_ERR_PROXY_UNEXPECTED 0x1012 295 /* This code is currently only used internally in FW. Its meaning is that 296 * an operation failed due to lack of SR-IOV privilege. 297 * Normally it is translated to EPERM by send_cmd_err(), 298 * but it may also be used to trigger some special mechanism 299 * for handling such case, e.g. to relay the failed request 300 * to a designated admin function for authorization. */ 301 #define MC_CMD_ERR_NO_PRIVILEGE 0x1013 302 /* Workaround 26807 could not be turned on/off because some functions 303 * have already installed filters. See the comment at 304 * MC_CMD_WORKAROUND_BUG26807. */ 305 #define MC_CMD_ERR_FILTERS_PRESENT 0x1014 306 /* The clock whose frequency you've attempted to set set 307 * doesn't exist on this NIC */ 308 #define MC_CMD_ERR_NO_CLOCK 0x1015 309 /* Returned by MC_CMD_TESTASSERT if the action that should 310 * have caused an assertion failed to do so. */ 311 #define MC_CMD_ERR_UNREACHABLE 0x1016 312 /* This command needs to be processed in the background but there were no 313 * resources to do so. Send it again after a command has completed. */ 314 #define MC_CMD_ERR_QUEUE_FULL 0x1017 315 316 #define MC_CMD_ERR_CODE_OFST 0 317 318 /* We define 8 "escape" commands to allow 319 for command number space extension */ 320 321 #define MC_CMD_CMD_SPACE_ESCAPE_0 0x78 322 #define MC_CMD_CMD_SPACE_ESCAPE_1 0x79 323 #define MC_CMD_CMD_SPACE_ESCAPE_2 0x7A 324 #define MC_CMD_CMD_SPACE_ESCAPE_3 0x7B 325 #define MC_CMD_CMD_SPACE_ESCAPE_4 0x7C 326 #define MC_CMD_CMD_SPACE_ESCAPE_5 0x7D 327 #define MC_CMD_CMD_SPACE_ESCAPE_6 0x7E 328 #define MC_CMD_CMD_SPACE_ESCAPE_7 0x7F 329 330 /* Vectors in the boot ROM */ 331 /* Point to the copycode entry point. */ 332 #define SIENA_MC_BOOTROM_COPYCODE_VEC (0x800 - 3 * 0x4) 333 #define HUNT_MC_BOOTROM_COPYCODE_VEC (0x8000 - 3 * 0x4) 334 #define MEDFORD_MC_BOOTROM_COPYCODE_VEC (0x10000 - 3 * 0x4) 335 /* Points to the recovery mode entry point. */ 336 #define SIENA_MC_BOOTROM_NOFLASH_VEC (0x800 - 2 * 0x4) 337 #define HUNT_MC_BOOTROM_NOFLASH_VEC (0x8000 - 2 * 0x4) 338 #define MEDFORD_MC_BOOTROM_NOFLASH_VEC (0x10000 - 2 * 0x4) 339 340 /* The command set exported by the boot ROM (MCDI v0) */ 341 #define MC_CMD_GET_VERSION_V0_SUPPORTED_FUNCS { \ 342 (1 << MC_CMD_READ32) | \ 343 (1 << MC_CMD_WRITE32) | \ 344 (1 << MC_CMD_COPYCODE) | \ 345 (1 << MC_CMD_GET_VERSION), \ 346 0, 0, 0 } 347 348 #define MC_CMD_SENSOR_INFO_OUT_OFFSET_OFST(_x) \ 349 (MC_CMD_SENSOR_ENTRY_OFST + (_x)) 350 351 #define MC_CMD_DBI_WRITE_IN_ADDRESS_OFST(n) \ 352 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \ 353 MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST + \ 354 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN) 355 356 #define MC_CMD_DBI_WRITE_IN_BYTE_MASK_OFST(n) \ 357 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \ 358 MC_CMD_DBIWROP_TYPEDEF_BYTE_MASK_OFST + \ 359 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN) 360 361 #define MC_CMD_DBI_WRITE_IN_VALUE_OFST(n) \ 362 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \ 363 MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST + \ 364 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN) 365 366 /* This may be ORed with an EVB_PORT_ID_xxx constant to pass a non-default 367 * stack ID (which must be in the range 1-255) along with an EVB port ID. 368 */ 369 #define EVB_STACK_ID(n) (((n) & 0xff) << 16) 370 371 372 #ifdef WITH_MCDI_V2 373 374 /* Version 2 adds an optional argument to error returns: the errno value 375 * may be followed by the (0-based) number of the first argument that 376 * could not be processed. 377 */ 378 #define MC_CMD_ERR_ARG_OFST 4 379 380 /* No space */ 381 #define MC_CMD_ERR_ENOSPC 28 382 383 #endif 384 385 /* MCDI_EVENT structuredef */ 386 #define MCDI_EVENT_LEN 8 387 #define MCDI_EVENT_CONT_LBN 32 388 #define MCDI_EVENT_CONT_WIDTH 1 389 #define MCDI_EVENT_LEVEL_LBN 33 390 #define MCDI_EVENT_LEVEL_WIDTH 3 391 /* enum: Info. */ 392 #define MCDI_EVENT_LEVEL_INFO 0x0 393 /* enum: Warning. */ 394 #define MCDI_EVENT_LEVEL_WARN 0x1 395 /* enum: Error. */ 396 #define MCDI_EVENT_LEVEL_ERR 0x2 397 /* enum: Fatal. */ 398 #define MCDI_EVENT_LEVEL_FATAL 0x3 399 #define MCDI_EVENT_DATA_OFST 0 400 #define MCDI_EVENT_CMDDONE_SEQ_LBN 0 401 #define MCDI_EVENT_CMDDONE_SEQ_WIDTH 8 402 #define MCDI_EVENT_CMDDONE_DATALEN_LBN 8 403 #define MCDI_EVENT_CMDDONE_DATALEN_WIDTH 8 404 #define MCDI_EVENT_CMDDONE_ERRNO_LBN 16 405 #define MCDI_EVENT_CMDDONE_ERRNO_WIDTH 8 406 #define MCDI_EVENT_LINKCHANGE_LP_CAP_LBN 0 407 #define MCDI_EVENT_LINKCHANGE_LP_CAP_WIDTH 16 408 #define MCDI_EVENT_LINKCHANGE_SPEED_LBN 16 409 #define MCDI_EVENT_LINKCHANGE_SPEED_WIDTH 4 410 /* enum: 100Mbs */ 411 #define MCDI_EVENT_LINKCHANGE_SPEED_100M 0x1 412 /* enum: 1Gbs */ 413 #define MCDI_EVENT_LINKCHANGE_SPEED_1G 0x2 414 /* enum: 10Gbs */ 415 #define MCDI_EVENT_LINKCHANGE_SPEED_10G 0x3 416 /* enum: 40Gbs */ 417 #define MCDI_EVENT_LINKCHANGE_SPEED_40G 0x4 418 #define MCDI_EVENT_LINKCHANGE_FCNTL_LBN 20 419 #define MCDI_EVENT_LINKCHANGE_FCNTL_WIDTH 4 420 #define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_LBN 24 421 #define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_WIDTH 8 422 #define MCDI_EVENT_SENSOREVT_MONITOR_LBN 0 423 #define MCDI_EVENT_SENSOREVT_MONITOR_WIDTH 8 424 #define MCDI_EVENT_SENSOREVT_STATE_LBN 8 425 #define MCDI_EVENT_SENSOREVT_STATE_WIDTH 8 426 #define MCDI_EVENT_SENSOREVT_VALUE_LBN 16 427 #define MCDI_EVENT_SENSOREVT_VALUE_WIDTH 16 428 #define MCDI_EVENT_FWALERT_DATA_LBN 8 429 #define MCDI_EVENT_FWALERT_DATA_WIDTH 24 430 #define MCDI_EVENT_FWALERT_REASON_LBN 0 431 #define MCDI_EVENT_FWALERT_REASON_WIDTH 8 432 /* enum: SRAM Access. */ 433 #define MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS 0x1 434 #define MCDI_EVENT_FLR_VF_LBN 0 435 #define MCDI_EVENT_FLR_VF_WIDTH 8 436 #define MCDI_EVENT_TX_ERR_TXQ_LBN 0 437 #define MCDI_EVENT_TX_ERR_TXQ_WIDTH 12 438 #define MCDI_EVENT_TX_ERR_TYPE_LBN 12 439 #define MCDI_EVENT_TX_ERR_TYPE_WIDTH 4 440 /* enum: Descriptor loader reported failure */ 441 #define MCDI_EVENT_TX_ERR_DL_FAIL 0x1 442 /* enum: Descriptor ring empty and no EOP seen for packet */ 443 #define MCDI_EVENT_TX_ERR_NO_EOP 0x2 444 /* enum: Overlength packet */ 445 #define MCDI_EVENT_TX_ERR_2BIG 0x3 446 /* enum: Malformed option descriptor */ 447 #define MCDI_EVENT_TX_BAD_OPTDESC 0x5 448 /* enum: Option descriptor part way through a packet */ 449 #define MCDI_EVENT_TX_OPT_IN_PKT 0x8 450 /* enum: DMA or PIO data access error */ 451 #define MCDI_EVENT_TX_ERR_BAD_DMA_OR_PIO 0x9 452 #define MCDI_EVENT_TX_ERR_INFO_LBN 16 453 #define MCDI_EVENT_TX_ERR_INFO_WIDTH 16 454 #define MCDI_EVENT_TX_FLUSH_TO_DRIVER_LBN 12 455 #define MCDI_EVENT_TX_FLUSH_TO_DRIVER_WIDTH 1 456 #define MCDI_EVENT_TX_FLUSH_TXQ_LBN 0 457 #define MCDI_EVENT_TX_FLUSH_TXQ_WIDTH 12 458 #define MCDI_EVENT_PTP_ERR_TYPE_LBN 0 459 #define MCDI_EVENT_PTP_ERR_TYPE_WIDTH 8 460 /* enum: PLL lost lock */ 461 #define MCDI_EVENT_PTP_ERR_PLL_LOST 0x1 462 /* enum: Filter overflow (PDMA) */ 463 #define MCDI_EVENT_PTP_ERR_FILTER 0x2 464 /* enum: FIFO overflow (FPGA) */ 465 #define MCDI_EVENT_PTP_ERR_FIFO 0x3 466 /* enum: Merge queue overflow */ 467 #define MCDI_EVENT_PTP_ERR_QUEUE 0x4 468 #define MCDI_EVENT_AOE_ERR_TYPE_LBN 0 469 #define MCDI_EVENT_AOE_ERR_TYPE_WIDTH 8 470 /* enum: AOE failed to load - no valid image? */ 471 #define MCDI_EVENT_AOE_NO_LOAD 0x1 472 /* enum: AOE FC reported an exception */ 473 #define MCDI_EVENT_AOE_FC_ASSERT 0x2 474 /* enum: AOE FC watchdogged */ 475 #define MCDI_EVENT_AOE_FC_WATCHDOG 0x3 476 /* enum: AOE FC failed to start */ 477 #define MCDI_EVENT_AOE_FC_NO_START 0x4 478 /* enum: Generic AOE fault - likely to have been reported via other means too 479 * but intended for use by aoex driver. 480 */ 481 #define MCDI_EVENT_AOE_FAULT 0x5 482 /* enum: Results of reprogramming the CPLD (status in AOE_ERR_DATA) */ 483 #define MCDI_EVENT_AOE_CPLD_REPROGRAMMED 0x6 484 /* enum: AOE loaded successfully */ 485 #define MCDI_EVENT_AOE_LOAD 0x7 486 /* enum: AOE DMA operation completed (LSB of HOST_HANDLE in AOE_ERR_DATA) */ 487 #define MCDI_EVENT_AOE_DMA 0x8 488 /* enum: AOE byteblaster connected/disconnected (Connection status in 489 * AOE_ERR_DATA) 490 */ 491 #define MCDI_EVENT_AOE_BYTEBLASTER 0x9 492 /* enum: DDR ECC status update */ 493 #define MCDI_EVENT_AOE_DDR_ECC_STATUS 0xa 494 /* enum: PTP status update */ 495 #define MCDI_EVENT_AOE_PTP_STATUS 0xb 496 /* enum: FPGA header incorrect */ 497 #define MCDI_EVENT_AOE_FPGA_LOAD_HEADER_ERR 0xc 498 /* enum: FPGA Powered Off due to error in powering up FPGA */ 499 #define MCDI_EVENT_AOE_FPGA_POWER_OFF 0xd 500 /* enum: AOE FPGA load failed due to MC to MUM communication failure */ 501 #define MCDI_EVENT_AOE_FPGA_LOAD_FAILED 0xe 502 /* enum: Notify that invalid flash type detected */ 503 #define MCDI_EVENT_AOE_INVALID_FPGA_FLASH_TYPE 0xf 504 /* enum: Notify that the attempt to run FPGA Controller firmware timedout */ 505 #define MCDI_EVENT_AOE_FC_RUN_TIMEDOUT 0x10 506 #define MCDI_EVENT_AOE_ERR_DATA_LBN 8 507 #define MCDI_EVENT_AOE_ERR_DATA_WIDTH 8 508 #define MCDI_EVENT_AOE_ERR_CODE_FPGA_HEADER_VERIFY_FAILED_LBN 8 509 #define MCDI_EVENT_AOE_ERR_CODE_FPGA_HEADER_VERIFY_FAILED_WIDTH 8 510 /* enum: Reading from NV failed */ 511 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_NV_READ_FAIL 0x0 512 /* enum: Invalid Magic Number if FPGA header */ 513 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_MAGIC_FAIL 0x1 514 /* enum: Invalid Silicon type detected in header */ 515 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_SILICON_TYPE 0x2 516 /* enum: Unsupported VRatio */ 517 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_VRATIO 0x3 518 /* enum: Unsupported DDR Type */ 519 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_TYPE 0x4 520 /* enum: DDR Voltage out of supported range */ 521 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_VOLTAGE 0x5 522 /* enum: Unsupported DDR speed */ 523 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_SPEED 0x6 524 /* enum: Unsupported DDR size */ 525 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_SIZE 0x7 526 /* enum: Unsupported DDR rank */ 527 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_RANK 0x8 528 #define MCDI_EVENT_AOE_ERR_CODE_INVALID_FPGA_FLASH_TYPE_INFO_LBN 8 529 #define MCDI_EVENT_AOE_ERR_CODE_INVALID_FPGA_FLASH_TYPE_INFO_WIDTH 8 530 /* enum: Primary boot flash */ 531 #define MCDI_EVENT_AOE_FLASH_TYPE_BOOT_PRIMARY 0x0 532 /* enum: Secondary boot flash */ 533 #define MCDI_EVENT_AOE_FLASH_TYPE_BOOT_SECONDARY 0x1 534 #define MCDI_EVENT_AOE_ERR_CODE_FPGA_POWER_OFF_LBN 8 535 #define MCDI_EVENT_AOE_ERR_CODE_FPGA_POWER_OFF_WIDTH 8 536 #define MCDI_EVENT_AOE_ERR_CODE_FPGA_LOAD_FAILED_LBN 8 537 #define MCDI_EVENT_AOE_ERR_CODE_FPGA_LOAD_FAILED_WIDTH 8 538 #define MCDI_EVENT_RX_ERR_RXQ_LBN 0 539 #define MCDI_EVENT_RX_ERR_RXQ_WIDTH 12 540 #define MCDI_EVENT_RX_ERR_TYPE_LBN 12 541 #define MCDI_EVENT_RX_ERR_TYPE_WIDTH 4 542 #define MCDI_EVENT_RX_ERR_INFO_LBN 16 543 #define MCDI_EVENT_RX_ERR_INFO_WIDTH 16 544 #define MCDI_EVENT_RX_FLUSH_TO_DRIVER_LBN 12 545 #define MCDI_EVENT_RX_FLUSH_TO_DRIVER_WIDTH 1 546 #define MCDI_EVENT_RX_FLUSH_RXQ_LBN 0 547 #define MCDI_EVENT_RX_FLUSH_RXQ_WIDTH 12 548 #define MCDI_EVENT_MC_REBOOT_COUNT_LBN 0 549 #define MCDI_EVENT_MC_REBOOT_COUNT_WIDTH 16 550 #define MCDI_EVENT_MUM_ERR_TYPE_LBN 0 551 #define MCDI_EVENT_MUM_ERR_TYPE_WIDTH 8 552 /* enum: MUM failed to load - no valid image? */ 553 #define MCDI_EVENT_MUM_NO_LOAD 0x1 554 /* enum: MUM f/w reported an exception */ 555 #define MCDI_EVENT_MUM_ASSERT 0x2 556 /* enum: MUM not kicking watchdog */ 557 #define MCDI_EVENT_MUM_WATCHDOG 0x3 558 #define MCDI_EVENT_MUM_ERR_DATA_LBN 8 559 #define MCDI_EVENT_MUM_ERR_DATA_WIDTH 8 560 #define MCDI_EVENT_DATA_LBN 0 561 #define MCDI_EVENT_DATA_WIDTH 32 562 #define MCDI_EVENT_SRC_LBN 36 563 #define MCDI_EVENT_SRC_WIDTH 8 564 #define MCDI_EVENT_EV_CODE_LBN 60 565 #define MCDI_EVENT_EV_CODE_WIDTH 4 566 #define MCDI_EVENT_CODE_LBN 44 567 #define MCDI_EVENT_CODE_WIDTH 8 568 /* enum: Event generated by host software */ 569 #define MCDI_EVENT_SW_EVENT 0x0 570 /* enum: Bad assert. */ 571 #define MCDI_EVENT_CODE_BADSSERT 0x1 572 /* enum: PM Notice. */ 573 #define MCDI_EVENT_CODE_PMNOTICE 0x2 574 /* enum: Command done. */ 575 #define MCDI_EVENT_CODE_CMDDONE 0x3 576 /* enum: Link change. */ 577 #define MCDI_EVENT_CODE_LINKCHANGE 0x4 578 /* enum: Sensor Event. */ 579 #define MCDI_EVENT_CODE_SENSOREVT 0x5 580 /* enum: Schedule error. */ 581 #define MCDI_EVENT_CODE_SCHEDERR 0x6 582 /* enum: Reboot. */ 583 #define MCDI_EVENT_CODE_REBOOT 0x7 584 /* enum: Mac stats DMA. */ 585 #define MCDI_EVENT_CODE_MAC_STATS_DMA 0x8 586 /* enum: Firmware alert. */ 587 #define MCDI_EVENT_CODE_FWALERT 0x9 588 /* enum: Function level reset. */ 589 #define MCDI_EVENT_CODE_FLR 0xa 590 /* enum: Transmit error */ 591 #define MCDI_EVENT_CODE_TX_ERR 0xb 592 /* enum: Tx flush has completed */ 593 #define MCDI_EVENT_CODE_TX_FLUSH 0xc 594 /* enum: PTP packet received timestamp */ 595 #define MCDI_EVENT_CODE_PTP_RX 0xd 596 /* enum: PTP NIC failure */ 597 #define MCDI_EVENT_CODE_PTP_FAULT 0xe 598 /* enum: PTP PPS event */ 599 #define MCDI_EVENT_CODE_PTP_PPS 0xf 600 /* enum: Rx flush has completed */ 601 #define MCDI_EVENT_CODE_RX_FLUSH 0x10 602 /* enum: Receive error */ 603 #define MCDI_EVENT_CODE_RX_ERR 0x11 604 /* enum: AOE fault */ 605 #define MCDI_EVENT_CODE_AOE 0x12 606 /* enum: Network port calibration failed (VCAL). */ 607 #define MCDI_EVENT_CODE_VCAL_FAIL 0x13 608 /* enum: HW PPS event */ 609 #define MCDI_EVENT_CODE_HW_PPS 0x14 610 /* enum: The MC has rebooted (huntington and later, siena uses CODE_REBOOT and 611 * a different format) 612 */ 613 #define MCDI_EVENT_CODE_MC_REBOOT 0x15 614 /* enum: the MC has detected a parity error */ 615 #define MCDI_EVENT_CODE_PAR_ERR 0x16 616 /* enum: the MC has detected a correctable error */ 617 #define MCDI_EVENT_CODE_ECC_CORR_ERR 0x17 618 /* enum: the MC has detected an uncorrectable error */ 619 #define MCDI_EVENT_CODE_ECC_FATAL_ERR 0x18 620 /* enum: The MC has entered offline BIST mode */ 621 #define MCDI_EVENT_CODE_MC_BIST 0x19 622 /* enum: PTP tick event providing current NIC time */ 623 #define MCDI_EVENT_CODE_PTP_TIME 0x1a 624 /* enum: MUM fault */ 625 #define MCDI_EVENT_CODE_MUM 0x1b 626 /* enum: notify the designated PF of a new authorization request */ 627 #define MCDI_EVENT_CODE_PROXY_REQUEST 0x1c 628 /* enum: notify a function that awaits an authorization that its request has 629 * been processed and it may now resend the command 630 */ 631 #define MCDI_EVENT_CODE_PROXY_RESPONSE 0x1d 632 /* enum: Artificial event generated by host and posted via MC for test 633 * purposes. 634 */ 635 #define MCDI_EVENT_CODE_TESTGEN 0xfa 636 #define MCDI_EVENT_CMDDONE_DATA_OFST 0 637 #define MCDI_EVENT_CMDDONE_DATA_LBN 0 638 #define MCDI_EVENT_CMDDONE_DATA_WIDTH 32 639 #define MCDI_EVENT_LINKCHANGE_DATA_OFST 0 640 #define MCDI_EVENT_LINKCHANGE_DATA_LBN 0 641 #define MCDI_EVENT_LINKCHANGE_DATA_WIDTH 32 642 #define MCDI_EVENT_SENSOREVT_DATA_OFST 0 643 #define MCDI_EVENT_SENSOREVT_DATA_LBN 0 644 #define MCDI_EVENT_SENSOREVT_DATA_WIDTH 32 645 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_OFST 0 646 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_LBN 0 647 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_WIDTH 32 648 #define MCDI_EVENT_TX_ERR_DATA_OFST 0 649 #define MCDI_EVENT_TX_ERR_DATA_LBN 0 650 #define MCDI_EVENT_TX_ERR_DATA_WIDTH 32 651 /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the seconds field of 652 * timestamp 653 */ 654 #define MCDI_EVENT_PTP_SECONDS_OFST 0 655 #define MCDI_EVENT_PTP_SECONDS_LBN 0 656 #define MCDI_EVENT_PTP_SECONDS_WIDTH 32 657 /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the major field of 658 * timestamp 659 */ 660 #define MCDI_EVENT_PTP_MAJOR_OFST 0 661 #define MCDI_EVENT_PTP_MAJOR_LBN 0 662 #define MCDI_EVENT_PTP_MAJOR_WIDTH 32 663 /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the nanoseconds field 664 * of timestamp 665 */ 666 #define MCDI_EVENT_PTP_NANOSECONDS_OFST 0 667 #define MCDI_EVENT_PTP_NANOSECONDS_LBN 0 668 #define MCDI_EVENT_PTP_NANOSECONDS_WIDTH 32 669 /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the minor field of 670 * timestamp 671 */ 672 #define MCDI_EVENT_PTP_MINOR_OFST 0 673 #define MCDI_EVENT_PTP_MINOR_LBN 0 674 #define MCDI_EVENT_PTP_MINOR_WIDTH 32 675 /* For CODE_PTP_RX events, the lowest four bytes of sourceUUID from PTP packet 676 */ 677 #define MCDI_EVENT_PTP_UUID_OFST 0 678 #define MCDI_EVENT_PTP_UUID_LBN 0 679 #define MCDI_EVENT_PTP_UUID_WIDTH 32 680 #define MCDI_EVENT_RX_ERR_DATA_OFST 0 681 #define MCDI_EVENT_RX_ERR_DATA_LBN 0 682 #define MCDI_EVENT_RX_ERR_DATA_WIDTH 32 683 #define MCDI_EVENT_PAR_ERR_DATA_OFST 0 684 #define MCDI_EVENT_PAR_ERR_DATA_LBN 0 685 #define MCDI_EVENT_PAR_ERR_DATA_WIDTH 32 686 #define MCDI_EVENT_ECC_CORR_ERR_DATA_OFST 0 687 #define MCDI_EVENT_ECC_CORR_ERR_DATA_LBN 0 688 #define MCDI_EVENT_ECC_CORR_ERR_DATA_WIDTH 32 689 #define MCDI_EVENT_ECC_FATAL_ERR_DATA_OFST 0 690 #define MCDI_EVENT_ECC_FATAL_ERR_DATA_LBN 0 691 #define MCDI_EVENT_ECC_FATAL_ERR_DATA_WIDTH 32 692 /* For CODE_PTP_TIME events, the major value of the PTP clock */ 693 #define MCDI_EVENT_PTP_TIME_MAJOR_OFST 0 694 #define MCDI_EVENT_PTP_TIME_MAJOR_LBN 0 695 #define MCDI_EVENT_PTP_TIME_MAJOR_WIDTH 32 696 /* For CODE_PTP_TIME events, bits 19-26 of the minor value of the PTP clock */ 697 #define MCDI_EVENT_PTP_TIME_MINOR_26_19_LBN 36 698 #define MCDI_EVENT_PTP_TIME_MINOR_26_19_WIDTH 8 699 /* For CODE_PTP_TIME events where report sync status is enabled, indicates 700 * whether the NIC clock has ever been set 701 */ 702 #define MCDI_EVENT_PTP_TIME_NIC_CLOCK_VALID_LBN 36 703 #define MCDI_EVENT_PTP_TIME_NIC_CLOCK_VALID_WIDTH 1 704 /* For CODE_PTP_TIME events where report sync status is enabled, indicates 705 * whether the NIC and System clocks are in sync 706 */ 707 #define MCDI_EVENT_PTP_TIME_HOST_NIC_IN_SYNC_LBN 37 708 #define MCDI_EVENT_PTP_TIME_HOST_NIC_IN_SYNC_WIDTH 1 709 /* For CODE_PTP_TIME events where report sync status is enabled, bits 21-26 of 710 * the minor value of the PTP clock 711 */ 712 #define MCDI_EVENT_PTP_TIME_MINOR_26_21_LBN 38 713 #define MCDI_EVENT_PTP_TIME_MINOR_26_21_WIDTH 6 714 #define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_OFST 0 715 #define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_LBN 0 716 #define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_WIDTH 32 717 #define MCDI_EVENT_PROXY_RESPONSE_HANDLE_OFST 0 718 #define MCDI_EVENT_PROXY_RESPONSE_HANDLE_LBN 0 719 #define MCDI_EVENT_PROXY_RESPONSE_HANDLE_WIDTH 32 720 /* Zero means that the request has been completed or authorized, and the driver 721 * should resend it. A non-zero value means that the authorization has been 722 * denied, and gives the reason. Typically it will be EPERM. 723 */ 724 #define MCDI_EVENT_PROXY_RESPONSE_RC_LBN 36 725 #define MCDI_EVENT_PROXY_RESPONSE_RC_WIDTH 8 726 727 /* FCDI_EVENT structuredef */ 728 #define FCDI_EVENT_LEN 8 729 #define FCDI_EVENT_CONT_LBN 32 730 #define FCDI_EVENT_CONT_WIDTH 1 731 #define FCDI_EVENT_LEVEL_LBN 33 732 #define FCDI_EVENT_LEVEL_WIDTH 3 733 /* enum: Info. */ 734 #define FCDI_EVENT_LEVEL_INFO 0x0 735 /* enum: Warning. */ 736 #define FCDI_EVENT_LEVEL_WARN 0x1 737 /* enum: Error. */ 738 #define FCDI_EVENT_LEVEL_ERR 0x2 739 /* enum: Fatal. */ 740 #define FCDI_EVENT_LEVEL_FATAL 0x3 741 #define FCDI_EVENT_DATA_OFST 0 742 #define FCDI_EVENT_LINK_STATE_STATUS_LBN 0 743 #define FCDI_EVENT_LINK_STATE_STATUS_WIDTH 1 744 #define FCDI_EVENT_LINK_DOWN 0x0 /* enum */ 745 #define FCDI_EVENT_LINK_UP 0x1 /* enum */ 746 #define FCDI_EVENT_DATA_LBN 0 747 #define FCDI_EVENT_DATA_WIDTH 32 748 #define FCDI_EVENT_SRC_LBN 36 749 #define FCDI_EVENT_SRC_WIDTH 8 750 #define FCDI_EVENT_EV_CODE_LBN 60 751 #define FCDI_EVENT_EV_CODE_WIDTH 4 752 #define FCDI_EVENT_CODE_LBN 44 753 #define FCDI_EVENT_CODE_WIDTH 8 754 /* enum: The FC was rebooted. */ 755 #define FCDI_EVENT_CODE_REBOOT 0x1 756 /* enum: Bad assert. */ 757 #define FCDI_EVENT_CODE_ASSERT 0x2 758 /* enum: DDR3 test result. */ 759 #define FCDI_EVENT_CODE_DDR_TEST_RESULT 0x3 760 /* enum: Link status. */ 761 #define FCDI_EVENT_CODE_LINK_STATE 0x4 762 /* enum: A timed read is ready to be serviced. */ 763 #define FCDI_EVENT_CODE_TIMED_READ 0x5 764 /* enum: One or more PPS IN events */ 765 #define FCDI_EVENT_CODE_PPS_IN 0x6 766 /* enum: Tick event from PTP clock */ 767 #define FCDI_EVENT_CODE_PTP_TICK 0x7 768 /* enum: ECC error counters */ 769 #define FCDI_EVENT_CODE_DDR_ECC_STATUS 0x8 770 /* enum: Current status of PTP */ 771 #define FCDI_EVENT_CODE_PTP_STATUS 0x9 772 /* enum: Port id config to map MC-FC port idx */ 773 #define FCDI_EVENT_CODE_PORT_CONFIG 0xa 774 /* enum: Boot result or error code */ 775 #define FCDI_EVENT_CODE_BOOT_RESULT 0xb 776 #define FCDI_EVENT_REBOOT_SRC_LBN 36 777 #define FCDI_EVENT_REBOOT_SRC_WIDTH 8 778 #define FCDI_EVENT_REBOOT_FC_FW 0x0 /* enum */ 779 #define FCDI_EVENT_REBOOT_FC_BOOTLOADER 0x1 /* enum */ 780 #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_OFST 0 781 #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_LBN 0 782 #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_WIDTH 32 783 #define FCDI_EVENT_ASSERT_TYPE_LBN 36 784 #define FCDI_EVENT_ASSERT_TYPE_WIDTH 8 785 #define FCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_LBN 36 786 #define FCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_WIDTH 8 787 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_OFST 0 788 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_LBN 0 789 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_WIDTH 32 790 #define FCDI_EVENT_LINK_STATE_DATA_OFST 0 791 #define FCDI_EVENT_LINK_STATE_DATA_LBN 0 792 #define FCDI_EVENT_LINK_STATE_DATA_WIDTH 32 793 #define FCDI_EVENT_PTP_STATE_OFST 0 794 #define FCDI_EVENT_PTP_UNDEFINED 0x0 /* enum */ 795 #define FCDI_EVENT_PTP_SETUP_FAILED 0x1 /* enum */ 796 #define FCDI_EVENT_PTP_OPERATIONAL 0x2 /* enum */ 797 #define FCDI_EVENT_PTP_STATE_LBN 0 798 #define FCDI_EVENT_PTP_STATE_WIDTH 32 799 #define FCDI_EVENT_DDR_ECC_STATUS_BANK_ID_LBN 36 800 #define FCDI_EVENT_DDR_ECC_STATUS_BANK_ID_WIDTH 8 801 #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_OFST 0 802 #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_LBN 0 803 #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_WIDTH 32 804 /* Index of MC port being referred to */ 805 #define FCDI_EVENT_PORT_CONFIG_SRC_LBN 36 806 #define FCDI_EVENT_PORT_CONFIG_SRC_WIDTH 8 807 /* FC Port index that matches the MC port index in SRC */ 808 #define FCDI_EVENT_PORT_CONFIG_DATA_OFST 0 809 #define FCDI_EVENT_PORT_CONFIG_DATA_LBN 0 810 #define FCDI_EVENT_PORT_CONFIG_DATA_WIDTH 32 811 #define FCDI_EVENT_BOOT_RESULT_OFST 0 812 /* Enum values, see field(s): */ 813 /* MC_CMD_AOE/MC_CMD_AOE_OUT_INFO/FC_BOOT_RESULT */ 814 #define FCDI_EVENT_BOOT_RESULT_LBN 0 815 #define FCDI_EVENT_BOOT_RESULT_WIDTH 32 816 817 /* FCDI_EXTENDED_EVENT_PPS structuredef: Extended FCDI event to send PPS events 818 * to the MC. Note that this structure | is overlayed over a normal FCDI event 819 * such that bits 32-63 containing | event code, level, source etc remain the 820 * same. In this case the data | field of the header is defined to be the 821 * number of timestamps 822 */ 823 #define FCDI_EXTENDED_EVENT_PPS_LENMIN 16 824 #define FCDI_EXTENDED_EVENT_PPS_LENMAX 248 825 #define FCDI_EXTENDED_EVENT_PPS_LEN(num) (8+8*(num)) 826 /* Number of timestamps following */ 827 #define FCDI_EXTENDED_EVENT_PPS_COUNT_OFST 0 828 #define FCDI_EXTENDED_EVENT_PPS_COUNT_LBN 0 829 #define FCDI_EXTENDED_EVENT_PPS_COUNT_WIDTH 32 830 /* Seconds field of a timestamp record */ 831 #define FCDI_EXTENDED_EVENT_PPS_SECONDS_OFST 8 832 #define FCDI_EXTENDED_EVENT_PPS_SECONDS_LBN 64 833 #define FCDI_EXTENDED_EVENT_PPS_SECONDS_WIDTH 32 834 /* Nanoseconds field of a timestamp record */ 835 #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_OFST 12 836 #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_LBN 96 837 #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_WIDTH 32 838 /* Timestamp records comprising the event */ 839 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_OFST 8 840 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LEN 8 841 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LO_OFST 8 842 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_HI_OFST 12 843 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MINNUM 1 844 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MAXNUM 30 845 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LBN 64 846 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_WIDTH 64 847 848 /* MUM_EVENT structuredef */ 849 #define MUM_EVENT_LEN 8 850 #define MUM_EVENT_CONT_LBN 32 851 #define MUM_EVENT_CONT_WIDTH 1 852 #define MUM_EVENT_LEVEL_LBN 33 853 #define MUM_EVENT_LEVEL_WIDTH 3 854 /* enum: Info. */ 855 #define MUM_EVENT_LEVEL_INFO 0x0 856 /* enum: Warning. */ 857 #define MUM_EVENT_LEVEL_WARN 0x1 858 /* enum: Error. */ 859 #define MUM_EVENT_LEVEL_ERR 0x2 860 /* enum: Fatal. */ 861 #define MUM_EVENT_LEVEL_FATAL 0x3 862 #define MUM_EVENT_DATA_OFST 0 863 #define MUM_EVENT_SENSOR_ID_LBN 0 864 #define MUM_EVENT_SENSOR_ID_WIDTH 8 865 /* Enum values, see field(s): */ 866 /* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */ 867 #define MUM_EVENT_SENSOR_STATE_LBN 8 868 #define MUM_EVENT_SENSOR_STATE_WIDTH 8 869 #define MUM_EVENT_PORT_PHY_READY_LBN 0 870 #define MUM_EVENT_PORT_PHY_READY_WIDTH 1 871 #define MUM_EVENT_PORT_PHY_LINK_UP_LBN 1 872 #define MUM_EVENT_PORT_PHY_LINK_UP_WIDTH 1 873 #define MUM_EVENT_PORT_PHY_TX_LOL_LBN 2 874 #define MUM_EVENT_PORT_PHY_TX_LOL_WIDTH 1 875 #define MUM_EVENT_PORT_PHY_RX_LOL_LBN 3 876 #define MUM_EVENT_PORT_PHY_RX_LOL_WIDTH 1 877 #define MUM_EVENT_PORT_PHY_TX_LOS_LBN 4 878 #define MUM_EVENT_PORT_PHY_TX_LOS_WIDTH 1 879 #define MUM_EVENT_PORT_PHY_RX_LOS_LBN 5 880 #define MUM_EVENT_PORT_PHY_RX_LOS_WIDTH 1 881 #define MUM_EVENT_PORT_PHY_TX_FAULT_LBN 6 882 #define MUM_EVENT_PORT_PHY_TX_FAULT_WIDTH 1 883 #define MUM_EVENT_DATA_LBN 0 884 #define MUM_EVENT_DATA_WIDTH 32 885 #define MUM_EVENT_SRC_LBN 36 886 #define MUM_EVENT_SRC_WIDTH 8 887 #define MUM_EVENT_EV_CODE_LBN 60 888 #define MUM_EVENT_EV_CODE_WIDTH 4 889 #define MUM_EVENT_CODE_LBN 44 890 #define MUM_EVENT_CODE_WIDTH 8 891 /* enum: The MUM was rebooted. */ 892 #define MUM_EVENT_CODE_REBOOT 0x1 893 /* enum: Bad assert. */ 894 #define MUM_EVENT_CODE_ASSERT 0x2 895 /* enum: Sensor failure. */ 896 #define MUM_EVENT_CODE_SENSOR 0x3 897 /* enum: Link fault has been asserted, or has cleared. */ 898 #define MUM_EVENT_CODE_QSFP_LASI_INTERRUPT 0x4 899 #define MUM_EVENT_SENSOR_DATA_OFST 0 900 #define MUM_EVENT_SENSOR_DATA_LBN 0 901 #define MUM_EVENT_SENSOR_DATA_WIDTH 32 902 #define MUM_EVENT_PORT_PHY_FLAGS_OFST 0 903 #define MUM_EVENT_PORT_PHY_FLAGS_LBN 0 904 #define MUM_EVENT_PORT_PHY_FLAGS_WIDTH 32 905 #define MUM_EVENT_PORT_PHY_COPPER_LEN_OFST 0 906 #define MUM_EVENT_PORT_PHY_COPPER_LEN_LBN 0 907 #define MUM_EVENT_PORT_PHY_COPPER_LEN_WIDTH 32 908 #define MUM_EVENT_PORT_PHY_CAPS_OFST 0 909 #define MUM_EVENT_PORT_PHY_CAPS_LBN 0 910 #define MUM_EVENT_PORT_PHY_CAPS_WIDTH 32 911 #define MUM_EVENT_PORT_PHY_TECH_OFST 0 912 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_UNKNOWN 0x0 /* enum */ 913 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_OPTICAL 0x1 /* enum */ 914 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_PASSIVE 0x2 /* enum */ 915 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_PASSIVE_EQUALIZED 0x3 /* enum */ 916 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_ACTIVE_LIMITING 0x4 /* enum */ 917 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_ACTIVE_LINEAR 0x5 /* enum */ 918 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_BASE_T 0x6 /* enum */ 919 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_LOOPBACK_PASSIVE 0x7 /* enum */ 920 #define MUM_EVENT_PORT_PHY_TECH_LBN 0 921 #define MUM_EVENT_PORT_PHY_TECH_WIDTH 32 922 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_LBN 36 923 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_WIDTH 4 924 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_FLAGS 0x0 /* enum */ 925 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_COPPER_LEN 0x1 /* enum */ 926 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_CAPS 0x2 /* enum */ 927 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_TECH 0x3 /* enum */ 928 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_MAX 0x4 /* enum */ 929 #define MUM_EVENT_PORT_PHY_SRC_PORT_NO_LBN 40 930 #define MUM_EVENT_PORT_PHY_SRC_PORT_NO_WIDTH 4 931 932 933 /***********************************/ 934 /* MC_CMD_READ32 935 * Read multiple 32byte words from MC memory. 936 */ 937 #define MC_CMD_READ32 0x1 938 #undef MC_CMD_0x1_PRIVILEGE_CTG 939 940 #define MC_CMD_0x1_PRIVILEGE_CTG SRIOV_CTG_ADMIN 941 942 /* MC_CMD_READ32_IN msgrequest */ 943 #define MC_CMD_READ32_IN_LEN 8 944 #define MC_CMD_READ32_IN_ADDR_OFST 0 945 #define MC_CMD_READ32_IN_NUMWORDS_OFST 4 946 947 /* MC_CMD_READ32_OUT msgresponse */ 948 #define MC_CMD_READ32_OUT_LENMIN 4 949 #define MC_CMD_READ32_OUT_LENMAX 252 950 #define MC_CMD_READ32_OUT_LEN(num) (0+4*(num)) 951 #define MC_CMD_READ32_OUT_BUFFER_OFST 0 952 #define MC_CMD_READ32_OUT_BUFFER_LEN 4 953 #define MC_CMD_READ32_OUT_BUFFER_MINNUM 1 954 #define MC_CMD_READ32_OUT_BUFFER_MAXNUM 63 955 956 957 /***********************************/ 958 /* MC_CMD_WRITE32 959 * Write multiple 32byte words to MC memory. 960 */ 961 #define MC_CMD_WRITE32 0x2 962 #undef MC_CMD_0x2_PRIVILEGE_CTG 963 964 #define MC_CMD_0x2_PRIVILEGE_CTG SRIOV_CTG_ADMIN 965 966 /* MC_CMD_WRITE32_IN msgrequest */ 967 #define MC_CMD_WRITE32_IN_LENMIN 8 968 #define MC_CMD_WRITE32_IN_LENMAX 252 969 #define MC_CMD_WRITE32_IN_LEN(num) (4+4*(num)) 970 #define MC_CMD_WRITE32_IN_ADDR_OFST 0 971 #define MC_CMD_WRITE32_IN_BUFFER_OFST 4 972 #define MC_CMD_WRITE32_IN_BUFFER_LEN 4 973 #define MC_CMD_WRITE32_IN_BUFFER_MINNUM 1 974 #define MC_CMD_WRITE32_IN_BUFFER_MAXNUM 62 975 976 /* MC_CMD_WRITE32_OUT msgresponse */ 977 #define MC_CMD_WRITE32_OUT_LEN 0 978 979 980 /***********************************/ 981 /* MC_CMD_COPYCODE 982 * Copy MC code between two locations and jump. 983 */ 984 #define MC_CMD_COPYCODE 0x3 985 #undef MC_CMD_0x3_PRIVILEGE_CTG 986 987 #define MC_CMD_0x3_PRIVILEGE_CTG SRIOV_CTG_ADMIN 988 989 /* MC_CMD_COPYCODE_IN msgrequest */ 990 #define MC_CMD_COPYCODE_IN_LEN 16 991 /* Source address 992 * 993 * The main image should be entered via a copy of a single word from and to a 994 * magic address, which controls various aspects of the boot. The magic address 995 * is a bitfield, with each bit as documented below. 996 */ 997 #define MC_CMD_COPYCODE_IN_SRC_ADDR_OFST 0 998 /* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT (see below) */ 999 #define MC_CMD_COPYCODE_HUNT_NO_MAGIC_ADDR 0x10000 1000 /* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT and 1001 * BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED (see below) 1002 */ 1003 #define MC_CMD_COPYCODE_HUNT_NO_DATAPATH_MAGIC_ADDR 0x1d0d0 1004 /* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT, 1005 * BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED and BOOT_MAGIC_IGNORE_CONFIG (see 1006 * below) 1007 */ 1008 #define MC_CMD_COPYCODE_HUNT_IGNORE_CONFIG_MAGIC_ADDR 0x1badc 1009 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_LBN 17 1010 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_WIDTH 1 1011 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_LBN 2 1012 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_WIDTH 1 1013 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_LBN 3 1014 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_WIDTH 1 1015 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_LBN 4 1016 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_WIDTH 1 1017 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_LBN 5 1018 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_WIDTH 1 1019 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_DISABLE_XIP_LBN 6 1020 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_DISABLE_XIP_WIDTH 1 1021 /* Destination address */ 1022 #define MC_CMD_COPYCODE_IN_DEST_ADDR_OFST 4 1023 #define MC_CMD_COPYCODE_IN_NUMWORDS_OFST 8 1024 /* Address of where to jump after copy. */ 1025 #define MC_CMD_COPYCODE_IN_JUMP_OFST 12 1026 /* enum: Control should return to the caller rather than jumping */ 1027 #define MC_CMD_COPYCODE_JUMP_NONE 0x1 1028 1029 /* MC_CMD_COPYCODE_OUT msgresponse */ 1030 #define MC_CMD_COPYCODE_OUT_LEN 0 1031 1032 1033 /***********************************/ 1034 /* MC_CMD_SET_FUNC 1035 * Select function for function-specific commands. 1036 */ 1037 #define MC_CMD_SET_FUNC 0x4 1038 #undef MC_CMD_0x4_PRIVILEGE_CTG 1039 1040 #define MC_CMD_0x4_PRIVILEGE_CTG SRIOV_CTG_ADMIN 1041 1042 /* MC_CMD_SET_FUNC_IN msgrequest */ 1043 #define MC_CMD_SET_FUNC_IN_LEN 4 1044 /* Set function */ 1045 #define MC_CMD_SET_FUNC_IN_FUNC_OFST 0 1046 1047 /* MC_CMD_SET_FUNC_OUT msgresponse */ 1048 #define MC_CMD_SET_FUNC_OUT_LEN 0 1049 1050 1051 /***********************************/ 1052 /* MC_CMD_GET_BOOT_STATUS 1053 * Get the instruction address from which the MC booted. 1054 */ 1055 #define MC_CMD_GET_BOOT_STATUS 0x5 1056 #undef MC_CMD_0x5_PRIVILEGE_CTG 1057 1058 #define MC_CMD_0x5_PRIVILEGE_CTG SRIOV_CTG_ADMIN 1059 1060 /* MC_CMD_GET_BOOT_STATUS_IN msgrequest */ 1061 #define MC_CMD_GET_BOOT_STATUS_IN_LEN 0 1062 1063 /* MC_CMD_GET_BOOT_STATUS_OUT msgresponse */ 1064 #define MC_CMD_GET_BOOT_STATUS_OUT_LEN 8 1065 /* ?? */ 1066 #define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_OFST 0 1067 /* enum: indicates that the MC wasn't flash booted */ 1068 #define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_NULL 0xdeadbeef 1069 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_OFST 4 1070 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_LBN 0 1071 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_WIDTH 1 1072 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_LBN 1 1073 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_WIDTH 1 1074 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_LBN 2 1075 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_WIDTH 1 1076 1077 1078 /***********************************/ 1079 /* MC_CMD_GET_ASSERTS 1080 * Get (and optionally clear) the current assertion status. Only 1081 * OUT.GLOBAL_FLAGS is guaranteed to exist in the completion payload. The other 1082 * fields will only be present if OUT.GLOBAL_FLAGS != NO_FAILS 1083 */ 1084 #define MC_CMD_GET_ASSERTS 0x6 1085 #undef MC_CMD_0x6_PRIVILEGE_CTG 1086 1087 #define MC_CMD_0x6_PRIVILEGE_CTG SRIOV_CTG_ADMIN 1088 1089 /* MC_CMD_GET_ASSERTS_IN msgrequest */ 1090 #define MC_CMD_GET_ASSERTS_IN_LEN 4 1091 /* Set to clear assertion */ 1092 #define MC_CMD_GET_ASSERTS_IN_CLEAR_OFST 0 1093 1094 /* MC_CMD_GET_ASSERTS_OUT msgresponse */ 1095 #define MC_CMD_GET_ASSERTS_OUT_LEN 140 1096 /* Assertion status flag. */ 1097 #define MC_CMD_GET_ASSERTS_OUT_GLOBAL_FLAGS_OFST 0 1098 /* enum: No assertions have failed. */ 1099 #define MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1 1100 /* enum: A system-level assertion has failed. */ 1101 #define MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2 1102 /* enum: A thread-level assertion has failed. */ 1103 #define MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3 1104 /* enum: The system was reset by the watchdog. */ 1105 #define MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4 1106 /* enum: An illegal address trap stopped the system (huntington and later) */ 1107 #define MC_CMD_GET_ASSERTS_FLAGS_ADDR_TRAP 0x5 1108 /* Failing PC value */ 1109 #define MC_CMD_GET_ASSERTS_OUT_SAVED_PC_OFFS_OFST 4 1110 /* Saved GP regs */ 1111 #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_OFST 8 1112 #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_LEN 4 1113 #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_NUM 31 1114 /* enum: A magic value hinting that the value in this register at the time of 1115 * the failure has likely been lost. 1116 */ 1117 #define MC_CMD_GET_ASSERTS_REG_NO_DATA 0xda7a1057 1118 /* Failing thread address */ 1119 #define MC_CMD_GET_ASSERTS_OUT_THREAD_OFFS_OFST 132 1120 #define MC_CMD_GET_ASSERTS_OUT_RESERVED_OFST 136 1121 1122 1123 /***********************************/ 1124 /* MC_CMD_LOG_CTRL 1125 * Configure the output stream for log events such as link state changes, 1126 * sensor notifications and MCDI completions 1127 */ 1128 #define MC_CMD_LOG_CTRL 0x7 1129 #undef MC_CMD_0x7_PRIVILEGE_CTG 1130 1131 #define MC_CMD_0x7_PRIVILEGE_CTG SRIOV_CTG_GENERAL 1132 1133 /* MC_CMD_LOG_CTRL_IN msgrequest */ 1134 #define MC_CMD_LOG_CTRL_IN_LEN 8 1135 /* Log destination */ 1136 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_OFST 0 1137 /* enum: UART. */ 1138 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_UART 0x1 1139 /* enum: Event queue. */ 1140 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ 0x2 1141 /* Legacy argument. Must be zero. */ 1142 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ_OFST 4 1143 1144 /* MC_CMD_LOG_CTRL_OUT msgresponse */ 1145 #define MC_CMD_LOG_CTRL_OUT_LEN 0 1146 1147 1148 /***********************************/ 1149 /* MC_CMD_GET_VERSION 1150 * Get version information about the MC firmware. 1151 */ 1152 #define MC_CMD_GET_VERSION 0x8 1153 #undef MC_CMD_0x8_PRIVILEGE_CTG 1154 1155 #define MC_CMD_0x8_PRIVILEGE_CTG SRIOV_CTG_GENERAL 1156 1157 /* MC_CMD_GET_VERSION_IN msgrequest */ 1158 #define MC_CMD_GET_VERSION_IN_LEN 0 1159 1160 /* MC_CMD_GET_VERSION_EXT_IN msgrequest: Asks for the extended version */ 1161 #define MC_CMD_GET_VERSION_EXT_IN_LEN 4 1162 /* placeholder, set to 0 */ 1163 #define MC_CMD_GET_VERSION_EXT_IN_EXT_FLAGS_OFST 0 1164 1165 /* MC_CMD_GET_VERSION_V0_OUT msgresponse: deprecated version format */ 1166 #define MC_CMD_GET_VERSION_V0_OUT_LEN 4 1167 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 1168 /* enum: Reserved version number to indicate "any" version. */ 1169 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_ANY 0xffffffff 1170 /* enum: Bootrom version value for Siena. */ 1171 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_SIENA_BOOTROM 0xb0070000 1172 /* enum: Bootrom version value for Huntington. */ 1173 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_HUNT_BOOTROM 0xb0070001 1174 1175 /* MC_CMD_GET_VERSION_OUT msgresponse */ 1176 #define MC_CMD_GET_VERSION_OUT_LEN 32 1177 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */ 1178 /* Enum values, see field(s): */ 1179 /* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */ 1180 #define MC_CMD_GET_VERSION_OUT_PCOL_OFST 4 1181 /* 128bit mask of functions supported by the current firmware */ 1182 #define MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_OFST 8 1183 #define MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_LEN 16 1184 #define MC_CMD_GET_VERSION_OUT_VERSION_OFST 24 1185 #define MC_CMD_GET_VERSION_OUT_VERSION_LEN 8 1186 #define MC_CMD_GET_VERSION_OUT_VERSION_LO_OFST 24 1187 #define MC_CMD_GET_VERSION_OUT_VERSION_HI_OFST 28 1188 1189 /* MC_CMD_GET_VERSION_EXT_OUT msgresponse */ 1190 #define MC_CMD_GET_VERSION_EXT_OUT_LEN 48 1191 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */ 1192 /* Enum values, see field(s): */ 1193 /* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */ 1194 #define MC_CMD_GET_VERSION_EXT_OUT_PCOL_OFST 4 1195 /* 128bit mask of functions supported by the current firmware */ 1196 #define MC_CMD_GET_VERSION_EXT_OUT_SUPPORTED_FUNCS_OFST 8 1197 #define MC_CMD_GET_VERSION_EXT_OUT_SUPPORTED_FUNCS_LEN 16 1198 #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_OFST 24 1199 #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LEN 8 1200 #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LO_OFST 24 1201 #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_HI_OFST 28 1202 /* extra info */ 1203 #define MC_CMD_GET_VERSION_EXT_OUT_EXTRA_OFST 32 1204 #define MC_CMD_GET_VERSION_EXT_OUT_EXTRA_LEN 16 1205 1206 1207 /***********************************/ 1208 /* MC_CMD_FC 1209 * Perform an FC operation 1210 */ 1211 #define MC_CMD_FC 0x9 1212 1213 /* MC_CMD_FC_IN msgrequest */ 1214 #define MC_CMD_FC_IN_LEN 4 1215 #define MC_CMD_FC_IN_OP_HDR_OFST 0 1216 #define MC_CMD_FC_IN_OP_LBN 0 1217 #define MC_CMD_FC_IN_OP_WIDTH 8 1218 /* enum: NULL MCDI command to FC. */ 1219 #define MC_CMD_FC_OP_NULL 0x1 1220 /* enum: Unused opcode */ 1221 #define MC_CMD_FC_OP_UNUSED 0x2 1222 /* enum: MAC driver commands */ 1223 #define MC_CMD_FC_OP_MAC 0x3 1224 /* enum: Read FC memory */ 1225 #define MC_CMD_FC_OP_READ32 0x4 1226 /* enum: Write to FC memory */ 1227 #define MC_CMD_FC_OP_WRITE32 0x5 1228 /* enum: Read FC memory */ 1229 #define MC_CMD_FC_OP_TRC_READ 0x6 1230 /* enum: Write to FC memory */ 1231 #define MC_CMD_FC_OP_TRC_WRITE 0x7 1232 /* enum: FC firmware Version */ 1233 #define MC_CMD_FC_OP_GET_VERSION 0x8 1234 /* enum: Read FC memory */ 1235 #define MC_CMD_FC_OP_TRC_RX_READ 0x9 1236 /* enum: Write to FC memory */ 1237 #define MC_CMD_FC_OP_TRC_RX_WRITE 0xa 1238 /* enum: SFP parameters */ 1239 #define MC_CMD_FC_OP_SFP 0xb 1240 /* enum: DDR3 test */ 1241 #define MC_CMD_FC_OP_DDR_TEST 0xc 1242 /* enum: Get Crash context from FC */ 1243 #define MC_CMD_FC_OP_GET_ASSERT 0xd 1244 /* enum: Get FPGA Build registers */ 1245 #define MC_CMD_FC_OP_FPGA_BUILD 0xe 1246 /* enum: Read map support commands */ 1247 #define MC_CMD_FC_OP_READ_MAP 0xf 1248 /* enum: FC Capabilities */ 1249 #define MC_CMD_FC_OP_CAPABILITIES 0x10 1250 /* enum: FC Global flags */ 1251 #define MC_CMD_FC_OP_GLOBAL_FLAGS 0x11 1252 /* enum: FC IO using relative addressing modes */ 1253 #define MC_CMD_FC_OP_IO_REL 0x12 1254 /* enum: FPGA link information */ 1255 #define MC_CMD_FC_OP_UHLINK 0x13 1256 /* enum: Configure loopbacks and link on FPGA ports */ 1257 #define MC_CMD_FC_OP_SET_LINK 0x14 1258 /* enum: Licensing operations relating to AOE */ 1259 #define MC_CMD_FC_OP_LICENSE 0x15 1260 /* enum: Startup information to the FC */ 1261 #define MC_CMD_FC_OP_STARTUP 0x16 1262 /* enum: Configure a DMA read */ 1263 #define MC_CMD_FC_OP_DMA 0x17 1264 /* enum: Configure a timed read */ 1265 #define MC_CMD_FC_OP_TIMED_READ 0x18 1266 /* enum: Control UART logging */ 1267 #define MC_CMD_FC_OP_LOG 0x19 1268 /* enum: Get the value of a given clock_id */ 1269 #define MC_CMD_FC_OP_CLOCK 0x1a 1270 /* enum: DDR3/QDR3 parameters */ 1271 #define MC_CMD_FC_OP_DDR 0x1b 1272 /* enum: PTP and timestamp control */ 1273 #define MC_CMD_FC_OP_TIMESTAMP 0x1c 1274 /* enum: Commands for SPI Flash interface */ 1275 #define MC_CMD_FC_OP_SPI 0x1d 1276 /* enum: Commands for diagnostic components */ 1277 #define MC_CMD_FC_OP_DIAG 0x1e 1278 /* enum: External AOE port. */ 1279 #define MC_CMD_FC_IN_PORT_EXT_OFST 0x0 1280 /* enum: Internal AOE port. */ 1281 #define MC_CMD_FC_IN_PORT_INT_OFST 0x40 1282 1283 /* MC_CMD_FC_IN_NULL msgrequest */ 1284 #define MC_CMD_FC_IN_NULL_LEN 4 1285 #define MC_CMD_FC_IN_CMD_OFST 0 1286 1287 /* MC_CMD_FC_IN_PHY msgrequest */ 1288 #define MC_CMD_FC_IN_PHY_LEN 5 1289 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1290 /* FC PHY driver operation code */ 1291 #define MC_CMD_FC_IN_PHY_OP_OFST 4 1292 #define MC_CMD_FC_IN_PHY_OP_LEN 1 1293 /* enum: PHY init handler */ 1294 #define MC_CMD_FC_OP_PHY_OP_INIT 0x1 1295 /* enum: PHY reconfigure handler */ 1296 #define MC_CMD_FC_OP_PHY_OP_RECONFIGURE 0x2 1297 /* enum: PHY reboot handler */ 1298 #define MC_CMD_FC_OP_PHY_OP_REBOOT 0x3 1299 /* enum: PHY get_supported_cap handler */ 1300 #define MC_CMD_FC_OP_PHY_OP_GET_SUPPORTED_CAP 0x4 1301 /* enum: PHY get_config handler */ 1302 #define MC_CMD_FC_OP_PHY_OP_GET_CONFIG 0x5 1303 /* enum: PHY get_media_info handler */ 1304 #define MC_CMD_FC_OP_PHY_OP_GET_MEDIA_INFO 0x6 1305 /* enum: PHY set_led handler */ 1306 #define MC_CMD_FC_OP_PHY_OP_SET_LED 0x7 1307 /* enum: PHY lasi_interrupt handler */ 1308 #define MC_CMD_FC_OP_PHY_OP_LASI_INTERRUPT 0x8 1309 /* enum: PHY check_link handler */ 1310 #define MC_CMD_FC_OP_PHY_OP_CHECK_LINK 0x9 1311 /* enum: PHY fill_stats handler */ 1312 #define MC_CMD_FC_OP_PHY_OP_FILL_STATS 0xa 1313 /* enum: PHY bpx_link_state_changed handler */ 1314 #define MC_CMD_FC_OP_PHY_OP_BPX_LINK_STATE_CHANGED 0xb 1315 /* enum: PHY get_state handler */ 1316 #define MC_CMD_FC_OP_PHY_OP_GET_STATE 0xc 1317 /* enum: PHY start_bist handler */ 1318 #define MC_CMD_FC_OP_PHY_OP_START_BIST 0xd 1319 /* enum: PHY poll_bist handler */ 1320 #define MC_CMD_FC_OP_PHY_OP_POLL_BIST 0xe 1321 /* enum: PHY nvram_test handler */ 1322 #define MC_CMD_FC_OP_PHY_OP_NVRAM_TEST 0xf 1323 /* enum: PHY relinquish handler */ 1324 #define MC_CMD_FC_OP_PHY_OP_RELINQUISH_SPI 0x10 1325 /* enum: PHY read connection from FC - may be not required */ 1326 #define MC_CMD_FC_OP_PHY_OP_GET_CONNECTION 0x11 1327 /* enum: PHY read flags from FC - may be not required */ 1328 #define MC_CMD_FC_OP_PHY_OP_GET_FLAGS 0x12 1329 1330 /* MC_CMD_FC_IN_PHY_INIT msgrequest */ 1331 #define MC_CMD_FC_IN_PHY_INIT_LEN 4 1332 #define MC_CMD_FC_IN_PHY_CMD_OFST 0 1333 1334 /* MC_CMD_FC_IN_MAC msgrequest */ 1335 #define MC_CMD_FC_IN_MAC_LEN 8 1336 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1337 #define MC_CMD_FC_IN_MAC_HEADER_OFST 4 1338 #define MC_CMD_FC_IN_MAC_OP_LBN 0 1339 #define MC_CMD_FC_IN_MAC_OP_WIDTH 8 1340 /* enum: MAC reconfigure handler */ 1341 #define MC_CMD_FC_OP_MAC_OP_RECONFIGURE 0x1 1342 /* enum: MAC Set command - same as MC_CMD_SET_MAC */ 1343 #define MC_CMD_FC_OP_MAC_OP_SET_LINK 0x2 1344 /* enum: MAC statistics */ 1345 #define MC_CMD_FC_OP_MAC_OP_GET_STATS 0x3 1346 /* enum: MAC RX statistics */ 1347 #define MC_CMD_FC_OP_MAC_OP_GET_RX_STATS 0x6 1348 /* enum: MAC TX statistics */ 1349 #define MC_CMD_FC_OP_MAC_OP_GET_TX_STATS 0x7 1350 /* enum: MAC Read status */ 1351 #define MC_CMD_FC_OP_MAC_OP_READ_STATUS 0x8 1352 #define MC_CMD_FC_IN_MAC_PORT_TYPE_LBN 8 1353 #define MC_CMD_FC_IN_MAC_PORT_TYPE_WIDTH 8 1354 /* enum: External FPGA port. */ 1355 #define MC_CMD_FC_PORT_EXT 0x0 1356 /* enum: Internal Siena-facing FPGA ports. */ 1357 #define MC_CMD_FC_PORT_INT 0x1 1358 #define MC_CMD_FC_IN_MAC_PORT_IDX_LBN 16 1359 #define MC_CMD_FC_IN_MAC_PORT_IDX_WIDTH 8 1360 #define MC_CMD_FC_IN_MAC_CMD_FORMAT_LBN 24 1361 #define MC_CMD_FC_IN_MAC_CMD_FORMAT_WIDTH 8 1362 /* enum: Default FC command format; the fields PORT_TYPE and PORT_IDX are 1363 * irrelevant. Port number is derived from pci_fn; passed in FC header. 1364 */ 1365 #define MC_CMD_FC_OP_MAC_CMD_FORMAT_DEFAULT 0x0 1366 /* enum: Override default port number. Port number determined by fields 1367 * PORT_TYPE and PORT_IDX. 1368 */ 1369 #define MC_CMD_FC_OP_MAC_CMD_FORMAT_PORT_OVERRIDE 0x1 1370 1371 /* MC_CMD_FC_IN_MAC_RECONFIGURE msgrequest */ 1372 #define MC_CMD_FC_IN_MAC_RECONFIGURE_LEN 8 1373 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1374 /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ 1375 1376 /* MC_CMD_FC_IN_MAC_SET_LINK msgrequest */ 1377 #define MC_CMD_FC_IN_MAC_SET_LINK_LEN 32 1378 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1379 /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ 1380 /* MTU size */ 1381 #define MC_CMD_FC_IN_MAC_SET_LINK_MTU_OFST 8 1382 /* Drain Tx FIFO */ 1383 #define MC_CMD_FC_IN_MAC_SET_LINK_DRAIN_OFST 12 1384 #define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_OFST 16 1385 #define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_LEN 8 1386 #define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_LO_OFST 16 1387 #define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_HI_OFST 20 1388 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_OFST 24 1389 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_UNICAST_LBN 0 1390 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_UNICAST_WIDTH 1 1391 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_BRDCAST_LBN 1 1392 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_BRDCAST_WIDTH 1 1393 #define MC_CMD_FC_IN_MAC_SET_LINK_FCNTL_OFST 28 1394 1395 /* MC_CMD_FC_IN_MAC_READ_STATUS msgrequest */ 1396 #define MC_CMD_FC_IN_MAC_READ_STATUS_LEN 8 1397 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1398 /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ 1399 1400 /* MC_CMD_FC_IN_MAC_GET_RX_STATS msgrequest */ 1401 #define MC_CMD_FC_IN_MAC_GET_RX_STATS_LEN 8 1402 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1403 /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ 1404 1405 /* MC_CMD_FC_IN_MAC_GET_TX_STATS msgrequest */ 1406 #define MC_CMD_FC_IN_MAC_GET_TX_STATS_LEN 8 1407 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1408 /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ 1409 1410 /* MC_CMD_FC_IN_MAC_GET_STATS msgrequest */ 1411 #define MC_CMD_FC_IN_MAC_GET_STATS_LEN 20 1412 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1413 /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ 1414 /* MC Statistics index */ 1415 #define MC_CMD_FC_IN_MAC_GET_STATS_STATS_INDEX_OFST 8 1416 #define MC_CMD_FC_IN_MAC_GET_STATS_FLAGS_OFST 12 1417 #define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_ALL_LBN 0 1418 #define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_ALL_WIDTH 1 1419 #define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_LBN 1 1420 #define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_WIDTH 1 1421 #define MC_CMD_FC_IN_MAC_GET_STATS_UPDATE_LBN 2 1422 #define MC_CMD_FC_IN_MAC_GET_STATS_UPDATE_WIDTH 1 1423 /* Number of statistics to read */ 1424 #define MC_CMD_FC_IN_MAC_GET_STATS_NUM_OFST 16 1425 #define MC_CMD_FC_MAC_NSTATS_PER_BLOCK 0x1e /* enum */ 1426 #define MC_CMD_FC_MAC_NBYTES_PER_STAT 0x8 /* enum */ 1427 1428 /* MC_CMD_FC_IN_READ32 msgrequest */ 1429 #define MC_CMD_FC_IN_READ32_LEN 16 1430 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1431 #define MC_CMD_FC_IN_READ32_ADDR_HI_OFST 4 1432 #define MC_CMD_FC_IN_READ32_ADDR_LO_OFST 8 1433 #define MC_CMD_FC_IN_READ32_NUMWORDS_OFST 12 1434 1435 /* MC_CMD_FC_IN_WRITE32 msgrequest */ 1436 #define MC_CMD_FC_IN_WRITE32_LENMIN 16 1437 #define MC_CMD_FC_IN_WRITE32_LENMAX 252 1438 #define MC_CMD_FC_IN_WRITE32_LEN(num) (12+4*(num)) 1439 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1440 #define MC_CMD_FC_IN_WRITE32_ADDR_HI_OFST 4 1441 #define MC_CMD_FC_IN_WRITE32_ADDR_LO_OFST 8 1442 #define MC_CMD_FC_IN_WRITE32_BUFFER_OFST 12 1443 #define MC_CMD_FC_IN_WRITE32_BUFFER_LEN 4 1444 #define MC_CMD_FC_IN_WRITE32_BUFFER_MINNUM 1 1445 #define MC_CMD_FC_IN_WRITE32_BUFFER_MAXNUM 60 1446 1447 /* MC_CMD_FC_IN_TRC_READ msgrequest */ 1448 #define MC_CMD_FC_IN_TRC_READ_LEN 12 1449 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1450 #define MC_CMD_FC_IN_TRC_READ_TRC_OFST 4 1451 #define MC_CMD_FC_IN_TRC_READ_CHANNEL_OFST 8 1452 1453 /* MC_CMD_FC_IN_TRC_WRITE msgrequest */ 1454 #define MC_CMD_FC_IN_TRC_WRITE_LEN 28 1455 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1456 #define MC_CMD_FC_IN_TRC_WRITE_TRC_OFST 4 1457 #define MC_CMD_FC_IN_TRC_WRITE_CHANNEL_OFST 8 1458 #define MC_CMD_FC_IN_TRC_WRITE_DATA_OFST 12 1459 #define MC_CMD_FC_IN_TRC_WRITE_DATA_LEN 4 1460 #define MC_CMD_FC_IN_TRC_WRITE_DATA_NUM 4 1461 1462 /* MC_CMD_FC_IN_GET_VERSION msgrequest */ 1463 #define MC_CMD_FC_IN_GET_VERSION_LEN 4 1464 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1465 1466 /* MC_CMD_FC_IN_TRC_RX_READ msgrequest */ 1467 #define MC_CMD_FC_IN_TRC_RX_READ_LEN 12 1468 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1469 #define MC_CMD_FC_IN_TRC_RX_READ_TRC_OFST 4 1470 #define MC_CMD_FC_IN_TRC_RX_READ_CHANNEL_OFST 8 1471 1472 /* MC_CMD_FC_IN_TRC_RX_WRITE msgrequest */ 1473 #define MC_CMD_FC_IN_TRC_RX_WRITE_LEN 20 1474 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1475 #define MC_CMD_FC_IN_TRC_RX_WRITE_TRC_OFST 4 1476 #define MC_CMD_FC_IN_TRC_RX_WRITE_CHANNEL_OFST 8 1477 #define MC_CMD_FC_IN_TRC_RX_WRITE_DATA_OFST 12 1478 #define MC_CMD_FC_IN_TRC_RX_WRITE_DATA_LEN 4 1479 #define MC_CMD_FC_IN_TRC_RX_WRITE_DATA_NUM 2 1480 1481 /* MC_CMD_FC_IN_SFP msgrequest */ 1482 #define MC_CMD_FC_IN_SFP_LEN 28 1483 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1484 /* Link speed is 100, 1000, 10000, 40000 */ 1485 #define MC_CMD_FC_IN_SFP_SPEED_OFST 4 1486 /* Length of copper cable - zero when not relevant (e.g. if cable is fibre) */ 1487 #define MC_CMD_FC_IN_SFP_COPPER_LEN_OFST 8 1488 /* Not relevant for cards with QSFP modules. For older cards, true if module is 1489 * a dual speed SFP+ module. 1490 */ 1491 #define MC_CMD_FC_IN_SFP_DUAL_SPEED_OFST 12 1492 /* True if an SFP Module is present (other fields valid when true) */ 1493 #define MC_CMD_FC_IN_SFP_PRESENT_OFST 16 1494 /* The type of the SFP+ Module. For later cards with QSFP modules, this field 1495 * is unused and the type is communicated by other means. 1496 */ 1497 #define MC_CMD_FC_IN_SFP_TYPE_OFST 20 1498 /* Capabilities corresponding to 1 bits. */ 1499 #define MC_CMD_FC_IN_SFP_CAPS_OFST 24 1500 1501 /* MC_CMD_FC_IN_DDR_TEST msgrequest */ 1502 #define MC_CMD_FC_IN_DDR_TEST_LEN 8 1503 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1504 #define MC_CMD_FC_IN_DDR_TEST_HEADER_OFST 4 1505 #define MC_CMD_FC_IN_DDR_TEST_OP_LBN 0 1506 #define MC_CMD_FC_IN_DDR_TEST_OP_WIDTH 8 1507 /* enum: DRAM Test Start */ 1508 #define MC_CMD_FC_OP_DDR_TEST_START 0x1 1509 /* enum: DRAM Test Poll */ 1510 #define MC_CMD_FC_OP_DDR_TEST_POLL 0x2 1511 1512 /* MC_CMD_FC_IN_DDR_TEST_START msgrequest */ 1513 #define MC_CMD_FC_IN_DDR_TEST_START_LEN 12 1514 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1515 /* MC_CMD_FC_IN_DDR_TEST_HEADER_OFST 4 */ 1516 #define MC_CMD_FC_IN_DDR_TEST_START_MASK_OFST 8 1517 #define MC_CMD_FC_IN_DDR_TEST_START_T0_LBN 0 1518 #define MC_CMD_FC_IN_DDR_TEST_START_T0_WIDTH 1 1519 #define MC_CMD_FC_IN_DDR_TEST_START_T1_LBN 1 1520 #define MC_CMD_FC_IN_DDR_TEST_START_T1_WIDTH 1 1521 #define MC_CMD_FC_IN_DDR_TEST_START_B0_LBN 2 1522 #define MC_CMD_FC_IN_DDR_TEST_START_B0_WIDTH 1 1523 #define MC_CMD_FC_IN_DDR_TEST_START_B1_LBN 3 1524 #define MC_CMD_FC_IN_DDR_TEST_START_B1_WIDTH 1 1525 1526 /* MC_CMD_FC_IN_DDR_TEST_POLL msgrequest */ 1527 #define MC_CMD_FC_IN_DDR_TEST_POLL_LEN 12 1528 #define MC_CMD_FC_IN_DDR_TEST_CMD_OFST 0 1529 /* MC_CMD_FC_IN_DDR_TEST_HEADER_OFST 4 */ 1530 /* Clear previous test result and prepare for restarting DDR test */ 1531 #define MC_CMD_FC_IN_DDR_TEST_POLL_CLEAR_RESULT_FOR_DDR_TEST_OFST 8 1532 1533 /* MC_CMD_FC_IN_GET_ASSERT msgrequest */ 1534 #define MC_CMD_FC_IN_GET_ASSERT_LEN 4 1535 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1536 1537 /* MC_CMD_FC_IN_FPGA_BUILD msgrequest */ 1538 #define MC_CMD_FC_IN_FPGA_BUILD_LEN 8 1539 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1540 /* FPGA build info operation code */ 1541 #define MC_CMD_FC_IN_FPGA_BUILD_OP_OFST 4 1542 /* enum: Get the build registers */ 1543 #define MC_CMD_FC_IN_FPGA_BUILD_BUILD 0x1 1544 /* enum: Get the services registers */ 1545 #define MC_CMD_FC_IN_FPGA_BUILD_SERVICES 0x2 1546 /* enum: Get the BSP version */ 1547 #define MC_CMD_FC_IN_FPGA_BUILD_BSP_VERSION 0x3 1548 /* enum: Get build register for V2 (SFA974X) */ 1549 #define MC_CMD_FC_IN_FPGA_BUILD_BUILD_V2 0x4 1550 /* enum: GEt the services register for V2 (SFA974X) */ 1551 #define MC_CMD_FC_IN_FPGA_BUILD_SERVICES_V2 0x5 1552 1553 /* MC_CMD_FC_IN_READ_MAP msgrequest */ 1554 #define MC_CMD_FC_IN_READ_MAP_LEN 8 1555 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1556 #define MC_CMD_FC_IN_READ_MAP_HEADER_OFST 4 1557 #define MC_CMD_FC_IN_READ_MAP_OP_LBN 0 1558 #define MC_CMD_FC_IN_READ_MAP_OP_WIDTH 8 1559 /* enum: Get the number of map regions */ 1560 #define MC_CMD_FC_OP_READ_MAP_COUNT 0x1 1561 /* enum: Get the specified map */ 1562 #define MC_CMD_FC_OP_READ_MAP_INDEX 0x2 1563 1564 /* MC_CMD_FC_IN_READ_MAP_COUNT msgrequest */ 1565 #define MC_CMD_FC_IN_READ_MAP_COUNT_LEN 8 1566 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1567 /* MC_CMD_FC_IN_READ_MAP_HEADER_OFST 4 */ 1568 1569 /* MC_CMD_FC_IN_READ_MAP_INDEX msgrequest */ 1570 #define MC_CMD_FC_IN_READ_MAP_INDEX_LEN 12 1571 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1572 /* MC_CMD_FC_IN_READ_MAP_HEADER_OFST 4 */ 1573 #define MC_CMD_FC_IN_MAP_INDEX_OFST 8 1574 1575 /* MC_CMD_FC_IN_CAPABILITIES msgrequest */ 1576 #define MC_CMD_FC_IN_CAPABILITIES_LEN 4 1577 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1578 1579 /* MC_CMD_FC_IN_GLOBAL_FLAGS msgrequest */ 1580 #define MC_CMD_FC_IN_GLOBAL_FLAGS_LEN 8 1581 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1582 #define MC_CMD_FC_IN_GLOBAL_FLAGS_FLAGS_OFST 4 1583 #define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_CABLE_PLUGGED_IN_LBN 0 1584 #define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_CABLE_PLUGGED_IN_WIDTH 1 1585 #define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_LINK_MONITORING_LBN 1 1586 #define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_LINK_MONITORING_WIDTH 1 1587 #define MC_CMD_FC_IN_GLOBAL_FLAGS_DFE_ENABLE_LBN 2 1588 #define MC_CMD_FC_IN_GLOBAL_FLAGS_DFE_ENABLE_WIDTH 1 1589 #define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_EYE_ENABLE_LBN 3 1590 #define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_EYE_ENABLE_WIDTH 1 1591 #define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_TUNING_ENABLE_LBN 4 1592 #define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_TUNING_ENABLE_WIDTH 1 1593 #define MC_CMD_FC_IN_GLOBAL_FLAGS_OFFCAL_ENABLE_LBN 5 1594 #define MC_CMD_FC_IN_GLOBAL_FLAGS_OFFCAL_ENABLE_WIDTH 1 1595 1596 /* MC_CMD_FC_IN_IO_REL msgrequest */ 1597 #define MC_CMD_FC_IN_IO_REL_LEN 8 1598 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1599 #define MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 1600 #define MC_CMD_FC_IN_IO_REL_OP_LBN 0 1601 #define MC_CMD_FC_IN_IO_REL_OP_WIDTH 8 1602 /* enum: Get the base address that the FC applies to relative commands */ 1603 #define MC_CMD_FC_IN_IO_REL_GET_ADDR 0x1 1604 /* enum: Read data */ 1605 #define MC_CMD_FC_IN_IO_REL_READ32 0x2 1606 /* enum: Write data */ 1607 #define MC_CMD_FC_IN_IO_REL_WRITE32 0x3 1608 #define MC_CMD_FC_IN_IO_REL_COMP_TYPE_LBN 8 1609 #define MC_CMD_FC_IN_IO_REL_COMP_TYPE_WIDTH 8 1610 /* enum: Application address space */ 1611 #define MC_CMD_FC_COMP_TYPE_APP_ADDR_SPACE 0x1 1612 /* enum: Flash address space */ 1613 #define MC_CMD_FC_COMP_TYPE_FLASH 0x2 1614 1615 /* MC_CMD_FC_IN_IO_REL_GET_ADDR msgrequest */ 1616 #define MC_CMD_FC_IN_IO_REL_GET_ADDR_LEN 8 1617 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1618 /* MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 */ 1619 1620 /* MC_CMD_FC_IN_IO_REL_READ32 msgrequest */ 1621 #define MC_CMD_FC_IN_IO_REL_READ32_LEN 20 1622 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1623 /* MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 */ 1624 #define MC_CMD_FC_IN_IO_REL_READ32_ADDR_HI_OFST 8 1625 #define MC_CMD_FC_IN_IO_REL_READ32_ADDR_LO_OFST 12 1626 #define MC_CMD_FC_IN_IO_REL_READ32_NUMWORDS_OFST 16 1627 1628 /* MC_CMD_FC_IN_IO_REL_WRITE32 msgrequest */ 1629 #define MC_CMD_FC_IN_IO_REL_WRITE32_LENMIN 20 1630 #define MC_CMD_FC_IN_IO_REL_WRITE32_LENMAX 252 1631 #define MC_CMD_FC_IN_IO_REL_WRITE32_LEN(num) (16+4*(num)) 1632 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1633 /* MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 */ 1634 #define MC_CMD_FC_IN_IO_REL_WRITE32_ADDR_HI_OFST 8 1635 #define MC_CMD_FC_IN_IO_REL_WRITE32_ADDR_LO_OFST 12 1636 #define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_OFST 16 1637 #define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_LEN 4 1638 #define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_MINNUM 1 1639 #define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_MAXNUM 59 1640 1641 /* MC_CMD_FC_IN_UHLINK msgrequest */ 1642 #define MC_CMD_FC_IN_UHLINK_LEN 8 1643 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1644 #define MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 1645 #define MC_CMD_FC_IN_UHLINK_OP_LBN 0 1646 #define MC_CMD_FC_IN_UHLINK_OP_WIDTH 8 1647 /* enum: Get PHY configuration info */ 1648 #define MC_CMD_FC_OP_UHLINK_PHY 0x1 1649 /* enum: Get MAC configuration info */ 1650 #define MC_CMD_FC_OP_UHLINK_MAC 0x2 1651 /* enum: Get Rx eye table */ 1652 #define MC_CMD_FC_OP_UHLINK_RX_EYE 0x3 1653 /* enum: Get Rx eye plot */ 1654 #define MC_CMD_FC_OP_UHLINK_DUMP_RX_EYE_PLOT 0x4 1655 /* enum: Get Rx eye plot */ 1656 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT 0x5 1657 /* enum: Retune Rx settings */ 1658 #define MC_CMD_FC_OP_UHLINK_RX_TUNE 0x6 1659 /* enum: Set loopback mode on fpga port */ 1660 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET 0x7 1661 /* enum: Get loopback mode config state on fpga port */ 1662 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_GET 0x8 1663 #define MC_CMD_FC_IN_UHLINK_PORT_TYPE_LBN 8 1664 #define MC_CMD_FC_IN_UHLINK_PORT_TYPE_WIDTH 8 1665 #define MC_CMD_FC_IN_UHLINK_PORT_IDX_LBN 16 1666 #define MC_CMD_FC_IN_UHLINK_PORT_IDX_WIDTH 8 1667 #define MC_CMD_FC_IN_UHLINK_CMD_FORMAT_LBN 24 1668 #define MC_CMD_FC_IN_UHLINK_CMD_FORMAT_WIDTH 8 1669 /* enum: Default FC command format; the fields PORT_TYPE and PORT_IDX are 1670 * irrelevant. Port number is derived from pci_fn; passed in FC header. 1671 */ 1672 #define MC_CMD_FC_OP_UHLINK_CMD_FORMAT_DEFAULT 0x0 1673 /* enum: Override default port number. Port number determined by fields 1674 * PORT_TYPE and PORT_IDX. 1675 */ 1676 #define MC_CMD_FC_OP_UHLINK_CMD_FORMAT_PORT_OVERRIDE 0x1 1677 1678 /* MC_CMD_FC_OP_UHLINK_PHY msgrequest */ 1679 #define MC_CMD_FC_OP_UHLINK_PHY_LEN 8 1680 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1681 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 1682 1683 /* MC_CMD_FC_OP_UHLINK_MAC msgrequest */ 1684 #define MC_CMD_FC_OP_UHLINK_MAC_LEN 8 1685 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1686 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 1687 1688 /* MC_CMD_FC_OP_UHLINK_RX_EYE msgrequest */ 1689 #define MC_CMD_FC_OP_UHLINK_RX_EYE_LEN 12 1690 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1691 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 1692 #define MC_CMD_FC_OP_UHLINK_RX_EYE_INDEX_OFST 8 1693 #define MC_CMD_FC_UHLINK_RX_EYE_PER_BLOCK 0x30 /* enum */ 1694 1695 /* MC_CMD_FC_OP_UHLINK_DUMP_RX_EYE_PLOT msgrequest */ 1696 #define MC_CMD_FC_OP_UHLINK_DUMP_RX_EYE_PLOT_LEN 8 1697 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1698 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 1699 1700 /* MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT msgrequest */ 1701 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_LEN 20 1702 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1703 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 1704 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_DC_GAIN_OFST 8 1705 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_EQ_CONTROL_OFST 12 1706 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_INDEX_OFST 16 1707 #define MC_CMD_FC_UHLINK_RX_EYE_PLOT_ROWS_PER_BLOCK 0x1e /* enum */ 1708 1709 /* MC_CMD_FC_OP_UHLINK_RX_TUNE msgrequest */ 1710 #define MC_CMD_FC_OP_UHLINK_RX_TUNE_LEN 8 1711 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1712 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 1713 1714 /* MC_CMD_FC_OP_UHLINK_LOOPBACK_SET msgrequest */ 1715 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET_LEN 16 1716 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1717 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 1718 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET_TYPE_OFST 8 1719 #define MC_CMD_FC_UHLINK_LOOPBACK_TYPE_PCS_SERIAL 0x0 /* enum */ 1720 #define MC_CMD_FC_UHLINK_LOOPBACK_TYPE_PMA_PRE_CDR 0x1 /* enum */ 1721 #define MC_CMD_FC_UHLINK_LOOPBACK_TYPE_PMA_POST_CDR 0x2 /* enum */ 1722 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET_STATE_OFST 12 1723 #define MC_CMD_FC_UHLINK_LOOPBACK_STATE_OFF 0x0 /* enum */ 1724 #define MC_CMD_FC_UHLINK_LOOPBACK_STATE_ON 0x1 /* enum */ 1725 1726 /* MC_CMD_FC_OP_UHLINK_LOOPBACK_GET msgrequest */ 1727 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_GET_LEN 12 1728 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1729 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 1730 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_GET_TYPE_OFST 8 1731 1732 /* MC_CMD_FC_IN_SET_LINK msgrequest */ 1733 #define MC_CMD_FC_IN_SET_LINK_LEN 16 1734 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1735 /* See MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */ 1736 #define MC_CMD_FC_IN_SET_LINK_MODE_OFST 4 1737 #define MC_CMD_FC_IN_SET_LINK_SPEED_OFST 8 1738 #define MC_CMD_FC_IN_SET_LINK_FLAGS_OFST 12 1739 #define MC_CMD_FC_IN_SET_LINK_LOWPOWER_LBN 0 1740 #define MC_CMD_FC_IN_SET_LINK_LOWPOWER_WIDTH 1 1741 #define MC_CMD_FC_IN_SET_LINK_POWEROFF_LBN 1 1742 #define MC_CMD_FC_IN_SET_LINK_POWEROFF_WIDTH 1 1743 #define MC_CMD_FC_IN_SET_LINK_TXDIS_LBN 2 1744 #define MC_CMD_FC_IN_SET_LINK_TXDIS_WIDTH 1 1745 1746 /* MC_CMD_FC_IN_LICENSE msgrequest */ 1747 #define MC_CMD_FC_IN_LICENSE_LEN 8 1748 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1749 #define MC_CMD_FC_IN_LICENSE_OP_OFST 4 1750 #define MC_CMD_FC_IN_LICENSE_UPDATE_LICENSE 0x0 /* enum */ 1751 #define MC_CMD_FC_IN_LICENSE_GET_KEY_STATS 0x1 /* enum */ 1752 1753 /* MC_CMD_FC_IN_STARTUP msgrequest */ 1754 #define MC_CMD_FC_IN_STARTUP_LEN 40 1755 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1756 #define MC_CMD_FC_IN_STARTUP_BASE_OFST 4 1757 #define MC_CMD_FC_IN_STARTUP_LENGTH_OFST 8 1758 /* Length of identifier */ 1759 #define MC_CMD_FC_IN_STARTUP_IDLENGTH_OFST 12 1760 /* Identifier for AOE FPGA */ 1761 #define MC_CMD_FC_IN_STARTUP_ID_OFST 16 1762 #define MC_CMD_FC_IN_STARTUP_ID_LEN 1 1763 #define MC_CMD_FC_IN_STARTUP_ID_NUM 24 1764 1765 /* MC_CMD_FC_IN_DMA msgrequest */ 1766 #define MC_CMD_FC_IN_DMA_LEN 8 1767 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1768 #define MC_CMD_FC_IN_DMA_OP_OFST 4 1769 #define MC_CMD_FC_IN_DMA_STOP 0x0 /* enum */ 1770 #define MC_CMD_FC_IN_DMA_READ 0x1 /* enum */ 1771 1772 /* MC_CMD_FC_IN_DMA_STOP msgrequest */ 1773 #define MC_CMD_FC_IN_DMA_STOP_LEN 12 1774 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1775 /* MC_CMD_FC_IN_DMA_OP_OFST 4 */ 1776 /* FC supplied handle */ 1777 #define MC_CMD_FC_IN_DMA_STOP_FC_HANDLE_OFST 8 1778 1779 /* MC_CMD_FC_IN_DMA_READ msgrequest */ 1780 #define MC_CMD_FC_IN_DMA_READ_LEN 16 1781 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1782 /* MC_CMD_FC_IN_DMA_OP_OFST 4 */ 1783 #define MC_CMD_FC_IN_DMA_READ_OFFSET_OFST 8 1784 #define MC_CMD_FC_IN_DMA_READ_LENGTH_OFST 12 1785 1786 /* MC_CMD_FC_IN_TIMED_READ msgrequest */ 1787 #define MC_CMD_FC_IN_TIMED_READ_LEN 8 1788 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1789 #define MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 1790 #define MC_CMD_FC_IN_TIMED_READ_SET 0x0 /* enum */ 1791 #define MC_CMD_FC_IN_TIMED_READ_GET 0x1 /* enum */ 1792 #define MC_CMD_FC_IN_TIMED_READ_CLEAR 0x2 /* enum */ 1793 1794 /* MC_CMD_FC_IN_TIMED_READ_SET msgrequest */ 1795 #define MC_CMD_FC_IN_TIMED_READ_SET_LEN 52 1796 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1797 /* MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 */ 1798 /* Host supplied handle (unique) */ 1799 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_HANDLE_OFST 8 1800 /* Address into which to transfer data in host */ 1801 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_OFST 12 1802 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_LEN 8 1803 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_LO_OFST 12 1804 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_HI_OFST 16 1805 /* AOE address from which to transfer data */ 1806 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_OFST 20 1807 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_LEN 8 1808 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_LO_OFST 20 1809 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_HI_OFST 24 1810 /* Length of AOE transfer (total) */ 1811 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_LENGTH_OFST 28 1812 /* Length of host transfer (total) */ 1813 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_LENGTH_OFST 32 1814 /* Offset back from aoe_address to apply operation to */ 1815 #define MC_CMD_FC_IN_TIMED_READ_SET_OFFSET_OFST 36 1816 /* Data to apply at offset */ 1817 #define MC_CMD_FC_IN_TIMED_READ_SET_DATA_OFST 40 1818 #define MC_CMD_FC_IN_TIMED_READ_SET_FLAGS_OFST 44 1819 #define MC_CMD_FC_IN_TIMED_READ_SET_INDIRECT_LBN 0 1820 #define MC_CMD_FC_IN_TIMED_READ_SET_INDIRECT_WIDTH 1 1821 #define MC_CMD_FC_IN_TIMED_READ_SET_DOUBLE_LBN 1 1822 #define MC_CMD_FC_IN_TIMED_READ_SET_DOUBLE_WIDTH 1 1823 #define MC_CMD_FC_IN_TIMED_READ_SET_EVENT_LBN 2 1824 #define MC_CMD_FC_IN_TIMED_READ_SET_EVENT_WIDTH 1 1825 #define MC_CMD_FC_IN_TIMED_READ_SET_PREREAD_LBN 3 1826 #define MC_CMD_FC_IN_TIMED_READ_SET_PREREAD_WIDTH 2 1827 #define MC_CMD_FC_IN_TIMED_READ_SET_NONE 0x0 /* enum */ 1828 #define MC_CMD_FC_IN_TIMED_READ_SET_READ 0x1 /* enum */ 1829 #define MC_CMD_FC_IN_TIMED_READ_SET_WRITE 0x2 /* enum */ 1830 #define MC_CMD_FC_IN_TIMED_READ_SET_READWRITE 0x3 /* enum */ 1831 /* Period at which reads are performed (100ms units) */ 1832 #define MC_CMD_FC_IN_TIMED_READ_SET_PERIOD_OFST 48 1833 1834 /* MC_CMD_FC_IN_TIMED_READ_GET msgrequest */ 1835 #define MC_CMD_FC_IN_TIMED_READ_GET_LEN 12 1836 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1837 /* MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 */ 1838 /* FC supplied handle */ 1839 #define MC_CMD_FC_IN_TIMED_READ_GET_FC_HANDLE_OFST 8 1840 1841 /* MC_CMD_FC_IN_TIMED_READ_CLEAR msgrequest */ 1842 #define MC_CMD_FC_IN_TIMED_READ_CLEAR_LEN 12 1843 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1844 /* MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 */ 1845 /* FC supplied handle */ 1846 #define MC_CMD_FC_IN_TIMED_READ_CLEAR_FC_HANDLE_OFST 8 1847 1848 /* MC_CMD_FC_IN_LOG msgrequest */ 1849 #define MC_CMD_FC_IN_LOG_LEN 8 1850 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1851 #define MC_CMD_FC_IN_LOG_OP_OFST 4 1852 #define MC_CMD_FC_IN_LOG_ADDR_RANGE 0x0 /* enum */ 1853 #define MC_CMD_FC_IN_LOG_JTAG_UART 0x1 /* enum */ 1854 1855 /* MC_CMD_FC_IN_LOG_ADDR_RANGE msgrequest */ 1856 #define MC_CMD_FC_IN_LOG_ADDR_RANGE_LEN 20 1857 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1858 /* MC_CMD_FC_IN_LOG_OP_OFST 4 */ 1859 /* Partition offset into flash */ 1860 #define MC_CMD_FC_IN_LOG_ADDR_RANGE_OFFSET_OFST 8 1861 /* Partition length */ 1862 #define MC_CMD_FC_IN_LOG_ADDR_RANGE_LENGTH_OFST 12 1863 /* Partition erase size */ 1864 #define MC_CMD_FC_IN_LOG_ADDR_RANGE_ERASE_SIZE_OFST 16 1865 1866 /* MC_CMD_FC_IN_LOG_JTAG_UART msgrequest */ 1867 #define MC_CMD_FC_IN_LOG_JTAG_UART_LEN 12 1868 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1869 /* MC_CMD_FC_IN_LOG_OP_OFST 4 */ 1870 /* Enable/disable printing to JTAG UART */ 1871 #define MC_CMD_FC_IN_LOG_JTAG_UART_ENABLE_OFST 8 1872 1873 /* MC_CMD_FC_IN_CLOCK msgrequest */ 1874 #define MC_CMD_FC_IN_CLOCK_LEN 12 1875 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1876 #define MC_CMD_FC_IN_CLOCK_OP_OFST 4 1877 #define MC_CMD_FC_IN_CLOCK_GET_TIME 0x0 /* enum */ 1878 #define MC_CMD_FC_IN_CLOCK_SET_TIME 0x1 /* enum */ 1879 /* Perform a clock operation */ 1880 #define MC_CMD_FC_IN_CLOCK_ID_OFST 8 1881 #define MC_CMD_FC_IN_CLOCK_STATS 0x0 /* enum */ 1882 #define MC_CMD_FC_IN_CLOCK_MAC 0x1 /* enum */ 1883 1884 /* MC_CMD_FC_IN_CLOCK_GET_TIME msgrequest */ 1885 #define MC_CMD_FC_IN_CLOCK_GET_TIME_LEN 12 1886 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1887 /* MC_CMD_FC_IN_CLOCK_OP_OFST 4 */ 1888 /* Retrieve the clock value of the specified clock */ 1889 /* MC_CMD_FC_IN_CLOCK_ID_OFST 8 */ 1890 1891 /* MC_CMD_FC_IN_CLOCK_SET_TIME msgrequest */ 1892 #define MC_CMD_FC_IN_CLOCK_SET_TIME_LEN 24 1893 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1894 /* MC_CMD_FC_IN_CLOCK_OP_OFST 4 */ 1895 /* MC_CMD_FC_IN_CLOCK_ID_OFST 8 */ 1896 #define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_OFST 12 1897 #define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LEN 8 1898 #define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LO_OFST 12 1899 #define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_HI_OFST 16 1900 /* Set the clock value of the specified clock */ 1901 #define MC_CMD_FC_IN_CLOCK_SET_TIME_NANOSECONDS_OFST 20 1902 1903 /* MC_CMD_FC_IN_DDR msgrequest */ 1904 #define MC_CMD_FC_IN_DDR_LEN 12 1905 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1906 #define MC_CMD_FC_IN_DDR_OP_OFST 4 1907 #define MC_CMD_FC_IN_DDR_SET_SPD 0x0 /* enum */ 1908 #define MC_CMD_FC_IN_DDR_GET_STATUS 0x1 /* enum */ 1909 #define MC_CMD_FC_IN_DDR_SET_INFO 0x2 /* enum */ 1910 #define MC_CMD_FC_IN_DDR_BANK_OFST 8 1911 #define MC_CMD_FC_IN_DDR_BANK_B0 0x0 /* enum */ 1912 #define MC_CMD_FC_IN_DDR_BANK_B1 0x1 /* enum */ 1913 #define MC_CMD_FC_IN_DDR_BANK_T0 0x2 /* enum */ 1914 #define MC_CMD_FC_IN_DDR_BANK_T1 0x3 /* enum */ 1915 #define MC_CMD_FC_IN_DDR_NUM_BANKS 0x4 /* enum */ 1916 1917 /* MC_CMD_FC_IN_DDR_SET_SPD msgrequest */ 1918 #define MC_CMD_FC_IN_DDR_SET_SPD_LEN 148 1919 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1920 /* MC_CMD_FC_IN_DDR_OP_OFST 4 */ 1921 /* Affected bank */ 1922 /* MC_CMD_FC_IN_DDR_BANK_OFST 8 */ 1923 /* Flags */ 1924 #define MC_CMD_FC_IN_DDR_FLAGS_OFST 12 1925 #define MC_CMD_FC_IN_DDR_SET_SPD_ACTIVE 0x1 /* enum */ 1926 /* 128-byte page of serial presence detect data read from module's EEPROM */ 1927 #define MC_CMD_FC_IN_DDR_SPD_OFST 16 1928 #define MC_CMD_FC_IN_DDR_SPD_LEN 1 1929 #define MC_CMD_FC_IN_DDR_SPD_NUM 128 1930 /* Page index of the spd data copied into MC_CMD_FC_IN_DDR_SPD */ 1931 #define MC_CMD_FC_IN_DDR_SPD_PAGE_ID_OFST 144 1932 1933 /* MC_CMD_FC_IN_DDR_SET_INFO msgrequest */ 1934 #define MC_CMD_FC_IN_DDR_SET_INFO_LEN 16 1935 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1936 /* MC_CMD_FC_IN_DDR_OP_OFST 4 */ 1937 /* Affected bank */ 1938 /* MC_CMD_FC_IN_DDR_BANK_OFST 8 */ 1939 /* Size of DDR */ 1940 #define MC_CMD_FC_IN_DDR_SIZE_OFST 12 1941 1942 /* MC_CMD_FC_IN_DDR_GET_STATUS msgrequest */ 1943 #define MC_CMD_FC_IN_DDR_GET_STATUS_LEN 12 1944 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1945 /* MC_CMD_FC_IN_DDR_OP_OFST 4 */ 1946 /* Affected bank */ 1947 /* MC_CMD_FC_IN_DDR_BANK_OFST 8 */ 1948 1949 /* MC_CMD_FC_IN_TIMESTAMP msgrequest */ 1950 #define MC_CMD_FC_IN_TIMESTAMP_LEN 8 1951 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1952 /* FC timestamp operation code */ 1953 #define MC_CMD_FC_IN_TIMESTAMP_OP_OFST 4 1954 /* enum: Read transmit timestamp(s) */ 1955 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT 0x0 1956 /* enum: Read snapshot timestamps */ 1957 #define MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT 0x1 1958 /* enum: Clear all transmit timestamps */ 1959 #define MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT 0x2 1960 1961 /* MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT msgrequest */ 1962 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_LEN 28 1963 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1964 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_OP_OFST 4 1965 /* Control filtering of the returned timestamp and sequence number specified 1966 * here 1967 */ 1968 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_FILTER_OFST 8 1969 /* enum: Return most recent timestamp. No filtering */ 1970 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_LATEST 0x0 1971 /* enum: Match timestamp against the PTP clock ID, port number and sequence 1972 * number specified 1973 */ 1974 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_MATCH 0x1 1975 /* Clock identity of PTP packet for which timestamp required */ 1976 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_OFST 12 1977 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_LEN 8 1978 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_LO_OFST 12 1979 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_HI_OFST 16 1980 /* Port number of PTP packet for which timestamp required */ 1981 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_PORT_NUM_OFST 20 1982 /* Sequence number of PTP packet for which timestamp required */ 1983 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_SEQ_NUM_OFST 24 1984 1985 /* MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT msgrequest */ 1986 #define MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT_LEN 8 1987 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1988 #define MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT_OP_OFST 4 1989 1990 /* MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT msgrequest */ 1991 #define MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT_LEN 8 1992 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1993 #define MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT_OP_OFST 4 1994 1995 /* MC_CMD_FC_IN_SPI msgrequest */ 1996 #define MC_CMD_FC_IN_SPI_LEN 8 1997 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1998 /* Basic commands for SPI Flash. */ 1999 #define MC_CMD_FC_IN_SPI_OP_OFST 4 2000 /* enum: SPI Flash read */ 2001 #define MC_CMD_FC_IN_SPI_READ 0x0 2002 /* enum: SPI Flash write */ 2003 #define MC_CMD_FC_IN_SPI_WRITE 0x1 2004 /* enum: SPI Flash erase */ 2005 #define MC_CMD_FC_IN_SPI_ERASE 0x2 2006 2007 /* MC_CMD_FC_IN_SPI_READ msgrequest */ 2008 #define MC_CMD_FC_IN_SPI_READ_LEN 16 2009 /* MC_CMD_FC_IN_CMD_OFST 0 */ 2010 #define MC_CMD_FC_IN_SPI_READ_OP_OFST 4 2011 #define MC_CMD_FC_IN_SPI_READ_ADDR_OFST 8 2012 #define MC_CMD_FC_IN_SPI_READ_NUMBYTES_OFST 12 2013 2014 /* MC_CMD_FC_IN_SPI_WRITE msgrequest */ 2015 #define MC_CMD_FC_IN_SPI_WRITE_LENMIN 16 2016 #define MC_CMD_FC_IN_SPI_WRITE_LENMAX 252 2017 #define MC_CMD_FC_IN_SPI_WRITE_LEN(num) (12+4*(num)) 2018 /* MC_CMD_FC_IN_CMD_OFST 0 */ 2019 #define MC_CMD_FC_IN_SPI_WRITE_OP_OFST 4 2020 #define MC_CMD_FC_IN_SPI_WRITE_ADDR_OFST 8 2021 #define MC_CMD_FC_IN_SPI_WRITE_BUFFER_OFST 12 2022 #define MC_CMD_FC_IN_SPI_WRITE_BUFFER_LEN 4 2023 #define MC_CMD_FC_IN_SPI_WRITE_BUFFER_MINNUM 1 2024 #define MC_CMD_FC_IN_SPI_WRITE_BUFFER_MAXNUM 60 2025 2026 /* MC_CMD_FC_IN_SPI_ERASE msgrequest */ 2027 #define MC_CMD_FC_IN_SPI_ERASE_LEN 16 2028 /* MC_CMD_FC_IN_CMD_OFST 0 */ 2029 #define MC_CMD_FC_IN_SPI_ERASE_OP_OFST 4 2030 #define MC_CMD_FC_IN_SPI_ERASE_ADDR_OFST 8 2031 #define MC_CMD_FC_IN_SPI_ERASE_NUMBYTES_OFST 12 2032 2033 /* MC_CMD_FC_IN_DIAG msgrequest */ 2034 #define MC_CMD_FC_IN_DIAG_LEN 8 2035 /* MC_CMD_FC_IN_CMD_OFST 0 */ 2036 /* Operation code indicating component type */ 2037 #define MC_CMD_FC_IN_DIAG_OP_OFST 4 2038 /* enum: Power noise generator. */ 2039 #define MC_CMD_FC_IN_DIAG_POWER_NOISE 0x0 2040 /* enum: DDR soak test component. */ 2041 #define MC_CMD_FC_IN_DIAG_DDR_SOAK 0x1 2042 /* enum: Diagnostics datapath control component. */ 2043 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL 0x2 2044 2045 /* MC_CMD_FC_IN_DIAG_POWER_NOISE msgrequest */ 2046 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_LEN 12 2047 /* MC_CMD_FC_IN_CMD_OFST 0 */ 2048 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_OP_OFST 4 2049 /* Sub-opcode describing the operation to be carried out */ 2050 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_SUB_OP_OFST 8 2051 /* enum: Read the configuration (the 32-bit values in each of the clock enable 2052 * count and toggle count registers) 2053 */ 2054 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG 0x0 2055 /* enum: Write a new configuration to the clock enable count and toggle count 2056 * registers 2057 */ 2058 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG 0x1 2059 2060 /* MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG msgrequest */ 2061 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_LEN 12 2062 /* MC_CMD_FC_IN_CMD_OFST 0 */ 2063 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_OP_OFST 4 2064 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_SUB_OP_OFST 8 2065 2066 /* MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG msgrequest */ 2067 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_LEN 20 2068 /* MC_CMD_FC_IN_CMD_OFST 0 */ 2069 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_OP_OFST 4 2070 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_SUB_OP_OFST 8 2071 /* The 32-bit value to be written to the toggle count register */ 2072 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_TOGGLE_COUNT_OFST 12 2073 /* The 32-bit value to be written to the clock enable count register */ 2074 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_CLKEN_COUNT_OFST 16 2075 2076 /* MC_CMD_FC_IN_DIAG_DDR_SOAK msgrequest */ 2077 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_LEN 12 2078 /* MC_CMD_FC_IN_CMD_OFST 0 */ 2079 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_OP_OFST 4 2080 /* Sub-opcode describing the operation to be carried out */ 2081 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_SUB_OP_OFST 8 2082 /* enum: Starts DDR soak test on selected banks */ 2083 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START 0x0 2084 /* enum: Read status of DDR soak test */ 2085 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT 0x1 2086 /* enum: Stop test */ 2087 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP 0x2 2088 /* enum: Set or clear bit that triggers fake errors. These cause subsequent 2089 * tests to fail until the bit is cleared. 2090 */ 2091 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR 0x3 2092 2093 /* MC_CMD_FC_IN_DIAG_DDR_SOAK_START msgrequest */ 2094 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_LEN 24 2095 /* MC_CMD_FC_IN_CMD_OFST 0 */ 2096 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_OP_OFST 4 2097 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_SUB_OP_OFST 8 2098 /* Mask of DDR banks to be tested */ 2099 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_BANK_MASK_OFST 12 2100 /* Pattern to use in the soak test */ 2101 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_TEST_PATTERN_OFST 16 2102 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_ZEROS 0x0 /* enum */ 2103 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_ONES 0x1 /* enum */ 2104 /* Either multiple automatic tests until a STOP command is issued, or one 2105 * single test 2106 */ 2107 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_TEST_TYPE_OFST 20 2108 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_ONGOING_TEST 0x0 /* enum */ 2109 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_SINGLE_TEST 0x1 /* enum */ 2110 2111 /* MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT msgrequest */ 2112 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_LEN 16 2113 /* MC_CMD_FC_IN_CMD_OFST 0 */ 2114 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_OP_OFST 4 2115 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_SUB_OP_OFST 8 2116 /* DDR bank to read status from */ 2117 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_BANK_ID_OFST 12 2118 #define MC_CMD_FC_DDR_BANK0 0x0 /* enum */ 2119 #define MC_CMD_FC_DDR_BANK1 0x1 /* enum */ 2120 #define MC_CMD_FC_DDR_BANK2 0x2 /* enum */ 2121 #define MC_CMD_FC_DDR_BANK3 0x3 /* enum */ 2122 #define MC_CMD_FC_DDR_AOEMEM_MAX_BANKS 0x4 /* enum */ 2123 2124 /* MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP msgrequest */ 2125 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_LEN 16 2126 /* MC_CMD_FC_IN_CMD_OFST 0 */ 2127 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_OP_OFST 4 2128 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_SUB_OP_OFST 8 2129 /* Mask of DDR banks to be tested */ 2130 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_BANK_MASK_OFST 12 2131 2132 /* MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR msgrequest */ 2133 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_LEN 20 2134 /* MC_CMD_FC_IN_CMD_OFST 0 */ 2135 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_OP_OFST 4 2136 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_SUB_OP_OFST 8 2137 /* Mask of DDR banks to set/clear error flag on */ 2138 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_BANK_MASK_OFST 12 2139 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_FLAG_ACTION_OFST 16 2140 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_CLEAR 0x0 /* enum */ 2141 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_SET 0x1 /* enum */ 2142 2143 /* MC_CMD_FC_IN_DIAG_DATAPATH_CTRL msgrequest */ 2144 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_LEN 12 2145 /* MC_CMD_FC_IN_CMD_OFST 0 */ 2146 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_OP_OFST 4 2147 /* Sub-opcode describing the operation to be carried out */ 2148 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SUB_OP_OFST 8 2149 /* enum: Set a known datapath configuration */ 2150 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE 0x0 2151 /* enum: Apply raw config to datapath control registers */ 2152 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG 0x1 2153 2154 /* MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE msgrequest */ 2155 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_LEN 16 2156 /* MC_CMD_FC_IN_CMD_OFST 0 */ 2157 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_OP_OFST 4 2158 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_SUB_OP_OFST 8 2159 /* Datapath configuration identifier */ 2160 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_MODE_OFST 12 2161 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_PASSTHROUGH 0x0 /* enum */ 2162 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_SNAKE 0x1 /* enum */ 2163 2164 /* MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG msgrequest */ 2165 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_LEN 24 2166 /* MC_CMD_FC_IN_CMD_OFST 0 */ 2167 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_OP_OFST 4 2168 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_SUB_OP_OFST 8 2169 /* Value to write into control register 1 */ 2170 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL1_OFST 12 2171 /* Value to write into control register 2 */ 2172 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL2_OFST 16 2173 /* Value to write into control register 3 */ 2174 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL3_OFST 20 2175 2176 /* MC_CMD_FC_OUT msgresponse */ 2177 #define MC_CMD_FC_OUT_LEN 0 2178 2179 /* MC_CMD_FC_OUT_NULL msgresponse */ 2180 #define MC_CMD_FC_OUT_NULL_LEN 0 2181 2182 /* MC_CMD_FC_OUT_READ32 msgresponse */ 2183 #define MC_CMD_FC_OUT_READ32_LENMIN 4 2184 #define MC_CMD_FC_OUT_READ32_LENMAX 252 2185 #define MC_CMD_FC_OUT_READ32_LEN(num) (0+4*(num)) 2186 #define MC_CMD_FC_OUT_READ32_BUFFER_OFST 0 2187 #define MC_CMD_FC_OUT_READ32_BUFFER_LEN 4 2188 #define MC_CMD_FC_OUT_READ32_BUFFER_MINNUM 1 2189 #define MC_CMD_FC_OUT_READ32_BUFFER_MAXNUM 63 2190 2191 /* MC_CMD_FC_OUT_WRITE32 msgresponse */ 2192 #define MC_CMD_FC_OUT_WRITE32_LEN 0 2193 2194 /* MC_CMD_FC_OUT_TRC_READ msgresponse */ 2195 #define MC_CMD_FC_OUT_TRC_READ_LEN 16 2196 #define MC_CMD_FC_OUT_TRC_READ_DATA_OFST 0 2197 #define MC_CMD_FC_OUT_TRC_READ_DATA_LEN 4 2198 #define MC_CMD_FC_OUT_TRC_READ_DATA_NUM 4 2199 2200 /* MC_CMD_FC_OUT_TRC_WRITE msgresponse */ 2201 #define MC_CMD_FC_OUT_TRC_WRITE_LEN 0 2202 2203 /* MC_CMD_FC_OUT_GET_VERSION msgresponse */ 2204 #define MC_CMD_FC_OUT_GET_VERSION_LEN 12 2205 #define MC_CMD_FC_OUT_GET_VERSION_FIRMWARE_OFST 0 2206 #define MC_CMD_FC_OUT_GET_VERSION_VERSION_OFST 4 2207 #define MC_CMD_FC_OUT_GET_VERSION_VERSION_LEN 8 2208 #define MC_CMD_FC_OUT_GET_VERSION_VERSION_LO_OFST 4 2209 #define MC_CMD_FC_OUT_GET_VERSION_VERSION_HI_OFST 8 2210 2211 /* MC_CMD_FC_OUT_TRC_RX_READ msgresponse */ 2212 #define MC_CMD_FC_OUT_TRC_RX_READ_LEN 8 2213 #define MC_CMD_FC_OUT_TRC_RX_READ_DATA_OFST 0 2214 #define MC_CMD_FC_OUT_TRC_RX_READ_DATA_LEN 4 2215 #define MC_CMD_FC_OUT_TRC_RX_READ_DATA_NUM 2 2216 2217 /* MC_CMD_FC_OUT_TRC_RX_WRITE msgresponse */ 2218 #define MC_CMD_FC_OUT_TRC_RX_WRITE_LEN 0 2219 2220 /* MC_CMD_FC_OUT_MAC_RECONFIGURE msgresponse */ 2221 #define MC_CMD_FC_OUT_MAC_RECONFIGURE_LEN 0 2222 2223 /* MC_CMD_FC_OUT_MAC_SET_LINK msgresponse */ 2224 #define MC_CMD_FC_OUT_MAC_SET_LINK_LEN 0 2225 2226 /* MC_CMD_FC_OUT_MAC_READ_STATUS msgresponse */ 2227 #define MC_CMD_FC_OUT_MAC_READ_STATUS_LEN 4 2228 #define MC_CMD_FC_OUT_MAC_READ_STATUS_STATUS_OFST 0 2229 2230 /* MC_CMD_FC_OUT_MAC_GET_RX_STATS msgresponse */ 2231 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_LEN ((((0-1+(64*MC_CMD_FC_MAC_RX_NSTATS))+1))>>3) 2232 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_OFST 0 2233 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_LEN 8 2234 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_LO_OFST 0 2235 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_HI_OFST 4 2236 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_NUM MC_CMD_FC_MAC_RX_NSTATS 2237 #define MC_CMD_FC_MAC_RX_STATS_OCTETS 0x0 /* enum */ 2238 #define MC_CMD_FC_MAC_RX_OCTETS_OK 0x1 /* enum */ 2239 #define MC_CMD_FC_MAC_RX_ALIGNMENT_ERRORS 0x2 /* enum */ 2240 #define MC_CMD_FC_MAC_RX_PAUSE_MAC_CTRL_FRAMES 0x3 /* enum */ 2241 #define MC_CMD_FC_MAC_RX_FRAMES_OK 0x4 /* enum */ 2242 #define MC_CMD_FC_MAC_RX_CRC_ERRORS 0x5 /* enum */ 2243 #define MC_CMD_FC_MAC_RX_VLAN_OK 0x6 /* enum */ 2244 #define MC_CMD_FC_MAC_RX_ERRORS 0x7 /* enum */ 2245 #define MC_CMD_FC_MAC_RX_UCAST_PKTS 0x8 /* enum */ 2246 #define MC_CMD_FC_MAC_RX_MULTICAST_PKTS 0x9 /* enum */ 2247 #define MC_CMD_FC_MAC_RX_BROADCAST_PKTS 0xa /* enum */ 2248 #define MC_CMD_FC_MAC_RX_STATS_DROP_EVENTS 0xb /* enum */ 2249 #define MC_CMD_FC_MAC_RX_STATS_PKTS 0xc /* enum */ 2250 #define MC_CMD_FC_MAC_RX_STATS_UNDERSIZE_PKTS 0xd /* enum */ 2251 #define MC_CMD_FC_MAC_RX_STATS_PKTS_64 0xe /* enum */ 2252 #define MC_CMD_FC_MAC_RX_STATS_PKTS_65_127 0xf /* enum */ 2253 #define MC_CMD_FC_MAC_RX_STATS_PKTS_128_255 0x10 /* enum */ 2254 #define MC_CMD_FC_MAC_RX_STATS_PKTS_256_511 0x11 /* enum */ 2255 #define MC_CMD_FC_MAC_RX_STATS_PKTS_512_1023 0x12 /* enum */ 2256 #define MC_CMD_FC_MAC_RX_STATS_PKTS_1024_1518 0x13 /* enum */ 2257 #define MC_CMD_FC_MAC_RX_STATS_PKTS_1519_MAX 0x14 /* enum */ 2258 #define MC_CMD_FC_MAC_RX_STATS_OVERSIZE_PKTS 0x15 /* enum */ 2259 #define MC_CMD_FC_MAC_RX_STATS_JABBERS 0x16 /* enum */ 2260 #define MC_CMD_FC_MAC_RX_STATS_FRAGMENTS 0x17 /* enum */ 2261 #define MC_CMD_FC_MAC_RX_MAC_CONTROL_FRAMES 0x18 /* enum */ 2262 /* enum: (Last entry) */ 2263 #define MC_CMD_FC_MAC_RX_NSTATS 0x19 2264 2265 /* MC_CMD_FC_OUT_MAC_GET_TX_STATS msgresponse */ 2266 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_LEN ((((0-1+(64*MC_CMD_FC_MAC_TX_NSTATS))+1))>>3) 2267 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_OFST 0 2268 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_LEN 8 2269 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_LO_OFST 0 2270 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_HI_OFST 4 2271 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_NUM MC_CMD_FC_MAC_TX_NSTATS 2272 #define MC_CMD_FC_MAC_TX_STATS_OCTETS 0x0 /* enum */ 2273 #define MC_CMD_FC_MAC_TX_OCTETS_OK 0x1 /* enum */ 2274 #define MC_CMD_FC_MAC_TX_ALIGNMENT_ERRORS 0x2 /* enum */ 2275 #define MC_CMD_FC_MAC_TX_PAUSE_MAC_CTRL_FRAMES 0x3 /* enum */ 2276 #define MC_CMD_FC_MAC_TX_FRAMES_OK 0x4 /* enum */ 2277 #define MC_CMD_FC_MAC_TX_CRC_ERRORS 0x5 /* enum */ 2278 #define MC_CMD_FC_MAC_TX_VLAN_OK 0x6 /* enum */ 2279 #define MC_CMD_FC_MAC_TX_ERRORS 0x7 /* enum */ 2280 #define MC_CMD_FC_MAC_TX_UCAST_PKTS 0x8 /* enum */ 2281 #define MC_CMD_FC_MAC_TX_MULTICAST_PKTS 0x9 /* enum */ 2282 #define MC_CMD_FC_MAC_TX_BROADCAST_PKTS 0xa /* enum */ 2283 #define MC_CMD_FC_MAC_TX_STATS_DROP_EVENTS 0xb /* enum */ 2284 #define MC_CMD_FC_MAC_TX_STATS_PKTS 0xc /* enum */ 2285 #define MC_CMD_FC_MAC_TX_STATS_UNDERSIZE_PKTS 0xd /* enum */ 2286 #define MC_CMD_FC_MAC_TX_STATS_PKTS_64 0xe /* enum */ 2287 #define MC_CMD_FC_MAC_TX_STATS_PKTS_65_127 0xf /* enum */ 2288 #define MC_CMD_FC_MAC_TX_STATS_PKTS_128_255 0x10 /* enum */ 2289 #define MC_CMD_FC_MAC_TX_STATS_PKTS_256_511 0x11 /* enum */ 2290 #define MC_CMD_FC_MAC_TX_STATS_PKTS_512_1023 0x12 /* enum */ 2291 #define MC_CMD_FC_MAC_TX_STATS_PKTS_1024_1518 0x13 /* enum */ 2292 #define MC_CMD_FC_MAC_TX_STATS_PKTS_1519_TX_MTU 0x14 /* enum */ 2293 #define MC_CMD_FC_MAC_TX_MAC_CONTROL_FRAMES 0x15 /* enum */ 2294 /* enum: (Last entry) */ 2295 #define MC_CMD_FC_MAC_TX_NSTATS 0x16 2296 2297 /* MC_CMD_FC_OUT_MAC_GET_STATS msgresponse */ 2298 #define MC_CMD_FC_OUT_MAC_GET_STATS_LEN ((((0-1+(64*MC_CMD_FC_MAC_NSTATS_PER_BLOCK))+1))>>3) 2299 /* MAC Statistics */ 2300 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_OFST 0 2301 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_LEN 8 2302 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_LO_OFST 0 2303 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_HI_OFST 4 2304 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_NUM MC_CMD_FC_MAC_NSTATS_PER_BLOCK 2305 2306 /* MC_CMD_FC_OUT_MAC msgresponse */ 2307 #define MC_CMD_FC_OUT_MAC_LEN 0 2308 2309 /* MC_CMD_FC_OUT_SFP msgresponse */ 2310 #define MC_CMD_FC_OUT_SFP_LEN 0 2311 2312 /* MC_CMD_FC_OUT_DDR_TEST_START msgresponse */ 2313 #define MC_CMD_FC_OUT_DDR_TEST_START_LEN 0 2314 2315 /* MC_CMD_FC_OUT_DDR_TEST_POLL msgresponse */ 2316 #define MC_CMD_FC_OUT_DDR_TEST_POLL_LEN 8 2317 #define MC_CMD_FC_OUT_DDR_TEST_POLL_STATUS_OFST 0 2318 #define MC_CMD_FC_OUT_DDR_TEST_POLL_CODE_LBN 0 2319 #define MC_CMD_FC_OUT_DDR_TEST_POLL_CODE_WIDTH 8 2320 /* enum: Test not yet initiated */ 2321 #define MC_CMD_FC_OP_DDR_TEST_NONE 0x0 2322 /* enum: Test is in progress */ 2323 #define MC_CMD_FC_OP_DDR_TEST_INPROGRESS 0x1 2324 /* enum: Timed completed */ 2325 #define MC_CMD_FC_OP_DDR_TEST_SUCCESS 0x2 2326 /* enum: Test did not complete in specified time */ 2327 #define MC_CMD_FC_OP_DDR_TEST_TIMER_EXPIRED 0x3 2328 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T0_LBN 11 2329 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T0_WIDTH 1 2330 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T1_LBN 10 2331 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T1_WIDTH 1 2332 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B0_LBN 9 2333 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B0_WIDTH 1 2334 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B1_LBN 8 2335 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B1_WIDTH 1 2336 /* Test result from FPGA */ 2337 #define MC_CMD_FC_OUT_DDR_TEST_POLL_RESULT_OFST 4 2338 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T0_LBN 31 2339 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T0_WIDTH 1 2340 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T1_LBN 30 2341 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T1_WIDTH 1 2342 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B0_LBN 29 2343 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B0_WIDTH 1 2344 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B1_LBN 28 2345 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B1_WIDTH 1 2346 #define MC_CMD_FC_OUT_DDR_TEST_POLL_T0_LBN 15 2347 #define MC_CMD_FC_OUT_DDR_TEST_POLL_T0_WIDTH 5 2348 #define MC_CMD_FC_OUT_DDR_TEST_POLL_T1_LBN 10 2349 #define MC_CMD_FC_OUT_DDR_TEST_POLL_T1_WIDTH 5 2350 #define MC_CMD_FC_OUT_DDR_TEST_POLL_B0_LBN 5 2351 #define MC_CMD_FC_OUT_DDR_TEST_POLL_B0_WIDTH 5 2352 #define MC_CMD_FC_OUT_DDR_TEST_POLL_B1_LBN 0 2353 #define MC_CMD_FC_OUT_DDR_TEST_POLL_B1_WIDTH 5 2354 #define MC_CMD_FC_OUT_DDR_TEST_POLL_TEST_COMPLETE 0x0 /* enum */ 2355 #define MC_CMD_FC_OUT_DDR_TEST_POLL_TEST_FAIL 0x1 /* enum */ 2356 #define MC_CMD_FC_OUT_DDR_TEST_POLL_TEST_PASS 0x2 /* enum */ 2357 #define MC_CMD_FC_OUT_DDR_TEST_POLL_CAL_FAIL 0x3 /* enum */ 2358 #define MC_CMD_FC_OUT_DDR_TEST_POLL_CAL_SUCCESS 0x4 /* enum */ 2359 2360 /* MC_CMD_FC_OUT_DDR_TEST msgresponse */ 2361 #define MC_CMD_FC_OUT_DDR_TEST_LEN 0 2362 2363 /* MC_CMD_FC_OUT_GET_ASSERT msgresponse */ 2364 #define MC_CMD_FC_OUT_GET_ASSERT_LEN 144 2365 /* Assertion status flag. */ 2366 #define MC_CMD_FC_OUT_GET_ASSERT_GLOBAL_FLAGS_OFST 0 2367 #define MC_CMD_FC_OUT_GET_ASSERT_STATE_LBN 8 2368 #define MC_CMD_FC_OUT_GET_ASSERT_STATE_WIDTH 8 2369 /* enum: No crash data available */ 2370 #define MC_CMD_FC_GET_ASSERT_FLAGS_STATE_CLEAR 0x0 2371 /* enum: New crash data available */ 2372 #define MC_CMD_FC_GET_ASSERT_FLAGS_STATE_NEW 0x1 2373 /* enum: Crash data has been sent */ 2374 #define MC_CMD_FC_GET_ASSERT_FLAGS_STATE_NOTIFIED 0x2 2375 #define MC_CMD_FC_OUT_GET_ASSERT_TYPE_LBN 0 2376 #define MC_CMD_FC_OUT_GET_ASSERT_TYPE_WIDTH 8 2377 /* enum: No crash has been recorded. */ 2378 #define MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_NONE 0x0 2379 /* enum: Crash due to exception. */ 2380 #define MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_EXCEPTION 0x1 2381 /* enum: Crash due to assertion. */ 2382 #define MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_ASSERTION 0x2 2383 /* Failing PC value */ 2384 #define MC_CMD_FC_OUT_GET_ASSERT_SAVED_PC_OFFS_OFST 4 2385 /* Saved GP regs */ 2386 #define MC_CMD_FC_OUT_GET_ASSERT_GP_REGS_OFFS_OFST 8 2387 #define MC_CMD_FC_OUT_GET_ASSERT_GP_REGS_OFFS_LEN 4 2388 #define MC_CMD_FC_OUT_GET_ASSERT_GP_REGS_OFFS_NUM 31 2389 /* Exception Type */ 2390 #define MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_TYPE_OFFS_OFST 132 2391 /* Instruction at which exception occurred */ 2392 #define MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_PC_ADDR_OFFS_OFST 136 2393 /* BAD Address that triggered address-based exception */ 2394 #define MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_BAD_ADDR_OFFS_OFST 140 2395 2396 /* MC_CMD_FC_OUT_FPGA_BUILD msgresponse */ 2397 #define MC_CMD_FC_OUT_FPGA_BUILD_LEN 32 2398 #define MC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_INFO_OFST 0 2399 #define MC_CMD_FC_OUT_FPGA_BUILD_IS_APPLICATION_LBN 31 2400 #define MC_CMD_FC_OUT_FPGA_BUILD_IS_APPLICATION_WIDTH 1 2401 #define MC_CMD_FC_OUT_FPGA_BUILD_IS_LICENSED_LBN 30 2402 #define MC_CMD_FC_OUT_FPGA_BUILD_IS_LICENSED_WIDTH 1 2403 #define MC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_ID_LBN 16 2404 #define MC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_ID_WIDTH 14 2405 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MAJOR_LBN 12 2406 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MAJOR_WIDTH 4 2407 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MINOR_LBN 4 2408 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MINOR_WIDTH 8 2409 #define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_NUM_LBN 0 2410 #define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_NUM_WIDTH 4 2411 /* Build timestamp (seconds since epoch) */ 2412 #define MC_CMD_FC_OUT_FPGA_BUILD_TIMESTAMP_OFST 4 2413 #define MC_CMD_FC_OUT_FPGA_BUILD_PARAMETERS_OFST 8 2414 #define MC_CMD_FC_OUT_FPGA_BUILD_FPGA_TYPE_LBN 0 2415 #define MC_CMD_FC_OUT_FPGA_BUILD_FPGA_TYPE_WIDTH 8 2416 #define MC_CMD_FC_FPGA_TYPE_A7 0xa7 /* enum */ 2417 #define MC_CMD_FC_FPGA_TYPE_A5 0xa5 /* enum */ 2418 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED1_LBN 8 2419 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED1_WIDTH 10 2420 #define MC_CMD_FC_OUT_FPGA_BUILD_PTP_ENABLED_LBN 18 2421 #define MC_CMD_FC_OUT_FPGA_BUILD_PTP_ENABLED_WIDTH 1 2422 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM1_RLDRAM_DEF_LBN 19 2423 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM1_RLDRAM_DEF_WIDTH 1 2424 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM2_RLDRAM_DEF_LBN 20 2425 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM2_RLDRAM_DEF_WIDTH 1 2426 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM3_RLDRAM_DEF_LBN 21 2427 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM3_RLDRAM_DEF_WIDTH 1 2428 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM4_RLDRAM_DEF_LBN 22 2429 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM4_RLDRAM_DEF_WIDTH 1 2430 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T0_DDR3_DEF_LBN 23 2431 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T0_DDR3_DEF_WIDTH 1 2432 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_DDR3_DEF_LBN 24 2433 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_DDR3_DEF_WIDTH 1 2434 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B0_DDR3_DEF_LBN 25 2435 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B0_DDR3_DEF_WIDTH 1 2436 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B1_DDR3_DEF_LBN 26 2437 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B1_DDR3_DEF_WIDTH 1 2438 #define MC_CMD_FC_OUT_FPGA_BUILD_DDR3_ECC_ENABLED_LBN 27 2439 #define MC_CMD_FC_OUT_FPGA_BUILD_DDR3_ECC_ENABLED_WIDTH 1 2440 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_QDR_DEF_LBN 28 2441 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_QDR_DEF_WIDTH 1 2442 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED2_LBN 29 2443 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED2_WIDTH 2 2444 #define MC_CMD_FC_OUT_FPGA_BUILD_CRC_APPEND_LBN 31 2445 #define MC_CMD_FC_OUT_FPGA_BUILD_CRC_APPEND_WIDTH 1 2446 #define MC_CMD_FC_OUT_FPGA_BUILD_IDENTIFIER_OFST 12 2447 #define MC_CMD_FC_OUT_FPGA_BUILD_CHANGESET_LBN 0 2448 #define MC_CMD_FC_OUT_FPGA_BUILD_CHANGESET_WIDTH 16 2449 #define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_FLAG_LBN 16 2450 #define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_FLAG_WIDTH 1 2451 #define MC_CMD_FC_FPGA_BUILD_FLAG_INTERNAL 0x0 /* enum */ 2452 #define MC_CMD_FC_FPGA_BUILD_FLAG_RELEASE 0x1 /* enum */ 2453 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED3_LBN 17 2454 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED3_WIDTH 15 2455 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_HI_OFST 16 2456 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MINOR_LBN 0 2457 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MINOR_WIDTH 16 2458 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MAJOR_LBN 16 2459 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MAJOR_WIDTH 16 2460 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_LO_OFST 20 2461 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_BUILD_LBN 0 2462 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_BUILD_WIDTH 16 2463 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MICRO_LBN 16 2464 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MICRO_WIDTH 16 2465 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_OFST 16 2466 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_LEN 8 2467 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_LO_OFST 16 2468 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_HI_OFST 20 2469 #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_LO_OFST 24 2470 #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HI_OFST 28 2471 #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HIGH_LBN 0 2472 #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HIGH_WIDTH 16 2473 2474 /* MC_CMD_FC_OUT_FPGA_BUILD_V2 msgresponse */ 2475 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_LEN 32 2476 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_INFO_OFST 0 2477 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_APPLICATION_LBN 31 2478 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_APPLICATION_WIDTH 1 2479 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_LICENSED_LBN 30 2480 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_LICENSED_WIDTH 1 2481 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_ID_LBN 16 2482 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_ID_WIDTH 14 2483 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MAJOR_LBN 12 2484 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MAJOR_WIDTH 4 2485 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MINOR_LBN 4 2486 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MINOR_WIDTH 8 2487 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_NUM_LBN 0 2488 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_NUM_WIDTH 4 2489 /* Build timestamp (seconds since epoch) */ 2490 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_TIMESTAMP_OFST 4 2491 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_PARAMETERS_OFST 8 2492 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_PMA_PASSTHROUGH_LBN 31 2493 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_PMA_PASSTHROUGH_WIDTH 1 2494 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_QDR_DEF_LBN 29 2495 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_QDR_DEF_WIDTH 1 2496 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_QDR_DEF_LBN 28 2497 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_QDR_DEF_WIDTH 1 2498 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DDR3_ECC_ENABLED_LBN 27 2499 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DDR3_ECC_ENABLED_WIDTH 1 2500 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_DDR3_DEF_LBN 26 2501 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_DDR3_DEF_WIDTH 1 2502 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_DDR3_DEF_LBN 25 2503 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_DDR3_DEF_WIDTH 1 2504 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_TO_DDR3_DEF_LBN 24 2505 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_TO_DDR3_DEF_WIDTH 1 2506 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_T0_DDR3_DEF_LBN 23 2507 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_T0_DDR3_DEF_WIDTH 1 2508 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_RLDRAM_DEF_LBN 22 2509 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_RLDRAM_DEF_WIDTH 1 2510 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_RLDRAM_DEF_LBN 21 2511 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_RLDRAM_DEF_WIDTH 1 2512 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_RLDRAM_DEF_LBN 20 2513 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_RLDRAM_DEF_WIDTH 1 2514 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_RLDRAM_DEF_LBN 19 2515 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_RLDRAM_DEF_WIDTH 1 2516 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_LBN 18 2517 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_WIDTH 1 2518 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_10G 0x0 /* enum */ 2519 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_40G 0x1 /* enum */ 2520 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_LBN 17 2521 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_WIDTH 1 2522 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_10G 0x0 /* enum */ 2523 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_40G 0x1 /* enum */ 2524 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_LBN 16 2525 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_WIDTH 1 2526 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_10G 0x0 /* enum */ 2527 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_40G 0x1 /* enum */ 2528 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP7_DEF_LBN 15 2529 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP7_DEF_WIDTH 1 2530 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP6_DEF_LBN 14 2531 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP6_DEF_WIDTH 1 2532 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP5_DEF_LBN 13 2533 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP5_DEF_WIDTH 1 2534 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_DEF_LBN 12 2535 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_DEF_WIDTH 1 2536 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP3_DEF_LBN 11 2537 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP3_DEF_WIDTH 1 2538 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP2_DEF_LBN 10 2539 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP2_DEF_WIDTH 1 2540 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP1_DEF_LBN 9 2541 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP1_DEF_WIDTH 1 2542 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_DEF_LBN 8 2543 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_DEF_WIDTH 1 2544 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC3_DEF_LBN 7 2545 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC3_DEF_WIDTH 1 2546 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC2_DEF_LBN 6 2547 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC2_DEF_WIDTH 1 2548 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC1_DEF_LBN 5 2549 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC1_DEF_WIDTH 1 2550 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_DEF_LBN 4 2551 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_DEF_WIDTH 1 2552 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_FPGA_TYPE_LBN 0 2553 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_FPGA_TYPE_WIDTH 4 2554 #define MC_CMD_FC_FPGA_V2_TYPE_A3 0x0 /* enum */ 2555 #define MC_CMD_FC_FPGA_V2_TYPE_A4 0x1 /* enum */ 2556 #define MC_CMD_FC_FPGA_V2_TYPE_A5 0x2 /* enum */ 2557 #define MC_CMD_FC_FPGA_V2_TYPE_A7 0x3 /* enum */ 2558 #define MC_CMD_FC_FPGA_V2_TYPE_D3 0x8 /* enum */ 2559 #define MC_CMD_FC_FPGA_V2_TYPE_D4 0x9 /* enum */ 2560 #define MC_CMD_FC_FPGA_V2_TYPE_D5 0xa /* enum */ 2561 #define MC_CMD_FC_FPGA_V2_TYPE_D7 0xb /* enum */ 2562 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_IDENTIFIER_OFST 12 2563 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_CHANGESET_LBN 0 2564 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_CHANGESET_WIDTH 16 2565 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_FLAG_LBN 16 2566 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_FLAG_WIDTH 1 2567 /* MC_CMD_FC_FPGA_BUILD_FLAG_INTERNAL 0x0 */ 2568 /* MC_CMD_FC_FPGA_BUILD_FLAG_RELEASE 0x1 */ 2569 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_HI_OFST 16 2570 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MINOR_LBN 0 2571 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MINOR_WIDTH 16 2572 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MAJOR_LBN 16 2573 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MAJOR_WIDTH 16 2574 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_LO_OFST 20 2575 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_BUILD_LBN 0 2576 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_BUILD_WIDTH 16 2577 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MICRO_LBN 16 2578 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MICRO_WIDTH 16 2579 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_LO_OFST 24 2580 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HI_OFST 28 2581 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HIGH_LBN 0 2582 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HIGH_WIDTH 16 2583 2584 /* MC_CMD_FC_OUT_FPGA_SERVICES msgresponse */ 2585 #define MC_CMD_FC_OUT_FPGA_SERVICES_LEN 32 2586 #define MC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_INFO_OFST 0 2587 #define MC_CMD_FC_OUT_FPGA_SERVICES_IS_APPLICATION_LBN 31 2588 #define MC_CMD_FC_OUT_FPGA_SERVICES_IS_APPLICATION_WIDTH 1 2589 #define MC_CMD_FC_OUT_FPGA_SERVICES_IS_LICENSED_LBN 30 2590 #define MC_CMD_FC_OUT_FPGA_SERVICES_IS_LICENSED_WIDTH 1 2591 #define MC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_ID_LBN 16 2592 #define MC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_ID_WIDTH 14 2593 #define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MAJOR_LBN 12 2594 #define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MAJOR_WIDTH 4 2595 #define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MINOR_LBN 4 2596 #define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MINOR_WIDTH 8 2597 #define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_NUM_LBN 0 2598 #define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_NUM_WIDTH 4 2599 /* Build timestamp (seconds since epoch) */ 2600 #define MC_CMD_FC_OUT_FPGA_SERVICES_TIMESTAMP_OFST 4 2601 #define MC_CMD_FC_OUT_FPGA_SERVICES_PARAMETERS_OFST 8 2602 #define MC_CMD_FC_OUT_FPGA_SERVICES_FC_FLASH_BOOTED_LBN 8 2603 #define MC_CMD_FC_OUT_FPGA_SERVICES_FC_FLASH_BOOTED_WIDTH 1 2604 #define MC_CMD_FC_OUT_FPGA_SERVICES_NIC0_DEF_LBN 27 2605 #define MC_CMD_FC_OUT_FPGA_SERVICES_NIC0_DEF_WIDTH 1 2606 #define MC_CMD_FC_OUT_FPGA_SERVICES_NIC1_DEF_LBN 28 2607 #define MC_CMD_FC_OUT_FPGA_SERVICES_NIC1_DEF_WIDTH 1 2608 #define MC_CMD_FC_OUT_FPGA_SERVICES_SFP0_DEF_LBN 29 2609 #define MC_CMD_FC_OUT_FPGA_SERVICES_SFP0_DEF_WIDTH 1 2610 #define MC_CMD_FC_OUT_FPGA_SERVICES_SFP1_DEF_LBN 30 2611 #define MC_CMD_FC_OUT_FPGA_SERVICES_SFP1_DEF_WIDTH 1 2612 #define MC_CMD_FC_OUT_FPGA_SERVICES_RESERVED_LBN 31 2613 #define MC_CMD_FC_OUT_FPGA_SERVICES_RESERVED_WIDTH 1 2614 #define MC_CMD_FC_OUT_FPGA_SERVICES_IDENTIFIER_OFST 12 2615 #define MC_CMD_FC_OUT_FPGA_SERVICES_CHANGESET_LBN 0 2616 #define MC_CMD_FC_OUT_FPGA_SERVICES_CHANGESET_WIDTH 16 2617 #define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_FLAG_LBN 16 2618 #define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_FLAG_WIDTH 1 2619 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_OFST 16 2620 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_WIDTH_LBN 0 2621 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_WIDTH_WIDTH 16 2622 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_COUNT_LBN 16 2623 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_COUNT_WIDTH 16 2624 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_OFST 20 2625 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_WIDTH_LBN 0 2626 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_WIDTH_WIDTH 16 2627 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_COUNT_LBN 16 2628 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_COUNT_WIDTH 16 2629 #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_LO_OFST 24 2630 #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HI_OFST 28 2631 #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HIGH_LBN 0 2632 #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HIGH_WIDTH 16 2633 2634 /* MC_CMD_FC_OUT_FPGA_SERVICES_V2 msgresponse */ 2635 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_LEN 32 2636 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_INFO_OFST 0 2637 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_APPLICATION_LBN 31 2638 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_APPLICATION_WIDTH 1 2639 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_LICENSED_LBN 30 2640 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_LICENSED_WIDTH 1 2641 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_ID_LBN 16 2642 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_ID_WIDTH 14 2643 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MAJOR_LBN 12 2644 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MAJOR_WIDTH 4 2645 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MINOR_LBN 4 2646 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MINOR_WIDTH 8 2647 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_NUM_LBN 0 2648 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_NUM_WIDTH 4 2649 /* Build timestamp (seconds since epoch) */ 2650 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_TIMESTAMP_OFST 4 2651 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_PARAMETERS_OFST 8 2652 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_PTP_ENABLED_LBN 0 2653 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_PTP_ENABLED_WIDTH 1 2654 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_FC_FLASH_BOOTED_LBN 8 2655 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_FC_FLASH_BOOTED_WIDTH 1 2656 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IDENTIFIER_OFST 12 2657 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_CHANGESET_LBN 0 2658 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_CHANGESET_WIDTH 16 2659 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_FLAG_LBN 16 2660 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_FLAG_WIDTH 1 2661 /* MC_CMD_FC_FPGA_BUILD_FLAG_INTERNAL 0x0 */ 2662 /* MC_CMD_FC_FPGA_BUILD_FLAG_RELEASE 0x1 */ 2663 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_LO_OFST 24 2664 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HI_OFST 28 2665 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HIGH_LBN 0 2666 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HIGH_WIDTH 16 2667 2668 /* MC_CMD_FC_OUT_BSP_VERSION msgresponse */ 2669 #define MC_CMD_FC_OUT_BSP_VERSION_LEN 4 2670 /* Qsys system ID */ 2671 #define MC_CMD_FC_OUT_BSP_VERSION_SYSID_OFST 0 2672 #define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MAJOR_LBN 12 2673 #define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MAJOR_WIDTH 4 2674 #define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MINOR_LBN 4 2675 #define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MINOR_WIDTH 8 2676 #define MC_CMD_FC_OUT_BSP_VERSION_BUILD_NUM_LBN 0 2677 #define MC_CMD_FC_OUT_BSP_VERSION_BUILD_NUM_WIDTH 4 2678 2679 /* MC_CMD_FC_OUT_READ_MAP_COUNT msgresponse */ 2680 #define MC_CMD_FC_OUT_READ_MAP_COUNT_LEN 4 2681 /* Number of maps */ 2682 #define MC_CMD_FC_OUT_READ_MAP_COUNT_NUM_MAPS_OFST 0 2683 2684 /* MC_CMD_FC_OUT_READ_MAP_INDEX msgresponse */ 2685 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN 164 2686 /* Index of the map */ 2687 #define MC_CMD_FC_OUT_READ_MAP_INDEX_INDEX_OFST 0 2688 /* Options for the map */ 2689 #define MC_CMD_FC_OUT_READ_MAP_INDEX_OPTIONS_OFST 4 2690 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_8 0x0 /* enum */ 2691 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_16 0x1 /* enum */ 2692 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_32 0x2 /* enum */ 2693 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_64 0x3 /* enum */ 2694 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_MASK 0x3 /* enum */ 2695 #define MC_CMD_FC_OUT_READ_MAP_INDEX_PATH_FC 0x4 /* enum */ 2696 #define MC_CMD_FC_OUT_READ_MAP_INDEX_PATH_MEM 0x8 /* enum */ 2697 #define MC_CMD_FC_OUT_READ_MAP_INDEX_PERM_READ 0x10 /* enum */ 2698 #define MC_CMD_FC_OUT_READ_MAP_INDEX_PERM_WRITE 0x20 /* enum */ 2699 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_FREE 0x0 /* enum */ 2700 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_LICENSED 0x40 /* enum */ 2701 /* Address of start of map */ 2702 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_OFST 8 2703 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_LEN 8 2704 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_LO_OFST 8 2705 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_HI_OFST 12 2706 /* Length of address map */ 2707 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_OFST 16 2708 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_LEN 8 2709 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_LO_OFST 16 2710 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_HI_OFST 20 2711 /* Component information field */ 2712 #define MC_CMD_FC_OUT_READ_MAP_INDEX_COMP_INFO_OFST 24 2713 /* License expiry data for map */ 2714 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_OFST 28 2715 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_LEN 8 2716 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_LO_OFST 28 2717 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_HI_OFST 32 2718 /* Name of the component */ 2719 #define MC_CMD_FC_OUT_READ_MAP_INDEX_NAME_OFST 36 2720 #define MC_CMD_FC_OUT_READ_MAP_INDEX_NAME_LEN 1 2721 #define MC_CMD_FC_OUT_READ_MAP_INDEX_NAME_NUM 128 2722 2723 /* MC_CMD_FC_OUT_READ_MAP msgresponse */ 2724 #define MC_CMD_FC_OUT_READ_MAP_LEN 0 2725 2726 /* MC_CMD_FC_OUT_CAPABILITIES msgresponse */ 2727 #define MC_CMD_FC_OUT_CAPABILITIES_LEN 8 2728 /* Number of internal ports */ 2729 #define MC_CMD_FC_OUT_CAPABILITIES_INTERNAL_OFST 0 2730 /* Number of external ports */ 2731 #define MC_CMD_FC_OUT_CAPABILITIES_EXTERNAL_OFST 4 2732 2733 /* MC_CMD_FC_OUT_GLOBAL_FLAGS msgresponse */ 2734 #define MC_CMD_FC_OUT_GLOBAL_FLAGS_LEN 4 2735 #define MC_CMD_FC_OUT_GLOBAL_FLAGS_FLAGS_OFST 0 2736 2737 /* MC_CMD_FC_OUT_IO_REL msgresponse */ 2738 #define MC_CMD_FC_OUT_IO_REL_LEN 0 2739 2740 /* MC_CMD_FC_OUT_IO_REL_GET_ADDR msgresponse */ 2741 #define MC_CMD_FC_OUT_IO_REL_GET_ADDR_LEN 8 2742 #define MC_CMD_FC_OUT_IO_REL_GET_ADDR_ADDR_HI_OFST 0 2743 #define MC_CMD_FC_OUT_IO_REL_GET_ADDR_ADDR_LO_OFST 4 2744 2745 /* MC_CMD_FC_OUT_IO_REL_READ32 msgresponse */ 2746 #define MC_CMD_FC_OUT_IO_REL_READ32_LENMIN 4 2747 #define MC_CMD_FC_OUT_IO_REL_READ32_LENMAX 252 2748 #define MC_CMD_FC_OUT_IO_REL_READ32_LEN(num) (0+4*(num)) 2749 #define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_OFST 0 2750 #define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_LEN 4 2751 #define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_MINNUM 1 2752 #define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_MAXNUM 63 2753 2754 /* MC_CMD_FC_OUT_IO_REL_WRITE32 msgresponse */ 2755 #define MC_CMD_FC_OUT_IO_REL_WRITE32_LEN 0 2756 2757 /* MC_CMD_FC_OUT_UHLINK_PHY msgresponse */ 2758 #define MC_CMD_FC_OUT_UHLINK_PHY_LEN 48 2759 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_SETTINGS_0_OFST 0 2760 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_VOD_LBN 0 2761 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_VOD_WIDTH 16 2762 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_1STPOSTTAP_LBN 16 2763 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_1STPOSTTAP_WIDTH 16 2764 /* Transceiver Transmit settings */ 2765 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_SETTINGS_1_OFST 4 2766 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_PRETAP_LBN 0 2767 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_PRETAP_WIDTH 16 2768 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_2NDPOSTTAP_LBN 16 2769 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_2NDPOSTTAP_WIDTH 16 2770 /* Transceiver Receive settings */ 2771 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_SETTINGS_OFST 8 2772 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_DC_GAIN_LBN 0 2773 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_DC_GAIN_WIDTH 16 2774 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_EQ_CONTROL_LBN 16 2775 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_EQ_CONTROL_WIDTH 16 2776 /* Rx eye opening */ 2777 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_OFST 12 2778 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_WIDTH_LBN 0 2779 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_WIDTH_WIDTH 16 2780 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_HEIGHT_LBN 16 2781 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_HEIGHT_WIDTH 16 2782 /* PCS status word */ 2783 #define MC_CMD_FC_OUT_UHLINK_PHY_PCS_STATUS_OFST 16 2784 /* Link status word */ 2785 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_WORD_OFST 20 2786 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_LBN 0 2787 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_WIDTH 1 2788 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_CONFIGURED_LBN 1 2789 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_CONFIGURED_WIDTH 1 2790 /* Current SFp parameters applied */ 2791 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_PARAMS_OFST 24 2792 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_PARAMS_LEN 20 2793 /* Link speed is 100, 1000, 10000 */ 2794 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_SPEED_OFST 24 2795 /* Length of copper cable - zero when not relevant */ 2796 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_COPPER_LEN_OFST 28 2797 /* True if a dual speed SFP+ module */ 2798 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_DUAL_SPEED_OFST 32 2799 /* True if an SFP Module is present (other fields valid when true) */ 2800 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_PRESENT_OFST 36 2801 /* The type of the SFP+ Module */ 2802 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_TYPE_OFST 40 2803 /* PHY config flags */ 2804 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_OFST 44 2805 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_DFE_LBN 0 2806 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_DFE_WIDTH 1 2807 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_AEQ_LBN 1 2808 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_AEQ_WIDTH 1 2809 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_RX_TUNING_LBN 2 2810 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_RX_TUNING_WIDTH 1 2811 2812 /* MC_CMD_FC_OUT_UHLINK_MAC msgresponse */ 2813 #define MC_CMD_FC_OUT_UHLINK_MAC_LEN 20 2814 /* MAC configuration applied */ 2815 #define MC_CMD_FC_OUT_UHLINK_MAC_CONFIG_OFST 0 2816 /* MTU size */ 2817 #define MC_CMD_FC_OUT_UHLINK_MAC_MTU_OFST 4 2818 /* IF Mode status */ 2819 #define MC_CMD_FC_OUT_UHLINK_MAC_IF_STATUS_OFST 8 2820 /* MAC address configured */ 2821 #define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_OFST 12 2822 #define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_LEN 8 2823 #define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_LO_OFST 12 2824 #define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_HI_OFST 16 2825 2826 /* MC_CMD_FC_OUT_UHLINK_RX_EYE msgresponse */ 2827 #define MC_CMD_FC_OUT_UHLINK_RX_EYE_LEN ((((0-1+(32*MC_CMD_FC_UHLINK_RX_EYE_PER_BLOCK))+1))>>3) 2828 /* Rx Eye measurements */ 2829 #define MC_CMD_FC_OUT_UHLINK_RX_EYE_RX_EYE_OFST 0 2830 #define MC_CMD_FC_OUT_UHLINK_RX_EYE_RX_EYE_LEN 4 2831 #define MC_CMD_FC_OUT_UHLINK_RX_EYE_RX_EYE_NUM MC_CMD_FC_UHLINK_RX_EYE_PER_BLOCK 2832 2833 /* MC_CMD_FC_OUT_UHLINK_DUMP_RX_EYE_PLOT msgresponse */ 2834 #define MC_CMD_FC_OUT_UHLINK_DUMP_RX_EYE_PLOT_LEN 0 2835 2836 /* MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT msgresponse */ 2837 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_LEN ((((32-1+(64*MC_CMD_FC_UHLINK_RX_EYE_PLOT_ROWS_PER_BLOCK))+1))>>3) 2838 /* Has the eye plot dump completed and data returned is valid? */ 2839 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_VALID_OFST 0 2840 /* Rx Eye binary plot */ 2841 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_OFST 4 2842 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_LEN 8 2843 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_LO_OFST 4 2844 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_HI_OFST 8 2845 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_NUM MC_CMD_FC_UHLINK_RX_EYE_PLOT_ROWS_PER_BLOCK 2846 2847 /* MC_CMD_FC_OUT_UHLINK_RX_TUNE msgresponse */ 2848 #define MC_CMD_FC_OUT_UHLINK_RX_TUNE_LEN 0 2849 2850 /* MC_CMD_FC_OUT_UHLINK_LOOPBACK_SET msgresponse */ 2851 #define MC_CMD_FC_OUT_UHLINK_LOOPBACK_SET_LEN 0 2852 2853 /* MC_CMD_FC_OUT_UHLINK_LOOPBACK_GET msgresponse */ 2854 #define MC_CMD_FC_OUT_UHLINK_LOOPBACK_GET_LEN 4 2855 #define MC_CMD_FC_OUT_UHLINK_LOOPBACK_GET_STATE_OFST 0 2856 2857 /* MC_CMD_FC_OUT_UHLINK msgresponse */ 2858 #define MC_CMD_FC_OUT_UHLINK_LEN 0 2859 2860 /* MC_CMD_FC_OUT_SET_LINK msgresponse */ 2861 #define MC_CMD_FC_OUT_SET_LINK_LEN 0 2862 2863 /* MC_CMD_FC_OUT_LICENSE msgresponse */ 2864 #define MC_CMD_FC_OUT_LICENSE_LEN 12 2865 /* Count of valid keys */ 2866 #define MC_CMD_FC_OUT_LICENSE_VALID_KEYS_OFST 0 2867 /* Count of invalid keys */ 2868 #define MC_CMD_FC_OUT_LICENSE_INVALID_KEYS_OFST 4 2869 /* Count of blacklisted keys */ 2870 #define MC_CMD_FC_OUT_LICENSE_BLACKLISTED_KEYS_OFST 8 2871 2872 /* MC_CMD_FC_OUT_STARTUP msgresponse */ 2873 #define MC_CMD_FC_OUT_STARTUP_LEN 4 2874 /* Capabilities of the FPGA/FC */ 2875 #define MC_CMD_FC_OUT_STARTUP_CAPABILITIES_OFST 0 2876 #define MC_CMD_FC_OUT_STARTUP_CAN_ACCESS_FLASH_LBN 0 2877 #define MC_CMD_FC_OUT_STARTUP_CAN_ACCESS_FLASH_WIDTH 1 2878 2879 /* MC_CMD_FC_OUT_DMA_READ msgresponse */ 2880 #define MC_CMD_FC_OUT_DMA_READ_LENMIN 1 2881 #define MC_CMD_FC_OUT_DMA_READ_LENMAX 252 2882 #define MC_CMD_FC_OUT_DMA_READ_LEN(num) (0+1*(num)) 2883 /* The data read */ 2884 #define MC_CMD_FC_OUT_DMA_READ_DATA_OFST 0 2885 #define MC_CMD_FC_OUT_DMA_READ_DATA_LEN 1 2886 #define MC_CMD_FC_OUT_DMA_READ_DATA_MINNUM 1 2887 #define MC_CMD_FC_OUT_DMA_READ_DATA_MAXNUM 252 2888 2889 /* MC_CMD_FC_OUT_TIMED_READ_SET msgresponse */ 2890 #define MC_CMD_FC_OUT_TIMED_READ_SET_LEN 4 2891 /* Timer handle */ 2892 #define MC_CMD_FC_OUT_TIMED_READ_SET_FC_HANDLE_OFST 0 2893 2894 /* MC_CMD_FC_OUT_TIMED_READ_GET msgresponse */ 2895 #define MC_CMD_FC_OUT_TIMED_READ_GET_LEN 52 2896 /* Host supplied handle (unique) */ 2897 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_HANDLE_OFST 0 2898 /* Address into which to transfer data in host */ 2899 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_OFST 4 2900 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_LEN 8 2901 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_LO_OFST 4 2902 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_HI_OFST 8 2903 /* AOE address from which to transfer data */ 2904 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_OFST 12 2905 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_LEN 8 2906 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_LO_OFST 12 2907 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_HI_OFST 16 2908 /* Length of AOE transfer (total) */ 2909 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_LENGTH_OFST 20 2910 /* Length of host transfer (total) */ 2911 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_LENGTH_OFST 24 2912 /* See FLAGS entry for MC_CMD_FC_IN_TIMED_READ_SET */ 2913 #define MC_CMD_FC_OUT_TIMED_READ_GET_FLAGS_OFST 28 2914 #define MC_CMD_FC_OUT_TIMED_READ_GET_PERIOD_OFST 32 2915 /* When active, start read time */ 2916 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_OFST 36 2917 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_LEN 8 2918 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_LO_OFST 36 2919 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_HI_OFST 40 2920 /* When active, end read time */ 2921 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_OFST 44 2922 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_LEN 8 2923 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_LO_OFST 44 2924 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_HI_OFST 48 2925 2926 /* MC_CMD_FC_OUT_LOG_ADDR_RANGE msgresponse */ 2927 #define MC_CMD_FC_OUT_LOG_ADDR_RANGE_LEN 0 2928 2929 /* MC_CMD_FC_OUT_LOG msgresponse */ 2930 #define MC_CMD_FC_OUT_LOG_LEN 0 2931 2932 /* MC_CMD_FC_OUT_CLOCK_GET_TIME msgresponse */ 2933 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_LEN 24 2934 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_CLOCK_ID_OFST 0 2935 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_OFST 4 2936 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_LEN 8 2937 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_LO_OFST 4 2938 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_HI_OFST 8 2939 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_NANOSECONDS_OFST 12 2940 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_RANGE_OFST 16 2941 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_PRECISION_OFST 20 2942 2943 /* MC_CMD_FC_OUT_CLOCK_SET_TIME msgresponse */ 2944 #define MC_CMD_FC_OUT_CLOCK_SET_TIME_LEN 0 2945 2946 /* MC_CMD_FC_OUT_DDR_SET_SPD msgresponse */ 2947 #define MC_CMD_FC_OUT_DDR_SET_SPD_LEN 0 2948 2949 /* MC_CMD_FC_OUT_DDR_SET_INFO msgresponse */ 2950 #define MC_CMD_FC_OUT_DDR_SET_INFO_LEN 0 2951 2952 /* MC_CMD_FC_OUT_DDR_GET_STATUS msgresponse */ 2953 #define MC_CMD_FC_OUT_DDR_GET_STATUS_LEN 4 2954 #define MC_CMD_FC_OUT_DDR_GET_STATUS_FLAGS_OFST 0 2955 #define MC_CMD_FC_OUT_DDR_GET_STATUS_READY_LBN 0 2956 #define MC_CMD_FC_OUT_DDR_GET_STATUS_READY_WIDTH 1 2957 #define MC_CMD_FC_OUT_DDR_GET_STATUS_CALIBRATED_LBN 1 2958 #define MC_CMD_FC_OUT_DDR_GET_STATUS_CALIBRATED_WIDTH 1 2959 2960 /* MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT msgresponse */ 2961 #define MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_LEN 8 2962 #define MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_SECONDS_OFST 0 2963 #define MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_NANOSECONDS_OFST 4 2964 2965 /* MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT msgresponse */ 2966 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LENMIN 8 2967 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LENMAX 248 2968 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LEN(num) (0+8*(num)) 2969 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_SECONDS_OFST 0 2970 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_NANOSECONDS_OFST 4 2971 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_OFST 0 2972 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_LEN 8 2973 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_LO_OFST 0 2974 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_HI_OFST 4 2975 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_MINNUM 0 2976 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_MAXNUM 31 2977 2978 /* MC_CMD_FC_OUT_SPI_READ msgresponse */ 2979 #define MC_CMD_FC_OUT_SPI_READ_LENMIN 4 2980 #define MC_CMD_FC_OUT_SPI_READ_LENMAX 252 2981 #define MC_CMD_FC_OUT_SPI_READ_LEN(num) (0+4*(num)) 2982 #define MC_CMD_FC_OUT_SPI_READ_BUFFER_OFST 0 2983 #define MC_CMD_FC_OUT_SPI_READ_BUFFER_LEN 4 2984 #define MC_CMD_FC_OUT_SPI_READ_BUFFER_MINNUM 1 2985 #define MC_CMD_FC_OUT_SPI_READ_BUFFER_MAXNUM 63 2986 2987 /* MC_CMD_FC_OUT_SPI_WRITE msgresponse */ 2988 #define MC_CMD_FC_OUT_SPI_WRITE_LEN 0 2989 2990 /* MC_CMD_FC_OUT_SPI_ERASE msgresponse */ 2991 #define MC_CMD_FC_OUT_SPI_ERASE_LEN 0 2992 2993 /* MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG msgresponse */ 2994 #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_LEN 8 2995 /* The 32-bit value read from the toggle count register */ 2996 #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_TOGGLE_COUNT_OFST 0 2997 /* The 32-bit value read from the clock enable count register */ 2998 #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_CLKEN_COUNT_OFST 4 2999 3000 /* MC_CMD_FC_OUT_DIAG_POWER_NOISE_WRITE_CONFIG msgresponse */ 3001 #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_WRITE_CONFIG_LEN 0 3002 3003 /* MC_CMD_FC_OUT_DIAG_DDR_SOAK_START msgresponse */ 3004 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_START_LEN 0 3005 3006 /* MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT msgresponse */ 3007 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_LEN 8 3008 /* DDR soak test status word; bits [4:0] are relevant. */ 3009 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_STATUS_OFST 0 3010 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PASSED_LBN 0 3011 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PASSED_WIDTH 1 3012 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_FAILED_LBN 1 3013 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_FAILED_WIDTH 1 3014 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_COMPLETED_LBN 2 3015 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_COMPLETED_WIDTH 1 3016 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_TIMEOUT_LBN 3 3017 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_TIMEOUT_WIDTH 1 3018 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PNF_LBN 4 3019 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PNF_WIDTH 1 3020 /* DDR soak test error count */ 3021 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_ERR_COUNT_OFST 4 3022 3023 /* MC_CMD_FC_OUT_DIAG_DDR_SOAK_STOP msgresponse */ 3024 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_STOP_LEN 0 3025 3026 /* MC_CMD_FC_OUT_DIAG_DDR_SOAK_ERROR msgresponse */ 3027 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_ERROR_LEN 0 3028 3029 /* MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_SET_MODE msgresponse */ 3030 #define MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_SET_MODE_LEN 0 3031 3032 /* MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_RAW_CONFIG msgresponse */ 3033 #define MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_RAW_CONFIG_LEN 0 3034 3035 3036 /***********************************/ 3037 /* MC_CMD_AOE 3038 * AOE operations on MC 3039 */ 3040 #define MC_CMD_AOE 0xa 3041 3042 /* MC_CMD_AOE_IN msgrequest */ 3043 #define MC_CMD_AOE_IN_LEN 4 3044 #define MC_CMD_AOE_IN_OP_HDR_OFST 0 3045 #define MC_CMD_AOE_IN_OP_LBN 0 3046 #define MC_CMD_AOE_IN_OP_WIDTH 8 3047 /* enum: FPGA and CPLD information */ 3048 #define MC_CMD_AOE_OP_INFO 0x1 3049 /* enum: Currents and voltages read from MCP3424s; DEBUG */ 3050 #define MC_CMD_AOE_OP_CURRENTS 0x2 3051 /* enum: Temperatures at locations around the PCB; DEBUG */ 3052 #define MC_CMD_AOE_OP_TEMPERATURES 0x3 3053 /* enum: Set CPLD to idle */ 3054 #define MC_CMD_AOE_OP_CPLD_IDLE 0x4 3055 /* enum: Read from CPLD register */ 3056 #define MC_CMD_AOE_OP_CPLD_READ 0x5 3057 /* enum: Write to CPLD register */ 3058 #define MC_CMD_AOE_OP_CPLD_WRITE 0x6 3059 /* enum: Execute CPLD instruction */ 3060 #define MC_CMD_AOE_OP_CPLD_INSTRUCTION 0x7 3061 /* enum: Reprogram the CPLD on the AOE device */ 3062 #define MC_CMD_AOE_OP_CPLD_REPROGRAM 0x8 3063 /* enum: AOE power control */ 3064 #define MC_CMD_AOE_OP_POWER 0x9 3065 /* enum: AOE image loading */ 3066 #define MC_CMD_AOE_OP_LOAD 0xa 3067 /* enum: Fan monitoring */ 3068 #define MC_CMD_AOE_OP_FAN_CONTROL 0xb 3069 /* enum: Fan failures since last reset */ 3070 #define MC_CMD_AOE_OP_FAN_FAILURES 0xc 3071 /* enum: Get generic AOE MAC statistics */ 3072 #define MC_CMD_AOE_OP_MAC_STATS 0xd 3073 /* enum: Retrieve PHY specific information */ 3074 #define MC_CMD_AOE_OP_GET_PHY_MEDIA_INFO 0xe 3075 /* enum: Write a number of JTAG primitive commands, return will give data */ 3076 #define MC_CMD_AOE_OP_JTAG_WRITE 0xf 3077 /* enum: Control access to the FPGA via the Siena JTAG Chain */ 3078 #define MC_CMD_AOE_OP_FPGA_ACCESS 0x10 3079 /* enum: Set the MTU offset between Siena and AOE MACs */ 3080 #define MC_CMD_AOE_OP_SET_MTU_OFFSET 0x11 3081 /* enum: How link state is handled */ 3082 #define MC_CMD_AOE_OP_LINK_STATE 0x12 3083 /* enum: How Siena MAC statistics are reported (deprecated - use 3084 * MC_CMD_AOE_OP_ASIC_STATS) 3085 */ 3086 #define MC_CMD_AOE_OP_SIENA_STATS 0x13 3087 /* enum: How native ASIC MAC statistics are reported - replaces the deprecated 3088 * command MC_CMD_AOE_OP_SIENA_STATS 3089 */ 3090 #define MC_CMD_AOE_OP_ASIC_STATS 0x13 3091 /* enum: DDR memory information */ 3092 #define MC_CMD_AOE_OP_DDR 0x14 3093 /* enum: FC control */ 3094 #define MC_CMD_AOE_OP_FC 0x15 3095 /* enum: DDR ECC status reads */ 3096 #define MC_CMD_AOE_OP_DDR_ECC_STATUS 0x16 3097 /* enum: Commands for MC-SPI Master emulation */ 3098 #define MC_CMD_AOE_OP_MC_SPI_MASTER 0x17 3099 /* enum: Commands for FC boot control */ 3100 #define MC_CMD_AOE_OP_FC_BOOT 0x18 3101 3102 /* MC_CMD_AOE_OUT msgresponse */ 3103 #define MC_CMD_AOE_OUT_LEN 0 3104 3105 /* MC_CMD_AOE_IN_INFO msgrequest */ 3106 #define MC_CMD_AOE_IN_INFO_LEN 4 3107 #define MC_CMD_AOE_IN_CMD_OFST 0 3108 3109 /* MC_CMD_AOE_IN_CURRENTS msgrequest */ 3110 #define MC_CMD_AOE_IN_CURRENTS_LEN 4 3111 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3112 3113 /* MC_CMD_AOE_IN_TEMPERATURES msgrequest */ 3114 #define MC_CMD_AOE_IN_TEMPERATURES_LEN 4 3115 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3116 3117 /* MC_CMD_AOE_IN_CPLD_IDLE msgrequest */ 3118 #define MC_CMD_AOE_IN_CPLD_IDLE_LEN 4 3119 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3120 3121 /* MC_CMD_AOE_IN_CPLD_READ msgrequest */ 3122 #define MC_CMD_AOE_IN_CPLD_READ_LEN 12 3123 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3124 #define MC_CMD_AOE_IN_CPLD_READ_REGISTER_OFST 4 3125 #define MC_CMD_AOE_IN_CPLD_READ_WIDTH_OFST 8 3126 3127 /* MC_CMD_AOE_IN_CPLD_WRITE msgrequest */ 3128 #define MC_CMD_AOE_IN_CPLD_WRITE_LEN 16 3129 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3130 #define MC_CMD_AOE_IN_CPLD_WRITE_REGISTER_OFST 4 3131 #define MC_CMD_AOE_IN_CPLD_WRITE_WIDTH_OFST 8 3132 #define MC_CMD_AOE_IN_CPLD_WRITE_VALUE_OFST 12 3133 3134 /* MC_CMD_AOE_IN_CPLD_INSTRUCTION msgrequest */ 3135 #define MC_CMD_AOE_IN_CPLD_INSTRUCTION_LEN 8 3136 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3137 #define MC_CMD_AOE_IN_CPLD_INSTRUCTION_INSTRUCTION_OFST 4 3138 3139 /* MC_CMD_AOE_IN_CPLD_REPROGRAM msgrequest */ 3140 #define MC_CMD_AOE_IN_CPLD_REPROGRAM_LEN 8 3141 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3142 #define MC_CMD_AOE_IN_CPLD_REPROGRAM_OP_OFST 4 3143 /* enum: Reprogram CPLD, poll for completion */ 3144 #define MC_CMD_AOE_IN_CPLD_REPROGRAM_REPROGRAM 0x1 3145 /* enum: Reprogram CPLD, send event on completion */ 3146 #define MC_CMD_AOE_IN_CPLD_REPROGRAM_REPROGRAM_EVENT 0x3 3147 /* enum: Get status of reprogramming operation */ 3148 #define MC_CMD_AOE_IN_CPLD_REPROGRAM_STATUS 0x4 3149 3150 /* MC_CMD_AOE_IN_POWER msgrequest */ 3151 #define MC_CMD_AOE_IN_POWER_LEN 8 3152 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3153 /* Turn on or off AOE power */ 3154 #define MC_CMD_AOE_IN_POWER_OP_OFST 4 3155 /* enum: Turn off FPGA power */ 3156 #define MC_CMD_AOE_IN_POWER_OFF 0x0 3157 /* enum: Turn on FPGA power */ 3158 #define MC_CMD_AOE_IN_POWER_ON 0x1 3159 /* enum: Clear peak power measurement */ 3160 #define MC_CMD_AOE_IN_POWER_CLEAR 0x2 3161 /* enum: Show current power in sensors output */ 3162 #define MC_CMD_AOE_IN_POWER_SHOW_CURRENT 0x3 3163 /* enum: Show peak power in sensors output */ 3164 #define MC_CMD_AOE_IN_POWER_SHOW_PEAK 0x4 3165 /* enum: Show current DDR current */ 3166 #define MC_CMD_AOE_IN_POWER_DDR_LAST 0x5 3167 /* enum: Show peak DDR current */ 3168 #define MC_CMD_AOE_IN_POWER_DDR_PEAK 0x6 3169 /* enum: Clear peak DDR current */ 3170 #define MC_CMD_AOE_IN_POWER_DDR_CLEAR 0x7 3171 3172 /* MC_CMD_AOE_IN_LOAD msgrequest */ 3173 #define MC_CMD_AOE_IN_LOAD_LEN 8 3174 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3175 /* Image to be loaded (0 - main or 1 - diagnostic) to load in normal sequence 3176 */ 3177 #define MC_CMD_AOE_IN_LOAD_IMAGE_OFST 4 3178 3179 /* MC_CMD_AOE_IN_FAN_CONTROL msgrequest */ 3180 #define MC_CMD_AOE_IN_FAN_CONTROL_LEN 8 3181 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3182 /* If non zero report measured fan RPM rather than nominal */ 3183 #define MC_CMD_AOE_IN_FAN_CONTROL_REAL_RPM_OFST 4 3184 3185 /* MC_CMD_AOE_IN_FAN_FAILURES msgrequest */ 3186 #define MC_CMD_AOE_IN_FAN_FAILURES_LEN 4 3187 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3188 3189 /* MC_CMD_AOE_IN_MAC_STATS msgrequest */ 3190 #define MC_CMD_AOE_IN_MAC_STATS_LEN 24 3191 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3192 /* AOE port */ 3193 #define MC_CMD_AOE_IN_MAC_STATS_PORT_OFST 4 3194 /* Host memory address for statistics */ 3195 #define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_OFST 8 3196 #define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_LEN 8 3197 #define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_LO_OFST 8 3198 #define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_HI_OFST 12 3199 #define MC_CMD_AOE_IN_MAC_STATS_CMD_OFST 16 3200 #define MC_CMD_AOE_IN_MAC_STATS_DMA_LBN 0 3201 #define MC_CMD_AOE_IN_MAC_STATS_DMA_WIDTH 1 3202 #define MC_CMD_AOE_IN_MAC_STATS_CLEAR_LBN 1 3203 #define MC_CMD_AOE_IN_MAC_STATS_CLEAR_WIDTH 1 3204 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CHANGE_LBN 2 3205 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CHANGE_WIDTH 1 3206 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_ENABLE_LBN 3 3207 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_ENABLE_WIDTH 1 3208 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CLEAR_LBN 4 3209 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CLEAR_WIDTH 1 3210 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_NOEVENT_LBN 5 3211 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_NOEVENT_WIDTH 1 3212 #define MC_CMD_AOE_IN_MAC_STATS_PERIOD_MS_LBN 16 3213 #define MC_CMD_AOE_IN_MAC_STATS_PERIOD_MS_WIDTH 16 3214 /* Length of DMA data (optional) */ 3215 #define MC_CMD_AOE_IN_MAC_STATS_DMA_LEN_OFST 20 3216 3217 /* MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO msgrequest */ 3218 #define MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_LEN 12 3219 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3220 /* AOE port */ 3221 #define MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_PORT_OFST 4 3222 #define MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_PAGE_OFST 8 3223 3224 /* MC_CMD_AOE_IN_JTAG_WRITE msgrequest */ 3225 #define MC_CMD_AOE_IN_JTAG_WRITE_LENMIN 12 3226 #define MC_CMD_AOE_IN_JTAG_WRITE_LENMAX 252 3227 #define MC_CMD_AOE_IN_JTAG_WRITE_LEN(num) (8+4*(num)) 3228 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3229 #define MC_CMD_AOE_IN_JTAG_WRITE_DATALEN_OFST 4 3230 #define MC_CMD_AOE_IN_JTAG_WRITE_DATA_OFST 8 3231 #define MC_CMD_AOE_IN_JTAG_WRITE_DATA_LEN 4 3232 #define MC_CMD_AOE_IN_JTAG_WRITE_DATA_MINNUM 1 3233 #define MC_CMD_AOE_IN_JTAG_WRITE_DATA_MAXNUM 61 3234 3235 /* MC_CMD_AOE_IN_FPGA_ACCESS msgrequest */ 3236 #define MC_CMD_AOE_IN_FPGA_ACCESS_LEN 8 3237 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3238 /* Enable or disable access */ 3239 #define MC_CMD_AOE_IN_FPGA_ACCESS_OP_OFST 4 3240 /* enum: Enable access */ 3241 #define MC_CMD_AOE_IN_FPGA_ACCESS_ENABLE 0x1 3242 /* enum: Disable access */ 3243 #define MC_CMD_AOE_IN_FPGA_ACCESS_DISABLE 0x2 3244 3245 /* MC_CMD_AOE_IN_SET_MTU_OFFSET msgrequest */ 3246 #define MC_CMD_AOE_IN_SET_MTU_OFFSET_LEN 12 3247 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3248 /* AOE port - when not ALL_EXTERNAL or ALL_INTERNAL specifies port number */ 3249 #define MC_CMD_AOE_IN_SET_MTU_OFFSET_PORT_OFST 4 3250 /* enum: Apply to all external ports */ 3251 #define MC_CMD_AOE_IN_SET_MTU_OFFSET_ALL_EXTERNAL 0x8000 3252 /* enum: Apply to all internal ports */ 3253 #define MC_CMD_AOE_IN_SET_MTU_OFFSET_ALL_INTERNAL 0x4000 3254 /* The MTU offset to be applied to the external ports */ 3255 #define MC_CMD_AOE_IN_SET_MTU_OFFSET_OFFSET_OFST 8 3256 3257 /* MC_CMD_AOE_IN_LINK_STATE msgrequest */ 3258 #define MC_CMD_AOE_IN_LINK_STATE_LEN 8 3259 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3260 #define MC_CMD_AOE_IN_LINK_STATE_MODE_OFST 4 3261 #define MC_CMD_AOE_IN_LINK_STATE_CONFIG_MODE_LBN 0 3262 #define MC_CMD_AOE_IN_LINK_STATE_CONFIG_MODE_WIDTH 8 3263 /* enum: AOE and associated external port */ 3264 #define MC_CMD_AOE_IN_LINK_STATE_SIMPLE_SEPARATE 0x0 3265 /* enum: AOE and OR of all external ports */ 3266 #define MC_CMD_AOE_IN_LINK_STATE_SIMPLE_COMBINED 0x1 3267 /* enum: Individual ports */ 3268 #define MC_CMD_AOE_IN_LINK_STATE_DIAGNOSTIC 0x2 3269 /* enum: Configure link state mode on given AOE port */ 3270 #define MC_CMD_AOE_IN_LINK_STATE_CUSTOM 0x3 3271 #define MC_CMD_AOE_IN_LINK_STATE_OPERATION_LBN 8 3272 #define MC_CMD_AOE_IN_LINK_STATE_OPERATION_WIDTH 8 3273 /* enum: No-op */ 3274 #define MC_CMD_AOE_IN_LINK_STATE_OP_NONE 0x0 3275 /* enum: logical OR of all SFP ports link status */ 3276 #define MC_CMD_AOE_IN_LINK_STATE_OP_OR 0x1 3277 /* enum: logical AND of all SFP ports link status */ 3278 #define MC_CMD_AOE_IN_LINK_STATE_OP_AND 0x2 3279 #define MC_CMD_AOE_IN_LINK_STATE_SFP_MASK_LBN 16 3280 #define MC_CMD_AOE_IN_LINK_STATE_SFP_MASK_WIDTH 16 3281 3282 /* MC_CMD_AOE_IN_SIENA_STATS msgrequest */ 3283 #define MC_CMD_AOE_IN_SIENA_STATS_LEN 8 3284 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3285 /* How MAC statistics are reported */ 3286 #define MC_CMD_AOE_IN_SIENA_STATS_MODE_OFST 4 3287 /* enum: Statistics from Siena (default) */ 3288 #define MC_CMD_AOE_IN_SIENA_STATS_STATS_SIENA 0x0 3289 /* enum: Statistics from AOE external ports */ 3290 #define MC_CMD_AOE_IN_SIENA_STATS_STATS_AOE 0x1 3291 3292 /* MC_CMD_AOE_IN_ASIC_STATS msgrequest */ 3293 #define MC_CMD_AOE_IN_ASIC_STATS_LEN 8 3294 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3295 /* How MAC statistics are reported */ 3296 #define MC_CMD_AOE_IN_ASIC_STATS_MODE_OFST 4 3297 /* enum: Statistics from the ASIC (default) */ 3298 #define MC_CMD_AOE_IN_ASIC_STATS_STATS_ASIC 0x0 3299 /* enum: Statistics from AOE external ports */ 3300 #define MC_CMD_AOE_IN_ASIC_STATS_STATS_AOE 0x1 3301 3302 /* MC_CMD_AOE_IN_DDR msgrequest */ 3303 #define MC_CMD_AOE_IN_DDR_LEN 12 3304 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3305 #define MC_CMD_AOE_IN_DDR_BANK_OFST 4 3306 /* Enum values, see field(s): */ 3307 /* MC_CMD_FC/MC_CMD_FC_IN_DDR/MC_CMD_FC_IN_DDR_BANK */ 3308 /* Page index of SPD data */ 3309 #define MC_CMD_AOE_IN_DDR_SPD_PAGE_ID_OFST 8 3310 3311 /* MC_CMD_AOE_IN_FC msgrequest */ 3312 #define MC_CMD_AOE_IN_FC_LEN 4 3313 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3314 3315 /* MC_CMD_AOE_IN_DDR_ECC_STATUS msgrequest */ 3316 #define MC_CMD_AOE_IN_DDR_ECC_STATUS_LEN 8 3317 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3318 #define MC_CMD_AOE_IN_DDR_ECC_STATUS_BANK_OFST 4 3319 /* Enum values, see field(s): */ 3320 /* MC_CMD_FC/MC_CMD_FC_IN_DDR/MC_CMD_FC_IN_DDR_BANK */ 3321 3322 /* MC_CMD_AOE_IN_MC_SPI_MASTER msgrequest */ 3323 #define MC_CMD_AOE_IN_MC_SPI_MASTER_LEN 8 3324 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3325 /* Basic commands for MC SPI Master emulation. */ 3326 #define MC_CMD_AOE_IN_MC_SPI_MASTER_OP_OFST 4 3327 /* enum: MC SPI read */ 3328 #define MC_CMD_AOE_IN_MC_SPI_MASTER_READ 0x0 3329 /* enum: MC SPI write */ 3330 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE 0x1 3331 3332 /* MC_CMD_AOE_IN_MC_SPI_MASTER_READ msgrequest */ 3333 #define MC_CMD_AOE_IN_MC_SPI_MASTER_READ_LEN 12 3334 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3335 #define MC_CMD_AOE_IN_MC_SPI_MASTER_READ_OP_OFST 4 3336 #define MC_CMD_AOE_IN_MC_SPI_MASTER_READ_OFFSET_OFST 8 3337 3338 /* MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE msgrequest */ 3339 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_LEN 16 3340 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3341 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_OP_OFST 4 3342 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_OFFSET_OFST 8 3343 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_DATA_OFST 12 3344 3345 /* MC_CMD_AOE_IN_FC_BOOT msgrequest */ 3346 #define MC_CMD_AOE_IN_FC_BOOT_LEN 8 3347 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3348 /* FC boot control flags */ 3349 #define MC_CMD_AOE_IN_FC_BOOT_CONTROL_OFST 4 3350 #define MC_CMD_AOE_IN_FC_BOOT_CONTROL_BOOT_ENABLE_LBN 0 3351 #define MC_CMD_AOE_IN_FC_BOOT_CONTROL_BOOT_ENABLE_WIDTH 1 3352 3353 /* MC_CMD_AOE_OUT_INFO msgresponse */ 3354 #define MC_CMD_AOE_OUT_INFO_LEN 44 3355 /* JTAG IDCODE of CPLD */ 3356 #define MC_CMD_AOE_OUT_INFO_CPLD_IDCODE_OFST 0 3357 /* Version of CPLD */ 3358 #define MC_CMD_AOE_OUT_INFO_CPLD_VERSION_OFST 4 3359 /* JTAG IDCODE of FPGA */ 3360 #define MC_CMD_AOE_OUT_INFO_FPGA_IDCODE_OFST 8 3361 /* JTAG USERCODE of FPGA */ 3362 #define MC_CMD_AOE_OUT_INFO_FPGA_VERSION_OFST 12 3363 /* FPGA type - read from CPLD straps */ 3364 #define MC_CMD_AOE_OUT_INFO_FPGA_TYPE_OFST 16 3365 #define MC_CMD_AOE_OUT_INFO_FPGA_TYPE_A5_C2 0x1 /* enum */ 3366 #define MC_CMD_AOE_OUT_INFO_FPGA_TYPE_A7_C2 0x2 /* enum */ 3367 /* FPGA state (debug) */ 3368 #define MC_CMD_AOE_OUT_INFO_FPGA_STATE_OFST 20 3369 /* FPGA image - partition from which loaded */ 3370 #define MC_CMD_AOE_OUT_INFO_FPGA_IMAGE_OFST 24 3371 /* FC state */ 3372 #define MC_CMD_AOE_OUT_INFO_FC_STATE_OFST 28 3373 /* enum: Set if watchdog working */ 3374 #define MC_CMD_AOE_OUT_INFO_WATCHDOG 0x1 3375 /* enum: Set if MC-FC communications working */ 3376 #define MC_CMD_AOE_OUT_INFO_COMMS 0x2 3377 /* Random pieces of information */ 3378 #define MC_CMD_AOE_OUT_INFO_FLAGS_OFST 32 3379 /* enum: Power to FPGA supplied by PEG connector, not PCIe bus */ 3380 #define MC_CMD_AOE_OUT_INFO_PEG_POWER 0x1 3381 /* enum: CPLD apparently good */ 3382 #define MC_CMD_AOE_OUT_INFO_CPLD_GOOD 0x2 3383 /* enum: FPGA working normally */ 3384 #define MC_CMD_AOE_OUT_INFO_FPGA_GOOD 0x4 3385 /* enum: FPGA is powered */ 3386 #define MC_CMD_AOE_OUT_INFO_FPGA_POWER 0x8 3387 /* enum: Board has incompatible SODIMMs fitted */ 3388 #define MC_CMD_AOE_OUT_INFO_BAD_SODIMM 0x10 3389 /* enum: Board has ByteBlaster connected */ 3390 #define MC_CMD_AOE_OUT_INFO_HAS_BYTEBLASTER 0x20 3391 /* enum: FPGA Boot flash has an invalid header. */ 3392 #define MC_CMD_AOE_OUT_INFO_FPGA_BAD_BOOT_HDR 0x40 3393 /* enum: FPGA Application flash is accessible. */ 3394 #define MC_CMD_AOE_OUT_INFO_FPGA_APP_FLASH_GOOD 0x80 3395 /* Revision of Modena and Sorrento boards. Sorrento can be R1_2 or R1_3. */ 3396 #define MC_CMD_AOE_OUT_INFO_BOARD_REVISION_OFST 36 3397 #define MC_CMD_AOE_OUT_INFO_UNKNOWN 0x0 /* enum */ 3398 #define MC_CMD_AOE_OUT_INFO_R1_0 0x10 /* enum */ 3399 #define MC_CMD_AOE_OUT_INFO_R1_1 0x11 /* enum */ 3400 #define MC_CMD_AOE_OUT_INFO_R1_2 0x12 /* enum */ 3401 #define MC_CMD_AOE_OUT_INFO_R1_3 0x13 /* enum */ 3402 /* Result of FC booting - not valid while a ByteBlaster is connected. */ 3403 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_RESULT_OFST 40 3404 /* enum: No error */ 3405 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_NO_ERROR 0x0 3406 /* enum: Bad address set in CPLD */ 3407 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_ADDRESS 0x1 3408 /* enum: Bad header */ 3409 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_MAGIC 0x2 3410 /* enum: Bad text section details */ 3411 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_TEXT 0x3 3412 /* enum: Bad checksum */ 3413 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_CHECKSUM 0x4 3414 /* enum: Bad BSP */ 3415 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_BSP 0x5 3416 /* enum: Flash mode is invalid */ 3417 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_INVALID_FLASH_MODE 0x6 3418 /* enum: FC application loaded and execution attempted */ 3419 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_APP_EXECUTE 0x80 3420 /* enum: FC application Started */ 3421 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_APP_STARTED 0x81 3422 /* enum: No bootrom in FPGA */ 3423 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_NO_BOOTROM 0xff 3424 3425 /* MC_CMD_AOE_OUT_CURRENTS msgresponse */ 3426 #define MC_CMD_AOE_OUT_CURRENTS_LEN 68 3427 /* Set of currents and voltages (mA or mV as appropriate) */ 3428 #define MC_CMD_AOE_OUT_CURRENTS_VALUES_OFST 0 3429 #define MC_CMD_AOE_OUT_CURRENTS_VALUES_LEN 4 3430 #define MC_CMD_AOE_OUT_CURRENTS_VALUES_NUM 17 3431 #define MC_CMD_AOE_OUT_CURRENTS_I_2V5 0x0 /* enum */ 3432 #define MC_CMD_AOE_OUT_CURRENTS_I_1V8 0x1 /* enum */ 3433 #define MC_CMD_AOE_OUT_CURRENTS_I_GXB 0x2 /* enum */ 3434 #define MC_CMD_AOE_OUT_CURRENTS_I_PGM 0x3 /* enum */ 3435 #define MC_CMD_AOE_OUT_CURRENTS_I_XCVR 0x4 /* enum */ 3436 #define MC_CMD_AOE_OUT_CURRENTS_I_1V5 0x5 /* enum */ 3437 #define MC_CMD_AOE_OUT_CURRENTS_V_3V3 0x6 /* enum */ 3438 #define MC_CMD_AOE_OUT_CURRENTS_V_1V5 0x7 /* enum */ 3439 #define MC_CMD_AOE_OUT_CURRENTS_I_IN 0x8 /* enum */ 3440 #define MC_CMD_AOE_OUT_CURRENTS_I_OUT 0x9 /* enum */ 3441 #define MC_CMD_AOE_OUT_CURRENTS_V_IN 0xa /* enum */ 3442 #define MC_CMD_AOE_OUT_CURRENTS_I_OUT_DDR1 0xb /* enum */ 3443 #define MC_CMD_AOE_OUT_CURRENTS_V_OUT_DDR1 0xc /* enum */ 3444 #define MC_CMD_AOE_OUT_CURRENTS_I_OUT_DDR2 0xd /* enum */ 3445 #define MC_CMD_AOE_OUT_CURRENTS_V_OUT_DDR2 0xe /* enum */ 3446 #define MC_CMD_AOE_OUT_CURRENTS_I_OUT_DDR3 0xf /* enum */ 3447 #define MC_CMD_AOE_OUT_CURRENTS_V_OUT_DDR3 0x10 /* enum */ 3448 3449 /* MC_CMD_AOE_OUT_TEMPERATURES msgresponse */ 3450 #define MC_CMD_AOE_OUT_TEMPERATURES_LEN 40 3451 /* Set of temperatures */ 3452 #define MC_CMD_AOE_OUT_TEMPERATURES_VALUES_OFST 0 3453 #define MC_CMD_AOE_OUT_TEMPERATURES_VALUES_LEN 4 3454 #define MC_CMD_AOE_OUT_TEMPERATURES_VALUES_NUM 10 3455 /* enum: The first set of enum values are for Modena code. */ 3456 #define MC_CMD_AOE_OUT_TEMPERATURES_MAIN_0 0x0 3457 #define MC_CMD_AOE_OUT_TEMPERATURES_MAIN_1 0x1 /* enum */ 3458 #define MC_CMD_AOE_OUT_TEMPERATURES_IND_0 0x2 /* enum */ 3459 #define MC_CMD_AOE_OUT_TEMPERATURES_IND_1 0x3 /* enum */ 3460 #define MC_CMD_AOE_OUT_TEMPERATURES_VCCIO1 0x4 /* enum */ 3461 #define MC_CMD_AOE_OUT_TEMPERATURES_VCCIO2 0x5 /* enum */ 3462 #define MC_CMD_AOE_OUT_TEMPERATURES_VCCIO3 0x6 /* enum */ 3463 #define MC_CMD_AOE_OUT_TEMPERATURES_PSU 0x7 /* enum */ 3464 #define MC_CMD_AOE_OUT_TEMPERATURES_FPGA 0x8 /* enum */ 3465 #define MC_CMD_AOE_OUT_TEMPERATURES_SIENA 0x9 /* enum */ 3466 /* enum: The second set of enum values are for Sorrento code. */ 3467 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_MAIN_0 0x0 3468 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_MAIN_1 0x1 /* enum */ 3469 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_IND_0 0x2 /* enum */ 3470 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_IND_1 0x3 /* enum */ 3471 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_SODIMM_0 0x4 /* enum */ 3472 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_SODIMM_1 0x5 /* enum */ 3473 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_FPGA 0x6 /* enum */ 3474 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_PHY0 0x7 /* enum */ 3475 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_PHY1 0x8 /* enum */ 3476 3477 /* MC_CMD_AOE_OUT_CPLD_READ msgresponse */ 3478 #define MC_CMD_AOE_OUT_CPLD_READ_LEN 4 3479 /* The value read from the CPLD */ 3480 #define MC_CMD_AOE_OUT_CPLD_READ_VALUE_OFST 0 3481 3482 /* MC_CMD_AOE_OUT_FAN_FAILURES msgresponse */ 3483 #define MC_CMD_AOE_OUT_FAN_FAILURES_LENMIN 4 3484 #define MC_CMD_AOE_OUT_FAN_FAILURES_LENMAX 252 3485 #define MC_CMD_AOE_OUT_FAN_FAILURES_LEN(num) (0+4*(num)) 3486 /* Failure counts for each fan */ 3487 #define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_OFST 0 3488 #define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_LEN 4 3489 #define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_MINNUM 1 3490 #define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_MAXNUM 63 3491 3492 /* MC_CMD_AOE_OUT_CPLD_REPROGRAM msgresponse */ 3493 #define MC_CMD_AOE_OUT_CPLD_REPROGRAM_LEN 4 3494 /* Results of status command (only) */ 3495 #define MC_CMD_AOE_OUT_CPLD_REPROGRAM_STATUS_OFST 0 3496 3497 /* MC_CMD_AOE_OUT_POWER_OFF msgresponse */ 3498 #define MC_CMD_AOE_OUT_POWER_OFF_LEN 0 3499 3500 /* MC_CMD_AOE_OUT_POWER_ON msgresponse */ 3501 #define MC_CMD_AOE_OUT_POWER_ON_LEN 0 3502 3503 /* MC_CMD_AOE_OUT_LOAD msgresponse */ 3504 #define MC_CMD_AOE_OUT_LOAD_LEN 0 3505 3506 /* MC_CMD_AOE_OUT_MAC_STATS_DMA msgresponse */ 3507 #define MC_CMD_AOE_OUT_MAC_STATS_DMA_LEN 0 3508 3509 /* MC_CMD_AOE_OUT_MAC_STATS_NO_DMA msgresponse: See MC_CMD_MAC_STATS_OUT_NO_DMA 3510 * for details 3511 */ 3512 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_LEN (((MC_CMD_MAC_NSTATS*64))>>3) 3513 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_OFST 0 3514 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_LEN 8 3515 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_LO_OFST 0 3516 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_HI_OFST 4 3517 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS 3518 3519 /* MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO msgresponse */ 3520 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LENMIN 5 3521 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LENMAX 252 3522 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LEN(num) (4+1*(num)) 3523 /* in bytes */ 3524 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATALEN_OFST 0 3525 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_OFST 4 3526 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_LEN 1 3527 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_MINNUM 1 3528 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_MAXNUM 248 3529 3530 /* MC_CMD_AOE_OUT_JTAG_WRITE msgresponse */ 3531 #define MC_CMD_AOE_OUT_JTAG_WRITE_LENMIN 12 3532 #define MC_CMD_AOE_OUT_JTAG_WRITE_LENMAX 252 3533 #define MC_CMD_AOE_OUT_JTAG_WRITE_LEN(num) (8+4*(num)) 3534 /* Used to align the in and out data blocks so the MC can re-use the cmd */ 3535 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATALEN_OFST 0 3536 /* out bytes */ 3537 #define MC_CMD_AOE_OUT_JTAG_WRITE_PAD_OFST 4 3538 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_OFST 8 3539 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_LEN 4 3540 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_MINNUM 1 3541 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_MAXNUM 61 3542 3543 /* MC_CMD_AOE_OUT_FPGA_ACCESS msgresponse */ 3544 #define MC_CMD_AOE_OUT_FPGA_ACCESS_LEN 0 3545 3546 /* MC_CMD_AOE_OUT_DDR msgresponse */ 3547 #define MC_CMD_AOE_OUT_DDR_LENMIN 17 3548 #define MC_CMD_AOE_OUT_DDR_LENMAX 252 3549 #define MC_CMD_AOE_OUT_DDR_LEN(num) (16+1*(num)) 3550 /* Information on the module. */ 3551 #define MC_CMD_AOE_OUT_DDR_FLAGS_OFST 0 3552 #define MC_CMD_AOE_OUT_DDR_PRESENT_LBN 0 3553 #define MC_CMD_AOE_OUT_DDR_PRESENT_WIDTH 1 3554 #define MC_CMD_AOE_OUT_DDR_POWERED_LBN 1 3555 #define MC_CMD_AOE_OUT_DDR_POWERED_WIDTH 1 3556 #define MC_CMD_AOE_OUT_DDR_OPERATIONAL_LBN 2 3557 #define MC_CMD_AOE_OUT_DDR_OPERATIONAL_WIDTH 1 3558 #define MC_CMD_AOE_OUT_DDR_NOT_REACHABLE_LBN 3 3559 #define MC_CMD_AOE_OUT_DDR_NOT_REACHABLE_WIDTH 1 3560 /* Memory size, in MB. */ 3561 #define MC_CMD_AOE_OUT_DDR_CAPACITY_OFST 4 3562 /* The memory type, as reported from SPD information */ 3563 #define MC_CMD_AOE_OUT_DDR_TYPE_OFST 8 3564 /* Nominal voltage of the module (as applied) */ 3565 #define MC_CMD_AOE_OUT_DDR_VOLTAGE_OFST 12 3566 /* SPD data read from the module */ 3567 #define MC_CMD_AOE_OUT_DDR_SPD_OFST 16 3568 #define MC_CMD_AOE_OUT_DDR_SPD_LEN 1 3569 #define MC_CMD_AOE_OUT_DDR_SPD_MINNUM 1 3570 #define MC_CMD_AOE_OUT_DDR_SPD_MAXNUM 236 3571 3572 /* MC_CMD_AOE_OUT_SET_MTU_OFFSET msgresponse */ 3573 #define MC_CMD_AOE_OUT_SET_MTU_OFFSET_LEN 0 3574 3575 /* MC_CMD_AOE_OUT_LINK_STATE msgresponse */ 3576 #define MC_CMD_AOE_OUT_LINK_STATE_LEN 0 3577 3578 /* MC_CMD_AOE_OUT_SIENA_STATS msgresponse */ 3579 #define MC_CMD_AOE_OUT_SIENA_STATS_LEN 0 3580 3581 /* MC_CMD_AOE_OUT_ASIC_STATS msgresponse */ 3582 #define MC_CMD_AOE_OUT_ASIC_STATS_LEN 0 3583 3584 /* MC_CMD_AOE_OUT_FC msgresponse */ 3585 #define MC_CMD_AOE_OUT_FC_LEN 0 3586 3587 /* MC_CMD_AOE_OUT_DDR_ECC_STATUS msgresponse */ 3588 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_LEN 8 3589 /* Flags describing status info on the module. */ 3590 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_FLAGS_OFST 0 3591 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_VALID_LBN 0 3592 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_VALID_WIDTH 1 3593 /* DDR ECC status on the module. */ 3594 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_STATUS_OFST 4 3595 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_LBN 0 3596 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_WIDTH 1 3597 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_LBN 1 3598 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_WIDTH 1 3599 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_LBN 2 3600 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_WIDTH 1 3601 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_COUNT_LBN 8 3602 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_COUNT_WIDTH 8 3603 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_COUNT_LBN 16 3604 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_COUNT_WIDTH 8 3605 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_COUNT_LBN 24 3606 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_COUNT_WIDTH 8 3607 3608 /* MC_CMD_AOE_OUT_MC_SPI_MASTER_READ msgresponse */ 3609 #define MC_CMD_AOE_OUT_MC_SPI_MASTER_READ_LEN 4 3610 #define MC_CMD_AOE_OUT_MC_SPI_MASTER_READ_DATA_OFST 0 3611 3612 /* MC_CMD_AOE_OUT_MC_SPI_MASTER_WRITE msgresponse */ 3613 #define MC_CMD_AOE_OUT_MC_SPI_MASTER_WRITE_LEN 0 3614 3615 /* MC_CMD_AOE_OUT_MC_SPI_MASTER msgresponse */ 3616 #define MC_CMD_AOE_OUT_MC_SPI_MASTER_LEN 0 3617 3618 /* MC_CMD_AOE_OUT_FC_BOOT msgresponse */ 3619 #define MC_CMD_AOE_OUT_FC_BOOT_LEN 0 3620 3621 3622 /***********************************/ 3623 /* MC_CMD_PTP 3624 * Perform PTP operation 3625 */ 3626 #define MC_CMD_PTP 0xb 3627 #undef MC_CMD_0xb_PRIVILEGE_CTG 3628 3629 #define MC_CMD_0xb_PRIVILEGE_CTG SRIOV_CTG_GENERAL 3630 3631 /* MC_CMD_PTP_IN msgrequest */ 3632 #define MC_CMD_PTP_IN_LEN 1 3633 /* PTP operation code */ 3634 #define MC_CMD_PTP_IN_OP_OFST 0 3635 #define MC_CMD_PTP_IN_OP_LEN 1 3636 /* enum: Enable PTP packet timestamping operation. */ 3637 #define MC_CMD_PTP_OP_ENABLE 0x1 3638 /* enum: Disable PTP packet timestamping operation. */ 3639 #define MC_CMD_PTP_OP_DISABLE 0x2 3640 /* enum: Send a PTP packet. */ 3641 #define MC_CMD_PTP_OP_TRANSMIT 0x3 3642 /* enum: Read the current NIC time. */ 3643 #define MC_CMD_PTP_OP_READ_NIC_TIME 0x4 3644 /* enum: Get the current PTP status. */ 3645 #define MC_CMD_PTP_OP_STATUS 0x5 3646 /* enum: Adjust the PTP NIC's time. */ 3647 #define MC_CMD_PTP_OP_ADJUST 0x6 3648 /* enum: Synchronize host and NIC time. */ 3649 #define MC_CMD_PTP_OP_SYNCHRONIZE 0x7 3650 /* enum: Basic manufacturing tests. */ 3651 #define MC_CMD_PTP_OP_MANFTEST_BASIC 0x8 3652 /* enum: Packet based manufacturing tests. */ 3653 #define MC_CMD_PTP_OP_MANFTEST_PACKET 0x9 3654 /* enum: Reset some of the PTP related statistics */ 3655 #define MC_CMD_PTP_OP_RESET_STATS 0xa 3656 /* enum: Debug operations to MC. */ 3657 #define MC_CMD_PTP_OP_DEBUG 0xb 3658 /* enum: Read an FPGA register */ 3659 #define MC_CMD_PTP_OP_FPGAREAD 0xc 3660 /* enum: Write an FPGA register */ 3661 #define MC_CMD_PTP_OP_FPGAWRITE 0xd 3662 /* enum: Apply an offset to the NIC clock */ 3663 #define MC_CMD_PTP_OP_CLOCK_OFFSET_ADJUST 0xe 3664 /* enum: Change Apply an offset to the NIC clock */ 3665 #define MC_CMD_PTP_OP_CLOCK_FREQ_ADJUST 0xf 3666 /* enum: Set the MC packet filter VLAN tags for received PTP packets */ 3667 #define MC_CMD_PTP_OP_RX_SET_VLAN_FILTER 0x10 3668 /* enum: Set the MC packet filter UUID for received PTP packets */ 3669 #define MC_CMD_PTP_OP_RX_SET_UUID_FILTER 0x11 3670 /* enum: Set the MC packet filter Domain for received PTP packets */ 3671 #define MC_CMD_PTP_OP_RX_SET_DOMAIN_FILTER 0x12 3672 /* enum: Set the clock source */ 3673 #define MC_CMD_PTP_OP_SET_CLK_SRC 0x13 3674 /* enum: Reset value of Timer Reg. */ 3675 #define MC_CMD_PTP_OP_RST_CLK 0x14 3676 /* enum: Enable the forwarding of PPS events to the host */ 3677 #define MC_CMD_PTP_OP_PPS_ENABLE 0x15 3678 /* enum: Get the time format used by this NIC for PTP operations */ 3679 #define MC_CMD_PTP_OP_GET_TIME_FORMAT 0x16 3680 /* enum: Get the clock attributes. NOTE- extended version of 3681 * MC_CMD_PTP_OP_GET_TIME_FORMAT 3682 */ 3683 #define MC_CMD_PTP_OP_GET_ATTRIBUTES 0x16 3684 /* enum: Get corrections that should be applied to the various different 3685 * timestamps 3686 */ 3687 #define MC_CMD_PTP_OP_GET_TIMESTAMP_CORRECTIONS 0x17 3688 /* enum: Subscribe to receive periodic time events indicating the current NIC 3689 * time 3690 */ 3691 #define MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE 0x18 3692 /* enum: Unsubscribe to stop receiving time events */ 3693 #define MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE 0x19 3694 /* enum: PPS based manfacturing tests. Requires PPS output to be looped to PPS 3695 * input on the same NIC. 3696 */ 3697 #define MC_CMD_PTP_OP_MANFTEST_PPS 0x1a 3698 /* enum: Set the PTP sync status. Status is used by firmware to report to event 3699 * subscribers. 3700 */ 3701 #define MC_CMD_PTP_OP_SET_SYNC_STATUS 0x1b 3702 /* enum: Above this for future use. */ 3703 #define MC_CMD_PTP_OP_MAX 0x1c 3704 3705 /* MC_CMD_PTP_IN_ENABLE msgrequest */ 3706 #define MC_CMD_PTP_IN_ENABLE_LEN 16 3707 #define MC_CMD_PTP_IN_CMD_OFST 0 3708 #define MC_CMD_PTP_IN_PERIPH_ID_OFST 4 3709 /* Event queue for PTP events */ 3710 #define MC_CMD_PTP_IN_ENABLE_QUEUE_OFST 8 3711 /* PTP timestamping mode */ 3712 #define MC_CMD_PTP_IN_ENABLE_MODE_OFST 12 3713 /* enum: PTP, version 1 */ 3714 #define MC_CMD_PTP_MODE_V1 0x0 3715 /* enum: PTP, version 1, with VLAN headers - deprecated */ 3716 #define MC_CMD_PTP_MODE_V1_VLAN 0x1 3717 /* enum: PTP, version 2 */ 3718 #define MC_CMD_PTP_MODE_V2 0x2 3719 /* enum: PTP, version 2, with VLAN headers - deprecated */ 3720 #define MC_CMD_PTP_MODE_V2_VLAN 0x3 3721 /* enum: PTP, version 2, with improved UUID filtering */ 3722 #define MC_CMD_PTP_MODE_V2_ENHANCED 0x4 3723 /* enum: FCoE (seconds and microseconds) */ 3724 #define MC_CMD_PTP_MODE_FCOE 0x5 3725 3726 /* MC_CMD_PTP_IN_DISABLE msgrequest */ 3727 #define MC_CMD_PTP_IN_DISABLE_LEN 8 3728 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3729 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3730 3731 /* MC_CMD_PTP_IN_TRANSMIT msgrequest */ 3732 #define MC_CMD_PTP_IN_TRANSMIT_LENMIN 13 3733 #define MC_CMD_PTP_IN_TRANSMIT_LENMAX 252 3734 #define MC_CMD_PTP_IN_TRANSMIT_LEN(num) (12+1*(num)) 3735 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3736 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3737 /* Transmit packet length */ 3738 #define MC_CMD_PTP_IN_TRANSMIT_LENGTH_OFST 8 3739 /* Transmit packet data */ 3740 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_OFST 12 3741 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_LEN 1 3742 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_MINNUM 1 3743 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_MAXNUM 240 3744 3745 /* MC_CMD_PTP_IN_READ_NIC_TIME msgrequest */ 3746 #define MC_CMD_PTP_IN_READ_NIC_TIME_LEN 8 3747 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3748 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3749 3750 /* MC_CMD_PTP_IN_STATUS msgrequest */ 3751 #define MC_CMD_PTP_IN_STATUS_LEN 8 3752 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3753 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3754 3755 /* MC_CMD_PTP_IN_ADJUST msgrequest */ 3756 #define MC_CMD_PTP_IN_ADJUST_LEN 24 3757 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3758 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3759 /* Frequency adjustment 40 bit fixed point ns */ 3760 #define MC_CMD_PTP_IN_ADJUST_FREQ_OFST 8 3761 #define MC_CMD_PTP_IN_ADJUST_FREQ_LEN 8 3762 #define MC_CMD_PTP_IN_ADJUST_FREQ_LO_OFST 8 3763 #define MC_CMD_PTP_IN_ADJUST_FREQ_HI_OFST 12 3764 /* enum: Number of fractional bits in frequency adjustment */ 3765 #define MC_CMD_PTP_IN_ADJUST_BITS 0x28 3766 /* Time adjustment in seconds */ 3767 #define MC_CMD_PTP_IN_ADJUST_SECONDS_OFST 16 3768 /* Time adjustment major value */ 3769 #define MC_CMD_PTP_IN_ADJUST_MAJOR_OFST 16 3770 /* Time adjustment in nanoseconds */ 3771 #define MC_CMD_PTP_IN_ADJUST_NANOSECONDS_OFST 20 3772 /* Time adjustment minor value */ 3773 #define MC_CMD_PTP_IN_ADJUST_MINOR_OFST 20 3774 3775 /* MC_CMD_PTP_IN_SYNCHRONIZE msgrequest */ 3776 #define MC_CMD_PTP_IN_SYNCHRONIZE_LEN 20 3777 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3778 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3779 /* Number of time readings to capture */ 3780 #define MC_CMD_PTP_IN_SYNCHRONIZE_NUMTIMESETS_OFST 8 3781 /* Host address in which to write "synchronization started" indication (64 3782 * bits) 3783 */ 3784 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_OFST 12 3785 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LEN 8 3786 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LO_OFST 12 3787 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_HI_OFST 16 3788 3789 /* MC_CMD_PTP_IN_MANFTEST_BASIC msgrequest */ 3790 #define MC_CMD_PTP_IN_MANFTEST_BASIC_LEN 8 3791 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3792 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3793 3794 /* MC_CMD_PTP_IN_MANFTEST_PACKET msgrequest */ 3795 #define MC_CMD_PTP_IN_MANFTEST_PACKET_LEN 12 3796 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3797 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3798 /* Enable or disable packet testing */ 3799 #define MC_CMD_PTP_IN_MANFTEST_PACKET_TEST_ENABLE_OFST 8 3800 3801 /* MC_CMD_PTP_IN_RESET_STATS msgrequest */ 3802 #define MC_CMD_PTP_IN_RESET_STATS_LEN 8 3803 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3804 /* Reset PTP statistics */ 3805 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3806 3807 /* MC_CMD_PTP_IN_DEBUG msgrequest */ 3808 #define MC_CMD_PTP_IN_DEBUG_LEN 12 3809 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3810 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3811 /* Debug operations */ 3812 #define MC_CMD_PTP_IN_DEBUG_DEBUG_PARAM_OFST 8 3813 3814 /* MC_CMD_PTP_IN_FPGAREAD msgrequest */ 3815 #define MC_CMD_PTP_IN_FPGAREAD_LEN 16 3816 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3817 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3818 #define MC_CMD_PTP_IN_FPGAREAD_ADDR_OFST 8 3819 #define MC_CMD_PTP_IN_FPGAREAD_NUMBYTES_OFST 12 3820 3821 /* MC_CMD_PTP_IN_FPGAWRITE msgrequest */ 3822 #define MC_CMD_PTP_IN_FPGAWRITE_LENMIN 13 3823 #define MC_CMD_PTP_IN_FPGAWRITE_LENMAX 252 3824 #define MC_CMD_PTP_IN_FPGAWRITE_LEN(num) (12+1*(num)) 3825 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3826 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3827 #define MC_CMD_PTP_IN_FPGAWRITE_ADDR_OFST 8 3828 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_OFST 12 3829 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_LEN 1 3830 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MINNUM 1 3831 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MAXNUM 240 3832 3833 /* MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST msgrequest */ 3834 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_LEN 16 3835 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3836 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3837 /* Time adjustment in seconds */ 3838 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_SECONDS_OFST 8 3839 /* Time adjustment major value */ 3840 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MAJOR_OFST 8 3841 /* Time adjustment in nanoseconds */ 3842 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_NANOSECONDS_OFST 12 3843 /* Time adjustment minor value */ 3844 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MINOR_OFST 12 3845 3846 /* MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST msgrequest */ 3847 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_LEN 16 3848 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3849 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3850 /* Frequency adjustment 40 bit fixed point ns */ 3851 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_OFST 8 3852 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LEN 8 3853 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LO_OFST 8 3854 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_HI_OFST 12 3855 /* enum: Number of fractional bits in frequency adjustment */ 3856 /* MC_CMD_PTP_IN_ADJUST_BITS 0x28 */ 3857 3858 /* MC_CMD_PTP_IN_RX_SET_VLAN_FILTER msgrequest */ 3859 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_LEN 24 3860 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3861 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3862 /* Number of VLAN tags, 0 if not VLAN */ 3863 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_NUM_VLAN_TAGS_OFST 8 3864 /* Set of VLAN tags to filter against */ 3865 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_OFST 12 3866 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_LEN 4 3867 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_NUM 3 3868 3869 /* MC_CMD_PTP_IN_RX_SET_UUID_FILTER msgrequest */ 3870 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_LEN 20 3871 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3872 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3873 /* 1 to enable UUID filtering, 0 to disable */ 3874 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_ENABLE_OFST 8 3875 /* UUID to filter against */ 3876 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_OFST 12 3877 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LEN 8 3878 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LO_OFST 12 3879 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_HI_OFST 16 3880 3881 /* MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER msgrequest */ 3882 #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_LEN 16 3883 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3884 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3885 /* 1 to enable Domain filtering, 0 to disable */ 3886 #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_ENABLE_OFST 8 3887 /* Domain number to filter against */ 3888 #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_DOMAIN_OFST 12 3889 3890 /* MC_CMD_PTP_IN_SET_CLK_SRC msgrequest */ 3891 #define MC_CMD_PTP_IN_SET_CLK_SRC_LEN 12 3892 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3893 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3894 /* Set the clock source. */ 3895 #define MC_CMD_PTP_IN_SET_CLK_SRC_CLK_OFST 8 3896 /* enum: Internal. */ 3897 #define MC_CMD_PTP_CLK_SRC_INTERNAL 0x0 3898 /* enum: External. */ 3899 #define MC_CMD_PTP_CLK_SRC_EXTERNAL 0x1 3900 3901 /* MC_CMD_PTP_IN_RST_CLK msgrequest */ 3902 #define MC_CMD_PTP_IN_RST_CLK_LEN 8 3903 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3904 /* Reset value of Timer Reg. */ 3905 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3906 3907 /* MC_CMD_PTP_IN_PPS_ENABLE msgrequest */ 3908 #define MC_CMD_PTP_IN_PPS_ENABLE_LEN 12 3909 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3910 /* Enable or disable */ 3911 #define MC_CMD_PTP_IN_PPS_ENABLE_OP_OFST 4 3912 /* enum: Enable */ 3913 #define MC_CMD_PTP_ENABLE_PPS 0x0 3914 /* enum: Disable */ 3915 #define MC_CMD_PTP_DISABLE_PPS 0x1 3916 /* Queue id to send events back */ 3917 #define MC_CMD_PTP_IN_PPS_ENABLE_QUEUE_ID_OFST 8 3918 3919 /* MC_CMD_PTP_IN_GET_TIME_FORMAT msgrequest */ 3920 #define MC_CMD_PTP_IN_GET_TIME_FORMAT_LEN 8 3921 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3922 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3923 3924 /* MC_CMD_PTP_IN_GET_ATTRIBUTES msgrequest */ 3925 #define MC_CMD_PTP_IN_GET_ATTRIBUTES_LEN 8 3926 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3927 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3928 3929 /* MC_CMD_PTP_IN_GET_TIMESTAMP_CORRECTIONS msgrequest */ 3930 #define MC_CMD_PTP_IN_GET_TIMESTAMP_CORRECTIONS_LEN 8 3931 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3932 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3933 3934 /* MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE msgrequest */ 3935 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN 12 3936 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3937 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3938 /* Original field containing queue ID. Now extended to include flags. */ 3939 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_OFST 8 3940 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_LBN 0 3941 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_WIDTH 16 3942 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_REPORT_SYNC_STATUS_LBN 31 3943 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_REPORT_SYNC_STATUS_WIDTH 1 3944 3945 /* MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE msgrequest */ 3946 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN 16 3947 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3948 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3949 /* Unsubscribe options */ 3950 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL_OFST 8 3951 /* enum: Unsubscribe a single queue */ 3952 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE 0x0 3953 /* enum: Unsubscribe all queues */ 3954 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_ALL 0x1 3955 /* Event queue ID */ 3956 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE_OFST 12 3957 3958 /* MC_CMD_PTP_IN_MANFTEST_PPS msgrequest */ 3959 #define MC_CMD_PTP_IN_MANFTEST_PPS_LEN 12 3960 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3961 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3962 /* 1 to enable PPS test mode, 0 to disable and return result. */ 3963 #define MC_CMD_PTP_IN_MANFTEST_PPS_TEST_ENABLE_OFST 8 3964 3965 /* MC_CMD_PTP_IN_SET_SYNC_STATUS msgrequest */ 3966 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_LEN 24 3967 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3968 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3969 /* NIC - Host System Clock Synchronization status */ 3970 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_STATUS_OFST 8 3971 /* enum: Host System clock and NIC clock are not in sync */ 3972 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_NOT_IN_SYNC 0x0 3973 /* enum: Host System clock and NIC clock are synchronized */ 3974 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_IN_SYNC 0x1 3975 /* If synchronized, number of seconds until clocks should be considered to be 3976 * no longer in sync. 3977 */ 3978 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_TIMEOUT_OFST 12 3979 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED0_OFST 16 3980 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED1_OFST 20 3981 3982 /* MC_CMD_PTP_OUT msgresponse */ 3983 #define MC_CMD_PTP_OUT_LEN 0 3984 3985 /* MC_CMD_PTP_OUT_TRANSMIT msgresponse */ 3986 #define MC_CMD_PTP_OUT_TRANSMIT_LEN 8 3987 /* Value of seconds timestamp */ 3988 #define MC_CMD_PTP_OUT_TRANSMIT_SECONDS_OFST 0 3989 /* Timestamp major value */ 3990 #define MC_CMD_PTP_OUT_TRANSMIT_MAJOR_OFST 0 3991 /* Value of nanoseconds timestamp */ 3992 #define MC_CMD_PTP_OUT_TRANSMIT_NANOSECONDS_OFST 4 3993 /* Timestamp minor value */ 3994 #define MC_CMD_PTP_OUT_TRANSMIT_MINOR_OFST 4 3995 3996 /* MC_CMD_PTP_OUT_TIME_EVENT_SUBSCRIBE msgresponse */ 3997 #define MC_CMD_PTP_OUT_TIME_EVENT_SUBSCRIBE_LEN 0 3998 3999 /* MC_CMD_PTP_OUT_TIME_EVENT_UNSUBSCRIBE msgresponse */ 4000 #define MC_CMD_PTP_OUT_TIME_EVENT_UNSUBSCRIBE_LEN 0 4001 4002 /* MC_CMD_PTP_OUT_READ_NIC_TIME msgresponse */ 4003 #define MC_CMD_PTP_OUT_READ_NIC_TIME_LEN 8 4004 /* Value of seconds timestamp */ 4005 #define MC_CMD_PTP_OUT_READ_NIC_TIME_SECONDS_OFST 0 4006 /* Timestamp major value */ 4007 #define MC_CMD_PTP_OUT_READ_NIC_TIME_MAJOR_OFST 0 4008 /* Value of nanoseconds timestamp */ 4009 #define MC_CMD_PTP_OUT_READ_NIC_TIME_NANOSECONDS_OFST 4 4010 /* Timestamp minor value */ 4011 #define MC_CMD_PTP_OUT_READ_NIC_TIME_MINOR_OFST 4 4012 4013 /* MC_CMD_PTP_OUT_STATUS msgresponse */ 4014 #define MC_CMD_PTP_OUT_STATUS_LEN 64 4015 /* Frequency of NIC's hardware clock */ 4016 #define MC_CMD_PTP_OUT_STATUS_CLOCK_FREQ_OFST 0 4017 /* Number of packets transmitted and timestamped */ 4018 #define MC_CMD_PTP_OUT_STATUS_STATS_TX_OFST 4 4019 /* Number of packets received and timestamped */ 4020 #define MC_CMD_PTP_OUT_STATUS_STATS_RX_OFST 8 4021 /* Number of packets timestamped by the FPGA */ 4022 #define MC_CMD_PTP_OUT_STATUS_STATS_TS_OFST 12 4023 /* Number of packets filter matched */ 4024 #define MC_CMD_PTP_OUT_STATUS_STATS_FM_OFST 16 4025 /* Number of packets not filter matched */ 4026 #define MC_CMD_PTP_OUT_STATUS_STATS_NFM_OFST 20 4027 /* Number of PPS overflows (noise on input?) */ 4028 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFLOW_OFST 24 4029 /* Number of PPS bad periods */ 4030 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_BAD_OFST 28 4031 /* Minimum period of PPS pulse in nanoseconds */ 4032 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MIN_OFST 32 4033 /* Maximum period of PPS pulse in nanoseconds */ 4034 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MAX_OFST 36 4035 /* Last period of PPS pulse in nanoseconds */ 4036 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_LAST_OFST 40 4037 /* Mean period of PPS pulse in nanoseconds */ 4038 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MEAN_OFST 44 4039 /* Minimum offset of PPS pulse in nanoseconds (signed) */ 4040 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MIN_OFST 48 4041 /* Maximum offset of PPS pulse in nanoseconds (signed) */ 4042 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MAX_OFST 52 4043 /* Last offset of PPS pulse in nanoseconds (signed) */ 4044 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_LAST_OFST 56 4045 /* Mean offset of PPS pulse in nanoseconds (signed) */ 4046 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MEAN_OFST 60 4047 4048 /* MC_CMD_PTP_OUT_SYNCHRONIZE msgresponse */ 4049 #define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMIN 20 4050 #define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMAX 240 4051 #define MC_CMD_PTP_OUT_SYNCHRONIZE_LEN(num) (0+20*(num)) 4052 /* A set of host and NIC times */ 4053 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_OFST 0 4054 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_LEN 20 4055 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MINNUM 1 4056 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MAXNUM 12 4057 /* Host time immediately before NIC's hardware clock read */ 4058 #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTSTART_OFST 0 4059 /* Value of seconds timestamp */ 4060 #define MC_CMD_PTP_OUT_SYNCHRONIZE_SECONDS_OFST 4 4061 /* Timestamp major value */ 4062 #define MC_CMD_PTP_OUT_SYNCHRONIZE_MAJOR_OFST 4 4063 /* Value of nanoseconds timestamp */ 4064 #define MC_CMD_PTP_OUT_SYNCHRONIZE_NANOSECONDS_OFST 8 4065 /* Timestamp minor value */ 4066 #define MC_CMD_PTP_OUT_SYNCHRONIZE_MINOR_OFST 8 4067 /* Host time immediately after NIC's hardware clock read */ 4068 #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTEND_OFST 12 4069 /* Number of nanoseconds waited after reading NIC's hardware clock */ 4070 #define MC_CMD_PTP_OUT_SYNCHRONIZE_WAITNS_OFST 16 4071 4072 /* MC_CMD_PTP_OUT_MANFTEST_BASIC msgresponse */ 4073 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_LEN 8 4074 /* Results of testing */ 4075 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_RESULT_OFST 0 4076 /* enum: Successful test */ 4077 #define MC_CMD_PTP_MANF_SUCCESS 0x0 4078 /* enum: FPGA load failed */ 4079 #define MC_CMD_PTP_MANF_FPGA_LOAD 0x1 4080 /* enum: FPGA version invalid */ 4081 #define MC_CMD_PTP_MANF_FPGA_VERSION 0x2 4082 /* enum: FPGA registers incorrect */ 4083 #define MC_CMD_PTP_MANF_FPGA_REGISTERS 0x3 4084 /* enum: Oscillator possibly not working? */ 4085 #define MC_CMD_PTP_MANF_OSCILLATOR 0x4 4086 /* enum: Timestamps not increasing */ 4087 #define MC_CMD_PTP_MANF_TIMESTAMPS 0x5 4088 /* enum: Mismatched packet count */ 4089 #define MC_CMD_PTP_MANF_PACKET_COUNT 0x6 4090 /* enum: Mismatched packet count (Siena filter and FPGA) */ 4091 #define MC_CMD_PTP_MANF_FILTER_COUNT 0x7 4092 /* enum: Not enough packets to perform timestamp check */ 4093 #define MC_CMD_PTP_MANF_PACKET_ENOUGH 0x8 4094 /* enum: Timestamp trigger GPIO not working */ 4095 #define MC_CMD_PTP_MANF_GPIO_TRIGGER 0x9 4096 /* enum: Insufficient PPS events to perform checks */ 4097 #define MC_CMD_PTP_MANF_PPS_ENOUGH 0xa 4098 /* enum: PPS time event period not sufficiently close to 1s. */ 4099 #define MC_CMD_PTP_MANF_PPS_PERIOD 0xb 4100 /* enum: PPS time event nS reading not sufficiently close to zero. */ 4101 #define MC_CMD_PTP_MANF_PPS_NS 0xc 4102 /* enum: PTP peripheral registers incorrect */ 4103 #define MC_CMD_PTP_MANF_REGISTERS 0xd 4104 /* enum: Failed to read time from PTP peripheral */ 4105 #define MC_CMD_PTP_MANF_CLOCK_READ 0xe 4106 /* Presence of external oscillator */ 4107 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_EXTOSC_OFST 4 4108 4109 /* MC_CMD_PTP_OUT_MANFTEST_PACKET msgresponse */ 4110 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_LEN 12 4111 /* Results of testing */ 4112 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_RESULT_OFST 0 4113 /* Number of packets received by FPGA */ 4114 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FPGACOUNT_OFST 4 4115 /* Number of packets received by Siena filters */ 4116 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FILTERCOUNT_OFST 8 4117 4118 /* MC_CMD_PTP_OUT_FPGAREAD msgresponse */ 4119 #define MC_CMD_PTP_OUT_FPGAREAD_LENMIN 1 4120 #define MC_CMD_PTP_OUT_FPGAREAD_LENMAX 252 4121 #define MC_CMD_PTP_OUT_FPGAREAD_LEN(num) (0+1*(num)) 4122 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_OFST 0 4123 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_LEN 1 4124 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MINNUM 1 4125 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MAXNUM 252 4126 4127 /* MC_CMD_PTP_OUT_GET_TIME_FORMAT msgresponse */ 4128 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_LEN 4 4129 /* Time format required/used by for this NIC. Applies to all PTP MCDI 4130 * operations that pass times between the host and firmware. If this operation 4131 * is not supported (older firmware) a format of seconds and nanoseconds should 4132 * be assumed. 4133 */ 4134 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_FORMAT_OFST 0 4135 /* enum: Times are in seconds and nanoseconds */ 4136 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_NANOSECONDS 0x0 4137 /* enum: Major register has units of 16 second per tick, minor 8 ns per tick */ 4138 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_16SECONDS_8NANOSECONDS 0x1 4139 /* enum: Major register has units of seconds, minor 2^-27s per tick */ 4140 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_27FRACTION 0x2 4141 4142 /* MC_CMD_PTP_OUT_GET_ATTRIBUTES msgresponse */ 4143 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_LEN 24 4144 /* Time format required/used by for this NIC. Applies to all PTP MCDI 4145 * operations that pass times between the host and firmware. If this operation 4146 * is not supported (older firmware) a format of seconds and nanoseconds should 4147 * be assumed. 4148 */ 4149 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_TIME_FORMAT_OFST 0 4150 /* enum: Times are in seconds and nanoseconds */ 4151 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_NANOSECONDS 0x0 4152 /* enum: Major register has units of 16 second per tick, minor 8 ns per tick */ 4153 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_16SECONDS_8NANOSECONDS 0x1 4154 /* enum: Major register has units of seconds, minor 2^-27s per tick */ 4155 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_27FRACTION 0x2 4156 /* Minimum acceptable value for a corrected synchronization timeset. When 4157 * comparing host and NIC clock times, the MC returns a set of samples that 4158 * contain the host start and end time, the MC time when the host start was 4159 * detected and the time the MC waited between reading the time and detecting 4160 * the host end. The corrected sync window is the difference between the host 4161 * end and start times minus the time that the MC waited for host end. 4162 */ 4163 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SYNC_WINDOW_MIN_OFST 4 4164 /* Various PTP capabilities */ 4165 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_CAPABILITIES_OFST 8 4166 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_LBN 0 4167 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_WIDTH 1 4168 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RX_TSTAMP_OOB_LBN 1 4169 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RX_TSTAMP_OOB_WIDTH 1 4170 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED0_OFST 12 4171 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED1_OFST 16 4172 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED2_OFST 20 4173 4174 /* MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS msgresponse */ 4175 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_LEN 16 4176 /* Uncorrected error on PTP transmit timestamps in NIC clock format */ 4177 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_TRANSMIT_OFST 0 4178 /* Uncorrected error on PTP receive timestamps in NIC clock format */ 4179 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_RECEIVE_OFST 4 4180 /* Uncorrected error on PPS output in NIC clock format */ 4181 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_OUT_OFST 8 4182 /* Uncorrected error on PPS input in NIC clock format */ 4183 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_IN_OFST 12 4184 4185 /* MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2 msgresponse */ 4186 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_LEN 24 4187 /* Uncorrected error on PTP transmit timestamps in NIC clock format */ 4188 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_TX_OFST 0 4189 /* Uncorrected error on PTP receive timestamps in NIC clock format */ 4190 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_RX_OFST 4 4191 /* Uncorrected error on PPS output in NIC clock format */ 4192 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_OUT_OFST 8 4193 /* Uncorrected error on PPS input in NIC clock format */ 4194 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_IN_OFST 12 4195 /* Uncorrected error on non-PTP transmit timestamps in NIC clock format */ 4196 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_TX_OFST 16 4197 /* Uncorrected error on non-PTP receive timestamps in NIC clock format */ 4198 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_RX_OFST 20 4199 4200 /* MC_CMD_PTP_OUT_MANFTEST_PPS msgresponse */ 4201 #define MC_CMD_PTP_OUT_MANFTEST_PPS_LEN 4 4202 /* Results of testing */ 4203 #define MC_CMD_PTP_OUT_MANFTEST_PPS_TEST_RESULT_OFST 0 4204 /* Enum values, see field(s): */ 4205 /* MC_CMD_PTP_OUT_MANFTEST_BASIC/TEST_RESULT */ 4206 4207 /* MC_CMD_PTP_OUT_SET_SYNC_STATUS msgresponse */ 4208 #define MC_CMD_PTP_OUT_SET_SYNC_STATUS_LEN 0 4209 4210 4211 /***********************************/ 4212 /* MC_CMD_CSR_READ32 4213 * Read 32bit words from the indirect memory map. 4214 */ 4215 #define MC_CMD_CSR_READ32 0xc 4216 #undef MC_CMD_0xc_PRIVILEGE_CTG 4217 4218 #define MC_CMD_0xc_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4219 4220 /* MC_CMD_CSR_READ32_IN msgrequest */ 4221 #define MC_CMD_CSR_READ32_IN_LEN 12 4222 /* Address */ 4223 #define MC_CMD_CSR_READ32_IN_ADDR_OFST 0 4224 #define MC_CMD_CSR_READ32_IN_STEP_OFST 4 4225 #define MC_CMD_CSR_READ32_IN_NUMWORDS_OFST 8 4226 4227 /* MC_CMD_CSR_READ32_OUT msgresponse */ 4228 #define MC_CMD_CSR_READ32_OUT_LENMIN 4 4229 #define MC_CMD_CSR_READ32_OUT_LENMAX 252 4230 #define MC_CMD_CSR_READ32_OUT_LEN(num) (0+4*(num)) 4231 /* The last dword is the status, not a value read */ 4232 #define MC_CMD_CSR_READ32_OUT_BUFFER_OFST 0 4233 #define MC_CMD_CSR_READ32_OUT_BUFFER_LEN 4 4234 #define MC_CMD_CSR_READ32_OUT_BUFFER_MINNUM 1 4235 #define MC_CMD_CSR_READ32_OUT_BUFFER_MAXNUM 63 4236 4237 4238 /***********************************/ 4239 /* MC_CMD_CSR_WRITE32 4240 * Write 32bit dwords to the indirect memory map. 4241 */ 4242 #define MC_CMD_CSR_WRITE32 0xd 4243 #undef MC_CMD_0xd_PRIVILEGE_CTG 4244 4245 #define MC_CMD_0xd_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4246 4247 /* MC_CMD_CSR_WRITE32_IN msgrequest */ 4248 #define MC_CMD_CSR_WRITE32_IN_LENMIN 12 4249 #define MC_CMD_CSR_WRITE32_IN_LENMAX 252 4250 #define MC_CMD_CSR_WRITE32_IN_LEN(num) (8+4*(num)) 4251 /* Address */ 4252 #define MC_CMD_CSR_WRITE32_IN_ADDR_OFST 0 4253 #define MC_CMD_CSR_WRITE32_IN_STEP_OFST 4 4254 #define MC_CMD_CSR_WRITE32_IN_BUFFER_OFST 8 4255 #define MC_CMD_CSR_WRITE32_IN_BUFFER_LEN 4 4256 #define MC_CMD_CSR_WRITE32_IN_BUFFER_MINNUM 1 4257 #define MC_CMD_CSR_WRITE32_IN_BUFFER_MAXNUM 61 4258 4259 /* MC_CMD_CSR_WRITE32_OUT msgresponse */ 4260 #define MC_CMD_CSR_WRITE32_OUT_LEN 4 4261 #define MC_CMD_CSR_WRITE32_OUT_STATUS_OFST 0 4262 4263 4264 /***********************************/ 4265 /* MC_CMD_HP 4266 * These commands are used for HP related features. They are grouped under one 4267 * MCDI command to avoid creating too many MCDI commands. 4268 */ 4269 #define MC_CMD_HP 0x54 4270 #undef MC_CMD_0x54_PRIVILEGE_CTG 4271 4272 #define MC_CMD_0x54_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4273 4274 /* MC_CMD_HP_IN msgrequest */ 4275 #define MC_CMD_HP_IN_LEN 16 4276 /* HP OCSD sub-command. When address is not NULL, request activation of OCSD at 4277 * the specified address with the specified interval.When address is NULL, 4278 * INTERVAL is interpreted as a command: 0: stop OCSD / 1: Report OCSD current 4279 * state / 2: (debug) Show temperature reported by one of the supported 4280 * sensors. 4281 */ 4282 #define MC_CMD_HP_IN_SUBCMD_OFST 0 4283 /* enum: OCSD (Option Card Sensor Data) sub-command. */ 4284 #define MC_CMD_HP_IN_OCSD_SUBCMD 0x0 4285 /* enum: Last known valid HP sub-command. */ 4286 #define MC_CMD_HP_IN_LAST_SUBCMD 0x0 4287 /* The address to the array of sensor fields. (Or NULL to use a sub-command.) 4288 */ 4289 #define MC_CMD_HP_IN_OCSD_ADDR_OFST 4 4290 #define MC_CMD_HP_IN_OCSD_ADDR_LEN 8 4291 #define MC_CMD_HP_IN_OCSD_ADDR_LO_OFST 4 4292 #define MC_CMD_HP_IN_OCSD_ADDR_HI_OFST 8 4293 /* The requested update interval, in seconds. (Or the sub-command if ADDR is 4294 * NULL.) 4295 */ 4296 #define MC_CMD_HP_IN_OCSD_INTERVAL_OFST 12 4297 4298 /* MC_CMD_HP_OUT msgresponse */ 4299 #define MC_CMD_HP_OUT_LEN 4 4300 #define MC_CMD_HP_OUT_OCSD_STATUS_OFST 0 4301 /* enum: OCSD stopped for this card. */ 4302 #define MC_CMD_HP_OUT_OCSD_STOPPED 0x1 4303 /* enum: OCSD was successfully started with the address provided. */ 4304 #define MC_CMD_HP_OUT_OCSD_STARTED 0x2 4305 /* enum: OCSD was already started for this card. */ 4306 #define MC_CMD_HP_OUT_OCSD_ALREADY_STARTED 0x3 4307 4308 4309 /***********************************/ 4310 /* MC_CMD_STACKINFO 4311 * Get stack information. 4312 */ 4313 #define MC_CMD_STACKINFO 0xf 4314 #undef MC_CMD_0xf_PRIVILEGE_CTG 4315 4316 #define MC_CMD_0xf_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4317 4318 /* MC_CMD_STACKINFO_IN msgrequest */ 4319 #define MC_CMD_STACKINFO_IN_LEN 0 4320 4321 /* MC_CMD_STACKINFO_OUT msgresponse */ 4322 #define MC_CMD_STACKINFO_OUT_LENMIN 12 4323 #define MC_CMD_STACKINFO_OUT_LENMAX 252 4324 #define MC_CMD_STACKINFO_OUT_LEN(num) (0+12*(num)) 4325 /* (thread ptr, stack size, free space) for each thread in system */ 4326 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_OFST 0 4327 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_LEN 12 4328 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_MINNUM 1 4329 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_MAXNUM 21 4330 4331 4332 /***********************************/ 4333 /* MC_CMD_MDIO_READ 4334 * MDIO register read. 4335 */ 4336 #define MC_CMD_MDIO_READ 0x10 4337 #undef MC_CMD_0x10_PRIVILEGE_CTG 4338 4339 #define MC_CMD_0x10_PRIVILEGE_CTG SRIOV_CTG_GENERAL 4340 4341 /* MC_CMD_MDIO_READ_IN msgrequest */ 4342 #define MC_CMD_MDIO_READ_IN_LEN 16 4343 /* Bus number; there are two MDIO buses: one for the internal PHY, and one for 4344 * external devices. 4345 */ 4346 #define MC_CMD_MDIO_READ_IN_BUS_OFST 0 4347 /* enum: Internal. */ 4348 #define MC_CMD_MDIO_BUS_INTERNAL 0x0 4349 /* enum: External. */ 4350 #define MC_CMD_MDIO_BUS_EXTERNAL 0x1 4351 /* Port address */ 4352 #define MC_CMD_MDIO_READ_IN_PRTAD_OFST 4 4353 /* Device Address or clause 22. */ 4354 #define MC_CMD_MDIO_READ_IN_DEVAD_OFST 8 4355 /* enum: By default all the MCDI MDIO operations perform clause45 mode. If you 4356 * want to use clause22 then set DEVAD = MC_CMD_MDIO_CLAUSE22. 4357 */ 4358 #define MC_CMD_MDIO_CLAUSE22 0x20 4359 /* Address */ 4360 #define MC_CMD_MDIO_READ_IN_ADDR_OFST 12 4361 4362 /* MC_CMD_MDIO_READ_OUT msgresponse */ 4363 #define MC_CMD_MDIO_READ_OUT_LEN 8 4364 /* Value */ 4365 #define MC_CMD_MDIO_READ_OUT_VALUE_OFST 0 4366 /* Status the MDIO commands return the raw status bits from the MDIO block. A 4367 * "good" transaction should have the DONE bit set and all other bits clear. 4368 */ 4369 #define MC_CMD_MDIO_READ_OUT_STATUS_OFST 4 4370 /* enum: Good. */ 4371 #define MC_CMD_MDIO_STATUS_GOOD 0x8 4372 4373 4374 /***********************************/ 4375 /* MC_CMD_MDIO_WRITE 4376 * MDIO register write. 4377 */ 4378 #define MC_CMD_MDIO_WRITE 0x11 4379 #undef MC_CMD_0x11_PRIVILEGE_CTG 4380 4381 #define MC_CMD_0x11_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4382 4383 /* MC_CMD_MDIO_WRITE_IN msgrequest */ 4384 #define MC_CMD_MDIO_WRITE_IN_LEN 20 4385 /* Bus number; there are two MDIO buses: one for the internal PHY, and one for 4386 * external devices. 4387 */ 4388 #define MC_CMD_MDIO_WRITE_IN_BUS_OFST 0 4389 /* enum: Internal. */ 4390 /* MC_CMD_MDIO_BUS_INTERNAL 0x0 */ 4391 /* enum: External. */ 4392 /* MC_CMD_MDIO_BUS_EXTERNAL 0x1 */ 4393 /* Port address */ 4394 #define MC_CMD_MDIO_WRITE_IN_PRTAD_OFST 4 4395 /* Device Address or clause 22. */ 4396 #define MC_CMD_MDIO_WRITE_IN_DEVAD_OFST 8 4397 /* enum: By default all the MCDI MDIO operations perform clause45 mode. If you 4398 * want to use clause22 then set DEVAD = MC_CMD_MDIO_CLAUSE22. 4399 */ 4400 /* MC_CMD_MDIO_CLAUSE22 0x20 */ 4401 /* Address */ 4402 #define MC_CMD_MDIO_WRITE_IN_ADDR_OFST 12 4403 /* Value */ 4404 #define MC_CMD_MDIO_WRITE_IN_VALUE_OFST 16 4405 4406 /* MC_CMD_MDIO_WRITE_OUT msgresponse */ 4407 #define MC_CMD_MDIO_WRITE_OUT_LEN 4 4408 /* Status; the MDIO commands return the raw status bits from the MDIO block. A 4409 * "good" transaction should have the DONE bit set and all other bits clear. 4410 */ 4411 #define MC_CMD_MDIO_WRITE_OUT_STATUS_OFST 0 4412 /* enum: Good. */ 4413 /* MC_CMD_MDIO_STATUS_GOOD 0x8 */ 4414 4415 4416 /***********************************/ 4417 /* MC_CMD_DBI_WRITE 4418 * Write DBI register(s). 4419 */ 4420 #define MC_CMD_DBI_WRITE 0x12 4421 #undef MC_CMD_0x12_PRIVILEGE_CTG 4422 4423 #define MC_CMD_0x12_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4424 4425 /* MC_CMD_DBI_WRITE_IN msgrequest */ 4426 #define MC_CMD_DBI_WRITE_IN_LENMIN 12 4427 #define MC_CMD_DBI_WRITE_IN_LENMAX 252 4428 #define MC_CMD_DBI_WRITE_IN_LEN(num) (0+12*(num)) 4429 /* Each write op consists of an address (offset 0), byte enable/VF/CS2 (offset 4430 * 32) and value (offset 64). See MC_CMD_DBIWROP_TYPEDEF. 4431 */ 4432 #define MC_CMD_DBI_WRITE_IN_DBIWROP_OFST 0 4433 #define MC_CMD_DBI_WRITE_IN_DBIWROP_LEN 12 4434 #define MC_CMD_DBI_WRITE_IN_DBIWROP_MINNUM 1 4435 #define MC_CMD_DBI_WRITE_IN_DBIWROP_MAXNUM 21 4436 4437 /* MC_CMD_DBI_WRITE_OUT msgresponse */ 4438 #define MC_CMD_DBI_WRITE_OUT_LEN 0 4439 4440 /* MC_CMD_DBIWROP_TYPEDEF structuredef */ 4441 #define MC_CMD_DBIWROP_TYPEDEF_LEN 12 4442 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST 0 4443 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_LBN 0 4444 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_WIDTH 32 4445 #define MC_CMD_DBIWROP_TYPEDEF_PARMS_OFST 4 4446 #define MC_CMD_DBIWROP_TYPEDEF_VF_NUM_LBN 16 4447 #define MC_CMD_DBIWROP_TYPEDEF_VF_NUM_WIDTH 16 4448 #define MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_LBN 15 4449 #define MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_WIDTH 1 4450 #define MC_CMD_DBIWROP_TYPEDEF_CS2_LBN 14 4451 #define MC_CMD_DBIWROP_TYPEDEF_CS2_WIDTH 1 4452 #define MC_CMD_DBIWROP_TYPEDEF_PARMS_LBN 32 4453 #define MC_CMD_DBIWROP_TYPEDEF_PARMS_WIDTH 32 4454 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST 8 4455 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_LBN 64 4456 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_WIDTH 32 4457 4458 4459 /***********************************/ 4460 /* MC_CMD_PORT_READ32 4461 * Read a 32-bit register from the indirect port register map. The port to 4462 * access is implied by the Shared memory channel used. 4463 */ 4464 #define MC_CMD_PORT_READ32 0x14 4465 4466 /* MC_CMD_PORT_READ32_IN msgrequest */ 4467 #define MC_CMD_PORT_READ32_IN_LEN 4 4468 /* Address */ 4469 #define MC_CMD_PORT_READ32_IN_ADDR_OFST 0 4470 4471 /* MC_CMD_PORT_READ32_OUT msgresponse */ 4472 #define MC_CMD_PORT_READ32_OUT_LEN 8 4473 /* Value */ 4474 #define MC_CMD_PORT_READ32_OUT_VALUE_OFST 0 4475 /* Status */ 4476 #define MC_CMD_PORT_READ32_OUT_STATUS_OFST 4 4477 4478 4479 /***********************************/ 4480 /* MC_CMD_PORT_WRITE32 4481 * Write a 32-bit register to the indirect port register map. The port to 4482 * access is implied by the Shared memory channel used. 4483 */ 4484 #define MC_CMD_PORT_WRITE32 0x15 4485 4486 /* MC_CMD_PORT_WRITE32_IN msgrequest */ 4487 #define MC_CMD_PORT_WRITE32_IN_LEN 8 4488 /* Address */ 4489 #define MC_CMD_PORT_WRITE32_IN_ADDR_OFST 0 4490 /* Value */ 4491 #define MC_CMD_PORT_WRITE32_IN_VALUE_OFST 4 4492 4493 /* MC_CMD_PORT_WRITE32_OUT msgresponse */ 4494 #define MC_CMD_PORT_WRITE32_OUT_LEN 4 4495 /* Status */ 4496 #define MC_CMD_PORT_WRITE32_OUT_STATUS_OFST 0 4497 4498 4499 /***********************************/ 4500 /* MC_CMD_PORT_READ128 4501 * Read a 128-bit register from the indirect port register map. The port to 4502 * access is implied by the Shared memory channel used. 4503 */ 4504 #define MC_CMD_PORT_READ128 0x16 4505 4506 /* MC_CMD_PORT_READ128_IN msgrequest */ 4507 #define MC_CMD_PORT_READ128_IN_LEN 4 4508 /* Address */ 4509 #define MC_CMD_PORT_READ128_IN_ADDR_OFST 0 4510 4511 /* MC_CMD_PORT_READ128_OUT msgresponse */ 4512 #define MC_CMD_PORT_READ128_OUT_LEN 20 4513 /* Value */ 4514 #define MC_CMD_PORT_READ128_OUT_VALUE_OFST 0 4515 #define MC_CMD_PORT_READ128_OUT_VALUE_LEN 16 4516 /* Status */ 4517 #define MC_CMD_PORT_READ128_OUT_STATUS_OFST 16 4518 4519 4520 /***********************************/ 4521 /* MC_CMD_PORT_WRITE128 4522 * Write a 128-bit register to the indirect port register map. The port to 4523 * access is implied by the Shared memory channel used. 4524 */ 4525 #define MC_CMD_PORT_WRITE128 0x17 4526 4527 /* MC_CMD_PORT_WRITE128_IN msgrequest */ 4528 #define MC_CMD_PORT_WRITE128_IN_LEN 20 4529 /* Address */ 4530 #define MC_CMD_PORT_WRITE128_IN_ADDR_OFST 0 4531 /* Value */ 4532 #define MC_CMD_PORT_WRITE128_IN_VALUE_OFST 4 4533 #define MC_CMD_PORT_WRITE128_IN_VALUE_LEN 16 4534 4535 /* MC_CMD_PORT_WRITE128_OUT msgresponse */ 4536 #define MC_CMD_PORT_WRITE128_OUT_LEN 4 4537 /* Status */ 4538 #define MC_CMD_PORT_WRITE128_OUT_STATUS_OFST 0 4539 4540 /* MC_CMD_CAPABILITIES structuredef */ 4541 #define MC_CMD_CAPABILITIES_LEN 4 4542 /* Small buf table. */ 4543 #define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_LBN 0 4544 #define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_WIDTH 1 4545 /* Turbo mode (for Maranello). */ 4546 #define MC_CMD_CAPABILITIES_TURBO_LBN 1 4547 #define MC_CMD_CAPABILITIES_TURBO_WIDTH 1 4548 /* Turbo mode active (for Maranello). */ 4549 #define MC_CMD_CAPABILITIES_TURBO_ACTIVE_LBN 2 4550 #define MC_CMD_CAPABILITIES_TURBO_ACTIVE_WIDTH 1 4551 /* PTP offload. */ 4552 #define MC_CMD_CAPABILITIES_PTP_LBN 3 4553 #define MC_CMD_CAPABILITIES_PTP_WIDTH 1 4554 /* AOE mode. */ 4555 #define MC_CMD_CAPABILITIES_AOE_LBN 4 4556 #define MC_CMD_CAPABILITIES_AOE_WIDTH 1 4557 /* AOE mode active. */ 4558 #define MC_CMD_CAPABILITIES_AOE_ACTIVE_LBN 5 4559 #define MC_CMD_CAPABILITIES_AOE_ACTIVE_WIDTH 1 4560 /* AOE mode active. */ 4561 #define MC_CMD_CAPABILITIES_FC_ACTIVE_LBN 6 4562 #define MC_CMD_CAPABILITIES_FC_ACTIVE_WIDTH 1 4563 #define MC_CMD_CAPABILITIES_RESERVED_LBN 7 4564 #define MC_CMD_CAPABILITIES_RESERVED_WIDTH 25 4565 4566 4567 /***********************************/ 4568 /* MC_CMD_GET_BOARD_CFG 4569 * Returns the MC firmware configuration structure. 4570 */ 4571 #define MC_CMD_GET_BOARD_CFG 0x18 4572 #undef MC_CMD_0x18_PRIVILEGE_CTG 4573 4574 #define MC_CMD_0x18_PRIVILEGE_CTG SRIOV_CTG_GENERAL 4575 4576 /* MC_CMD_GET_BOARD_CFG_IN msgrequest */ 4577 #define MC_CMD_GET_BOARD_CFG_IN_LEN 0 4578 4579 /* MC_CMD_GET_BOARD_CFG_OUT msgresponse */ 4580 #define MC_CMD_GET_BOARD_CFG_OUT_LENMIN 96 4581 #define MC_CMD_GET_BOARD_CFG_OUT_LENMAX 136 4582 #define MC_CMD_GET_BOARD_CFG_OUT_LEN(num) (72+2*(num)) 4583 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_OFST 0 4584 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_OFST 4 4585 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_LEN 32 4586 /* See MC_CMD_CAPABILITIES */ 4587 #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT0_OFST 36 4588 /* See MC_CMD_CAPABILITIES */ 4589 #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT1_OFST 40 4590 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_OFST 44 4591 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_LEN 6 4592 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_OFST 50 4593 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_LEN 6 4594 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT0_OFST 56 4595 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT1_OFST 60 4596 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT0_OFST 64 4597 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT1_OFST 68 4598 /* This field contains a 16-bit value for each of the types of NVRAM area. The 4599 * values are defined in the firmware/mc/platform/.c file for a specific board 4600 * type, but otherwise have no meaning to the MC; they are used by the driver 4601 * to manage selection of appropriate firmware updates. 4602 */ 4603 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_OFST 72 4604 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_LEN 2 4605 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MINNUM 12 4606 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM 32 4607 4608 4609 /***********************************/ 4610 /* MC_CMD_DBI_READX 4611 * Read DBI register(s) -- extended functionality 4612 */ 4613 #define MC_CMD_DBI_READX 0x19 4614 #undef MC_CMD_0x19_PRIVILEGE_CTG 4615 4616 #define MC_CMD_0x19_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4617 4618 /* MC_CMD_DBI_READX_IN msgrequest */ 4619 #define MC_CMD_DBI_READX_IN_LENMIN 8 4620 #define MC_CMD_DBI_READX_IN_LENMAX 248 4621 #define MC_CMD_DBI_READX_IN_LEN(num) (0+8*(num)) 4622 /* Each Read op consists of an address (offset 0), VF/CS2) */ 4623 #define MC_CMD_DBI_READX_IN_DBIRDOP_OFST 0 4624 #define MC_CMD_DBI_READX_IN_DBIRDOP_LEN 8 4625 #define MC_CMD_DBI_READX_IN_DBIRDOP_LO_OFST 0 4626 #define MC_CMD_DBI_READX_IN_DBIRDOP_HI_OFST 4 4627 #define MC_CMD_DBI_READX_IN_DBIRDOP_MINNUM 1 4628 #define MC_CMD_DBI_READX_IN_DBIRDOP_MAXNUM 31 4629 4630 /* MC_CMD_DBI_READX_OUT msgresponse */ 4631 #define MC_CMD_DBI_READX_OUT_LENMIN 4 4632 #define MC_CMD_DBI_READX_OUT_LENMAX 252 4633 #define MC_CMD_DBI_READX_OUT_LEN(num) (0+4*(num)) 4634 /* Value */ 4635 #define MC_CMD_DBI_READX_OUT_VALUE_OFST 0 4636 #define MC_CMD_DBI_READX_OUT_VALUE_LEN 4 4637 #define MC_CMD_DBI_READX_OUT_VALUE_MINNUM 1 4638 #define MC_CMD_DBI_READX_OUT_VALUE_MAXNUM 63 4639 4640 /* MC_CMD_DBIRDOP_TYPEDEF structuredef */ 4641 #define MC_CMD_DBIRDOP_TYPEDEF_LEN 8 4642 #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_OFST 0 4643 #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_LBN 0 4644 #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_WIDTH 32 4645 #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_OFST 4 4646 #define MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_LBN 16 4647 #define MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_WIDTH 16 4648 #define MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_LBN 15 4649 #define MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_WIDTH 1 4650 #define MC_CMD_DBIRDOP_TYPEDEF_CS2_LBN 14 4651 #define MC_CMD_DBIRDOP_TYPEDEF_CS2_WIDTH 1 4652 #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_LBN 32 4653 #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_WIDTH 32 4654 4655 4656 /***********************************/ 4657 /* MC_CMD_SET_RAND_SEED 4658 * Set the 16byte seed for the MC pseudo-random generator. 4659 */ 4660 #define MC_CMD_SET_RAND_SEED 0x1a 4661 #undef MC_CMD_0x1a_PRIVILEGE_CTG 4662 4663 #define MC_CMD_0x1a_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4664 4665 /* MC_CMD_SET_RAND_SEED_IN msgrequest */ 4666 #define MC_CMD_SET_RAND_SEED_IN_LEN 16 4667 /* Seed value. */ 4668 #define MC_CMD_SET_RAND_SEED_IN_SEED_OFST 0 4669 #define MC_CMD_SET_RAND_SEED_IN_SEED_LEN 16 4670 4671 /* MC_CMD_SET_RAND_SEED_OUT msgresponse */ 4672 #define MC_CMD_SET_RAND_SEED_OUT_LEN 0 4673 4674 4675 /***********************************/ 4676 /* MC_CMD_LTSSM_HIST 4677 * Retrieve the history of the LTSSM, if the build supports it. 4678 */ 4679 #define MC_CMD_LTSSM_HIST 0x1b 4680 4681 /* MC_CMD_LTSSM_HIST_IN msgrequest */ 4682 #define MC_CMD_LTSSM_HIST_IN_LEN 0 4683 4684 /* MC_CMD_LTSSM_HIST_OUT msgresponse */ 4685 #define MC_CMD_LTSSM_HIST_OUT_LENMIN 0 4686 #define MC_CMD_LTSSM_HIST_OUT_LENMAX 252 4687 #define MC_CMD_LTSSM_HIST_OUT_LEN(num) (0+4*(num)) 4688 /* variable number of LTSSM values, as bytes. The history is read-to-clear. */ 4689 #define MC_CMD_LTSSM_HIST_OUT_DATA_OFST 0 4690 #define MC_CMD_LTSSM_HIST_OUT_DATA_LEN 4 4691 #define MC_CMD_LTSSM_HIST_OUT_DATA_MINNUM 0 4692 #define MC_CMD_LTSSM_HIST_OUT_DATA_MAXNUM 63 4693 4694 4695 /***********************************/ 4696 /* MC_CMD_DRV_ATTACH 4697 * Inform MCPU that this port is managed on the host (i.e. driver active). For 4698 * Huntington, also request the preferred datapath firmware to use if possible 4699 * (it may not be possible for this request to be fulfilled; the driver must 4700 * issue a subsequent MC_CMD_GET_CAPABILITIES command to determine which 4701 * features are actually available). The FIRMWARE_ID field is ignored by older 4702 * platforms. 4703 */ 4704 #define MC_CMD_DRV_ATTACH 0x1c 4705 #undef MC_CMD_0x1c_PRIVILEGE_CTG 4706 4707 #define MC_CMD_0x1c_PRIVILEGE_CTG SRIOV_CTG_GENERAL 4708 4709 /* MC_CMD_DRV_ATTACH_IN msgrequest */ 4710 #define MC_CMD_DRV_ATTACH_IN_LEN 12 4711 /* new state to set if UPDATE=1 */ 4712 #define MC_CMD_DRV_ATTACH_IN_NEW_STATE_OFST 0 4713 #define MC_CMD_DRV_ATTACH_LBN 0 4714 #define MC_CMD_DRV_ATTACH_WIDTH 1 4715 #define MC_CMD_DRV_PREBOOT_LBN 1 4716 #define MC_CMD_DRV_PREBOOT_WIDTH 1 4717 /* 1 to set new state, or 0 to just report the existing state */ 4718 #define MC_CMD_DRV_ATTACH_IN_UPDATE_OFST 4 4719 /* preferred datapath firmware (for Huntington; ignored for Siena) */ 4720 #define MC_CMD_DRV_ATTACH_IN_FIRMWARE_ID_OFST 8 4721 /* enum: Prefer to use full featured firmware */ 4722 #define MC_CMD_FW_FULL_FEATURED 0x0 4723 /* enum: Prefer to use firmware with fewer features but lower latency */ 4724 #define MC_CMD_FW_LOW_LATENCY 0x1 4725 /* enum: Prefer to use firmware for SolarCapture packed stream mode */ 4726 #define MC_CMD_FW_PACKED_STREAM 0x2 4727 /* enum: Prefer to use firmware with fewer features and simpler TX event 4728 * batching but higher TX packet rate 4729 */ 4730 #define MC_CMD_FW_HIGH_TX_RATE 0x3 4731 /* enum: Reserved value */ 4732 #define MC_CMD_FW_PACKED_STREAM_HASH_MODE_1 0x4 4733 /* enum: Prefer to use firmware with additional "rules engine" filtering 4734 * support 4735 */ 4736 #define MC_CMD_FW_RULES_ENGINE 0x5 4737 /* enum: Only this option is allowed for non-admin functions */ 4738 #define MC_CMD_FW_DONT_CARE 0xffffffff 4739 4740 /* MC_CMD_DRV_ATTACH_OUT msgresponse */ 4741 #define MC_CMD_DRV_ATTACH_OUT_LEN 4 4742 /* previous or existing state, see the bitmask at NEW_STATE */ 4743 #define MC_CMD_DRV_ATTACH_OUT_OLD_STATE_OFST 0 4744 4745 /* MC_CMD_DRV_ATTACH_EXT_OUT msgresponse */ 4746 #define MC_CMD_DRV_ATTACH_EXT_OUT_LEN 8 4747 /* previous or existing state, see the bitmask at NEW_STATE */ 4748 #define MC_CMD_DRV_ATTACH_EXT_OUT_OLD_STATE_OFST 0 4749 /* Flags associated with this function */ 4750 #define MC_CMD_DRV_ATTACH_EXT_OUT_FUNC_FLAGS_OFST 4 4751 /* enum: Labels the lowest-numbered function visible to the OS */ 4752 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY 0x0 4753 /* enum: The function can control the link state of the physical port it is 4754 * bound to. 4755 */ 4756 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL 0x1 4757 /* enum: The function can perform privileged operations */ 4758 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TRUSTED 0x2 4759 /* enum: The function does not have an active port associated with it. The port 4760 * refers to the Sorrento external FPGA port. 4761 */ 4762 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_NO_ACTIVE_PORT 0x3 4763 4764 4765 /***********************************/ 4766 /* MC_CMD_SHMUART 4767 * Route UART output to circular buffer in shared memory instead. 4768 */ 4769 #define MC_CMD_SHMUART 0x1f 4770 4771 /* MC_CMD_SHMUART_IN msgrequest */ 4772 #define MC_CMD_SHMUART_IN_LEN 4 4773 /* ??? */ 4774 #define MC_CMD_SHMUART_IN_FLAG_OFST 0 4775 4776 /* MC_CMD_SHMUART_OUT msgresponse */ 4777 #define MC_CMD_SHMUART_OUT_LEN 0 4778 4779 4780 /***********************************/ 4781 /* MC_CMD_PORT_RESET 4782 * Generic per-port reset. There is no equivalent for per-board reset. Locks 4783 * required: None; Return code: 0, ETIME. NOTE: This command is deprecated - 4784 * use MC_CMD_ENTITY_RESET instead. 4785 */ 4786 #define MC_CMD_PORT_RESET 0x20 4787 #undef MC_CMD_0x20_PRIVILEGE_CTG 4788 4789 #define MC_CMD_0x20_PRIVILEGE_CTG SRIOV_CTG_GENERAL 4790 4791 /* MC_CMD_PORT_RESET_IN msgrequest */ 4792 #define MC_CMD_PORT_RESET_IN_LEN 0 4793 4794 /* MC_CMD_PORT_RESET_OUT msgresponse */ 4795 #define MC_CMD_PORT_RESET_OUT_LEN 0 4796 4797 4798 /***********************************/ 4799 /* MC_CMD_ENTITY_RESET 4800 * Generic per-resource reset. There is no equivalent for per-board reset. 4801 * Locks required: None; Return code: 0, ETIME. NOTE: This command is an 4802 * extended version of the deprecated MC_CMD_PORT_RESET with added fields. 4803 */ 4804 #define MC_CMD_ENTITY_RESET 0x20 4805 /* MC_CMD_0x20_PRIVILEGE_CTG SRIOV_CTG_GENERAL */ 4806 4807 /* MC_CMD_ENTITY_RESET_IN msgrequest */ 4808 #define MC_CMD_ENTITY_RESET_IN_LEN 4 4809 /* Optional flags field. Omitting this will perform a "legacy" reset action 4810 * (TBD). 4811 */ 4812 #define MC_CMD_ENTITY_RESET_IN_FLAG_OFST 0 4813 #define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_LBN 0 4814 #define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_WIDTH 1 4815 4816 /* MC_CMD_ENTITY_RESET_OUT msgresponse */ 4817 #define MC_CMD_ENTITY_RESET_OUT_LEN 0 4818 4819 4820 /***********************************/ 4821 /* MC_CMD_PCIE_CREDITS 4822 * Read instantaneous and minimum flow control thresholds. 4823 */ 4824 #define MC_CMD_PCIE_CREDITS 0x21 4825 4826 /* MC_CMD_PCIE_CREDITS_IN msgrequest */ 4827 #define MC_CMD_PCIE_CREDITS_IN_LEN 8 4828 /* poll period. 0 is disabled */ 4829 #define MC_CMD_PCIE_CREDITS_IN_POLL_PERIOD_OFST 0 4830 /* wipe statistics */ 4831 #define MC_CMD_PCIE_CREDITS_IN_WIPE_OFST 4 4832 4833 /* MC_CMD_PCIE_CREDITS_OUT msgresponse */ 4834 #define MC_CMD_PCIE_CREDITS_OUT_LEN 16 4835 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_OFST 0 4836 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_LEN 2 4837 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_OFST 2 4838 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_LEN 2 4839 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_OFST 4 4840 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_LEN 2 4841 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_OFST 6 4842 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_LEN 2 4843 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_OFST 8 4844 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_LEN 2 4845 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_OFST 10 4846 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_LEN 2 4847 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_OFST 12 4848 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_LEN 2 4849 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_OFST 14 4850 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_LEN 2 4851 4852 4853 /***********************************/ 4854 /* MC_CMD_RXD_MONITOR 4855 * Get histogram of RX queue fill level. 4856 */ 4857 #define MC_CMD_RXD_MONITOR 0x22 4858 4859 /* MC_CMD_RXD_MONITOR_IN msgrequest */ 4860 #define MC_CMD_RXD_MONITOR_IN_LEN 12 4861 #define MC_CMD_RXD_MONITOR_IN_QID_OFST 0 4862 #define MC_CMD_RXD_MONITOR_IN_POLL_PERIOD_OFST 4 4863 #define MC_CMD_RXD_MONITOR_IN_WIPE_OFST 8 4864 4865 /* MC_CMD_RXD_MONITOR_OUT msgresponse */ 4866 #define MC_CMD_RXD_MONITOR_OUT_LEN 80 4867 #define MC_CMD_RXD_MONITOR_OUT_QID_OFST 0 4868 #define MC_CMD_RXD_MONITOR_OUT_RING_FILL_OFST 4 4869 #define MC_CMD_RXD_MONITOR_OUT_CACHE_FILL_OFST 8 4870 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_1_OFST 12 4871 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_2_OFST 16 4872 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_4_OFST 20 4873 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_8_OFST 24 4874 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_16_OFST 28 4875 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_32_OFST 32 4876 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_64_OFST 36 4877 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_128_OFST 40 4878 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_256_OFST 44 4879 #define MC_CMD_RXD_MONITOR_OUT_RING_GE_256_OFST 48 4880 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_1_OFST 52 4881 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_2_OFST 56 4882 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_4_OFST 60 4883 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_8_OFST 64 4884 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_16_OFST 68 4885 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_32_OFST 72 4886 #define MC_CMD_RXD_MONITOR_OUT_CACHE_GE_32_OFST 76 4887 4888 4889 /***********************************/ 4890 /* MC_CMD_PUTS 4891 * Copy the given ASCII string out onto UART and/or out of the network port. 4892 */ 4893 #define MC_CMD_PUTS 0x23 4894 #undef MC_CMD_0x23_PRIVILEGE_CTG 4895 4896 #define MC_CMD_0x23_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4897 4898 /* MC_CMD_PUTS_IN msgrequest */ 4899 #define MC_CMD_PUTS_IN_LENMIN 13 4900 #define MC_CMD_PUTS_IN_LENMAX 252 4901 #define MC_CMD_PUTS_IN_LEN(num) (12+1*(num)) 4902 #define MC_CMD_PUTS_IN_DEST_OFST 0 4903 #define MC_CMD_PUTS_IN_UART_LBN 0 4904 #define MC_CMD_PUTS_IN_UART_WIDTH 1 4905 #define MC_CMD_PUTS_IN_PORT_LBN 1 4906 #define MC_CMD_PUTS_IN_PORT_WIDTH 1 4907 #define MC_CMD_PUTS_IN_DHOST_OFST 4 4908 #define MC_CMD_PUTS_IN_DHOST_LEN 6 4909 #define MC_CMD_PUTS_IN_STRING_OFST 12 4910 #define MC_CMD_PUTS_IN_STRING_LEN 1 4911 #define MC_CMD_PUTS_IN_STRING_MINNUM 1 4912 #define MC_CMD_PUTS_IN_STRING_MAXNUM 240 4913 4914 /* MC_CMD_PUTS_OUT msgresponse */ 4915 #define MC_CMD_PUTS_OUT_LEN 0 4916 4917 4918 /***********************************/ 4919 /* MC_CMD_GET_PHY_CFG 4920 * Report PHY configuration. This guarantees to succeed even if the PHY is in a 4921 * 'zombie' state. Locks required: None 4922 */ 4923 #define MC_CMD_GET_PHY_CFG 0x24 4924 #undef MC_CMD_0x24_PRIVILEGE_CTG 4925 4926 #define MC_CMD_0x24_PRIVILEGE_CTG SRIOV_CTG_GENERAL 4927 4928 /* MC_CMD_GET_PHY_CFG_IN msgrequest */ 4929 #define MC_CMD_GET_PHY_CFG_IN_LEN 0 4930 4931 /* MC_CMD_GET_PHY_CFG_OUT msgresponse */ 4932 #define MC_CMD_GET_PHY_CFG_OUT_LEN 72 4933 /* flags */ 4934 #define MC_CMD_GET_PHY_CFG_OUT_FLAGS_OFST 0 4935 #define MC_CMD_GET_PHY_CFG_OUT_PRESENT_LBN 0 4936 #define MC_CMD_GET_PHY_CFG_OUT_PRESENT_WIDTH 1 4937 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_LBN 1 4938 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_WIDTH 1 4939 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_LBN 2 4940 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_WIDTH 1 4941 #define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_LBN 3 4942 #define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_WIDTH 1 4943 #define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_LBN 4 4944 #define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_WIDTH 1 4945 #define MC_CMD_GET_PHY_CFG_OUT_TXDIS_LBN 5 4946 #define MC_CMD_GET_PHY_CFG_OUT_TXDIS_WIDTH 1 4947 #define MC_CMD_GET_PHY_CFG_OUT_BIST_LBN 6 4948 #define MC_CMD_GET_PHY_CFG_OUT_BIST_WIDTH 1 4949 /* ?? */ 4950 #define MC_CMD_GET_PHY_CFG_OUT_TYPE_OFST 4 4951 /* Bitmask of supported capabilities */ 4952 #define MC_CMD_GET_PHY_CFG_OUT_SUPPORTED_CAP_OFST 8 4953 #define MC_CMD_PHY_CAP_10HDX_LBN 1 4954 #define MC_CMD_PHY_CAP_10HDX_WIDTH 1 4955 #define MC_CMD_PHY_CAP_10FDX_LBN 2 4956 #define MC_CMD_PHY_CAP_10FDX_WIDTH 1 4957 #define MC_CMD_PHY_CAP_100HDX_LBN 3 4958 #define MC_CMD_PHY_CAP_100HDX_WIDTH 1 4959 #define MC_CMD_PHY_CAP_100FDX_LBN 4 4960 #define MC_CMD_PHY_CAP_100FDX_WIDTH 1 4961 #define MC_CMD_PHY_CAP_1000HDX_LBN 5 4962 #define MC_CMD_PHY_CAP_1000HDX_WIDTH 1 4963 #define MC_CMD_PHY_CAP_1000FDX_LBN 6 4964 #define MC_CMD_PHY_CAP_1000FDX_WIDTH 1 4965 #define MC_CMD_PHY_CAP_10000FDX_LBN 7 4966 #define MC_CMD_PHY_CAP_10000FDX_WIDTH 1 4967 #define MC_CMD_PHY_CAP_PAUSE_LBN 8 4968 #define MC_CMD_PHY_CAP_PAUSE_WIDTH 1 4969 #define MC_CMD_PHY_CAP_ASYM_LBN 9 4970 #define MC_CMD_PHY_CAP_ASYM_WIDTH 1 4971 #define MC_CMD_PHY_CAP_AN_LBN 10 4972 #define MC_CMD_PHY_CAP_AN_WIDTH 1 4973 #define MC_CMD_PHY_CAP_40000FDX_LBN 11 4974 #define MC_CMD_PHY_CAP_40000FDX_WIDTH 1 4975 #define MC_CMD_PHY_CAP_DDM_LBN 12 4976 #define MC_CMD_PHY_CAP_DDM_WIDTH 1 4977 /* ?? */ 4978 #define MC_CMD_GET_PHY_CFG_OUT_CHANNEL_OFST 12 4979 /* ?? */ 4980 #define MC_CMD_GET_PHY_CFG_OUT_PRT_OFST 16 4981 /* ?? */ 4982 #define MC_CMD_GET_PHY_CFG_OUT_STATS_MASK_OFST 20 4983 /* ?? */ 4984 #define MC_CMD_GET_PHY_CFG_OUT_NAME_OFST 24 4985 #define MC_CMD_GET_PHY_CFG_OUT_NAME_LEN 20 4986 /* ?? */ 4987 #define MC_CMD_GET_PHY_CFG_OUT_MEDIA_TYPE_OFST 44 4988 /* enum: Xaui. */ 4989 #define MC_CMD_MEDIA_XAUI 0x1 4990 /* enum: CX4. */ 4991 #define MC_CMD_MEDIA_CX4 0x2 4992 /* enum: KX4. */ 4993 #define MC_CMD_MEDIA_KX4 0x3 4994 /* enum: XFP Far. */ 4995 #define MC_CMD_MEDIA_XFP 0x4 4996 /* enum: SFP+. */ 4997 #define MC_CMD_MEDIA_SFP_PLUS 0x5 4998 /* enum: 10GBaseT. */ 4999 #define MC_CMD_MEDIA_BASE_T 0x6 5000 /* enum: QSFP+. */ 5001 #define MC_CMD_MEDIA_QSFP_PLUS 0x7 5002 #define MC_CMD_GET_PHY_CFG_OUT_MMD_MASK_OFST 48 5003 /* enum: Native clause 22 */ 5004 #define MC_CMD_MMD_CLAUSE22 0x0 5005 #define MC_CMD_MMD_CLAUSE45_PMAPMD 0x1 /* enum */ 5006 #define MC_CMD_MMD_CLAUSE45_WIS 0x2 /* enum */ 5007 #define MC_CMD_MMD_CLAUSE45_PCS 0x3 /* enum */ 5008 #define MC_CMD_MMD_CLAUSE45_PHYXS 0x4 /* enum */ 5009 #define MC_CMD_MMD_CLAUSE45_DTEXS 0x5 /* enum */ 5010 #define MC_CMD_MMD_CLAUSE45_TC 0x6 /* enum */ 5011 #define MC_CMD_MMD_CLAUSE45_AN 0x7 /* enum */ 5012 /* enum: Clause22 proxied over clause45 by PHY. */ 5013 #define MC_CMD_MMD_CLAUSE45_C22EXT 0x1d 5014 #define MC_CMD_MMD_CLAUSE45_VEND1 0x1e /* enum */ 5015 #define MC_CMD_MMD_CLAUSE45_VEND2 0x1f /* enum */ 5016 #define MC_CMD_GET_PHY_CFG_OUT_REVISION_OFST 52 5017 #define MC_CMD_GET_PHY_CFG_OUT_REVISION_LEN 20 5018 5019 5020 /***********************************/ 5021 /* MC_CMD_START_BIST 5022 * Start a BIST test on the PHY. Locks required: PHY_LOCK if doing a PHY BIST 5023 * Return code: 0, EINVAL, EACCES (if PHY_LOCK is not held) 5024 */ 5025 #define MC_CMD_START_BIST 0x25 5026 #undef MC_CMD_0x25_PRIVILEGE_CTG 5027 5028 #define MC_CMD_0x25_PRIVILEGE_CTG SRIOV_CTG_ADMIN 5029 5030 /* MC_CMD_START_BIST_IN msgrequest */ 5031 #define MC_CMD_START_BIST_IN_LEN 4 5032 /* Type of test. */ 5033 #define MC_CMD_START_BIST_IN_TYPE_OFST 0 5034 /* enum: Run the PHY's short cable BIST. */ 5035 #define MC_CMD_PHY_BIST_CABLE_SHORT 0x1 5036 /* enum: Run the PHY's long cable BIST. */ 5037 #define MC_CMD_PHY_BIST_CABLE_LONG 0x2 5038 /* enum: Run BIST on the currently selected BPX Serdes (XAUI or XFI) . */ 5039 #define MC_CMD_BPX_SERDES_BIST 0x3 5040 /* enum: Run the MC loopback tests. */ 5041 #define MC_CMD_MC_LOOPBACK_BIST 0x4 5042 /* enum: Run the PHY's standard BIST. */ 5043 #define MC_CMD_PHY_BIST 0x5 5044 /* enum: Run MC RAM test. */ 5045 #define MC_CMD_MC_MEM_BIST 0x6 5046 /* enum: Run Port RAM test. */ 5047 #define MC_CMD_PORT_MEM_BIST 0x7 5048 /* enum: Run register test. */ 5049 #define MC_CMD_REG_BIST 0x8 5050 5051 /* MC_CMD_START_BIST_OUT msgresponse */ 5052 #define MC_CMD_START_BIST_OUT_LEN 0 5053 5054 5055 /***********************************/ 5056 /* MC_CMD_POLL_BIST 5057 * Poll for BIST completion. Returns a single status code, and optionally some 5058 * PHY specific bist output. The driver should only consume the BIST output 5059 * after validating OUTLEN and MC_CMD_GET_PHY_CFG.TYPE. If a driver can't 5060 * successfully parse the BIST output, it should still respect the pass/Fail in 5061 * OUT.RESULT. Locks required: PHY_LOCK if doing a PHY BIST. Return code: 0, 5062 * EACCES (if PHY_LOCK is not held). 5063 */ 5064 #define MC_CMD_POLL_BIST 0x26 5065 #undef MC_CMD_0x26_PRIVILEGE_CTG 5066 5067 #define MC_CMD_0x26_PRIVILEGE_CTG SRIOV_CTG_ADMIN 5068 5069 /* MC_CMD_POLL_BIST_IN msgrequest */ 5070 #define MC_CMD_POLL_BIST_IN_LEN 0 5071 5072 /* MC_CMD_POLL_BIST_OUT msgresponse */ 5073 #define MC_CMD_POLL_BIST_OUT_LEN 8 5074 /* result */ 5075 #define MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 5076 /* enum: Running. */ 5077 #define MC_CMD_POLL_BIST_RUNNING 0x1 5078 /* enum: Passed. */ 5079 #define MC_CMD_POLL_BIST_PASSED 0x2 5080 /* enum: Failed. */ 5081 #define MC_CMD_POLL_BIST_FAILED 0x3 5082 /* enum: Timed-out. */ 5083 #define MC_CMD_POLL_BIST_TIMEOUT 0x4 5084 #define MC_CMD_POLL_BIST_OUT_PRIVATE_OFST 4 5085 5086 /* MC_CMD_POLL_BIST_OUT_SFT9001 msgresponse */ 5087 #define MC_CMD_POLL_BIST_OUT_SFT9001_LEN 36 5088 /* result */ 5089 /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */ 5090 /* Enum values, see field(s): */ 5091 /* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */ 5092 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A_OFST 4 5093 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B_OFST 8 5094 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C_OFST 12 5095 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D_OFST 16 5096 /* Status of each channel A */ 5097 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_A_OFST 20 5098 /* enum: Ok. */ 5099 #define MC_CMD_POLL_BIST_SFT9001_PAIR_OK 0x1 5100 /* enum: Open. */ 5101 #define MC_CMD_POLL_BIST_SFT9001_PAIR_OPEN 0x2 5102 /* enum: Intra-pair short. */ 5103 #define MC_CMD_POLL_BIST_SFT9001_INTRA_PAIR_SHORT 0x3 5104 /* enum: Inter-pair short. */ 5105 #define MC_CMD_POLL_BIST_SFT9001_INTER_PAIR_SHORT 0x4 5106 /* enum: Busy. */ 5107 #define MC_CMD_POLL_BIST_SFT9001_PAIR_BUSY 0x9 5108 /* Status of each channel B */ 5109 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_B_OFST 24 5110 /* Enum values, see field(s): */ 5111 /* CABLE_STATUS_A */ 5112 /* Status of each channel C */ 5113 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_C_OFST 28 5114 /* Enum values, see field(s): */ 5115 /* CABLE_STATUS_A */ 5116 /* Status of each channel D */ 5117 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_D_OFST 32 5118 /* Enum values, see field(s): */ 5119 /* CABLE_STATUS_A */ 5120 5121 /* MC_CMD_POLL_BIST_OUT_MRSFP msgresponse */ 5122 #define MC_CMD_POLL_BIST_OUT_MRSFP_LEN 8 5123 /* result */ 5124 /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */ 5125 /* Enum values, see field(s): */ 5126 /* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */ 5127 #define MC_CMD_POLL_BIST_OUT_MRSFP_TEST_OFST 4 5128 /* enum: Complete. */ 5129 #define MC_CMD_POLL_BIST_MRSFP_TEST_COMPLETE 0x0 5130 /* enum: Bus switch off I2C write. */ 5131 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_WRITE 0x1 5132 /* enum: Bus switch off I2C no access IO exp. */ 5133 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_IO_EXP 0x2 5134 /* enum: Bus switch off I2C no access module. */ 5135 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_MODULE 0x3 5136 /* enum: IO exp I2C configure. */ 5137 #define MC_CMD_POLL_BIST_MRSFP_TEST_IO_EXP_I2C_CONFIGURE 0x4 5138 /* enum: Bus switch I2C no cross talk. */ 5139 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_I2C_NO_CROSSTALK 0x5 5140 /* enum: Module presence. */ 5141 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_PRESENCE 0x6 5142 /* enum: Module ID I2C access. */ 5143 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_I2C_ACCESS 0x7 5144 /* enum: Module ID sane value. */ 5145 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_SANE_VALUE 0x8 5146 5147 /* MC_CMD_POLL_BIST_OUT_MEM msgresponse */ 5148 #define MC_CMD_POLL_BIST_OUT_MEM_LEN 36 5149 /* result */ 5150 /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */ 5151 /* Enum values, see field(s): */ 5152 /* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */ 5153 #define MC_CMD_POLL_BIST_OUT_MEM_TEST_OFST 4 5154 /* enum: Test has completed. */ 5155 #define MC_CMD_POLL_BIST_MEM_COMPLETE 0x0 5156 /* enum: RAM test - walk ones. */ 5157 #define MC_CMD_POLL_BIST_MEM_MEM_WALK_ONES 0x1 5158 /* enum: RAM test - walk zeros. */ 5159 #define MC_CMD_POLL_BIST_MEM_MEM_WALK_ZEROS 0x2 5160 /* enum: RAM test - walking inversions zeros/ones. */ 5161 #define MC_CMD_POLL_BIST_MEM_MEM_INV_ZERO_ONE 0x3 5162 /* enum: RAM test - walking inversions checkerboard. */ 5163 #define MC_CMD_POLL_BIST_MEM_MEM_INV_CHKBOARD 0x4 5164 /* enum: Register test - set / clear individual bits. */ 5165 #define MC_CMD_POLL_BIST_MEM_REG 0x5 5166 /* enum: ECC error detected. */ 5167 #define MC_CMD_POLL_BIST_MEM_ECC 0x6 5168 /* Failure address, only valid if result is POLL_BIST_FAILED */ 5169 #define MC_CMD_POLL_BIST_OUT_MEM_ADDR_OFST 8 5170 /* Bus or address space to which the failure address corresponds */ 5171 #define MC_CMD_POLL_BIST_OUT_MEM_BUS_OFST 12 5172 /* enum: MC MIPS bus. */ 5173 #define MC_CMD_POLL_BIST_MEM_BUS_MC 0x0 5174 /* enum: CSR IREG bus. */ 5175 #define MC_CMD_POLL_BIST_MEM_BUS_CSR 0x1 5176 /* enum: RX0 DPCPU bus. */ 5177 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_RX 0x2 5178 /* enum: TX0 DPCPU bus. */ 5179 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX0 0x3 5180 /* enum: TX1 DPCPU bus. */ 5181 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX1 0x4 5182 /* enum: RX0 DICPU bus. */ 5183 #define MC_CMD_POLL_BIST_MEM_BUS_DICPU_RX 0x5 5184 /* enum: TX DICPU bus. */ 5185 #define MC_CMD_POLL_BIST_MEM_BUS_DICPU_TX 0x6 5186 /* enum: RX1 DPCPU bus. */ 5187 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_RX1 0x7 5188 /* enum: RX1 DICPU bus. */ 5189 #define MC_CMD_POLL_BIST_MEM_BUS_DICPU_RX1 0x8 5190 /* Pattern written to RAM / register */ 5191 #define MC_CMD_POLL_BIST_OUT_MEM_EXPECT_OFST 16 5192 /* Actual value read from RAM / register */ 5193 #define MC_CMD_POLL_BIST_OUT_MEM_ACTUAL_OFST 20 5194 /* ECC error mask */ 5195 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_OFST 24 5196 /* ECC parity error mask */ 5197 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_PARITY_OFST 28 5198 /* ECC fatal error mask */ 5199 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_FATAL_OFST 32 5200 5201 5202 /***********************************/ 5203 /* MC_CMD_FLUSH_RX_QUEUES 5204 * Flush receive queue(s). If SRIOV is enabled (via MC_CMD_SRIOV), then RXQ 5205 * flushes should be initiated via this MCDI operation, rather than via 5206 * directly writing FLUSH_CMD. 5207 * 5208 * The flush is completed (either done/fail) asynchronously (after this command 5209 * returns). The driver must still wait for flush done/failure events as usual. 5210 */ 5211 #define MC_CMD_FLUSH_RX_QUEUES 0x27 5212 5213 /* MC_CMD_FLUSH_RX_QUEUES_IN msgrequest */ 5214 #define MC_CMD_FLUSH_RX_QUEUES_IN_LENMIN 4 5215 #define MC_CMD_FLUSH_RX_QUEUES_IN_LENMAX 252 5216 #define MC_CMD_FLUSH_RX_QUEUES_IN_LEN(num) (0+4*(num)) 5217 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_OFST 0 5218 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_LEN 4 5219 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MINNUM 1 5220 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MAXNUM 63 5221 5222 /* MC_CMD_FLUSH_RX_QUEUES_OUT msgresponse */ 5223 #define MC_CMD_FLUSH_RX_QUEUES_OUT_LEN 0 5224 5225 5226 /***********************************/ 5227 /* MC_CMD_GET_LOOPBACK_MODES 5228 * Returns a bitmask of loopback modes available at each speed. 5229 */ 5230 #define MC_CMD_GET_LOOPBACK_MODES 0x28 5231 #undef MC_CMD_0x28_PRIVILEGE_CTG 5232 5233 #define MC_CMD_0x28_PRIVILEGE_CTG SRIOV_CTG_GENERAL 5234 5235 /* MC_CMD_GET_LOOPBACK_MODES_IN msgrequest */ 5236 #define MC_CMD_GET_LOOPBACK_MODES_IN_LEN 0 5237 5238 /* MC_CMD_GET_LOOPBACK_MODES_OUT msgresponse */ 5239 #define MC_CMD_GET_LOOPBACK_MODES_OUT_LEN 40 5240 /* Supported loopbacks. */ 5241 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_OFST 0 5242 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LEN 8 5243 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_OFST 0 5244 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_OFST 4 5245 /* enum: None. */ 5246 #define MC_CMD_LOOPBACK_NONE 0x0 5247 /* enum: Data. */ 5248 #define MC_CMD_LOOPBACK_DATA 0x1 5249 /* enum: GMAC. */ 5250 #define MC_CMD_LOOPBACK_GMAC 0x2 5251 /* enum: XGMII. */ 5252 #define MC_CMD_LOOPBACK_XGMII 0x3 5253 /* enum: XGXS. */ 5254 #define MC_CMD_LOOPBACK_XGXS 0x4 5255 /* enum: XAUI. */ 5256 #define MC_CMD_LOOPBACK_XAUI 0x5 5257 /* enum: GMII. */ 5258 #define MC_CMD_LOOPBACK_GMII 0x6 5259 /* enum: SGMII. */ 5260 #define MC_CMD_LOOPBACK_SGMII 0x7 5261 /* enum: XGBR. */ 5262 #define MC_CMD_LOOPBACK_XGBR 0x8 5263 /* enum: XFI. */ 5264 #define MC_CMD_LOOPBACK_XFI 0x9 5265 /* enum: XAUI Far. */ 5266 #define MC_CMD_LOOPBACK_XAUI_FAR 0xa 5267 /* enum: GMII Far. */ 5268 #define MC_CMD_LOOPBACK_GMII_FAR 0xb 5269 /* enum: SGMII Far. */ 5270 #define MC_CMD_LOOPBACK_SGMII_FAR 0xc 5271 /* enum: XFI Far. */ 5272 #define MC_CMD_LOOPBACK_XFI_FAR 0xd 5273 /* enum: GPhy. */ 5274 #define MC_CMD_LOOPBACK_GPHY 0xe 5275 /* enum: PhyXS. */ 5276 #define MC_CMD_LOOPBACK_PHYXS 0xf 5277 /* enum: PCS. */ 5278 #define MC_CMD_LOOPBACK_PCS 0x10 5279 /* enum: PMA-PMD. */ 5280 #define MC_CMD_LOOPBACK_PMAPMD 0x11 5281 /* enum: Cross-Port. */ 5282 #define MC_CMD_LOOPBACK_XPORT 0x12 5283 /* enum: XGMII-Wireside. */ 5284 #define MC_CMD_LOOPBACK_XGMII_WS 0x13 5285 /* enum: XAUI Wireside. */ 5286 #define MC_CMD_LOOPBACK_XAUI_WS 0x14 5287 /* enum: XAUI Wireside Far. */ 5288 #define MC_CMD_LOOPBACK_XAUI_WS_FAR 0x15 5289 /* enum: XAUI Wireside near. */ 5290 #define MC_CMD_LOOPBACK_XAUI_WS_NEAR 0x16 5291 /* enum: GMII Wireside. */ 5292 #define MC_CMD_LOOPBACK_GMII_WS 0x17 5293 /* enum: XFI Wireside. */ 5294 #define MC_CMD_LOOPBACK_XFI_WS 0x18 5295 /* enum: XFI Wireside Far. */ 5296 #define MC_CMD_LOOPBACK_XFI_WS_FAR 0x19 5297 /* enum: PhyXS Wireside. */ 5298 #define MC_CMD_LOOPBACK_PHYXS_WS 0x1a 5299 /* enum: PMA lanes MAC-Serdes. */ 5300 #define MC_CMD_LOOPBACK_PMA_INT 0x1b 5301 /* enum: KR Serdes Parallel (Encoder). */ 5302 #define MC_CMD_LOOPBACK_SD_NEAR 0x1c 5303 /* enum: KR Serdes Serial. */ 5304 #define MC_CMD_LOOPBACK_SD_FAR 0x1d 5305 /* enum: PMA lanes MAC-Serdes Wireside. */ 5306 #define MC_CMD_LOOPBACK_PMA_INT_WS 0x1e 5307 /* enum: KR Serdes Parallel Wireside (Full PCS). */ 5308 #define MC_CMD_LOOPBACK_SD_FEP2_WS 0x1f 5309 /* enum: KR Serdes Parallel Wireside (Sym Aligner to TX). */ 5310 #define MC_CMD_LOOPBACK_SD_FEP1_5_WS 0x20 5311 /* enum: KR Serdes Parallel Wireside (Deserializer to Serializer). */ 5312 #define MC_CMD_LOOPBACK_SD_FEP_WS 0x21 5313 /* enum: KR Serdes Serial Wireside. */ 5314 #define MC_CMD_LOOPBACK_SD_FES_WS 0x22 5315 /* enum: Near side of AOE Siena side port */ 5316 #define MC_CMD_LOOPBACK_AOE_INT_NEAR 0x23 5317 /* enum: Medford Wireside datapath loopback */ 5318 #define MC_CMD_LOOPBACK_DATA_WS 0x24 5319 /* enum: Force link up without setting up any physical loopback (snapper use 5320 * only) 5321 */ 5322 #define MC_CMD_LOOPBACK_FORCE_EXT_LINK 0x25 5323 /* Supported loopbacks. */ 5324 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_OFST 8 5325 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LEN 8 5326 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LO_OFST 8 5327 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_HI_OFST 12 5328 /* Enum values, see field(s): */ 5329 /* 100M */ 5330 /* Supported loopbacks. */ 5331 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_OFST 16 5332 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LEN 8 5333 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LO_OFST 16 5334 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_HI_OFST 20 5335 /* Enum values, see field(s): */ 5336 /* 100M */ 5337 /* Supported loopbacks. */ 5338 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_OFST 24 5339 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LEN 8 5340 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LO_OFST 24 5341 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_HI_OFST 28 5342 /* Enum values, see field(s): */ 5343 /* 100M */ 5344 /* Supported loopbacks. */ 5345 #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_OFST 32 5346 #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LEN 8 5347 #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LO_OFST 32 5348 #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_HI_OFST 36 5349 /* Enum values, see field(s): */ 5350 /* 100M */ 5351 5352 5353 /***********************************/ 5354 /* MC_CMD_GET_LINK 5355 * Read the unified MAC/PHY link state. Locks required: None Return code: 0, 5356 * ETIME. 5357 */ 5358 #define MC_CMD_GET_LINK 0x29 5359 #undef MC_CMD_0x29_PRIVILEGE_CTG 5360 5361 #define MC_CMD_0x29_PRIVILEGE_CTG SRIOV_CTG_GENERAL 5362 5363 /* MC_CMD_GET_LINK_IN msgrequest */ 5364 #define MC_CMD_GET_LINK_IN_LEN 0 5365 5366 /* MC_CMD_GET_LINK_OUT msgresponse */ 5367 #define MC_CMD_GET_LINK_OUT_LEN 28 5368 /* near-side advertised capabilities */ 5369 #define MC_CMD_GET_LINK_OUT_CAP_OFST 0 5370 /* link-partner advertised capabilities */ 5371 #define MC_CMD_GET_LINK_OUT_LP_CAP_OFST 4 5372 /* Autonegotiated speed in mbit/s. The link may still be down even if this 5373 * reads non-zero. 5374 */ 5375 #define MC_CMD_GET_LINK_OUT_LINK_SPEED_OFST 8 5376 /* Current loopback setting. */ 5377 #define MC_CMD_GET_LINK_OUT_LOOPBACK_MODE_OFST 12 5378 /* Enum values, see field(s): */ 5379 /* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */ 5380 #define MC_CMD_GET_LINK_OUT_FLAGS_OFST 16 5381 #define MC_CMD_GET_LINK_OUT_LINK_UP_LBN 0 5382 #define MC_CMD_GET_LINK_OUT_LINK_UP_WIDTH 1 5383 #define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_LBN 1 5384 #define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_WIDTH 1 5385 #define MC_CMD_GET_LINK_OUT_BPX_LINK_LBN 2 5386 #define MC_CMD_GET_LINK_OUT_BPX_LINK_WIDTH 1 5387 #define MC_CMD_GET_LINK_OUT_PHY_LINK_LBN 3 5388 #define MC_CMD_GET_LINK_OUT_PHY_LINK_WIDTH 1 5389 #define MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_LBN 6 5390 #define MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_WIDTH 1 5391 #define MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_LBN 7 5392 #define MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_WIDTH 1 5393 /* This returns the negotiated flow control value. */ 5394 #define MC_CMD_GET_LINK_OUT_FCNTL_OFST 20 5395 /* Enum values, see field(s): */ 5396 /* MC_CMD_SET_MAC/MC_CMD_SET_MAC_IN/FCNTL */ 5397 #define MC_CMD_GET_LINK_OUT_MAC_FAULT_OFST 24 5398 #define MC_CMD_MAC_FAULT_XGMII_LOCAL_LBN 0 5399 #define MC_CMD_MAC_FAULT_XGMII_LOCAL_WIDTH 1 5400 #define MC_CMD_MAC_FAULT_XGMII_REMOTE_LBN 1 5401 #define MC_CMD_MAC_FAULT_XGMII_REMOTE_WIDTH 1 5402 #define MC_CMD_MAC_FAULT_SGMII_REMOTE_LBN 2 5403 #define MC_CMD_MAC_FAULT_SGMII_REMOTE_WIDTH 1 5404 #define MC_CMD_MAC_FAULT_PENDING_RECONFIG_LBN 3 5405 #define MC_CMD_MAC_FAULT_PENDING_RECONFIG_WIDTH 1 5406 5407 5408 /***********************************/ 5409 /* MC_CMD_SET_LINK 5410 * Write the unified MAC/PHY link configuration. Locks required: None. Return 5411 * code: 0, EINVAL, ETIME 5412 */ 5413 #define MC_CMD_SET_LINK 0x2a 5414 #undef MC_CMD_0x2a_PRIVILEGE_CTG 5415 5416 #define MC_CMD_0x2a_PRIVILEGE_CTG SRIOV_CTG_LINK 5417 5418 /* MC_CMD_SET_LINK_IN msgrequest */ 5419 #define MC_CMD_SET_LINK_IN_LEN 16 5420 /* ??? */ 5421 #define MC_CMD_SET_LINK_IN_CAP_OFST 0 5422 /* Flags */ 5423 #define MC_CMD_SET_LINK_IN_FLAGS_OFST 4 5424 #define MC_CMD_SET_LINK_IN_LOWPOWER_LBN 0 5425 #define MC_CMD_SET_LINK_IN_LOWPOWER_WIDTH 1 5426 #define MC_CMD_SET_LINK_IN_POWEROFF_LBN 1 5427 #define MC_CMD_SET_LINK_IN_POWEROFF_WIDTH 1 5428 #define MC_CMD_SET_LINK_IN_TXDIS_LBN 2 5429 #define MC_CMD_SET_LINK_IN_TXDIS_WIDTH 1 5430 /* Loopback mode. */ 5431 #define MC_CMD_SET_LINK_IN_LOOPBACK_MODE_OFST 8 5432 /* Enum values, see field(s): */ 5433 /* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */ 5434 /* A loopback speed of "0" is supported, and means (choose any available 5435 * speed). 5436 */ 5437 #define MC_CMD_SET_LINK_IN_LOOPBACK_SPEED_OFST 12 5438 5439 /* MC_CMD_SET_LINK_OUT msgresponse */ 5440 #define MC_CMD_SET_LINK_OUT_LEN 0 5441 5442 5443 /***********************************/ 5444 /* MC_CMD_SET_ID_LED 5445 * Set identification LED state. Locks required: None. Return code: 0, EINVAL 5446 */ 5447 #define MC_CMD_SET_ID_LED 0x2b 5448 #undef MC_CMD_0x2b_PRIVILEGE_CTG 5449 5450 #define MC_CMD_0x2b_PRIVILEGE_CTG SRIOV_CTG_LINK 5451 5452 /* MC_CMD_SET_ID_LED_IN msgrequest */ 5453 #define MC_CMD_SET_ID_LED_IN_LEN 4 5454 /* Set LED state. */ 5455 #define MC_CMD_SET_ID_LED_IN_STATE_OFST 0 5456 #define MC_CMD_LED_OFF 0x0 /* enum */ 5457 #define MC_CMD_LED_ON 0x1 /* enum */ 5458 #define MC_CMD_LED_DEFAULT 0x2 /* enum */ 5459 5460 /* MC_CMD_SET_ID_LED_OUT msgresponse */ 5461 #define MC_CMD_SET_ID_LED_OUT_LEN 0 5462 5463 5464 /***********************************/ 5465 /* MC_CMD_SET_MAC 5466 * Set MAC configuration. Locks required: None. Return code: 0, EINVAL 5467 */ 5468 #define MC_CMD_SET_MAC 0x2c 5469 #undef MC_CMD_0x2c_PRIVILEGE_CTG 5470 5471 #define MC_CMD_0x2c_PRIVILEGE_CTG SRIOV_CTG_GENERAL 5472 5473 /* MC_CMD_SET_MAC_IN msgrequest */ 5474 #define MC_CMD_SET_MAC_IN_LEN 28 5475 /* The MTU is the MTU programmed directly into the XMAC/GMAC (inclusive of 5476 * EtherII, VLAN, bug16011 padding). 5477 */ 5478 #define MC_CMD_SET_MAC_IN_MTU_OFST 0 5479 #define MC_CMD_SET_MAC_IN_DRAIN_OFST 4 5480 #define MC_CMD_SET_MAC_IN_ADDR_OFST 8 5481 #define MC_CMD_SET_MAC_IN_ADDR_LEN 8 5482 #define MC_CMD_SET_MAC_IN_ADDR_LO_OFST 8 5483 #define MC_CMD_SET_MAC_IN_ADDR_HI_OFST 12 5484 #define MC_CMD_SET_MAC_IN_REJECT_OFST 16 5485 #define MC_CMD_SET_MAC_IN_REJECT_UNCST_LBN 0 5486 #define MC_CMD_SET_MAC_IN_REJECT_UNCST_WIDTH 1 5487 #define MC_CMD_SET_MAC_IN_REJECT_BRDCST_LBN 1 5488 #define MC_CMD_SET_MAC_IN_REJECT_BRDCST_WIDTH 1 5489 #define MC_CMD_SET_MAC_IN_FCNTL_OFST 20 5490 /* enum: Flow control is off. */ 5491 #define MC_CMD_FCNTL_OFF 0x0 5492 /* enum: Respond to flow control. */ 5493 #define MC_CMD_FCNTL_RESPOND 0x1 5494 /* enum: Respond to and Issue flow control. */ 5495 #define MC_CMD_FCNTL_BIDIR 0x2 5496 /* enum: Auto neg flow control. */ 5497 #define MC_CMD_FCNTL_AUTO 0x3 5498 /* enum: Priority flow control (eftest builds only). */ 5499 #define MC_CMD_FCNTL_QBB 0x4 5500 /* enum: Issue flow control. */ 5501 #define MC_CMD_FCNTL_GENERATE 0x5 5502 #define MC_CMD_SET_MAC_IN_FLAGS_OFST 24 5503 #define MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_LBN 0 5504 #define MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_WIDTH 1 5505 5506 /* MC_CMD_SET_MAC_EXT_IN msgrequest */ 5507 #define MC_CMD_SET_MAC_EXT_IN_LEN 32 5508 /* The MTU is the MTU programmed directly into the XMAC/GMAC (inclusive of 5509 * EtherII, VLAN, bug16011 padding). 5510 */ 5511 #define MC_CMD_SET_MAC_EXT_IN_MTU_OFST 0 5512 #define MC_CMD_SET_MAC_EXT_IN_DRAIN_OFST 4 5513 #define MC_CMD_SET_MAC_EXT_IN_ADDR_OFST 8 5514 #define MC_CMD_SET_MAC_EXT_IN_ADDR_LEN 8 5515 #define MC_CMD_SET_MAC_EXT_IN_ADDR_LO_OFST 8 5516 #define MC_CMD_SET_MAC_EXT_IN_ADDR_HI_OFST 12 5517 #define MC_CMD_SET_MAC_EXT_IN_REJECT_OFST 16 5518 #define MC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_LBN 0 5519 #define MC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_WIDTH 1 5520 #define MC_CMD_SET_MAC_EXT_IN_REJECT_BRDCST_LBN 1 5521 #define MC_CMD_SET_MAC_EXT_IN_REJECT_BRDCST_WIDTH 1 5522 #define MC_CMD_SET_MAC_EXT_IN_FCNTL_OFST 20 5523 /* enum: Flow control is off. */ 5524 /* MC_CMD_FCNTL_OFF 0x0 */ 5525 /* enum: Respond to flow control. */ 5526 /* MC_CMD_FCNTL_RESPOND 0x1 */ 5527 /* enum: Respond to and Issue flow control. */ 5528 /* MC_CMD_FCNTL_BIDIR 0x2 */ 5529 /* enum: Auto neg flow control. */ 5530 /* MC_CMD_FCNTL_AUTO 0x3 */ 5531 /* enum: Priority flow control (eftest builds only). */ 5532 /* MC_CMD_FCNTL_QBB 0x4 */ 5533 /* enum: Issue flow control. */ 5534 /* MC_CMD_FCNTL_GENERATE 0x5 */ 5535 #define MC_CMD_SET_MAC_EXT_IN_FLAGS_OFST 24 5536 #define MC_CMD_SET_MAC_EXT_IN_FLAG_INCLUDE_FCS_LBN 0 5537 #define MC_CMD_SET_MAC_EXT_IN_FLAG_INCLUDE_FCS_WIDTH 1 5538 /* Select which parameters to configure. A parameter will only be modified if 5539 * the corresponding control flag is set. If SET_MAC_ENHANCED is not set in 5540 * capabilities then this field is ignored (and all flags are assumed to be 5541 * set). 5542 */ 5543 #define MC_CMD_SET_MAC_EXT_IN_CONTROL_OFST 28 5544 #define MC_CMD_SET_MAC_EXT_IN_CFG_MTU_LBN 0 5545 #define MC_CMD_SET_MAC_EXT_IN_CFG_MTU_WIDTH 1 5546 #define MC_CMD_SET_MAC_EXT_IN_CFG_DRAIN_LBN 1 5547 #define MC_CMD_SET_MAC_EXT_IN_CFG_DRAIN_WIDTH 1 5548 #define MC_CMD_SET_MAC_EXT_IN_CFG_REJECT_LBN 2 5549 #define MC_CMD_SET_MAC_EXT_IN_CFG_REJECT_WIDTH 1 5550 #define MC_CMD_SET_MAC_EXT_IN_CFG_FCNTL_LBN 3 5551 #define MC_CMD_SET_MAC_EXT_IN_CFG_FCNTL_WIDTH 1 5552 #define MC_CMD_SET_MAC_EXT_IN_CFG_FCS_LBN 4 5553 #define MC_CMD_SET_MAC_EXT_IN_CFG_FCS_WIDTH 1 5554 5555 /* MC_CMD_SET_MAC_OUT msgresponse */ 5556 #define MC_CMD_SET_MAC_OUT_LEN 0 5557 5558 /* MC_CMD_SET_MAC_V2_OUT msgresponse */ 5559 #define MC_CMD_SET_MAC_V2_OUT_LEN 4 5560 /* MTU as configured after processing the request. See comment at 5561 * MC_CMD_SET_MAC_IN/MTU. To query MTU without doing any changes, set CONTROL 5562 * to 0. 5563 */ 5564 #define MC_CMD_SET_MAC_V2_OUT_MTU_OFST 0 5565 5566 5567 /***********************************/ 5568 /* MC_CMD_PHY_STATS 5569 * Get generic PHY statistics. This call returns the statistics for a generic 5570 * PHY in a sparse array (indexed by the enumerate). Each value is represented 5571 * by a 32bit number. If the DMA_ADDR is 0, then no DMA is performed, and the 5572 * statistics may be read from the message response. If DMA_ADDR != 0, then the 5573 * statistics are dmad to that (page-aligned location). Locks required: None. 5574 * Returns: 0, ETIME 5575 */ 5576 #define MC_CMD_PHY_STATS 0x2d 5577 #undef MC_CMD_0x2d_PRIVILEGE_CTG 5578 5579 #define MC_CMD_0x2d_PRIVILEGE_CTG SRIOV_CTG_LINK 5580 5581 /* MC_CMD_PHY_STATS_IN msgrequest */ 5582 #define MC_CMD_PHY_STATS_IN_LEN 8 5583 /* ??? */ 5584 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_OFST 0 5585 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_LEN 8 5586 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_OFST 0 5587 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_HI_OFST 4 5588 5589 /* MC_CMD_PHY_STATS_OUT_DMA msgresponse */ 5590 #define MC_CMD_PHY_STATS_OUT_DMA_LEN 0 5591 5592 /* MC_CMD_PHY_STATS_OUT_NO_DMA msgresponse */ 5593 #define MC_CMD_PHY_STATS_OUT_NO_DMA_LEN (((MC_CMD_PHY_NSTATS*32))>>3) 5594 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_OFST 0 5595 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_LEN 4 5596 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_PHY_NSTATS 5597 /* enum: OUI. */ 5598 #define MC_CMD_OUI 0x0 5599 /* enum: PMA-PMD Link Up. */ 5600 #define MC_CMD_PMA_PMD_LINK_UP 0x1 5601 /* enum: PMA-PMD RX Fault. */ 5602 #define MC_CMD_PMA_PMD_RX_FAULT 0x2 5603 /* enum: PMA-PMD TX Fault. */ 5604 #define MC_CMD_PMA_PMD_TX_FAULT 0x3 5605 /* enum: PMA-PMD Signal */ 5606 #define MC_CMD_PMA_PMD_SIGNAL 0x4 5607 /* enum: PMA-PMD SNR A. */ 5608 #define MC_CMD_PMA_PMD_SNR_A 0x5 5609 /* enum: PMA-PMD SNR B. */ 5610 #define MC_CMD_PMA_PMD_SNR_B 0x6 5611 /* enum: PMA-PMD SNR C. */ 5612 #define MC_CMD_PMA_PMD_SNR_C 0x7 5613 /* enum: PMA-PMD SNR D. */ 5614 #define MC_CMD_PMA_PMD_SNR_D 0x8 5615 /* enum: PCS Link Up. */ 5616 #define MC_CMD_PCS_LINK_UP 0x9 5617 /* enum: PCS RX Fault. */ 5618 #define MC_CMD_PCS_RX_FAULT 0xa 5619 /* enum: PCS TX Fault. */ 5620 #define MC_CMD_PCS_TX_FAULT 0xb 5621 /* enum: PCS BER. */ 5622 #define MC_CMD_PCS_BER 0xc 5623 /* enum: PCS Block Errors. */ 5624 #define MC_CMD_PCS_BLOCK_ERRORS 0xd 5625 /* enum: PhyXS Link Up. */ 5626 #define MC_CMD_PHYXS_LINK_UP 0xe 5627 /* enum: PhyXS RX Fault. */ 5628 #define MC_CMD_PHYXS_RX_FAULT 0xf 5629 /* enum: PhyXS TX Fault. */ 5630 #define MC_CMD_PHYXS_TX_FAULT 0x10 5631 /* enum: PhyXS Align. */ 5632 #define MC_CMD_PHYXS_ALIGN 0x11 5633 /* enum: PhyXS Sync. */ 5634 #define MC_CMD_PHYXS_SYNC 0x12 5635 /* enum: AN link-up. */ 5636 #define MC_CMD_AN_LINK_UP 0x13 5637 /* enum: AN Complete. */ 5638 #define MC_CMD_AN_COMPLETE 0x14 5639 /* enum: AN 10GBaseT Status. */ 5640 #define MC_CMD_AN_10GBT_STATUS 0x15 5641 /* enum: Clause 22 Link-Up. */ 5642 #define MC_CMD_CL22_LINK_UP 0x16 5643 /* enum: (Last entry) */ 5644 #define MC_CMD_PHY_NSTATS 0x17 5645 5646 5647 /***********************************/ 5648 /* MC_CMD_MAC_STATS 5649 * Get generic MAC statistics. This call returns unified statistics maintained 5650 * by the MC as it switches between the GMAC and XMAC. The MC will write out 5651 * all supported stats. The driver should zero initialise the buffer to 5652 * guarantee consistent results. If the DMA_ADDR is 0, then no DMA is 5653 * performed, and the statistics may be read from the message response. If 5654 * DMA_ADDR != 0, then the statistics are dmad to that (page-aligned location). 5655 * Locks required: None. The PERIODIC_CLEAR option is not used and now has no 5656 * effect. Returns: 0, ETIME 5657 */ 5658 #define MC_CMD_MAC_STATS 0x2e 5659 #undef MC_CMD_0x2e_PRIVILEGE_CTG 5660 5661 #define MC_CMD_0x2e_PRIVILEGE_CTG SRIOV_CTG_GENERAL 5662 5663 /* MC_CMD_MAC_STATS_IN msgrequest */ 5664 #define MC_CMD_MAC_STATS_IN_LEN 20 5665 /* ??? */ 5666 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_OFST 0 5667 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_LEN 8 5668 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_OFST 0 5669 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_OFST 4 5670 #define MC_CMD_MAC_STATS_IN_CMD_OFST 8 5671 #define MC_CMD_MAC_STATS_IN_DMA_LBN 0 5672 #define MC_CMD_MAC_STATS_IN_DMA_WIDTH 1 5673 #define MC_CMD_MAC_STATS_IN_CLEAR_LBN 1 5674 #define MC_CMD_MAC_STATS_IN_CLEAR_WIDTH 1 5675 #define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_LBN 2 5676 #define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_WIDTH 1 5677 #define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_LBN 3 5678 #define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_WIDTH 1 5679 #define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_LBN 4 5680 #define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_WIDTH 1 5681 #define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_LBN 5 5682 #define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_WIDTH 1 5683 #define MC_CMD_MAC_STATS_IN_PERIOD_MS_LBN 16 5684 #define MC_CMD_MAC_STATS_IN_PERIOD_MS_WIDTH 16 5685 #define MC_CMD_MAC_STATS_IN_DMA_LEN_OFST 12 5686 /* port id so vadapter stats can be provided */ 5687 #define MC_CMD_MAC_STATS_IN_PORT_ID_OFST 16 5688 5689 /* MC_CMD_MAC_STATS_OUT_DMA msgresponse */ 5690 #define MC_CMD_MAC_STATS_OUT_DMA_LEN 0 5691 5692 /* MC_CMD_MAC_STATS_OUT_NO_DMA msgresponse */ 5693 #define MC_CMD_MAC_STATS_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS*64))>>3) 5694 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_OFST 0 5695 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LEN 8 5696 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_OFST 0 5697 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_OFST 4 5698 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS 5699 #define MC_CMD_MAC_GENERATION_START 0x0 /* enum */ 5700 #define MC_CMD_MAC_DMABUF_START 0x1 /* enum */ 5701 #define MC_CMD_MAC_TX_PKTS 0x1 /* enum */ 5702 #define MC_CMD_MAC_TX_PAUSE_PKTS 0x2 /* enum */ 5703 #define MC_CMD_MAC_TX_CONTROL_PKTS 0x3 /* enum */ 5704 #define MC_CMD_MAC_TX_UNICAST_PKTS 0x4 /* enum */ 5705 #define MC_CMD_MAC_TX_MULTICAST_PKTS 0x5 /* enum */ 5706 #define MC_CMD_MAC_TX_BROADCAST_PKTS 0x6 /* enum */ 5707 #define MC_CMD_MAC_TX_BYTES 0x7 /* enum */ 5708 #define MC_CMD_MAC_TX_BAD_BYTES 0x8 /* enum */ 5709 #define MC_CMD_MAC_TX_LT64_PKTS 0x9 /* enum */ 5710 #define MC_CMD_MAC_TX_64_PKTS 0xa /* enum */ 5711 #define MC_CMD_MAC_TX_65_TO_127_PKTS 0xb /* enum */ 5712 #define MC_CMD_MAC_TX_128_TO_255_PKTS 0xc /* enum */ 5713 #define MC_CMD_MAC_TX_256_TO_511_PKTS 0xd /* enum */ 5714 #define MC_CMD_MAC_TX_512_TO_1023_PKTS 0xe /* enum */ 5715 #define MC_CMD_MAC_TX_1024_TO_15XX_PKTS 0xf /* enum */ 5716 #define MC_CMD_MAC_TX_15XX_TO_JUMBO_PKTS 0x10 /* enum */ 5717 #define MC_CMD_MAC_TX_GTJUMBO_PKTS 0x11 /* enum */ 5718 #define MC_CMD_MAC_TX_BAD_FCS_PKTS 0x12 /* enum */ 5719 #define MC_CMD_MAC_TX_SINGLE_COLLISION_PKTS 0x13 /* enum */ 5720 #define MC_CMD_MAC_TX_MULTIPLE_COLLISION_PKTS 0x14 /* enum */ 5721 #define MC_CMD_MAC_TX_EXCESSIVE_COLLISION_PKTS 0x15 /* enum */ 5722 #define MC_CMD_MAC_TX_LATE_COLLISION_PKTS 0x16 /* enum */ 5723 #define MC_CMD_MAC_TX_DEFERRED_PKTS 0x17 /* enum */ 5724 #define MC_CMD_MAC_TX_EXCESSIVE_DEFERRED_PKTS 0x18 /* enum */ 5725 #define MC_CMD_MAC_TX_NON_TCPUDP_PKTS 0x19 /* enum */ 5726 #define MC_CMD_MAC_TX_MAC_SRC_ERR_PKTS 0x1a /* enum */ 5727 #define MC_CMD_MAC_TX_IP_SRC_ERR_PKTS 0x1b /* enum */ 5728 #define MC_CMD_MAC_RX_PKTS 0x1c /* enum */ 5729 #define MC_CMD_MAC_RX_PAUSE_PKTS 0x1d /* enum */ 5730 #define MC_CMD_MAC_RX_GOOD_PKTS 0x1e /* enum */ 5731 #define MC_CMD_MAC_RX_CONTROL_PKTS 0x1f /* enum */ 5732 #define MC_CMD_MAC_RX_UNICAST_PKTS 0x20 /* enum */ 5733 #define MC_CMD_MAC_RX_MULTICAST_PKTS 0x21 /* enum */ 5734 #define MC_CMD_MAC_RX_BROADCAST_PKTS 0x22 /* enum */ 5735 #define MC_CMD_MAC_RX_BYTES 0x23 /* enum */ 5736 #define MC_CMD_MAC_RX_BAD_BYTES 0x24 /* enum */ 5737 #define MC_CMD_MAC_RX_64_PKTS 0x25 /* enum */ 5738 #define MC_CMD_MAC_RX_65_TO_127_PKTS 0x26 /* enum */ 5739 #define MC_CMD_MAC_RX_128_TO_255_PKTS 0x27 /* enum */ 5740 #define MC_CMD_MAC_RX_256_TO_511_PKTS 0x28 /* enum */ 5741 #define MC_CMD_MAC_RX_512_TO_1023_PKTS 0x29 /* enum */ 5742 #define MC_CMD_MAC_RX_1024_TO_15XX_PKTS 0x2a /* enum */ 5743 #define MC_CMD_MAC_RX_15XX_TO_JUMBO_PKTS 0x2b /* enum */ 5744 #define MC_CMD_MAC_RX_GTJUMBO_PKTS 0x2c /* enum */ 5745 #define MC_CMD_MAC_RX_UNDERSIZE_PKTS 0x2d /* enum */ 5746 #define MC_CMD_MAC_RX_BAD_FCS_PKTS 0x2e /* enum */ 5747 #define MC_CMD_MAC_RX_OVERFLOW_PKTS 0x2f /* enum */ 5748 #define MC_CMD_MAC_RX_FALSE_CARRIER_PKTS 0x30 /* enum */ 5749 #define MC_CMD_MAC_RX_SYMBOL_ERROR_PKTS 0x31 /* enum */ 5750 #define MC_CMD_MAC_RX_ALIGN_ERROR_PKTS 0x32 /* enum */ 5751 #define MC_CMD_MAC_RX_LENGTH_ERROR_PKTS 0x33 /* enum */ 5752 #define MC_CMD_MAC_RX_INTERNAL_ERROR_PKTS 0x34 /* enum */ 5753 #define MC_CMD_MAC_RX_JABBER_PKTS 0x35 /* enum */ 5754 #define MC_CMD_MAC_RX_NODESC_DROPS 0x36 /* enum */ 5755 #define MC_CMD_MAC_RX_LANES01_CHAR_ERR 0x37 /* enum */ 5756 #define MC_CMD_MAC_RX_LANES23_CHAR_ERR 0x38 /* enum */ 5757 #define MC_CMD_MAC_RX_LANES01_DISP_ERR 0x39 /* enum */ 5758 #define MC_CMD_MAC_RX_LANES23_DISP_ERR 0x3a /* enum */ 5759 #define MC_CMD_MAC_RX_MATCH_FAULT 0x3b /* enum */ 5760 /* enum: PM trunc_bb_overflow counter. Valid for EF10 with PM_AND_RXDP_COUNTERS 5761 * capability only. 5762 */ 5763 #define MC_CMD_MAC_PM_TRUNC_BB_OVERFLOW 0x3c 5764 /* enum: PM discard_bb_overflow counter. Valid for EF10 with 5765 * PM_AND_RXDP_COUNTERS capability only. 5766 */ 5767 #define MC_CMD_MAC_PM_DISCARD_BB_OVERFLOW 0x3d 5768 /* enum: PM trunc_vfifo_full counter. Valid for EF10 with PM_AND_RXDP_COUNTERS 5769 * capability only. 5770 */ 5771 #define MC_CMD_MAC_PM_TRUNC_VFIFO_FULL 0x3e 5772 /* enum: PM discard_vfifo_full counter. Valid for EF10 with 5773 * PM_AND_RXDP_COUNTERS capability only. 5774 */ 5775 #define MC_CMD_MAC_PM_DISCARD_VFIFO_FULL 0x3f 5776 /* enum: PM trunc_qbb counter. Valid for EF10 with PM_AND_RXDP_COUNTERS 5777 * capability only. 5778 */ 5779 #define MC_CMD_MAC_PM_TRUNC_QBB 0x40 5780 /* enum: PM discard_qbb counter. Valid for EF10 with PM_AND_RXDP_COUNTERS 5781 * capability only. 5782 */ 5783 #define MC_CMD_MAC_PM_DISCARD_QBB 0x41 5784 /* enum: PM discard_mapping counter. Valid for EF10 with PM_AND_RXDP_COUNTERS 5785 * capability only. 5786 */ 5787 #define MC_CMD_MAC_PM_DISCARD_MAPPING 0x42 5788 /* enum: RXDP counter: Number of packets dropped due to the queue being 5789 * disabled. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only. 5790 */ 5791 #define MC_CMD_MAC_RXDP_Q_DISABLED_PKTS 0x43 5792 /* enum: RXDP counter: Number of packets dropped by the DICPU. Valid for EF10 5793 * with PM_AND_RXDP_COUNTERS capability only. 5794 */ 5795 #define MC_CMD_MAC_RXDP_DI_DROPPED_PKTS 0x45 5796 /* enum: RXDP counter: Number of non-host packets. Valid for EF10 with 5797 * PM_AND_RXDP_COUNTERS capability only. 5798 */ 5799 #define MC_CMD_MAC_RXDP_STREAMING_PKTS 0x46 5800 /* enum: RXDP counter: Number of times an hlb descriptor fetch was performed. 5801 * Valid for EF10 with PM_AND_RXDP_COUNTERS capability only. 5802 */ 5803 #define MC_CMD_MAC_RXDP_HLB_FETCH_CONDITIONS 0x47 5804 /* enum: RXDP counter: Number of times the DPCPU waited for an existing 5805 * descriptor fetch. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only. 5806 */ 5807 #define MC_CMD_MAC_RXDP_HLB_WAIT_CONDITIONS 0x48 5808 #define MC_CMD_MAC_VADAPTER_RX_DMABUF_START 0x4c /* enum */ 5809 #define MC_CMD_MAC_VADAPTER_RX_UNICAST_PACKETS 0x4c /* enum */ 5810 #define MC_CMD_MAC_VADAPTER_RX_UNICAST_BYTES 0x4d /* enum */ 5811 #define MC_CMD_MAC_VADAPTER_RX_MULTICAST_PACKETS 0x4e /* enum */ 5812 #define MC_CMD_MAC_VADAPTER_RX_MULTICAST_BYTES 0x4f /* enum */ 5813 #define MC_CMD_MAC_VADAPTER_RX_BROADCAST_PACKETS 0x50 /* enum */ 5814 #define MC_CMD_MAC_VADAPTER_RX_BROADCAST_BYTES 0x51 /* enum */ 5815 #define MC_CMD_MAC_VADAPTER_RX_BAD_PACKETS 0x52 /* enum */ 5816 #define MC_CMD_MAC_VADAPTER_RX_BAD_BYTES 0x53 /* enum */ 5817 #define MC_CMD_MAC_VADAPTER_RX_OVERFLOW 0x54 /* enum */ 5818 #define MC_CMD_MAC_VADAPTER_TX_DMABUF_START 0x57 /* enum */ 5819 #define MC_CMD_MAC_VADAPTER_TX_UNICAST_PACKETS 0x57 /* enum */ 5820 #define MC_CMD_MAC_VADAPTER_TX_UNICAST_BYTES 0x58 /* enum */ 5821 #define MC_CMD_MAC_VADAPTER_TX_MULTICAST_PACKETS 0x59 /* enum */ 5822 #define MC_CMD_MAC_VADAPTER_TX_MULTICAST_BYTES 0x5a /* enum */ 5823 #define MC_CMD_MAC_VADAPTER_TX_BROADCAST_PACKETS 0x5b /* enum */ 5824 #define MC_CMD_MAC_VADAPTER_TX_BROADCAST_BYTES 0x5c /* enum */ 5825 #define MC_CMD_MAC_VADAPTER_TX_BAD_PACKETS 0x5d /* enum */ 5826 #define MC_CMD_MAC_VADAPTER_TX_BAD_BYTES 0x5e /* enum */ 5827 #define MC_CMD_MAC_VADAPTER_TX_OVERFLOW 0x5f /* enum */ 5828 /* enum: Start of GMAC stats buffer space, for Siena only. */ 5829 #define MC_CMD_GMAC_DMABUF_START 0x40 5830 /* enum: End of GMAC stats buffer space, for Siena only. */ 5831 #define MC_CMD_GMAC_DMABUF_END 0x5f 5832 #define MC_CMD_MAC_GENERATION_END 0x60 /* enum */ 5833 #define MC_CMD_MAC_NSTATS 0x61 /* enum */ 5834 5835 5836 /***********************************/ 5837 /* MC_CMD_SRIOV 5838 * to be documented 5839 */ 5840 #define MC_CMD_SRIOV 0x30 5841 5842 /* MC_CMD_SRIOV_IN msgrequest */ 5843 #define MC_CMD_SRIOV_IN_LEN 12 5844 #define MC_CMD_SRIOV_IN_ENABLE_OFST 0 5845 #define MC_CMD_SRIOV_IN_VI_BASE_OFST 4 5846 #define MC_CMD_SRIOV_IN_VF_COUNT_OFST 8 5847 5848 /* MC_CMD_SRIOV_OUT msgresponse */ 5849 #define MC_CMD_SRIOV_OUT_LEN 8 5850 #define MC_CMD_SRIOV_OUT_VI_SCALE_OFST 0 5851 #define MC_CMD_SRIOV_OUT_VF_TOTAL_OFST 4 5852 5853 /* MC_CMD_MEMCPY_RECORD_TYPEDEF structuredef */ 5854 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LEN 32 5855 /* this is only used for the first record */ 5856 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_OFST 0 5857 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_LBN 0 5858 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_WIDTH 32 5859 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_OFST 4 5860 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_LBN 32 5861 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_WIDTH 32 5862 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_OFST 8 5863 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LEN 8 5864 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LO_OFST 8 5865 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_HI_OFST 12 5866 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LBN 64 5867 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_WIDTH 64 5868 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_OFST 16 5869 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_RID_INLINE 0x100 /* enum */ 5870 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_LBN 128 5871 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_WIDTH 32 5872 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_OFST 20 5873 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LEN 8 5874 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LO_OFST 20 5875 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_HI_OFST 24 5876 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LBN 160 5877 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_WIDTH 64 5878 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_OFST 28 5879 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_LBN 224 5880 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_WIDTH 32 5881 5882 5883 /***********************************/ 5884 /* MC_CMD_MEMCPY 5885 * DMA write data into (Rid,Addr), either by dma reading (Rid,Addr), or by data 5886 * embedded directly in the command. 5887 * 5888 * A common pattern is for a client to use generation counts to signal a dma 5889 * update of a datastructure. To facilitate this, this MCDI operation can 5890 * contain multiple requests which are executed in strict order. Requests take 5891 * the form of duplicating the entire MCDI request continuously (including the 5892 * requests record, which is ignored in all but the first structure) 5893 * 5894 * The source data can either come from a DMA from the host, or it can be 5895 * embedded within the request directly, thereby eliminating a DMA read. To 5896 * indicate this, the client sets FROM_RID=%RID_INLINE, ADDR_HI=0, and 5897 * ADDR_LO=offset, and inserts the data at %offset from the start of the 5898 * payload. It's the callers responsibility to ensure that the embedded data 5899 * doesn't overlap the records. 5900 * 5901 * Returns: 0, EINVAL (invalid RID) 5902 */ 5903 #define MC_CMD_MEMCPY 0x31 5904 5905 /* MC_CMD_MEMCPY_IN msgrequest */ 5906 #define MC_CMD_MEMCPY_IN_LENMIN 32 5907 #define MC_CMD_MEMCPY_IN_LENMAX 224 5908 #define MC_CMD_MEMCPY_IN_LEN(num) (0+32*(num)) 5909 /* see MC_CMD_MEMCPY_RECORD_TYPEDEF */ 5910 #define MC_CMD_MEMCPY_IN_RECORD_OFST 0 5911 #define MC_CMD_MEMCPY_IN_RECORD_LEN 32 5912 #define MC_CMD_MEMCPY_IN_RECORD_MINNUM 1 5913 #define MC_CMD_MEMCPY_IN_RECORD_MAXNUM 7 5914 5915 /* MC_CMD_MEMCPY_OUT msgresponse */ 5916 #define MC_CMD_MEMCPY_OUT_LEN 0 5917 5918 5919 /***********************************/ 5920 /* MC_CMD_WOL_FILTER_SET 5921 * Set a WoL filter. 5922 */ 5923 #define MC_CMD_WOL_FILTER_SET 0x32 5924 #undef MC_CMD_0x32_PRIVILEGE_CTG 5925 5926 #define MC_CMD_0x32_PRIVILEGE_CTG SRIOV_CTG_LINK 5927 5928 /* MC_CMD_WOL_FILTER_SET_IN msgrequest */ 5929 #define MC_CMD_WOL_FILTER_SET_IN_LEN 192 5930 #define MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 5931 #define MC_CMD_FILTER_MODE_SIMPLE 0x0 /* enum */ 5932 #define MC_CMD_FILTER_MODE_STRUCTURED 0xffffffff /* enum */ 5933 /* A type value of 1 is unused. */ 5934 #define MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 5935 /* enum: Magic */ 5936 #define MC_CMD_WOL_TYPE_MAGIC 0x0 5937 /* enum: MS Windows Magic */ 5938 #define MC_CMD_WOL_TYPE_WIN_MAGIC 0x2 5939 /* enum: IPv4 Syn */ 5940 #define MC_CMD_WOL_TYPE_IPV4_SYN 0x3 5941 /* enum: IPv6 Syn */ 5942 #define MC_CMD_WOL_TYPE_IPV6_SYN 0x4 5943 /* enum: Bitmap */ 5944 #define MC_CMD_WOL_TYPE_BITMAP 0x5 5945 /* enum: Link */ 5946 #define MC_CMD_WOL_TYPE_LINK 0x6 5947 /* enum: (Above this for future use) */ 5948 #define MC_CMD_WOL_TYPE_MAX 0x7 5949 #define MC_CMD_WOL_FILTER_SET_IN_DATA_OFST 8 5950 #define MC_CMD_WOL_FILTER_SET_IN_DATA_LEN 4 5951 #define MC_CMD_WOL_FILTER_SET_IN_DATA_NUM 46 5952 5953 /* MC_CMD_WOL_FILTER_SET_IN_MAGIC msgrequest */ 5954 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_LEN 16 5955 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 5956 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 5957 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_OFST 8 5958 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LEN 8 5959 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LO_OFST 8 5960 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_HI_OFST 12 5961 5962 /* MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN msgrequest */ 5963 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_LEN 20 5964 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 5965 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 5966 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_IP_OFST 8 5967 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_IP_OFST 12 5968 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_OFST 16 5969 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_LEN 2 5970 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_OFST 18 5971 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_LEN 2 5972 5973 /* MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN msgrequest */ 5974 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_LEN 44 5975 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 5976 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 5977 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_OFST 8 5978 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_LEN 16 5979 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_OFST 24 5980 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_LEN 16 5981 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_OFST 40 5982 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_LEN 2 5983 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_OFST 42 5984 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_LEN 2 5985 5986 /* MC_CMD_WOL_FILTER_SET_IN_BITMAP msgrequest */ 5987 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN 187 5988 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 5989 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 5990 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_OFST 8 5991 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_LEN 48 5992 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_OFST 56 5993 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_LEN 128 5994 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_OFST 184 5995 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_LEN 1 5996 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_OFST 185 5997 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_LEN 1 5998 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_OFST 186 5999 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_LEN 1 6000 6001 /* MC_CMD_WOL_FILTER_SET_IN_LINK msgrequest */ 6002 #define MC_CMD_WOL_FILTER_SET_IN_LINK_LEN 12 6003 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 6004 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 6005 #define MC_CMD_WOL_FILTER_SET_IN_LINK_MASK_OFST 8 6006 #define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_LBN 0 6007 #define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_WIDTH 1 6008 #define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_LBN 1 6009 #define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_WIDTH 1 6010 6011 /* MC_CMD_WOL_FILTER_SET_OUT msgresponse */ 6012 #define MC_CMD_WOL_FILTER_SET_OUT_LEN 4 6013 #define MC_CMD_WOL_FILTER_SET_OUT_FILTER_ID_OFST 0 6014 6015 6016 /***********************************/ 6017 /* MC_CMD_WOL_FILTER_REMOVE 6018 * Remove a WoL filter. Locks required: None. Returns: 0, EINVAL, ENOSYS 6019 */ 6020 #define MC_CMD_WOL_FILTER_REMOVE 0x33 6021 #undef MC_CMD_0x33_PRIVILEGE_CTG 6022 6023 #define MC_CMD_0x33_PRIVILEGE_CTG SRIOV_CTG_LINK 6024 6025 /* MC_CMD_WOL_FILTER_REMOVE_IN msgrequest */ 6026 #define MC_CMD_WOL_FILTER_REMOVE_IN_LEN 4 6027 #define MC_CMD_WOL_FILTER_REMOVE_IN_FILTER_ID_OFST 0 6028 6029 /* MC_CMD_WOL_FILTER_REMOVE_OUT msgresponse */ 6030 #define MC_CMD_WOL_FILTER_REMOVE_OUT_LEN 0 6031 6032 6033 /***********************************/ 6034 /* MC_CMD_WOL_FILTER_RESET 6035 * Reset (i.e. remove all) WoL filters. Locks required: None. Returns: 0, 6036 * ENOSYS 6037 */ 6038 #define MC_CMD_WOL_FILTER_RESET 0x34 6039 #undef MC_CMD_0x34_PRIVILEGE_CTG 6040 6041 #define MC_CMD_0x34_PRIVILEGE_CTG SRIOV_CTG_LINK 6042 6043 /* MC_CMD_WOL_FILTER_RESET_IN msgrequest */ 6044 #define MC_CMD_WOL_FILTER_RESET_IN_LEN 4 6045 #define MC_CMD_WOL_FILTER_RESET_IN_MASK_OFST 0 6046 #define MC_CMD_WOL_FILTER_RESET_IN_WAKE_FILTERS 0x1 /* enum */ 6047 #define MC_CMD_WOL_FILTER_RESET_IN_LIGHTSOUT_OFFLOADS 0x2 /* enum */ 6048 6049 /* MC_CMD_WOL_FILTER_RESET_OUT msgresponse */ 6050 #define MC_CMD_WOL_FILTER_RESET_OUT_LEN 0 6051 6052 6053 /***********************************/ 6054 /* MC_CMD_SET_MCAST_HASH 6055 * Set the MCAST hash value without otherwise reconfiguring the MAC 6056 */ 6057 #define MC_CMD_SET_MCAST_HASH 0x35 6058 6059 /* MC_CMD_SET_MCAST_HASH_IN msgrequest */ 6060 #define MC_CMD_SET_MCAST_HASH_IN_LEN 32 6061 #define MC_CMD_SET_MCAST_HASH_IN_HASH0_OFST 0 6062 #define MC_CMD_SET_MCAST_HASH_IN_HASH0_LEN 16 6063 #define MC_CMD_SET_MCAST_HASH_IN_HASH1_OFST 16 6064 #define MC_CMD_SET_MCAST_HASH_IN_HASH1_LEN 16 6065 6066 /* MC_CMD_SET_MCAST_HASH_OUT msgresponse */ 6067 #define MC_CMD_SET_MCAST_HASH_OUT_LEN 0 6068 6069 6070 /***********************************/ 6071 /* MC_CMD_NVRAM_TYPES 6072 * Return bitfield indicating available types of virtual NVRAM partitions. 6073 * Locks required: none. Returns: 0 6074 */ 6075 #define MC_CMD_NVRAM_TYPES 0x36 6076 #undef MC_CMD_0x36_PRIVILEGE_CTG 6077 6078 #define MC_CMD_0x36_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6079 6080 /* MC_CMD_NVRAM_TYPES_IN msgrequest */ 6081 #define MC_CMD_NVRAM_TYPES_IN_LEN 0 6082 6083 /* MC_CMD_NVRAM_TYPES_OUT msgresponse */ 6084 #define MC_CMD_NVRAM_TYPES_OUT_LEN 4 6085 /* Bit mask of supported types. */ 6086 #define MC_CMD_NVRAM_TYPES_OUT_TYPES_OFST 0 6087 /* enum: Disabled callisto. */ 6088 #define MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO 0x0 6089 /* enum: MC firmware. */ 6090 #define MC_CMD_NVRAM_TYPE_MC_FW 0x1 6091 /* enum: MC backup firmware. */ 6092 #define MC_CMD_NVRAM_TYPE_MC_FW_BACKUP 0x2 6093 /* enum: Static configuration Port0. */ 6094 #define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0 0x3 6095 /* enum: Static configuration Port1. */ 6096 #define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1 0x4 6097 /* enum: Dynamic configuration Port0. */ 6098 #define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0 0x5 6099 /* enum: Dynamic configuration Port1. */ 6100 #define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1 0x6 6101 /* enum: Expansion Rom. */ 6102 #define MC_CMD_NVRAM_TYPE_EXP_ROM 0x7 6103 /* enum: Expansion Rom Configuration Port0. */ 6104 #define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0 0x8 6105 /* enum: Expansion Rom Configuration Port1. */ 6106 #define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1 0x9 6107 /* enum: Phy Configuration Port0. */ 6108 #define MC_CMD_NVRAM_TYPE_PHY_PORT0 0xa 6109 /* enum: Phy Configuration Port1. */ 6110 #define MC_CMD_NVRAM_TYPE_PHY_PORT1 0xb 6111 /* enum: Log. */ 6112 #define MC_CMD_NVRAM_TYPE_LOG 0xc 6113 /* enum: FPGA image. */ 6114 #define MC_CMD_NVRAM_TYPE_FPGA 0xd 6115 /* enum: FPGA backup image */ 6116 #define MC_CMD_NVRAM_TYPE_FPGA_BACKUP 0xe 6117 /* enum: FC firmware. */ 6118 #define MC_CMD_NVRAM_TYPE_FC_FW 0xf 6119 /* enum: FC backup firmware. */ 6120 #define MC_CMD_NVRAM_TYPE_FC_FW_BACKUP 0x10 6121 /* enum: CPLD image. */ 6122 #define MC_CMD_NVRAM_TYPE_CPLD 0x11 6123 /* enum: Licensing information. */ 6124 #define MC_CMD_NVRAM_TYPE_LICENSE 0x12 6125 /* enum: FC Log. */ 6126 #define MC_CMD_NVRAM_TYPE_FC_LOG 0x13 6127 /* enum: Additional flash on FPGA. */ 6128 #define MC_CMD_NVRAM_TYPE_FC_EXTRA 0x14 6129 6130 6131 /***********************************/ 6132 /* MC_CMD_NVRAM_INFO 6133 * Read info about a virtual NVRAM partition. Locks required: none. Returns: 0, 6134 * EINVAL (bad type). 6135 */ 6136 #define MC_CMD_NVRAM_INFO 0x37 6137 #undef MC_CMD_0x37_PRIVILEGE_CTG 6138 6139 #define MC_CMD_0x37_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6140 6141 /* MC_CMD_NVRAM_INFO_IN msgrequest */ 6142 #define MC_CMD_NVRAM_INFO_IN_LEN 4 6143 #define MC_CMD_NVRAM_INFO_IN_TYPE_OFST 0 6144 /* Enum values, see field(s): */ 6145 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 6146 6147 /* MC_CMD_NVRAM_INFO_OUT msgresponse */ 6148 #define MC_CMD_NVRAM_INFO_OUT_LEN 24 6149 #define MC_CMD_NVRAM_INFO_OUT_TYPE_OFST 0 6150 /* Enum values, see field(s): */ 6151 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 6152 #define MC_CMD_NVRAM_INFO_OUT_SIZE_OFST 4 6153 #define MC_CMD_NVRAM_INFO_OUT_ERASESIZE_OFST 8 6154 #define MC_CMD_NVRAM_INFO_OUT_FLAGS_OFST 12 6155 #define MC_CMD_NVRAM_INFO_OUT_PROTECTED_LBN 0 6156 #define MC_CMD_NVRAM_INFO_OUT_PROTECTED_WIDTH 1 6157 #define MC_CMD_NVRAM_INFO_OUT_TLV_LBN 1 6158 #define MC_CMD_NVRAM_INFO_OUT_TLV_WIDTH 1 6159 #define MC_CMD_NVRAM_INFO_OUT_READ_ONLY_LBN 5 6160 #define MC_CMD_NVRAM_INFO_OUT_READ_ONLY_WIDTH 1 6161 #define MC_CMD_NVRAM_INFO_OUT_CMAC_LBN 6 6162 #define MC_CMD_NVRAM_INFO_OUT_CMAC_WIDTH 1 6163 #define MC_CMD_NVRAM_INFO_OUT_A_B_LBN 7 6164 #define MC_CMD_NVRAM_INFO_OUT_A_B_WIDTH 1 6165 #define MC_CMD_NVRAM_INFO_OUT_PHYSDEV_OFST 16 6166 #define MC_CMD_NVRAM_INFO_OUT_PHYSADDR_OFST 20 6167 6168 /* MC_CMD_NVRAM_INFO_V2_OUT msgresponse */ 6169 #define MC_CMD_NVRAM_INFO_V2_OUT_LEN 28 6170 #define MC_CMD_NVRAM_INFO_V2_OUT_TYPE_OFST 0 6171 /* Enum values, see field(s): */ 6172 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 6173 #define MC_CMD_NVRAM_INFO_V2_OUT_SIZE_OFST 4 6174 #define MC_CMD_NVRAM_INFO_V2_OUT_ERASESIZE_OFST 8 6175 #define MC_CMD_NVRAM_INFO_V2_OUT_FLAGS_OFST 12 6176 #define MC_CMD_NVRAM_INFO_V2_OUT_PROTECTED_LBN 0 6177 #define MC_CMD_NVRAM_INFO_V2_OUT_PROTECTED_WIDTH 1 6178 #define MC_CMD_NVRAM_INFO_V2_OUT_TLV_LBN 1 6179 #define MC_CMD_NVRAM_INFO_V2_OUT_TLV_WIDTH 1 6180 #define MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_LBN 5 6181 #define MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_WIDTH 1 6182 #define MC_CMD_NVRAM_INFO_V2_OUT_A_B_LBN 7 6183 #define MC_CMD_NVRAM_INFO_V2_OUT_A_B_WIDTH 1 6184 #define MC_CMD_NVRAM_INFO_V2_OUT_PHYSDEV_OFST 16 6185 #define MC_CMD_NVRAM_INFO_V2_OUT_PHYSADDR_OFST 20 6186 /* Writes must be multiples of this size. Added to support the MUM on Sorrento. 6187 */ 6188 #define MC_CMD_NVRAM_INFO_V2_OUT_WRITESIZE_OFST 24 6189 6190 6191 /***********************************/ 6192 /* MC_CMD_NVRAM_UPDATE_START 6193 * Start a group of update operations on a virtual NVRAM partition. Locks 6194 * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad type), EACCES (if 6195 * PHY_LOCK required and not held). 6196 */ 6197 #define MC_CMD_NVRAM_UPDATE_START 0x38 6198 #undef MC_CMD_0x38_PRIVILEGE_CTG 6199 6200 #define MC_CMD_0x38_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6201 6202 /* MC_CMD_NVRAM_UPDATE_START_IN msgrequest: Legacy NVRAM_UPDATE_START request. 6203 * Use NVRAM_UPDATE_START_V2_IN in new code 6204 */ 6205 #define MC_CMD_NVRAM_UPDATE_START_IN_LEN 4 6206 #define MC_CMD_NVRAM_UPDATE_START_IN_TYPE_OFST 0 6207 /* Enum values, see field(s): */ 6208 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 6209 6210 /* MC_CMD_NVRAM_UPDATE_START_V2_IN msgrequest: Extended NVRAM_UPDATE_START 6211 * request with additional flags indicating version of command in use. See 6212 * MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT for details of extended functionality. Use 6213 * paired up with NVRAM_UPDATE_FINISH_V2_IN. 6214 */ 6215 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_LEN 8 6216 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_TYPE_OFST 0 6217 /* Enum values, see field(s): */ 6218 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 6219 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAGS_OFST 4 6220 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAG_REPORT_VERIFY_RESULT_LBN 0 6221 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAG_REPORT_VERIFY_RESULT_WIDTH 1 6222 6223 /* MC_CMD_NVRAM_UPDATE_START_OUT msgresponse */ 6224 #define MC_CMD_NVRAM_UPDATE_START_OUT_LEN 0 6225 6226 6227 /***********************************/ 6228 /* MC_CMD_NVRAM_READ 6229 * Read data from a virtual NVRAM partition. Locks required: PHY_LOCK if 6230 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if 6231 * PHY_LOCK required and not held) 6232 */ 6233 #define MC_CMD_NVRAM_READ 0x39 6234 #undef MC_CMD_0x39_PRIVILEGE_CTG 6235 6236 #define MC_CMD_0x39_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6237 6238 /* MC_CMD_NVRAM_READ_IN msgrequest */ 6239 #define MC_CMD_NVRAM_READ_IN_LEN 12 6240 #define MC_CMD_NVRAM_READ_IN_TYPE_OFST 0 6241 /* Enum values, see field(s): */ 6242 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 6243 #define MC_CMD_NVRAM_READ_IN_OFFSET_OFST 4 6244 /* amount to read in bytes */ 6245 #define MC_CMD_NVRAM_READ_IN_LENGTH_OFST 8 6246 6247 /* MC_CMD_NVRAM_READ_IN_V2 msgrequest */ 6248 #define MC_CMD_NVRAM_READ_IN_V2_LEN 16 6249 #define MC_CMD_NVRAM_READ_IN_V2_TYPE_OFST 0 6250 /* Enum values, see field(s): */ 6251 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 6252 #define MC_CMD_NVRAM_READ_IN_V2_OFFSET_OFST 4 6253 /* amount to read in bytes */ 6254 #define MC_CMD_NVRAM_READ_IN_V2_LENGTH_OFST 8 6255 /* Optional control info. If a partition is stored with an A/B versioning 6256 * scheme (i.e. in more than one physical partition in NVRAM) the host can set 6257 * this to control which underlying physical partition is used to read data 6258 * from. This allows it to perform a read-modify-write-verify with the write 6259 * lock continuously held by calling NVRAM_UPDATE_START, reading the old 6260 * contents using MODE=TARGET_CURRENT, overwriting the old partition and then 6261 * verifying by reading with MODE=TARGET_BACKUP. 6262 */ 6263 #define MC_CMD_NVRAM_READ_IN_V2_MODE_OFST 12 6264 /* enum: Same as omitting MODE: caller sees data in current partition unless it 6265 * holds the write lock in which case it sees data in the partition it is 6266 * updating. 6267 */ 6268 #define MC_CMD_NVRAM_READ_IN_V2_DEFAULT 0x0 6269 /* enum: Read from the current partition of an A/B pair, even if holding the 6270 * write lock. 6271 */ 6272 #define MC_CMD_NVRAM_READ_IN_V2_TARGET_CURRENT 0x1 6273 /* enum: Read from the non-current (i.e. to be updated) partition of an A/B 6274 * pair 6275 */ 6276 #define MC_CMD_NVRAM_READ_IN_V2_TARGET_BACKUP 0x2 6277 6278 /* MC_CMD_NVRAM_READ_OUT msgresponse */ 6279 #define MC_CMD_NVRAM_READ_OUT_LENMIN 1 6280 #define MC_CMD_NVRAM_READ_OUT_LENMAX 252 6281 #define MC_CMD_NVRAM_READ_OUT_LEN(num) (0+1*(num)) 6282 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_OFST 0 6283 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_LEN 1 6284 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MINNUM 1 6285 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MAXNUM 252 6286 6287 6288 /***********************************/ 6289 /* MC_CMD_NVRAM_WRITE 6290 * Write data to a virtual NVRAM partition. Locks required: PHY_LOCK if 6291 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if 6292 * PHY_LOCK required and not held) 6293 */ 6294 #define MC_CMD_NVRAM_WRITE 0x3a 6295 #undef MC_CMD_0x3a_PRIVILEGE_CTG 6296 6297 #define MC_CMD_0x3a_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6298 6299 /* MC_CMD_NVRAM_WRITE_IN msgrequest */ 6300 #define MC_CMD_NVRAM_WRITE_IN_LENMIN 13 6301 #define MC_CMD_NVRAM_WRITE_IN_LENMAX 252 6302 #define MC_CMD_NVRAM_WRITE_IN_LEN(num) (12+1*(num)) 6303 #define MC_CMD_NVRAM_WRITE_IN_TYPE_OFST 0 6304 /* Enum values, see field(s): */ 6305 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 6306 #define MC_CMD_NVRAM_WRITE_IN_OFFSET_OFST 4 6307 #define MC_CMD_NVRAM_WRITE_IN_LENGTH_OFST 8 6308 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_OFST 12 6309 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_LEN 1 6310 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MINNUM 1 6311 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MAXNUM 240 6312 6313 /* MC_CMD_NVRAM_WRITE_OUT msgresponse */ 6314 #define MC_CMD_NVRAM_WRITE_OUT_LEN 0 6315 6316 6317 /***********************************/ 6318 /* MC_CMD_NVRAM_ERASE 6319 * Erase sector(s) from a virtual NVRAM partition. Locks required: PHY_LOCK if 6320 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if 6321 * PHY_LOCK required and not held) 6322 */ 6323 #define MC_CMD_NVRAM_ERASE 0x3b 6324 #undef MC_CMD_0x3b_PRIVILEGE_CTG 6325 6326 #define MC_CMD_0x3b_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6327 6328 /* MC_CMD_NVRAM_ERASE_IN msgrequest */ 6329 #define MC_CMD_NVRAM_ERASE_IN_LEN 12 6330 #define MC_CMD_NVRAM_ERASE_IN_TYPE_OFST 0 6331 /* Enum values, see field(s): */ 6332 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 6333 #define MC_CMD_NVRAM_ERASE_IN_OFFSET_OFST 4 6334 #define MC_CMD_NVRAM_ERASE_IN_LENGTH_OFST 8 6335 6336 /* MC_CMD_NVRAM_ERASE_OUT msgresponse */ 6337 #define MC_CMD_NVRAM_ERASE_OUT_LEN 0 6338 6339 6340 /***********************************/ 6341 /* MC_CMD_NVRAM_UPDATE_FINISH 6342 * Finish a group of update operations on a virtual NVRAM partition. Locks 6343 * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad 6344 * type/offset/length), EACCES (if PHY_LOCK required and not held) 6345 */ 6346 #define MC_CMD_NVRAM_UPDATE_FINISH 0x3c 6347 #undef MC_CMD_0x3c_PRIVILEGE_CTG 6348 6349 #define MC_CMD_0x3c_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6350 6351 /* MC_CMD_NVRAM_UPDATE_FINISH_IN msgrequest: Legacy NVRAM_UPDATE_FINISH 6352 * request. Use NVRAM_UPDATE_FINISH_V2_IN in new code 6353 */ 6354 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_LEN 8 6355 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_TYPE_OFST 0 6356 /* Enum values, see field(s): */ 6357 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 6358 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_REBOOT_OFST 4 6359 6360 /* MC_CMD_NVRAM_UPDATE_FINISH_V2_IN msgrequest: Extended NVRAM_UPDATE_FINISH 6361 * request with additional flags indicating version of NVRAM_UPDATE commands in 6362 * use. See MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT for details of extended 6363 * functionality. Use paired up with NVRAM_UPDATE_START_V2_IN. 6364 */ 6365 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_LEN 12 6366 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_TYPE_OFST 0 6367 /* Enum values, see field(s): */ 6368 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 6369 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_REBOOT_OFST 4 6370 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAGS_OFST 8 6371 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_REPORT_VERIFY_RESULT_LBN 0 6372 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_REPORT_VERIFY_RESULT_WIDTH 1 6373 6374 /* MC_CMD_NVRAM_UPDATE_FINISH_OUT msgresponse: Legacy NVRAM_UPDATE_FINISH 6375 * response. Use NVRAM_UPDATE_FINISH_V2_OUT in new code 6376 */ 6377 #define MC_CMD_NVRAM_UPDATE_FINISH_OUT_LEN 0 6378 6379 /* MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT msgresponse: 6380 * 6381 * Extended NVRAM_UPDATE_FINISH response that communicates the result of secure 6382 * firmware validation where applicable back to the host. 6383 * 6384 * Medford only: For signed firmware images, such as those for medford, the MC 6385 * firmware verifies the signature before marking the firmware image as valid. 6386 * This process takes a few seconds to complete. So is likely to take more than 6387 * the MCDI timeout. Hence signature verification is initiated when 6388 * MC_CMD_NVRAM_UPDATE_FINISH_V2_IN is received by the firmware, however, the 6389 * MCDI command is run in a background MCDI processing thread. This response 6390 * payload includes the results of the signature verification. Note that the 6391 * per-partition nvram lock in firmware is only released after the verification 6392 * has completed. 6393 */ 6394 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_LEN 4 6395 /* Result of nvram update completion processing */ 6396 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_RESULT_CODE_OFST 0 6397 /* enum: Invalid return code; only non-zero values are defined. Defined as 6398 * unknown for backwards compatibility with NVRAM_UPDATE_FINISH_OUT. 6399 */ 6400 #define MC_CMD_NVRAM_VERIFY_RC_UNKNOWN 0x0 6401 /* enum: Verify succeeded without any errors. */ 6402 #define MC_CMD_NVRAM_VERIFY_RC_SUCCESS 0x1 6403 /* enum: CMS format verification failed due to an internal error. */ 6404 #define MC_CMD_NVRAM_VERIFY_RC_CMS_CHECK_FAILED 0x2 6405 /* enum: Invalid CMS format in image metadata. */ 6406 #define MC_CMD_NVRAM_VERIFY_RC_INVALID_CMS_FORMAT 0x3 6407 /* enum: Message digest verification failed due to an internal error. */ 6408 #define MC_CMD_NVRAM_VERIFY_RC_MESSAGE_DIGEST_CHECK_FAILED 0x4 6409 /* enum: Error in message digest calculated over the reflash-header, payload 6410 * and reflash-trailer. 6411 */ 6412 #define MC_CMD_NVRAM_VERIFY_RC_BAD_MESSAGE_DIGEST 0x5 6413 /* enum: Signature verification failed due to an internal error. */ 6414 #define MC_CMD_NVRAM_VERIFY_RC_SIGNATURE_CHECK_FAILED 0x6 6415 /* enum: There are no valid signatures in the image. */ 6416 #define MC_CMD_NVRAM_VERIFY_RC_NO_VALID_SIGNATURES 0x7 6417 /* enum: Trusted approvers verification failed due to an internal error. */ 6418 #define MC_CMD_NVRAM_VERIFY_RC_TRUSTED_APPROVERS_CHECK_FAILED 0x8 6419 /* enum: The Trusted approver's list is empty. */ 6420 #define MC_CMD_NVRAM_VERIFY_RC_NO_TRUSTED_APPROVERS 0x9 6421 /* enum: Signature chain verification failed due to an internal error. */ 6422 #define MC_CMD_NVRAM_VERIFY_RC_SIGNATURE_CHAIN_CHECK_FAILED 0xa 6423 /* enum: The signers of the signatures in the image are not listed in the 6424 * Trusted approver's list. 6425 */ 6426 #define MC_CMD_NVRAM_VERIFY_RC_NO_SIGNATURE_MATCH 0xb 6427 /* enum: The image contains a test-signed certificate, but the adapter accepts 6428 * only production signed images. 6429 */ 6430 #define MC_CMD_NVRAM_VERIFY_RC_REJECT_TEST_SIGNED 0xc 6431 6432 6433 /***********************************/ 6434 /* MC_CMD_REBOOT 6435 * Reboot the MC. 6436 * 6437 * The AFTER_ASSERTION flag is intended to be used when the driver notices an 6438 * assertion failure (at which point it is expected to perform a complete tear 6439 * down and reinitialise), to allow both ports to reset the MC once in an 6440 * atomic fashion. 6441 * 6442 * Production mc firmwares are generally compiled with REBOOT_ON_ASSERT=1, 6443 * which means that they will automatically reboot out of the assertion 6444 * handler, so this is in practise an optional operation. It is still 6445 * recommended that drivers execute this to support custom firmwares with 6446 * REBOOT_ON_ASSERT=0. 6447 * 6448 * Locks required: NONE Returns: Nothing. You get back a response with ERR=1, 6449 * DATALEN=0 6450 */ 6451 #define MC_CMD_REBOOT 0x3d 6452 #undef MC_CMD_0x3d_PRIVILEGE_CTG 6453 6454 #define MC_CMD_0x3d_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6455 6456 /* MC_CMD_REBOOT_IN msgrequest */ 6457 #define MC_CMD_REBOOT_IN_LEN 4 6458 #define MC_CMD_REBOOT_IN_FLAGS_OFST 0 6459 #define MC_CMD_REBOOT_FLAGS_AFTER_ASSERTION 0x1 /* enum */ 6460 6461 /* MC_CMD_REBOOT_OUT msgresponse */ 6462 #define MC_CMD_REBOOT_OUT_LEN 0 6463 6464 6465 /***********************************/ 6466 /* MC_CMD_SCHEDINFO 6467 * Request scheduler info. Locks required: NONE. Returns: An array of 6468 * (timeslice,maximum overrun), one for each thread, in ascending order of 6469 * thread address. 6470 */ 6471 #define MC_CMD_SCHEDINFO 0x3e 6472 #undef MC_CMD_0x3e_PRIVILEGE_CTG 6473 6474 #define MC_CMD_0x3e_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6475 6476 /* MC_CMD_SCHEDINFO_IN msgrequest */ 6477 #define MC_CMD_SCHEDINFO_IN_LEN 0 6478 6479 /* MC_CMD_SCHEDINFO_OUT msgresponse */ 6480 #define MC_CMD_SCHEDINFO_OUT_LENMIN 4 6481 #define MC_CMD_SCHEDINFO_OUT_LENMAX 252 6482 #define MC_CMD_SCHEDINFO_OUT_LEN(num) (0+4*(num)) 6483 #define MC_CMD_SCHEDINFO_OUT_DATA_OFST 0 6484 #define MC_CMD_SCHEDINFO_OUT_DATA_LEN 4 6485 #define MC_CMD_SCHEDINFO_OUT_DATA_MINNUM 1 6486 #define MC_CMD_SCHEDINFO_OUT_DATA_MAXNUM 63 6487 6488 6489 /***********************************/ 6490 /* MC_CMD_REBOOT_MODE 6491 * Set the mode for the next MC reboot. Locks required: NONE. Sets the reboot 6492 * mode to the specified value. Returns the old mode. 6493 */ 6494 #define MC_CMD_REBOOT_MODE 0x3f 6495 #undef MC_CMD_0x3f_PRIVILEGE_CTG 6496 6497 #define MC_CMD_0x3f_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6498 6499 /* MC_CMD_REBOOT_MODE_IN msgrequest */ 6500 #define MC_CMD_REBOOT_MODE_IN_LEN 4 6501 #define MC_CMD_REBOOT_MODE_IN_VALUE_OFST 0 6502 /* enum: Normal. */ 6503 #define MC_CMD_REBOOT_MODE_NORMAL 0x0 6504 /* enum: Power-on Reset. */ 6505 #define MC_CMD_REBOOT_MODE_POR 0x2 6506 /* enum: Snapper. */ 6507 #define MC_CMD_REBOOT_MODE_SNAPPER 0x3 6508 /* enum: snapper fake POR */ 6509 #define MC_CMD_REBOOT_MODE_SNAPPER_POR 0x4 6510 #define MC_CMD_REBOOT_MODE_IN_FAKE_LBN 7 6511 #define MC_CMD_REBOOT_MODE_IN_FAKE_WIDTH 1 6512 6513 /* MC_CMD_REBOOT_MODE_OUT msgresponse */ 6514 #define MC_CMD_REBOOT_MODE_OUT_LEN 4 6515 #define MC_CMD_REBOOT_MODE_OUT_VALUE_OFST 0 6516 6517 6518 /***********************************/ 6519 /* MC_CMD_SENSOR_INFO 6520 * Returns information about every available sensor. 6521 * 6522 * Each sensor has a single (16bit) value, and a corresponding state. The 6523 * mapping between value and state is nominally determined by the MC, but may 6524 * be implemented using up to 2 ranges per sensor. 6525 * 6526 * This call returns a mask (32bit) of the sensors that are supported by this 6527 * platform, then an array of sensor information structures, in order of sensor 6528 * type (but without gaps for unimplemented sensors). Each structure defines 6529 * the ranges for the corresponding sensor. An unused range is indicated by 6530 * equal limit values. If one range is used, a value outside that range results 6531 * in STATE_FATAL. If two ranges are used, a value outside the second range 6532 * results in STATE_FATAL while a value outside the first and inside the second 6533 * range results in STATE_WARNING. 6534 * 6535 * Sensor masks and sensor information arrays are organised into pages. For 6536 * backward compatibility, older host software can only use sensors in page 0. 6537 * Bit 32 in the sensor mask was previously unused, and is no reserved for use 6538 * as the next page flag. 6539 * 6540 * If the request does not contain a PAGE value then firmware will only return 6541 * page 0 of sensor information, with bit 31 in the sensor mask cleared. 6542 * 6543 * If the request contains a PAGE value then firmware responds with the sensor 6544 * mask and sensor information array for that page of sensors. In this case bit 6545 * 31 in the mask is set if another page exists. 6546 * 6547 * Locks required: None Returns: 0 6548 */ 6549 #define MC_CMD_SENSOR_INFO 0x41 6550 #undef MC_CMD_0x41_PRIVILEGE_CTG 6551 6552 #define MC_CMD_0x41_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6553 6554 /* MC_CMD_SENSOR_INFO_IN msgrequest */ 6555 #define MC_CMD_SENSOR_INFO_IN_LEN 0 6556 6557 /* MC_CMD_SENSOR_INFO_EXT_IN msgrequest */ 6558 #define MC_CMD_SENSOR_INFO_EXT_IN_LEN 4 6559 /* Which page of sensors to report. 6560 * 6561 * Page 0 contains sensors 0 to 30 (sensor 31 is the next page bit). 6562 * 6563 * Page 1 contains sensors 32 to 62 (sensor 63 is the next page bit). etc. 6564 */ 6565 #define MC_CMD_SENSOR_INFO_EXT_IN_PAGE_OFST 0 6566 6567 /* MC_CMD_SENSOR_INFO_OUT msgresponse */ 6568 #define MC_CMD_SENSOR_INFO_OUT_LENMIN 4 6569 #define MC_CMD_SENSOR_INFO_OUT_LENMAX 252 6570 #define MC_CMD_SENSOR_INFO_OUT_LEN(num) (4+8*(num)) 6571 #define MC_CMD_SENSOR_INFO_OUT_MASK_OFST 0 6572 /* enum: Controller temperature: degC */ 6573 #define MC_CMD_SENSOR_CONTROLLER_TEMP 0x0 6574 /* enum: Phy common temperature: degC */ 6575 #define MC_CMD_SENSOR_PHY_COMMON_TEMP 0x1 6576 /* enum: Controller cooling: bool */ 6577 #define MC_CMD_SENSOR_CONTROLLER_COOLING 0x2 6578 /* enum: Phy 0 temperature: degC */ 6579 #define MC_CMD_SENSOR_PHY0_TEMP 0x3 6580 /* enum: Phy 0 cooling: bool */ 6581 #define MC_CMD_SENSOR_PHY0_COOLING 0x4 6582 /* enum: Phy 1 temperature: degC */ 6583 #define MC_CMD_SENSOR_PHY1_TEMP 0x5 6584 /* enum: Phy 1 cooling: bool */ 6585 #define MC_CMD_SENSOR_PHY1_COOLING 0x6 6586 /* enum: 1.0v power: mV */ 6587 #define MC_CMD_SENSOR_IN_1V0 0x7 6588 /* enum: 1.2v power: mV */ 6589 #define MC_CMD_SENSOR_IN_1V2 0x8 6590 /* enum: 1.8v power: mV */ 6591 #define MC_CMD_SENSOR_IN_1V8 0x9 6592 /* enum: 2.5v power: mV */ 6593 #define MC_CMD_SENSOR_IN_2V5 0xa 6594 /* enum: 3.3v power: mV */ 6595 #define MC_CMD_SENSOR_IN_3V3 0xb 6596 /* enum: 12v power: mV */ 6597 #define MC_CMD_SENSOR_IN_12V0 0xc 6598 /* enum: 1.2v analogue power: mV */ 6599 #define MC_CMD_SENSOR_IN_1V2A 0xd 6600 /* enum: reference voltage: mV */ 6601 #define MC_CMD_SENSOR_IN_VREF 0xe 6602 /* enum: AOE FPGA power: mV */ 6603 #define MC_CMD_SENSOR_OUT_VAOE 0xf 6604 /* enum: AOE FPGA temperature: degC */ 6605 #define MC_CMD_SENSOR_AOE_TEMP 0x10 6606 /* enum: AOE FPGA PSU temperature: degC */ 6607 #define MC_CMD_SENSOR_PSU_AOE_TEMP 0x11 6608 /* enum: AOE PSU temperature: degC */ 6609 #define MC_CMD_SENSOR_PSU_TEMP 0x12 6610 /* enum: Fan 0 speed: RPM */ 6611 #define MC_CMD_SENSOR_FAN_0 0x13 6612 /* enum: Fan 1 speed: RPM */ 6613 #define MC_CMD_SENSOR_FAN_1 0x14 6614 /* enum: Fan 2 speed: RPM */ 6615 #define MC_CMD_SENSOR_FAN_2 0x15 6616 /* enum: Fan 3 speed: RPM */ 6617 #define MC_CMD_SENSOR_FAN_3 0x16 6618 /* enum: Fan 4 speed: RPM */ 6619 #define MC_CMD_SENSOR_FAN_4 0x17 6620 /* enum: AOE FPGA input power: mV */ 6621 #define MC_CMD_SENSOR_IN_VAOE 0x18 6622 /* enum: AOE FPGA current: mA */ 6623 #define MC_CMD_SENSOR_OUT_IAOE 0x19 6624 /* enum: AOE FPGA input current: mA */ 6625 #define MC_CMD_SENSOR_IN_IAOE 0x1a 6626 /* enum: NIC power consumption: W */ 6627 #define MC_CMD_SENSOR_NIC_POWER 0x1b 6628 /* enum: 0.9v power voltage: mV */ 6629 #define MC_CMD_SENSOR_IN_0V9 0x1c 6630 /* enum: 0.9v power current: mA */ 6631 #define MC_CMD_SENSOR_IN_I0V9 0x1d 6632 /* enum: 1.2v power current: mA */ 6633 #define MC_CMD_SENSOR_IN_I1V2 0x1e 6634 /* enum: Not a sensor: reserved for the next page flag */ 6635 #define MC_CMD_SENSOR_PAGE0_NEXT 0x1f 6636 /* enum: 0.9v power voltage (at ADC): mV */ 6637 #define MC_CMD_SENSOR_IN_0V9_ADC 0x20 6638 /* enum: Controller temperature 2: degC */ 6639 #define MC_CMD_SENSOR_CONTROLLER_2_TEMP 0x21 6640 /* enum: Voltage regulator internal temperature: degC */ 6641 #define MC_CMD_SENSOR_VREG_INTERNAL_TEMP 0x22 6642 /* enum: 0.9V voltage regulator temperature: degC */ 6643 #define MC_CMD_SENSOR_VREG_0V9_TEMP 0x23 6644 /* enum: 1.2V voltage regulator temperature: degC */ 6645 #define MC_CMD_SENSOR_VREG_1V2_TEMP 0x24 6646 /* enum: controller internal temperature sensor voltage (internal ADC): mV */ 6647 #define MC_CMD_SENSOR_CONTROLLER_VPTAT 0x25 6648 /* enum: controller internal temperature (internal ADC): degC */ 6649 #define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP 0x26 6650 /* enum: controller internal temperature sensor voltage (external ADC): mV */ 6651 #define MC_CMD_SENSOR_CONTROLLER_VPTAT_EXTADC 0x27 6652 /* enum: controller internal temperature (external ADC): degC */ 6653 #define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP_EXTADC 0x28 6654 /* enum: ambient temperature: degC */ 6655 #define MC_CMD_SENSOR_AMBIENT_TEMP 0x29 6656 /* enum: air flow: bool */ 6657 #define MC_CMD_SENSOR_AIRFLOW 0x2a 6658 /* enum: voltage between VSS08D and VSS08D at CSR: mV */ 6659 #define MC_CMD_SENSOR_VDD08D_VSS08D_CSR 0x2b 6660 /* enum: voltage between VSS08D and VSS08D at CSR (external ADC): mV */ 6661 #define MC_CMD_SENSOR_VDD08D_VSS08D_CSR_EXTADC 0x2c 6662 /* enum: Hotpoint temperature: degC */ 6663 #define MC_CMD_SENSOR_HOTPOINT_TEMP 0x2d 6664 /* enum: Port 0 PHY power switch over-current: bool */ 6665 #define MC_CMD_SENSOR_PHY_POWER_PORT0 0x2e 6666 /* enum: Port 1 PHY power switch over-current: bool */ 6667 #define MC_CMD_SENSOR_PHY_POWER_PORT1 0x2f 6668 /* enum: Mop-up microcontroller reference voltage (millivolts) */ 6669 #define MC_CMD_SENSOR_MUM_VCC 0x30 6670 /* enum: 0.9v power phase A voltage: mV */ 6671 #define MC_CMD_SENSOR_IN_0V9_A 0x31 6672 /* enum: 0.9v power phase A current: mA */ 6673 #define MC_CMD_SENSOR_IN_I0V9_A 0x32 6674 /* enum: 0.9V voltage regulator phase A temperature: degC */ 6675 #define MC_CMD_SENSOR_VREG_0V9_A_TEMP 0x33 6676 /* enum: 0.9v power phase B voltage: mV */ 6677 #define MC_CMD_SENSOR_IN_0V9_B 0x34 6678 /* enum: 0.9v power phase B current: mA */ 6679 #define MC_CMD_SENSOR_IN_I0V9_B 0x35 6680 /* enum: 0.9V voltage regulator phase B temperature: degC */ 6681 #define MC_CMD_SENSOR_VREG_0V9_B_TEMP 0x36 6682 /* enum: CCOM AVREG 1v2 supply (interval ADC): mV */ 6683 #define MC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY 0x37 6684 /* enum: CCOM AVREG 1v2 supply (external ADC): mV */ 6685 #define MC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY_EXTADC 0x38 6686 /* enum: CCOM AVREG 1v8 supply (interval ADC): mV */ 6687 #define MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY 0x39 6688 /* enum: CCOM AVREG 1v8 supply (external ADC): mV */ 6689 #define MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY_EXTADC 0x3a 6690 /* enum: CCOM RTS temperature: degC */ 6691 #define MC_CMD_SENSOR_CONTROLLER_RTS 0x3b 6692 /* enum: Not a sensor: reserved for the next page flag */ 6693 #define MC_CMD_SENSOR_PAGE1_NEXT 0x3f 6694 /* enum: controller internal temperature sensor voltage on master core 6695 * (internal ADC): mV 6696 */ 6697 #define MC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT 0x40 6698 /* enum: controller internal temperature on master core (internal ADC): degC */ 6699 #define MC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP 0x41 6700 /* enum: controller internal temperature sensor voltage on master core 6701 * (external ADC): mV 6702 */ 6703 #define MC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT_EXTADC 0x42 6704 /* enum: controller internal temperature on master core (external ADC): degC */ 6705 #define MC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC 0x43 6706 /* enum: controller internal temperature on slave core sensor voltage (internal 6707 * ADC): mV 6708 */ 6709 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT 0x44 6710 /* enum: controller internal temperature on slave core (internal ADC): degC */ 6711 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP 0x45 6712 /* enum: controller internal temperature on slave core sensor voltage (external 6713 * ADC): mV 6714 */ 6715 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT_EXTADC 0x46 6716 /* enum: controller internal temperature on slave core (external ADC): degC */ 6717 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC 0x47 6718 /* enum: Voltage supplied to the SODIMMs from their power supply: mV */ 6719 #define MC_CMD_SENSOR_SODIMM_VOUT 0x49 6720 /* enum: Temperature of SODIMM 0 (if installed): degC */ 6721 #define MC_CMD_SENSOR_SODIMM_0_TEMP 0x4a 6722 /* enum: Temperature of SODIMM 1 (if installed): degC */ 6723 #define MC_CMD_SENSOR_SODIMM_1_TEMP 0x4b 6724 /* enum: Voltage supplied to the QSFP #0 from their power supply: mV */ 6725 #define MC_CMD_SENSOR_PHY0_VCC 0x4c 6726 /* enum: Voltage supplied to the QSFP #1 from their power supply: mV */ 6727 #define MC_CMD_SENSOR_PHY1_VCC 0x4d 6728 /* enum: Controller die temperature (TDIODE): degC */ 6729 #define MC_CMD_SENSOR_CONTROLLER_TDIODE_TEMP 0x4e 6730 /* enum: Board temperature (front): degC */ 6731 #define MC_CMD_SENSOR_BOARD_FRONT_TEMP 0x4f 6732 /* enum: Board temperature (back): degC */ 6733 #define MC_CMD_SENSOR_BOARD_BACK_TEMP 0x50 6734 /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */ 6735 #define MC_CMD_SENSOR_ENTRY_OFST 4 6736 #define MC_CMD_SENSOR_ENTRY_LEN 8 6737 #define MC_CMD_SENSOR_ENTRY_LO_OFST 4 6738 #define MC_CMD_SENSOR_ENTRY_HI_OFST 8 6739 #define MC_CMD_SENSOR_ENTRY_MINNUM 0 6740 #define MC_CMD_SENSOR_ENTRY_MAXNUM 31 6741 6742 /* MC_CMD_SENSOR_INFO_EXT_OUT msgresponse */ 6743 #define MC_CMD_SENSOR_INFO_EXT_OUT_LENMIN 4 6744 #define MC_CMD_SENSOR_INFO_EXT_OUT_LENMAX 252 6745 #define MC_CMD_SENSOR_INFO_EXT_OUT_LEN(num) (4+8*(num)) 6746 #define MC_CMD_SENSOR_INFO_EXT_OUT_MASK_OFST 0 6747 /* Enum values, see field(s): */ 6748 /* MC_CMD_SENSOR_INFO_OUT */ 6749 #define MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_LBN 31 6750 #define MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_WIDTH 1 6751 /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */ 6752 /* MC_CMD_SENSOR_ENTRY_OFST 4 */ 6753 /* MC_CMD_SENSOR_ENTRY_LEN 8 */ 6754 /* MC_CMD_SENSOR_ENTRY_LO_OFST 4 */ 6755 /* MC_CMD_SENSOR_ENTRY_HI_OFST 8 */ 6756 /* MC_CMD_SENSOR_ENTRY_MINNUM 0 */ 6757 /* MC_CMD_SENSOR_ENTRY_MAXNUM 31 */ 6758 6759 /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF structuredef */ 6760 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_LEN 8 6761 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_OFST 0 6762 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LEN 2 6763 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LBN 0 6764 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_WIDTH 16 6765 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_OFST 2 6766 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LEN 2 6767 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LBN 16 6768 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_WIDTH 16 6769 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_OFST 4 6770 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LEN 2 6771 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LBN 32 6772 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_WIDTH 16 6773 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_OFST 6 6774 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LEN 2 6775 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LBN 48 6776 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_WIDTH 16 6777 6778 6779 /***********************************/ 6780 /* MC_CMD_READ_SENSORS 6781 * Returns the current reading from each sensor. DMAs an array of sensor 6782 * readings, in order of sensor type (but without gaps for unimplemented 6783 * sensors), into host memory. Each array element is a 6784 * MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF dword. 6785 * 6786 * If the request does not contain the LENGTH field then only sensors 0 to 30 6787 * are reported, to avoid DMA buffer overflow in older host software. If the 6788 * sensor reading require more space than the LENGTH allows, then return 6789 * EINVAL. 6790 * 6791 * The MC will send a SENSOREVT event every time any sensor changes state. The 6792 * driver is responsible for ensuring that it doesn't miss any events. The 6793 * board will function normally if all sensors are in STATE_OK or 6794 * STATE_WARNING. Otherwise the board should not be expected to function. 6795 */ 6796 #define MC_CMD_READ_SENSORS 0x42 6797 #undef MC_CMD_0x42_PRIVILEGE_CTG 6798 6799 #define MC_CMD_0x42_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6800 6801 /* MC_CMD_READ_SENSORS_IN msgrequest */ 6802 #define MC_CMD_READ_SENSORS_IN_LEN 8 6803 /* DMA address of host buffer for sensor readings (must be 4Kbyte aligned). */ 6804 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_OFST 0 6805 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LEN 8 6806 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_OFST 0 6807 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_OFST 4 6808 6809 /* MC_CMD_READ_SENSORS_EXT_IN msgrequest */ 6810 #define MC_CMD_READ_SENSORS_EXT_IN_LEN 12 6811 /* DMA address of host buffer for sensor readings (must be 4Kbyte aligned). */ 6812 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_OFST 0 6813 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LEN 8 6814 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_OFST 0 6815 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_HI_OFST 4 6816 /* Size in bytes of host buffer. */ 6817 #define MC_CMD_READ_SENSORS_EXT_IN_LENGTH_OFST 8 6818 6819 /* MC_CMD_READ_SENSORS_OUT msgresponse */ 6820 #define MC_CMD_READ_SENSORS_OUT_LEN 0 6821 6822 /* MC_CMD_READ_SENSORS_EXT_OUT msgresponse */ 6823 #define MC_CMD_READ_SENSORS_EXT_OUT_LEN 0 6824 6825 /* MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF structuredef */ 6826 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_LEN 4 6827 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_OFST 0 6828 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LEN 2 6829 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LBN 0 6830 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_WIDTH 16 6831 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_OFST 2 6832 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LEN 1 6833 /* enum: Ok. */ 6834 #define MC_CMD_SENSOR_STATE_OK 0x0 6835 /* enum: Breached warning threshold. */ 6836 #define MC_CMD_SENSOR_STATE_WARNING 0x1 6837 /* enum: Breached fatal threshold. */ 6838 #define MC_CMD_SENSOR_STATE_FATAL 0x2 6839 /* enum: Fault with sensor. */ 6840 #define MC_CMD_SENSOR_STATE_BROKEN 0x3 6841 /* enum: Sensor is working but does not currently have a reading. */ 6842 #define MC_CMD_SENSOR_STATE_NO_READING 0x4 6843 /* enum: Sensor initialisation failed. */ 6844 #define MC_CMD_SENSOR_STATE_INIT_FAILED 0x5 6845 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LBN 16 6846 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_WIDTH 8 6847 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_OFST 3 6848 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_LEN 1 6849 /* Enum values, see field(s): */ 6850 /* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */ 6851 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_LBN 24 6852 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_WIDTH 8 6853 6854 6855 /***********************************/ 6856 /* MC_CMD_GET_PHY_STATE 6857 * Report current state of PHY. A 'zombie' PHY is a PHY that has failed to boot 6858 * (e.g. due to missing or corrupted firmware). Locks required: None. Return 6859 * code: 0 6860 */ 6861 #define MC_CMD_GET_PHY_STATE 0x43 6862 #undef MC_CMD_0x43_PRIVILEGE_CTG 6863 6864 #define MC_CMD_0x43_PRIVILEGE_CTG SRIOV_CTG_GENERAL 6865 6866 /* MC_CMD_GET_PHY_STATE_IN msgrequest */ 6867 #define MC_CMD_GET_PHY_STATE_IN_LEN 0 6868 6869 /* MC_CMD_GET_PHY_STATE_OUT msgresponse */ 6870 #define MC_CMD_GET_PHY_STATE_OUT_LEN 4 6871 #define MC_CMD_GET_PHY_STATE_OUT_STATE_OFST 0 6872 /* enum: Ok. */ 6873 #define MC_CMD_PHY_STATE_OK 0x1 6874 /* enum: Faulty. */ 6875 #define MC_CMD_PHY_STATE_ZOMBIE 0x2 6876 6877 6878 /***********************************/ 6879 /* MC_CMD_SETUP_8021QBB 6880 * 802.1Qbb control. 8 Tx queues that map to priorities 0 - 7. Use all 1s to 6881 * disable 802.Qbb for a given priority. 6882 */ 6883 #define MC_CMD_SETUP_8021QBB 0x44 6884 6885 /* MC_CMD_SETUP_8021QBB_IN msgrequest */ 6886 #define MC_CMD_SETUP_8021QBB_IN_LEN 32 6887 #define MC_CMD_SETUP_8021QBB_IN_TXQS_OFST 0 6888 #define MC_CMD_SETUP_8021QBB_IN_TXQS_LEN 32 6889 6890 /* MC_CMD_SETUP_8021QBB_OUT msgresponse */ 6891 #define MC_CMD_SETUP_8021QBB_OUT_LEN 0 6892 6893 6894 /***********************************/ 6895 /* MC_CMD_WOL_FILTER_GET 6896 * Retrieve ID of any WoL filters. Locks required: None. Returns: 0, ENOSYS 6897 */ 6898 #define MC_CMD_WOL_FILTER_GET 0x45 6899 #undef MC_CMD_0x45_PRIVILEGE_CTG 6900 6901 #define MC_CMD_0x45_PRIVILEGE_CTG SRIOV_CTG_LINK 6902 6903 /* MC_CMD_WOL_FILTER_GET_IN msgrequest */ 6904 #define MC_CMD_WOL_FILTER_GET_IN_LEN 0 6905 6906 /* MC_CMD_WOL_FILTER_GET_OUT msgresponse */ 6907 #define MC_CMD_WOL_FILTER_GET_OUT_LEN 4 6908 #define MC_CMD_WOL_FILTER_GET_OUT_FILTER_ID_OFST 0 6909 6910 6911 /***********************************/ 6912 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD 6913 * Add a protocol offload to NIC for lights-out state. Locks required: None. 6914 * Returns: 0, ENOSYS 6915 */ 6916 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD 0x46 6917 #undef MC_CMD_0x46_PRIVILEGE_CTG 6918 6919 #define MC_CMD_0x46_PRIVILEGE_CTG SRIOV_CTG_LINK 6920 6921 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN msgrequest */ 6922 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMIN 8 6923 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMAX 252 6924 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LEN(num) (4+4*(num)) 6925 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 6926 #define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_ARP 0x1 /* enum */ 6927 #define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_NS 0x2 /* enum */ 6928 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_OFST 4 6929 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_LEN 4 6930 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MINNUM 1 6931 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MAXNUM 62 6932 6933 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP msgrequest */ 6934 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_LEN 14 6935 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */ 6936 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_OFST 4 6937 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_LEN 6 6938 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_IP_OFST 10 6939 6940 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS msgrequest */ 6941 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_LEN 42 6942 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */ 6943 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_OFST 4 6944 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_LEN 6 6945 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_OFST 10 6946 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_LEN 16 6947 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_OFST 26 6948 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_LEN 16 6949 6950 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT msgresponse */ 6951 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_LEN 4 6952 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_FILTER_ID_OFST 0 6953 6954 6955 /***********************************/ 6956 /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD 6957 * Remove a protocol offload from NIC for lights-out state. Locks required: 6958 * None. Returns: 0, ENOSYS 6959 */ 6960 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD 0x47 6961 #undef MC_CMD_0x47_PRIVILEGE_CTG 6962 6963 #define MC_CMD_0x47_PRIVILEGE_CTG SRIOV_CTG_LINK 6964 6965 /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN msgrequest */ 6966 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_LEN 8 6967 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 6968 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_FILTER_ID_OFST 4 6969 6970 /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT msgresponse */ 6971 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT_LEN 0 6972 6973 6974 /***********************************/ 6975 /* MC_CMD_MAC_RESET_RESTORE 6976 * Restore MAC after block reset. Locks required: None. Returns: 0. 6977 */ 6978 #define MC_CMD_MAC_RESET_RESTORE 0x48 6979 6980 /* MC_CMD_MAC_RESET_RESTORE_IN msgrequest */ 6981 #define MC_CMD_MAC_RESET_RESTORE_IN_LEN 0 6982 6983 /* MC_CMD_MAC_RESET_RESTORE_OUT msgresponse */ 6984 #define MC_CMD_MAC_RESET_RESTORE_OUT_LEN 0 6985 6986 6987 /***********************************/ 6988 /* MC_CMD_TESTASSERT 6989 * Deliberately trigger an assert-detonation in the firmware for testing 6990 * purposes (i.e. to allow tests that the driver copes gracefully). Locks 6991 * required: None Returns: 0 6992 */ 6993 #define MC_CMD_TESTASSERT 0x49 6994 #undef MC_CMD_0x49_PRIVILEGE_CTG 6995 6996 #define MC_CMD_0x49_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6997 6998 /* MC_CMD_TESTASSERT_IN msgrequest */ 6999 #define MC_CMD_TESTASSERT_IN_LEN 0 7000 7001 /* MC_CMD_TESTASSERT_OUT msgresponse */ 7002 #define MC_CMD_TESTASSERT_OUT_LEN 0 7003 7004 /* MC_CMD_TESTASSERT_V2_IN msgrequest */ 7005 #define MC_CMD_TESTASSERT_V2_IN_LEN 4 7006 /* How to provoke the assertion */ 7007 #define MC_CMD_TESTASSERT_V2_IN_TYPE_OFST 0 7008 /* enum: Assert using the FAIL_ASSERTION_WITH_USEFUL_VALUES macro. Unless 7009 * you're testing firmware, this is what you want. 7010 */ 7011 #define MC_CMD_TESTASSERT_V2_IN_FAIL_ASSERTION_WITH_USEFUL_VALUES 0x0 7012 /* enum: Assert using assert(0); */ 7013 #define MC_CMD_TESTASSERT_V2_IN_ASSERT_FALSE 0x1 7014 /* enum: Deliberately trigger a watchdog */ 7015 #define MC_CMD_TESTASSERT_V2_IN_WATCHDOG 0x2 7016 /* enum: Deliberately trigger a trap by loading from an invalid address */ 7017 #define MC_CMD_TESTASSERT_V2_IN_LOAD_TRAP 0x3 7018 /* enum: Deliberately trigger a trap by storing to an invalid address */ 7019 #define MC_CMD_TESTASSERT_V2_IN_STORE_TRAP 0x4 7020 /* enum: Jump to an invalid address */ 7021 #define MC_CMD_TESTASSERT_V2_IN_JUMP_TRAP 0x5 7022 7023 /* MC_CMD_TESTASSERT_V2_OUT msgresponse */ 7024 #define MC_CMD_TESTASSERT_V2_OUT_LEN 0 7025 7026 7027 /***********************************/ 7028 /* MC_CMD_WORKAROUND 7029 * Enable/Disable a given workaround. The mcfw will return EINVAL if it doesn't 7030 * understand the given workaround number - which should not be treated as a 7031 * hard error by client code. This op does not imply any semantics about each 7032 * workaround, that's between the driver and the mcfw on a per-workaround 7033 * basis. Locks required: None. Returns: 0, EINVAL . 7034 */ 7035 #define MC_CMD_WORKAROUND 0x4a 7036 #undef MC_CMD_0x4a_PRIVILEGE_CTG 7037 7038 #define MC_CMD_0x4a_PRIVILEGE_CTG SRIOV_CTG_ADMIN 7039 7040 /* MC_CMD_WORKAROUND_IN msgrequest */ 7041 #define MC_CMD_WORKAROUND_IN_LEN 8 7042 /* The enums here must correspond with those in MC_CMD_GET_WORKAROUND. */ 7043 #define MC_CMD_WORKAROUND_IN_TYPE_OFST 0 7044 /* enum: Bug 17230 work around. */ 7045 #define MC_CMD_WORKAROUND_BUG17230 0x1 7046 /* enum: Bug 35388 work around (unsafe EVQ writes). */ 7047 #define MC_CMD_WORKAROUND_BUG35388 0x2 7048 /* enum: Bug35017 workaround (A64 tables must be identity map) */ 7049 #define MC_CMD_WORKAROUND_BUG35017 0x3 7050 /* enum: Bug 41750 present (MC_CMD_TRIGGER_INTERRUPT won't work) */ 7051 #define MC_CMD_WORKAROUND_BUG41750 0x4 7052 /* enum: Bug 42008 present (Interrupts can overtake associated events). Caution 7053 * - before adding code that queries this workaround, remember that there's 7054 * released Monza firmware that doesn't understand MC_CMD_WORKAROUND_BUG42008, 7055 * and will hence (incorrectly) report that the bug doesn't exist. 7056 */ 7057 #define MC_CMD_WORKAROUND_BUG42008 0x5 7058 /* enum: Bug 26807 features present in firmware (multicast filter chaining) 7059 * This feature cannot be turned on/off while there are any filters already 7060 * present. The behaviour in such case depends on the acting client's privilege 7061 * level. If the client has the admin privilege, then all functions that have 7062 * filters installed will be FLRed and the FLR_DONE flag will be set. Otherwise 7063 * the command will fail with MC_CMD_ERR_FILTERS_PRESENT. 7064 */ 7065 #define MC_CMD_WORKAROUND_BUG26807 0x6 7066 /* enum: Bug 61265 work around (broken EVQ TMR writes). */ 7067 #define MC_CMD_WORKAROUND_BUG61265 0x7 7068 /* 0 = disable the workaround indicated by TYPE; any non-zero value = enable 7069 * the workaround 7070 */ 7071 #define MC_CMD_WORKAROUND_IN_ENABLED_OFST 4 7072 7073 /* MC_CMD_WORKAROUND_OUT msgresponse */ 7074 #define MC_CMD_WORKAROUND_OUT_LEN 0 7075 7076 /* MC_CMD_WORKAROUND_EXT_OUT msgresponse: This response format will be used 7077 * when (TYPE == MC_CMD_WORKAROUND_BUG26807) 7078 */ 7079 #define MC_CMD_WORKAROUND_EXT_OUT_LEN 4 7080 #define MC_CMD_WORKAROUND_EXT_OUT_FLAGS_OFST 0 7081 #define MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN 0 7082 #define MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_WIDTH 1 7083 7084 7085 /***********************************/ 7086 /* MC_CMD_GET_PHY_MEDIA_INFO 7087 * Read media-specific data from PHY (e.g. SFP/SFP+ module ID information for 7088 * SFP+ PHYs). The 'media type' can be found via GET_PHY_CFG 7089 * (GET_PHY_CFG_OUT_MEDIA_TYPE); the valid 'page number' input values, and the 7090 * output data, are interpreted on a per-type basis. For SFP+: PAGE=0 or 1 7091 * returns a 128-byte block read from module I2C address 0xA0 offset 0 or 0x80. 7092 * Anything else: currently undefined. Locks required: None. Return code: 0. 7093 */ 7094 #define MC_CMD_GET_PHY_MEDIA_INFO 0x4b 7095 #undef MC_CMD_0x4b_PRIVILEGE_CTG 7096 7097 #define MC_CMD_0x4b_PRIVILEGE_CTG SRIOV_CTG_ADMIN 7098 7099 /* MC_CMD_GET_PHY_MEDIA_INFO_IN msgrequest */ 7100 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_LEN 4 7101 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_PAGE_OFST 0 7102 7103 /* MC_CMD_GET_PHY_MEDIA_INFO_OUT msgresponse */ 7104 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMIN 5 7105 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMAX 252 7106 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LEN(num) (4+1*(num)) 7107 /* in bytes */ 7108 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATALEN_OFST 0 7109 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_OFST 4 7110 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_LEN 1 7111 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MINNUM 1 7112 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MAXNUM 248 7113 7114 7115 /***********************************/ 7116 /* MC_CMD_NVRAM_TEST 7117 * Test a particular NVRAM partition for valid contents (where "valid" depends 7118 * on the type of partition). 7119 */ 7120 #define MC_CMD_NVRAM_TEST 0x4c 7121 #undef MC_CMD_0x4c_PRIVILEGE_CTG 7122 7123 #define MC_CMD_0x4c_PRIVILEGE_CTG SRIOV_CTG_ADMIN 7124 7125 /* MC_CMD_NVRAM_TEST_IN msgrequest */ 7126 #define MC_CMD_NVRAM_TEST_IN_LEN 4 7127 #define MC_CMD_NVRAM_TEST_IN_TYPE_OFST 0 7128 /* Enum values, see field(s): */ 7129 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 7130 7131 /* MC_CMD_NVRAM_TEST_OUT msgresponse */ 7132 #define MC_CMD_NVRAM_TEST_OUT_LEN 4 7133 #define MC_CMD_NVRAM_TEST_OUT_RESULT_OFST 0 7134 /* enum: Passed. */ 7135 #define MC_CMD_NVRAM_TEST_PASS 0x0 7136 /* enum: Failed. */ 7137 #define MC_CMD_NVRAM_TEST_FAIL 0x1 7138 /* enum: Not supported. */ 7139 #define MC_CMD_NVRAM_TEST_NOTSUPP 0x2 7140 7141 7142 /***********************************/ 7143 /* MC_CMD_MRSFP_TWEAK 7144 * Read status and/or set parameters for the 'mrsfp' driver in mr_rusty builds. 7145 * I2C I/O expander bits are always read; if equaliser parameters are supplied, 7146 * they are configured first. Locks required: None. Return code: 0, EINVAL. 7147 */ 7148 #define MC_CMD_MRSFP_TWEAK 0x4d 7149 7150 /* MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG msgrequest */ 7151 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_LEN 16 7152 /* 0-6 low->high de-emph. */ 7153 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_LEVEL_OFST 0 7154 /* 0-8 low->high ref.V */ 7155 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_DT_CFG_OFST 4 7156 /* 0-8 0-8 low->high boost */ 7157 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_BOOST_OFST 8 7158 /* 0-8 low->high ref.V */ 7159 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_DT_CFG_OFST 12 7160 7161 /* MC_CMD_MRSFP_TWEAK_IN_READ_ONLY msgrequest */ 7162 #define MC_CMD_MRSFP_TWEAK_IN_READ_ONLY_LEN 0 7163 7164 /* MC_CMD_MRSFP_TWEAK_OUT msgresponse */ 7165 #define MC_CMD_MRSFP_TWEAK_OUT_LEN 12 7166 /* input bits */ 7167 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_INPUTS_OFST 0 7168 /* output bits */ 7169 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_OUTPUTS_OFST 4 7170 /* direction */ 7171 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OFST 8 7172 /* enum: Out. */ 7173 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OUT 0x0 7174 /* enum: In. */ 7175 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_IN 0x1 7176 7177 7178 /***********************************/ 7179 /* MC_CMD_SENSOR_SET_LIMS 7180 * Adjusts the sensor limits. This is a warranty-voiding operation. Returns: 7181 * ENOENT if the sensor specified does not exist, EINVAL if the limits are out 7182 * of range. 7183 */ 7184 #define MC_CMD_SENSOR_SET_LIMS 0x4e 7185 #undef MC_CMD_0x4e_PRIVILEGE_CTG 7186 7187 #define MC_CMD_0x4e_PRIVILEGE_CTG SRIOV_CTG_ADMIN 7188 7189 /* MC_CMD_SENSOR_SET_LIMS_IN msgrequest */ 7190 #define MC_CMD_SENSOR_SET_LIMS_IN_LEN 20 7191 #define MC_CMD_SENSOR_SET_LIMS_IN_SENSOR_OFST 0 7192 /* Enum values, see field(s): */ 7193 /* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */ 7194 /* interpretation is is sensor-specific. */ 7195 #define MC_CMD_SENSOR_SET_LIMS_IN_LOW0_OFST 4 7196 /* interpretation is is sensor-specific. */ 7197 #define MC_CMD_SENSOR_SET_LIMS_IN_HI0_OFST 8 7198 /* interpretation is is sensor-specific. */ 7199 #define MC_CMD_SENSOR_SET_LIMS_IN_LOW1_OFST 12 7200 /* interpretation is is sensor-specific. */ 7201 #define MC_CMD_SENSOR_SET_LIMS_IN_HI1_OFST 16 7202 7203 /* MC_CMD_SENSOR_SET_LIMS_OUT msgresponse */ 7204 #define MC_CMD_SENSOR_SET_LIMS_OUT_LEN 0 7205 7206 7207 /***********************************/ 7208 /* MC_CMD_GET_RESOURCE_LIMITS 7209 */ 7210 #define MC_CMD_GET_RESOURCE_LIMITS 0x4f 7211 7212 /* MC_CMD_GET_RESOURCE_LIMITS_IN msgrequest */ 7213 #define MC_CMD_GET_RESOURCE_LIMITS_IN_LEN 0 7214 7215 /* MC_CMD_GET_RESOURCE_LIMITS_OUT msgresponse */ 7216 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_LEN 16 7217 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_BUFTBL_OFST 0 7218 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_EVQ_OFST 4 7219 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_RXQ_OFST 8 7220 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_TXQ_OFST 12 7221 7222 7223 /***********************************/ 7224 /* MC_CMD_NVRAM_PARTITIONS 7225 * Reads the list of available virtual NVRAM partition types. Locks required: 7226 * none. Returns: 0, EINVAL (bad type). 7227 */ 7228 #define MC_CMD_NVRAM_PARTITIONS 0x51 7229 #undef MC_CMD_0x51_PRIVILEGE_CTG 7230 7231 #define MC_CMD_0x51_PRIVILEGE_CTG SRIOV_CTG_ADMIN 7232 7233 /* MC_CMD_NVRAM_PARTITIONS_IN msgrequest */ 7234 #define MC_CMD_NVRAM_PARTITIONS_IN_LEN 0 7235 7236 /* MC_CMD_NVRAM_PARTITIONS_OUT msgresponse */ 7237 #define MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN 4 7238 #define MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX 252 7239 #define MC_CMD_NVRAM_PARTITIONS_OUT_LEN(num) (4+4*(num)) 7240 /* total number of partitions */ 7241 #define MC_CMD_NVRAM_PARTITIONS_OUT_NUM_PARTITIONS_OFST 0 7242 /* type ID code for each of NUM_PARTITIONS partitions */ 7243 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_OFST 4 7244 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_LEN 4 7245 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MINNUM 0 7246 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MAXNUM 62 7247 7248 7249 /***********************************/ 7250 /* MC_CMD_NVRAM_METADATA 7251 * Reads soft metadata for a virtual NVRAM partition type. Locks required: 7252 * none. Returns: 0, EINVAL (bad type). 7253 */ 7254 #define MC_CMD_NVRAM_METADATA 0x52 7255 #undef MC_CMD_0x52_PRIVILEGE_CTG 7256 7257 #define MC_CMD_0x52_PRIVILEGE_CTG SRIOV_CTG_ADMIN 7258 7259 /* MC_CMD_NVRAM_METADATA_IN msgrequest */ 7260 #define MC_CMD_NVRAM_METADATA_IN_LEN 4 7261 /* Partition type ID code */ 7262 #define MC_CMD_NVRAM_METADATA_IN_TYPE_OFST 0 7263 7264 /* MC_CMD_NVRAM_METADATA_OUT msgresponse */ 7265 #define MC_CMD_NVRAM_METADATA_OUT_LENMIN 20 7266 #define MC_CMD_NVRAM_METADATA_OUT_LENMAX 252 7267 #define MC_CMD_NVRAM_METADATA_OUT_LEN(num) (20+1*(num)) 7268 /* Partition type ID code */ 7269 #define MC_CMD_NVRAM_METADATA_OUT_TYPE_OFST 0 7270 #define MC_CMD_NVRAM_METADATA_OUT_FLAGS_OFST 4 7271 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN 0 7272 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_WIDTH 1 7273 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_LBN 1 7274 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_WIDTH 1 7275 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_LBN 2 7276 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_WIDTH 1 7277 /* Subtype ID code for content of this partition */ 7278 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_OFST 8 7279 /* 1st component of W.X.Y.Z version number for content of this partition */ 7280 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_W_OFST 12 7281 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_W_LEN 2 7282 /* 2nd component of W.X.Y.Z version number for content of this partition */ 7283 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_X_OFST 14 7284 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_X_LEN 2 7285 /* 3rd component of W.X.Y.Z version number for content of this partition */ 7286 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Y_OFST 16 7287 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Y_LEN 2 7288 /* 4th component of W.X.Y.Z version number for content of this partition */ 7289 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Z_OFST 18 7290 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Z_LEN 2 7291 /* Zero-terminated string describing the content of this partition */ 7292 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_OFST 20 7293 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_LEN 1 7294 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MINNUM 0 7295 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MAXNUM 232 7296 7297 7298 /***********************************/ 7299 /* MC_CMD_GET_MAC_ADDRESSES 7300 * Returns the base MAC, count and stride for the requesting function 7301 */ 7302 #define MC_CMD_GET_MAC_ADDRESSES 0x55 7303 #undef MC_CMD_0x55_PRIVILEGE_CTG 7304 7305 #define MC_CMD_0x55_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7306 7307 /* MC_CMD_GET_MAC_ADDRESSES_IN msgrequest */ 7308 #define MC_CMD_GET_MAC_ADDRESSES_IN_LEN 0 7309 7310 /* MC_CMD_GET_MAC_ADDRESSES_OUT msgresponse */ 7311 #define MC_CMD_GET_MAC_ADDRESSES_OUT_LEN 16 7312 /* Base MAC address */ 7313 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE_OFST 0 7314 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE_LEN 6 7315 /* Padding */ 7316 #define MC_CMD_GET_MAC_ADDRESSES_OUT_RESERVED_OFST 6 7317 #define MC_CMD_GET_MAC_ADDRESSES_OUT_RESERVED_LEN 2 7318 /* Number of allocated MAC addresses */ 7319 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_COUNT_OFST 8 7320 /* Spacing of allocated MAC addresses */ 7321 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_STRIDE_OFST 12 7322 7323 7324 /***********************************/ 7325 /* MC_CMD_CLP 7326 * Perform a CLP related operation 7327 */ 7328 #define MC_CMD_CLP 0x56 7329 #undef MC_CMD_0x56_PRIVILEGE_CTG 7330 7331 #define MC_CMD_0x56_PRIVILEGE_CTG SRIOV_CTG_ADMIN 7332 7333 /* MC_CMD_CLP_IN msgrequest */ 7334 #define MC_CMD_CLP_IN_LEN 4 7335 /* Sub operation */ 7336 #define MC_CMD_CLP_IN_OP_OFST 0 7337 /* enum: Return to factory default settings */ 7338 #define MC_CMD_CLP_OP_DEFAULT 0x1 7339 /* enum: Set MAC address */ 7340 #define MC_CMD_CLP_OP_SET_MAC 0x2 7341 /* enum: Get MAC address */ 7342 #define MC_CMD_CLP_OP_GET_MAC 0x3 7343 /* enum: Set UEFI/GPXE boot mode */ 7344 #define MC_CMD_CLP_OP_SET_BOOT 0x4 7345 /* enum: Get UEFI/GPXE boot mode */ 7346 #define MC_CMD_CLP_OP_GET_BOOT 0x5 7347 7348 /* MC_CMD_CLP_OUT msgresponse */ 7349 #define MC_CMD_CLP_OUT_LEN 0 7350 7351 /* MC_CMD_CLP_IN_DEFAULT msgrequest */ 7352 #define MC_CMD_CLP_IN_DEFAULT_LEN 4 7353 /* MC_CMD_CLP_IN_OP_OFST 0 */ 7354 7355 /* MC_CMD_CLP_OUT_DEFAULT msgresponse */ 7356 #define MC_CMD_CLP_OUT_DEFAULT_LEN 0 7357 7358 /* MC_CMD_CLP_IN_SET_MAC msgrequest */ 7359 #define MC_CMD_CLP_IN_SET_MAC_LEN 12 7360 /* MC_CMD_CLP_IN_OP_OFST 0 */ 7361 /* MAC address assigned to port */ 7362 #define MC_CMD_CLP_IN_SET_MAC_ADDR_OFST 4 7363 #define MC_CMD_CLP_IN_SET_MAC_ADDR_LEN 6 7364 /* Padding */ 7365 #define MC_CMD_CLP_IN_SET_MAC_RESERVED_OFST 10 7366 #define MC_CMD_CLP_IN_SET_MAC_RESERVED_LEN 2 7367 7368 /* MC_CMD_CLP_OUT_SET_MAC msgresponse */ 7369 #define MC_CMD_CLP_OUT_SET_MAC_LEN 0 7370 7371 /* MC_CMD_CLP_IN_GET_MAC msgrequest */ 7372 #define MC_CMD_CLP_IN_GET_MAC_LEN 4 7373 /* MC_CMD_CLP_IN_OP_OFST 0 */ 7374 7375 /* MC_CMD_CLP_OUT_GET_MAC msgresponse */ 7376 #define MC_CMD_CLP_OUT_GET_MAC_LEN 8 7377 /* MAC address assigned to port */ 7378 #define MC_CMD_CLP_OUT_GET_MAC_ADDR_OFST 0 7379 #define MC_CMD_CLP_OUT_GET_MAC_ADDR_LEN 6 7380 /* Padding */ 7381 #define MC_CMD_CLP_OUT_GET_MAC_RESERVED_OFST 6 7382 #define MC_CMD_CLP_OUT_GET_MAC_RESERVED_LEN 2 7383 7384 /* MC_CMD_CLP_IN_SET_BOOT msgrequest */ 7385 #define MC_CMD_CLP_IN_SET_BOOT_LEN 5 7386 /* MC_CMD_CLP_IN_OP_OFST 0 */ 7387 /* Boot flag */ 7388 #define MC_CMD_CLP_IN_SET_BOOT_FLAG_OFST 4 7389 #define MC_CMD_CLP_IN_SET_BOOT_FLAG_LEN 1 7390 7391 /* MC_CMD_CLP_OUT_SET_BOOT msgresponse */ 7392 #define MC_CMD_CLP_OUT_SET_BOOT_LEN 0 7393 7394 /* MC_CMD_CLP_IN_GET_BOOT msgrequest */ 7395 #define MC_CMD_CLP_IN_GET_BOOT_LEN 4 7396 /* MC_CMD_CLP_IN_OP_OFST 0 */ 7397 7398 /* MC_CMD_CLP_OUT_GET_BOOT msgresponse */ 7399 #define MC_CMD_CLP_OUT_GET_BOOT_LEN 4 7400 /* Boot flag */ 7401 #define MC_CMD_CLP_OUT_GET_BOOT_FLAG_OFST 0 7402 #define MC_CMD_CLP_OUT_GET_BOOT_FLAG_LEN 1 7403 /* Padding */ 7404 #define MC_CMD_CLP_OUT_GET_BOOT_RESERVED_OFST 1 7405 #define MC_CMD_CLP_OUT_GET_BOOT_RESERVED_LEN 3 7406 7407 7408 /***********************************/ 7409 /* MC_CMD_MUM 7410 * Perform a MUM operation 7411 */ 7412 #define MC_CMD_MUM 0x57 7413 #undef MC_CMD_0x57_PRIVILEGE_CTG 7414 7415 #define MC_CMD_0x57_PRIVILEGE_CTG SRIOV_CTG_ADMIN 7416 7417 /* MC_CMD_MUM_IN msgrequest */ 7418 #define MC_CMD_MUM_IN_LEN 4 7419 #define MC_CMD_MUM_IN_OP_HDR_OFST 0 7420 #define MC_CMD_MUM_IN_OP_LBN 0 7421 #define MC_CMD_MUM_IN_OP_WIDTH 8 7422 /* enum: NULL MCDI command to MUM */ 7423 #define MC_CMD_MUM_OP_NULL 0x1 7424 /* enum: Get MUM version */ 7425 #define MC_CMD_MUM_OP_GET_VERSION 0x2 7426 /* enum: Issue raw I2C command to MUM */ 7427 #define MC_CMD_MUM_OP_RAW_CMD 0x3 7428 /* enum: Read from registers on devices connected to MUM. */ 7429 #define MC_CMD_MUM_OP_READ 0x4 7430 /* enum: Write to registers on devices connected to MUM. */ 7431 #define MC_CMD_MUM_OP_WRITE 0x5 7432 /* enum: Control UART logging. */ 7433 #define MC_CMD_MUM_OP_LOG 0x6 7434 /* enum: Operations on MUM GPIO lines */ 7435 #define MC_CMD_MUM_OP_GPIO 0x7 7436 /* enum: Get sensor readings from MUM */ 7437 #define MC_CMD_MUM_OP_READ_SENSORS 0x8 7438 /* enum: Initiate clock programming on the MUM */ 7439 #define MC_CMD_MUM_OP_PROGRAM_CLOCKS 0x9 7440 /* enum: Initiate FPGA load from flash on the MUM */ 7441 #define MC_CMD_MUM_OP_FPGA_LOAD 0xa 7442 /* enum: Request sensor reading from MUM ADC resulting from earlier request via 7443 * MUM ATB 7444 */ 7445 #define MC_CMD_MUM_OP_READ_ATB_SENSOR 0xb 7446 /* enum: Send commands relating to the QSFP ports via the MUM for PHY 7447 * operations 7448 */ 7449 #define MC_CMD_MUM_OP_QSFP 0xc 7450 /* enum: Request discrete and SODIMM DDR info (type, size, speed grade, voltage 7451 * level) from MUM 7452 */ 7453 #define MC_CMD_MUM_OP_READ_DDR_INFO 0xd 7454 7455 /* MC_CMD_MUM_IN_NULL msgrequest */ 7456 #define MC_CMD_MUM_IN_NULL_LEN 4 7457 /* MUM cmd header */ 7458 #define MC_CMD_MUM_IN_CMD_OFST 0 7459 7460 /* MC_CMD_MUM_IN_GET_VERSION msgrequest */ 7461 #define MC_CMD_MUM_IN_GET_VERSION_LEN 4 7462 /* MUM cmd header */ 7463 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7464 7465 /* MC_CMD_MUM_IN_READ msgrequest */ 7466 #define MC_CMD_MUM_IN_READ_LEN 16 7467 /* MUM cmd header */ 7468 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7469 /* ID of (device connected to MUM) to read from registers of */ 7470 #define MC_CMD_MUM_IN_READ_DEVICE_OFST 4 7471 /* enum: Hittite HMC1035 clock generator on Sorrento board */ 7472 #define MC_CMD_MUM_DEV_HITTITE 0x1 7473 /* enum: Hittite HMC1035 clock generator for NIC-side on Sorrento board */ 7474 #define MC_CMD_MUM_DEV_HITTITE_NIC 0x2 7475 /* 32-bit address to read from */ 7476 #define MC_CMD_MUM_IN_READ_ADDR_OFST 8 7477 /* Number of words to read. */ 7478 #define MC_CMD_MUM_IN_READ_NUMWORDS_OFST 12 7479 7480 /* MC_CMD_MUM_IN_WRITE msgrequest */ 7481 #define MC_CMD_MUM_IN_WRITE_LENMIN 16 7482 #define MC_CMD_MUM_IN_WRITE_LENMAX 252 7483 #define MC_CMD_MUM_IN_WRITE_LEN(num) (12+4*(num)) 7484 /* MUM cmd header */ 7485 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7486 /* ID of (device connected to MUM) to write to registers of */ 7487 #define MC_CMD_MUM_IN_WRITE_DEVICE_OFST 4 7488 /* enum: Hittite HMC1035 clock generator on Sorrento board */ 7489 /* MC_CMD_MUM_DEV_HITTITE 0x1 */ 7490 /* 32-bit address to write to */ 7491 #define MC_CMD_MUM_IN_WRITE_ADDR_OFST 8 7492 /* Words to write */ 7493 #define MC_CMD_MUM_IN_WRITE_BUFFER_OFST 12 7494 #define MC_CMD_MUM_IN_WRITE_BUFFER_LEN 4 7495 #define MC_CMD_MUM_IN_WRITE_BUFFER_MINNUM 1 7496 #define MC_CMD_MUM_IN_WRITE_BUFFER_MAXNUM 60 7497 7498 /* MC_CMD_MUM_IN_RAW_CMD msgrequest */ 7499 #define MC_CMD_MUM_IN_RAW_CMD_LENMIN 17 7500 #define MC_CMD_MUM_IN_RAW_CMD_LENMAX 252 7501 #define MC_CMD_MUM_IN_RAW_CMD_LEN(num) (16+1*(num)) 7502 /* MUM cmd header */ 7503 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7504 /* MUM I2C cmd code */ 7505 #define MC_CMD_MUM_IN_RAW_CMD_CMD_CODE_OFST 4 7506 /* Number of bytes to write */ 7507 #define MC_CMD_MUM_IN_RAW_CMD_NUM_WRITE_OFST 8 7508 /* Number of bytes to read */ 7509 #define MC_CMD_MUM_IN_RAW_CMD_NUM_READ_OFST 12 7510 /* Bytes to write */ 7511 #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_OFST 16 7512 #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_LEN 1 7513 #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_MINNUM 1 7514 #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_MAXNUM 236 7515 7516 /* MC_CMD_MUM_IN_LOG msgrequest */ 7517 #define MC_CMD_MUM_IN_LOG_LEN 8 7518 /* MUM cmd header */ 7519 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7520 #define MC_CMD_MUM_IN_LOG_OP_OFST 4 7521 #define MC_CMD_MUM_IN_LOG_OP_UART 0x1 /* enum */ 7522 7523 /* MC_CMD_MUM_IN_LOG_OP_UART msgrequest */ 7524 #define MC_CMD_MUM_IN_LOG_OP_UART_LEN 12 7525 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7526 /* MC_CMD_MUM_IN_LOG_OP_OFST 4 */ 7527 /* Enable/disable debug output to UART */ 7528 #define MC_CMD_MUM_IN_LOG_OP_UART_ENABLE_OFST 8 7529 7530 /* MC_CMD_MUM_IN_GPIO msgrequest */ 7531 #define MC_CMD_MUM_IN_GPIO_LEN 8 7532 /* MUM cmd header */ 7533 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7534 #define MC_CMD_MUM_IN_GPIO_HDR_OFST 4 7535 #define MC_CMD_MUM_IN_GPIO_OPCODE_LBN 0 7536 #define MC_CMD_MUM_IN_GPIO_OPCODE_WIDTH 8 7537 #define MC_CMD_MUM_IN_GPIO_IN_READ 0x0 /* enum */ 7538 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE 0x1 /* enum */ 7539 #define MC_CMD_MUM_IN_GPIO_OUT_READ 0x2 /* enum */ 7540 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE 0x3 /* enum */ 7541 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ 0x4 /* enum */ 7542 #define MC_CMD_MUM_IN_GPIO_OP 0x5 /* enum */ 7543 7544 /* MC_CMD_MUM_IN_GPIO_IN_READ msgrequest */ 7545 #define MC_CMD_MUM_IN_GPIO_IN_READ_LEN 8 7546 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7547 #define MC_CMD_MUM_IN_GPIO_IN_READ_HDR_OFST 4 7548 7549 /* MC_CMD_MUM_IN_GPIO_OUT_WRITE msgrequest */ 7550 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_LEN 16 7551 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7552 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_HDR_OFST 4 7553 /* The first 32-bit word to be written to the GPIO OUT register. */ 7554 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK1_OFST 8 7555 /* The second 32-bit word to be written to the GPIO OUT register. */ 7556 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK2_OFST 12 7557 7558 /* MC_CMD_MUM_IN_GPIO_OUT_READ msgrequest */ 7559 #define MC_CMD_MUM_IN_GPIO_OUT_READ_LEN 8 7560 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7561 #define MC_CMD_MUM_IN_GPIO_OUT_READ_HDR_OFST 4 7562 7563 /* MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE msgrequest */ 7564 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_LEN 16 7565 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7566 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_HDR_OFST 4 7567 /* The first 32-bit word to be written to the GPIO OUT ENABLE register. */ 7568 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK1_OFST 8 7569 /* The second 32-bit word to be written to the GPIO OUT ENABLE register. */ 7570 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK2_OFST 12 7571 7572 /* MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ msgrequest */ 7573 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_LEN 8 7574 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7575 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_HDR_OFST 4 7576 7577 /* MC_CMD_MUM_IN_GPIO_OP msgrequest */ 7578 #define MC_CMD_MUM_IN_GPIO_OP_LEN 8 7579 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7580 #define MC_CMD_MUM_IN_GPIO_OP_HDR_OFST 4 7581 #define MC_CMD_MUM_IN_GPIO_OP_BITWISE_OP_LBN 8 7582 #define MC_CMD_MUM_IN_GPIO_OP_BITWISE_OP_WIDTH 8 7583 #define MC_CMD_MUM_IN_GPIO_OP_OUT_READ 0x0 /* enum */ 7584 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE 0x1 /* enum */ 7585 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG 0x2 /* enum */ 7586 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE 0x3 /* enum */ 7587 #define MC_CMD_MUM_IN_GPIO_OP_GPIO_NUMBER_LBN 16 7588 #define MC_CMD_MUM_IN_GPIO_OP_GPIO_NUMBER_WIDTH 8 7589 7590 /* MC_CMD_MUM_IN_GPIO_OP_OUT_READ msgrequest */ 7591 #define MC_CMD_MUM_IN_GPIO_OP_OUT_READ_LEN 8 7592 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7593 #define MC_CMD_MUM_IN_GPIO_OP_OUT_READ_HDR_OFST 4 7594 7595 /* MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE msgrequest */ 7596 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_LEN 8 7597 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7598 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_HDR_OFST 4 7599 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_WRITEBIT_LBN 24 7600 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_WRITEBIT_WIDTH 8 7601 7602 /* MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG msgrequest */ 7603 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_LEN 8 7604 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7605 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_HDR_OFST 4 7606 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_CFG_LBN 24 7607 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_CFG_WIDTH 8 7608 7609 /* MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE msgrequest */ 7610 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_LEN 8 7611 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7612 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_HDR_OFST 4 7613 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_ENABLEBIT_LBN 24 7614 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_ENABLEBIT_WIDTH 8 7615 7616 /* MC_CMD_MUM_IN_READ_SENSORS msgrequest */ 7617 #define MC_CMD_MUM_IN_READ_SENSORS_LEN 8 7618 /* MUM cmd header */ 7619 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7620 #define MC_CMD_MUM_IN_READ_SENSORS_PARAMS_OFST 4 7621 #define MC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_LBN 0 7622 #define MC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_WIDTH 8 7623 #define MC_CMD_MUM_IN_READ_SENSORS_NUM_SENSORS_LBN 8 7624 #define MC_CMD_MUM_IN_READ_SENSORS_NUM_SENSORS_WIDTH 8 7625 7626 /* MC_CMD_MUM_IN_PROGRAM_CLOCKS msgrequest */ 7627 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_LEN 12 7628 /* MUM cmd header */ 7629 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7630 /* Bit-mask of clocks to be programmed */ 7631 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_MASK_OFST 4 7632 #define MC_CMD_MUM_CLOCK_ID_FPGA 0x0 /* enum */ 7633 #define MC_CMD_MUM_CLOCK_ID_DDR 0x1 /* enum */ 7634 #define MC_CMD_MUM_CLOCK_ID_NIC 0x2 /* enum */ 7635 /* Control flags for clock programming */ 7636 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_FLAGS_OFST 8 7637 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_LBN 0 7638 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_WIDTH 1 7639 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_NIC_FROM_FPGA_LBN 1 7640 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_NIC_FROM_FPGA_WIDTH 1 7641 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_REF_FROM_XO_LBN 2 7642 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_REF_FROM_XO_WIDTH 1 7643 7644 /* MC_CMD_MUM_IN_FPGA_LOAD msgrequest */ 7645 #define MC_CMD_MUM_IN_FPGA_LOAD_LEN 8 7646 /* MUM cmd header */ 7647 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7648 /* Enable/Disable FPGA config from flash */ 7649 #define MC_CMD_MUM_IN_FPGA_LOAD_ENABLE_OFST 4 7650 7651 /* MC_CMD_MUM_IN_READ_ATB_SENSOR msgrequest */ 7652 #define MC_CMD_MUM_IN_READ_ATB_SENSOR_LEN 4 7653 /* MUM cmd header */ 7654 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7655 7656 /* MC_CMD_MUM_IN_QSFP msgrequest */ 7657 #define MC_CMD_MUM_IN_QSFP_LEN 12 7658 /* MUM cmd header */ 7659 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7660 #define MC_CMD_MUM_IN_QSFP_HDR_OFST 4 7661 #define MC_CMD_MUM_IN_QSFP_OPCODE_LBN 0 7662 #define MC_CMD_MUM_IN_QSFP_OPCODE_WIDTH 4 7663 #define MC_CMD_MUM_IN_QSFP_INIT 0x0 /* enum */ 7664 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE 0x1 /* enum */ 7665 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP 0x2 /* enum */ 7666 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO 0x3 /* enum */ 7667 #define MC_CMD_MUM_IN_QSFP_FILL_STATS 0x4 /* enum */ 7668 #define MC_CMD_MUM_IN_QSFP_POLL_BIST 0x5 /* enum */ 7669 #define MC_CMD_MUM_IN_QSFP_IDX_OFST 8 7670 7671 /* MC_CMD_MUM_IN_QSFP_INIT msgrequest */ 7672 #define MC_CMD_MUM_IN_QSFP_INIT_LEN 16 7673 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7674 #define MC_CMD_MUM_IN_QSFP_INIT_HDR_OFST 4 7675 #define MC_CMD_MUM_IN_QSFP_INIT_IDX_OFST 8 7676 #define MC_CMD_MUM_IN_QSFP_INIT_CAGE_OFST 12 7677 7678 /* MC_CMD_MUM_IN_QSFP_RECONFIGURE msgrequest */ 7679 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_LEN 24 7680 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7681 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_HDR_OFST 4 7682 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_IDX_OFST 8 7683 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_TX_DISABLE_OFST 12 7684 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LANES_OFST 16 7685 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LINK_SPEED_OFST 20 7686 7687 /* MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP msgrequest */ 7688 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_LEN 12 7689 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7690 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_HDR_OFST 4 7691 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_IDX_OFST 8 7692 7693 /* MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO msgrequest */ 7694 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_LEN 16 7695 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7696 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_HDR_OFST 4 7697 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_IDX_OFST 8 7698 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_PAGE_OFST 12 7699 7700 /* MC_CMD_MUM_IN_QSFP_FILL_STATS msgrequest */ 7701 #define MC_CMD_MUM_IN_QSFP_FILL_STATS_LEN 12 7702 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7703 #define MC_CMD_MUM_IN_QSFP_FILL_STATS_HDR_OFST 4 7704 #define MC_CMD_MUM_IN_QSFP_FILL_STATS_IDX_OFST 8 7705 7706 /* MC_CMD_MUM_IN_QSFP_POLL_BIST msgrequest */ 7707 #define MC_CMD_MUM_IN_QSFP_POLL_BIST_LEN 12 7708 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7709 #define MC_CMD_MUM_IN_QSFP_POLL_BIST_HDR_OFST 4 7710 #define MC_CMD_MUM_IN_QSFP_POLL_BIST_IDX_OFST 8 7711 7712 /* MC_CMD_MUM_IN_READ_DDR_INFO msgrequest */ 7713 #define MC_CMD_MUM_IN_READ_DDR_INFO_LEN 4 7714 /* MUM cmd header */ 7715 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7716 7717 /* MC_CMD_MUM_OUT msgresponse */ 7718 #define MC_CMD_MUM_OUT_LEN 0 7719 7720 /* MC_CMD_MUM_OUT_NULL msgresponse */ 7721 #define MC_CMD_MUM_OUT_NULL_LEN 0 7722 7723 /* MC_CMD_MUM_OUT_GET_VERSION msgresponse */ 7724 #define MC_CMD_MUM_OUT_GET_VERSION_LEN 12 7725 #define MC_CMD_MUM_OUT_GET_VERSION_FIRMWARE_OFST 0 7726 #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_OFST 4 7727 #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LEN 8 7728 #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LO_OFST 4 7729 #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_HI_OFST 8 7730 7731 /* MC_CMD_MUM_OUT_RAW_CMD msgresponse */ 7732 #define MC_CMD_MUM_OUT_RAW_CMD_LENMIN 1 7733 #define MC_CMD_MUM_OUT_RAW_CMD_LENMAX 252 7734 #define MC_CMD_MUM_OUT_RAW_CMD_LEN(num) (0+1*(num)) 7735 /* returned data */ 7736 #define MC_CMD_MUM_OUT_RAW_CMD_DATA_OFST 0 7737 #define MC_CMD_MUM_OUT_RAW_CMD_DATA_LEN 1 7738 #define MC_CMD_MUM_OUT_RAW_CMD_DATA_MINNUM 1 7739 #define MC_CMD_MUM_OUT_RAW_CMD_DATA_MAXNUM 252 7740 7741 /* MC_CMD_MUM_OUT_READ msgresponse */ 7742 #define MC_CMD_MUM_OUT_READ_LENMIN 4 7743 #define MC_CMD_MUM_OUT_READ_LENMAX 252 7744 #define MC_CMD_MUM_OUT_READ_LEN(num) (0+4*(num)) 7745 #define MC_CMD_MUM_OUT_READ_BUFFER_OFST 0 7746 #define MC_CMD_MUM_OUT_READ_BUFFER_LEN 4 7747 #define MC_CMD_MUM_OUT_READ_BUFFER_MINNUM 1 7748 #define MC_CMD_MUM_OUT_READ_BUFFER_MAXNUM 63 7749 7750 /* MC_CMD_MUM_OUT_WRITE msgresponse */ 7751 #define MC_CMD_MUM_OUT_WRITE_LEN 0 7752 7753 /* MC_CMD_MUM_OUT_LOG msgresponse */ 7754 #define MC_CMD_MUM_OUT_LOG_LEN 0 7755 7756 /* MC_CMD_MUM_OUT_LOG_OP_UART msgresponse */ 7757 #define MC_CMD_MUM_OUT_LOG_OP_UART_LEN 0 7758 7759 /* MC_CMD_MUM_OUT_GPIO_IN_READ msgresponse */ 7760 #define MC_CMD_MUM_OUT_GPIO_IN_READ_LEN 8 7761 /* The first 32-bit word read from the GPIO IN register. */ 7762 #define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK1_OFST 0 7763 /* The second 32-bit word read from the GPIO IN register. */ 7764 #define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK2_OFST 4 7765 7766 /* MC_CMD_MUM_OUT_GPIO_OUT_WRITE msgresponse */ 7767 #define MC_CMD_MUM_OUT_GPIO_OUT_WRITE_LEN 0 7768 7769 /* MC_CMD_MUM_OUT_GPIO_OUT_READ msgresponse */ 7770 #define MC_CMD_MUM_OUT_GPIO_OUT_READ_LEN 8 7771 /* The first 32-bit word read from the GPIO OUT register. */ 7772 #define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK1_OFST 0 7773 /* The second 32-bit word read from the GPIO OUT register. */ 7774 #define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK2_OFST 4 7775 7776 /* MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_WRITE msgresponse */ 7777 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_WRITE_LEN 0 7778 7779 /* MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ msgresponse */ 7780 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_LEN 8 7781 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK1_OFST 0 7782 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK2_OFST 4 7783 7784 /* MC_CMD_MUM_OUT_GPIO_OP_OUT_READ msgresponse */ 7785 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_LEN 4 7786 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_BIT_READ_OFST 0 7787 7788 /* MC_CMD_MUM_OUT_GPIO_OP_OUT_WRITE msgresponse */ 7789 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_WRITE_LEN 0 7790 7791 /* MC_CMD_MUM_OUT_GPIO_OP_OUT_CONFIG msgresponse */ 7792 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_CONFIG_LEN 0 7793 7794 /* MC_CMD_MUM_OUT_GPIO_OP_OUT_ENABLE msgresponse */ 7795 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_ENABLE_LEN 0 7796 7797 /* MC_CMD_MUM_OUT_READ_SENSORS msgresponse */ 7798 #define MC_CMD_MUM_OUT_READ_SENSORS_LENMIN 4 7799 #define MC_CMD_MUM_OUT_READ_SENSORS_LENMAX 252 7800 #define MC_CMD_MUM_OUT_READ_SENSORS_LEN(num) (0+4*(num)) 7801 #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_OFST 0 7802 #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_LEN 4 7803 #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_MINNUM 1 7804 #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_MAXNUM 63 7805 #define MC_CMD_MUM_OUT_READ_SENSORS_READING_LBN 0 7806 #define MC_CMD_MUM_OUT_READ_SENSORS_READING_WIDTH 16 7807 #define MC_CMD_MUM_OUT_READ_SENSORS_STATE_LBN 16 7808 #define MC_CMD_MUM_OUT_READ_SENSORS_STATE_WIDTH 8 7809 #define MC_CMD_MUM_OUT_READ_SENSORS_TYPE_LBN 24 7810 #define MC_CMD_MUM_OUT_READ_SENSORS_TYPE_WIDTH 8 7811 7812 /* MC_CMD_MUM_OUT_PROGRAM_CLOCKS msgresponse */ 7813 #define MC_CMD_MUM_OUT_PROGRAM_CLOCKS_LEN 4 7814 #define MC_CMD_MUM_OUT_PROGRAM_CLOCKS_OK_MASK_OFST 0 7815 7816 /* MC_CMD_MUM_OUT_FPGA_LOAD msgresponse */ 7817 #define MC_CMD_MUM_OUT_FPGA_LOAD_LEN 0 7818 7819 /* MC_CMD_MUM_OUT_READ_ATB_SENSOR msgresponse */ 7820 #define MC_CMD_MUM_OUT_READ_ATB_SENSOR_LEN 4 7821 #define MC_CMD_MUM_OUT_READ_ATB_SENSOR_RESULT_OFST 0 7822 7823 /* MC_CMD_MUM_OUT_QSFP_INIT msgresponse */ 7824 #define MC_CMD_MUM_OUT_QSFP_INIT_LEN 0 7825 7826 /* MC_CMD_MUM_OUT_QSFP_RECONFIGURE msgresponse */ 7827 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_LEN 8 7828 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LP_CAP_OFST 0 7829 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_FLAGS_OFST 4 7830 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_LBN 0 7831 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_WIDTH 1 7832 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_LBN 1 7833 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_WIDTH 1 7834 7835 /* MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP msgresponse */ 7836 #define MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_LEN 4 7837 #define MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_PORT_PHY_LP_CAP_OFST 0 7838 7839 /* MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO msgresponse */ 7840 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LENMIN 5 7841 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LENMAX 252 7842 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LEN(num) (4+1*(num)) 7843 /* in bytes */ 7844 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATALEN_OFST 0 7845 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_OFST 4 7846 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_LEN 1 7847 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_MINNUM 1 7848 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_MAXNUM 248 7849 7850 /* MC_CMD_MUM_OUT_QSFP_FILL_STATS msgresponse */ 7851 #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_LEN 8 7852 #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PMA_PMD_LINK_UP_OFST 0 7853 #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PCS_LINK_UP_OFST 4 7854 7855 /* MC_CMD_MUM_OUT_QSFP_POLL_BIST msgresponse */ 7856 #define MC_CMD_MUM_OUT_QSFP_POLL_BIST_LEN 4 7857 #define MC_CMD_MUM_OUT_QSFP_POLL_BIST_TEST_OFST 0 7858 7859 /* MC_CMD_MUM_OUT_READ_DDR_INFO msgresponse */ 7860 #define MC_CMD_MUM_OUT_READ_DDR_INFO_LENMIN 24 7861 #define MC_CMD_MUM_OUT_READ_DDR_INFO_LENMAX 248 7862 #define MC_CMD_MUM_OUT_READ_DDR_INFO_LEN(num) (8+8*(num)) 7863 /* Discrete (soldered) DDR resistor strap info */ 7864 #define MC_CMD_MUM_OUT_READ_DDR_INFO_DISCRETE_DDR_INFO_OFST 0 7865 #define MC_CMD_MUM_OUT_READ_DDR_INFO_VRATIO_LBN 0 7866 #define MC_CMD_MUM_OUT_READ_DDR_INFO_VRATIO_WIDTH 16 7867 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED1_LBN 16 7868 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED1_WIDTH 16 7869 /* Number of SODIMM info records */ 7870 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_RECORDS_OFST 4 7871 /* Array of SODIMM info records */ 7872 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_OFST 8 7873 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LEN 8 7874 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LO_OFST 8 7875 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_HI_OFST 12 7876 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MINNUM 2 7877 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MAXNUM 30 7878 #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK_ID_LBN 0 7879 #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK_ID_WIDTH 8 7880 /* enum: SODIMM bank 1 (Top SODIMM for Sorrento) */ 7881 #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK1 0x0 7882 /* enum: SODIMM bank 2 (Bottom SODDIMM for Sorrento) */ 7883 #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK2 0x1 7884 /* enum: Total number of SODIMM banks */ 7885 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_BANKS 0x2 7886 #define MC_CMD_MUM_OUT_READ_DDR_INFO_TYPE_LBN 8 7887 #define MC_CMD_MUM_OUT_READ_DDR_INFO_TYPE_WIDTH 8 7888 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RANK_LBN 16 7889 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RANK_WIDTH 4 7890 #define MC_CMD_MUM_OUT_READ_DDR_INFO_VOLTAGE_LBN 20 7891 #define MC_CMD_MUM_OUT_READ_DDR_INFO_VOLTAGE_WIDTH 4 7892 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NOT_POWERED 0x0 /* enum */ 7893 #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V25 0x1 /* enum */ 7894 #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V35 0x2 /* enum */ 7895 #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V5 0x3 /* enum */ 7896 /* enum: Values 5-15 are reserved for future usage */ 7897 #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V8 0x4 7898 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SIZE_LBN 24 7899 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SIZE_WIDTH 8 7900 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SPEED_LBN 32 7901 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SPEED_WIDTH 16 7902 #define MC_CMD_MUM_OUT_READ_DDR_INFO_STATE_LBN 48 7903 #define MC_CMD_MUM_OUT_READ_DDR_INFO_STATE_WIDTH 4 7904 /* enum: No module present */ 7905 #define MC_CMD_MUM_OUT_READ_DDR_INFO_ABSENT 0x0 7906 /* enum: Module present supported and powered on */ 7907 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_POWERED 0x1 7908 /* enum: Module present but bad type */ 7909 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_TYPE 0x2 7910 /* enum: Module present but incompatible voltage */ 7911 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_VOLTAGE 0x3 7912 /* enum: Module present but unknown SPD */ 7913 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_SPD 0x4 7914 /* enum: Module present but slot cannot support it */ 7915 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_SLOT 0x5 7916 /* enum: Modules may or may not be present, but cannot establish contact by I2C 7917 */ 7918 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NOT_REACHABLE 0x6 7919 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED2_LBN 52 7920 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED2_WIDTH 12 7921 7922 /* MC_CMD_RESOURCE_SPECIFIER enum */ 7923 /* enum: Any */ 7924 #define MC_CMD_RESOURCE_INSTANCE_ANY 0xffffffff 7925 /* enum: None */ 7926 #define MC_CMD_RESOURCE_INSTANCE_NONE 0xfffffffe 7927 7928 /* EVB_PORT_ID structuredef */ 7929 #define EVB_PORT_ID_LEN 4 7930 #define EVB_PORT_ID_PORT_ID_OFST 0 7931 /* enum: An invalid port handle. */ 7932 #define EVB_PORT_ID_NULL 0x0 7933 /* enum: The port assigned to this function.. */ 7934 #define EVB_PORT_ID_ASSIGNED 0x1000000 7935 /* enum: External network port 0 */ 7936 #define EVB_PORT_ID_MAC0 0x2000000 7937 /* enum: External network port 1 */ 7938 #define EVB_PORT_ID_MAC1 0x2000001 7939 /* enum: External network port 2 */ 7940 #define EVB_PORT_ID_MAC2 0x2000002 7941 /* enum: External network port 3 */ 7942 #define EVB_PORT_ID_MAC3 0x2000003 7943 #define EVB_PORT_ID_PORT_ID_LBN 0 7944 #define EVB_PORT_ID_PORT_ID_WIDTH 32 7945 7946 /* EVB_VLAN_TAG structuredef */ 7947 #define EVB_VLAN_TAG_LEN 2 7948 /* The VLAN tag value */ 7949 #define EVB_VLAN_TAG_VLAN_ID_LBN 0 7950 #define EVB_VLAN_TAG_VLAN_ID_WIDTH 12 7951 #define EVB_VLAN_TAG_MODE_LBN 12 7952 #define EVB_VLAN_TAG_MODE_WIDTH 4 7953 /* enum: Insert the VLAN. */ 7954 #define EVB_VLAN_TAG_INSERT 0x0 7955 /* enum: Replace the VLAN if already present. */ 7956 #define EVB_VLAN_TAG_REPLACE 0x1 7957 7958 /* BUFTBL_ENTRY structuredef */ 7959 #define BUFTBL_ENTRY_LEN 12 7960 /* the owner ID */ 7961 #define BUFTBL_ENTRY_OID_OFST 0 7962 #define BUFTBL_ENTRY_OID_LEN 2 7963 #define BUFTBL_ENTRY_OID_LBN 0 7964 #define BUFTBL_ENTRY_OID_WIDTH 16 7965 /* the page parameter as one of ESE_DZ_SMC_PAGE_SIZE_ */ 7966 #define BUFTBL_ENTRY_PGSZ_OFST 2 7967 #define BUFTBL_ENTRY_PGSZ_LEN 2 7968 #define BUFTBL_ENTRY_PGSZ_LBN 16 7969 #define BUFTBL_ENTRY_PGSZ_WIDTH 16 7970 /* the raw 64-bit address field from the SMC, not adjusted for page size */ 7971 #define BUFTBL_ENTRY_RAWADDR_OFST 4 7972 #define BUFTBL_ENTRY_RAWADDR_LEN 8 7973 #define BUFTBL_ENTRY_RAWADDR_LO_OFST 4 7974 #define BUFTBL_ENTRY_RAWADDR_HI_OFST 8 7975 #define BUFTBL_ENTRY_RAWADDR_LBN 32 7976 #define BUFTBL_ENTRY_RAWADDR_WIDTH 64 7977 7978 /* NVRAM_PARTITION_TYPE structuredef */ 7979 #define NVRAM_PARTITION_TYPE_LEN 2 7980 #define NVRAM_PARTITION_TYPE_ID_OFST 0 7981 #define NVRAM_PARTITION_TYPE_ID_LEN 2 7982 /* enum: Primary MC firmware partition */ 7983 #define NVRAM_PARTITION_TYPE_MC_FIRMWARE 0x100 7984 /* enum: Secondary MC firmware partition */ 7985 #define NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP 0x200 7986 /* enum: Expansion ROM partition */ 7987 #define NVRAM_PARTITION_TYPE_EXPANSION_ROM 0x300 7988 /* enum: Static configuration TLV partition */ 7989 #define NVRAM_PARTITION_TYPE_STATIC_CONFIG 0x400 7990 /* enum: Dynamic configuration TLV partition */ 7991 #define NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG 0x500 7992 /* enum: Expansion ROM configuration data for port 0 */ 7993 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0 0x600 7994 /* enum: Synonym for EXPROM_CONFIG_PORT0 as used in pmap files */ 7995 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG 0x600 7996 /* enum: Expansion ROM configuration data for port 1 */ 7997 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1 0x601 7998 /* enum: Expansion ROM configuration data for port 2 */ 7999 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2 0x602 8000 /* enum: Expansion ROM configuration data for port 3 */ 8001 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3 0x603 8002 /* enum: Non-volatile log output partition */ 8003 #define NVRAM_PARTITION_TYPE_LOG 0x700 8004 /* enum: Non-volatile log output of second core on dual-core device */ 8005 #define NVRAM_PARTITION_TYPE_LOG_SLAVE 0x701 8006 /* enum: Device state dump output partition */ 8007 #define NVRAM_PARTITION_TYPE_DUMP 0x800 8008 /* enum: Application license key storage partition */ 8009 #define NVRAM_PARTITION_TYPE_LICENSE 0x900 8010 /* enum: Start of range used for PHY partitions (low 8 bits are the PHY ID) */ 8011 #define NVRAM_PARTITION_TYPE_PHY_MIN 0xa00 8012 /* enum: End of range used for PHY partitions (low 8 bits are the PHY ID) */ 8013 #define NVRAM_PARTITION_TYPE_PHY_MAX 0xaff 8014 /* enum: Primary FPGA partition */ 8015 #define NVRAM_PARTITION_TYPE_FPGA 0xb00 8016 /* enum: Secondary FPGA partition */ 8017 #define NVRAM_PARTITION_TYPE_FPGA_BACKUP 0xb01 8018 /* enum: FC firmware partition */ 8019 #define NVRAM_PARTITION_TYPE_FC_FIRMWARE 0xb02 8020 /* enum: FC License partition */ 8021 #define NVRAM_PARTITION_TYPE_FC_LICENSE 0xb03 8022 /* enum: Non-volatile log output partition for FC */ 8023 #define NVRAM_PARTITION_TYPE_FC_LOG 0xb04 8024 /* enum: MUM firmware partition */ 8025 #define NVRAM_PARTITION_TYPE_MUM_FIRMWARE 0xc00 8026 /* enum: MUM Non-volatile log output partition. */ 8027 #define NVRAM_PARTITION_TYPE_MUM_LOG 0xc01 8028 /* enum: MUM Application table partition. */ 8029 #define NVRAM_PARTITION_TYPE_MUM_APPTABLE 0xc02 8030 /* enum: MUM boot rom partition. */ 8031 #define NVRAM_PARTITION_TYPE_MUM_BOOT_ROM 0xc03 8032 /* enum: MUM production signatures & calibration rom partition. */ 8033 #define NVRAM_PARTITION_TYPE_MUM_PROD_ROM 0xc04 8034 /* enum: MUM user signatures & calibration rom partition. */ 8035 #define NVRAM_PARTITION_TYPE_MUM_USER_ROM 0xc05 8036 /* enum: MUM fuses and lockbits partition. */ 8037 #define NVRAM_PARTITION_TYPE_MUM_FUSELOCK 0xc06 8038 /* enum: UEFI expansion ROM if separate from PXE */ 8039 #define NVRAM_PARTITION_TYPE_EXPANSION_UEFI 0xd00 8040 /* enum: Spare partition 0 */ 8041 #define NVRAM_PARTITION_TYPE_SPARE_0 0x1000 8042 /* enum: Used for XIP code of shmbooted images */ 8043 #define NVRAM_PARTITION_TYPE_XIP_SCRATCH 0x1100 8044 /* enum: Spare partition 2 */ 8045 #define NVRAM_PARTITION_TYPE_SPARE_2 0x1200 8046 /* enum: Manufacturing partition. Used during manufacture to pass information 8047 * between XJTAG and Manftest. 8048 */ 8049 #define NVRAM_PARTITION_TYPE_MANUFACTURING 0x1300 8050 /* enum: Spare partition 4 */ 8051 #define NVRAM_PARTITION_TYPE_SPARE_4 0x1400 8052 /* enum: Spare partition 5 */ 8053 #define NVRAM_PARTITION_TYPE_SPARE_5 0x1500 8054 /* enum: Partition for reporting MC status. See mc_flash_layout.h 8055 * medford_mc_status_hdr_t for layout on Medford. 8056 */ 8057 #define NVRAM_PARTITION_TYPE_STATUS 0x1600 8058 /* enum: Start of reserved value range (firmware may use for any purpose) */ 8059 #define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MIN 0xff00 8060 /* enum: End of reserved value range (firmware may use for any purpose) */ 8061 #define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MAX 0xfffd 8062 /* enum: Recovery partition map (provided if real map is missing or corrupt) */ 8063 #define NVRAM_PARTITION_TYPE_RECOVERY_MAP 0xfffe 8064 /* enum: Partition map (real map as stored in flash) */ 8065 #define NVRAM_PARTITION_TYPE_PARTITION_MAP 0xffff 8066 #define NVRAM_PARTITION_TYPE_ID_LBN 0 8067 #define NVRAM_PARTITION_TYPE_ID_WIDTH 16 8068 8069 /* LICENSED_APP_ID structuredef */ 8070 #define LICENSED_APP_ID_LEN 4 8071 #define LICENSED_APP_ID_ID_OFST 0 8072 /* enum: OpenOnload */ 8073 #define LICENSED_APP_ID_ONLOAD 0x1 8074 /* enum: PTP timestamping */ 8075 #define LICENSED_APP_ID_PTP 0x2 8076 /* enum: SolarCapture Pro */ 8077 #define LICENSED_APP_ID_SOLARCAPTURE_PRO 0x4 8078 /* enum: SolarSecure filter engine */ 8079 #define LICENSED_APP_ID_SOLARSECURE 0x8 8080 /* enum: Performance monitor */ 8081 #define LICENSED_APP_ID_PERF_MONITOR 0x10 8082 /* enum: SolarCapture Live */ 8083 #define LICENSED_APP_ID_SOLARCAPTURE_LIVE 0x20 8084 /* enum: Capture SolarSystem */ 8085 #define LICENSED_APP_ID_CAPTURE_SOLARSYSTEM 0x40 8086 /* enum: Network Access Control */ 8087 #define LICENSED_APP_ID_NETWORK_ACCESS_CONTROL 0x80 8088 /* enum: TCP Direct */ 8089 #define LICENSED_APP_ID_TCP_DIRECT 0x100 8090 /* enum: Low Latency */ 8091 #define LICENSED_APP_ID_LOW_LATENCY 0x200 8092 /* enum: SolarCapture Tap */ 8093 #define LICENSED_APP_ID_SOLARCAPTURE_TAP 0x400 8094 /* enum: Capture SolarSystem 40G */ 8095 #define LICENSED_APP_ID_CAPTURE_SOLARSYSTEM_40G 0x800 8096 /* enum: Capture SolarSystem 1G */ 8097 #define LICENSED_APP_ID_CAPTURE_SOLARSYSTEM_1G 0x1000 8098 #define LICENSED_APP_ID_ID_LBN 0 8099 #define LICENSED_APP_ID_ID_WIDTH 32 8100 8101 /* LICENSED_FEATURES structuredef */ 8102 #define LICENSED_FEATURES_LEN 8 8103 /* Bitmask of licensed firmware features */ 8104 #define LICENSED_FEATURES_MASK_OFST 0 8105 #define LICENSED_FEATURES_MASK_LEN 8 8106 #define LICENSED_FEATURES_MASK_LO_OFST 0 8107 #define LICENSED_FEATURES_MASK_HI_OFST 4 8108 #define LICENSED_FEATURES_RX_CUT_THROUGH_LBN 0 8109 #define LICENSED_FEATURES_RX_CUT_THROUGH_WIDTH 1 8110 #define LICENSED_FEATURES_PIO_LBN 1 8111 #define LICENSED_FEATURES_PIO_WIDTH 1 8112 #define LICENSED_FEATURES_EVQ_TIMER_LBN 2 8113 #define LICENSED_FEATURES_EVQ_TIMER_WIDTH 1 8114 #define LICENSED_FEATURES_CLOCK_LBN 3 8115 #define LICENSED_FEATURES_CLOCK_WIDTH 1 8116 #define LICENSED_FEATURES_RX_TIMESTAMPS_LBN 4 8117 #define LICENSED_FEATURES_RX_TIMESTAMPS_WIDTH 1 8118 #define LICENSED_FEATURES_TX_TIMESTAMPS_LBN 5 8119 #define LICENSED_FEATURES_TX_TIMESTAMPS_WIDTH 1 8120 #define LICENSED_FEATURES_RX_SNIFF_LBN 6 8121 #define LICENSED_FEATURES_RX_SNIFF_WIDTH 1 8122 #define LICENSED_FEATURES_TX_SNIFF_LBN 7 8123 #define LICENSED_FEATURES_TX_SNIFF_WIDTH 1 8124 #define LICENSED_FEATURES_PROXY_FILTER_OPS_LBN 8 8125 #define LICENSED_FEATURES_PROXY_FILTER_OPS_WIDTH 1 8126 #define LICENSED_FEATURES_EVENT_CUT_THROUGH_LBN 9 8127 #define LICENSED_FEATURES_EVENT_CUT_THROUGH_WIDTH 1 8128 #define LICENSED_FEATURES_MASK_LBN 0 8129 #define LICENSED_FEATURES_MASK_WIDTH 64 8130 8131 /* LICENSED_V3_APPS structuredef */ 8132 #define LICENSED_V3_APPS_LEN 8 8133 /* Bitmask of licensed applications */ 8134 #define LICENSED_V3_APPS_MASK_OFST 0 8135 #define LICENSED_V3_APPS_MASK_LEN 8 8136 #define LICENSED_V3_APPS_MASK_LO_OFST 0 8137 #define LICENSED_V3_APPS_MASK_HI_OFST 4 8138 #define LICENSED_V3_APPS_ONLOAD_LBN 0 8139 #define LICENSED_V3_APPS_ONLOAD_WIDTH 1 8140 #define LICENSED_V3_APPS_PTP_LBN 1 8141 #define LICENSED_V3_APPS_PTP_WIDTH 1 8142 #define LICENSED_V3_APPS_SOLARCAPTURE_PRO_LBN 2 8143 #define LICENSED_V3_APPS_SOLARCAPTURE_PRO_WIDTH 1 8144 #define LICENSED_V3_APPS_SOLARSECURE_LBN 3 8145 #define LICENSED_V3_APPS_SOLARSECURE_WIDTH 1 8146 #define LICENSED_V3_APPS_PERF_MONITOR_LBN 4 8147 #define LICENSED_V3_APPS_PERF_MONITOR_WIDTH 1 8148 #define LICENSED_V3_APPS_SOLARCAPTURE_LIVE_LBN 5 8149 #define LICENSED_V3_APPS_SOLARCAPTURE_LIVE_WIDTH 1 8150 #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_LBN 6 8151 #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_WIDTH 1 8152 #define LICENSED_V3_APPS_NETWORK_ACCESS_CONTROL_LBN 7 8153 #define LICENSED_V3_APPS_NETWORK_ACCESS_CONTROL_WIDTH 1 8154 #define LICENSED_V3_APPS_TCP_DIRECT_LBN 8 8155 #define LICENSED_V3_APPS_TCP_DIRECT_WIDTH 1 8156 #define LICENSED_V3_APPS_LOW_LATENCY_LBN 9 8157 #define LICENSED_V3_APPS_LOW_LATENCY_WIDTH 1 8158 #define LICENSED_V3_APPS_SOLARCAPTURE_TAP_LBN 10 8159 #define LICENSED_V3_APPS_SOLARCAPTURE_TAP_WIDTH 1 8160 #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_40G_LBN 11 8161 #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_40G_WIDTH 1 8162 #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_1G_LBN 12 8163 #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_1G_WIDTH 1 8164 #define LICENSED_V3_APPS_MASK_LBN 0 8165 #define LICENSED_V3_APPS_MASK_WIDTH 64 8166 8167 /* LICENSED_V3_FEATURES structuredef */ 8168 #define LICENSED_V3_FEATURES_LEN 8 8169 /* Bitmask of licensed firmware features */ 8170 #define LICENSED_V3_FEATURES_MASK_OFST 0 8171 #define LICENSED_V3_FEATURES_MASK_LEN 8 8172 #define LICENSED_V3_FEATURES_MASK_LO_OFST 0 8173 #define LICENSED_V3_FEATURES_MASK_HI_OFST 4 8174 #define LICENSED_V3_FEATURES_RX_CUT_THROUGH_LBN 0 8175 #define LICENSED_V3_FEATURES_RX_CUT_THROUGH_WIDTH 1 8176 #define LICENSED_V3_FEATURES_PIO_LBN 1 8177 #define LICENSED_V3_FEATURES_PIO_WIDTH 1 8178 #define LICENSED_V3_FEATURES_EVQ_TIMER_LBN 2 8179 #define LICENSED_V3_FEATURES_EVQ_TIMER_WIDTH 1 8180 #define LICENSED_V3_FEATURES_CLOCK_LBN 3 8181 #define LICENSED_V3_FEATURES_CLOCK_WIDTH 1 8182 #define LICENSED_V3_FEATURES_RX_TIMESTAMPS_LBN 4 8183 #define LICENSED_V3_FEATURES_RX_TIMESTAMPS_WIDTH 1 8184 #define LICENSED_V3_FEATURES_TX_TIMESTAMPS_LBN 5 8185 #define LICENSED_V3_FEATURES_TX_TIMESTAMPS_WIDTH 1 8186 #define LICENSED_V3_FEATURES_RX_SNIFF_LBN 6 8187 #define LICENSED_V3_FEATURES_RX_SNIFF_WIDTH 1 8188 #define LICENSED_V3_FEATURES_TX_SNIFF_LBN 7 8189 #define LICENSED_V3_FEATURES_TX_SNIFF_WIDTH 1 8190 #define LICENSED_V3_FEATURES_PROXY_FILTER_OPS_LBN 8 8191 #define LICENSED_V3_FEATURES_PROXY_FILTER_OPS_WIDTH 1 8192 #define LICENSED_V3_FEATURES_EVENT_CUT_THROUGH_LBN 9 8193 #define LICENSED_V3_FEATURES_EVENT_CUT_THROUGH_WIDTH 1 8194 #define LICENSED_V3_FEATURES_MASK_LBN 0 8195 #define LICENSED_V3_FEATURES_MASK_WIDTH 64 8196 8197 /* TX_TIMESTAMP_EVENT structuredef */ 8198 #define TX_TIMESTAMP_EVENT_LEN 6 8199 /* lower 16 bits of timestamp data */ 8200 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_OFST 0 8201 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_LEN 2 8202 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_LBN 0 8203 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_WIDTH 16 8204 /* Type of TX event, ordinary TX completion, low or high part of TX timestamp 8205 */ 8206 #define TX_TIMESTAMP_EVENT_TX_EV_TYPE_OFST 3 8207 #define TX_TIMESTAMP_EVENT_TX_EV_TYPE_LEN 1 8208 /* enum: This is a TX completion event, not a timestamp */ 8209 #define TX_TIMESTAMP_EVENT_TX_EV_COMPLETION 0x0 8210 /* enum: This is the low part of a TX timestamp event */ 8211 #define TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_LO 0x51 8212 /* enum: This is the high part of a TX timestamp event */ 8213 #define TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_HI 0x52 8214 #define TX_TIMESTAMP_EVENT_TX_EV_TYPE_LBN 24 8215 #define TX_TIMESTAMP_EVENT_TX_EV_TYPE_WIDTH 8 8216 /* upper 16 bits of timestamp data */ 8217 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_OFST 4 8218 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_LEN 2 8219 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_LBN 32 8220 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_WIDTH 16 8221 8222 /* RSS_MODE structuredef */ 8223 #define RSS_MODE_LEN 1 8224 /* The RSS mode for a particular packet type is a value from 0 - 15 which can 8225 * be considered as 4 bits selecting which fields are included in the hash. (A 8226 * value 0 effectively disables RSS spreading for the packet type.) The YAML 8227 * generation tools require this structure to be a whole number of bytes wide, 8228 * but only 4 bits are relevant. 8229 */ 8230 #define RSS_MODE_HASH_SELECTOR_OFST 0 8231 #define RSS_MODE_HASH_SELECTOR_LEN 1 8232 #define RSS_MODE_HASH_SRC_ADDR_LBN 0 8233 #define RSS_MODE_HASH_SRC_ADDR_WIDTH 1 8234 #define RSS_MODE_HASH_DST_ADDR_LBN 1 8235 #define RSS_MODE_HASH_DST_ADDR_WIDTH 1 8236 #define RSS_MODE_HASH_SRC_PORT_LBN 2 8237 #define RSS_MODE_HASH_SRC_PORT_WIDTH 1 8238 #define RSS_MODE_HASH_DST_PORT_LBN 3 8239 #define RSS_MODE_HASH_DST_PORT_WIDTH 1 8240 #define RSS_MODE_HASH_SELECTOR_LBN 0 8241 #define RSS_MODE_HASH_SELECTOR_WIDTH 8 8242 8243 /* CTPIO_STATS_MAP structuredef */ 8244 #define CTPIO_STATS_MAP_LEN 4 8245 /* The (function relative) VI number */ 8246 #define CTPIO_STATS_MAP_VI_OFST 0 8247 #define CTPIO_STATS_MAP_VI_LEN 2 8248 #define CTPIO_STATS_MAP_VI_LBN 0 8249 #define CTPIO_STATS_MAP_VI_WIDTH 16 8250 /* The target bucket for the VI */ 8251 #define CTPIO_STATS_MAP_BUCKET_OFST 2 8252 #define CTPIO_STATS_MAP_BUCKET_LEN 2 8253 #define CTPIO_STATS_MAP_BUCKET_LBN 16 8254 #define CTPIO_STATS_MAP_BUCKET_WIDTH 16 8255 8256 8257 /***********************************/ 8258 /* MC_CMD_READ_REGS 8259 * Get a dump of the MCPU registers 8260 */ 8261 #define MC_CMD_READ_REGS 0x50 8262 #undef MC_CMD_0x50_PRIVILEGE_CTG 8263 8264 #define MC_CMD_0x50_PRIVILEGE_CTG SRIOV_CTG_ADMIN 8265 8266 /* MC_CMD_READ_REGS_IN msgrequest */ 8267 #define MC_CMD_READ_REGS_IN_LEN 0 8268 8269 /* MC_CMD_READ_REGS_OUT msgresponse */ 8270 #define MC_CMD_READ_REGS_OUT_LEN 308 8271 /* Whether the corresponding register entry contains a valid value */ 8272 #define MC_CMD_READ_REGS_OUT_MASK_OFST 0 8273 #define MC_CMD_READ_REGS_OUT_MASK_LEN 16 8274 /* Same order as MIPS GDB (r0-r31, sr, lo, hi, bad, cause, 32 x float, fsr, 8275 * fir, fp) 8276 */ 8277 #define MC_CMD_READ_REGS_OUT_REGS_OFST 16 8278 #define MC_CMD_READ_REGS_OUT_REGS_LEN 4 8279 #define MC_CMD_READ_REGS_OUT_REGS_NUM 73 8280 8281 8282 /***********************************/ 8283 /* MC_CMD_INIT_EVQ 8284 * Set up an event queue according to the supplied parameters. The IN arguments 8285 * end with an address for each 4k of host memory required to back the EVQ. 8286 */ 8287 #define MC_CMD_INIT_EVQ 0x80 8288 #undef MC_CMD_0x80_PRIVILEGE_CTG 8289 8290 #define MC_CMD_0x80_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8291 8292 /* MC_CMD_INIT_EVQ_IN msgrequest */ 8293 #define MC_CMD_INIT_EVQ_IN_LENMIN 44 8294 #define MC_CMD_INIT_EVQ_IN_LENMAX 548 8295 #define MC_CMD_INIT_EVQ_IN_LEN(num) (36+8*(num)) 8296 /* Size, in entries */ 8297 #define MC_CMD_INIT_EVQ_IN_SIZE_OFST 0 8298 /* Desired instance. Must be set to a specific instance, which is a function 8299 * local queue index. 8300 */ 8301 #define MC_CMD_INIT_EVQ_IN_INSTANCE_OFST 4 8302 /* The initial timer value. The load value is ignored if the timer mode is DIS. 8303 */ 8304 #define MC_CMD_INIT_EVQ_IN_TMR_LOAD_OFST 8 8305 /* The reload value is ignored in one-shot modes */ 8306 #define MC_CMD_INIT_EVQ_IN_TMR_RELOAD_OFST 12 8307 /* tbd */ 8308 #define MC_CMD_INIT_EVQ_IN_FLAGS_OFST 16 8309 #define MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_LBN 0 8310 #define MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_WIDTH 1 8311 #define MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_LBN 1 8312 #define MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_WIDTH 1 8313 #define MC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_LBN 2 8314 #define MC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_WIDTH 1 8315 #define MC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_LBN 3 8316 #define MC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_WIDTH 1 8317 #define MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_LBN 4 8318 #define MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_WIDTH 1 8319 #define MC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_LBN 5 8320 #define MC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_WIDTH 1 8321 #define MC_CMD_INIT_EVQ_IN_FLAG_USE_TIMER_LBN 6 8322 #define MC_CMD_INIT_EVQ_IN_FLAG_USE_TIMER_WIDTH 1 8323 #define MC_CMD_INIT_EVQ_IN_TMR_MODE_OFST 20 8324 /* enum: Disabled */ 8325 #define MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS 0x0 8326 /* enum: Immediate */ 8327 #define MC_CMD_INIT_EVQ_IN_TMR_IMMED_START 0x1 8328 /* enum: Triggered */ 8329 #define MC_CMD_INIT_EVQ_IN_TMR_TRIG_START 0x2 8330 /* enum: Hold-off */ 8331 #define MC_CMD_INIT_EVQ_IN_TMR_INT_HLDOFF 0x3 8332 /* Target EVQ for wakeups if in wakeup mode. */ 8333 #define MC_CMD_INIT_EVQ_IN_TARGET_EVQ_OFST 24 8334 /* Target interrupt if in interrupting mode (note union with target EVQ). Use 8335 * MC_CMD_RESOURCE_INSTANCE_ANY unless a specific one required for test 8336 * purposes. 8337 */ 8338 #define MC_CMD_INIT_EVQ_IN_IRQ_NUM_OFST 24 8339 /* Event Counter Mode. */ 8340 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_OFST 28 8341 /* enum: Disabled */ 8342 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS 0x0 8343 /* enum: Disabled */ 8344 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_RX 0x1 8345 /* enum: Disabled */ 8346 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_TX 0x2 8347 /* enum: Disabled */ 8348 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_RXTX 0x3 8349 /* Event queue packet count threshold. */ 8350 #define MC_CMD_INIT_EVQ_IN_COUNT_THRSHLD_OFST 32 8351 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 8352 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_OFST 36 8353 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LEN 8 8354 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LO_OFST 36 8355 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_HI_OFST 40 8356 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MINNUM 1 8357 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MAXNUM 64 8358 8359 /* MC_CMD_INIT_EVQ_OUT msgresponse */ 8360 #define MC_CMD_INIT_EVQ_OUT_LEN 4 8361 /* Only valid if INTRFLAG was true */ 8362 #define MC_CMD_INIT_EVQ_OUT_IRQ_OFST 0 8363 8364 /* MC_CMD_INIT_EVQ_V2_IN msgrequest */ 8365 #define MC_CMD_INIT_EVQ_V2_IN_LENMIN 44 8366 #define MC_CMD_INIT_EVQ_V2_IN_LENMAX 548 8367 #define MC_CMD_INIT_EVQ_V2_IN_LEN(num) (36+8*(num)) 8368 /* Size, in entries */ 8369 #define MC_CMD_INIT_EVQ_V2_IN_SIZE_OFST 0 8370 /* Desired instance. Must be set to a specific instance, which is a function 8371 * local queue index. 8372 */ 8373 #define MC_CMD_INIT_EVQ_V2_IN_INSTANCE_OFST 4 8374 /* The initial timer value. The load value is ignored if the timer mode is DIS. 8375 */ 8376 #define MC_CMD_INIT_EVQ_V2_IN_TMR_LOAD_OFST 8 8377 /* The reload value is ignored in one-shot modes */ 8378 #define MC_CMD_INIT_EVQ_V2_IN_TMR_RELOAD_OFST 12 8379 /* tbd */ 8380 #define MC_CMD_INIT_EVQ_V2_IN_FLAGS_OFST 16 8381 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_INTERRUPTING_LBN 0 8382 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_INTERRUPTING_WIDTH 1 8383 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_RPTR_DOS_LBN 1 8384 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_RPTR_DOS_WIDTH 1 8385 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_INT_ARMD_LBN 2 8386 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_INT_ARMD_WIDTH 1 8387 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_CUT_THRU_LBN 3 8388 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_CUT_THRU_WIDTH 1 8389 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_RX_MERGE_LBN 4 8390 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_RX_MERGE_WIDTH 1 8391 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TX_MERGE_LBN 5 8392 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TX_MERGE_WIDTH 1 8393 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_USE_TIMER_LBN 6 8394 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_USE_TIMER_WIDTH 1 8395 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_LBN 7 8396 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_WIDTH 4 8397 /* enum: All initialisation flags specified by host. */ 8398 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_MANUAL 0x0 8399 /* enum: MEDFORD only. Certain initialisation flags specified by host may be 8400 * over-ridden by firmware based on licenses and firmware variant in order to 8401 * provide the lowest latency achievable. See 8402 * MC_CMD_INIT_EVQ_V2/MC_CMD_INIT_EVQ_V2_OUT/FLAGS for list of affected flags. 8403 */ 8404 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_LOW_LATENCY 0x1 8405 /* enum: MEDFORD only. Certain initialisation flags specified by host may be 8406 * over-ridden by firmware based on licenses and firmware variant in order to 8407 * provide the best throughput achievable. See 8408 * MC_CMD_INIT_EVQ_V2/MC_CMD_INIT_EVQ_V2_OUT/FLAGS for list of affected flags. 8409 */ 8410 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_THROUGHPUT 0x2 8411 /* enum: MEDFORD only. Certain initialisation flags may be over-ridden by 8412 * firmware based on licenses and firmware variant. See 8413 * MC_CMD_INIT_EVQ_V2/MC_CMD_INIT_EVQ_V2_OUT/FLAGS for list of affected flags. 8414 */ 8415 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_AUTO 0x3 8416 #define MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_OFST 20 8417 /* enum: Disabled */ 8418 #define MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_DIS 0x0 8419 /* enum: Immediate */ 8420 #define MC_CMD_INIT_EVQ_V2_IN_TMR_IMMED_START 0x1 8421 /* enum: Triggered */ 8422 #define MC_CMD_INIT_EVQ_V2_IN_TMR_TRIG_START 0x2 8423 /* enum: Hold-off */ 8424 #define MC_CMD_INIT_EVQ_V2_IN_TMR_INT_HLDOFF 0x3 8425 /* Target EVQ for wakeups if in wakeup mode. */ 8426 #define MC_CMD_INIT_EVQ_V2_IN_TARGET_EVQ_OFST 24 8427 /* Target interrupt if in interrupting mode (note union with target EVQ). Use 8428 * MC_CMD_RESOURCE_INSTANCE_ANY unless a specific one required for test 8429 * purposes. 8430 */ 8431 #define MC_CMD_INIT_EVQ_V2_IN_IRQ_NUM_OFST 24 8432 /* Event Counter Mode. */ 8433 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_OFST 28 8434 /* enum: Disabled */ 8435 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_DIS 0x0 8436 /* enum: Disabled */ 8437 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_RX 0x1 8438 /* enum: Disabled */ 8439 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_TX 0x2 8440 /* enum: Disabled */ 8441 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_RXTX 0x3 8442 /* Event queue packet count threshold. */ 8443 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_THRSHLD_OFST 32 8444 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 8445 #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_OFST 36 8446 #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_LEN 8 8447 #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_LO_OFST 36 8448 #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_HI_OFST 40 8449 #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_MINNUM 1 8450 #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_MAXNUM 64 8451 8452 /* MC_CMD_INIT_EVQ_V2_OUT msgresponse */ 8453 #define MC_CMD_INIT_EVQ_V2_OUT_LEN 8 8454 /* Only valid if INTRFLAG was true */ 8455 #define MC_CMD_INIT_EVQ_V2_OUT_IRQ_OFST 0 8456 /* Actual configuration applied on the card */ 8457 #define MC_CMD_INIT_EVQ_V2_OUT_FLAGS_OFST 4 8458 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_CUT_THRU_LBN 0 8459 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_CUT_THRU_WIDTH 1 8460 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RX_MERGE_LBN 1 8461 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RX_MERGE_WIDTH 1 8462 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_TX_MERGE_LBN 2 8463 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_TX_MERGE_WIDTH 1 8464 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RXQ_FORCE_EV_MERGING_LBN 3 8465 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RXQ_FORCE_EV_MERGING_WIDTH 1 8466 8467 /* QUEUE_CRC_MODE structuredef */ 8468 #define QUEUE_CRC_MODE_LEN 1 8469 #define QUEUE_CRC_MODE_MODE_LBN 0 8470 #define QUEUE_CRC_MODE_MODE_WIDTH 4 8471 /* enum: No CRC. */ 8472 #define QUEUE_CRC_MODE_NONE 0x0 8473 /* enum: CRC Fiber channel over ethernet. */ 8474 #define QUEUE_CRC_MODE_FCOE 0x1 8475 /* enum: CRC (digest) iSCSI header only. */ 8476 #define QUEUE_CRC_MODE_ISCSI_HDR 0x2 8477 /* enum: CRC (digest) iSCSI header and payload. */ 8478 #define QUEUE_CRC_MODE_ISCSI 0x3 8479 /* enum: CRC Fiber channel over IP over ethernet. */ 8480 #define QUEUE_CRC_MODE_FCOIPOE 0x4 8481 /* enum: CRC MPA. */ 8482 #define QUEUE_CRC_MODE_MPA 0x5 8483 #define QUEUE_CRC_MODE_SPARE_LBN 4 8484 #define QUEUE_CRC_MODE_SPARE_WIDTH 4 8485 8486 8487 /***********************************/ 8488 /* MC_CMD_INIT_RXQ 8489 * set up a receive queue according to the supplied parameters. The IN 8490 * arguments end with an address for each 4k of host memory required to back 8491 * the RXQ. 8492 */ 8493 #define MC_CMD_INIT_RXQ 0x81 8494 #undef MC_CMD_0x81_PRIVILEGE_CTG 8495 8496 #define MC_CMD_0x81_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8497 8498 /* MC_CMD_INIT_RXQ_IN msgrequest: Legacy RXQ_INIT request. Use extended version 8499 * in new code. 8500 */ 8501 #define MC_CMD_INIT_RXQ_IN_LENMIN 36 8502 #define MC_CMD_INIT_RXQ_IN_LENMAX 252 8503 #define MC_CMD_INIT_RXQ_IN_LEN(num) (28+8*(num)) 8504 /* Size, in entries */ 8505 #define MC_CMD_INIT_RXQ_IN_SIZE_OFST 0 8506 /* The EVQ to send events to. This is an index originally specified to INIT_EVQ 8507 */ 8508 #define MC_CMD_INIT_RXQ_IN_TARGET_EVQ_OFST 4 8509 /* The value to put in the event data. Check hardware spec. for valid range. */ 8510 #define MC_CMD_INIT_RXQ_IN_LABEL_OFST 8 8511 /* Desired instance. Must be set to a specific instance, which is a function 8512 * local queue index. 8513 */ 8514 #define MC_CMD_INIT_RXQ_IN_INSTANCE_OFST 12 8515 /* There will be more flags here. */ 8516 #define MC_CMD_INIT_RXQ_IN_FLAGS_OFST 16 8517 #define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_LBN 0 8518 #define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_WIDTH 1 8519 #define MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_LBN 1 8520 #define MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_WIDTH 1 8521 #define MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_LBN 2 8522 #define MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_WIDTH 1 8523 #define MC_CMD_INIT_RXQ_IN_CRC_MODE_LBN 3 8524 #define MC_CMD_INIT_RXQ_IN_CRC_MODE_WIDTH 4 8525 #define MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_LBN 7 8526 #define MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_WIDTH 1 8527 #define MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_LBN 8 8528 #define MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_WIDTH 1 8529 #define MC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_LBN 9 8530 #define MC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_WIDTH 1 8531 #define MC_CMD_INIT_RXQ_IN_UNUSED_LBN 10 8532 #define MC_CMD_INIT_RXQ_IN_UNUSED_WIDTH 1 8533 /* Owner ID to use if in buffer mode (zero if physical) */ 8534 #define MC_CMD_INIT_RXQ_IN_OWNER_ID_OFST 20 8535 /* The port ID associated with the v-adaptor which should contain this DMAQ. */ 8536 #define MC_CMD_INIT_RXQ_IN_PORT_ID_OFST 24 8537 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 8538 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_OFST 28 8539 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LEN 8 8540 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LO_OFST 28 8541 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_HI_OFST 32 8542 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MINNUM 1 8543 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MAXNUM 28 8544 8545 /* MC_CMD_INIT_RXQ_EXT_IN msgrequest: Extended RXQ_INIT with additional mode 8546 * flags 8547 */ 8548 #define MC_CMD_INIT_RXQ_EXT_IN_LEN 544 8549 /* Size, in entries */ 8550 #define MC_CMD_INIT_RXQ_EXT_IN_SIZE_OFST 0 8551 /* The EVQ to send events to. This is an index originally specified to INIT_EVQ 8552 */ 8553 #define MC_CMD_INIT_RXQ_EXT_IN_TARGET_EVQ_OFST 4 8554 /* The value to put in the event data. Check hardware spec. for valid range. */ 8555 #define MC_CMD_INIT_RXQ_EXT_IN_LABEL_OFST 8 8556 /* Desired instance. Must be set to a specific instance, which is a function 8557 * local queue index. 8558 */ 8559 #define MC_CMD_INIT_RXQ_EXT_IN_INSTANCE_OFST 12 8560 /* There will be more flags here. */ 8561 #define MC_CMD_INIT_RXQ_EXT_IN_FLAGS_OFST 16 8562 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_LBN 0 8563 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_WIDTH 1 8564 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT_LBN 1 8565 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT_WIDTH 1 8566 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_TIMESTAMP_LBN 2 8567 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_TIMESTAMP_WIDTH 1 8568 #define MC_CMD_INIT_RXQ_EXT_IN_CRC_MODE_LBN 3 8569 #define MC_CMD_INIT_RXQ_EXT_IN_CRC_MODE_WIDTH 4 8570 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_CHAIN_LBN 7 8571 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_CHAIN_WIDTH 1 8572 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_PREFIX_LBN 8 8573 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_PREFIX_WIDTH 1 8574 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER_LBN 9 8575 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER_WIDTH 1 8576 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_LBN 10 8577 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_WIDTH 4 8578 /* enum: One packet per descriptor (for normal networking) */ 8579 #define MC_CMD_INIT_RXQ_EXT_IN_SINGLE_PACKET 0x0 8580 /* enum: Pack multiple packets into large descriptors (for SolarCapture) */ 8581 #define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM 0x1 8582 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_LBN 14 8583 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_WIDTH 1 8584 #define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE_LBN 15 8585 #define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE_WIDTH 3 8586 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_1M 0x0 /* enum */ 8587 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_512K 0x1 /* enum */ 8588 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_256K 0x2 /* enum */ 8589 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_128K 0x3 /* enum */ 8590 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_64K 0x4 /* enum */ 8591 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES_LBN 18 8592 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 1 8593 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_FORCE_EV_MERGING_LBN 19 8594 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_FORCE_EV_MERGING_WIDTH 1 8595 /* Owner ID to use if in buffer mode (zero if physical) */ 8596 #define MC_CMD_INIT_RXQ_EXT_IN_OWNER_ID_OFST 20 8597 /* The port ID associated with the v-adaptor which should contain this DMAQ. */ 8598 #define MC_CMD_INIT_RXQ_EXT_IN_PORT_ID_OFST 24 8599 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 8600 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_OFST 28 8601 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LEN 8 8602 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LO_OFST 28 8603 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_HI_OFST 32 8604 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_NUM 64 8605 /* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */ 8606 #define MC_CMD_INIT_RXQ_EXT_IN_SNAPSHOT_LENGTH_OFST 540 8607 8608 /* MC_CMD_INIT_RXQ_OUT msgresponse */ 8609 #define MC_CMD_INIT_RXQ_OUT_LEN 0 8610 8611 /* MC_CMD_INIT_RXQ_EXT_OUT msgresponse */ 8612 #define MC_CMD_INIT_RXQ_EXT_OUT_LEN 0 8613 8614 8615 /***********************************/ 8616 /* MC_CMD_INIT_TXQ 8617 */ 8618 #define MC_CMD_INIT_TXQ 0x82 8619 #undef MC_CMD_0x82_PRIVILEGE_CTG 8620 8621 #define MC_CMD_0x82_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8622 8623 /* MC_CMD_INIT_TXQ_IN msgrequest: Legacy INIT_TXQ request. Use extended version 8624 * in new code. 8625 */ 8626 #define MC_CMD_INIT_TXQ_IN_LENMIN 36 8627 #define MC_CMD_INIT_TXQ_IN_LENMAX 252 8628 #define MC_CMD_INIT_TXQ_IN_LEN(num) (28+8*(num)) 8629 /* Size, in entries */ 8630 #define MC_CMD_INIT_TXQ_IN_SIZE_OFST 0 8631 /* The EVQ to send events to. This is an index originally specified to 8632 * INIT_EVQ. 8633 */ 8634 #define MC_CMD_INIT_TXQ_IN_TARGET_EVQ_OFST 4 8635 /* The value to put in the event data. Check hardware spec. for valid range. */ 8636 #define MC_CMD_INIT_TXQ_IN_LABEL_OFST 8 8637 /* Desired instance. Must be set to a specific instance, which is a function 8638 * local queue index. 8639 */ 8640 #define MC_CMD_INIT_TXQ_IN_INSTANCE_OFST 12 8641 /* There will be more flags here. */ 8642 #define MC_CMD_INIT_TXQ_IN_FLAGS_OFST 16 8643 #define MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_LBN 0 8644 #define MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_WIDTH 1 8645 #define MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_LBN 1 8646 #define MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_WIDTH 1 8647 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_LBN 2 8648 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_WIDTH 1 8649 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_LBN 3 8650 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_WIDTH 1 8651 #define MC_CMD_INIT_TXQ_IN_CRC_MODE_LBN 4 8652 #define MC_CMD_INIT_TXQ_IN_CRC_MODE_WIDTH 4 8653 #define MC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_LBN 8 8654 #define MC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_WIDTH 1 8655 #define MC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_LBN 9 8656 #define MC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_WIDTH 1 8657 #define MC_CMD_INIT_TXQ_IN_FLAG_INNER_IP_CSUM_EN_LBN 10 8658 #define MC_CMD_INIT_TXQ_IN_FLAG_INNER_IP_CSUM_EN_WIDTH 1 8659 #define MC_CMD_INIT_TXQ_IN_FLAG_INNER_TCP_CSUM_EN_LBN 11 8660 #define MC_CMD_INIT_TXQ_IN_FLAG_INNER_TCP_CSUM_EN_WIDTH 1 8661 /* Owner ID to use if in buffer mode (zero if physical) */ 8662 #define MC_CMD_INIT_TXQ_IN_OWNER_ID_OFST 20 8663 /* The port ID associated with the v-adaptor which should contain this DMAQ. */ 8664 #define MC_CMD_INIT_TXQ_IN_PORT_ID_OFST 24 8665 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 8666 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_OFST 28 8667 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LEN 8 8668 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LO_OFST 28 8669 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_HI_OFST 32 8670 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MINNUM 1 8671 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MAXNUM 28 8672 8673 /* MC_CMD_INIT_TXQ_EXT_IN msgrequest: Extended INIT_TXQ with additional mode 8674 * flags 8675 */ 8676 #define MC_CMD_INIT_TXQ_EXT_IN_LEN 544 8677 /* Size, in entries */ 8678 #define MC_CMD_INIT_TXQ_EXT_IN_SIZE_OFST 0 8679 /* The EVQ to send events to. This is an index originally specified to 8680 * INIT_EVQ. 8681 */ 8682 #define MC_CMD_INIT_TXQ_EXT_IN_TARGET_EVQ_OFST 4 8683 /* The value to put in the event data. Check hardware spec. for valid range. */ 8684 #define MC_CMD_INIT_TXQ_EXT_IN_LABEL_OFST 8 8685 /* Desired instance. Must be set to a specific instance, which is a function 8686 * local queue index. 8687 */ 8688 #define MC_CMD_INIT_TXQ_EXT_IN_INSTANCE_OFST 12 8689 /* There will be more flags here. */ 8690 #define MC_CMD_INIT_TXQ_EXT_IN_FLAGS_OFST 16 8691 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_BUFF_MODE_LBN 0 8692 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_BUFF_MODE_WIDTH 1 8693 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_IP_CSUM_DIS_LBN 1 8694 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_IP_CSUM_DIS_WIDTH 1 8695 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_CSUM_DIS_LBN 2 8696 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_CSUM_DIS_WIDTH 1 8697 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_UDP_ONLY_LBN 3 8698 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_UDP_ONLY_WIDTH 1 8699 #define MC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_LBN 4 8700 #define MC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_WIDTH 4 8701 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TIMESTAMP_LBN 8 8702 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TIMESTAMP_WIDTH 1 8703 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_PACER_BYPASS_LBN 9 8704 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_PACER_BYPASS_WIDTH 1 8705 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN_LBN 10 8706 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN_WIDTH 1 8707 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN_LBN 11 8708 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN_WIDTH 1 8709 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TSOV2_EN_LBN 12 8710 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TSOV2_EN_WIDTH 1 8711 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_LBN 13 8712 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_WIDTH 1 8713 /* Owner ID to use if in buffer mode (zero if physical) */ 8714 #define MC_CMD_INIT_TXQ_EXT_IN_OWNER_ID_OFST 20 8715 /* The port ID associated with the v-adaptor which should contain this DMAQ. */ 8716 #define MC_CMD_INIT_TXQ_EXT_IN_PORT_ID_OFST 24 8717 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 8718 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_OFST 28 8719 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LEN 8 8720 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LO_OFST 28 8721 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_HI_OFST 32 8722 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MINNUM 1 8723 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MAXNUM 64 8724 /* Flags related to Qbb flow control mode. */ 8725 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_FLAGS_OFST 540 8726 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_ENABLE_LBN 0 8727 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_ENABLE_WIDTH 1 8728 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_PRIORITY_LBN 1 8729 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_PRIORITY_WIDTH 3 8730 8731 /* MC_CMD_INIT_TXQ_OUT msgresponse */ 8732 #define MC_CMD_INIT_TXQ_OUT_LEN 0 8733 8734 8735 /***********************************/ 8736 /* MC_CMD_FINI_EVQ 8737 * Teardown an EVQ. 8738 * 8739 * All DMAQs or EVQs that point to the EVQ to tear down must be torn down first 8740 * or the operation will fail with EBUSY 8741 */ 8742 #define MC_CMD_FINI_EVQ 0x83 8743 #undef MC_CMD_0x83_PRIVILEGE_CTG 8744 8745 #define MC_CMD_0x83_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8746 8747 /* MC_CMD_FINI_EVQ_IN msgrequest */ 8748 #define MC_CMD_FINI_EVQ_IN_LEN 4 8749 /* Instance of EVQ to destroy. Should be the same instance as that previously 8750 * passed to INIT_EVQ 8751 */ 8752 #define MC_CMD_FINI_EVQ_IN_INSTANCE_OFST 0 8753 8754 /* MC_CMD_FINI_EVQ_OUT msgresponse */ 8755 #define MC_CMD_FINI_EVQ_OUT_LEN 0 8756 8757 8758 /***********************************/ 8759 /* MC_CMD_FINI_RXQ 8760 * Teardown a RXQ. 8761 */ 8762 #define MC_CMD_FINI_RXQ 0x84 8763 #undef MC_CMD_0x84_PRIVILEGE_CTG 8764 8765 #define MC_CMD_0x84_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8766 8767 /* MC_CMD_FINI_RXQ_IN msgrequest */ 8768 #define MC_CMD_FINI_RXQ_IN_LEN 4 8769 /* Instance of RXQ to destroy */ 8770 #define MC_CMD_FINI_RXQ_IN_INSTANCE_OFST 0 8771 8772 /* MC_CMD_FINI_RXQ_OUT msgresponse */ 8773 #define MC_CMD_FINI_RXQ_OUT_LEN 0 8774 8775 8776 /***********************************/ 8777 /* MC_CMD_FINI_TXQ 8778 * Teardown a TXQ. 8779 */ 8780 #define MC_CMD_FINI_TXQ 0x85 8781 #undef MC_CMD_0x85_PRIVILEGE_CTG 8782 8783 #define MC_CMD_0x85_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8784 8785 /* MC_CMD_FINI_TXQ_IN msgrequest */ 8786 #define MC_CMD_FINI_TXQ_IN_LEN 4 8787 /* Instance of TXQ to destroy */ 8788 #define MC_CMD_FINI_TXQ_IN_INSTANCE_OFST 0 8789 8790 /* MC_CMD_FINI_TXQ_OUT msgresponse */ 8791 #define MC_CMD_FINI_TXQ_OUT_LEN 0 8792 8793 8794 /***********************************/ 8795 /* MC_CMD_DRIVER_EVENT 8796 * Generate an event on an EVQ belonging to the function issuing the command. 8797 */ 8798 #define MC_CMD_DRIVER_EVENT 0x86 8799 #undef MC_CMD_0x86_PRIVILEGE_CTG 8800 8801 #define MC_CMD_0x86_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8802 8803 /* MC_CMD_DRIVER_EVENT_IN msgrequest */ 8804 #define MC_CMD_DRIVER_EVENT_IN_LEN 12 8805 /* Handle of target EVQ */ 8806 #define MC_CMD_DRIVER_EVENT_IN_EVQ_OFST 0 8807 /* Bits 0 - 63 of event */ 8808 #define MC_CMD_DRIVER_EVENT_IN_DATA_OFST 4 8809 #define MC_CMD_DRIVER_EVENT_IN_DATA_LEN 8 8810 #define MC_CMD_DRIVER_EVENT_IN_DATA_LO_OFST 4 8811 #define MC_CMD_DRIVER_EVENT_IN_DATA_HI_OFST 8 8812 8813 /* MC_CMD_DRIVER_EVENT_OUT msgresponse */ 8814 #define MC_CMD_DRIVER_EVENT_OUT_LEN 0 8815 8816 8817 /***********************************/ 8818 /* MC_CMD_PROXY_CMD 8819 * Execute an arbitrary MCDI command on behalf of a different function, subject 8820 * to security restrictions. The command to be proxied follows immediately 8821 * afterward in the host buffer (or on the UART). This command supercedes 8822 * MC_CMD_SET_FUNC, which remains available for Siena but now deprecated. 8823 */ 8824 #define MC_CMD_PROXY_CMD 0x5b 8825 #undef MC_CMD_0x5b_PRIVILEGE_CTG 8826 8827 #define MC_CMD_0x5b_PRIVILEGE_CTG SRIOV_CTG_ADMIN 8828 8829 /* MC_CMD_PROXY_CMD_IN msgrequest */ 8830 #define MC_CMD_PROXY_CMD_IN_LEN 4 8831 /* The handle of the target function. */ 8832 #define MC_CMD_PROXY_CMD_IN_TARGET_OFST 0 8833 #define MC_CMD_PROXY_CMD_IN_TARGET_PF_LBN 0 8834 #define MC_CMD_PROXY_CMD_IN_TARGET_PF_WIDTH 16 8835 #define MC_CMD_PROXY_CMD_IN_TARGET_VF_LBN 16 8836 #define MC_CMD_PROXY_CMD_IN_TARGET_VF_WIDTH 16 8837 #define MC_CMD_PROXY_CMD_IN_VF_NULL 0xffff /* enum */ 8838 8839 /* MC_CMD_PROXY_CMD_OUT msgresponse */ 8840 #define MC_CMD_PROXY_CMD_OUT_LEN 0 8841 8842 /* MC_PROXY_STATUS_BUFFER structuredef: Host memory status buffer used to 8843 * manage proxied requests 8844 */ 8845 #define MC_PROXY_STATUS_BUFFER_LEN 16 8846 /* Handle allocated by the firmware for this proxy transaction */ 8847 #define MC_PROXY_STATUS_BUFFER_HANDLE_OFST 0 8848 /* enum: An invalid handle. */ 8849 #define MC_PROXY_STATUS_BUFFER_HANDLE_INVALID 0x0 8850 #define MC_PROXY_STATUS_BUFFER_HANDLE_LBN 0 8851 #define MC_PROXY_STATUS_BUFFER_HANDLE_WIDTH 32 8852 /* The requesting physical function number */ 8853 #define MC_PROXY_STATUS_BUFFER_PF_OFST 4 8854 #define MC_PROXY_STATUS_BUFFER_PF_LEN 2 8855 #define MC_PROXY_STATUS_BUFFER_PF_LBN 32 8856 #define MC_PROXY_STATUS_BUFFER_PF_WIDTH 16 8857 /* The requesting virtual function number. Set to VF_NULL if the target is a 8858 * PF. 8859 */ 8860 #define MC_PROXY_STATUS_BUFFER_VF_OFST 6 8861 #define MC_PROXY_STATUS_BUFFER_VF_LEN 2 8862 #define MC_PROXY_STATUS_BUFFER_VF_LBN 48 8863 #define MC_PROXY_STATUS_BUFFER_VF_WIDTH 16 8864 /* The target function RID. */ 8865 #define MC_PROXY_STATUS_BUFFER_RID_OFST 8 8866 #define MC_PROXY_STATUS_BUFFER_RID_LEN 2 8867 #define MC_PROXY_STATUS_BUFFER_RID_LBN 64 8868 #define MC_PROXY_STATUS_BUFFER_RID_WIDTH 16 8869 /* The status of the proxy as described in MC_CMD_PROXY_COMPLETE. */ 8870 #define MC_PROXY_STATUS_BUFFER_STATUS_OFST 10 8871 #define MC_PROXY_STATUS_BUFFER_STATUS_LEN 2 8872 #define MC_PROXY_STATUS_BUFFER_STATUS_LBN 80 8873 #define MC_PROXY_STATUS_BUFFER_STATUS_WIDTH 16 8874 /* If a request is authorized rather than carried out by the host, this is the 8875 * elevated privilege mask granted to the requesting function. 8876 */ 8877 #define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_OFST 12 8878 #define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_LBN 96 8879 #define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_WIDTH 32 8880 8881 8882 /***********************************/ 8883 /* MC_CMD_PROXY_CONFIGURE 8884 * Enable/disable authorization of MCDI requests from unprivileged functions by 8885 * a designated admin function 8886 */ 8887 #define MC_CMD_PROXY_CONFIGURE 0x58 8888 #undef MC_CMD_0x58_PRIVILEGE_CTG 8889 8890 #define MC_CMD_0x58_PRIVILEGE_CTG SRIOV_CTG_ADMIN 8891 8892 /* MC_CMD_PROXY_CONFIGURE_IN msgrequest */ 8893 #define MC_CMD_PROXY_CONFIGURE_IN_LEN 108 8894 #define MC_CMD_PROXY_CONFIGURE_IN_FLAGS_OFST 0 8895 #define MC_CMD_PROXY_CONFIGURE_IN_ENABLE_LBN 0 8896 #define MC_CMD_PROXY_CONFIGURE_IN_ENABLE_WIDTH 1 8897 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 8898 * of blocks, each of the size REQUEST_BLOCK_SIZE. 8899 */ 8900 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_OFST 4 8901 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LEN 8 8902 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LO_OFST 4 8903 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_HI_OFST 8 8904 /* Must be a power of 2 */ 8905 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BLOCK_SIZE_OFST 12 8906 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 8907 * of blocks, each of the size REPLY_BLOCK_SIZE. 8908 */ 8909 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_OFST 16 8910 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LEN 8 8911 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LO_OFST 16 8912 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_HI_OFST 20 8913 /* Must be a power of 2 */ 8914 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BLOCK_SIZE_OFST 24 8915 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 8916 * of blocks, each of the size STATUS_BLOCK_SIZE. This buffer is only needed if 8917 * host intends to complete proxied operations by using MC_CMD_PROXY_CMD. 8918 */ 8919 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_OFST 28 8920 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LEN 8 8921 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LO_OFST 28 8922 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_HI_OFST 32 8923 /* Must be a power of 2, or zero if this buffer is not provided */ 8924 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BLOCK_SIZE_OFST 36 8925 /* Applies to all three buffers */ 8926 #define MC_CMD_PROXY_CONFIGURE_IN_NUM_BLOCKS_OFST 40 8927 /* A bit mask defining which MCDI operations may be proxied */ 8928 #define MC_CMD_PROXY_CONFIGURE_IN_ALLOWED_MCDI_MASK_OFST 44 8929 #define MC_CMD_PROXY_CONFIGURE_IN_ALLOWED_MCDI_MASK_LEN 64 8930 8931 /* MC_CMD_PROXY_CONFIGURE_EXT_IN msgrequest */ 8932 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_LEN 112 8933 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_FLAGS_OFST 0 8934 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_ENABLE_LBN 0 8935 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_ENABLE_WIDTH 1 8936 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 8937 * of blocks, each of the size REQUEST_BLOCK_SIZE. 8938 */ 8939 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_OFST 4 8940 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LEN 8 8941 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LO_OFST 4 8942 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_HI_OFST 8 8943 /* Must be a power of 2 */ 8944 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BLOCK_SIZE_OFST 12 8945 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 8946 * of blocks, each of the size REPLY_BLOCK_SIZE. 8947 */ 8948 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_OFST 16 8949 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_LEN 8 8950 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_LO_OFST 16 8951 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_HI_OFST 20 8952 /* Must be a power of 2 */ 8953 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BLOCK_SIZE_OFST 24 8954 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 8955 * of blocks, each of the size STATUS_BLOCK_SIZE. This buffer is only needed if 8956 * host intends to complete proxied operations by using MC_CMD_PROXY_CMD. 8957 */ 8958 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_OFST 28 8959 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_LEN 8 8960 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_LO_OFST 28 8961 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_HI_OFST 32 8962 /* Must be a power of 2, or zero if this buffer is not provided */ 8963 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BLOCK_SIZE_OFST 36 8964 /* Applies to all three buffers */ 8965 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_NUM_BLOCKS_OFST 40 8966 /* A bit mask defining which MCDI operations may be proxied */ 8967 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_ALLOWED_MCDI_MASK_OFST 44 8968 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_ALLOWED_MCDI_MASK_LEN 64 8969 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_RESERVED_OFST 108 8970 8971 /* MC_CMD_PROXY_CONFIGURE_OUT msgresponse */ 8972 #define MC_CMD_PROXY_CONFIGURE_OUT_LEN 0 8973 8974 8975 /***********************************/ 8976 /* MC_CMD_PROXY_COMPLETE 8977 * Tells FW that a requested proxy operation has either been completed (by 8978 * using MC_CMD_PROXY_CMD) or authorized/declined. May only be sent by the 8979 * function that enabled proxying/authorization (by using 8980 * MC_CMD_PROXY_CONFIGURE). 8981 */ 8982 #define MC_CMD_PROXY_COMPLETE 0x5f 8983 #undef MC_CMD_0x5f_PRIVILEGE_CTG 8984 8985 #define MC_CMD_0x5f_PRIVILEGE_CTG SRIOV_CTG_ADMIN 8986 8987 /* MC_CMD_PROXY_COMPLETE_IN msgrequest */ 8988 #define MC_CMD_PROXY_COMPLETE_IN_LEN 12 8989 #define MC_CMD_PROXY_COMPLETE_IN_BLOCK_INDEX_OFST 0 8990 #define MC_CMD_PROXY_COMPLETE_IN_STATUS_OFST 4 8991 /* enum: The operation has been completed by using MC_CMD_PROXY_CMD, the reply 8992 * is stored in the REPLY_BUFF. 8993 */ 8994 #define MC_CMD_PROXY_COMPLETE_IN_COMPLETE 0x0 8995 /* enum: The operation has been authorized. The originating function may now 8996 * try again. 8997 */ 8998 #define MC_CMD_PROXY_COMPLETE_IN_AUTHORIZED 0x1 8999 /* enum: The operation has been declined. */ 9000 #define MC_CMD_PROXY_COMPLETE_IN_DECLINED 0x2 9001 /* enum: The authorization failed because the relevant application did not 9002 * respond in time. 9003 */ 9004 #define MC_CMD_PROXY_COMPLETE_IN_TIMEDOUT 0x3 9005 #define MC_CMD_PROXY_COMPLETE_IN_HANDLE_OFST 8 9006 9007 /* MC_CMD_PROXY_COMPLETE_OUT msgresponse */ 9008 #define MC_CMD_PROXY_COMPLETE_OUT_LEN 0 9009 9010 9011 /***********************************/ 9012 /* MC_CMD_ALLOC_BUFTBL_CHUNK 9013 * Allocate a set of buffer table entries using the specified owner ID. This 9014 * operation allocates the required buffer table entries (and fails if it 9015 * cannot do so). The buffer table entries will initially be zeroed. 9016 */ 9017 #define MC_CMD_ALLOC_BUFTBL_CHUNK 0x87 9018 #undef MC_CMD_0x87_PRIVILEGE_CTG 9019 9020 #define MC_CMD_0x87_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 9021 9022 /* MC_CMD_ALLOC_BUFTBL_CHUNK_IN msgrequest */ 9023 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_LEN 8 9024 /* Owner ID to use */ 9025 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_OWNER_OFST 0 9026 /* Size of buffer table pages to use, in bytes (note that only a few values are 9027 * legal on any specific hardware). 9028 */ 9029 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_PAGE_SIZE_OFST 4 9030 9031 /* MC_CMD_ALLOC_BUFTBL_CHUNK_OUT msgresponse */ 9032 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_LEN 12 9033 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_HANDLE_OFST 0 9034 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_NUMENTRIES_OFST 4 9035 /* Buffer table IDs for use in DMA descriptors. */ 9036 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_ID_OFST 8 9037 9038 9039 /***********************************/ 9040 /* MC_CMD_PROGRAM_BUFTBL_ENTRIES 9041 * Reprogram a set of buffer table entries in the specified chunk. 9042 */ 9043 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES 0x88 9044 #undef MC_CMD_0x88_PRIVILEGE_CTG 9045 9046 #define MC_CMD_0x88_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 9047 9048 /* MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN msgrequest */ 9049 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMIN 20 9050 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMAX 268 9051 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LEN(num) (12+8*(num)) 9052 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_HANDLE_OFST 0 9053 /* ID */ 9054 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_FIRSTID_OFST 4 9055 /* Num entries */ 9056 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_NUMENTRIES_OFST 8 9057 /* Buffer table entry address */ 9058 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_OFST 12 9059 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LEN 8 9060 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LO_OFST 12 9061 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_HI_OFST 16 9062 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MINNUM 1 9063 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MAXNUM 32 9064 9065 /* MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT msgresponse */ 9066 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT_LEN 0 9067 9068 9069 /***********************************/ 9070 /* MC_CMD_FREE_BUFTBL_CHUNK 9071 */ 9072 #define MC_CMD_FREE_BUFTBL_CHUNK 0x89 9073 #undef MC_CMD_0x89_PRIVILEGE_CTG 9074 9075 #define MC_CMD_0x89_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 9076 9077 /* MC_CMD_FREE_BUFTBL_CHUNK_IN msgrequest */ 9078 #define MC_CMD_FREE_BUFTBL_CHUNK_IN_LEN 4 9079 #define MC_CMD_FREE_BUFTBL_CHUNK_IN_HANDLE_OFST 0 9080 9081 /* MC_CMD_FREE_BUFTBL_CHUNK_OUT msgresponse */ 9082 #define MC_CMD_FREE_BUFTBL_CHUNK_OUT_LEN 0 9083 9084 /* PORT_CONFIG_ENTRY structuredef */ 9085 #define PORT_CONFIG_ENTRY_LEN 16 9086 /* External port number (label) */ 9087 #define PORT_CONFIG_ENTRY_EXT_NUMBER_OFST 0 9088 #define PORT_CONFIG_ENTRY_EXT_NUMBER_LEN 1 9089 #define PORT_CONFIG_ENTRY_EXT_NUMBER_LBN 0 9090 #define PORT_CONFIG_ENTRY_EXT_NUMBER_WIDTH 8 9091 /* Port core location */ 9092 #define PORT_CONFIG_ENTRY_CORE_OFST 1 9093 #define PORT_CONFIG_ENTRY_CORE_LEN 1 9094 #define PORT_CONFIG_ENTRY_STANDALONE 0x0 /* enum */ 9095 #define PORT_CONFIG_ENTRY_MASTER 0x1 /* enum */ 9096 #define PORT_CONFIG_ENTRY_SLAVE 0x2 /* enum */ 9097 #define PORT_CONFIG_ENTRY_CORE_LBN 8 9098 #define PORT_CONFIG_ENTRY_CORE_WIDTH 8 9099 /* Internal number (HW resource) relative to the core */ 9100 #define PORT_CONFIG_ENTRY_INT_NUMBER_OFST 2 9101 #define PORT_CONFIG_ENTRY_INT_NUMBER_LEN 1 9102 #define PORT_CONFIG_ENTRY_INT_NUMBER_LBN 16 9103 #define PORT_CONFIG_ENTRY_INT_NUMBER_WIDTH 8 9104 /* Reserved */ 9105 #define PORT_CONFIG_ENTRY_RSVD_OFST 3 9106 #define PORT_CONFIG_ENTRY_RSVD_LEN 1 9107 #define PORT_CONFIG_ENTRY_RSVD_LBN 24 9108 #define PORT_CONFIG_ENTRY_RSVD_WIDTH 8 9109 /* Bitmask of KR lanes used by the port */ 9110 #define PORT_CONFIG_ENTRY_LANES_OFST 4 9111 #define PORT_CONFIG_ENTRY_LANES_LBN 32 9112 #define PORT_CONFIG_ENTRY_LANES_WIDTH 32 9113 /* Port capabilities (MC_CMD_PHY_CAP_*) */ 9114 #define PORT_CONFIG_ENTRY_SUPPORTED_CAPS_OFST 8 9115 #define PORT_CONFIG_ENTRY_SUPPORTED_CAPS_LBN 64 9116 #define PORT_CONFIG_ENTRY_SUPPORTED_CAPS_WIDTH 32 9117 /* Reserved (align to 16 bytes) */ 9118 #define PORT_CONFIG_ENTRY_RSVD2_OFST 12 9119 #define PORT_CONFIG_ENTRY_RSVD2_LBN 96 9120 #define PORT_CONFIG_ENTRY_RSVD2_WIDTH 32 9121 9122 9123 /***********************************/ 9124 /* MC_CMD_FILTER_OP 9125 * Multiplexed MCDI call for filter operations 9126 */ 9127 #define MC_CMD_FILTER_OP 0x8a 9128 #undef MC_CMD_0x8a_PRIVILEGE_CTG 9129 9130 #define MC_CMD_0x8a_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9131 9132 /* MC_CMD_FILTER_OP_IN msgrequest */ 9133 #define MC_CMD_FILTER_OP_IN_LEN 108 9134 /* identifies the type of operation requested */ 9135 #define MC_CMD_FILTER_OP_IN_OP_OFST 0 9136 /* enum: single-recipient filter insert */ 9137 #define MC_CMD_FILTER_OP_IN_OP_INSERT 0x0 9138 /* enum: single-recipient filter remove */ 9139 #define MC_CMD_FILTER_OP_IN_OP_REMOVE 0x1 9140 /* enum: multi-recipient filter subscribe */ 9141 #define MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE 0x2 9142 /* enum: multi-recipient filter unsubscribe */ 9143 #define MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE 0x3 9144 /* enum: replace one recipient with another (warning - the filter handle may 9145 * change) 9146 */ 9147 #define MC_CMD_FILTER_OP_IN_OP_REPLACE 0x4 9148 /* filter handle (for remove / unsubscribe operations) */ 9149 #define MC_CMD_FILTER_OP_IN_HANDLE_OFST 4 9150 #define MC_CMD_FILTER_OP_IN_HANDLE_LEN 8 9151 #define MC_CMD_FILTER_OP_IN_HANDLE_LO_OFST 4 9152 #define MC_CMD_FILTER_OP_IN_HANDLE_HI_OFST 8 9153 /* The port ID associated with the v-adaptor which should contain this filter. 9154 */ 9155 #define MC_CMD_FILTER_OP_IN_PORT_ID_OFST 12 9156 /* fields to include in match criteria */ 9157 #define MC_CMD_FILTER_OP_IN_MATCH_FIELDS_OFST 16 9158 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_LBN 0 9159 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_WIDTH 1 9160 #define MC_CMD_FILTER_OP_IN_MATCH_DST_IP_LBN 1 9161 #define MC_CMD_FILTER_OP_IN_MATCH_DST_IP_WIDTH 1 9162 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_LBN 2 9163 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_WIDTH 1 9164 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_LBN 3 9165 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_WIDTH 1 9166 #define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_LBN 4 9167 #define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_WIDTH 1 9168 #define MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_LBN 5 9169 #define MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_WIDTH 1 9170 #define MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_LBN 6 9171 #define MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_WIDTH 1 9172 #define MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_LBN 7 9173 #define MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_WIDTH 1 9174 #define MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_LBN 8 9175 #define MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_WIDTH 1 9176 #define MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_LBN 9 9177 #define MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_WIDTH 1 9178 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_LBN 10 9179 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_WIDTH 1 9180 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_LBN 11 9181 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_WIDTH 1 9182 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN 30 9183 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1 9184 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN 31 9185 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1 9186 /* receive destination */ 9187 #define MC_CMD_FILTER_OP_IN_RX_DEST_OFST 20 9188 /* enum: drop packets */ 9189 #define MC_CMD_FILTER_OP_IN_RX_DEST_DROP 0x0 9190 /* enum: receive to host */ 9191 #define MC_CMD_FILTER_OP_IN_RX_DEST_HOST 0x1 9192 /* enum: receive to MC */ 9193 #define MC_CMD_FILTER_OP_IN_RX_DEST_MC 0x2 9194 /* enum: loop back to TXDP 0 */ 9195 #define MC_CMD_FILTER_OP_IN_RX_DEST_TX0 0x3 9196 /* enum: loop back to TXDP 1 */ 9197 #define MC_CMD_FILTER_OP_IN_RX_DEST_TX1 0x4 9198 /* receive queue handle (for multiple queue modes, this is the base queue) */ 9199 #define MC_CMD_FILTER_OP_IN_RX_QUEUE_OFST 24 9200 /* receive mode */ 9201 #define MC_CMD_FILTER_OP_IN_RX_MODE_OFST 28 9202 /* enum: receive to just the specified queue */ 9203 #define MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE 0x0 9204 /* enum: receive to multiple queues using RSS context */ 9205 #define MC_CMD_FILTER_OP_IN_RX_MODE_RSS 0x1 9206 /* enum: receive to multiple queues using .1p mapping */ 9207 #define MC_CMD_FILTER_OP_IN_RX_MODE_DOT1P_MAPPING 0x2 9208 /* enum: install a filter entry that will never match; for test purposes only 9209 */ 9210 #define MC_CMD_FILTER_OP_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000 9211 /* RSS context (for RX_MODE_RSS) or .1p mapping handle (for 9212 * RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or 9213 * MC_CMD_DOT1P_MAPPING_ALLOC. 9214 */ 9215 #define MC_CMD_FILTER_OP_IN_RX_CONTEXT_OFST 32 9216 /* transmit domain (reserved; set to 0) */ 9217 #define MC_CMD_FILTER_OP_IN_TX_DOMAIN_OFST 36 9218 /* transmit destination (either set the MAC and/or PM bits for explicit 9219 * control, or set this field to TX_DEST_DEFAULT for sensible default 9220 * behaviour) 9221 */ 9222 #define MC_CMD_FILTER_OP_IN_TX_DEST_OFST 40 9223 /* enum: request default behaviour (based on filter type) */ 9224 #define MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT 0xffffffff 9225 #define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_LBN 0 9226 #define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_WIDTH 1 9227 #define MC_CMD_FILTER_OP_IN_TX_DEST_PM_LBN 1 9228 #define MC_CMD_FILTER_OP_IN_TX_DEST_PM_WIDTH 1 9229 /* source MAC address to match (as bytes in network order) */ 9230 #define MC_CMD_FILTER_OP_IN_SRC_MAC_OFST 44 9231 #define MC_CMD_FILTER_OP_IN_SRC_MAC_LEN 6 9232 /* source port to match (as bytes in network order) */ 9233 #define MC_CMD_FILTER_OP_IN_SRC_PORT_OFST 50 9234 #define MC_CMD_FILTER_OP_IN_SRC_PORT_LEN 2 9235 /* destination MAC address to match (as bytes in network order) */ 9236 #define MC_CMD_FILTER_OP_IN_DST_MAC_OFST 52 9237 #define MC_CMD_FILTER_OP_IN_DST_MAC_LEN 6 9238 /* destination port to match (as bytes in network order) */ 9239 #define MC_CMD_FILTER_OP_IN_DST_PORT_OFST 58 9240 #define MC_CMD_FILTER_OP_IN_DST_PORT_LEN 2 9241 /* Ethernet type to match (as bytes in network order) */ 9242 #define MC_CMD_FILTER_OP_IN_ETHER_TYPE_OFST 60 9243 #define MC_CMD_FILTER_OP_IN_ETHER_TYPE_LEN 2 9244 /* Inner VLAN tag to match (as bytes in network order) */ 9245 #define MC_CMD_FILTER_OP_IN_INNER_VLAN_OFST 62 9246 #define MC_CMD_FILTER_OP_IN_INNER_VLAN_LEN 2 9247 /* Outer VLAN tag to match (as bytes in network order) */ 9248 #define MC_CMD_FILTER_OP_IN_OUTER_VLAN_OFST 64 9249 #define MC_CMD_FILTER_OP_IN_OUTER_VLAN_LEN 2 9250 /* IP protocol to match (in low byte; set high byte to 0) */ 9251 #define MC_CMD_FILTER_OP_IN_IP_PROTO_OFST 66 9252 #define MC_CMD_FILTER_OP_IN_IP_PROTO_LEN 2 9253 /* Firmware defined register 0 to match (reserved; set to 0) */ 9254 #define MC_CMD_FILTER_OP_IN_FWDEF0_OFST 68 9255 /* Firmware defined register 1 to match (reserved; set to 0) */ 9256 #define MC_CMD_FILTER_OP_IN_FWDEF1_OFST 72 9257 /* source IP address to match (as bytes in network order; set last 12 bytes to 9258 * 0 for IPv4 address) 9259 */ 9260 #define MC_CMD_FILTER_OP_IN_SRC_IP_OFST 76 9261 #define MC_CMD_FILTER_OP_IN_SRC_IP_LEN 16 9262 /* destination IP address to match (as bytes in network order; set last 12 9263 * bytes to 0 for IPv4 address) 9264 */ 9265 #define MC_CMD_FILTER_OP_IN_DST_IP_OFST 92 9266 #define MC_CMD_FILTER_OP_IN_DST_IP_LEN 16 9267 9268 /* MC_CMD_FILTER_OP_EXT_IN msgrequest: Extension to MC_CMD_FILTER_OP_IN to 9269 * include handling of VXLAN/NVGRE encapsulated frame filtering (which is 9270 * supported on Medford only). 9271 */ 9272 #define MC_CMD_FILTER_OP_EXT_IN_LEN 172 9273 /* identifies the type of operation requested */ 9274 #define MC_CMD_FILTER_OP_EXT_IN_OP_OFST 0 9275 /* Enum values, see field(s): */ 9276 /* MC_CMD_FILTER_OP_IN/OP */ 9277 /* filter handle (for remove / unsubscribe operations) */ 9278 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_OFST 4 9279 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LEN 8 9280 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LO_OFST 4 9281 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_HI_OFST 8 9282 /* The port ID associated with the v-adaptor which should contain this filter. 9283 */ 9284 #define MC_CMD_FILTER_OP_EXT_IN_PORT_ID_OFST 12 9285 /* fields to include in match criteria */ 9286 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_FIELDS_OFST 16 9287 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_LBN 0 9288 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_WIDTH 1 9289 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_IP_LBN 1 9290 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_IP_WIDTH 1 9291 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_MAC_LBN 2 9292 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_MAC_WIDTH 1 9293 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_PORT_LBN 3 9294 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_PORT_WIDTH 1 9295 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_LBN 4 9296 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_WIDTH 1 9297 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_PORT_LBN 5 9298 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_PORT_WIDTH 1 9299 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_LBN 6 9300 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_WIDTH 1 9301 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_INNER_VLAN_LBN 7 9302 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_INNER_VLAN_WIDTH 1 9303 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_OUTER_VLAN_LBN 8 9304 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_OUTER_VLAN_WIDTH 1 9305 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_LBN 9 9306 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_WIDTH 1 9307 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_FWDEF0_LBN 10 9308 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_FWDEF0_WIDTH 1 9309 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_VNI_OR_VSID_LBN 11 9310 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_VNI_OR_VSID_WIDTH 1 9311 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_IP_LBN 12 9312 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_IP_WIDTH 1 9313 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_IP_LBN 13 9314 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_IP_WIDTH 1 9315 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_MAC_LBN 14 9316 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_MAC_WIDTH 1 9317 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_PORT_LBN 15 9318 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_PORT_WIDTH 1 9319 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_MAC_LBN 16 9320 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_MAC_WIDTH 1 9321 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_PORT_LBN 17 9322 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_PORT_WIDTH 1 9323 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ETHER_TYPE_LBN 18 9324 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ETHER_TYPE_WIDTH 1 9325 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_INNER_VLAN_LBN 19 9326 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_INNER_VLAN_WIDTH 1 9327 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_OUTER_VLAN_LBN 20 9328 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_OUTER_VLAN_WIDTH 1 9329 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_IP_PROTO_LBN 21 9330 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_IP_PROTO_WIDTH 1 9331 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF0_LBN 22 9332 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF0_WIDTH 1 9333 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF1_LBN 23 9334 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF1_WIDTH 1 9335 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_LBN 24 9336 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_WIDTH 1 9337 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_LBN 25 9338 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_WIDTH 1 9339 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_LBN 30 9340 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1 9341 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_LBN 31 9342 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1 9343 /* receive destination */ 9344 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_OFST 20 9345 /* enum: drop packets */ 9346 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_DROP 0x0 9347 /* enum: receive to host */ 9348 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_HOST 0x1 9349 /* enum: receive to MC */ 9350 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_MC 0x2 9351 /* enum: loop back to TXDP 0 */ 9352 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_TX0 0x3 9353 /* enum: loop back to TXDP 1 */ 9354 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_TX1 0x4 9355 /* receive queue handle (for multiple queue modes, this is the base queue) */ 9356 #define MC_CMD_FILTER_OP_EXT_IN_RX_QUEUE_OFST 24 9357 /* receive mode */ 9358 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_OFST 28 9359 /* enum: receive to just the specified queue */ 9360 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_SIMPLE 0x0 9361 /* enum: receive to multiple queues using RSS context */ 9362 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_RSS 0x1 9363 /* enum: receive to multiple queues using .1p mapping */ 9364 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_DOT1P_MAPPING 0x2 9365 /* enum: install a filter entry that will never match; for test purposes only 9366 */ 9367 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000 9368 /* RSS context (for RX_MODE_RSS) or .1p mapping handle (for 9369 * RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or 9370 * MC_CMD_DOT1P_MAPPING_ALLOC. 9371 */ 9372 #define MC_CMD_FILTER_OP_EXT_IN_RX_CONTEXT_OFST 32 9373 /* transmit domain (reserved; set to 0) */ 9374 #define MC_CMD_FILTER_OP_EXT_IN_TX_DOMAIN_OFST 36 9375 /* transmit destination (either set the MAC and/or PM bits for explicit 9376 * control, or set this field to TX_DEST_DEFAULT for sensible default 9377 * behaviour) 9378 */ 9379 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_OFST 40 9380 /* enum: request default behaviour (based on filter type) */ 9381 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_DEFAULT 0xffffffff 9382 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_LBN 0 9383 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_WIDTH 1 9384 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_PM_LBN 1 9385 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_PM_WIDTH 1 9386 /* source MAC address to match (as bytes in network order) */ 9387 #define MC_CMD_FILTER_OP_EXT_IN_SRC_MAC_OFST 44 9388 #define MC_CMD_FILTER_OP_EXT_IN_SRC_MAC_LEN 6 9389 /* source port to match (as bytes in network order) */ 9390 #define MC_CMD_FILTER_OP_EXT_IN_SRC_PORT_OFST 50 9391 #define MC_CMD_FILTER_OP_EXT_IN_SRC_PORT_LEN 2 9392 /* destination MAC address to match (as bytes in network order) */ 9393 #define MC_CMD_FILTER_OP_EXT_IN_DST_MAC_OFST 52 9394 #define MC_CMD_FILTER_OP_EXT_IN_DST_MAC_LEN 6 9395 /* destination port to match (as bytes in network order) */ 9396 #define MC_CMD_FILTER_OP_EXT_IN_DST_PORT_OFST 58 9397 #define MC_CMD_FILTER_OP_EXT_IN_DST_PORT_LEN 2 9398 /* Ethernet type to match (as bytes in network order) */ 9399 #define MC_CMD_FILTER_OP_EXT_IN_ETHER_TYPE_OFST 60 9400 #define MC_CMD_FILTER_OP_EXT_IN_ETHER_TYPE_LEN 2 9401 /* Inner VLAN tag to match (as bytes in network order) */ 9402 #define MC_CMD_FILTER_OP_EXT_IN_INNER_VLAN_OFST 62 9403 #define MC_CMD_FILTER_OP_EXT_IN_INNER_VLAN_LEN 2 9404 /* Outer VLAN tag to match (as bytes in network order) */ 9405 #define MC_CMD_FILTER_OP_EXT_IN_OUTER_VLAN_OFST 64 9406 #define MC_CMD_FILTER_OP_EXT_IN_OUTER_VLAN_LEN 2 9407 /* IP protocol to match (in low byte; set high byte to 0) */ 9408 #define MC_CMD_FILTER_OP_EXT_IN_IP_PROTO_OFST 66 9409 #define MC_CMD_FILTER_OP_EXT_IN_IP_PROTO_LEN 2 9410 /* Firmware defined register 0 to match (reserved; set to 0) */ 9411 #define MC_CMD_FILTER_OP_EXT_IN_FWDEF0_OFST 68 9412 /* VNI (for VXLAN/Geneve, when IP protocol is UDP) or VSID (for NVGRE, when IP 9413 * protocol is GRE) to match (as bytes in network order; set last byte to 0 for 9414 * VXLAN/NVGRE, or 1 for Geneve) 9415 */ 9416 #define MC_CMD_FILTER_OP_EXT_IN_VNI_OR_VSID_OFST 72 9417 #define MC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_LBN 0 9418 #define MC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_WIDTH 24 9419 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_LBN 24 9420 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_WIDTH 8 9421 /* enum: Match VXLAN traffic with this VNI */ 9422 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_VXLAN 0x0 9423 /* enum: Match Geneve traffic with this VNI */ 9424 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_GENEVE 0x1 9425 /* enum: Reserved for experimental development use */ 9426 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_EXPERIMENTAL 0xfe 9427 #define MC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_LBN 0 9428 #define MC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_WIDTH 24 9429 #define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_LBN 24 9430 #define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_WIDTH 8 9431 /* enum: Match NVGRE traffic with this VSID */ 9432 #define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_NVGRE 0x0 9433 /* source IP address to match (as bytes in network order; set last 12 bytes to 9434 * 0 for IPv4 address) 9435 */ 9436 #define MC_CMD_FILTER_OP_EXT_IN_SRC_IP_OFST 76 9437 #define MC_CMD_FILTER_OP_EXT_IN_SRC_IP_LEN 16 9438 /* destination IP address to match (as bytes in network order; set last 12 9439 * bytes to 0 for IPv4 address) 9440 */ 9441 #define MC_CMD_FILTER_OP_EXT_IN_DST_IP_OFST 92 9442 #define MC_CMD_FILTER_OP_EXT_IN_DST_IP_LEN 16 9443 /* VXLAN/NVGRE inner frame source MAC address to match (as bytes in network 9444 * order) 9445 */ 9446 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_MAC_OFST 108 9447 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_MAC_LEN 6 9448 /* VXLAN/NVGRE inner frame source port to match (as bytes in network order) */ 9449 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_PORT_OFST 114 9450 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_PORT_LEN 2 9451 /* VXLAN/NVGRE inner frame destination MAC address to match (as bytes in 9452 * network order) 9453 */ 9454 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_MAC_OFST 116 9455 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_MAC_LEN 6 9456 /* VXLAN/NVGRE inner frame destination port to match (as bytes in network 9457 * order) 9458 */ 9459 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_PORT_OFST 122 9460 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_PORT_LEN 2 9461 /* VXLAN/NVGRE inner frame Ethernet type to match (as bytes in network order) 9462 */ 9463 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_ETHER_TYPE_OFST 124 9464 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_ETHER_TYPE_LEN 2 9465 /* VXLAN/NVGRE inner frame Inner VLAN tag to match (as bytes in network order) 9466 */ 9467 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_INNER_VLAN_OFST 126 9468 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_INNER_VLAN_LEN 2 9469 /* VXLAN/NVGRE inner frame Outer VLAN tag to match (as bytes in network order) 9470 */ 9471 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_OUTER_VLAN_OFST 128 9472 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_OUTER_VLAN_LEN 2 9473 /* VXLAN/NVGRE inner frame IP protocol to match (in low byte; set high byte to 9474 * 0) 9475 */ 9476 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_IP_PROTO_OFST 130 9477 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_IP_PROTO_LEN 2 9478 /* VXLAN/NVGRE inner frame Firmware defined register 0 to match (reserved; set 9479 * to 0) 9480 */ 9481 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF0_OFST 132 9482 /* VXLAN/NVGRE inner frame Firmware defined register 1 to match (reserved; set 9483 * to 0) 9484 */ 9485 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF1_OFST 136 9486 /* VXLAN/NVGRE inner frame source IP address to match (as bytes in network 9487 * order; set last 12 bytes to 0 for IPv4 address) 9488 */ 9489 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_IP_OFST 140 9490 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_IP_LEN 16 9491 /* VXLAN/NVGRE inner frame destination IP address to match (as bytes in network 9492 * order; set last 12 bytes to 0 for IPv4 address) 9493 */ 9494 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_IP_OFST 156 9495 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_IP_LEN 16 9496 9497 /* MC_CMD_FILTER_OP_OUT msgresponse */ 9498 #define MC_CMD_FILTER_OP_OUT_LEN 12 9499 /* identifies the type of operation requested */ 9500 #define MC_CMD_FILTER_OP_OUT_OP_OFST 0 9501 /* Enum values, see field(s): */ 9502 /* MC_CMD_FILTER_OP_IN/OP */ 9503 /* Returned filter handle (for insert / subscribe operations). Note that these 9504 * handles should be considered opaque to the host, although a value of 9505 * 0xFFFFFFFF_FFFFFFFF is guaranteed never to be a valid handle. 9506 */ 9507 #define MC_CMD_FILTER_OP_OUT_HANDLE_OFST 4 9508 #define MC_CMD_FILTER_OP_OUT_HANDLE_LEN 8 9509 #define MC_CMD_FILTER_OP_OUT_HANDLE_LO_OFST 4 9510 #define MC_CMD_FILTER_OP_OUT_HANDLE_HI_OFST 8 9511 /* enum: guaranteed invalid filter handle (low 32 bits) */ 9512 #define MC_CMD_FILTER_OP_OUT_HANDLE_LO_INVALID 0xffffffff 9513 /* enum: guaranteed invalid filter handle (high 32 bits) */ 9514 #define MC_CMD_FILTER_OP_OUT_HANDLE_HI_INVALID 0xffffffff 9515 9516 /* MC_CMD_FILTER_OP_EXT_OUT msgresponse */ 9517 #define MC_CMD_FILTER_OP_EXT_OUT_LEN 12 9518 /* identifies the type of operation requested */ 9519 #define MC_CMD_FILTER_OP_EXT_OUT_OP_OFST 0 9520 /* Enum values, see field(s): */ 9521 /* MC_CMD_FILTER_OP_EXT_IN/OP */ 9522 /* Returned filter handle (for insert / subscribe operations). Note that these 9523 * handles should be considered opaque to the host, although a value of 9524 * 0xFFFFFFFF_FFFFFFFF is guaranteed never to be a valid handle. 9525 */ 9526 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_OFST 4 9527 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LEN 8 9528 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LO_OFST 4 9529 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_HI_OFST 8 9530 /* Enum values, see field(s): */ 9531 /* MC_CMD_FILTER_OP_OUT/HANDLE */ 9532 9533 9534 /***********************************/ 9535 /* MC_CMD_GET_PARSER_DISP_INFO 9536 * Get information related to the parser-dispatcher subsystem 9537 */ 9538 #define MC_CMD_GET_PARSER_DISP_INFO 0xe4 9539 #undef MC_CMD_0xe4_PRIVILEGE_CTG 9540 9541 #define MC_CMD_0xe4_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9542 9543 /* MC_CMD_GET_PARSER_DISP_INFO_IN msgrequest */ 9544 #define MC_CMD_GET_PARSER_DISP_INFO_IN_LEN 4 9545 /* identifies the type of operation requested */ 9546 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_OFST 0 9547 /* enum: read the list of supported RX filter matches */ 9548 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES 0x1 9549 /* enum: read flags indicating restrictions on filter insertion for the calling 9550 * client 9551 */ 9552 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_RESTRICTIONS 0x2 9553 /* enum: read properties relating to security rules (Medford-only; for use by 9554 * SolarSecure apps, not directly by drivers. See SF-114946-SW.) 9555 */ 9556 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SECURITY_RULE_INFO 0x3 9557 /* enum: read the list of supported RX filter matches for VXLAN/NVGRE 9558 * encapsulated frames, which follow a different match sequence to normal 9559 * frames (Medford only) 9560 */ 9561 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_ENCAP_RX_MATCHES 0x4 9562 9563 /* MC_CMD_GET_PARSER_DISP_INFO_OUT msgresponse */ 9564 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMIN 8 9565 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX 252 9566 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_LEN(num) (8+4*(num)) 9567 /* identifies the type of operation requested */ 9568 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_OP_OFST 0 9569 /* Enum values, see field(s): */ 9570 /* MC_CMD_GET_PARSER_DISP_INFO_IN/OP */ 9571 /* number of supported match types */ 9572 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_NUM_SUPPORTED_MATCHES_OFST 4 9573 /* array of supported match types (valid MATCH_FIELDS values for 9574 * MC_CMD_FILTER_OP) sorted in decreasing priority order 9575 */ 9576 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_OFST 8 9577 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_LEN 4 9578 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MINNUM 0 9579 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM 61 9580 9581 /* MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT msgresponse */ 9582 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_LEN 8 9583 /* identifies the type of operation requested */ 9584 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_OP_OFST 0 9585 /* Enum values, see field(s): */ 9586 /* MC_CMD_GET_PARSER_DISP_INFO_IN/OP */ 9587 /* bitfield of filter insertion restrictions */ 9588 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_RESTRICTION_FLAGS_OFST 4 9589 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_LBN 0 9590 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_WIDTH 1 9591 9592 /* MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT msgresponse: 9593 * GET_PARSER_DISP_INFO response format for OP_GET_SECURITY_RULE_INFO. 9594 * (Medford-only; for use by SolarSecure apps, not directly by drivers. See 9595 * SF-114946-SW.) NOTE - this message definition is provisional. It has not yet 9596 * been used in any released code and may change during development. This note 9597 * will be removed once it is regarded as stable. 9598 */ 9599 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_LEN 36 9600 /* identifies the type of operation requested */ 9601 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_OP_OFST 0 9602 /* Enum values, see field(s): */ 9603 /* MC_CMD_GET_PARSER_DISP_INFO_IN/OP */ 9604 /* a version number representing the set of rule lookups that are implemented 9605 * by the currently running firmware 9606 */ 9607 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_RULES_VERSION_OFST 4 9608 /* enum: implements lookup sequences described in SF-114946-SW draft C */ 9609 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_RULES_VERSION_SF_114946_SW_C 0x0 9610 /* the number of nodes in the subnet map */ 9611 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_MAP_NUM_NODES_OFST 8 9612 /* the number of entries in one subnet map node */ 9613 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_MAP_NUM_ENTRIES_PER_NODE_OFST 12 9614 /* minimum valid value for a subnet ID in a subnet map leaf */ 9615 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_ID_MIN_OFST 16 9616 /* maximum valid value for a subnet ID in a subnet map leaf */ 9617 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_ID_MAX_OFST 20 9618 /* the number of entries in the local and remote port range maps */ 9619 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_PORTRANGE_TREE_NUM_ENTRIES_OFST 24 9620 /* minimum valid value for a portrange ID in a port range map leaf */ 9621 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_PORTRANGE_ID_MIN_OFST 28 9622 /* maximum valid value for a portrange ID in a port range map leaf */ 9623 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_PORTRANGE_ID_MAX_OFST 32 9624 9625 9626 /***********************************/ 9627 /* MC_CMD_PARSER_DISP_RW 9628 * Direct read/write of parser-dispatcher state (DICPUs and LUE) for debugging. 9629 * Please note that this interface is only of use to debug tools which have 9630 * knowledge of firmware and hardware data structures; nothing here is intended 9631 * for use by normal driver code. 9632 */ 9633 #define MC_CMD_PARSER_DISP_RW 0xe5 9634 #undef MC_CMD_0xe5_PRIVILEGE_CTG 9635 9636 #define MC_CMD_0xe5_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9637 9638 /* MC_CMD_PARSER_DISP_RW_IN msgrequest */ 9639 #define MC_CMD_PARSER_DISP_RW_IN_LEN 32 9640 /* identifies the target of the operation */ 9641 #define MC_CMD_PARSER_DISP_RW_IN_TARGET_OFST 0 9642 /* enum: RX dispatcher CPU */ 9643 #define MC_CMD_PARSER_DISP_RW_IN_RX_DICPU 0x0 9644 /* enum: TX dispatcher CPU */ 9645 #define MC_CMD_PARSER_DISP_RW_IN_TX_DICPU 0x1 9646 /* enum: Lookup engine (with original metadata format). Deprecated; used only 9647 * by cmdclient as a fallback for very old Huntington firmware, and not 9648 * supported in firmware beyond v6.4.0.1005. Use LUE_VERSIONED_METADATA 9649 * instead. 9650 */ 9651 #define MC_CMD_PARSER_DISP_RW_IN_LUE 0x2 9652 /* enum: Lookup engine (with requested metadata format) */ 9653 #define MC_CMD_PARSER_DISP_RW_IN_LUE_VERSIONED_METADATA 0x3 9654 /* enum: RX0 dispatcher CPU (alias for RX_DICPU; Medford has 2 RX DICPUs) */ 9655 #define MC_CMD_PARSER_DISP_RW_IN_RX0_DICPU 0x0 9656 /* enum: RX1 dispatcher CPU (only valid for Medford) */ 9657 #define MC_CMD_PARSER_DISP_RW_IN_RX1_DICPU 0x4 9658 /* enum: Miscellaneous other state (only valid for Medford) */ 9659 #define MC_CMD_PARSER_DISP_RW_IN_MISC_STATE 0x5 9660 /* identifies the type of operation requested */ 9661 #define MC_CMD_PARSER_DISP_RW_IN_OP_OFST 4 9662 /* enum: read a word of DICPU DMEM or a LUE entry */ 9663 #define MC_CMD_PARSER_DISP_RW_IN_READ 0x0 9664 /* enum: write a word of DICPU DMEM or a LUE entry */ 9665 #define MC_CMD_PARSER_DISP_RW_IN_WRITE 0x1 9666 /* enum: read-modify-write a word of DICPU DMEM (not valid for LUE) */ 9667 #define MC_CMD_PARSER_DISP_RW_IN_RMW 0x2 9668 /* data memory address (DICPU targets) or LUE index (LUE targets) */ 9669 #define MC_CMD_PARSER_DISP_RW_IN_ADDRESS_OFST 8 9670 /* selector (for MISC_STATE target) */ 9671 #define MC_CMD_PARSER_DISP_RW_IN_SELECTOR_OFST 8 9672 /* enum: Port to datapath mapping */ 9673 #define MC_CMD_PARSER_DISP_RW_IN_PORT_DP_MAPPING 0x1 9674 /* value to write (for DMEM writes) */ 9675 #define MC_CMD_PARSER_DISP_RW_IN_DMEM_WRITE_VALUE_OFST 12 9676 /* XOR value (for DMEM read-modify-writes: new = (old & mask) ^ value) */ 9677 #define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_XOR_VALUE_OFST 12 9678 /* AND mask (for DMEM read-modify-writes: new = (old & mask) ^ value) */ 9679 #define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_AND_MASK_OFST 16 9680 /* metadata format (for LUE reads using LUE_VERSIONED_METADATA) */ 9681 #define MC_CMD_PARSER_DISP_RW_IN_LUE_READ_METADATA_VERSION_OFST 12 9682 /* value to write (for LUE writes) */ 9683 #define MC_CMD_PARSER_DISP_RW_IN_LUE_WRITE_VALUE_OFST 12 9684 #define MC_CMD_PARSER_DISP_RW_IN_LUE_WRITE_VALUE_LEN 20 9685 9686 /* MC_CMD_PARSER_DISP_RW_OUT msgresponse */ 9687 #define MC_CMD_PARSER_DISP_RW_OUT_LEN 52 9688 /* value read (for DMEM reads) */ 9689 #define MC_CMD_PARSER_DISP_RW_OUT_DMEM_READ_VALUE_OFST 0 9690 /* value read (for LUE reads) */ 9691 #define MC_CMD_PARSER_DISP_RW_OUT_LUE_READ_VALUE_OFST 0 9692 #define MC_CMD_PARSER_DISP_RW_OUT_LUE_READ_VALUE_LEN 20 9693 /* up to 8 32-bit words of additional soft state from the LUE manager (the 9694 * exact content is firmware-dependent and intended only for debug use) 9695 */ 9696 #define MC_CMD_PARSER_DISP_RW_OUT_LUE_MGR_STATE_OFST 20 9697 #define MC_CMD_PARSER_DISP_RW_OUT_LUE_MGR_STATE_LEN 32 9698 /* datapath(s) used for each port (for MISC_STATE PORT_DP_MAPPING selector) */ 9699 #define MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_OFST 0 9700 #define MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_LEN 4 9701 #define MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_NUM 4 9702 #define MC_CMD_PARSER_DISP_RW_OUT_DP0 0x1 /* enum */ 9703 #define MC_CMD_PARSER_DISP_RW_OUT_DP1 0x2 /* enum */ 9704 9705 9706 /***********************************/ 9707 /* MC_CMD_GET_PF_COUNT 9708 * Get number of PFs on the device. 9709 */ 9710 #define MC_CMD_GET_PF_COUNT 0xb6 9711 #undef MC_CMD_0xb6_PRIVILEGE_CTG 9712 9713 #define MC_CMD_0xb6_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9714 9715 /* MC_CMD_GET_PF_COUNT_IN msgrequest */ 9716 #define MC_CMD_GET_PF_COUNT_IN_LEN 0 9717 9718 /* MC_CMD_GET_PF_COUNT_OUT msgresponse */ 9719 #define MC_CMD_GET_PF_COUNT_OUT_LEN 1 9720 /* Identifies the number of PFs on the device. */ 9721 #define MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_OFST 0 9722 #define MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_LEN 1 9723 9724 9725 /***********************************/ 9726 /* MC_CMD_SET_PF_COUNT 9727 * Set number of PFs on the device. 9728 */ 9729 #define MC_CMD_SET_PF_COUNT 0xb7 9730 9731 /* MC_CMD_SET_PF_COUNT_IN msgrequest */ 9732 #define MC_CMD_SET_PF_COUNT_IN_LEN 4 9733 /* New number of PFs on the device. */ 9734 #define MC_CMD_SET_PF_COUNT_IN_PF_COUNT_OFST 0 9735 9736 /* MC_CMD_SET_PF_COUNT_OUT msgresponse */ 9737 #define MC_CMD_SET_PF_COUNT_OUT_LEN 0 9738 9739 9740 /***********************************/ 9741 /* MC_CMD_GET_PORT_ASSIGNMENT 9742 * Get port assignment for current PCI function. 9743 */ 9744 #define MC_CMD_GET_PORT_ASSIGNMENT 0xb8 9745 #undef MC_CMD_0xb8_PRIVILEGE_CTG 9746 9747 #define MC_CMD_0xb8_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9748 9749 /* MC_CMD_GET_PORT_ASSIGNMENT_IN msgrequest */ 9750 #define MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN 0 9751 9752 /* MC_CMD_GET_PORT_ASSIGNMENT_OUT msgresponse */ 9753 #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN 4 9754 /* Identifies the port assignment for this function. */ 9755 #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_PORT_OFST 0 9756 9757 9758 /***********************************/ 9759 /* MC_CMD_SET_PORT_ASSIGNMENT 9760 * Set port assignment for current PCI function. 9761 */ 9762 #define MC_CMD_SET_PORT_ASSIGNMENT 0xb9 9763 #undef MC_CMD_0xb9_PRIVILEGE_CTG 9764 9765 #define MC_CMD_0xb9_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9766 9767 /* MC_CMD_SET_PORT_ASSIGNMENT_IN msgrequest */ 9768 #define MC_CMD_SET_PORT_ASSIGNMENT_IN_LEN 4 9769 /* Identifies the port assignment for this function. */ 9770 #define MC_CMD_SET_PORT_ASSIGNMENT_IN_PORT_OFST 0 9771 9772 /* MC_CMD_SET_PORT_ASSIGNMENT_OUT msgresponse */ 9773 #define MC_CMD_SET_PORT_ASSIGNMENT_OUT_LEN 0 9774 9775 9776 /***********************************/ 9777 /* MC_CMD_ALLOC_VIS 9778 * Allocate VIs for current PCI function. 9779 */ 9780 #define MC_CMD_ALLOC_VIS 0x8b 9781 #undef MC_CMD_0x8b_PRIVILEGE_CTG 9782 9783 #define MC_CMD_0x8b_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9784 9785 /* MC_CMD_ALLOC_VIS_IN msgrequest */ 9786 #define MC_CMD_ALLOC_VIS_IN_LEN 8 9787 /* The minimum number of VIs that is acceptable */ 9788 #define MC_CMD_ALLOC_VIS_IN_MIN_VI_COUNT_OFST 0 9789 /* The maximum number of VIs that would be useful */ 9790 #define MC_CMD_ALLOC_VIS_IN_MAX_VI_COUNT_OFST 4 9791 9792 /* MC_CMD_ALLOC_VIS_OUT msgresponse: Huntington-compatible VI_ALLOC request. 9793 * Use extended version in new code. 9794 */ 9795 #define MC_CMD_ALLOC_VIS_OUT_LEN 8 9796 /* The number of VIs allocated on this function */ 9797 #define MC_CMD_ALLOC_VIS_OUT_VI_COUNT_OFST 0 9798 /* The base absolute VI number allocated to this function. Required to 9799 * correctly interpret wakeup events. 9800 */ 9801 #define MC_CMD_ALLOC_VIS_OUT_VI_BASE_OFST 4 9802 9803 /* MC_CMD_ALLOC_VIS_EXT_OUT msgresponse */ 9804 #define MC_CMD_ALLOC_VIS_EXT_OUT_LEN 12 9805 /* The number of VIs allocated on this function */ 9806 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_COUNT_OFST 0 9807 /* The base absolute VI number allocated to this function. Required to 9808 * correctly interpret wakeup events. 9809 */ 9810 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_BASE_OFST 4 9811 /* Function's port vi_shift value (always 0 on Huntington) */ 9812 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_SHIFT_OFST 8 9813 9814 9815 /***********************************/ 9816 /* MC_CMD_FREE_VIS 9817 * Free VIs for current PCI function. Any linked PIO buffers will be unlinked, 9818 * but not freed. 9819 */ 9820 #define MC_CMD_FREE_VIS 0x8c 9821 #undef MC_CMD_0x8c_PRIVILEGE_CTG 9822 9823 #define MC_CMD_0x8c_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9824 9825 /* MC_CMD_FREE_VIS_IN msgrequest */ 9826 #define MC_CMD_FREE_VIS_IN_LEN 0 9827 9828 /* MC_CMD_FREE_VIS_OUT msgresponse */ 9829 #define MC_CMD_FREE_VIS_OUT_LEN 0 9830 9831 9832 /***********************************/ 9833 /* MC_CMD_GET_SRIOV_CFG 9834 * Get SRIOV config for this PF. 9835 */ 9836 #define MC_CMD_GET_SRIOV_CFG 0xba 9837 #undef MC_CMD_0xba_PRIVILEGE_CTG 9838 9839 #define MC_CMD_0xba_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9840 9841 /* MC_CMD_GET_SRIOV_CFG_IN msgrequest */ 9842 #define MC_CMD_GET_SRIOV_CFG_IN_LEN 0 9843 9844 /* MC_CMD_GET_SRIOV_CFG_OUT msgresponse */ 9845 #define MC_CMD_GET_SRIOV_CFG_OUT_LEN 20 9846 /* Number of VFs currently enabled. */ 9847 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_CURRENT_OFST 0 9848 /* Max number of VFs before sriov stride and offset may need to be changed. */ 9849 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_MAX_OFST 4 9850 #define MC_CMD_GET_SRIOV_CFG_OUT_FLAGS_OFST 8 9851 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_LBN 0 9852 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_WIDTH 1 9853 /* RID offset of first VF from PF. */ 9854 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_OFFSET_OFST 12 9855 /* RID offset of each subsequent VF from the previous. */ 9856 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_STRIDE_OFST 16 9857 9858 9859 /***********************************/ 9860 /* MC_CMD_SET_SRIOV_CFG 9861 * Set SRIOV config for this PF. 9862 */ 9863 #define MC_CMD_SET_SRIOV_CFG 0xbb 9864 #undef MC_CMD_0xbb_PRIVILEGE_CTG 9865 9866 #define MC_CMD_0xbb_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9867 9868 /* MC_CMD_SET_SRIOV_CFG_IN msgrequest */ 9869 #define MC_CMD_SET_SRIOV_CFG_IN_LEN 20 9870 /* Number of VFs currently enabled. */ 9871 #define MC_CMD_SET_SRIOV_CFG_IN_VF_CURRENT_OFST 0 9872 /* Max number of VFs before sriov stride and offset may need to be changed. */ 9873 #define MC_CMD_SET_SRIOV_CFG_IN_VF_MAX_OFST 4 9874 #define MC_CMD_SET_SRIOV_CFG_IN_FLAGS_OFST 8 9875 #define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_LBN 0 9876 #define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_WIDTH 1 9877 /* RID offset of first VF from PF, or 0 for no change, or 9878 * MC_CMD_RESOURCE_INSTANCE_ANY to allow the system to allocate an offset. 9879 */ 9880 #define MC_CMD_SET_SRIOV_CFG_IN_VF_OFFSET_OFST 12 9881 /* RID offset of each subsequent VF from the previous, 0 for no change, or 9882 * MC_CMD_RESOURCE_INSTANCE_ANY to allow the system to allocate a stride. 9883 */ 9884 #define MC_CMD_SET_SRIOV_CFG_IN_VF_STRIDE_OFST 16 9885 9886 /* MC_CMD_SET_SRIOV_CFG_OUT msgresponse */ 9887 #define MC_CMD_SET_SRIOV_CFG_OUT_LEN 0 9888 9889 9890 /***********************************/ 9891 /* MC_CMD_GET_VI_ALLOC_INFO 9892 * Get information about number of VI's and base VI number allocated to this 9893 * function. 9894 */ 9895 #define MC_CMD_GET_VI_ALLOC_INFO 0x8d 9896 #undef MC_CMD_0x8d_PRIVILEGE_CTG 9897 9898 #define MC_CMD_0x8d_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9899 9900 /* MC_CMD_GET_VI_ALLOC_INFO_IN msgrequest */ 9901 #define MC_CMD_GET_VI_ALLOC_INFO_IN_LEN 0 9902 9903 /* MC_CMD_GET_VI_ALLOC_INFO_OUT msgresponse */ 9904 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_LEN 12 9905 /* The number of VIs allocated on this function */ 9906 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_COUNT_OFST 0 9907 /* The base absolute VI number allocated to this function. Required to 9908 * correctly interpret wakeup events. 9909 */ 9910 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_BASE_OFST 4 9911 /* Function's port vi_shift value (always 0 on Huntington) */ 9912 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_SHIFT_OFST 8 9913 9914 9915 /***********************************/ 9916 /* MC_CMD_DUMP_VI_STATE 9917 * For CmdClient use. Dump pertinent information on a specific absolute VI. 9918 */ 9919 #define MC_CMD_DUMP_VI_STATE 0x8e 9920 #undef MC_CMD_0x8e_PRIVILEGE_CTG 9921 9922 #define MC_CMD_0x8e_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9923 9924 /* MC_CMD_DUMP_VI_STATE_IN msgrequest */ 9925 #define MC_CMD_DUMP_VI_STATE_IN_LEN 4 9926 /* The VI number to query. */ 9927 #define MC_CMD_DUMP_VI_STATE_IN_VI_NUMBER_OFST 0 9928 9929 /* MC_CMD_DUMP_VI_STATE_OUT msgresponse */ 9930 #define MC_CMD_DUMP_VI_STATE_OUT_LEN 96 9931 /* The PF part of the function owning this VI. */ 9932 #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_OFST 0 9933 #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_LEN 2 9934 /* The VF part of the function owning this VI. */ 9935 #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_VF_OFST 2 9936 #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_VF_LEN 2 9937 /* Base of VIs allocated to this function. */ 9938 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_BASE_OFST 4 9939 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_BASE_LEN 2 9940 /* Count of VIs allocated to the owner function. */ 9941 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_COUNT_OFST 6 9942 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_COUNT_LEN 2 9943 /* Base interrupt vector allocated to this function. */ 9944 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_BASE_OFST 8 9945 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_BASE_LEN 2 9946 /* Number of interrupt vectors allocated to this function. */ 9947 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_COUNT_OFST 10 9948 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_COUNT_LEN 2 9949 /* Raw evq ptr table data. */ 9950 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_OFST 12 9951 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LEN 8 9952 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LO_OFST 12 9953 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_HI_OFST 16 9954 /* Raw evq timer table data. */ 9955 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_OFST 20 9956 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LEN 8 9957 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LO_OFST 20 9958 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_HI_OFST 24 9959 /* Combined metadata field. */ 9960 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_OFST 28 9961 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_LBN 0 9962 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_WIDTH 16 9963 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_LBN 16 9964 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_WIDTH 8 9965 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_LBN 24 9966 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_WIDTH 8 9967 /* TXDPCPU raw table data for queue. */ 9968 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_OFST 32 9969 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LEN 8 9970 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LO_OFST 32 9971 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_HI_OFST 36 9972 /* TXDPCPU raw table data for queue. */ 9973 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_OFST 40 9974 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LEN 8 9975 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LO_OFST 40 9976 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_HI_OFST 44 9977 /* TXDPCPU raw table data for queue. */ 9978 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_OFST 48 9979 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LEN 8 9980 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LO_OFST 48 9981 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_HI_OFST 52 9982 /* Combined metadata field. */ 9983 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_OFST 56 9984 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LEN 8 9985 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LO_OFST 56 9986 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_HI_OFST 60 9987 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_LBN 0 9988 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_WIDTH 16 9989 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_LBN 16 9990 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_WIDTH 8 9991 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_LBN 24 9992 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_WIDTH 8 9993 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_LBN 32 9994 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_WIDTH 8 9995 #define MC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_LBN 40 9996 #define MC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_WIDTH 24 9997 /* RXDPCPU raw table data for queue. */ 9998 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_OFST 64 9999 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LEN 8 10000 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LO_OFST 64 10001 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_HI_OFST 68 10002 /* RXDPCPU raw table data for queue. */ 10003 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_OFST 72 10004 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LEN 8 10005 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LO_OFST 72 10006 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_HI_OFST 76 10007 /* Reserved, currently 0. */ 10008 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_OFST 80 10009 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LEN 8 10010 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LO_OFST 80 10011 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_HI_OFST 84 10012 /* Combined metadata field. */ 10013 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_OFST 88 10014 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LEN 8 10015 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LO_OFST 88 10016 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_HI_OFST 92 10017 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_LBN 0 10018 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_WIDTH 16 10019 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_LBN 16 10020 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_WIDTH 8 10021 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_LBN 24 10022 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_WIDTH 8 10023 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_LBN 32 10024 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_WIDTH 8 10025 10026 10027 /***********************************/ 10028 /* MC_CMD_ALLOC_PIOBUF 10029 * Allocate a push I/O buffer for later use with a tx queue. 10030 */ 10031 #define MC_CMD_ALLOC_PIOBUF 0x8f 10032 #undef MC_CMD_0x8f_PRIVILEGE_CTG 10033 10034 #define MC_CMD_0x8f_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 10035 10036 /* MC_CMD_ALLOC_PIOBUF_IN msgrequest */ 10037 #define MC_CMD_ALLOC_PIOBUF_IN_LEN 0 10038 10039 /* MC_CMD_ALLOC_PIOBUF_OUT msgresponse */ 10040 #define MC_CMD_ALLOC_PIOBUF_OUT_LEN 4 10041 /* Handle for allocated push I/O buffer. */ 10042 #define MC_CMD_ALLOC_PIOBUF_OUT_PIOBUF_HANDLE_OFST 0 10043 10044 10045 /***********************************/ 10046 /* MC_CMD_FREE_PIOBUF 10047 * Free a push I/O buffer. 10048 */ 10049 #define MC_CMD_FREE_PIOBUF 0x90 10050 #undef MC_CMD_0x90_PRIVILEGE_CTG 10051 10052 #define MC_CMD_0x90_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 10053 10054 /* MC_CMD_FREE_PIOBUF_IN msgrequest */ 10055 #define MC_CMD_FREE_PIOBUF_IN_LEN 4 10056 /* Handle for allocated push I/O buffer. */ 10057 #define MC_CMD_FREE_PIOBUF_IN_PIOBUF_HANDLE_OFST 0 10058 10059 /* MC_CMD_FREE_PIOBUF_OUT msgresponse */ 10060 #define MC_CMD_FREE_PIOBUF_OUT_LEN 0 10061 10062 10063 /***********************************/ 10064 /* MC_CMD_GET_VI_TLP_PROCESSING 10065 * Get TLP steering and ordering information for a VI. 10066 */ 10067 #define MC_CMD_GET_VI_TLP_PROCESSING 0xb0 10068 #undef MC_CMD_0xb0_PRIVILEGE_CTG 10069 10070 #define MC_CMD_0xb0_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10071 10072 /* MC_CMD_GET_VI_TLP_PROCESSING_IN msgrequest */ 10073 #define MC_CMD_GET_VI_TLP_PROCESSING_IN_LEN 4 10074 /* VI number to get information for. */ 10075 #define MC_CMD_GET_VI_TLP_PROCESSING_IN_INSTANCE_OFST 0 10076 10077 /* MC_CMD_GET_VI_TLP_PROCESSING_OUT msgresponse */ 10078 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_LEN 4 10079 /* Transaction processing steering hint 1 for use with the Rx Queue. */ 10080 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG1_RX_OFST 0 10081 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG1_RX_LEN 1 10082 /* Transaction processing steering hint 2 for use with the Ev Queue. */ 10083 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG2_EV_OFST 1 10084 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG2_EV_LEN 1 10085 /* Use Relaxed ordering model for TLPs on this VI. */ 10086 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_RELAXED_ORDERING_LBN 16 10087 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_RELAXED_ORDERING_WIDTH 1 10088 /* Use ID based ordering for TLPs on this VI. */ 10089 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_ID_BASED_ORDERING_LBN 17 10090 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_ID_BASED_ORDERING_WIDTH 1 10091 /* Set no snoop bit for TLPs on this VI. */ 10092 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_NO_SNOOP_LBN 18 10093 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_NO_SNOOP_WIDTH 1 10094 /* Enable TPH for TLPs on this VI. */ 10095 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_ON_LBN 19 10096 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_ON_WIDTH 1 10097 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_DATA_OFST 0 10098 10099 10100 /***********************************/ 10101 /* MC_CMD_SET_VI_TLP_PROCESSING 10102 * Set TLP steering and ordering information for a VI. 10103 */ 10104 #define MC_CMD_SET_VI_TLP_PROCESSING 0xb1 10105 #undef MC_CMD_0xb1_PRIVILEGE_CTG 10106 10107 #define MC_CMD_0xb1_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10108 10109 /* MC_CMD_SET_VI_TLP_PROCESSING_IN msgrequest */ 10110 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_LEN 8 10111 /* VI number to set information for. */ 10112 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_INSTANCE_OFST 0 10113 /* Transaction processing steering hint 1 for use with the Rx Queue. */ 10114 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG1_RX_OFST 4 10115 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG1_RX_LEN 1 10116 /* Transaction processing steering hint 2 for use with the Ev Queue. */ 10117 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG2_EV_OFST 5 10118 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG2_EV_LEN 1 10119 /* Use Relaxed ordering model for TLPs on this VI. */ 10120 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_RELAXED_ORDERING_LBN 48 10121 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_RELAXED_ORDERING_WIDTH 1 10122 /* Use ID based ordering for TLPs on this VI. */ 10123 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_ID_BASED_ORDERING_LBN 49 10124 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_ID_BASED_ORDERING_WIDTH 1 10125 /* Set the no snoop bit for TLPs on this VI. */ 10126 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_NO_SNOOP_LBN 50 10127 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_NO_SNOOP_WIDTH 1 10128 /* Enable TPH for TLPs on this VI. */ 10129 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_ON_LBN 51 10130 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_ON_WIDTH 1 10131 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_DATA_OFST 4 10132 10133 /* MC_CMD_SET_VI_TLP_PROCESSING_OUT msgresponse */ 10134 #define MC_CMD_SET_VI_TLP_PROCESSING_OUT_LEN 0 10135 10136 10137 /***********************************/ 10138 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS 10139 * Get global PCIe steering and transaction processing configuration. 10140 */ 10141 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS 0xbc 10142 #undef MC_CMD_0xbc_PRIVILEGE_CTG 10143 10144 #define MC_CMD_0xbc_PRIVILEGE_CTG SRIOV_CTG_ADMIN 10145 10146 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN msgrequest */ 10147 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_LEN 4 10148 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_OFST 0 10149 /* enum: MISC. */ 10150 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_MISC 0x0 10151 /* enum: IDO. */ 10152 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_IDO 0x1 10153 /* enum: RO. */ 10154 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_RO 0x2 10155 /* enum: TPH Type. */ 10156 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_TPH_TYPE 0x3 10157 10158 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT msgresponse */ 10159 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_LEN 8 10160 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_GLOBAL_CATEGORY_OFST 0 10161 /* Enum values, see field(s): */ 10162 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN/TLP_GLOBAL_CATEGORY */ 10163 /* Amalgamated TLP info word. */ 10164 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_WORD_OFST 4 10165 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_LBN 0 10166 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_WIDTH 1 10167 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_LBN 1 10168 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_WIDTH 31 10169 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_LBN 0 10170 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_WIDTH 1 10171 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_LBN 1 10172 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_WIDTH 1 10173 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_EV_EN_LBN 2 10174 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_EV_EN_WIDTH 1 10175 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_LBN 3 10176 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_WIDTH 1 10177 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_LBN 4 10178 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_WIDTH 28 10179 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_LBN 0 10180 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_WIDTH 1 10181 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_LBN 1 10182 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_WIDTH 1 10183 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_LBN 2 10184 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_WIDTH 1 10185 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_LBN 3 10186 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_WIDTH 29 10187 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_LBN 0 10188 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_WIDTH 2 10189 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_DL_LBN 2 10190 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_DL_WIDTH 2 10191 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_LBN 4 10192 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_WIDTH 2 10193 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_EV_LBN 6 10194 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_EV_WIDTH 2 10195 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_LBN 8 10196 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_WIDTH 2 10197 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_LBN 9 10198 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_WIDTH 23 10199 10200 10201 /***********************************/ 10202 /* MC_CMD_SET_TLP_PROCESSING_GLOBALS 10203 * Set global PCIe steering and transaction processing configuration. 10204 */ 10205 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS 0xbd 10206 #undef MC_CMD_0xbd_PRIVILEGE_CTG 10207 10208 #define MC_CMD_0xbd_PRIVILEGE_CTG SRIOV_CTG_ADMIN 10209 10210 /* MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN msgrequest */ 10211 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_LEN 8 10212 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_OFST 0 10213 /* Enum values, see field(s): */ 10214 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS/MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN/TLP_GLOBAL_CATEGORY */ 10215 /* Amalgamated TLP info word. */ 10216 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_WORD_OFST 4 10217 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_LBN 0 10218 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_WIDTH 1 10219 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_LBN 0 10220 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_WIDTH 1 10221 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_LBN 1 10222 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_WIDTH 1 10223 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_EV_EN_LBN 2 10224 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_EV_EN_WIDTH 1 10225 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_RX_EN_LBN 3 10226 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_RX_EN_WIDTH 1 10227 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_LBN 0 10228 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_WIDTH 1 10229 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_LBN 1 10230 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_WIDTH 1 10231 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_DL_EN_LBN 2 10232 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_DL_EN_WIDTH 1 10233 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_LBN 0 10234 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_WIDTH 2 10235 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_DL_LBN 2 10236 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_DL_WIDTH 2 10237 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_LBN 4 10238 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_WIDTH 2 10239 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_EV_LBN 6 10240 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_EV_WIDTH 2 10241 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_LBN 8 10242 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_WIDTH 2 10243 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_LBN 10 10244 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_WIDTH 22 10245 10246 /* MC_CMD_SET_TLP_PROCESSING_GLOBALS_OUT msgresponse */ 10247 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_OUT_LEN 0 10248 10249 10250 /***********************************/ 10251 /* MC_CMD_SATELLITE_DOWNLOAD 10252 * Download a new set of images to the satellite CPUs from the host. 10253 */ 10254 #define MC_CMD_SATELLITE_DOWNLOAD 0x91 10255 #undef MC_CMD_0x91_PRIVILEGE_CTG 10256 10257 #define MC_CMD_0x91_PRIVILEGE_CTG SRIOV_CTG_ADMIN 10258 10259 /* MC_CMD_SATELLITE_DOWNLOAD_IN msgrequest: The reset requirements for the CPUs 10260 * are subtle, and so downloads must proceed in a number of phases. 10261 * 10262 * 1) PHASE_RESET with a target of TARGET_ALL and chunk ID/length of 0. 10263 * 10264 * 2) PHASE_IMEMS for each of the IMEM targets (target IDs 0-11). Each download 10265 * may consist of multiple chunks. The final chunk (with CHUNK_ID_LAST) should 10266 * be a checksum (a simple 32-bit sum) of the transferred data. An individual 10267 * download may be aborted using CHUNK_ID_ABORT. 10268 * 10269 * 3) PHASE_VECTORS for each of the vector table targets (target IDs 12-15), 10270 * similar to PHASE_IMEMS. 10271 * 10272 * 4) PHASE_READY with a target of TARGET_ALL and chunk ID/length of 0. 10273 * 10274 * After any error (a requested abort is not considered to be an error) the 10275 * sequence must be restarted from PHASE_RESET. 10276 */ 10277 #define MC_CMD_SATELLITE_DOWNLOAD_IN_LENMIN 20 10278 #define MC_CMD_SATELLITE_DOWNLOAD_IN_LENMAX 252 10279 #define MC_CMD_SATELLITE_DOWNLOAD_IN_LEN(num) (16+4*(num)) 10280 /* Download phase. (Note: the IDLE phase is used internally and is never valid 10281 * in a command from the host.) 10282 */ 10283 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_OFST 0 10284 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_IDLE 0x0 /* enum */ 10285 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_RESET 0x1 /* enum */ 10286 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_IMEMS 0x2 /* enum */ 10287 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_VECTORS 0x3 /* enum */ 10288 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_READY 0x4 /* enum */ 10289 /* Target for download. (These match the blob numbers defined in 10290 * mc_flash_layout.h.) 10291 */ 10292 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_OFST 4 10293 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 10294 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_TEXT 0x0 10295 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 10296 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_TEXT 0x1 10297 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 10298 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDP_TEXT 0x2 10299 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 10300 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDP_TEXT 0x3 10301 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 10302 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_LUT 0x4 10303 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 10304 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_LUT_CFG 0x5 10305 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 10306 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_LUT 0x6 10307 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 10308 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_LUT_CFG 0x7 10309 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 10310 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_PGM 0x8 10311 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 10312 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_SL_PGM 0x9 10313 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 10314 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_PGM 0xa 10315 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 10316 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_SL_PGM 0xb 10317 /* enum: Valid in phase 3 (PHASE_VECTORS) only */ 10318 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_VTBL0 0xc 10319 /* enum: Valid in phase 3 (PHASE_VECTORS) only */ 10320 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_VTBL0 0xd 10321 /* enum: Valid in phase 3 (PHASE_VECTORS) only */ 10322 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_VTBL1 0xe 10323 /* enum: Valid in phase 3 (PHASE_VECTORS) only */ 10324 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_VTBL1 0xf 10325 /* enum: Valid in phases 1 (PHASE_RESET) and 4 (PHASE_READY) only */ 10326 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_ALL 0xffffffff 10327 /* Chunk ID, or CHUNK_ID_LAST or CHUNK_ID_ABORT */ 10328 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_OFST 8 10329 /* enum: Last chunk, containing checksum rather than data */ 10330 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_LAST 0xffffffff 10331 /* enum: Abort download of this item */ 10332 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_ABORT 0xfffffffe 10333 /* Length of this chunk in bytes */ 10334 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_LEN_OFST 12 10335 /* Data for this chunk */ 10336 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_OFST 16 10337 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_LEN 4 10338 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_MINNUM 1 10339 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_MAXNUM 59 10340 10341 /* MC_CMD_SATELLITE_DOWNLOAD_OUT msgresponse */ 10342 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_LEN 8 10343 /* Same as MC_CMD_ERR field, but included as 0 in success cases */ 10344 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_RESULT_OFST 0 10345 /* Extra status information */ 10346 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_INFO_OFST 4 10347 /* enum: Code download OK, completed. */ 10348 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_COMPLETE 0x0 10349 /* enum: Code download aborted as requested. */ 10350 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_ABORTED 0x1 10351 /* enum: Code download OK so far, send next chunk. */ 10352 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_NEXT_CHUNK 0x2 10353 /* enum: Download phases out of sequence */ 10354 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_PHASE 0x100 10355 /* enum: Bad target for this phase */ 10356 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_TARGET 0x101 10357 /* enum: Chunk ID out of sequence */ 10358 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHUNK_ID 0x200 10359 /* enum: Chunk length zero or too large */ 10360 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHUNK_LEN 0x201 10361 /* enum: Checksum was incorrect */ 10362 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHECKSUM 0x300 10363 10364 10365 /***********************************/ 10366 /* MC_CMD_GET_CAPABILITIES 10367 * Get device capabilities. 10368 * 10369 * This is supplementary to the MC_CMD_GET_BOARD_CFG command, and intended to 10370 * reference inherent device capabilities as opposed to current NVRAM config. 10371 */ 10372 #define MC_CMD_GET_CAPABILITIES 0xbe 10373 #undef MC_CMD_0xbe_PRIVILEGE_CTG 10374 10375 #define MC_CMD_0xbe_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10376 10377 /* MC_CMD_GET_CAPABILITIES_IN msgrequest */ 10378 #define MC_CMD_GET_CAPABILITIES_IN_LEN 0 10379 10380 /* MC_CMD_GET_CAPABILITIES_OUT msgresponse */ 10381 #define MC_CMD_GET_CAPABILITIES_OUT_LEN 20 10382 /* First word of flags. */ 10383 #define MC_CMD_GET_CAPABILITIES_OUT_FLAGS1_OFST 0 10384 #define MC_CMD_GET_CAPABILITIES_OUT_VPORT_RECONFIGURE_LBN 3 10385 #define MC_CMD_GET_CAPABILITIES_OUT_VPORT_RECONFIGURE_WIDTH 1 10386 #define MC_CMD_GET_CAPABILITIES_OUT_TX_STRIPING_LBN 4 10387 #define MC_CMD_GET_CAPABILITIES_OUT_TX_STRIPING_WIDTH 1 10388 #define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_LBN 5 10389 #define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_WIDTH 1 10390 #define MC_CMD_GET_CAPABILITIES_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6 10391 #define MC_CMD_GET_CAPABILITIES_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1 10392 #define MC_CMD_GET_CAPABILITIES_OUT_DRV_ATTACH_PREBOOT_LBN 7 10393 #define MC_CMD_GET_CAPABILITIES_OUT_DRV_ATTACH_PREBOOT_WIDTH 1 10394 #define MC_CMD_GET_CAPABILITIES_OUT_RX_FORCE_EVENT_MERGING_LBN 8 10395 #define MC_CMD_GET_CAPABILITIES_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1 10396 #define MC_CMD_GET_CAPABILITIES_OUT_SET_MAC_ENHANCED_LBN 9 10397 #define MC_CMD_GET_CAPABILITIES_OUT_SET_MAC_ENHANCED_WIDTH 1 10398 #define MC_CMD_GET_CAPABILITIES_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10 10399 #define MC_CMD_GET_CAPABILITIES_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1 10400 #define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11 10401 #define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1 10402 #define MC_CMD_GET_CAPABILITIES_OUT_TX_MAC_SECURITY_FILTERING_LBN 12 10403 #define MC_CMD_GET_CAPABILITIES_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1 10404 #define MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_LBN 13 10405 #define MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_WIDTH 1 10406 #define MC_CMD_GET_CAPABILITIES_OUT_QBB_LBN 14 10407 #define MC_CMD_GET_CAPABILITIES_OUT_QBB_WIDTH 1 10408 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15 10409 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1 10410 #define MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_LBN 16 10411 #define MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_WIDTH 1 10412 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_LBN 17 10413 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_WIDTH 1 10414 #define MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_LBN 18 10415 #define MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_WIDTH 1 10416 #define MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_LBN 19 10417 #define MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_WIDTH 1 10418 #define MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_LBN 20 10419 #define MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_WIDTH 1 10420 #define MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN 21 10421 #define MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_WIDTH 1 10422 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_LBN 22 10423 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_WIDTH 1 10424 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN 23 10425 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_WIDTH 1 10426 #define MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_LBN 24 10427 #define MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_WIDTH 1 10428 #define MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN 25 10429 #define MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_WIDTH 1 10430 #define MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_LBN 26 10431 #define MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_WIDTH 1 10432 #define MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN 27 10433 #define MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1 10434 #define MC_CMD_GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER_LBN 28 10435 #define MC_CMD_GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER_WIDTH 1 10436 #define MC_CMD_GET_CAPABILITIES_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29 10437 #define MC_CMD_GET_CAPABILITIES_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1 10438 #define MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN 30 10439 #define MC_CMD_GET_CAPABILITIES_OUT_EVB_WIDTH 1 10440 #define MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN 31 10441 #define MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_WIDTH 1 10442 /* RxDPCPU firmware id. */ 10443 #define MC_CMD_GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID_OFST 4 10444 #define MC_CMD_GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID_LEN 2 10445 /* enum: Standard RXDP firmware */ 10446 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP 0x0 10447 /* enum: Low latency RXDP firmware */ 10448 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_LOW_LATENCY 0x1 10449 /* enum: Packed stream RXDP firmware */ 10450 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_PACKED_STREAM 0x2 10451 /* enum: BIST RXDP firmware */ 10452 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_BIST 0x10a 10453 /* enum: RXDP Test firmware image 1 */ 10454 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101 10455 /* enum: RXDP Test firmware image 2 */ 10456 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102 10457 /* enum: RXDP Test firmware image 3 */ 10458 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103 10459 /* enum: RXDP Test firmware image 4 */ 10460 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104 10461 /* enum: RXDP Test firmware image 5 */ 10462 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_BACKPRESSURE 0x105 10463 /* enum: RXDP Test firmware image 6 */ 10464 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106 10465 /* enum: RXDP Test firmware image 7 */ 10466 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107 10467 /* enum: RXDP Test firmware image 8 */ 10468 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_DISABLE_DL 0x108 10469 /* enum: RXDP Test firmware image 9 */ 10470 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b 10471 /* TxDPCPU firmware id. */ 10472 #define MC_CMD_GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID_OFST 6 10473 #define MC_CMD_GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID_LEN 2 10474 /* enum: Standard TXDP firmware */ 10475 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP 0x0 10476 /* enum: Low latency TXDP firmware */ 10477 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_LOW_LATENCY 0x1 10478 /* enum: High packet rate TXDP firmware */ 10479 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_HIGH_PACKET_RATE 0x3 10480 /* enum: BIST TXDP firmware */ 10481 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_BIST 0x12d 10482 /* enum: TXDP Test firmware image 1 */ 10483 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_TSO_EDIT 0x101 10484 /* enum: TXDP Test firmware image 2 */ 10485 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102 10486 /* enum: TXDP CSR bus test firmware */ 10487 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_CSR 0x103 10488 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_OFST 8 10489 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_LEN 2 10490 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_LBN 0 10491 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_WIDTH 12 10492 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_LBN 12 10493 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4 10494 /* enum: reserved value - do not use (may indicate alternative interpretation 10495 * of REV field in future) 10496 */ 10497 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_RESERVED 0x0 10498 /* enum: Trivial RX PD firmware for early Huntington development (Huntington 10499 * development only) 10500 */ 10501 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1 10502 /* enum: RX PD firmware with approximately Siena-compatible behaviour 10503 * (Huntington development only) 10504 */ 10505 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2 10506 /* enum: Full featured RX PD production firmware */ 10507 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3 10508 /* enum: (deprecated original name for the FULL_FEATURED variant) */ 10509 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_VSWITCH 0x3 10510 /* enum: siena_compat variant RX PD firmware using PM rather than MAC 10511 * (Huntington development only) 10512 */ 10513 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 10514 /* enum: Low latency RX PD production firmware */ 10515 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5 10516 /* enum: Packed stream RX PD production firmware */ 10517 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6 10518 /* enum: RX PD firmware handling layer 2 only for high packet rate performance 10519 * tests (Medford development only) 10520 */ 10521 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7 10522 /* enum: Rules engine RX PD production firmware */ 10523 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8 10524 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 10525 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 10526 /* enum: RX PD firmware parsing but not filtering network overlay tunnel 10527 * encapsulations (Medford development only) 10528 */ 10529 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf 10530 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_OFST 10 10531 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_LEN 2 10532 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_LBN 0 10533 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_WIDTH 12 10534 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_LBN 12 10535 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4 10536 /* enum: reserved value - do not use (may indicate alternative interpretation 10537 * of REV field in future) 10538 */ 10539 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_RESERVED 0x0 10540 /* enum: Trivial TX PD firmware for early Huntington development (Huntington 10541 * development only) 10542 */ 10543 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1 10544 /* enum: TX PD firmware with approximately Siena-compatible behaviour 10545 * (Huntington development only) 10546 */ 10547 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2 10548 /* enum: Full featured TX PD production firmware */ 10549 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3 10550 /* enum: (deprecated original name for the FULL_FEATURED variant) */ 10551 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_VSWITCH 0x3 10552 /* enum: siena_compat variant TX PD firmware using PM rather than MAC 10553 * (Huntington development only) 10554 */ 10555 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 10556 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */ 10557 /* enum: TX PD firmware handling layer 2 only for high packet rate performance 10558 * tests (Medford development only) 10559 */ 10560 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7 10561 /* enum: Rules engine TX PD production firmware */ 10562 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8 10563 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 10564 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 10565 /* Hardware capabilities of NIC */ 10566 #define MC_CMD_GET_CAPABILITIES_OUT_HW_CAPABILITIES_OFST 12 10567 /* Licensed capabilities */ 10568 #define MC_CMD_GET_CAPABILITIES_OUT_LICENSE_CAPABILITIES_OFST 16 10569 10570 /* MC_CMD_GET_CAPABILITIES_V2_IN msgrequest */ 10571 #define MC_CMD_GET_CAPABILITIES_V2_IN_LEN 0 10572 10573 /* MC_CMD_GET_CAPABILITIES_V2_OUT msgresponse */ 10574 #define MC_CMD_GET_CAPABILITIES_V2_OUT_LEN 72 10575 /* First word of flags. */ 10576 #define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS1_OFST 0 10577 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VPORT_RECONFIGURE_LBN 3 10578 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VPORT_RECONFIGURE_WIDTH 1 10579 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_STRIPING_LBN 4 10580 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_STRIPING_WIDTH 1 10581 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_QUERY_LBN 5 10582 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_QUERY_WIDTH 1 10583 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6 10584 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1 10585 #define MC_CMD_GET_CAPABILITIES_V2_OUT_DRV_ATTACH_PREBOOT_LBN 7 10586 #define MC_CMD_GET_CAPABILITIES_V2_OUT_DRV_ATTACH_PREBOOT_WIDTH 1 10587 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_FORCE_EVENT_MERGING_LBN 8 10588 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1 10589 #define MC_CMD_GET_CAPABILITIES_V2_OUT_SET_MAC_ENHANCED_LBN 9 10590 #define MC_CMD_GET_CAPABILITIES_V2_OUT_SET_MAC_ENHANCED_WIDTH 1 10591 #define MC_CMD_GET_CAPABILITIES_V2_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10 10592 #define MC_CMD_GET_CAPABILITIES_V2_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1 10593 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11 10594 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1 10595 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_SECURITY_FILTERING_LBN 12 10596 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1 10597 #define MC_CMD_GET_CAPABILITIES_V2_OUT_ADDITIONAL_RSS_MODES_LBN 13 10598 #define MC_CMD_GET_CAPABILITIES_V2_OUT_ADDITIONAL_RSS_MODES_WIDTH 1 10599 #define MC_CMD_GET_CAPABILITIES_V2_OUT_QBB_LBN 14 10600 #define MC_CMD_GET_CAPABILITIES_V2_OUT_QBB_WIDTH 1 10601 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15 10602 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1 10603 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_RSS_LIMITED_LBN 16 10604 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_RSS_LIMITED_WIDTH 1 10605 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_LBN 17 10606 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_WIDTH 1 10607 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_INCLUDE_FCS_LBN 18 10608 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_INCLUDE_FCS_WIDTH 1 10609 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VLAN_INSERTION_LBN 19 10610 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VLAN_INSERTION_WIDTH 1 10611 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_VLAN_STRIPPING_LBN 20 10612 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_VLAN_STRIPPING_WIDTH 1 10613 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_LBN 21 10614 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_WIDTH 1 10615 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_0_LBN 22 10616 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_0_WIDTH 1 10617 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_14_LBN 23 10618 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_14_WIDTH 1 10619 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_TIMESTAMP_LBN 24 10620 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_TIMESTAMP_WIDTH 1 10621 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_BATCHING_LBN 25 10622 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_BATCHING_WIDTH 1 10623 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MCAST_FILTER_CHAINING_LBN 26 10624 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MCAST_FILTER_CHAINING_WIDTH 1 10625 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PM_AND_RXDP_COUNTERS_LBN 27 10626 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1 10627 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DISABLE_SCATTER_LBN 28 10628 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DISABLE_SCATTER_WIDTH 1 10629 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29 10630 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1 10631 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_LBN 30 10632 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_WIDTH 1 10633 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VXLAN_NVGRE_LBN 31 10634 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VXLAN_NVGRE_WIDTH 1 10635 /* RxDPCPU firmware id. */ 10636 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DPCPU_FW_ID_OFST 4 10637 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DPCPU_FW_ID_LEN 2 10638 /* enum: Standard RXDP firmware */ 10639 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP 0x0 10640 /* enum: Low latency RXDP firmware */ 10641 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_LOW_LATENCY 0x1 10642 /* enum: Packed stream RXDP firmware */ 10643 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_PACKED_STREAM 0x2 10644 /* enum: BIST RXDP firmware */ 10645 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_BIST 0x10a 10646 /* enum: RXDP Test firmware image 1 */ 10647 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101 10648 /* enum: RXDP Test firmware image 2 */ 10649 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102 10650 /* enum: RXDP Test firmware image 3 */ 10651 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103 10652 /* enum: RXDP Test firmware image 4 */ 10653 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104 10654 /* enum: RXDP Test firmware image 5 */ 10655 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_BACKPRESSURE 0x105 10656 /* enum: RXDP Test firmware image 6 */ 10657 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106 10658 /* enum: RXDP Test firmware image 7 */ 10659 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107 10660 /* enum: RXDP Test firmware image 8 */ 10661 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_DISABLE_DL 0x108 10662 /* enum: RXDP Test firmware image 9 */ 10663 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b 10664 /* TxDPCPU firmware id. */ 10665 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DPCPU_FW_ID_OFST 6 10666 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DPCPU_FW_ID_LEN 2 10667 /* enum: Standard TXDP firmware */ 10668 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP 0x0 10669 /* enum: Low latency TXDP firmware */ 10670 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_LOW_LATENCY 0x1 10671 /* enum: High packet rate TXDP firmware */ 10672 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_HIGH_PACKET_RATE 0x3 10673 /* enum: BIST TXDP firmware */ 10674 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_BIST 0x12d 10675 /* enum: TXDP Test firmware image 1 */ 10676 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_TSO_EDIT 0x101 10677 /* enum: TXDP Test firmware image 2 */ 10678 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102 10679 /* enum: TXDP CSR bus test firmware */ 10680 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_CSR 0x103 10681 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_OFST 8 10682 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_LEN 2 10683 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_REV_LBN 0 10684 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_REV_WIDTH 12 10685 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_TYPE_LBN 12 10686 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4 10687 /* enum: reserved value - do not use (may indicate alternative interpretation 10688 * of REV field in future) 10689 */ 10690 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_RESERVED 0x0 10691 /* enum: Trivial RX PD firmware for early Huntington development (Huntington 10692 * development only) 10693 */ 10694 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1 10695 /* enum: RX PD firmware with approximately Siena-compatible behaviour 10696 * (Huntington development only) 10697 */ 10698 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2 10699 /* enum: Full featured RX PD production firmware */ 10700 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3 10701 /* enum: (deprecated original name for the FULL_FEATURED variant) */ 10702 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_VSWITCH 0x3 10703 /* enum: siena_compat variant RX PD firmware using PM rather than MAC 10704 * (Huntington development only) 10705 */ 10706 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 10707 /* enum: Low latency RX PD production firmware */ 10708 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5 10709 /* enum: Packed stream RX PD production firmware */ 10710 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6 10711 /* enum: RX PD firmware handling layer 2 only for high packet rate performance 10712 * tests (Medford development only) 10713 */ 10714 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7 10715 /* enum: Rules engine RX PD production firmware */ 10716 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8 10717 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 10718 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 10719 /* enum: RX PD firmware parsing but not filtering network overlay tunnel 10720 * encapsulations (Medford development only) 10721 */ 10722 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf 10723 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_OFST 10 10724 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_LEN 2 10725 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_REV_LBN 0 10726 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_REV_WIDTH 12 10727 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_TYPE_LBN 12 10728 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4 10729 /* enum: reserved value - do not use (may indicate alternative interpretation 10730 * of REV field in future) 10731 */ 10732 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_RESERVED 0x0 10733 /* enum: Trivial TX PD firmware for early Huntington development (Huntington 10734 * development only) 10735 */ 10736 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1 10737 /* enum: TX PD firmware with approximately Siena-compatible behaviour 10738 * (Huntington development only) 10739 */ 10740 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2 10741 /* enum: Full featured TX PD production firmware */ 10742 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3 10743 /* enum: (deprecated original name for the FULL_FEATURED variant) */ 10744 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_VSWITCH 0x3 10745 /* enum: siena_compat variant TX PD firmware using PM rather than MAC 10746 * (Huntington development only) 10747 */ 10748 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 10749 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */ 10750 /* enum: TX PD firmware handling layer 2 only for high packet rate performance 10751 * tests (Medford development only) 10752 */ 10753 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7 10754 /* enum: Rules engine TX PD production firmware */ 10755 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8 10756 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 10757 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 10758 /* Hardware capabilities of NIC */ 10759 #define MC_CMD_GET_CAPABILITIES_V2_OUT_HW_CAPABILITIES_OFST 12 10760 /* Licensed capabilities */ 10761 #define MC_CMD_GET_CAPABILITIES_V2_OUT_LICENSE_CAPABILITIES_OFST 16 10762 /* Second word of flags. Not present on older firmware (check the length). */ 10763 #define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS2_OFST 20 10764 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN 0 10765 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_WIDTH 1 10766 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_ENCAP_LBN 1 10767 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_ENCAP_WIDTH 1 10768 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVQ_TIMER_CTRL_LBN 2 10769 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVQ_TIMER_CTRL_WIDTH 1 10770 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVENT_CUT_THROUGH_LBN 3 10771 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVENT_CUT_THROUGH_WIDTH 1 10772 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_CUT_THROUGH_LBN 4 10773 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_CUT_THROUGH_WIDTH 1 10774 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VFIFO_ULL_MODE_LBN 5 10775 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VFIFO_ULL_MODE_WIDTH 1 10776 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6 10777 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1 10778 #define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_LBN 7 10779 #define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_WIDTH 1 10780 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_TIMESTAMPING_LBN 8 10781 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_TIMESTAMPING_WIDTH 1 10782 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TIMESTAMP_LBN 9 10783 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TIMESTAMP_WIDTH 1 10784 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_SNIFF_LBN 10 10785 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_SNIFF_WIDTH 1 10786 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_SNIFF_LBN 11 10787 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_SNIFF_WIDTH 1 10788 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12 10789 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1 10790 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_BACKGROUND_LBN 13 10791 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_BACKGROUND_WIDTH 1 10792 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_DB_RETURN_LBN 14 10793 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_DB_RETURN_WIDTH 1 10794 /* Number of FATSOv2 contexts per datapath supported by this NIC. Not present 10795 * on older firmware (check the length). 10796 */ 10797 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24 10798 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2 10799 /* One byte per PF containing the number of the external port assigned to this 10800 * PF, indexed by PF number. Special values indicate that a PF is either not 10801 * present or not assigned. 10802 */ 10803 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26 10804 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1 10805 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16 10806 /* enum: The caller is not permitted to access information on this PF. */ 10807 #define MC_CMD_GET_CAPABILITIES_V2_OUT_ACCESS_NOT_PERMITTED 0xff 10808 /* enum: PF does not exist. */ 10809 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_PRESENT 0xfe 10810 /* enum: PF does exist but is not assigned to any external port. */ 10811 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_ASSIGNED 0xfd 10812 /* enum: This value indicates that PF is assigned, but it cannot be expressed 10813 * in this field. It is intended for a possible future situation where a more 10814 * complex scheme of PFs to ports mapping is being used. The future driver 10815 * should look for a new field supporting the new scheme. The current/old 10816 * driver should treat this value as PF_NOT_ASSIGNED. 10817 */ 10818 #define MC_CMD_GET_CAPABILITIES_V2_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc 10819 /* One byte per PF containing the number of its VFs, indexed by PF number. A 10820 * special value indicates that a PF is not present. 10821 */ 10822 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VFS_PER_PF_OFST 42 10823 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VFS_PER_PF_LEN 1 10824 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VFS_PER_PF_NUM 16 10825 /* enum: The caller is not permitted to access information on this PF. */ 10826 /* MC_CMD_GET_CAPABILITIES_V2_OUT_ACCESS_NOT_PERMITTED 0xff */ 10827 /* enum: PF does not exist. */ 10828 /* MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_PRESENT 0xfe */ 10829 /* Number of VIs available for each external port */ 10830 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_OFST 58 10831 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_LEN 2 10832 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_NUM 4 10833 /* Size of RX descriptor cache expressed as binary logarithm The actual size 10834 * equals (2 ^ RX_DESC_CACHE_SIZE) 10835 */ 10836 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DESC_CACHE_SIZE_OFST 66 10837 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DESC_CACHE_SIZE_LEN 1 10838 /* Size of TX descriptor cache expressed as binary logarithm The actual size 10839 * equals (2 ^ TX_DESC_CACHE_SIZE) 10840 */ 10841 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DESC_CACHE_SIZE_OFST 67 10842 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DESC_CACHE_SIZE_LEN 1 10843 /* Total number of available PIO buffers */ 10844 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_PIO_BUFFS_OFST 68 10845 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_PIO_BUFFS_LEN 2 10846 /* Size of a single PIO buffer */ 10847 #define MC_CMD_GET_CAPABILITIES_V2_OUT_SIZE_PIO_BUFF_OFST 70 10848 #define MC_CMD_GET_CAPABILITIES_V2_OUT_SIZE_PIO_BUFF_LEN 2 10849 10850 /* MC_CMD_GET_CAPABILITIES_V3_OUT msgresponse */ 10851 #define MC_CMD_GET_CAPABILITIES_V3_OUT_LEN 76 10852 /* First word of flags. */ 10853 #define MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS1_OFST 0 10854 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VPORT_RECONFIGURE_LBN 3 10855 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VPORT_RECONFIGURE_WIDTH 1 10856 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_STRIPING_LBN 4 10857 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_STRIPING_WIDTH 1 10858 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_QUERY_LBN 5 10859 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_QUERY_WIDTH 1 10860 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6 10861 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1 10862 #define MC_CMD_GET_CAPABILITIES_V3_OUT_DRV_ATTACH_PREBOOT_LBN 7 10863 #define MC_CMD_GET_CAPABILITIES_V3_OUT_DRV_ATTACH_PREBOOT_WIDTH 1 10864 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_FORCE_EVENT_MERGING_LBN 8 10865 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1 10866 #define MC_CMD_GET_CAPABILITIES_V3_OUT_SET_MAC_ENHANCED_LBN 9 10867 #define MC_CMD_GET_CAPABILITIES_V3_OUT_SET_MAC_ENHANCED_WIDTH 1 10868 #define MC_CMD_GET_CAPABILITIES_V3_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10 10869 #define MC_CMD_GET_CAPABILITIES_V3_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1 10870 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11 10871 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1 10872 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_SECURITY_FILTERING_LBN 12 10873 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1 10874 #define MC_CMD_GET_CAPABILITIES_V3_OUT_ADDITIONAL_RSS_MODES_LBN 13 10875 #define MC_CMD_GET_CAPABILITIES_V3_OUT_ADDITIONAL_RSS_MODES_WIDTH 1 10876 #define MC_CMD_GET_CAPABILITIES_V3_OUT_QBB_LBN 14 10877 #define MC_CMD_GET_CAPABILITIES_V3_OUT_QBB_WIDTH 1 10878 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15 10879 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1 10880 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_RSS_LIMITED_LBN 16 10881 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_RSS_LIMITED_WIDTH 1 10882 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_LBN 17 10883 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_WIDTH 1 10884 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_INCLUDE_FCS_LBN 18 10885 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_INCLUDE_FCS_WIDTH 1 10886 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VLAN_INSERTION_LBN 19 10887 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VLAN_INSERTION_WIDTH 1 10888 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_VLAN_STRIPPING_LBN 20 10889 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_VLAN_STRIPPING_WIDTH 1 10890 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_LBN 21 10891 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_WIDTH 1 10892 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_0_LBN 22 10893 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_0_WIDTH 1 10894 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_14_LBN 23 10895 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_14_WIDTH 1 10896 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_TIMESTAMP_LBN 24 10897 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_TIMESTAMP_WIDTH 1 10898 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_BATCHING_LBN 25 10899 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_BATCHING_WIDTH 1 10900 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MCAST_FILTER_CHAINING_LBN 26 10901 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MCAST_FILTER_CHAINING_WIDTH 1 10902 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PM_AND_RXDP_COUNTERS_LBN 27 10903 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1 10904 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DISABLE_SCATTER_LBN 28 10905 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DISABLE_SCATTER_WIDTH 1 10906 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29 10907 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1 10908 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_LBN 30 10909 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_WIDTH 1 10910 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VXLAN_NVGRE_LBN 31 10911 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VXLAN_NVGRE_WIDTH 1 10912 /* RxDPCPU firmware id. */ 10913 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DPCPU_FW_ID_OFST 4 10914 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DPCPU_FW_ID_LEN 2 10915 /* enum: Standard RXDP firmware */ 10916 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP 0x0 10917 /* enum: Low latency RXDP firmware */ 10918 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_LOW_LATENCY 0x1 10919 /* enum: Packed stream RXDP firmware */ 10920 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_PACKED_STREAM 0x2 10921 /* enum: BIST RXDP firmware */ 10922 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_BIST 0x10a 10923 /* enum: RXDP Test firmware image 1 */ 10924 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101 10925 /* enum: RXDP Test firmware image 2 */ 10926 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102 10927 /* enum: RXDP Test firmware image 3 */ 10928 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103 10929 /* enum: RXDP Test firmware image 4 */ 10930 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104 10931 /* enum: RXDP Test firmware image 5 */ 10932 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_BACKPRESSURE 0x105 10933 /* enum: RXDP Test firmware image 6 */ 10934 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106 10935 /* enum: RXDP Test firmware image 7 */ 10936 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107 10937 /* enum: RXDP Test firmware image 8 */ 10938 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_DISABLE_DL 0x108 10939 /* enum: RXDP Test firmware image 9 */ 10940 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b 10941 /* TxDPCPU firmware id. */ 10942 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_DPCPU_FW_ID_OFST 6 10943 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_DPCPU_FW_ID_LEN 2 10944 /* enum: Standard TXDP firmware */ 10945 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP 0x0 10946 /* enum: Low latency TXDP firmware */ 10947 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_LOW_LATENCY 0x1 10948 /* enum: High packet rate TXDP firmware */ 10949 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_HIGH_PACKET_RATE 0x3 10950 /* enum: BIST TXDP firmware */ 10951 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_BIST 0x12d 10952 /* enum: TXDP Test firmware image 1 */ 10953 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_TSO_EDIT 0x101 10954 /* enum: TXDP Test firmware image 2 */ 10955 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102 10956 /* enum: TXDP CSR bus test firmware */ 10957 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_CSR 0x103 10958 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_OFST 8 10959 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_LEN 2 10960 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_REV_LBN 0 10961 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_REV_WIDTH 12 10962 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_TYPE_LBN 12 10963 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4 10964 /* enum: reserved value - do not use (may indicate alternative interpretation 10965 * of REV field in future) 10966 */ 10967 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_RESERVED 0x0 10968 /* enum: Trivial RX PD firmware for early Huntington development (Huntington 10969 * development only) 10970 */ 10971 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1 10972 /* enum: RX PD firmware with approximately Siena-compatible behaviour 10973 * (Huntington development only) 10974 */ 10975 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2 10976 /* enum: Full featured RX PD production firmware */ 10977 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3 10978 /* enum: (deprecated original name for the FULL_FEATURED variant) */ 10979 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_VSWITCH 0x3 10980 /* enum: siena_compat variant RX PD firmware using PM rather than MAC 10981 * (Huntington development only) 10982 */ 10983 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 10984 /* enum: Low latency RX PD production firmware */ 10985 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5 10986 /* enum: Packed stream RX PD production firmware */ 10987 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6 10988 /* enum: RX PD firmware handling layer 2 only for high packet rate performance 10989 * tests (Medford development only) 10990 */ 10991 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7 10992 /* enum: Rules engine RX PD production firmware */ 10993 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8 10994 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 10995 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 10996 /* enum: RX PD firmware parsing but not filtering network overlay tunnel 10997 * encapsulations (Medford development only) 10998 */ 10999 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf 11000 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_OFST 10 11001 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_LEN 2 11002 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_REV_LBN 0 11003 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_REV_WIDTH 12 11004 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_TYPE_LBN 12 11005 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4 11006 /* enum: reserved value - do not use (may indicate alternative interpretation 11007 * of REV field in future) 11008 */ 11009 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_RESERVED 0x0 11010 /* enum: Trivial TX PD firmware for early Huntington development (Huntington 11011 * development only) 11012 */ 11013 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1 11014 /* enum: TX PD firmware with approximately Siena-compatible behaviour 11015 * (Huntington development only) 11016 */ 11017 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2 11018 /* enum: Full featured TX PD production firmware */ 11019 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3 11020 /* enum: (deprecated original name for the FULL_FEATURED variant) */ 11021 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_VSWITCH 0x3 11022 /* enum: siena_compat variant TX PD firmware using PM rather than MAC 11023 * (Huntington development only) 11024 */ 11025 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 11026 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */ 11027 /* enum: TX PD firmware handling layer 2 only for high packet rate performance 11028 * tests (Medford development only) 11029 */ 11030 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7 11031 /* enum: Rules engine TX PD production firmware */ 11032 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8 11033 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 11034 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 11035 /* Hardware capabilities of NIC */ 11036 #define MC_CMD_GET_CAPABILITIES_V3_OUT_HW_CAPABILITIES_OFST 12 11037 /* Licensed capabilities */ 11038 #define MC_CMD_GET_CAPABILITIES_V3_OUT_LICENSE_CAPABILITIES_OFST 16 11039 /* Second word of flags. Not present on older firmware (check the length). */ 11040 #define MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS2_OFST 20 11041 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_LBN 0 11042 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_WIDTH 1 11043 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_ENCAP_LBN 1 11044 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_ENCAP_WIDTH 1 11045 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVQ_TIMER_CTRL_LBN 2 11046 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVQ_TIMER_CTRL_WIDTH 1 11047 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVENT_CUT_THROUGH_LBN 3 11048 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVENT_CUT_THROUGH_WIDTH 1 11049 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_CUT_THROUGH_LBN 4 11050 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_CUT_THROUGH_WIDTH 1 11051 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VFIFO_ULL_MODE_LBN 5 11052 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VFIFO_ULL_MODE_WIDTH 1 11053 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6 11054 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1 11055 #define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_V2_LBN 7 11056 #define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_V2_WIDTH 1 11057 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_TIMESTAMPING_LBN 8 11058 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_TIMESTAMPING_WIDTH 1 11059 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TIMESTAMP_LBN 9 11060 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TIMESTAMP_WIDTH 1 11061 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_SNIFF_LBN 10 11062 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_SNIFF_WIDTH 1 11063 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_SNIFF_LBN 11 11064 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_SNIFF_WIDTH 1 11065 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12 11066 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1 11067 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_BACKGROUND_LBN 13 11068 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_BACKGROUND_WIDTH 1 11069 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_DB_RETURN_LBN 14 11070 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_DB_RETURN_WIDTH 1 11071 /* Number of FATSOv2 contexts per datapath supported by this NIC. Not present 11072 * on older firmware (check the length). 11073 */ 11074 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24 11075 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2 11076 /* One byte per PF containing the number of the external port assigned to this 11077 * PF, indexed by PF number. Special values indicate that a PF is either not 11078 * present or not assigned. 11079 */ 11080 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26 11081 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1 11082 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16 11083 /* enum: The caller is not permitted to access information on this PF. */ 11084 #define MC_CMD_GET_CAPABILITIES_V3_OUT_ACCESS_NOT_PERMITTED 0xff 11085 /* enum: PF does not exist. */ 11086 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_PRESENT 0xfe 11087 /* enum: PF does exist but is not assigned to any external port. */ 11088 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_ASSIGNED 0xfd 11089 /* enum: This value indicates that PF is assigned, but it cannot be expressed 11090 * in this field. It is intended for a possible future situation where a more 11091 * complex scheme of PFs to ports mapping is being used. The future driver 11092 * should look for a new field supporting the new scheme. The current/old 11093 * driver should treat this value as PF_NOT_ASSIGNED. 11094 */ 11095 #define MC_CMD_GET_CAPABILITIES_V3_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc 11096 /* One byte per PF containing the number of its VFs, indexed by PF number. A 11097 * special value indicates that a PF is not present. 11098 */ 11099 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VFS_PER_PF_OFST 42 11100 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VFS_PER_PF_LEN 1 11101 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VFS_PER_PF_NUM 16 11102 /* enum: The caller is not permitted to access information on this PF. */ 11103 /* MC_CMD_GET_CAPABILITIES_V3_OUT_ACCESS_NOT_PERMITTED 0xff */ 11104 /* enum: PF does not exist. */ 11105 /* MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_PRESENT 0xfe */ 11106 /* Number of VIs available for each external port */ 11107 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VIS_PER_PORT_OFST 58 11108 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VIS_PER_PORT_LEN 2 11109 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VIS_PER_PORT_NUM 4 11110 /* Size of RX descriptor cache expressed as binary logarithm The actual size 11111 * equals (2 ^ RX_DESC_CACHE_SIZE) 11112 */ 11113 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DESC_CACHE_SIZE_OFST 66 11114 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DESC_CACHE_SIZE_LEN 1 11115 /* Size of TX descriptor cache expressed as binary logarithm The actual size 11116 * equals (2 ^ TX_DESC_CACHE_SIZE) 11117 */ 11118 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_DESC_CACHE_SIZE_OFST 67 11119 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_DESC_CACHE_SIZE_LEN 1 11120 /* Total number of available PIO buffers */ 11121 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_PIO_BUFFS_OFST 68 11122 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_PIO_BUFFS_LEN 2 11123 /* Size of a single PIO buffer */ 11124 #define MC_CMD_GET_CAPABILITIES_V3_OUT_SIZE_PIO_BUFF_OFST 70 11125 #define MC_CMD_GET_CAPABILITIES_V3_OUT_SIZE_PIO_BUFF_LEN 2 11126 /* On chips later than Medford the amount of address space assigned to each VI 11127 * is configurable. This is a global setting that the driver must query to 11128 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available 11129 * with 8k VI windows. 11130 */ 11131 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_OFST 72 11132 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_LEN 1 11133 /* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k. 11134 * CTPIO is not mapped. 11135 */ 11136 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_8K 0x0 11137 /* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */ 11138 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_16K 0x1 11139 /* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */ 11140 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_64K 0x2 11141 /* Number of vFIFOs per adapter that can be used for VFIFO Stuffing 11142 * (SF-115995-SW) in the present configuration of firmware and port mode. 11143 */ 11144 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 73 11145 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1 11146 /* Number of buffers per adapter that can be used for VFIFO Stuffing 11147 * (SF-115995-SW) in the present configuration of firmware and port mode. 11148 */ 11149 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 74 11150 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 2 11151 11152 11153 /***********************************/ 11154 /* MC_CMD_V2_EXTN 11155 * Encapsulation for a v2 extended command 11156 */ 11157 #define MC_CMD_V2_EXTN 0x7f 11158 11159 /* MC_CMD_V2_EXTN_IN msgrequest */ 11160 #define MC_CMD_V2_EXTN_IN_LEN 4 11161 /* the extended command number */ 11162 #define MC_CMD_V2_EXTN_IN_EXTENDED_CMD_LBN 0 11163 #define MC_CMD_V2_EXTN_IN_EXTENDED_CMD_WIDTH 15 11164 #define MC_CMD_V2_EXTN_IN_UNUSED_LBN 15 11165 #define MC_CMD_V2_EXTN_IN_UNUSED_WIDTH 1 11166 /* the actual length of the encapsulated command (which is not in the v1 11167 * header) 11168 */ 11169 #define MC_CMD_V2_EXTN_IN_ACTUAL_LEN_LBN 16 11170 #define MC_CMD_V2_EXTN_IN_ACTUAL_LEN_WIDTH 10 11171 #define MC_CMD_V2_EXTN_IN_UNUSED2_LBN 26 11172 #define MC_CMD_V2_EXTN_IN_UNUSED2_WIDTH 6 11173 11174 11175 /***********************************/ 11176 /* MC_CMD_TCM_BUCKET_ALLOC 11177 * Allocate a pacer bucket (for qau rp or a snapper test) 11178 */ 11179 #define MC_CMD_TCM_BUCKET_ALLOC 0xb2 11180 #undef MC_CMD_0xb2_PRIVILEGE_CTG 11181 11182 #define MC_CMD_0xb2_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11183 11184 /* MC_CMD_TCM_BUCKET_ALLOC_IN msgrequest */ 11185 #define MC_CMD_TCM_BUCKET_ALLOC_IN_LEN 0 11186 11187 /* MC_CMD_TCM_BUCKET_ALLOC_OUT msgresponse */ 11188 #define MC_CMD_TCM_BUCKET_ALLOC_OUT_LEN 4 11189 /* the bucket id */ 11190 #define MC_CMD_TCM_BUCKET_ALLOC_OUT_BUCKET_OFST 0 11191 11192 11193 /***********************************/ 11194 /* MC_CMD_TCM_BUCKET_FREE 11195 * Free a pacer bucket 11196 */ 11197 #define MC_CMD_TCM_BUCKET_FREE 0xb3 11198 #undef MC_CMD_0xb3_PRIVILEGE_CTG 11199 11200 #define MC_CMD_0xb3_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11201 11202 /* MC_CMD_TCM_BUCKET_FREE_IN msgrequest */ 11203 #define MC_CMD_TCM_BUCKET_FREE_IN_LEN 4 11204 /* the bucket id */ 11205 #define MC_CMD_TCM_BUCKET_FREE_IN_BUCKET_OFST 0 11206 11207 /* MC_CMD_TCM_BUCKET_FREE_OUT msgresponse */ 11208 #define MC_CMD_TCM_BUCKET_FREE_OUT_LEN 0 11209 11210 11211 /***********************************/ 11212 /* MC_CMD_TCM_BUCKET_INIT 11213 * Initialise pacer bucket with a given rate 11214 */ 11215 #define MC_CMD_TCM_BUCKET_INIT 0xb4 11216 #undef MC_CMD_0xb4_PRIVILEGE_CTG 11217 11218 #define MC_CMD_0xb4_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11219 11220 /* MC_CMD_TCM_BUCKET_INIT_IN msgrequest */ 11221 #define MC_CMD_TCM_BUCKET_INIT_IN_LEN 8 11222 /* the bucket id */ 11223 #define MC_CMD_TCM_BUCKET_INIT_IN_BUCKET_OFST 0 11224 /* the rate in mbps */ 11225 #define MC_CMD_TCM_BUCKET_INIT_IN_RATE_OFST 4 11226 11227 /* MC_CMD_TCM_BUCKET_INIT_EXT_IN msgrequest */ 11228 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_LEN 12 11229 /* the bucket id */ 11230 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_BUCKET_OFST 0 11231 /* the rate in mbps */ 11232 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_RATE_OFST 4 11233 /* the desired maximum fill level */ 11234 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_MAX_FILL_OFST 8 11235 11236 /* MC_CMD_TCM_BUCKET_INIT_OUT msgresponse */ 11237 #define MC_CMD_TCM_BUCKET_INIT_OUT_LEN 0 11238 11239 11240 /***********************************/ 11241 /* MC_CMD_TCM_TXQ_INIT 11242 * Initialise txq in pacer with given options or set options 11243 */ 11244 #define MC_CMD_TCM_TXQ_INIT 0xb5 11245 #undef MC_CMD_0xb5_PRIVILEGE_CTG 11246 11247 #define MC_CMD_0xb5_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11248 11249 /* MC_CMD_TCM_TXQ_INIT_IN msgrequest */ 11250 #define MC_CMD_TCM_TXQ_INIT_IN_LEN 28 11251 /* the txq id */ 11252 #define MC_CMD_TCM_TXQ_INIT_IN_QID_OFST 0 11253 /* the static priority associated with the txq */ 11254 #define MC_CMD_TCM_TXQ_INIT_IN_LABEL_OFST 4 11255 /* bitmask of the priority queues this txq is inserted into when inserted. */ 11256 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAGS_OFST 8 11257 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_GUARANTEED_LBN 0 11258 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_GUARANTEED_WIDTH 1 11259 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_NORMAL_LBN 1 11260 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_NORMAL_WIDTH 1 11261 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_LOW_LBN 2 11262 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_LOW_WIDTH 1 11263 /* the reaction point (RP) bucket */ 11264 #define MC_CMD_TCM_TXQ_INIT_IN_RP_BKT_OFST 12 11265 /* an already reserved bucket (typically set to bucket associated with outer 11266 * vswitch) 11267 */ 11268 #define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT1_OFST 16 11269 /* an already reserved bucket (typically set to bucket associated with inner 11270 * vswitch) 11271 */ 11272 #define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT2_OFST 20 11273 /* the min bucket (typically for ETS/minimum bandwidth) */ 11274 #define MC_CMD_TCM_TXQ_INIT_IN_MIN_BKT_OFST 24 11275 11276 /* MC_CMD_TCM_TXQ_INIT_EXT_IN msgrequest */ 11277 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_LEN 32 11278 /* the txq id */ 11279 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_QID_OFST 0 11280 /* the static priority associated with the txq */ 11281 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_NORMAL_OFST 4 11282 /* bitmask of the priority queues this txq is inserted into when inserted. */ 11283 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAGS_OFST 8 11284 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_GUARANTEED_LBN 0 11285 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_GUARANTEED_WIDTH 1 11286 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_NORMAL_LBN 1 11287 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_NORMAL_WIDTH 1 11288 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_LOW_LBN 2 11289 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_LOW_WIDTH 1 11290 /* the reaction point (RP) bucket */ 11291 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_RP_BKT_OFST 12 11292 /* an already reserved bucket (typically set to bucket associated with outer 11293 * vswitch) 11294 */ 11295 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT1_OFST 16 11296 /* an already reserved bucket (typically set to bucket associated with inner 11297 * vswitch) 11298 */ 11299 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT2_OFST 20 11300 /* the min bucket (typically for ETS/minimum bandwidth) */ 11301 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MIN_BKT_OFST 24 11302 /* the static priority associated with the txq */ 11303 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_GUARANTEED_OFST 28 11304 11305 /* MC_CMD_TCM_TXQ_INIT_OUT msgresponse */ 11306 #define MC_CMD_TCM_TXQ_INIT_OUT_LEN 0 11307 11308 11309 /***********************************/ 11310 /* MC_CMD_LINK_PIOBUF 11311 * Link a push I/O buffer to a TxQ 11312 */ 11313 #define MC_CMD_LINK_PIOBUF 0x92 11314 #undef MC_CMD_0x92_PRIVILEGE_CTG 11315 11316 #define MC_CMD_0x92_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 11317 11318 /* MC_CMD_LINK_PIOBUF_IN msgrequest */ 11319 #define MC_CMD_LINK_PIOBUF_IN_LEN 8 11320 /* Handle for allocated push I/O buffer. */ 11321 #define MC_CMD_LINK_PIOBUF_IN_PIOBUF_HANDLE_OFST 0 11322 /* Function Local Instance (VI) number. */ 11323 #define MC_CMD_LINK_PIOBUF_IN_TXQ_INSTANCE_OFST 4 11324 11325 /* MC_CMD_LINK_PIOBUF_OUT msgresponse */ 11326 #define MC_CMD_LINK_PIOBUF_OUT_LEN 0 11327 11328 11329 /***********************************/ 11330 /* MC_CMD_UNLINK_PIOBUF 11331 * Unlink a push I/O buffer from a TxQ 11332 */ 11333 #define MC_CMD_UNLINK_PIOBUF 0x93 11334 #undef MC_CMD_0x93_PRIVILEGE_CTG 11335 11336 #define MC_CMD_0x93_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 11337 11338 /* MC_CMD_UNLINK_PIOBUF_IN msgrequest */ 11339 #define MC_CMD_UNLINK_PIOBUF_IN_LEN 4 11340 /* Function Local Instance (VI) number. */ 11341 #define MC_CMD_UNLINK_PIOBUF_IN_TXQ_INSTANCE_OFST 0 11342 11343 /* MC_CMD_UNLINK_PIOBUF_OUT msgresponse */ 11344 #define MC_CMD_UNLINK_PIOBUF_OUT_LEN 0 11345 11346 11347 /***********************************/ 11348 /* MC_CMD_VSWITCH_ALLOC 11349 * allocate and initialise a v-switch. 11350 */ 11351 #define MC_CMD_VSWITCH_ALLOC 0x94 11352 #undef MC_CMD_0x94_PRIVILEGE_CTG 11353 11354 #define MC_CMD_0x94_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11355 11356 /* MC_CMD_VSWITCH_ALLOC_IN msgrequest */ 11357 #define MC_CMD_VSWITCH_ALLOC_IN_LEN 16 11358 /* The port to connect to the v-switch's upstream port. */ 11359 #define MC_CMD_VSWITCH_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 11360 /* The type of v-switch to create. */ 11361 #define MC_CMD_VSWITCH_ALLOC_IN_TYPE_OFST 4 11362 /* enum: VLAN */ 11363 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VLAN 0x1 11364 /* enum: VEB */ 11365 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEB 0x2 11366 /* enum: VEPA (obsolete) */ 11367 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEPA 0x3 11368 /* enum: MUX */ 11369 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_MUX 0x4 11370 /* enum: Snapper specific; semantics TBD */ 11371 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_TEST 0x5 11372 /* Flags controlling v-port creation */ 11373 #define MC_CMD_VSWITCH_ALLOC_IN_FLAGS_OFST 8 11374 #define MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_LBN 0 11375 #define MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_WIDTH 1 11376 /* The number of VLAN tags to allow for attached v-ports. For VLAN aggregators, 11377 * this must be one or greated, and the attached v-ports must have exactly this 11378 * number of tags. For other v-switch types, this must be zero of greater, and 11379 * is an upper limit on the number of VLAN tags for attached v-ports. An error 11380 * will be returned if existing configuration means we can't support attached 11381 * v-ports with this number of tags. 11382 */ 11383 #define MC_CMD_VSWITCH_ALLOC_IN_NUM_VLAN_TAGS_OFST 12 11384 11385 /* MC_CMD_VSWITCH_ALLOC_OUT msgresponse */ 11386 #define MC_CMD_VSWITCH_ALLOC_OUT_LEN 0 11387 11388 11389 /***********************************/ 11390 /* MC_CMD_VSWITCH_FREE 11391 * de-allocate a v-switch. 11392 */ 11393 #define MC_CMD_VSWITCH_FREE 0x95 11394 #undef MC_CMD_0x95_PRIVILEGE_CTG 11395 11396 #define MC_CMD_0x95_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11397 11398 /* MC_CMD_VSWITCH_FREE_IN msgrequest */ 11399 #define MC_CMD_VSWITCH_FREE_IN_LEN 4 11400 /* The port to which the v-switch is connected. */ 11401 #define MC_CMD_VSWITCH_FREE_IN_UPSTREAM_PORT_ID_OFST 0 11402 11403 /* MC_CMD_VSWITCH_FREE_OUT msgresponse */ 11404 #define MC_CMD_VSWITCH_FREE_OUT_LEN 0 11405 11406 11407 /***********************************/ 11408 /* MC_CMD_VSWITCH_QUERY 11409 * read some config of v-switch. For now this command is an empty placeholder. 11410 * It may be used to check if a v-switch is connected to a given EVB port (if 11411 * not, then the command returns ENOENT). 11412 */ 11413 #define MC_CMD_VSWITCH_QUERY 0x63 11414 #undef MC_CMD_0x63_PRIVILEGE_CTG 11415 11416 #define MC_CMD_0x63_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11417 11418 /* MC_CMD_VSWITCH_QUERY_IN msgrequest */ 11419 #define MC_CMD_VSWITCH_QUERY_IN_LEN 4 11420 /* The port to which the v-switch is connected. */ 11421 #define MC_CMD_VSWITCH_QUERY_IN_UPSTREAM_PORT_ID_OFST 0 11422 11423 /* MC_CMD_VSWITCH_QUERY_OUT msgresponse */ 11424 #define MC_CMD_VSWITCH_QUERY_OUT_LEN 0 11425 11426 11427 /***********************************/ 11428 /* MC_CMD_VPORT_ALLOC 11429 * allocate a v-port. 11430 */ 11431 #define MC_CMD_VPORT_ALLOC 0x96 11432 #undef MC_CMD_0x96_PRIVILEGE_CTG 11433 11434 #define MC_CMD_0x96_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11435 11436 /* MC_CMD_VPORT_ALLOC_IN msgrequest */ 11437 #define MC_CMD_VPORT_ALLOC_IN_LEN 20 11438 /* The port to which the v-switch is connected. */ 11439 #define MC_CMD_VPORT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 11440 /* The type of the new v-port. */ 11441 #define MC_CMD_VPORT_ALLOC_IN_TYPE_OFST 4 11442 /* enum: VLAN (obsolete) */ 11443 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VLAN 0x1 11444 /* enum: VEB (obsolete) */ 11445 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEB 0x2 11446 /* enum: VEPA (obsolete) */ 11447 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEPA 0x3 11448 /* enum: A normal v-port receives packets which match a specified MAC and/or 11449 * VLAN. 11450 */ 11451 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_NORMAL 0x4 11452 /* enum: An expansion v-port packets traffic which don't match any other 11453 * v-port. 11454 */ 11455 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_EXPANSION 0x5 11456 /* enum: An test v-port receives packets which match any filters installed by 11457 * its downstream components. 11458 */ 11459 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_TEST 0x6 11460 /* Flags controlling v-port creation */ 11461 #define MC_CMD_VPORT_ALLOC_IN_FLAGS_OFST 8 11462 #define MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_LBN 0 11463 #define MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_WIDTH 1 11464 #define MC_CMD_VPORT_ALLOC_IN_FLAG_VLAN_RESTRICT_LBN 1 11465 #define MC_CMD_VPORT_ALLOC_IN_FLAG_VLAN_RESTRICT_WIDTH 1 11466 /* The number of VLAN tags to insert/remove. An error will be returned if 11467 * incompatible with the number of VLAN tags specified for the upstream 11468 * v-switch. 11469 */ 11470 #define MC_CMD_VPORT_ALLOC_IN_NUM_VLAN_TAGS_OFST 12 11471 /* The actual VLAN tags to insert/remove */ 11472 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAGS_OFST 16 11473 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_LBN 0 11474 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_WIDTH 16 11475 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_LBN 16 11476 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_WIDTH 16 11477 11478 /* MC_CMD_VPORT_ALLOC_OUT msgresponse */ 11479 #define MC_CMD_VPORT_ALLOC_OUT_LEN 4 11480 /* The handle of the new v-port */ 11481 #define MC_CMD_VPORT_ALLOC_OUT_VPORT_ID_OFST 0 11482 11483 11484 /***********************************/ 11485 /* MC_CMD_VPORT_FREE 11486 * de-allocate a v-port. 11487 */ 11488 #define MC_CMD_VPORT_FREE 0x97 11489 #undef MC_CMD_0x97_PRIVILEGE_CTG 11490 11491 #define MC_CMD_0x97_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11492 11493 /* MC_CMD_VPORT_FREE_IN msgrequest */ 11494 #define MC_CMD_VPORT_FREE_IN_LEN 4 11495 /* The handle of the v-port */ 11496 #define MC_CMD_VPORT_FREE_IN_VPORT_ID_OFST 0 11497 11498 /* MC_CMD_VPORT_FREE_OUT msgresponse */ 11499 #define MC_CMD_VPORT_FREE_OUT_LEN 0 11500 11501 11502 /***********************************/ 11503 /* MC_CMD_VADAPTOR_ALLOC 11504 * allocate a v-adaptor. 11505 */ 11506 #define MC_CMD_VADAPTOR_ALLOC 0x98 11507 #undef MC_CMD_0x98_PRIVILEGE_CTG 11508 11509 #define MC_CMD_0x98_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11510 11511 /* MC_CMD_VADAPTOR_ALLOC_IN msgrequest */ 11512 #define MC_CMD_VADAPTOR_ALLOC_IN_LEN 30 11513 /* The port to connect to the v-adaptor's port. */ 11514 #define MC_CMD_VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 11515 /* Flags controlling v-adaptor creation */ 11516 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAGS_OFST 8 11517 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_LBN 0 11518 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_WIDTH 1 11519 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 1 11520 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1 11521 /* The number of VLAN tags to strip on receive */ 11522 #define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLANS_OFST 12 11523 /* The number of VLAN tags to transparently insert/remove. */ 11524 #define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLAN_TAGS_OFST 16 11525 /* The actual VLAN tags to insert/remove */ 11526 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAGS_OFST 20 11527 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_0_LBN 0 11528 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_0_WIDTH 16 11529 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_1_LBN 16 11530 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_1_WIDTH 16 11531 /* The MAC address to assign to this v-adaptor */ 11532 #define MC_CMD_VADAPTOR_ALLOC_IN_MACADDR_OFST 24 11533 #define MC_CMD_VADAPTOR_ALLOC_IN_MACADDR_LEN 6 11534 /* enum: Derive the MAC address from the upstream port */ 11535 #define MC_CMD_VADAPTOR_ALLOC_IN_AUTO_MAC 0x0 11536 11537 /* MC_CMD_VADAPTOR_ALLOC_OUT msgresponse */ 11538 #define MC_CMD_VADAPTOR_ALLOC_OUT_LEN 0 11539 11540 11541 /***********************************/ 11542 /* MC_CMD_VADAPTOR_FREE 11543 * de-allocate a v-adaptor. 11544 */ 11545 #define MC_CMD_VADAPTOR_FREE 0x99 11546 #undef MC_CMD_0x99_PRIVILEGE_CTG 11547 11548 #define MC_CMD_0x99_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11549 11550 /* MC_CMD_VADAPTOR_FREE_IN msgrequest */ 11551 #define MC_CMD_VADAPTOR_FREE_IN_LEN 4 11552 /* The port to which the v-adaptor is connected. */ 11553 #define MC_CMD_VADAPTOR_FREE_IN_UPSTREAM_PORT_ID_OFST 0 11554 11555 /* MC_CMD_VADAPTOR_FREE_OUT msgresponse */ 11556 #define MC_CMD_VADAPTOR_FREE_OUT_LEN 0 11557 11558 11559 /***********************************/ 11560 /* MC_CMD_VADAPTOR_SET_MAC 11561 * assign a new MAC address to a v-adaptor. 11562 */ 11563 #define MC_CMD_VADAPTOR_SET_MAC 0x5d 11564 #undef MC_CMD_0x5d_PRIVILEGE_CTG 11565 11566 #define MC_CMD_0x5d_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11567 11568 /* MC_CMD_VADAPTOR_SET_MAC_IN msgrequest */ 11569 #define MC_CMD_VADAPTOR_SET_MAC_IN_LEN 10 11570 /* The port to which the v-adaptor is connected. */ 11571 #define MC_CMD_VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID_OFST 0 11572 /* The new MAC address to assign to this v-adaptor */ 11573 #define MC_CMD_VADAPTOR_SET_MAC_IN_MACADDR_OFST 4 11574 #define MC_CMD_VADAPTOR_SET_MAC_IN_MACADDR_LEN 6 11575 11576 /* MC_CMD_VADAPTOR_SET_MAC_OUT msgresponse */ 11577 #define MC_CMD_VADAPTOR_SET_MAC_OUT_LEN 0 11578 11579 11580 /***********************************/ 11581 /* MC_CMD_VADAPTOR_GET_MAC 11582 * read the MAC address assigned to a v-adaptor. 11583 */ 11584 #define MC_CMD_VADAPTOR_GET_MAC 0x5e 11585 #undef MC_CMD_0x5e_PRIVILEGE_CTG 11586 11587 #define MC_CMD_0x5e_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11588 11589 /* MC_CMD_VADAPTOR_GET_MAC_IN msgrequest */ 11590 #define MC_CMD_VADAPTOR_GET_MAC_IN_LEN 4 11591 /* The port to which the v-adaptor is connected. */ 11592 #define MC_CMD_VADAPTOR_GET_MAC_IN_UPSTREAM_PORT_ID_OFST 0 11593 11594 /* MC_CMD_VADAPTOR_GET_MAC_OUT msgresponse */ 11595 #define MC_CMD_VADAPTOR_GET_MAC_OUT_LEN 6 11596 /* The MAC address assigned to this v-adaptor */ 11597 #define MC_CMD_VADAPTOR_GET_MAC_OUT_MACADDR_OFST 0 11598 #define MC_CMD_VADAPTOR_GET_MAC_OUT_MACADDR_LEN 6 11599 11600 11601 /***********************************/ 11602 /* MC_CMD_VADAPTOR_QUERY 11603 * read some config of v-adaptor. 11604 */ 11605 #define MC_CMD_VADAPTOR_QUERY 0x61 11606 #undef MC_CMD_0x61_PRIVILEGE_CTG 11607 11608 #define MC_CMD_0x61_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11609 11610 /* MC_CMD_VADAPTOR_QUERY_IN msgrequest */ 11611 #define MC_CMD_VADAPTOR_QUERY_IN_LEN 4 11612 /* The port to which the v-adaptor is connected. */ 11613 #define MC_CMD_VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID_OFST 0 11614 11615 /* MC_CMD_VADAPTOR_QUERY_OUT msgresponse */ 11616 #define MC_CMD_VADAPTOR_QUERY_OUT_LEN 12 11617 /* The EVB port flags as defined at MC_CMD_VPORT_ALLOC. */ 11618 #define MC_CMD_VADAPTOR_QUERY_OUT_PORT_FLAGS_OFST 0 11619 /* The v-adaptor flags as defined at MC_CMD_VADAPTOR_ALLOC. */ 11620 #define MC_CMD_VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS_OFST 4 11621 /* The number of VLAN tags that may still be added */ 11622 #define MC_CMD_VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_OFST 8 11623 11624 11625 /***********************************/ 11626 /* MC_CMD_EVB_PORT_ASSIGN 11627 * assign a port to a PCI function. 11628 */ 11629 #define MC_CMD_EVB_PORT_ASSIGN 0x9a 11630 #undef MC_CMD_0x9a_PRIVILEGE_CTG 11631 11632 #define MC_CMD_0x9a_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11633 11634 /* MC_CMD_EVB_PORT_ASSIGN_IN msgrequest */ 11635 #define MC_CMD_EVB_PORT_ASSIGN_IN_LEN 8 11636 /* The port to assign. */ 11637 #define MC_CMD_EVB_PORT_ASSIGN_IN_PORT_ID_OFST 0 11638 /* The target function to modify. */ 11639 #define MC_CMD_EVB_PORT_ASSIGN_IN_FUNCTION_OFST 4 11640 #define MC_CMD_EVB_PORT_ASSIGN_IN_PF_LBN 0 11641 #define MC_CMD_EVB_PORT_ASSIGN_IN_PF_WIDTH 16 11642 #define MC_CMD_EVB_PORT_ASSIGN_IN_VF_LBN 16 11643 #define MC_CMD_EVB_PORT_ASSIGN_IN_VF_WIDTH 16 11644 11645 /* MC_CMD_EVB_PORT_ASSIGN_OUT msgresponse */ 11646 #define MC_CMD_EVB_PORT_ASSIGN_OUT_LEN 0 11647 11648 11649 /***********************************/ 11650 /* MC_CMD_RDWR_A64_REGIONS 11651 * Assign the 64 bit region addresses. 11652 */ 11653 #define MC_CMD_RDWR_A64_REGIONS 0x9b 11654 #undef MC_CMD_0x9b_PRIVILEGE_CTG 11655 11656 #define MC_CMD_0x9b_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11657 11658 /* MC_CMD_RDWR_A64_REGIONS_IN msgrequest */ 11659 #define MC_CMD_RDWR_A64_REGIONS_IN_LEN 17 11660 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION0_OFST 0 11661 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION1_OFST 4 11662 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION2_OFST 8 11663 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION3_OFST 12 11664 /* Write enable bits 0-3, set to write, clear to read. */ 11665 #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_LBN 128 11666 #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_WIDTH 4 11667 #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_BYTE_OFST 16 11668 #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_BYTE_LEN 1 11669 11670 /* MC_CMD_RDWR_A64_REGIONS_OUT msgresponse: This data always included 11671 * regardless of state of write bits in the request. 11672 */ 11673 #define MC_CMD_RDWR_A64_REGIONS_OUT_LEN 16 11674 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION0_OFST 0 11675 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION1_OFST 4 11676 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION2_OFST 8 11677 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION3_OFST 12 11678 11679 11680 /***********************************/ 11681 /* MC_CMD_ONLOAD_STACK_ALLOC 11682 * Allocate an Onload stack ID. 11683 */ 11684 #define MC_CMD_ONLOAD_STACK_ALLOC 0x9c 11685 #undef MC_CMD_0x9c_PRIVILEGE_CTG 11686 11687 #define MC_CMD_0x9c_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 11688 11689 /* MC_CMD_ONLOAD_STACK_ALLOC_IN msgrequest */ 11690 #define MC_CMD_ONLOAD_STACK_ALLOC_IN_LEN 4 11691 /* The handle of the owning upstream port */ 11692 #define MC_CMD_ONLOAD_STACK_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 11693 11694 /* MC_CMD_ONLOAD_STACK_ALLOC_OUT msgresponse */ 11695 #define MC_CMD_ONLOAD_STACK_ALLOC_OUT_LEN 4 11696 /* The handle of the new Onload stack */ 11697 #define MC_CMD_ONLOAD_STACK_ALLOC_OUT_ONLOAD_STACK_ID_OFST 0 11698 11699 11700 /***********************************/ 11701 /* MC_CMD_ONLOAD_STACK_FREE 11702 * Free an Onload stack ID. 11703 */ 11704 #define MC_CMD_ONLOAD_STACK_FREE 0x9d 11705 #undef MC_CMD_0x9d_PRIVILEGE_CTG 11706 11707 #define MC_CMD_0x9d_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 11708 11709 /* MC_CMD_ONLOAD_STACK_FREE_IN msgrequest */ 11710 #define MC_CMD_ONLOAD_STACK_FREE_IN_LEN 4 11711 /* The handle of the Onload stack */ 11712 #define MC_CMD_ONLOAD_STACK_FREE_IN_ONLOAD_STACK_ID_OFST 0 11713 11714 /* MC_CMD_ONLOAD_STACK_FREE_OUT msgresponse */ 11715 #define MC_CMD_ONLOAD_STACK_FREE_OUT_LEN 0 11716 11717 11718 /***********************************/ 11719 /* MC_CMD_RSS_CONTEXT_ALLOC 11720 * Allocate an RSS context. 11721 */ 11722 #define MC_CMD_RSS_CONTEXT_ALLOC 0x9e 11723 #undef MC_CMD_0x9e_PRIVILEGE_CTG 11724 11725 #define MC_CMD_0x9e_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11726 11727 /* MC_CMD_RSS_CONTEXT_ALLOC_IN msgrequest */ 11728 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN 12 11729 /* The handle of the owning upstream port */ 11730 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 11731 /* The type of context to allocate */ 11732 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_OFST 4 11733 /* enum: Allocate a context for exclusive use. The key and indirection table 11734 * must be explicitly configured. 11735 */ 11736 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE 0x0 11737 /* enum: Allocate a context for shared use; this will spread across a range of 11738 * queues, but the key and indirection table are pre-configured and may not be 11739 * changed. For this mode, NUM_QUEUES must 2, 4, 8, 16, 32 or 64. 11740 */ 11741 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED 0x1 11742 /* Number of queues spanned by this context, in the range 1-64; valid offsets 11743 * in the indirection table will be in the range 0 to NUM_QUEUES-1. 11744 */ 11745 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_NUM_QUEUES_OFST 8 11746 11747 /* MC_CMD_RSS_CONTEXT_ALLOC_OUT msgresponse */ 11748 #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN 4 11749 /* The handle of the new RSS context. This should be considered opaque to the 11750 * host, although a value of 0xFFFFFFFF is guaranteed never to be a valid 11751 * handle. 11752 */ 11753 #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_OFST 0 11754 /* enum: guaranteed invalid RSS context handle value */ 11755 #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_INVALID 0xffffffff 11756 11757 11758 /***********************************/ 11759 /* MC_CMD_RSS_CONTEXT_FREE 11760 * Free an RSS context. 11761 */ 11762 #define MC_CMD_RSS_CONTEXT_FREE 0x9f 11763 #undef MC_CMD_0x9f_PRIVILEGE_CTG 11764 11765 #define MC_CMD_0x9f_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11766 11767 /* MC_CMD_RSS_CONTEXT_FREE_IN msgrequest */ 11768 #define MC_CMD_RSS_CONTEXT_FREE_IN_LEN 4 11769 /* The handle of the RSS context */ 11770 #define MC_CMD_RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID_OFST 0 11771 11772 /* MC_CMD_RSS_CONTEXT_FREE_OUT msgresponse */ 11773 #define MC_CMD_RSS_CONTEXT_FREE_OUT_LEN 0 11774 11775 11776 /***********************************/ 11777 /* MC_CMD_RSS_CONTEXT_SET_KEY 11778 * Set the Toeplitz hash key for an RSS context. 11779 */ 11780 #define MC_CMD_RSS_CONTEXT_SET_KEY 0xa0 11781 #undef MC_CMD_0xa0_PRIVILEGE_CTG 11782 11783 #define MC_CMD_0xa0_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11784 11785 /* MC_CMD_RSS_CONTEXT_SET_KEY_IN msgrequest */ 11786 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN 44 11787 /* The handle of the RSS context */ 11788 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID_OFST 0 11789 /* The 40-byte Toeplitz hash key (TBD endianness issues?) */ 11790 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_OFST 4 11791 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN 40 11792 11793 /* MC_CMD_RSS_CONTEXT_SET_KEY_OUT msgresponse */ 11794 #define MC_CMD_RSS_CONTEXT_SET_KEY_OUT_LEN 0 11795 11796 11797 /***********************************/ 11798 /* MC_CMD_RSS_CONTEXT_GET_KEY 11799 * Get the Toeplitz hash key for an RSS context. 11800 */ 11801 #define MC_CMD_RSS_CONTEXT_GET_KEY 0xa1 11802 #undef MC_CMD_0xa1_PRIVILEGE_CTG 11803 11804 #define MC_CMD_0xa1_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11805 11806 /* MC_CMD_RSS_CONTEXT_GET_KEY_IN msgrequest */ 11807 #define MC_CMD_RSS_CONTEXT_GET_KEY_IN_LEN 4 11808 /* The handle of the RSS context */ 11809 #define MC_CMD_RSS_CONTEXT_GET_KEY_IN_RSS_CONTEXT_ID_OFST 0 11810 11811 /* MC_CMD_RSS_CONTEXT_GET_KEY_OUT msgresponse */ 11812 #define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_LEN 44 11813 /* The 40-byte Toeplitz hash key (TBD endianness issues?) */ 11814 #define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY_OFST 4 11815 #define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY_LEN 40 11816 11817 11818 /***********************************/ 11819 /* MC_CMD_RSS_CONTEXT_SET_TABLE 11820 * Set the indirection table for an RSS context. 11821 */ 11822 #define MC_CMD_RSS_CONTEXT_SET_TABLE 0xa2 11823 #undef MC_CMD_0xa2_PRIVILEGE_CTG 11824 11825 #define MC_CMD_0xa2_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11826 11827 /* MC_CMD_RSS_CONTEXT_SET_TABLE_IN msgrequest */ 11828 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN 132 11829 /* The handle of the RSS context */ 11830 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID_OFST 0 11831 /* The 128-byte indirection table (1 byte per entry) */ 11832 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_OFST 4 11833 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN 128 11834 11835 /* MC_CMD_RSS_CONTEXT_SET_TABLE_OUT msgresponse */ 11836 #define MC_CMD_RSS_CONTEXT_SET_TABLE_OUT_LEN 0 11837 11838 11839 /***********************************/ 11840 /* MC_CMD_RSS_CONTEXT_GET_TABLE 11841 * Get the indirection table for an RSS context. 11842 */ 11843 #define MC_CMD_RSS_CONTEXT_GET_TABLE 0xa3 11844 #undef MC_CMD_0xa3_PRIVILEGE_CTG 11845 11846 #define MC_CMD_0xa3_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11847 11848 /* MC_CMD_RSS_CONTEXT_GET_TABLE_IN msgrequest */ 11849 #define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_LEN 4 11850 /* The handle of the RSS context */ 11851 #define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_RSS_CONTEXT_ID_OFST 0 11852 11853 /* MC_CMD_RSS_CONTEXT_GET_TABLE_OUT msgresponse */ 11854 #define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_LEN 132 11855 /* The 128-byte indirection table (1 byte per entry) */ 11856 #define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_OFST 4 11857 #define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_LEN 128 11858 11859 11860 /***********************************/ 11861 /* MC_CMD_RSS_CONTEXT_SET_FLAGS 11862 * Set various control flags for an RSS context. 11863 */ 11864 #define MC_CMD_RSS_CONTEXT_SET_FLAGS 0xe1 11865 #undef MC_CMD_0xe1_PRIVILEGE_CTG 11866 11867 #define MC_CMD_0xe1_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11868 11869 /* MC_CMD_RSS_CONTEXT_SET_FLAGS_IN msgrequest */ 11870 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_LEN 8 11871 /* The handle of the RSS context */ 11872 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID_OFST 0 11873 /* Hash control flags. The _EN bits are always supported, but new modes are 11874 * available when ADDITIONAL_RSS_MODES is reported by MC_CMD_GET_CAPABILITIES: 11875 * in this case, the MODE fields may be set to non-zero values, and will take 11876 * effect regardless of the settings of the _EN flags. See the RSS_MODE 11877 * structure for the meaning of the mode bits. Drivers must check the 11878 * capability before trying to set any _MODE fields, as older firmware will 11879 * reject any attempt to set the FLAGS field to a value > 0xff with EINVAL. In 11880 * the case where all the _MODE flags are zero, the _EN flags take effect, 11881 * providing backward compatibility for existing drivers. (Setting all _MODE 11882 * *and* all _EN flags to zero is valid, to disable RSS spreading for that 11883 * particular packet type.) 11884 */ 11885 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_FLAGS_OFST 4 11886 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_LBN 0 11887 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_WIDTH 1 11888 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_LBN 1 11889 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_WIDTH 1 11890 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_LBN 2 11891 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_WIDTH 1 11892 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_LBN 3 11893 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_WIDTH 1 11894 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_LBN 4 11895 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_WIDTH 4 11896 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_LBN 8 11897 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_WIDTH 4 11898 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE_LBN 12 11899 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE_WIDTH 4 11900 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_LBN 16 11901 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_WIDTH 4 11902 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_LBN 20 11903 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_WIDTH 4 11904 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE_LBN 24 11905 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE_WIDTH 4 11906 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_LBN 28 11907 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_WIDTH 4 11908 11909 /* MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT msgresponse */ 11910 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT_LEN 0 11911 11912 11913 /***********************************/ 11914 /* MC_CMD_RSS_CONTEXT_GET_FLAGS 11915 * Get various control flags for an RSS context. 11916 */ 11917 #define MC_CMD_RSS_CONTEXT_GET_FLAGS 0xe2 11918 #undef MC_CMD_0xe2_PRIVILEGE_CTG 11919 11920 #define MC_CMD_0xe2_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11921 11922 /* MC_CMD_RSS_CONTEXT_GET_FLAGS_IN msgrequest */ 11923 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_LEN 4 11924 /* The handle of the RSS context */ 11925 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_RSS_CONTEXT_ID_OFST 0 11926 11927 /* MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT msgresponse */ 11928 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN 8 11929 /* Hash control flags. If all _MODE bits are zero (which will always be true 11930 * for older firmware which does not report the ADDITIONAL_RSS_MODES 11931 * capability), the _EN bits report the state. If any _MODE bits are non-zero 11932 * (which will only be true when the firmware reports ADDITIONAL_RSS_MODES) 11933 * then the _EN bits should be disregarded, although the _MODE flags are 11934 * guaranteed to be consistent with the _EN flags for a freshly-allocated RSS 11935 * context and in the case where the _EN flags were used in the SET. This 11936 * provides backward compatibility: old drivers will not be attempting to 11937 * derive any meaning from the _MODE bits (and can never set them to any value 11938 * not representable by the _EN bits); new drivers can always determine the 11939 * mode by looking only at the _MODE bits; the value returned by a GET can 11940 * always be used for a SET regardless of old/new driver vs. old/new firmware. 11941 */ 11942 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_OFST 4 11943 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_LBN 0 11944 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_WIDTH 1 11945 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_LBN 1 11946 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_WIDTH 1 11947 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_LBN 2 11948 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_WIDTH 1 11949 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_LBN 3 11950 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_WIDTH 1 11951 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_LBN 4 11952 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_WIDTH 4 11953 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_LBN 8 11954 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_WIDTH 4 11955 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_LBN 12 11956 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_WIDTH 4 11957 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_LBN 16 11958 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_WIDTH 4 11959 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_LBN 20 11960 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_WIDTH 4 11961 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_LBN 24 11962 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_WIDTH 4 11963 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_LBN 28 11964 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_WIDTH 4 11965 11966 11967 /***********************************/ 11968 /* MC_CMD_DOT1P_MAPPING_ALLOC 11969 * Allocate a .1p mapping. 11970 */ 11971 #define MC_CMD_DOT1P_MAPPING_ALLOC 0xa4 11972 #undef MC_CMD_0xa4_PRIVILEGE_CTG 11973 11974 #define MC_CMD_0xa4_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11975 11976 /* MC_CMD_DOT1P_MAPPING_ALLOC_IN msgrequest */ 11977 #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_LEN 8 11978 /* The handle of the owning upstream port */ 11979 #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 11980 /* Number of queues spanned by this mapping, in the range 1-64; valid fixed 11981 * offsets in the mapping table will be in the range 0 to NUM_QUEUES-1, and 11982 * referenced RSS contexts must span no more than this number. 11983 */ 11984 #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_NUM_QUEUES_OFST 4 11985 11986 /* MC_CMD_DOT1P_MAPPING_ALLOC_OUT msgresponse */ 11987 #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_LEN 4 11988 /* The handle of the new .1p mapping. This should be considered opaque to the 11989 * host, although a value of 0xFFFFFFFF is guaranteed never to be a valid 11990 * handle. 11991 */ 11992 #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_OFST 0 11993 /* enum: guaranteed invalid .1p mapping handle value */ 11994 #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_INVALID 0xffffffff 11995 11996 11997 /***********************************/ 11998 /* MC_CMD_DOT1P_MAPPING_FREE 11999 * Free a .1p mapping. 12000 */ 12001 #define MC_CMD_DOT1P_MAPPING_FREE 0xa5 12002 #undef MC_CMD_0xa5_PRIVILEGE_CTG 12003 12004 #define MC_CMD_0xa5_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12005 12006 /* MC_CMD_DOT1P_MAPPING_FREE_IN msgrequest */ 12007 #define MC_CMD_DOT1P_MAPPING_FREE_IN_LEN 4 12008 /* The handle of the .1p mapping */ 12009 #define MC_CMD_DOT1P_MAPPING_FREE_IN_DOT1P_MAPPING_ID_OFST 0 12010 12011 /* MC_CMD_DOT1P_MAPPING_FREE_OUT msgresponse */ 12012 #define MC_CMD_DOT1P_MAPPING_FREE_OUT_LEN 0 12013 12014 12015 /***********************************/ 12016 /* MC_CMD_DOT1P_MAPPING_SET_TABLE 12017 * Set the mapping table for a .1p mapping. 12018 */ 12019 #define MC_CMD_DOT1P_MAPPING_SET_TABLE 0xa6 12020 #undef MC_CMD_0xa6_PRIVILEGE_CTG 12021 12022 #define MC_CMD_0xa6_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12023 12024 /* MC_CMD_DOT1P_MAPPING_SET_TABLE_IN msgrequest */ 12025 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_LEN 36 12026 /* The handle of the .1p mapping */ 12027 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_DOT1P_MAPPING_ID_OFST 0 12028 /* Per-priority mappings (1 32-bit word per entry - an offset or RSS context 12029 * handle) 12030 */ 12031 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_MAPPING_TABLE_OFST 4 12032 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_MAPPING_TABLE_LEN 32 12033 12034 /* MC_CMD_DOT1P_MAPPING_SET_TABLE_OUT msgresponse */ 12035 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_OUT_LEN 0 12036 12037 12038 /***********************************/ 12039 /* MC_CMD_DOT1P_MAPPING_GET_TABLE 12040 * Get the mapping table for a .1p mapping. 12041 */ 12042 #define MC_CMD_DOT1P_MAPPING_GET_TABLE 0xa7 12043 #undef MC_CMD_0xa7_PRIVILEGE_CTG 12044 12045 #define MC_CMD_0xa7_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12046 12047 /* MC_CMD_DOT1P_MAPPING_GET_TABLE_IN msgrequest */ 12048 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_IN_LEN 4 12049 /* The handle of the .1p mapping */ 12050 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_IN_DOT1P_MAPPING_ID_OFST 0 12051 12052 /* MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT msgresponse */ 12053 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_LEN 36 12054 /* Per-priority mappings (1 32-bit word per entry - an offset or RSS context 12055 * handle) 12056 */ 12057 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_MAPPING_TABLE_OFST 4 12058 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_MAPPING_TABLE_LEN 32 12059 12060 12061 /***********************************/ 12062 /* MC_CMD_GET_VECTOR_CFG 12063 * Get Interrupt Vector config for this PF. 12064 */ 12065 #define MC_CMD_GET_VECTOR_CFG 0xbf 12066 #undef MC_CMD_0xbf_PRIVILEGE_CTG 12067 12068 #define MC_CMD_0xbf_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12069 12070 /* MC_CMD_GET_VECTOR_CFG_IN msgrequest */ 12071 #define MC_CMD_GET_VECTOR_CFG_IN_LEN 0 12072 12073 /* MC_CMD_GET_VECTOR_CFG_OUT msgresponse */ 12074 #define MC_CMD_GET_VECTOR_CFG_OUT_LEN 12 12075 /* Base absolute interrupt vector number. */ 12076 #define MC_CMD_GET_VECTOR_CFG_OUT_VEC_BASE_OFST 0 12077 /* Number of interrupt vectors allocate to this PF. */ 12078 #define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_PF_OFST 4 12079 /* Number of interrupt vectors to allocate per VF. */ 12080 #define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_VF_OFST 8 12081 12082 12083 /***********************************/ 12084 /* MC_CMD_SET_VECTOR_CFG 12085 * Set Interrupt Vector config for this PF. 12086 */ 12087 #define MC_CMD_SET_VECTOR_CFG 0xc0 12088 #undef MC_CMD_0xc0_PRIVILEGE_CTG 12089 12090 #define MC_CMD_0xc0_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12091 12092 /* MC_CMD_SET_VECTOR_CFG_IN msgrequest */ 12093 #define MC_CMD_SET_VECTOR_CFG_IN_LEN 12 12094 /* Base absolute interrupt vector number, or MC_CMD_RESOURCE_INSTANCE_ANY to 12095 * let the system find a suitable base. 12096 */ 12097 #define MC_CMD_SET_VECTOR_CFG_IN_VEC_BASE_OFST 0 12098 /* Number of interrupt vectors allocate to this PF. */ 12099 #define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_PF_OFST 4 12100 /* Number of interrupt vectors to allocate per VF. */ 12101 #define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_VF_OFST 8 12102 12103 /* MC_CMD_SET_VECTOR_CFG_OUT msgresponse */ 12104 #define MC_CMD_SET_VECTOR_CFG_OUT_LEN 0 12105 12106 12107 /***********************************/ 12108 /* MC_CMD_VPORT_ADD_MAC_ADDRESS 12109 * Add a MAC address to a v-port 12110 */ 12111 #define MC_CMD_VPORT_ADD_MAC_ADDRESS 0xa8 12112 #undef MC_CMD_0xa8_PRIVILEGE_CTG 12113 12114 #define MC_CMD_0xa8_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12115 12116 /* MC_CMD_VPORT_ADD_MAC_ADDRESS_IN msgrequest */ 12117 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN 10 12118 /* The handle of the v-port */ 12119 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID_OFST 0 12120 /* MAC address to add */ 12121 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_MACADDR_OFST 4 12122 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_MACADDR_LEN 6 12123 12124 /* MC_CMD_VPORT_ADD_MAC_ADDRESS_OUT msgresponse */ 12125 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_OUT_LEN 0 12126 12127 12128 /***********************************/ 12129 /* MC_CMD_VPORT_DEL_MAC_ADDRESS 12130 * Delete a MAC address from a v-port 12131 */ 12132 #define MC_CMD_VPORT_DEL_MAC_ADDRESS 0xa9 12133 #undef MC_CMD_0xa9_PRIVILEGE_CTG 12134 12135 #define MC_CMD_0xa9_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12136 12137 /* MC_CMD_VPORT_DEL_MAC_ADDRESS_IN msgrequest */ 12138 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN 10 12139 /* The handle of the v-port */ 12140 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID_OFST 0 12141 /* MAC address to add */ 12142 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_MACADDR_OFST 4 12143 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_MACADDR_LEN 6 12144 12145 /* MC_CMD_VPORT_DEL_MAC_ADDRESS_OUT msgresponse */ 12146 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_OUT_LEN 0 12147 12148 12149 /***********************************/ 12150 /* MC_CMD_VPORT_GET_MAC_ADDRESSES 12151 * Delete a MAC address from a v-port 12152 */ 12153 #define MC_CMD_VPORT_GET_MAC_ADDRESSES 0xaa 12154 #undef MC_CMD_0xaa_PRIVILEGE_CTG 12155 12156 #define MC_CMD_0xaa_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12157 12158 /* MC_CMD_VPORT_GET_MAC_ADDRESSES_IN msgrequest */ 12159 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN 4 12160 /* The handle of the v-port */ 12161 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID_OFST 0 12162 12163 /* MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT msgresponse */ 12164 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN 4 12165 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX 250 12166 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LEN(num) (4+6*(num)) 12167 /* The number of MAC addresses returned */ 12168 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT_OFST 0 12169 /* Array of MAC addresses */ 12170 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_OFST 4 12171 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_LEN 6 12172 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MINNUM 0 12173 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MAXNUM 41 12174 12175 12176 /***********************************/ 12177 /* MC_CMD_VPORT_RECONFIGURE 12178 * Replace VLAN tags and/or MAC addresses of an existing v-port. If the v-port 12179 * has already been passed to another function (v-port's user), then that 12180 * function will be reset before applying the changes. 12181 */ 12182 #define MC_CMD_VPORT_RECONFIGURE 0xeb 12183 #undef MC_CMD_0xeb_PRIVILEGE_CTG 12184 12185 #define MC_CMD_0xeb_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12186 12187 /* MC_CMD_VPORT_RECONFIGURE_IN msgrequest */ 12188 #define MC_CMD_VPORT_RECONFIGURE_IN_LEN 44 12189 /* The handle of the v-port */ 12190 #define MC_CMD_VPORT_RECONFIGURE_IN_VPORT_ID_OFST 0 12191 /* Flags requesting what should be changed. */ 12192 #define MC_CMD_VPORT_RECONFIGURE_IN_FLAGS_OFST 4 12193 #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_VLAN_TAGS_LBN 0 12194 #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_VLAN_TAGS_WIDTH 1 12195 #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_MACADDRS_LBN 1 12196 #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_MACADDRS_WIDTH 1 12197 /* The number of VLAN tags to insert/remove. An error will be returned if 12198 * incompatible with the number of VLAN tags specified for the upstream 12199 * v-switch. 12200 */ 12201 #define MC_CMD_VPORT_RECONFIGURE_IN_NUM_VLAN_TAGS_OFST 8 12202 /* The actual VLAN tags to insert/remove */ 12203 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAGS_OFST 12 12204 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_0_LBN 0 12205 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_0_WIDTH 16 12206 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_1_LBN 16 12207 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_1_WIDTH 16 12208 /* The number of MAC addresses to add */ 12209 #define MC_CMD_VPORT_RECONFIGURE_IN_NUM_MACADDRS_OFST 16 12210 /* MAC addresses to add */ 12211 #define MC_CMD_VPORT_RECONFIGURE_IN_MACADDRS_OFST 20 12212 #define MC_CMD_VPORT_RECONFIGURE_IN_MACADDRS_LEN 6 12213 #define MC_CMD_VPORT_RECONFIGURE_IN_MACADDRS_NUM 4 12214 12215 /* MC_CMD_VPORT_RECONFIGURE_OUT msgresponse */ 12216 #define MC_CMD_VPORT_RECONFIGURE_OUT_LEN 4 12217 #define MC_CMD_VPORT_RECONFIGURE_OUT_FLAGS_OFST 0 12218 #define MC_CMD_VPORT_RECONFIGURE_OUT_RESET_DONE_LBN 0 12219 #define MC_CMD_VPORT_RECONFIGURE_OUT_RESET_DONE_WIDTH 1 12220 12221 12222 /***********************************/ 12223 /* MC_CMD_EVB_PORT_QUERY 12224 * read some config of v-port. 12225 */ 12226 #define MC_CMD_EVB_PORT_QUERY 0x62 12227 #undef MC_CMD_0x62_PRIVILEGE_CTG 12228 12229 #define MC_CMD_0x62_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12230 12231 /* MC_CMD_EVB_PORT_QUERY_IN msgrequest */ 12232 #define MC_CMD_EVB_PORT_QUERY_IN_LEN 4 12233 /* The handle of the v-port */ 12234 #define MC_CMD_EVB_PORT_QUERY_IN_PORT_ID_OFST 0 12235 12236 /* MC_CMD_EVB_PORT_QUERY_OUT msgresponse */ 12237 #define MC_CMD_EVB_PORT_QUERY_OUT_LEN 8 12238 /* The EVB port flags as defined at MC_CMD_VPORT_ALLOC. */ 12239 #define MC_CMD_EVB_PORT_QUERY_OUT_PORT_FLAGS_OFST 0 12240 /* The number of VLAN tags that may be used on a v-adaptor connected to this 12241 * EVB port. 12242 */ 12243 #define MC_CMD_EVB_PORT_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_OFST 4 12244 12245 12246 /***********************************/ 12247 /* MC_CMD_DUMP_BUFTBL_ENTRIES 12248 * Dump buffer table entries, mainly for command client debug use. Dumps 12249 * absolute entries, and does not use chunk handles. All entries must be in 12250 * range, and used for q page mapping, Although the latter restriction may be 12251 * lifted in future. 12252 */ 12253 #define MC_CMD_DUMP_BUFTBL_ENTRIES 0xab 12254 #undef MC_CMD_0xab_PRIVILEGE_CTG 12255 12256 #define MC_CMD_0xab_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12257 12258 /* MC_CMD_DUMP_BUFTBL_ENTRIES_IN msgrequest */ 12259 #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_LEN 8 12260 /* Index of the first buffer table entry. */ 12261 #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_FIRSTID_OFST 0 12262 /* Number of buffer table entries to dump. */ 12263 #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_NUMENTRIES_OFST 4 12264 12265 /* MC_CMD_DUMP_BUFTBL_ENTRIES_OUT msgresponse */ 12266 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LENMIN 12 12267 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LENMAX 252 12268 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LEN(num) (0+12*(num)) 12269 /* Raw buffer table entries, layed out as BUFTBL_ENTRY. */ 12270 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_OFST 0 12271 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_LEN 12 12272 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_MINNUM 1 12273 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_MAXNUM 21 12274 12275 12276 /***********************************/ 12277 /* MC_CMD_SET_RXDP_CONFIG 12278 * Set global RXDP configuration settings 12279 */ 12280 #define MC_CMD_SET_RXDP_CONFIG 0xc1 12281 #undef MC_CMD_0xc1_PRIVILEGE_CTG 12282 12283 #define MC_CMD_0xc1_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12284 12285 /* MC_CMD_SET_RXDP_CONFIG_IN msgrequest */ 12286 #define MC_CMD_SET_RXDP_CONFIG_IN_LEN 4 12287 #define MC_CMD_SET_RXDP_CONFIG_IN_DATA_OFST 0 12288 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_LBN 0 12289 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_WIDTH 1 12290 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_LEN_LBN 1 12291 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_LEN_WIDTH 2 12292 /* enum: pad to 64 bytes */ 12293 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_64 0x0 12294 /* enum: pad to 128 bytes (Medford only) */ 12295 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_128 0x1 12296 /* enum: pad to 256 bytes (Medford only) */ 12297 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_256 0x2 12298 12299 /* MC_CMD_SET_RXDP_CONFIG_OUT msgresponse */ 12300 #define MC_CMD_SET_RXDP_CONFIG_OUT_LEN 0 12301 12302 12303 /***********************************/ 12304 /* MC_CMD_GET_RXDP_CONFIG 12305 * Get global RXDP configuration settings 12306 */ 12307 #define MC_CMD_GET_RXDP_CONFIG 0xc2 12308 #undef MC_CMD_0xc2_PRIVILEGE_CTG 12309 12310 #define MC_CMD_0xc2_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12311 12312 /* MC_CMD_GET_RXDP_CONFIG_IN msgrequest */ 12313 #define MC_CMD_GET_RXDP_CONFIG_IN_LEN 0 12314 12315 /* MC_CMD_GET_RXDP_CONFIG_OUT msgresponse */ 12316 #define MC_CMD_GET_RXDP_CONFIG_OUT_LEN 4 12317 #define MC_CMD_GET_RXDP_CONFIG_OUT_DATA_OFST 0 12318 #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_LBN 0 12319 #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_WIDTH 1 12320 #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_LEN_LBN 1 12321 #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_LEN_WIDTH 2 12322 /* Enum values, see field(s): */ 12323 /* MC_CMD_SET_RXDP_CONFIG/MC_CMD_SET_RXDP_CONFIG_IN/PAD_HOST_LEN */ 12324 12325 12326 /***********************************/ 12327 /* MC_CMD_GET_CLOCK 12328 * Return the system and PDCPU clock frequencies. 12329 */ 12330 #define MC_CMD_GET_CLOCK 0xac 12331 #undef MC_CMD_0xac_PRIVILEGE_CTG 12332 12333 #define MC_CMD_0xac_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12334 12335 /* MC_CMD_GET_CLOCK_IN msgrequest */ 12336 #define MC_CMD_GET_CLOCK_IN_LEN 0 12337 12338 /* MC_CMD_GET_CLOCK_OUT msgresponse */ 12339 #define MC_CMD_GET_CLOCK_OUT_LEN 8 12340 /* System frequency, MHz */ 12341 #define MC_CMD_GET_CLOCK_OUT_SYS_FREQ_OFST 0 12342 /* DPCPU frequency, MHz */ 12343 #define MC_CMD_GET_CLOCK_OUT_DPCPU_FREQ_OFST 4 12344 12345 12346 /***********************************/ 12347 /* MC_CMD_SET_CLOCK 12348 * Control the system and DPCPU clock frequencies. Changes are lost reboot. 12349 */ 12350 #define MC_CMD_SET_CLOCK 0xad 12351 #undef MC_CMD_0xad_PRIVILEGE_CTG 12352 12353 #define MC_CMD_0xad_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12354 12355 /* MC_CMD_SET_CLOCK_IN msgrequest */ 12356 #define MC_CMD_SET_CLOCK_IN_LEN 28 12357 /* Requested frequency in MHz for system clock domain */ 12358 #define MC_CMD_SET_CLOCK_IN_SYS_FREQ_OFST 0 12359 /* enum: Leave the system clock domain frequency unchanged */ 12360 #define MC_CMD_SET_CLOCK_IN_SYS_DOMAIN_DONT_CHANGE 0x0 12361 /* Requested frequency in MHz for inter-core clock domain */ 12362 #define MC_CMD_SET_CLOCK_IN_ICORE_FREQ_OFST 4 12363 /* enum: Leave the inter-core clock domain frequency unchanged */ 12364 #define MC_CMD_SET_CLOCK_IN_ICORE_DOMAIN_DONT_CHANGE 0x0 12365 /* Requested frequency in MHz for DPCPU clock domain */ 12366 #define MC_CMD_SET_CLOCK_IN_DPCPU_FREQ_OFST 8 12367 /* enum: Leave the DPCPU clock domain frequency unchanged */ 12368 #define MC_CMD_SET_CLOCK_IN_DPCPU_DOMAIN_DONT_CHANGE 0x0 12369 /* Requested frequency in MHz for PCS clock domain */ 12370 #define MC_CMD_SET_CLOCK_IN_PCS_FREQ_OFST 12 12371 /* enum: Leave the PCS clock domain frequency unchanged */ 12372 #define MC_CMD_SET_CLOCK_IN_PCS_DOMAIN_DONT_CHANGE 0x0 12373 /* Requested frequency in MHz for MC clock domain */ 12374 #define MC_CMD_SET_CLOCK_IN_MC_FREQ_OFST 16 12375 /* enum: Leave the MC clock domain frequency unchanged */ 12376 #define MC_CMD_SET_CLOCK_IN_MC_DOMAIN_DONT_CHANGE 0x0 12377 /* Requested frequency in MHz for rmon clock domain */ 12378 #define MC_CMD_SET_CLOCK_IN_RMON_FREQ_OFST 20 12379 /* enum: Leave the rmon clock domain frequency unchanged */ 12380 #define MC_CMD_SET_CLOCK_IN_RMON_DOMAIN_DONT_CHANGE 0x0 12381 /* Requested frequency in MHz for vswitch clock domain */ 12382 #define MC_CMD_SET_CLOCK_IN_VSWITCH_FREQ_OFST 24 12383 /* enum: Leave the vswitch clock domain frequency unchanged */ 12384 #define MC_CMD_SET_CLOCK_IN_VSWITCH_DOMAIN_DONT_CHANGE 0x0 12385 12386 /* MC_CMD_SET_CLOCK_OUT msgresponse */ 12387 #define MC_CMD_SET_CLOCK_OUT_LEN 28 12388 /* Resulting system frequency in MHz */ 12389 #define MC_CMD_SET_CLOCK_OUT_SYS_FREQ_OFST 0 12390 /* enum: The system clock domain doesn't exist */ 12391 #define MC_CMD_SET_CLOCK_OUT_SYS_DOMAIN_UNSUPPORTED 0x0 12392 /* Resulting inter-core frequency in MHz */ 12393 #define MC_CMD_SET_CLOCK_OUT_ICORE_FREQ_OFST 4 12394 /* enum: The inter-core clock domain doesn't exist / isn't used */ 12395 #define MC_CMD_SET_CLOCK_OUT_ICORE_DOMAIN_UNSUPPORTED 0x0 12396 /* Resulting DPCPU frequency in MHz */ 12397 #define MC_CMD_SET_CLOCK_OUT_DPCPU_FREQ_OFST 8 12398 /* enum: The dpcpu clock domain doesn't exist */ 12399 #define MC_CMD_SET_CLOCK_OUT_DPCPU_DOMAIN_UNSUPPORTED 0x0 12400 /* Resulting PCS frequency in MHz */ 12401 #define MC_CMD_SET_CLOCK_OUT_PCS_FREQ_OFST 12 12402 /* enum: The PCS clock domain doesn't exist / isn't controlled */ 12403 #define MC_CMD_SET_CLOCK_OUT_PCS_DOMAIN_UNSUPPORTED 0x0 12404 /* Resulting MC frequency in MHz */ 12405 #define MC_CMD_SET_CLOCK_OUT_MC_FREQ_OFST 16 12406 /* enum: The MC clock domain doesn't exist / isn't controlled */ 12407 #define MC_CMD_SET_CLOCK_OUT_MC_DOMAIN_UNSUPPORTED 0x0 12408 /* Resulting rmon frequency in MHz */ 12409 #define MC_CMD_SET_CLOCK_OUT_RMON_FREQ_OFST 20 12410 /* enum: The rmon clock domain doesn't exist / isn't controlled */ 12411 #define MC_CMD_SET_CLOCK_OUT_RMON_DOMAIN_UNSUPPORTED 0x0 12412 /* Resulting vswitch frequency in MHz */ 12413 #define MC_CMD_SET_CLOCK_OUT_VSWITCH_FREQ_OFST 24 12414 /* enum: The vswitch clock domain doesn't exist / isn't controlled */ 12415 #define MC_CMD_SET_CLOCK_OUT_VSWITCH_DOMAIN_UNSUPPORTED 0x0 12416 12417 12418 /***********************************/ 12419 /* MC_CMD_DPCPU_RPC 12420 * Send an arbitrary DPCPU message. 12421 */ 12422 #define MC_CMD_DPCPU_RPC 0xae 12423 #undef MC_CMD_0xae_PRIVILEGE_CTG 12424 12425 #define MC_CMD_0xae_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12426 12427 /* MC_CMD_DPCPU_RPC_IN msgrequest */ 12428 #define MC_CMD_DPCPU_RPC_IN_LEN 36 12429 #define MC_CMD_DPCPU_RPC_IN_CPU_OFST 0 12430 /* enum: RxDPCPU0 */ 12431 #define MC_CMD_DPCPU_RPC_IN_DPCPU_RX0 0x0 12432 /* enum: TxDPCPU0 */ 12433 #define MC_CMD_DPCPU_RPC_IN_DPCPU_TX0 0x1 12434 /* enum: TxDPCPU1 */ 12435 #define MC_CMD_DPCPU_RPC_IN_DPCPU_TX1 0x2 12436 /* enum: RxDPCPU1 (Medford only) */ 12437 #define MC_CMD_DPCPU_RPC_IN_DPCPU_RX1 0x3 12438 /* enum: RxDPCPU (will be for the calling function; for now, just an alias of 12439 * DPCPU_RX0) 12440 */ 12441 #define MC_CMD_DPCPU_RPC_IN_DPCPU_RX 0x80 12442 /* enum: TxDPCPU (will be for the calling function; for now, just an alias of 12443 * DPCPU_TX0) 12444 */ 12445 #define MC_CMD_DPCPU_RPC_IN_DPCPU_TX 0x81 12446 /* First 8 bits [39:32] of DATA are consumed by MC-DPCPU protocol and must be 12447 * initialised to zero 12448 */ 12449 #define MC_CMD_DPCPU_RPC_IN_DATA_OFST 4 12450 #define MC_CMD_DPCPU_RPC_IN_DATA_LEN 32 12451 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_CMDNUM_LBN 8 12452 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_CMDNUM_WIDTH 8 12453 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_READ 0x6 /* enum */ 12454 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_WRITE 0x7 /* enum */ 12455 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_SELF_TEST 0xc /* enum */ 12456 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_CSR_ACCESS 0xe /* enum */ 12457 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_READ 0x46 /* enum */ 12458 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_WRITE 0x47 /* enum */ 12459 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_SELF_TEST 0x4a /* enum */ 12460 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_CSR_ACCESS 0x4c /* enum */ 12461 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_SET_MC_REPLAY_CNTXT 0x4d /* enum */ 12462 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_OBJID_LBN 16 12463 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_OBJID_WIDTH 16 12464 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_ADDR_LBN 16 12465 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_ADDR_WIDTH 16 12466 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_COUNT_LBN 48 12467 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_COUNT_WIDTH 16 12468 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_INFO_LBN 16 12469 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_INFO_WIDTH 240 12470 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_LBN 16 12471 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_WIDTH 16 12472 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_STOP_RETURN_RESULT 0x0 /* enum */ 12473 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_READ 0x1 /* enum */ 12474 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_WRITE 0x2 /* enum */ 12475 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_WRITE_READ 0x3 /* enum */ 12476 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_PIPELINED_READ 0x4 /* enum */ 12477 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_START_DELAY_LBN 48 12478 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_START_DELAY_WIDTH 16 12479 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_RPT_COUNT_LBN 64 12480 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_RPT_COUNT_WIDTH 16 12481 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_GAP_DELAY_LBN 80 12482 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_GAP_DELAY_WIDTH 16 12483 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_LBN 16 12484 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_WIDTH 16 12485 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_CUT_THROUGH 0x1 /* enum */ 12486 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_STORE_FORWARD 0x2 /* enum */ 12487 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_STORE_FORWARD_FIRST 0x3 /* enum */ 12488 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_CNTXT_LBN 64 12489 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_CNTXT_WIDTH 16 12490 #define MC_CMD_DPCPU_RPC_IN_WDATA_OFST 12 12491 #define MC_CMD_DPCPU_RPC_IN_WDATA_LEN 24 12492 /* Register data to write. Only valid in write/write-read. */ 12493 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_DATA_OFST 16 12494 /* Register address. */ 12495 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_ADDRESS_OFST 20 12496 12497 /* MC_CMD_DPCPU_RPC_OUT msgresponse */ 12498 #define MC_CMD_DPCPU_RPC_OUT_LEN 36 12499 #define MC_CMD_DPCPU_RPC_OUT_RC_OFST 0 12500 /* DATA */ 12501 #define MC_CMD_DPCPU_RPC_OUT_DATA_OFST 4 12502 #define MC_CMD_DPCPU_RPC_OUT_DATA_LEN 32 12503 #define MC_CMD_DPCPU_RPC_OUT_HDR_CMD_RESP_ERRCODE_LBN 32 12504 #define MC_CMD_DPCPU_RPC_OUT_HDR_CMD_RESP_ERRCODE_WIDTH 16 12505 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_COUNT_LBN 48 12506 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_COUNT_WIDTH 16 12507 #define MC_CMD_DPCPU_RPC_OUT_RDATA_OFST 12 12508 #define MC_CMD_DPCPU_RPC_OUT_RDATA_LEN 24 12509 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_1_OFST 12 12510 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_2_OFST 16 12511 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_3_OFST 20 12512 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_4_OFST 24 12513 12514 12515 /***********************************/ 12516 /* MC_CMD_TRIGGER_INTERRUPT 12517 * Trigger an interrupt by prodding the BIU. 12518 */ 12519 #define MC_CMD_TRIGGER_INTERRUPT 0xe3 12520 #undef MC_CMD_0xe3_PRIVILEGE_CTG 12521 12522 #define MC_CMD_0xe3_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12523 12524 /* MC_CMD_TRIGGER_INTERRUPT_IN msgrequest */ 12525 #define MC_CMD_TRIGGER_INTERRUPT_IN_LEN 4 12526 /* Interrupt level relative to base for function. */ 12527 #define MC_CMD_TRIGGER_INTERRUPT_IN_INTR_LEVEL_OFST 0 12528 12529 /* MC_CMD_TRIGGER_INTERRUPT_OUT msgresponse */ 12530 #define MC_CMD_TRIGGER_INTERRUPT_OUT_LEN 0 12531 12532 12533 /***********************************/ 12534 /* MC_CMD_SHMBOOT_OP 12535 * Special operations to support (for now) shmboot. 12536 */ 12537 #define MC_CMD_SHMBOOT_OP 0xe6 12538 #undef MC_CMD_0xe6_PRIVILEGE_CTG 12539 12540 #define MC_CMD_0xe6_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12541 12542 /* MC_CMD_SHMBOOT_OP_IN msgrequest */ 12543 #define MC_CMD_SHMBOOT_OP_IN_LEN 4 12544 /* Identifies the operation to perform */ 12545 #define MC_CMD_SHMBOOT_OP_IN_SHMBOOT_OP_OFST 0 12546 /* enum: Copy slave_data section to the slave core. (Greenport only) */ 12547 #define MC_CMD_SHMBOOT_OP_IN_PUSH_SLAVE_DATA 0x0 12548 12549 /* MC_CMD_SHMBOOT_OP_OUT msgresponse */ 12550 #define MC_CMD_SHMBOOT_OP_OUT_LEN 0 12551 12552 12553 /***********************************/ 12554 /* MC_CMD_CAP_BLK_READ 12555 * Read multiple 64bit words from capture block memory 12556 */ 12557 #define MC_CMD_CAP_BLK_READ 0xe7 12558 #undef MC_CMD_0xe7_PRIVILEGE_CTG 12559 12560 #define MC_CMD_0xe7_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12561 12562 /* MC_CMD_CAP_BLK_READ_IN msgrequest */ 12563 #define MC_CMD_CAP_BLK_READ_IN_LEN 12 12564 #define MC_CMD_CAP_BLK_READ_IN_CAP_REG_OFST 0 12565 #define MC_CMD_CAP_BLK_READ_IN_ADDR_OFST 4 12566 #define MC_CMD_CAP_BLK_READ_IN_COUNT_OFST 8 12567 12568 /* MC_CMD_CAP_BLK_READ_OUT msgresponse */ 12569 #define MC_CMD_CAP_BLK_READ_OUT_LENMIN 8 12570 #define MC_CMD_CAP_BLK_READ_OUT_LENMAX 248 12571 #define MC_CMD_CAP_BLK_READ_OUT_LEN(num) (0+8*(num)) 12572 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_OFST 0 12573 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LEN 8 12574 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LO_OFST 0 12575 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_HI_OFST 4 12576 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_MINNUM 1 12577 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_MAXNUM 31 12578 12579 12580 /***********************************/ 12581 /* MC_CMD_DUMP_DO 12582 * Take a dump of the DUT state 12583 */ 12584 #define MC_CMD_DUMP_DO 0xe8 12585 #undef MC_CMD_0xe8_PRIVILEGE_CTG 12586 12587 #define MC_CMD_0xe8_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12588 12589 /* MC_CMD_DUMP_DO_IN msgrequest */ 12590 #define MC_CMD_DUMP_DO_IN_LEN 52 12591 #define MC_CMD_DUMP_DO_IN_PADDING_OFST 0 12592 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_OFST 4 12593 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM 0x0 /* enum */ 12594 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_DEFAULT 0x1 /* enum */ 12595 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_TYPE_OFST 8 12596 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_NVRAM 0x1 /* enum */ 12597 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_HOST_MEMORY 0x2 /* enum */ 12598 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_HOST_MEMORY_MLI 0x3 /* enum */ 12599 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_UART 0x4 /* enum */ 12600 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 12 12601 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_OFST 16 12602 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 12 12603 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 16 12604 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 12 12605 #define MC_CMD_DUMP_DO_IN_HOST_MEMORY_MLI_PAGE_SIZE 0x1000 /* enum */ 12606 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 16 12607 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 20 12608 #define MC_CMD_DUMP_DO_IN_HOST_MEMORY_MLI_MAX_DEPTH 0x2 /* enum */ 12609 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_OFST 12 12610 /* enum: The uart port this command was received over (if using a uart 12611 * transport) 12612 */ 12613 #define MC_CMD_DUMP_DO_IN_UART_PORT_SRC 0xff 12614 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_SIZE_OFST 24 12615 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_OFST 28 12616 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM 0x0 /* enum */ 12617 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_NVRAM_DUMP_PARTITION 0x1 /* enum */ 12618 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_TYPE_OFST 32 12619 /* Enum values, see field(s): */ 12620 /* MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */ 12621 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 36 12622 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_OFST 40 12623 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 36 12624 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 40 12625 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 36 12626 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 40 12627 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 44 12628 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_UART_PORT_OFST 36 12629 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_SIZE_OFST 48 12630 12631 /* MC_CMD_DUMP_DO_OUT msgresponse */ 12632 #define MC_CMD_DUMP_DO_OUT_LEN 4 12633 #define MC_CMD_DUMP_DO_OUT_DUMPFILE_SIZE_OFST 0 12634 12635 12636 /***********************************/ 12637 /* MC_CMD_DUMP_CONFIGURE_UNSOLICITED 12638 * Configure unsolicited dumps 12639 */ 12640 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED 0xe9 12641 #undef MC_CMD_0xe9_PRIVILEGE_CTG 12642 12643 #define MC_CMD_0xe9_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12644 12645 /* MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN msgrequest */ 12646 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_LEN 52 12647 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_ENABLE_OFST 0 12648 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_OFST 4 12649 /* Enum values, see field(s): */ 12650 /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC */ 12651 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_TYPE_OFST 8 12652 /* Enum values, see field(s): */ 12653 /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */ 12654 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 12 12655 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_OFST 16 12656 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 12 12657 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 16 12658 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 12 12659 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 16 12660 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 20 12661 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_OFST 12 12662 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_SIZE_OFST 24 12663 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_OFST 28 12664 /* Enum values, see field(s): */ 12665 /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPFILE_DST */ 12666 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_TYPE_OFST 32 12667 /* Enum values, see field(s): */ 12668 /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */ 12669 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 36 12670 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_OFST 40 12671 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 36 12672 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 40 12673 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 36 12674 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 40 12675 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 44 12676 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_UART_PORT_OFST 36 12677 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_SIZE_OFST 48 12678 12679 12680 /***********************************/ 12681 /* MC_CMD_SET_PSU 12682 * Adjusts power supply parameters. This is a warranty-voiding operation. 12683 * Returns: ENOENT if the parameter or rail specified does not exist, EINVAL if 12684 * the parameter is out of range. 12685 */ 12686 #define MC_CMD_SET_PSU 0xea 12687 #undef MC_CMD_0xea_PRIVILEGE_CTG 12688 12689 #define MC_CMD_0xea_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12690 12691 /* MC_CMD_SET_PSU_IN msgrequest */ 12692 #define MC_CMD_SET_PSU_IN_LEN 12 12693 #define MC_CMD_SET_PSU_IN_PARAM_OFST 0 12694 #define MC_CMD_SET_PSU_IN_PARAM_SUPPLY_VOLTAGE 0x0 /* enum */ 12695 #define MC_CMD_SET_PSU_IN_RAIL_OFST 4 12696 #define MC_CMD_SET_PSU_IN_RAIL_0V9 0x0 /* enum */ 12697 #define MC_CMD_SET_PSU_IN_RAIL_1V2 0x1 /* enum */ 12698 /* desired value, eg voltage in mV */ 12699 #define MC_CMD_SET_PSU_IN_VALUE_OFST 8 12700 12701 /* MC_CMD_SET_PSU_OUT msgresponse */ 12702 #define MC_CMD_SET_PSU_OUT_LEN 0 12703 12704 12705 /***********************************/ 12706 /* MC_CMD_GET_FUNCTION_INFO 12707 * Get function information. PF and VF number. 12708 */ 12709 #define MC_CMD_GET_FUNCTION_INFO 0xec 12710 #undef MC_CMD_0xec_PRIVILEGE_CTG 12711 12712 #define MC_CMD_0xec_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12713 12714 /* MC_CMD_GET_FUNCTION_INFO_IN msgrequest */ 12715 #define MC_CMD_GET_FUNCTION_INFO_IN_LEN 0 12716 12717 /* MC_CMD_GET_FUNCTION_INFO_OUT msgresponse */ 12718 #define MC_CMD_GET_FUNCTION_INFO_OUT_LEN 8 12719 #define MC_CMD_GET_FUNCTION_INFO_OUT_PF_OFST 0 12720 #define MC_CMD_GET_FUNCTION_INFO_OUT_VF_OFST 4 12721 12722 12723 /***********************************/ 12724 /* MC_CMD_ENABLE_OFFLINE_BIST 12725 * Enters offline BIST mode. All queues are torn down, chip enters quiescent 12726 * mode, calling function gets exclusive MCDI ownership. The only way out is 12727 * reboot. 12728 */ 12729 #define MC_CMD_ENABLE_OFFLINE_BIST 0xed 12730 #undef MC_CMD_0xed_PRIVILEGE_CTG 12731 12732 #define MC_CMD_0xed_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12733 12734 /* MC_CMD_ENABLE_OFFLINE_BIST_IN msgrequest */ 12735 #define MC_CMD_ENABLE_OFFLINE_BIST_IN_LEN 0 12736 12737 /* MC_CMD_ENABLE_OFFLINE_BIST_OUT msgresponse */ 12738 #define MC_CMD_ENABLE_OFFLINE_BIST_OUT_LEN 0 12739 12740 12741 /***********************************/ 12742 /* MC_CMD_UART_SEND_DATA 12743 * Send checksummed[sic] block of data over the uart. Response is a placeholder 12744 * should we wish to make this reliable; currently requests are fire-and- 12745 * forget. 12746 */ 12747 #define MC_CMD_UART_SEND_DATA 0xee 12748 #undef MC_CMD_0xee_PRIVILEGE_CTG 12749 12750 #define MC_CMD_0xee_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12751 12752 /* MC_CMD_UART_SEND_DATA_OUT msgrequest */ 12753 #define MC_CMD_UART_SEND_DATA_OUT_LENMIN 16 12754 #define MC_CMD_UART_SEND_DATA_OUT_LENMAX 252 12755 #define MC_CMD_UART_SEND_DATA_OUT_LEN(num) (16+1*(num)) 12756 /* CRC32 over OFFSET, LENGTH, RESERVED, DATA */ 12757 #define MC_CMD_UART_SEND_DATA_OUT_CHECKSUM_OFST 0 12758 /* Offset at which to write the data */ 12759 #define MC_CMD_UART_SEND_DATA_OUT_OFFSET_OFST 4 12760 /* Length of data */ 12761 #define MC_CMD_UART_SEND_DATA_OUT_LENGTH_OFST 8 12762 /* Reserved for future use */ 12763 #define MC_CMD_UART_SEND_DATA_OUT_RESERVED_OFST 12 12764 #define MC_CMD_UART_SEND_DATA_OUT_DATA_OFST 16 12765 #define MC_CMD_UART_SEND_DATA_OUT_DATA_LEN 1 12766 #define MC_CMD_UART_SEND_DATA_OUT_DATA_MINNUM 0 12767 #define MC_CMD_UART_SEND_DATA_OUT_DATA_MAXNUM 236 12768 12769 /* MC_CMD_UART_SEND_DATA_IN msgresponse */ 12770 #define MC_CMD_UART_SEND_DATA_IN_LEN 0 12771 12772 12773 /***********************************/ 12774 /* MC_CMD_UART_RECV_DATA 12775 * Request checksummed[sic] block of data over the uart. Only a placeholder, 12776 * subject to change and not currently implemented. 12777 */ 12778 #define MC_CMD_UART_RECV_DATA 0xef 12779 #undef MC_CMD_0xef_PRIVILEGE_CTG 12780 12781 #define MC_CMD_0xef_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12782 12783 /* MC_CMD_UART_RECV_DATA_OUT msgrequest */ 12784 #define MC_CMD_UART_RECV_DATA_OUT_LEN 16 12785 /* CRC32 over OFFSET, LENGTH, RESERVED */ 12786 #define MC_CMD_UART_RECV_DATA_OUT_CHECKSUM_OFST 0 12787 /* Offset from which to read the data */ 12788 #define MC_CMD_UART_RECV_DATA_OUT_OFFSET_OFST 4 12789 /* Length of data */ 12790 #define MC_CMD_UART_RECV_DATA_OUT_LENGTH_OFST 8 12791 /* Reserved for future use */ 12792 #define MC_CMD_UART_RECV_DATA_OUT_RESERVED_OFST 12 12793 12794 /* MC_CMD_UART_RECV_DATA_IN msgresponse */ 12795 #define MC_CMD_UART_RECV_DATA_IN_LENMIN 16 12796 #define MC_CMD_UART_RECV_DATA_IN_LENMAX 252 12797 #define MC_CMD_UART_RECV_DATA_IN_LEN(num) (16+1*(num)) 12798 /* CRC32 over RESERVED1, RESERVED2, RESERVED3, DATA */ 12799 #define MC_CMD_UART_RECV_DATA_IN_CHECKSUM_OFST 0 12800 /* Offset at which to write the data */ 12801 #define MC_CMD_UART_RECV_DATA_IN_RESERVED1_OFST 4 12802 /* Length of data */ 12803 #define MC_CMD_UART_RECV_DATA_IN_RESERVED2_OFST 8 12804 /* Reserved for future use */ 12805 #define MC_CMD_UART_RECV_DATA_IN_RESERVED3_OFST 12 12806 #define MC_CMD_UART_RECV_DATA_IN_DATA_OFST 16 12807 #define MC_CMD_UART_RECV_DATA_IN_DATA_LEN 1 12808 #define MC_CMD_UART_RECV_DATA_IN_DATA_MINNUM 0 12809 #define MC_CMD_UART_RECV_DATA_IN_DATA_MAXNUM 236 12810 12811 12812 /***********************************/ 12813 /* MC_CMD_READ_FUSES 12814 * Read data programmed into the device One-Time-Programmable (OTP) Fuses 12815 */ 12816 #define MC_CMD_READ_FUSES 0xf0 12817 #undef MC_CMD_0xf0_PRIVILEGE_CTG 12818 12819 #define MC_CMD_0xf0_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12820 12821 /* MC_CMD_READ_FUSES_IN msgrequest */ 12822 #define MC_CMD_READ_FUSES_IN_LEN 8 12823 /* Offset in OTP to read */ 12824 #define MC_CMD_READ_FUSES_IN_OFFSET_OFST 0 12825 /* Length of data to read in bytes */ 12826 #define MC_CMD_READ_FUSES_IN_LENGTH_OFST 4 12827 12828 /* MC_CMD_READ_FUSES_OUT msgresponse */ 12829 #define MC_CMD_READ_FUSES_OUT_LENMIN 4 12830 #define MC_CMD_READ_FUSES_OUT_LENMAX 252 12831 #define MC_CMD_READ_FUSES_OUT_LEN(num) (4+1*(num)) 12832 /* Length of returned OTP data in bytes */ 12833 #define MC_CMD_READ_FUSES_OUT_LENGTH_OFST 0 12834 /* Returned data */ 12835 #define MC_CMD_READ_FUSES_OUT_DATA_OFST 4 12836 #define MC_CMD_READ_FUSES_OUT_DATA_LEN 1 12837 #define MC_CMD_READ_FUSES_OUT_DATA_MINNUM 0 12838 #define MC_CMD_READ_FUSES_OUT_DATA_MAXNUM 248 12839 12840 12841 /***********************************/ 12842 /* MC_CMD_KR_TUNE 12843 * Get or set KR Serdes RXEQ and TX Driver settings 12844 */ 12845 #define MC_CMD_KR_TUNE 0xf1 12846 #undef MC_CMD_0xf1_PRIVILEGE_CTG 12847 12848 #define MC_CMD_0xf1_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12849 12850 /* MC_CMD_KR_TUNE_IN msgrequest */ 12851 #define MC_CMD_KR_TUNE_IN_LENMIN 4 12852 #define MC_CMD_KR_TUNE_IN_LENMAX 252 12853 #define MC_CMD_KR_TUNE_IN_LEN(num) (4+4*(num)) 12854 /* Requested operation */ 12855 #define MC_CMD_KR_TUNE_IN_KR_TUNE_OP_OFST 0 12856 #define MC_CMD_KR_TUNE_IN_KR_TUNE_OP_LEN 1 12857 /* enum: Get current RXEQ settings */ 12858 #define MC_CMD_KR_TUNE_IN_RXEQ_GET 0x0 12859 /* enum: Override RXEQ settings */ 12860 #define MC_CMD_KR_TUNE_IN_RXEQ_SET 0x1 12861 /* enum: Get current TX Driver settings */ 12862 #define MC_CMD_KR_TUNE_IN_TXEQ_GET 0x2 12863 /* enum: Override TX Driver settings */ 12864 #define MC_CMD_KR_TUNE_IN_TXEQ_SET 0x3 12865 /* enum: Force KR Serdes reset / recalibration */ 12866 #define MC_CMD_KR_TUNE_IN_RECAL 0x4 12867 /* enum: Start KR Serdes Eye diagram plot on a given lane. Lane must have valid 12868 * signal. 12869 */ 12870 #define MC_CMD_KR_TUNE_IN_START_EYE_PLOT 0x5 12871 /* enum: Poll KR Serdes Eye diagram plot. Returns one row of BER data. The 12872 * caller should call this command repeatedly after starting eye plot, until no 12873 * more data is returned. 12874 */ 12875 #define MC_CMD_KR_TUNE_IN_POLL_EYE_PLOT 0x6 12876 /* enum: Read Figure Of Merit (eye quality, higher is better). */ 12877 #define MC_CMD_KR_TUNE_IN_READ_FOM 0x7 12878 /* Align the arguments to 32 bits */ 12879 #define MC_CMD_KR_TUNE_IN_KR_TUNE_RSVD_OFST 1 12880 #define MC_CMD_KR_TUNE_IN_KR_TUNE_RSVD_LEN 3 12881 /* Arguments specific to the operation */ 12882 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_OFST 4 12883 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_LEN 4 12884 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_MINNUM 0 12885 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_MAXNUM 62 12886 12887 /* MC_CMD_KR_TUNE_OUT msgresponse */ 12888 #define MC_CMD_KR_TUNE_OUT_LEN 0 12889 12890 /* MC_CMD_KR_TUNE_RXEQ_GET_IN msgrequest */ 12891 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_LEN 4 12892 /* Requested operation */ 12893 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_OP_OFST 0 12894 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_OP_LEN 1 12895 /* Align the arguments to 32 bits */ 12896 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_RSVD_OFST 1 12897 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_RSVD_LEN 3 12898 12899 /* MC_CMD_KR_TUNE_RXEQ_GET_OUT msgresponse */ 12900 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LENMIN 4 12901 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LENMAX 252 12902 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LEN(num) (0+4*(num)) 12903 /* RXEQ Parameter */ 12904 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_OFST 0 12905 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LEN 4 12906 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_MINNUM 1 12907 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_MAXNUM 63 12908 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_LBN 0 12909 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_WIDTH 8 12910 /* enum: Attenuation (0-15, Huntington) */ 12911 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_ATT 0x0 12912 /* enum: CTLE Boost (0-15, Huntington) */ 12913 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_BOOST 0x1 12914 /* enum: Edge DFE Tap1 (Huntington - 0 - max negative, 64 - zero, 127 - max 12915 * positive, Medford - 0-31) 12916 */ 12917 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP1 0x2 12918 /* enum: Edge DFE Tap2 (Huntington - 0 - max negative, 32 - zero, 63 - max 12919 * positive, Medford - 0-31) 12920 */ 12921 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP2 0x3 12922 /* enum: Edge DFE Tap3 (Huntington - 0 - max negative, 32 - zero, 63 - max 12923 * positive, Medford - 0-16) 12924 */ 12925 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP3 0x4 12926 /* enum: Edge DFE Tap4 (Huntington - 0 - max negative, 32 - zero, 63 - max 12927 * positive, Medford - 0-16) 12928 */ 12929 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP4 0x5 12930 /* enum: Edge DFE Tap5 (Huntington - 0 - max negative, 32 - zero, 63 - max 12931 * positive, Medford - 0-16) 12932 */ 12933 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP5 0x6 12934 /* enum: Edge DFE DLEV (0-128 for Medford) */ 12935 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_DLEV 0x7 12936 /* enum: Variable Gain Amplifier (0-15, Medford) */ 12937 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_VGA 0x8 12938 /* enum: CTLE EQ Capacitor (0-15, Medford) */ 12939 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_EQC 0x9 12940 /* enum: CTLE EQ Resistor (0-7, Medford) */ 12941 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_EQRES 0xa 12942 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_LBN 8 12943 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_WIDTH 3 12944 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */ 12945 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_1 0x1 /* enum */ 12946 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_2 0x2 /* enum */ 12947 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_3 0x3 /* enum */ 12948 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_ALL 0x4 /* enum */ 12949 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_LBN 11 12950 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_WIDTH 1 12951 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_RESERVED_LBN 12 12952 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_RESERVED_WIDTH 4 12953 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_INITIAL_LBN 16 12954 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_INITIAL_WIDTH 8 12955 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_LBN 24 12956 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8 12957 12958 /* MC_CMD_KR_TUNE_RXEQ_SET_IN msgrequest */ 12959 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_LENMIN 8 12960 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_LENMAX 252 12961 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_LEN(num) (4+4*(num)) 12962 /* Requested operation */ 12963 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_OP_OFST 0 12964 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_OP_LEN 1 12965 /* Align the arguments to 32 bits */ 12966 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_RSVD_OFST 1 12967 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_RSVD_LEN 3 12968 /* RXEQ Parameter */ 12969 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_OFST 4 12970 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LEN 4 12971 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_MINNUM 1 12972 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_MAXNUM 62 12973 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_ID_LBN 0 12974 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_ID_WIDTH 8 12975 /* Enum values, see field(s): */ 12976 /* MC_CMD_KR_TUNE_RXEQ_GET_OUT/PARAM_ID */ 12977 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LANE_LBN 8 12978 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LANE_WIDTH 3 12979 /* Enum values, see field(s): */ 12980 /* MC_CMD_KR_TUNE_RXEQ_GET_OUT/PARAM_LANE */ 12981 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_LBN 11 12982 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_WIDTH 1 12983 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED_LBN 12 12984 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED_WIDTH 4 12985 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_INITIAL_LBN 16 12986 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_INITIAL_WIDTH 8 12987 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED2_LBN 24 12988 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED2_WIDTH 8 12989 12990 /* MC_CMD_KR_TUNE_RXEQ_SET_OUT msgresponse */ 12991 #define MC_CMD_KR_TUNE_RXEQ_SET_OUT_LEN 0 12992 12993 /* MC_CMD_KR_TUNE_TXEQ_GET_IN msgrequest */ 12994 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_LEN 4 12995 /* Requested operation */ 12996 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_OP_OFST 0 12997 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_OP_LEN 1 12998 /* Align the arguments to 32 bits */ 12999 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_RSVD_OFST 1 13000 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_RSVD_LEN 3 13001 13002 /* MC_CMD_KR_TUNE_TXEQ_GET_OUT msgresponse */ 13003 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LENMIN 4 13004 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LENMAX 252 13005 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LEN(num) (0+4*(num)) 13006 /* TXEQ Parameter */ 13007 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_OFST 0 13008 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LEN 4 13009 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_MINNUM 1 13010 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_MAXNUM 63 13011 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_LBN 0 13012 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_WIDTH 8 13013 /* enum: TX Amplitude (Huntington, Medford) */ 13014 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV 0x0 13015 /* enum: De-Emphasis Tap1 Magnitude (0-7) (Huntington) */ 13016 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_MODE 0x1 13017 /* enum: De-Emphasis Tap1 Fine */ 13018 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_DTLEV 0x2 13019 /* enum: De-Emphasis Tap2 Magnitude (0-6) (Huntington) */ 13020 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_D2 0x3 13021 /* enum: De-Emphasis Tap2 Fine (Huntington) */ 13022 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_D2TLEV 0x4 13023 /* enum: Pre-Emphasis Magnitude (Huntington) */ 13024 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_E 0x5 13025 /* enum: Pre-Emphasis Fine (Huntington) */ 13026 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_ETLEV 0x6 13027 /* enum: TX Slew Rate Coarse control (Huntington) */ 13028 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_PREDRV_DLY 0x7 13029 /* enum: TX Slew Rate Fine control (Huntington) */ 13030 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_SR_SET 0x8 13031 /* enum: TX Termination Impedance control (Huntington) */ 13032 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_RT_SET 0x9 13033 /* enum: TX Amplitude Fine control (Medford) */ 13034 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV_FINE 0xa 13035 /* enum: Pre-shoot Tap (Medford) */ 13036 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_ADV 0xb 13037 /* enum: De-emphasis Tap (Medford) */ 13038 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_DLY 0xc 13039 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LANE_LBN 8 13040 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LANE_WIDTH 3 13041 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_0 0x0 /* enum */ 13042 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_1 0x1 /* enum */ 13043 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_2 0x2 /* enum */ 13044 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_3 0x3 /* enum */ 13045 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_ALL 0x4 /* enum */ 13046 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED_LBN 11 13047 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED_WIDTH 5 13048 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_INITIAL_LBN 16 13049 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_INITIAL_WIDTH 8 13050 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED2_LBN 24 13051 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED2_WIDTH 8 13052 13053 /* MC_CMD_KR_TUNE_TXEQ_SET_IN msgrequest */ 13054 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_LENMIN 8 13055 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_LENMAX 252 13056 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_LEN(num) (4+4*(num)) 13057 /* Requested operation */ 13058 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_OP_OFST 0 13059 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_OP_LEN 1 13060 /* Align the arguments to 32 bits */ 13061 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_RSVD_OFST 1 13062 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_RSVD_LEN 3 13063 /* TXEQ Parameter */ 13064 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_OFST 4 13065 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LEN 4 13066 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_MINNUM 1 13067 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_MAXNUM 62 13068 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_ID_LBN 0 13069 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_ID_WIDTH 8 13070 /* Enum values, see field(s): */ 13071 /* MC_CMD_KR_TUNE_TXEQ_GET_OUT/PARAM_ID */ 13072 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LANE_LBN 8 13073 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LANE_WIDTH 3 13074 /* Enum values, see field(s): */ 13075 /* MC_CMD_KR_TUNE_TXEQ_GET_OUT/PARAM_LANE */ 13076 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED_LBN 11 13077 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED_WIDTH 5 13078 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_INITIAL_LBN 16 13079 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_INITIAL_WIDTH 8 13080 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED2_LBN 24 13081 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED2_WIDTH 8 13082 13083 /* MC_CMD_KR_TUNE_TXEQ_SET_OUT msgresponse */ 13084 #define MC_CMD_KR_TUNE_TXEQ_SET_OUT_LEN 0 13085 13086 /* MC_CMD_KR_TUNE_RECAL_IN msgrequest */ 13087 #define MC_CMD_KR_TUNE_RECAL_IN_LEN 4 13088 /* Requested operation */ 13089 #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_OP_OFST 0 13090 #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_OP_LEN 1 13091 /* Align the arguments to 32 bits */ 13092 #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_RSVD_OFST 1 13093 #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_RSVD_LEN 3 13094 13095 /* MC_CMD_KR_TUNE_RECAL_OUT msgresponse */ 13096 #define MC_CMD_KR_TUNE_RECAL_OUT_LEN 0 13097 13098 /* MC_CMD_KR_TUNE_START_EYE_PLOT_IN msgrequest */ 13099 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_LEN 8 13100 /* Requested operation */ 13101 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_OP_OFST 0 13102 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_OP_LEN 1 13103 /* Align the arguments to 32 bits */ 13104 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_RSVD_OFST 1 13105 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_RSVD_LEN 3 13106 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_LANE_OFST 4 13107 13108 /* MC_CMD_KR_TUNE_START_EYE_PLOT_OUT msgresponse */ 13109 #define MC_CMD_KR_TUNE_START_EYE_PLOT_OUT_LEN 0 13110 13111 /* MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN msgrequest */ 13112 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_LEN 4 13113 /* Requested operation */ 13114 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_OP_OFST 0 13115 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_OP_LEN 1 13116 /* Align the arguments to 32 bits */ 13117 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_RSVD_OFST 1 13118 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_RSVD_LEN 3 13119 13120 /* MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT msgresponse */ 13121 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LENMIN 0 13122 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LENMAX 252 13123 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LEN(num) (0+2*(num)) 13124 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_OFST 0 13125 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_LEN 2 13126 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MINNUM 0 13127 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MAXNUM 126 13128 13129 /* MC_CMD_KR_TUNE_READ_FOM_IN msgrequest */ 13130 #define MC_CMD_KR_TUNE_READ_FOM_IN_LEN 8 13131 /* Requested operation */ 13132 #define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_OP_OFST 0 13133 #define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_OP_LEN 1 13134 /* Align the arguments to 32 bits */ 13135 #define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_RSVD_OFST 1 13136 #define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_RSVD_LEN 3 13137 #define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_OFST 4 13138 13139 /* MC_CMD_KR_TUNE_READ_FOM_OUT msgresponse */ 13140 #define MC_CMD_KR_TUNE_READ_FOM_OUT_LEN 4 13141 #define MC_CMD_KR_TUNE_READ_FOM_OUT_FOM_OFST 0 13142 13143 13144 /***********************************/ 13145 /* MC_CMD_PCIE_TUNE 13146 * Get or set PCIE Serdes RXEQ and TX Driver settings 13147 */ 13148 #define MC_CMD_PCIE_TUNE 0xf2 13149 #undef MC_CMD_0xf2_PRIVILEGE_CTG 13150 13151 #define MC_CMD_0xf2_PRIVILEGE_CTG SRIOV_CTG_ADMIN 13152 13153 /* MC_CMD_PCIE_TUNE_IN msgrequest */ 13154 #define MC_CMD_PCIE_TUNE_IN_LENMIN 4 13155 #define MC_CMD_PCIE_TUNE_IN_LENMAX 252 13156 #define MC_CMD_PCIE_TUNE_IN_LEN(num) (4+4*(num)) 13157 /* Requested operation */ 13158 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_OP_OFST 0 13159 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_OP_LEN 1 13160 /* enum: Get current RXEQ settings */ 13161 #define MC_CMD_PCIE_TUNE_IN_RXEQ_GET 0x0 13162 /* enum: Override RXEQ settings */ 13163 #define MC_CMD_PCIE_TUNE_IN_RXEQ_SET 0x1 13164 /* enum: Get current TX Driver settings */ 13165 #define MC_CMD_PCIE_TUNE_IN_TXEQ_GET 0x2 13166 /* enum: Override TX Driver settings */ 13167 #define MC_CMD_PCIE_TUNE_IN_TXEQ_SET 0x3 13168 /* enum: Start PCIe Serdes Eye diagram plot on a given lane. */ 13169 #define MC_CMD_PCIE_TUNE_IN_START_EYE_PLOT 0x5 13170 /* enum: Poll PCIe Serdes Eye diagram plot. Returns one row of BER data. The 13171 * caller should call this command repeatedly after starting eye plot, until no 13172 * more data is returned. 13173 */ 13174 #define MC_CMD_PCIE_TUNE_IN_POLL_EYE_PLOT 0x6 13175 /* enum: Enable the SERDES BIST and set it to generate a 200MHz square wave */ 13176 #define MC_CMD_PCIE_TUNE_IN_BIST_SQUARE_WAVE 0x7 13177 /* Align the arguments to 32 bits */ 13178 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_RSVD_OFST 1 13179 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_RSVD_LEN 3 13180 /* Arguments specific to the operation */ 13181 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_OFST 4 13182 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_LEN 4 13183 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_MINNUM 0 13184 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_MAXNUM 62 13185 13186 /* MC_CMD_PCIE_TUNE_OUT msgresponse */ 13187 #define MC_CMD_PCIE_TUNE_OUT_LEN 0 13188 13189 /* MC_CMD_PCIE_TUNE_RXEQ_GET_IN msgrequest */ 13190 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_LEN 4 13191 /* Requested operation */ 13192 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_OP_OFST 0 13193 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_OP_LEN 1 13194 /* Align the arguments to 32 bits */ 13195 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_RSVD_OFST 1 13196 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_RSVD_LEN 3 13197 13198 /* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT msgresponse */ 13199 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LENMIN 4 13200 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LENMAX 252 13201 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LEN(num) (0+4*(num)) 13202 /* RXEQ Parameter */ 13203 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_OFST 0 13204 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LEN 4 13205 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_MINNUM 1 13206 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_MAXNUM 63 13207 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_ID_LBN 0 13208 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_ID_WIDTH 8 13209 /* enum: Attenuation (0-15) */ 13210 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_ATT 0x0 13211 /* enum: CTLE Boost (0-15) */ 13212 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_BOOST 0x1 13213 /* enum: DFE Tap1 (0 - max negative, 64 - zero, 127 - max positive) */ 13214 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP1 0x2 13215 /* enum: DFE Tap2 (0 - max negative, 32 - zero, 63 - max positive) */ 13216 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP2 0x3 13217 /* enum: DFE Tap3 (0 - max negative, 32 - zero, 63 - max positive) */ 13218 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP3 0x4 13219 /* enum: DFE Tap4 (0 - max negative, 32 - zero, 63 - max positive) */ 13220 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP4 0x5 13221 /* enum: DFE Tap5 (0 - max negative, 32 - zero, 63 - max positive) */ 13222 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP5 0x6 13223 /* enum: DFE DLev */ 13224 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_DLEV 0x7 13225 /* enum: Figure of Merit */ 13226 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_FOM 0x8 13227 /* enum: CTLE EQ Capacitor (HF Gain) */ 13228 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_CTLE_EQC 0x9 13229 /* enum: CTLE EQ Resistor (DC Gain) */ 13230 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_CTLE_EQRES 0xa 13231 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_LBN 8 13232 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_WIDTH 5 13233 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */ 13234 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_1 0x1 /* enum */ 13235 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_2 0x2 /* enum */ 13236 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_3 0x3 /* enum */ 13237 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_4 0x4 /* enum */ 13238 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_5 0x5 /* enum */ 13239 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_6 0x6 /* enum */ 13240 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_7 0x7 /* enum */ 13241 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_8 0x8 /* enum */ 13242 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_9 0x9 /* enum */ 13243 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_10 0xa /* enum */ 13244 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_11 0xb /* enum */ 13245 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_12 0xc /* enum */ 13246 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_13 0xd /* enum */ 13247 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_14 0xe /* enum */ 13248 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_15 0xf /* enum */ 13249 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_ALL 0x10 /* enum */ 13250 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_LBN 13 13251 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_WIDTH 1 13252 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_LBN 14 13253 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_WIDTH 10 13254 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_LBN 24 13255 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8 13256 13257 /* MC_CMD_PCIE_TUNE_RXEQ_SET_IN msgrequest */ 13258 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LENMIN 8 13259 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LENMAX 252 13260 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LEN(num) (4+4*(num)) 13261 /* Requested operation */ 13262 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_OP_OFST 0 13263 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_OP_LEN 1 13264 /* Align the arguments to 32 bits */ 13265 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_RSVD_OFST 1 13266 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_RSVD_LEN 3 13267 /* RXEQ Parameter */ 13268 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_OFST 4 13269 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LEN 4 13270 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_MINNUM 1 13271 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_MAXNUM 62 13272 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_ID_LBN 0 13273 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_ID_WIDTH 8 13274 /* Enum values, see field(s): */ 13275 /* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_ID */ 13276 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LANE_LBN 8 13277 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LANE_WIDTH 5 13278 /* Enum values, see field(s): */ 13279 /* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_LANE */ 13280 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_LBN 13 13281 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_WIDTH 1 13282 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED_LBN 14 13283 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED_WIDTH 2 13284 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_INITIAL_LBN 16 13285 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_INITIAL_WIDTH 8 13286 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED2_LBN 24 13287 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED2_WIDTH 8 13288 13289 /* MC_CMD_PCIE_TUNE_RXEQ_SET_OUT msgresponse */ 13290 #define MC_CMD_PCIE_TUNE_RXEQ_SET_OUT_LEN 0 13291 13292 /* MC_CMD_PCIE_TUNE_TXEQ_GET_IN msgrequest */ 13293 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_LEN 4 13294 /* Requested operation */ 13295 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_OP_OFST 0 13296 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_OP_LEN 1 13297 /* Align the arguments to 32 bits */ 13298 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_RSVD_OFST 1 13299 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_RSVD_LEN 3 13300 13301 /* MC_CMD_PCIE_TUNE_TXEQ_GET_OUT msgresponse */ 13302 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LENMIN 4 13303 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LENMAX 252 13304 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LEN(num) (0+4*(num)) 13305 /* RXEQ Parameter */ 13306 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_OFST 0 13307 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LEN 4 13308 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_MINNUM 1 13309 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_MAXNUM 63 13310 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_ID_LBN 0 13311 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_ID_WIDTH 8 13312 /* enum: TxMargin (PIPE) */ 13313 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_TXMARGIN 0x0 13314 /* enum: TxSwing (PIPE) */ 13315 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_TXSWING 0x1 13316 /* enum: De-emphasis coefficient C(-1) (PIPE) */ 13317 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_CM1 0x2 13318 /* enum: De-emphasis coefficient C(0) (PIPE) */ 13319 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_C0 0x3 13320 /* enum: De-emphasis coefficient C(+1) (PIPE) */ 13321 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_CP1 0x4 13322 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LANE_LBN 8 13323 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LANE_WIDTH 4 13324 /* Enum values, see field(s): */ 13325 /* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_LANE */ 13326 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_RESERVED_LBN 12 13327 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_RESERVED_WIDTH 12 13328 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_CURRENT_LBN 24 13329 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8 13330 13331 /* MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN msgrequest */ 13332 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_LEN 8 13333 /* Requested operation */ 13334 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_OP_OFST 0 13335 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_OP_LEN 1 13336 /* Align the arguments to 32 bits */ 13337 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_RSVD_OFST 1 13338 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_RSVD_LEN 3 13339 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_LANE_OFST 4 13340 13341 /* MC_CMD_PCIE_TUNE_START_EYE_PLOT_OUT msgresponse */ 13342 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_OUT_LEN 0 13343 13344 /* MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN msgrequest */ 13345 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_LEN 4 13346 /* Requested operation */ 13347 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_OP_OFST 0 13348 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_OP_LEN 1 13349 /* Align the arguments to 32 bits */ 13350 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_RSVD_OFST 1 13351 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_RSVD_LEN 3 13352 13353 /* MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT msgresponse */ 13354 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LENMIN 0 13355 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LENMAX 252 13356 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LEN(num) (0+2*(num)) 13357 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_OFST 0 13358 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_LEN 2 13359 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MINNUM 0 13360 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MAXNUM 126 13361 13362 /* MC_CMD_PCIE_TUNE_BIST_SQUARE_WAVE_IN msgrequest */ 13363 #define MC_CMD_PCIE_TUNE_BIST_SQUARE_WAVE_IN_LEN 0 13364 13365 /* MC_CMD_PCIE_TUNE_BIST_SQUARE_WAVE_OUT msgrequest */ 13366 #define MC_CMD_PCIE_TUNE_BIST_SQUARE_WAVE_OUT_LEN 0 13367 13368 13369 /***********************************/ 13370 /* MC_CMD_LICENSING 13371 * Operations on the NVRAM_PARTITION_TYPE_LICENSE application license partition 13372 * - not used for V3 licensing 13373 */ 13374 #define MC_CMD_LICENSING 0xf3 13375 #undef MC_CMD_0xf3_PRIVILEGE_CTG 13376 13377 #define MC_CMD_0xf3_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13378 13379 /* MC_CMD_LICENSING_IN msgrequest */ 13380 #define MC_CMD_LICENSING_IN_LEN 4 13381 /* identifies the type of operation requested */ 13382 #define MC_CMD_LICENSING_IN_OP_OFST 0 13383 /* enum: re-read and apply licenses after a license key partition update; note 13384 * that this operation returns a zero-length response 13385 */ 13386 #define MC_CMD_LICENSING_IN_OP_UPDATE_LICENSE 0x0 13387 /* enum: report counts of installed licenses */ 13388 #define MC_CMD_LICENSING_IN_OP_GET_KEY_STATS 0x1 13389 13390 /* MC_CMD_LICENSING_OUT msgresponse */ 13391 #define MC_CMD_LICENSING_OUT_LEN 28 13392 /* count of application keys which are valid */ 13393 #define MC_CMD_LICENSING_OUT_VALID_APP_KEYS_OFST 0 13394 /* sum of UNVERIFIABLE_APP_KEYS + WRONG_NODE_APP_KEYS (for compatibility with 13395 * MC_CMD_FC_OP_LICENSE) 13396 */ 13397 #define MC_CMD_LICENSING_OUT_INVALID_APP_KEYS_OFST 4 13398 /* count of application keys which are invalid due to being blacklisted */ 13399 #define MC_CMD_LICENSING_OUT_BLACKLISTED_APP_KEYS_OFST 8 13400 /* count of application keys which are invalid due to being unverifiable */ 13401 #define MC_CMD_LICENSING_OUT_UNVERIFIABLE_APP_KEYS_OFST 12 13402 /* count of application keys which are invalid due to being for the wrong node 13403 */ 13404 #define MC_CMD_LICENSING_OUT_WRONG_NODE_APP_KEYS_OFST 16 13405 /* licensing state (for diagnostics; the exact meaning of the bits in this 13406 * field are private to the firmware) 13407 */ 13408 #define MC_CMD_LICENSING_OUT_LICENSING_STATE_OFST 20 13409 /* licensing subsystem self-test report (for manftest) */ 13410 #define MC_CMD_LICENSING_OUT_LICENSING_SELF_TEST_OFST 24 13411 /* enum: licensing subsystem self-test failed */ 13412 #define MC_CMD_LICENSING_OUT_SELF_TEST_FAIL 0x0 13413 /* enum: licensing subsystem self-test passed */ 13414 #define MC_CMD_LICENSING_OUT_SELF_TEST_PASS 0x1 13415 13416 13417 /***********************************/ 13418 /* MC_CMD_LICENSING_V3 13419 * Operations on the NVRAM_PARTITION_TYPE_LICENSE application license partition 13420 * - V3 licensing (Medford) 13421 */ 13422 #define MC_CMD_LICENSING_V3 0xd0 13423 #undef MC_CMD_0xd0_PRIVILEGE_CTG 13424 13425 #define MC_CMD_0xd0_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13426 13427 /* MC_CMD_LICENSING_V3_IN msgrequest */ 13428 #define MC_CMD_LICENSING_V3_IN_LEN 4 13429 /* identifies the type of operation requested */ 13430 #define MC_CMD_LICENSING_V3_IN_OP_OFST 0 13431 /* enum: re-read and apply licenses after a license key partition update; note 13432 * that this operation returns a zero-length response 13433 */ 13434 #define MC_CMD_LICENSING_V3_IN_OP_UPDATE_LICENSE 0x0 13435 /* enum: report counts of installed licenses Returns EAGAIN if license 13436 * processing (updating) has been started but not yet completed. 13437 */ 13438 #define MC_CMD_LICENSING_V3_IN_OP_REPORT_LICENSE 0x1 13439 13440 /* MC_CMD_LICENSING_V3_OUT msgresponse */ 13441 #define MC_CMD_LICENSING_V3_OUT_LEN 88 13442 /* count of keys which are valid */ 13443 #define MC_CMD_LICENSING_V3_OUT_VALID_KEYS_OFST 0 13444 /* sum of UNVERIFIABLE_KEYS + WRONG_NODE_KEYS (for compatibility with 13445 * MC_CMD_FC_OP_LICENSE) 13446 */ 13447 #define MC_CMD_LICENSING_V3_OUT_INVALID_KEYS_OFST 4 13448 /* count of keys which are invalid due to being unverifiable */ 13449 #define MC_CMD_LICENSING_V3_OUT_UNVERIFIABLE_KEYS_OFST 8 13450 /* count of keys which are invalid due to being for the wrong node */ 13451 #define MC_CMD_LICENSING_V3_OUT_WRONG_NODE_KEYS_OFST 12 13452 /* licensing state (for diagnostics; the exact meaning of the bits in this 13453 * field are private to the firmware) 13454 */ 13455 #define MC_CMD_LICENSING_V3_OUT_LICENSING_STATE_OFST 16 13456 /* licensing subsystem self-test report (for manftest) */ 13457 #define MC_CMD_LICENSING_V3_OUT_LICENSING_SELF_TEST_OFST 20 13458 /* enum: licensing subsystem self-test failed */ 13459 #define MC_CMD_LICENSING_V3_OUT_SELF_TEST_FAIL 0x0 13460 /* enum: licensing subsystem self-test passed */ 13461 #define MC_CMD_LICENSING_V3_OUT_SELF_TEST_PASS 0x1 13462 /* bitmask of licensed applications */ 13463 #define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_OFST 24 13464 #define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LEN 8 13465 #define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LO_OFST 24 13466 #define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_HI_OFST 28 13467 /* reserved for future use */ 13468 #define MC_CMD_LICENSING_V3_OUT_RESERVED_0_OFST 32 13469 #define MC_CMD_LICENSING_V3_OUT_RESERVED_0_LEN 24 13470 /* bitmask of licensed features */ 13471 #define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_OFST 56 13472 #define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LEN 8 13473 #define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LO_OFST 56 13474 #define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_HI_OFST 60 13475 /* reserved for future use */ 13476 #define MC_CMD_LICENSING_V3_OUT_RESERVED_1_OFST 64 13477 #define MC_CMD_LICENSING_V3_OUT_RESERVED_1_LEN 24 13478 13479 13480 /***********************************/ 13481 /* MC_CMD_LICENSING_GET_ID_V3 13482 * Get ID and type from the NVRAM_PARTITION_TYPE_LICENSE application license 13483 * partition - V3 licensing (Medford) 13484 */ 13485 #define MC_CMD_LICENSING_GET_ID_V3 0xd1 13486 #undef MC_CMD_0xd1_PRIVILEGE_CTG 13487 13488 #define MC_CMD_0xd1_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13489 13490 /* MC_CMD_LICENSING_GET_ID_V3_IN msgrequest */ 13491 #define MC_CMD_LICENSING_GET_ID_V3_IN_LEN 0 13492 13493 /* MC_CMD_LICENSING_GET_ID_V3_OUT msgresponse */ 13494 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LENMIN 8 13495 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LENMAX 252 13496 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LEN(num) (8+1*(num)) 13497 /* type of license (eg 3) */ 13498 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_TYPE_OFST 0 13499 /* length of the license ID (in bytes) */ 13500 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_LENGTH_OFST 4 13501 /* the unique license ID of the adapter */ 13502 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_OFST 8 13503 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_LEN 1 13504 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_MINNUM 0 13505 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_MAXNUM 244 13506 13507 13508 /***********************************/ 13509 /* MC_CMD_MC2MC_PROXY 13510 * Execute an arbitrary MCDI command on the slave MC of a dual-core device. 13511 * This will fail on a single-core system. 13512 */ 13513 #define MC_CMD_MC2MC_PROXY 0xf4 13514 #undef MC_CMD_0xf4_PRIVILEGE_CTG 13515 13516 #define MC_CMD_0xf4_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13517 13518 /* MC_CMD_MC2MC_PROXY_IN msgrequest */ 13519 #define MC_CMD_MC2MC_PROXY_IN_LEN 0 13520 13521 /* MC_CMD_MC2MC_PROXY_OUT msgresponse */ 13522 #define MC_CMD_MC2MC_PROXY_OUT_LEN 0 13523 13524 13525 /***********************************/ 13526 /* MC_CMD_GET_LICENSED_APP_STATE 13527 * Query the state of an individual licensed application. (Note that the actual 13528 * state may be invalidated by the MC_CMD_LICENSING OP_UPDATE_LICENSE operation 13529 * or a reboot of the MC.) Not used for V3 licensing 13530 */ 13531 #define MC_CMD_GET_LICENSED_APP_STATE 0xf5 13532 #undef MC_CMD_0xf5_PRIVILEGE_CTG 13533 13534 #define MC_CMD_0xf5_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13535 13536 /* MC_CMD_GET_LICENSED_APP_STATE_IN msgrequest */ 13537 #define MC_CMD_GET_LICENSED_APP_STATE_IN_LEN 4 13538 /* application ID to query (LICENSED_APP_ID_xxx) */ 13539 #define MC_CMD_GET_LICENSED_APP_STATE_IN_APP_ID_OFST 0 13540 13541 /* MC_CMD_GET_LICENSED_APP_STATE_OUT msgresponse */ 13542 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_LEN 4 13543 /* state of this application */ 13544 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_STATE_OFST 0 13545 /* enum: no (or invalid) license is present for the application */ 13546 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_NOT_LICENSED 0x0 13547 /* enum: a valid license is present for the application */ 13548 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_LICENSED 0x1 13549 13550 13551 /***********************************/ 13552 /* MC_CMD_GET_LICENSED_V3_APP_STATE 13553 * Query the state of an individual licensed application. (Note that the actual 13554 * state may be invalidated by the MC_CMD_LICENSING_V3 OP_UPDATE_LICENSE 13555 * operation or a reboot of the MC.) Used for V3 licensing (Medford) 13556 */ 13557 #define MC_CMD_GET_LICENSED_V3_APP_STATE 0xd2 13558 #undef MC_CMD_0xd2_PRIVILEGE_CTG 13559 13560 #define MC_CMD_0xd2_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13561 13562 /* MC_CMD_GET_LICENSED_V3_APP_STATE_IN msgrequest */ 13563 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_LEN 8 13564 /* application ID to query (LICENSED_V3_APPS_xxx) expressed as a single bit 13565 * mask 13566 */ 13567 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_OFST 0 13568 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LEN 8 13569 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LO_OFST 0 13570 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_HI_OFST 4 13571 13572 /* MC_CMD_GET_LICENSED_V3_APP_STATE_OUT msgresponse */ 13573 #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_LEN 4 13574 /* state of this application */ 13575 #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_STATE_OFST 0 13576 /* enum: no (or invalid) license is present for the application */ 13577 #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_NOT_LICENSED 0x0 13578 /* enum: a valid license is present for the application */ 13579 #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_LICENSED 0x1 13580 13581 13582 /***********************************/ 13583 /* MC_CMD_GET_LICENSED_V3_FEATURE_STATES 13584 * Query the state of an one or more licensed features. (Note that the actual 13585 * state may be invalidated by the MC_CMD_LICENSING_V3 OP_UPDATE_LICENSE 13586 * operation or a reboot of the MC.) Used for V3 licensing (Medford) 13587 */ 13588 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES 0xd3 13589 #undef MC_CMD_0xd3_PRIVILEGE_CTG 13590 13591 #define MC_CMD_0xd3_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13592 13593 /* MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN msgrequest */ 13594 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_LEN 8 13595 /* features to query (LICENSED_V3_FEATURES_xxx) expressed as a mask with one or 13596 * more bits set 13597 */ 13598 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_OFST 0 13599 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LEN 8 13600 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LO_OFST 0 13601 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_HI_OFST 4 13602 13603 /* MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT msgresponse */ 13604 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_LEN 8 13605 /* states of these features - bit set for licensed, clear for not licensed */ 13606 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_OFST 0 13607 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LEN 8 13608 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LO_OFST 0 13609 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_HI_OFST 4 13610 13611 13612 /***********************************/ 13613 /* MC_CMD_LICENSED_APP_OP 13614 * Perform an action for an individual licensed application - not used for V3 13615 * licensing. 13616 */ 13617 #define MC_CMD_LICENSED_APP_OP 0xf6 13618 #undef MC_CMD_0xf6_PRIVILEGE_CTG 13619 13620 #define MC_CMD_0xf6_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13621 13622 /* MC_CMD_LICENSED_APP_OP_IN msgrequest */ 13623 #define MC_CMD_LICENSED_APP_OP_IN_LENMIN 8 13624 #define MC_CMD_LICENSED_APP_OP_IN_LENMAX 252 13625 #define MC_CMD_LICENSED_APP_OP_IN_LEN(num) (8+4*(num)) 13626 /* application ID */ 13627 #define MC_CMD_LICENSED_APP_OP_IN_APP_ID_OFST 0 13628 /* the type of operation requested */ 13629 #define MC_CMD_LICENSED_APP_OP_IN_OP_OFST 4 13630 /* enum: validate application */ 13631 #define MC_CMD_LICENSED_APP_OP_IN_OP_VALIDATE 0x0 13632 /* enum: mask application */ 13633 #define MC_CMD_LICENSED_APP_OP_IN_OP_MASK 0x1 13634 /* arguments specific to this particular operation */ 13635 #define MC_CMD_LICENSED_APP_OP_IN_ARGS_OFST 8 13636 #define MC_CMD_LICENSED_APP_OP_IN_ARGS_LEN 4 13637 #define MC_CMD_LICENSED_APP_OP_IN_ARGS_MINNUM 0 13638 #define MC_CMD_LICENSED_APP_OP_IN_ARGS_MAXNUM 61 13639 13640 /* MC_CMD_LICENSED_APP_OP_OUT msgresponse */ 13641 #define MC_CMD_LICENSED_APP_OP_OUT_LENMIN 0 13642 #define MC_CMD_LICENSED_APP_OP_OUT_LENMAX 252 13643 #define MC_CMD_LICENSED_APP_OP_OUT_LEN(num) (0+4*(num)) 13644 /* result specific to this particular operation */ 13645 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_OFST 0 13646 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_LEN 4 13647 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_MINNUM 0 13648 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_MAXNUM 63 13649 13650 /* MC_CMD_LICENSED_APP_OP_VALIDATE_IN msgrequest */ 13651 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_LEN 72 13652 /* application ID */ 13653 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_APP_ID_OFST 0 13654 /* the type of operation requested */ 13655 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_OP_OFST 4 13656 /* validation challenge */ 13657 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_CHALLENGE_OFST 8 13658 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_CHALLENGE_LEN 64 13659 13660 /* MC_CMD_LICENSED_APP_OP_VALIDATE_OUT msgresponse */ 13661 #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_LEN 68 13662 /* feature expiry (time_t) */ 13663 #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_EXPIRY_OFST 0 13664 /* validation response */ 13665 #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_RESPONSE_OFST 4 13666 #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_RESPONSE_LEN 64 13667 13668 /* MC_CMD_LICENSED_APP_OP_MASK_IN msgrequest */ 13669 #define MC_CMD_LICENSED_APP_OP_MASK_IN_LEN 12 13670 /* application ID */ 13671 #define MC_CMD_LICENSED_APP_OP_MASK_IN_APP_ID_OFST 0 13672 /* the type of operation requested */ 13673 #define MC_CMD_LICENSED_APP_OP_MASK_IN_OP_OFST 4 13674 /* flag */ 13675 #define MC_CMD_LICENSED_APP_OP_MASK_IN_FLAG_OFST 8 13676 13677 /* MC_CMD_LICENSED_APP_OP_MASK_OUT msgresponse */ 13678 #define MC_CMD_LICENSED_APP_OP_MASK_OUT_LEN 0 13679 13680 13681 /***********************************/ 13682 /* MC_CMD_LICENSED_V3_VALIDATE_APP 13683 * Perform validation for an individual licensed application - V3 licensing 13684 * (Medford) 13685 */ 13686 #define MC_CMD_LICENSED_V3_VALIDATE_APP 0xd4 13687 #undef MC_CMD_0xd4_PRIVILEGE_CTG 13688 13689 #define MC_CMD_0xd4_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13690 13691 /* MC_CMD_LICENSED_V3_VALIDATE_APP_IN msgrequest */ 13692 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_LEN 56 13693 /* challenge for validation (384 bits) */ 13694 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_CHALLENGE_OFST 0 13695 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_CHALLENGE_LEN 48 13696 /* application ID expressed as a single bit mask */ 13697 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_OFST 48 13698 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LEN 8 13699 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LO_OFST 48 13700 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_HI_OFST 52 13701 13702 /* MC_CMD_LICENSED_V3_VALIDATE_APP_OUT msgresponse */ 13703 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_LEN 116 13704 /* validation response to challenge in the form of ECDSA signature consisting 13705 * of two 384-bit integers, r and s, in big-endian order. The signature signs a 13706 * SHA-384 digest of a message constructed from the concatenation of the input 13707 * message and the remaining fields of this output message, e.g. challenge[48 13708 * bytes] ... expiry_time[4 bytes] ... 13709 */ 13710 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_RESPONSE_OFST 0 13711 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_RESPONSE_LEN 96 13712 /* application expiry time */ 13713 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_TIME_OFST 96 13714 /* application expiry units */ 13715 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNITS_OFST 100 13716 /* enum: expiry units are accounting units */ 13717 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNIT_ACC 0x0 13718 /* enum: expiry units are calendar days */ 13719 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNIT_DAYS 0x1 13720 /* base MAC address of the NIC stored in NVRAM (note that this is a constant 13721 * value for a given NIC regardless which function is calling, effectively this 13722 * is PF0 base MAC address) 13723 */ 13724 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_BASE_MACADDR_OFST 104 13725 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_BASE_MACADDR_LEN 6 13726 /* MAC address of v-adaptor associated with the client. If no such v-adapator 13727 * exists, then the field is filled with 0xFF. 13728 */ 13729 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_VADAPTOR_MACADDR_OFST 110 13730 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_VADAPTOR_MACADDR_LEN 6 13731 13732 13733 /***********************************/ 13734 /* MC_CMD_LICENSED_V3_MASK_FEATURES 13735 * Mask features - V3 licensing (Medford) 13736 */ 13737 #define MC_CMD_LICENSED_V3_MASK_FEATURES 0xd5 13738 #undef MC_CMD_0xd5_PRIVILEGE_CTG 13739 13740 #define MC_CMD_0xd5_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13741 13742 /* MC_CMD_LICENSED_V3_MASK_FEATURES_IN msgrequest */ 13743 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_LEN 12 13744 /* mask to be applied to features to be changed */ 13745 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_OFST 0 13746 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LEN 8 13747 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LO_OFST 0 13748 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_HI_OFST 4 13749 /* whether to turn on or turn off the masked features */ 13750 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_FLAG_OFST 8 13751 /* enum: turn the features off */ 13752 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_OFF 0x0 13753 /* enum: turn the features back on */ 13754 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_ON 0x1 13755 13756 /* MC_CMD_LICENSED_V3_MASK_FEATURES_OUT msgresponse */ 13757 #define MC_CMD_LICENSED_V3_MASK_FEATURES_OUT_LEN 0 13758 13759 13760 /***********************************/ 13761 /* MC_CMD_LICENSING_V3_TEMPORARY 13762 * Perform operations to support installation of a single temporary license in 13763 * the adapter, in addition to those found in the licensing partition. See 13764 * SF-116124-SW for an overview of how this could be used. The license is 13765 * stored in MC persistent data and so will survive a MC reboot, but will be 13766 * erased when the adapter is power cycled 13767 */ 13768 #define MC_CMD_LICENSING_V3_TEMPORARY 0xd6 13769 #undef MC_CMD_0xd6_PRIVILEGE_CTG 13770 13771 #define MC_CMD_0xd6_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13772 13773 /* MC_CMD_LICENSING_V3_TEMPORARY_IN msgrequest */ 13774 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_LEN 4 13775 /* operation code */ 13776 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_OP_OFST 0 13777 /* enum: install a new license, overwriting any existing temporary license. 13778 * This is an asynchronous operation owing to the time taken to validate an 13779 * ECDSA license 13780 */ 13781 #define MC_CMD_LICENSING_V3_TEMPORARY_SET 0x0 13782 /* enum: clear the license immediately rather than waiting for the next power 13783 * cycle 13784 */ 13785 #define MC_CMD_LICENSING_V3_TEMPORARY_CLEAR 0x1 13786 /* enum: get the status of the asynchronous MC_CMD_LICENSING_V3_TEMPORARY_SET 13787 * operation 13788 */ 13789 #define MC_CMD_LICENSING_V3_TEMPORARY_STATUS 0x2 13790 13791 /* MC_CMD_LICENSING_V3_TEMPORARY_IN_SET msgrequest */ 13792 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_LEN 164 13793 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_OP_OFST 0 13794 /* ECDSA license and signature */ 13795 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_LICENSE_OFST 4 13796 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_LICENSE_LEN 160 13797 13798 /* MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR msgrequest */ 13799 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR_LEN 4 13800 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR_OP_OFST 0 13801 13802 /* MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS msgrequest */ 13803 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS_LEN 4 13804 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS_OP_OFST 0 13805 13806 /* MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS msgresponse */ 13807 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LEN 12 13808 /* status code */ 13809 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_STATUS_OFST 0 13810 /* enum: finished validating and installing license */ 13811 #define MC_CMD_LICENSING_V3_TEMPORARY_STATUS_OK 0x0 13812 /* enum: license validation and installation in progress */ 13813 #define MC_CMD_LICENSING_V3_TEMPORARY_STATUS_IN_PROGRESS 0x1 13814 /* enum: licensing error. More specific error messages are not provided to 13815 * avoid exposing details of the licensing system to the client 13816 */ 13817 #define MC_CMD_LICENSING_V3_TEMPORARY_STATUS_ERROR 0x2 13818 /* bitmask of licensed features */ 13819 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_OFST 4 13820 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_LEN 8 13821 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_LO_OFST 4 13822 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_HI_OFST 8 13823 13824 13825 /***********************************/ 13826 /* MC_CMD_SET_PORT_SNIFF_CONFIG 13827 * Configure RX port sniffing for the physical port associated with the calling 13828 * function. Only a privileged function may change the port sniffing 13829 * configuration. A copy of all traffic delivered to the host (non-promiscuous 13830 * mode) or all traffic arriving at the port (promiscuous mode) may be 13831 * delivered to a specific queue, or a set of queues with RSS. 13832 */ 13833 #define MC_CMD_SET_PORT_SNIFF_CONFIG 0xf7 13834 #undef MC_CMD_0xf7_PRIVILEGE_CTG 13835 13836 #define MC_CMD_0xf7_PRIVILEGE_CTG SRIOV_CTG_ADMIN 13837 13838 /* MC_CMD_SET_PORT_SNIFF_CONFIG_IN msgrequest */ 13839 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_LEN 16 13840 /* configuration flags */ 13841 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_FLAGS_OFST 0 13842 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_ENABLE_LBN 0 13843 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_ENABLE_WIDTH 1 13844 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_PROMISCUOUS_LBN 1 13845 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_PROMISCUOUS_WIDTH 1 13846 /* receive queue handle (for RSS mode, this is the base queue) */ 13847 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_QUEUE_OFST 4 13848 /* receive mode */ 13849 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_OFST 8 13850 /* enum: receive to just the specified queue */ 13851 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_SIMPLE 0x0 13852 /* enum: receive to multiple queues using RSS context */ 13853 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_RSS 0x1 13854 /* RSS context (for RX_MODE_RSS) as returned by MC_CMD_RSS_CONTEXT_ALLOC. Note 13855 * that these handles should be considered opaque to the host, although a value 13856 * of 0xFFFFFFFF is guaranteed never to be a valid handle. 13857 */ 13858 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_OFST 12 13859 13860 /* MC_CMD_SET_PORT_SNIFF_CONFIG_OUT msgresponse */ 13861 #define MC_CMD_SET_PORT_SNIFF_CONFIG_OUT_LEN 0 13862 13863 13864 /***********************************/ 13865 /* MC_CMD_GET_PORT_SNIFF_CONFIG 13866 * Obtain the current RX port sniffing configuration for the physical port 13867 * associated with the calling function. Only a privileged function may read 13868 * the configuration. 13869 */ 13870 #define MC_CMD_GET_PORT_SNIFF_CONFIG 0xf8 13871 #undef MC_CMD_0xf8_PRIVILEGE_CTG 13872 13873 #define MC_CMD_0xf8_PRIVILEGE_CTG SRIOV_CTG_ADMIN 13874 13875 /* MC_CMD_GET_PORT_SNIFF_CONFIG_IN msgrequest */ 13876 #define MC_CMD_GET_PORT_SNIFF_CONFIG_IN_LEN 0 13877 13878 /* MC_CMD_GET_PORT_SNIFF_CONFIG_OUT msgresponse */ 13879 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_LEN 16 13880 /* configuration flags */ 13881 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_FLAGS_OFST 0 13882 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_ENABLE_LBN 0 13883 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_ENABLE_WIDTH 1 13884 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_PROMISCUOUS_LBN 1 13885 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_PROMISCUOUS_WIDTH 1 13886 /* receiving queue handle (for RSS mode, this is the base queue) */ 13887 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_OFST 4 13888 /* receive mode */ 13889 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_OFST 8 13890 /* enum: receiving to just the specified queue */ 13891 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_SIMPLE 0x0 13892 /* enum: receiving to multiple queues using RSS context */ 13893 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_RSS 0x1 13894 /* RSS context (for RX_MODE_RSS) */ 13895 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_OFST 12 13896 13897 13898 /***********************************/ 13899 /* MC_CMD_SET_PARSER_DISP_CONFIG 13900 * Change configuration related to the parser-dispatcher subsystem. 13901 */ 13902 #define MC_CMD_SET_PARSER_DISP_CONFIG 0xf9 13903 #undef MC_CMD_0xf9_PRIVILEGE_CTG 13904 13905 #define MC_CMD_0xf9_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13906 13907 /* MC_CMD_SET_PARSER_DISP_CONFIG_IN msgrequest */ 13908 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LENMIN 12 13909 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LENMAX 252 13910 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LEN(num) (8+4*(num)) 13911 /* the type of configuration setting to change */ 13912 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_TYPE_OFST 0 13913 /* enum: Per-TXQ enable for multicast UDP destination lookup for possible 13914 * internal loopback. (ENTITY is a queue handle, VALUE is a single boolean.) 13915 */ 13916 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_TXQ_MCAST_UDP_DST_LOOKUP_EN 0x0 13917 /* enum: Per-v-adaptor enable for suppression of self-transmissions on the 13918 * internal loopback path. (ENTITY is an EVB_PORT_ID, VALUE is a single 13919 * boolean.) 13920 */ 13921 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VADAPTOR_SUPPRESS_SELF_TX 0x1 13922 /* handle for the entity to update: queue handle, EVB port ID, etc. depending 13923 * on the type of configuration setting being changed 13924 */ 13925 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_ENTITY_OFST 4 13926 /* new value: the details depend on the type of configuration setting being 13927 * changed 13928 */ 13929 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_OFST 8 13930 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_LEN 4 13931 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_MINNUM 1 13932 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_MAXNUM 61 13933 13934 /* MC_CMD_SET_PARSER_DISP_CONFIG_OUT msgresponse */ 13935 #define MC_CMD_SET_PARSER_DISP_CONFIG_OUT_LEN 0 13936 13937 13938 /***********************************/ 13939 /* MC_CMD_GET_PARSER_DISP_CONFIG 13940 * Read configuration related to the parser-dispatcher subsystem. 13941 */ 13942 #define MC_CMD_GET_PARSER_DISP_CONFIG 0xfa 13943 #undef MC_CMD_0xfa_PRIVILEGE_CTG 13944 13945 #define MC_CMD_0xfa_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13946 13947 /* MC_CMD_GET_PARSER_DISP_CONFIG_IN msgrequest */ 13948 #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_LEN 8 13949 /* the type of configuration setting to read */ 13950 #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_TYPE_OFST 0 13951 /* Enum values, see field(s): */ 13952 /* MC_CMD_SET_PARSER_DISP_CONFIG/MC_CMD_SET_PARSER_DISP_CONFIG_IN/TYPE */ 13953 /* handle for the entity to query: queue handle, EVB port ID, etc. depending on 13954 * the type of configuration setting being read 13955 */ 13956 #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_ENTITY_OFST 4 13957 13958 /* MC_CMD_GET_PARSER_DISP_CONFIG_OUT msgresponse */ 13959 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LENMIN 4 13960 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LENMAX 252 13961 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LEN(num) (0+4*(num)) 13962 /* current value: the details depend on the type of configuration setting being 13963 * read 13964 */ 13965 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_OFST 0 13966 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_LEN 4 13967 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_MINNUM 1 13968 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_MAXNUM 63 13969 13970 13971 /***********************************/ 13972 /* MC_CMD_SET_TX_PORT_SNIFF_CONFIG 13973 * Configure TX port sniffing for the physical port associated with the calling 13974 * function. Only a privileged function may change the port sniffing 13975 * configuration. A copy of all traffic transmitted through the port may be 13976 * delivered to a specific queue, or a set of queues with RSS. Note that these 13977 * packets are delivered with transmit timestamps in the packet prefix, not 13978 * receive timestamps, so it is likely that the queue(s) will need to be 13979 * dedicated as TX sniff receivers. 13980 */ 13981 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG 0xfb 13982 #undef MC_CMD_0xfb_PRIVILEGE_CTG 13983 13984 #define MC_CMD_0xfb_PRIVILEGE_CTG SRIOV_CTG_ADMIN 13985 13986 /* MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN msgrequest */ 13987 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_LEN 16 13988 /* configuration flags */ 13989 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_FLAGS_OFST 0 13990 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_ENABLE_LBN 0 13991 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_ENABLE_WIDTH 1 13992 /* receive queue handle (for RSS mode, this is the base queue) */ 13993 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_QUEUE_OFST 4 13994 /* receive mode */ 13995 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_OFST 8 13996 /* enum: receive to just the specified queue */ 13997 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_SIMPLE 0x0 13998 /* enum: receive to multiple queues using RSS context */ 13999 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_RSS 0x1 14000 /* RSS context (for RX_MODE_RSS) as returned by MC_CMD_RSS_CONTEXT_ALLOC. Note 14001 * that these handles should be considered opaque to the host, although a value 14002 * of 0xFFFFFFFF is guaranteed never to be a valid handle. 14003 */ 14004 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_OFST 12 14005 14006 /* MC_CMD_SET_TX_PORT_SNIFF_CONFIG_OUT msgresponse */ 14007 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_OUT_LEN 0 14008 14009 14010 /***********************************/ 14011 /* MC_CMD_GET_TX_PORT_SNIFF_CONFIG 14012 * Obtain the current TX port sniffing configuration for the physical port 14013 * associated with the calling function. Only a privileged function may read 14014 * the configuration. 14015 */ 14016 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG 0xfc 14017 #undef MC_CMD_0xfc_PRIVILEGE_CTG 14018 14019 #define MC_CMD_0xfc_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14020 14021 /* MC_CMD_GET_TX_PORT_SNIFF_CONFIG_IN msgrequest */ 14022 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_IN_LEN 0 14023 14024 /* MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT msgresponse */ 14025 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_LEN 16 14026 /* configuration flags */ 14027 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_FLAGS_OFST 0 14028 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_ENABLE_LBN 0 14029 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_ENABLE_WIDTH 1 14030 /* receiving queue handle (for RSS mode, this is the base queue) */ 14031 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_OFST 4 14032 /* receive mode */ 14033 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_OFST 8 14034 /* enum: receiving to just the specified queue */ 14035 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_SIMPLE 0x0 14036 /* enum: receiving to multiple queues using RSS context */ 14037 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_RSS 0x1 14038 /* RSS context (for RX_MODE_RSS) */ 14039 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_OFST 12 14040 14041 14042 /***********************************/ 14043 /* MC_CMD_RMON_STATS_RX_ERRORS 14044 * Per queue rx error stats. 14045 */ 14046 #define MC_CMD_RMON_STATS_RX_ERRORS 0xfe 14047 #undef MC_CMD_0xfe_PRIVILEGE_CTG 14048 14049 #define MC_CMD_0xfe_PRIVILEGE_CTG SRIOV_CTG_GENERAL 14050 14051 /* MC_CMD_RMON_STATS_RX_ERRORS_IN msgrequest */ 14052 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_LEN 8 14053 /* The rx queue to get stats for. */ 14054 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_RX_QUEUE_OFST 0 14055 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_FLAGS_OFST 4 14056 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_RST_LBN 0 14057 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_RST_WIDTH 1 14058 14059 /* MC_CMD_RMON_STATS_RX_ERRORS_OUT msgresponse */ 14060 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_LEN 16 14061 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_CRC_ERRORS_OFST 0 14062 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_TRUNC_ERRORS_OFST 4 14063 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_NO_DESC_DROPS_OFST 8 14064 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_ABORT_OFST 12 14065 14066 14067 /***********************************/ 14068 /* MC_CMD_GET_PCIE_RESOURCE_INFO 14069 * Find out about available PCIE resources 14070 */ 14071 #define MC_CMD_GET_PCIE_RESOURCE_INFO 0xfd 14072 14073 /* MC_CMD_GET_PCIE_RESOURCE_INFO_IN msgrequest */ 14074 #define MC_CMD_GET_PCIE_RESOURCE_INFO_IN_LEN 0 14075 14076 /* MC_CMD_GET_PCIE_RESOURCE_INFO_OUT msgresponse */ 14077 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_LEN 28 14078 /* The maximum number of PFs the device can expose */ 14079 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PFS_OFST 0 14080 /* The maximum number of VFs the device can expose in total */ 14081 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VFS_OFST 4 14082 /* The maximum number of MSI-X vectors the device can provide in total */ 14083 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VECTORS_OFST 8 14084 /* the number of MSI-X vectors the device will allocate by default to each PF 14085 */ 14086 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_PF_VECTORS_OFST 12 14087 /* the number of MSI-X vectors the device will allocate by default to each VF 14088 */ 14089 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_VF_VECTORS_OFST 16 14090 /* the maximum number of MSI-X vectors the device can allocate to any one PF */ 14091 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PF_VECTORS_OFST 20 14092 /* the maximum number of MSI-X vectors the device can allocate to any one VF */ 14093 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VF_VECTORS_OFST 24 14094 14095 14096 /***********************************/ 14097 /* MC_CMD_GET_PORT_MODES 14098 * Find out about available port modes 14099 */ 14100 #define MC_CMD_GET_PORT_MODES 0xff 14101 #undef MC_CMD_0xff_PRIVILEGE_CTG 14102 14103 #define MC_CMD_0xff_PRIVILEGE_CTG SRIOV_CTG_GENERAL 14104 14105 /* MC_CMD_GET_PORT_MODES_IN msgrequest */ 14106 #define MC_CMD_GET_PORT_MODES_IN_LEN 0 14107 14108 /* MC_CMD_GET_PORT_MODES_OUT msgresponse */ 14109 #define MC_CMD_GET_PORT_MODES_OUT_LEN 12 14110 /* Bitmask of port modes available on the board (indexed by TLV_PORT_MODE_*) */ 14111 #define MC_CMD_GET_PORT_MODES_OUT_MODES_OFST 0 14112 /* Default (canonical) board mode */ 14113 #define MC_CMD_GET_PORT_MODES_OUT_DEFAULT_MODE_OFST 4 14114 /* Current board mode */ 14115 #define MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST 8 14116 14117 14118 /***********************************/ 14119 /* MC_CMD_READ_ATB 14120 * Sample voltages on the ATB 14121 */ 14122 #define MC_CMD_READ_ATB 0x100 14123 #undef MC_CMD_0x100_PRIVILEGE_CTG 14124 14125 #define MC_CMD_0x100_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14126 14127 /* MC_CMD_READ_ATB_IN msgrequest */ 14128 #define MC_CMD_READ_ATB_IN_LEN 16 14129 #define MC_CMD_READ_ATB_IN_SIGNAL_BUS_OFST 0 14130 #define MC_CMD_READ_ATB_IN_BUS_CCOM 0x0 /* enum */ 14131 #define MC_CMD_READ_ATB_IN_BUS_CKR 0x1 /* enum */ 14132 #define MC_CMD_READ_ATB_IN_BUS_CPCIE 0x8 /* enum */ 14133 #define MC_CMD_READ_ATB_IN_SIGNAL_EN_BITNO_OFST 4 14134 #define MC_CMD_READ_ATB_IN_SIGNAL_SEL_OFST 8 14135 #define MC_CMD_READ_ATB_IN_SETTLING_TIME_US_OFST 12 14136 14137 /* MC_CMD_READ_ATB_OUT msgresponse */ 14138 #define MC_CMD_READ_ATB_OUT_LEN 4 14139 #define MC_CMD_READ_ATB_OUT_SAMPLE_MV_OFST 0 14140 14141 14142 /***********************************/ 14143 /* MC_CMD_GET_WORKAROUNDS 14144 * Read the list of all implemented and all currently enabled workarounds. The 14145 * enums here must correspond with those in MC_CMD_WORKAROUND. 14146 */ 14147 #define MC_CMD_GET_WORKAROUNDS 0x59 14148 #undef MC_CMD_0x59_PRIVILEGE_CTG 14149 14150 #define MC_CMD_0x59_PRIVILEGE_CTG SRIOV_CTG_GENERAL 14151 14152 /* MC_CMD_GET_WORKAROUNDS_OUT msgresponse */ 14153 #define MC_CMD_GET_WORKAROUNDS_OUT_LEN 8 14154 /* Each workaround is represented by a single bit according to the enums below. 14155 */ 14156 #define MC_CMD_GET_WORKAROUNDS_OUT_IMPLEMENTED_OFST 0 14157 #define MC_CMD_GET_WORKAROUNDS_OUT_ENABLED_OFST 4 14158 /* enum: Bug 17230 work around. */ 14159 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG17230 0x2 14160 /* enum: Bug 35388 work around (unsafe EVQ writes). */ 14161 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG35388 0x4 14162 /* enum: Bug35017 workaround (A64 tables must be identity map) */ 14163 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG35017 0x8 14164 /* enum: Bug 41750 present (MC_CMD_TRIGGER_INTERRUPT won't work) */ 14165 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG41750 0x10 14166 /* enum: Bug 42008 present (Interrupts can overtake associated events). Caution 14167 * - before adding code that queries this workaround, remember that there's 14168 * released Monza firmware that doesn't understand MC_CMD_WORKAROUND_BUG42008, 14169 * and will hence (incorrectly) report that the bug doesn't exist. 14170 */ 14171 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG42008 0x20 14172 /* enum: Bug 26807 features present in firmware (multicast filter chaining) */ 14173 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG26807 0x40 14174 /* enum: Bug 61265 work around (broken EVQ TMR writes). */ 14175 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG61265 0x80 14176 14177 14178 /***********************************/ 14179 /* MC_CMD_PRIVILEGE_MASK 14180 * Read/set privileges of an arbitrary PCIe function 14181 */ 14182 #define MC_CMD_PRIVILEGE_MASK 0x5a 14183 #undef MC_CMD_0x5a_PRIVILEGE_CTG 14184 14185 #define MC_CMD_0x5a_PRIVILEGE_CTG SRIOV_CTG_GENERAL 14186 14187 /* MC_CMD_PRIVILEGE_MASK_IN msgrequest */ 14188 #define MC_CMD_PRIVILEGE_MASK_IN_LEN 8 14189 /* The target function to have its mask read or set e.g. PF 0 = 0xFFFF0000, VF 14190 * 1,3 = 0x00030001 14191 */ 14192 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_OFST 0 14193 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_PF_LBN 0 14194 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_PF_WIDTH 16 14195 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_VF_LBN 16 14196 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_VF_WIDTH 16 14197 #define MC_CMD_PRIVILEGE_MASK_IN_VF_NULL 0xffff /* enum */ 14198 /* New privilege mask to be set. The mask will only be changed if the MSB is 14199 * set to 1. 14200 */ 14201 #define MC_CMD_PRIVILEGE_MASK_IN_NEW_MASK_OFST 4 14202 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN 0x1 /* enum */ 14203 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_LINK 0x2 /* enum */ 14204 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ONLOAD 0x4 /* enum */ 14205 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_PTP 0x8 /* enum */ 14206 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE_FILTERS 0x10 /* enum */ 14207 /* enum: Deprecated. Equivalent to MAC_SPOOFING_TX combined with CHANGE_MAC. */ 14208 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING 0x20 14209 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_UNICAST 0x40 /* enum */ 14210 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_MULTICAST 0x80 /* enum */ 14211 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_BROADCAST 0x100 /* enum */ 14212 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ALL_MULTICAST 0x200 /* enum */ 14213 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_PROMISCUOUS 0x400 /* enum */ 14214 /* enum: Allows to set the TX packets' source MAC address to any arbitrary MAC 14215 * adress. 14216 */ 14217 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING_TX 0x800 14218 /* enum: Privilege that allows a Function to change the MAC address configured 14219 * in its associated vAdapter/vPort. 14220 */ 14221 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_CHANGE_MAC 0x1000 14222 /* enum: Privilege that allows a Function to install filters that specify VLANs 14223 * that are not in the permit list for the associated vPort. This privilege is 14224 * primarily to support ESX where vPorts are created that restrict traffic to 14225 * only a set of permitted VLANs. See the vPort flag FLAG_VLAN_RESTRICT. 14226 */ 14227 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_UNRESTRICTED_VLAN 0x2000 14228 /* enum: Set this bit to indicate that a new privilege mask is to be set, 14229 * otherwise the command will only read the existing mask. 14230 */ 14231 #define MC_CMD_PRIVILEGE_MASK_IN_DO_CHANGE 0x80000000 14232 14233 /* MC_CMD_PRIVILEGE_MASK_OUT msgresponse */ 14234 #define MC_CMD_PRIVILEGE_MASK_OUT_LEN 4 14235 /* For an admin function, always all the privileges are reported. */ 14236 #define MC_CMD_PRIVILEGE_MASK_OUT_OLD_MASK_OFST 0 14237 14238 14239 /***********************************/ 14240 /* MC_CMD_LINK_STATE_MODE 14241 * Read/set link state mode of a VF 14242 */ 14243 #define MC_CMD_LINK_STATE_MODE 0x5c 14244 #undef MC_CMD_0x5c_PRIVILEGE_CTG 14245 14246 #define MC_CMD_0x5c_PRIVILEGE_CTG SRIOV_CTG_GENERAL 14247 14248 /* MC_CMD_LINK_STATE_MODE_IN msgrequest */ 14249 #define MC_CMD_LINK_STATE_MODE_IN_LEN 8 14250 /* The target function to have its link state mode read or set, must be a VF 14251 * e.g. VF 1,3 = 0x00030001 14252 */ 14253 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_OFST 0 14254 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_LBN 0 14255 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_WIDTH 16 14256 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_VF_LBN 16 14257 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_VF_WIDTH 16 14258 /* New link state mode to be set */ 14259 #define MC_CMD_LINK_STATE_MODE_IN_NEW_MODE_OFST 4 14260 #define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_AUTO 0x0 /* enum */ 14261 #define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_UP 0x1 /* enum */ 14262 #define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_DOWN 0x2 /* enum */ 14263 /* enum: Use this value to just read the existing setting without modifying it. 14264 */ 14265 #define MC_CMD_LINK_STATE_MODE_IN_DO_NOT_CHANGE 0xffffffff 14266 14267 /* MC_CMD_LINK_STATE_MODE_OUT msgresponse */ 14268 #define MC_CMD_LINK_STATE_MODE_OUT_LEN 4 14269 #define MC_CMD_LINK_STATE_MODE_OUT_OLD_MODE_OFST 0 14270 14271 14272 /***********************************/ 14273 /* MC_CMD_GET_SNAPSHOT_LENGTH 14274 * Obtain the curent range of allowable values for the SNAPSHOT_LENGTH 14275 * parameter to MC_CMD_INIT_RXQ. 14276 */ 14277 #define MC_CMD_GET_SNAPSHOT_LENGTH 0x101 14278 #undef MC_CMD_0x101_PRIVILEGE_CTG 14279 14280 #define MC_CMD_0x101_PRIVILEGE_CTG SRIOV_CTG_GENERAL 14281 14282 /* MC_CMD_GET_SNAPSHOT_LENGTH_IN msgrequest */ 14283 #define MC_CMD_GET_SNAPSHOT_LENGTH_IN_LEN 0 14284 14285 /* MC_CMD_GET_SNAPSHOT_LENGTH_OUT msgresponse */ 14286 #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_LEN 8 14287 /* Minimum acceptable snapshot length. */ 14288 #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MIN_OFST 0 14289 /* Maximum acceptable snapshot length. */ 14290 #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MAX_OFST 4 14291 14292 14293 /***********************************/ 14294 /* MC_CMD_FUSE_DIAGS 14295 * Additional fuse diagnostics 14296 */ 14297 #define MC_CMD_FUSE_DIAGS 0x102 14298 #undef MC_CMD_0x102_PRIVILEGE_CTG 14299 14300 #define MC_CMD_0x102_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14301 14302 /* MC_CMD_FUSE_DIAGS_IN msgrequest */ 14303 #define MC_CMD_FUSE_DIAGS_IN_LEN 0 14304 14305 /* MC_CMD_FUSE_DIAGS_OUT msgresponse */ 14306 #define MC_CMD_FUSE_DIAGS_OUT_LEN 48 14307 /* Total number of mismatched bits between pairs in area 0 */ 14308 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_MISMATCH_BITS_OFST 0 14309 /* Total number of unexpectedly clear (set in B but not A) bits in area 0 */ 14310 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_A_BAD_BITS_OFST 4 14311 /* Total number of unexpectedly clear (set in A but not B) bits in area 0 */ 14312 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_B_BAD_BITS_OFST 8 14313 /* Checksum of data after logical OR of pairs in area 0 */ 14314 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_CHECKSUM_OFST 12 14315 /* Total number of mismatched bits between pairs in area 1 */ 14316 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_MISMATCH_BITS_OFST 16 14317 /* Total number of unexpectedly clear (set in B but not A) bits in area 1 */ 14318 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_A_BAD_BITS_OFST 20 14319 /* Total number of unexpectedly clear (set in A but not B) bits in area 1 */ 14320 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_B_BAD_BITS_OFST 24 14321 /* Checksum of data after logical OR of pairs in area 1 */ 14322 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_CHECKSUM_OFST 28 14323 /* Total number of mismatched bits between pairs in area 2 */ 14324 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_MISMATCH_BITS_OFST 32 14325 /* Total number of unexpectedly clear (set in B but not A) bits in area 2 */ 14326 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_A_BAD_BITS_OFST 36 14327 /* Total number of unexpectedly clear (set in A but not B) bits in area 2 */ 14328 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_B_BAD_BITS_OFST 40 14329 /* Checksum of data after logical OR of pairs in area 2 */ 14330 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_CHECKSUM_OFST 44 14331 14332 14333 /***********************************/ 14334 /* MC_CMD_PRIVILEGE_MODIFY 14335 * Modify the privileges of a set of PCIe functions. Note that this operation 14336 * only effects non-admin functions unless the admin privilege itself is 14337 * included in one of the masks provided. 14338 */ 14339 #define MC_CMD_PRIVILEGE_MODIFY 0x60 14340 #undef MC_CMD_0x60_PRIVILEGE_CTG 14341 14342 #define MC_CMD_0x60_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14343 14344 /* MC_CMD_PRIVILEGE_MODIFY_IN msgrequest */ 14345 #define MC_CMD_PRIVILEGE_MODIFY_IN_LEN 16 14346 /* The groups of functions to have their privilege masks modified. */ 14347 #define MC_CMD_PRIVILEGE_MODIFY_IN_FN_GROUP_OFST 0 14348 #define MC_CMD_PRIVILEGE_MODIFY_IN_NONE 0x0 /* enum */ 14349 #define MC_CMD_PRIVILEGE_MODIFY_IN_ALL 0x1 /* enum */ 14350 #define MC_CMD_PRIVILEGE_MODIFY_IN_PFS_ONLY 0x2 /* enum */ 14351 #define MC_CMD_PRIVILEGE_MODIFY_IN_VFS_ONLY 0x3 /* enum */ 14352 #define MC_CMD_PRIVILEGE_MODIFY_IN_VFS_OF_PF 0x4 /* enum */ 14353 #define MC_CMD_PRIVILEGE_MODIFY_IN_ONE 0x5 /* enum */ 14354 /* For VFS_OF_PF specify the PF, for ONE specify the target function */ 14355 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_OFST 4 14356 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_PF_LBN 0 14357 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_PF_WIDTH 16 14358 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_VF_LBN 16 14359 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_VF_WIDTH 16 14360 /* Privileges to be added to the target functions. For privilege definitions 14361 * refer to the command MC_CMD_PRIVILEGE_MASK 14362 */ 14363 #define MC_CMD_PRIVILEGE_MODIFY_IN_ADD_MASK_OFST 8 14364 /* Privileges to be removed from the target functions. For privilege 14365 * definitions refer to the command MC_CMD_PRIVILEGE_MASK 14366 */ 14367 #define MC_CMD_PRIVILEGE_MODIFY_IN_REMOVE_MASK_OFST 12 14368 14369 /* MC_CMD_PRIVILEGE_MODIFY_OUT msgresponse */ 14370 #define MC_CMD_PRIVILEGE_MODIFY_OUT_LEN 0 14371 14372 14373 /***********************************/ 14374 /* MC_CMD_XPM_READ_BYTES 14375 * Read XPM memory 14376 */ 14377 #define MC_CMD_XPM_READ_BYTES 0x103 14378 #undef MC_CMD_0x103_PRIVILEGE_CTG 14379 14380 #define MC_CMD_0x103_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14381 14382 /* MC_CMD_XPM_READ_BYTES_IN msgrequest */ 14383 #define MC_CMD_XPM_READ_BYTES_IN_LEN 8 14384 /* Start address (byte) */ 14385 #define MC_CMD_XPM_READ_BYTES_IN_ADDR_OFST 0 14386 /* Count (bytes) */ 14387 #define MC_CMD_XPM_READ_BYTES_IN_COUNT_OFST 4 14388 14389 /* MC_CMD_XPM_READ_BYTES_OUT msgresponse */ 14390 #define MC_CMD_XPM_READ_BYTES_OUT_LENMIN 0 14391 #define MC_CMD_XPM_READ_BYTES_OUT_LENMAX 252 14392 #define MC_CMD_XPM_READ_BYTES_OUT_LEN(num) (0+1*(num)) 14393 /* Data */ 14394 #define MC_CMD_XPM_READ_BYTES_OUT_DATA_OFST 0 14395 #define MC_CMD_XPM_READ_BYTES_OUT_DATA_LEN 1 14396 #define MC_CMD_XPM_READ_BYTES_OUT_DATA_MINNUM 0 14397 #define MC_CMD_XPM_READ_BYTES_OUT_DATA_MAXNUM 252 14398 14399 14400 /***********************************/ 14401 /* MC_CMD_XPM_WRITE_BYTES 14402 * Write XPM memory 14403 */ 14404 #define MC_CMD_XPM_WRITE_BYTES 0x104 14405 #undef MC_CMD_0x104_PRIVILEGE_CTG 14406 14407 #define MC_CMD_0x104_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14408 14409 /* MC_CMD_XPM_WRITE_BYTES_IN msgrequest */ 14410 #define MC_CMD_XPM_WRITE_BYTES_IN_LENMIN 8 14411 #define MC_CMD_XPM_WRITE_BYTES_IN_LENMAX 252 14412 #define MC_CMD_XPM_WRITE_BYTES_IN_LEN(num) (8+1*(num)) 14413 /* Start address (byte) */ 14414 #define MC_CMD_XPM_WRITE_BYTES_IN_ADDR_OFST 0 14415 /* Count (bytes) */ 14416 #define MC_CMD_XPM_WRITE_BYTES_IN_COUNT_OFST 4 14417 /* Data */ 14418 #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_OFST 8 14419 #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_LEN 1 14420 #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_MINNUM 0 14421 #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_MAXNUM 244 14422 14423 /* MC_CMD_XPM_WRITE_BYTES_OUT msgresponse */ 14424 #define MC_CMD_XPM_WRITE_BYTES_OUT_LEN 0 14425 14426 14427 /***********************************/ 14428 /* MC_CMD_XPM_READ_SECTOR 14429 * Read XPM sector 14430 */ 14431 #define MC_CMD_XPM_READ_SECTOR 0x105 14432 #undef MC_CMD_0x105_PRIVILEGE_CTG 14433 14434 #define MC_CMD_0x105_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14435 14436 /* MC_CMD_XPM_READ_SECTOR_IN msgrequest */ 14437 #define MC_CMD_XPM_READ_SECTOR_IN_LEN 8 14438 /* Sector index */ 14439 #define MC_CMD_XPM_READ_SECTOR_IN_INDEX_OFST 0 14440 /* Sector size */ 14441 #define MC_CMD_XPM_READ_SECTOR_IN_SIZE_OFST 4 14442 14443 /* MC_CMD_XPM_READ_SECTOR_OUT msgresponse */ 14444 #define MC_CMD_XPM_READ_SECTOR_OUT_LENMIN 4 14445 #define MC_CMD_XPM_READ_SECTOR_OUT_LENMAX 36 14446 #define MC_CMD_XPM_READ_SECTOR_OUT_LEN(num) (4+1*(num)) 14447 /* Sector type */ 14448 #define MC_CMD_XPM_READ_SECTOR_OUT_TYPE_OFST 0 14449 #define MC_CMD_XPM_READ_SECTOR_OUT_BLANK 0x0 /* enum */ 14450 #define MC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_KEY_128 0x1 /* enum */ 14451 #define MC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_KEY_256 0x2 /* enum */ 14452 #define MC_CMD_XPM_READ_SECTOR_OUT_INVALID 0xff /* enum */ 14453 /* Sector data */ 14454 #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_OFST 4 14455 #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_LEN 1 14456 #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_MINNUM 0 14457 #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_MAXNUM 32 14458 14459 14460 /***********************************/ 14461 /* MC_CMD_XPM_WRITE_SECTOR 14462 * Write XPM sector 14463 */ 14464 #define MC_CMD_XPM_WRITE_SECTOR 0x106 14465 #undef MC_CMD_0x106_PRIVILEGE_CTG 14466 14467 #define MC_CMD_0x106_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14468 14469 /* MC_CMD_XPM_WRITE_SECTOR_IN msgrequest */ 14470 #define MC_CMD_XPM_WRITE_SECTOR_IN_LENMIN 12 14471 #define MC_CMD_XPM_WRITE_SECTOR_IN_LENMAX 44 14472 #define MC_CMD_XPM_WRITE_SECTOR_IN_LEN(num) (12+1*(num)) 14473 /* If writing fails due to an uncorrectable error, try up to RETRIES following 14474 * sectors (or until no more space available). If 0, only one write attempt is 14475 * made. Note that uncorrectable errors are unlikely, thanks to XPM self-repair 14476 * mechanism. 14477 */ 14478 #define MC_CMD_XPM_WRITE_SECTOR_IN_RETRIES_OFST 0 14479 #define MC_CMD_XPM_WRITE_SECTOR_IN_RETRIES_LEN 1 14480 #define MC_CMD_XPM_WRITE_SECTOR_IN_RESERVED_OFST 1 14481 #define MC_CMD_XPM_WRITE_SECTOR_IN_RESERVED_LEN 3 14482 /* Sector type */ 14483 #define MC_CMD_XPM_WRITE_SECTOR_IN_TYPE_OFST 4 14484 /* Enum values, see field(s): */ 14485 /* MC_CMD_XPM_READ_SECTOR/MC_CMD_XPM_READ_SECTOR_OUT/TYPE */ 14486 /* Sector size */ 14487 #define MC_CMD_XPM_WRITE_SECTOR_IN_SIZE_OFST 8 14488 /* Sector data */ 14489 #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_OFST 12 14490 #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_LEN 1 14491 #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_MINNUM 0 14492 #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_MAXNUM 32 14493 14494 /* MC_CMD_XPM_WRITE_SECTOR_OUT msgresponse */ 14495 #define MC_CMD_XPM_WRITE_SECTOR_OUT_LEN 4 14496 /* New sector index */ 14497 #define MC_CMD_XPM_WRITE_SECTOR_OUT_INDEX_OFST 0 14498 14499 14500 /***********************************/ 14501 /* MC_CMD_XPM_INVALIDATE_SECTOR 14502 * Invalidate XPM sector 14503 */ 14504 #define MC_CMD_XPM_INVALIDATE_SECTOR 0x107 14505 #undef MC_CMD_0x107_PRIVILEGE_CTG 14506 14507 #define MC_CMD_0x107_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14508 14509 /* MC_CMD_XPM_INVALIDATE_SECTOR_IN msgrequest */ 14510 #define MC_CMD_XPM_INVALIDATE_SECTOR_IN_LEN 4 14511 /* Sector index */ 14512 #define MC_CMD_XPM_INVALIDATE_SECTOR_IN_INDEX_OFST 0 14513 14514 /* MC_CMD_XPM_INVALIDATE_SECTOR_OUT msgresponse */ 14515 #define MC_CMD_XPM_INVALIDATE_SECTOR_OUT_LEN 0 14516 14517 14518 /***********************************/ 14519 /* MC_CMD_XPM_BLANK_CHECK 14520 * Blank-check XPM memory and report bad locations 14521 */ 14522 #define MC_CMD_XPM_BLANK_CHECK 0x108 14523 #undef MC_CMD_0x108_PRIVILEGE_CTG 14524 14525 #define MC_CMD_0x108_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14526 14527 /* MC_CMD_XPM_BLANK_CHECK_IN msgrequest */ 14528 #define MC_CMD_XPM_BLANK_CHECK_IN_LEN 8 14529 /* Start address (byte) */ 14530 #define MC_CMD_XPM_BLANK_CHECK_IN_ADDR_OFST 0 14531 /* Count (bytes) */ 14532 #define MC_CMD_XPM_BLANK_CHECK_IN_COUNT_OFST 4 14533 14534 /* MC_CMD_XPM_BLANK_CHECK_OUT msgresponse */ 14535 #define MC_CMD_XPM_BLANK_CHECK_OUT_LENMIN 4 14536 #define MC_CMD_XPM_BLANK_CHECK_OUT_LENMAX 252 14537 #define MC_CMD_XPM_BLANK_CHECK_OUT_LEN(num) (4+2*(num)) 14538 /* Total number of bad (non-blank) locations */ 14539 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_COUNT_OFST 0 14540 /* Addresses of bad locations (may be less than BAD_COUNT, if all cannot fit 14541 * into MCDI response) 14542 */ 14543 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_OFST 4 14544 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_LEN 2 14545 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_MINNUM 0 14546 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_MAXNUM 124 14547 14548 14549 /***********************************/ 14550 /* MC_CMD_XPM_REPAIR 14551 * Blank-check and repair XPM memory 14552 */ 14553 #define MC_CMD_XPM_REPAIR 0x109 14554 #undef MC_CMD_0x109_PRIVILEGE_CTG 14555 14556 #define MC_CMD_0x109_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14557 14558 /* MC_CMD_XPM_REPAIR_IN msgrequest */ 14559 #define MC_CMD_XPM_REPAIR_IN_LEN 8 14560 /* Start address (byte) */ 14561 #define MC_CMD_XPM_REPAIR_IN_ADDR_OFST 0 14562 /* Count (bytes) */ 14563 #define MC_CMD_XPM_REPAIR_IN_COUNT_OFST 4 14564 14565 /* MC_CMD_XPM_REPAIR_OUT msgresponse */ 14566 #define MC_CMD_XPM_REPAIR_OUT_LEN 0 14567 14568 14569 /***********************************/ 14570 /* MC_CMD_XPM_DECODER_TEST 14571 * Test XPM memory address decoders for gross manufacturing defects. Can only 14572 * be performed on an unprogrammed part. 14573 */ 14574 #define MC_CMD_XPM_DECODER_TEST 0x10a 14575 #undef MC_CMD_0x10a_PRIVILEGE_CTG 14576 14577 #define MC_CMD_0x10a_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14578 14579 /* MC_CMD_XPM_DECODER_TEST_IN msgrequest */ 14580 #define MC_CMD_XPM_DECODER_TEST_IN_LEN 0 14581 14582 /* MC_CMD_XPM_DECODER_TEST_OUT msgresponse */ 14583 #define MC_CMD_XPM_DECODER_TEST_OUT_LEN 0 14584 14585 14586 /***********************************/ 14587 /* MC_CMD_XPM_WRITE_TEST 14588 * XPM memory write test. Test XPM write logic for gross manufacturing defects 14589 * by writing to a dedicated test row. There are 16 locations in the test row 14590 * and the test can only be performed on locations that have not been 14591 * previously used (i.e. can be run at most 16 times). The test will pick the 14592 * first available location to use, or fail with ENOSPC if none left. 14593 */ 14594 #define MC_CMD_XPM_WRITE_TEST 0x10b 14595 #undef MC_CMD_0x10b_PRIVILEGE_CTG 14596 14597 #define MC_CMD_0x10b_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14598 14599 /* MC_CMD_XPM_WRITE_TEST_IN msgrequest */ 14600 #define MC_CMD_XPM_WRITE_TEST_IN_LEN 0 14601 14602 /* MC_CMD_XPM_WRITE_TEST_OUT msgresponse */ 14603 #define MC_CMD_XPM_WRITE_TEST_OUT_LEN 0 14604 14605 14606 /***********************************/ 14607 /* MC_CMD_EXEC_SIGNED 14608 * Check the CMAC of the contents of IMEM and DMEM against the value supplied 14609 * and if correct begin execution from the start of IMEM. The caller supplies a 14610 * key ID, the length of IMEM and DMEM to validate and the expected CMAC. CMAC 14611 * computation runs from the start of IMEM, and from the start of DMEM + 16k, 14612 * to match flash booting. The command will respond with EINVAL if the CMAC 14613 * does match, otherwise it will respond with success before it jumps to IMEM. 14614 */ 14615 #define MC_CMD_EXEC_SIGNED 0x10c 14616 #undef MC_CMD_0x10c_PRIVILEGE_CTG 14617 14618 #define MC_CMD_0x10c_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14619 14620 /* MC_CMD_EXEC_SIGNED_IN msgrequest */ 14621 #define MC_CMD_EXEC_SIGNED_IN_LEN 28 14622 /* the length of code to include in the CMAC */ 14623 #define MC_CMD_EXEC_SIGNED_IN_CODELEN_OFST 0 14624 /* the length of date to include in the CMAC */ 14625 #define MC_CMD_EXEC_SIGNED_IN_DATALEN_OFST 4 14626 /* the XPM sector containing the key to use */ 14627 #define MC_CMD_EXEC_SIGNED_IN_KEYSECTOR_OFST 8 14628 /* the expected CMAC value */ 14629 #define MC_CMD_EXEC_SIGNED_IN_CMAC_OFST 12 14630 #define MC_CMD_EXEC_SIGNED_IN_CMAC_LEN 16 14631 14632 /* MC_CMD_EXEC_SIGNED_OUT msgresponse */ 14633 #define MC_CMD_EXEC_SIGNED_OUT_LEN 0 14634 14635 14636 /***********************************/ 14637 /* MC_CMD_PREPARE_SIGNED 14638 * Prepare to upload a signed image. This will scrub the specified length of 14639 * the data region, which must be at least as large as the DATALEN supplied to 14640 * MC_CMD_EXEC_SIGNED. 14641 */ 14642 #define MC_CMD_PREPARE_SIGNED 0x10d 14643 #undef MC_CMD_0x10d_PRIVILEGE_CTG 14644 14645 #define MC_CMD_0x10d_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14646 14647 /* MC_CMD_PREPARE_SIGNED_IN msgrequest */ 14648 #define MC_CMD_PREPARE_SIGNED_IN_LEN 4 14649 /* the length of data area to clear */ 14650 #define MC_CMD_PREPARE_SIGNED_IN_DATALEN_OFST 0 14651 14652 /* MC_CMD_PREPARE_SIGNED_OUT msgresponse */ 14653 #define MC_CMD_PREPARE_SIGNED_OUT_LEN 0 14654 14655 14656 /***********************************/ 14657 /* MC_CMD_SET_SECURITY_RULE 14658 * Set blacklist and/or whitelist action for a particular match criteria. 14659 * (Medford-only; for use by SolarSecure apps, not directly by drivers. See 14660 * SF-114946-SW.) NOTE - this message definition is provisional. It has not yet 14661 * been used in any released code and may change during development. This note 14662 * will be removed once it is regarded as stable. 14663 */ 14664 #define MC_CMD_SET_SECURITY_RULE 0x10f 14665 #undef MC_CMD_0x10f_PRIVILEGE_CTG 14666 14667 #define MC_CMD_0x10f_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14668 14669 /* MC_CMD_SET_SECURITY_RULE_IN msgrequest */ 14670 #define MC_CMD_SET_SECURITY_RULE_IN_LEN 92 14671 /* fields to include in match criteria */ 14672 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_FIELDS_OFST 0 14673 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_IP_LBN 0 14674 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_IP_WIDTH 1 14675 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_IP_LBN 1 14676 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_IP_WIDTH 1 14677 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_MAC_LBN 2 14678 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_MAC_WIDTH 1 14679 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_PORT_LBN 3 14680 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_PORT_WIDTH 1 14681 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_MAC_LBN 4 14682 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_MAC_WIDTH 1 14683 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_PORT_LBN 5 14684 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_PORT_WIDTH 1 14685 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_ETHER_TYPE_LBN 6 14686 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_ETHER_TYPE_WIDTH 1 14687 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_INNER_VLAN_LBN 7 14688 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_INNER_VLAN_WIDTH 1 14689 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_OUTER_VLAN_LBN 8 14690 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_OUTER_VLAN_WIDTH 1 14691 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_IP_PROTO_LBN 9 14692 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_IP_PROTO_WIDTH 1 14693 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_PHYSICAL_PORT_LBN 10 14694 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_PHYSICAL_PORT_WIDTH 1 14695 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_RESERVED_LBN 11 14696 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_RESERVED_WIDTH 1 14697 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_SUBNET_ID_LBN 12 14698 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_SUBNET_ID_WIDTH 1 14699 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_PORTRANGE_ID_LBN 13 14700 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_PORTRANGE_ID_WIDTH 1 14701 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_PORTRANGE_ID_LBN 14 14702 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_PORTRANGE_ID_WIDTH 1 14703 /* remote MAC address to match (as bytes in network order) */ 14704 #define MC_CMD_SET_SECURITY_RULE_IN_REMOTE_MAC_OFST 4 14705 #define MC_CMD_SET_SECURITY_RULE_IN_REMOTE_MAC_LEN 6 14706 /* remote port to match (as bytes in network order) */ 14707 #define MC_CMD_SET_SECURITY_RULE_IN_REMOTE_PORT_OFST 10 14708 #define MC_CMD_SET_SECURITY_RULE_IN_REMOTE_PORT_LEN 2 14709 /* local MAC address to match (as bytes in network order) */ 14710 #define MC_CMD_SET_SECURITY_RULE_IN_LOCAL_MAC_OFST 12 14711 #define MC_CMD_SET_SECURITY_RULE_IN_LOCAL_MAC_LEN 6 14712 /* local port to match (as bytes in network order) */ 14713 #define MC_CMD_SET_SECURITY_RULE_IN_LOCAL_PORT_OFST 18 14714 #define MC_CMD_SET_SECURITY_RULE_IN_LOCAL_PORT_LEN 2 14715 /* Ethernet type to match (as bytes in network order) */ 14716 #define MC_CMD_SET_SECURITY_RULE_IN_ETHER_TYPE_OFST 20 14717 #define MC_CMD_SET_SECURITY_RULE_IN_ETHER_TYPE_LEN 2 14718 /* Inner VLAN tag to match (as bytes in network order) */ 14719 #define MC_CMD_SET_SECURITY_RULE_IN_INNER_VLAN_OFST 22 14720 #define MC_CMD_SET_SECURITY_RULE_IN_INNER_VLAN_LEN 2 14721 /* Outer VLAN tag to match (as bytes in network order) */ 14722 #define MC_CMD_SET_SECURITY_RULE_IN_OUTER_VLAN_OFST 24 14723 #define MC_CMD_SET_SECURITY_RULE_IN_OUTER_VLAN_LEN 2 14724 /* IP protocol to match (in low byte; set high byte to 0) */ 14725 #define MC_CMD_SET_SECURITY_RULE_IN_IP_PROTO_OFST 26 14726 #define MC_CMD_SET_SECURITY_RULE_IN_IP_PROTO_LEN 2 14727 /* Physical port to match (as little-endian 32-bit value) */ 14728 #define MC_CMD_SET_SECURITY_RULE_IN_PHYSICAL_PORT_OFST 28 14729 /* Reserved; set to 0 */ 14730 #define MC_CMD_SET_SECURITY_RULE_IN_RESERVED_OFST 32 14731 /* remote IP address to match (as bytes in network order; set last 12 bytes to 14732 * 0 for IPv4 address) 14733 */ 14734 #define MC_CMD_SET_SECURITY_RULE_IN_REMOTE_IP_OFST 36 14735 #define MC_CMD_SET_SECURITY_RULE_IN_REMOTE_IP_LEN 16 14736 /* local IP address to match (as bytes in network order; set last 12 bytes to 0 14737 * for IPv4 address) 14738 */ 14739 #define MC_CMD_SET_SECURITY_RULE_IN_LOCAL_IP_OFST 52 14740 #define MC_CMD_SET_SECURITY_RULE_IN_LOCAL_IP_LEN 16 14741 /* remote subnet ID to match (as little-endian 32-bit value); note that remote 14742 * subnets are matched by mapping the remote IP address to a "subnet ID" via a 14743 * data structure which must already have been configured using 14744 * MC_CMD_SUBNET_MAP_SET_NODE appropriately 14745 */ 14746 #define MC_CMD_SET_SECURITY_RULE_IN_REMOTE_SUBNET_ID_OFST 68 14747 /* remote portrange ID to match (as little-endian 32-bit value); note that 14748 * remote port ranges are matched by mapping the remote port to a "portrange 14749 * ID" via a data structure which must already have been configured using 14750 * MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE 14751 */ 14752 #define MC_CMD_SET_SECURITY_RULE_IN_REMOTE_PORTRANGE_ID_OFST 72 14753 /* local portrange ID to match (as little-endian 32-bit value); note that local 14754 * port ranges are matched by mapping the local port to a "portrange ID" via a 14755 * data structure which must already have been configured using 14756 * MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE 14757 */ 14758 #define MC_CMD_SET_SECURITY_RULE_IN_LOCAL_PORTRANGE_ID_OFST 76 14759 /* set the action for transmitted packets matching this rule */ 14760 #define MC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_OFST 80 14761 /* enum: make no decision */ 14762 #define MC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_NONE 0x0 14763 /* enum: decide to accept the packet */ 14764 #define MC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_WHITELIST 0x1 14765 /* enum: decide to drop the packet */ 14766 #define MC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_BLACKLIST 0x2 14767 /* enum: do not change the current TX action */ 14768 #define MC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_UNCHANGED 0xffffffff 14769 /* set the action for received packets matching this rule */ 14770 #define MC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_OFST 84 14771 /* enum: make no decision */ 14772 #define MC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_NONE 0x0 14773 /* enum: decide to accept the packet */ 14774 #define MC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_WHITELIST 0x1 14775 /* enum: decide to drop the packet */ 14776 #define MC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_BLACKLIST 0x2 14777 /* enum: do not change the current RX action */ 14778 #define MC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_UNCHANGED 0xffffffff 14779 /* counter ID to associate with this rule; IDs are allocated using 14780 * MC_CMD_SECURITY_RULE_COUNTER_ALLOC 14781 */ 14782 #define MC_CMD_SET_SECURITY_RULE_IN_COUNTER_ID_OFST 88 14783 /* enum: special value for the null counter ID */ 14784 #define MC_CMD_SET_SECURITY_RULE_IN_COUNTER_ID_NONE 0x0 14785 14786 /* MC_CMD_SET_SECURITY_RULE_OUT msgresponse */ 14787 #define MC_CMD_SET_SECURITY_RULE_OUT_LEN 28 14788 /* new reference count for uses of counter ID */ 14789 #define MC_CMD_SET_SECURITY_RULE_OUT_COUNTER_REFCNT_OFST 0 14790 /* constructed match bits for this rule (as a tracing aid only) */ 14791 #define MC_CMD_SET_SECURITY_RULE_OUT_LUE_MATCH_BITS_OFST 4 14792 #define MC_CMD_SET_SECURITY_RULE_OUT_LUE_MATCH_BITS_LEN 12 14793 /* constructed discriminator bits for this rule (as a tracing aid only) */ 14794 #define MC_CMD_SET_SECURITY_RULE_OUT_LUE_DISCRIMINATOR_OFST 16 14795 /* base location for probes for this rule (as a tracing aid only) */ 14796 #define MC_CMD_SET_SECURITY_RULE_OUT_LUE_PROBE_BASE_OFST 20 14797 /* step for probes for this rule (as a tracing aid only) */ 14798 #define MC_CMD_SET_SECURITY_RULE_OUT_LUE_PROBE_STEP_OFST 24 14799 14800 14801 /***********************************/ 14802 /* MC_CMD_RESET_SECURITY_RULES 14803 * Reset all blacklist and whitelist actions for a particular physical port, or 14804 * all ports. (Medford-only; for use by SolarSecure apps, not directly by 14805 * drivers. See SF-114946-SW.) NOTE - this message definition is provisional. 14806 * It has not yet been used in any released code and may change during 14807 * development. This note will be removed once it is regarded as stable. 14808 */ 14809 #define MC_CMD_RESET_SECURITY_RULES 0x110 14810 #undef MC_CMD_0x110_PRIVILEGE_CTG 14811 14812 #define MC_CMD_0x110_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14813 14814 /* MC_CMD_RESET_SECURITY_RULES_IN msgrequest */ 14815 #define MC_CMD_RESET_SECURITY_RULES_IN_LEN 4 14816 /* index of physical port to reset (or ALL_PHYSICAL_PORTS to reset all) */ 14817 #define MC_CMD_RESET_SECURITY_RULES_IN_PHYSICAL_PORT_OFST 0 14818 /* enum: special value to reset all physical ports */ 14819 #define MC_CMD_RESET_SECURITY_RULES_IN_ALL_PHYSICAL_PORTS 0xffffffff 14820 14821 /* MC_CMD_RESET_SECURITY_RULES_OUT msgresponse */ 14822 #define MC_CMD_RESET_SECURITY_RULES_OUT_LEN 0 14823 14824 14825 /***********************************/ 14826 /* MC_CMD_GET_SECURITY_RULESET_VERSION 14827 * Return a large hash value representing a "version" of the complete set of 14828 * currently active blacklist / whitelist rules and associated data structures. 14829 * (Medford-only; for use by SolarSecure apps, not directly by drivers. See 14830 * SF-114946-SW.) NOTE - this message definition is provisional. It has not yet 14831 * been used in any released code and may change during development. This note 14832 * will be removed once it is regarded as stable. 14833 */ 14834 #define MC_CMD_GET_SECURITY_RULESET_VERSION 0x111 14835 #undef MC_CMD_0x111_PRIVILEGE_CTG 14836 14837 #define MC_CMD_0x111_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14838 14839 /* MC_CMD_GET_SECURITY_RULESET_VERSION_IN msgrequest */ 14840 #define MC_CMD_GET_SECURITY_RULESET_VERSION_IN_LEN 0 14841 14842 /* MC_CMD_GET_SECURITY_RULESET_VERSION_OUT msgresponse */ 14843 #define MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_LENMIN 1 14844 #define MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_LENMAX 252 14845 #define MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_LEN(num) (0+1*(num)) 14846 /* Opaque hash value; length may vary depending on the hash scheme used */ 14847 #define MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_VERSION_OFST 0 14848 #define MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_VERSION_LEN 1 14849 #define MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_VERSION_MINNUM 1 14850 #define MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_VERSION_MAXNUM 252 14851 14852 14853 /***********************************/ 14854 /* MC_CMD_SECURITY_RULE_COUNTER_ALLOC 14855 * Allocate counters for use with blacklist / whitelist rules. (Medford-only; 14856 * for use by SolarSecure apps, not directly by drivers. See SF-114946-SW.) 14857 * NOTE - this message definition is provisional. It has not yet been used in 14858 * any released code and may change during development. This note will be 14859 * removed once it is regarded as stable. 14860 */ 14861 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC 0x112 14862 #undef MC_CMD_0x112_PRIVILEGE_CTG 14863 14864 #define MC_CMD_0x112_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14865 14866 /* MC_CMD_SECURITY_RULE_COUNTER_ALLOC_IN msgrequest */ 14867 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_IN_LEN 4 14868 /* the number of new counter IDs to request */ 14869 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_IN_NUM_COUNTERS_OFST 0 14870 14871 /* MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT msgresponse */ 14872 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_LENMIN 4 14873 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_LENMAX 252 14874 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_LEN(num) (4+4*(num)) 14875 /* the number of new counter IDs allocated (may be less than the number 14876 * requested if resources are unavailable) 14877 */ 14878 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_NUM_COUNTERS_OFST 0 14879 /* new counter ID(s) */ 14880 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_COUNTER_ID_OFST 4 14881 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_COUNTER_ID_LEN 4 14882 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_COUNTER_ID_MINNUM 0 14883 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_COUNTER_ID_MAXNUM 62 14884 14885 14886 /***********************************/ 14887 /* MC_CMD_SECURITY_RULE_COUNTER_FREE 14888 * Allocate counters for use with blacklist / whitelist rules. (Medford-only; 14889 * for use by SolarSecure apps, not directly by drivers. See SF-114946-SW.) 14890 * NOTE - this message definition is provisional. It has not yet been used in 14891 * any released code and may change during development. This note will be 14892 * removed once it is regarded as stable. 14893 */ 14894 #define MC_CMD_SECURITY_RULE_COUNTER_FREE 0x113 14895 #undef MC_CMD_0x113_PRIVILEGE_CTG 14896 14897 #define MC_CMD_0x113_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14898 14899 /* MC_CMD_SECURITY_RULE_COUNTER_FREE_IN msgrequest */ 14900 #define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_LENMIN 4 14901 #define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_LENMAX 252 14902 #define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_LEN(num) (4+4*(num)) 14903 /* the number of counter IDs to free */ 14904 #define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_NUM_COUNTERS_OFST 0 14905 /* the counter ID(s) to free */ 14906 #define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_COUNTER_ID_OFST 4 14907 #define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_COUNTER_ID_LEN 4 14908 #define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_COUNTER_ID_MINNUM 0 14909 #define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_COUNTER_ID_MAXNUM 62 14910 14911 /* MC_CMD_SECURITY_RULE_COUNTER_FREE_OUT msgresponse */ 14912 #define MC_CMD_SECURITY_RULE_COUNTER_FREE_OUT_LEN 0 14913 14914 14915 /***********************************/ 14916 /* MC_CMD_SUBNET_MAP_SET_NODE 14917 * Atomically update a trie node in the map of subnets to subnet IDs. The 14918 * constants in the descriptions of the fields of this message may be retrieved 14919 * by the GET_SECURITY_RULE_INFO op of MC_CMD_GET_PARSER_DISP_INFO. (Medford- 14920 * only; for use by SolarSecure apps, not directly by drivers. See 14921 * SF-114946-SW.) NOTE - this message definition is provisional. It has not yet 14922 * been used in any released code and may change during development. This note 14923 * will be removed once it is regarded as stable. 14924 */ 14925 #define MC_CMD_SUBNET_MAP_SET_NODE 0x114 14926 #undef MC_CMD_0x114_PRIVILEGE_CTG 14927 14928 #define MC_CMD_0x114_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14929 14930 /* MC_CMD_SUBNET_MAP_SET_NODE_IN msgrequest */ 14931 #define MC_CMD_SUBNET_MAP_SET_NODE_IN_LENMIN 6 14932 #define MC_CMD_SUBNET_MAP_SET_NODE_IN_LENMAX 252 14933 #define MC_CMD_SUBNET_MAP_SET_NODE_IN_LEN(num) (4+2*(num)) 14934 /* node to update in the range 0 .. SUBNET_MAP_NUM_NODES-1 */ 14935 #define MC_CMD_SUBNET_MAP_SET_NODE_IN_NODE_ID_OFST 0 14936 /* SUBNET_MAP_NUM_ENTRIES_PER_NODE new entries; each entry is either a pointer 14937 * to the next node, expressed as an offset in the trie memory (i.e. node ID 14938 * multiplied by SUBNET_MAP_NUM_ENTRIES_PER_NODE), or a leaf value in the range 14939 * SUBNET_ID_MIN .. SUBNET_ID_MAX 14940 */ 14941 #define MC_CMD_SUBNET_MAP_SET_NODE_IN_ENTRY_OFST 4 14942 #define MC_CMD_SUBNET_MAP_SET_NODE_IN_ENTRY_LEN 2 14943 #define MC_CMD_SUBNET_MAP_SET_NODE_IN_ENTRY_MINNUM 1 14944 #define MC_CMD_SUBNET_MAP_SET_NODE_IN_ENTRY_MAXNUM 124 14945 14946 /* MC_CMD_SUBNET_MAP_SET_NODE_OUT msgresponse */ 14947 #define MC_CMD_SUBNET_MAP_SET_NODE_OUT_LEN 0 14948 14949 /* PORTRANGE_TREE_ENTRY structuredef */ 14950 #define PORTRANGE_TREE_ENTRY_LEN 4 14951 /* key for branch nodes (<= key takes left branch, > key takes right branch), 14952 * or magic value for leaf nodes 14953 */ 14954 #define PORTRANGE_TREE_ENTRY_BRANCH_KEY_OFST 0 14955 #define PORTRANGE_TREE_ENTRY_BRANCH_KEY_LEN 2 14956 #define PORTRANGE_TREE_ENTRY_LEAF_NODE_KEY 0xffff /* enum */ 14957 #define PORTRANGE_TREE_ENTRY_BRANCH_KEY_LBN 0 14958 #define PORTRANGE_TREE_ENTRY_BRANCH_KEY_WIDTH 16 14959 /* final portrange ID for leaf nodes (don't care for branch nodes) */ 14960 #define PORTRANGE_TREE_ENTRY_LEAF_PORTRANGE_ID_OFST 2 14961 #define PORTRANGE_TREE_ENTRY_LEAF_PORTRANGE_ID_LEN 2 14962 #define PORTRANGE_TREE_ENTRY_LEAF_PORTRANGE_ID_LBN 16 14963 #define PORTRANGE_TREE_ENTRY_LEAF_PORTRANGE_ID_WIDTH 16 14964 14965 14966 /***********************************/ 14967 /* MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE 14968 * Atomically update the entire tree mapping remote port ranges to portrange 14969 * IDs. The constants in the descriptions of the fields of this message may be 14970 * retrieved by the GET_SECURITY_RULE_INFO op of MC_CMD_GET_PARSER_DISP_INFO. 14971 * (Medford-only; for use by SolarSecure apps, not directly by drivers. See 14972 * SF-114946-SW.) NOTE - this message definition is provisional. It has not yet 14973 * been used in any released code and may change during development. This note 14974 * will be removed once it is regarded as stable. 14975 */ 14976 #define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE 0x115 14977 #undef MC_CMD_0x115_PRIVILEGE_CTG 14978 14979 #define MC_CMD_0x115_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14980 14981 /* MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN msgrequest */ 14982 #define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN_LENMIN 4 14983 #define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN_LENMAX 252 14984 #define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN_LEN(num) (0+4*(num)) 14985 /* PORTRANGE_TREE_NUM_ENTRIES new entries, each laid out as a 14986 * PORTRANGE_TREE_ENTRY 14987 */ 14988 #define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_OFST 0 14989 #define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_LEN 4 14990 #define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_MINNUM 1 14991 #define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_MAXNUM 63 14992 14993 /* MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_OUT msgresponse */ 14994 #define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_OUT_LEN 0 14995 14996 14997 /***********************************/ 14998 /* MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE 14999 * Atomically update the entire tree mapping remote port ranges to portrange 15000 * IDs. The constants in the descriptions of the fields of this message may be 15001 * retrieved by the GET_SECURITY_RULE_INFO op of MC_CMD_GET_PARSER_DISP_INFO. 15002 * (Medford-only; for use by SolarSecure apps, not directly by drivers. See 15003 * SF-114946-SW.) NOTE - this message definition is provisional. It has not yet 15004 * been used in any released code and may change during development. This note 15005 * will be removed once it is regarded as stable. 15006 */ 15007 #define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE 0x116 15008 #undef MC_CMD_0x116_PRIVILEGE_CTG 15009 15010 #define MC_CMD_0x116_PRIVILEGE_CTG SRIOV_CTG_ADMIN 15011 15012 /* MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN msgrequest */ 15013 #define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN_LENMIN 4 15014 #define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN_LENMAX 252 15015 #define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN_LEN(num) (0+4*(num)) 15016 /* PORTRANGE_TREE_NUM_ENTRIES new entries, each laid out as a 15017 * PORTRANGE_TREE_ENTRY 15018 */ 15019 #define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_OFST 0 15020 #define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_LEN 4 15021 #define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_MINNUM 1 15022 #define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_MAXNUM 63 15023 15024 /* MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_OUT msgresponse */ 15025 #define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_OUT_LEN 0 15026 15027 /* TUNNEL_ENCAP_UDP_PORT_ENTRY structuredef */ 15028 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_LEN 4 15029 /* UDP port (the standard ports are named below but any port may be used) */ 15030 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_OFST 0 15031 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_LEN 2 15032 /* enum: the IANA allocated UDP port for VXLAN */ 15033 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_IANA_VXLAN_UDP_PORT 0x12b5 15034 /* enum: the IANA allocated UDP port for Geneve */ 15035 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_IANA_GENEVE_UDP_PORT 0x17c1 15036 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_LBN 0 15037 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_WIDTH 16 15038 /* tunnel encapsulation protocol (only those named below are supported) */ 15039 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_OFST 2 15040 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_LEN 2 15041 /* enum: This port will be used for VXLAN on both IPv4 and IPv6 */ 15042 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_VXLAN 0x0 15043 /* enum: This port will be used for Geneve on both IPv4 and IPv6 */ 15044 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_GENEVE 0x1 15045 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_LBN 16 15046 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_WIDTH 16 15047 15048 15049 /***********************************/ 15050 /* MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS 15051 * Configure UDP ports for tunnel encapsulation hardware acceleration. The 15052 * parser-dispatcher will attempt to parse traffic on these ports as tunnel 15053 * encapsulation PDUs and filter them using the tunnel encapsulation filter 15054 * chain rather than the standard filter chain. Note that this command can 15055 * cause all functions to see a reset. (Available on Medford only.) 15056 */ 15057 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS 0x117 15058 #undef MC_CMD_0x117_PRIVILEGE_CTG 15059 15060 #define MC_CMD_0x117_PRIVILEGE_CTG SRIOV_CTG_ADMIN 15061 15062 /* MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN msgrequest */ 15063 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMIN 4 15064 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMAX 68 15065 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LEN(num) (4+4*(num)) 15066 /* Flags */ 15067 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_OFST 0 15068 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_LEN 2 15069 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING_LBN 0 15070 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING_WIDTH 1 15071 /* The number of entries in the ENTRIES array */ 15072 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_OFST 2 15073 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_LEN 2 15074 /* Entries defining the UDP port to protocol mapping, each laid out as a 15075 * TUNNEL_ENCAP_UDP_PORT_ENTRY 15076 */ 15077 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_OFST 4 15078 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_LEN 4 15079 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MINNUM 0 15080 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MAXNUM 16 15081 15082 /* MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT msgresponse */ 15083 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_LEN 2 15084 /* Flags */ 15085 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_FLAGS_OFST 0 15086 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_FLAGS_LEN 2 15087 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_LBN 0 15088 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_WIDTH 1 15089 15090 15091 /***********************************/ 15092 /* MC_CMD_RX_BALANCING 15093 * Configure a port upconverter to distribute the packets on both RX engines. 15094 * Packets are distributed based on a table with the destination vFIFO. The 15095 * index of the table is a hash of source and destination of IPV4 and VLAN 15096 * priority. 15097 */ 15098 #define MC_CMD_RX_BALANCING 0x118 15099 #undef MC_CMD_0x118_PRIVILEGE_CTG 15100 15101 #define MC_CMD_0x118_PRIVILEGE_CTG SRIOV_CTG_ADMIN 15102 15103 /* MC_CMD_RX_BALANCING_IN msgrequest */ 15104 #define MC_CMD_RX_BALANCING_IN_LEN 16 15105 /* The RX port whose upconverter table will be modified */ 15106 #define MC_CMD_RX_BALANCING_IN_PORT_OFST 0 15107 /* The VLAN priority associated to the table index and vFIFO */ 15108 #define MC_CMD_RX_BALANCING_IN_PRIORITY_OFST 4 15109 /* The resulting bit of SRC^DST for indexing the table */ 15110 #define MC_CMD_RX_BALANCING_IN_SRC_DST_OFST 8 15111 /* The RX engine to which the vFIFO in the table entry will point to */ 15112 #define MC_CMD_RX_BALANCING_IN_ENG_OFST 12 15113 15114 /* MC_CMD_RX_BALANCING_OUT msgresponse */ 15115 #define MC_CMD_RX_BALANCING_OUT_LEN 0 15116 15117 15118 /***********************************/ 15119 /* MC_CMD_TSA_BIND 15120 * TSAN - TSAC binding communication protocol. Refer to SF-115479-TC for more 15121 * info in respect to the binding protocol. This MCDI command is only available 15122 * over a TLS secure connection between the TSAN and TSAC, and is not available 15123 * to host software. Note- The messages definitions that do comprise this MCDI 15124 * command deemed as provisional. This MCDI command has not yet been used in 15125 * any released code and may change during development. This note will be 15126 * removed once it is regarded as stable. 15127 */ 15128 #define MC_CMD_TSA_BIND 0x119 15129 #undef MC_CMD_0x119_PRIVILEGE_CTG 15130 15131 #define MC_CMD_0x119_PRIVILEGE_CTG SRIOV_CTG_ADMIN 15132 15133 /* MC_CMD_TSA_BIND_IN msgrequest: Protocol operation code */ 15134 #define MC_CMD_TSA_BIND_IN_LEN 4 15135 #define MC_CMD_TSA_BIND_IN_OP_OFST 0 15136 /* enum: Retrieve the TSAN ID from a TSAN. TSAN ID is a unique identifier for 15137 * the network adapter. More specifically, TSAN ID equals the MAC address of 15138 * the network adapter. TSAN ID is used as part of the TSAN authentication 15139 * protocol. Refer to SF-114946-SW for more information. 15140 */ 15141 #define MC_CMD_TSA_BIND_OP_GET_ID 0x1 15142 /* enum: Get a binding ticket from the TSAN. The binding ticket is used as part 15143 * of the binding procedure to authorize the binding of an adapter to a TSAID. 15144 * Refer to SF-114946-SW for more information. 15145 */ 15146 #define MC_CMD_TSA_BIND_OP_GET_TICKET 0x2 15147 /* enum: Opcode associated with the propagation of a private key that TSAN uses 15148 * as part of post-binding authentication procedure. More specifically, TSAN 15149 * uses this key for a signing operation. TSAC uses the counterpart public key 15150 * to verify the signature. Note - The post-binding authentication occurs when 15151 * the TSAN-TSAC connection terminates and TSAN tries to reconnect. Refer to 15152 * SF-114946-SW for more information. 15153 */ 15154 #define MC_CMD_TSA_BIND_OP_SET_KEY 0x3 15155 /* enum: Request an unbinding operation. Note- TSAN clears the binding ticket 15156 * from the Nvram section. 15157 */ 15158 #define MC_CMD_TSA_BIND_OP_UNBIND 0x4 15159 15160 /* MC_CMD_TSA_BIND_IN_GET_ID msgrequest */ 15161 #define MC_CMD_TSA_BIND_IN_GET_ID_LEN 20 15162 /* The operation requested. */ 15163 #define MC_CMD_TSA_BIND_IN_GET_ID_OP_OFST 0 15164 /* Cryptographic nonce that TSAC generates and sends to TSAN. TSAC generates 15165 * the nonce every time as part of the TSAN post-binding authentication 15166 * procedure when the TSAN-TSAC connection terminates and TSAN does need to re- 15167 * connect to the TSAC. Refer to SF-114946-SW for more information. 15168 */ 15169 #define MC_CMD_TSA_BIND_IN_GET_ID_NONCE_OFST 4 15170 #define MC_CMD_TSA_BIND_IN_GET_ID_NONCE_LEN 16 15171 15172 /* MC_CMD_TSA_BIND_IN_GET_TICKET msgrequest */ 15173 #define MC_CMD_TSA_BIND_IN_GET_TICKET_LEN 4 15174 /* The operation requested. */ 15175 #define MC_CMD_TSA_BIND_IN_GET_TICKET_OP_OFST 0 15176 15177 /* MC_CMD_TSA_BIND_IN_SET_KEY msgrequest */ 15178 #define MC_CMD_TSA_BIND_IN_SET_KEY_LENMIN 5 15179 #define MC_CMD_TSA_BIND_IN_SET_KEY_LENMAX 252 15180 #define MC_CMD_TSA_BIND_IN_SET_KEY_LEN(num) (4+1*(num)) 15181 /* The operation requested. */ 15182 #define MC_CMD_TSA_BIND_IN_SET_KEY_OP_OFST 0 15183 /* This data blob contains the private key generated by the TSAC. TSAN uses 15184 * this key for a signing operation. Note- This private key is used in 15185 * conjunction with the post-binding TSAN authentication procedure that occurs 15186 * when the TSAN-TSAC connection terminates and TSAN tries to reconnect. Refer 15187 * to SF-114946-SW for more information. 15188 */ 15189 #define MC_CMD_TSA_BIND_IN_SET_KEY_DATKEY_OFST 4 15190 #define MC_CMD_TSA_BIND_IN_SET_KEY_DATKEY_LEN 1 15191 #define MC_CMD_TSA_BIND_IN_SET_KEY_DATKEY_MINNUM 1 15192 #define MC_CMD_TSA_BIND_IN_SET_KEY_DATKEY_MAXNUM 248 15193 15194 /* MC_CMD_TSA_BIND_IN_UNBIND msgrequest: Asks for the un-binding procedure */ 15195 #define MC_CMD_TSA_BIND_IN_UNBIND_LEN 10 15196 /* The operation requested. */ 15197 #define MC_CMD_TSA_BIND_IN_UNBIND_OP_OFST 0 15198 /* TSAN unique identifier for the network adapter */ 15199 #define MC_CMD_TSA_BIND_IN_UNBIND_TSANID_OFST 4 15200 #define MC_CMD_TSA_BIND_IN_UNBIND_TSANID_LEN 6 15201 15202 /* MC_CMD_TSA_BIND_OUT_GET_ID msgresponse */ 15203 #define MC_CMD_TSA_BIND_OUT_GET_ID_LENMIN 15 15204 #define MC_CMD_TSA_BIND_OUT_GET_ID_LENMAX 252 15205 #define MC_CMD_TSA_BIND_OUT_GET_ID_LEN(num) (14+1*(num)) 15206 /* The operation completion code. */ 15207 #define MC_CMD_TSA_BIND_OUT_GET_ID_OP_OFST 0 15208 /* Rules engine type. Note- The rules engine type allows TSAC to further 15209 * identify the connected endpoint (e.g. TSAN, NIC Emulator) type and take the 15210 * proper action accordingly. As an example, TSAC uses the rules engine type to 15211 * select the SF key that differs in the case of TSAN vs. NIC Emulator. 15212 */ 15213 #define MC_CMD_TSA_BIND_OUT_GET_ID_RULE_ENGINE_OFST 4 15214 /* enum: Hardware rules engine. */ 15215 #define MC_CMD_TSA_BIND_OUT_GET_ID_RULE_ENGINE_TSAN 0x1 15216 /* enum: Nic emulator rules engine. */ 15217 #define MC_CMD_TSA_BIND_OUT_GET_ID_RULE_ENGINE_NEMU 0x2 15218 /* enum: SSFE. */ 15219 #define MC_CMD_TSA_BIND_OUT_GET_ID_RULE_ENGINE_SSFE 0x3 15220 /* TSAN unique identifier for the network adapter */ 15221 #define MC_CMD_TSA_BIND_OUT_GET_ID_TSANID_OFST 8 15222 #define MC_CMD_TSA_BIND_OUT_GET_ID_TSANID_LEN 6 15223 /* The signature data blob. The signature is computed against the message 15224 * formed by TSAN ID concatenated with the NONCE value. Refer to SF-115479-TC 15225 * for more information also in respect to the private keys that are used to 15226 * sign the message based on TSAN pre/post-binding authentication procedure. 15227 */ 15228 #define MC_CMD_TSA_BIND_OUT_GET_ID_SIG_OFST 14 15229 #define MC_CMD_TSA_BIND_OUT_GET_ID_SIG_LEN 1 15230 #define MC_CMD_TSA_BIND_OUT_GET_ID_SIG_MINNUM 1 15231 #define MC_CMD_TSA_BIND_OUT_GET_ID_SIG_MAXNUM 238 15232 15233 /* MC_CMD_TSA_BIND_OUT_GET_TICKET msgresponse */ 15234 #define MC_CMD_TSA_BIND_OUT_GET_TICKET_LENMIN 5 15235 #define MC_CMD_TSA_BIND_OUT_GET_TICKET_LENMAX 252 15236 #define MC_CMD_TSA_BIND_OUT_GET_TICKET_LEN(num) (4+1*(num)) 15237 /* The operation completion code. */ 15238 #define MC_CMD_TSA_BIND_OUT_GET_TICKET_OP_OFST 0 15239 /* The ticket represents the data blob construct that TSAN sends to TSAC as 15240 * part of the binding protocol. From the TSAN perspective the ticket is an 15241 * opaque construct. For more info refer to SF-115479-TC. 15242 */ 15243 #define MC_CMD_TSA_BIND_OUT_GET_TICKET_TICKET_OFST 4 15244 #define MC_CMD_TSA_BIND_OUT_GET_TICKET_TICKET_LEN 1 15245 #define MC_CMD_TSA_BIND_OUT_GET_TICKET_TICKET_MINNUM 1 15246 #define MC_CMD_TSA_BIND_OUT_GET_TICKET_TICKET_MAXNUM 248 15247 15248 /* MC_CMD_TSA_BIND_OUT_SET_KEY msgresponse */ 15249 #define MC_CMD_TSA_BIND_OUT_SET_KEY_LEN 4 15250 /* The operation completion code. */ 15251 #define MC_CMD_TSA_BIND_OUT_SET_KEY_OP_OFST 0 15252 15253 /* MC_CMD_TSA_BIND_OUT_UNBIND msgresponse */ 15254 #define MC_CMD_TSA_BIND_OUT_UNBIND_LEN 8 15255 /* Same as MC_CMD_ERR field, but included as 0 in success cases */ 15256 #define MC_CMD_TSA_BIND_OUT_UNBIND_RESULT_OFST 0 15257 /* Extra status information */ 15258 #define MC_CMD_TSA_BIND_OUT_UNBIND_INFO_OFST 4 15259 /* enum: Unbind successful. */ 15260 #define MC_CMD_TSA_BIND_OUT_UNBIND_OK_UNBOUND 0x0 15261 /* enum: TSANID mismatch */ 15262 #define MC_CMD_TSA_BIND_OUT_UNBIND_ERR_BAD_TSANID 0x1 15263 /* enum: Unable to remove the binding ticket from persistent storage. */ 15264 #define MC_CMD_TSA_BIND_OUT_UNBIND_ERR_REMOVE_TICKET 0x2 15265 /* enum: TSAN is not bound to a binding ticket. */ 15266 #define MC_CMD_TSA_BIND_OUT_UNBIND_ERR_NOT_BOUND 0x3 15267 15268 15269 /***********************************/ 15270 /* MC_CMD_MANAGE_SECURITY_RULESET_CACHE 15271 * Manage the persistent NVRAM cache of security rules created with 15272 * MC_CMD_SET_SECURITY_RULE. Note that the cache is not automatically updated 15273 * as rules are added or removed; the active ruleset must be explicitly 15274 * committed to the cache. The cache may also be explicitly invalidated, 15275 * without affecting the currently active ruleset. When the cache is valid, it 15276 * will be loaded at power on or MC reboot, instead of the default ruleset. 15277 * Rollback of the currently active ruleset to the cached version (when it is 15278 * valid) is also supported. (Medford-only; for use by SolarSecure apps, not 15279 * directly by drivers. See SF-114946-SW.) NOTE - this message definition is 15280 * provisional. It has not yet been used in any released code and may change 15281 * during development. This note will be removed once it is regarded as stable. 15282 */ 15283 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE 0x11a 15284 #undef MC_CMD_0x11a_PRIVILEGE_CTG 15285 15286 #define MC_CMD_0x11a_PRIVILEGE_CTG SRIOV_CTG_ADMIN 15287 15288 /* MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN msgrequest */ 15289 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_LEN 4 15290 /* the operation to perform */ 15291 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_OP_OFST 0 15292 /* enum: reports the ruleset version that is cached in persistent storage but 15293 * performs no other action 15294 */ 15295 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_OP_GET_CACHED_VERSION 0x0 15296 /* enum: rolls back the active state to the cached version. (May fail with 15297 * ENOENT if there is no valid cached version.) 15298 */ 15299 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_OP_ROLLBACK 0x1 15300 /* enum: commits the active state to the persistent cache */ 15301 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_OP_COMMIT 0x2 15302 /* enum: invalidates the persistent cache without affecting the active state */ 15303 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_OP_INVALIDATE 0x3 15304 15305 /* MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT msgresponse */ 15306 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_LENMIN 5 15307 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_LENMAX 252 15308 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_LEN(num) (4+1*(num)) 15309 /* indicates whether the persistent cache is valid (after completion of the 15310 * requested operation in the case of rollback, commit, or invalidate) 15311 */ 15312 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_STATE_OFST 0 15313 /* enum: persistent cache is invalid (the VERSION field will be empty in this 15314 * case) 15315 */ 15316 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_STATE_INVALID 0x0 15317 /* enum: persistent cache is valid */ 15318 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_STATE_VALID 0x1 15319 /* cached ruleset version (after completion of the requested operation, in the 15320 * case of rollback, commit, or invalidate) as an opaque hash value in the same 15321 * form as MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_VERSION 15322 */ 15323 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_VERSION_OFST 4 15324 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_VERSION_LEN 1 15325 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_VERSION_MINNUM 1 15326 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_VERSION_MAXNUM 248 15327 15328 15329 /***********************************/ 15330 /* MC_CMD_NVRAM_PRIVATE_APPEND 15331 * Append a single TLV to the MC_USAGE_TLV partition. Returns MC_CMD_ERR_EEXIST 15332 * if the tag is already present. 15333 */ 15334 #define MC_CMD_NVRAM_PRIVATE_APPEND 0x11c 15335 #undef MC_CMD_0x11c_PRIVILEGE_CTG 15336 15337 #define MC_CMD_0x11c_PRIVILEGE_CTG SRIOV_CTG_ADMIN 15338 15339 /* MC_CMD_NVRAM_PRIVATE_APPEND_IN msgrequest */ 15340 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_LENMIN 9 15341 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_LENMAX 252 15342 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_LEN(num) (8+1*(num)) 15343 /* The tag to be appended */ 15344 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_TAG_OFST 0 15345 /* The length of the data */ 15346 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_LENGTH_OFST 4 15347 /* The data to be contained in the TLV structure */ 15348 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_OFST 8 15349 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_LEN 1 15350 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_MINNUM 1 15351 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_MAXNUM 244 15352 15353 /* MC_CMD_NVRAM_PRIVATE_APPEND_OUT msgresponse */ 15354 #define MC_CMD_NVRAM_PRIVATE_APPEND_OUT_LEN 0 15355 15356 15357 /***********************************/ 15358 /* MC_CMD_XPM_VERIFY_CONTENTS 15359 * Verify that the contents of the XPM memory is correct (Medford only). This 15360 * is used during manufacture to check that the XPM memory has been programmed 15361 * correctly at ATE. 15362 */ 15363 #define MC_CMD_XPM_VERIFY_CONTENTS 0x11b 15364 #undef MC_CMD_0x11b_PRIVILEGE_CTG 15365 15366 #define MC_CMD_0x11b_PRIVILEGE_CTG SRIOV_CTG_ADMIN 15367 15368 /* MC_CMD_XPM_VERIFY_CONTENTS_IN msgrequest */ 15369 #define MC_CMD_XPM_VERIFY_CONTENTS_IN_LEN 4 15370 /* Data type to be checked */ 15371 #define MC_CMD_XPM_VERIFY_CONTENTS_IN_DATA_TYPE_OFST 0 15372 15373 /* MC_CMD_XPM_VERIFY_CONTENTS_OUT msgresponse */ 15374 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_LENMIN 12 15375 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_LENMAX 252 15376 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_LEN(num) (12+1*(num)) 15377 /* Number of sectors found (test builds only) */ 15378 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_NUM_SECTORS_OFST 0 15379 /* Number of bytes found (test builds only) */ 15380 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_NUM_BYTES_OFST 4 15381 /* Length of signature */ 15382 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIG_LENGTH_OFST 8 15383 /* Signature */ 15384 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_OFST 12 15385 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_LEN 1 15386 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_MINNUM 0 15387 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_MAXNUM 240 15388 15389 15390 /***********************************/ 15391 /* MC_CMD_SET_EVQ_TMR 15392 * Update the timer load, timer reload and timer mode values for a given EVQ. 15393 * The requested timer values (in TMR_LOAD_REQ_NS and TMR_RELOAD_REQ_NS) will 15394 * be rounded up to the granularity supported by the hardware, then truncated 15395 * to the range supported by the hardware. The resulting value after the 15396 * rounding and truncation will be returned to the caller (in TMR_LOAD_ACT_NS 15397 * and TMR_RELOAD_ACT_NS). 15398 */ 15399 #define MC_CMD_SET_EVQ_TMR 0x120 15400 #undef MC_CMD_0x120_PRIVILEGE_CTG 15401 15402 #define MC_CMD_0x120_PRIVILEGE_CTG SRIOV_CTG_GENERAL 15403 15404 /* MC_CMD_SET_EVQ_TMR_IN msgrequest */ 15405 #define MC_CMD_SET_EVQ_TMR_IN_LEN 16 15406 /* Function-relative queue instance */ 15407 #define MC_CMD_SET_EVQ_TMR_IN_INSTANCE_OFST 0 15408 /* Requested value for timer load (in nanoseconds) */ 15409 #define MC_CMD_SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS_OFST 4 15410 /* Requested value for timer reload (in nanoseconds) */ 15411 #define MC_CMD_SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS_OFST 8 15412 /* Timer mode. Meanings as per EVQ_TMR_REG.TC_TIMER_VAL */ 15413 #define MC_CMD_SET_EVQ_TMR_IN_TMR_MODE_OFST 12 15414 #define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_DIS 0x0 /* enum */ 15415 #define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_IMMED_START 0x1 /* enum */ 15416 #define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_TRIG_START 0x2 /* enum */ 15417 #define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_INT_HLDOFF 0x3 /* enum */ 15418 15419 /* MC_CMD_SET_EVQ_TMR_OUT msgresponse */ 15420 #define MC_CMD_SET_EVQ_TMR_OUT_LEN 8 15421 /* Actual value for timer load (in nanoseconds) */ 15422 #define MC_CMD_SET_EVQ_TMR_OUT_TMR_LOAD_ACT_NS_OFST 0 15423 /* Actual value for timer reload (in nanoseconds) */ 15424 #define MC_CMD_SET_EVQ_TMR_OUT_TMR_RELOAD_ACT_NS_OFST 4 15425 15426 15427 /***********************************/ 15428 /* MC_CMD_GET_EVQ_TMR_PROPERTIES 15429 * Query properties about the event queue timers. 15430 */ 15431 #define MC_CMD_GET_EVQ_TMR_PROPERTIES 0x122 15432 #undef MC_CMD_0x122_PRIVILEGE_CTG 15433 15434 #define MC_CMD_0x122_PRIVILEGE_CTG SRIOV_CTG_GENERAL 15435 15436 /* MC_CMD_GET_EVQ_TMR_PROPERTIES_IN msgrequest */ 15437 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_IN_LEN 0 15438 15439 /* MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT msgresponse */ 15440 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN 36 15441 /* Reserved for future use. */ 15442 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_FLAGS_OFST 0 15443 /* For timers updated via writes to EVQ_TMR_REG, this is the time interval (in 15444 * nanoseconds) for each increment of the timer load/reload count. The 15445 * requested duration of a timer is this value multiplied by the timer 15446 * load/reload count. 15447 */ 15448 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_NS_PER_COUNT_OFST 4 15449 /* For timers updated via writes to EVQ_TMR_REG, this is the maximum value 15450 * allowed for timer load/reload counts. 15451 */ 15452 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_MAX_COUNT_OFST 8 15453 /* For timers updated via writes to EVQ_TMR_REG, timer load/reload counts not a 15454 * multiple of this step size will be rounded in an implementation defined 15455 * manner. 15456 */ 15457 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_STEP_OFST 12 15458 /* Maximum timer duration (in nanoseconds) for timers updated via MCDI. Only 15459 * meaningful if MC_CMD_SET_EVQ_TMR is implemented. 15460 */ 15461 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_MAX_NS_OFST 16 15462 /* Timer durations requested via MCDI that are not a multiple of this step size 15463 * will be rounded up. Only meaningful if MC_CMD_SET_EVQ_TMR is implemented. 15464 */ 15465 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_STEP_NS_OFST 20 15466 /* For timers updated using the bug35388 workaround, this is the time interval 15467 * (in nanoseconds) for each increment of the timer load/reload count. The 15468 * requested duration of a timer is this value multiplied by the timer 15469 * load/reload count. This field is only meaningful if the bug35388 workaround 15470 * is enabled. 15471 */ 15472 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_NS_PER_COUNT_OFST 24 15473 /* For timers updated using the bug35388 workaround, this is the maximum value 15474 * allowed for timer load/reload counts. This field is only meaningful if the 15475 * bug35388 workaround is enabled. 15476 */ 15477 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_MAX_COUNT_OFST 28 15478 /* For timers updated using the bug35388 workaround, timer load/reload counts 15479 * not a multiple of this step size will be rounded in an implementation 15480 * defined manner. This field is only meaningful if the bug35388 workaround is 15481 * enabled. 15482 */ 15483 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_STEP_OFST 32 15484 15485 15486 /***********************************/ 15487 /* MC_CMD_ALLOCATE_TX_VFIFO_CP 15488 * When we use the TX_vFIFO_ULL mode, we can allocate common pools using the 15489 * non used switch buffers. 15490 */ 15491 #define MC_CMD_ALLOCATE_TX_VFIFO_CP 0x11d 15492 #undef MC_CMD_0x11d_PRIVILEGE_CTG 15493 15494 #define MC_CMD_0x11d_PRIVILEGE_CTG SRIOV_CTG_ADMIN 15495 15496 /* MC_CMD_ALLOCATE_TX_VFIFO_CP_IN msgrequest */ 15497 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_LEN 20 15498 /* Desired instance. Must be set to a specific instance, which is a function 15499 * local queue index. 15500 */ 15501 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_INSTANCE_OFST 0 15502 /* Will the common pool be used as TX_vFIFO_ULL (1) */ 15503 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_MODE_OFST 4 15504 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_ENABLED 0x1 /* enum */ 15505 /* enum: Using this interface without TX_vFIFO_ULL is not supported for now */ 15506 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_DISABLED 0x0 15507 /* Number of buffers to reserve for the common pool */ 15508 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_SIZE_OFST 8 15509 /* TX datapath to which the Common Pool is connected to. */ 15510 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_INGRESS_OFST 12 15511 /* enum: Extracts information from function */ 15512 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_USE_FUNCTION_VALUE -0x1 15513 /* Network port or RX Engine to which the common pool connects. */ 15514 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_EGRESS_OFST 16 15515 /* enum: Extracts information from function */ 15516 /* MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_USE_FUNCTION_VALUE -0x1 */ 15517 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT0 0x0 /* enum */ 15518 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT1 0x1 /* enum */ 15519 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT2 0x2 /* enum */ 15520 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT3 0x3 /* enum */ 15521 /* enum: To enable Switch loopback with Rx engine 0 */ 15522 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_RX_ENGINE0 0x4 15523 /* enum: To enable Switch loopback with Rx engine 1 */ 15524 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_RX_ENGINE1 0x5 15525 15526 /* MC_CMD_ALLOCATE_TX_VFIFO_CP_OUT msgresponse */ 15527 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_OUT_LEN 4 15528 /* ID of the common pool allocated */ 15529 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_OUT_CP_ID_OFST 0 15530 15531 15532 /***********************************/ 15533 /* MC_CMD_ALLOCATE_TX_VFIFO_VFIFO 15534 * When we use the TX_vFIFO_ULL mode, we can allocate vFIFOs using the 15535 * previously allocated common pools. 15536 */ 15537 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO 0x11e 15538 #undef MC_CMD_0x11e_PRIVILEGE_CTG 15539 15540 #define MC_CMD_0x11e_PRIVILEGE_CTG SRIOV_CTG_ADMIN 15541 15542 /* MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN msgrequest */ 15543 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_LEN 20 15544 /* Common pool previously allocated to which the new vFIFO will be associated 15545 */ 15546 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_CP_OFST 0 15547 /* Port or RX engine to associate the vFIFO egress */ 15548 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_EGRESS_OFST 4 15549 /* enum: Extracts information from common pool */ 15550 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_USE_CP_VALUE -0x1 15551 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT0 0x0 /* enum */ 15552 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT1 0x1 /* enum */ 15553 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT2 0x2 /* enum */ 15554 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT3 0x3 /* enum */ 15555 /* enum: To enable Switch loopback with Rx engine 0 */ 15556 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_RX_ENGINE0 0x4 15557 /* enum: To enable Switch loopback with Rx engine 1 */ 15558 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_RX_ENGINE1 0x5 15559 /* Minimum number of buffers that the pool must have */ 15560 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_SIZE_OFST 8 15561 /* enum: Do not check the space available */ 15562 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_NO_MINIMUM 0x0 15563 /* Will the vFIFO be used as TX_vFIFO_ULL */ 15564 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_MODE_OFST 12 15565 /* Network priority of the vFIFO,if applicable */ 15566 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PRIORITY_OFST 16 15567 /* enum: Search for the lowest unused priority */ 15568 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_LOWEST_AVAILABLE -0x1 15569 15570 /* MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT msgresponse */ 15571 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_LEN 8 15572 /* Short vFIFO ID */ 15573 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_VID_OFST 0 15574 /* Network priority of the vFIFO */ 15575 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_PRIORITY_OFST 4 15576 15577 15578 /***********************************/ 15579 /* MC_CMD_TEARDOWN_TX_VFIFO_VF 15580 * This interface clears the configuration of the given vFIFO and leaves it 15581 * ready to be re-used. 15582 */ 15583 #define MC_CMD_TEARDOWN_TX_VFIFO_VF 0x11f 15584 #undef MC_CMD_0x11f_PRIVILEGE_CTG 15585 15586 #define MC_CMD_0x11f_PRIVILEGE_CTG SRIOV_CTG_ADMIN 15587 15588 /* MC_CMD_TEARDOWN_TX_VFIFO_VF_IN msgrequest */ 15589 #define MC_CMD_TEARDOWN_TX_VFIFO_VF_IN_LEN 4 15590 /* Short vFIFO ID */ 15591 #define MC_CMD_TEARDOWN_TX_VFIFO_VF_IN_VFIFO_OFST 0 15592 15593 /* MC_CMD_TEARDOWN_TX_VFIFO_VF_OUT msgresponse */ 15594 #define MC_CMD_TEARDOWN_TX_VFIFO_VF_OUT_LEN 0 15595 15596 15597 /***********************************/ 15598 /* MC_CMD_DEALLOCATE_TX_VFIFO_CP 15599 * This interface clears the configuration of the given common pool and leaves 15600 * it ready to be re-used. 15601 */ 15602 #define MC_CMD_DEALLOCATE_TX_VFIFO_CP 0x121 15603 #undef MC_CMD_0x121_PRIVILEGE_CTG 15604 15605 #define MC_CMD_0x121_PRIVILEGE_CTG SRIOV_CTG_ADMIN 15606 15607 /* MC_CMD_DEALLOCATE_TX_VFIFO_CP_IN msgrequest */ 15608 #define MC_CMD_DEALLOCATE_TX_VFIFO_CP_IN_LEN 4 15609 /* Common pool ID given when pool allocated */ 15610 #define MC_CMD_DEALLOCATE_TX_VFIFO_CP_IN_POOL_ID_OFST 0 15611 15612 /* MC_CMD_DEALLOCATE_TX_VFIFO_CP_OUT msgresponse */ 15613 #define MC_CMD_DEALLOCATE_TX_VFIFO_CP_OUT_LEN 0 15614 15615 15616 /***********************************/ 15617 /* MC_CMD_REKEY 15618 * This request causes the NIC to generate a new per-NIC key and program it 15619 * into the write-once memory. During the process all flash partitions that are 15620 * protected with a CMAC are verified with the old per-NIC key and then signed 15621 * with the new per-NIC key. If the NIC has already reached its rekey limit the 15622 * REKEY op will return MC_CMD_ERR_ERANGE. The REKEY op may block until 15623 * completion or it may return 0 and continue processing, therefore the caller 15624 * must poll at least once to confirm that the rekeying has completed. The POLL 15625 * operation returns MC_CMD_ERR_EBUSY if the rekey process is still running 15626 * otherwise it will return the result of the last completed rekey operation, 15627 * or 0 if there has not been a previous rekey. 15628 */ 15629 #define MC_CMD_REKEY 0x123 15630 #undef MC_CMD_0x123_PRIVILEGE_CTG 15631 15632 #define MC_CMD_0x123_PRIVILEGE_CTG SRIOV_CTG_ADMIN 15633 15634 /* MC_CMD_REKEY_IN msgrequest */ 15635 #define MC_CMD_REKEY_IN_LEN 4 15636 /* the type of operation requested */ 15637 #define MC_CMD_REKEY_IN_OP_OFST 0 15638 /* enum: Start the rekeying operation */ 15639 #define MC_CMD_REKEY_IN_OP_REKEY 0x0 15640 /* enum: Poll for completion of the rekeying operation */ 15641 #define MC_CMD_REKEY_IN_OP_POLL 0x1 15642 15643 /* MC_CMD_REKEY_OUT msgresponse */ 15644 #define MC_CMD_REKEY_OUT_LEN 0 15645 15646 15647 /***********************************/ 15648 /* MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS 15649 * This interface allows the host to find out how many common pool buffers are 15650 * not yet assigned. 15651 */ 15652 #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS 0x124 15653 #undef MC_CMD_0x124_PRIVILEGE_CTG 15654 15655 #define MC_CMD_0x124_PRIVILEGE_CTG SRIOV_CTG_ADMIN 15656 15657 /* MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_IN msgrequest */ 15658 #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_IN_LEN 0 15659 15660 /* MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT msgresponse */ 15661 #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_LEN 8 15662 /* Available buffers for the ENG to NET vFIFOs. */ 15663 #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_NET_OFST 0 15664 /* Available buffers for the ENG to ENG and NET to ENG vFIFOs. */ 15665 #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_ENG_OFST 4 15666 15667 15668 /***********************************/ 15669 /* MC_CMD_SET_SECURITY_FUSES 15670 * Change the security level of the adapter by setting bits in the write-once 15671 * memory. The firmware maps each flag in the message to a set of one or more 15672 * hardware-defined or software-defined bits and sets these bits in the write- 15673 * once memory. For Medford the hardware-defined bits are defined in 15674 * SF-112079-PS 5.3, the software-defined bits are defined in xpm.h. Returns 0 15675 * if all of the required bits were set and returns MC_CMD_ERR_EIO if any of 15676 * the required bits were not set. 15677 */ 15678 #define MC_CMD_SET_SECURITY_FUSES 0x126 15679 #undef MC_CMD_0x126_PRIVILEGE_CTG 15680 15681 #define MC_CMD_0x126_PRIVILEGE_CTG SRIOV_CTG_ADMIN 15682 15683 /* MC_CMD_SET_SECURITY_FUSES_IN msgrequest */ 15684 #define MC_CMD_SET_SECURITY_FUSES_IN_LEN 4 15685 /* Flags specifying what type of security features are being set */ 15686 #define MC_CMD_SET_SECURITY_FUSES_IN_FLAGS_OFST 0 15687 #define MC_CMD_SET_SECURITY_FUSES_IN_SECURE_BOOT_LBN 0 15688 #define MC_CMD_SET_SECURITY_FUSES_IN_SECURE_BOOT_WIDTH 1 15689 #define MC_CMD_SET_SECURITY_FUSES_IN_REJECT_TEST_SIGNED_LBN 1 15690 #define MC_CMD_SET_SECURITY_FUSES_IN_REJECT_TEST_SIGNED_WIDTH 1 15691 15692 /* MC_CMD_SET_SECURITY_FUSES_OUT msgresponse */ 15693 #define MC_CMD_SET_SECURITY_FUSES_OUT_LEN 0 15694 15695 #endif /* _SIENA_MC_DRIVER_PCOL_H */ 15696