1 /*- 2 * Copyright 2008-2013 Solarflare Communications Inc. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #ifndef _SIENA_MC_DRIVER_PCOL_H 29 #define _SIENA_MC_DRIVER_PCOL_H 30 31 32 /* Values to be written into FMCR_CZ_RESET_STATE_REG to control boot. */ 33 /* Power-on reset state */ 34 #define MC_FW_STATE_POR (1) 35 /* If this is set in MC_RESET_STATE_REG then it should be 36 * possible to jump into IMEM without loading code from flash. */ 37 #define MC_FW_WARM_BOOT_OK (2) 38 /* The MC main image has started to boot. */ 39 #define MC_FW_STATE_BOOTING (4) 40 /* The Scheduler has started. */ 41 #define MC_FW_STATE_SCHED (8) 42 /* If this is set in MC_RESET_STATE_REG then it should be 43 * possible to jump into IMEM without loading code from flash. 44 * Unlike a warm boot, assume DMEM has been reloaded, so that 45 * the MC persistent data must be reinitialised. */ 46 #define MC_FW_TEPID_BOOT_OK (16) 47 /* We have entered the main firmware via recovery mode. This 48 * means that MC persistent data must be reinitialised, but that 49 * we shouldn't touch PCIe config. */ 50 #define MC_FW_RECOVERY_MODE_PCIE_INIT_OK (32) 51 /* BIST state has been initialized */ 52 #define MC_FW_BIST_INIT_OK (128) 53 54 /* Siena MC shared memmory offsets */ 55 /* The 'doorbell' addresses are hard-wired to alert the MC when written */ 56 #define MC_SMEM_P0_DOORBELL_OFST 0x000 57 #define MC_SMEM_P1_DOORBELL_OFST 0x004 58 /* The rest of these are firmware-defined */ 59 #define MC_SMEM_P0_PDU_OFST 0x008 60 #define MC_SMEM_P1_PDU_OFST 0x108 61 #define MC_SMEM_PDU_LEN 0x100 62 #define MC_SMEM_P0_PTP_TIME_OFST 0x7f0 63 #define MC_SMEM_P0_STATUS_OFST 0x7f8 64 #define MC_SMEM_P1_STATUS_OFST 0x7fc 65 66 /* Values to be written to the per-port status dword in shared 67 * memory on reboot and assert */ 68 #define MC_STATUS_DWORD_REBOOT (0xb007b007) 69 #define MC_STATUS_DWORD_ASSERT (0xdeaddead) 70 71 /* Check whether an mcfw version (in host order) belongs to a bootloader */ 72 #define MC_FW_VERSION_IS_BOOTLOADER(_v) (((_v) >> 16) == 0xb007) 73 74 /* The current version of the MCDI protocol. 75 * 76 * Note that the ROM burnt into the card only talks V0, so at the very 77 * least every driver must support version 0 and MCDI_PCOL_VERSION 78 */ 79 #ifdef WITH_MCDI_V2 80 #define MCDI_PCOL_VERSION 2 81 #else 82 #define MCDI_PCOL_VERSION 1 83 #endif 84 85 /* Unused commands: 0x23, 0x27, 0x30, 0x31 */ 86 87 /* MCDI version 1 88 * 89 * Each MCDI request starts with an MCDI_HEADER, which is a 32bit 90 * structure, filled in by the client. 91 * 92 * 0 7 8 16 20 22 23 24 31 93 * | CODE | R | LEN | SEQ | Rsvd | E | R | XFLAGS | 94 * | | | 95 * | | \--- Response 96 * | \------- Error 97 * \------------------------------ Resync (always set) 98 * 99 * The client writes it's request into MC shared memory, and rings the 100 * doorbell. Each request is completed by either by the MC writting 101 * back into shared memory, or by writting out an event. 102 * 103 * All MCDI commands support completion by shared memory response. Each 104 * request may also contain additional data (accounted for by HEADER.LEN), 105 * and some response's may also contain additional data (again, accounted 106 * for by HEADER.LEN). 107 * 108 * Some MCDI commands support completion by event, in which any associated 109 * response data is included in the event. 110 * 111 * The protocol requires one response to be delivered for every request, a 112 * request should not be sent unless the response for the previous request 113 * has been received (either by polling shared memory, or by receiving 114 * an event). 115 */ 116 117 /** Request/Response structure */ 118 #define MCDI_HEADER_OFST 0 119 #define MCDI_HEADER_CODE_LBN 0 120 #define MCDI_HEADER_CODE_WIDTH 7 121 #define MCDI_HEADER_RESYNC_LBN 7 122 #define MCDI_HEADER_RESYNC_WIDTH 1 123 #define MCDI_HEADER_DATALEN_LBN 8 124 #define MCDI_HEADER_DATALEN_WIDTH 8 125 #define MCDI_HEADER_SEQ_LBN 16 126 #define MCDI_HEADER_SEQ_WIDTH 4 127 #define MCDI_HEADER_RSVD_LBN 20 128 #define MCDI_HEADER_RSVD_WIDTH 1 129 #define MCDI_HEADER_NOT_EPOCH_LBN 21 130 #define MCDI_HEADER_NOT_EPOCH_WIDTH 1 131 #define MCDI_HEADER_ERROR_LBN 22 132 #define MCDI_HEADER_ERROR_WIDTH 1 133 #define MCDI_HEADER_RESPONSE_LBN 23 134 #define MCDI_HEADER_RESPONSE_WIDTH 1 135 #define MCDI_HEADER_XFLAGS_LBN 24 136 #define MCDI_HEADER_XFLAGS_WIDTH 8 137 /* Request response using event */ 138 #define MCDI_HEADER_XFLAGS_EVREQ 0x01 139 140 /* Maximum number of payload bytes */ 141 #define MCDI_CTL_SDU_LEN_MAX_V1 0xfc 142 #define MCDI_CTL_SDU_LEN_MAX_V2 0x400 143 144 #ifdef WITH_MCDI_V2 145 #define MCDI_CTL_SDU_LEN_MAX MCDI_CTL_SDU_LEN_MAX_V2 146 #else 147 #define MCDI_CTL_SDU_LEN_MAX MCDI_CTL_SDU_LEN_MAX_V1 148 #endif 149 150 151 /* The MC can generate events for two reasons: 152 * - To complete a shared memory request if XFLAGS_EVREQ was set 153 * - As a notification (link state, i2c event), controlled 154 * via MC_CMD_LOG_CTRL 155 * 156 * Both events share a common structure: 157 * 158 * 0 32 33 36 44 52 60 159 * | Data | Cont | Level | Src | Code | Rsvd | 160 * | 161 * \ There is another event pending in this notification 162 * 163 * If Code==CMDDONE, then the fields are further interpreted as: 164 * 165 * - LEVEL==INFO Command succeeded 166 * - LEVEL==ERR Command failed 167 * 168 * 0 8 16 24 32 169 * | Seq | Datalen | Errno | Rsvd | 170 * 171 * These fields are taken directly out of the standard MCDI header, i.e., 172 * LEVEL==ERR, Datalen == 0 => Reboot 173 * 174 * Events can be squirted out of the UART (using LOG_CTRL) without a 175 * MCDI header. An event can be distinguished from a MCDI response by 176 * examining the first byte which is 0xc0. This corresponds to the 177 * non-existent MCDI command MC_CMD_DEBUG_LOG. 178 * 179 * 0 7 8 180 * | command | Resync | = 0xc0 181 * 182 * Since the event is written in big-endian byte order, this works 183 * providing bits 56-63 of the event are 0xc0. 184 * 185 * 56 60 63 186 * | Rsvd | Code | = 0xc0 187 * 188 * Which means for convenience the event code is 0xc for all MC 189 * generated events. 190 */ 191 #define FSE_AZ_EV_CODE_MCDI_EVRESPONSE 0xc 192 193 194 /* Operation not permitted. */ 195 #define MC_CMD_ERR_EPERM 1 196 /* Non-existent command target */ 197 #define MC_CMD_ERR_ENOENT 2 198 /* assert() has killed the MC */ 199 #define MC_CMD_ERR_EINTR 4 200 /* I/O failure */ 201 #define MC_CMD_ERR_EIO 5 202 /* Already exists */ 203 #define MC_CMD_ERR_EEXIST 6 204 /* Try again */ 205 #define MC_CMD_ERR_EAGAIN 11 206 /* Out of memory */ 207 #define MC_CMD_ERR_ENOMEM 12 208 /* Caller does not hold required locks */ 209 #define MC_CMD_ERR_EACCES 13 210 /* Resource is currently unavailable (e.g. lock contention) */ 211 #define MC_CMD_ERR_EBUSY 16 212 /* No such device */ 213 #define MC_CMD_ERR_ENODEV 19 214 /* Invalid argument to target */ 215 #define MC_CMD_ERR_EINVAL 22 216 /* Broken pipe */ 217 #define MC_CMD_ERR_EPIPE 32 218 /* Read-only */ 219 #define MC_CMD_ERR_EROFS 30 220 /* Out of range */ 221 #define MC_CMD_ERR_ERANGE 34 222 /* Non-recursive resource is already acquired */ 223 #define MC_CMD_ERR_EDEADLK 35 224 /* Operation not implemented */ 225 #define MC_CMD_ERR_ENOSYS 38 226 /* Operation timed out */ 227 #define MC_CMD_ERR_ETIME 62 228 /* Link has been severed */ 229 #define MC_CMD_ERR_ENOLINK 67 230 /* Protocol error */ 231 #define MC_CMD_ERR_EPROTO 71 232 /* Operation not supported */ 233 #define MC_CMD_ERR_ENOTSUP 95 234 /* Address not available */ 235 #define MC_CMD_ERR_EADDRNOTAVAIL 99 236 /* Not connected */ 237 #define MC_CMD_ERR_ENOTCONN 107 238 /* Operation already in progress */ 239 #define MC_CMD_ERR_EALREADY 114 240 241 /* Resource allocation failed. */ 242 #define MC_CMD_ERR_ALLOC_FAIL 0x1000 243 /* V-adaptor not found. */ 244 #define MC_CMD_ERR_NO_VADAPTOR 0x1001 245 /* EVB port not found. */ 246 #define MC_CMD_ERR_NO_EVB_PORT 0x1002 247 /* V-switch not found. */ 248 #define MC_CMD_ERR_NO_VSWITCH 0x1003 249 /* Too many VLAN tags. */ 250 #define MC_CMD_ERR_VLAN_LIMIT 0x1004 251 /* Bad PCI function number. */ 252 #define MC_CMD_ERR_BAD_PCI_FUNC 0x1005 253 /* Invalid VLAN mode. */ 254 #define MC_CMD_ERR_BAD_VLAN_MODE 0x1006 255 /* Invalid v-switch type. */ 256 #define MC_CMD_ERR_BAD_VSWITCH_TYPE 0x1007 257 /* Invalid v-port type. */ 258 #define MC_CMD_ERR_BAD_VPORT_TYPE 0x1008 259 /* MAC address exists. */ 260 #define MC_CMD_ERR_MAC_EXIST 0x1009 261 /* Slave core not present */ 262 #define MC_CMD_ERR_SLAVE_NOT_PRESENT 0x100a 263 /* The datapath is disabled. */ 264 #define MC_CMD_ERR_DATAPATH_DISABLED 0x100b 265 /* The requesting client is not a function */ 266 #define MC_CMD_ERR_CLIENT_NOT_FN 0x100c 267 /* The requested operation might require the 268 command to be passed between MCs, and the 269 transport doesn't support that. Should 270 only ever been seen over the UART. */ 271 #define MC_CMD_ERR_TRANSPORT_NOPROXY 0x100d 272 /* VLAN tag(s) exists */ 273 #define MC_CMD_ERR_VLAN_EXIST 0x100e 274 /* No MAC address assigned to an EVB port */ 275 #define MC_CMD_ERR_NO_MAC_ADDR 0x100f 276 /* Notifies the driver that the request has been relayed 277 * to an admin function for authorization. The driver should 278 * wait for a PROXY_RESPONSE event and then resend its request. 279 * This error code is followed by a 32-bit handle that 280 * helps matching it with the respective PROXY_RESPONSE event. */ 281 #define MC_CMD_ERR_PROXY_PENDING 0x1010 282 #define MC_CMD_ERR_PROXY_PENDING_HANDLE_OFST 4 283 /* The request cannot be passed for authorization because 284 * another request from the same function is currently being 285 * authorized. The drvier should try again later. */ 286 #define MC_CMD_ERR_PROXY_INPROGRESS 0x1011 287 /* Returned by MC_CMD_PROXY_COMPLETE if the caller is not the function 288 * that has enabled proxying or BLOCK_INDEX points to a function that 289 * doesn't await an authorization. */ 290 #define MC_CMD_ERR_PROXY_UNEXPECTED 0x1012 291 /* This code is currently only used internally in FW. Its meaning is that 292 * an operation failed due to lack of SR-IOV privilege. 293 * Normally it is translated to EPERM by send_cmd_err(), 294 * but it may also be used to trigger some special mechanism 295 * for handling such case, e.g. to relay the failed request 296 * to a designated admin function for authorization. */ 297 #define MC_CMD_ERR_NO_PRIVILEGE 0x1013 298 /* Workaround 26807 could not be turned on/off because some functions 299 * have already installed filters. See the comment at 300 * MC_CMD_WORKAROUND_BUG26807. */ 301 #define MC_CMD_ERR_FILTERS_PRESENT 0x1014 302 /* The clock whose frequency you've attempted to set set 303 * doesn't exist on this NIC */ 304 #define MC_CMD_ERR_NO_CLOCK 0x1015 305 306 #define MC_CMD_ERR_CODE_OFST 0 307 308 /* We define 8 "escape" commands to allow 309 for command number space extension */ 310 311 #define MC_CMD_CMD_SPACE_ESCAPE_0 0x78 312 #define MC_CMD_CMD_SPACE_ESCAPE_1 0x79 313 #define MC_CMD_CMD_SPACE_ESCAPE_2 0x7A 314 #define MC_CMD_CMD_SPACE_ESCAPE_3 0x7B 315 #define MC_CMD_CMD_SPACE_ESCAPE_4 0x7C 316 #define MC_CMD_CMD_SPACE_ESCAPE_5 0x7D 317 #define MC_CMD_CMD_SPACE_ESCAPE_6 0x7E 318 #define MC_CMD_CMD_SPACE_ESCAPE_7 0x7F 319 320 /* Vectors in the boot ROM */ 321 /* Point to the copycode entry point. */ 322 #define SIENA_MC_BOOTROM_COPYCODE_VEC (0x800 - 3 * 0x4) 323 #define HUNT_MC_BOOTROM_COPYCODE_VEC (0x8000 - 3 * 0x4) 324 #define MEDFORD_MC_BOOTROM_COPYCODE_VEC (0x10000 - 3 * 0x4) 325 /* Points to the recovery mode entry point. */ 326 #define SIENA_MC_BOOTROM_NOFLASH_VEC (0x800 - 2 * 0x4) 327 #define HUNT_MC_BOOTROM_NOFLASH_VEC (0x8000 - 2 * 0x4) 328 #define MEDFORD_MC_BOOTROM_NOFLASH_VEC (0x10000 - 2 * 0x4) 329 330 /* The command set exported by the boot ROM (MCDI v0) */ 331 #define MC_CMD_GET_VERSION_V0_SUPPORTED_FUNCS { \ 332 (1 << MC_CMD_READ32) | \ 333 (1 << MC_CMD_WRITE32) | \ 334 (1 << MC_CMD_COPYCODE) | \ 335 (1 << MC_CMD_GET_VERSION), \ 336 0, 0, 0 } 337 338 #define MC_CMD_SENSOR_INFO_OUT_OFFSET_OFST(_x) \ 339 (MC_CMD_SENSOR_ENTRY_OFST + (_x)) 340 341 #define MC_CMD_DBI_WRITE_IN_ADDRESS_OFST(n) \ 342 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \ 343 MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST + \ 344 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN) 345 346 #define MC_CMD_DBI_WRITE_IN_BYTE_MASK_OFST(n) \ 347 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \ 348 MC_CMD_DBIWROP_TYPEDEF_BYTE_MASK_OFST + \ 349 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN) 350 351 #define MC_CMD_DBI_WRITE_IN_VALUE_OFST(n) \ 352 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \ 353 MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST + \ 354 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN) 355 356 /* This may be ORed with an EVB_PORT_ID_xxx constant to pass a non-default 357 * stack ID (which must be in the range 1-255) along with an EVB port ID. 358 */ 359 #define EVB_STACK_ID(n) (((n) & 0xff) << 16) 360 361 362 #ifdef WITH_MCDI_V2 363 364 /* Version 2 adds an optional argument to error returns: the errno value 365 * may be followed by the (0-based) number of the first argument that 366 * could not be processed. 367 */ 368 #define MC_CMD_ERR_ARG_OFST 4 369 370 /* No space */ 371 #define MC_CMD_ERR_ENOSPC 28 372 373 #endif 374 375 /* MCDI_EVENT structuredef */ 376 #define MCDI_EVENT_LEN 8 377 #define MCDI_EVENT_CONT_LBN 32 378 #define MCDI_EVENT_CONT_WIDTH 1 379 #define MCDI_EVENT_LEVEL_LBN 33 380 #define MCDI_EVENT_LEVEL_WIDTH 3 381 /* enum: Info. */ 382 #define MCDI_EVENT_LEVEL_INFO 0x0 383 /* enum: Warning. */ 384 #define MCDI_EVENT_LEVEL_WARN 0x1 385 /* enum: Error. */ 386 #define MCDI_EVENT_LEVEL_ERR 0x2 387 /* enum: Fatal. */ 388 #define MCDI_EVENT_LEVEL_FATAL 0x3 389 #define MCDI_EVENT_DATA_OFST 0 390 #define MCDI_EVENT_CMDDONE_SEQ_LBN 0 391 #define MCDI_EVENT_CMDDONE_SEQ_WIDTH 8 392 #define MCDI_EVENT_CMDDONE_DATALEN_LBN 8 393 #define MCDI_EVENT_CMDDONE_DATALEN_WIDTH 8 394 #define MCDI_EVENT_CMDDONE_ERRNO_LBN 16 395 #define MCDI_EVENT_CMDDONE_ERRNO_WIDTH 8 396 #define MCDI_EVENT_LINKCHANGE_LP_CAP_LBN 0 397 #define MCDI_EVENT_LINKCHANGE_LP_CAP_WIDTH 16 398 #define MCDI_EVENT_LINKCHANGE_SPEED_LBN 16 399 #define MCDI_EVENT_LINKCHANGE_SPEED_WIDTH 4 400 /* enum: 100Mbs */ 401 #define MCDI_EVENT_LINKCHANGE_SPEED_100M 0x1 402 /* enum: 1Gbs */ 403 #define MCDI_EVENT_LINKCHANGE_SPEED_1G 0x2 404 /* enum: 10Gbs */ 405 #define MCDI_EVENT_LINKCHANGE_SPEED_10G 0x3 406 /* enum: 40Gbs */ 407 #define MCDI_EVENT_LINKCHANGE_SPEED_40G 0x4 408 #define MCDI_EVENT_LINKCHANGE_FCNTL_LBN 20 409 #define MCDI_EVENT_LINKCHANGE_FCNTL_WIDTH 4 410 #define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_LBN 24 411 #define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_WIDTH 8 412 #define MCDI_EVENT_SENSOREVT_MONITOR_LBN 0 413 #define MCDI_EVENT_SENSOREVT_MONITOR_WIDTH 8 414 #define MCDI_EVENT_SENSOREVT_STATE_LBN 8 415 #define MCDI_EVENT_SENSOREVT_STATE_WIDTH 8 416 #define MCDI_EVENT_SENSOREVT_VALUE_LBN 16 417 #define MCDI_EVENT_SENSOREVT_VALUE_WIDTH 16 418 #define MCDI_EVENT_FWALERT_DATA_LBN 8 419 #define MCDI_EVENT_FWALERT_DATA_WIDTH 24 420 #define MCDI_EVENT_FWALERT_REASON_LBN 0 421 #define MCDI_EVENT_FWALERT_REASON_WIDTH 8 422 /* enum: SRAM Access. */ 423 #define MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS 0x1 424 #define MCDI_EVENT_FLR_VF_LBN 0 425 #define MCDI_EVENT_FLR_VF_WIDTH 8 426 #define MCDI_EVENT_TX_ERR_TXQ_LBN 0 427 #define MCDI_EVENT_TX_ERR_TXQ_WIDTH 12 428 #define MCDI_EVENT_TX_ERR_TYPE_LBN 12 429 #define MCDI_EVENT_TX_ERR_TYPE_WIDTH 4 430 /* enum: Descriptor loader reported failure */ 431 #define MCDI_EVENT_TX_ERR_DL_FAIL 0x1 432 /* enum: Descriptor ring empty and no EOP seen for packet */ 433 #define MCDI_EVENT_TX_ERR_NO_EOP 0x2 434 /* enum: Overlength packet */ 435 #define MCDI_EVENT_TX_ERR_2BIG 0x3 436 /* enum: Malformed option descriptor */ 437 #define MCDI_EVENT_TX_BAD_OPTDESC 0x5 438 /* enum: Option descriptor part way through a packet */ 439 #define MCDI_EVENT_TX_OPT_IN_PKT 0x8 440 /* enum: DMA or PIO data access error */ 441 #define MCDI_EVENT_TX_ERR_BAD_DMA_OR_PIO 0x9 442 #define MCDI_EVENT_TX_ERR_INFO_LBN 16 443 #define MCDI_EVENT_TX_ERR_INFO_WIDTH 16 444 #define MCDI_EVENT_TX_FLUSH_TO_DRIVER_LBN 12 445 #define MCDI_EVENT_TX_FLUSH_TO_DRIVER_WIDTH 1 446 #define MCDI_EVENT_TX_FLUSH_TXQ_LBN 0 447 #define MCDI_EVENT_TX_FLUSH_TXQ_WIDTH 12 448 #define MCDI_EVENT_PTP_ERR_TYPE_LBN 0 449 #define MCDI_EVENT_PTP_ERR_TYPE_WIDTH 8 450 /* enum: PLL lost lock */ 451 #define MCDI_EVENT_PTP_ERR_PLL_LOST 0x1 452 /* enum: Filter overflow (PDMA) */ 453 #define MCDI_EVENT_PTP_ERR_FILTER 0x2 454 /* enum: FIFO overflow (FPGA) */ 455 #define MCDI_EVENT_PTP_ERR_FIFO 0x3 456 /* enum: Merge queue overflow */ 457 #define MCDI_EVENT_PTP_ERR_QUEUE 0x4 458 #define MCDI_EVENT_AOE_ERR_TYPE_LBN 0 459 #define MCDI_EVENT_AOE_ERR_TYPE_WIDTH 8 460 /* enum: AOE failed to load - no valid image? */ 461 #define MCDI_EVENT_AOE_NO_LOAD 0x1 462 /* enum: AOE FC reported an exception */ 463 #define MCDI_EVENT_AOE_FC_ASSERT 0x2 464 /* enum: AOE FC watchdogged */ 465 #define MCDI_EVENT_AOE_FC_WATCHDOG 0x3 466 /* enum: AOE FC failed to start */ 467 #define MCDI_EVENT_AOE_FC_NO_START 0x4 468 /* enum: Generic AOE fault - likely to have been reported via other means too 469 * but intended for use by aoex driver. 470 */ 471 #define MCDI_EVENT_AOE_FAULT 0x5 472 /* enum: Results of reprogramming the CPLD (status in AOE_ERR_DATA) */ 473 #define MCDI_EVENT_AOE_CPLD_REPROGRAMMED 0x6 474 /* enum: AOE loaded successfully */ 475 #define MCDI_EVENT_AOE_LOAD 0x7 476 /* enum: AOE DMA operation completed (LSB of HOST_HANDLE in AOE_ERR_DATA) */ 477 #define MCDI_EVENT_AOE_DMA 0x8 478 /* enum: AOE byteblaster connected/disconnected (Connection status in 479 * AOE_ERR_DATA) 480 */ 481 #define MCDI_EVENT_AOE_BYTEBLASTER 0x9 482 /* enum: DDR ECC status update */ 483 #define MCDI_EVENT_AOE_DDR_ECC_STATUS 0xa 484 /* enum: PTP status update */ 485 #define MCDI_EVENT_AOE_PTP_STATUS 0xb 486 #define MCDI_EVENT_AOE_ERR_DATA_LBN 8 487 #define MCDI_EVENT_AOE_ERR_DATA_WIDTH 8 488 #define MCDI_EVENT_RX_ERR_RXQ_LBN 0 489 #define MCDI_EVENT_RX_ERR_RXQ_WIDTH 12 490 #define MCDI_EVENT_RX_ERR_TYPE_LBN 12 491 #define MCDI_EVENT_RX_ERR_TYPE_WIDTH 4 492 #define MCDI_EVENT_RX_ERR_INFO_LBN 16 493 #define MCDI_EVENT_RX_ERR_INFO_WIDTH 16 494 #define MCDI_EVENT_RX_FLUSH_TO_DRIVER_LBN 12 495 #define MCDI_EVENT_RX_FLUSH_TO_DRIVER_WIDTH 1 496 #define MCDI_EVENT_RX_FLUSH_RXQ_LBN 0 497 #define MCDI_EVENT_RX_FLUSH_RXQ_WIDTH 12 498 #define MCDI_EVENT_MC_REBOOT_COUNT_LBN 0 499 #define MCDI_EVENT_MC_REBOOT_COUNT_WIDTH 16 500 #define MCDI_EVENT_MUM_ERR_TYPE_LBN 0 501 #define MCDI_EVENT_MUM_ERR_TYPE_WIDTH 8 502 /* enum: MUM failed to load - no valid image? */ 503 #define MCDI_EVENT_MUM_NO_LOAD 0x1 504 /* enum: MUM f/w reported an exception */ 505 #define MCDI_EVENT_MUM_ASSERT 0x2 506 /* enum: MUM not kicking watchdog */ 507 #define MCDI_EVENT_MUM_WATCHDOG 0x3 508 #define MCDI_EVENT_MUM_ERR_DATA_LBN 8 509 #define MCDI_EVENT_MUM_ERR_DATA_WIDTH 8 510 #define MCDI_EVENT_DATA_LBN 0 511 #define MCDI_EVENT_DATA_WIDTH 32 512 #define MCDI_EVENT_SRC_LBN 36 513 #define MCDI_EVENT_SRC_WIDTH 8 514 #define MCDI_EVENT_EV_CODE_LBN 60 515 #define MCDI_EVENT_EV_CODE_WIDTH 4 516 #define MCDI_EVENT_CODE_LBN 44 517 #define MCDI_EVENT_CODE_WIDTH 8 518 /* enum: Event generated by host software */ 519 #define MCDI_EVENT_SW_EVENT 0x0 520 /* enum: Bad assert. */ 521 #define MCDI_EVENT_CODE_BADSSERT 0x1 522 /* enum: PM Notice. */ 523 #define MCDI_EVENT_CODE_PMNOTICE 0x2 524 /* enum: Command done. */ 525 #define MCDI_EVENT_CODE_CMDDONE 0x3 526 /* enum: Link change. */ 527 #define MCDI_EVENT_CODE_LINKCHANGE 0x4 528 /* enum: Sensor Event. */ 529 #define MCDI_EVENT_CODE_SENSOREVT 0x5 530 /* enum: Schedule error. */ 531 #define MCDI_EVENT_CODE_SCHEDERR 0x6 532 /* enum: Reboot. */ 533 #define MCDI_EVENT_CODE_REBOOT 0x7 534 /* enum: Mac stats DMA. */ 535 #define MCDI_EVENT_CODE_MAC_STATS_DMA 0x8 536 /* enum: Firmware alert. */ 537 #define MCDI_EVENT_CODE_FWALERT 0x9 538 /* enum: Function level reset. */ 539 #define MCDI_EVENT_CODE_FLR 0xa 540 /* enum: Transmit error */ 541 #define MCDI_EVENT_CODE_TX_ERR 0xb 542 /* enum: Tx flush has completed */ 543 #define MCDI_EVENT_CODE_TX_FLUSH 0xc 544 /* enum: PTP packet received timestamp */ 545 #define MCDI_EVENT_CODE_PTP_RX 0xd 546 /* enum: PTP NIC failure */ 547 #define MCDI_EVENT_CODE_PTP_FAULT 0xe 548 /* enum: PTP PPS event */ 549 #define MCDI_EVENT_CODE_PTP_PPS 0xf 550 /* enum: Rx flush has completed */ 551 #define MCDI_EVENT_CODE_RX_FLUSH 0x10 552 /* enum: Receive error */ 553 #define MCDI_EVENT_CODE_RX_ERR 0x11 554 /* enum: AOE fault */ 555 #define MCDI_EVENT_CODE_AOE 0x12 556 /* enum: Network port calibration failed (VCAL). */ 557 #define MCDI_EVENT_CODE_VCAL_FAIL 0x13 558 /* enum: HW PPS event */ 559 #define MCDI_EVENT_CODE_HW_PPS 0x14 560 /* enum: The MC has rebooted (huntington and later, siena uses CODE_REBOOT and 561 * a different format) 562 */ 563 #define MCDI_EVENT_CODE_MC_REBOOT 0x15 564 /* enum: the MC has detected a parity error */ 565 #define MCDI_EVENT_CODE_PAR_ERR 0x16 566 /* enum: the MC has detected a correctable error */ 567 #define MCDI_EVENT_CODE_ECC_CORR_ERR 0x17 568 /* enum: the MC has detected an uncorrectable error */ 569 #define MCDI_EVENT_CODE_ECC_FATAL_ERR 0x18 570 /* enum: The MC has entered offline BIST mode */ 571 #define MCDI_EVENT_CODE_MC_BIST 0x19 572 /* enum: PTP tick event providing current NIC time */ 573 #define MCDI_EVENT_CODE_PTP_TIME 0x1a 574 /* enum: MUM fault */ 575 #define MCDI_EVENT_CODE_MUM 0x1b 576 /* enum: notify the designated PF of a new authorization request */ 577 #define MCDI_EVENT_CODE_PROXY_REQUEST 0x1c 578 /* enum: notify a function that awaits an authorization that its request has 579 * been processed and it may now resend the command 580 */ 581 #define MCDI_EVENT_CODE_PROXY_RESPONSE 0x1d 582 /* enum: Artificial event generated by host and posted via MC for test 583 * purposes. 584 */ 585 #define MCDI_EVENT_CODE_TESTGEN 0xfa 586 #define MCDI_EVENT_CMDDONE_DATA_OFST 0 587 #define MCDI_EVENT_CMDDONE_DATA_LBN 0 588 #define MCDI_EVENT_CMDDONE_DATA_WIDTH 32 589 #define MCDI_EVENT_LINKCHANGE_DATA_OFST 0 590 #define MCDI_EVENT_LINKCHANGE_DATA_LBN 0 591 #define MCDI_EVENT_LINKCHANGE_DATA_WIDTH 32 592 #define MCDI_EVENT_SENSOREVT_DATA_OFST 0 593 #define MCDI_EVENT_SENSOREVT_DATA_LBN 0 594 #define MCDI_EVENT_SENSOREVT_DATA_WIDTH 32 595 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_OFST 0 596 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_LBN 0 597 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_WIDTH 32 598 #define MCDI_EVENT_TX_ERR_DATA_OFST 0 599 #define MCDI_EVENT_TX_ERR_DATA_LBN 0 600 #define MCDI_EVENT_TX_ERR_DATA_WIDTH 32 601 /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the seconds field of 602 * timestamp 603 */ 604 #define MCDI_EVENT_PTP_SECONDS_OFST 0 605 #define MCDI_EVENT_PTP_SECONDS_LBN 0 606 #define MCDI_EVENT_PTP_SECONDS_WIDTH 32 607 /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the major field of 608 * timestamp 609 */ 610 #define MCDI_EVENT_PTP_MAJOR_OFST 0 611 #define MCDI_EVENT_PTP_MAJOR_LBN 0 612 #define MCDI_EVENT_PTP_MAJOR_WIDTH 32 613 /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the nanoseconds field 614 * of timestamp 615 */ 616 #define MCDI_EVENT_PTP_NANOSECONDS_OFST 0 617 #define MCDI_EVENT_PTP_NANOSECONDS_LBN 0 618 #define MCDI_EVENT_PTP_NANOSECONDS_WIDTH 32 619 /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the minor field of 620 * timestamp 621 */ 622 #define MCDI_EVENT_PTP_MINOR_OFST 0 623 #define MCDI_EVENT_PTP_MINOR_LBN 0 624 #define MCDI_EVENT_PTP_MINOR_WIDTH 32 625 /* For CODE_PTP_RX events, the lowest four bytes of sourceUUID from PTP packet 626 */ 627 #define MCDI_EVENT_PTP_UUID_OFST 0 628 #define MCDI_EVENT_PTP_UUID_LBN 0 629 #define MCDI_EVENT_PTP_UUID_WIDTH 32 630 #define MCDI_EVENT_RX_ERR_DATA_OFST 0 631 #define MCDI_EVENT_RX_ERR_DATA_LBN 0 632 #define MCDI_EVENT_RX_ERR_DATA_WIDTH 32 633 #define MCDI_EVENT_PAR_ERR_DATA_OFST 0 634 #define MCDI_EVENT_PAR_ERR_DATA_LBN 0 635 #define MCDI_EVENT_PAR_ERR_DATA_WIDTH 32 636 #define MCDI_EVENT_ECC_CORR_ERR_DATA_OFST 0 637 #define MCDI_EVENT_ECC_CORR_ERR_DATA_LBN 0 638 #define MCDI_EVENT_ECC_CORR_ERR_DATA_WIDTH 32 639 #define MCDI_EVENT_ECC_FATAL_ERR_DATA_OFST 0 640 #define MCDI_EVENT_ECC_FATAL_ERR_DATA_LBN 0 641 #define MCDI_EVENT_ECC_FATAL_ERR_DATA_WIDTH 32 642 /* For CODE_PTP_TIME events, the major value of the PTP clock */ 643 #define MCDI_EVENT_PTP_TIME_MAJOR_OFST 0 644 #define MCDI_EVENT_PTP_TIME_MAJOR_LBN 0 645 #define MCDI_EVENT_PTP_TIME_MAJOR_WIDTH 32 646 /* For CODE_PTP_TIME events, bits 19-26 of the minor value of the PTP clock */ 647 #define MCDI_EVENT_PTP_TIME_MINOR_26_19_LBN 36 648 #define MCDI_EVENT_PTP_TIME_MINOR_26_19_WIDTH 8 649 /* For CODE_PTP_TIME events where report sync status is enabled, indicates 650 * whether the NIC clock has ever been set 651 */ 652 #define MCDI_EVENT_PTP_TIME_NIC_CLOCK_VALID_LBN 36 653 #define MCDI_EVENT_PTP_TIME_NIC_CLOCK_VALID_WIDTH 1 654 /* For CODE_PTP_TIME events where report sync status is enabled, indicates 655 * whether the NIC and System clocks are in sync 656 */ 657 #define MCDI_EVENT_PTP_TIME_HOST_NIC_IN_SYNC_LBN 37 658 #define MCDI_EVENT_PTP_TIME_HOST_NIC_IN_SYNC_WIDTH 1 659 /* For CODE_PTP_TIME events where report sync status is enabled, bits 21-26 of 660 * the minor value of the PTP clock 661 */ 662 #define MCDI_EVENT_PTP_TIME_MINOR_26_21_LBN 38 663 #define MCDI_EVENT_PTP_TIME_MINOR_26_21_WIDTH 6 664 #define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_OFST 0 665 #define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_LBN 0 666 #define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_WIDTH 32 667 #define MCDI_EVENT_PROXY_RESPONSE_HANDLE_OFST 0 668 #define MCDI_EVENT_PROXY_RESPONSE_HANDLE_LBN 0 669 #define MCDI_EVENT_PROXY_RESPONSE_HANDLE_WIDTH 32 670 /* Zero means that the request has been completed or authorized, and the driver 671 * should resend it. A non-zero value means that the authorization has been 672 * denied, and gives the reason. Typically it will be EPERM. 673 */ 674 #define MCDI_EVENT_PROXY_RESPONSE_RC_LBN 36 675 #define MCDI_EVENT_PROXY_RESPONSE_RC_WIDTH 8 676 677 /* FCDI_EVENT structuredef */ 678 #define FCDI_EVENT_LEN 8 679 #define FCDI_EVENT_CONT_LBN 32 680 #define FCDI_EVENT_CONT_WIDTH 1 681 #define FCDI_EVENT_LEVEL_LBN 33 682 #define FCDI_EVENT_LEVEL_WIDTH 3 683 /* enum: Info. */ 684 #define FCDI_EVENT_LEVEL_INFO 0x0 685 /* enum: Warning. */ 686 #define FCDI_EVENT_LEVEL_WARN 0x1 687 /* enum: Error. */ 688 #define FCDI_EVENT_LEVEL_ERR 0x2 689 /* enum: Fatal. */ 690 #define FCDI_EVENT_LEVEL_FATAL 0x3 691 #define FCDI_EVENT_DATA_OFST 0 692 #define FCDI_EVENT_LINK_STATE_STATUS_LBN 0 693 #define FCDI_EVENT_LINK_STATE_STATUS_WIDTH 1 694 #define FCDI_EVENT_LINK_DOWN 0x0 /* enum */ 695 #define FCDI_EVENT_LINK_UP 0x1 /* enum */ 696 #define FCDI_EVENT_DATA_LBN 0 697 #define FCDI_EVENT_DATA_WIDTH 32 698 #define FCDI_EVENT_SRC_LBN 36 699 #define FCDI_EVENT_SRC_WIDTH 8 700 #define FCDI_EVENT_EV_CODE_LBN 60 701 #define FCDI_EVENT_EV_CODE_WIDTH 4 702 #define FCDI_EVENT_CODE_LBN 44 703 #define FCDI_EVENT_CODE_WIDTH 8 704 /* enum: The FC was rebooted. */ 705 #define FCDI_EVENT_CODE_REBOOT 0x1 706 /* enum: Bad assert. */ 707 #define FCDI_EVENT_CODE_ASSERT 0x2 708 /* enum: DDR3 test result. */ 709 #define FCDI_EVENT_CODE_DDR_TEST_RESULT 0x3 710 /* enum: Link status. */ 711 #define FCDI_EVENT_CODE_LINK_STATE 0x4 712 /* enum: A timed read is ready to be serviced. */ 713 #define FCDI_EVENT_CODE_TIMED_READ 0x5 714 /* enum: One or more PPS IN events */ 715 #define FCDI_EVENT_CODE_PPS_IN 0x6 716 /* enum: Tick event from PTP clock */ 717 #define FCDI_EVENT_CODE_PTP_TICK 0x7 718 /* enum: ECC error counters */ 719 #define FCDI_EVENT_CODE_DDR_ECC_STATUS 0x8 720 /* enum: Current status of PTP */ 721 #define FCDI_EVENT_CODE_PTP_STATUS 0x9 722 /* enum: Port id config to map MC-FC port idx */ 723 #define FCDI_EVENT_CODE_PORT_CONFIG 0xa 724 /* enum: Boot result or error code */ 725 #define FCDI_EVENT_CODE_BOOT_RESULT 0xb 726 #define FCDI_EVENT_REBOOT_SRC_LBN 36 727 #define FCDI_EVENT_REBOOT_SRC_WIDTH 8 728 #define FCDI_EVENT_REBOOT_FC_FW 0x0 /* enum */ 729 #define FCDI_EVENT_REBOOT_FC_BOOTLOADER 0x1 /* enum */ 730 #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_OFST 0 731 #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_LBN 0 732 #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_WIDTH 32 733 #define FCDI_EVENT_ASSERT_TYPE_LBN 36 734 #define FCDI_EVENT_ASSERT_TYPE_WIDTH 8 735 #define FCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_LBN 36 736 #define FCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_WIDTH 8 737 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_OFST 0 738 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_LBN 0 739 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_WIDTH 32 740 #define FCDI_EVENT_LINK_STATE_DATA_OFST 0 741 #define FCDI_EVENT_LINK_STATE_DATA_LBN 0 742 #define FCDI_EVENT_LINK_STATE_DATA_WIDTH 32 743 #define FCDI_EVENT_PTP_STATE_OFST 0 744 #define FCDI_EVENT_PTP_UNDEFINED 0x0 /* enum */ 745 #define FCDI_EVENT_PTP_SETUP_FAILED 0x1 /* enum */ 746 #define FCDI_EVENT_PTP_OPERATIONAL 0x2 /* enum */ 747 #define FCDI_EVENT_PTP_STATE_LBN 0 748 #define FCDI_EVENT_PTP_STATE_WIDTH 32 749 #define FCDI_EVENT_DDR_ECC_STATUS_BANK_ID_LBN 36 750 #define FCDI_EVENT_DDR_ECC_STATUS_BANK_ID_WIDTH 8 751 #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_OFST 0 752 #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_LBN 0 753 #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_WIDTH 32 754 /* Index of MC port being referred to */ 755 #define FCDI_EVENT_PORT_CONFIG_SRC_LBN 36 756 #define FCDI_EVENT_PORT_CONFIG_SRC_WIDTH 8 757 /* FC Port index that matches the MC port index in SRC */ 758 #define FCDI_EVENT_PORT_CONFIG_DATA_OFST 0 759 #define FCDI_EVENT_PORT_CONFIG_DATA_LBN 0 760 #define FCDI_EVENT_PORT_CONFIG_DATA_WIDTH 32 761 #define FCDI_EVENT_BOOT_RESULT_OFST 0 762 /* Enum values, see field(s): */ 763 /* MC_CMD_AOE/MC_CMD_AOE_OUT_INFO/FC_BOOT_RESULT */ 764 #define FCDI_EVENT_BOOT_RESULT_LBN 0 765 #define FCDI_EVENT_BOOT_RESULT_WIDTH 32 766 767 /* FCDI_EXTENDED_EVENT_PPS structuredef: Extended FCDI event to send PPS events 768 * to the MC. Note that this structure | is overlaid over a normal FCDI event 769 * such that bits 32-63 containing | event code, level, source etc remain the 770 * same. In this case the data | field of the header is defined to be the 771 * number of timestamps 772 */ 773 #define FCDI_EXTENDED_EVENT_PPS_LENMIN 16 774 #define FCDI_EXTENDED_EVENT_PPS_LENMAX 248 775 #define FCDI_EXTENDED_EVENT_PPS_LEN(num) (8+8*(num)) 776 /* Number of timestamps following */ 777 #define FCDI_EXTENDED_EVENT_PPS_COUNT_OFST 0 778 #define FCDI_EXTENDED_EVENT_PPS_COUNT_LBN 0 779 #define FCDI_EXTENDED_EVENT_PPS_COUNT_WIDTH 32 780 /* Seconds field of a timestamp record */ 781 #define FCDI_EXTENDED_EVENT_PPS_SECONDS_OFST 8 782 #define FCDI_EXTENDED_EVENT_PPS_SECONDS_LBN 64 783 #define FCDI_EXTENDED_EVENT_PPS_SECONDS_WIDTH 32 784 /* Nanoseconds field of a timestamp record */ 785 #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_OFST 12 786 #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_LBN 96 787 #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_WIDTH 32 788 /* Timestamp records comprising the event */ 789 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_OFST 8 790 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LEN 8 791 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LO_OFST 8 792 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_HI_OFST 12 793 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MINNUM 1 794 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MAXNUM 30 795 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LBN 64 796 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_WIDTH 64 797 798 /* MUM_EVENT structuredef */ 799 #define MUM_EVENT_LEN 8 800 #define MUM_EVENT_CONT_LBN 32 801 #define MUM_EVENT_CONT_WIDTH 1 802 #define MUM_EVENT_LEVEL_LBN 33 803 #define MUM_EVENT_LEVEL_WIDTH 3 804 /* enum: Info. */ 805 #define MUM_EVENT_LEVEL_INFO 0x0 806 /* enum: Warning. */ 807 #define MUM_EVENT_LEVEL_WARN 0x1 808 /* enum: Error. */ 809 #define MUM_EVENT_LEVEL_ERR 0x2 810 /* enum: Fatal. */ 811 #define MUM_EVENT_LEVEL_FATAL 0x3 812 #define MUM_EVENT_DATA_OFST 0 813 #define MUM_EVENT_SENSOR_ID_LBN 0 814 #define MUM_EVENT_SENSOR_ID_WIDTH 8 815 /* Enum values, see field(s): */ 816 /* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */ 817 #define MUM_EVENT_SENSOR_STATE_LBN 8 818 #define MUM_EVENT_SENSOR_STATE_WIDTH 8 819 #define MUM_EVENT_PORT_PHY_READY_LBN 0 820 #define MUM_EVENT_PORT_PHY_READY_WIDTH 1 821 #define MUM_EVENT_PORT_PHY_LINK_UP_LBN 1 822 #define MUM_EVENT_PORT_PHY_LINK_UP_WIDTH 1 823 #define MUM_EVENT_PORT_PHY_TX_LOL_LBN 2 824 #define MUM_EVENT_PORT_PHY_TX_LOL_WIDTH 1 825 #define MUM_EVENT_PORT_PHY_RX_LOL_LBN 3 826 #define MUM_EVENT_PORT_PHY_RX_LOL_WIDTH 1 827 #define MUM_EVENT_PORT_PHY_TX_LOS_LBN 4 828 #define MUM_EVENT_PORT_PHY_TX_LOS_WIDTH 1 829 #define MUM_EVENT_PORT_PHY_RX_LOS_LBN 5 830 #define MUM_EVENT_PORT_PHY_RX_LOS_WIDTH 1 831 #define MUM_EVENT_PORT_PHY_TX_FAULT_LBN 6 832 #define MUM_EVENT_PORT_PHY_TX_FAULT_WIDTH 1 833 #define MUM_EVENT_DATA_LBN 0 834 #define MUM_EVENT_DATA_WIDTH 32 835 #define MUM_EVENT_SRC_LBN 36 836 #define MUM_EVENT_SRC_WIDTH 8 837 #define MUM_EVENT_EV_CODE_LBN 60 838 #define MUM_EVENT_EV_CODE_WIDTH 4 839 #define MUM_EVENT_CODE_LBN 44 840 #define MUM_EVENT_CODE_WIDTH 8 841 /* enum: The MUM was rebooted. */ 842 #define MUM_EVENT_CODE_REBOOT 0x1 843 /* enum: Bad assert. */ 844 #define MUM_EVENT_CODE_ASSERT 0x2 845 /* enum: Sensor failure. */ 846 #define MUM_EVENT_CODE_SENSOR 0x3 847 /* enum: Link fault has been asserted, or has cleared. */ 848 #define MUM_EVENT_CODE_QSFP_LASI_INTERRUPT 0x4 849 #define MUM_EVENT_SENSOR_DATA_OFST 0 850 #define MUM_EVENT_SENSOR_DATA_LBN 0 851 #define MUM_EVENT_SENSOR_DATA_WIDTH 32 852 #define MUM_EVENT_PORT_PHY_FLAGS_OFST 0 853 #define MUM_EVENT_PORT_PHY_FLAGS_LBN 0 854 #define MUM_EVENT_PORT_PHY_FLAGS_WIDTH 32 855 #define MUM_EVENT_PORT_PHY_COPPER_LEN_OFST 0 856 #define MUM_EVENT_PORT_PHY_COPPER_LEN_LBN 0 857 #define MUM_EVENT_PORT_PHY_COPPER_LEN_WIDTH 32 858 #define MUM_EVENT_PORT_PHY_CAPS_OFST 0 859 #define MUM_EVENT_PORT_PHY_CAPS_LBN 0 860 #define MUM_EVENT_PORT_PHY_CAPS_WIDTH 32 861 #define MUM_EVENT_PORT_PHY_TECH_OFST 0 862 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_UNKNOWN 0x0 /* enum */ 863 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_OPTICAL 0x1 /* enum */ 864 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_PASSIVE 0x2 /* enum */ 865 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_PASSIVE_EQUALIZED 0x3 /* enum */ 866 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_ACTIVE_LIMITING 0x4 /* enum */ 867 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_ACTIVE_LINEAR 0x5 /* enum */ 868 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_BASE_T 0x6 /* enum */ 869 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_LOOPBACK_PASSIVE 0x7 /* enum */ 870 #define MUM_EVENT_PORT_PHY_TECH_LBN 0 871 #define MUM_EVENT_PORT_PHY_TECH_WIDTH 32 872 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_LBN 36 873 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_WIDTH 4 874 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_FLAGS 0x0 /* enum */ 875 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_COPPER_LEN 0x1 /* enum */ 876 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_CAPS 0x2 /* enum */ 877 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_TECH 0x3 /* enum */ 878 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_MAX 0x4 /* enum */ 879 #define MUM_EVENT_PORT_PHY_SRC_PORT_NO_LBN 40 880 #define MUM_EVENT_PORT_PHY_SRC_PORT_NO_WIDTH 4 881 882 883 /***********************************/ 884 /* MC_CMD_READ32 885 * Read multiple 32byte words from MC memory. 886 */ 887 #define MC_CMD_READ32 0x1 888 #undef MC_CMD_0x1_PRIVILEGE_CTG 889 890 #define MC_CMD_0x1_PRIVILEGE_CTG SRIOV_CTG_ADMIN 891 892 /* MC_CMD_READ32_IN msgrequest */ 893 #define MC_CMD_READ32_IN_LEN 8 894 #define MC_CMD_READ32_IN_ADDR_OFST 0 895 #define MC_CMD_READ32_IN_NUMWORDS_OFST 4 896 897 /* MC_CMD_READ32_OUT msgresponse */ 898 #define MC_CMD_READ32_OUT_LENMIN 4 899 #define MC_CMD_READ32_OUT_LENMAX 252 900 #define MC_CMD_READ32_OUT_LEN(num) (0+4*(num)) 901 #define MC_CMD_READ32_OUT_BUFFER_OFST 0 902 #define MC_CMD_READ32_OUT_BUFFER_LEN 4 903 #define MC_CMD_READ32_OUT_BUFFER_MINNUM 1 904 #define MC_CMD_READ32_OUT_BUFFER_MAXNUM 63 905 906 907 /***********************************/ 908 /* MC_CMD_WRITE32 909 * Write multiple 32byte words to MC memory. 910 */ 911 #define MC_CMD_WRITE32 0x2 912 #undef MC_CMD_0x2_PRIVILEGE_CTG 913 914 #define MC_CMD_0x2_PRIVILEGE_CTG SRIOV_CTG_ADMIN 915 916 /* MC_CMD_WRITE32_IN msgrequest */ 917 #define MC_CMD_WRITE32_IN_LENMIN 8 918 #define MC_CMD_WRITE32_IN_LENMAX 252 919 #define MC_CMD_WRITE32_IN_LEN(num) (4+4*(num)) 920 #define MC_CMD_WRITE32_IN_ADDR_OFST 0 921 #define MC_CMD_WRITE32_IN_BUFFER_OFST 4 922 #define MC_CMD_WRITE32_IN_BUFFER_LEN 4 923 #define MC_CMD_WRITE32_IN_BUFFER_MINNUM 1 924 #define MC_CMD_WRITE32_IN_BUFFER_MAXNUM 62 925 926 /* MC_CMD_WRITE32_OUT msgresponse */ 927 #define MC_CMD_WRITE32_OUT_LEN 0 928 929 930 /***********************************/ 931 /* MC_CMD_COPYCODE 932 * Copy MC code between two locations and jump. 933 */ 934 #define MC_CMD_COPYCODE 0x3 935 #undef MC_CMD_0x3_PRIVILEGE_CTG 936 937 #define MC_CMD_0x3_PRIVILEGE_CTG SRIOV_CTG_ADMIN 938 939 /* MC_CMD_COPYCODE_IN msgrequest */ 940 #define MC_CMD_COPYCODE_IN_LEN 16 941 /* Source address 942 * 943 * The main image should be entered via a copy of a single word from and to a 944 * magic address, which controls various aspects of the boot. The magic address 945 * is a bitfield, with each bit as documented below. 946 */ 947 #define MC_CMD_COPYCODE_IN_SRC_ADDR_OFST 0 948 /* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT (see below) */ 949 #define MC_CMD_COPYCODE_HUNT_NO_MAGIC_ADDR 0x10000 950 /* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT and 951 * BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED (see below) 952 */ 953 #define MC_CMD_COPYCODE_HUNT_NO_DATAPATH_MAGIC_ADDR 0x1d0d0 954 /* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT, 955 * BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED and BOOT_MAGIC_IGNORE_CONFIG (see 956 * below) 957 */ 958 #define MC_CMD_COPYCODE_HUNT_IGNORE_CONFIG_MAGIC_ADDR 0x1badc 959 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_LBN 17 960 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_WIDTH 1 961 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_LBN 2 962 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_WIDTH 1 963 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_LBN 3 964 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_WIDTH 1 965 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_LBN 4 966 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_WIDTH 1 967 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_LBN 5 968 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_WIDTH 1 969 /* Destination address */ 970 #define MC_CMD_COPYCODE_IN_DEST_ADDR_OFST 4 971 #define MC_CMD_COPYCODE_IN_NUMWORDS_OFST 8 972 /* Address of where to jump after copy. */ 973 #define MC_CMD_COPYCODE_IN_JUMP_OFST 12 974 /* enum: Control should return to the caller rather than jumping */ 975 #define MC_CMD_COPYCODE_JUMP_NONE 0x1 976 977 /* MC_CMD_COPYCODE_OUT msgresponse */ 978 #define MC_CMD_COPYCODE_OUT_LEN 0 979 980 981 /***********************************/ 982 /* MC_CMD_SET_FUNC 983 * Select function for function-specific commands. 984 */ 985 #define MC_CMD_SET_FUNC 0x4 986 #undef MC_CMD_0x4_PRIVILEGE_CTG 987 988 #define MC_CMD_0x4_PRIVILEGE_CTG SRIOV_CTG_ADMIN 989 990 /* MC_CMD_SET_FUNC_IN msgrequest */ 991 #define MC_CMD_SET_FUNC_IN_LEN 4 992 /* Set function */ 993 #define MC_CMD_SET_FUNC_IN_FUNC_OFST 0 994 995 /* MC_CMD_SET_FUNC_OUT msgresponse */ 996 #define MC_CMD_SET_FUNC_OUT_LEN 0 997 998 999 /***********************************/ 1000 /* MC_CMD_GET_BOOT_STATUS 1001 * Get the instruction address from which the MC booted. 1002 */ 1003 #define MC_CMD_GET_BOOT_STATUS 0x5 1004 #undef MC_CMD_0x5_PRIVILEGE_CTG 1005 1006 #define MC_CMD_0x5_PRIVILEGE_CTG SRIOV_CTG_ADMIN 1007 1008 /* MC_CMD_GET_BOOT_STATUS_IN msgrequest */ 1009 #define MC_CMD_GET_BOOT_STATUS_IN_LEN 0 1010 1011 /* MC_CMD_GET_BOOT_STATUS_OUT msgresponse */ 1012 #define MC_CMD_GET_BOOT_STATUS_OUT_LEN 8 1013 /* ?? */ 1014 #define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_OFST 0 1015 /* enum: indicates that the MC wasn't flash booted */ 1016 #define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_NULL 0xdeadbeef 1017 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_OFST 4 1018 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_LBN 0 1019 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_WIDTH 1 1020 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_LBN 1 1021 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_WIDTH 1 1022 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_LBN 2 1023 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_WIDTH 1 1024 1025 1026 /***********************************/ 1027 /* MC_CMD_GET_ASSERTS 1028 * Get (and optionally clear) the current assertion status. Only 1029 * OUT.GLOBAL_FLAGS is guaranteed to exist in the completion payload. The other 1030 * fields will only be present if OUT.GLOBAL_FLAGS != NO_FAILS 1031 */ 1032 #define MC_CMD_GET_ASSERTS 0x6 1033 #undef MC_CMD_0x6_PRIVILEGE_CTG 1034 1035 #define MC_CMD_0x6_PRIVILEGE_CTG SRIOV_CTG_ADMIN 1036 1037 /* MC_CMD_GET_ASSERTS_IN msgrequest */ 1038 #define MC_CMD_GET_ASSERTS_IN_LEN 4 1039 /* Set to clear assertion */ 1040 #define MC_CMD_GET_ASSERTS_IN_CLEAR_OFST 0 1041 1042 /* MC_CMD_GET_ASSERTS_OUT msgresponse */ 1043 #define MC_CMD_GET_ASSERTS_OUT_LEN 140 1044 /* Assertion status flag. */ 1045 #define MC_CMD_GET_ASSERTS_OUT_GLOBAL_FLAGS_OFST 0 1046 /* enum: No assertions have failed. */ 1047 #define MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1 1048 /* enum: A system-level assertion has failed. */ 1049 #define MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2 1050 /* enum: A thread-level assertion has failed. */ 1051 #define MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3 1052 /* enum: The system was reset by the watchdog. */ 1053 #define MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4 1054 /* enum: An illegal address trap stopped the system (huntington and later) */ 1055 #define MC_CMD_GET_ASSERTS_FLAGS_ADDR_TRAP 0x5 1056 /* Failing PC value */ 1057 #define MC_CMD_GET_ASSERTS_OUT_SAVED_PC_OFFS_OFST 4 1058 /* Saved GP regs */ 1059 #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_OFST 8 1060 #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_LEN 4 1061 #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_NUM 31 1062 /* enum: A magic value hinting that the value in this register at the time of 1063 * the failure has likely been lost. 1064 */ 1065 #define MC_CMD_GET_ASSERTS_REG_NO_DATA 0xda7a1057 1066 /* Failing thread address */ 1067 #define MC_CMD_GET_ASSERTS_OUT_THREAD_OFFS_OFST 132 1068 #define MC_CMD_GET_ASSERTS_OUT_RESERVED_OFST 136 1069 1070 1071 /***********************************/ 1072 /* MC_CMD_LOG_CTRL 1073 * Configure the output stream for log events such as link state changes, 1074 * sensor notifications and MCDI completions 1075 */ 1076 #define MC_CMD_LOG_CTRL 0x7 1077 #undef MC_CMD_0x7_PRIVILEGE_CTG 1078 1079 #define MC_CMD_0x7_PRIVILEGE_CTG SRIOV_CTG_GENERAL 1080 1081 /* MC_CMD_LOG_CTRL_IN msgrequest */ 1082 #define MC_CMD_LOG_CTRL_IN_LEN 8 1083 /* Log destination */ 1084 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_OFST 0 1085 /* enum: UART. */ 1086 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_UART 0x1 1087 /* enum: Event queue. */ 1088 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ 0x2 1089 /* Legacy argument. Must be zero. */ 1090 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ_OFST 4 1091 1092 /* MC_CMD_LOG_CTRL_OUT msgresponse */ 1093 #define MC_CMD_LOG_CTRL_OUT_LEN 0 1094 1095 1096 /***********************************/ 1097 /* MC_CMD_GET_VERSION 1098 * Get version information about the MC firmware. 1099 */ 1100 #define MC_CMD_GET_VERSION 0x8 1101 #undef MC_CMD_0x8_PRIVILEGE_CTG 1102 1103 #define MC_CMD_0x8_PRIVILEGE_CTG SRIOV_CTG_GENERAL 1104 1105 /* MC_CMD_GET_VERSION_IN msgrequest */ 1106 #define MC_CMD_GET_VERSION_IN_LEN 0 1107 1108 /* MC_CMD_GET_VERSION_EXT_IN msgrequest: Asks for the extended version */ 1109 #define MC_CMD_GET_VERSION_EXT_IN_LEN 4 1110 /* placeholder, set to 0 */ 1111 #define MC_CMD_GET_VERSION_EXT_IN_EXT_FLAGS_OFST 0 1112 1113 /* MC_CMD_GET_VERSION_V0_OUT msgresponse: deprecated version format */ 1114 #define MC_CMD_GET_VERSION_V0_OUT_LEN 4 1115 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 1116 /* enum: Reserved version number to indicate "any" version. */ 1117 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_ANY 0xffffffff 1118 /* enum: Bootrom version value for Siena. */ 1119 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_SIENA_BOOTROM 0xb0070000 1120 /* enum: Bootrom version value for Huntington. */ 1121 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_HUNT_BOOTROM 0xb0070001 1122 1123 /* MC_CMD_GET_VERSION_OUT msgresponse */ 1124 #define MC_CMD_GET_VERSION_OUT_LEN 32 1125 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */ 1126 /* Enum values, see field(s): */ 1127 /* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */ 1128 #define MC_CMD_GET_VERSION_OUT_PCOL_OFST 4 1129 /* 128bit mask of functions supported by the current firmware */ 1130 #define MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_OFST 8 1131 #define MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_LEN 16 1132 #define MC_CMD_GET_VERSION_OUT_VERSION_OFST 24 1133 #define MC_CMD_GET_VERSION_OUT_VERSION_LEN 8 1134 #define MC_CMD_GET_VERSION_OUT_VERSION_LO_OFST 24 1135 #define MC_CMD_GET_VERSION_OUT_VERSION_HI_OFST 28 1136 1137 /* MC_CMD_GET_VERSION_EXT_OUT msgresponse */ 1138 #define MC_CMD_GET_VERSION_EXT_OUT_LEN 48 1139 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */ 1140 /* Enum values, see field(s): */ 1141 /* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */ 1142 #define MC_CMD_GET_VERSION_EXT_OUT_PCOL_OFST 4 1143 /* 128bit mask of functions supported by the current firmware */ 1144 #define MC_CMD_GET_VERSION_EXT_OUT_SUPPORTED_FUNCS_OFST 8 1145 #define MC_CMD_GET_VERSION_EXT_OUT_SUPPORTED_FUNCS_LEN 16 1146 #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_OFST 24 1147 #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LEN 8 1148 #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LO_OFST 24 1149 #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_HI_OFST 28 1150 /* extra info */ 1151 #define MC_CMD_GET_VERSION_EXT_OUT_EXTRA_OFST 32 1152 #define MC_CMD_GET_VERSION_EXT_OUT_EXTRA_LEN 16 1153 1154 1155 /***********************************/ 1156 /* MC_CMD_FC 1157 * Perform an FC operation 1158 */ 1159 #define MC_CMD_FC 0x9 1160 1161 /* MC_CMD_FC_IN msgrequest */ 1162 #define MC_CMD_FC_IN_LEN 4 1163 #define MC_CMD_FC_IN_OP_HDR_OFST 0 1164 #define MC_CMD_FC_IN_OP_LBN 0 1165 #define MC_CMD_FC_IN_OP_WIDTH 8 1166 /* enum: NULL MCDI command to FC. */ 1167 #define MC_CMD_FC_OP_NULL 0x1 1168 /* enum: Unused opcode */ 1169 #define MC_CMD_FC_OP_UNUSED 0x2 1170 /* enum: MAC driver commands */ 1171 #define MC_CMD_FC_OP_MAC 0x3 1172 /* enum: Read FC memory */ 1173 #define MC_CMD_FC_OP_READ32 0x4 1174 /* enum: Write to FC memory */ 1175 #define MC_CMD_FC_OP_WRITE32 0x5 1176 /* enum: Read FC memory */ 1177 #define MC_CMD_FC_OP_TRC_READ 0x6 1178 /* enum: Write to FC memory */ 1179 #define MC_CMD_FC_OP_TRC_WRITE 0x7 1180 /* enum: FC firmware Version */ 1181 #define MC_CMD_FC_OP_GET_VERSION 0x8 1182 /* enum: Read FC memory */ 1183 #define MC_CMD_FC_OP_TRC_RX_READ 0x9 1184 /* enum: Write to FC memory */ 1185 #define MC_CMD_FC_OP_TRC_RX_WRITE 0xa 1186 /* enum: SFP parameters */ 1187 #define MC_CMD_FC_OP_SFP 0xb 1188 /* enum: DDR3 test */ 1189 #define MC_CMD_FC_OP_DDR_TEST 0xc 1190 /* enum: Get Crash context from FC */ 1191 #define MC_CMD_FC_OP_GET_ASSERT 0xd 1192 /* enum: Get FPGA Build registers */ 1193 #define MC_CMD_FC_OP_FPGA_BUILD 0xe 1194 /* enum: Read map support commands */ 1195 #define MC_CMD_FC_OP_READ_MAP 0xf 1196 /* enum: FC Capabilities */ 1197 #define MC_CMD_FC_OP_CAPABILITIES 0x10 1198 /* enum: FC Global flags */ 1199 #define MC_CMD_FC_OP_GLOBAL_FLAGS 0x11 1200 /* enum: FC IO using relative addressing modes */ 1201 #define MC_CMD_FC_OP_IO_REL 0x12 1202 /* enum: FPGA link information */ 1203 #define MC_CMD_FC_OP_UHLINK 0x13 1204 /* enum: Configure loopbacks and link on FPGA ports */ 1205 #define MC_CMD_FC_OP_SET_LINK 0x14 1206 /* enum: Licensing operations relating to AOE */ 1207 #define MC_CMD_FC_OP_LICENSE 0x15 1208 /* enum: Startup information to the FC */ 1209 #define MC_CMD_FC_OP_STARTUP 0x16 1210 /* enum: Configure a DMA read */ 1211 #define MC_CMD_FC_OP_DMA 0x17 1212 /* enum: Configure a timed read */ 1213 #define MC_CMD_FC_OP_TIMED_READ 0x18 1214 /* enum: Control UART logging */ 1215 #define MC_CMD_FC_OP_LOG 0x19 1216 /* enum: Get the value of a given clock_id */ 1217 #define MC_CMD_FC_OP_CLOCK 0x1a 1218 /* enum: DDR3/QDR3 parameters */ 1219 #define MC_CMD_FC_OP_DDR 0x1b 1220 /* enum: PTP and timestamp control */ 1221 #define MC_CMD_FC_OP_TIMESTAMP 0x1c 1222 /* enum: Commands for SPI Flash interface */ 1223 #define MC_CMD_FC_OP_SPI 0x1d 1224 /* enum: Commands for diagnostic components */ 1225 #define MC_CMD_FC_OP_DIAG 0x1e 1226 /* enum: External AOE port. */ 1227 #define MC_CMD_FC_IN_PORT_EXT_OFST 0x0 1228 /* enum: Internal AOE port. */ 1229 #define MC_CMD_FC_IN_PORT_INT_OFST 0x40 1230 1231 /* MC_CMD_FC_IN_NULL msgrequest */ 1232 #define MC_CMD_FC_IN_NULL_LEN 4 1233 #define MC_CMD_FC_IN_CMD_OFST 0 1234 1235 /* MC_CMD_FC_IN_PHY msgrequest */ 1236 #define MC_CMD_FC_IN_PHY_LEN 5 1237 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1238 /* FC PHY driver operation code */ 1239 #define MC_CMD_FC_IN_PHY_OP_OFST 4 1240 #define MC_CMD_FC_IN_PHY_OP_LEN 1 1241 /* enum: PHY init handler */ 1242 #define MC_CMD_FC_OP_PHY_OP_INIT 0x1 1243 /* enum: PHY reconfigure handler */ 1244 #define MC_CMD_FC_OP_PHY_OP_RECONFIGURE 0x2 1245 /* enum: PHY reboot handler */ 1246 #define MC_CMD_FC_OP_PHY_OP_REBOOT 0x3 1247 /* enum: PHY get_supported_cap handler */ 1248 #define MC_CMD_FC_OP_PHY_OP_GET_SUPPORTED_CAP 0x4 1249 /* enum: PHY get_config handler */ 1250 #define MC_CMD_FC_OP_PHY_OP_GET_CONFIG 0x5 1251 /* enum: PHY get_media_info handler */ 1252 #define MC_CMD_FC_OP_PHY_OP_GET_MEDIA_INFO 0x6 1253 /* enum: PHY set_led handler */ 1254 #define MC_CMD_FC_OP_PHY_OP_SET_LED 0x7 1255 /* enum: PHY lasi_interrupt handler */ 1256 #define MC_CMD_FC_OP_PHY_OP_LASI_INTERRUPT 0x8 1257 /* enum: PHY check_link handler */ 1258 #define MC_CMD_FC_OP_PHY_OP_CHECK_LINK 0x9 1259 /* enum: PHY fill_stats handler */ 1260 #define MC_CMD_FC_OP_PHY_OP_FILL_STATS 0xa 1261 /* enum: PHY bpx_link_state_changed handler */ 1262 #define MC_CMD_FC_OP_PHY_OP_BPX_LINK_STATE_CHANGED 0xb 1263 /* enum: PHY get_state handler */ 1264 #define MC_CMD_FC_OP_PHY_OP_GET_STATE 0xc 1265 /* enum: PHY start_bist handler */ 1266 #define MC_CMD_FC_OP_PHY_OP_START_BIST 0xd 1267 /* enum: PHY poll_bist handler */ 1268 #define MC_CMD_FC_OP_PHY_OP_POLL_BIST 0xe 1269 /* enum: PHY nvram_test handler */ 1270 #define MC_CMD_FC_OP_PHY_OP_NVRAM_TEST 0xf 1271 /* enum: PHY relinquish handler */ 1272 #define MC_CMD_FC_OP_PHY_OP_RELINQUISH_SPI 0x10 1273 /* enum: PHY read connection from FC - may be not required */ 1274 #define MC_CMD_FC_OP_PHY_OP_GET_CONNECTION 0x11 1275 /* enum: PHY read flags from FC - may be not required */ 1276 #define MC_CMD_FC_OP_PHY_OP_GET_FLAGS 0x12 1277 1278 /* MC_CMD_FC_IN_PHY_INIT msgrequest */ 1279 #define MC_CMD_FC_IN_PHY_INIT_LEN 4 1280 #define MC_CMD_FC_IN_PHY_CMD_OFST 0 1281 1282 /* MC_CMD_FC_IN_MAC msgrequest */ 1283 #define MC_CMD_FC_IN_MAC_LEN 8 1284 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1285 #define MC_CMD_FC_IN_MAC_HEADER_OFST 4 1286 #define MC_CMD_FC_IN_MAC_OP_LBN 0 1287 #define MC_CMD_FC_IN_MAC_OP_WIDTH 8 1288 /* enum: MAC reconfigure handler */ 1289 #define MC_CMD_FC_OP_MAC_OP_RECONFIGURE 0x1 1290 /* enum: MAC Set command - same as MC_CMD_SET_MAC */ 1291 #define MC_CMD_FC_OP_MAC_OP_SET_LINK 0x2 1292 /* enum: MAC statistics */ 1293 #define MC_CMD_FC_OP_MAC_OP_GET_STATS 0x3 1294 /* enum: MAC RX statistics */ 1295 #define MC_CMD_FC_OP_MAC_OP_GET_RX_STATS 0x6 1296 /* enum: MAC TX statistics */ 1297 #define MC_CMD_FC_OP_MAC_OP_GET_TX_STATS 0x7 1298 /* enum: MAC Read status */ 1299 #define MC_CMD_FC_OP_MAC_OP_READ_STATUS 0x8 1300 #define MC_CMD_FC_IN_MAC_PORT_TYPE_LBN 8 1301 #define MC_CMD_FC_IN_MAC_PORT_TYPE_WIDTH 8 1302 /* enum: External FPGA port. */ 1303 #define MC_CMD_FC_PORT_EXT 0x0 1304 /* enum: Internal Siena-facing FPGA ports. */ 1305 #define MC_CMD_FC_PORT_INT 0x1 1306 #define MC_CMD_FC_IN_MAC_PORT_IDX_LBN 16 1307 #define MC_CMD_FC_IN_MAC_PORT_IDX_WIDTH 8 1308 #define MC_CMD_FC_IN_MAC_CMD_FORMAT_LBN 24 1309 #define MC_CMD_FC_IN_MAC_CMD_FORMAT_WIDTH 8 1310 /* enum: Default FC command format; the fields PORT_TYPE and PORT_IDX are 1311 * irrelevant. Port number is derived from pci_fn; passed in FC header. 1312 */ 1313 #define MC_CMD_FC_OP_MAC_CMD_FORMAT_DEFAULT 0x0 1314 /* enum: Override default port number. Port number determined by fields 1315 * PORT_TYPE and PORT_IDX. 1316 */ 1317 #define MC_CMD_FC_OP_MAC_CMD_FORMAT_PORT_OVERRIDE 0x1 1318 1319 /* MC_CMD_FC_IN_MAC_RECONFIGURE msgrequest */ 1320 #define MC_CMD_FC_IN_MAC_RECONFIGURE_LEN 8 1321 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1322 /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ 1323 1324 /* MC_CMD_FC_IN_MAC_SET_LINK msgrequest */ 1325 #define MC_CMD_FC_IN_MAC_SET_LINK_LEN 32 1326 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1327 /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ 1328 /* MTU size */ 1329 #define MC_CMD_FC_IN_MAC_SET_LINK_MTU_OFST 8 1330 /* Drain Tx FIFO */ 1331 #define MC_CMD_FC_IN_MAC_SET_LINK_DRAIN_OFST 12 1332 #define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_OFST 16 1333 #define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_LEN 8 1334 #define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_LO_OFST 16 1335 #define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_HI_OFST 20 1336 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_OFST 24 1337 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_UNICAST_LBN 0 1338 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_UNICAST_WIDTH 1 1339 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_BRDCAST_LBN 1 1340 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_BRDCAST_WIDTH 1 1341 #define MC_CMD_FC_IN_MAC_SET_LINK_FCNTL_OFST 28 1342 1343 /* MC_CMD_FC_IN_MAC_READ_STATUS msgrequest */ 1344 #define MC_CMD_FC_IN_MAC_READ_STATUS_LEN 8 1345 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1346 /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ 1347 1348 /* MC_CMD_FC_IN_MAC_GET_RX_STATS msgrequest */ 1349 #define MC_CMD_FC_IN_MAC_GET_RX_STATS_LEN 8 1350 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1351 /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ 1352 1353 /* MC_CMD_FC_IN_MAC_GET_TX_STATS msgrequest */ 1354 #define MC_CMD_FC_IN_MAC_GET_TX_STATS_LEN 8 1355 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1356 /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ 1357 1358 /* MC_CMD_FC_IN_MAC_GET_STATS msgrequest */ 1359 #define MC_CMD_FC_IN_MAC_GET_STATS_LEN 20 1360 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1361 /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ 1362 /* MC Statistics index */ 1363 #define MC_CMD_FC_IN_MAC_GET_STATS_STATS_INDEX_OFST 8 1364 #define MC_CMD_FC_IN_MAC_GET_STATS_FLAGS_OFST 12 1365 #define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_ALL_LBN 0 1366 #define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_ALL_WIDTH 1 1367 #define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_LBN 1 1368 #define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_WIDTH 1 1369 #define MC_CMD_FC_IN_MAC_GET_STATS_UPDATE_LBN 2 1370 #define MC_CMD_FC_IN_MAC_GET_STATS_UPDATE_WIDTH 1 1371 /* Number of statistics to read */ 1372 #define MC_CMD_FC_IN_MAC_GET_STATS_NUM_OFST 16 1373 #define MC_CMD_FC_MAC_NSTATS_PER_BLOCK 0x1e /* enum */ 1374 #define MC_CMD_FC_MAC_NBYTES_PER_STAT 0x8 /* enum */ 1375 1376 /* MC_CMD_FC_IN_READ32 msgrequest */ 1377 #define MC_CMD_FC_IN_READ32_LEN 16 1378 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1379 #define MC_CMD_FC_IN_READ32_ADDR_HI_OFST 4 1380 #define MC_CMD_FC_IN_READ32_ADDR_LO_OFST 8 1381 #define MC_CMD_FC_IN_READ32_NUMWORDS_OFST 12 1382 1383 /* MC_CMD_FC_IN_WRITE32 msgrequest */ 1384 #define MC_CMD_FC_IN_WRITE32_LENMIN 16 1385 #define MC_CMD_FC_IN_WRITE32_LENMAX 252 1386 #define MC_CMD_FC_IN_WRITE32_LEN(num) (12+4*(num)) 1387 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1388 #define MC_CMD_FC_IN_WRITE32_ADDR_HI_OFST 4 1389 #define MC_CMD_FC_IN_WRITE32_ADDR_LO_OFST 8 1390 #define MC_CMD_FC_IN_WRITE32_BUFFER_OFST 12 1391 #define MC_CMD_FC_IN_WRITE32_BUFFER_LEN 4 1392 #define MC_CMD_FC_IN_WRITE32_BUFFER_MINNUM 1 1393 #define MC_CMD_FC_IN_WRITE32_BUFFER_MAXNUM 60 1394 1395 /* MC_CMD_FC_IN_TRC_READ msgrequest */ 1396 #define MC_CMD_FC_IN_TRC_READ_LEN 12 1397 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1398 #define MC_CMD_FC_IN_TRC_READ_TRC_OFST 4 1399 #define MC_CMD_FC_IN_TRC_READ_CHANNEL_OFST 8 1400 1401 /* MC_CMD_FC_IN_TRC_WRITE msgrequest */ 1402 #define MC_CMD_FC_IN_TRC_WRITE_LEN 28 1403 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1404 #define MC_CMD_FC_IN_TRC_WRITE_TRC_OFST 4 1405 #define MC_CMD_FC_IN_TRC_WRITE_CHANNEL_OFST 8 1406 #define MC_CMD_FC_IN_TRC_WRITE_DATA_OFST 12 1407 #define MC_CMD_FC_IN_TRC_WRITE_DATA_LEN 4 1408 #define MC_CMD_FC_IN_TRC_WRITE_DATA_NUM 4 1409 1410 /* MC_CMD_FC_IN_GET_VERSION msgrequest */ 1411 #define MC_CMD_FC_IN_GET_VERSION_LEN 4 1412 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1413 1414 /* MC_CMD_FC_IN_TRC_RX_READ msgrequest */ 1415 #define MC_CMD_FC_IN_TRC_RX_READ_LEN 12 1416 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1417 #define MC_CMD_FC_IN_TRC_RX_READ_TRC_OFST 4 1418 #define MC_CMD_FC_IN_TRC_RX_READ_CHANNEL_OFST 8 1419 1420 /* MC_CMD_FC_IN_TRC_RX_WRITE msgrequest */ 1421 #define MC_CMD_FC_IN_TRC_RX_WRITE_LEN 20 1422 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1423 #define MC_CMD_FC_IN_TRC_RX_WRITE_TRC_OFST 4 1424 #define MC_CMD_FC_IN_TRC_RX_WRITE_CHANNEL_OFST 8 1425 #define MC_CMD_FC_IN_TRC_RX_WRITE_DATA_OFST 12 1426 #define MC_CMD_FC_IN_TRC_RX_WRITE_DATA_LEN 4 1427 #define MC_CMD_FC_IN_TRC_RX_WRITE_DATA_NUM 2 1428 1429 /* MC_CMD_FC_IN_SFP msgrequest */ 1430 #define MC_CMD_FC_IN_SFP_LEN 28 1431 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1432 /* Link speed is 100, 1000, 10000, 40000 */ 1433 #define MC_CMD_FC_IN_SFP_SPEED_OFST 4 1434 /* Length of copper cable - zero when not relevant (e.g. if cable is fibre) */ 1435 #define MC_CMD_FC_IN_SFP_COPPER_LEN_OFST 8 1436 /* Not relevant for cards with QSFP modules. For older cards, true if module is 1437 * a dual speed SFP+ module. 1438 */ 1439 #define MC_CMD_FC_IN_SFP_DUAL_SPEED_OFST 12 1440 /* True if an SFP Module is present (other fields valid when true) */ 1441 #define MC_CMD_FC_IN_SFP_PRESENT_OFST 16 1442 /* The type of the SFP+ Module. For later cards with QSFP modules, this field 1443 * is unused and the type is communicated by other means. 1444 */ 1445 #define MC_CMD_FC_IN_SFP_TYPE_OFST 20 1446 /* Capabilities corresponding to 1 bits. */ 1447 #define MC_CMD_FC_IN_SFP_CAPS_OFST 24 1448 1449 /* MC_CMD_FC_IN_DDR_TEST msgrequest */ 1450 #define MC_CMD_FC_IN_DDR_TEST_LEN 8 1451 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1452 #define MC_CMD_FC_IN_DDR_TEST_HEADER_OFST 4 1453 #define MC_CMD_FC_IN_DDR_TEST_OP_LBN 0 1454 #define MC_CMD_FC_IN_DDR_TEST_OP_WIDTH 8 1455 /* enum: DRAM Test Start */ 1456 #define MC_CMD_FC_OP_DDR_TEST_START 0x1 1457 /* enum: DRAM Test Poll */ 1458 #define MC_CMD_FC_OP_DDR_TEST_POLL 0x2 1459 1460 /* MC_CMD_FC_IN_DDR_TEST_START msgrequest */ 1461 #define MC_CMD_FC_IN_DDR_TEST_START_LEN 12 1462 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1463 /* MC_CMD_FC_IN_DDR_TEST_HEADER_OFST 4 */ 1464 #define MC_CMD_FC_IN_DDR_TEST_START_MASK_OFST 8 1465 #define MC_CMD_FC_IN_DDR_TEST_START_T0_LBN 0 1466 #define MC_CMD_FC_IN_DDR_TEST_START_T0_WIDTH 1 1467 #define MC_CMD_FC_IN_DDR_TEST_START_T1_LBN 1 1468 #define MC_CMD_FC_IN_DDR_TEST_START_T1_WIDTH 1 1469 #define MC_CMD_FC_IN_DDR_TEST_START_B0_LBN 2 1470 #define MC_CMD_FC_IN_DDR_TEST_START_B0_WIDTH 1 1471 #define MC_CMD_FC_IN_DDR_TEST_START_B1_LBN 3 1472 #define MC_CMD_FC_IN_DDR_TEST_START_B1_WIDTH 1 1473 1474 /* MC_CMD_FC_IN_DDR_TEST_POLL msgrequest */ 1475 #define MC_CMD_FC_IN_DDR_TEST_POLL_LEN 12 1476 #define MC_CMD_FC_IN_DDR_TEST_CMD_OFST 0 1477 /* MC_CMD_FC_IN_DDR_TEST_HEADER_OFST 4 */ 1478 /* Clear previous test result and prepare for restarting DDR test */ 1479 #define MC_CMD_FC_IN_DDR_TEST_POLL_CLEAR_RESULT_FOR_DDR_TEST_OFST 8 1480 1481 /* MC_CMD_FC_IN_GET_ASSERT msgrequest */ 1482 #define MC_CMD_FC_IN_GET_ASSERT_LEN 4 1483 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1484 1485 /* MC_CMD_FC_IN_FPGA_BUILD msgrequest */ 1486 #define MC_CMD_FC_IN_FPGA_BUILD_LEN 8 1487 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1488 /* FPGA build info operation code */ 1489 #define MC_CMD_FC_IN_FPGA_BUILD_OP_OFST 4 1490 /* enum: Get the build registers */ 1491 #define MC_CMD_FC_IN_FPGA_BUILD_BUILD 0x1 1492 /* enum: Get the services registers */ 1493 #define MC_CMD_FC_IN_FPGA_BUILD_SERVICES 0x2 1494 /* enum: Get the BSP version */ 1495 #define MC_CMD_FC_IN_FPGA_BUILD_BSP_VERSION 0x3 1496 /* enum: Get build register for V2 (SFA974X) */ 1497 #define MC_CMD_FC_IN_FPGA_BUILD_BUILD_V2 0x4 1498 /* enum: GEt the services register for V2 (SFA974X) */ 1499 #define MC_CMD_FC_IN_FPGA_BUILD_SERVICES_V2 0x5 1500 1501 /* MC_CMD_FC_IN_READ_MAP msgrequest */ 1502 #define MC_CMD_FC_IN_READ_MAP_LEN 8 1503 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1504 #define MC_CMD_FC_IN_READ_MAP_HEADER_OFST 4 1505 #define MC_CMD_FC_IN_READ_MAP_OP_LBN 0 1506 #define MC_CMD_FC_IN_READ_MAP_OP_WIDTH 8 1507 /* enum: Get the number of map regions */ 1508 #define MC_CMD_FC_OP_READ_MAP_COUNT 0x1 1509 /* enum: Get the specified map */ 1510 #define MC_CMD_FC_OP_READ_MAP_INDEX 0x2 1511 1512 /* MC_CMD_FC_IN_READ_MAP_COUNT msgrequest */ 1513 #define MC_CMD_FC_IN_READ_MAP_COUNT_LEN 8 1514 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1515 /* MC_CMD_FC_IN_READ_MAP_HEADER_OFST 4 */ 1516 1517 /* MC_CMD_FC_IN_READ_MAP_INDEX msgrequest */ 1518 #define MC_CMD_FC_IN_READ_MAP_INDEX_LEN 12 1519 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1520 /* MC_CMD_FC_IN_READ_MAP_HEADER_OFST 4 */ 1521 #define MC_CMD_FC_IN_MAP_INDEX_OFST 8 1522 1523 /* MC_CMD_FC_IN_CAPABILITIES msgrequest */ 1524 #define MC_CMD_FC_IN_CAPABILITIES_LEN 4 1525 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1526 1527 /* MC_CMD_FC_IN_GLOBAL_FLAGS msgrequest */ 1528 #define MC_CMD_FC_IN_GLOBAL_FLAGS_LEN 8 1529 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1530 #define MC_CMD_FC_IN_GLOBAL_FLAGS_FLAGS_OFST 4 1531 #define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_CABLE_PLUGGED_IN_LBN 0 1532 #define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_CABLE_PLUGGED_IN_WIDTH 1 1533 #define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_LINK_MONITORING_LBN 1 1534 #define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_LINK_MONITORING_WIDTH 1 1535 #define MC_CMD_FC_IN_GLOBAL_FLAGS_DFE_ENABLE_LBN 2 1536 #define MC_CMD_FC_IN_GLOBAL_FLAGS_DFE_ENABLE_WIDTH 1 1537 #define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_EYE_ENABLE_LBN 3 1538 #define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_EYE_ENABLE_WIDTH 1 1539 #define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_TUNING_ENABLE_LBN 4 1540 #define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_TUNING_ENABLE_WIDTH 1 1541 #define MC_CMD_FC_IN_GLOBAL_FLAGS_OFFCAL_ENABLE_LBN 5 1542 #define MC_CMD_FC_IN_GLOBAL_FLAGS_OFFCAL_ENABLE_WIDTH 1 1543 1544 /* MC_CMD_FC_IN_IO_REL msgrequest */ 1545 #define MC_CMD_FC_IN_IO_REL_LEN 8 1546 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1547 #define MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 1548 #define MC_CMD_FC_IN_IO_REL_OP_LBN 0 1549 #define MC_CMD_FC_IN_IO_REL_OP_WIDTH 8 1550 /* enum: Get the base address that the FC applies to relative commands */ 1551 #define MC_CMD_FC_IN_IO_REL_GET_ADDR 0x1 1552 /* enum: Read data */ 1553 #define MC_CMD_FC_IN_IO_REL_READ32 0x2 1554 /* enum: Write data */ 1555 #define MC_CMD_FC_IN_IO_REL_WRITE32 0x3 1556 #define MC_CMD_FC_IN_IO_REL_COMP_TYPE_LBN 8 1557 #define MC_CMD_FC_IN_IO_REL_COMP_TYPE_WIDTH 8 1558 /* enum: Application address space */ 1559 #define MC_CMD_FC_COMP_TYPE_APP_ADDR_SPACE 0x1 1560 /* enum: Flash address space */ 1561 #define MC_CMD_FC_COMP_TYPE_FLASH 0x2 1562 1563 /* MC_CMD_FC_IN_IO_REL_GET_ADDR msgrequest */ 1564 #define MC_CMD_FC_IN_IO_REL_GET_ADDR_LEN 8 1565 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1566 /* MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 */ 1567 1568 /* MC_CMD_FC_IN_IO_REL_READ32 msgrequest */ 1569 #define MC_CMD_FC_IN_IO_REL_READ32_LEN 20 1570 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1571 /* MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 */ 1572 #define MC_CMD_FC_IN_IO_REL_READ32_ADDR_HI_OFST 8 1573 #define MC_CMD_FC_IN_IO_REL_READ32_ADDR_LO_OFST 12 1574 #define MC_CMD_FC_IN_IO_REL_READ32_NUMWORDS_OFST 16 1575 1576 /* MC_CMD_FC_IN_IO_REL_WRITE32 msgrequest */ 1577 #define MC_CMD_FC_IN_IO_REL_WRITE32_LENMIN 20 1578 #define MC_CMD_FC_IN_IO_REL_WRITE32_LENMAX 252 1579 #define MC_CMD_FC_IN_IO_REL_WRITE32_LEN(num) (16+4*(num)) 1580 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1581 /* MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 */ 1582 #define MC_CMD_FC_IN_IO_REL_WRITE32_ADDR_HI_OFST 8 1583 #define MC_CMD_FC_IN_IO_REL_WRITE32_ADDR_LO_OFST 12 1584 #define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_OFST 16 1585 #define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_LEN 4 1586 #define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_MINNUM 1 1587 #define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_MAXNUM 59 1588 1589 /* MC_CMD_FC_IN_UHLINK msgrequest */ 1590 #define MC_CMD_FC_IN_UHLINK_LEN 8 1591 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1592 #define MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 1593 #define MC_CMD_FC_IN_UHLINK_OP_LBN 0 1594 #define MC_CMD_FC_IN_UHLINK_OP_WIDTH 8 1595 /* enum: Get PHY configuration info */ 1596 #define MC_CMD_FC_OP_UHLINK_PHY 0x1 1597 /* enum: Get MAC configuration info */ 1598 #define MC_CMD_FC_OP_UHLINK_MAC 0x2 1599 /* enum: Get Rx eye table */ 1600 #define MC_CMD_FC_OP_UHLINK_RX_EYE 0x3 1601 /* enum: Get Rx eye plot */ 1602 #define MC_CMD_FC_OP_UHLINK_DUMP_RX_EYE_PLOT 0x4 1603 /* enum: Get Rx eye plot */ 1604 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT 0x5 1605 /* enum: Retune Rx settings */ 1606 #define MC_CMD_FC_OP_UHLINK_RX_TUNE 0x6 1607 /* enum: Set loopback mode on fpga port */ 1608 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET 0x7 1609 /* enum: Get loopback mode config state on fpga port */ 1610 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_GET 0x8 1611 #define MC_CMD_FC_IN_UHLINK_PORT_TYPE_LBN 8 1612 #define MC_CMD_FC_IN_UHLINK_PORT_TYPE_WIDTH 8 1613 #define MC_CMD_FC_IN_UHLINK_PORT_IDX_LBN 16 1614 #define MC_CMD_FC_IN_UHLINK_PORT_IDX_WIDTH 8 1615 #define MC_CMD_FC_IN_UHLINK_CMD_FORMAT_LBN 24 1616 #define MC_CMD_FC_IN_UHLINK_CMD_FORMAT_WIDTH 8 1617 /* enum: Default FC command format; the fields PORT_TYPE and PORT_IDX are 1618 * irrelevant. Port number is derived from pci_fn; passed in FC header. 1619 */ 1620 #define MC_CMD_FC_OP_UHLINK_CMD_FORMAT_DEFAULT 0x0 1621 /* enum: Override default port number. Port number determined by fields 1622 * PORT_TYPE and PORT_IDX. 1623 */ 1624 #define MC_CMD_FC_OP_UHLINK_CMD_FORMAT_PORT_OVERRIDE 0x1 1625 1626 /* MC_CMD_FC_OP_UHLINK_PHY msgrequest */ 1627 #define MC_CMD_FC_OP_UHLINK_PHY_LEN 8 1628 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1629 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 1630 1631 /* MC_CMD_FC_OP_UHLINK_MAC msgrequest */ 1632 #define MC_CMD_FC_OP_UHLINK_MAC_LEN 8 1633 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1634 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 1635 1636 /* MC_CMD_FC_OP_UHLINK_RX_EYE msgrequest */ 1637 #define MC_CMD_FC_OP_UHLINK_RX_EYE_LEN 12 1638 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1639 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 1640 #define MC_CMD_FC_OP_UHLINK_RX_EYE_INDEX_OFST 8 1641 #define MC_CMD_FC_UHLINK_RX_EYE_PER_BLOCK 0x30 /* enum */ 1642 1643 /* MC_CMD_FC_OP_UHLINK_DUMP_RX_EYE_PLOT msgrequest */ 1644 #define MC_CMD_FC_OP_UHLINK_DUMP_RX_EYE_PLOT_LEN 8 1645 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1646 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 1647 1648 /* MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT msgrequest */ 1649 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_LEN 20 1650 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1651 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 1652 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_DC_GAIN_OFST 8 1653 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_EQ_CONTROL_OFST 12 1654 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_INDEX_OFST 16 1655 #define MC_CMD_FC_UHLINK_RX_EYE_PLOT_ROWS_PER_BLOCK 0x1e /* enum */ 1656 1657 /* MC_CMD_FC_OP_UHLINK_RX_TUNE msgrequest */ 1658 #define MC_CMD_FC_OP_UHLINK_RX_TUNE_LEN 8 1659 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1660 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 1661 1662 /* MC_CMD_FC_OP_UHLINK_LOOPBACK_SET msgrequest */ 1663 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET_LEN 16 1664 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1665 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 1666 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET_TYPE_OFST 8 1667 #define MC_CMD_FC_UHLINK_LOOPBACK_TYPE_PCS_SERIAL 0x0 /* enum */ 1668 #define MC_CMD_FC_UHLINK_LOOPBACK_TYPE_PMA_PRE_CDR 0x1 /* enum */ 1669 #define MC_CMD_FC_UHLINK_LOOPBACK_TYPE_PMA_POST_CDR 0x2 /* enum */ 1670 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET_STATE_OFST 12 1671 #define MC_CMD_FC_UHLINK_LOOPBACK_STATE_OFF 0x0 /* enum */ 1672 #define MC_CMD_FC_UHLINK_LOOPBACK_STATE_ON 0x1 /* enum */ 1673 1674 /* MC_CMD_FC_OP_UHLINK_LOOPBACK_GET msgrequest */ 1675 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_GET_LEN 12 1676 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1677 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 1678 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_GET_TYPE_OFST 8 1679 1680 /* MC_CMD_FC_IN_SET_LINK msgrequest */ 1681 #define MC_CMD_FC_IN_SET_LINK_LEN 16 1682 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1683 /* See MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */ 1684 #define MC_CMD_FC_IN_SET_LINK_MODE_OFST 4 1685 #define MC_CMD_FC_IN_SET_LINK_SPEED_OFST 8 1686 #define MC_CMD_FC_IN_SET_LINK_FLAGS_OFST 12 1687 #define MC_CMD_FC_IN_SET_LINK_LOWPOWER_LBN 0 1688 #define MC_CMD_FC_IN_SET_LINK_LOWPOWER_WIDTH 1 1689 #define MC_CMD_FC_IN_SET_LINK_POWEROFF_LBN 1 1690 #define MC_CMD_FC_IN_SET_LINK_POWEROFF_WIDTH 1 1691 #define MC_CMD_FC_IN_SET_LINK_TXDIS_LBN 2 1692 #define MC_CMD_FC_IN_SET_LINK_TXDIS_WIDTH 1 1693 1694 /* MC_CMD_FC_IN_LICENSE msgrequest */ 1695 #define MC_CMD_FC_IN_LICENSE_LEN 8 1696 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1697 #define MC_CMD_FC_IN_LICENSE_OP_OFST 4 1698 #define MC_CMD_FC_IN_LICENSE_UPDATE_LICENSE 0x0 /* enum */ 1699 #define MC_CMD_FC_IN_LICENSE_GET_KEY_STATS 0x1 /* enum */ 1700 1701 /* MC_CMD_FC_IN_STARTUP msgrequest */ 1702 #define MC_CMD_FC_IN_STARTUP_LEN 40 1703 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1704 #define MC_CMD_FC_IN_STARTUP_BASE_OFST 4 1705 #define MC_CMD_FC_IN_STARTUP_LENGTH_OFST 8 1706 /* Length of identifier */ 1707 #define MC_CMD_FC_IN_STARTUP_IDLENGTH_OFST 12 1708 /* Identifier for AOE FPGA */ 1709 #define MC_CMD_FC_IN_STARTUP_ID_OFST 16 1710 #define MC_CMD_FC_IN_STARTUP_ID_LEN 1 1711 #define MC_CMD_FC_IN_STARTUP_ID_NUM 24 1712 1713 /* MC_CMD_FC_IN_DMA msgrequest */ 1714 #define MC_CMD_FC_IN_DMA_LEN 8 1715 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1716 #define MC_CMD_FC_IN_DMA_OP_OFST 4 1717 #define MC_CMD_FC_IN_DMA_STOP 0x0 /* enum */ 1718 #define MC_CMD_FC_IN_DMA_READ 0x1 /* enum */ 1719 1720 /* MC_CMD_FC_IN_DMA_STOP msgrequest */ 1721 #define MC_CMD_FC_IN_DMA_STOP_LEN 12 1722 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1723 /* MC_CMD_FC_IN_DMA_OP_OFST 4 */ 1724 /* FC supplied handle */ 1725 #define MC_CMD_FC_IN_DMA_STOP_FC_HANDLE_OFST 8 1726 1727 /* MC_CMD_FC_IN_DMA_READ msgrequest */ 1728 #define MC_CMD_FC_IN_DMA_READ_LEN 16 1729 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1730 /* MC_CMD_FC_IN_DMA_OP_OFST 4 */ 1731 #define MC_CMD_FC_IN_DMA_READ_OFFSET_OFST 8 1732 #define MC_CMD_FC_IN_DMA_READ_LENGTH_OFST 12 1733 1734 /* MC_CMD_FC_IN_TIMED_READ msgrequest */ 1735 #define MC_CMD_FC_IN_TIMED_READ_LEN 8 1736 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1737 #define MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 1738 #define MC_CMD_FC_IN_TIMED_READ_SET 0x0 /* enum */ 1739 #define MC_CMD_FC_IN_TIMED_READ_GET 0x1 /* enum */ 1740 #define MC_CMD_FC_IN_TIMED_READ_CLEAR 0x2 /* enum */ 1741 1742 /* MC_CMD_FC_IN_TIMED_READ_SET msgrequest */ 1743 #define MC_CMD_FC_IN_TIMED_READ_SET_LEN 52 1744 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1745 /* MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 */ 1746 /* Host supplied handle (unique) */ 1747 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_HANDLE_OFST 8 1748 /* Address into which to transfer data in host */ 1749 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_OFST 12 1750 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_LEN 8 1751 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_LO_OFST 12 1752 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_HI_OFST 16 1753 /* AOE address from which to transfer data */ 1754 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_OFST 20 1755 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_LEN 8 1756 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_LO_OFST 20 1757 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_HI_OFST 24 1758 /* Length of AOE transfer (total) */ 1759 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_LENGTH_OFST 28 1760 /* Length of host transfer (total) */ 1761 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_LENGTH_OFST 32 1762 /* Offset back from aoe_address to apply operation to */ 1763 #define MC_CMD_FC_IN_TIMED_READ_SET_OFFSET_OFST 36 1764 /* Data to apply at offset */ 1765 #define MC_CMD_FC_IN_TIMED_READ_SET_DATA_OFST 40 1766 #define MC_CMD_FC_IN_TIMED_READ_SET_FLAGS_OFST 44 1767 #define MC_CMD_FC_IN_TIMED_READ_SET_INDIRECT_LBN 0 1768 #define MC_CMD_FC_IN_TIMED_READ_SET_INDIRECT_WIDTH 1 1769 #define MC_CMD_FC_IN_TIMED_READ_SET_DOUBLE_LBN 1 1770 #define MC_CMD_FC_IN_TIMED_READ_SET_DOUBLE_WIDTH 1 1771 #define MC_CMD_FC_IN_TIMED_READ_SET_EVENT_LBN 2 1772 #define MC_CMD_FC_IN_TIMED_READ_SET_EVENT_WIDTH 1 1773 #define MC_CMD_FC_IN_TIMED_READ_SET_PREREAD_LBN 3 1774 #define MC_CMD_FC_IN_TIMED_READ_SET_PREREAD_WIDTH 2 1775 #define MC_CMD_FC_IN_TIMED_READ_SET_NONE 0x0 /* enum */ 1776 #define MC_CMD_FC_IN_TIMED_READ_SET_READ 0x1 /* enum */ 1777 #define MC_CMD_FC_IN_TIMED_READ_SET_WRITE 0x2 /* enum */ 1778 #define MC_CMD_FC_IN_TIMED_READ_SET_READWRITE 0x3 /* enum */ 1779 /* Period at which reads are performed (100ms units) */ 1780 #define MC_CMD_FC_IN_TIMED_READ_SET_PERIOD_OFST 48 1781 1782 /* MC_CMD_FC_IN_TIMED_READ_GET msgrequest */ 1783 #define MC_CMD_FC_IN_TIMED_READ_GET_LEN 12 1784 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1785 /* MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 */ 1786 /* FC supplied handle */ 1787 #define MC_CMD_FC_IN_TIMED_READ_GET_FC_HANDLE_OFST 8 1788 1789 /* MC_CMD_FC_IN_TIMED_READ_CLEAR msgrequest */ 1790 #define MC_CMD_FC_IN_TIMED_READ_CLEAR_LEN 12 1791 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1792 /* MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 */ 1793 /* FC supplied handle */ 1794 #define MC_CMD_FC_IN_TIMED_READ_CLEAR_FC_HANDLE_OFST 8 1795 1796 /* MC_CMD_FC_IN_LOG msgrequest */ 1797 #define MC_CMD_FC_IN_LOG_LEN 8 1798 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1799 #define MC_CMD_FC_IN_LOG_OP_OFST 4 1800 #define MC_CMD_FC_IN_LOG_ADDR_RANGE 0x0 /* enum */ 1801 #define MC_CMD_FC_IN_LOG_JTAG_UART 0x1 /* enum */ 1802 1803 /* MC_CMD_FC_IN_LOG_ADDR_RANGE msgrequest */ 1804 #define MC_CMD_FC_IN_LOG_ADDR_RANGE_LEN 20 1805 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1806 /* MC_CMD_FC_IN_LOG_OP_OFST 4 */ 1807 /* Partition offset into flash */ 1808 #define MC_CMD_FC_IN_LOG_ADDR_RANGE_OFFSET_OFST 8 1809 /* Partition length */ 1810 #define MC_CMD_FC_IN_LOG_ADDR_RANGE_LENGTH_OFST 12 1811 /* Partition erase size */ 1812 #define MC_CMD_FC_IN_LOG_ADDR_RANGE_ERASE_SIZE_OFST 16 1813 1814 /* MC_CMD_FC_IN_LOG_JTAG_UART msgrequest */ 1815 #define MC_CMD_FC_IN_LOG_JTAG_UART_LEN 12 1816 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1817 /* MC_CMD_FC_IN_LOG_OP_OFST 4 */ 1818 /* Enable/disable printing to JTAG UART */ 1819 #define MC_CMD_FC_IN_LOG_JTAG_UART_ENABLE_OFST 8 1820 1821 /* MC_CMD_FC_IN_CLOCK msgrequest */ 1822 #define MC_CMD_FC_IN_CLOCK_LEN 12 1823 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1824 #define MC_CMD_FC_IN_CLOCK_OP_OFST 4 1825 #define MC_CMD_FC_IN_CLOCK_GET_TIME 0x0 /* enum */ 1826 #define MC_CMD_FC_IN_CLOCK_SET_TIME 0x1 /* enum */ 1827 /* Perform a clock operation */ 1828 #define MC_CMD_FC_IN_CLOCK_ID_OFST 8 1829 #define MC_CMD_FC_IN_CLOCK_STATS 0x0 /* enum */ 1830 #define MC_CMD_FC_IN_CLOCK_MAC 0x1 /* enum */ 1831 1832 /* MC_CMD_FC_IN_CLOCK_GET_TIME msgrequest */ 1833 #define MC_CMD_FC_IN_CLOCK_GET_TIME_LEN 12 1834 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1835 /* MC_CMD_FC_IN_CLOCK_OP_OFST 4 */ 1836 /* Retrieve the clock value of the specified clock */ 1837 /* MC_CMD_FC_IN_CLOCK_ID_OFST 8 */ 1838 1839 /* MC_CMD_FC_IN_CLOCK_SET_TIME msgrequest */ 1840 #define MC_CMD_FC_IN_CLOCK_SET_TIME_LEN 24 1841 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1842 /* MC_CMD_FC_IN_CLOCK_OP_OFST 4 */ 1843 /* MC_CMD_FC_IN_CLOCK_ID_OFST 8 */ 1844 #define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_OFST 12 1845 #define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LEN 8 1846 #define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LO_OFST 12 1847 #define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_HI_OFST 16 1848 /* Set the clock value of the specified clock */ 1849 #define MC_CMD_FC_IN_CLOCK_SET_TIME_NANOSECONDS_OFST 20 1850 1851 /* MC_CMD_FC_IN_DDR msgrequest */ 1852 #define MC_CMD_FC_IN_DDR_LEN 12 1853 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1854 #define MC_CMD_FC_IN_DDR_OP_OFST 4 1855 #define MC_CMD_FC_IN_DDR_SET_SPD 0x0 /* enum */ 1856 #define MC_CMD_FC_IN_DDR_GET_STATUS 0x1 /* enum */ 1857 #define MC_CMD_FC_IN_DDR_SET_INFO 0x2 /* enum */ 1858 #define MC_CMD_FC_IN_DDR_BANK_OFST 8 1859 #define MC_CMD_FC_IN_DDR_BANK_B0 0x0 /* enum */ 1860 #define MC_CMD_FC_IN_DDR_BANK_B1 0x1 /* enum */ 1861 #define MC_CMD_FC_IN_DDR_BANK_T0 0x2 /* enum */ 1862 #define MC_CMD_FC_IN_DDR_BANK_T1 0x3 /* enum */ 1863 #define MC_CMD_FC_IN_DDR_NUM_BANKS 0x4 /* enum */ 1864 1865 /* MC_CMD_FC_IN_DDR_SET_SPD msgrequest */ 1866 #define MC_CMD_FC_IN_DDR_SET_SPD_LEN 148 1867 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1868 /* MC_CMD_FC_IN_DDR_OP_OFST 4 */ 1869 /* Affected bank */ 1870 /* MC_CMD_FC_IN_DDR_BANK_OFST 8 */ 1871 /* Flags */ 1872 #define MC_CMD_FC_IN_DDR_FLAGS_OFST 12 1873 #define MC_CMD_FC_IN_DDR_SET_SPD_ACTIVE 0x1 /* enum */ 1874 /* 128-byte page of serial presence detect data read from module's EEPROM */ 1875 #define MC_CMD_FC_IN_DDR_SPD_OFST 16 1876 #define MC_CMD_FC_IN_DDR_SPD_LEN 1 1877 #define MC_CMD_FC_IN_DDR_SPD_NUM 128 1878 /* Page index of the spd data copied into MC_CMD_FC_IN_DDR_SPD */ 1879 #define MC_CMD_FC_IN_DDR_SPD_PAGE_ID_OFST 144 1880 1881 /* MC_CMD_FC_IN_DDR_SET_INFO msgrequest */ 1882 #define MC_CMD_FC_IN_DDR_SET_INFO_LEN 16 1883 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1884 /* MC_CMD_FC_IN_DDR_OP_OFST 4 */ 1885 /* Affected bank */ 1886 /* MC_CMD_FC_IN_DDR_BANK_OFST 8 */ 1887 /* Size of DDR */ 1888 #define MC_CMD_FC_IN_DDR_SIZE_OFST 12 1889 1890 /* MC_CMD_FC_IN_DDR_GET_STATUS msgrequest */ 1891 #define MC_CMD_FC_IN_DDR_GET_STATUS_LEN 12 1892 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1893 /* MC_CMD_FC_IN_DDR_OP_OFST 4 */ 1894 /* Affected bank */ 1895 /* MC_CMD_FC_IN_DDR_BANK_OFST 8 */ 1896 1897 /* MC_CMD_FC_IN_TIMESTAMP msgrequest */ 1898 #define MC_CMD_FC_IN_TIMESTAMP_LEN 8 1899 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1900 /* FC timestamp operation code */ 1901 #define MC_CMD_FC_IN_TIMESTAMP_OP_OFST 4 1902 /* enum: Read transmit timestamp(s) */ 1903 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT 0x0 1904 /* enum: Read snapshot timestamps */ 1905 #define MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT 0x1 1906 /* enum: Clear all transmit timestamps */ 1907 #define MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT 0x2 1908 1909 /* MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT msgrequest */ 1910 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_LEN 28 1911 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1912 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_OP_OFST 4 1913 /* Control filtering of the returned timestamp and sequence number specified 1914 * here 1915 */ 1916 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_FILTER_OFST 8 1917 /* enum: Return most recent timestamp. No filtering */ 1918 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_LATEST 0x0 1919 /* enum: Match timestamp against the PTP clock ID, port number and sequence 1920 * number specified 1921 */ 1922 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_MATCH 0x1 1923 /* Clock identity of PTP packet for which timestamp required */ 1924 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_OFST 12 1925 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_LEN 8 1926 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_LO_OFST 12 1927 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_HI_OFST 16 1928 /* Port number of PTP packet for which timestamp required */ 1929 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_PORT_NUM_OFST 20 1930 /* Sequence number of PTP packet for which timestamp required */ 1931 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_SEQ_NUM_OFST 24 1932 1933 /* MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT msgrequest */ 1934 #define MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT_LEN 8 1935 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1936 #define MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT_OP_OFST 4 1937 1938 /* MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT msgrequest */ 1939 #define MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT_LEN 8 1940 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1941 #define MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT_OP_OFST 4 1942 1943 /* MC_CMD_FC_IN_SPI msgrequest */ 1944 #define MC_CMD_FC_IN_SPI_LEN 8 1945 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1946 /* Basic commands for SPI Flash. */ 1947 #define MC_CMD_FC_IN_SPI_OP_OFST 4 1948 /* enum: SPI Flash read */ 1949 #define MC_CMD_FC_IN_SPI_READ 0x0 1950 /* enum: SPI Flash write */ 1951 #define MC_CMD_FC_IN_SPI_WRITE 0x1 1952 /* enum: SPI Flash erase */ 1953 #define MC_CMD_FC_IN_SPI_ERASE 0x2 1954 1955 /* MC_CMD_FC_IN_SPI_READ msgrequest */ 1956 #define MC_CMD_FC_IN_SPI_READ_LEN 16 1957 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1958 #define MC_CMD_FC_IN_SPI_READ_OP_OFST 4 1959 #define MC_CMD_FC_IN_SPI_READ_ADDR_OFST 8 1960 #define MC_CMD_FC_IN_SPI_READ_NUMBYTES_OFST 12 1961 1962 /* MC_CMD_FC_IN_SPI_WRITE msgrequest */ 1963 #define MC_CMD_FC_IN_SPI_WRITE_LENMIN 16 1964 #define MC_CMD_FC_IN_SPI_WRITE_LENMAX 252 1965 #define MC_CMD_FC_IN_SPI_WRITE_LEN(num) (12+4*(num)) 1966 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1967 #define MC_CMD_FC_IN_SPI_WRITE_OP_OFST 4 1968 #define MC_CMD_FC_IN_SPI_WRITE_ADDR_OFST 8 1969 #define MC_CMD_FC_IN_SPI_WRITE_BUFFER_OFST 12 1970 #define MC_CMD_FC_IN_SPI_WRITE_BUFFER_LEN 4 1971 #define MC_CMD_FC_IN_SPI_WRITE_BUFFER_MINNUM 1 1972 #define MC_CMD_FC_IN_SPI_WRITE_BUFFER_MAXNUM 60 1973 1974 /* MC_CMD_FC_IN_SPI_ERASE msgrequest */ 1975 #define MC_CMD_FC_IN_SPI_ERASE_LEN 16 1976 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1977 #define MC_CMD_FC_IN_SPI_ERASE_OP_OFST 4 1978 #define MC_CMD_FC_IN_SPI_ERASE_ADDR_OFST 8 1979 #define MC_CMD_FC_IN_SPI_ERASE_NUMBYTES_OFST 12 1980 1981 /* MC_CMD_FC_IN_DIAG msgrequest */ 1982 #define MC_CMD_FC_IN_DIAG_LEN 8 1983 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1984 /* Operation code indicating component type */ 1985 #define MC_CMD_FC_IN_DIAG_OP_OFST 4 1986 /* enum: Power noise generator. */ 1987 #define MC_CMD_FC_IN_DIAG_POWER_NOISE 0x0 1988 /* enum: DDR soak test component. */ 1989 #define MC_CMD_FC_IN_DIAG_DDR_SOAK 0x1 1990 /* enum: Diagnostics datapath control component. */ 1991 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL 0x2 1992 1993 /* MC_CMD_FC_IN_DIAG_POWER_NOISE msgrequest */ 1994 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_LEN 12 1995 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1996 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_OP_OFST 4 1997 /* Sub-opcode describing the operation to be carried out */ 1998 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_SUB_OP_OFST 8 1999 /* enum: Read the configuration (the 32-bit values in each of the clock enable 2000 * count and toggle count registers) 2001 */ 2002 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG 0x0 2003 /* enum: Write a new configuration to the clock enable count and toggle count 2004 * registers 2005 */ 2006 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG 0x1 2007 2008 /* MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG msgrequest */ 2009 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_LEN 12 2010 /* MC_CMD_FC_IN_CMD_OFST 0 */ 2011 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_OP_OFST 4 2012 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_SUB_OP_OFST 8 2013 2014 /* MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG msgrequest */ 2015 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_LEN 20 2016 /* MC_CMD_FC_IN_CMD_OFST 0 */ 2017 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_OP_OFST 4 2018 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_SUB_OP_OFST 8 2019 /* The 32-bit value to be written to the toggle count register */ 2020 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_TOGGLE_COUNT_OFST 12 2021 /* The 32-bit value to be written to the clock enable count register */ 2022 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_CLKEN_COUNT_OFST 16 2023 2024 /* MC_CMD_FC_IN_DIAG_DDR_SOAK msgrequest */ 2025 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_LEN 12 2026 /* MC_CMD_FC_IN_CMD_OFST 0 */ 2027 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_OP_OFST 4 2028 /* Sub-opcode describing the operation to be carried out */ 2029 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_SUB_OP_OFST 8 2030 /* enum: Starts DDR soak test on selected banks */ 2031 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START 0x0 2032 /* enum: Read status of DDR soak test */ 2033 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT 0x1 2034 /* enum: Stop test */ 2035 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP 0x2 2036 /* enum: Set or clear bit that triggers fake errors. These cause subsequent 2037 * tests to fail until the bit is cleared. 2038 */ 2039 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR 0x3 2040 2041 /* MC_CMD_FC_IN_DIAG_DDR_SOAK_START msgrequest */ 2042 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_LEN 24 2043 /* MC_CMD_FC_IN_CMD_OFST 0 */ 2044 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_OP_OFST 4 2045 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_SUB_OP_OFST 8 2046 /* Mask of DDR banks to be tested */ 2047 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_BANK_MASK_OFST 12 2048 /* Pattern to use in the soak test */ 2049 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_TEST_PATTERN_OFST 16 2050 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_ZEROS 0x0 /* enum */ 2051 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_ONES 0x1 /* enum */ 2052 /* Either multiple automatic tests until a STOP command is issued, or one 2053 * single test 2054 */ 2055 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_TEST_TYPE_OFST 20 2056 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_ONGOING_TEST 0x0 /* enum */ 2057 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_SINGLE_TEST 0x1 /* enum */ 2058 2059 /* MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT msgrequest */ 2060 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_LEN 16 2061 /* MC_CMD_FC_IN_CMD_OFST 0 */ 2062 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_OP_OFST 4 2063 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_SUB_OP_OFST 8 2064 /* DDR bank to read status from */ 2065 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_BANK_ID_OFST 12 2066 #define MC_CMD_FC_DDR_BANK0 0x0 /* enum */ 2067 #define MC_CMD_FC_DDR_BANK1 0x1 /* enum */ 2068 #define MC_CMD_FC_DDR_BANK2 0x2 /* enum */ 2069 #define MC_CMD_FC_DDR_BANK3 0x3 /* enum */ 2070 #define MC_CMD_FC_DDR_AOEMEM_MAX_BANKS 0x4 /* enum */ 2071 2072 /* MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP msgrequest */ 2073 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_LEN 16 2074 /* MC_CMD_FC_IN_CMD_OFST 0 */ 2075 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_OP_OFST 4 2076 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_SUB_OP_OFST 8 2077 /* Mask of DDR banks to be tested */ 2078 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_BANK_MASK_OFST 12 2079 2080 /* MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR msgrequest */ 2081 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_LEN 20 2082 /* MC_CMD_FC_IN_CMD_OFST 0 */ 2083 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_OP_OFST 4 2084 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_SUB_OP_OFST 8 2085 /* Mask of DDR banks to set/clear error flag on */ 2086 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_BANK_MASK_OFST 12 2087 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_FLAG_ACTION_OFST 16 2088 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_CLEAR 0x0 /* enum */ 2089 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_SET 0x1 /* enum */ 2090 2091 /* MC_CMD_FC_IN_DIAG_DATAPATH_CTRL msgrequest */ 2092 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_LEN 12 2093 /* MC_CMD_FC_IN_CMD_OFST 0 */ 2094 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_OP_OFST 4 2095 /* Sub-opcode describing the operation to be carried out */ 2096 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SUB_OP_OFST 8 2097 /* enum: Set a known datapath configuration */ 2098 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE 0x0 2099 /* enum: Apply raw config to datapath control registers */ 2100 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG 0x1 2101 2102 /* MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE msgrequest */ 2103 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_LEN 16 2104 /* MC_CMD_FC_IN_CMD_OFST 0 */ 2105 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_OP_OFST 4 2106 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_SUB_OP_OFST 8 2107 /* Datapath configuration identifier */ 2108 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_MODE_OFST 12 2109 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_PASSTHROUGH 0x0 /* enum */ 2110 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_SNAKE 0x1 /* enum */ 2111 2112 /* MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG msgrequest */ 2113 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_LEN 24 2114 /* MC_CMD_FC_IN_CMD_OFST 0 */ 2115 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_OP_OFST 4 2116 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_SUB_OP_OFST 8 2117 /* Value to write into control register 1 */ 2118 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL1_OFST 12 2119 /* Value to write into control register 2 */ 2120 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL2_OFST 16 2121 /* Value to write into control register 3 */ 2122 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL3_OFST 20 2123 2124 /* MC_CMD_FC_OUT msgresponse */ 2125 #define MC_CMD_FC_OUT_LEN 0 2126 2127 /* MC_CMD_FC_OUT_NULL msgresponse */ 2128 #define MC_CMD_FC_OUT_NULL_LEN 0 2129 2130 /* MC_CMD_FC_OUT_READ32 msgresponse */ 2131 #define MC_CMD_FC_OUT_READ32_LENMIN 4 2132 #define MC_CMD_FC_OUT_READ32_LENMAX 252 2133 #define MC_CMD_FC_OUT_READ32_LEN(num) (0+4*(num)) 2134 #define MC_CMD_FC_OUT_READ32_BUFFER_OFST 0 2135 #define MC_CMD_FC_OUT_READ32_BUFFER_LEN 4 2136 #define MC_CMD_FC_OUT_READ32_BUFFER_MINNUM 1 2137 #define MC_CMD_FC_OUT_READ32_BUFFER_MAXNUM 63 2138 2139 /* MC_CMD_FC_OUT_WRITE32 msgresponse */ 2140 #define MC_CMD_FC_OUT_WRITE32_LEN 0 2141 2142 /* MC_CMD_FC_OUT_TRC_READ msgresponse */ 2143 #define MC_CMD_FC_OUT_TRC_READ_LEN 16 2144 #define MC_CMD_FC_OUT_TRC_READ_DATA_OFST 0 2145 #define MC_CMD_FC_OUT_TRC_READ_DATA_LEN 4 2146 #define MC_CMD_FC_OUT_TRC_READ_DATA_NUM 4 2147 2148 /* MC_CMD_FC_OUT_TRC_WRITE msgresponse */ 2149 #define MC_CMD_FC_OUT_TRC_WRITE_LEN 0 2150 2151 /* MC_CMD_FC_OUT_GET_VERSION msgresponse */ 2152 #define MC_CMD_FC_OUT_GET_VERSION_LEN 12 2153 #define MC_CMD_FC_OUT_GET_VERSION_FIRMWARE_OFST 0 2154 #define MC_CMD_FC_OUT_GET_VERSION_VERSION_OFST 4 2155 #define MC_CMD_FC_OUT_GET_VERSION_VERSION_LEN 8 2156 #define MC_CMD_FC_OUT_GET_VERSION_VERSION_LO_OFST 4 2157 #define MC_CMD_FC_OUT_GET_VERSION_VERSION_HI_OFST 8 2158 2159 /* MC_CMD_FC_OUT_TRC_RX_READ msgresponse */ 2160 #define MC_CMD_FC_OUT_TRC_RX_READ_LEN 8 2161 #define MC_CMD_FC_OUT_TRC_RX_READ_DATA_OFST 0 2162 #define MC_CMD_FC_OUT_TRC_RX_READ_DATA_LEN 4 2163 #define MC_CMD_FC_OUT_TRC_RX_READ_DATA_NUM 2 2164 2165 /* MC_CMD_FC_OUT_TRC_RX_WRITE msgresponse */ 2166 #define MC_CMD_FC_OUT_TRC_RX_WRITE_LEN 0 2167 2168 /* MC_CMD_FC_OUT_MAC_RECONFIGURE msgresponse */ 2169 #define MC_CMD_FC_OUT_MAC_RECONFIGURE_LEN 0 2170 2171 /* MC_CMD_FC_OUT_MAC_SET_LINK msgresponse */ 2172 #define MC_CMD_FC_OUT_MAC_SET_LINK_LEN 0 2173 2174 /* MC_CMD_FC_OUT_MAC_READ_STATUS msgresponse */ 2175 #define MC_CMD_FC_OUT_MAC_READ_STATUS_LEN 4 2176 #define MC_CMD_FC_OUT_MAC_READ_STATUS_STATUS_OFST 0 2177 2178 /* MC_CMD_FC_OUT_MAC_GET_RX_STATS msgresponse */ 2179 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_LEN ((((0-1+(64*MC_CMD_FC_MAC_RX_NSTATS))+1))>>3) 2180 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_OFST 0 2181 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_LEN 8 2182 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_LO_OFST 0 2183 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_HI_OFST 4 2184 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_NUM MC_CMD_FC_MAC_RX_NSTATS 2185 #define MC_CMD_FC_MAC_RX_STATS_OCTETS 0x0 /* enum */ 2186 #define MC_CMD_FC_MAC_RX_OCTETS_OK 0x1 /* enum */ 2187 #define MC_CMD_FC_MAC_RX_ALIGNMENT_ERRORS 0x2 /* enum */ 2188 #define MC_CMD_FC_MAC_RX_PAUSE_MAC_CTRL_FRAMES 0x3 /* enum */ 2189 #define MC_CMD_FC_MAC_RX_FRAMES_OK 0x4 /* enum */ 2190 #define MC_CMD_FC_MAC_RX_CRC_ERRORS 0x5 /* enum */ 2191 #define MC_CMD_FC_MAC_RX_VLAN_OK 0x6 /* enum */ 2192 #define MC_CMD_FC_MAC_RX_ERRORS 0x7 /* enum */ 2193 #define MC_CMD_FC_MAC_RX_UCAST_PKTS 0x8 /* enum */ 2194 #define MC_CMD_FC_MAC_RX_MULTICAST_PKTS 0x9 /* enum */ 2195 #define MC_CMD_FC_MAC_RX_BROADCAST_PKTS 0xa /* enum */ 2196 #define MC_CMD_FC_MAC_RX_STATS_DROP_EVENTS 0xb /* enum */ 2197 #define MC_CMD_FC_MAC_RX_STATS_PKTS 0xc /* enum */ 2198 #define MC_CMD_FC_MAC_RX_STATS_UNDERSIZE_PKTS 0xd /* enum */ 2199 #define MC_CMD_FC_MAC_RX_STATS_PKTS_64 0xe /* enum */ 2200 #define MC_CMD_FC_MAC_RX_STATS_PKTS_65_127 0xf /* enum */ 2201 #define MC_CMD_FC_MAC_RX_STATS_PKTS_128_255 0x10 /* enum */ 2202 #define MC_CMD_FC_MAC_RX_STATS_PKTS_256_511 0x11 /* enum */ 2203 #define MC_CMD_FC_MAC_RX_STATS_PKTS_512_1023 0x12 /* enum */ 2204 #define MC_CMD_FC_MAC_RX_STATS_PKTS_1024_1518 0x13 /* enum */ 2205 #define MC_CMD_FC_MAC_RX_STATS_PKTS_1519_MAX 0x14 /* enum */ 2206 #define MC_CMD_FC_MAC_RX_STATS_OVERSIZE_PKTS 0x15 /* enum */ 2207 #define MC_CMD_FC_MAC_RX_STATS_JABBERS 0x16 /* enum */ 2208 #define MC_CMD_FC_MAC_RX_STATS_FRAGMENTS 0x17 /* enum */ 2209 #define MC_CMD_FC_MAC_RX_MAC_CONTROL_FRAMES 0x18 /* enum */ 2210 /* enum: (Last entry) */ 2211 #define MC_CMD_FC_MAC_RX_NSTATS 0x19 2212 2213 /* MC_CMD_FC_OUT_MAC_GET_TX_STATS msgresponse */ 2214 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_LEN ((((0-1+(64*MC_CMD_FC_MAC_TX_NSTATS))+1))>>3) 2215 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_OFST 0 2216 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_LEN 8 2217 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_LO_OFST 0 2218 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_HI_OFST 4 2219 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_NUM MC_CMD_FC_MAC_TX_NSTATS 2220 #define MC_CMD_FC_MAC_TX_STATS_OCTETS 0x0 /* enum */ 2221 #define MC_CMD_FC_MAC_TX_OCTETS_OK 0x1 /* enum */ 2222 #define MC_CMD_FC_MAC_TX_ALIGNMENT_ERRORS 0x2 /* enum */ 2223 #define MC_CMD_FC_MAC_TX_PAUSE_MAC_CTRL_FRAMES 0x3 /* enum */ 2224 #define MC_CMD_FC_MAC_TX_FRAMES_OK 0x4 /* enum */ 2225 #define MC_CMD_FC_MAC_TX_CRC_ERRORS 0x5 /* enum */ 2226 #define MC_CMD_FC_MAC_TX_VLAN_OK 0x6 /* enum */ 2227 #define MC_CMD_FC_MAC_TX_ERRORS 0x7 /* enum */ 2228 #define MC_CMD_FC_MAC_TX_UCAST_PKTS 0x8 /* enum */ 2229 #define MC_CMD_FC_MAC_TX_MULTICAST_PKTS 0x9 /* enum */ 2230 #define MC_CMD_FC_MAC_TX_BROADCAST_PKTS 0xa /* enum */ 2231 #define MC_CMD_FC_MAC_TX_STATS_DROP_EVENTS 0xb /* enum */ 2232 #define MC_CMD_FC_MAC_TX_STATS_PKTS 0xc /* enum */ 2233 #define MC_CMD_FC_MAC_TX_STATS_UNDERSIZE_PKTS 0xd /* enum */ 2234 #define MC_CMD_FC_MAC_TX_STATS_PKTS_64 0xe /* enum */ 2235 #define MC_CMD_FC_MAC_TX_STATS_PKTS_65_127 0xf /* enum */ 2236 #define MC_CMD_FC_MAC_TX_STATS_PKTS_128_255 0x10 /* enum */ 2237 #define MC_CMD_FC_MAC_TX_STATS_PKTS_256_511 0x11 /* enum */ 2238 #define MC_CMD_FC_MAC_TX_STATS_PKTS_512_1023 0x12 /* enum */ 2239 #define MC_CMD_FC_MAC_TX_STATS_PKTS_1024_1518 0x13 /* enum */ 2240 #define MC_CMD_FC_MAC_TX_STATS_PKTS_1519_TX_MTU 0x14 /* enum */ 2241 #define MC_CMD_FC_MAC_TX_MAC_CONTROL_FRAMES 0x15 /* enum */ 2242 /* enum: (Last entry) */ 2243 #define MC_CMD_FC_MAC_TX_NSTATS 0x16 2244 2245 /* MC_CMD_FC_OUT_MAC_GET_STATS msgresponse */ 2246 #define MC_CMD_FC_OUT_MAC_GET_STATS_LEN ((((0-1+(64*MC_CMD_FC_MAC_NSTATS_PER_BLOCK))+1))>>3) 2247 /* MAC Statistics */ 2248 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_OFST 0 2249 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_LEN 8 2250 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_LO_OFST 0 2251 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_HI_OFST 4 2252 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_NUM MC_CMD_FC_MAC_NSTATS_PER_BLOCK 2253 2254 /* MC_CMD_FC_OUT_MAC msgresponse */ 2255 #define MC_CMD_FC_OUT_MAC_LEN 0 2256 2257 /* MC_CMD_FC_OUT_SFP msgresponse */ 2258 #define MC_CMD_FC_OUT_SFP_LEN 0 2259 2260 /* MC_CMD_FC_OUT_DDR_TEST_START msgresponse */ 2261 #define MC_CMD_FC_OUT_DDR_TEST_START_LEN 0 2262 2263 /* MC_CMD_FC_OUT_DDR_TEST_POLL msgresponse */ 2264 #define MC_CMD_FC_OUT_DDR_TEST_POLL_LEN 8 2265 #define MC_CMD_FC_OUT_DDR_TEST_POLL_STATUS_OFST 0 2266 #define MC_CMD_FC_OUT_DDR_TEST_POLL_CODE_LBN 0 2267 #define MC_CMD_FC_OUT_DDR_TEST_POLL_CODE_WIDTH 8 2268 /* enum: Test not yet initiated */ 2269 #define MC_CMD_FC_OP_DDR_TEST_NONE 0x0 2270 /* enum: Test is in progress */ 2271 #define MC_CMD_FC_OP_DDR_TEST_INPROGRESS 0x1 2272 /* enum: Timed completed */ 2273 #define MC_CMD_FC_OP_DDR_TEST_SUCCESS 0x2 2274 /* enum: Test did not complete in specified time */ 2275 #define MC_CMD_FC_OP_DDR_TEST_TIMER_EXPIRED 0x3 2276 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T0_LBN 11 2277 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T0_WIDTH 1 2278 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T1_LBN 10 2279 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T1_WIDTH 1 2280 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B0_LBN 9 2281 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B0_WIDTH 1 2282 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B1_LBN 8 2283 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B1_WIDTH 1 2284 /* Test result from FPGA */ 2285 #define MC_CMD_FC_OUT_DDR_TEST_POLL_RESULT_OFST 4 2286 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T0_LBN 31 2287 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T0_WIDTH 1 2288 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T1_LBN 30 2289 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T1_WIDTH 1 2290 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B0_LBN 29 2291 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B0_WIDTH 1 2292 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B1_LBN 28 2293 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B1_WIDTH 1 2294 #define MC_CMD_FC_OUT_DDR_TEST_POLL_T0_LBN 15 2295 #define MC_CMD_FC_OUT_DDR_TEST_POLL_T0_WIDTH 5 2296 #define MC_CMD_FC_OUT_DDR_TEST_POLL_T1_LBN 10 2297 #define MC_CMD_FC_OUT_DDR_TEST_POLL_T1_WIDTH 5 2298 #define MC_CMD_FC_OUT_DDR_TEST_POLL_B0_LBN 5 2299 #define MC_CMD_FC_OUT_DDR_TEST_POLL_B0_WIDTH 5 2300 #define MC_CMD_FC_OUT_DDR_TEST_POLL_B1_LBN 0 2301 #define MC_CMD_FC_OUT_DDR_TEST_POLL_B1_WIDTH 5 2302 #define MC_CMD_FC_OUT_DDR_TEST_POLL_TEST_COMPLETE 0x0 /* enum */ 2303 #define MC_CMD_FC_OUT_DDR_TEST_POLL_TEST_FAIL 0x1 /* enum */ 2304 #define MC_CMD_FC_OUT_DDR_TEST_POLL_TEST_PASS 0x2 /* enum */ 2305 #define MC_CMD_FC_OUT_DDR_TEST_POLL_CAL_FAIL 0x3 /* enum */ 2306 #define MC_CMD_FC_OUT_DDR_TEST_POLL_CAL_SUCCESS 0x4 /* enum */ 2307 2308 /* MC_CMD_FC_OUT_DDR_TEST msgresponse */ 2309 #define MC_CMD_FC_OUT_DDR_TEST_LEN 0 2310 2311 /* MC_CMD_FC_OUT_GET_ASSERT msgresponse */ 2312 #define MC_CMD_FC_OUT_GET_ASSERT_LEN 144 2313 /* Assertion status flag. */ 2314 #define MC_CMD_FC_OUT_GET_ASSERT_GLOBAL_FLAGS_OFST 0 2315 #define MC_CMD_FC_OUT_GET_ASSERT_STATE_LBN 8 2316 #define MC_CMD_FC_OUT_GET_ASSERT_STATE_WIDTH 8 2317 /* enum: No crash data available */ 2318 #define MC_CMD_FC_GET_ASSERT_FLAGS_STATE_CLEAR 0x0 2319 /* enum: New crash data available */ 2320 #define MC_CMD_FC_GET_ASSERT_FLAGS_STATE_NEW 0x1 2321 /* enum: Crash data has been sent */ 2322 #define MC_CMD_FC_GET_ASSERT_FLAGS_STATE_NOTIFIED 0x2 2323 #define MC_CMD_FC_OUT_GET_ASSERT_TYPE_LBN 0 2324 #define MC_CMD_FC_OUT_GET_ASSERT_TYPE_WIDTH 8 2325 /* enum: No crash has been recorded. */ 2326 #define MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_NONE 0x0 2327 /* enum: Crash due to exception. */ 2328 #define MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_EXCEPTION 0x1 2329 /* enum: Crash due to assertion. */ 2330 #define MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_ASSERTION 0x2 2331 /* Failing PC value */ 2332 #define MC_CMD_FC_OUT_GET_ASSERT_SAVED_PC_OFFS_OFST 4 2333 /* Saved GP regs */ 2334 #define MC_CMD_FC_OUT_GET_ASSERT_GP_REGS_OFFS_OFST 8 2335 #define MC_CMD_FC_OUT_GET_ASSERT_GP_REGS_OFFS_LEN 4 2336 #define MC_CMD_FC_OUT_GET_ASSERT_GP_REGS_OFFS_NUM 31 2337 /* Exception Type */ 2338 #define MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_TYPE_OFFS_OFST 132 2339 /* Instruction at which exception occurred */ 2340 #define MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_PC_ADDR_OFFS_OFST 136 2341 /* BAD Address that triggered address-based exception */ 2342 #define MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_BAD_ADDR_OFFS_OFST 140 2343 2344 /* MC_CMD_FC_OUT_FPGA_BUILD msgresponse */ 2345 #define MC_CMD_FC_OUT_FPGA_BUILD_LEN 32 2346 #define MC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_INFO_OFST 0 2347 #define MC_CMD_FC_OUT_FPGA_BUILD_IS_APPLICATION_LBN 31 2348 #define MC_CMD_FC_OUT_FPGA_BUILD_IS_APPLICATION_WIDTH 1 2349 #define MC_CMD_FC_OUT_FPGA_BUILD_IS_LICENSED_LBN 30 2350 #define MC_CMD_FC_OUT_FPGA_BUILD_IS_LICENSED_WIDTH 1 2351 #define MC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_ID_LBN 16 2352 #define MC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_ID_WIDTH 14 2353 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MAJOR_LBN 12 2354 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MAJOR_WIDTH 4 2355 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MINOR_LBN 4 2356 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MINOR_WIDTH 8 2357 #define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_NUM_LBN 0 2358 #define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_NUM_WIDTH 4 2359 /* Build timestamp (seconds since epoch) */ 2360 #define MC_CMD_FC_OUT_FPGA_BUILD_TIMESTAMP_OFST 4 2361 #define MC_CMD_FC_OUT_FPGA_BUILD_PARAMETERS_OFST 8 2362 #define MC_CMD_FC_OUT_FPGA_BUILD_FPGA_TYPE_LBN 0 2363 #define MC_CMD_FC_OUT_FPGA_BUILD_FPGA_TYPE_WIDTH 8 2364 #define MC_CMD_FC_FPGA_TYPE_A7 0xa7 /* enum */ 2365 #define MC_CMD_FC_FPGA_TYPE_A5 0xa5 /* enum */ 2366 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED1_LBN 8 2367 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED1_WIDTH 10 2368 #define MC_CMD_FC_OUT_FPGA_BUILD_PTP_ENABLED_LBN 18 2369 #define MC_CMD_FC_OUT_FPGA_BUILD_PTP_ENABLED_WIDTH 1 2370 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM1_RLDRAM_DEF_LBN 19 2371 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM1_RLDRAM_DEF_WIDTH 1 2372 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM2_RLDRAM_DEF_LBN 20 2373 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM2_RLDRAM_DEF_WIDTH 1 2374 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM3_RLDRAM_DEF_LBN 21 2375 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM3_RLDRAM_DEF_WIDTH 1 2376 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM4_RLDRAM_DEF_LBN 22 2377 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM4_RLDRAM_DEF_WIDTH 1 2378 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T0_DDR3_DEF_LBN 23 2379 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T0_DDR3_DEF_WIDTH 1 2380 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_DDR3_DEF_LBN 24 2381 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_DDR3_DEF_WIDTH 1 2382 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B0_DDR3_DEF_LBN 25 2383 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B0_DDR3_DEF_WIDTH 1 2384 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B1_DDR3_DEF_LBN 26 2385 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B1_DDR3_DEF_WIDTH 1 2386 #define MC_CMD_FC_OUT_FPGA_BUILD_DDR3_ECC_ENABLED_LBN 27 2387 #define MC_CMD_FC_OUT_FPGA_BUILD_DDR3_ECC_ENABLED_WIDTH 1 2388 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_QDR_DEF_LBN 28 2389 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_QDR_DEF_WIDTH 1 2390 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED2_LBN 29 2391 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED2_WIDTH 2 2392 #define MC_CMD_FC_OUT_FPGA_BUILD_CRC_APPEND_LBN 31 2393 #define MC_CMD_FC_OUT_FPGA_BUILD_CRC_APPEND_WIDTH 1 2394 #define MC_CMD_FC_OUT_FPGA_BUILD_IDENTIFIER_OFST 12 2395 #define MC_CMD_FC_OUT_FPGA_BUILD_CHANGESET_LBN 0 2396 #define MC_CMD_FC_OUT_FPGA_BUILD_CHANGESET_WIDTH 16 2397 #define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_FLAG_LBN 16 2398 #define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_FLAG_WIDTH 1 2399 #define MC_CMD_FC_FPGA_BUILD_FLAG_INTERNAL 0x0 /* enum */ 2400 #define MC_CMD_FC_FPGA_BUILD_FLAG_RELEASE 0x1 /* enum */ 2401 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED3_LBN 17 2402 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED3_WIDTH 15 2403 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_HI_OFST 16 2404 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MINOR_LBN 0 2405 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MINOR_WIDTH 16 2406 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MAJOR_LBN 16 2407 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MAJOR_WIDTH 16 2408 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_LO_OFST 20 2409 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_BUILD_LBN 0 2410 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_BUILD_WIDTH 16 2411 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MICRO_LBN 16 2412 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MICRO_WIDTH 16 2413 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_OFST 16 2414 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_LEN 8 2415 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_LO_OFST 16 2416 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_HI_OFST 20 2417 #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_LO_OFST 24 2418 #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HI_OFST 28 2419 #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HIGH_LBN 0 2420 #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HIGH_WIDTH 16 2421 2422 /* MC_CMD_FC_OUT_FPGA_BUILD_V2 msgresponse */ 2423 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_LEN 32 2424 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_INFO_OFST 0 2425 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_APPLICATION_LBN 31 2426 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_APPLICATION_WIDTH 1 2427 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_LICENSED_LBN 30 2428 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_LICENSED_WIDTH 1 2429 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_ID_LBN 16 2430 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_ID_WIDTH 14 2431 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MAJOR_LBN 12 2432 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MAJOR_WIDTH 4 2433 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MINOR_LBN 4 2434 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MINOR_WIDTH 8 2435 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_NUM_LBN 0 2436 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_NUM_WIDTH 4 2437 /* Build timestamp (seconds since epoch) */ 2438 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_TIMESTAMP_OFST 4 2439 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_PARAMETERS_OFST 8 2440 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_PMA_PASSTHROUGH_LBN 31 2441 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_PMA_PASSTHROUGH_WIDTH 1 2442 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_QDR_DEF_LBN 29 2443 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_QDR_DEF_WIDTH 1 2444 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_QDR_DEF_LBN 28 2445 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_QDR_DEF_WIDTH 1 2446 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DDR3_ECC_ENABLED_LBN 27 2447 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DDR3_ECC_ENABLED_WIDTH 1 2448 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_DDR3_DEF_LBN 26 2449 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_DDR3_DEF_WIDTH 1 2450 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_DDR3_DEF_LBN 25 2451 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_DDR3_DEF_WIDTH 1 2452 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_TO_DDR3_DEF_LBN 24 2453 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_TO_DDR3_DEF_WIDTH 1 2454 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_T0_DDR3_DEF_LBN 23 2455 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_T0_DDR3_DEF_WIDTH 1 2456 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_RLDRAM_DEF_LBN 22 2457 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_RLDRAM_DEF_WIDTH 1 2458 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_RLDRAM_DEF_LBN 21 2459 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_RLDRAM_DEF_WIDTH 1 2460 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_RLDRAM_DEF_LBN 20 2461 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_RLDRAM_DEF_WIDTH 1 2462 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_RLDRAM_DEF_LBN 19 2463 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_RLDRAM_DEF_WIDTH 1 2464 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_LBN 18 2465 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_WIDTH 1 2466 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_10G 0x0 /* enum */ 2467 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_40G 0x1 /* enum */ 2468 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_LBN 17 2469 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_WIDTH 1 2470 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_10G 0x0 /* enum */ 2471 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_40G 0x1 /* enum */ 2472 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_LBN 16 2473 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_WIDTH 1 2474 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_10G 0x0 /* enum */ 2475 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_40G 0x1 /* enum */ 2476 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP7_DEF_LBN 15 2477 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP7_DEF_WIDTH 1 2478 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP6_DEF_LBN 14 2479 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP6_DEF_WIDTH 1 2480 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP5_DEF_LBN 13 2481 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP5_DEF_WIDTH 1 2482 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_DEF_LBN 12 2483 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_DEF_WIDTH 1 2484 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP3_DEF_LBN 11 2485 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP3_DEF_WIDTH 1 2486 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP2_DEF_LBN 10 2487 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP2_DEF_WIDTH 1 2488 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP1_DEF_LBN 9 2489 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP1_DEF_WIDTH 1 2490 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_DEF_LBN 8 2491 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_DEF_WIDTH 1 2492 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC3_DEF_LBN 7 2493 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC3_DEF_WIDTH 1 2494 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC2_DEF_LBN 6 2495 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC2_DEF_WIDTH 1 2496 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC1_DEF_LBN 5 2497 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC1_DEF_WIDTH 1 2498 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_DEF_LBN 4 2499 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_DEF_WIDTH 1 2500 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_FPGA_TYPE_LBN 0 2501 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_FPGA_TYPE_WIDTH 4 2502 #define MC_CMD_FC_FPGA_V2_TYPE_A3 0x0 /* enum */ 2503 #define MC_CMD_FC_FPGA_V2_TYPE_A4 0x1 /* enum */ 2504 #define MC_CMD_FC_FPGA_V2_TYPE_A5 0x2 /* enum */ 2505 #define MC_CMD_FC_FPGA_V2_TYPE_A7 0x3 /* enum */ 2506 #define MC_CMD_FC_FPGA_V2_TYPE_D3 0x8 /* enum */ 2507 #define MC_CMD_FC_FPGA_V2_TYPE_D4 0x9 /* enum */ 2508 #define MC_CMD_FC_FPGA_V2_TYPE_D5 0xa /* enum */ 2509 #define MC_CMD_FC_FPGA_V2_TYPE_D7 0xb /* enum */ 2510 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_IDENTIFIER_OFST 12 2511 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_CHANGESET_LBN 0 2512 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_CHANGESET_WIDTH 16 2513 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_FLAG_LBN 16 2514 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_FLAG_WIDTH 1 2515 /* MC_CMD_FC_FPGA_BUILD_FLAG_INTERNAL 0x0 */ 2516 /* MC_CMD_FC_FPGA_BUILD_FLAG_RELEASE 0x1 */ 2517 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_HI_OFST 16 2518 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MINOR_LBN 0 2519 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MINOR_WIDTH 16 2520 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MAJOR_LBN 16 2521 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MAJOR_WIDTH 16 2522 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_LO_OFST 20 2523 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_BUILD_LBN 0 2524 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_BUILD_WIDTH 16 2525 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MICRO_LBN 16 2526 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MICRO_WIDTH 16 2527 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_LO_OFST 24 2528 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HI_OFST 28 2529 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HIGH_LBN 0 2530 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HIGH_WIDTH 16 2531 2532 /* MC_CMD_FC_OUT_FPGA_SERVICES msgresponse */ 2533 #define MC_CMD_FC_OUT_FPGA_SERVICES_LEN 32 2534 #define MC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_INFO_OFST 0 2535 #define MC_CMD_FC_OUT_FPGA_SERVICES_IS_APPLICATION_LBN 31 2536 #define MC_CMD_FC_OUT_FPGA_SERVICES_IS_APPLICATION_WIDTH 1 2537 #define MC_CMD_FC_OUT_FPGA_SERVICES_IS_LICENSED_LBN 30 2538 #define MC_CMD_FC_OUT_FPGA_SERVICES_IS_LICENSED_WIDTH 1 2539 #define MC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_ID_LBN 16 2540 #define MC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_ID_WIDTH 14 2541 #define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MAJOR_LBN 12 2542 #define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MAJOR_WIDTH 4 2543 #define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MINOR_LBN 4 2544 #define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MINOR_WIDTH 8 2545 #define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_NUM_LBN 0 2546 #define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_NUM_WIDTH 4 2547 /* Build timestamp (seconds since epoch) */ 2548 #define MC_CMD_FC_OUT_FPGA_SERVICES_TIMESTAMP_OFST 4 2549 #define MC_CMD_FC_OUT_FPGA_SERVICES_PARAMETERS_OFST 8 2550 #define MC_CMD_FC_OUT_FPGA_SERVICES_FC_FLASH_BOOTED_LBN 8 2551 #define MC_CMD_FC_OUT_FPGA_SERVICES_FC_FLASH_BOOTED_WIDTH 1 2552 #define MC_CMD_FC_OUT_FPGA_SERVICES_NIC0_DEF_LBN 27 2553 #define MC_CMD_FC_OUT_FPGA_SERVICES_NIC0_DEF_WIDTH 1 2554 #define MC_CMD_FC_OUT_FPGA_SERVICES_NIC1_DEF_LBN 28 2555 #define MC_CMD_FC_OUT_FPGA_SERVICES_NIC1_DEF_WIDTH 1 2556 #define MC_CMD_FC_OUT_FPGA_SERVICES_SFP0_DEF_LBN 29 2557 #define MC_CMD_FC_OUT_FPGA_SERVICES_SFP0_DEF_WIDTH 1 2558 #define MC_CMD_FC_OUT_FPGA_SERVICES_SFP1_DEF_LBN 30 2559 #define MC_CMD_FC_OUT_FPGA_SERVICES_SFP1_DEF_WIDTH 1 2560 #define MC_CMD_FC_OUT_FPGA_SERVICES_RESERVED_LBN 31 2561 #define MC_CMD_FC_OUT_FPGA_SERVICES_RESERVED_WIDTH 1 2562 #define MC_CMD_FC_OUT_FPGA_SERVICES_IDENTIFIER_OFST 12 2563 #define MC_CMD_FC_OUT_FPGA_SERVICES_CHANGESET_LBN 0 2564 #define MC_CMD_FC_OUT_FPGA_SERVICES_CHANGESET_WIDTH 16 2565 #define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_FLAG_LBN 16 2566 #define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_FLAG_WIDTH 1 2567 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_OFST 16 2568 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_WIDTH_LBN 0 2569 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_WIDTH_WIDTH 16 2570 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_COUNT_LBN 16 2571 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_COUNT_WIDTH 16 2572 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_OFST 20 2573 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_WIDTH_LBN 0 2574 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_WIDTH_WIDTH 16 2575 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_COUNT_LBN 16 2576 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_COUNT_WIDTH 16 2577 #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_LO_OFST 24 2578 #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HI_OFST 28 2579 #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HIGH_LBN 0 2580 #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HIGH_WIDTH 16 2581 2582 /* MC_CMD_FC_OUT_FPGA_SERVICES_V2 msgresponse */ 2583 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_LEN 32 2584 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_INFO_OFST 0 2585 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_APPLICATION_LBN 31 2586 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_APPLICATION_WIDTH 1 2587 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_LICENSED_LBN 30 2588 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_LICENSED_WIDTH 1 2589 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_ID_LBN 16 2590 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_ID_WIDTH 14 2591 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MAJOR_LBN 12 2592 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MAJOR_WIDTH 4 2593 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MINOR_LBN 4 2594 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MINOR_WIDTH 8 2595 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_NUM_LBN 0 2596 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_NUM_WIDTH 4 2597 /* Build timestamp (seconds since epoch) */ 2598 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_TIMESTAMP_OFST 4 2599 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_PARAMETERS_OFST 8 2600 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_PTP_ENABLED_LBN 0 2601 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_PTP_ENABLED_WIDTH 1 2602 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_FC_FLASH_BOOTED_LBN 8 2603 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_FC_FLASH_BOOTED_WIDTH 1 2604 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IDENTIFIER_OFST 12 2605 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_CHANGESET_LBN 0 2606 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_CHANGESET_WIDTH 16 2607 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_FLAG_LBN 16 2608 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_FLAG_WIDTH 1 2609 /* MC_CMD_FC_FPGA_BUILD_FLAG_INTERNAL 0x0 */ 2610 /* MC_CMD_FC_FPGA_BUILD_FLAG_RELEASE 0x1 */ 2611 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_LO_OFST 24 2612 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HI_OFST 28 2613 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HIGH_LBN 0 2614 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HIGH_WIDTH 16 2615 2616 /* MC_CMD_FC_OUT_BSP_VERSION msgresponse */ 2617 #define MC_CMD_FC_OUT_BSP_VERSION_LEN 4 2618 /* Qsys system ID */ 2619 #define MC_CMD_FC_OUT_BSP_VERSION_SYSID_OFST 0 2620 #define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MAJOR_LBN 12 2621 #define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MAJOR_WIDTH 4 2622 #define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MINOR_LBN 4 2623 #define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MINOR_WIDTH 8 2624 #define MC_CMD_FC_OUT_BSP_VERSION_BUILD_NUM_LBN 0 2625 #define MC_CMD_FC_OUT_BSP_VERSION_BUILD_NUM_WIDTH 4 2626 2627 /* MC_CMD_FC_OUT_READ_MAP_COUNT msgresponse */ 2628 #define MC_CMD_FC_OUT_READ_MAP_COUNT_LEN 4 2629 /* Number of maps */ 2630 #define MC_CMD_FC_OUT_READ_MAP_COUNT_NUM_MAPS_OFST 0 2631 2632 /* MC_CMD_FC_OUT_READ_MAP_INDEX msgresponse */ 2633 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN 164 2634 /* Index of the map */ 2635 #define MC_CMD_FC_OUT_READ_MAP_INDEX_INDEX_OFST 0 2636 /* Options for the map */ 2637 #define MC_CMD_FC_OUT_READ_MAP_INDEX_OPTIONS_OFST 4 2638 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_8 0x0 /* enum */ 2639 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_16 0x1 /* enum */ 2640 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_32 0x2 /* enum */ 2641 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_64 0x3 /* enum */ 2642 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_MASK 0x3 /* enum */ 2643 #define MC_CMD_FC_OUT_READ_MAP_INDEX_PATH_FC 0x4 /* enum */ 2644 #define MC_CMD_FC_OUT_READ_MAP_INDEX_PATH_MEM 0x8 /* enum */ 2645 #define MC_CMD_FC_OUT_READ_MAP_INDEX_PERM_READ 0x10 /* enum */ 2646 #define MC_CMD_FC_OUT_READ_MAP_INDEX_PERM_WRITE 0x20 /* enum */ 2647 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_FREE 0x0 /* enum */ 2648 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_LICENSED 0x40 /* enum */ 2649 /* Address of start of map */ 2650 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_OFST 8 2651 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_LEN 8 2652 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_LO_OFST 8 2653 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_HI_OFST 12 2654 /* Length of address map */ 2655 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_OFST 16 2656 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_LEN 8 2657 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_LO_OFST 16 2658 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_HI_OFST 20 2659 /* Component information field */ 2660 #define MC_CMD_FC_OUT_READ_MAP_INDEX_COMP_INFO_OFST 24 2661 /* License expiry data for map */ 2662 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_OFST 28 2663 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_LEN 8 2664 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_LO_OFST 28 2665 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_HI_OFST 32 2666 /* Name of the component */ 2667 #define MC_CMD_FC_OUT_READ_MAP_INDEX_NAME_OFST 36 2668 #define MC_CMD_FC_OUT_READ_MAP_INDEX_NAME_LEN 1 2669 #define MC_CMD_FC_OUT_READ_MAP_INDEX_NAME_NUM 128 2670 2671 /* MC_CMD_FC_OUT_READ_MAP msgresponse */ 2672 #define MC_CMD_FC_OUT_READ_MAP_LEN 0 2673 2674 /* MC_CMD_FC_OUT_CAPABILITIES msgresponse */ 2675 #define MC_CMD_FC_OUT_CAPABILITIES_LEN 8 2676 /* Number of internal ports */ 2677 #define MC_CMD_FC_OUT_CAPABILITIES_INTERNAL_OFST 0 2678 /* Number of external ports */ 2679 #define MC_CMD_FC_OUT_CAPABILITIES_EXTERNAL_OFST 4 2680 2681 /* MC_CMD_FC_OUT_GLOBAL_FLAGS msgresponse */ 2682 #define MC_CMD_FC_OUT_GLOBAL_FLAGS_LEN 4 2683 #define MC_CMD_FC_OUT_GLOBAL_FLAGS_FLAGS_OFST 0 2684 2685 /* MC_CMD_FC_OUT_IO_REL msgresponse */ 2686 #define MC_CMD_FC_OUT_IO_REL_LEN 0 2687 2688 /* MC_CMD_FC_OUT_IO_REL_GET_ADDR msgresponse */ 2689 #define MC_CMD_FC_OUT_IO_REL_GET_ADDR_LEN 8 2690 #define MC_CMD_FC_OUT_IO_REL_GET_ADDR_ADDR_HI_OFST 0 2691 #define MC_CMD_FC_OUT_IO_REL_GET_ADDR_ADDR_LO_OFST 4 2692 2693 /* MC_CMD_FC_OUT_IO_REL_READ32 msgresponse */ 2694 #define MC_CMD_FC_OUT_IO_REL_READ32_LENMIN 4 2695 #define MC_CMD_FC_OUT_IO_REL_READ32_LENMAX 252 2696 #define MC_CMD_FC_OUT_IO_REL_READ32_LEN(num) (0+4*(num)) 2697 #define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_OFST 0 2698 #define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_LEN 4 2699 #define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_MINNUM 1 2700 #define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_MAXNUM 63 2701 2702 /* MC_CMD_FC_OUT_IO_REL_WRITE32 msgresponse */ 2703 #define MC_CMD_FC_OUT_IO_REL_WRITE32_LEN 0 2704 2705 /* MC_CMD_FC_OUT_UHLINK_PHY msgresponse */ 2706 #define MC_CMD_FC_OUT_UHLINK_PHY_LEN 48 2707 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_SETTINGS_0_OFST 0 2708 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_VOD_LBN 0 2709 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_VOD_WIDTH 16 2710 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_1STPOSTTAP_LBN 16 2711 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_1STPOSTTAP_WIDTH 16 2712 /* Transceiver Transmit settings */ 2713 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_SETTINGS_1_OFST 4 2714 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_PRETAP_LBN 0 2715 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_PRETAP_WIDTH 16 2716 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_2NDPOSTTAP_LBN 16 2717 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_2NDPOSTTAP_WIDTH 16 2718 /* Transceiver Receive settings */ 2719 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_SETTINGS_OFST 8 2720 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_DC_GAIN_LBN 0 2721 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_DC_GAIN_WIDTH 16 2722 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_EQ_CONTROL_LBN 16 2723 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_EQ_CONTROL_WIDTH 16 2724 /* Rx eye opening */ 2725 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_OFST 12 2726 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_WIDTH_LBN 0 2727 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_WIDTH_WIDTH 16 2728 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_HEIGHT_LBN 16 2729 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_HEIGHT_WIDTH 16 2730 /* PCS status word */ 2731 #define MC_CMD_FC_OUT_UHLINK_PHY_PCS_STATUS_OFST 16 2732 /* Link status word */ 2733 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_WORD_OFST 20 2734 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_LBN 0 2735 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_WIDTH 1 2736 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_CONFIGURED_LBN 1 2737 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_CONFIGURED_WIDTH 1 2738 /* Current SFp parameters applied */ 2739 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_PARAMS_OFST 24 2740 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_PARAMS_LEN 20 2741 /* Link speed is 100, 1000, 10000 */ 2742 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_SPEED_OFST 24 2743 /* Length of copper cable - zero when not relevant */ 2744 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_COPPER_LEN_OFST 28 2745 /* True if a dual speed SFP+ module */ 2746 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_DUAL_SPEED_OFST 32 2747 /* True if an SFP Module is present (other fields valid when true) */ 2748 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_PRESENT_OFST 36 2749 /* The type of the SFP+ Module */ 2750 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_TYPE_OFST 40 2751 /* PHY config flags */ 2752 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_OFST 44 2753 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_DFE_LBN 0 2754 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_DFE_WIDTH 1 2755 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_AEQ_LBN 1 2756 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_AEQ_WIDTH 1 2757 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_RX_TUNING_LBN 2 2758 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_RX_TUNING_WIDTH 1 2759 2760 /* MC_CMD_FC_OUT_UHLINK_MAC msgresponse */ 2761 #define MC_CMD_FC_OUT_UHLINK_MAC_LEN 20 2762 /* MAC configuration applied */ 2763 #define MC_CMD_FC_OUT_UHLINK_MAC_CONFIG_OFST 0 2764 /* MTU size */ 2765 #define MC_CMD_FC_OUT_UHLINK_MAC_MTU_OFST 4 2766 /* IF Mode status */ 2767 #define MC_CMD_FC_OUT_UHLINK_MAC_IF_STATUS_OFST 8 2768 /* MAC address configured */ 2769 #define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_OFST 12 2770 #define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_LEN 8 2771 #define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_LO_OFST 12 2772 #define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_HI_OFST 16 2773 2774 /* MC_CMD_FC_OUT_UHLINK_RX_EYE msgresponse */ 2775 #define MC_CMD_FC_OUT_UHLINK_RX_EYE_LEN ((((0-1+(32*MC_CMD_FC_UHLINK_RX_EYE_PER_BLOCK))+1))>>3) 2776 /* Rx Eye measurements */ 2777 #define MC_CMD_FC_OUT_UHLINK_RX_EYE_RX_EYE_OFST 0 2778 #define MC_CMD_FC_OUT_UHLINK_RX_EYE_RX_EYE_LEN 4 2779 #define MC_CMD_FC_OUT_UHLINK_RX_EYE_RX_EYE_NUM MC_CMD_FC_UHLINK_RX_EYE_PER_BLOCK 2780 2781 /* MC_CMD_FC_OUT_UHLINK_DUMP_RX_EYE_PLOT msgresponse */ 2782 #define MC_CMD_FC_OUT_UHLINK_DUMP_RX_EYE_PLOT_LEN 0 2783 2784 /* MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT msgresponse */ 2785 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_LEN ((((32-1+(64*MC_CMD_FC_UHLINK_RX_EYE_PLOT_ROWS_PER_BLOCK))+1))>>3) 2786 /* Has the eye plot dump completed and data returned is valid? */ 2787 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_VALID_OFST 0 2788 /* Rx Eye binary plot */ 2789 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_OFST 4 2790 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_LEN 8 2791 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_LO_OFST 4 2792 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_HI_OFST 8 2793 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_NUM MC_CMD_FC_UHLINK_RX_EYE_PLOT_ROWS_PER_BLOCK 2794 2795 /* MC_CMD_FC_OUT_UHLINK_RX_TUNE msgresponse */ 2796 #define MC_CMD_FC_OUT_UHLINK_RX_TUNE_LEN 0 2797 2798 /* MC_CMD_FC_OUT_UHLINK_LOOPBACK_SET msgresponse */ 2799 #define MC_CMD_FC_OUT_UHLINK_LOOPBACK_SET_LEN 0 2800 2801 /* MC_CMD_FC_OUT_UHLINK_LOOPBACK_GET msgresponse */ 2802 #define MC_CMD_FC_OUT_UHLINK_LOOPBACK_GET_LEN 4 2803 #define MC_CMD_FC_OUT_UHLINK_LOOPBACK_GET_STATE_OFST 0 2804 2805 /* MC_CMD_FC_OUT_UHLINK msgresponse */ 2806 #define MC_CMD_FC_OUT_UHLINK_LEN 0 2807 2808 /* MC_CMD_FC_OUT_SET_LINK msgresponse */ 2809 #define MC_CMD_FC_OUT_SET_LINK_LEN 0 2810 2811 /* MC_CMD_FC_OUT_LICENSE msgresponse */ 2812 #define MC_CMD_FC_OUT_LICENSE_LEN 12 2813 /* Count of valid keys */ 2814 #define MC_CMD_FC_OUT_LICENSE_VALID_KEYS_OFST 0 2815 /* Count of invalid keys */ 2816 #define MC_CMD_FC_OUT_LICENSE_INVALID_KEYS_OFST 4 2817 /* Count of blacklisted keys */ 2818 #define MC_CMD_FC_OUT_LICENSE_BLACKLISTED_KEYS_OFST 8 2819 2820 /* MC_CMD_FC_OUT_STARTUP msgresponse */ 2821 #define MC_CMD_FC_OUT_STARTUP_LEN 4 2822 /* Capabilities of the FPGA/FC */ 2823 #define MC_CMD_FC_OUT_STARTUP_CAPABILITIES_OFST 0 2824 #define MC_CMD_FC_OUT_STARTUP_CAN_ACCESS_FLASH_LBN 0 2825 #define MC_CMD_FC_OUT_STARTUP_CAN_ACCESS_FLASH_WIDTH 1 2826 2827 /* MC_CMD_FC_OUT_DMA_READ msgresponse */ 2828 #define MC_CMD_FC_OUT_DMA_READ_LENMIN 1 2829 #define MC_CMD_FC_OUT_DMA_READ_LENMAX 252 2830 #define MC_CMD_FC_OUT_DMA_READ_LEN(num) (0+1*(num)) 2831 /* The data read */ 2832 #define MC_CMD_FC_OUT_DMA_READ_DATA_OFST 0 2833 #define MC_CMD_FC_OUT_DMA_READ_DATA_LEN 1 2834 #define MC_CMD_FC_OUT_DMA_READ_DATA_MINNUM 1 2835 #define MC_CMD_FC_OUT_DMA_READ_DATA_MAXNUM 252 2836 2837 /* MC_CMD_FC_OUT_TIMED_READ_SET msgresponse */ 2838 #define MC_CMD_FC_OUT_TIMED_READ_SET_LEN 4 2839 /* Timer handle */ 2840 #define MC_CMD_FC_OUT_TIMED_READ_SET_FC_HANDLE_OFST 0 2841 2842 /* MC_CMD_FC_OUT_TIMED_READ_GET msgresponse */ 2843 #define MC_CMD_FC_OUT_TIMED_READ_GET_LEN 52 2844 /* Host supplied handle (unique) */ 2845 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_HANDLE_OFST 0 2846 /* Address into which to transfer data in host */ 2847 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_OFST 4 2848 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_LEN 8 2849 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_LO_OFST 4 2850 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_HI_OFST 8 2851 /* AOE address from which to transfer data */ 2852 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_OFST 12 2853 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_LEN 8 2854 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_LO_OFST 12 2855 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_HI_OFST 16 2856 /* Length of AOE transfer (total) */ 2857 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_LENGTH_OFST 20 2858 /* Length of host transfer (total) */ 2859 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_LENGTH_OFST 24 2860 /* See FLAGS entry for MC_CMD_FC_IN_TIMED_READ_SET */ 2861 #define MC_CMD_FC_OUT_TIMED_READ_GET_FLAGS_OFST 28 2862 #define MC_CMD_FC_OUT_TIMED_READ_GET_PERIOD_OFST 32 2863 /* When active, start read time */ 2864 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_OFST 36 2865 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_LEN 8 2866 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_LO_OFST 36 2867 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_HI_OFST 40 2868 /* When active, end read time */ 2869 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_OFST 44 2870 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_LEN 8 2871 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_LO_OFST 44 2872 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_HI_OFST 48 2873 2874 /* MC_CMD_FC_OUT_LOG_ADDR_RANGE msgresponse */ 2875 #define MC_CMD_FC_OUT_LOG_ADDR_RANGE_LEN 0 2876 2877 /* MC_CMD_FC_OUT_LOG msgresponse */ 2878 #define MC_CMD_FC_OUT_LOG_LEN 0 2879 2880 /* MC_CMD_FC_OUT_CLOCK_GET_TIME msgresponse */ 2881 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_LEN 24 2882 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_CLOCK_ID_OFST 0 2883 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_OFST 4 2884 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_LEN 8 2885 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_LO_OFST 4 2886 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_HI_OFST 8 2887 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_NANOSECONDS_OFST 12 2888 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_RANGE_OFST 16 2889 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_PRECISION_OFST 20 2890 2891 /* MC_CMD_FC_OUT_CLOCK_SET_TIME msgresponse */ 2892 #define MC_CMD_FC_OUT_CLOCK_SET_TIME_LEN 0 2893 2894 /* MC_CMD_FC_OUT_DDR_SET_SPD msgresponse */ 2895 #define MC_CMD_FC_OUT_DDR_SET_SPD_LEN 0 2896 2897 /* MC_CMD_FC_OUT_DDR_SET_INFO msgresponse */ 2898 #define MC_CMD_FC_OUT_DDR_SET_INFO_LEN 0 2899 2900 /* MC_CMD_FC_OUT_DDR_GET_STATUS msgresponse */ 2901 #define MC_CMD_FC_OUT_DDR_GET_STATUS_LEN 4 2902 #define MC_CMD_FC_OUT_DDR_GET_STATUS_FLAGS_OFST 0 2903 #define MC_CMD_FC_OUT_DDR_GET_STATUS_READY_LBN 0 2904 #define MC_CMD_FC_OUT_DDR_GET_STATUS_READY_WIDTH 1 2905 #define MC_CMD_FC_OUT_DDR_GET_STATUS_CALIBRATED_LBN 1 2906 #define MC_CMD_FC_OUT_DDR_GET_STATUS_CALIBRATED_WIDTH 1 2907 2908 /* MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT msgresponse */ 2909 #define MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_LEN 8 2910 #define MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_SECONDS_OFST 0 2911 #define MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_NANOSECONDS_OFST 4 2912 2913 /* MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT msgresponse */ 2914 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LENMIN 8 2915 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LENMAX 248 2916 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LEN(num) (0+8*(num)) 2917 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_SECONDS_OFST 0 2918 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_NANOSECONDS_OFST 4 2919 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_OFST 0 2920 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_LEN 8 2921 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_LO_OFST 0 2922 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_HI_OFST 4 2923 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_MINNUM 0 2924 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_MAXNUM 31 2925 2926 /* MC_CMD_FC_OUT_SPI_READ msgresponse */ 2927 #define MC_CMD_FC_OUT_SPI_READ_LENMIN 4 2928 #define MC_CMD_FC_OUT_SPI_READ_LENMAX 252 2929 #define MC_CMD_FC_OUT_SPI_READ_LEN(num) (0+4*(num)) 2930 #define MC_CMD_FC_OUT_SPI_READ_BUFFER_OFST 0 2931 #define MC_CMD_FC_OUT_SPI_READ_BUFFER_LEN 4 2932 #define MC_CMD_FC_OUT_SPI_READ_BUFFER_MINNUM 1 2933 #define MC_CMD_FC_OUT_SPI_READ_BUFFER_MAXNUM 63 2934 2935 /* MC_CMD_FC_OUT_SPI_WRITE msgresponse */ 2936 #define MC_CMD_FC_OUT_SPI_WRITE_LEN 0 2937 2938 /* MC_CMD_FC_OUT_SPI_ERASE msgresponse */ 2939 #define MC_CMD_FC_OUT_SPI_ERASE_LEN 0 2940 2941 /* MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG msgresponse */ 2942 #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_LEN 8 2943 /* The 32-bit value read from the toggle count register */ 2944 #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_TOGGLE_COUNT_OFST 0 2945 /* The 32-bit value read from the clock enable count register */ 2946 #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_CLKEN_COUNT_OFST 4 2947 2948 /* MC_CMD_FC_OUT_DIAG_POWER_NOISE_WRITE_CONFIG msgresponse */ 2949 #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_WRITE_CONFIG_LEN 0 2950 2951 /* MC_CMD_FC_OUT_DIAG_DDR_SOAK_START msgresponse */ 2952 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_START_LEN 0 2953 2954 /* MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT msgresponse */ 2955 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_LEN 8 2956 /* DDR soak test status word; bits [4:0] are relevant. */ 2957 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_STATUS_OFST 0 2958 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PASSED_LBN 0 2959 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PASSED_WIDTH 1 2960 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_FAILED_LBN 1 2961 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_FAILED_WIDTH 1 2962 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_COMPLETED_LBN 2 2963 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_COMPLETED_WIDTH 1 2964 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_TIMEOUT_LBN 3 2965 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_TIMEOUT_WIDTH 1 2966 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PNF_LBN 4 2967 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PNF_WIDTH 1 2968 /* DDR soak test error count */ 2969 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_ERR_COUNT_OFST 4 2970 2971 /* MC_CMD_FC_OUT_DIAG_DDR_SOAK_STOP msgresponse */ 2972 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_STOP_LEN 0 2973 2974 /* MC_CMD_FC_OUT_DIAG_DDR_SOAK_ERROR msgresponse */ 2975 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_ERROR_LEN 0 2976 2977 /* MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_SET_MODE msgresponse */ 2978 #define MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_SET_MODE_LEN 0 2979 2980 /* MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_RAW_CONFIG msgresponse */ 2981 #define MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_RAW_CONFIG_LEN 0 2982 2983 2984 /***********************************/ 2985 /* MC_CMD_AOE 2986 * AOE operations on MC 2987 */ 2988 #define MC_CMD_AOE 0xa 2989 2990 /* MC_CMD_AOE_IN msgrequest */ 2991 #define MC_CMD_AOE_IN_LEN 4 2992 #define MC_CMD_AOE_IN_OP_HDR_OFST 0 2993 #define MC_CMD_AOE_IN_OP_LBN 0 2994 #define MC_CMD_AOE_IN_OP_WIDTH 8 2995 /* enum: FPGA and CPLD information */ 2996 #define MC_CMD_AOE_OP_INFO 0x1 2997 /* enum: Currents and voltages read from MCP3424s; DEBUG */ 2998 #define MC_CMD_AOE_OP_CURRENTS 0x2 2999 /* enum: Temperatures at locations around the PCB; DEBUG */ 3000 #define MC_CMD_AOE_OP_TEMPERATURES 0x3 3001 /* enum: Set CPLD to idle */ 3002 #define MC_CMD_AOE_OP_CPLD_IDLE 0x4 3003 /* enum: Read from CPLD register */ 3004 #define MC_CMD_AOE_OP_CPLD_READ 0x5 3005 /* enum: Write to CPLD register */ 3006 #define MC_CMD_AOE_OP_CPLD_WRITE 0x6 3007 /* enum: Execute CPLD instruction */ 3008 #define MC_CMD_AOE_OP_CPLD_INSTRUCTION 0x7 3009 /* enum: Reprogram the CPLD on the AOE device */ 3010 #define MC_CMD_AOE_OP_CPLD_REPROGRAM 0x8 3011 /* enum: AOE power control */ 3012 #define MC_CMD_AOE_OP_POWER 0x9 3013 /* enum: AOE image loading */ 3014 #define MC_CMD_AOE_OP_LOAD 0xa 3015 /* enum: Fan monitoring */ 3016 #define MC_CMD_AOE_OP_FAN_CONTROL 0xb 3017 /* enum: Fan failures since last reset */ 3018 #define MC_CMD_AOE_OP_FAN_FAILURES 0xc 3019 /* enum: Get generic AOE MAC statistics */ 3020 #define MC_CMD_AOE_OP_MAC_STATS 0xd 3021 /* enum: Retrieve PHY specific information */ 3022 #define MC_CMD_AOE_OP_GET_PHY_MEDIA_INFO 0xe 3023 /* enum: Write a number of JTAG primitive commands, return will give data */ 3024 #define MC_CMD_AOE_OP_JTAG_WRITE 0xf 3025 /* enum: Control access to the FPGA via the Siena JTAG Chain */ 3026 #define MC_CMD_AOE_OP_FPGA_ACCESS 0x10 3027 /* enum: Set the MTU offset between Siena and AOE MACs */ 3028 #define MC_CMD_AOE_OP_SET_MTU_OFFSET 0x11 3029 /* enum: How link state is handled */ 3030 #define MC_CMD_AOE_OP_LINK_STATE 0x12 3031 /* enum: How Siena MAC statistics are reported (deprecated - use 3032 * MC_CMD_AOE_OP_ASIC_STATS) 3033 */ 3034 #define MC_CMD_AOE_OP_SIENA_STATS 0x13 3035 /* enum: How native ASIC MAC statistics are reported - replaces the deprecated 3036 * command MC_CMD_AOE_OP_SIENA_STATS 3037 */ 3038 #define MC_CMD_AOE_OP_ASIC_STATS 0x13 3039 /* enum: DDR memory information */ 3040 #define MC_CMD_AOE_OP_DDR 0x14 3041 /* enum: FC control */ 3042 #define MC_CMD_AOE_OP_FC 0x15 3043 /* enum: DDR ECC status reads */ 3044 #define MC_CMD_AOE_OP_DDR_ECC_STATUS 0x16 3045 /* enum: Commands for MC-SPI Master emulation */ 3046 #define MC_CMD_AOE_OP_MC_SPI_MASTER 0x17 3047 /* enum: Commands for FC boot control */ 3048 #define MC_CMD_AOE_OP_FC_BOOT 0x18 3049 3050 /* MC_CMD_AOE_OUT msgresponse */ 3051 #define MC_CMD_AOE_OUT_LEN 0 3052 3053 /* MC_CMD_AOE_IN_INFO msgrequest */ 3054 #define MC_CMD_AOE_IN_INFO_LEN 4 3055 #define MC_CMD_AOE_IN_CMD_OFST 0 3056 3057 /* MC_CMD_AOE_IN_CURRENTS msgrequest */ 3058 #define MC_CMD_AOE_IN_CURRENTS_LEN 4 3059 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3060 3061 /* MC_CMD_AOE_IN_TEMPERATURES msgrequest */ 3062 #define MC_CMD_AOE_IN_TEMPERATURES_LEN 4 3063 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3064 3065 /* MC_CMD_AOE_IN_CPLD_IDLE msgrequest */ 3066 #define MC_CMD_AOE_IN_CPLD_IDLE_LEN 4 3067 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3068 3069 /* MC_CMD_AOE_IN_CPLD_READ msgrequest */ 3070 #define MC_CMD_AOE_IN_CPLD_READ_LEN 12 3071 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3072 #define MC_CMD_AOE_IN_CPLD_READ_REGISTER_OFST 4 3073 #define MC_CMD_AOE_IN_CPLD_READ_WIDTH_OFST 8 3074 3075 /* MC_CMD_AOE_IN_CPLD_WRITE msgrequest */ 3076 #define MC_CMD_AOE_IN_CPLD_WRITE_LEN 16 3077 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3078 #define MC_CMD_AOE_IN_CPLD_WRITE_REGISTER_OFST 4 3079 #define MC_CMD_AOE_IN_CPLD_WRITE_WIDTH_OFST 8 3080 #define MC_CMD_AOE_IN_CPLD_WRITE_VALUE_OFST 12 3081 3082 /* MC_CMD_AOE_IN_CPLD_INSTRUCTION msgrequest */ 3083 #define MC_CMD_AOE_IN_CPLD_INSTRUCTION_LEN 8 3084 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3085 #define MC_CMD_AOE_IN_CPLD_INSTRUCTION_INSTRUCTION_OFST 4 3086 3087 /* MC_CMD_AOE_IN_CPLD_REPROGRAM msgrequest */ 3088 #define MC_CMD_AOE_IN_CPLD_REPROGRAM_LEN 8 3089 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3090 #define MC_CMD_AOE_IN_CPLD_REPROGRAM_OP_OFST 4 3091 /* enum: Reprogram CPLD, poll for completion */ 3092 #define MC_CMD_AOE_IN_CPLD_REPROGRAM_REPROGRAM 0x1 3093 /* enum: Reprogram CPLD, send event on completion */ 3094 #define MC_CMD_AOE_IN_CPLD_REPROGRAM_REPROGRAM_EVENT 0x3 3095 /* enum: Get status of reprogramming operation */ 3096 #define MC_CMD_AOE_IN_CPLD_REPROGRAM_STATUS 0x4 3097 3098 /* MC_CMD_AOE_IN_POWER msgrequest */ 3099 #define MC_CMD_AOE_IN_POWER_LEN 8 3100 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3101 /* Turn on or off AOE power */ 3102 #define MC_CMD_AOE_IN_POWER_OP_OFST 4 3103 /* enum: Turn off FPGA power */ 3104 #define MC_CMD_AOE_IN_POWER_OFF 0x0 3105 /* enum: Turn on FPGA power */ 3106 #define MC_CMD_AOE_IN_POWER_ON 0x1 3107 /* enum: Clear peak power measurement */ 3108 #define MC_CMD_AOE_IN_POWER_CLEAR 0x2 3109 /* enum: Show current power in sensors output */ 3110 #define MC_CMD_AOE_IN_POWER_SHOW_CURRENT 0x3 3111 /* enum: Show peak power in sensors output */ 3112 #define MC_CMD_AOE_IN_POWER_SHOW_PEAK 0x4 3113 /* enum: Show current DDR current */ 3114 #define MC_CMD_AOE_IN_POWER_DDR_LAST 0x5 3115 /* enum: Show peak DDR current */ 3116 #define MC_CMD_AOE_IN_POWER_DDR_PEAK 0x6 3117 /* enum: Clear peak DDR current */ 3118 #define MC_CMD_AOE_IN_POWER_DDR_CLEAR 0x7 3119 3120 /* MC_CMD_AOE_IN_LOAD msgrequest */ 3121 #define MC_CMD_AOE_IN_LOAD_LEN 8 3122 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3123 /* Image to be loaded (0 - main or 1 - diagnostic) to load in normal sequence 3124 */ 3125 #define MC_CMD_AOE_IN_LOAD_IMAGE_OFST 4 3126 3127 /* MC_CMD_AOE_IN_FAN_CONTROL msgrequest */ 3128 #define MC_CMD_AOE_IN_FAN_CONTROL_LEN 8 3129 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3130 /* If non zero report measured fan RPM rather than nominal */ 3131 #define MC_CMD_AOE_IN_FAN_CONTROL_REAL_RPM_OFST 4 3132 3133 /* MC_CMD_AOE_IN_FAN_FAILURES msgrequest */ 3134 #define MC_CMD_AOE_IN_FAN_FAILURES_LEN 4 3135 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3136 3137 /* MC_CMD_AOE_IN_MAC_STATS msgrequest */ 3138 #define MC_CMD_AOE_IN_MAC_STATS_LEN 24 3139 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3140 /* AOE port */ 3141 #define MC_CMD_AOE_IN_MAC_STATS_PORT_OFST 4 3142 /* Host memory address for statistics */ 3143 #define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_OFST 8 3144 #define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_LEN 8 3145 #define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_LO_OFST 8 3146 #define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_HI_OFST 12 3147 #define MC_CMD_AOE_IN_MAC_STATS_CMD_OFST 16 3148 #define MC_CMD_AOE_IN_MAC_STATS_DMA_LBN 0 3149 #define MC_CMD_AOE_IN_MAC_STATS_DMA_WIDTH 1 3150 #define MC_CMD_AOE_IN_MAC_STATS_CLEAR_LBN 1 3151 #define MC_CMD_AOE_IN_MAC_STATS_CLEAR_WIDTH 1 3152 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CHANGE_LBN 2 3153 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CHANGE_WIDTH 1 3154 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_ENABLE_LBN 3 3155 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_ENABLE_WIDTH 1 3156 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CLEAR_LBN 4 3157 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CLEAR_WIDTH 1 3158 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_NOEVENT_LBN 5 3159 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_NOEVENT_WIDTH 1 3160 #define MC_CMD_AOE_IN_MAC_STATS_PERIOD_MS_LBN 16 3161 #define MC_CMD_AOE_IN_MAC_STATS_PERIOD_MS_WIDTH 16 3162 /* Length of DMA data (optional) */ 3163 #define MC_CMD_AOE_IN_MAC_STATS_DMA_LEN_OFST 20 3164 3165 /* MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO msgrequest */ 3166 #define MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_LEN 12 3167 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3168 /* AOE port */ 3169 #define MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_PORT_OFST 4 3170 #define MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_PAGE_OFST 8 3171 3172 /* MC_CMD_AOE_IN_JTAG_WRITE msgrequest */ 3173 #define MC_CMD_AOE_IN_JTAG_WRITE_LENMIN 12 3174 #define MC_CMD_AOE_IN_JTAG_WRITE_LENMAX 252 3175 #define MC_CMD_AOE_IN_JTAG_WRITE_LEN(num) (8+4*(num)) 3176 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3177 #define MC_CMD_AOE_IN_JTAG_WRITE_DATALEN_OFST 4 3178 #define MC_CMD_AOE_IN_JTAG_WRITE_DATA_OFST 8 3179 #define MC_CMD_AOE_IN_JTAG_WRITE_DATA_LEN 4 3180 #define MC_CMD_AOE_IN_JTAG_WRITE_DATA_MINNUM 1 3181 #define MC_CMD_AOE_IN_JTAG_WRITE_DATA_MAXNUM 61 3182 3183 /* MC_CMD_AOE_IN_FPGA_ACCESS msgrequest */ 3184 #define MC_CMD_AOE_IN_FPGA_ACCESS_LEN 8 3185 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3186 /* Enable or disable access */ 3187 #define MC_CMD_AOE_IN_FPGA_ACCESS_OP_OFST 4 3188 /* enum: Enable access */ 3189 #define MC_CMD_AOE_IN_FPGA_ACCESS_ENABLE 0x1 3190 /* enum: Disable access */ 3191 #define MC_CMD_AOE_IN_FPGA_ACCESS_DISABLE 0x2 3192 3193 /* MC_CMD_AOE_IN_SET_MTU_OFFSET msgrequest */ 3194 #define MC_CMD_AOE_IN_SET_MTU_OFFSET_LEN 12 3195 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3196 /* AOE port - when not ALL_EXTERNAL or ALL_INTERNAL specifies port number */ 3197 #define MC_CMD_AOE_IN_SET_MTU_OFFSET_PORT_OFST 4 3198 /* enum: Apply to all external ports */ 3199 #define MC_CMD_AOE_IN_SET_MTU_OFFSET_ALL_EXTERNAL 0x8000 3200 /* enum: Apply to all internal ports */ 3201 #define MC_CMD_AOE_IN_SET_MTU_OFFSET_ALL_INTERNAL 0x4000 3202 /* The MTU offset to be applied to the external ports */ 3203 #define MC_CMD_AOE_IN_SET_MTU_OFFSET_OFFSET_OFST 8 3204 3205 /* MC_CMD_AOE_IN_LINK_STATE msgrequest */ 3206 #define MC_CMD_AOE_IN_LINK_STATE_LEN 8 3207 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3208 #define MC_CMD_AOE_IN_LINK_STATE_MODE_OFST 4 3209 #define MC_CMD_AOE_IN_LINK_STATE_CONFIG_MODE_LBN 0 3210 #define MC_CMD_AOE_IN_LINK_STATE_CONFIG_MODE_WIDTH 8 3211 /* enum: AOE and associated external port */ 3212 #define MC_CMD_AOE_IN_LINK_STATE_SIMPLE_SEPARATE 0x0 3213 /* enum: AOE and OR of all external ports */ 3214 #define MC_CMD_AOE_IN_LINK_STATE_SIMPLE_COMBINED 0x1 3215 /* enum: Individual ports */ 3216 #define MC_CMD_AOE_IN_LINK_STATE_DIAGNOSTIC 0x2 3217 /* enum: Configure link state mode on given AOE port */ 3218 #define MC_CMD_AOE_IN_LINK_STATE_CUSTOM 0x3 3219 #define MC_CMD_AOE_IN_LINK_STATE_OPERATION_LBN 8 3220 #define MC_CMD_AOE_IN_LINK_STATE_OPERATION_WIDTH 8 3221 /* enum: No-op */ 3222 #define MC_CMD_AOE_IN_LINK_STATE_OP_NONE 0x0 3223 /* enum: logical OR of all SFP ports link status */ 3224 #define MC_CMD_AOE_IN_LINK_STATE_OP_OR 0x1 3225 /* enum: logical AND of all SFP ports link status */ 3226 #define MC_CMD_AOE_IN_LINK_STATE_OP_AND 0x2 3227 #define MC_CMD_AOE_IN_LINK_STATE_SFP_MASK_LBN 16 3228 #define MC_CMD_AOE_IN_LINK_STATE_SFP_MASK_WIDTH 16 3229 3230 /* MC_CMD_AOE_IN_SIENA_STATS msgrequest */ 3231 #define MC_CMD_AOE_IN_SIENA_STATS_LEN 8 3232 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3233 /* How MAC statistics are reported */ 3234 #define MC_CMD_AOE_IN_SIENA_STATS_MODE_OFST 4 3235 /* enum: Statistics from Siena (default) */ 3236 #define MC_CMD_AOE_IN_SIENA_STATS_STATS_SIENA 0x0 3237 /* enum: Statistics from AOE external ports */ 3238 #define MC_CMD_AOE_IN_SIENA_STATS_STATS_AOE 0x1 3239 3240 /* MC_CMD_AOE_IN_ASIC_STATS msgrequest */ 3241 #define MC_CMD_AOE_IN_ASIC_STATS_LEN 8 3242 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3243 /* How MAC statistics are reported */ 3244 #define MC_CMD_AOE_IN_ASIC_STATS_MODE_OFST 4 3245 /* enum: Statistics from the ASIC (default) */ 3246 #define MC_CMD_AOE_IN_ASIC_STATS_STATS_ASIC 0x0 3247 /* enum: Statistics from AOE external ports */ 3248 #define MC_CMD_AOE_IN_ASIC_STATS_STATS_AOE 0x1 3249 3250 /* MC_CMD_AOE_IN_DDR msgrequest */ 3251 #define MC_CMD_AOE_IN_DDR_LEN 12 3252 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3253 #define MC_CMD_AOE_IN_DDR_BANK_OFST 4 3254 /* Enum values, see field(s): */ 3255 /* MC_CMD_FC/MC_CMD_FC_IN_DDR/MC_CMD_FC_IN_DDR_BANK */ 3256 /* Page index of SPD data */ 3257 #define MC_CMD_AOE_IN_DDR_SPD_PAGE_ID_OFST 8 3258 3259 /* MC_CMD_AOE_IN_FC msgrequest */ 3260 #define MC_CMD_AOE_IN_FC_LEN 4 3261 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3262 3263 /* MC_CMD_AOE_IN_DDR_ECC_STATUS msgrequest */ 3264 #define MC_CMD_AOE_IN_DDR_ECC_STATUS_LEN 8 3265 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3266 #define MC_CMD_AOE_IN_DDR_ECC_STATUS_BANK_OFST 4 3267 /* Enum values, see field(s): */ 3268 /* MC_CMD_FC/MC_CMD_FC_IN_DDR/MC_CMD_FC_IN_DDR_BANK */ 3269 3270 /* MC_CMD_AOE_IN_MC_SPI_MASTER msgrequest */ 3271 #define MC_CMD_AOE_IN_MC_SPI_MASTER_LEN 8 3272 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3273 /* Basic commands for MC SPI Master emulation. */ 3274 #define MC_CMD_AOE_IN_MC_SPI_MASTER_OP_OFST 4 3275 /* enum: MC SPI read */ 3276 #define MC_CMD_AOE_IN_MC_SPI_MASTER_READ 0x0 3277 /* enum: MC SPI write */ 3278 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE 0x1 3279 3280 /* MC_CMD_AOE_IN_MC_SPI_MASTER_READ msgrequest */ 3281 #define MC_CMD_AOE_IN_MC_SPI_MASTER_READ_LEN 12 3282 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3283 #define MC_CMD_AOE_IN_MC_SPI_MASTER_READ_OP_OFST 4 3284 #define MC_CMD_AOE_IN_MC_SPI_MASTER_READ_OFFSET_OFST 8 3285 3286 /* MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE msgrequest */ 3287 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_LEN 16 3288 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3289 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_OP_OFST 4 3290 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_OFFSET_OFST 8 3291 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_DATA_OFST 12 3292 3293 /* MC_CMD_AOE_IN_FC_BOOT msgrequest */ 3294 #define MC_CMD_AOE_IN_FC_BOOT_LEN 8 3295 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3296 /* FC boot control flags */ 3297 #define MC_CMD_AOE_IN_FC_BOOT_CONTROL_OFST 4 3298 #define MC_CMD_AOE_IN_FC_BOOT_CONTROL_BOOT_ENABLE_LBN 0 3299 #define MC_CMD_AOE_IN_FC_BOOT_CONTROL_BOOT_ENABLE_WIDTH 1 3300 3301 /* MC_CMD_AOE_OUT_INFO msgresponse */ 3302 #define MC_CMD_AOE_OUT_INFO_LEN 44 3303 /* JTAG IDCODE of CPLD */ 3304 #define MC_CMD_AOE_OUT_INFO_CPLD_IDCODE_OFST 0 3305 /* Version of CPLD */ 3306 #define MC_CMD_AOE_OUT_INFO_CPLD_VERSION_OFST 4 3307 /* JTAG IDCODE of FPGA */ 3308 #define MC_CMD_AOE_OUT_INFO_FPGA_IDCODE_OFST 8 3309 /* JTAG USERCODE of FPGA */ 3310 #define MC_CMD_AOE_OUT_INFO_FPGA_VERSION_OFST 12 3311 /* FPGA type - read from CPLD straps */ 3312 #define MC_CMD_AOE_OUT_INFO_FPGA_TYPE_OFST 16 3313 #define MC_CMD_AOE_OUT_INFO_FPGA_TYPE_A5_C2 0x1 /* enum */ 3314 #define MC_CMD_AOE_OUT_INFO_FPGA_TYPE_A7_C2 0x2 /* enum */ 3315 /* FPGA state (debug) */ 3316 #define MC_CMD_AOE_OUT_INFO_FPGA_STATE_OFST 20 3317 /* FPGA image - partition from which loaded */ 3318 #define MC_CMD_AOE_OUT_INFO_FPGA_IMAGE_OFST 24 3319 /* FC state */ 3320 #define MC_CMD_AOE_OUT_INFO_FC_STATE_OFST 28 3321 /* enum: Set if watchdog working */ 3322 #define MC_CMD_AOE_OUT_INFO_WATCHDOG 0x1 3323 /* enum: Set if MC-FC communications working */ 3324 #define MC_CMD_AOE_OUT_INFO_COMMS 0x2 3325 /* Random pieces of information */ 3326 #define MC_CMD_AOE_OUT_INFO_FLAGS_OFST 32 3327 /* enum: Power to FPGA supplied by PEG connector, not PCIe bus */ 3328 #define MC_CMD_AOE_OUT_INFO_PEG_POWER 0x1 3329 /* enum: CPLD apparently good */ 3330 #define MC_CMD_AOE_OUT_INFO_CPLD_GOOD 0x2 3331 /* enum: FPGA working normally */ 3332 #define MC_CMD_AOE_OUT_INFO_FPGA_GOOD 0x4 3333 /* enum: FPGA is powered */ 3334 #define MC_CMD_AOE_OUT_INFO_FPGA_POWER 0x8 3335 /* enum: Board has incompatible SODIMMs fitted */ 3336 #define MC_CMD_AOE_OUT_INFO_BAD_SODIMM 0x10 3337 /* enum: Board has ByteBlaster connected */ 3338 #define MC_CMD_AOE_OUT_INFO_HAS_BYTEBLASTER 0x20 3339 /* enum: FPGA Boot flash has an invalid header. */ 3340 #define MC_CMD_AOE_OUT_INFO_FPGA_BAD_BOOT_HDR 0x40 3341 /* enum: FPGA Application flash is accessible. */ 3342 #define MC_CMD_AOE_OUT_INFO_FPGA_APP_FLASH_GOOD 0x80 3343 /* Revision of Modena and Sorrento boards. Sorrento can be R1_2 or R1_3. */ 3344 #define MC_CMD_AOE_OUT_INFO_BOARD_REVISION_OFST 36 3345 #define MC_CMD_AOE_OUT_INFO_UNKNOWN 0x0 /* enum */ 3346 #define MC_CMD_AOE_OUT_INFO_R1_0 0x10 /* enum */ 3347 #define MC_CMD_AOE_OUT_INFO_R1_1 0x11 /* enum */ 3348 #define MC_CMD_AOE_OUT_INFO_R1_2 0x12 /* enum */ 3349 #define MC_CMD_AOE_OUT_INFO_R1_3 0x13 /* enum */ 3350 /* Result of FC booting - not valid while a ByteBlaster is connected. */ 3351 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_RESULT_OFST 40 3352 /* enum: No error */ 3353 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_NO_ERROR 0x0 3354 /* enum: Bad address set in CPLD */ 3355 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_ADDRESS 0x1 3356 /* enum: Bad header */ 3357 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_MAGIC 0x2 3358 /* enum: Bad text section details */ 3359 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_TEXT 0x3 3360 /* enum: Bad checksum */ 3361 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_CHECKSUM 0x4 3362 /* enum: Bad BSP */ 3363 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_BSP 0x5 3364 /* enum: Flash mode is invalid */ 3365 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_INVALID_FLASH_MODE 0x6 3366 /* enum: FC application loaded and execution attempted */ 3367 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_APP_EXECUTE 0x80 3368 /* enum: FC application Started */ 3369 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_APP_STARTED 0x81 3370 /* enum: No bootrom in FPGA */ 3371 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_NO_BOOTROM 0xff 3372 3373 /* MC_CMD_AOE_OUT_CURRENTS msgresponse */ 3374 #define MC_CMD_AOE_OUT_CURRENTS_LEN 68 3375 /* Set of currents and voltages (mA or mV as appropriate) */ 3376 #define MC_CMD_AOE_OUT_CURRENTS_VALUES_OFST 0 3377 #define MC_CMD_AOE_OUT_CURRENTS_VALUES_LEN 4 3378 #define MC_CMD_AOE_OUT_CURRENTS_VALUES_NUM 17 3379 #define MC_CMD_AOE_OUT_CURRENTS_I_2V5 0x0 /* enum */ 3380 #define MC_CMD_AOE_OUT_CURRENTS_I_1V8 0x1 /* enum */ 3381 #define MC_CMD_AOE_OUT_CURRENTS_I_GXB 0x2 /* enum */ 3382 #define MC_CMD_AOE_OUT_CURRENTS_I_PGM 0x3 /* enum */ 3383 #define MC_CMD_AOE_OUT_CURRENTS_I_XCVR 0x4 /* enum */ 3384 #define MC_CMD_AOE_OUT_CURRENTS_I_1V5 0x5 /* enum */ 3385 #define MC_CMD_AOE_OUT_CURRENTS_V_3V3 0x6 /* enum */ 3386 #define MC_CMD_AOE_OUT_CURRENTS_V_1V5 0x7 /* enum */ 3387 #define MC_CMD_AOE_OUT_CURRENTS_I_IN 0x8 /* enum */ 3388 #define MC_CMD_AOE_OUT_CURRENTS_I_OUT 0x9 /* enum */ 3389 #define MC_CMD_AOE_OUT_CURRENTS_V_IN 0xa /* enum */ 3390 #define MC_CMD_AOE_OUT_CURRENTS_I_OUT_DDR1 0xb /* enum */ 3391 #define MC_CMD_AOE_OUT_CURRENTS_V_OUT_DDR1 0xc /* enum */ 3392 #define MC_CMD_AOE_OUT_CURRENTS_I_OUT_DDR2 0xd /* enum */ 3393 #define MC_CMD_AOE_OUT_CURRENTS_V_OUT_DDR2 0xe /* enum */ 3394 #define MC_CMD_AOE_OUT_CURRENTS_I_OUT_DDR3 0xf /* enum */ 3395 #define MC_CMD_AOE_OUT_CURRENTS_V_OUT_DDR3 0x10 /* enum */ 3396 3397 /* MC_CMD_AOE_OUT_TEMPERATURES msgresponse */ 3398 #define MC_CMD_AOE_OUT_TEMPERATURES_LEN 40 3399 /* Set of temperatures */ 3400 #define MC_CMD_AOE_OUT_TEMPERATURES_VALUES_OFST 0 3401 #define MC_CMD_AOE_OUT_TEMPERATURES_VALUES_LEN 4 3402 #define MC_CMD_AOE_OUT_TEMPERATURES_VALUES_NUM 10 3403 /* enum: The first set of enum values are for Modena code. */ 3404 #define MC_CMD_AOE_OUT_TEMPERATURES_MAIN_0 0x0 3405 #define MC_CMD_AOE_OUT_TEMPERATURES_MAIN_1 0x1 /* enum */ 3406 #define MC_CMD_AOE_OUT_TEMPERATURES_IND_0 0x2 /* enum */ 3407 #define MC_CMD_AOE_OUT_TEMPERATURES_IND_1 0x3 /* enum */ 3408 #define MC_CMD_AOE_OUT_TEMPERATURES_VCCIO1 0x4 /* enum */ 3409 #define MC_CMD_AOE_OUT_TEMPERATURES_VCCIO2 0x5 /* enum */ 3410 #define MC_CMD_AOE_OUT_TEMPERATURES_VCCIO3 0x6 /* enum */ 3411 #define MC_CMD_AOE_OUT_TEMPERATURES_PSU 0x7 /* enum */ 3412 #define MC_CMD_AOE_OUT_TEMPERATURES_FPGA 0x8 /* enum */ 3413 #define MC_CMD_AOE_OUT_TEMPERATURES_SIENA 0x9 /* enum */ 3414 /* enum: The second set of enum values are for Sorrento code. */ 3415 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_MAIN_0 0x0 3416 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_MAIN_1 0x1 /* enum */ 3417 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_IND_0 0x2 /* enum */ 3418 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_IND_1 0x3 /* enum */ 3419 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_SODIMM_0 0x4 /* enum */ 3420 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_SODIMM_1 0x5 /* enum */ 3421 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_FPGA 0x6 /* enum */ 3422 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_PHY0 0x7 /* enum */ 3423 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_PHY1 0x8 /* enum */ 3424 3425 /* MC_CMD_AOE_OUT_CPLD_READ msgresponse */ 3426 #define MC_CMD_AOE_OUT_CPLD_READ_LEN 4 3427 /* The value read from the CPLD */ 3428 #define MC_CMD_AOE_OUT_CPLD_READ_VALUE_OFST 0 3429 3430 /* MC_CMD_AOE_OUT_FAN_FAILURES msgresponse */ 3431 #define MC_CMD_AOE_OUT_FAN_FAILURES_LENMIN 4 3432 #define MC_CMD_AOE_OUT_FAN_FAILURES_LENMAX 252 3433 #define MC_CMD_AOE_OUT_FAN_FAILURES_LEN(num) (0+4*(num)) 3434 /* Failure counts for each fan */ 3435 #define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_OFST 0 3436 #define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_LEN 4 3437 #define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_MINNUM 1 3438 #define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_MAXNUM 63 3439 3440 /* MC_CMD_AOE_OUT_CPLD_REPROGRAM msgresponse */ 3441 #define MC_CMD_AOE_OUT_CPLD_REPROGRAM_LEN 4 3442 /* Results of status command (only) */ 3443 #define MC_CMD_AOE_OUT_CPLD_REPROGRAM_STATUS_OFST 0 3444 3445 /* MC_CMD_AOE_OUT_POWER_OFF msgresponse */ 3446 #define MC_CMD_AOE_OUT_POWER_OFF_LEN 0 3447 3448 /* MC_CMD_AOE_OUT_POWER_ON msgresponse */ 3449 #define MC_CMD_AOE_OUT_POWER_ON_LEN 0 3450 3451 /* MC_CMD_AOE_OUT_LOAD msgresponse */ 3452 #define MC_CMD_AOE_OUT_LOAD_LEN 0 3453 3454 /* MC_CMD_AOE_OUT_MAC_STATS_DMA msgresponse */ 3455 #define MC_CMD_AOE_OUT_MAC_STATS_DMA_LEN 0 3456 3457 /* MC_CMD_AOE_OUT_MAC_STATS_NO_DMA msgresponse: See MC_CMD_MAC_STATS_OUT_NO_DMA 3458 * for details 3459 */ 3460 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_LEN (((MC_CMD_MAC_NSTATS*64))>>3) 3461 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_OFST 0 3462 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_LEN 8 3463 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_LO_OFST 0 3464 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_HI_OFST 4 3465 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS 3466 3467 /* MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO msgresponse */ 3468 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LENMIN 5 3469 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LENMAX 252 3470 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LEN(num) (4+1*(num)) 3471 /* in bytes */ 3472 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATALEN_OFST 0 3473 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_OFST 4 3474 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_LEN 1 3475 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_MINNUM 1 3476 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_MAXNUM 248 3477 3478 /* MC_CMD_AOE_OUT_JTAG_WRITE msgresponse */ 3479 #define MC_CMD_AOE_OUT_JTAG_WRITE_LENMIN 12 3480 #define MC_CMD_AOE_OUT_JTAG_WRITE_LENMAX 252 3481 #define MC_CMD_AOE_OUT_JTAG_WRITE_LEN(num) (8+4*(num)) 3482 /* Used to align the in and out data blocks so the MC can re-use the cmd */ 3483 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATALEN_OFST 0 3484 /* out bytes */ 3485 #define MC_CMD_AOE_OUT_JTAG_WRITE_PAD_OFST 4 3486 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_OFST 8 3487 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_LEN 4 3488 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_MINNUM 1 3489 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_MAXNUM 61 3490 3491 /* MC_CMD_AOE_OUT_FPGA_ACCESS msgresponse */ 3492 #define MC_CMD_AOE_OUT_FPGA_ACCESS_LEN 0 3493 3494 /* MC_CMD_AOE_OUT_DDR msgresponse */ 3495 #define MC_CMD_AOE_OUT_DDR_LENMIN 17 3496 #define MC_CMD_AOE_OUT_DDR_LENMAX 252 3497 #define MC_CMD_AOE_OUT_DDR_LEN(num) (16+1*(num)) 3498 /* Information on the module. */ 3499 #define MC_CMD_AOE_OUT_DDR_FLAGS_OFST 0 3500 #define MC_CMD_AOE_OUT_DDR_PRESENT_LBN 0 3501 #define MC_CMD_AOE_OUT_DDR_PRESENT_WIDTH 1 3502 #define MC_CMD_AOE_OUT_DDR_POWERED_LBN 1 3503 #define MC_CMD_AOE_OUT_DDR_POWERED_WIDTH 1 3504 #define MC_CMD_AOE_OUT_DDR_OPERATIONAL_LBN 2 3505 #define MC_CMD_AOE_OUT_DDR_OPERATIONAL_WIDTH 1 3506 #define MC_CMD_AOE_OUT_DDR_NOT_REACHABLE_LBN 3 3507 #define MC_CMD_AOE_OUT_DDR_NOT_REACHABLE_WIDTH 1 3508 /* Memory size, in MB. */ 3509 #define MC_CMD_AOE_OUT_DDR_CAPACITY_OFST 4 3510 /* The memory type, as reported from SPD information */ 3511 #define MC_CMD_AOE_OUT_DDR_TYPE_OFST 8 3512 /* Nominal voltage of the module (as applied) */ 3513 #define MC_CMD_AOE_OUT_DDR_VOLTAGE_OFST 12 3514 /* SPD data read from the module */ 3515 #define MC_CMD_AOE_OUT_DDR_SPD_OFST 16 3516 #define MC_CMD_AOE_OUT_DDR_SPD_LEN 1 3517 #define MC_CMD_AOE_OUT_DDR_SPD_MINNUM 1 3518 #define MC_CMD_AOE_OUT_DDR_SPD_MAXNUM 236 3519 3520 /* MC_CMD_AOE_OUT_SET_MTU_OFFSET msgresponse */ 3521 #define MC_CMD_AOE_OUT_SET_MTU_OFFSET_LEN 0 3522 3523 /* MC_CMD_AOE_OUT_LINK_STATE msgresponse */ 3524 #define MC_CMD_AOE_OUT_LINK_STATE_LEN 0 3525 3526 /* MC_CMD_AOE_OUT_SIENA_STATS msgresponse */ 3527 #define MC_CMD_AOE_OUT_SIENA_STATS_LEN 0 3528 3529 /* MC_CMD_AOE_OUT_ASIC_STATS msgresponse */ 3530 #define MC_CMD_AOE_OUT_ASIC_STATS_LEN 0 3531 3532 /* MC_CMD_AOE_OUT_FC msgresponse */ 3533 #define MC_CMD_AOE_OUT_FC_LEN 0 3534 3535 /* MC_CMD_AOE_OUT_DDR_ECC_STATUS msgresponse */ 3536 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_LEN 8 3537 /* Flags describing status info on the module. */ 3538 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_FLAGS_OFST 0 3539 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_VALID_LBN 0 3540 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_VALID_WIDTH 1 3541 /* DDR ECC status on the module. */ 3542 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_STATUS_OFST 4 3543 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_LBN 0 3544 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_WIDTH 1 3545 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_LBN 1 3546 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_WIDTH 1 3547 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_LBN 2 3548 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_WIDTH 1 3549 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_COUNT_LBN 8 3550 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_COUNT_WIDTH 8 3551 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_COUNT_LBN 16 3552 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_COUNT_WIDTH 8 3553 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_COUNT_LBN 24 3554 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_COUNT_WIDTH 8 3555 3556 /* MC_CMD_AOE_OUT_MC_SPI_MASTER_READ msgresponse */ 3557 #define MC_CMD_AOE_OUT_MC_SPI_MASTER_READ_LEN 4 3558 #define MC_CMD_AOE_OUT_MC_SPI_MASTER_READ_DATA_OFST 0 3559 3560 /* MC_CMD_AOE_OUT_MC_SPI_MASTER_WRITE msgresponse */ 3561 #define MC_CMD_AOE_OUT_MC_SPI_MASTER_WRITE_LEN 0 3562 3563 /* MC_CMD_AOE_OUT_MC_SPI_MASTER msgresponse */ 3564 #define MC_CMD_AOE_OUT_MC_SPI_MASTER_LEN 0 3565 3566 /* MC_CMD_AOE_OUT_FC_BOOT msgresponse */ 3567 #define MC_CMD_AOE_OUT_FC_BOOT_LEN 0 3568 3569 3570 /***********************************/ 3571 /* MC_CMD_PTP 3572 * Perform PTP operation 3573 */ 3574 #define MC_CMD_PTP 0xb 3575 #undef MC_CMD_0xb_PRIVILEGE_CTG 3576 3577 #define MC_CMD_0xb_PRIVILEGE_CTG SRIOV_CTG_GENERAL 3578 3579 /* MC_CMD_PTP_IN msgrequest */ 3580 #define MC_CMD_PTP_IN_LEN 1 3581 /* PTP operation code */ 3582 #define MC_CMD_PTP_IN_OP_OFST 0 3583 #define MC_CMD_PTP_IN_OP_LEN 1 3584 /* enum: Enable PTP packet timestamping operation. */ 3585 #define MC_CMD_PTP_OP_ENABLE 0x1 3586 /* enum: Disable PTP packet timestamping operation. */ 3587 #define MC_CMD_PTP_OP_DISABLE 0x2 3588 /* enum: Send a PTP packet. */ 3589 #define MC_CMD_PTP_OP_TRANSMIT 0x3 3590 /* enum: Read the current NIC time. */ 3591 #define MC_CMD_PTP_OP_READ_NIC_TIME 0x4 3592 /* enum: Get the current PTP status. */ 3593 #define MC_CMD_PTP_OP_STATUS 0x5 3594 /* enum: Adjust the PTP NIC's time. */ 3595 #define MC_CMD_PTP_OP_ADJUST 0x6 3596 /* enum: Synchronize host and NIC time. */ 3597 #define MC_CMD_PTP_OP_SYNCHRONIZE 0x7 3598 /* enum: Basic manufacturing tests. */ 3599 #define MC_CMD_PTP_OP_MANFTEST_BASIC 0x8 3600 /* enum: Packet based manufacturing tests. */ 3601 #define MC_CMD_PTP_OP_MANFTEST_PACKET 0x9 3602 /* enum: Reset some of the PTP related statistics */ 3603 #define MC_CMD_PTP_OP_RESET_STATS 0xa 3604 /* enum: Debug operations to MC. */ 3605 #define MC_CMD_PTP_OP_DEBUG 0xb 3606 /* enum: Read an FPGA register */ 3607 #define MC_CMD_PTP_OP_FPGAREAD 0xc 3608 /* enum: Write an FPGA register */ 3609 #define MC_CMD_PTP_OP_FPGAWRITE 0xd 3610 /* enum: Apply an offset to the NIC clock */ 3611 #define MC_CMD_PTP_OP_CLOCK_OFFSET_ADJUST 0xe 3612 /* enum: Change Apply an offset to the NIC clock */ 3613 #define MC_CMD_PTP_OP_CLOCK_FREQ_ADJUST 0xf 3614 /* enum: Set the MC packet filter VLAN tags for received PTP packets */ 3615 #define MC_CMD_PTP_OP_RX_SET_VLAN_FILTER 0x10 3616 /* enum: Set the MC packet filter UUID for received PTP packets */ 3617 #define MC_CMD_PTP_OP_RX_SET_UUID_FILTER 0x11 3618 /* enum: Set the MC packet filter Domain for received PTP packets */ 3619 #define MC_CMD_PTP_OP_RX_SET_DOMAIN_FILTER 0x12 3620 /* enum: Set the clock source */ 3621 #define MC_CMD_PTP_OP_SET_CLK_SRC 0x13 3622 /* enum: Reset value of Timer Reg. */ 3623 #define MC_CMD_PTP_OP_RST_CLK 0x14 3624 /* enum: Enable the forwarding of PPS events to the host */ 3625 #define MC_CMD_PTP_OP_PPS_ENABLE 0x15 3626 /* enum: Get the time format used by this NIC for PTP operations */ 3627 #define MC_CMD_PTP_OP_GET_TIME_FORMAT 0x16 3628 /* enum: Get the clock attributes. NOTE- extended version of 3629 * MC_CMD_PTP_OP_GET_TIME_FORMAT 3630 */ 3631 #define MC_CMD_PTP_OP_GET_ATTRIBUTES 0x16 3632 /* enum: Get corrections that should be applied to the various different 3633 * timestamps 3634 */ 3635 #define MC_CMD_PTP_OP_GET_TIMESTAMP_CORRECTIONS 0x17 3636 /* enum: Subscribe to receive periodic time events indicating the current NIC 3637 * time 3638 */ 3639 #define MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE 0x18 3640 /* enum: Unsubscribe to stop receiving time events */ 3641 #define MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE 0x19 3642 /* enum: PPS based manfacturing tests. Requires PPS output to be looped to PPS 3643 * input on the same NIC. 3644 */ 3645 #define MC_CMD_PTP_OP_MANFTEST_PPS 0x1a 3646 /* enum: Set the PTP sync status. Status is used by firmware to report to event 3647 * subscribers. 3648 */ 3649 #define MC_CMD_PTP_OP_SET_SYNC_STATUS 0x1b 3650 /* enum: Above this for future use. */ 3651 #define MC_CMD_PTP_OP_MAX 0x1c 3652 3653 /* MC_CMD_PTP_IN_ENABLE msgrequest */ 3654 #define MC_CMD_PTP_IN_ENABLE_LEN 16 3655 #define MC_CMD_PTP_IN_CMD_OFST 0 3656 #define MC_CMD_PTP_IN_PERIPH_ID_OFST 4 3657 /* Event queue for PTP events */ 3658 #define MC_CMD_PTP_IN_ENABLE_QUEUE_OFST 8 3659 /* PTP timestamping mode */ 3660 #define MC_CMD_PTP_IN_ENABLE_MODE_OFST 12 3661 /* enum: PTP, version 1 */ 3662 #define MC_CMD_PTP_MODE_V1 0x0 3663 /* enum: PTP, version 1, with VLAN headers - deprecated */ 3664 #define MC_CMD_PTP_MODE_V1_VLAN 0x1 3665 /* enum: PTP, version 2 */ 3666 #define MC_CMD_PTP_MODE_V2 0x2 3667 /* enum: PTP, version 2, with VLAN headers - deprecated */ 3668 #define MC_CMD_PTP_MODE_V2_VLAN 0x3 3669 /* enum: PTP, version 2, with improved UUID filtering */ 3670 #define MC_CMD_PTP_MODE_V2_ENHANCED 0x4 3671 /* enum: FCoE (seconds and microseconds) */ 3672 #define MC_CMD_PTP_MODE_FCOE 0x5 3673 3674 /* MC_CMD_PTP_IN_DISABLE msgrequest */ 3675 #define MC_CMD_PTP_IN_DISABLE_LEN 8 3676 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3677 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3678 3679 /* MC_CMD_PTP_IN_TRANSMIT msgrequest */ 3680 #define MC_CMD_PTP_IN_TRANSMIT_LENMIN 13 3681 #define MC_CMD_PTP_IN_TRANSMIT_LENMAX 252 3682 #define MC_CMD_PTP_IN_TRANSMIT_LEN(num) (12+1*(num)) 3683 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3684 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3685 /* Transmit packet length */ 3686 #define MC_CMD_PTP_IN_TRANSMIT_LENGTH_OFST 8 3687 /* Transmit packet data */ 3688 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_OFST 12 3689 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_LEN 1 3690 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_MINNUM 1 3691 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_MAXNUM 240 3692 3693 /* MC_CMD_PTP_IN_READ_NIC_TIME msgrequest */ 3694 #define MC_CMD_PTP_IN_READ_NIC_TIME_LEN 8 3695 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3696 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3697 3698 /* MC_CMD_PTP_IN_STATUS msgrequest */ 3699 #define MC_CMD_PTP_IN_STATUS_LEN 8 3700 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3701 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3702 3703 /* MC_CMD_PTP_IN_ADJUST msgrequest */ 3704 #define MC_CMD_PTP_IN_ADJUST_LEN 24 3705 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3706 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3707 /* Frequency adjustment 40 bit fixed point ns */ 3708 #define MC_CMD_PTP_IN_ADJUST_FREQ_OFST 8 3709 #define MC_CMD_PTP_IN_ADJUST_FREQ_LEN 8 3710 #define MC_CMD_PTP_IN_ADJUST_FREQ_LO_OFST 8 3711 #define MC_CMD_PTP_IN_ADJUST_FREQ_HI_OFST 12 3712 /* enum: Number of fractional bits in frequency adjustment */ 3713 #define MC_CMD_PTP_IN_ADJUST_BITS 0x28 3714 /* Time adjustment in seconds */ 3715 #define MC_CMD_PTP_IN_ADJUST_SECONDS_OFST 16 3716 /* Time adjustment major value */ 3717 #define MC_CMD_PTP_IN_ADJUST_MAJOR_OFST 16 3718 /* Time adjustment in nanoseconds */ 3719 #define MC_CMD_PTP_IN_ADJUST_NANOSECONDS_OFST 20 3720 /* Time adjustment minor value */ 3721 #define MC_CMD_PTP_IN_ADJUST_MINOR_OFST 20 3722 3723 /* MC_CMD_PTP_IN_SYNCHRONIZE msgrequest */ 3724 #define MC_CMD_PTP_IN_SYNCHRONIZE_LEN 20 3725 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3726 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3727 /* Number of time readings to capture */ 3728 #define MC_CMD_PTP_IN_SYNCHRONIZE_NUMTIMESETS_OFST 8 3729 /* Host address in which to write "synchronization started" indication (64 3730 * bits) 3731 */ 3732 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_OFST 12 3733 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LEN 8 3734 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LO_OFST 12 3735 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_HI_OFST 16 3736 3737 /* MC_CMD_PTP_IN_MANFTEST_BASIC msgrequest */ 3738 #define MC_CMD_PTP_IN_MANFTEST_BASIC_LEN 8 3739 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3740 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3741 3742 /* MC_CMD_PTP_IN_MANFTEST_PACKET msgrequest */ 3743 #define MC_CMD_PTP_IN_MANFTEST_PACKET_LEN 12 3744 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3745 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3746 /* Enable or disable packet testing */ 3747 #define MC_CMD_PTP_IN_MANFTEST_PACKET_TEST_ENABLE_OFST 8 3748 3749 /* MC_CMD_PTP_IN_RESET_STATS msgrequest */ 3750 #define MC_CMD_PTP_IN_RESET_STATS_LEN 8 3751 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3752 /* Reset PTP statistics */ 3753 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3754 3755 /* MC_CMD_PTP_IN_DEBUG msgrequest */ 3756 #define MC_CMD_PTP_IN_DEBUG_LEN 12 3757 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3758 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3759 /* Debug operations */ 3760 #define MC_CMD_PTP_IN_DEBUG_DEBUG_PARAM_OFST 8 3761 3762 /* MC_CMD_PTP_IN_FPGAREAD msgrequest */ 3763 #define MC_CMD_PTP_IN_FPGAREAD_LEN 16 3764 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3765 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3766 #define MC_CMD_PTP_IN_FPGAREAD_ADDR_OFST 8 3767 #define MC_CMD_PTP_IN_FPGAREAD_NUMBYTES_OFST 12 3768 3769 /* MC_CMD_PTP_IN_FPGAWRITE msgrequest */ 3770 #define MC_CMD_PTP_IN_FPGAWRITE_LENMIN 13 3771 #define MC_CMD_PTP_IN_FPGAWRITE_LENMAX 252 3772 #define MC_CMD_PTP_IN_FPGAWRITE_LEN(num) (12+1*(num)) 3773 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3774 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3775 #define MC_CMD_PTP_IN_FPGAWRITE_ADDR_OFST 8 3776 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_OFST 12 3777 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_LEN 1 3778 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MINNUM 1 3779 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MAXNUM 240 3780 3781 /* MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST msgrequest */ 3782 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_LEN 16 3783 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3784 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3785 /* Time adjustment in seconds */ 3786 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_SECONDS_OFST 8 3787 /* Time adjustment major value */ 3788 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MAJOR_OFST 8 3789 /* Time adjustment in nanoseconds */ 3790 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_NANOSECONDS_OFST 12 3791 /* Time adjustment minor value */ 3792 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MINOR_OFST 12 3793 3794 /* MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST msgrequest */ 3795 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_LEN 16 3796 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3797 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3798 /* Frequency adjustment 40 bit fixed point ns */ 3799 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_OFST 8 3800 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LEN 8 3801 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LO_OFST 8 3802 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_HI_OFST 12 3803 /* enum: Number of fractional bits in frequency adjustment */ 3804 /* MC_CMD_PTP_IN_ADJUST_BITS 0x28 */ 3805 3806 /* MC_CMD_PTP_IN_RX_SET_VLAN_FILTER msgrequest */ 3807 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_LEN 24 3808 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3809 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3810 /* Number of VLAN tags, 0 if not VLAN */ 3811 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_NUM_VLAN_TAGS_OFST 8 3812 /* Set of VLAN tags to filter against */ 3813 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_OFST 12 3814 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_LEN 4 3815 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_NUM 3 3816 3817 /* MC_CMD_PTP_IN_RX_SET_UUID_FILTER msgrequest */ 3818 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_LEN 20 3819 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3820 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3821 /* 1 to enable UUID filtering, 0 to disable */ 3822 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_ENABLE_OFST 8 3823 /* UUID to filter against */ 3824 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_OFST 12 3825 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LEN 8 3826 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LO_OFST 12 3827 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_HI_OFST 16 3828 3829 /* MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER msgrequest */ 3830 #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_LEN 16 3831 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3832 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3833 /* 1 to enable Domain filtering, 0 to disable */ 3834 #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_ENABLE_OFST 8 3835 /* Domain number to filter against */ 3836 #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_DOMAIN_OFST 12 3837 3838 /* MC_CMD_PTP_IN_SET_CLK_SRC msgrequest */ 3839 #define MC_CMD_PTP_IN_SET_CLK_SRC_LEN 12 3840 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3841 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3842 /* Set the clock source. */ 3843 #define MC_CMD_PTP_IN_SET_CLK_SRC_CLK_OFST 8 3844 /* enum: Internal. */ 3845 #define MC_CMD_PTP_CLK_SRC_INTERNAL 0x0 3846 /* enum: External. */ 3847 #define MC_CMD_PTP_CLK_SRC_EXTERNAL 0x1 3848 3849 /* MC_CMD_PTP_IN_RST_CLK msgrequest */ 3850 #define MC_CMD_PTP_IN_RST_CLK_LEN 8 3851 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3852 /* Reset value of Timer Reg. */ 3853 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3854 3855 /* MC_CMD_PTP_IN_PPS_ENABLE msgrequest */ 3856 #define MC_CMD_PTP_IN_PPS_ENABLE_LEN 12 3857 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3858 /* Enable or disable */ 3859 #define MC_CMD_PTP_IN_PPS_ENABLE_OP_OFST 4 3860 /* enum: Enable */ 3861 #define MC_CMD_PTP_ENABLE_PPS 0x0 3862 /* enum: Disable */ 3863 #define MC_CMD_PTP_DISABLE_PPS 0x1 3864 /* Queue id to send events back */ 3865 #define MC_CMD_PTP_IN_PPS_ENABLE_QUEUE_ID_OFST 8 3866 3867 /* MC_CMD_PTP_IN_GET_TIME_FORMAT msgrequest */ 3868 #define MC_CMD_PTP_IN_GET_TIME_FORMAT_LEN 8 3869 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3870 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3871 3872 /* MC_CMD_PTP_IN_GET_ATTRIBUTES msgrequest */ 3873 #define MC_CMD_PTP_IN_GET_ATTRIBUTES_LEN 8 3874 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3875 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3876 3877 /* MC_CMD_PTP_IN_GET_TIMESTAMP_CORRECTIONS msgrequest */ 3878 #define MC_CMD_PTP_IN_GET_TIMESTAMP_CORRECTIONS_LEN 8 3879 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3880 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3881 3882 /* MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE msgrequest */ 3883 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN 12 3884 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3885 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3886 /* Original field containing queue ID. Now extended to include flags. */ 3887 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_OFST 8 3888 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_LBN 0 3889 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_WIDTH 16 3890 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_REPORT_SYNC_STATUS_LBN 31 3891 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_REPORT_SYNC_STATUS_WIDTH 1 3892 3893 /* MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE msgrequest */ 3894 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN 16 3895 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3896 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3897 /* Unsubscribe options */ 3898 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL_OFST 8 3899 /* enum: Unsubscribe a single queue */ 3900 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE 0x0 3901 /* enum: Unsubscribe all queues */ 3902 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_ALL 0x1 3903 /* Event queue ID */ 3904 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE_OFST 12 3905 3906 /* MC_CMD_PTP_IN_MANFTEST_PPS msgrequest */ 3907 #define MC_CMD_PTP_IN_MANFTEST_PPS_LEN 12 3908 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3909 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3910 /* 1 to enable PPS test mode, 0 to disable and return result. */ 3911 #define MC_CMD_PTP_IN_MANFTEST_PPS_TEST_ENABLE_OFST 8 3912 3913 /* MC_CMD_PTP_IN_SET_SYNC_STATUS msgrequest */ 3914 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_LEN 24 3915 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3916 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3917 /* NIC - Host System Clock Synchronization status */ 3918 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_STATUS_OFST 8 3919 /* enum: Host System clock and NIC clock are not in sync */ 3920 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_NOT_IN_SYNC 0x0 3921 /* enum: Host System clock and NIC clock are synchronized */ 3922 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_IN_SYNC 0x1 3923 /* If synchronized, number of seconds until clocks should be considered to be 3924 * no longer in sync. 3925 */ 3926 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_TIMEOUT_OFST 12 3927 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED0_OFST 16 3928 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED1_OFST 20 3929 3930 /* MC_CMD_PTP_OUT msgresponse */ 3931 #define MC_CMD_PTP_OUT_LEN 0 3932 3933 /* MC_CMD_PTP_OUT_TRANSMIT msgresponse */ 3934 #define MC_CMD_PTP_OUT_TRANSMIT_LEN 8 3935 /* Value of seconds timestamp */ 3936 #define MC_CMD_PTP_OUT_TRANSMIT_SECONDS_OFST 0 3937 /* Timestamp major value */ 3938 #define MC_CMD_PTP_OUT_TRANSMIT_MAJOR_OFST 0 3939 /* Value of nanoseconds timestamp */ 3940 #define MC_CMD_PTP_OUT_TRANSMIT_NANOSECONDS_OFST 4 3941 /* Timestamp minor value */ 3942 #define MC_CMD_PTP_OUT_TRANSMIT_MINOR_OFST 4 3943 3944 /* MC_CMD_PTP_OUT_TIME_EVENT_SUBSCRIBE msgresponse */ 3945 #define MC_CMD_PTP_OUT_TIME_EVENT_SUBSCRIBE_LEN 0 3946 3947 /* MC_CMD_PTP_OUT_TIME_EVENT_UNSUBSCRIBE msgresponse */ 3948 #define MC_CMD_PTP_OUT_TIME_EVENT_UNSUBSCRIBE_LEN 0 3949 3950 /* MC_CMD_PTP_OUT_READ_NIC_TIME msgresponse */ 3951 #define MC_CMD_PTP_OUT_READ_NIC_TIME_LEN 8 3952 /* Value of seconds timestamp */ 3953 #define MC_CMD_PTP_OUT_READ_NIC_TIME_SECONDS_OFST 0 3954 /* Timestamp major value */ 3955 #define MC_CMD_PTP_OUT_READ_NIC_TIME_MAJOR_OFST 0 3956 /* Value of nanoseconds timestamp */ 3957 #define MC_CMD_PTP_OUT_READ_NIC_TIME_NANOSECONDS_OFST 4 3958 /* Timestamp minor value */ 3959 #define MC_CMD_PTP_OUT_READ_NIC_TIME_MINOR_OFST 4 3960 3961 /* MC_CMD_PTP_OUT_STATUS msgresponse */ 3962 #define MC_CMD_PTP_OUT_STATUS_LEN 64 3963 /* Frequency of NIC's hardware clock */ 3964 #define MC_CMD_PTP_OUT_STATUS_CLOCK_FREQ_OFST 0 3965 /* Number of packets transmitted and timestamped */ 3966 #define MC_CMD_PTP_OUT_STATUS_STATS_TX_OFST 4 3967 /* Number of packets received and timestamped */ 3968 #define MC_CMD_PTP_OUT_STATUS_STATS_RX_OFST 8 3969 /* Number of packets timestamped by the FPGA */ 3970 #define MC_CMD_PTP_OUT_STATUS_STATS_TS_OFST 12 3971 /* Number of packets filter matched */ 3972 #define MC_CMD_PTP_OUT_STATUS_STATS_FM_OFST 16 3973 /* Number of packets not filter matched */ 3974 #define MC_CMD_PTP_OUT_STATUS_STATS_NFM_OFST 20 3975 /* Number of PPS overflows (noise on input?) */ 3976 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFLOW_OFST 24 3977 /* Number of PPS bad periods */ 3978 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_BAD_OFST 28 3979 /* Minimum period of PPS pulse in nanoseconds */ 3980 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MIN_OFST 32 3981 /* Maximum period of PPS pulse in nanoseconds */ 3982 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MAX_OFST 36 3983 /* Last period of PPS pulse in nanoseconds */ 3984 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_LAST_OFST 40 3985 /* Mean period of PPS pulse in nanoseconds */ 3986 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MEAN_OFST 44 3987 /* Minimum offset of PPS pulse in nanoseconds (signed) */ 3988 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MIN_OFST 48 3989 /* Maximum offset of PPS pulse in nanoseconds (signed) */ 3990 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MAX_OFST 52 3991 /* Last offset of PPS pulse in nanoseconds (signed) */ 3992 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_LAST_OFST 56 3993 /* Mean offset of PPS pulse in nanoseconds (signed) */ 3994 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MEAN_OFST 60 3995 3996 /* MC_CMD_PTP_OUT_SYNCHRONIZE msgresponse */ 3997 #define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMIN 20 3998 #define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMAX 240 3999 #define MC_CMD_PTP_OUT_SYNCHRONIZE_LEN(num) (0+20*(num)) 4000 /* A set of host and NIC times */ 4001 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_OFST 0 4002 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_LEN 20 4003 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MINNUM 1 4004 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MAXNUM 12 4005 /* Host time immediately before NIC's hardware clock read */ 4006 #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTSTART_OFST 0 4007 /* Value of seconds timestamp */ 4008 #define MC_CMD_PTP_OUT_SYNCHRONIZE_SECONDS_OFST 4 4009 /* Timestamp major value */ 4010 #define MC_CMD_PTP_OUT_SYNCHRONIZE_MAJOR_OFST 4 4011 /* Value of nanoseconds timestamp */ 4012 #define MC_CMD_PTP_OUT_SYNCHRONIZE_NANOSECONDS_OFST 8 4013 /* Timestamp minor value */ 4014 #define MC_CMD_PTP_OUT_SYNCHRONIZE_MINOR_OFST 8 4015 /* Host time immediately after NIC's hardware clock read */ 4016 #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTEND_OFST 12 4017 /* Number of nanoseconds waited after reading NIC's hardware clock */ 4018 #define MC_CMD_PTP_OUT_SYNCHRONIZE_WAITNS_OFST 16 4019 4020 /* MC_CMD_PTP_OUT_MANFTEST_BASIC msgresponse */ 4021 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_LEN 8 4022 /* Results of testing */ 4023 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_RESULT_OFST 0 4024 /* enum: Successful test */ 4025 #define MC_CMD_PTP_MANF_SUCCESS 0x0 4026 /* enum: FPGA load failed */ 4027 #define MC_CMD_PTP_MANF_FPGA_LOAD 0x1 4028 /* enum: FPGA version invalid */ 4029 #define MC_CMD_PTP_MANF_FPGA_VERSION 0x2 4030 /* enum: FPGA registers incorrect */ 4031 #define MC_CMD_PTP_MANF_FPGA_REGISTERS 0x3 4032 /* enum: Oscillator possibly not working? */ 4033 #define MC_CMD_PTP_MANF_OSCILLATOR 0x4 4034 /* enum: Timestamps not increasing */ 4035 #define MC_CMD_PTP_MANF_TIMESTAMPS 0x5 4036 /* enum: Mismatched packet count */ 4037 #define MC_CMD_PTP_MANF_PACKET_COUNT 0x6 4038 /* enum: Mismatched packet count (Siena filter and FPGA) */ 4039 #define MC_CMD_PTP_MANF_FILTER_COUNT 0x7 4040 /* enum: Not enough packets to perform timestamp check */ 4041 #define MC_CMD_PTP_MANF_PACKET_ENOUGH 0x8 4042 /* enum: Timestamp trigger GPIO not working */ 4043 #define MC_CMD_PTP_MANF_GPIO_TRIGGER 0x9 4044 /* enum: Insufficient PPS events to perform checks */ 4045 #define MC_CMD_PTP_MANF_PPS_ENOUGH 0xa 4046 /* enum: PPS time event period not sufficiently close to 1s. */ 4047 #define MC_CMD_PTP_MANF_PPS_PERIOD 0xb 4048 /* enum: PPS time event nS reading not sufficiently close to zero. */ 4049 #define MC_CMD_PTP_MANF_PPS_NS 0xc 4050 /* enum: PTP peripheral registers incorrect */ 4051 #define MC_CMD_PTP_MANF_REGISTERS 0xd 4052 /* enum: Failed to read time from PTP peripheral */ 4053 #define MC_CMD_PTP_MANF_CLOCK_READ 0xe 4054 /* Presence of external oscillator */ 4055 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_EXTOSC_OFST 4 4056 4057 /* MC_CMD_PTP_OUT_MANFTEST_PACKET msgresponse */ 4058 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_LEN 12 4059 /* Results of testing */ 4060 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_RESULT_OFST 0 4061 /* Number of packets received by FPGA */ 4062 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FPGACOUNT_OFST 4 4063 /* Number of packets received by Siena filters */ 4064 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FILTERCOUNT_OFST 8 4065 4066 /* MC_CMD_PTP_OUT_FPGAREAD msgresponse */ 4067 #define MC_CMD_PTP_OUT_FPGAREAD_LENMIN 1 4068 #define MC_CMD_PTP_OUT_FPGAREAD_LENMAX 252 4069 #define MC_CMD_PTP_OUT_FPGAREAD_LEN(num) (0+1*(num)) 4070 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_OFST 0 4071 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_LEN 1 4072 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MINNUM 1 4073 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MAXNUM 252 4074 4075 /* MC_CMD_PTP_OUT_GET_TIME_FORMAT msgresponse */ 4076 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_LEN 4 4077 /* Time format required/used by for this NIC. Applies to all PTP MCDI 4078 * operations that pass times between the host and firmware. If this operation 4079 * is not supported (older firmware) a format of seconds and nanoseconds should 4080 * be assumed. 4081 */ 4082 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_FORMAT_OFST 0 4083 /* enum: Times are in seconds and nanoseconds */ 4084 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_NANOSECONDS 0x0 4085 /* enum: Major register has units of 16 second per tick, minor 8 ns per tick */ 4086 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_16SECONDS_8NANOSECONDS 0x1 4087 /* enum: Major register has units of seconds, minor 2^-27s per tick */ 4088 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_27FRACTION 0x2 4089 4090 /* MC_CMD_PTP_OUT_GET_ATTRIBUTES msgresponse */ 4091 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_LEN 24 4092 /* Time format required/used by for this NIC. Applies to all PTP MCDI 4093 * operations that pass times between the host and firmware. If this operation 4094 * is not supported (older firmware) a format of seconds and nanoseconds should 4095 * be assumed. 4096 */ 4097 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_TIME_FORMAT_OFST 0 4098 /* enum: Times are in seconds and nanoseconds */ 4099 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_NANOSECONDS 0x0 4100 /* enum: Major register has units of 16 second per tick, minor 8 ns per tick */ 4101 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_16SECONDS_8NANOSECONDS 0x1 4102 /* enum: Major register has units of seconds, minor 2^-27s per tick */ 4103 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_27FRACTION 0x2 4104 /* Minimum acceptable value for a corrected synchronization timeset. When 4105 * comparing host and NIC clock times, the MC returns a set of samples that 4106 * contain the host start and end time, the MC time when the host start was 4107 * detected and the time the MC waited between reading the time and detecting 4108 * the host end. The corrected sync window is the difference between the host 4109 * end and start times minus the time that the MC waited for host end. 4110 */ 4111 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SYNC_WINDOW_MIN_OFST 4 4112 /* Various PTP capabilities */ 4113 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_CAPABILITIES_OFST 8 4114 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_LBN 0 4115 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_WIDTH 1 4116 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED0_OFST 12 4117 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED1_OFST 16 4118 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED2_OFST 20 4119 4120 /* MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS msgresponse */ 4121 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_LEN 16 4122 /* Uncorrected error on PTP transmit timestamps in NIC clock format */ 4123 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_TRANSMIT_OFST 0 4124 /* Uncorrected error on PTP receive timestamps in NIC clock format */ 4125 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_RECEIVE_OFST 4 4126 /* Uncorrected error on PPS output in NIC clock format */ 4127 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_OUT_OFST 8 4128 /* Uncorrected error on PPS input in NIC clock format */ 4129 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_IN_OFST 12 4130 4131 /* MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2 msgresponse */ 4132 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_LEN 24 4133 /* Uncorrected error on PTP transmit timestamps in NIC clock format */ 4134 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_TX_OFST 0 4135 /* Uncorrected error on PTP receive timestamps in NIC clock format */ 4136 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_RX_OFST 4 4137 /* Uncorrected error on PPS output in NIC clock format */ 4138 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_OUT_OFST 8 4139 /* Uncorrected error on PPS input in NIC clock format */ 4140 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_IN_OFST 12 4141 /* Uncorrected error on non-PTP transmit timestamps in NIC clock format */ 4142 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_TX_OFST 16 4143 /* Uncorrected error on non-PTP receive timestamps in NIC clock format */ 4144 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_RX_OFST 20 4145 4146 /* MC_CMD_PTP_OUT_MANFTEST_PPS msgresponse */ 4147 #define MC_CMD_PTP_OUT_MANFTEST_PPS_LEN 4 4148 /* Results of testing */ 4149 #define MC_CMD_PTP_OUT_MANFTEST_PPS_TEST_RESULT_OFST 0 4150 /* Enum values, see field(s): */ 4151 /* MC_CMD_PTP_OUT_MANFTEST_BASIC/TEST_RESULT */ 4152 4153 /* MC_CMD_PTP_OUT_SET_SYNC_STATUS msgresponse */ 4154 #define MC_CMD_PTP_OUT_SET_SYNC_STATUS_LEN 0 4155 4156 4157 /***********************************/ 4158 /* MC_CMD_CSR_READ32 4159 * Read 32bit words from the indirect memory map. 4160 */ 4161 #define MC_CMD_CSR_READ32 0xc 4162 #undef MC_CMD_0xc_PRIVILEGE_CTG 4163 4164 #define MC_CMD_0xc_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4165 4166 /* MC_CMD_CSR_READ32_IN msgrequest */ 4167 #define MC_CMD_CSR_READ32_IN_LEN 12 4168 /* Address */ 4169 #define MC_CMD_CSR_READ32_IN_ADDR_OFST 0 4170 #define MC_CMD_CSR_READ32_IN_STEP_OFST 4 4171 #define MC_CMD_CSR_READ32_IN_NUMWORDS_OFST 8 4172 4173 /* MC_CMD_CSR_READ32_OUT msgresponse */ 4174 #define MC_CMD_CSR_READ32_OUT_LENMIN 4 4175 #define MC_CMD_CSR_READ32_OUT_LENMAX 252 4176 #define MC_CMD_CSR_READ32_OUT_LEN(num) (0+4*(num)) 4177 /* The last dword is the status, not a value read */ 4178 #define MC_CMD_CSR_READ32_OUT_BUFFER_OFST 0 4179 #define MC_CMD_CSR_READ32_OUT_BUFFER_LEN 4 4180 #define MC_CMD_CSR_READ32_OUT_BUFFER_MINNUM 1 4181 #define MC_CMD_CSR_READ32_OUT_BUFFER_MAXNUM 63 4182 4183 4184 /***********************************/ 4185 /* MC_CMD_CSR_WRITE32 4186 * Write 32bit dwords to the indirect memory map. 4187 */ 4188 #define MC_CMD_CSR_WRITE32 0xd 4189 #undef MC_CMD_0xd_PRIVILEGE_CTG 4190 4191 #define MC_CMD_0xd_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4192 4193 /* MC_CMD_CSR_WRITE32_IN msgrequest */ 4194 #define MC_CMD_CSR_WRITE32_IN_LENMIN 12 4195 #define MC_CMD_CSR_WRITE32_IN_LENMAX 252 4196 #define MC_CMD_CSR_WRITE32_IN_LEN(num) (8+4*(num)) 4197 /* Address */ 4198 #define MC_CMD_CSR_WRITE32_IN_ADDR_OFST 0 4199 #define MC_CMD_CSR_WRITE32_IN_STEP_OFST 4 4200 #define MC_CMD_CSR_WRITE32_IN_BUFFER_OFST 8 4201 #define MC_CMD_CSR_WRITE32_IN_BUFFER_LEN 4 4202 #define MC_CMD_CSR_WRITE32_IN_BUFFER_MINNUM 1 4203 #define MC_CMD_CSR_WRITE32_IN_BUFFER_MAXNUM 61 4204 4205 /* MC_CMD_CSR_WRITE32_OUT msgresponse */ 4206 #define MC_CMD_CSR_WRITE32_OUT_LEN 4 4207 #define MC_CMD_CSR_WRITE32_OUT_STATUS_OFST 0 4208 4209 4210 /***********************************/ 4211 /* MC_CMD_HP 4212 * These commands are used for HP related features. They are grouped under one 4213 * MCDI command to avoid creating too many MCDI commands. 4214 */ 4215 #define MC_CMD_HP 0x54 4216 #undef MC_CMD_0x54_PRIVILEGE_CTG 4217 4218 #define MC_CMD_0x54_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4219 4220 /* MC_CMD_HP_IN msgrequest */ 4221 #define MC_CMD_HP_IN_LEN 16 4222 /* HP OCSD sub-command. When address is not NULL, request activation of OCSD at 4223 * the specified address with the specified interval.When address is NULL, 4224 * INTERVAL is interpreted as a command: 0: stop OCSD / 1: Report OCSD current 4225 * state / 2: (debug) Show temperature reported by one of the supported 4226 * sensors. 4227 */ 4228 #define MC_CMD_HP_IN_SUBCMD_OFST 0 4229 /* enum: OCSD (Option Card Sensor Data) sub-command. */ 4230 #define MC_CMD_HP_IN_OCSD_SUBCMD 0x0 4231 /* enum: Last known valid HP sub-command. */ 4232 #define MC_CMD_HP_IN_LAST_SUBCMD 0x0 4233 /* The address to the array of sensor fields. (Or NULL to use a sub-command.) 4234 */ 4235 #define MC_CMD_HP_IN_OCSD_ADDR_OFST 4 4236 #define MC_CMD_HP_IN_OCSD_ADDR_LEN 8 4237 #define MC_CMD_HP_IN_OCSD_ADDR_LO_OFST 4 4238 #define MC_CMD_HP_IN_OCSD_ADDR_HI_OFST 8 4239 /* The requested update interval, in seconds. (Or the sub-command if ADDR is 4240 * NULL.) 4241 */ 4242 #define MC_CMD_HP_IN_OCSD_INTERVAL_OFST 12 4243 4244 /* MC_CMD_HP_OUT msgresponse */ 4245 #define MC_CMD_HP_OUT_LEN 4 4246 #define MC_CMD_HP_OUT_OCSD_STATUS_OFST 0 4247 /* enum: OCSD stopped for this card. */ 4248 #define MC_CMD_HP_OUT_OCSD_STOPPED 0x1 4249 /* enum: OCSD was successfully started with the address provided. */ 4250 #define MC_CMD_HP_OUT_OCSD_STARTED 0x2 4251 /* enum: OCSD was already started for this card. */ 4252 #define MC_CMD_HP_OUT_OCSD_ALREADY_STARTED 0x3 4253 4254 4255 /***********************************/ 4256 /* MC_CMD_STACKINFO 4257 * Get stack information. 4258 */ 4259 #define MC_CMD_STACKINFO 0xf 4260 #undef MC_CMD_0xf_PRIVILEGE_CTG 4261 4262 #define MC_CMD_0xf_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4263 4264 /* MC_CMD_STACKINFO_IN msgrequest */ 4265 #define MC_CMD_STACKINFO_IN_LEN 0 4266 4267 /* MC_CMD_STACKINFO_OUT msgresponse */ 4268 #define MC_CMD_STACKINFO_OUT_LENMIN 12 4269 #define MC_CMD_STACKINFO_OUT_LENMAX 252 4270 #define MC_CMD_STACKINFO_OUT_LEN(num) (0+12*(num)) 4271 /* (thread ptr, stack size, free space) for each thread in system */ 4272 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_OFST 0 4273 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_LEN 12 4274 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_MINNUM 1 4275 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_MAXNUM 21 4276 4277 4278 /***********************************/ 4279 /* MC_CMD_MDIO_READ 4280 * MDIO register read. 4281 */ 4282 #define MC_CMD_MDIO_READ 0x10 4283 #undef MC_CMD_0x10_PRIVILEGE_CTG 4284 4285 #define MC_CMD_0x10_PRIVILEGE_CTG SRIOV_CTG_GENERAL 4286 4287 /* MC_CMD_MDIO_READ_IN msgrequest */ 4288 #define MC_CMD_MDIO_READ_IN_LEN 16 4289 /* Bus number; there are two MDIO buses: one for the internal PHY, and one for 4290 * external devices. 4291 */ 4292 #define MC_CMD_MDIO_READ_IN_BUS_OFST 0 4293 /* enum: Internal. */ 4294 #define MC_CMD_MDIO_BUS_INTERNAL 0x0 4295 /* enum: External. */ 4296 #define MC_CMD_MDIO_BUS_EXTERNAL 0x1 4297 /* Port address */ 4298 #define MC_CMD_MDIO_READ_IN_PRTAD_OFST 4 4299 /* Device Address or clause 22. */ 4300 #define MC_CMD_MDIO_READ_IN_DEVAD_OFST 8 4301 /* enum: By default all the MCDI MDIO operations perform clause45 mode. If you 4302 * want to use clause22 then set DEVAD = MC_CMD_MDIO_CLAUSE22. 4303 */ 4304 #define MC_CMD_MDIO_CLAUSE22 0x20 4305 /* Address */ 4306 #define MC_CMD_MDIO_READ_IN_ADDR_OFST 12 4307 4308 /* MC_CMD_MDIO_READ_OUT msgresponse */ 4309 #define MC_CMD_MDIO_READ_OUT_LEN 8 4310 /* Value */ 4311 #define MC_CMD_MDIO_READ_OUT_VALUE_OFST 0 4312 /* Status the MDIO commands return the raw status bits from the MDIO block. A 4313 * "good" transaction should have the DONE bit set and all other bits clear. 4314 */ 4315 #define MC_CMD_MDIO_READ_OUT_STATUS_OFST 4 4316 /* enum: Good. */ 4317 #define MC_CMD_MDIO_STATUS_GOOD 0x8 4318 4319 4320 /***********************************/ 4321 /* MC_CMD_MDIO_WRITE 4322 * MDIO register write. 4323 */ 4324 #define MC_CMD_MDIO_WRITE 0x11 4325 #undef MC_CMD_0x11_PRIVILEGE_CTG 4326 4327 #define MC_CMD_0x11_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4328 4329 /* MC_CMD_MDIO_WRITE_IN msgrequest */ 4330 #define MC_CMD_MDIO_WRITE_IN_LEN 20 4331 /* Bus number; there are two MDIO buses: one for the internal PHY, and one for 4332 * external devices. 4333 */ 4334 #define MC_CMD_MDIO_WRITE_IN_BUS_OFST 0 4335 /* enum: Internal. */ 4336 /* MC_CMD_MDIO_BUS_INTERNAL 0x0 */ 4337 /* enum: External. */ 4338 /* MC_CMD_MDIO_BUS_EXTERNAL 0x1 */ 4339 /* Port address */ 4340 #define MC_CMD_MDIO_WRITE_IN_PRTAD_OFST 4 4341 /* Device Address or clause 22. */ 4342 #define MC_CMD_MDIO_WRITE_IN_DEVAD_OFST 8 4343 /* enum: By default all the MCDI MDIO operations perform clause45 mode. If you 4344 * want to use clause22 then set DEVAD = MC_CMD_MDIO_CLAUSE22. 4345 */ 4346 /* MC_CMD_MDIO_CLAUSE22 0x20 */ 4347 /* Address */ 4348 #define MC_CMD_MDIO_WRITE_IN_ADDR_OFST 12 4349 /* Value */ 4350 #define MC_CMD_MDIO_WRITE_IN_VALUE_OFST 16 4351 4352 /* MC_CMD_MDIO_WRITE_OUT msgresponse */ 4353 #define MC_CMD_MDIO_WRITE_OUT_LEN 4 4354 /* Status; the MDIO commands return the raw status bits from the MDIO block. A 4355 * "good" transaction should have the DONE bit set and all other bits clear. 4356 */ 4357 #define MC_CMD_MDIO_WRITE_OUT_STATUS_OFST 0 4358 /* enum: Good. */ 4359 /* MC_CMD_MDIO_STATUS_GOOD 0x8 */ 4360 4361 4362 /***********************************/ 4363 /* MC_CMD_DBI_WRITE 4364 * Write DBI register(s). 4365 */ 4366 #define MC_CMD_DBI_WRITE 0x12 4367 #undef MC_CMD_0x12_PRIVILEGE_CTG 4368 4369 #define MC_CMD_0x12_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4370 4371 /* MC_CMD_DBI_WRITE_IN msgrequest */ 4372 #define MC_CMD_DBI_WRITE_IN_LENMIN 12 4373 #define MC_CMD_DBI_WRITE_IN_LENMAX 252 4374 #define MC_CMD_DBI_WRITE_IN_LEN(num) (0+12*(num)) 4375 /* Each write op consists of an address (offset 0), byte enable/VF/CS2 (offset 4376 * 32) and value (offset 64). See MC_CMD_DBIWROP_TYPEDEF. 4377 */ 4378 #define MC_CMD_DBI_WRITE_IN_DBIWROP_OFST 0 4379 #define MC_CMD_DBI_WRITE_IN_DBIWROP_LEN 12 4380 #define MC_CMD_DBI_WRITE_IN_DBIWROP_MINNUM 1 4381 #define MC_CMD_DBI_WRITE_IN_DBIWROP_MAXNUM 21 4382 4383 /* MC_CMD_DBI_WRITE_OUT msgresponse */ 4384 #define MC_CMD_DBI_WRITE_OUT_LEN 0 4385 4386 /* MC_CMD_DBIWROP_TYPEDEF structuredef */ 4387 #define MC_CMD_DBIWROP_TYPEDEF_LEN 12 4388 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST 0 4389 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_LBN 0 4390 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_WIDTH 32 4391 #define MC_CMD_DBIWROP_TYPEDEF_PARMS_OFST 4 4392 #define MC_CMD_DBIWROP_TYPEDEF_VF_NUM_LBN 16 4393 #define MC_CMD_DBIWROP_TYPEDEF_VF_NUM_WIDTH 16 4394 #define MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_LBN 15 4395 #define MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_WIDTH 1 4396 #define MC_CMD_DBIWROP_TYPEDEF_CS2_LBN 14 4397 #define MC_CMD_DBIWROP_TYPEDEF_CS2_WIDTH 1 4398 #define MC_CMD_DBIWROP_TYPEDEF_PARMS_LBN 32 4399 #define MC_CMD_DBIWROP_TYPEDEF_PARMS_WIDTH 32 4400 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST 8 4401 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_LBN 64 4402 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_WIDTH 32 4403 4404 4405 /***********************************/ 4406 /* MC_CMD_PORT_READ32 4407 * Read a 32-bit register from the indirect port register map. The port to 4408 * access is implied by the Shared memory channel used. 4409 */ 4410 #define MC_CMD_PORT_READ32 0x14 4411 4412 /* MC_CMD_PORT_READ32_IN msgrequest */ 4413 #define MC_CMD_PORT_READ32_IN_LEN 4 4414 /* Address */ 4415 #define MC_CMD_PORT_READ32_IN_ADDR_OFST 0 4416 4417 /* MC_CMD_PORT_READ32_OUT msgresponse */ 4418 #define MC_CMD_PORT_READ32_OUT_LEN 8 4419 /* Value */ 4420 #define MC_CMD_PORT_READ32_OUT_VALUE_OFST 0 4421 /* Status */ 4422 #define MC_CMD_PORT_READ32_OUT_STATUS_OFST 4 4423 4424 4425 /***********************************/ 4426 /* MC_CMD_PORT_WRITE32 4427 * Write a 32-bit register to the indirect port register map. The port to 4428 * access is implied by the Shared memory channel used. 4429 */ 4430 #define MC_CMD_PORT_WRITE32 0x15 4431 4432 /* MC_CMD_PORT_WRITE32_IN msgrequest */ 4433 #define MC_CMD_PORT_WRITE32_IN_LEN 8 4434 /* Address */ 4435 #define MC_CMD_PORT_WRITE32_IN_ADDR_OFST 0 4436 /* Value */ 4437 #define MC_CMD_PORT_WRITE32_IN_VALUE_OFST 4 4438 4439 /* MC_CMD_PORT_WRITE32_OUT msgresponse */ 4440 #define MC_CMD_PORT_WRITE32_OUT_LEN 4 4441 /* Status */ 4442 #define MC_CMD_PORT_WRITE32_OUT_STATUS_OFST 0 4443 4444 4445 /***********************************/ 4446 /* MC_CMD_PORT_READ128 4447 * Read a 128-bit register from the indirect port register map. The port to 4448 * access is implied by the Shared memory channel used. 4449 */ 4450 #define MC_CMD_PORT_READ128 0x16 4451 4452 /* MC_CMD_PORT_READ128_IN msgrequest */ 4453 #define MC_CMD_PORT_READ128_IN_LEN 4 4454 /* Address */ 4455 #define MC_CMD_PORT_READ128_IN_ADDR_OFST 0 4456 4457 /* MC_CMD_PORT_READ128_OUT msgresponse */ 4458 #define MC_CMD_PORT_READ128_OUT_LEN 20 4459 /* Value */ 4460 #define MC_CMD_PORT_READ128_OUT_VALUE_OFST 0 4461 #define MC_CMD_PORT_READ128_OUT_VALUE_LEN 16 4462 /* Status */ 4463 #define MC_CMD_PORT_READ128_OUT_STATUS_OFST 16 4464 4465 4466 /***********************************/ 4467 /* MC_CMD_PORT_WRITE128 4468 * Write a 128-bit register to the indirect port register map. The port to 4469 * access is implied by the Shared memory channel used. 4470 */ 4471 #define MC_CMD_PORT_WRITE128 0x17 4472 4473 /* MC_CMD_PORT_WRITE128_IN msgrequest */ 4474 #define MC_CMD_PORT_WRITE128_IN_LEN 20 4475 /* Address */ 4476 #define MC_CMD_PORT_WRITE128_IN_ADDR_OFST 0 4477 /* Value */ 4478 #define MC_CMD_PORT_WRITE128_IN_VALUE_OFST 4 4479 #define MC_CMD_PORT_WRITE128_IN_VALUE_LEN 16 4480 4481 /* MC_CMD_PORT_WRITE128_OUT msgresponse */ 4482 #define MC_CMD_PORT_WRITE128_OUT_LEN 4 4483 /* Status */ 4484 #define MC_CMD_PORT_WRITE128_OUT_STATUS_OFST 0 4485 4486 /* MC_CMD_CAPABILITIES structuredef */ 4487 #define MC_CMD_CAPABILITIES_LEN 4 4488 /* Small buf table. */ 4489 #define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_LBN 0 4490 #define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_WIDTH 1 4491 /* Turbo mode (for Maranello). */ 4492 #define MC_CMD_CAPABILITIES_TURBO_LBN 1 4493 #define MC_CMD_CAPABILITIES_TURBO_WIDTH 1 4494 /* Turbo mode active (for Maranello). */ 4495 #define MC_CMD_CAPABILITIES_TURBO_ACTIVE_LBN 2 4496 #define MC_CMD_CAPABILITIES_TURBO_ACTIVE_WIDTH 1 4497 /* PTP offload. */ 4498 #define MC_CMD_CAPABILITIES_PTP_LBN 3 4499 #define MC_CMD_CAPABILITIES_PTP_WIDTH 1 4500 /* AOE mode. */ 4501 #define MC_CMD_CAPABILITIES_AOE_LBN 4 4502 #define MC_CMD_CAPABILITIES_AOE_WIDTH 1 4503 /* AOE mode active. */ 4504 #define MC_CMD_CAPABILITIES_AOE_ACTIVE_LBN 5 4505 #define MC_CMD_CAPABILITIES_AOE_ACTIVE_WIDTH 1 4506 /* AOE mode active. */ 4507 #define MC_CMD_CAPABILITIES_FC_ACTIVE_LBN 6 4508 #define MC_CMD_CAPABILITIES_FC_ACTIVE_WIDTH 1 4509 #define MC_CMD_CAPABILITIES_RESERVED_LBN 7 4510 #define MC_CMD_CAPABILITIES_RESERVED_WIDTH 25 4511 4512 4513 /***********************************/ 4514 /* MC_CMD_GET_BOARD_CFG 4515 * Returns the MC firmware configuration structure. 4516 */ 4517 #define MC_CMD_GET_BOARD_CFG 0x18 4518 #undef MC_CMD_0x18_PRIVILEGE_CTG 4519 4520 #define MC_CMD_0x18_PRIVILEGE_CTG SRIOV_CTG_GENERAL 4521 4522 /* MC_CMD_GET_BOARD_CFG_IN msgrequest */ 4523 #define MC_CMD_GET_BOARD_CFG_IN_LEN 0 4524 4525 /* MC_CMD_GET_BOARD_CFG_OUT msgresponse */ 4526 #define MC_CMD_GET_BOARD_CFG_OUT_LENMIN 96 4527 #define MC_CMD_GET_BOARD_CFG_OUT_LENMAX 136 4528 #define MC_CMD_GET_BOARD_CFG_OUT_LEN(num) (72+2*(num)) 4529 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_OFST 0 4530 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_OFST 4 4531 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_LEN 32 4532 /* See MC_CMD_CAPABILITIES */ 4533 #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT0_OFST 36 4534 /* See MC_CMD_CAPABILITIES */ 4535 #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT1_OFST 40 4536 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_OFST 44 4537 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_LEN 6 4538 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_OFST 50 4539 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_LEN 6 4540 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT0_OFST 56 4541 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT1_OFST 60 4542 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT0_OFST 64 4543 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT1_OFST 68 4544 /* This field contains a 16-bit value for each of the types of NVRAM area. The 4545 * values are defined in the firmware/mc/platform/.c file for a specific board 4546 * type, but otherwise have no meaning to the MC; they are used by the driver 4547 * to manage selection of appropriate firmware updates. 4548 */ 4549 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_OFST 72 4550 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_LEN 2 4551 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MINNUM 12 4552 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM 32 4553 4554 4555 /***********************************/ 4556 /* MC_CMD_DBI_READX 4557 * Read DBI register(s) -- extended functionality 4558 */ 4559 #define MC_CMD_DBI_READX 0x19 4560 #undef MC_CMD_0x19_PRIVILEGE_CTG 4561 4562 #define MC_CMD_0x19_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4563 4564 /* MC_CMD_DBI_READX_IN msgrequest */ 4565 #define MC_CMD_DBI_READX_IN_LENMIN 8 4566 #define MC_CMD_DBI_READX_IN_LENMAX 248 4567 #define MC_CMD_DBI_READX_IN_LEN(num) (0+8*(num)) 4568 /* Each Read op consists of an address (offset 0), VF/CS2) */ 4569 #define MC_CMD_DBI_READX_IN_DBIRDOP_OFST 0 4570 #define MC_CMD_DBI_READX_IN_DBIRDOP_LEN 8 4571 #define MC_CMD_DBI_READX_IN_DBIRDOP_LO_OFST 0 4572 #define MC_CMD_DBI_READX_IN_DBIRDOP_HI_OFST 4 4573 #define MC_CMD_DBI_READX_IN_DBIRDOP_MINNUM 1 4574 #define MC_CMD_DBI_READX_IN_DBIRDOP_MAXNUM 31 4575 4576 /* MC_CMD_DBI_READX_OUT msgresponse */ 4577 #define MC_CMD_DBI_READX_OUT_LENMIN 4 4578 #define MC_CMD_DBI_READX_OUT_LENMAX 252 4579 #define MC_CMD_DBI_READX_OUT_LEN(num) (0+4*(num)) 4580 /* Value */ 4581 #define MC_CMD_DBI_READX_OUT_VALUE_OFST 0 4582 #define MC_CMD_DBI_READX_OUT_VALUE_LEN 4 4583 #define MC_CMD_DBI_READX_OUT_VALUE_MINNUM 1 4584 #define MC_CMD_DBI_READX_OUT_VALUE_MAXNUM 63 4585 4586 /* MC_CMD_DBIRDOP_TYPEDEF structuredef */ 4587 #define MC_CMD_DBIRDOP_TYPEDEF_LEN 8 4588 #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_OFST 0 4589 #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_LBN 0 4590 #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_WIDTH 32 4591 #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_OFST 4 4592 #define MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_LBN 16 4593 #define MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_WIDTH 16 4594 #define MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_LBN 15 4595 #define MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_WIDTH 1 4596 #define MC_CMD_DBIRDOP_TYPEDEF_CS2_LBN 14 4597 #define MC_CMD_DBIRDOP_TYPEDEF_CS2_WIDTH 1 4598 #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_LBN 32 4599 #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_WIDTH 32 4600 4601 4602 /***********************************/ 4603 /* MC_CMD_SET_RAND_SEED 4604 * Set the 16byte seed for the MC pseudo-random generator. 4605 */ 4606 #define MC_CMD_SET_RAND_SEED 0x1a 4607 #undef MC_CMD_0x1a_PRIVILEGE_CTG 4608 4609 #define MC_CMD_0x1a_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4610 4611 /* MC_CMD_SET_RAND_SEED_IN msgrequest */ 4612 #define MC_CMD_SET_RAND_SEED_IN_LEN 16 4613 /* Seed value. */ 4614 #define MC_CMD_SET_RAND_SEED_IN_SEED_OFST 0 4615 #define MC_CMD_SET_RAND_SEED_IN_SEED_LEN 16 4616 4617 /* MC_CMD_SET_RAND_SEED_OUT msgresponse */ 4618 #define MC_CMD_SET_RAND_SEED_OUT_LEN 0 4619 4620 4621 /***********************************/ 4622 /* MC_CMD_LTSSM_HIST 4623 * Retrieve the history of the LTSSM, if the build supports it. 4624 */ 4625 #define MC_CMD_LTSSM_HIST 0x1b 4626 4627 /* MC_CMD_LTSSM_HIST_IN msgrequest */ 4628 #define MC_CMD_LTSSM_HIST_IN_LEN 0 4629 4630 /* MC_CMD_LTSSM_HIST_OUT msgresponse */ 4631 #define MC_CMD_LTSSM_HIST_OUT_LENMIN 0 4632 #define MC_CMD_LTSSM_HIST_OUT_LENMAX 252 4633 #define MC_CMD_LTSSM_HIST_OUT_LEN(num) (0+4*(num)) 4634 /* variable number of LTSSM values, as bytes. The history is read-to-clear. */ 4635 #define MC_CMD_LTSSM_HIST_OUT_DATA_OFST 0 4636 #define MC_CMD_LTSSM_HIST_OUT_DATA_LEN 4 4637 #define MC_CMD_LTSSM_HIST_OUT_DATA_MINNUM 0 4638 #define MC_CMD_LTSSM_HIST_OUT_DATA_MAXNUM 63 4639 4640 4641 /***********************************/ 4642 /* MC_CMD_DRV_ATTACH 4643 * Inform MCPU that this port is managed on the host (i.e. driver active). For 4644 * Huntington, also request the preferred datapath firmware to use if possible 4645 * (it may not be possible for this request to be fulfilled; the driver must 4646 * issue a subsequent MC_CMD_GET_CAPABILITIES command to determine which 4647 * features are actually available). The FIRMWARE_ID field is ignored by older 4648 * platforms. 4649 */ 4650 #define MC_CMD_DRV_ATTACH 0x1c 4651 #undef MC_CMD_0x1c_PRIVILEGE_CTG 4652 4653 #define MC_CMD_0x1c_PRIVILEGE_CTG SRIOV_CTG_GENERAL 4654 4655 /* MC_CMD_DRV_ATTACH_IN msgrequest */ 4656 #define MC_CMD_DRV_ATTACH_IN_LEN 12 4657 /* new state to set if UPDATE=1 */ 4658 #define MC_CMD_DRV_ATTACH_IN_NEW_STATE_OFST 0 4659 #define MC_CMD_DRV_ATTACH_LBN 0 4660 #define MC_CMD_DRV_ATTACH_WIDTH 1 4661 #define MC_CMD_DRV_PREBOOT_LBN 1 4662 #define MC_CMD_DRV_PREBOOT_WIDTH 1 4663 /* 1 to set new state, or 0 to just report the existing state */ 4664 #define MC_CMD_DRV_ATTACH_IN_UPDATE_OFST 4 4665 /* preferred datapath firmware (for Huntington; ignored for Siena) */ 4666 #define MC_CMD_DRV_ATTACH_IN_FIRMWARE_ID_OFST 8 4667 /* enum: Prefer to use full featured firmware */ 4668 #define MC_CMD_FW_FULL_FEATURED 0x0 4669 /* enum: Prefer to use firmware with fewer features but lower latency */ 4670 #define MC_CMD_FW_LOW_LATENCY 0x1 4671 /* enum: Prefer to use firmware for SolarCapture packed stream mode */ 4672 #define MC_CMD_FW_PACKED_STREAM 0x2 4673 /* enum: Prefer to use firmware with fewer features and simpler TX event 4674 * batching but higher TX packet rate 4675 */ 4676 #define MC_CMD_FW_HIGH_TX_RATE 0x3 4677 /* enum: Reserved value */ 4678 #define MC_CMD_FW_PACKED_STREAM_HASH_MODE_1 0x4 4679 /* enum: Only this option is allowed for non-admin functions */ 4680 #define MC_CMD_FW_DONT_CARE 0xffffffff 4681 4682 /* MC_CMD_DRV_ATTACH_OUT msgresponse */ 4683 #define MC_CMD_DRV_ATTACH_OUT_LEN 4 4684 /* previous or existing state, see the bitmask at NEW_STATE */ 4685 #define MC_CMD_DRV_ATTACH_OUT_OLD_STATE_OFST 0 4686 4687 /* MC_CMD_DRV_ATTACH_EXT_OUT msgresponse */ 4688 #define MC_CMD_DRV_ATTACH_EXT_OUT_LEN 8 4689 /* previous or existing state, see the bitmask at NEW_STATE */ 4690 #define MC_CMD_DRV_ATTACH_EXT_OUT_OLD_STATE_OFST 0 4691 /* Flags associated with this function */ 4692 #define MC_CMD_DRV_ATTACH_EXT_OUT_FUNC_FLAGS_OFST 4 4693 /* enum: Labels the lowest-numbered function visible to the OS */ 4694 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY 0x0 4695 /* enum: The function can control the link state of the physical port it is 4696 * bound to. 4697 */ 4698 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL 0x1 4699 /* enum: The function can perform privileged operations */ 4700 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TRUSTED 0x2 4701 /* enum: The function does not have an active port associated with it. The port 4702 * refers to the Sorrento external FPGA port. 4703 */ 4704 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_NO_ACTIVE_PORT 0x3 4705 4706 4707 /***********************************/ 4708 /* MC_CMD_SHMUART 4709 * Route UART output to circular buffer in shared memory instead. 4710 */ 4711 #define MC_CMD_SHMUART 0x1f 4712 4713 /* MC_CMD_SHMUART_IN msgrequest */ 4714 #define MC_CMD_SHMUART_IN_LEN 4 4715 /* ??? */ 4716 #define MC_CMD_SHMUART_IN_FLAG_OFST 0 4717 4718 /* MC_CMD_SHMUART_OUT msgresponse */ 4719 #define MC_CMD_SHMUART_OUT_LEN 0 4720 4721 4722 /***********************************/ 4723 /* MC_CMD_PORT_RESET 4724 * Generic per-port reset. There is no equivalent for per-board reset. Locks 4725 * required: None; Return code: 0, ETIME. NOTE: This command is deprecated - 4726 * use MC_CMD_ENTITY_RESET instead. 4727 */ 4728 #define MC_CMD_PORT_RESET 0x20 4729 #undef MC_CMD_0x20_PRIVILEGE_CTG 4730 4731 #define MC_CMD_0x20_PRIVILEGE_CTG SRIOV_CTG_GENERAL 4732 4733 /* MC_CMD_PORT_RESET_IN msgrequest */ 4734 #define MC_CMD_PORT_RESET_IN_LEN 0 4735 4736 /* MC_CMD_PORT_RESET_OUT msgresponse */ 4737 #define MC_CMD_PORT_RESET_OUT_LEN 0 4738 4739 4740 /***********************************/ 4741 /* MC_CMD_ENTITY_RESET 4742 * Generic per-resource reset. There is no equivalent for per-board reset. 4743 * Locks required: None; Return code: 0, ETIME. NOTE: This command is an 4744 * extended version of the deprecated MC_CMD_PORT_RESET with added fields. 4745 */ 4746 #define MC_CMD_ENTITY_RESET 0x20 4747 /* MC_CMD_0x20_PRIVILEGE_CTG SRIOV_CTG_GENERAL */ 4748 4749 /* MC_CMD_ENTITY_RESET_IN msgrequest */ 4750 #define MC_CMD_ENTITY_RESET_IN_LEN 4 4751 /* Optional flags field. Omitting this will perform a "legacy" reset action 4752 * (TBD). 4753 */ 4754 #define MC_CMD_ENTITY_RESET_IN_FLAG_OFST 0 4755 #define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_LBN 0 4756 #define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_WIDTH 1 4757 4758 /* MC_CMD_ENTITY_RESET_OUT msgresponse */ 4759 #define MC_CMD_ENTITY_RESET_OUT_LEN 0 4760 4761 4762 /***********************************/ 4763 /* MC_CMD_PCIE_CREDITS 4764 * Read instantaneous and minimum flow control thresholds. 4765 */ 4766 #define MC_CMD_PCIE_CREDITS 0x21 4767 4768 /* MC_CMD_PCIE_CREDITS_IN msgrequest */ 4769 #define MC_CMD_PCIE_CREDITS_IN_LEN 8 4770 /* poll period. 0 is disabled */ 4771 #define MC_CMD_PCIE_CREDITS_IN_POLL_PERIOD_OFST 0 4772 /* wipe statistics */ 4773 #define MC_CMD_PCIE_CREDITS_IN_WIPE_OFST 4 4774 4775 /* MC_CMD_PCIE_CREDITS_OUT msgresponse */ 4776 #define MC_CMD_PCIE_CREDITS_OUT_LEN 16 4777 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_OFST 0 4778 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_LEN 2 4779 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_OFST 2 4780 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_LEN 2 4781 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_OFST 4 4782 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_LEN 2 4783 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_OFST 6 4784 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_LEN 2 4785 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_OFST 8 4786 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_LEN 2 4787 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_OFST 10 4788 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_LEN 2 4789 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_OFST 12 4790 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_LEN 2 4791 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_OFST 14 4792 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_LEN 2 4793 4794 4795 /***********************************/ 4796 /* MC_CMD_RXD_MONITOR 4797 * Get histogram of RX queue fill level. 4798 */ 4799 #define MC_CMD_RXD_MONITOR 0x22 4800 4801 /* MC_CMD_RXD_MONITOR_IN msgrequest */ 4802 #define MC_CMD_RXD_MONITOR_IN_LEN 12 4803 #define MC_CMD_RXD_MONITOR_IN_QID_OFST 0 4804 #define MC_CMD_RXD_MONITOR_IN_POLL_PERIOD_OFST 4 4805 #define MC_CMD_RXD_MONITOR_IN_WIPE_OFST 8 4806 4807 /* MC_CMD_RXD_MONITOR_OUT msgresponse */ 4808 #define MC_CMD_RXD_MONITOR_OUT_LEN 80 4809 #define MC_CMD_RXD_MONITOR_OUT_QID_OFST 0 4810 #define MC_CMD_RXD_MONITOR_OUT_RING_FILL_OFST 4 4811 #define MC_CMD_RXD_MONITOR_OUT_CACHE_FILL_OFST 8 4812 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_1_OFST 12 4813 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_2_OFST 16 4814 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_4_OFST 20 4815 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_8_OFST 24 4816 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_16_OFST 28 4817 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_32_OFST 32 4818 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_64_OFST 36 4819 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_128_OFST 40 4820 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_256_OFST 44 4821 #define MC_CMD_RXD_MONITOR_OUT_RING_GE_256_OFST 48 4822 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_1_OFST 52 4823 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_2_OFST 56 4824 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_4_OFST 60 4825 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_8_OFST 64 4826 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_16_OFST 68 4827 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_32_OFST 72 4828 #define MC_CMD_RXD_MONITOR_OUT_CACHE_GE_32_OFST 76 4829 4830 4831 /***********************************/ 4832 /* MC_CMD_PUTS 4833 * Copy the given ASCII string out onto UART and/or out of the network port. 4834 */ 4835 #define MC_CMD_PUTS 0x23 4836 #undef MC_CMD_0x23_PRIVILEGE_CTG 4837 4838 #define MC_CMD_0x23_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4839 4840 /* MC_CMD_PUTS_IN msgrequest */ 4841 #define MC_CMD_PUTS_IN_LENMIN 13 4842 #define MC_CMD_PUTS_IN_LENMAX 252 4843 #define MC_CMD_PUTS_IN_LEN(num) (12+1*(num)) 4844 #define MC_CMD_PUTS_IN_DEST_OFST 0 4845 #define MC_CMD_PUTS_IN_UART_LBN 0 4846 #define MC_CMD_PUTS_IN_UART_WIDTH 1 4847 #define MC_CMD_PUTS_IN_PORT_LBN 1 4848 #define MC_CMD_PUTS_IN_PORT_WIDTH 1 4849 #define MC_CMD_PUTS_IN_DHOST_OFST 4 4850 #define MC_CMD_PUTS_IN_DHOST_LEN 6 4851 #define MC_CMD_PUTS_IN_STRING_OFST 12 4852 #define MC_CMD_PUTS_IN_STRING_LEN 1 4853 #define MC_CMD_PUTS_IN_STRING_MINNUM 1 4854 #define MC_CMD_PUTS_IN_STRING_MAXNUM 240 4855 4856 /* MC_CMD_PUTS_OUT msgresponse */ 4857 #define MC_CMD_PUTS_OUT_LEN 0 4858 4859 4860 /***********************************/ 4861 /* MC_CMD_GET_PHY_CFG 4862 * Report PHY configuration. This guarantees to succeed even if the PHY is in a 4863 * 'zombie' state. Locks required: None 4864 */ 4865 #define MC_CMD_GET_PHY_CFG 0x24 4866 #undef MC_CMD_0x24_PRIVILEGE_CTG 4867 4868 #define MC_CMD_0x24_PRIVILEGE_CTG SRIOV_CTG_GENERAL 4869 4870 /* MC_CMD_GET_PHY_CFG_IN msgrequest */ 4871 #define MC_CMD_GET_PHY_CFG_IN_LEN 0 4872 4873 /* MC_CMD_GET_PHY_CFG_OUT msgresponse */ 4874 #define MC_CMD_GET_PHY_CFG_OUT_LEN 72 4875 /* flags */ 4876 #define MC_CMD_GET_PHY_CFG_OUT_FLAGS_OFST 0 4877 #define MC_CMD_GET_PHY_CFG_OUT_PRESENT_LBN 0 4878 #define MC_CMD_GET_PHY_CFG_OUT_PRESENT_WIDTH 1 4879 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_LBN 1 4880 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_WIDTH 1 4881 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_LBN 2 4882 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_WIDTH 1 4883 #define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_LBN 3 4884 #define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_WIDTH 1 4885 #define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_LBN 4 4886 #define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_WIDTH 1 4887 #define MC_CMD_GET_PHY_CFG_OUT_TXDIS_LBN 5 4888 #define MC_CMD_GET_PHY_CFG_OUT_TXDIS_WIDTH 1 4889 #define MC_CMD_GET_PHY_CFG_OUT_BIST_LBN 6 4890 #define MC_CMD_GET_PHY_CFG_OUT_BIST_WIDTH 1 4891 /* ?? */ 4892 #define MC_CMD_GET_PHY_CFG_OUT_TYPE_OFST 4 4893 /* Bitmask of supported capabilities */ 4894 #define MC_CMD_GET_PHY_CFG_OUT_SUPPORTED_CAP_OFST 8 4895 #define MC_CMD_PHY_CAP_10HDX_LBN 1 4896 #define MC_CMD_PHY_CAP_10HDX_WIDTH 1 4897 #define MC_CMD_PHY_CAP_10FDX_LBN 2 4898 #define MC_CMD_PHY_CAP_10FDX_WIDTH 1 4899 #define MC_CMD_PHY_CAP_100HDX_LBN 3 4900 #define MC_CMD_PHY_CAP_100HDX_WIDTH 1 4901 #define MC_CMD_PHY_CAP_100FDX_LBN 4 4902 #define MC_CMD_PHY_CAP_100FDX_WIDTH 1 4903 #define MC_CMD_PHY_CAP_1000HDX_LBN 5 4904 #define MC_CMD_PHY_CAP_1000HDX_WIDTH 1 4905 #define MC_CMD_PHY_CAP_1000FDX_LBN 6 4906 #define MC_CMD_PHY_CAP_1000FDX_WIDTH 1 4907 #define MC_CMD_PHY_CAP_10000FDX_LBN 7 4908 #define MC_CMD_PHY_CAP_10000FDX_WIDTH 1 4909 #define MC_CMD_PHY_CAP_PAUSE_LBN 8 4910 #define MC_CMD_PHY_CAP_PAUSE_WIDTH 1 4911 #define MC_CMD_PHY_CAP_ASYM_LBN 9 4912 #define MC_CMD_PHY_CAP_ASYM_WIDTH 1 4913 #define MC_CMD_PHY_CAP_AN_LBN 10 4914 #define MC_CMD_PHY_CAP_AN_WIDTH 1 4915 #define MC_CMD_PHY_CAP_40000FDX_LBN 11 4916 #define MC_CMD_PHY_CAP_40000FDX_WIDTH 1 4917 #define MC_CMD_PHY_CAP_DDM_LBN 12 4918 #define MC_CMD_PHY_CAP_DDM_WIDTH 1 4919 /* ?? */ 4920 #define MC_CMD_GET_PHY_CFG_OUT_CHANNEL_OFST 12 4921 /* ?? */ 4922 #define MC_CMD_GET_PHY_CFG_OUT_PRT_OFST 16 4923 /* ?? */ 4924 #define MC_CMD_GET_PHY_CFG_OUT_STATS_MASK_OFST 20 4925 /* ?? */ 4926 #define MC_CMD_GET_PHY_CFG_OUT_NAME_OFST 24 4927 #define MC_CMD_GET_PHY_CFG_OUT_NAME_LEN 20 4928 /* ?? */ 4929 #define MC_CMD_GET_PHY_CFG_OUT_MEDIA_TYPE_OFST 44 4930 /* enum: Xaui. */ 4931 #define MC_CMD_MEDIA_XAUI 0x1 4932 /* enum: CX4. */ 4933 #define MC_CMD_MEDIA_CX4 0x2 4934 /* enum: KX4. */ 4935 #define MC_CMD_MEDIA_KX4 0x3 4936 /* enum: XFP Far. */ 4937 #define MC_CMD_MEDIA_XFP 0x4 4938 /* enum: SFP+. */ 4939 #define MC_CMD_MEDIA_SFP_PLUS 0x5 4940 /* enum: 10GBaseT. */ 4941 #define MC_CMD_MEDIA_BASE_T 0x6 4942 /* enum: QSFP+. */ 4943 #define MC_CMD_MEDIA_QSFP_PLUS 0x7 4944 #define MC_CMD_GET_PHY_CFG_OUT_MMD_MASK_OFST 48 4945 /* enum: Native clause 22 */ 4946 #define MC_CMD_MMD_CLAUSE22 0x0 4947 #define MC_CMD_MMD_CLAUSE45_PMAPMD 0x1 /* enum */ 4948 #define MC_CMD_MMD_CLAUSE45_WIS 0x2 /* enum */ 4949 #define MC_CMD_MMD_CLAUSE45_PCS 0x3 /* enum */ 4950 #define MC_CMD_MMD_CLAUSE45_PHYXS 0x4 /* enum */ 4951 #define MC_CMD_MMD_CLAUSE45_DTEXS 0x5 /* enum */ 4952 #define MC_CMD_MMD_CLAUSE45_TC 0x6 /* enum */ 4953 #define MC_CMD_MMD_CLAUSE45_AN 0x7 /* enum */ 4954 /* enum: Clause22 proxied over clause45 by PHY. */ 4955 #define MC_CMD_MMD_CLAUSE45_C22EXT 0x1d 4956 #define MC_CMD_MMD_CLAUSE45_VEND1 0x1e /* enum */ 4957 #define MC_CMD_MMD_CLAUSE45_VEND2 0x1f /* enum */ 4958 #define MC_CMD_GET_PHY_CFG_OUT_REVISION_OFST 52 4959 #define MC_CMD_GET_PHY_CFG_OUT_REVISION_LEN 20 4960 4961 4962 /***********************************/ 4963 /* MC_CMD_START_BIST 4964 * Start a BIST test on the PHY. Locks required: PHY_LOCK if doing a PHY BIST 4965 * Return code: 0, EINVAL, EACCES (if PHY_LOCK is not held) 4966 */ 4967 #define MC_CMD_START_BIST 0x25 4968 #undef MC_CMD_0x25_PRIVILEGE_CTG 4969 4970 #define MC_CMD_0x25_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4971 4972 /* MC_CMD_START_BIST_IN msgrequest */ 4973 #define MC_CMD_START_BIST_IN_LEN 4 4974 /* Type of test. */ 4975 #define MC_CMD_START_BIST_IN_TYPE_OFST 0 4976 /* enum: Run the PHY's short cable BIST. */ 4977 #define MC_CMD_PHY_BIST_CABLE_SHORT 0x1 4978 /* enum: Run the PHY's long cable BIST. */ 4979 #define MC_CMD_PHY_BIST_CABLE_LONG 0x2 4980 /* enum: Run BIST on the currently selected BPX Serdes (XAUI or XFI) . */ 4981 #define MC_CMD_BPX_SERDES_BIST 0x3 4982 /* enum: Run the MC loopback tests. */ 4983 #define MC_CMD_MC_LOOPBACK_BIST 0x4 4984 /* enum: Run the PHY's standard BIST. */ 4985 #define MC_CMD_PHY_BIST 0x5 4986 /* enum: Run MC RAM test. */ 4987 #define MC_CMD_MC_MEM_BIST 0x6 4988 /* enum: Run Port RAM test. */ 4989 #define MC_CMD_PORT_MEM_BIST 0x7 4990 /* enum: Run register test. */ 4991 #define MC_CMD_REG_BIST 0x8 4992 4993 /* MC_CMD_START_BIST_OUT msgresponse */ 4994 #define MC_CMD_START_BIST_OUT_LEN 0 4995 4996 4997 /***********************************/ 4998 /* MC_CMD_POLL_BIST 4999 * Poll for BIST completion. Returns a single status code, and optionally some 5000 * PHY specific bist output. The driver should only consume the BIST output 5001 * after validating OUTLEN and MC_CMD_GET_PHY_CFG.TYPE. If a driver can't 5002 * successfully parse the BIST output, it should still respect the pass/Fail in 5003 * OUT.RESULT. Locks required: PHY_LOCK if doing a PHY BIST. Return code: 0, 5004 * EACCES (if PHY_LOCK is not held). 5005 */ 5006 #define MC_CMD_POLL_BIST 0x26 5007 #undef MC_CMD_0x26_PRIVILEGE_CTG 5008 5009 #define MC_CMD_0x26_PRIVILEGE_CTG SRIOV_CTG_ADMIN 5010 5011 /* MC_CMD_POLL_BIST_IN msgrequest */ 5012 #define MC_CMD_POLL_BIST_IN_LEN 0 5013 5014 /* MC_CMD_POLL_BIST_OUT msgresponse */ 5015 #define MC_CMD_POLL_BIST_OUT_LEN 8 5016 /* result */ 5017 #define MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 5018 /* enum: Running. */ 5019 #define MC_CMD_POLL_BIST_RUNNING 0x1 5020 /* enum: Passed. */ 5021 #define MC_CMD_POLL_BIST_PASSED 0x2 5022 /* enum: Failed. */ 5023 #define MC_CMD_POLL_BIST_FAILED 0x3 5024 /* enum: Timed-out. */ 5025 #define MC_CMD_POLL_BIST_TIMEOUT 0x4 5026 #define MC_CMD_POLL_BIST_OUT_PRIVATE_OFST 4 5027 5028 /* MC_CMD_POLL_BIST_OUT_SFT9001 msgresponse */ 5029 #define MC_CMD_POLL_BIST_OUT_SFT9001_LEN 36 5030 /* result */ 5031 /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */ 5032 /* Enum values, see field(s): */ 5033 /* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */ 5034 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A_OFST 4 5035 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B_OFST 8 5036 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C_OFST 12 5037 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D_OFST 16 5038 /* Status of each channel A */ 5039 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_A_OFST 20 5040 /* enum: Ok. */ 5041 #define MC_CMD_POLL_BIST_SFT9001_PAIR_OK 0x1 5042 /* enum: Open. */ 5043 #define MC_CMD_POLL_BIST_SFT9001_PAIR_OPEN 0x2 5044 /* enum: Intra-pair short. */ 5045 #define MC_CMD_POLL_BIST_SFT9001_INTRA_PAIR_SHORT 0x3 5046 /* enum: Inter-pair short. */ 5047 #define MC_CMD_POLL_BIST_SFT9001_INTER_PAIR_SHORT 0x4 5048 /* enum: Busy. */ 5049 #define MC_CMD_POLL_BIST_SFT9001_PAIR_BUSY 0x9 5050 /* Status of each channel B */ 5051 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_B_OFST 24 5052 /* Enum values, see field(s): */ 5053 /* CABLE_STATUS_A */ 5054 /* Status of each channel C */ 5055 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_C_OFST 28 5056 /* Enum values, see field(s): */ 5057 /* CABLE_STATUS_A */ 5058 /* Status of each channel D */ 5059 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_D_OFST 32 5060 /* Enum values, see field(s): */ 5061 /* CABLE_STATUS_A */ 5062 5063 /* MC_CMD_POLL_BIST_OUT_MRSFP msgresponse */ 5064 #define MC_CMD_POLL_BIST_OUT_MRSFP_LEN 8 5065 /* result */ 5066 /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */ 5067 /* Enum values, see field(s): */ 5068 /* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */ 5069 #define MC_CMD_POLL_BIST_OUT_MRSFP_TEST_OFST 4 5070 /* enum: Complete. */ 5071 #define MC_CMD_POLL_BIST_MRSFP_TEST_COMPLETE 0x0 5072 /* enum: Bus switch off I2C write. */ 5073 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_WRITE 0x1 5074 /* enum: Bus switch off I2C no access IO exp. */ 5075 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_IO_EXP 0x2 5076 /* enum: Bus switch off I2C no access module. */ 5077 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_MODULE 0x3 5078 /* enum: IO exp I2C configure. */ 5079 #define MC_CMD_POLL_BIST_MRSFP_TEST_IO_EXP_I2C_CONFIGURE 0x4 5080 /* enum: Bus switch I2C no cross talk. */ 5081 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_I2C_NO_CROSSTALK 0x5 5082 /* enum: Module presence. */ 5083 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_PRESENCE 0x6 5084 /* enum: Module ID I2C access. */ 5085 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_I2C_ACCESS 0x7 5086 /* enum: Module ID sane value. */ 5087 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_SANE_VALUE 0x8 5088 5089 /* MC_CMD_POLL_BIST_OUT_MEM msgresponse */ 5090 #define MC_CMD_POLL_BIST_OUT_MEM_LEN 36 5091 /* result */ 5092 /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */ 5093 /* Enum values, see field(s): */ 5094 /* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */ 5095 #define MC_CMD_POLL_BIST_OUT_MEM_TEST_OFST 4 5096 /* enum: Test has completed. */ 5097 #define MC_CMD_POLL_BIST_MEM_COMPLETE 0x0 5098 /* enum: RAM test - walk ones. */ 5099 #define MC_CMD_POLL_BIST_MEM_MEM_WALK_ONES 0x1 5100 /* enum: RAM test - walk zeros. */ 5101 #define MC_CMD_POLL_BIST_MEM_MEM_WALK_ZEROS 0x2 5102 /* enum: RAM test - walking inversions zeros/ones. */ 5103 #define MC_CMD_POLL_BIST_MEM_MEM_INV_ZERO_ONE 0x3 5104 /* enum: RAM test - walking inversions checkerboard. */ 5105 #define MC_CMD_POLL_BIST_MEM_MEM_INV_CHKBOARD 0x4 5106 /* enum: Register test - set / clear individual bits. */ 5107 #define MC_CMD_POLL_BIST_MEM_REG 0x5 5108 /* enum: ECC error detected. */ 5109 #define MC_CMD_POLL_BIST_MEM_ECC 0x6 5110 /* Failure address, only valid if result is POLL_BIST_FAILED */ 5111 #define MC_CMD_POLL_BIST_OUT_MEM_ADDR_OFST 8 5112 /* Bus or address space to which the failure address corresponds */ 5113 #define MC_CMD_POLL_BIST_OUT_MEM_BUS_OFST 12 5114 /* enum: MC MIPS bus. */ 5115 #define MC_CMD_POLL_BIST_MEM_BUS_MC 0x0 5116 /* enum: CSR IREG bus. */ 5117 #define MC_CMD_POLL_BIST_MEM_BUS_CSR 0x1 5118 /* enum: RX DPCPU bus. */ 5119 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_RX 0x2 5120 /* enum: TX0 DPCPU bus. */ 5121 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX0 0x3 5122 /* enum: TX1 DPCPU bus. */ 5123 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX1 0x4 5124 /* enum: RX DICPU bus. */ 5125 #define MC_CMD_POLL_BIST_MEM_BUS_DICPU_RX 0x5 5126 /* enum: TX DICPU bus. */ 5127 #define MC_CMD_POLL_BIST_MEM_BUS_DICPU_TX 0x6 5128 /* Pattern written to RAM / register */ 5129 #define MC_CMD_POLL_BIST_OUT_MEM_EXPECT_OFST 16 5130 /* Actual value read from RAM / register */ 5131 #define MC_CMD_POLL_BIST_OUT_MEM_ACTUAL_OFST 20 5132 /* ECC error mask */ 5133 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_OFST 24 5134 /* ECC parity error mask */ 5135 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_PARITY_OFST 28 5136 /* ECC fatal error mask */ 5137 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_FATAL_OFST 32 5138 5139 5140 /***********************************/ 5141 /* MC_CMD_FLUSH_RX_QUEUES 5142 * Flush receive queue(s). If SRIOV is enabled (via MC_CMD_SRIOV), then RXQ 5143 * flushes should be initiated via this MCDI operation, rather than via 5144 * directly writing FLUSH_CMD. 5145 * 5146 * The flush is completed (either done/fail) asynchronously (after this command 5147 * returns). The driver must still wait for flush done/failure events as usual. 5148 */ 5149 #define MC_CMD_FLUSH_RX_QUEUES 0x27 5150 5151 /* MC_CMD_FLUSH_RX_QUEUES_IN msgrequest */ 5152 #define MC_CMD_FLUSH_RX_QUEUES_IN_LENMIN 4 5153 #define MC_CMD_FLUSH_RX_QUEUES_IN_LENMAX 252 5154 #define MC_CMD_FLUSH_RX_QUEUES_IN_LEN(num) (0+4*(num)) 5155 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_OFST 0 5156 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_LEN 4 5157 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MINNUM 1 5158 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MAXNUM 63 5159 5160 /* MC_CMD_FLUSH_RX_QUEUES_OUT msgresponse */ 5161 #define MC_CMD_FLUSH_RX_QUEUES_OUT_LEN 0 5162 5163 5164 /***********************************/ 5165 /* MC_CMD_GET_LOOPBACK_MODES 5166 * Returns a bitmask of loopback modes available at each speed. 5167 */ 5168 #define MC_CMD_GET_LOOPBACK_MODES 0x28 5169 #undef MC_CMD_0x28_PRIVILEGE_CTG 5170 5171 #define MC_CMD_0x28_PRIVILEGE_CTG SRIOV_CTG_GENERAL 5172 5173 /* MC_CMD_GET_LOOPBACK_MODES_IN msgrequest */ 5174 #define MC_CMD_GET_LOOPBACK_MODES_IN_LEN 0 5175 5176 /* MC_CMD_GET_LOOPBACK_MODES_OUT msgresponse */ 5177 #define MC_CMD_GET_LOOPBACK_MODES_OUT_LEN 40 5178 /* Supported loopbacks. */ 5179 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_OFST 0 5180 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LEN 8 5181 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_OFST 0 5182 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_OFST 4 5183 /* enum: None. */ 5184 #define MC_CMD_LOOPBACK_NONE 0x0 5185 /* enum: Data. */ 5186 #define MC_CMD_LOOPBACK_DATA 0x1 5187 /* enum: GMAC. */ 5188 #define MC_CMD_LOOPBACK_GMAC 0x2 5189 /* enum: XGMII. */ 5190 #define MC_CMD_LOOPBACK_XGMII 0x3 5191 /* enum: XGXS. */ 5192 #define MC_CMD_LOOPBACK_XGXS 0x4 5193 /* enum: XAUI. */ 5194 #define MC_CMD_LOOPBACK_XAUI 0x5 5195 /* enum: GMII. */ 5196 #define MC_CMD_LOOPBACK_GMII 0x6 5197 /* enum: SGMII. */ 5198 #define MC_CMD_LOOPBACK_SGMII 0x7 5199 /* enum: XGBR. */ 5200 #define MC_CMD_LOOPBACK_XGBR 0x8 5201 /* enum: XFI. */ 5202 #define MC_CMD_LOOPBACK_XFI 0x9 5203 /* enum: XAUI Far. */ 5204 #define MC_CMD_LOOPBACK_XAUI_FAR 0xa 5205 /* enum: GMII Far. */ 5206 #define MC_CMD_LOOPBACK_GMII_FAR 0xb 5207 /* enum: SGMII Far. */ 5208 #define MC_CMD_LOOPBACK_SGMII_FAR 0xc 5209 /* enum: XFI Far. */ 5210 #define MC_CMD_LOOPBACK_XFI_FAR 0xd 5211 /* enum: GPhy. */ 5212 #define MC_CMD_LOOPBACK_GPHY 0xe 5213 /* enum: PhyXS. */ 5214 #define MC_CMD_LOOPBACK_PHYXS 0xf 5215 /* enum: PCS. */ 5216 #define MC_CMD_LOOPBACK_PCS 0x10 5217 /* enum: PMA-PMD. */ 5218 #define MC_CMD_LOOPBACK_PMAPMD 0x11 5219 /* enum: Cross-Port. */ 5220 #define MC_CMD_LOOPBACK_XPORT 0x12 5221 /* enum: XGMII-Wireside. */ 5222 #define MC_CMD_LOOPBACK_XGMII_WS 0x13 5223 /* enum: XAUI Wireside. */ 5224 #define MC_CMD_LOOPBACK_XAUI_WS 0x14 5225 /* enum: XAUI Wireside Far. */ 5226 #define MC_CMD_LOOPBACK_XAUI_WS_FAR 0x15 5227 /* enum: XAUI Wireside near. */ 5228 #define MC_CMD_LOOPBACK_XAUI_WS_NEAR 0x16 5229 /* enum: GMII Wireside. */ 5230 #define MC_CMD_LOOPBACK_GMII_WS 0x17 5231 /* enum: XFI Wireside. */ 5232 #define MC_CMD_LOOPBACK_XFI_WS 0x18 5233 /* enum: XFI Wireside Far. */ 5234 #define MC_CMD_LOOPBACK_XFI_WS_FAR 0x19 5235 /* enum: PhyXS Wireside. */ 5236 #define MC_CMD_LOOPBACK_PHYXS_WS 0x1a 5237 /* enum: PMA lanes MAC-Serdes. */ 5238 #define MC_CMD_LOOPBACK_PMA_INT 0x1b 5239 /* enum: KR Serdes Parallel (Encoder). */ 5240 #define MC_CMD_LOOPBACK_SD_NEAR 0x1c 5241 /* enum: KR Serdes Serial. */ 5242 #define MC_CMD_LOOPBACK_SD_FAR 0x1d 5243 /* enum: PMA lanes MAC-Serdes Wireside. */ 5244 #define MC_CMD_LOOPBACK_PMA_INT_WS 0x1e 5245 /* enum: KR Serdes Parallel Wireside (Full PCS). */ 5246 #define MC_CMD_LOOPBACK_SD_FEP2_WS 0x1f 5247 /* enum: KR Serdes Parallel Wireside (Sym Aligner to TX). */ 5248 #define MC_CMD_LOOPBACK_SD_FEP1_5_WS 0x20 5249 /* enum: KR Serdes Parallel Wireside (Deserializer to Serializer). */ 5250 #define MC_CMD_LOOPBACK_SD_FEP_WS 0x21 5251 /* enum: KR Serdes Serial Wireside. */ 5252 #define MC_CMD_LOOPBACK_SD_FES_WS 0x22 5253 /* enum: Near side of AOE Siena side port */ 5254 #define MC_CMD_LOOPBACK_AOE_INT_NEAR 0x23 5255 /* enum: Medford Wireside datapath loopback */ 5256 #define MC_CMD_LOOPBACK_DATA_WS 0x24 5257 /* enum: Force link up without setting up any physical loopback (snapper use 5258 * only) 5259 */ 5260 #define MC_CMD_LOOPBACK_FORCE_EXT_LINK 0x25 5261 /* Supported loopbacks. */ 5262 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_OFST 8 5263 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LEN 8 5264 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LO_OFST 8 5265 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_HI_OFST 12 5266 /* Enum values, see field(s): */ 5267 /* 100M */ 5268 /* Supported loopbacks. */ 5269 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_OFST 16 5270 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LEN 8 5271 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LO_OFST 16 5272 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_HI_OFST 20 5273 /* Enum values, see field(s): */ 5274 /* 100M */ 5275 /* Supported loopbacks. */ 5276 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_OFST 24 5277 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LEN 8 5278 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LO_OFST 24 5279 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_HI_OFST 28 5280 /* Enum values, see field(s): */ 5281 /* 100M */ 5282 /* Supported loopbacks. */ 5283 #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_OFST 32 5284 #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LEN 8 5285 #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LO_OFST 32 5286 #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_HI_OFST 36 5287 /* Enum values, see field(s): */ 5288 /* 100M */ 5289 5290 5291 /***********************************/ 5292 /* MC_CMD_GET_LINK 5293 * Read the unified MAC/PHY link state. Locks required: None Return code: 0, 5294 * ETIME. 5295 */ 5296 #define MC_CMD_GET_LINK 0x29 5297 #undef MC_CMD_0x29_PRIVILEGE_CTG 5298 5299 #define MC_CMD_0x29_PRIVILEGE_CTG SRIOV_CTG_GENERAL 5300 5301 /* MC_CMD_GET_LINK_IN msgrequest */ 5302 #define MC_CMD_GET_LINK_IN_LEN 0 5303 5304 /* MC_CMD_GET_LINK_OUT msgresponse */ 5305 #define MC_CMD_GET_LINK_OUT_LEN 28 5306 /* near-side advertised capabilities */ 5307 #define MC_CMD_GET_LINK_OUT_CAP_OFST 0 5308 /* link-partner advertised capabilities */ 5309 #define MC_CMD_GET_LINK_OUT_LP_CAP_OFST 4 5310 /* Autonegotiated speed in mbit/s. The link may still be down even if this 5311 * reads non-zero. 5312 */ 5313 #define MC_CMD_GET_LINK_OUT_LINK_SPEED_OFST 8 5314 /* Current loopback setting. */ 5315 #define MC_CMD_GET_LINK_OUT_LOOPBACK_MODE_OFST 12 5316 /* Enum values, see field(s): */ 5317 /* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */ 5318 #define MC_CMD_GET_LINK_OUT_FLAGS_OFST 16 5319 #define MC_CMD_GET_LINK_OUT_LINK_UP_LBN 0 5320 #define MC_CMD_GET_LINK_OUT_LINK_UP_WIDTH 1 5321 #define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_LBN 1 5322 #define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_WIDTH 1 5323 #define MC_CMD_GET_LINK_OUT_BPX_LINK_LBN 2 5324 #define MC_CMD_GET_LINK_OUT_BPX_LINK_WIDTH 1 5325 #define MC_CMD_GET_LINK_OUT_PHY_LINK_LBN 3 5326 #define MC_CMD_GET_LINK_OUT_PHY_LINK_WIDTH 1 5327 #define MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_LBN 6 5328 #define MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_WIDTH 1 5329 #define MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_LBN 7 5330 #define MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_WIDTH 1 5331 /* This returns the negotiated flow control value. */ 5332 #define MC_CMD_GET_LINK_OUT_FCNTL_OFST 20 5333 /* Enum values, see field(s): */ 5334 /* MC_CMD_SET_MAC/MC_CMD_SET_MAC_IN/FCNTL */ 5335 #define MC_CMD_GET_LINK_OUT_MAC_FAULT_OFST 24 5336 #define MC_CMD_MAC_FAULT_XGMII_LOCAL_LBN 0 5337 #define MC_CMD_MAC_FAULT_XGMII_LOCAL_WIDTH 1 5338 #define MC_CMD_MAC_FAULT_XGMII_REMOTE_LBN 1 5339 #define MC_CMD_MAC_FAULT_XGMII_REMOTE_WIDTH 1 5340 #define MC_CMD_MAC_FAULT_SGMII_REMOTE_LBN 2 5341 #define MC_CMD_MAC_FAULT_SGMII_REMOTE_WIDTH 1 5342 #define MC_CMD_MAC_FAULT_PENDING_RECONFIG_LBN 3 5343 #define MC_CMD_MAC_FAULT_PENDING_RECONFIG_WIDTH 1 5344 5345 5346 /***********************************/ 5347 /* MC_CMD_SET_LINK 5348 * Write the unified MAC/PHY link configuration. Locks required: None. Return 5349 * code: 0, EINVAL, ETIME 5350 */ 5351 #define MC_CMD_SET_LINK 0x2a 5352 #undef MC_CMD_0x2a_PRIVILEGE_CTG 5353 5354 #define MC_CMD_0x2a_PRIVILEGE_CTG SRIOV_CTG_LINK 5355 5356 /* MC_CMD_SET_LINK_IN msgrequest */ 5357 #define MC_CMD_SET_LINK_IN_LEN 16 5358 /* ??? */ 5359 #define MC_CMD_SET_LINK_IN_CAP_OFST 0 5360 /* Flags */ 5361 #define MC_CMD_SET_LINK_IN_FLAGS_OFST 4 5362 #define MC_CMD_SET_LINK_IN_LOWPOWER_LBN 0 5363 #define MC_CMD_SET_LINK_IN_LOWPOWER_WIDTH 1 5364 #define MC_CMD_SET_LINK_IN_POWEROFF_LBN 1 5365 #define MC_CMD_SET_LINK_IN_POWEROFF_WIDTH 1 5366 #define MC_CMD_SET_LINK_IN_TXDIS_LBN 2 5367 #define MC_CMD_SET_LINK_IN_TXDIS_WIDTH 1 5368 /* Loopback mode. */ 5369 #define MC_CMD_SET_LINK_IN_LOOPBACK_MODE_OFST 8 5370 /* Enum values, see field(s): */ 5371 /* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */ 5372 /* A loopback speed of "0" is supported, and means (choose any available 5373 * speed). 5374 */ 5375 #define MC_CMD_SET_LINK_IN_LOOPBACK_SPEED_OFST 12 5376 5377 /* MC_CMD_SET_LINK_OUT msgresponse */ 5378 #define MC_CMD_SET_LINK_OUT_LEN 0 5379 5380 5381 /***********************************/ 5382 /* MC_CMD_SET_ID_LED 5383 * Set identification LED state. Locks required: None. Return code: 0, EINVAL 5384 */ 5385 #define MC_CMD_SET_ID_LED 0x2b 5386 #undef MC_CMD_0x2b_PRIVILEGE_CTG 5387 5388 #define MC_CMD_0x2b_PRIVILEGE_CTG SRIOV_CTG_LINK 5389 5390 /* MC_CMD_SET_ID_LED_IN msgrequest */ 5391 #define MC_CMD_SET_ID_LED_IN_LEN 4 5392 /* Set LED state. */ 5393 #define MC_CMD_SET_ID_LED_IN_STATE_OFST 0 5394 #define MC_CMD_LED_OFF 0x0 /* enum */ 5395 #define MC_CMD_LED_ON 0x1 /* enum */ 5396 #define MC_CMD_LED_DEFAULT 0x2 /* enum */ 5397 5398 /* MC_CMD_SET_ID_LED_OUT msgresponse */ 5399 #define MC_CMD_SET_ID_LED_OUT_LEN 0 5400 5401 5402 /***********************************/ 5403 /* MC_CMD_SET_MAC 5404 * Set MAC configuration. Locks required: None. Return code: 0, EINVAL 5405 */ 5406 #define MC_CMD_SET_MAC 0x2c 5407 #undef MC_CMD_0x2c_PRIVILEGE_CTG 5408 5409 #define MC_CMD_0x2c_PRIVILEGE_CTG SRIOV_CTG_GENERAL 5410 5411 /* MC_CMD_SET_MAC_IN msgrequest */ 5412 #define MC_CMD_SET_MAC_IN_LEN 28 5413 /* The MTU is the MTU programmed directly into the XMAC/GMAC (inclusive of 5414 * EtherII, VLAN, bug16011 padding). 5415 */ 5416 #define MC_CMD_SET_MAC_IN_MTU_OFST 0 5417 #define MC_CMD_SET_MAC_IN_DRAIN_OFST 4 5418 #define MC_CMD_SET_MAC_IN_ADDR_OFST 8 5419 #define MC_CMD_SET_MAC_IN_ADDR_LEN 8 5420 #define MC_CMD_SET_MAC_IN_ADDR_LO_OFST 8 5421 #define MC_CMD_SET_MAC_IN_ADDR_HI_OFST 12 5422 #define MC_CMD_SET_MAC_IN_REJECT_OFST 16 5423 #define MC_CMD_SET_MAC_IN_REJECT_UNCST_LBN 0 5424 #define MC_CMD_SET_MAC_IN_REJECT_UNCST_WIDTH 1 5425 #define MC_CMD_SET_MAC_IN_REJECT_BRDCST_LBN 1 5426 #define MC_CMD_SET_MAC_IN_REJECT_BRDCST_WIDTH 1 5427 #define MC_CMD_SET_MAC_IN_FCNTL_OFST 20 5428 /* enum: Flow control is off. */ 5429 #define MC_CMD_FCNTL_OFF 0x0 5430 /* enum: Respond to flow control. */ 5431 #define MC_CMD_FCNTL_RESPOND 0x1 5432 /* enum: Respond to and Issue flow control. */ 5433 #define MC_CMD_FCNTL_BIDIR 0x2 5434 /* enum: Auto neg flow control. */ 5435 #define MC_CMD_FCNTL_AUTO 0x3 5436 /* enum: Priority flow control (eftest builds only). */ 5437 #define MC_CMD_FCNTL_QBB 0x4 5438 /* enum: Issue flow control. */ 5439 #define MC_CMD_FCNTL_GENERATE 0x5 5440 #define MC_CMD_SET_MAC_IN_FLAGS_OFST 24 5441 #define MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_LBN 0 5442 #define MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_WIDTH 1 5443 5444 /* MC_CMD_SET_MAC_EXT_IN msgrequest */ 5445 #define MC_CMD_SET_MAC_EXT_IN_LEN 32 5446 /* The MTU is the MTU programmed directly into the XMAC/GMAC (inclusive of 5447 * EtherII, VLAN, bug16011 padding). 5448 */ 5449 #define MC_CMD_SET_MAC_EXT_IN_MTU_OFST 0 5450 #define MC_CMD_SET_MAC_EXT_IN_DRAIN_OFST 4 5451 #define MC_CMD_SET_MAC_EXT_IN_ADDR_OFST 8 5452 #define MC_CMD_SET_MAC_EXT_IN_ADDR_LEN 8 5453 #define MC_CMD_SET_MAC_EXT_IN_ADDR_LO_OFST 8 5454 #define MC_CMD_SET_MAC_EXT_IN_ADDR_HI_OFST 12 5455 #define MC_CMD_SET_MAC_EXT_IN_REJECT_OFST 16 5456 #define MC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_LBN 0 5457 #define MC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_WIDTH 1 5458 #define MC_CMD_SET_MAC_EXT_IN_REJECT_BRDCST_LBN 1 5459 #define MC_CMD_SET_MAC_EXT_IN_REJECT_BRDCST_WIDTH 1 5460 #define MC_CMD_SET_MAC_EXT_IN_FCNTL_OFST 20 5461 /* enum: Flow control is off. */ 5462 /* MC_CMD_FCNTL_OFF 0x0 */ 5463 /* enum: Respond to flow control. */ 5464 /* MC_CMD_FCNTL_RESPOND 0x1 */ 5465 /* enum: Respond to and Issue flow control. */ 5466 /* MC_CMD_FCNTL_BIDIR 0x2 */ 5467 /* enum: Auto neg flow control. */ 5468 /* MC_CMD_FCNTL_AUTO 0x3 */ 5469 /* enum: Priority flow control (eftest builds only). */ 5470 /* MC_CMD_FCNTL_QBB 0x4 */ 5471 /* enum: Issue flow control. */ 5472 /* MC_CMD_FCNTL_GENERATE 0x5 */ 5473 #define MC_CMD_SET_MAC_EXT_IN_FLAGS_OFST 24 5474 #define MC_CMD_SET_MAC_EXT_IN_FLAG_INCLUDE_FCS_LBN 0 5475 #define MC_CMD_SET_MAC_EXT_IN_FLAG_INCLUDE_FCS_WIDTH 1 5476 /* Select which parameters to configure. A parameter will only be modified if 5477 * the corresponding control flag is set. If SET_MAC_ENHANCED is not set in 5478 * capabilities then this field is ignored (and all flags are assumed to be 5479 * set). 5480 */ 5481 #define MC_CMD_SET_MAC_EXT_IN_CONTROL_OFST 28 5482 #define MC_CMD_SET_MAC_EXT_IN_CFG_MTU_LBN 0 5483 #define MC_CMD_SET_MAC_EXT_IN_CFG_MTU_WIDTH 1 5484 #define MC_CMD_SET_MAC_EXT_IN_CFG_DRAIN_LBN 1 5485 #define MC_CMD_SET_MAC_EXT_IN_CFG_DRAIN_WIDTH 1 5486 #define MC_CMD_SET_MAC_EXT_IN_CFG_REJECT_LBN 2 5487 #define MC_CMD_SET_MAC_EXT_IN_CFG_REJECT_WIDTH 1 5488 #define MC_CMD_SET_MAC_EXT_IN_CFG_FCNTL_LBN 3 5489 #define MC_CMD_SET_MAC_EXT_IN_CFG_FCNTL_WIDTH 1 5490 #define MC_CMD_SET_MAC_EXT_IN_CFG_FCS_LBN 4 5491 #define MC_CMD_SET_MAC_EXT_IN_CFG_FCS_WIDTH 1 5492 5493 /* MC_CMD_SET_MAC_OUT msgresponse */ 5494 #define MC_CMD_SET_MAC_OUT_LEN 0 5495 5496 /* MC_CMD_SET_MAC_V2_OUT msgresponse */ 5497 #define MC_CMD_SET_MAC_V2_OUT_LEN 4 5498 /* MTU as configured after processing the request. See comment at 5499 * MC_CMD_SET_MAC_IN/MTU. To query MTU without doing any changes, set CONTROL 5500 * to 0. 5501 */ 5502 #define MC_CMD_SET_MAC_V2_OUT_MTU_OFST 0 5503 5504 5505 /***********************************/ 5506 /* MC_CMD_PHY_STATS 5507 * Get generic PHY statistics. This call returns the statistics for a generic 5508 * PHY in a sparse array (indexed by the enumerate). Each value is represented 5509 * by a 32bit number. If the DMA_ADDR is 0, then no DMA is performed, and the 5510 * statistics may be read from the message response. If DMA_ADDR != 0, then the 5511 * statistics are dmad to that (page-aligned location). Locks required: None. 5512 * Returns: 0, ETIME 5513 */ 5514 #define MC_CMD_PHY_STATS 0x2d 5515 #undef MC_CMD_0x2d_PRIVILEGE_CTG 5516 5517 #define MC_CMD_0x2d_PRIVILEGE_CTG SRIOV_CTG_LINK 5518 5519 /* MC_CMD_PHY_STATS_IN msgrequest */ 5520 #define MC_CMD_PHY_STATS_IN_LEN 8 5521 /* ??? */ 5522 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_OFST 0 5523 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_LEN 8 5524 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_OFST 0 5525 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_HI_OFST 4 5526 5527 /* MC_CMD_PHY_STATS_OUT_DMA msgresponse */ 5528 #define MC_CMD_PHY_STATS_OUT_DMA_LEN 0 5529 5530 /* MC_CMD_PHY_STATS_OUT_NO_DMA msgresponse */ 5531 #define MC_CMD_PHY_STATS_OUT_NO_DMA_LEN (((MC_CMD_PHY_NSTATS*32))>>3) 5532 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_OFST 0 5533 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_LEN 4 5534 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_PHY_NSTATS 5535 /* enum: OUI. */ 5536 #define MC_CMD_OUI 0x0 5537 /* enum: PMA-PMD Link Up. */ 5538 #define MC_CMD_PMA_PMD_LINK_UP 0x1 5539 /* enum: PMA-PMD RX Fault. */ 5540 #define MC_CMD_PMA_PMD_RX_FAULT 0x2 5541 /* enum: PMA-PMD TX Fault. */ 5542 #define MC_CMD_PMA_PMD_TX_FAULT 0x3 5543 /* enum: PMA-PMD Signal */ 5544 #define MC_CMD_PMA_PMD_SIGNAL 0x4 5545 /* enum: PMA-PMD SNR A. */ 5546 #define MC_CMD_PMA_PMD_SNR_A 0x5 5547 /* enum: PMA-PMD SNR B. */ 5548 #define MC_CMD_PMA_PMD_SNR_B 0x6 5549 /* enum: PMA-PMD SNR C. */ 5550 #define MC_CMD_PMA_PMD_SNR_C 0x7 5551 /* enum: PMA-PMD SNR D. */ 5552 #define MC_CMD_PMA_PMD_SNR_D 0x8 5553 /* enum: PCS Link Up. */ 5554 #define MC_CMD_PCS_LINK_UP 0x9 5555 /* enum: PCS RX Fault. */ 5556 #define MC_CMD_PCS_RX_FAULT 0xa 5557 /* enum: PCS TX Fault. */ 5558 #define MC_CMD_PCS_TX_FAULT 0xb 5559 /* enum: PCS BER. */ 5560 #define MC_CMD_PCS_BER 0xc 5561 /* enum: PCS Block Errors. */ 5562 #define MC_CMD_PCS_BLOCK_ERRORS 0xd 5563 /* enum: PhyXS Link Up. */ 5564 #define MC_CMD_PHYXS_LINK_UP 0xe 5565 /* enum: PhyXS RX Fault. */ 5566 #define MC_CMD_PHYXS_RX_FAULT 0xf 5567 /* enum: PhyXS TX Fault. */ 5568 #define MC_CMD_PHYXS_TX_FAULT 0x10 5569 /* enum: PhyXS Align. */ 5570 #define MC_CMD_PHYXS_ALIGN 0x11 5571 /* enum: PhyXS Sync. */ 5572 #define MC_CMD_PHYXS_SYNC 0x12 5573 /* enum: AN link-up. */ 5574 #define MC_CMD_AN_LINK_UP 0x13 5575 /* enum: AN Complete. */ 5576 #define MC_CMD_AN_COMPLETE 0x14 5577 /* enum: AN 10GBaseT Status. */ 5578 #define MC_CMD_AN_10GBT_STATUS 0x15 5579 /* enum: Clause 22 Link-Up. */ 5580 #define MC_CMD_CL22_LINK_UP 0x16 5581 /* enum: (Last entry) */ 5582 #define MC_CMD_PHY_NSTATS 0x17 5583 5584 5585 /***********************************/ 5586 /* MC_CMD_MAC_STATS 5587 * Get generic MAC statistics. This call returns unified statistics maintained 5588 * by the MC as it switches between the GMAC and XMAC. The MC will write out 5589 * all supported stats. The driver should zero initialise the buffer to 5590 * guarantee consistent results. If the DMA_ADDR is 0, then no DMA is 5591 * performed, and the statistics may be read from the message response. If 5592 * DMA_ADDR != 0, then the statistics are dmad to that (page-aligned location). 5593 * Locks required: None. The PERIODIC_CLEAR option is not used and now has no 5594 * effect. Returns: 0, ETIME 5595 */ 5596 #define MC_CMD_MAC_STATS 0x2e 5597 #undef MC_CMD_0x2e_PRIVILEGE_CTG 5598 5599 #define MC_CMD_0x2e_PRIVILEGE_CTG SRIOV_CTG_GENERAL 5600 5601 /* MC_CMD_MAC_STATS_IN msgrequest */ 5602 #define MC_CMD_MAC_STATS_IN_LEN 20 5603 /* ??? */ 5604 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_OFST 0 5605 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_LEN 8 5606 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_OFST 0 5607 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_OFST 4 5608 #define MC_CMD_MAC_STATS_IN_CMD_OFST 8 5609 #define MC_CMD_MAC_STATS_IN_DMA_LBN 0 5610 #define MC_CMD_MAC_STATS_IN_DMA_WIDTH 1 5611 #define MC_CMD_MAC_STATS_IN_CLEAR_LBN 1 5612 #define MC_CMD_MAC_STATS_IN_CLEAR_WIDTH 1 5613 #define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_LBN 2 5614 #define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_WIDTH 1 5615 #define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_LBN 3 5616 #define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_WIDTH 1 5617 #define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_LBN 4 5618 #define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_WIDTH 1 5619 #define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_LBN 5 5620 #define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_WIDTH 1 5621 #define MC_CMD_MAC_STATS_IN_PERIOD_MS_LBN 16 5622 #define MC_CMD_MAC_STATS_IN_PERIOD_MS_WIDTH 16 5623 #define MC_CMD_MAC_STATS_IN_DMA_LEN_OFST 12 5624 /* port id so vadapter stats can be provided */ 5625 #define MC_CMD_MAC_STATS_IN_PORT_ID_OFST 16 5626 5627 /* MC_CMD_MAC_STATS_OUT_DMA msgresponse */ 5628 #define MC_CMD_MAC_STATS_OUT_DMA_LEN 0 5629 5630 /* MC_CMD_MAC_STATS_OUT_NO_DMA msgresponse */ 5631 #define MC_CMD_MAC_STATS_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS*64))>>3) 5632 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_OFST 0 5633 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LEN 8 5634 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_OFST 0 5635 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_OFST 4 5636 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS 5637 #define MC_CMD_MAC_GENERATION_START 0x0 /* enum */ 5638 #define MC_CMD_MAC_DMABUF_START 0x1 /* enum */ 5639 #define MC_CMD_MAC_TX_PKTS 0x1 /* enum */ 5640 #define MC_CMD_MAC_TX_PAUSE_PKTS 0x2 /* enum */ 5641 #define MC_CMD_MAC_TX_CONTROL_PKTS 0x3 /* enum */ 5642 #define MC_CMD_MAC_TX_UNICAST_PKTS 0x4 /* enum */ 5643 #define MC_CMD_MAC_TX_MULTICAST_PKTS 0x5 /* enum */ 5644 #define MC_CMD_MAC_TX_BROADCAST_PKTS 0x6 /* enum */ 5645 #define MC_CMD_MAC_TX_BYTES 0x7 /* enum */ 5646 #define MC_CMD_MAC_TX_BAD_BYTES 0x8 /* enum */ 5647 #define MC_CMD_MAC_TX_LT64_PKTS 0x9 /* enum */ 5648 #define MC_CMD_MAC_TX_64_PKTS 0xa /* enum */ 5649 #define MC_CMD_MAC_TX_65_TO_127_PKTS 0xb /* enum */ 5650 #define MC_CMD_MAC_TX_128_TO_255_PKTS 0xc /* enum */ 5651 #define MC_CMD_MAC_TX_256_TO_511_PKTS 0xd /* enum */ 5652 #define MC_CMD_MAC_TX_512_TO_1023_PKTS 0xe /* enum */ 5653 #define MC_CMD_MAC_TX_1024_TO_15XX_PKTS 0xf /* enum */ 5654 #define MC_CMD_MAC_TX_15XX_TO_JUMBO_PKTS 0x10 /* enum */ 5655 #define MC_CMD_MAC_TX_GTJUMBO_PKTS 0x11 /* enum */ 5656 #define MC_CMD_MAC_TX_BAD_FCS_PKTS 0x12 /* enum */ 5657 #define MC_CMD_MAC_TX_SINGLE_COLLISION_PKTS 0x13 /* enum */ 5658 #define MC_CMD_MAC_TX_MULTIPLE_COLLISION_PKTS 0x14 /* enum */ 5659 #define MC_CMD_MAC_TX_EXCESSIVE_COLLISION_PKTS 0x15 /* enum */ 5660 #define MC_CMD_MAC_TX_LATE_COLLISION_PKTS 0x16 /* enum */ 5661 #define MC_CMD_MAC_TX_DEFERRED_PKTS 0x17 /* enum */ 5662 #define MC_CMD_MAC_TX_EXCESSIVE_DEFERRED_PKTS 0x18 /* enum */ 5663 #define MC_CMD_MAC_TX_NON_TCPUDP_PKTS 0x19 /* enum */ 5664 #define MC_CMD_MAC_TX_MAC_SRC_ERR_PKTS 0x1a /* enum */ 5665 #define MC_CMD_MAC_TX_IP_SRC_ERR_PKTS 0x1b /* enum */ 5666 #define MC_CMD_MAC_RX_PKTS 0x1c /* enum */ 5667 #define MC_CMD_MAC_RX_PAUSE_PKTS 0x1d /* enum */ 5668 #define MC_CMD_MAC_RX_GOOD_PKTS 0x1e /* enum */ 5669 #define MC_CMD_MAC_RX_CONTROL_PKTS 0x1f /* enum */ 5670 #define MC_CMD_MAC_RX_UNICAST_PKTS 0x20 /* enum */ 5671 #define MC_CMD_MAC_RX_MULTICAST_PKTS 0x21 /* enum */ 5672 #define MC_CMD_MAC_RX_BROADCAST_PKTS 0x22 /* enum */ 5673 #define MC_CMD_MAC_RX_BYTES 0x23 /* enum */ 5674 #define MC_CMD_MAC_RX_BAD_BYTES 0x24 /* enum */ 5675 #define MC_CMD_MAC_RX_64_PKTS 0x25 /* enum */ 5676 #define MC_CMD_MAC_RX_65_TO_127_PKTS 0x26 /* enum */ 5677 #define MC_CMD_MAC_RX_128_TO_255_PKTS 0x27 /* enum */ 5678 #define MC_CMD_MAC_RX_256_TO_511_PKTS 0x28 /* enum */ 5679 #define MC_CMD_MAC_RX_512_TO_1023_PKTS 0x29 /* enum */ 5680 #define MC_CMD_MAC_RX_1024_TO_15XX_PKTS 0x2a /* enum */ 5681 #define MC_CMD_MAC_RX_15XX_TO_JUMBO_PKTS 0x2b /* enum */ 5682 #define MC_CMD_MAC_RX_GTJUMBO_PKTS 0x2c /* enum */ 5683 #define MC_CMD_MAC_RX_UNDERSIZE_PKTS 0x2d /* enum */ 5684 #define MC_CMD_MAC_RX_BAD_FCS_PKTS 0x2e /* enum */ 5685 #define MC_CMD_MAC_RX_OVERFLOW_PKTS 0x2f /* enum */ 5686 #define MC_CMD_MAC_RX_FALSE_CARRIER_PKTS 0x30 /* enum */ 5687 #define MC_CMD_MAC_RX_SYMBOL_ERROR_PKTS 0x31 /* enum */ 5688 #define MC_CMD_MAC_RX_ALIGN_ERROR_PKTS 0x32 /* enum */ 5689 #define MC_CMD_MAC_RX_LENGTH_ERROR_PKTS 0x33 /* enum */ 5690 #define MC_CMD_MAC_RX_INTERNAL_ERROR_PKTS 0x34 /* enum */ 5691 #define MC_CMD_MAC_RX_JABBER_PKTS 0x35 /* enum */ 5692 #define MC_CMD_MAC_RX_NODESC_DROPS 0x36 /* enum */ 5693 #define MC_CMD_MAC_RX_LANES01_CHAR_ERR 0x37 /* enum */ 5694 #define MC_CMD_MAC_RX_LANES23_CHAR_ERR 0x38 /* enum */ 5695 #define MC_CMD_MAC_RX_LANES01_DISP_ERR 0x39 /* enum */ 5696 #define MC_CMD_MAC_RX_LANES23_DISP_ERR 0x3a /* enum */ 5697 #define MC_CMD_MAC_RX_MATCH_FAULT 0x3b /* enum */ 5698 /* enum: PM trunc_bb_overflow counter. Valid for EF10 with PM_AND_RXDP_COUNTERS 5699 * capability only. 5700 */ 5701 #define MC_CMD_MAC_PM_TRUNC_BB_OVERFLOW 0x3c 5702 /* enum: PM discard_bb_overflow counter. Valid for EF10 with 5703 * PM_AND_RXDP_COUNTERS capability only. 5704 */ 5705 #define MC_CMD_MAC_PM_DISCARD_BB_OVERFLOW 0x3d 5706 /* enum: PM trunc_vfifo_full counter. Valid for EF10 with PM_AND_RXDP_COUNTERS 5707 * capability only. 5708 */ 5709 #define MC_CMD_MAC_PM_TRUNC_VFIFO_FULL 0x3e 5710 /* enum: PM discard_vfifo_full counter. Valid for EF10 with 5711 * PM_AND_RXDP_COUNTERS capability only. 5712 */ 5713 #define MC_CMD_MAC_PM_DISCARD_VFIFO_FULL 0x3f 5714 /* enum: PM trunc_qbb counter. Valid for EF10 with PM_AND_RXDP_COUNTERS 5715 * capability only. 5716 */ 5717 #define MC_CMD_MAC_PM_TRUNC_QBB 0x40 5718 /* enum: PM discard_qbb counter. Valid for EF10 with PM_AND_RXDP_COUNTERS 5719 * capability only. 5720 */ 5721 #define MC_CMD_MAC_PM_DISCARD_QBB 0x41 5722 /* enum: PM discard_mapping counter. Valid for EF10 with PM_AND_RXDP_COUNTERS 5723 * capability only. 5724 */ 5725 #define MC_CMD_MAC_PM_DISCARD_MAPPING 0x42 5726 /* enum: RXDP counter: Number of packets dropped due to the queue being 5727 * disabled. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only. 5728 */ 5729 #define MC_CMD_MAC_RXDP_Q_DISABLED_PKTS 0x43 5730 /* enum: RXDP counter: Number of packets dropped by the DICPU. Valid for EF10 5731 * with PM_AND_RXDP_COUNTERS capability only. 5732 */ 5733 #define MC_CMD_MAC_RXDP_DI_DROPPED_PKTS 0x45 5734 /* enum: RXDP counter: Number of non-host packets. Valid for EF10 with 5735 * PM_AND_RXDP_COUNTERS capability only. 5736 */ 5737 #define MC_CMD_MAC_RXDP_STREAMING_PKTS 0x46 5738 /* enum: RXDP counter: Number of times an hlb descriptor fetch was performed. 5739 * Valid for EF10 with PM_AND_RXDP_COUNTERS capability only. 5740 */ 5741 #define MC_CMD_MAC_RXDP_HLB_FETCH_CONDITIONS 0x47 5742 /* enum: RXDP counter: Number of times the DPCPU waited for an existing 5743 * descriptor fetch. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only. 5744 */ 5745 #define MC_CMD_MAC_RXDP_HLB_WAIT_CONDITIONS 0x48 5746 #define MC_CMD_MAC_VADAPTER_RX_DMABUF_START 0x4c /* enum */ 5747 #define MC_CMD_MAC_VADAPTER_RX_UNICAST_PACKETS 0x4c /* enum */ 5748 #define MC_CMD_MAC_VADAPTER_RX_UNICAST_BYTES 0x4d /* enum */ 5749 #define MC_CMD_MAC_VADAPTER_RX_MULTICAST_PACKETS 0x4e /* enum */ 5750 #define MC_CMD_MAC_VADAPTER_RX_MULTICAST_BYTES 0x4f /* enum */ 5751 #define MC_CMD_MAC_VADAPTER_RX_BROADCAST_PACKETS 0x50 /* enum */ 5752 #define MC_CMD_MAC_VADAPTER_RX_BROADCAST_BYTES 0x51 /* enum */ 5753 #define MC_CMD_MAC_VADAPTER_RX_BAD_PACKETS 0x52 /* enum */ 5754 #define MC_CMD_MAC_VADAPTER_RX_BAD_BYTES 0x53 /* enum */ 5755 #define MC_CMD_MAC_VADAPTER_RX_OVERFLOW 0x54 /* enum */ 5756 #define MC_CMD_MAC_VADAPTER_TX_DMABUF_START 0x57 /* enum */ 5757 #define MC_CMD_MAC_VADAPTER_TX_UNICAST_PACKETS 0x57 /* enum */ 5758 #define MC_CMD_MAC_VADAPTER_TX_UNICAST_BYTES 0x58 /* enum */ 5759 #define MC_CMD_MAC_VADAPTER_TX_MULTICAST_PACKETS 0x59 /* enum */ 5760 #define MC_CMD_MAC_VADAPTER_TX_MULTICAST_BYTES 0x5a /* enum */ 5761 #define MC_CMD_MAC_VADAPTER_TX_BROADCAST_PACKETS 0x5b /* enum */ 5762 #define MC_CMD_MAC_VADAPTER_TX_BROADCAST_BYTES 0x5c /* enum */ 5763 #define MC_CMD_MAC_VADAPTER_TX_BAD_PACKETS 0x5d /* enum */ 5764 #define MC_CMD_MAC_VADAPTER_TX_BAD_BYTES 0x5e /* enum */ 5765 #define MC_CMD_MAC_VADAPTER_TX_OVERFLOW 0x5f /* enum */ 5766 /* enum: Start of GMAC stats buffer space, for Siena only. */ 5767 #define MC_CMD_GMAC_DMABUF_START 0x40 5768 /* enum: End of GMAC stats buffer space, for Siena only. */ 5769 #define MC_CMD_GMAC_DMABUF_END 0x5f 5770 #define MC_CMD_MAC_GENERATION_END 0x60 /* enum */ 5771 #define MC_CMD_MAC_NSTATS 0x61 /* enum */ 5772 5773 5774 /***********************************/ 5775 /* MC_CMD_SRIOV 5776 * to be documented 5777 */ 5778 #define MC_CMD_SRIOV 0x30 5779 5780 /* MC_CMD_SRIOV_IN msgrequest */ 5781 #define MC_CMD_SRIOV_IN_LEN 12 5782 #define MC_CMD_SRIOV_IN_ENABLE_OFST 0 5783 #define MC_CMD_SRIOV_IN_VI_BASE_OFST 4 5784 #define MC_CMD_SRIOV_IN_VF_COUNT_OFST 8 5785 5786 /* MC_CMD_SRIOV_OUT msgresponse */ 5787 #define MC_CMD_SRIOV_OUT_LEN 8 5788 #define MC_CMD_SRIOV_OUT_VI_SCALE_OFST 0 5789 #define MC_CMD_SRIOV_OUT_VF_TOTAL_OFST 4 5790 5791 /* MC_CMD_MEMCPY_RECORD_TYPEDEF structuredef */ 5792 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LEN 32 5793 /* this is only used for the first record */ 5794 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_OFST 0 5795 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_LBN 0 5796 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_WIDTH 32 5797 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_OFST 4 5798 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_LBN 32 5799 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_WIDTH 32 5800 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_OFST 8 5801 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LEN 8 5802 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LO_OFST 8 5803 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_HI_OFST 12 5804 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LBN 64 5805 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_WIDTH 64 5806 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_OFST 16 5807 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_RID_INLINE 0x100 /* enum */ 5808 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_LBN 128 5809 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_WIDTH 32 5810 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_OFST 20 5811 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LEN 8 5812 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LO_OFST 20 5813 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_HI_OFST 24 5814 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LBN 160 5815 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_WIDTH 64 5816 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_OFST 28 5817 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_LBN 224 5818 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_WIDTH 32 5819 5820 5821 /***********************************/ 5822 /* MC_CMD_MEMCPY 5823 * DMA write data into (Rid,Addr), either by dma reading (Rid,Addr), or by data 5824 * embedded directly in the command. 5825 * 5826 * A common pattern is for a client to use generation counts to signal a dma 5827 * update of a datastructure. To facilitate this, this MCDI operation can 5828 * contain multiple requests which are executed in strict order. Requests take 5829 * the form of duplicating the entire MCDI request continuously (including the 5830 * requests record, which is ignored in all but the first structure) 5831 * 5832 * The source data can either come from a DMA from the host, or it can be 5833 * embedded within the request directly, thereby eliminating a DMA read. To 5834 * indicate this, the client sets FROM_RID=%RID_INLINE, ADDR_HI=0, and 5835 * ADDR_LO=offset, and inserts the data at %offset from the start of the 5836 * payload. It's the callers responsibility to ensure that the embedded data 5837 * doesn't overlap the records. 5838 * 5839 * Returns: 0, EINVAL (invalid RID) 5840 */ 5841 #define MC_CMD_MEMCPY 0x31 5842 5843 /* MC_CMD_MEMCPY_IN msgrequest */ 5844 #define MC_CMD_MEMCPY_IN_LENMIN 32 5845 #define MC_CMD_MEMCPY_IN_LENMAX 224 5846 #define MC_CMD_MEMCPY_IN_LEN(num) (0+32*(num)) 5847 /* see MC_CMD_MEMCPY_RECORD_TYPEDEF */ 5848 #define MC_CMD_MEMCPY_IN_RECORD_OFST 0 5849 #define MC_CMD_MEMCPY_IN_RECORD_LEN 32 5850 #define MC_CMD_MEMCPY_IN_RECORD_MINNUM 1 5851 #define MC_CMD_MEMCPY_IN_RECORD_MAXNUM 7 5852 5853 /* MC_CMD_MEMCPY_OUT msgresponse */ 5854 #define MC_CMD_MEMCPY_OUT_LEN 0 5855 5856 5857 /***********************************/ 5858 /* MC_CMD_WOL_FILTER_SET 5859 * Set a WoL filter. 5860 */ 5861 #define MC_CMD_WOL_FILTER_SET 0x32 5862 #undef MC_CMD_0x32_PRIVILEGE_CTG 5863 5864 #define MC_CMD_0x32_PRIVILEGE_CTG SRIOV_CTG_LINK 5865 5866 /* MC_CMD_WOL_FILTER_SET_IN msgrequest */ 5867 #define MC_CMD_WOL_FILTER_SET_IN_LEN 192 5868 #define MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 5869 #define MC_CMD_FILTER_MODE_SIMPLE 0x0 /* enum */ 5870 #define MC_CMD_FILTER_MODE_STRUCTURED 0xffffffff /* enum */ 5871 /* A type value of 1 is unused. */ 5872 #define MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 5873 /* enum: Magic */ 5874 #define MC_CMD_WOL_TYPE_MAGIC 0x0 5875 /* enum: MS Windows Magic */ 5876 #define MC_CMD_WOL_TYPE_WIN_MAGIC 0x2 5877 /* enum: IPv4 Syn */ 5878 #define MC_CMD_WOL_TYPE_IPV4_SYN 0x3 5879 /* enum: IPv6 Syn */ 5880 #define MC_CMD_WOL_TYPE_IPV6_SYN 0x4 5881 /* enum: Bitmap */ 5882 #define MC_CMD_WOL_TYPE_BITMAP 0x5 5883 /* enum: Link */ 5884 #define MC_CMD_WOL_TYPE_LINK 0x6 5885 /* enum: (Above this for future use) */ 5886 #define MC_CMD_WOL_TYPE_MAX 0x7 5887 #define MC_CMD_WOL_FILTER_SET_IN_DATA_OFST 8 5888 #define MC_CMD_WOL_FILTER_SET_IN_DATA_LEN 4 5889 #define MC_CMD_WOL_FILTER_SET_IN_DATA_NUM 46 5890 5891 /* MC_CMD_WOL_FILTER_SET_IN_MAGIC msgrequest */ 5892 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_LEN 16 5893 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 5894 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 5895 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_OFST 8 5896 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LEN 8 5897 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LO_OFST 8 5898 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_HI_OFST 12 5899 5900 /* MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN msgrequest */ 5901 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_LEN 20 5902 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 5903 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 5904 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_IP_OFST 8 5905 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_IP_OFST 12 5906 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_OFST 16 5907 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_LEN 2 5908 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_OFST 18 5909 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_LEN 2 5910 5911 /* MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN msgrequest */ 5912 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_LEN 44 5913 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 5914 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 5915 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_OFST 8 5916 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_LEN 16 5917 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_OFST 24 5918 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_LEN 16 5919 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_OFST 40 5920 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_LEN 2 5921 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_OFST 42 5922 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_LEN 2 5923 5924 /* MC_CMD_WOL_FILTER_SET_IN_BITMAP msgrequest */ 5925 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN 187 5926 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 5927 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 5928 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_OFST 8 5929 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_LEN 48 5930 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_OFST 56 5931 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_LEN 128 5932 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_OFST 184 5933 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_LEN 1 5934 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_OFST 185 5935 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_LEN 1 5936 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_OFST 186 5937 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_LEN 1 5938 5939 /* MC_CMD_WOL_FILTER_SET_IN_LINK msgrequest */ 5940 #define MC_CMD_WOL_FILTER_SET_IN_LINK_LEN 12 5941 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 5942 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 5943 #define MC_CMD_WOL_FILTER_SET_IN_LINK_MASK_OFST 8 5944 #define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_LBN 0 5945 #define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_WIDTH 1 5946 #define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_LBN 1 5947 #define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_WIDTH 1 5948 5949 /* MC_CMD_WOL_FILTER_SET_OUT msgresponse */ 5950 #define MC_CMD_WOL_FILTER_SET_OUT_LEN 4 5951 #define MC_CMD_WOL_FILTER_SET_OUT_FILTER_ID_OFST 0 5952 5953 5954 /***********************************/ 5955 /* MC_CMD_WOL_FILTER_REMOVE 5956 * Remove a WoL filter. Locks required: None. Returns: 0, EINVAL, ENOSYS 5957 */ 5958 #define MC_CMD_WOL_FILTER_REMOVE 0x33 5959 #undef MC_CMD_0x33_PRIVILEGE_CTG 5960 5961 #define MC_CMD_0x33_PRIVILEGE_CTG SRIOV_CTG_LINK 5962 5963 /* MC_CMD_WOL_FILTER_REMOVE_IN msgrequest */ 5964 #define MC_CMD_WOL_FILTER_REMOVE_IN_LEN 4 5965 #define MC_CMD_WOL_FILTER_REMOVE_IN_FILTER_ID_OFST 0 5966 5967 /* MC_CMD_WOL_FILTER_REMOVE_OUT msgresponse */ 5968 #define MC_CMD_WOL_FILTER_REMOVE_OUT_LEN 0 5969 5970 5971 /***********************************/ 5972 /* MC_CMD_WOL_FILTER_RESET 5973 * Reset (i.e. remove all) WoL filters. Locks required: None. Returns: 0, 5974 * ENOSYS 5975 */ 5976 #define MC_CMD_WOL_FILTER_RESET 0x34 5977 #undef MC_CMD_0x34_PRIVILEGE_CTG 5978 5979 #define MC_CMD_0x34_PRIVILEGE_CTG SRIOV_CTG_LINK 5980 5981 /* MC_CMD_WOL_FILTER_RESET_IN msgrequest */ 5982 #define MC_CMD_WOL_FILTER_RESET_IN_LEN 4 5983 #define MC_CMD_WOL_FILTER_RESET_IN_MASK_OFST 0 5984 #define MC_CMD_WOL_FILTER_RESET_IN_WAKE_FILTERS 0x1 /* enum */ 5985 #define MC_CMD_WOL_FILTER_RESET_IN_LIGHTSOUT_OFFLOADS 0x2 /* enum */ 5986 5987 /* MC_CMD_WOL_FILTER_RESET_OUT msgresponse */ 5988 #define MC_CMD_WOL_FILTER_RESET_OUT_LEN 0 5989 5990 5991 /***********************************/ 5992 /* MC_CMD_SET_MCAST_HASH 5993 * Set the MCAST hash value without otherwise reconfiguring the MAC 5994 */ 5995 #define MC_CMD_SET_MCAST_HASH 0x35 5996 5997 /* MC_CMD_SET_MCAST_HASH_IN msgrequest */ 5998 #define MC_CMD_SET_MCAST_HASH_IN_LEN 32 5999 #define MC_CMD_SET_MCAST_HASH_IN_HASH0_OFST 0 6000 #define MC_CMD_SET_MCAST_HASH_IN_HASH0_LEN 16 6001 #define MC_CMD_SET_MCAST_HASH_IN_HASH1_OFST 16 6002 #define MC_CMD_SET_MCAST_HASH_IN_HASH1_LEN 16 6003 6004 /* MC_CMD_SET_MCAST_HASH_OUT msgresponse */ 6005 #define MC_CMD_SET_MCAST_HASH_OUT_LEN 0 6006 6007 6008 /***********************************/ 6009 /* MC_CMD_NVRAM_TYPES 6010 * Return bitfield indicating available types of virtual NVRAM partitions. 6011 * Locks required: none. Returns: 0 6012 */ 6013 #define MC_CMD_NVRAM_TYPES 0x36 6014 #undef MC_CMD_0x36_PRIVILEGE_CTG 6015 6016 #define MC_CMD_0x36_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6017 6018 /* MC_CMD_NVRAM_TYPES_IN msgrequest */ 6019 #define MC_CMD_NVRAM_TYPES_IN_LEN 0 6020 6021 /* MC_CMD_NVRAM_TYPES_OUT msgresponse */ 6022 #define MC_CMD_NVRAM_TYPES_OUT_LEN 4 6023 /* Bit mask of supported types. */ 6024 #define MC_CMD_NVRAM_TYPES_OUT_TYPES_OFST 0 6025 /* enum: Disabled callisto. */ 6026 #define MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO 0x0 6027 /* enum: MC firmware. */ 6028 #define MC_CMD_NVRAM_TYPE_MC_FW 0x1 6029 /* enum: MC backup firmware. */ 6030 #define MC_CMD_NVRAM_TYPE_MC_FW_BACKUP 0x2 6031 /* enum: Static configuration Port0. */ 6032 #define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0 0x3 6033 /* enum: Static configuration Port1. */ 6034 #define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1 0x4 6035 /* enum: Dynamic configuration Port0. */ 6036 #define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0 0x5 6037 /* enum: Dynamic configuration Port1. */ 6038 #define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1 0x6 6039 /* enum: Expansion Rom. */ 6040 #define MC_CMD_NVRAM_TYPE_EXP_ROM 0x7 6041 /* enum: Expansion Rom Configuration Port0. */ 6042 #define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0 0x8 6043 /* enum: Expansion Rom Configuration Port1. */ 6044 #define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1 0x9 6045 /* enum: Phy Configuration Port0. */ 6046 #define MC_CMD_NVRAM_TYPE_PHY_PORT0 0xa 6047 /* enum: Phy Configuration Port1. */ 6048 #define MC_CMD_NVRAM_TYPE_PHY_PORT1 0xb 6049 /* enum: Log. */ 6050 #define MC_CMD_NVRAM_TYPE_LOG 0xc 6051 /* enum: FPGA image. */ 6052 #define MC_CMD_NVRAM_TYPE_FPGA 0xd 6053 /* enum: FPGA backup image */ 6054 #define MC_CMD_NVRAM_TYPE_FPGA_BACKUP 0xe 6055 /* enum: FC firmware. */ 6056 #define MC_CMD_NVRAM_TYPE_FC_FW 0xf 6057 /* enum: FC backup firmware. */ 6058 #define MC_CMD_NVRAM_TYPE_FC_FW_BACKUP 0x10 6059 /* enum: CPLD image. */ 6060 #define MC_CMD_NVRAM_TYPE_CPLD 0x11 6061 /* enum: Licensing information. */ 6062 #define MC_CMD_NVRAM_TYPE_LICENSE 0x12 6063 /* enum: FC Log. */ 6064 #define MC_CMD_NVRAM_TYPE_FC_LOG 0x13 6065 /* enum: Additional flash on FPGA. */ 6066 #define MC_CMD_NVRAM_TYPE_FC_EXTRA 0x14 6067 6068 6069 /***********************************/ 6070 /* MC_CMD_NVRAM_INFO 6071 * Read info about a virtual NVRAM partition. Locks required: none. Returns: 0, 6072 * EINVAL (bad type). 6073 */ 6074 #define MC_CMD_NVRAM_INFO 0x37 6075 #undef MC_CMD_0x37_PRIVILEGE_CTG 6076 6077 #define MC_CMD_0x37_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6078 6079 /* MC_CMD_NVRAM_INFO_IN msgrequest */ 6080 #define MC_CMD_NVRAM_INFO_IN_LEN 4 6081 #define MC_CMD_NVRAM_INFO_IN_TYPE_OFST 0 6082 /* Enum values, see field(s): */ 6083 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 6084 6085 /* MC_CMD_NVRAM_INFO_OUT msgresponse */ 6086 #define MC_CMD_NVRAM_INFO_OUT_LEN 24 6087 #define MC_CMD_NVRAM_INFO_OUT_TYPE_OFST 0 6088 /* Enum values, see field(s): */ 6089 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 6090 #define MC_CMD_NVRAM_INFO_OUT_SIZE_OFST 4 6091 #define MC_CMD_NVRAM_INFO_OUT_ERASESIZE_OFST 8 6092 #define MC_CMD_NVRAM_INFO_OUT_FLAGS_OFST 12 6093 #define MC_CMD_NVRAM_INFO_OUT_PROTECTED_LBN 0 6094 #define MC_CMD_NVRAM_INFO_OUT_PROTECTED_WIDTH 1 6095 #define MC_CMD_NVRAM_INFO_OUT_TLV_LBN 1 6096 #define MC_CMD_NVRAM_INFO_OUT_TLV_WIDTH 1 6097 #define MC_CMD_NVRAM_INFO_OUT_A_B_LBN 7 6098 #define MC_CMD_NVRAM_INFO_OUT_A_B_WIDTH 1 6099 #define MC_CMD_NVRAM_INFO_OUT_PHYSDEV_OFST 16 6100 #define MC_CMD_NVRAM_INFO_OUT_PHYSADDR_OFST 20 6101 6102 /* MC_CMD_NVRAM_INFO_V2_OUT msgresponse */ 6103 #define MC_CMD_NVRAM_INFO_V2_OUT_LEN 28 6104 #define MC_CMD_NVRAM_INFO_V2_OUT_TYPE_OFST 0 6105 /* Enum values, see field(s): */ 6106 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 6107 #define MC_CMD_NVRAM_INFO_V2_OUT_SIZE_OFST 4 6108 #define MC_CMD_NVRAM_INFO_V2_OUT_ERASESIZE_OFST 8 6109 #define MC_CMD_NVRAM_INFO_V2_OUT_FLAGS_OFST 12 6110 #define MC_CMD_NVRAM_INFO_V2_OUT_PROTECTED_LBN 0 6111 #define MC_CMD_NVRAM_INFO_V2_OUT_PROTECTED_WIDTH 1 6112 #define MC_CMD_NVRAM_INFO_V2_OUT_TLV_LBN 1 6113 #define MC_CMD_NVRAM_INFO_V2_OUT_TLV_WIDTH 1 6114 #define MC_CMD_NVRAM_INFO_V2_OUT_A_B_LBN 7 6115 #define MC_CMD_NVRAM_INFO_V2_OUT_A_B_WIDTH 1 6116 #define MC_CMD_NVRAM_INFO_V2_OUT_PHYSDEV_OFST 16 6117 #define MC_CMD_NVRAM_INFO_V2_OUT_PHYSADDR_OFST 20 6118 /* Writes must be multiples of this size. Added to support the MUM on Sorrento. 6119 */ 6120 #define MC_CMD_NVRAM_INFO_V2_OUT_WRITESIZE_OFST 24 6121 6122 6123 /***********************************/ 6124 /* MC_CMD_NVRAM_UPDATE_START 6125 * Start a group of update operations on a virtual NVRAM partition. Locks 6126 * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad type), EACCES (if 6127 * PHY_LOCK required and not held). 6128 */ 6129 #define MC_CMD_NVRAM_UPDATE_START 0x38 6130 #undef MC_CMD_0x38_PRIVILEGE_CTG 6131 6132 #define MC_CMD_0x38_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6133 6134 /* MC_CMD_NVRAM_UPDATE_START_IN msgrequest */ 6135 #define MC_CMD_NVRAM_UPDATE_START_IN_LEN 4 6136 #define MC_CMD_NVRAM_UPDATE_START_IN_TYPE_OFST 0 6137 /* Enum values, see field(s): */ 6138 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 6139 6140 /* MC_CMD_NVRAM_UPDATE_START_OUT msgresponse */ 6141 #define MC_CMD_NVRAM_UPDATE_START_OUT_LEN 0 6142 6143 6144 /***********************************/ 6145 /* MC_CMD_NVRAM_READ 6146 * Read data from a virtual NVRAM partition. Locks required: PHY_LOCK if 6147 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if 6148 * PHY_LOCK required and not held) 6149 */ 6150 #define MC_CMD_NVRAM_READ 0x39 6151 #undef MC_CMD_0x39_PRIVILEGE_CTG 6152 6153 #define MC_CMD_0x39_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6154 6155 /* MC_CMD_NVRAM_READ_IN msgrequest */ 6156 #define MC_CMD_NVRAM_READ_IN_LEN 12 6157 #define MC_CMD_NVRAM_READ_IN_TYPE_OFST 0 6158 /* Enum values, see field(s): */ 6159 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 6160 #define MC_CMD_NVRAM_READ_IN_OFFSET_OFST 4 6161 /* amount to read in bytes */ 6162 #define MC_CMD_NVRAM_READ_IN_LENGTH_OFST 8 6163 6164 /* MC_CMD_NVRAM_READ_IN_V2 msgrequest */ 6165 #define MC_CMD_NVRAM_READ_IN_V2_LEN 16 6166 #define MC_CMD_NVRAM_READ_IN_V2_TYPE_OFST 0 6167 /* Enum values, see field(s): */ 6168 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 6169 #define MC_CMD_NVRAM_READ_IN_V2_OFFSET_OFST 4 6170 /* amount to read in bytes */ 6171 #define MC_CMD_NVRAM_READ_IN_V2_LENGTH_OFST 8 6172 /* Optional control info. If a partition is stored with an A/B versioning 6173 * scheme (i.e. in more than one physical partition in NVRAM) the host can set 6174 * this to control which underlying physical partition is used to read data 6175 * from. This allows it to perform a read-modify-write-verify with the write 6176 * lock continuously held by calling NVRAM_UPDATE_START, reading the old 6177 * contents using MODE=TARGET_CURRENT, overwriting the old partition and then 6178 * verifying by reading with MODE=TARGET_BACKUP. 6179 */ 6180 #define MC_CMD_NVRAM_READ_IN_V2_MODE_OFST 12 6181 /* enum: Same as omitting MODE: caller sees data in current partition unless it 6182 * holds the write lock in which case it sees data in the partition it is 6183 * updating. 6184 */ 6185 #define MC_CMD_NVRAM_READ_IN_V2_DEFAULT 0x0 6186 /* enum: Read from the current partition of an A/B pair, even if holding the 6187 * write lock. 6188 */ 6189 #define MC_CMD_NVRAM_READ_IN_V2_TARGET_CURRENT 0x1 6190 /* enum: Read from the non-current (i.e. to be updated) partition of an A/B 6191 * pair 6192 */ 6193 #define MC_CMD_NVRAM_READ_IN_V2_TARGET_BACKUP 0x2 6194 6195 /* MC_CMD_NVRAM_READ_OUT msgresponse */ 6196 #define MC_CMD_NVRAM_READ_OUT_LENMIN 1 6197 #define MC_CMD_NVRAM_READ_OUT_LENMAX 252 6198 #define MC_CMD_NVRAM_READ_OUT_LEN(num) (0+1*(num)) 6199 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_OFST 0 6200 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_LEN 1 6201 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MINNUM 1 6202 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MAXNUM 252 6203 6204 6205 /***********************************/ 6206 /* MC_CMD_NVRAM_WRITE 6207 * Write data to a virtual NVRAM partition. Locks required: PHY_LOCK if 6208 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if 6209 * PHY_LOCK required and not held) 6210 */ 6211 #define MC_CMD_NVRAM_WRITE 0x3a 6212 #undef MC_CMD_0x3a_PRIVILEGE_CTG 6213 6214 #define MC_CMD_0x3a_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6215 6216 /* MC_CMD_NVRAM_WRITE_IN msgrequest */ 6217 #define MC_CMD_NVRAM_WRITE_IN_LENMIN 13 6218 #define MC_CMD_NVRAM_WRITE_IN_LENMAX 252 6219 #define MC_CMD_NVRAM_WRITE_IN_LEN(num) (12+1*(num)) 6220 #define MC_CMD_NVRAM_WRITE_IN_TYPE_OFST 0 6221 /* Enum values, see field(s): */ 6222 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 6223 #define MC_CMD_NVRAM_WRITE_IN_OFFSET_OFST 4 6224 #define MC_CMD_NVRAM_WRITE_IN_LENGTH_OFST 8 6225 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_OFST 12 6226 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_LEN 1 6227 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MINNUM 1 6228 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MAXNUM 240 6229 6230 /* MC_CMD_NVRAM_WRITE_OUT msgresponse */ 6231 #define MC_CMD_NVRAM_WRITE_OUT_LEN 0 6232 6233 6234 /***********************************/ 6235 /* MC_CMD_NVRAM_ERASE 6236 * Erase sector(s) from a virtual NVRAM partition. Locks required: PHY_LOCK if 6237 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if 6238 * PHY_LOCK required and not held) 6239 */ 6240 #define MC_CMD_NVRAM_ERASE 0x3b 6241 #undef MC_CMD_0x3b_PRIVILEGE_CTG 6242 6243 #define MC_CMD_0x3b_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6244 6245 /* MC_CMD_NVRAM_ERASE_IN msgrequest */ 6246 #define MC_CMD_NVRAM_ERASE_IN_LEN 12 6247 #define MC_CMD_NVRAM_ERASE_IN_TYPE_OFST 0 6248 /* Enum values, see field(s): */ 6249 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 6250 #define MC_CMD_NVRAM_ERASE_IN_OFFSET_OFST 4 6251 #define MC_CMD_NVRAM_ERASE_IN_LENGTH_OFST 8 6252 6253 /* MC_CMD_NVRAM_ERASE_OUT msgresponse */ 6254 #define MC_CMD_NVRAM_ERASE_OUT_LEN 0 6255 6256 6257 /***********************************/ 6258 /* MC_CMD_NVRAM_UPDATE_FINISH 6259 * Finish a group of update operations on a virtual NVRAM partition. Locks 6260 * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad 6261 * type/offset/length), EACCES (if PHY_LOCK required and not held) 6262 */ 6263 #define MC_CMD_NVRAM_UPDATE_FINISH 0x3c 6264 #undef MC_CMD_0x3c_PRIVILEGE_CTG 6265 6266 #define MC_CMD_0x3c_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6267 6268 /* MC_CMD_NVRAM_UPDATE_FINISH_IN msgrequest */ 6269 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_LEN 8 6270 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_TYPE_OFST 0 6271 /* Enum values, see field(s): */ 6272 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 6273 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_REBOOT_OFST 4 6274 6275 /* MC_CMD_NVRAM_UPDATE_FINISH_OUT msgresponse */ 6276 #define MC_CMD_NVRAM_UPDATE_FINISH_OUT_LEN 0 6277 6278 6279 /***********************************/ 6280 /* MC_CMD_REBOOT 6281 * Reboot the MC. 6282 * 6283 * The AFTER_ASSERTION flag is intended to be used when the driver notices an 6284 * assertion failure (at which point it is expected to perform a complete tear 6285 * down and reinitialise), to allow both ports to reset the MC once in an 6286 * atomic fashion. 6287 * 6288 * Production mc firmwares are generally compiled with REBOOT_ON_ASSERT=1, 6289 * which means that they will automatically reboot out of the assertion 6290 * handler, so this is in practise an optional operation. It is still 6291 * recommended that drivers execute this to support custom firmwares with 6292 * REBOOT_ON_ASSERT=0. 6293 * 6294 * Locks required: NONE Returns: Nothing. You get back a response with ERR=1, 6295 * DATALEN=0 6296 */ 6297 #define MC_CMD_REBOOT 0x3d 6298 #undef MC_CMD_0x3d_PRIVILEGE_CTG 6299 6300 #define MC_CMD_0x3d_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6301 6302 /* MC_CMD_REBOOT_IN msgrequest */ 6303 #define MC_CMD_REBOOT_IN_LEN 4 6304 #define MC_CMD_REBOOT_IN_FLAGS_OFST 0 6305 #define MC_CMD_REBOOT_FLAGS_AFTER_ASSERTION 0x1 /* enum */ 6306 6307 /* MC_CMD_REBOOT_OUT msgresponse */ 6308 #define MC_CMD_REBOOT_OUT_LEN 0 6309 6310 6311 /***********************************/ 6312 /* MC_CMD_SCHEDINFO 6313 * Request scheduler info. Locks required: NONE. Returns: An array of 6314 * (timeslice,maximum overrun), one for each thread, in ascending order of 6315 * thread address. 6316 */ 6317 #define MC_CMD_SCHEDINFO 0x3e 6318 #undef MC_CMD_0x3e_PRIVILEGE_CTG 6319 6320 #define MC_CMD_0x3e_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6321 6322 /* MC_CMD_SCHEDINFO_IN msgrequest */ 6323 #define MC_CMD_SCHEDINFO_IN_LEN 0 6324 6325 /* MC_CMD_SCHEDINFO_OUT msgresponse */ 6326 #define MC_CMD_SCHEDINFO_OUT_LENMIN 4 6327 #define MC_CMD_SCHEDINFO_OUT_LENMAX 252 6328 #define MC_CMD_SCHEDINFO_OUT_LEN(num) (0+4*(num)) 6329 #define MC_CMD_SCHEDINFO_OUT_DATA_OFST 0 6330 #define MC_CMD_SCHEDINFO_OUT_DATA_LEN 4 6331 #define MC_CMD_SCHEDINFO_OUT_DATA_MINNUM 1 6332 #define MC_CMD_SCHEDINFO_OUT_DATA_MAXNUM 63 6333 6334 6335 /***********************************/ 6336 /* MC_CMD_REBOOT_MODE 6337 * Set the mode for the next MC reboot. Locks required: NONE. Sets the reboot 6338 * mode to the specified value. Returns the old mode. 6339 */ 6340 #define MC_CMD_REBOOT_MODE 0x3f 6341 #undef MC_CMD_0x3f_PRIVILEGE_CTG 6342 6343 #define MC_CMD_0x3f_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6344 6345 /* MC_CMD_REBOOT_MODE_IN msgrequest */ 6346 #define MC_CMD_REBOOT_MODE_IN_LEN 4 6347 #define MC_CMD_REBOOT_MODE_IN_VALUE_OFST 0 6348 /* enum: Normal. */ 6349 #define MC_CMD_REBOOT_MODE_NORMAL 0x0 6350 /* enum: Power-on Reset. */ 6351 #define MC_CMD_REBOOT_MODE_POR 0x2 6352 /* enum: Snapper. */ 6353 #define MC_CMD_REBOOT_MODE_SNAPPER 0x3 6354 /* enum: snapper fake POR */ 6355 #define MC_CMD_REBOOT_MODE_SNAPPER_POR 0x4 6356 #define MC_CMD_REBOOT_MODE_IN_FAKE_LBN 7 6357 #define MC_CMD_REBOOT_MODE_IN_FAKE_WIDTH 1 6358 6359 /* MC_CMD_REBOOT_MODE_OUT msgresponse */ 6360 #define MC_CMD_REBOOT_MODE_OUT_LEN 4 6361 #define MC_CMD_REBOOT_MODE_OUT_VALUE_OFST 0 6362 6363 6364 /***********************************/ 6365 /* MC_CMD_SENSOR_INFO 6366 * Returns information about every available sensor. 6367 * 6368 * Each sensor has a single (16bit) value, and a corresponding state. The 6369 * mapping between value and state is nominally determined by the MC, but may 6370 * be implemented using up to 2 ranges per sensor. 6371 * 6372 * This call returns a mask (32bit) of the sensors that are supported by this 6373 * platform, then an array of sensor information structures, in order of sensor 6374 * type (but without gaps for unimplemented sensors). Each structure defines 6375 * the ranges for the corresponding sensor. An unused range is indicated by 6376 * equal limit values. If one range is used, a value outside that range results 6377 * in STATE_FATAL. If two ranges are used, a value outside the second range 6378 * results in STATE_FATAL while a value outside the first and inside the second 6379 * range results in STATE_WARNING. 6380 * 6381 * Sensor masks and sensor information arrays are organised into pages. For 6382 * backward compatibility, older host software can only use sensors in page 0. 6383 * Bit 32 in the sensor mask was previously unused, and is no reserved for use 6384 * as the next page flag. 6385 * 6386 * If the request does not contain a PAGE value then firmware will only return 6387 * page 0 of sensor information, with bit 31 in the sensor mask cleared. 6388 * 6389 * If the request contains a PAGE value then firmware responds with the sensor 6390 * mask and sensor information array for that page of sensors. In this case bit 6391 * 31 in the mask is set if another page exists. 6392 * 6393 * Locks required: None Returns: 0 6394 */ 6395 #define MC_CMD_SENSOR_INFO 0x41 6396 #undef MC_CMD_0x41_PRIVILEGE_CTG 6397 6398 #define MC_CMD_0x41_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6399 6400 /* MC_CMD_SENSOR_INFO_IN msgrequest */ 6401 #define MC_CMD_SENSOR_INFO_IN_LEN 0 6402 6403 /* MC_CMD_SENSOR_INFO_EXT_IN msgrequest */ 6404 #define MC_CMD_SENSOR_INFO_EXT_IN_LEN 4 6405 /* Which page of sensors to report. 6406 * 6407 * Page 0 contains sensors 0 to 30 (sensor 31 is the next page bit). 6408 * 6409 * Page 1 contains sensors 32 to 62 (sensor 63 is the next page bit). etc. 6410 */ 6411 #define MC_CMD_SENSOR_INFO_EXT_IN_PAGE_OFST 0 6412 6413 /* MC_CMD_SENSOR_INFO_OUT msgresponse */ 6414 #define MC_CMD_SENSOR_INFO_OUT_LENMIN 4 6415 #define MC_CMD_SENSOR_INFO_OUT_LENMAX 252 6416 #define MC_CMD_SENSOR_INFO_OUT_LEN(num) (4+8*(num)) 6417 #define MC_CMD_SENSOR_INFO_OUT_MASK_OFST 0 6418 /* enum: Controller temperature: degC */ 6419 #define MC_CMD_SENSOR_CONTROLLER_TEMP 0x0 6420 /* enum: Phy common temperature: degC */ 6421 #define MC_CMD_SENSOR_PHY_COMMON_TEMP 0x1 6422 /* enum: Controller cooling: bool */ 6423 #define MC_CMD_SENSOR_CONTROLLER_COOLING 0x2 6424 /* enum: Phy 0 temperature: degC */ 6425 #define MC_CMD_SENSOR_PHY0_TEMP 0x3 6426 /* enum: Phy 0 cooling: bool */ 6427 #define MC_CMD_SENSOR_PHY0_COOLING 0x4 6428 /* enum: Phy 1 temperature: degC */ 6429 #define MC_CMD_SENSOR_PHY1_TEMP 0x5 6430 /* enum: Phy 1 cooling: bool */ 6431 #define MC_CMD_SENSOR_PHY1_COOLING 0x6 6432 /* enum: 1.0v power: mV */ 6433 #define MC_CMD_SENSOR_IN_1V0 0x7 6434 /* enum: 1.2v power: mV */ 6435 #define MC_CMD_SENSOR_IN_1V2 0x8 6436 /* enum: 1.8v power: mV */ 6437 #define MC_CMD_SENSOR_IN_1V8 0x9 6438 /* enum: 2.5v power: mV */ 6439 #define MC_CMD_SENSOR_IN_2V5 0xa 6440 /* enum: 3.3v power: mV */ 6441 #define MC_CMD_SENSOR_IN_3V3 0xb 6442 /* enum: 12v power: mV */ 6443 #define MC_CMD_SENSOR_IN_12V0 0xc 6444 /* enum: 1.2v analogue power: mV */ 6445 #define MC_CMD_SENSOR_IN_1V2A 0xd 6446 /* enum: reference voltage: mV */ 6447 #define MC_CMD_SENSOR_IN_VREF 0xe 6448 /* enum: AOE FPGA power: mV */ 6449 #define MC_CMD_SENSOR_OUT_VAOE 0xf 6450 /* enum: AOE FPGA temperature: degC */ 6451 #define MC_CMD_SENSOR_AOE_TEMP 0x10 6452 /* enum: AOE FPGA PSU temperature: degC */ 6453 #define MC_CMD_SENSOR_PSU_AOE_TEMP 0x11 6454 /* enum: AOE PSU temperature: degC */ 6455 #define MC_CMD_SENSOR_PSU_TEMP 0x12 6456 /* enum: Fan 0 speed: RPM */ 6457 #define MC_CMD_SENSOR_FAN_0 0x13 6458 /* enum: Fan 1 speed: RPM */ 6459 #define MC_CMD_SENSOR_FAN_1 0x14 6460 /* enum: Fan 2 speed: RPM */ 6461 #define MC_CMD_SENSOR_FAN_2 0x15 6462 /* enum: Fan 3 speed: RPM */ 6463 #define MC_CMD_SENSOR_FAN_3 0x16 6464 /* enum: Fan 4 speed: RPM */ 6465 #define MC_CMD_SENSOR_FAN_4 0x17 6466 /* enum: AOE FPGA input power: mV */ 6467 #define MC_CMD_SENSOR_IN_VAOE 0x18 6468 /* enum: AOE FPGA current: mA */ 6469 #define MC_CMD_SENSOR_OUT_IAOE 0x19 6470 /* enum: AOE FPGA input current: mA */ 6471 #define MC_CMD_SENSOR_IN_IAOE 0x1a 6472 /* enum: NIC power consumption: W */ 6473 #define MC_CMD_SENSOR_NIC_POWER 0x1b 6474 /* enum: 0.9v power voltage: mV */ 6475 #define MC_CMD_SENSOR_IN_0V9 0x1c 6476 /* enum: 0.9v power current: mA */ 6477 #define MC_CMD_SENSOR_IN_I0V9 0x1d 6478 /* enum: 1.2v power current: mA */ 6479 #define MC_CMD_SENSOR_IN_I1V2 0x1e 6480 /* enum: Not a sensor: reserved for the next page flag */ 6481 #define MC_CMD_SENSOR_PAGE0_NEXT 0x1f 6482 /* enum: 0.9v power voltage (at ADC): mV */ 6483 #define MC_CMD_SENSOR_IN_0V9_ADC 0x20 6484 /* enum: Controller temperature 2: degC */ 6485 #define MC_CMD_SENSOR_CONTROLLER_2_TEMP 0x21 6486 /* enum: Voltage regulator internal temperature: degC */ 6487 #define MC_CMD_SENSOR_VREG_INTERNAL_TEMP 0x22 6488 /* enum: 0.9V voltage regulator temperature: degC */ 6489 #define MC_CMD_SENSOR_VREG_0V9_TEMP 0x23 6490 /* enum: 1.2V voltage regulator temperature: degC */ 6491 #define MC_CMD_SENSOR_VREG_1V2_TEMP 0x24 6492 /* enum: controller internal temperature sensor voltage (internal ADC): mV */ 6493 #define MC_CMD_SENSOR_CONTROLLER_VPTAT 0x25 6494 /* enum: controller internal temperature (internal ADC): degC */ 6495 #define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP 0x26 6496 /* enum: controller internal temperature sensor voltage (external ADC): mV */ 6497 #define MC_CMD_SENSOR_CONTROLLER_VPTAT_EXTADC 0x27 6498 /* enum: controller internal temperature (external ADC): degC */ 6499 #define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP_EXTADC 0x28 6500 /* enum: ambient temperature: degC */ 6501 #define MC_CMD_SENSOR_AMBIENT_TEMP 0x29 6502 /* enum: air flow: bool */ 6503 #define MC_CMD_SENSOR_AIRFLOW 0x2a 6504 /* enum: voltage between VSS08D and VSS08D at CSR: mV */ 6505 #define MC_CMD_SENSOR_VDD08D_VSS08D_CSR 0x2b 6506 /* enum: voltage between VSS08D and VSS08D at CSR (external ADC): mV */ 6507 #define MC_CMD_SENSOR_VDD08D_VSS08D_CSR_EXTADC 0x2c 6508 /* enum: Hotpoint temperature: degC */ 6509 #define MC_CMD_SENSOR_HOTPOINT_TEMP 0x2d 6510 /* enum: Port 0 PHY power switch over-current: bool */ 6511 #define MC_CMD_SENSOR_PHY_POWER_PORT0 0x2e 6512 /* enum: Port 1 PHY power switch over-current: bool */ 6513 #define MC_CMD_SENSOR_PHY_POWER_PORT1 0x2f 6514 /* enum: Mop-up microcontroller reference voltage (millivolts) */ 6515 #define MC_CMD_SENSOR_MUM_VCC 0x30 6516 /* enum: 0.9v power phase A voltage: mV */ 6517 #define MC_CMD_SENSOR_IN_0V9_A 0x31 6518 /* enum: 0.9v power phase A current: mA */ 6519 #define MC_CMD_SENSOR_IN_I0V9_A 0x32 6520 /* enum: 0.9V voltage regulator phase A temperature: degC */ 6521 #define MC_CMD_SENSOR_VREG_0V9_A_TEMP 0x33 6522 /* enum: 0.9v power phase B voltage: mV */ 6523 #define MC_CMD_SENSOR_IN_0V9_B 0x34 6524 /* enum: 0.9v power phase B current: mA */ 6525 #define MC_CMD_SENSOR_IN_I0V9_B 0x35 6526 /* enum: 0.9V voltage regulator phase B temperature: degC */ 6527 #define MC_CMD_SENSOR_VREG_0V9_B_TEMP 0x36 6528 /* enum: CCOM AVREG 1v2 supply (interval ADC): mV */ 6529 #define MC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY 0x37 6530 /* enum: CCOM AVREG 1v2 supply (external ADC): mV */ 6531 #define MC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY_EXTADC 0x38 6532 /* enum: CCOM AVREG 1v8 supply (interval ADC): mV */ 6533 #define MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY 0x39 6534 /* enum: CCOM AVREG 1v8 supply (external ADC): mV */ 6535 #define MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY_EXTADC 0x3a 6536 /* enum: CCOM RTS temperature: degC */ 6537 #define MC_CMD_SENSOR_CONTROLLER_RTS 0x3b 6538 /* enum: Not a sensor: reserved for the next page flag */ 6539 #define MC_CMD_SENSOR_PAGE1_NEXT 0x3f 6540 /* enum: controller internal temperature sensor voltage on master core 6541 * (internal ADC): mV 6542 */ 6543 #define MC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT 0x40 6544 /* enum: controller internal temperature on master core (internal ADC): degC */ 6545 #define MC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP 0x41 6546 /* enum: controller internal temperature sensor voltage on master core 6547 * (external ADC): mV 6548 */ 6549 #define MC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT_EXTADC 0x42 6550 /* enum: controller internal temperature on master core (external ADC): degC */ 6551 #define MC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC 0x43 6552 /* enum: controller internal temperature on slave core sensor voltage (internal 6553 * ADC): mV 6554 */ 6555 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT 0x44 6556 /* enum: controller internal temperature on slave core (internal ADC): degC */ 6557 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP 0x45 6558 /* enum: controller internal temperature on slave core sensor voltage (external 6559 * ADC): mV 6560 */ 6561 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT_EXTADC 0x46 6562 /* enum: controller internal temperature on slave core (external ADC): degC */ 6563 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC 0x47 6564 /* enum: Voltage supplied to the SODIMMs from their power supply: mV */ 6565 #define MC_CMD_SENSOR_SODIMM_VOUT 0x49 6566 /* enum: Temperature of SODIMM 0 (if installed): degC */ 6567 #define MC_CMD_SENSOR_SODIMM_0_TEMP 0x4a 6568 /* enum: Temperature of SODIMM 1 (if installed): degC */ 6569 #define MC_CMD_SENSOR_SODIMM_1_TEMP 0x4b 6570 /* enum: Voltage supplied to the QSFP #0 from their power supply: mV */ 6571 #define MC_CMD_SENSOR_PHY0_VCC 0x4c 6572 /* enum: Voltage supplied to the QSFP #1 from their power supply: mV */ 6573 #define MC_CMD_SENSOR_PHY1_VCC 0x4d 6574 /* enum: Controller die temperature (TDIODE): degC */ 6575 #define MC_CMD_SENSOR_CONTROLLER_TDIODE_TEMP 0x4e 6576 /* enum: Board temperature (front): degC */ 6577 #define MC_CMD_SENSOR_BOARD_FRONT_TEMP 0x4f 6578 /* enum: Board temperature (back): degC */ 6579 #define MC_CMD_SENSOR_BOARD_BACK_TEMP 0x50 6580 /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */ 6581 #define MC_CMD_SENSOR_ENTRY_OFST 4 6582 #define MC_CMD_SENSOR_ENTRY_LEN 8 6583 #define MC_CMD_SENSOR_ENTRY_LO_OFST 4 6584 #define MC_CMD_SENSOR_ENTRY_HI_OFST 8 6585 #define MC_CMD_SENSOR_ENTRY_MINNUM 0 6586 #define MC_CMD_SENSOR_ENTRY_MAXNUM 31 6587 6588 /* MC_CMD_SENSOR_INFO_EXT_OUT msgresponse */ 6589 #define MC_CMD_SENSOR_INFO_EXT_OUT_LENMIN 4 6590 #define MC_CMD_SENSOR_INFO_EXT_OUT_LENMAX 252 6591 #define MC_CMD_SENSOR_INFO_EXT_OUT_LEN(num) (4+8*(num)) 6592 #define MC_CMD_SENSOR_INFO_EXT_OUT_MASK_OFST 0 6593 /* Enum values, see field(s): */ 6594 /* MC_CMD_SENSOR_INFO_OUT */ 6595 #define MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_LBN 31 6596 #define MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_WIDTH 1 6597 /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */ 6598 /* MC_CMD_SENSOR_ENTRY_OFST 4 */ 6599 /* MC_CMD_SENSOR_ENTRY_LEN 8 */ 6600 /* MC_CMD_SENSOR_ENTRY_LO_OFST 4 */ 6601 /* MC_CMD_SENSOR_ENTRY_HI_OFST 8 */ 6602 /* MC_CMD_SENSOR_ENTRY_MINNUM 0 */ 6603 /* MC_CMD_SENSOR_ENTRY_MAXNUM 31 */ 6604 6605 /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF structuredef */ 6606 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_LEN 8 6607 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_OFST 0 6608 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LEN 2 6609 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LBN 0 6610 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_WIDTH 16 6611 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_OFST 2 6612 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LEN 2 6613 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LBN 16 6614 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_WIDTH 16 6615 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_OFST 4 6616 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LEN 2 6617 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LBN 32 6618 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_WIDTH 16 6619 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_OFST 6 6620 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LEN 2 6621 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LBN 48 6622 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_WIDTH 16 6623 6624 6625 /***********************************/ 6626 /* MC_CMD_READ_SENSORS 6627 * Returns the current reading from each sensor. DMAs an array of sensor 6628 * readings, in order of sensor type (but without gaps for unimplemented 6629 * sensors), into host memory. Each array element is a 6630 * MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF dword. 6631 * 6632 * If the request does not contain the LENGTH field then only sensors 0 to 30 6633 * are reported, to avoid DMA buffer overflow in older host software. If the 6634 * sensor reading require more space than the LENGTH allows, then return 6635 * EINVAL. 6636 * 6637 * The MC will send a SENSOREVT event every time any sensor changes state. The 6638 * driver is responsible for ensuring that it doesn't miss any events. The 6639 * board will function normally if all sensors are in STATE_OK or 6640 * STATE_WARNING. Otherwise the board should not be expected to function. 6641 */ 6642 #define MC_CMD_READ_SENSORS 0x42 6643 #undef MC_CMD_0x42_PRIVILEGE_CTG 6644 6645 #define MC_CMD_0x42_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6646 6647 /* MC_CMD_READ_SENSORS_IN msgrequest */ 6648 #define MC_CMD_READ_SENSORS_IN_LEN 8 6649 /* DMA address of host buffer for sensor readings (must be 4Kbyte aligned). */ 6650 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_OFST 0 6651 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LEN 8 6652 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_OFST 0 6653 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_OFST 4 6654 6655 /* MC_CMD_READ_SENSORS_EXT_IN msgrequest */ 6656 #define MC_CMD_READ_SENSORS_EXT_IN_LEN 12 6657 /* DMA address of host buffer for sensor readings (must be 4Kbyte aligned). */ 6658 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_OFST 0 6659 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LEN 8 6660 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_OFST 0 6661 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_HI_OFST 4 6662 /* Size in bytes of host buffer. */ 6663 #define MC_CMD_READ_SENSORS_EXT_IN_LENGTH_OFST 8 6664 6665 /* MC_CMD_READ_SENSORS_OUT msgresponse */ 6666 #define MC_CMD_READ_SENSORS_OUT_LEN 0 6667 6668 /* MC_CMD_READ_SENSORS_EXT_OUT msgresponse */ 6669 #define MC_CMD_READ_SENSORS_EXT_OUT_LEN 0 6670 6671 /* MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF structuredef */ 6672 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_LEN 4 6673 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_OFST 0 6674 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LEN 2 6675 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LBN 0 6676 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_WIDTH 16 6677 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_OFST 2 6678 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LEN 1 6679 /* enum: Ok. */ 6680 #define MC_CMD_SENSOR_STATE_OK 0x0 6681 /* enum: Breached warning threshold. */ 6682 #define MC_CMD_SENSOR_STATE_WARNING 0x1 6683 /* enum: Breached fatal threshold. */ 6684 #define MC_CMD_SENSOR_STATE_FATAL 0x2 6685 /* enum: Fault with sensor. */ 6686 #define MC_CMD_SENSOR_STATE_BROKEN 0x3 6687 /* enum: Sensor is working but does not currently have a reading. */ 6688 #define MC_CMD_SENSOR_STATE_NO_READING 0x4 6689 /* enum: Sensor initialisation failed. */ 6690 #define MC_CMD_SENSOR_STATE_INIT_FAILED 0x5 6691 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LBN 16 6692 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_WIDTH 8 6693 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_OFST 3 6694 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_LEN 1 6695 /* Enum values, see field(s): */ 6696 /* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */ 6697 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_LBN 24 6698 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_WIDTH 8 6699 6700 6701 /***********************************/ 6702 /* MC_CMD_GET_PHY_STATE 6703 * Report current state of PHY. A 'zombie' PHY is a PHY that has failed to boot 6704 * (e.g. due to missing or corrupted firmware). Locks required: None. Return 6705 * code: 0 6706 */ 6707 #define MC_CMD_GET_PHY_STATE 0x43 6708 #undef MC_CMD_0x43_PRIVILEGE_CTG 6709 6710 #define MC_CMD_0x43_PRIVILEGE_CTG SRIOV_CTG_GENERAL 6711 6712 /* MC_CMD_GET_PHY_STATE_IN msgrequest */ 6713 #define MC_CMD_GET_PHY_STATE_IN_LEN 0 6714 6715 /* MC_CMD_GET_PHY_STATE_OUT msgresponse */ 6716 #define MC_CMD_GET_PHY_STATE_OUT_LEN 4 6717 #define MC_CMD_GET_PHY_STATE_OUT_STATE_OFST 0 6718 /* enum: Ok. */ 6719 #define MC_CMD_PHY_STATE_OK 0x1 6720 /* enum: Faulty. */ 6721 #define MC_CMD_PHY_STATE_ZOMBIE 0x2 6722 6723 6724 /***********************************/ 6725 /* MC_CMD_SETUP_8021QBB 6726 * 802.1Qbb control. 8 Tx queues that map to priorities 0 - 7. Use all 1s to 6727 * disable 802.Qbb for a given priority. 6728 */ 6729 #define MC_CMD_SETUP_8021QBB 0x44 6730 6731 /* MC_CMD_SETUP_8021QBB_IN msgrequest */ 6732 #define MC_CMD_SETUP_8021QBB_IN_LEN 32 6733 #define MC_CMD_SETUP_8021QBB_IN_TXQS_OFST 0 6734 #define MC_CMD_SETUP_8021QBB_IN_TXQS_LEN 32 6735 6736 /* MC_CMD_SETUP_8021QBB_OUT msgresponse */ 6737 #define MC_CMD_SETUP_8021QBB_OUT_LEN 0 6738 6739 6740 /***********************************/ 6741 /* MC_CMD_WOL_FILTER_GET 6742 * Retrieve ID of any WoL filters. Locks required: None. Returns: 0, ENOSYS 6743 */ 6744 #define MC_CMD_WOL_FILTER_GET 0x45 6745 #undef MC_CMD_0x45_PRIVILEGE_CTG 6746 6747 #define MC_CMD_0x45_PRIVILEGE_CTG SRIOV_CTG_LINK 6748 6749 /* MC_CMD_WOL_FILTER_GET_IN msgrequest */ 6750 #define MC_CMD_WOL_FILTER_GET_IN_LEN 0 6751 6752 /* MC_CMD_WOL_FILTER_GET_OUT msgresponse */ 6753 #define MC_CMD_WOL_FILTER_GET_OUT_LEN 4 6754 #define MC_CMD_WOL_FILTER_GET_OUT_FILTER_ID_OFST 0 6755 6756 6757 /***********************************/ 6758 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD 6759 * Add a protocol offload to NIC for lights-out state. Locks required: None. 6760 * Returns: 0, ENOSYS 6761 */ 6762 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD 0x46 6763 #undef MC_CMD_0x46_PRIVILEGE_CTG 6764 6765 #define MC_CMD_0x46_PRIVILEGE_CTG SRIOV_CTG_LINK 6766 6767 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN msgrequest */ 6768 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMIN 8 6769 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMAX 252 6770 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LEN(num) (4+4*(num)) 6771 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 6772 #define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_ARP 0x1 /* enum */ 6773 #define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_NS 0x2 /* enum */ 6774 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_OFST 4 6775 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_LEN 4 6776 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MINNUM 1 6777 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MAXNUM 62 6778 6779 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP msgrequest */ 6780 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_LEN 14 6781 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */ 6782 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_OFST 4 6783 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_LEN 6 6784 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_IP_OFST 10 6785 6786 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS msgrequest */ 6787 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_LEN 42 6788 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */ 6789 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_OFST 4 6790 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_LEN 6 6791 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_OFST 10 6792 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_LEN 16 6793 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_OFST 26 6794 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_LEN 16 6795 6796 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT msgresponse */ 6797 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_LEN 4 6798 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_FILTER_ID_OFST 0 6799 6800 6801 /***********************************/ 6802 /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD 6803 * Remove a protocol offload from NIC for lights-out state. Locks required: 6804 * None. Returns: 0, ENOSYS 6805 */ 6806 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD 0x47 6807 #undef MC_CMD_0x47_PRIVILEGE_CTG 6808 6809 #define MC_CMD_0x47_PRIVILEGE_CTG SRIOV_CTG_LINK 6810 6811 /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN msgrequest */ 6812 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_LEN 8 6813 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 6814 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_FILTER_ID_OFST 4 6815 6816 /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT msgresponse */ 6817 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT_LEN 0 6818 6819 6820 /***********************************/ 6821 /* MC_CMD_MAC_RESET_RESTORE 6822 * Restore MAC after block reset. Locks required: None. Returns: 0. 6823 */ 6824 #define MC_CMD_MAC_RESET_RESTORE 0x48 6825 6826 /* MC_CMD_MAC_RESET_RESTORE_IN msgrequest */ 6827 #define MC_CMD_MAC_RESET_RESTORE_IN_LEN 0 6828 6829 /* MC_CMD_MAC_RESET_RESTORE_OUT msgresponse */ 6830 #define MC_CMD_MAC_RESET_RESTORE_OUT_LEN 0 6831 6832 6833 /***********************************/ 6834 /* MC_CMD_TESTASSERT 6835 * Deliberately trigger an assert-detonation in the firmware for testing 6836 * purposes (i.e. to allow tests that the driver copes gracefully). Locks 6837 * required: None Returns: 0 6838 */ 6839 #define MC_CMD_TESTASSERT 0x49 6840 #undef MC_CMD_0x49_PRIVILEGE_CTG 6841 6842 #define MC_CMD_0x49_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6843 6844 /* MC_CMD_TESTASSERT_IN msgrequest */ 6845 #define MC_CMD_TESTASSERT_IN_LEN 0 6846 6847 /* MC_CMD_TESTASSERT_OUT msgresponse */ 6848 #define MC_CMD_TESTASSERT_OUT_LEN 0 6849 6850 6851 /***********************************/ 6852 /* MC_CMD_WORKAROUND 6853 * Enable/Disable a given workaround. The mcfw will return EINVAL if it doesn't 6854 * understand the given workaround number - which should not be treated as a 6855 * hard error by client code. This op does not imply any semantics about each 6856 * workaround, that's between the driver and the mcfw on a per-workaround 6857 * basis. Locks required: None. Returns: 0, EINVAL . 6858 */ 6859 #define MC_CMD_WORKAROUND 0x4a 6860 #undef MC_CMD_0x4a_PRIVILEGE_CTG 6861 6862 #define MC_CMD_0x4a_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6863 6864 /* MC_CMD_WORKAROUND_IN msgrequest */ 6865 #define MC_CMD_WORKAROUND_IN_LEN 8 6866 /* The enums here must correspond with those in MC_CMD_GET_WORKAROUND. */ 6867 #define MC_CMD_WORKAROUND_IN_TYPE_OFST 0 6868 /* enum: Bug 17230 work around. */ 6869 #define MC_CMD_WORKAROUND_BUG17230 0x1 6870 /* enum: Bug 35388 work around (unsafe EVQ writes). */ 6871 #define MC_CMD_WORKAROUND_BUG35388 0x2 6872 /* enum: Bug35017 workaround (A64 tables must be identity map) */ 6873 #define MC_CMD_WORKAROUND_BUG35017 0x3 6874 /* enum: Bug 41750 present (MC_CMD_TRIGGER_INTERRUPT won't work) */ 6875 #define MC_CMD_WORKAROUND_BUG41750 0x4 6876 /* enum: Bug 42008 present (Interrupts can overtake associated events). Caution 6877 * - before adding code that queries this workaround, remember that there's 6878 * released Monza firmware that doesn't understand MC_CMD_WORKAROUND_BUG42008, 6879 * and will hence (incorrectly) report that the bug doesn't exist. 6880 */ 6881 #define MC_CMD_WORKAROUND_BUG42008 0x5 6882 /* enum: Bug 26807 features present in firmware (multicast filter chaining) 6883 * This feature cannot be turned on/off while there are any filters already 6884 * present. The behaviour in such case depends on the acting client's privilege 6885 * level. If the client has the admin privilege, then all functions that have 6886 * filters installed will be FLRed and the FLR_DONE flag will be set. Otherwise 6887 * the command will fail with MC_CMD_ERR_FILTERS_PRESENT. 6888 */ 6889 #define MC_CMD_WORKAROUND_BUG26807 0x6 6890 /* 0 = disable the workaround indicated by TYPE; any non-zero value = enable 6891 * the workaround 6892 */ 6893 #define MC_CMD_WORKAROUND_IN_ENABLED_OFST 4 6894 6895 /* MC_CMD_WORKAROUND_OUT msgresponse */ 6896 #define MC_CMD_WORKAROUND_OUT_LEN 0 6897 6898 /* MC_CMD_WORKAROUND_EXT_OUT msgresponse: This response format will be used 6899 * when (TYPE == MC_CMD_WORKAROUND_BUG26807) 6900 */ 6901 #define MC_CMD_WORKAROUND_EXT_OUT_LEN 4 6902 #define MC_CMD_WORKAROUND_EXT_OUT_FLAGS_OFST 0 6903 #define MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN 0 6904 #define MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_WIDTH 1 6905 6906 6907 /***********************************/ 6908 /* MC_CMD_GET_PHY_MEDIA_INFO 6909 * Read media-specific data from PHY (e.g. SFP/SFP+ module ID information for 6910 * SFP+ PHYs). The 'media type' can be found via GET_PHY_CFG 6911 * (GET_PHY_CFG_OUT_MEDIA_TYPE); the valid 'page number' input values, and the 6912 * output data, are interpreted on a per-type basis. For SFP+: PAGE=0 or 1 6913 * returns a 128-byte block read from module I2C address 0xA0 offset 0 or 0x80. 6914 * Anything else: currently undefined. Locks required: None. Return code: 0. 6915 */ 6916 #define MC_CMD_GET_PHY_MEDIA_INFO 0x4b 6917 #undef MC_CMD_0x4b_PRIVILEGE_CTG 6918 6919 #define MC_CMD_0x4b_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6920 6921 /* MC_CMD_GET_PHY_MEDIA_INFO_IN msgrequest */ 6922 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_LEN 4 6923 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_PAGE_OFST 0 6924 6925 /* MC_CMD_GET_PHY_MEDIA_INFO_OUT msgresponse */ 6926 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMIN 5 6927 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMAX 252 6928 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LEN(num) (4+1*(num)) 6929 /* in bytes */ 6930 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATALEN_OFST 0 6931 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_OFST 4 6932 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_LEN 1 6933 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MINNUM 1 6934 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MAXNUM 248 6935 6936 6937 /***********************************/ 6938 /* MC_CMD_NVRAM_TEST 6939 * Test a particular NVRAM partition for valid contents (where "valid" depends 6940 * on the type of partition). 6941 */ 6942 #define MC_CMD_NVRAM_TEST 0x4c 6943 #undef MC_CMD_0x4c_PRIVILEGE_CTG 6944 6945 #define MC_CMD_0x4c_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6946 6947 /* MC_CMD_NVRAM_TEST_IN msgrequest */ 6948 #define MC_CMD_NVRAM_TEST_IN_LEN 4 6949 #define MC_CMD_NVRAM_TEST_IN_TYPE_OFST 0 6950 /* Enum values, see field(s): */ 6951 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 6952 6953 /* MC_CMD_NVRAM_TEST_OUT msgresponse */ 6954 #define MC_CMD_NVRAM_TEST_OUT_LEN 4 6955 #define MC_CMD_NVRAM_TEST_OUT_RESULT_OFST 0 6956 /* enum: Passed. */ 6957 #define MC_CMD_NVRAM_TEST_PASS 0x0 6958 /* enum: Failed. */ 6959 #define MC_CMD_NVRAM_TEST_FAIL 0x1 6960 /* enum: Not supported. */ 6961 #define MC_CMD_NVRAM_TEST_NOTSUPP 0x2 6962 6963 6964 /***********************************/ 6965 /* MC_CMD_MRSFP_TWEAK 6966 * Read status and/or set parameters for the 'mrsfp' driver in mr_rusty builds. 6967 * I2C I/O expander bits are always read; if equaliser parameters are supplied, 6968 * they are configured first. Locks required: None. Return code: 0, EINVAL. 6969 */ 6970 #define MC_CMD_MRSFP_TWEAK 0x4d 6971 6972 /* MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG msgrequest */ 6973 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_LEN 16 6974 /* 0-6 low->high de-emph. */ 6975 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_LEVEL_OFST 0 6976 /* 0-8 low->high ref.V */ 6977 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_DT_CFG_OFST 4 6978 /* 0-8 0-8 low->high boost */ 6979 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_BOOST_OFST 8 6980 /* 0-8 low->high ref.V */ 6981 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_DT_CFG_OFST 12 6982 6983 /* MC_CMD_MRSFP_TWEAK_IN_READ_ONLY msgrequest */ 6984 #define MC_CMD_MRSFP_TWEAK_IN_READ_ONLY_LEN 0 6985 6986 /* MC_CMD_MRSFP_TWEAK_OUT msgresponse */ 6987 #define MC_CMD_MRSFP_TWEAK_OUT_LEN 12 6988 /* input bits */ 6989 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_INPUTS_OFST 0 6990 /* output bits */ 6991 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_OUTPUTS_OFST 4 6992 /* direction */ 6993 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OFST 8 6994 /* enum: Out. */ 6995 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OUT 0x0 6996 /* enum: In. */ 6997 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_IN 0x1 6998 6999 7000 /***********************************/ 7001 /* MC_CMD_SENSOR_SET_LIMS 7002 * Adjusts the sensor limits. This is a warranty-voiding operation. Returns: 7003 * ENOENT if the sensor specified does not exist, EINVAL if the limits are out 7004 * of range. 7005 */ 7006 #define MC_CMD_SENSOR_SET_LIMS 0x4e 7007 #undef MC_CMD_0x4e_PRIVILEGE_CTG 7008 7009 #define MC_CMD_0x4e_PRIVILEGE_CTG SRIOV_CTG_ADMIN 7010 7011 /* MC_CMD_SENSOR_SET_LIMS_IN msgrequest */ 7012 #define MC_CMD_SENSOR_SET_LIMS_IN_LEN 20 7013 #define MC_CMD_SENSOR_SET_LIMS_IN_SENSOR_OFST 0 7014 /* Enum values, see field(s): */ 7015 /* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */ 7016 /* interpretation is is sensor-specific. */ 7017 #define MC_CMD_SENSOR_SET_LIMS_IN_LOW0_OFST 4 7018 /* interpretation is is sensor-specific. */ 7019 #define MC_CMD_SENSOR_SET_LIMS_IN_HI0_OFST 8 7020 /* interpretation is is sensor-specific. */ 7021 #define MC_CMD_SENSOR_SET_LIMS_IN_LOW1_OFST 12 7022 /* interpretation is is sensor-specific. */ 7023 #define MC_CMD_SENSOR_SET_LIMS_IN_HI1_OFST 16 7024 7025 /* MC_CMD_SENSOR_SET_LIMS_OUT msgresponse */ 7026 #define MC_CMD_SENSOR_SET_LIMS_OUT_LEN 0 7027 7028 7029 /***********************************/ 7030 /* MC_CMD_GET_RESOURCE_LIMITS 7031 */ 7032 #define MC_CMD_GET_RESOURCE_LIMITS 0x4f 7033 7034 /* MC_CMD_GET_RESOURCE_LIMITS_IN msgrequest */ 7035 #define MC_CMD_GET_RESOURCE_LIMITS_IN_LEN 0 7036 7037 /* MC_CMD_GET_RESOURCE_LIMITS_OUT msgresponse */ 7038 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_LEN 16 7039 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_BUFTBL_OFST 0 7040 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_EVQ_OFST 4 7041 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_RXQ_OFST 8 7042 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_TXQ_OFST 12 7043 7044 7045 /***********************************/ 7046 /* MC_CMD_NVRAM_PARTITIONS 7047 * Reads the list of available virtual NVRAM partition types. Locks required: 7048 * none. Returns: 0, EINVAL (bad type). 7049 */ 7050 #define MC_CMD_NVRAM_PARTITIONS 0x51 7051 #undef MC_CMD_0x51_PRIVILEGE_CTG 7052 7053 #define MC_CMD_0x51_PRIVILEGE_CTG SRIOV_CTG_ADMIN 7054 7055 /* MC_CMD_NVRAM_PARTITIONS_IN msgrequest */ 7056 #define MC_CMD_NVRAM_PARTITIONS_IN_LEN 0 7057 7058 /* MC_CMD_NVRAM_PARTITIONS_OUT msgresponse */ 7059 #define MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN 4 7060 #define MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX 252 7061 #define MC_CMD_NVRAM_PARTITIONS_OUT_LEN(num) (4+4*(num)) 7062 /* total number of partitions */ 7063 #define MC_CMD_NVRAM_PARTITIONS_OUT_NUM_PARTITIONS_OFST 0 7064 /* type ID code for each of NUM_PARTITIONS partitions */ 7065 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_OFST 4 7066 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_LEN 4 7067 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MINNUM 0 7068 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MAXNUM 62 7069 7070 7071 /***********************************/ 7072 /* MC_CMD_NVRAM_METADATA 7073 * Reads soft metadata for a virtual NVRAM partition type. Locks required: 7074 * none. Returns: 0, EINVAL (bad type). 7075 */ 7076 #define MC_CMD_NVRAM_METADATA 0x52 7077 #undef MC_CMD_0x52_PRIVILEGE_CTG 7078 7079 #define MC_CMD_0x52_PRIVILEGE_CTG SRIOV_CTG_ADMIN 7080 7081 /* MC_CMD_NVRAM_METADATA_IN msgrequest */ 7082 #define MC_CMD_NVRAM_METADATA_IN_LEN 4 7083 /* Partition type ID code */ 7084 #define MC_CMD_NVRAM_METADATA_IN_TYPE_OFST 0 7085 7086 /* MC_CMD_NVRAM_METADATA_OUT msgresponse */ 7087 #define MC_CMD_NVRAM_METADATA_OUT_LENMIN 20 7088 #define MC_CMD_NVRAM_METADATA_OUT_LENMAX 252 7089 #define MC_CMD_NVRAM_METADATA_OUT_LEN(num) (20+1*(num)) 7090 /* Partition type ID code */ 7091 #define MC_CMD_NVRAM_METADATA_OUT_TYPE_OFST 0 7092 #define MC_CMD_NVRAM_METADATA_OUT_FLAGS_OFST 4 7093 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN 0 7094 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_WIDTH 1 7095 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_LBN 1 7096 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_WIDTH 1 7097 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_LBN 2 7098 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_WIDTH 1 7099 /* Subtype ID code for content of this partition */ 7100 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_OFST 8 7101 /* 1st component of W.X.Y.Z version number for content of this partition */ 7102 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_W_OFST 12 7103 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_W_LEN 2 7104 /* 2nd component of W.X.Y.Z version number for content of this partition */ 7105 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_X_OFST 14 7106 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_X_LEN 2 7107 /* 3rd component of W.X.Y.Z version number for content of this partition */ 7108 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Y_OFST 16 7109 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Y_LEN 2 7110 /* 4th component of W.X.Y.Z version number for content of this partition */ 7111 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Z_OFST 18 7112 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Z_LEN 2 7113 /* Zero-terminated string describing the content of this partition */ 7114 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_OFST 20 7115 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_LEN 1 7116 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MINNUM 0 7117 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MAXNUM 232 7118 7119 7120 /***********************************/ 7121 /* MC_CMD_GET_MAC_ADDRESSES 7122 * Returns the base MAC, count and stride for the requesting function 7123 */ 7124 #define MC_CMD_GET_MAC_ADDRESSES 0x55 7125 #undef MC_CMD_0x55_PRIVILEGE_CTG 7126 7127 #define MC_CMD_0x55_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7128 7129 /* MC_CMD_GET_MAC_ADDRESSES_IN msgrequest */ 7130 #define MC_CMD_GET_MAC_ADDRESSES_IN_LEN 0 7131 7132 /* MC_CMD_GET_MAC_ADDRESSES_OUT msgresponse */ 7133 #define MC_CMD_GET_MAC_ADDRESSES_OUT_LEN 16 7134 /* Base MAC address */ 7135 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE_OFST 0 7136 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE_LEN 6 7137 /* Padding */ 7138 #define MC_CMD_GET_MAC_ADDRESSES_OUT_RESERVED_OFST 6 7139 #define MC_CMD_GET_MAC_ADDRESSES_OUT_RESERVED_LEN 2 7140 /* Number of allocated MAC addresses */ 7141 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_COUNT_OFST 8 7142 /* Spacing of allocated MAC addresses */ 7143 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_STRIDE_OFST 12 7144 7145 7146 /***********************************/ 7147 /* MC_CMD_CLP 7148 * Perform a CLP related operation 7149 */ 7150 #define MC_CMD_CLP 0x56 7151 #undef MC_CMD_0x56_PRIVILEGE_CTG 7152 7153 #define MC_CMD_0x56_PRIVILEGE_CTG SRIOV_CTG_ADMIN 7154 7155 /* MC_CMD_CLP_IN msgrequest */ 7156 #define MC_CMD_CLP_IN_LEN 4 7157 /* Sub operation */ 7158 #define MC_CMD_CLP_IN_OP_OFST 0 7159 /* enum: Return to factory default settings */ 7160 #define MC_CMD_CLP_OP_DEFAULT 0x1 7161 /* enum: Set MAC address */ 7162 #define MC_CMD_CLP_OP_SET_MAC 0x2 7163 /* enum: Get MAC address */ 7164 #define MC_CMD_CLP_OP_GET_MAC 0x3 7165 /* enum: Set UEFI/GPXE boot mode */ 7166 #define MC_CMD_CLP_OP_SET_BOOT 0x4 7167 /* enum: Get UEFI/GPXE boot mode */ 7168 #define MC_CMD_CLP_OP_GET_BOOT 0x5 7169 7170 /* MC_CMD_CLP_OUT msgresponse */ 7171 #define MC_CMD_CLP_OUT_LEN 0 7172 7173 /* MC_CMD_CLP_IN_DEFAULT msgrequest */ 7174 #define MC_CMD_CLP_IN_DEFAULT_LEN 4 7175 /* MC_CMD_CLP_IN_OP_OFST 0 */ 7176 7177 /* MC_CMD_CLP_OUT_DEFAULT msgresponse */ 7178 #define MC_CMD_CLP_OUT_DEFAULT_LEN 0 7179 7180 /* MC_CMD_CLP_IN_SET_MAC msgrequest */ 7181 #define MC_CMD_CLP_IN_SET_MAC_LEN 12 7182 /* MC_CMD_CLP_IN_OP_OFST 0 */ 7183 /* MAC address assigned to port */ 7184 #define MC_CMD_CLP_IN_SET_MAC_ADDR_OFST 4 7185 #define MC_CMD_CLP_IN_SET_MAC_ADDR_LEN 6 7186 /* Padding */ 7187 #define MC_CMD_CLP_IN_SET_MAC_RESERVED_OFST 10 7188 #define MC_CMD_CLP_IN_SET_MAC_RESERVED_LEN 2 7189 7190 /* MC_CMD_CLP_OUT_SET_MAC msgresponse */ 7191 #define MC_CMD_CLP_OUT_SET_MAC_LEN 0 7192 7193 /* MC_CMD_CLP_IN_GET_MAC msgrequest */ 7194 #define MC_CMD_CLP_IN_GET_MAC_LEN 4 7195 /* MC_CMD_CLP_IN_OP_OFST 0 */ 7196 7197 /* MC_CMD_CLP_OUT_GET_MAC msgresponse */ 7198 #define MC_CMD_CLP_OUT_GET_MAC_LEN 8 7199 /* MAC address assigned to port */ 7200 #define MC_CMD_CLP_OUT_GET_MAC_ADDR_OFST 0 7201 #define MC_CMD_CLP_OUT_GET_MAC_ADDR_LEN 6 7202 /* Padding */ 7203 #define MC_CMD_CLP_OUT_GET_MAC_RESERVED_OFST 6 7204 #define MC_CMD_CLP_OUT_GET_MAC_RESERVED_LEN 2 7205 7206 /* MC_CMD_CLP_IN_SET_BOOT msgrequest */ 7207 #define MC_CMD_CLP_IN_SET_BOOT_LEN 5 7208 /* MC_CMD_CLP_IN_OP_OFST 0 */ 7209 /* Boot flag */ 7210 #define MC_CMD_CLP_IN_SET_BOOT_FLAG_OFST 4 7211 #define MC_CMD_CLP_IN_SET_BOOT_FLAG_LEN 1 7212 7213 /* MC_CMD_CLP_OUT_SET_BOOT msgresponse */ 7214 #define MC_CMD_CLP_OUT_SET_BOOT_LEN 0 7215 7216 /* MC_CMD_CLP_IN_GET_BOOT msgrequest */ 7217 #define MC_CMD_CLP_IN_GET_BOOT_LEN 4 7218 /* MC_CMD_CLP_IN_OP_OFST 0 */ 7219 7220 /* MC_CMD_CLP_OUT_GET_BOOT msgresponse */ 7221 #define MC_CMD_CLP_OUT_GET_BOOT_LEN 4 7222 /* Boot flag */ 7223 #define MC_CMD_CLP_OUT_GET_BOOT_FLAG_OFST 0 7224 #define MC_CMD_CLP_OUT_GET_BOOT_FLAG_LEN 1 7225 /* Padding */ 7226 #define MC_CMD_CLP_OUT_GET_BOOT_RESERVED_OFST 1 7227 #define MC_CMD_CLP_OUT_GET_BOOT_RESERVED_LEN 3 7228 7229 7230 /***********************************/ 7231 /* MC_CMD_MUM 7232 * Perform a MUM operation 7233 */ 7234 #define MC_CMD_MUM 0x57 7235 #undef MC_CMD_0x57_PRIVILEGE_CTG 7236 7237 #define MC_CMD_0x57_PRIVILEGE_CTG SRIOV_CTG_ADMIN 7238 7239 /* MC_CMD_MUM_IN msgrequest */ 7240 #define MC_CMD_MUM_IN_LEN 4 7241 #define MC_CMD_MUM_IN_OP_HDR_OFST 0 7242 #define MC_CMD_MUM_IN_OP_LBN 0 7243 #define MC_CMD_MUM_IN_OP_WIDTH 8 7244 /* enum: NULL MCDI command to MUM */ 7245 #define MC_CMD_MUM_OP_NULL 0x1 7246 /* enum: Get MUM version */ 7247 #define MC_CMD_MUM_OP_GET_VERSION 0x2 7248 /* enum: Issue raw I2C command to MUM */ 7249 #define MC_CMD_MUM_OP_RAW_CMD 0x3 7250 /* enum: Read from registers on devices connected to MUM. */ 7251 #define MC_CMD_MUM_OP_READ 0x4 7252 /* enum: Write to registers on devices connected to MUM. */ 7253 #define MC_CMD_MUM_OP_WRITE 0x5 7254 /* enum: Control UART logging. */ 7255 #define MC_CMD_MUM_OP_LOG 0x6 7256 /* enum: Operations on MUM GPIO lines */ 7257 #define MC_CMD_MUM_OP_GPIO 0x7 7258 /* enum: Get sensor readings from MUM */ 7259 #define MC_CMD_MUM_OP_READ_SENSORS 0x8 7260 /* enum: Initiate clock programming on the MUM */ 7261 #define MC_CMD_MUM_OP_PROGRAM_CLOCKS 0x9 7262 /* enum: Initiate FPGA load from flash on the MUM */ 7263 #define MC_CMD_MUM_OP_FPGA_LOAD 0xa 7264 /* enum: Request sensor reading from MUM ADC resulting from earlier request via 7265 * MUM ATB 7266 */ 7267 #define MC_CMD_MUM_OP_READ_ATB_SENSOR 0xb 7268 /* enum: Send commands relating to the QSFP ports via the MUM for PHY 7269 * operations 7270 */ 7271 #define MC_CMD_MUM_OP_QSFP 0xc 7272 /* enum: Request discrete and SODIMM DDR info (type, size, speed grade, voltage 7273 * level) from MUM 7274 */ 7275 #define MC_CMD_MUM_OP_READ_DDR_INFO 0xd 7276 7277 /* MC_CMD_MUM_IN_NULL msgrequest */ 7278 #define MC_CMD_MUM_IN_NULL_LEN 4 7279 /* MUM cmd header */ 7280 #define MC_CMD_MUM_IN_CMD_OFST 0 7281 7282 /* MC_CMD_MUM_IN_GET_VERSION msgrequest */ 7283 #define MC_CMD_MUM_IN_GET_VERSION_LEN 4 7284 /* MUM cmd header */ 7285 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7286 7287 /* MC_CMD_MUM_IN_READ msgrequest */ 7288 #define MC_CMD_MUM_IN_READ_LEN 16 7289 /* MUM cmd header */ 7290 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7291 /* ID of (device connected to MUM) to read from registers of */ 7292 #define MC_CMD_MUM_IN_READ_DEVICE_OFST 4 7293 /* enum: Hittite HMC1035 clock generator on Sorrento board */ 7294 #define MC_CMD_MUM_DEV_HITTITE 0x1 7295 /* enum: Hittite HMC1035 clock generator for NIC-side on Sorrento board */ 7296 #define MC_CMD_MUM_DEV_HITTITE_NIC 0x2 7297 /* 32-bit address to read from */ 7298 #define MC_CMD_MUM_IN_READ_ADDR_OFST 8 7299 /* Number of words to read. */ 7300 #define MC_CMD_MUM_IN_READ_NUMWORDS_OFST 12 7301 7302 /* MC_CMD_MUM_IN_WRITE msgrequest */ 7303 #define MC_CMD_MUM_IN_WRITE_LENMIN 16 7304 #define MC_CMD_MUM_IN_WRITE_LENMAX 252 7305 #define MC_CMD_MUM_IN_WRITE_LEN(num) (12+4*(num)) 7306 /* MUM cmd header */ 7307 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7308 /* ID of (device connected to MUM) to write to registers of */ 7309 #define MC_CMD_MUM_IN_WRITE_DEVICE_OFST 4 7310 /* enum: Hittite HMC1035 clock generator on Sorrento board */ 7311 /* MC_CMD_MUM_DEV_HITTITE 0x1 */ 7312 /* 32-bit address to write to */ 7313 #define MC_CMD_MUM_IN_WRITE_ADDR_OFST 8 7314 /* Words to write */ 7315 #define MC_CMD_MUM_IN_WRITE_BUFFER_OFST 12 7316 #define MC_CMD_MUM_IN_WRITE_BUFFER_LEN 4 7317 #define MC_CMD_MUM_IN_WRITE_BUFFER_MINNUM 1 7318 #define MC_CMD_MUM_IN_WRITE_BUFFER_MAXNUM 60 7319 7320 /* MC_CMD_MUM_IN_RAW_CMD msgrequest */ 7321 #define MC_CMD_MUM_IN_RAW_CMD_LENMIN 17 7322 #define MC_CMD_MUM_IN_RAW_CMD_LENMAX 252 7323 #define MC_CMD_MUM_IN_RAW_CMD_LEN(num) (16+1*(num)) 7324 /* MUM cmd header */ 7325 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7326 /* MUM I2C cmd code */ 7327 #define MC_CMD_MUM_IN_RAW_CMD_CMD_CODE_OFST 4 7328 /* Number of bytes to write */ 7329 #define MC_CMD_MUM_IN_RAW_CMD_NUM_WRITE_OFST 8 7330 /* Number of bytes to read */ 7331 #define MC_CMD_MUM_IN_RAW_CMD_NUM_READ_OFST 12 7332 /* Bytes to write */ 7333 #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_OFST 16 7334 #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_LEN 1 7335 #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_MINNUM 1 7336 #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_MAXNUM 236 7337 7338 /* MC_CMD_MUM_IN_LOG msgrequest */ 7339 #define MC_CMD_MUM_IN_LOG_LEN 8 7340 /* MUM cmd header */ 7341 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7342 #define MC_CMD_MUM_IN_LOG_OP_OFST 4 7343 #define MC_CMD_MUM_IN_LOG_OP_UART 0x1 /* enum */ 7344 7345 /* MC_CMD_MUM_IN_LOG_OP_UART msgrequest */ 7346 #define MC_CMD_MUM_IN_LOG_OP_UART_LEN 12 7347 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7348 /* MC_CMD_MUM_IN_LOG_OP_OFST 4 */ 7349 /* Enable/disable debug output to UART */ 7350 #define MC_CMD_MUM_IN_LOG_OP_UART_ENABLE_OFST 8 7351 7352 /* MC_CMD_MUM_IN_GPIO msgrequest */ 7353 #define MC_CMD_MUM_IN_GPIO_LEN 8 7354 /* MUM cmd header */ 7355 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7356 #define MC_CMD_MUM_IN_GPIO_HDR_OFST 4 7357 #define MC_CMD_MUM_IN_GPIO_OPCODE_LBN 0 7358 #define MC_CMD_MUM_IN_GPIO_OPCODE_WIDTH 8 7359 #define MC_CMD_MUM_IN_GPIO_IN_READ 0x0 /* enum */ 7360 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE 0x1 /* enum */ 7361 #define MC_CMD_MUM_IN_GPIO_OUT_READ 0x2 /* enum */ 7362 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE 0x3 /* enum */ 7363 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ 0x4 /* enum */ 7364 #define MC_CMD_MUM_IN_GPIO_OP 0x5 /* enum */ 7365 7366 /* MC_CMD_MUM_IN_GPIO_IN_READ msgrequest */ 7367 #define MC_CMD_MUM_IN_GPIO_IN_READ_LEN 8 7368 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7369 #define MC_CMD_MUM_IN_GPIO_IN_READ_HDR_OFST 4 7370 7371 /* MC_CMD_MUM_IN_GPIO_OUT_WRITE msgrequest */ 7372 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_LEN 16 7373 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7374 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_HDR_OFST 4 7375 /* The first 32-bit word to be written to the GPIO OUT register. */ 7376 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK1_OFST 8 7377 /* The second 32-bit word to be written to the GPIO OUT register. */ 7378 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK2_OFST 12 7379 7380 /* MC_CMD_MUM_IN_GPIO_OUT_READ msgrequest */ 7381 #define MC_CMD_MUM_IN_GPIO_OUT_READ_LEN 8 7382 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7383 #define MC_CMD_MUM_IN_GPIO_OUT_READ_HDR_OFST 4 7384 7385 /* MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE msgrequest */ 7386 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_LEN 16 7387 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7388 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_HDR_OFST 4 7389 /* The first 32-bit word to be written to the GPIO OUT ENABLE register. */ 7390 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK1_OFST 8 7391 /* The second 32-bit word to be written to the GPIO OUT ENABLE register. */ 7392 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK2_OFST 12 7393 7394 /* MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ msgrequest */ 7395 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_LEN 8 7396 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7397 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_HDR_OFST 4 7398 7399 /* MC_CMD_MUM_IN_GPIO_OP msgrequest */ 7400 #define MC_CMD_MUM_IN_GPIO_OP_LEN 8 7401 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7402 #define MC_CMD_MUM_IN_GPIO_OP_HDR_OFST 4 7403 #define MC_CMD_MUM_IN_GPIO_OP_BITWISE_OP_LBN 8 7404 #define MC_CMD_MUM_IN_GPIO_OP_BITWISE_OP_WIDTH 8 7405 #define MC_CMD_MUM_IN_GPIO_OP_OUT_READ 0x0 /* enum */ 7406 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE 0x1 /* enum */ 7407 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG 0x2 /* enum */ 7408 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE 0x3 /* enum */ 7409 #define MC_CMD_MUM_IN_GPIO_OP_GPIO_NUMBER_LBN 16 7410 #define MC_CMD_MUM_IN_GPIO_OP_GPIO_NUMBER_WIDTH 8 7411 7412 /* MC_CMD_MUM_IN_GPIO_OP_OUT_READ msgrequest */ 7413 #define MC_CMD_MUM_IN_GPIO_OP_OUT_READ_LEN 8 7414 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7415 #define MC_CMD_MUM_IN_GPIO_OP_OUT_READ_HDR_OFST 4 7416 7417 /* MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE msgrequest */ 7418 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_LEN 8 7419 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7420 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_HDR_OFST 4 7421 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_WRITEBIT_LBN 24 7422 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_WRITEBIT_WIDTH 8 7423 7424 /* MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG msgrequest */ 7425 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_LEN 8 7426 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7427 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_HDR_OFST 4 7428 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_CFG_LBN 24 7429 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_CFG_WIDTH 8 7430 7431 /* MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE msgrequest */ 7432 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_LEN 8 7433 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7434 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_HDR_OFST 4 7435 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_ENABLEBIT_LBN 24 7436 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_ENABLEBIT_WIDTH 8 7437 7438 /* MC_CMD_MUM_IN_READ_SENSORS msgrequest */ 7439 #define MC_CMD_MUM_IN_READ_SENSORS_LEN 8 7440 /* MUM cmd header */ 7441 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7442 #define MC_CMD_MUM_IN_READ_SENSORS_PARAMS_OFST 4 7443 #define MC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_LBN 0 7444 #define MC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_WIDTH 8 7445 #define MC_CMD_MUM_IN_READ_SENSORS_NUM_SENSORS_LBN 8 7446 #define MC_CMD_MUM_IN_READ_SENSORS_NUM_SENSORS_WIDTH 8 7447 7448 /* MC_CMD_MUM_IN_PROGRAM_CLOCKS msgrequest */ 7449 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_LEN 12 7450 /* MUM cmd header */ 7451 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7452 /* Bit-mask of clocks to be programmed */ 7453 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_MASK_OFST 4 7454 #define MC_CMD_MUM_CLOCK_ID_FPGA 0x0 /* enum */ 7455 #define MC_CMD_MUM_CLOCK_ID_DDR 0x1 /* enum */ 7456 #define MC_CMD_MUM_CLOCK_ID_NIC 0x2 /* enum */ 7457 /* Control flags for clock programming */ 7458 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_FLAGS_OFST 8 7459 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_LBN 0 7460 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_WIDTH 1 7461 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_NIC_FROM_FPGA_LBN 1 7462 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_NIC_FROM_FPGA_WIDTH 1 7463 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_REF_FROM_XO_LBN 2 7464 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_REF_FROM_XO_WIDTH 1 7465 7466 /* MC_CMD_MUM_IN_FPGA_LOAD msgrequest */ 7467 #define MC_CMD_MUM_IN_FPGA_LOAD_LEN 8 7468 /* MUM cmd header */ 7469 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7470 /* Enable/Disable FPGA config from flash */ 7471 #define MC_CMD_MUM_IN_FPGA_LOAD_ENABLE_OFST 4 7472 7473 /* MC_CMD_MUM_IN_READ_ATB_SENSOR msgrequest */ 7474 #define MC_CMD_MUM_IN_READ_ATB_SENSOR_LEN 4 7475 /* MUM cmd header */ 7476 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7477 7478 /* MC_CMD_MUM_IN_QSFP msgrequest */ 7479 #define MC_CMD_MUM_IN_QSFP_LEN 12 7480 /* MUM cmd header */ 7481 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7482 #define MC_CMD_MUM_IN_QSFP_HDR_OFST 4 7483 #define MC_CMD_MUM_IN_QSFP_OPCODE_LBN 0 7484 #define MC_CMD_MUM_IN_QSFP_OPCODE_WIDTH 4 7485 #define MC_CMD_MUM_IN_QSFP_INIT 0x0 /* enum */ 7486 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE 0x1 /* enum */ 7487 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP 0x2 /* enum */ 7488 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO 0x3 /* enum */ 7489 #define MC_CMD_MUM_IN_QSFP_FILL_STATS 0x4 /* enum */ 7490 #define MC_CMD_MUM_IN_QSFP_POLL_BIST 0x5 /* enum */ 7491 #define MC_CMD_MUM_IN_QSFP_IDX_OFST 8 7492 7493 /* MC_CMD_MUM_IN_QSFP_INIT msgrequest */ 7494 #define MC_CMD_MUM_IN_QSFP_INIT_LEN 16 7495 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7496 #define MC_CMD_MUM_IN_QSFP_INIT_HDR_OFST 4 7497 #define MC_CMD_MUM_IN_QSFP_INIT_IDX_OFST 8 7498 #define MC_CMD_MUM_IN_QSFP_INIT_CAGE_OFST 12 7499 7500 /* MC_CMD_MUM_IN_QSFP_RECONFIGURE msgrequest */ 7501 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_LEN 24 7502 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7503 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_HDR_OFST 4 7504 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_IDX_OFST 8 7505 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_TX_DISABLE_OFST 12 7506 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LANES_OFST 16 7507 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LINK_SPEED_OFST 20 7508 7509 /* MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP msgrequest */ 7510 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_LEN 12 7511 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7512 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_HDR_OFST 4 7513 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_IDX_OFST 8 7514 7515 /* MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO msgrequest */ 7516 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_LEN 16 7517 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7518 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_HDR_OFST 4 7519 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_IDX_OFST 8 7520 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_PAGE_OFST 12 7521 7522 /* MC_CMD_MUM_IN_QSFP_FILL_STATS msgrequest */ 7523 #define MC_CMD_MUM_IN_QSFP_FILL_STATS_LEN 12 7524 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7525 #define MC_CMD_MUM_IN_QSFP_FILL_STATS_HDR_OFST 4 7526 #define MC_CMD_MUM_IN_QSFP_FILL_STATS_IDX_OFST 8 7527 7528 /* MC_CMD_MUM_IN_QSFP_POLL_BIST msgrequest */ 7529 #define MC_CMD_MUM_IN_QSFP_POLL_BIST_LEN 12 7530 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7531 #define MC_CMD_MUM_IN_QSFP_POLL_BIST_HDR_OFST 4 7532 #define MC_CMD_MUM_IN_QSFP_POLL_BIST_IDX_OFST 8 7533 7534 /* MC_CMD_MUM_IN_READ_DDR_INFO msgrequest */ 7535 #define MC_CMD_MUM_IN_READ_DDR_INFO_LEN 4 7536 /* MUM cmd header */ 7537 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7538 7539 /* MC_CMD_MUM_OUT msgresponse */ 7540 #define MC_CMD_MUM_OUT_LEN 0 7541 7542 /* MC_CMD_MUM_OUT_NULL msgresponse */ 7543 #define MC_CMD_MUM_OUT_NULL_LEN 0 7544 7545 /* MC_CMD_MUM_OUT_GET_VERSION msgresponse */ 7546 #define MC_CMD_MUM_OUT_GET_VERSION_LEN 12 7547 #define MC_CMD_MUM_OUT_GET_VERSION_FIRMWARE_OFST 0 7548 #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_OFST 4 7549 #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LEN 8 7550 #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LO_OFST 4 7551 #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_HI_OFST 8 7552 7553 /* MC_CMD_MUM_OUT_RAW_CMD msgresponse */ 7554 #define MC_CMD_MUM_OUT_RAW_CMD_LENMIN 1 7555 #define MC_CMD_MUM_OUT_RAW_CMD_LENMAX 252 7556 #define MC_CMD_MUM_OUT_RAW_CMD_LEN(num) (0+1*(num)) 7557 /* returned data */ 7558 #define MC_CMD_MUM_OUT_RAW_CMD_DATA_OFST 0 7559 #define MC_CMD_MUM_OUT_RAW_CMD_DATA_LEN 1 7560 #define MC_CMD_MUM_OUT_RAW_CMD_DATA_MINNUM 1 7561 #define MC_CMD_MUM_OUT_RAW_CMD_DATA_MAXNUM 252 7562 7563 /* MC_CMD_MUM_OUT_READ msgresponse */ 7564 #define MC_CMD_MUM_OUT_READ_LENMIN 4 7565 #define MC_CMD_MUM_OUT_READ_LENMAX 252 7566 #define MC_CMD_MUM_OUT_READ_LEN(num) (0+4*(num)) 7567 #define MC_CMD_MUM_OUT_READ_BUFFER_OFST 0 7568 #define MC_CMD_MUM_OUT_READ_BUFFER_LEN 4 7569 #define MC_CMD_MUM_OUT_READ_BUFFER_MINNUM 1 7570 #define MC_CMD_MUM_OUT_READ_BUFFER_MAXNUM 63 7571 7572 /* MC_CMD_MUM_OUT_WRITE msgresponse */ 7573 #define MC_CMD_MUM_OUT_WRITE_LEN 0 7574 7575 /* MC_CMD_MUM_OUT_LOG msgresponse */ 7576 #define MC_CMD_MUM_OUT_LOG_LEN 0 7577 7578 /* MC_CMD_MUM_OUT_LOG_OP_UART msgresponse */ 7579 #define MC_CMD_MUM_OUT_LOG_OP_UART_LEN 0 7580 7581 /* MC_CMD_MUM_OUT_GPIO_IN_READ msgresponse */ 7582 #define MC_CMD_MUM_OUT_GPIO_IN_READ_LEN 8 7583 /* The first 32-bit word read from the GPIO IN register. */ 7584 #define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK1_OFST 0 7585 /* The second 32-bit word read from the GPIO IN register. */ 7586 #define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK2_OFST 4 7587 7588 /* MC_CMD_MUM_OUT_GPIO_OUT_WRITE msgresponse */ 7589 #define MC_CMD_MUM_OUT_GPIO_OUT_WRITE_LEN 0 7590 7591 /* MC_CMD_MUM_OUT_GPIO_OUT_READ msgresponse */ 7592 #define MC_CMD_MUM_OUT_GPIO_OUT_READ_LEN 8 7593 /* The first 32-bit word read from the GPIO OUT register. */ 7594 #define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK1_OFST 0 7595 /* The second 32-bit word read from the GPIO OUT register. */ 7596 #define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK2_OFST 4 7597 7598 /* MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_WRITE msgresponse */ 7599 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_WRITE_LEN 0 7600 7601 /* MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ msgresponse */ 7602 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_LEN 8 7603 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK1_OFST 0 7604 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK2_OFST 4 7605 7606 /* MC_CMD_MUM_OUT_GPIO_OP_OUT_READ msgresponse */ 7607 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_LEN 4 7608 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_BIT_READ_OFST 0 7609 7610 /* MC_CMD_MUM_OUT_GPIO_OP_OUT_WRITE msgresponse */ 7611 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_WRITE_LEN 0 7612 7613 /* MC_CMD_MUM_OUT_GPIO_OP_OUT_CONFIG msgresponse */ 7614 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_CONFIG_LEN 0 7615 7616 /* MC_CMD_MUM_OUT_GPIO_OP_OUT_ENABLE msgresponse */ 7617 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_ENABLE_LEN 0 7618 7619 /* MC_CMD_MUM_OUT_READ_SENSORS msgresponse */ 7620 #define MC_CMD_MUM_OUT_READ_SENSORS_LENMIN 4 7621 #define MC_CMD_MUM_OUT_READ_SENSORS_LENMAX 252 7622 #define MC_CMD_MUM_OUT_READ_SENSORS_LEN(num) (0+4*(num)) 7623 #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_OFST 0 7624 #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_LEN 4 7625 #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_MINNUM 1 7626 #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_MAXNUM 63 7627 #define MC_CMD_MUM_OUT_READ_SENSORS_READING_LBN 0 7628 #define MC_CMD_MUM_OUT_READ_SENSORS_READING_WIDTH 16 7629 #define MC_CMD_MUM_OUT_READ_SENSORS_STATE_LBN 16 7630 #define MC_CMD_MUM_OUT_READ_SENSORS_STATE_WIDTH 8 7631 #define MC_CMD_MUM_OUT_READ_SENSORS_TYPE_LBN 24 7632 #define MC_CMD_MUM_OUT_READ_SENSORS_TYPE_WIDTH 8 7633 7634 /* MC_CMD_MUM_OUT_PROGRAM_CLOCKS msgresponse */ 7635 #define MC_CMD_MUM_OUT_PROGRAM_CLOCKS_LEN 4 7636 #define MC_CMD_MUM_OUT_PROGRAM_CLOCKS_OK_MASK_OFST 0 7637 7638 /* MC_CMD_MUM_OUT_FPGA_LOAD msgresponse */ 7639 #define MC_CMD_MUM_OUT_FPGA_LOAD_LEN 0 7640 7641 /* MC_CMD_MUM_OUT_READ_ATB_SENSOR msgresponse */ 7642 #define MC_CMD_MUM_OUT_READ_ATB_SENSOR_LEN 4 7643 #define MC_CMD_MUM_OUT_READ_ATB_SENSOR_RESULT_OFST 0 7644 7645 /* MC_CMD_MUM_OUT_QSFP_INIT msgresponse */ 7646 #define MC_CMD_MUM_OUT_QSFP_INIT_LEN 0 7647 7648 /* MC_CMD_MUM_OUT_QSFP_RECONFIGURE msgresponse */ 7649 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_LEN 8 7650 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LP_CAP_OFST 0 7651 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_FLAGS_OFST 4 7652 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_LBN 0 7653 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_WIDTH 1 7654 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_LBN 1 7655 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_WIDTH 1 7656 7657 /* MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP msgresponse */ 7658 #define MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_LEN 4 7659 #define MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_PORT_PHY_LP_CAP_OFST 0 7660 7661 /* MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO msgresponse */ 7662 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LENMIN 5 7663 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LENMAX 252 7664 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LEN(num) (4+1*(num)) 7665 /* in bytes */ 7666 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATALEN_OFST 0 7667 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_OFST 4 7668 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_LEN 1 7669 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_MINNUM 1 7670 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_MAXNUM 248 7671 7672 /* MC_CMD_MUM_OUT_QSFP_FILL_STATS msgresponse */ 7673 #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_LEN 8 7674 #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PMA_PMD_LINK_UP_OFST 0 7675 #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PCS_LINK_UP_OFST 4 7676 7677 /* MC_CMD_MUM_OUT_QSFP_POLL_BIST msgresponse */ 7678 #define MC_CMD_MUM_OUT_QSFP_POLL_BIST_LEN 4 7679 #define MC_CMD_MUM_OUT_QSFP_POLL_BIST_TEST_OFST 0 7680 7681 /* MC_CMD_MUM_OUT_READ_DDR_INFO msgresponse */ 7682 #define MC_CMD_MUM_OUT_READ_DDR_INFO_LENMIN 24 7683 #define MC_CMD_MUM_OUT_READ_DDR_INFO_LENMAX 248 7684 #define MC_CMD_MUM_OUT_READ_DDR_INFO_LEN(num) (8+8*(num)) 7685 /* Discrete (soldered) DDR resistor strap info */ 7686 #define MC_CMD_MUM_OUT_READ_DDR_INFO_DISCRETE_DDR_INFO_OFST 0 7687 #define MC_CMD_MUM_OUT_READ_DDR_INFO_VRATIO_LBN 0 7688 #define MC_CMD_MUM_OUT_READ_DDR_INFO_VRATIO_WIDTH 16 7689 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED1_LBN 16 7690 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED1_WIDTH 16 7691 /* Number of SODIMM info records */ 7692 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_RECORDS_OFST 4 7693 /* Array of SODIMM info records */ 7694 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_OFST 8 7695 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LEN 8 7696 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LO_OFST 8 7697 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_HI_OFST 12 7698 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MINNUM 2 7699 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MAXNUM 30 7700 #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK_ID_LBN 0 7701 #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK_ID_WIDTH 8 7702 /* enum: SODIMM bank 1 (Top SODIMM for Sorrento) */ 7703 #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK1 0x0 7704 /* enum: SODIMM bank 2 (Bottom SODDIMM for Sorrento) */ 7705 #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK2 0x1 7706 /* enum: Total number of SODIMM banks */ 7707 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_BANKS 0x2 7708 #define MC_CMD_MUM_OUT_READ_DDR_INFO_TYPE_LBN 8 7709 #define MC_CMD_MUM_OUT_READ_DDR_INFO_TYPE_WIDTH 8 7710 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RANK_LBN 16 7711 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RANK_WIDTH 4 7712 #define MC_CMD_MUM_OUT_READ_DDR_INFO_VOLTAGE_LBN 20 7713 #define MC_CMD_MUM_OUT_READ_DDR_INFO_VOLTAGE_WIDTH 4 7714 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NOT_POWERED 0x0 /* enum */ 7715 #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V25 0x1 /* enum */ 7716 #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V35 0x2 /* enum */ 7717 #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V5 0x3 /* enum */ 7718 /* enum: Values 5-15 are reserved for future usage */ 7719 #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V8 0x4 7720 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SIZE_LBN 24 7721 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SIZE_WIDTH 8 7722 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SPEED_LBN 32 7723 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SPEED_WIDTH 16 7724 #define MC_CMD_MUM_OUT_READ_DDR_INFO_STATE_LBN 48 7725 #define MC_CMD_MUM_OUT_READ_DDR_INFO_STATE_WIDTH 4 7726 /* enum: No module present */ 7727 #define MC_CMD_MUM_OUT_READ_DDR_INFO_ABSENT 0x0 7728 /* enum: Module present supported and powered on */ 7729 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_POWERED 0x1 7730 /* enum: Module present but bad type */ 7731 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_TYPE 0x2 7732 /* enum: Module present but incompatible voltage */ 7733 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_VOLTAGE 0x3 7734 /* enum: Module present but unknown SPD */ 7735 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_SPD 0x4 7736 /* enum: Module present but slot cannot support it */ 7737 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_SLOT 0x5 7738 /* enum: Modules may or may not be present, but cannot establish contact by I2C 7739 */ 7740 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NOT_REACHABLE 0x6 7741 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED2_LBN 52 7742 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED2_WIDTH 12 7743 7744 /* MC_CMD_RESOURCE_SPECIFIER enum */ 7745 /* enum: Any */ 7746 #define MC_CMD_RESOURCE_INSTANCE_ANY 0xffffffff 7747 /* enum: None */ 7748 #define MC_CMD_RESOURCE_INSTANCE_NONE 0xfffffffe 7749 7750 /* EVB_PORT_ID structuredef */ 7751 #define EVB_PORT_ID_LEN 4 7752 #define EVB_PORT_ID_PORT_ID_OFST 0 7753 /* enum: An invalid port handle. */ 7754 #define EVB_PORT_ID_NULL 0x0 7755 /* enum: The port assigned to this function.. */ 7756 #define EVB_PORT_ID_ASSIGNED 0x1000000 7757 /* enum: External network port 0 */ 7758 #define EVB_PORT_ID_MAC0 0x2000000 7759 /* enum: External network port 1 */ 7760 #define EVB_PORT_ID_MAC1 0x2000001 7761 /* enum: External network port 2 */ 7762 #define EVB_PORT_ID_MAC2 0x2000002 7763 /* enum: External network port 3 */ 7764 #define EVB_PORT_ID_MAC3 0x2000003 7765 #define EVB_PORT_ID_PORT_ID_LBN 0 7766 #define EVB_PORT_ID_PORT_ID_WIDTH 32 7767 7768 /* EVB_VLAN_TAG structuredef */ 7769 #define EVB_VLAN_TAG_LEN 2 7770 /* The VLAN tag value */ 7771 #define EVB_VLAN_TAG_VLAN_ID_LBN 0 7772 #define EVB_VLAN_TAG_VLAN_ID_WIDTH 12 7773 #define EVB_VLAN_TAG_MODE_LBN 12 7774 #define EVB_VLAN_TAG_MODE_WIDTH 4 7775 /* enum: Insert the VLAN. */ 7776 #define EVB_VLAN_TAG_INSERT 0x0 7777 /* enum: Replace the VLAN if already present. */ 7778 #define EVB_VLAN_TAG_REPLACE 0x1 7779 7780 /* BUFTBL_ENTRY structuredef */ 7781 #define BUFTBL_ENTRY_LEN 12 7782 /* the owner ID */ 7783 #define BUFTBL_ENTRY_OID_OFST 0 7784 #define BUFTBL_ENTRY_OID_LEN 2 7785 #define BUFTBL_ENTRY_OID_LBN 0 7786 #define BUFTBL_ENTRY_OID_WIDTH 16 7787 /* the page parameter as one of ESE_DZ_SMC_PAGE_SIZE_ */ 7788 #define BUFTBL_ENTRY_PGSZ_OFST 2 7789 #define BUFTBL_ENTRY_PGSZ_LEN 2 7790 #define BUFTBL_ENTRY_PGSZ_LBN 16 7791 #define BUFTBL_ENTRY_PGSZ_WIDTH 16 7792 /* the raw 64-bit address field from the SMC, not adjusted for page size */ 7793 #define BUFTBL_ENTRY_RAWADDR_OFST 4 7794 #define BUFTBL_ENTRY_RAWADDR_LEN 8 7795 #define BUFTBL_ENTRY_RAWADDR_LO_OFST 4 7796 #define BUFTBL_ENTRY_RAWADDR_HI_OFST 8 7797 #define BUFTBL_ENTRY_RAWADDR_LBN 32 7798 #define BUFTBL_ENTRY_RAWADDR_WIDTH 64 7799 7800 /* NVRAM_PARTITION_TYPE structuredef */ 7801 #define NVRAM_PARTITION_TYPE_LEN 2 7802 #define NVRAM_PARTITION_TYPE_ID_OFST 0 7803 #define NVRAM_PARTITION_TYPE_ID_LEN 2 7804 /* enum: Primary MC firmware partition */ 7805 #define NVRAM_PARTITION_TYPE_MC_FIRMWARE 0x100 7806 /* enum: Secondary MC firmware partition */ 7807 #define NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP 0x200 7808 /* enum: Expansion ROM partition */ 7809 #define NVRAM_PARTITION_TYPE_EXPANSION_ROM 0x300 7810 /* enum: Static configuration TLV partition */ 7811 #define NVRAM_PARTITION_TYPE_STATIC_CONFIG 0x400 7812 /* enum: Dynamic configuration TLV partition */ 7813 #define NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG 0x500 7814 /* enum: Expansion ROM configuration data for port 0 */ 7815 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0 0x600 7816 /* enum: Synonym for EXPROM_CONFIG_PORT0 as used in pmap files */ 7817 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG 0x600 7818 /* enum: Expansion ROM configuration data for port 1 */ 7819 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1 0x601 7820 /* enum: Expansion ROM configuration data for port 2 */ 7821 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2 0x602 7822 /* enum: Expansion ROM configuration data for port 3 */ 7823 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3 0x603 7824 /* enum: Non-volatile log output partition */ 7825 #define NVRAM_PARTITION_TYPE_LOG 0x700 7826 /* enum: Non-volatile log output of second core on dual-core device */ 7827 #define NVRAM_PARTITION_TYPE_LOG_SLAVE 0x701 7828 /* enum: Device state dump output partition */ 7829 #define NVRAM_PARTITION_TYPE_DUMP 0x800 7830 /* enum: Application license key storage partition */ 7831 #define NVRAM_PARTITION_TYPE_LICENSE 0x900 7832 /* enum: Start of range used for PHY partitions (low 8 bits are the PHY ID) */ 7833 #define NVRAM_PARTITION_TYPE_PHY_MIN 0xa00 7834 /* enum: End of range used for PHY partitions (low 8 bits are the PHY ID) */ 7835 #define NVRAM_PARTITION_TYPE_PHY_MAX 0xaff 7836 /* enum: Primary FPGA partition */ 7837 #define NVRAM_PARTITION_TYPE_FPGA 0xb00 7838 /* enum: Secondary FPGA partition */ 7839 #define NVRAM_PARTITION_TYPE_FPGA_BACKUP 0xb01 7840 /* enum: FC firmware partition */ 7841 #define NVRAM_PARTITION_TYPE_FC_FIRMWARE 0xb02 7842 /* enum: FC License partition */ 7843 #define NVRAM_PARTITION_TYPE_FC_LICENSE 0xb03 7844 /* enum: Non-volatile log output partition for FC */ 7845 #define NVRAM_PARTITION_TYPE_FC_LOG 0xb04 7846 /* enum: MUM firmware partition */ 7847 #define NVRAM_PARTITION_TYPE_MUM_FIRMWARE 0xc00 7848 /* enum: MUM Non-volatile log output partition. */ 7849 #define NVRAM_PARTITION_TYPE_MUM_LOG 0xc01 7850 /* enum: MUM Application table partition. */ 7851 #define NVRAM_PARTITION_TYPE_MUM_APPTABLE 0xc02 7852 /* enum: MUM boot rom partition. */ 7853 #define NVRAM_PARTITION_TYPE_MUM_BOOT_ROM 0xc03 7854 /* enum: MUM production signatures & calibration rom partition. */ 7855 #define NVRAM_PARTITION_TYPE_MUM_PROD_ROM 0xc04 7856 /* enum: MUM user signatures & calibration rom partition. */ 7857 #define NVRAM_PARTITION_TYPE_MUM_USER_ROM 0xc05 7858 /* enum: MUM fuses and lockbits partition. */ 7859 #define NVRAM_PARTITION_TYPE_MUM_FUSELOCK 0xc06 7860 /* enum: UEFI expansion ROM if separate from PXE */ 7861 #define NVRAM_PARTITION_TYPE_EXPANSION_UEFI 0xd00 7862 /* enum: Spare partition 0 */ 7863 #define NVRAM_PARTITION_TYPE_SPARE_0 0x1000 7864 /* enum: Spare partition 1 */ 7865 #define NVRAM_PARTITION_TYPE_SPARE_1 0x1100 7866 /* enum: Spare partition 2 */ 7867 #define NVRAM_PARTITION_TYPE_SPARE_2 0x1200 7868 /* enum: Spare partition 3 */ 7869 #define NVRAM_PARTITION_TYPE_SPARE_3 0x1300 7870 /* enum: Spare partition 4 */ 7871 #define NVRAM_PARTITION_TYPE_SPARE_4 0x1400 7872 /* enum: Spare partition 5 */ 7873 #define NVRAM_PARTITION_TYPE_SPARE_5 0x1500 7874 /* enum: Start of reserved value range (firmware may use for any purpose) */ 7875 #define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MIN 0xff00 7876 /* enum: End of reserved value range (firmware may use for any purpose) */ 7877 #define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MAX 0xfffd 7878 /* enum: Recovery partition map (provided if real map is missing or corrupt) */ 7879 #define NVRAM_PARTITION_TYPE_RECOVERY_MAP 0xfffe 7880 /* enum: Partition map (real map as stored in flash) */ 7881 #define NVRAM_PARTITION_TYPE_PARTITION_MAP 0xffff 7882 #define NVRAM_PARTITION_TYPE_ID_LBN 0 7883 #define NVRAM_PARTITION_TYPE_ID_WIDTH 16 7884 7885 /* LICENSED_APP_ID structuredef */ 7886 #define LICENSED_APP_ID_LEN 4 7887 #define LICENSED_APP_ID_ID_OFST 0 7888 /* enum: OpenOnload */ 7889 #define LICENSED_APP_ID_ONLOAD 0x1 7890 /* enum: PTP timestamping */ 7891 #define LICENSED_APP_ID_PTP 0x2 7892 /* enum: SolarCapture Pro */ 7893 #define LICENSED_APP_ID_SOLARCAPTURE_PRO 0x4 7894 /* enum: SolarSecure filter engine */ 7895 #define LICENSED_APP_ID_SOLARSECURE 0x8 7896 /* enum: Performance monitor */ 7897 #define LICENSED_APP_ID_PERF_MONITOR 0x10 7898 /* enum: SolarCapture Live */ 7899 #define LICENSED_APP_ID_SOLARCAPTURE_LIVE 0x20 7900 /* enum: Capture SolarSystem */ 7901 #define LICENSED_APP_ID_CAPTURE_SOLARSYSTEM 0x40 7902 /* enum: Network Access Control */ 7903 #define LICENSED_APP_ID_NETWORK_ACCESS_CONTROL 0x80 7904 #define LICENSED_APP_ID_ID_LBN 0 7905 #define LICENSED_APP_ID_ID_WIDTH 32 7906 7907 /* LICENSED_FEATURES structuredef */ 7908 #define LICENSED_FEATURES_LEN 8 7909 /* Bitmask of licensed firmware features */ 7910 #define LICENSED_FEATURES_MASK_OFST 0 7911 #define LICENSED_FEATURES_MASK_LEN 8 7912 #define LICENSED_FEATURES_MASK_LO_OFST 0 7913 #define LICENSED_FEATURES_MASK_HI_OFST 4 7914 #define LICENSED_FEATURES_RX_CUT_THROUGH_LBN 0 7915 #define LICENSED_FEATURES_RX_CUT_THROUGH_WIDTH 1 7916 #define LICENSED_FEATURES_PIO_LBN 1 7917 #define LICENSED_FEATURES_PIO_WIDTH 1 7918 #define LICENSED_FEATURES_EVQ_TIMER_LBN 2 7919 #define LICENSED_FEATURES_EVQ_TIMER_WIDTH 1 7920 #define LICENSED_FEATURES_CLOCK_LBN 3 7921 #define LICENSED_FEATURES_CLOCK_WIDTH 1 7922 #define LICENSED_FEATURES_RX_TIMESTAMPS_LBN 4 7923 #define LICENSED_FEATURES_RX_TIMESTAMPS_WIDTH 1 7924 #define LICENSED_FEATURES_TX_TIMESTAMPS_LBN 5 7925 #define LICENSED_FEATURES_TX_TIMESTAMPS_WIDTH 1 7926 #define LICENSED_FEATURES_RX_SNIFF_LBN 6 7927 #define LICENSED_FEATURES_RX_SNIFF_WIDTH 1 7928 #define LICENSED_FEATURES_TX_SNIFF_LBN 7 7929 #define LICENSED_FEATURES_TX_SNIFF_WIDTH 1 7930 #define LICENSED_FEATURES_PROXY_FILTER_OPS_LBN 8 7931 #define LICENSED_FEATURES_PROXY_FILTER_OPS_WIDTH 1 7932 #define LICENSED_FEATURES_EVENT_CUT_THROUGH_LBN 9 7933 #define LICENSED_FEATURES_EVENT_CUT_THROUGH_WIDTH 1 7934 #define LICENSED_FEATURES_MASK_LBN 0 7935 #define LICENSED_FEATURES_MASK_WIDTH 64 7936 7937 /* LICENSED_V3_APPS structuredef */ 7938 #define LICENSED_V3_APPS_LEN 8 7939 /* Bitmask of licensed applications */ 7940 #define LICENSED_V3_APPS_MASK_OFST 0 7941 #define LICENSED_V3_APPS_MASK_LEN 8 7942 #define LICENSED_V3_APPS_MASK_LO_OFST 0 7943 #define LICENSED_V3_APPS_MASK_HI_OFST 4 7944 #define LICENSED_V3_APPS_ONLOAD_LBN 0 7945 #define LICENSED_V3_APPS_ONLOAD_WIDTH 1 7946 #define LICENSED_V3_APPS_PTP_LBN 1 7947 #define LICENSED_V3_APPS_PTP_WIDTH 1 7948 #define LICENSED_V3_APPS_SOLARCAPTURE_PRO_LBN 2 7949 #define LICENSED_V3_APPS_SOLARCAPTURE_PRO_WIDTH 1 7950 #define LICENSED_V3_APPS_SOLARSECURE_LBN 3 7951 #define LICENSED_V3_APPS_SOLARSECURE_WIDTH 1 7952 #define LICENSED_V3_APPS_PERF_MONITOR_LBN 4 7953 #define LICENSED_V3_APPS_PERF_MONITOR_WIDTH 1 7954 #define LICENSED_V3_APPS_SOLARCAPTURE_LIVE_LBN 5 7955 #define LICENSED_V3_APPS_SOLARCAPTURE_LIVE_WIDTH 1 7956 #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_LBN 6 7957 #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_WIDTH 1 7958 #define LICENSED_V3_APPS_NETWORK_ACCESS_CONTROL_LBN 7 7959 #define LICENSED_V3_APPS_NETWORK_ACCESS_CONTROL_WIDTH 1 7960 #define LICENSED_V3_APPS_MASK_LBN 0 7961 #define LICENSED_V3_APPS_MASK_WIDTH 64 7962 7963 /* LICENSED_V3_FEATURES structuredef */ 7964 #define LICENSED_V3_FEATURES_LEN 8 7965 /* Bitmask of licensed firmware features */ 7966 #define LICENSED_V3_FEATURES_MASK_OFST 0 7967 #define LICENSED_V3_FEATURES_MASK_LEN 8 7968 #define LICENSED_V3_FEATURES_MASK_LO_OFST 0 7969 #define LICENSED_V3_FEATURES_MASK_HI_OFST 4 7970 #define LICENSED_V3_FEATURES_RX_CUT_THROUGH_LBN 0 7971 #define LICENSED_V3_FEATURES_RX_CUT_THROUGH_WIDTH 1 7972 #define LICENSED_V3_FEATURES_PIO_LBN 1 7973 #define LICENSED_V3_FEATURES_PIO_WIDTH 1 7974 #define LICENSED_V3_FEATURES_EVQ_TIMER_LBN 2 7975 #define LICENSED_V3_FEATURES_EVQ_TIMER_WIDTH 1 7976 #define LICENSED_V3_FEATURES_CLOCK_LBN 3 7977 #define LICENSED_V3_FEATURES_CLOCK_WIDTH 1 7978 #define LICENSED_V3_FEATURES_RX_TIMESTAMPS_LBN 4 7979 #define LICENSED_V3_FEATURES_RX_TIMESTAMPS_WIDTH 1 7980 #define LICENSED_V3_FEATURES_TX_TIMESTAMPS_LBN 5 7981 #define LICENSED_V3_FEATURES_TX_TIMESTAMPS_WIDTH 1 7982 #define LICENSED_V3_FEATURES_RX_SNIFF_LBN 6 7983 #define LICENSED_V3_FEATURES_RX_SNIFF_WIDTH 1 7984 #define LICENSED_V3_FEATURES_TX_SNIFF_LBN 7 7985 #define LICENSED_V3_FEATURES_TX_SNIFF_WIDTH 1 7986 #define LICENSED_V3_FEATURES_PROXY_FILTER_OPS_LBN 8 7987 #define LICENSED_V3_FEATURES_PROXY_FILTER_OPS_WIDTH 1 7988 #define LICENSED_V3_FEATURES_MASK_LBN 0 7989 #define LICENSED_V3_FEATURES_MASK_WIDTH 64 7990 7991 /* TX_TIMESTAMP_EVENT structuredef */ 7992 #define TX_TIMESTAMP_EVENT_LEN 6 7993 /* lower 16 bits of timestamp data */ 7994 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_OFST 0 7995 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_LEN 2 7996 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_LBN 0 7997 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_WIDTH 16 7998 /* Type of TX event, ordinary TX completion, low or high part of TX timestamp 7999 */ 8000 #define TX_TIMESTAMP_EVENT_TX_EV_TYPE_OFST 3 8001 #define TX_TIMESTAMP_EVENT_TX_EV_TYPE_LEN 1 8002 /* enum: This is a TX completion event, not a timestamp */ 8003 #define TX_TIMESTAMP_EVENT_TX_EV_COMPLETION 0x0 8004 /* enum: This is the low part of a TX timestamp event */ 8005 #define TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_LO 0x51 8006 /* enum: This is the high part of a TX timestamp event */ 8007 #define TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_HI 0x52 8008 #define TX_TIMESTAMP_EVENT_TX_EV_TYPE_LBN 24 8009 #define TX_TIMESTAMP_EVENT_TX_EV_TYPE_WIDTH 8 8010 /* upper 16 bits of timestamp data */ 8011 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_OFST 4 8012 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_LEN 2 8013 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_LBN 32 8014 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_WIDTH 16 8015 8016 /* RSS_MODE structuredef */ 8017 #define RSS_MODE_LEN 1 8018 /* The RSS mode for a particular packet type is a value from 0 - 15 which can 8019 * be considered as 4 bits selecting which fields are included in the hash. (A 8020 * value 0 effectively disables RSS spreading for the packet type.) The YAML 8021 * generation tools require this structure to be a whole number of bytes wide, 8022 * but only 4 bits are relevant. 8023 */ 8024 #define RSS_MODE_HASH_SELECTOR_OFST 0 8025 #define RSS_MODE_HASH_SELECTOR_LEN 1 8026 #define RSS_MODE_HASH_SRC_ADDR_LBN 0 8027 #define RSS_MODE_HASH_SRC_ADDR_WIDTH 1 8028 #define RSS_MODE_HASH_DST_ADDR_LBN 1 8029 #define RSS_MODE_HASH_DST_ADDR_WIDTH 1 8030 #define RSS_MODE_HASH_SRC_PORT_LBN 2 8031 #define RSS_MODE_HASH_SRC_PORT_WIDTH 1 8032 #define RSS_MODE_HASH_DST_PORT_LBN 3 8033 #define RSS_MODE_HASH_DST_PORT_WIDTH 1 8034 #define RSS_MODE_HASH_SELECTOR_LBN 0 8035 #define RSS_MODE_HASH_SELECTOR_WIDTH 8 8036 8037 8038 /***********************************/ 8039 /* MC_CMD_READ_REGS 8040 * Get a dump of the MCPU registers 8041 */ 8042 #define MC_CMD_READ_REGS 0x50 8043 #undef MC_CMD_0x50_PRIVILEGE_CTG 8044 8045 #define MC_CMD_0x50_PRIVILEGE_CTG SRIOV_CTG_ADMIN 8046 8047 /* MC_CMD_READ_REGS_IN msgrequest */ 8048 #define MC_CMD_READ_REGS_IN_LEN 0 8049 8050 /* MC_CMD_READ_REGS_OUT msgresponse */ 8051 #define MC_CMD_READ_REGS_OUT_LEN 308 8052 /* Whether the corresponding register entry contains a valid value */ 8053 #define MC_CMD_READ_REGS_OUT_MASK_OFST 0 8054 #define MC_CMD_READ_REGS_OUT_MASK_LEN 16 8055 /* Same order as MIPS GDB (r0-r31, sr, lo, hi, bad, cause, 32 x float, fsr, 8056 * fir, fp) 8057 */ 8058 #define MC_CMD_READ_REGS_OUT_REGS_OFST 16 8059 #define MC_CMD_READ_REGS_OUT_REGS_LEN 4 8060 #define MC_CMD_READ_REGS_OUT_REGS_NUM 73 8061 8062 8063 /***********************************/ 8064 /* MC_CMD_INIT_EVQ 8065 * Set up an event queue according to the supplied parameters. The IN arguments 8066 * end with an address for each 4k of host memory required to back the EVQ. 8067 */ 8068 #define MC_CMD_INIT_EVQ 0x80 8069 #undef MC_CMD_0x80_PRIVILEGE_CTG 8070 8071 #define MC_CMD_0x80_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8072 8073 /* MC_CMD_INIT_EVQ_IN msgrequest */ 8074 #define MC_CMD_INIT_EVQ_IN_LENMIN 44 8075 #define MC_CMD_INIT_EVQ_IN_LENMAX 548 8076 #define MC_CMD_INIT_EVQ_IN_LEN(num) (36+8*(num)) 8077 /* Size, in entries */ 8078 #define MC_CMD_INIT_EVQ_IN_SIZE_OFST 0 8079 /* Desired instance. Must be set to a specific instance, which is a function 8080 * local queue index. 8081 */ 8082 #define MC_CMD_INIT_EVQ_IN_INSTANCE_OFST 4 8083 /* The initial timer value. The load value is ignored if the timer mode is DIS. 8084 */ 8085 #define MC_CMD_INIT_EVQ_IN_TMR_LOAD_OFST 8 8086 /* The reload value is ignored in one-shot modes */ 8087 #define MC_CMD_INIT_EVQ_IN_TMR_RELOAD_OFST 12 8088 /* tbd */ 8089 #define MC_CMD_INIT_EVQ_IN_FLAGS_OFST 16 8090 #define MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_LBN 0 8091 #define MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_WIDTH 1 8092 #define MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_LBN 1 8093 #define MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_WIDTH 1 8094 #define MC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_LBN 2 8095 #define MC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_WIDTH 1 8096 #define MC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_LBN 3 8097 #define MC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_WIDTH 1 8098 #define MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_LBN 4 8099 #define MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_WIDTH 1 8100 #define MC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_LBN 5 8101 #define MC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_WIDTH 1 8102 #define MC_CMD_INIT_EVQ_IN_FLAG_USE_TIMER_LBN 6 8103 #define MC_CMD_INIT_EVQ_IN_FLAG_USE_TIMER_WIDTH 1 8104 #define MC_CMD_INIT_EVQ_IN_TMR_MODE_OFST 20 8105 /* enum: Disabled */ 8106 #define MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS 0x0 8107 /* enum: Immediate */ 8108 #define MC_CMD_INIT_EVQ_IN_TMR_IMMED_START 0x1 8109 /* enum: Triggered */ 8110 #define MC_CMD_INIT_EVQ_IN_TMR_TRIG_START 0x2 8111 /* enum: Hold-off */ 8112 #define MC_CMD_INIT_EVQ_IN_TMR_INT_HLDOFF 0x3 8113 /* Target EVQ for wakeups if in wakeup mode. */ 8114 #define MC_CMD_INIT_EVQ_IN_TARGET_EVQ_OFST 24 8115 /* Target interrupt if in interrupting mode (note union with target EVQ). Use 8116 * MC_CMD_RESOURCE_INSTANCE_ANY unless a specific one required for test 8117 * purposes. 8118 */ 8119 #define MC_CMD_INIT_EVQ_IN_IRQ_NUM_OFST 24 8120 /* Event Counter Mode. */ 8121 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_OFST 28 8122 /* enum: Disabled */ 8123 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS 0x0 8124 /* enum: Disabled */ 8125 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_RX 0x1 8126 /* enum: Disabled */ 8127 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_TX 0x2 8128 /* enum: Disabled */ 8129 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_RXTX 0x3 8130 /* Event queue packet count threshold. */ 8131 #define MC_CMD_INIT_EVQ_IN_COUNT_THRSHLD_OFST 32 8132 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 8133 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_OFST 36 8134 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LEN 8 8135 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LO_OFST 36 8136 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_HI_OFST 40 8137 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MINNUM 1 8138 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MAXNUM 64 8139 8140 /* MC_CMD_INIT_EVQ_OUT msgresponse */ 8141 #define MC_CMD_INIT_EVQ_OUT_LEN 4 8142 /* Only valid if INTRFLAG was true */ 8143 #define MC_CMD_INIT_EVQ_OUT_IRQ_OFST 0 8144 8145 /* QUEUE_CRC_MODE structuredef */ 8146 #define QUEUE_CRC_MODE_LEN 1 8147 #define QUEUE_CRC_MODE_MODE_LBN 0 8148 #define QUEUE_CRC_MODE_MODE_WIDTH 4 8149 /* enum: No CRC. */ 8150 #define QUEUE_CRC_MODE_NONE 0x0 8151 /* enum: CRC Fiber channel over ethernet. */ 8152 #define QUEUE_CRC_MODE_FCOE 0x1 8153 /* enum: CRC (digest) iSCSI header only. */ 8154 #define QUEUE_CRC_MODE_ISCSI_HDR 0x2 8155 /* enum: CRC (digest) iSCSI header and payload. */ 8156 #define QUEUE_CRC_MODE_ISCSI 0x3 8157 /* enum: CRC Fiber channel over IP over ethernet. */ 8158 #define QUEUE_CRC_MODE_FCOIPOE 0x4 8159 /* enum: CRC MPA. */ 8160 #define QUEUE_CRC_MODE_MPA 0x5 8161 #define QUEUE_CRC_MODE_SPARE_LBN 4 8162 #define QUEUE_CRC_MODE_SPARE_WIDTH 4 8163 8164 8165 /***********************************/ 8166 /* MC_CMD_INIT_RXQ 8167 * set up a receive queue according to the supplied parameters. The IN 8168 * arguments end with an address for each 4k of host memory required to back 8169 * the RXQ. 8170 */ 8171 #define MC_CMD_INIT_RXQ 0x81 8172 #undef MC_CMD_0x81_PRIVILEGE_CTG 8173 8174 #define MC_CMD_0x81_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8175 8176 /* MC_CMD_INIT_RXQ_IN msgrequest: Legacy RXQ_INIT request. Use extended version 8177 * in new code. 8178 */ 8179 #define MC_CMD_INIT_RXQ_IN_LENMIN 36 8180 #define MC_CMD_INIT_RXQ_IN_LENMAX 252 8181 #define MC_CMD_INIT_RXQ_IN_LEN(num) (28+8*(num)) 8182 /* Size, in entries */ 8183 #define MC_CMD_INIT_RXQ_IN_SIZE_OFST 0 8184 /* The EVQ to send events to. This is an index originally specified to INIT_EVQ 8185 */ 8186 #define MC_CMD_INIT_RXQ_IN_TARGET_EVQ_OFST 4 8187 /* The value to put in the event data. Check hardware spec. for valid range. */ 8188 #define MC_CMD_INIT_RXQ_IN_LABEL_OFST 8 8189 /* Desired instance. Must be set to a specific instance, which is a function 8190 * local queue index. 8191 */ 8192 #define MC_CMD_INIT_RXQ_IN_INSTANCE_OFST 12 8193 /* There will be more flags here. */ 8194 #define MC_CMD_INIT_RXQ_IN_FLAGS_OFST 16 8195 #define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_LBN 0 8196 #define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_WIDTH 1 8197 #define MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_LBN 1 8198 #define MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_WIDTH 1 8199 #define MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_LBN 2 8200 #define MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_WIDTH 1 8201 #define MC_CMD_INIT_RXQ_IN_CRC_MODE_LBN 3 8202 #define MC_CMD_INIT_RXQ_IN_CRC_MODE_WIDTH 4 8203 #define MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_LBN 7 8204 #define MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_WIDTH 1 8205 #define MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_LBN 8 8206 #define MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_WIDTH 1 8207 #define MC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_LBN 9 8208 #define MC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_WIDTH 1 8209 #define MC_CMD_INIT_RXQ_IN_FLAG_FORCE_EV_MERGING_LBN 10 8210 #define MC_CMD_INIT_RXQ_IN_FLAG_FORCE_EV_MERGING_WIDTH 1 8211 /* Owner ID to use if in buffer mode (zero if physical) */ 8212 #define MC_CMD_INIT_RXQ_IN_OWNER_ID_OFST 20 8213 /* The port ID associated with the v-adaptor which should contain this DMAQ. */ 8214 #define MC_CMD_INIT_RXQ_IN_PORT_ID_OFST 24 8215 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 8216 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_OFST 28 8217 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LEN 8 8218 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LO_OFST 28 8219 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_HI_OFST 32 8220 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MINNUM 1 8221 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MAXNUM 28 8222 8223 /* MC_CMD_INIT_RXQ_EXT_IN msgrequest: Extended RXQ_INIT with additional mode 8224 * flags 8225 */ 8226 #define MC_CMD_INIT_RXQ_EXT_IN_LEN 544 8227 /* Size, in entries */ 8228 #define MC_CMD_INIT_RXQ_EXT_IN_SIZE_OFST 0 8229 /* The EVQ to send events to. This is an index originally specified to INIT_EVQ 8230 */ 8231 #define MC_CMD_INIT_RXQ_EXT_IN_TARGET_EVQ_OFST 4 8232 /* The value to put in the event data. Check hardware spec. for valid range. */ 8233 #define MC_CMD_INIT_RXQ_EXT_IN_LABEL_OFST 8 8234 /* Desired instance. Must be set to a specific instance, which is a function 8235 * local queue index. 8236 */ 8237 #define MC_CMD_INIT_RXQ_EXT_IN_INSTANCE_OFST 12 8238 /* There will be more flags here. */ 8239 #define MC_CMD_INIT_RXQ_EXT_IN_FLAGS_OFST 16 8240 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_LBN 0 8241 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_WIDTH 1 8242 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT_LBN 1 8243 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT_WIDTH 1 8244 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_TIMESTAMP_LBN 2 8245 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_TIMESTAMP_WIDTH 1 8246 #define MC_CMD_INIT_RXQ_EXT_IN_CRC_MODE_LBN 3 8247 #define MC_CMD_INIT_RXQ_EXT_IN_CRC_MODE_WIDTH 4 8248 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_CHAIN_LBN 7 8249 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_CHAIN_WIDTH 1 8250 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_PREFIX_LBN 8 8251 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_PREFIX_WIDTH 1 8252 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER_LBN 9 8253 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER_WIDTH 1 8254 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_LBN 10 8255 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_WIDTH 4 8256 /* enum: One packet per descriptor (for normal networking) */ 8257 #define MC_CMD_INIT_RXQ_EXT_IN_SINGLE_PACKET 0x0 8258 /* enum: Pack multiple packets into large descriptors (for SolarCapture) */ 8259 #define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM 0x1 8260 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_LBN 14 8261 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_WIDTH 1 8262 #define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE_LBN 15 8263 #define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE_WIDTH 3 8264 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_1M 0x0 /* enum */ 8265 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_512K 0x1 /* enum */ 8266 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_256K 0x2 /* enum */ 8267 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_128K 0x3 /* enum */ 8268 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_64K 0x4 /* enum */ 8269 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES_LBN 18 8270 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 1 8271 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_FORCE_EV_MERGING_LBN 19 8272 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_FORCE_EV_MERGING_WIDTH 1 8273 /* Owner ID to use if in buffer mode (zero if physical) */ 8274 #define MC_CMD_INIT_RXQ_EXT_IN_OWNER_ID_OFST 20 8275 /* The port ID associated with the v-adaptor which should contain this DMAQ. */ 8276 #define MC_CMD_INIT_RXQ_EXT_IN_PORT_ID_OFST 24 8277 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 8278 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_OFST 28 8279 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LEN 8 8280 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LO_OFST 28 8281 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_HI_OFST 32 8282 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_NUM 64 8283 /* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */ 8284 #define MC_CMD_INIT_RXQ_EXT_IN_SNAPSHOT_LENGTH_OFST 540 8285 8286 /* MC_CMD_INIT_RXQ_OUT msgresponse */ 8287 #define MC_CMD_INIT_RXQ_OUT_LEN 0 8288 8289 /* MC_CMD_INIT_RXQ_EXT_OUT msgresponse */ 8290 #define MC_CMD_INIT_RXQ_EXT_OUT_LEN 0 8291 8292 8293 /***********************************/ 8294 /* MC_CMD_INIT_TXQ 8295 */ 8296 #define MC_CMD_INIT_TXQ 0x82 8297 #undef MC_CMD_0x82_PRIVILEGE_CTG 8298 8299 #define MC_CMD_0x82_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8300 8301 /* MC_CMD_INIT_TXQ_IN msgrequest: Legacy INIT_TXQ request. Use extended version 8302 * in new code. 8303 */ 8304 #define MC_CMD_INIT_TXQ_IN_LENMIN 36 8305 #define MC_CMD_INIT_TXQ_IN_LENMAX 252 8306 #define MC_CMD_INIT_TXQ_IN_LEN(num) (28+8*(num)) 8307 /* Size, in entries */ 8308 #define MC_CMD_INIT_TXQ_IN_SIZE_OFST 0 8309 /* The EVQ to send events to. This is an index originally specified to 8310 * INIT_EVQ. 8311 */ 8312 #define MC_CMD_INIT_TXQ_IN_TARGET_EVQ_OFST 4 8313 /* The value to put in the event data. Check hardware spec. for valid range. */ 8314 #define MC_CMD_INIT_TXQ_IN_LABEL_OFST 8 8315 /* Desired instance. Must be set to a specific instance, which is a function 8316 * local queue index. 8317 */ 8318 #define MC_CMD_INIT_TXQ_IN_INSTANCE_OFST 12 8319 /* There will be more flags here. */ 8320 #define MC_CMD_INIT_TXQ_IN_FLAGS_OFST 16 8321 #define MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_LBN 0 8322 #define MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_WIDTH 1 8323 #define MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_LBN 1 8324 #define MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_WIDTH 1 8325 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_LBN 2 8326 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_WIDTH 1 8327 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_LBN 3 8328 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_WIDTH 1 8329 #define MC_CMD_INIT_TXQ_IN_CRC_MODE_LBN 4 8330 #define MC_CMD_INIT_TXQ_IN_CRC_MODE_WIDTH 4 8331 #define MC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_LBN 8 8332 #define MC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_WIDTH 1 8333 #define MC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_LBN 9 8334 #define MC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_WIDTH 1 8335 #define MC_CMD_INIT_TXQ_IN_FLAG_INNER_IP_CSUM_EN_LBN 10 8336 #define MC_CMD_INIT_TXQ_IN_FLAG_INNER_IP_CSUM_EN_WIDTH 1 8337 #define MC_CMD_INIT_TXQ_IN_FLAG_INNER_TCP_CSUM_EN_LBN 11 8338 #define MC_CMD_INIT_TXQ_IN_FLAG_INNER_TCP_CSUM_EN_WIDTH 1 8339 /* Owner ID to use if in buffer mode (zero if physical) */ 8340 #define MC_CMD_INIT_TXQ_IN_OWNER_ID_OFST 20 8341 /* The port ID associated with the v-adaptor which should contain this DMAQ. */ 8342 #define MC_CMD_INIT_TXQ_IN_PORT_ID_OFST 24 8343 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 8344 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_OFST 28 8345 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LEN 8 8346 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LO_OFST 28 8347 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_HI_OFST 32 8348 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MINNUM 1 8349 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MAXNUM 28 8350 8351 /* MC_CMD_INIT_TXQ_EXT_IN msgrequest: Extended INIT_TXQ with additional mode 8352 * flags 8353 */ 8354 #define MC_CMD_INIT_TXQ_EXT_IN_LEN 544 8355 /* Size, in entries */ 8356 #define MC_CMD_INIT_TXQ_EXT_IN_SIZE_OFST 0 8357 /* The EVQ to send events to. This is an index originally specified to 8358 * INIT_EVQ. 8359 */ 8360 #define MC_CMD_INIT_TXQ_EXT_IN_TARGET_EVQ_OFST 4 8361 /* The value to put in the event data. Check hardware spec. for valid range. */ 8362 #define MC_CMD_INIT_TXQ_EXT_IN_LABEL_OFST 8 8363 /* Desired instance. Must be set to a specific instance, which is a function 8364 * local queue index. 8365 */ 8366 #define MC_CMD_INIT_TXQ_EXT_IN_INSTANCE_OFST 12 8367 /* There will be more flags here. */ 8368 #define MC_CMD_INIT_TXQ_EXT_IN_FLAGS_OFST 16 8369 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_BUFF_MODE_LBN 0 8370 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_BUFF_MODE_WIDTH 1 8371 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_IP_CSUM_DIS_LBN 1 8372 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_IP_CSUM_DIS_WIDTH 1 8373 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_CSUM_DIS_LBN 2 8374 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_CSUM_DIS_WIDTH 1 8375 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_UDP_ONLY_LBN 3 8376 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_UDP_ONLY_WIDTH 1 8377 #define MC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_LBN 4 8378 #define MC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_WIDTH 4 8379 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TIMESTAMP_LBN 8 8380 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TIMESTAMP_WIDTH 1 8381 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_PACER_BYPASS_LBN 9 8382 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_PACER_BYPASS_WIDTH 1 8383 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN_LBN 10 8384 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN_WIDTH 1 8385 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN_LBN 11 8386 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN_WIDTH 1 8387 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TSOV2_EN_LBN 12 8388 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TSOV2_EN_WIDTH 1 8389 /* Owner ID to use if in buffer mode (zero if physical) */ 8390 #define MC_CMD_INIT_TXQ_EXT_IN_OWNER_ID_OFST 20 8391 /* The port ID associated with the v-adaptor which should contain this DMAQ. */ 8392 #define MC_CMD_INIT_TXQ_EXT_IN_PORT_ID_OFST 24 8393 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 8394 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_OFST 28 8395 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LEN 8 8396 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LO_OFST 28 8397 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_HI_OFST 32 8398 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MINNUM 1 8399 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MAXNUM 64 8400 /* Flags related to Qbb flow control mode. */ 8401 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_FLAGS_OFST 540 8402 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_ENABLE_LBN 0 8403 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_ENABLE_WIDTH 1 8404 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_PRIORITY_LBN 1 8405 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_PRIORITY_WIDTH 3 8406 8407 /* MC_CMD_INIT_TXQ_OUT msgresponse */ 8408 #define MC_CMD_INIT_TXQ_OUT_LEN 0 8409 8410 8411 /***********************************/ 8412 /* MC_CMD_FINI_EVQ 8413 * Teardown an EVQ. 8414 * 8415 * All DMAQs or EVQs that point to the EVQ to tear down must be torn down first 8416 * or the operation will fail with EBUSY 8417 */ 8418 #define MC_CMD_FINI_EVQ 0x83 8419 #undef MC_CMD_0x83_PRIVILEGE_CTG 8420 8421 #define MC_CMD_0x83_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8422 8423 /* MC_CMD_FINI_EVQ_IN msgrequest */ 8424 #define MC_CMD_FINI_EVQ_IN_LEN 4 8425 /* Instance of EVQ to destroy. Should be the same instance as that previously 8426 * passed to INIT_EVQ 8427 */ 8428 #define MC_CMD_FINI_EVQ_IN_INSTANCE_OFST 0 8429 8430 /* MC_CMD_FINI_EVQ_OUT msgresponse */ 8431 #define MC_CMD_FINI_EVQ_OUT_LEN 0 8432 8433 8434 /***********************************/ 8435 /* MC_CMD_FINI_RXQ 8436 * Teardown a RXQ. 8437 */ 8438 #define MC_CMD_FINI_RXQ 0x84 8439 #undef MC_CMD_0x84_PRIVILEGE_CTG 8440 8441 #define MC_CMD_0x84_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8442 8443 /* MC_CMD_FINI_RXQ_IN msgrequest */ 8444 #define MC_CMD_FINI_RXQ_IN_LEN 4 8445 /* Instance of RXQ to destroy */ 8446 #define MC_CMD_FINI_RXQ_IN_INSTANCE_OFST 0 8447 8448 /* MC_CMD_FINI_RXQ_OUT msgresponse */ 8449 #define MC_CMD_FINI_RXQ_OUT_LEN 0 8450 8451 8452 /***********************************/ 8453 /* MC_CMD_FINI_TXQ 8454 * Teardown a TXQ. 8455 */ 8456 #define MC_CMD_FINI_TXQ 0x85 8457 #undef MC_CMD_0x85_PRIVILEGE_CTG 8458 8459 #define MC_CMD_0x85_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8460 8461 /* MC_CMD_FINI_TXQ_IN msgrequest */ 8462 #define MC_CMD_FINI_TXQ_IN_LEN 4 8463 /* Instance of TXQ to destroy */ 8464 #define MC_CMD_FINI_TXQ_IN_INSTANCE_OFST 0 8465 8466 /* MC_CMD_FINI_TXQ_OUT msgresponse */ 8467 #define MC_CMD_FINI_TXQ_OUT_LEN 0 8468 8469 8470 /***********************************/ 8471 /* MC_CMD_DRIVER_EVENT 8472 * Generate an event on an EVQ belonging to the function issuing the command. 8473 */ 8474 #define MC_CMD_DRIVER_EVENT 0x86 8475 #undef MC_CMD_0x86_PRIVILEGE_CTG 8476 8477 #define MC_CMD_0x86_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8478 8479 /* MC_CMD_DRIVER_EVENT_IN msgrequest */ 8480 #define MC_CMD_DRIVER_EVENT_IN_LEN 12 8481 /* Handle of target EVQ */ 8482 #define MC_CMD_DRIVER_EVENT_IN_EVQ_OFST 0 8483 /* Bits 0 - 63 of event */ 8484 #define MC_CMD_DRIVER_EVENT_IN_DATA_OFST 4 8485 #define MC_CMD_DRIVER_EVENT_IN_DATA_LEN 8 8486 #define MC_CMD_DRIVER_EVENT_IN_DATA_LO_OFST 4 8487 #define MC_CMD_DRIVER_EVENT_IN_DATA_HI_OFST 8 8488 8489 /* MC_CMD_DRIVER_EVENT_OUT msgresponse */ 8490 #define MC_CMD_DRIVER_EVENT_OUT_LEN 0 8491 8492 8493 /***********************************/ 8494 /* MC_CMD_PROXY_CMD 8495 * Execute an arbitrary MCDI command on behalf of a different function, subject 8496 * to security restrictions. The command to be proxied follows immediately 8497 * afterward in the host buffer (or on the UART). This command supercedes 8498 * MC_CMD_SET_FUNC, which remains available for Siena but now deprecated. 8499 */ 8500 #define MC_CMD_PROXY_CMD 0x5b 8501 #undef MC_CMD_0x5b_PRIVILEGE_CTG 8502 8503 #define MC_CMD_0x5b_PRIVILEGE_CTG SRIOV_CTG_ADMIN 8504 8505 /* MC_CMD_PROXY_CMD_IN msgrequest */ 8506 #define MC_CMD_PROXY_CMD_IN_LEN 4 8507 /* The handle of the target function. */ 8508 #define MC_CMD_PROXY_CMD_IN_TARGET_OFST 0 8509 #define MC_CMD_PROXY_CMD_IN_TARGET_PF_LBN 0 8510 #define MC_CMD_PROXY_CMD_IN_TARGET_PF_WIDTH 16 8511 #define MC_CMD_PROXY_CMD_IN_TARGET_VF_LBN 16 8512 #define MC_CMD_PROXY_CMD_IN_TARGET_VF_WIDTH 16 8513 #define MC_CMD_PROXY_CMD_IN_VF_NULL 0xffff /* enum */ 8514 8515 /* MC_CMD_PROXY_CMD_OUT msgresponse */ 8516 #define MC_CMD_PROXY_CMD_OUT_LEN 0 8517 8518 /* MC_PROXY_STATUS_BUFFER structuredef: Host memory status buffer used to 8519 * manage proxied requests 8520 */ 8521 #define MC_PROXY_STATUS_BUFFER_LEN 16 8522 /* Handle allocated by the firmware for this proxy transaction */ 8523 #define MC_PROXY_STATUS_BUFFER_HANDLE_OFST 0 8524 /* enum: An invalid handle. */ 8525 #define MC_PROXY_STATUS_BUFFER_HANDLE_INVALID 0x0 8526 #define MC_PROXY_STATUS_BUFFER_HANDLE_LBN 0 8527 #define MC_PROXY_STATUS_BUFFER_HANDLE_WIDTH 32 8528 /* The requesting physical function number */ 8529 #define MC_PROXY_STATUS_BUFFER_PF_OFST 4 8530 #define MC_PROXY_STATUS_BUFFER_PF_LEN 2 8531 #define MC_PROXY_STATUS_BUFFER_PF_LBN 32 8532 #define MC_PROXY_STATUS_BUFFER_PF_WIDTH 16 8533 /* The requesting virtual function number. Set to VF_NULL if the target is a 8534 * PF. 8535 */ 8536 #define MC_PROXY_STATUS_BUFFER_VF_OFST 6 8537 #define MC_PROXY_STATUS_BUFFER_VF_LEN 2 8538 #define MC_PROXY_STATUS_BUFFER_VF_LBN 48 8539 #define MC_PROXY_STATUS_BUFFER_VF_WIDTH 16 8540 /* The target function RID. */ 8541 #define MC_PROXY_STATUS_BUFFER_RID_OFST 8 8542 #define MC_PROXY_STATUS_BUFFER_RID_LEN 2 8543 #define MC_PROXY_STATUS_BUFFER_RID_LBN 64 8544 #define MC_PROXY_STATUS_BUFFER_RID_WIDTH 16 8545 /* The status of the proxy as described in MC_CMD_PROXY_COMPLETE. */ 8546 #define MC_PROXY_STATUS_BUFFER_STATUS_OFST 10 8547 #define MC_PROXY_STATUS_BUFFER_STATUS_LEN 2 8548 #define MC_PROXY_STATUS_BUFFER_STATUS_LBN 80 8549 #define MC_PROXY_STATUS_BUFFER_STATUS_WIDTH 16 8550 /* If a request is authorized rather than carried out by the host, this is the 8551 * elevated privilege mask granted to the requesting function. 8552 */ 8553 #define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_OFST 12 8554 #define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_LBN 96 8555 #define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_WIDTH 32 8556 8557 8558 /***********************************/ 8559 /* MC_CMD_PROXY_CONFIGURE 8560 * Enable/disable authorization of MCDI requests from unprivileged functions by 8561 * a designated admin function 8562 */ 8563 #define MC_CMD_PROXY_CONFIGURE 0x58 8564 #undef MC_CMD_0x58_PRIVILEGE_CTG 8565 8566 #define MC_CMD_0x58_PRIVILEGE_CTG SRIOV_CTG_ADMIN 8567 8568 /* MC_CMD_PROXY_CONFIGURE_IN msgrequest */ 8569 #define MC_CMD_PROXY_CONFIGURE_IN_LEN 108 8570 #define MC_CMD_PROXY_CONFIGURE_IN_FLAGS_OFST 0 8571 #define MC_CMD_PROXY_CONFIGURE_IN_ENABLE_LBN 0 8572 #define MC_CMD_PROXY_CONFIGURE_IN_ENABLE_WIDTH 1 8573 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 8574 * of blocks, each of the size REQUEST_BLOCK_SIZE. 8575 */ 8576 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_OFST 4 8577 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LEN 8 8578 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LO_OFST 4 8579 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_HI_OFST 8 8580 /* Must be a power of 2 */ 8581 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BLOCK_SIZE_OFST 12 8582 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 8583 * of blocks, each of the size REPLY_BLOCK_SIZE. 8584 */ 8585 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_OFST 16 8586 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LEN 8 8587 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LO_OFST 16 8588 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_HI_OFST 20 8589 /* Must be a power of 2 */ 8590 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BLOCK_SIZE_OFST 24 8591 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 8592 * of blocks, each of the size STATUS_BLOCK_SIZE. This buffer is only needed if 8593 * host intends to complete proxied operations by using MC_CMD_PROXY_CMD. 8594 */ 8595 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_OFST 28 8596 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LEN 8 8597 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LO_OFST 28 8598 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_HI_OFST 32 8599 /* Must be a power of 2, or zero if this buffer is not provided */ 8600 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BLOCK_SIZE_OFST 36 8601 /* Applies to all three buffers */ 8602 #define MC_CMD_PROXY_CONFIGURE_IN_NUM_BLOCKS_OFST 40 8603 /* A bit mask defining which MCDI operations may be proxied */ 8604 #define MC_CMD_PROXY_CONFIGURE_IN_ALLOWED_MCDI_MASK_OFST 44 8605 #define MC_CMD_PROXY_CONFIGURE_IN_ALLOWED_MCDI_MASK_LEN 64 8606 8607 /* MC_CMD_PROXY_CONFIGURE_EXT_IN msgrequest */ 8608 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_LEN 112 8609 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_FLAGS_OFST 0 8610 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_ENABLE_LBN 0 8611 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_ENABLE_WIDTH 1 8612 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 8613 * of blocks, each of the size REQUEST_BLOCK_SIZE. 8614 */ 8615 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_OFST 4 8616 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LEN 8 8617 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LO_OFST 4 8618 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_HI_OFST 8 8619 /* Must be a power of 2 */ 8620 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BLOCK_SIZE_OFST 12 8621 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 8622 * of blocks, each of the size REPLY_BLOCK_SIZE. 8623 */ 8624 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_OFST 16 8625 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_LEN 8 8626 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_LO_OFST 16 8627 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_HI_OFST 20 8628 /* Must be a power of 2 */ 8629 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BLOCK_SIZE_OFST 24 8630 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 8631 * of blocks, each of the size STATUS_BLOCK_SIZE. This buffer is only needed if 8632 * host intends to complete proxied operations by using MC_CMD_PROXY_CMD. 8633 */ 8634 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_OFST 28 8635 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_LEN 8 8636 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_LO_OFST 28 8637 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_HI_OFST 32 8638 /* Must be a power of 2, or zero if this buffer is not provided */ 8639 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BLOCK_SIZE_OFST 36 8640 /* Applies to all three buffers */ 8641 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_NUM_BLOCKS_OFST 40 8642 /* A bit mask defining which MCDI operations may be proxied */ 8643 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_ALLOWED_MCDI_MASK_OFST 44 8644 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_ALLOWED_MCDI_MASK_LEN 64 8645 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_RESERVED_OFST 108 8646 8647 /* MC_CMD_PROXY_CONFIGURE_OUT msgresponse */ 8648 #define MC_CMD_PROXY_CONFIGURE_OUT_LEN 0 8649 8650 8651 /***********************************/ 8652 /* MC_CMD_PROXY_COMPLETE 8653 * Tells FW that a requested proxy operation has either been completed (by 8654 * using MC_CMD_PROXY_CMD) or authorized/declined. May only be sent by the 8655 * function that enabled proxying/authorization (by using 8656 * MC_CMD_PROXY_CONFIGURE). 8657 */ 8658 #define MC_CMD_PROXY_COMPLETE 0x5f 8659 #undef MC_CMD_0x5f_PRIVILEGE_CTG 8660 8661 #define MC_CMD_0x5f_PRIVILEGE_CTG SRIOV_CTG_ADMIN 8662 8663 /* MC_CMD_PROXY_COMPLETE_IN msgrequest */ 8664 #define MC_CMD_PROXY_COMPLETE_IN_LEN 12 8665 #define MC_CMD_PROXY_COMPLETE_IN_BLOCK_INDEX_OFST 0 8666 #define MC_CMD_PROXY_COMPLETE_IN_STATUS_OFST 4 8667 /* enum: The operation has been completed by using MC_CMD_PROXY_CMD, the reply 8668 * is stored in the REPLY_BUFF. 8669 */ 8670 #define MC_CMD_PROXY_COMPLETE_IN_COMPLETE 0x0 8671 /* enum: The operation has been authorized. The originating function may now 8672 * try again. 8673 */ 8674 #define MC_CMD_PROXY_COMPLETE_IN_AUTHORIZED 0x1 8675 /* enum: The operation has been declined. */ 8676 #define MC_CMD_PROXY_COMPLETE_IN_DECLINED 0x2 8677 /* enum: The authorization failed because the relevant application did not 8678 * respond in time. 8679 */ 8680 #define MC_CMD_PROXY_COMPLETE_IN_TIMEDOUT 0x3 8681 #define MC_CMD_PROXY_COMPLETE_IN_HANDLE_OFST 8 8682 8683 /* MC_CMD_PROXY_COMPLETE_OUT msgresponse */ 8684 #define MC_CMD_PROXY_COMPLETE_OUT_LEN 0 8685 8686 8687 /***********************************/ 8688 /* MC_CMD_ALLOC_BUFTBL_CHUNK 8689 * Allocate a set of buffer table entries using the specified owner ID. This 8690 * operation allocates the required buffer table entries (and fails if it 8691 * cannot do so). The buffer table entries will initially be zeroed. 8692 */ 8693 #define MC_CMD_ALLOC_BUFTBL_CHUNK 0x87 8694 #undef MC_CMD_0x87_PRIVILEGE_CTG 8695 8696 #define MC_CMD_0x87_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 8697 8698 /* MC_CMD_ALLOC_BUFTBL_CHUNK_IN msgrequest */ 8699 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_LEN 8 8700 /* Owner ID to use */ 8701 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_OWNER_OFST 0 8702 /* Size of buffer table pages to use, in bytes (note that only a few values are 8703 * legal on any specific hardware). 8704 */ 8705 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_PAGE_SIZE_OFST 4 8706 8707 /* MC_CMD_ALLOC_BUFTBL_CHUNK_OUT msgresponse */ 8708 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_LEN 12 8709 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_HANDLE_OFST 0 8710 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_NUMENTRIES_OFST 4 8711 /* Buffer table IDs for use in DMA descriptors. */ 8712 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_ID_OFST 8 8713 8714 8715 /***********************************/ 8716 /* MC_CMD_PROGRAM_BUFTBL_ENTRIES 8717 * Reprogram a set of buffer table entries in the specified chunk. 8718 */ 8719 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES 0x88 8720 #undef MC_CMD_0x88_PRIVILEGE_CTG 8721 8722 #define MC_CMD_0x88_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 8723 8724 /* MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN msgrequest */ 8725 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMIN 20 8726 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMAX 268 8727 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LEN(num) (12+8*(num)) 8728 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_HANDLE_OFST 0 8729 /* ID */ 8730 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_FIRSTID_OFST 4 8731 /* Num entries */ 8732 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_NUMENTRIES_OFST 8 8733 /* Buffer table entry address */ 8734 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_OFST 12 8735 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LEN 8 8736 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LO_OFST 12 8737 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_HI_OFST 16 8738 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MINNUM 1 8739 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MAXNUM 32 8740 8741 /* MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT msgresponse */ 8742 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT_LEN 0 8743 8744 8745 /***********************************/ 8746 /* MC_CMD_FREE_BUFTBL_CHUNK 8747 */ 8748 #define MC_CMD_FREE_BUFTBL_CHUNK 0x89 8749 #undef MC_CMD_0x89_PRIVILEGE_CTG 8750 8751 #define MC_CMD_0x89_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 8752 8753 /* MC_CMD_FREE_BUFTBL_CHUNK_IN msgrequest */ 8754 #define MC_CMD_FREE_BUFTBL_CHUNK_IN_LEN 4 8755 #define MC_CMD_FREE_BUFTBL_CHUNK_IN_HANDLE_OFST 0 8756 8757 /* MC_CMD_FREE_BUFTBL_CHUNK_OUT msgresponse */ 8758 #define MC_CMD_FREE_BUFTBL_CHUNK_OUT_LEN 0 8759 8760 /* PORT_CONFIG_ENTRY structuredef */ 8761 #define PORT_CONFIG_ENTRY_LEN 16 8762 /* External port number (label) */ 8763 #define PORT_CONFIG_ENTRY_EXT_NUMBER_OFST 0 8764 #define PORT_CONFIG_ENTRY_EXT_NUMBER_LEN 1 8765 #define PORT_CONFIG_ENTRY_EXT_NUMBER_LBN 0 8766 #define PORT_CONFIG_ENTRY_EXT_NUMBER_WIDTH 8 8767 /* Port core location */ 8768 #define PORT_CONFIG_ENTRY_CORE_OFST 1 8769 #define PORT_CONFIG_ENTRY_CORE_LEN 1 8770 #define PORT_CONFIG_ENTRY_STANDALONE 0x0 /* enum */ 8771 #define PORT_CONFIG_ENTRY_MASTER 0x1 /* enum */ 8772 #define PORT_CONFIG_ENTRY_SLAVE 0x2 /* enum */ 8773 #define PORT_CONFIG_ENTRY_CORE_LBN 8 8774 #define PORT_CONFIG_ENTRY_CORE_WIDTH 8 8775 /* Internal number (HW resource) relative to the core */ 8776 #define PORT_CONFIG_ENTRY_INT_NUMBER_OFST 2 8777 #define PORT_CONFIG_ENTRY_INT_NUMBER_LEN 1 8778 #define PORT_CONFIG_ENTRY_INT_NUMBER_LBN 16 8779 #define PORT_CONFIG_ENTRY_INT_NUMBER_WIDTH 8 8780 /* Reserved */ 8781 #define PORT_CONFIG_ENTRY_RSVD_OFST 3 8782 #define PORT_CONFIG_ENTRY_RSVD_LEN 1 8783 #define PORT_CONFIG_ENTRY_RSVD_LBN 24 8784 #define PORT_CONFIG_ENTRY_RSVD_WIDTH 8 8785 /* Bitmask of KR lanes used by the port */ 8786 #define PORT_CONFIG_ENTRY_LANES_OFST 4 8787 #define PORT_CONFIG_ENTRY_LANES_LBN 32 8788 #define PORT_CONFIG_ENTRY_LANES_WIDTH 32 8789 /* Port capabilities (MC_CMD_PHY_CAP_*) */ 8790 #define PORT_CONFIG_ENTRY_SUPPORTED_CAPS_OFST 8 8791 #define PORT_CONFIG_ENTRY_SUPPORTED_CAPS_LBN 64 8792 #define PORT_CONFIG_ENTRY_SUPPORTED_CAPS_WIDTH 32 8793 /* Reserved (align to 16 bytes) */ 8794 #define PORT_CONFIG_ENTRY_RSVD2_OFST 12 8795 #define PORT_CONFIG_ENTRY_RSVD2_LBN 96 8796 #define PORT_CONFIG_ENTRY_RSVD2_WIDTH 32 8797 8798 8799 /***********************************/ 8800 /* MC_CMD_FILTER_OP 8801 * Multiplexed MCDI call for filter operations 8802 */ 8803 #define MC_CMD_FILTER_OP 0x8a 8804 #undef MC_CMD_0x8a_PRIVILEGE_CTG 8805 8806 #define MC_CMD_0x8a_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8807 8808 /* MC_CMD_FILTER_OP_IN msgrequest */ 8809 #define MC_CMD_FILTER_OP_IN_LEN 108 8810 /* identifies the type of operation requested */ 8811 #define MC_CMD_FILTER_OP_IN_OP_OFST 0 8812 /* enum: single-recipient filter insert */ 8813 #define MC_CMD_FILTER_OP_IN_OP_INSERT 0x0 8814 /* enum: single-recipient filter remove */ 8815 #define MC_CMD_FILTER_OP_IN_OP_REMOVE 0x1 8816 /* enum: multi-recipient filter subscribe */ 8817 #define MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE 0x2 8818 /* enum: multi-recipient filter unsubscribe */ 8819 #define MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE 0x3 8820 /* enum: replace one recipient with another (warning - the filter handle may 8821 * change) 8822 */ 8823 #define MC_CMD_FILTER_OP_IN_OP_REPLACE 0x4 8824 /* filter handle (for remove / unsubscribe operations) */ 8825 #define MC_CMD_FILTER_OP_IN_HANDLE_OFST 4 8826 #define MC_CMD_FILTER_OP_IN_HANDLE_LEN 8 8827 #define MC_CMD_FILTER_OP_IN_HANDLE_LO_OFST 4 8828 #define MC_CMD_FILTER_OP_IN_HANDLE_HI_OFST 8 8829 /* The port ID associated with the v-adaptor which should contain this filter. 8830 */ 8831 #define MC_CMD_FILTER_OP_IN_PORT_ID_OFST 12 8832 /* fields to include in match criteria */ 8833 #define MC_CMD_FILTER_OP_IN_MATCH_FIELDS_OFST 16 8834 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_LBN 0 8835 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_WIDTH 1 8836 #define MC_CMD_FILTER_OP_IN_MATCH_DST_IP_LBN 1 8837 #define MC_CMD_FILTER_OP_IN_MATCH_DST_IP_WIDTH 1 8838 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_LBN 2 8839 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_WIDTH 1 8840 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_LBN 3 8841 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_WIDTH 1 8842 #define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_LBN 4 8843 #define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_WIDTH 1 8844 #define MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_LBN 5 8845 #define MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_WIDTH 1 8846 #define MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_LBN 6 8847 #define MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_WIDTH 1 8848 #define MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_LBN 7 8849 #define MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_WIDTH 1 8850 #define MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_LBN 8 8851 #define MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_WIDTH 1 8852 #define MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_LBN 9 8853 #define MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_WIDTH 1 8854 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_LBN 10 8855 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_WIDTH 1 8856 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_LBN 11 8857 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_WIDTH 1 8858 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN 30 8859 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1 8860 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN 31 8861 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1 8862 /* receive destination */ 8863 #define MC_CMD_FILTER_OP_IN_RX_DEST_OFST 20 8864 /* enum: drop packets */ 8865 #define MC_CMD_FILTER_OP_IN_RX_DEST_DROP 0x0 8866 /* enum: receive to host */ 8867 #define MC_CMD_FILTER_OP_IN_RX_DEST_HOST 0x1 8868 /* enum: receive to MC */ 8869 #define MC_CMD_FILTER_OP_IN_RX_DEST_MC 0x2 8870 /* enum: loop back to TXDP 0 */ 8871 #define MC_CMD_FILTER_OP_IN_RX_DEST_TX0 0x3 8872 /* enum: loop back to TXDP 1 */ 8873 #define MC_CMD_FILTER_OP_IN_RX_DEST_TX1 0x4 8874 /* receive queue handle (for multiple queue modes, this is the base queue) */ 8875 #define MC_CMD_FILTER_OP_IN_RX_QUEUE_OFST 24 8876 /* receive mode */ 8877 #define MC_CMD_FILTER_OP_IN_RX_MODE_OFST 28 8878 /* enum: receive to just the specified queue */ 8879 #define MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE 0x0 8880 /* enum: receive to multiple queues using RSS context */ 8881 #define MC_CMD_FILTER_OP_IN_RX_MODE_RSS 0x1 8882 /* enum: receive to multiple queues using .1p mapping */ 8883 #define MC_CMD_FILTER_OP_IN_RX_MODE_DOT1P_MAPPING 0x2 8884 /* enum: install a filter entry that will never match; for test purposes only 8885 */ 8886 #define MC_CMD_FILTER_OP_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000 8887 /* RSS context (for RX_MODE_RSS) or .1p mapping handle (for 8888 * RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or 8889 * MC_CMD_DOT1P_MAPPING_ALLOC. 8890 */ 8891 #define MC_CMD_FILTER_OP_IN_RX_CONTEXT_OFST 32 8892 /* transmit domain (reserved; set to 0) */ 8893 #define MC_CMD_FILTER_OP_IN_TX_DOMAIN_OFST 36 8894 /* transmit destination (either set the MAC and/or PM bits for explicit 8895 * control, or set this field to TX_DEST_DEFAULT for sensible default 8896 * behaviour) 8897 */ 8898 #define MC_CMD_FILTER_OP_IN_TX_DEST_OFST 40 8899 /* enum: request default behaviour (based on filter type) */ 8900 #define MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT 0xffffffff 8901 #define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_LBN 0 8902 #define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_WIDTH 1 8903 #define MC_CMD_FILTER_OP_IN_TX_DEST_PM_LBN 1 8904 #define MC_CMD_FILTER_OP_IN_TX_DEST_PM_WIDTH 1 8905 /* source MAC address to match (as bytes in network order) */ 8906 #define MC_CMD_FILTER_OP_IN_SRC_MAC_OFST 44 8907 #define MC_CMD_FILTER_OP_IN_SRC_MAC_LEN 6 8908 /* source port to match (as bytes in network order) */ 8909 #define MC_CMD_FILTER_OP_IN_SRC_PORT_OFST 50 8910 #define MC_CMD_FILTER_OP_IN_SRC_PORT_LEN 2 8911 /* destination MAC address to match (as bytes in network order) */ 8912 #define MC_CMD_FILTER_OP_IN_DST_MAC_OFST 52 8913 #define MC_CMD_FILTER_OP_IN_DST_MAC_LEN 6 8914 /* destination port to match (as bytes in network order) */ 8915 #define MC_CMD_FILTER_OP_IN_DST_PORT_OFST 58 8916 #define MC_CMD_FILTER_OP_IN_DST_PORT_LEN 2 8917 /* Ethernet type to match (as bytes in network order) */ 8918 #define MC_CMD_FILTER_OP_IN_ETHER_TYPE_OFST 60 8919 #define MC_CMD_FILTER_OP_IN_ETHER_TYPE_LEN 2 8920 /* Inner VLAN tag to match (as bytes in network order) */ 8921 #define MC_CMD_FILTER_OP_IN_INNER_VLAN_OFST 62 8922 #define MC_CMD_FILTER_OP_IN_INNER_VLAN_LEN 2 8923 /* Outer VLAN tag to match (as bytes in network order) */ 8924 #define MC_CMD_FILTER_OP_IN_OUTER_VLAN_OFST 64 8925 #define MC_CMD_FILTER_OP_IN_OUTER_VLAN_LEN 2 8926 /* IP protocol to match (in low byte; set high byte to 0) */ 8927 #define MC_CMD_FILTER_OP_IN_IP_PROTO_OFST 66 8928 #define MC_CMD_FILTER_OP_IN_IP_PROTO_LEN 2 8929 /* Firmware defined register 0 to match (reserved; set to 0) */ 8930 #define MC_CMD_FILTER_OP_IN_FWDEF0_OFST 68 8931 /* Firmware defined register 1 to match (reserved; set to 0) */ 8932 #define MC_CMD_FILTER_OP_IN_FWDEF1_OFST 72 8933 /* source IP address to match (as bytes in network order; set last 12 bytes to 8934 * 0 for IPv4 address) 8935 */ 8936 #define MC_CMD_FILTER_OP_IN_SRC_IP_OFST 76 8937 #define MC_CMD_FILTER_OP_IN_SRC_IP_LEN 16 8938 /* destination IP address to match (as bytes in network order; set last 12 8939 * bytes to 0 for IPv4 address) 8940 */ 8941 #define MC_CMD_FILTER_OP_IN_DST_IP_OFST 92 8942 #define MC_CMD_FILTER_OP_IN_DST_IP_LEN 16 8943 8944 /* MC_CMD_FILTER_OP_EXT_IN msgrequest: Extension to MC_CMD_FILTER_OP_IN to 8945 * include handling of VXLAN/NVGRE encapsulated frame filtering (which is 8946 * supported on Medford only). 8947 */ 8948 #define MC_CMD_FILTER_OP_EXT_IN_LEN 172 8949 /* identifies the type of operation requested */ 8950 #define MC_CMD_FILTER_OP_EXT_IN_OP_OFST 0 8951 /* Enum values, see field(s): */ 8952 /* MC_CMD_FILTER_OP_IN/OP */ 8953 /* filter handle (for remove / unsubscribe operations) */ 8954 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_OFST 4 8955 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LEN 8 8956 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LO_OFST 4 8957 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_HI_OFST 8 8958 /* The port ID associated with the v-adaptor which should contain this filter. 8959 */ 8960 #define MC_CMD_FILTER_OP_EXT_IN_PORT_ID_OFST 12 8961 /* fields to include in match criteria */ 8962 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_FIELDS_OFST 16 8963 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_LBN 0 8964 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_WIDTH 1 8965 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_IP_LBN 1 8966 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_IP_WIDTH 1 8967 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_MAC_LBN 2 8968 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_MAC_WIDTH 1 8969 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_PORT_LBN 3 8970 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_PORT_WIDTH 1 8971 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_LBN 4 8972 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_WIDTH 1 8973 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_PORT_LBN 5 8974 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_PORT_WIDTH 1 8975 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_LBN 6 8976 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_WIDTH 1 8977 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_INNER_VLAN_LBN 7 8978 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_INNER_VLAN_WIDTH 1 8979 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_OUTER_VLAN_LBN 8 8980 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_OUTER_VLAN_WIDTH 1 8981 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_LBN 9 8982 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_WIDTH 1 8983 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_FWDEF0_LBN 10 8984 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_FWDEF0_WIDTH 1 8985 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_VNI_OR_VSID_LBN 11 8986 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_VNI_OR_VSID_WIDTH 1 8987 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_IP_LBN 12 8988 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_IP_WIDTH 1 8989 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_IP_LBN 13 8990 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_IP_WIDTH 1 8991 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_MAC_LBN 14 8992 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_MAC_WIDTH 1 8993 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_PORT_LBN 15 8994 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_PORT_WIDTH 1 8995 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_MAC_LBN 16 8996 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_MAC_WIDTH 1 8997 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_PORT_LBN 17 8998 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_PORT_WIDTH 1 8999 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ETHER_TYPE_LBN 18 9000 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ETHER_TYPE_WIDTH 1 9001 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_INNER_VLAN_LBN 19 9002 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_INNER_VLAN_WIDTH 1 9003 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_OUTER_VLAN_LBN 20 9004 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_OUTER_VLAN_WIDTH 1 9005 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_IP_PROTO_LBN 21 9006 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_IP_PROTO_WIDTH 1 9007 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF0_LBN 22 9008 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF0_WIDTH 1 9009 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF1_LBN 23 9010 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF1_WIDTH 1 9011 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_LBN 24 9012 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_WIDTH 1 9013 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_LBN 25 9014 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_WIDTH 1 9015 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_LBN 30 9016 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1 9017 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_LBN 31 9018 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1 9019 /* receive destination */ 9020 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_OFST 20 9021 /* enum: drop packets */ 9022 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_DROP 0x0 9023 /* enum: receive to host */ 9024 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_HOST 0x1 9025 /* enum: receive to MC */ 9026 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_MC 0x2 9027 /* enum: loop back to TXDP 0 */ 9028 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_TX0 0x3 9029 /* enum: loop back to TXDP 1 */ 9030 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_TX1 0x4 9031 /* receive queue handle (for multiple queue modes, this is the base queue) */ 9032 #define MC_CMD_FILTER_OP_EXT_IN_RX_QUEUE_OFST 24 9033 /* receive mode */ 9034 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_OFST 28 9035 /* enum: receive to just the specified queue */ 9036 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_SIMPLE 0x0 9037 /* enum: receive to multiple queues using RSS context */ 9038 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_RSS 0x1 9039 /* enum: receive to multiple queues using .1p mapping */ 9040 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_DOT1P_MAPPING 0x2 9041 /* enum: install a filter entry that will never match; for test purposes only 9042 */ 9043 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000 9044 /* RSS context (for RX_MODE_RSS) or .1p mapping handle (for 9045 * RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or 9046 * MC_CMD_DOT1P_MAPPING_ALLOC. 9047 */ 9048 #define MC_CMD_FILTER_OP_EXT_IN_RX_CONTEXT_OFST 32 9049 /* transmit domain (reserved; set to 0) */ 9050 #define MC_CMD_FILTER_OP_EXT_IN_TX_DOMAIN_OFST 36 9051 /* transmit destination (either set the MAC and/or PM bits for explicit 9052 * control, or set this field to TX_DEST_DEFAULT for sensible default 9053 * behaviour) 9054 */ 9055 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_OFST 40 9056 /* enum: request default behaviour (based on filter type) */ 9057 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_DEFAULT 0xffffffff 9058 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_LBN 0 9059 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_WIDTH 1 9060 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_PM_LBN 1 9061 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_PM_WIDTH 1 9062 /* source MAC address to match (as bytes in network order) */ 9063 #define MC_CMD_FILTER_OP_EXT_IN_SRC_MAC_OFST 44 9064 #define MC_CMD_FILTER_OP_EXT_IN_SRC_MAC_LEN 6 9065 /* source port to match (as bytes in network order) */ 9066 #define MC_CMD_FILTER_OP_EXT_IN_SRC_PORT_OFST 50 9067 #define MC_CMD_FILTER_OP_EXT_IN_SRC_PORT_LEN 2 9068 /* destination MAC address to match (as bytes in network order) */ 9069 #define MC_CMD_FILTER_OP_EXT_IN_DST_MAC_OFST 52 9070 #define MC_CMD_FILTER_OP_EXT_IN_DST_MAC_LEN 6 9071 /* destination port to match (as bytes in network order) */ 9072 #define MC_CMD_FILTER_OP_EXT_IN_DST_PORT_OFST 58 9073 #define MC_CMD_FILTER_OP_EXT_IN_DST_PORT_LEN 2 9074 /* Ethernet type to match (as bytes in network order) */ 9075 #define MC_CMD_FILTER_OP_EXT_IN_ETHER_TYPE_OFST 60 9076 #define MC_CMD_FILTER_OP_EXT_IN_ETHER_TYPE_LEN 2 9077 /* Inner VLAN tag to match (as bytes in network order) */ 9078 #define MC_CMD_FILTER_OP_EXT_IN_INNER_VLAN_OFST 62 9079 #define MC_CMD_FILTER_OP_EXT_IN_INNER_VLAN_LEN 2 9080 /* Outer VLAN tag to match (as bytes in network order) */ 9081 #define MC_CMD_FILTER_OP_EXT_IN_OUTER_VLAN_OFST 64 9082 #define MC_CMD_FILTER_OP_EXT_IN_OUTER_VLAN_LEN 2 9083 /* IP protocol to match (in low byte; set high byte to 0) */ 9084 #define MC_CMD_FILTER_OP_EXT_IN_IP_PROTO_OFST 66 9085 #define MC_CMD_FILTER_OP_EXT_IN_IP_PROTO_LEN 2 9086 /* Firmware defined register 0 to match (reserved; set to 0) */ 9087 #define MC_CMD_FILTER_OP_EXT_IN_FWDEF0_OFST 68 9088 /* VNI (for VXLAN/Geneve, when IP protocol is UDP) or VSID (for NVGRE, when IP 9089 * protocol is GRE) to match (as bytes in network order; set last byte to 0 for 9090 * VXLAN/NVGRE, or 1 for Geneve) 9091 */ 9092 #define MC_CMD_FILTER_OP_EXT_IN_VNI_OR_VSID_OFST 72 9093 #define MC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_LBN 0 9094 #define MC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_WIDTH 24 9095 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_LBN 24 9096 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_WIDTH 8 9097 /* enum: Match VXLAN traffic with this VNI */ 9098 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_VXLAN 0x0 9099 /* enum: Match Geneve traffic with this VNI */ 9100 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_GENEVE 0x1 9101 /* enum: Reserved for experimental development use */ 9102 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_EXPERIMENTAL 0xfe 9103 #define MC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_LBN 0 9104 #define MC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_WIDTH 24 9105 #define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_LBN 24 9106 #define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_WIDTH 8 9107 /* enum: Match NVGRE traffic with this VSID */ 9108 #define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_NVGRE 0x0 9109 /* source IP address to match (as bytes in network order; set last 12 bytes to 9110 * 0 for IPv4 address) 9111 */ 9112 #define MC_CMD_FILTER_OP_EXT_IN_SRC_IP_OFST 76 9113 #define MC_CMD_FILTER_OP_EXT_IN_SRC_IP_LEN 16 9114 /* destination IP address to match (as bytes in network order; set last 12 9115 * bytes to 0 for IPv4 address) 9116 */ 9117 #define MC_CMD_FILTER_OP_EXT_IN_DST_IP_OFST 92 9118 #define MC_CMD_FILTER_OP_EXT_IN_DST_IP_LEN 16 9119 /* VXLAN/NVGRE inner frame source MAC address to match (as bytes in network 9120 * order) 9121 */ 9122 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_MAC_OFST 108 9123 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_MAC_LEN 6 9124 /* VXLAN/NVGRE inner frame source port to match (as bytes in network order) */ 9125 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_PORT_OFST 114 9126 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_PORT_LEN 2 9127 /* VXLAN/NVGRE inner frame destination MAC address to match (as bytes in 9128 * network order) 9129 */ 9130 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_MAC_OFST 116 9131 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_MAC_LEN 6 9132 /* VXLAN/NVGRE inner frame destination port to match (as bytes in network 9133 * order) 9134 */ 9135 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_PORT_OFST 122 9136 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_PORT_LEN 2 9137 /* VXLAN/NVGRE inner frame Ethernet type to match (as bytes in network order) 9138 */ 9139 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_ETHER_TYPE_OFST 124 9140 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_ETHER_TYPE_LEN 2 9141 /* VXLAN/NVGRE inner frame Inner VLAN tag to match (as bytes in network order) 9142 */ 9143 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_INNER_VLAN_OFST 126 9144 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_INNER_VLAN_LEN 2 9145 /* VXLAN/NVGRE inner frame Outer VLAN tag to match (as bytes in network order) 9146 */ 9147 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_OUTER_VLAN_OFST 128 9148 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_OUTER_VLAN_LEN 2 9149 /* VXLAN/NVGRE inner frame IP protocol to match (in low byte; set high byte to 9150 * 0) 9151 */ 9152 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_IP_PROTO_OFST 130 9153 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_IP_PROTO_LEN 2 9154 /* VXLAN/NVGRE inner frame Firmware defined register 0 to match (reserved; set 9155 * to 0) 9156 */ 9157 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF0_OFST 132 9158 /* VXLAN/NVGRE inner frame Firmware defined register 1 to match (reserved; set 9159 * to 0) 9160 */ 9161 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF1_OFST 136 9162 /* VXLAN/NVGRE inner frame source IP address to match (as bytes in network 9163 * order; set last 12 bytes to 0 for IPv4 address) 9164 */ 9165 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_IP_OFST 140 9166 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_IP_LEN 16 9167 /* VXLAN/NVGRE inner frame destination IP address to match (as bytes in network 9168 * order; set last 12 bytes to 0 for IPv4 address) 9169 */ 9170 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_IP_OFST 156 9171 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_IP_LEN 16 9172 9173 /* MC_CMD_FILTER_OP_OUT msgresponse */ 9174 #define MC_CMD_FILTER_OP_OUT_LEN 12 9175 /* identifies the type of operation requested */ 9176 #define MC_CMD_FILTER_OP_OUT_OP_OFST 0 9177 /* Enum values, see field(s): */ 9178 /* MC_CMD_FILTER_OP_IN/OP */ 9179 /* Returned filter handle (for insert / subscribe operations). Note that these 9180 * handles should be considered opaque to the host, although a value of 9181 * 0xFFFFFFFF_FFFFFFFF is guaranteed never to be a valid handle. 9182 */ 9183 #define MC_CMD_FILTER_OP_OUT_HANDLE_OFST 4 9184 #define MC_CMD_FILTER_OP_OUT_HANDLE_LEN 8 9185 #define MC_CMD_FILTER_OP_OUT_HANDLE_LO_OFST 4 9186 #define MC_CMD_FILTER_OP_OUT_HANDLE_HI_OFST 8 9187 /* enum: guaranteed invalid filter handle (low 32 bits) */ 9188 #define MC_CMD_FILTER_OP_OUT_HANDLE_LO_INVALID 0xffffffff 9189 /* enum: guaranteed invalid filter handle (high 32 bits) */ 9190 #define MC_CMD_FILTER_OP_OUT_HANDLE_HI_INVALID 0xffffffff 9191 9192 /* MC_CMD_FILTER_OP_EXT_OUT msgresponse */ 9193 #define MC_CMD_FILTER_OP_EXT_OUT_LEN 12 9194 /* identifies the type of operation requested */ 9195 #define MC_CMD_FILTER_OP_EXT_OUT_OP_OFST 0 9196 /* Enum values, see field(s): */ 9197 /* MC_CMD_FILTER_OP_EXT_IN/OP */ 9198 /* Returned filter handle (for insert / subscribe operations). Note that these 9199 * handles should be considered opaque to the host, although a value of 9200 * 0xFFFFFFFF_FFFFFFFF is guaranteed never to be a valid handle. 9201 */ 9202 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_OFST 4 9203 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LEN 8 9204 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LO_OFST 4 9205 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_HI_OFST 8 9206 /* Enum values, see field(s): */ 9207 /* MC_CMD_FILTER_OP_OUT/HANDLE */ 9208 9209 9210 /***********************************/ 9211 /* MC_CMD_GET_PARSER_DISP_INFO 9212 * Get information related to the parser-dispatcher subsystem 9213 */ 9214 #define MC_CMD_GET_PARSER_DISP_INFO 0xe4 9215 #undef MC_CMD_0xe4_PRIVILEGE_CTG 9216 9217 #define MC_CMD_0xe4_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9218 9219 /* MC_CMD_GET_PARSER_DISP_INFO_IN msgrequest */ 9220 #define MC_CMD_GET_PARSER_DISP_INFO_IN_LEN 4 9221 /* identifies the type of operation requested */ 9222 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_OFST 0 9223 /* enum: read the list of supported RX filter matches */ 9224 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES 0x1 9225 /* enum: read flags indicating restrictions on filter insertion for the calling 9226 * client 9227 */ 9228 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_RESTRICTIONS 0x2 9229 /* enum: read properties relating to security rules (Medford-only; for use by 9230 * SolarSecure apps, not directly by drivers. See SF-114946-SW.) 9231 */ 9232 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SECURITY_RULE_INFO 0x3 9233 /* enum: read the list of supported RX filter matches for VXLAN/NVGRE 9234 * encapsulated frames, which follow a different match sequence to normal 9235 * frames (Medford only) 9236 */ 9237 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_ENCAP_RX_MATCHES 0x4 9238 9239 /* MC_CMD_GET_PARSER_DISP_INFO_OUT msgresponse */ 9240 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMIN 8 9241 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX 252 9242 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_LEN(num) (8+4*(num)) 9243 /* identifies the type of operation requested */ 9244 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_OP_OFST 0 9245 /* Enum values, see field(s): */ 9246 /* MC_CMD_GET_PARSER_DISP_INFO_IN/OP */ 9247 /* number of supported match types */ 9248 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_NUM_SUPPORTED_MATCHES_OFST 4 9249 /* array of supported match types (valid MATCH_FIELDS values for 9250 * MC_CMD_FILTER_OP) sorted in decreasing priority order 9251 */ 9252 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_OFST 8 9253 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_LEN 4 9254 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MINNUM 0 9255 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM 61 9256 9257 /* MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT msgresponse */ 9258 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_LEN 8 9259 /* identifies the type of operation requested */ 9260 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_OP_OFST 0 9261 /* Enum values, see field(s): */ 9262 /* MC_CMD_GET_PARSER_DISP_INFO_IN/OP */ 9263 /* bitfield of filter insertion restrictions */ 9264 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_RESTRICTION_FLAGS_OFST 4 9265 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_LBN 0 9266 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_WIDTH 1 9267 9268 /* MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT msgresponse: 9269 * GET_PARSER_DISP_INFO response format for OP_GET_SECURITY_RULE_INFO. 9270 * (Medford-only; for use by SolarSecure apps, not directly by drivers. See 9271 * SF-114946-SW.) NOTE - this message definition is provisional. It has not yet 9272 * been used in any released code and may change during development. This note 9273 * will be removed once it is regarded as stable. 9274 */ 9275 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_LEN 36 9276 /* identifies the type of operation requested */ 9277 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_OP_OFST 0 9278 /* Enum values, see field(s): */ 9279 /* MC_CMD_GET_PARSER_DISP_INFO_IN/OP */ 9280 /* a version number representing the set of rule lookups that are implemented 9281 * by the currently running firmware 9282 */ 9283 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_RULES_VERSION_OFST 4 9284 /* enum: implements lookup sequences described in SF-114946-SW draft C */ 9285 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_RULES_VERSION_SF_114946_SW_C 0x0 9286 /* the number of nodes in the subnet map */ 9287 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_MAP_NUM_NODES_OFST 8 9288 /* the number of entries in one subnet map node */ 9289 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_MAP_NUM_ENTRIES_PER_NODE_OFST 12 9290 /* minimum valid value for a subnet ID in a subnet map leaf */ 9291 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_ID_MIN_OFST 16 9292 /* maximum valid value for a subnet ID in a subnet map leaf */ 9293 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_ID_MAX_OFST 20 9294 /* the number of entries in the local and remote port range maps */ 9295 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_PORTRANGE_TREE_NUM_ENTRIES_OFST 24 9296 /* minimum valid value for a portrange ID in a port range map leaf */ 9297 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_PORTRANGE_ID_MIN_OFST 28 9298 /* maximum valid value for a portrange ID in a port range map leaf */ 9299 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_PORTRANGE_ID_MAX_OFST 32 9300 9301 9302 /***********************************/ 9303 /* MC_CMD_PARSER_DISP_RW 9304 * Direct read/write of parser-dispatcher state (DICPUs and LUE) for debugging. 9305 * Please note that this interface is only of use to debug tools which have 9306 * knowledge of firmware and hardware data structures; nothing here is intended 9307 * for use by normal driver code. 9308 */ 9309 #define MC_CMD_PARSER_DISP_RW 0xe5 9310 #undef MC_CMD_0xe5_PRIVILEGE_CTG 9311 9312 #define MC_CMD_0xe5_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9313 9314 /* MC_CMD_PARSER_DISP_RW_IN msgrequest */ 9315 #define MC_CMD_PARSER_DISP_RW_IN_LEN 32 9316 /* identifies the target of the operation */ 9317 #define MC_CMD_PARSER_DISP_RW_IN_TARGET_OFST 0 9318 /* enum: RX dispatcher CPU */ 9319 #define MC_CMD_PARSER_DISP_RW_IN_RX_DICPU 0x0 9320 /* enum: TX dispatcher CPU */ 9321 #define MC_CMD_PARSER_DISP_RW_IN_TX_DICPU 0x1 9322 /* enum: Lookup engine (with original metadata format) */ 9323 #define MC_CMD_PARSER_DISP_RW_IN_LUE 0x2 9324 /* enum: Lookup engine (with requested metadata format) */ 9325 #define MC_CMD_PARSER_DISP_RW_IN_LUE_VERSIONED_METADATA 0x3 9326 /* enum: RX0 dispatcher CPU (alias for RX_DICPU; Medford has 2 RX DICPUs) */ 9327 #define MC_CMD_PARSER_DISP_RW_IN_RX0_DICPU 0x0 9328 /* enum: RX1 dispatcher CPU (only valid for Medford) */ 9329 #define MC_CMD_PARSER_DISP_RW_IN_RX1_DICPU 0x4 9330 /* enum: Miscellaneous other state (only valid for Medford) */ 9331 #define MC_CMD_PARSER_DISP_RW_IN_MISC_STATE 0x5 9332 /* identifies the type of operation requested */ 9333 #define MC_CMD_PARSER_DISP_RW_IN_OP_OFST 4 9334 /* enum: read a word of DICPU DMEM or a LUE entry */ 9335 #define MC_CMD_PARSER_DISP_RW_IN_READ 0x0 9336 /* enum: write a word of DICPU DMEM or a LUE entry */ 9337 #define MC_CMD_PARSER_DISP_RW_IN_WRITE 0x1 9338 /* enum: read-modify-write a word of DICPU DMEM (not valid for LUE) */ 9339 #define MC_CMD_PARSER_DISP_RW_IN_RMW 0x2 9340 /* data memory address (DICPU targets) or LUE index (LUE targets) */ 9341 #define MC_CMD_PARSER_DISP_RW_IN_ADDRESS_OFST 8 9342 /* selector (for MISC_STATE target) */ 9343 #define MC_CMD_PARSER_DISP_RW_IN_SELECTOR_OFST 8 9344 /* enum: Port to datapath mapping */ 9345 #define MC_CMD_PARSER_DISP_RW_IN_PORT_DP_MAPPING 0x1 9346 /* value to write (for DMEM writes) */ 9347 #define MC_CMD_PARSER_DISP_RW_IN_DMEM_WRITE_VALUE_OFST 12 9348 /* XOR value (for DMEM read-modify-writes: new = (old & mask) ^ value) */ 9349 #define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_XOR_VALUE_OFST 12 9350 /* AND mask (for DMEM read-modify-writes: new = (old & mask) ^ value) */ 9351 #define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_AND_MASK_OFST 16 9352 /* metadata format (for LUE reads using LUE_VERSIONED_METADATA) */ 9353 #define MC_CMD_PARSER_DISP_RW_IN_LUE_READ_METADATA_VERSION_OFST 12 9354 /* value to write (for LUE writes) */ 9355 #define MC_CMD_PARSER_DISP_RW_IN_LUE_WRITE_VALUE_OFST 12 9356 #define MC_CMD_PARSER_DISP_RW_IN_LUE_WRITE_VALUE_LEN 20 9357 9358 /* MC_CMD_PARSER_DISP_RW_OUT msgresponse */ 9359 #define MC_CMD_PARSER_DISP_RW_OUT_LEN 52 9360 /* value read (for DMEM reads) */ 9361 #define MC_CMD_PARSER_DISP_RW_OUT_DMEM_READ_VALUE_OFST 0 9362 /* value read (for LUE reads) */ 9363 #define MC_CMD_PARSER_DISP_RW_OUT_LUE_READ_VALUE_OFST 0 9364 #define MC_CMD_PARSER_DISP_RW_OUT_LUE_READ_VALUE_LEN 20 9365 /* up to 8 32-bit words of additional soft state from the LUE manager (the 9366 * exact content is firmware-dependent and intended only for debug use) 9367 */ 9368 #define MC_CMD_PARSER_DISP_RW_OUT_LUE_MGR_STATE_OFST 20 9369 #define MC_CMD_PARSER_DISP_RW_OUT_LUE_MGR_STATE_LEN 32 9370 /* datapath(s) used for each port (for MISC_STATE PORT_DP_MAPPING selector) */ 9371 #define MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_OFST 0 9372 #define MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_LEN 4 9373 #define MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_NUM 4 9374 #define MC_CMD_PARSER_DISP_RW_OUT_DP0 0x1 /* enum */ 9375 #define MC_CMD_PARSER_DISP_RW_OUT_DP1 0x2 /* enum */ 9376 9377 9378 /***********************************/ 9379 /* MC_CMD_GET_PF_COUNT 9380 * Get number of PFs on the device. 9381 */ 9382 #define MC_CMD_GET_PF_COUNT 0xb6 9383 #undef MC_CMD_0xb6_PRIVILEGE_CTG 9384 9385 #define MC_CMD_0xb6_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9386 9387 /* MC_CMD_GET_PF_COUNT_IN msgrequest */ 9388 #define MC_CMD_GET_PF_COUNT_IN_LEN 0 9389 9390 /* MC_CMD_GET_PF_COUNT_OUT msgresponse */ 9391 #define MC_CMD_GET_PF_COUNT_OUT_LEN 1 9392 /* Identifies the number of PFs on the device. */ 9393 #define MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_OFST 0 9394 #define MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_LEN 1 9395 9396 9397 /***********************************/ 9398 /* MC_CMD_SET_PF_COUNT 9399 * Set number of PFs on the device. 9400 */ 9401 #define MC_CMD_SET_PF_COUNT 0xb7 9402 9403 /* MC_CMD_SET_PF_COUNT_IN msgrequest */ 9404 #define MC_CMD_SET_PF_COUNT_IN_LEN 4 9405 /* New number of PFs on the device. */ 9406 #define MC_CMD_SET_PF_COUNT_IN_PF_COUNT_OFST 0 9407 9408 /* MC_CMD_SET_PF_COUNT_OUT msgresponse */ 9409 #define MC_CMD_SET_PF_COUNT_OUT_LEN 0 9410 9411 9412 /***********************************/ 9413 /* MC_CMD_GET_PORT_ASSIGNMENT 9414 * Get port assignment for current PCI function. 9415 */ 9416 #define MC_CMD_GET_PORT_ASSIGNMENT 0xb8 9417 #undef MC_CMD_0xb8_PRIVILEGE_CTG 9418 9419 #define MC_CMD_0xb8_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9420 9421 /* MC_CMD_GET_PORT_ASSIGNMENT_IN msgrequest */ 9422 #define MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN 0 9423 9424 /* MC_CMD_GET_PORT_ASSIGNMENT_OUT msgresponse */ 9425 #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN 4 9426 /* Identifies the port assignment for this function. */ 9427 #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_PORT_OFST 0 9428 9429 9430 /***********************************/ 9431 /* MC_CMD_SET_PORT_ASSIGNMENT 9432 * Set port assignment for current PCI function. 9433 */ 9434 #define MC_CMD_SET_PORT_ASSIGNMENT 0xb9 9435 #undef MC_CMD_0xb9_PRIVILEGE_CTG 9436 9437 #define MC_CMD_0xb9_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9438 9439 /* MC_CMD_SET_PORT_ASSIGNMENT_IN msgrequest */ 9440 #define MC_CMD_SET_PORT_ASSIGNMENT_IN_LEN 4 9441 /* Identifies the port assignment for this function. */ 9442 #define MC_CMD_SET_PORT_ASSIGNMENT_IN_PORT_OFST 0 9443 9444 /* MC_CMD_SET_PORT_ASSIGNMENT_OUT msgresponse */ 9445 #define MC_CMD_SET_PORT_ASSIGNMENT_OUT_LEN 0 9446 9447 9448 /***********************************/ 9449 /* MC_CMD_ALLOC_VIS 9450 * Allocate VIs for current PCI function. 9451 */ 9452 #define MC_CMD_ALLOC_VIS 0x8b 9453 #undef MC_CMD_0x8b_PRIVILEGE_CTG 9454 9455 #define MC_CMD_0x8b_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9456 9457 /* MC_CMD_ALLOC_VIS_IN msgrequest */ 9458 #define MC_CMD_ALLOC_VIS_IN_LEN 8 9459 /* The minimum number of VIs that is acceptable */ 9460 #define MC_CMD_ALLOC_VIS_IN_MIN_VI_COUNT_OFST 0 9461 /* The maximum number of VIs that would be useful */ 9462 #define MC_CMD_ALLOC_VIS_IN_MAX_VI_COUNT_OFST 4 9463 9464 /* MC_CMD_ALLOC_VIS_OUT msgresponse: Huntington-compatible VI_ALLOC request. 9465 * Use extended version in new code. 9466 */ 9467 #define MC_CMD_ALLOC_VIS_OUT_LEN 8 9468 /* The number of VIs allocated on this function */ 9469 #define MC_CMD_ALLOC_VIS_OUT_VI_COUNT_OFST 0 9470 /* The base absolute VI number allocated to this function. Required to 9471 * correctly interpret wakeup events. 9472 */ 9473 #define MC_CMD_ALLOC_VIS_OUT_VI_BASE_OFST 4 9474 9475 /* MC_CMD_ALLOC_VIS_EXT_OUT msgresponse */ 9476 #define MC_CMD_ALLOC_VIS_EXT_OUT_LEN 12 9477 /* The number of VIs allocated on this function */ 9478 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_COUNT_OFST 0 9479 /* The base absolute VI number allocated to this function. Required to 9480 * correctly interpret wakeup events. 9481 */ 9482 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_BASE_OFST 4 9483 /* Function's port vi_shift value (always 0 on Huntington) */ 9484 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_SHIFT_OFST 8 9485 9486 9487 /***********************************/ 9488 /* MC_CMD_FREE_VIS 9489 * Free VIs for current PCI function. Any linked PIO buffers will be unlinked, 9490 * but not freed. 9491 */ 9492 #define MC_CMD_FREE_VIS 0x8c 9493 #undef MC_CMD_0x8c_PRIVILEGE_CTG 9494 9495 #define MC_CMD_0x8c_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9496 9497 /* MC_CMD_FREE_VIS_IN msgrequest */ 9498 #define MC_CMD_FREE_VIS_IN_LEN 0 9499 9500 /* MC_CMD_FREE_VIS_OUT msgresponse */ 9501 #define MC_CMD_FREE_VIS_OUT_LEN 0 9502 9503 9504 /***********************************/ 9505 /* MC_CMD_GET_SRIOV_CFG 9506 * Get SRIOV config for this PF. 9507 */ 9508 #define MC_CMD_GET_SRIOV_CFG 0xba 9509 #undef MC_CMD_0xba_PRIVILEGE_CTG 9510 9511 #define MC_CMD_0xba_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9512 9513 /* MC_CMD_GET_SRIOV_CFG_IN msgrequest */ 9514 #define MC_CMD_GET_SRIOV_CFG_IN_LEN 0 9515 9516 /* MC_CMD_GET_SRIOV_CFG_OUT msgresponse */ 9517 #define MC_CMD_GET_SRIOV_CFG_OUT_LEN 20 9518 /* Number of VFs currently enabled. */ 9519 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_CURRENT_OFST 0 9520 /* Max number of VFs before sriov stride and offset may need to be changed. */ 9521 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_MAX_OFST 4 9522 #define MC_CMD_GET_SRIOV_CFG_OUT_FLAGS_OFST 8 9523 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_LBN 0 9524 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_WIDTH 1 9525 /* RID offset of first VF from PF. */ 9526 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_OFFSET_OFST 12 9527 /* RID offset of each subsequent VF from the previous. */ 9528 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_STRIDE_OFST 16 9529 9530 9531 /***********************************/ 9532 /* MC_CMD_SET_SRIOV_CFG 9533 * Set SRIOV config for this PF. 9534 */ 9535 #define MC_CMD_SET_SRIOV_CFG 0xbb 9536 #undef MC_CMD_0xbb_PRIVILEGE_CTG 9537 9538 #define MC_CMD_0xbb_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9539 9540 /* MC_CMD_SET_SRIOV_CFG_IN msgrequest */ 9541 #define MC_CMD_SET_SRIOV_CFG_IN_LEN 20 9542 /* Number of VFs currently enabled. */ 9543 #define MC_CMD_SET_SRIOV_CFG_IN_VF_CURRENT_OFST 0 9544 /* Max number of VFs before sriov stride and offset may need to be changed. */ 9545 #define MC_CMD_SET_SRIOV_CFG_IN_VF_MAX_OFST 4 9546 #define MC_CMD_SET_SRIOV_CFG_IN_FLAGS_OFST 8 9547 #define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_LBN 0 9548 #define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_WIDTH 1 9549 /* RID offset of first VF from PF, or 0 for no change, or 9550 * MC_CMD_RESOURCE_INSTANCE_ANY to allow the system to allocate an offset. 9551 */ 9552 #define MC_CMD_SET_SRIOV_CFG_IN_VF_OFFSET_OFST 12 9553 /* RID offset of each subsequent VF from the previous, 0 for no change, or 9554 * MC_CMD_RESOURCE_INSTANCE_ANY to allow the system to allocate a stride. 9555 */ 9556 #define MC_CMD_SET_SRIOV_CFG_IN_VF_STRIDE_OFST 16 9557 9558 /* MC_CMD_SET_SRIOV_CFG_OUT msgresponse */ 9559 #define MC_CMD_SET_SRIOV_CFG_OUT_LEN 0 9560 9561 9562 /***********************************/ 9563 /* MC_CMD_GET_VI_ALLOC_INFO 9564 * Get information about number of VI's and base VI number allocated to this 9565 * function. 9566 */ 9567 #define MC_CMD_GET_VI_ALLOC_INFO 0x8d 9568 #undef MC_CMD_0x8d_PRIVILEGE_CTG 9569 9570 #define MC_CMD_0x8d_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9571 9572 /* MC_CMD_GET_VI_ALLOC_INFO_IN msgrequest */ 9573 #define MC_CMD_GET_VI_ALLOC_INFO_IN_LEN 0 9574 9575 /* MC_CMD_GET_VI_ALLOC_INFO_OUT msgresponse */ 9576 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_LEN 12 9577 /* The number of VIs allocated on this function */ 9578 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_COUNT_OFST 0 9579 /* The base absolute VI number allocated to this function. Required to 9580 * correctly interpret wakeup events. 9581 */ 9582 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_BASE_OFST 4 9583 /* Function's port vi_shift value (always 0 on Huntington) */ 9584 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_SHIFT_OFST 8 9585 9586 9587 /***********************************/ 9588 /* MC_CMD_DUMP_VI_STATE 9589 * For CmdClient use. Dump pertinent information on a specific absolute VI. 9590 */ 9591 #define MC_CMD_DUMP_VI_STATE 0x8e 9592 #undef MC_CMD_0x8e_PRIVILEGE_CTG 9593 9594 #define MC_CMD_0x8e_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9595 9596 /* MC_CMD_DUMP_VI_STATE_IN msgrequest */ 9597 #define MC_CMD_DUMP_VI_STATE_IN_LEN 4 9598 /* The VI number to query. */ 9599 #define MC_CMD_DUMP_VI_STATE_IN_VI_NUMBER_OFST 0 9600 9601 /* MC_CMD_DUMP_VI_STATE_OUT msgresponse */ 9602 #define MC_CMD_DUMP_VI_STATE_OUT_LEN 96 9603 /* The PF part of the function owning this VI. */ 9604 #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_OFST 0 9605 #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_LEN 2 9606 /* The VF part of the function owning this VI. */ 9607 #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_VF_OFST 2 9608 #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_VF_LEN 2 9609 /* Base of VIs allocated to this function. */ 9610 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_BASE_OFST 4 9611 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_BASE_LEN 2 9612 /* Count of VIs allocated to the owner function. */ 9613 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_COUNT_OFST 6 9614 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_COUNT_LEN 2 9615 /* Base interrupt vector allocated to this function. */ 9616 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_BASE_OFST 8 9617 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_BASE_LEN 2 9618 /* Number of interrupt vectors allocated to this function. */ 9619 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_COUNT_OFST 10 9620 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_COUNT_LEN 2 9621 /* Raw evq ptr table data. */ 9622 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_OFST 12 9623 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LEN 8 9624 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LO_OFST 12 9625 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_HI_OFST 16 9626 /* Raw evq timer table data. */ 9627 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_OFST 20 9628 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LEN 8 9629 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LO_OFST 20 9630 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_HI_OFST 24 9631 /* Combined metadata field. */ 9632 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_OFST 28 9633 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_LBN 0 9634 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_WIDTH 16 9635 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_LBN 16 9636 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_WIDTH 8 9637 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_LBN 24 9638 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_WIDTH 8 9639 /* TXDPCPU raw table data for queue. */ 9640 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_OFST 32 9641 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LEN 8 9642 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LO_OFST 32 9643 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_HI_OFST 36 9644 /* TXDPCPU raw table data for queue. */ 9645 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_OFST 40 9646 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LEN 8 9647 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LO_OFST 40 9648 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_HI_OFST 44 9649 /* TXDPCPU raw table data for queue. */ 9650 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_OFST 48 9651 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LEN 8 9652 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LO_OFST 48 9653 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_HI_OFST 52 9654 /* Combined metadata field. */ 9655 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_OFST 56 9656 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LEN 8 9657 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LO_OFST 56 9658 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_HI_OFST 60 9659 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_LBN 0 9660 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_WIDTH 16 9661 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_LBN 16 9662 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_WIDTH 8 9663 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_LBN 24 9664 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_WIDTH 8 9665 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_LBN 32 9666 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_WIDTH 8 9667 #define MC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_LBN 40 9668 #define MC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_WIDTH 24 9669 /* RXDPCPU raw table data for queue. */ 9670 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_OFST 64 9671 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LEN 8 9672 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LO_OFST 64 9673 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_HI_OFST 68 9674 /* RXDPCPU raw table data for queue. */ 9675 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_OFST 72 9676 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LEN 8 9677 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LO_OFST 72 9678 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_HI_OFST 76 9679 /* Reserved, currently 0. */ 9680 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_OFST 80 9681 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LEN 8 9682 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LO_OFST 80 9683 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_HI_OFST 84 9684 /* Combined metadata field. */ 9685 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_OFST 88 9686 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LEN 8 9687 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LO_OFST 88 9688 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_HI_OFST 92 9689 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_LBN 0 9690 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_WIDTH 16 9691 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_LBN 16 9692 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_WIDTH 8 9693 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_LBN 24 9694 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_WIDTH 8 9695 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_LBN 32 9696 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_WIDTH 8 9697 9698 9699 /***********************************/ 9700 /* MC_CMD_ALLOC_PIOBUF 9701 * Allocate a push I/O buffer for later use with a tx queue. 9702 */ 9703 #define MC_CMD_ALLOC_PIOBUF 0x8f 9704 #undef MC_CMD_0x8f_PRIVILEGE_CTG 9705 9706 #define MC_CMD_0x8f_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 9707 9708 /* MC_CMD_ALLOC_PIOBUF_IN msgrequest */ 9709 #define MC_CMD_ALLOC_PIOBUF_IN_LEN 0 9710 9711 /* MC_CMD_ALLOC_PIOBUF_OUT msgresponse */ 9712 #define MC_CMD_ALLOC_PIOBUF_OUT_LEN 4 9713 /* Handle for allocated push I/O buffer. */ 9714 #define MC_CMD_ALLOC_PIOBUF_OUT_PIOBUF_HANDLE_OFST 0 9715 9716 9717 /***********************************/ 9718 /* MC_CMD_FREE_PIOBUF 9719 * Free a push I/O buffer. 9720 */ 9721 #define MC_CMD_FREE_PIOBUF 0x90 9722 #undef MC_CMD_0x90_PRIVILEGE_CTG 9723 9724 #define MC_CMD_0x90_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 9725 9726 /* MC_CMD_FREE_PIOBUF_IN msgrequest */ 9727 #define MC_CMD_FREE_PIOBUF_IN_LEN 4 9728 /* Handle for allocated push I/O buffer. */ 9729 #define MC_CMD_FREE_PIOBUF_IN_PIOBUF_HANDLE_OFST 0 9730 9731 /* MC_CMD_FREE_PIOBUF_OUT msgresponse */ 9732 #define MC_CMD_FREE_PIOBUF_OUT_LEN 0 9733 9734 9735 /***********************************/ 9736 /* MC_CMD_GET_VI_TLP_PROCESSING 9737 * Get TLP steering and ordering information for a VI. 9738 */ 9739 #define MC_CMD_GET_VI_TLP_PROCESSING 0xb0 9740 #undef MC_CMD_0xb0_PRIVILEGE_CTG 9741 9742 #define MC_CMD_0xb0_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9743 9744 /* MC_CMD_GET_VI_TLP_PROCESSING_IN msgrequest */ 9745 #define MC_CMD_GET_VI_TLP_PROCESSING_IN_LEN 4 9746 /* VI number to get information for. */ 9747 #define MC_CMD_GET_VI_TLP_PROCESSING_IN_INSTANCE_OFST 0 9748 9749 /* MC_CMD_GET_VI_TLP_PROCESSING_OUT msgresponse */ 9750 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_LEN 4 9751 /* Transaction processing steering hint 1 for use with the Rx Queue. */ 9752 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG1_RX_OFST 0 9753 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG1_RX_LEN 1 9754 /* Transaction processing steering hint 2 for use with the Ev Queue. */ 9755 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG2_EV_OFST 1 9756 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG2_EV_LEN 1 9757 /* Use Relaxed ordering model for TLPs on this VI. */ 9758 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_RELAXED_ORDERING_LBN 16 9759 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_RELAXED_ORDERING_WIDTH 1 9760 /* Use ID based ordering for TLPs on this VI. */ 9761 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_ID_BASED_ORDERING_LBN 17 9762 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_ID_BASED_ORDERING_WIDTH 1 9763 /* Set no snoop bit for TLPs on this VI. */ 9764 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_NO_SNOOP_LBN 18 9765 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_NO_SNOOP_WIDTH 1 9766 /* Enable TPH for TLPs on this VI. */ 9767 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_ON_LBN 19 9768 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_ON_WIDTH 1 9769 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_DATA_OFST 0 9770 9771 9772 /***********************************/ 9773 /* MC_CMD_SET_VI_TLP_PROCESSING 9774 * Set TLP steering and ordering information for a VI. 9775 */ 9776 #define MC_CMD_SET_VI_TLP_PROCESSING 0xb1 9777 #undef MC_CMD_0xb1_PRIVILEGE_CTG 9778 9779 #define MC_CMD_0xb1_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9780 9781 /* MC_CMD_SET_VI_TLP_PROCESSING_IN msgrequest */ 9782 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_LEN 8 9783 /* VI number to set information for. */ 9784 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_INSTANCE_OFST 0 9785 /* Transaction processing steering hint 1 for use with the Rx Queue. */ 9786 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG1_RX_OFST 4 9787 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG1_RX_LEN 1 9788 /* Transaction processing steering hint 2 for use with the Ev Queue. */ 9789 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG2_EV_OFST 5 9790 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG2_EV_LEN 1 9791 /* Use Relaxed ordering model for TLPs on this VI. */ 9792 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_RELAXED_ORDERING_LBN 48 9793 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_RELAXED_ORDERING_WIDTH 1 9794 /* Use ID based ordering for TLPs on this VI. */ 9795 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_ID_BASED_ORDERING_LBN 49 9796 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_ID_BASED_ORDERING_WIDTH 1 9797 /* Set the no snoop bit for TLPs on this VI. */ 9798 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_NO_SNOOP_LBN 50 9799 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_NO_SNOOP_WIDTH 1 9800 /* Enable TPH for TLPs on this VI. */ 9801 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_ON_LBN 51 9802 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_ON_WIDTH 1 9803 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_DATA_OFST 4 9804 9805 /* MC_CMD_SET_VI_TLP_PROCESSING_OUT msgresponse */ 9806 #define MC_CMD_SET_VI_TLP_PROCESSING_OUT_LEN 0 9807 9808 9809 /***********************************/ 9810 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS 9811 * Get global PCIe steering and transaction processing configuration. 9812 */ 9813 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS 0xbc 9814 #undef MC_CMD_0xbc_PRIVILEGE_CTG 9815 9816 #define MC_CMD_0xbc_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9817 9818 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN msgrequest */ 9819 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_LEN 4 9820 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_OFST 0 9821 /* enum: MISC. */ 9822 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_MISC 0x0 9823 /* enum: IDO. */ 9824 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_IDO 0x1 9825 /* enum: RO. */ 9826 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_RO 0x2 9827 /* enum: TPH Type. */ 9828 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_TPH_TYPE 0x3 9829 9830 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT msgresponse */ 9831 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_LEN 8 9832 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_GLOBAL_CATEGORY_OFST 0 9833 /* Enum values, see field(s): */ 9834 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN/TLP_GLOBAL_CATEGORY */ 9835 /* Amalgamated TLP info word. */ 9836 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_WORD_OFST 4 9837 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_LBN 0 9838 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_WIDTH 1 9839 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_LBN 1 9840 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_WIDTH 31 9841 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_LBN 0 9842 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_WIDTH 1 9843 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_LBN 1 9844 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_WIDTH 1 9845 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_EV_EN_LBN 2 9846 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_EV_EN_WIDTH 1 9847 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_LBN 3 9848 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_WIDTH 1 9849 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_LBN 4 9850 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_WIDTH 28 9851 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_LBN 0 9852 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_WIDTH 1 9853 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_LBN 1 9854 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_WIDTH 1 9855 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_LBN 2 9856 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_WIDTH 1 9857 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_LBN 3 9858 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_WIDTH 29 9859 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_LBN 0 9860 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_WIDTH 2 9861 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_DL_LBN 2 9862 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_DL_WIDTH 2 9863 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_LBN 4 9864 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_WIDTH 2 9865 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_EV_LBN 6 9866 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_EV_WIDTH 2 9867 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_LBN 8 9868 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_WIDTH 2 9869 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_LBN 9 9870 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_WIDTH 23 9871 9872 9873 /***********************************/ 9874 /* MC_CMD_SET_TLP_PROCESSING_GLOBALS 9875 * Set global PCIe steering and transaction processing configuration. 9876 */ 9877 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS 0xbd 9878 #undef MC_CMD_0xbd_PRIVILEGE_CTG 9879 9880 #define MC_CMD_0xbd_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9881 9882 /* MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN msgrequest */ 9883 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_LEN 8 9884 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_OFST 0 9885 /* Enum values, see field(s): */ 9886 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS/MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN/TLP_GLOBAL_CATEGORY */ 9887 /* Amalgamated TLP info word. */ 9888 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_WORD_OFST 4 9889 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_LBN 0 9890 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_WIDTH 1 9891 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_LBN 0 9892 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_WIDTH 1 9893 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_LBN 1 9894 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_WIDTH 1 9895 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_EV_EN_LBN 2 9896 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_EV_EN_WIDTH 1 9897 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_RX_EN_LBN 3 9898 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_RX_EN_WIDTH 1 9899 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_LBN 0 9900 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_WIDTH 1 9901 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_LBN 1 9902 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_WIDTH 1 9903 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_DL_EN_LBN 2 9904 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_DL_EN_WIDTH 1 9905 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_LBN 0 9906 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_WIDTH 2 9907 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_DL_LBN 2 9908 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_DL_WIDTH 2 9909 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_LBN 4 9910 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_WIDTH 2 9911 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_EV_LBN 6 9912 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_EV_WIDTH 2 9913 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_LBN 8 9914 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_WIDTH 2 9915 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_LBN 10 9916 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_WIDTH 22 9917 9918 /* MC_CMD_SET_TLP_PROCESSING_GLOBALS_OUT msgresponse */ 9919 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_OUT_LEN 0 9920 9921 9922 /***********************************/ 9923 /* MC_CMD_SATELLITE_DOWNLOAD 9924 * Download a new set of images to the satellite CPUs from the host. 9925 */ 9926 #define MC_CMD_SATELLITE_DOWNLOAD 0x91 9927 #undef MC_CMD_0x91_PRIVILEGE_CTG 9928 9929 #define MC_CMD_0x91_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9930 9931 /* MC_CMD_SATELLITE_DOWNLOAD_IN msgrequest: The reset requirements for the CPUs 9932 * are subtle, and so downloads must proceed in a number of phases. 9933 * 9934 * 1) PHASE_RESET with a target of TARGET_ALL and chunk ID/length of 0. 9935 * 9936 * 2) PHASE_IMEMS for each of the IMEM targets (target IDs 0-11). Each download 9937 * may consist of multiple chunks. The final chunk (with CHUNK_ID_LAST) should 9938 * be a checksum (a simple 32-bit sum) of the transferred data. An individual 9939 * download may be aborted using CHUNK_ID_ABORT. 9940 * 9941 * 3) PHASE_VECTORS for each of the vector table targets (target IDs 12-15), 9942 * similar to PHASE_IMEMS. 9943 * 9944 * 4) PHASE_READY with a target of TARGET_ALL and chunk ID/length of 0. 9945 * 9946 * After any error (a requested abort is not considered to be an error) the 9947 * sequence must be restarted from PHASE_RESET. 9948 */ 9949 #define MC_CMD_SATELLITE_DOWNLOAD_IN_LENMIN 20 9950 #define MC_CMD_SATELLITE_DOWNLOAD_IN_LENMAX 252 9951 #define MC_CMD_SATELLITE_DOWNLOAD_IN_LEN(num) (16+4*(num)) 9952 /* Download phase. (Note: the IDLE phase is used internally and is never valid 9953 * in a command from the host.) 9954 */ 9955 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_OFST 0 9956 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_IDLE 0x0 /* enum */ 9957 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_RESET 0x1 /* enum */ 9958 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_IMEMS 0x2 /* enum */ 9959 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_VECTORS 0x3 /* enum */ 9960 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_READY 0x4 /* enum */ 9961 /* Target for download. (These match the blob numbers defined in 9962 * mc_flash_layout.h.) 9963 */ 9964 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_OFST 4 9965 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 9966 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_TEXT 0x0 9967 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 9968 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_TEXT 0x1 9969 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 9970 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDP_TEXT 0x2 9971 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 9972 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDP_TEXT 0x3 9973 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 9974 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_LUT 0x4 9975 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 9976 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_LUT_CFG 0x5 9977 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 9978 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_LUT 0x6 9979 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 9980 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_LUT_CFG 0x7 9981 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 9982 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_PGM 0x8 9983 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 9984 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_SL_PGM 0x9 9985 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 9986 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_PGM 0xa 9987 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 9988 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_SL_PGM 0xb 9989 /* enum: Valid in phase 3 (PHASE_VECTORS) only */ 9990 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_VTBL0 0xc 9991 /* enum: Valid in phase 3 (PHASE_VECTORS) only */ 9992 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_VTBL0 0xd 9993 /* enum: Valid in phase 3 (PHASE_VECTORS) only */ 9994 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_VTBL1 0xe 9995 /* enum: Valid in phase 3 (PHASE_VECTORS) only */ 9996 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_VTBL1 0xf 9997 /* enum: Valid in phases 1 (PHASE_RESET) and 4 (PHASE_READY) only */ 9998 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_ALL 0xffffffff 9999 /* Chunk ID, or CHUNK_ID_LAST or CHUNK_ID_ABORT */ 10000 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_OFST 8 10001 /* enum: Last chunk, containing checksum rather than data */ 10002 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_LAST 0xffffffff 10003 /* enum: Abort download of this item */ 10004 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_ABORT 0xfffffffe 10005 /* Length of this chunk in bytes */ 10006 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_LEN_OFST 12 10007 /* Data for this chunk */ 10008 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_OFST 16 10009 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_LEN 4 10010 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_MINNUM 1 10011 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_MAXNUM 59 10012 10013 /* MC_CMD_SATELLITE_DOWNLOAD_OUT msgresponse */ 10014 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_LEN 8 10015 /* Same as MC_CMD_ERR field, but included as 0 in success cases */ 10016 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_RESULT_OFST 0 10017 /* Extra status information */ 10018 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_INFO_OFST 4 10019 /* enum: Code download OK, completed. */ 10020 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_COMPLETE 0x0 10021 /* enum: Code download aborted as requested. */ 10022 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_ABORTED 0x1 10023 /* enum: Code download OK so far, send next chunk. */ 10024 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_NEXT_CHUNK 0x2 10025 /* enum: Download phases out of sequence */ 10026 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_PHASE 0x100 10027 /* enum: Bad target for this phase */ 10028 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_TARGET 0x101 10029 /* enum: Chunk ID out of sequence */ 10030 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHUNK_ID 0x200 10031 /* enum: Chunk length zero or too large */ 10032 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHUNK_LEN 0x201 10033 /* enum: Checksum was incorrect */ 10034 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHECKSUM 0x300 10035 10036 10037 /***********************************/ 10038 /* MC_CMD_GET_CAPABILITIES 10039 * Get device capabilities. 10040 * 10041 * This is supplementary to the MC_CMD_GET_BOARD_CFG command, and intended to 10042 * reference inherent device capabilities as opposed to current NVRAM config. 10043 */ 10044 #define MC_CMD_GET_CAPABILITIES 0xbe 10045 #undef MC_CMD_0xbe_PRIVILEGE_CTG 10046 10047 #define MC_CMD_0xbe_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10048 10049 /* MC_CMD_GET_CAPABILITIES_IN msgrequest */ 10050 #define MC_CMD_GET_CAPABILITIES_IN_LEN 0 10051 10052 /* MC_CMD_GET_CAPABILITIES_OUT msgresponse */ 10053 #define MC_CMD_GET_CAPABILITIES_OUT_LEN 20 10054 /* First word of flags. */ 10055 #define MC_CMD_GET_CAPABILITIES_OUT_FLAGS1_OFST 0 10056 #define MC_CMD_GET_CAPABILITIES_OUT_VPORT_RECONFIGURE_LBN 3 10057 #define MC_CMD_GET_CAPABILITIES_OUT_VPORT_RECONFIGURE_WIDTH 1 10058 #define MC_CMD_GET_CAPABILITIES_OUT_TX_STRIPING_LBN 4 10059 #define MC_CMD_GET_CAPABILITIES_OUT_TX_STRIPING_WIDTH 1 10060 #define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_LBN 5 10061 #define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_WIDTH 1 10062 #define MC_CMD_GET_CAPABILITIES_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6 10063 #define MC_CMD_GET_CAPABILITIES_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1 10064 #define MC_CMD_GET_CAPABILITIES_OUT_DRV_ATTACH_PREBOOT_LBN 7 10065 #define MC_CMD_GET_CAPABILITIES_OUT_DRV_ATTACH_PREBOOT_WIDTH 1 10066 #define MC_CMD_GET_CAPABILITIES_OUT_RX_FORCE_EVENT_MERGING_LBN 8 10067 #define MC_CMD_GET_CAPABILITIES_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1 10068 #define MC_CMD_GET_CAPABILITIES_OUT_SET_MAC_ENHANCED_LBN 9 10069 #define MC_CMD_GET_CAPABILITIES_OUT_SET_MAC_ENHANCED_WIDTH 1 10070 #define MC_CMD_GET_CAPABILITIES_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10 10071 #define MC_CMD_GET_CAPABILITIES_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1 10072 #define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11 10073 #define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1 10074 #define MC_CMD_GET_CAPABILITIES_OUT_TX_MAC_SECURITY_FILTERING_LBN 12 10075 #define MC_CMD_GET_CAPABILITIES_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1 10076 #define MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_LBN 13 10077 #define MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_WIDTH 1 10078 #define MC_CMD_GET_CAPABILITIES_OUT_QBB_LBN 14 10079 #define MC_CMD_GET_CAPABILITIES_OUT_QBB_WIDTH 1 10080 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15 10081 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1 10082 #define MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_LBN 16 10083 #define MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_WIDTH 1 10084 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_LBN 17 10085 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_WIDTH 1 10086 #define MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_LBN 18 10087 #define MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_WIDTH 1 10088 #define MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_LBN 19 10089 #define MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_WIDTH 1 10090 #define MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_LBN 20 10091 #define MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_WIDTH 1 10092 #define MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN 21 10093 #define MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_WIDTH 1 10094 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_LBN 22 10095 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_WIDTH 1 10096 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN 23 10097 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_WIDTH 1 10098 #define MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_LBN 24 10099 #define MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_WIDTH 1 10100 #define MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN 25 10101 #define MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_WIDTH 1 10102 #define MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_LBN 26 10103 #define MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_WIDTH 1 10104 #define MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN 27 10105 #define MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1 10106 #define MC_CMD_GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER_LBN 28 10107 #define MC_CMD_GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER_WIDTH 1 10108 #define MC_CMD_GET_CAPABILITIES_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29 10109 #define MC_CMD_GET_CAPABILITIES_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1 10110 #define MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN 30 10111 #define MC_CMD_GET_CAPABILITIES_OUT_EVB_WIDTH 1 10112 #define MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN 31 10113 #define MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_WIDTH 1 10114 /* RxDPCPU firmware id. */ 10115 #define MC_CMD_GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID_OFST 4 10116 #define MC_CMD_GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID_LEN 2 10117 /* enum: Standard RXDP firmware */ 10118 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP 0x0 10119 /* enum: Low latency RXDP firmware */ 10120 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_LOW_LATENCY 0x1 10121 /* enum: Packed stream RXDP firmware */ 10122 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_PACKED_STREAM 0x2 10123 /* enum: BIST RXDP firmware */ 10124 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_BIST 0x10a 10125 /* enum: RXDP Test firmware image 1 */ 10126 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101 10127 /* enum: RXDP Test firmware image 2 */ 10128 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102 10129 /* enum: RXDP Test firmware image 3 */ 10130 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103 10131 /* enum: RXDP Test firmware image 4 */ 10132 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104 10133 /* enum: RXDP Test firmware image 5 */ 10134 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_BACKPRESSURE 0x105 10135 /* enum: RXDP Test firmware image 6 */ 10136 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106 10137 /* enum: RXDP Test firmware image 7 */ 10138 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107 10139 /* enum: RXDP Test firmware image 8 */ 10140 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_DISABLE_DL 0x108 10141 /* enum: RXDP Test firmware image 9 */ 10142 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b 10143 /* TxDPCPU firmware id. */ 10144 #define MC_CMD_GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID_OFST 6 10145 #define MC_CMD_GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID_LEN 2 10146 /* enum: Standard TXDP firmware */ 10147 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP 0x0 10148 /* enum: Low latency TXDP firmware */ 10149 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_LOW_LATENCY 0x1 10150 /* enum: High packet rate TXDP firmware */ 10151 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_HIGH_PACKET_RATE 0x3 10152 /* enum: BIST TXDP firmware */ 10153 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_BIST 0x12d 10154 /* enum: TXDP Test firmware image 1 */ 10155 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_TSO_EDIT 0x101 10156 /* enum: TXDP Test firmware image 2 */ 10157 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102 10158 /* enum: TXDP CSR bus test firmware */ 10159 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_CSR 0x103 10160 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_OFST 8 10161 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_LEN 2 10162 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_LBN 0 10163 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_WIDTH 12 10164 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_LBN 12 10165 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4 10166 /* enum: reserved value - do not use (may indicate alternative interpretation 10167 * of REV field in future) 10168 */ 10169 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_RESERVED 0x0 10170 /* enum: Trivial RX PD firmware for early Huntington development (Huntington 10171 * development only) 10172 */ 10173 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1 10174 /* enum: RX PD firmware with approximately Siena-compatible behaviour 10175 * (Huntington development only) 10176 */ 10177 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2 10178 /* enum: Virtual switching (full feature) RX PD production firmware */ 10179 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_VSWITCH 0x3 10180 /* enum: siena_compat variant RX PD firmware using PM rather than MAC 10181 * (Huntington development only) 10182 */ 10183 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 10184 /* enum: Low latency RX PD production firmware */ 10185 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5 10186 /* enum: Packed stream RX PD production firmware */ 10187 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6 10188 /* enum: RX PD firmware handling layer 2 only for high packet rate performance 10189 * tests (Medford development only) 10190 */ 10191 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7 10192 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 10193 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 10194 /* enum: RX PD firmware parsing but not filtering network overlay tunnel 10195 * encapsulations (Medford development only) 10196 */ 10197 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf 10198 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_OFST 10 10199 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_LEN 2 10200 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_LBN 0 10201 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_WIDTH 12 10202 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_LBN 12 10203 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4 10204 /* enum: reserved value - do not use (may indicate alternative interpretation 10205 * of REV field in future) 10206 */ 10207 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_RESERVED 0x0 10208 /* enum: Trivial TX PD firmware for early Huntington development (Huntington 10209 * development only) 10210 */ 10211 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1 10212 /* enum: TX PD firmware with approximately Siena-compatible behaviour 10213 * (Huntington development only) 10214 */ 10215 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2 10216 /* enum: Virtual switching (full feature) TX PD production firmware */ 10217 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_VSWITCH 0x3 10218 /* enum: siena_compat variant TX PD firmware using PM rather than MAC 10219 * (Huntington development only) 10220 */ 10221 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 10222 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */ 10223 /* enum: TX PD firmware handling layer 2 only for high packet rate performance 10224 * tests (Medford development only) 10225 */ 10226 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7 10227 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 10228 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 10229 /* Hardware capabilities of NIC */ 10230 #define MC_CMD_GET_CAPABILITIES_OUT_HW_CAPABILITIES_OFST 12 10231 /* Licensed capabilities */ 10232 #define MC_CMD_GET_CAPABILITIES_OUT_LICENSE_CAPABILITIES_OFST 16 10233 10234 /* MC_CMD_GET_CAPABILITIES_V2_IN msgrequest */ 10235 #define MC_CMD_GET_CAPABILITIES_V2_IN_LEN 0 10236 10237 /* MC_CMD_GET_CAPABILITIES_V2_OUT msgresponse */ 10238 #define MC_CMD_GET_CAPABILITIES_V2_OUT_LEN 72 10239 /* First word of flags. */ 10240 #define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS1_OFST 0 10241 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VPORT_RECONFIGURE_LBN 3 10242 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VPORT_RECONFIGURE_WIDTH 1 10243 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_STRIPING_LBN 4 10244 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_STRIPING_WIDTH 1 10245 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_QUERY_LBN 5 10246 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_QUERY_WIDTH 1 10247 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6 10248 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1 10249 #define MC_CMD_GET_CAPABILITIES_V2_OUT_DRV_ATTACH_PREBOOT_LBN 7 10250 #define MC_CMD_GET_CAPABILITIES_V2_OUT_DRV_ATTACH_PREBOOT_WIDTH 1 10251 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_FORCE_EVENT_MERGING_LBN 8 10252 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1 10253 #define MC_CMD_GET_CAPABILITIES_V2_OUT_SET_MAC_ENHANCED_LBN 9 10254 #define MC_CMD_GET_CAPABILITIES_V2_OUT_SET_MAC_ENHANCED_WIDTH 1 10255 #define MC_CMD_GET_CAPABILITIES_V2_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10 10256 #define MC_CMD_GET_CAPABILITIES_V2_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1 10257 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11 10258 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1 10259 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_SECURITY_FILTERING_LBN 12 10260 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1 10261 #define MC_CMD_GET_CAPABILITIES_V2_OUT_ADDITIONAL_RSS_MODES_LBN 13 10262 #define MC_CMD_GET_CAPABILITIES_V2_OUT_ADDITIONAL_RSS_MODES_WIDTH 1 10263 #define MC_CMD_GET_CAPABILITIES_V2_OUT_QBB_LBN 14 10264 #define MC_CMD_GET_CAPABILITIES_V2_OUT_QBB_WIDTH 1 10265 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15 10266 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1 10267 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_RSS_LIMITED_LBN 16 10268 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_RSS_LIMITED_WIDTH 1 10269 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_LBN 17 10270 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_WIDTH 1 10271 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_INCLUDE_FCS_LBN 18 10272 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_INCLUDE_FCS_WIDTH 1 10273 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VLAN_INSERTION_LBN 19 10274 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VLAN_INSERTION_WIDTH 1 10275 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_VLAN_STRIPPING_LBN 20 10276 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_VLAN_STRIPPING_WIDTH 1 10277 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_LBN 21 10278 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_WIDTH 1 10279 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_0_LBN 22 10280 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_0_WIDTH 1 10281 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_14_LBN 23 10282 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_14_WIDTH 1 10283 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_TIMESTAMP_LBN 24 10284 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_TIMESTAMP_WIDTH 1 10285 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_BATCHING_LBN 25 10286 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_BATCHING_WIDTH 1 10287 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MCAST_FILTER_CHAINING_LBN 26 10288 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MCAST_FILTER_CHAINING_WIDTH 1 10289 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PM_AND_RXDP_COUNTERS_LBN 27 10290 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1 10291 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DISABLE_SCATTER_LBN 28 10292 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DISABLE_SCATTER_WIDTH 1 10293 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29 10294 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1 10295 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_LBN 30 10296 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_WIDTH 1 10297 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VXLAN_NVGRE_LBN 31 10298 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VXLAN_NVGRE_WIDTH 1 10299 /* RxDPCPU firmware id. */ 10300 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DPCPU_FW_ID_OFST 4 10301 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DPCPU_FW_ID_LEN 2 10302 /* enum: Standard RXDP firmware */ 10303 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP 0x0 10304 /* enum: Low latency RXDP firmware */ 10305 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_LOW_LATENCY 0x1 10306 /* enum: Packed stream RXDP firmware */ 10307 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_PACKED_STREAM 0x2 10308 /* enum: BIST RXDP firmware */ 10309 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_BIST 0x10a 10310 /* enum: RXDP Test firmware image 1 */ 10311 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101 10312 /* enum: RXDP Test firmware image 2 */ 10313 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102 10314 /* enum: RXDP Test firmware image 3 */ 10315 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103 10316 /* enum: RXDP Test firmware image 4 */ 10317 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104 10318 /* enum: RXDP Test firmware image 5 */ 10319 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_BACKPRESSURE 0x105 10320 /* enum: RXDP Test firmware image 6 */ 10321 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106 10322 /* enum: RXDP Test firmware image 7 */ 10323 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107 10324 /* enum: RXDP Test firmware image 8 */ 10325 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_DISABLE_DL 0x108 10326 /* enum: RXDP Test firmware image 9 */ 10327 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b 10328 /* TxDPCPU firmware id. */ 10329 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DPCPU_FW_ID_OFST 6 10330 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DPCPU_FW_ID_LEN 2 10331 /* enum: Standard TXDP firmware */ 10332 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP 0x0 10333 /* enum: Low latency TXDP firmware */ 10334 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_LOW_LATENCY 0x1 10335 /* enum: High packet rate TXDP firmware */ 10336 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_HIGH_PACKET_RATE 0x3 10337 /* enum: BIST TXDP firmware */ 10338 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_BIST 0x12d 10339 /* enum: TXDP Test firmware image 1 */ 10340 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_TSO_EDIT 0x101 10341 /* enum: TXDP Test firmware image 2 */ 10342 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102 10343 /* enum: TXDP CSR bus test firmware */ 10344 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_CSR 0x103 10345 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_OFST 8 10346 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_LEN 2 10347 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_REV_LBN 0 10348 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_REV_WIDTH 12 10349 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_TYPE_LBN 12 10350 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4 10351 /* enum: reserved value - do not use (may indicate alternative interpretation 10352 * of REV field in future) 10353 */ 10354 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_RESERVED 0x0 10355 /* enum: Trivial RX PD firmware for early Huntington development (Huntington 10356 * development only) 10357 */ 10358 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1 10359 /* enum: RX PD firmware with approximately Siena-compatible behaviour 10360 * (Huntington development only) 10361 */ 10362 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2 10363 /* enum: Virtual switching (full feature) RX PD production firmware */ 10364 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_VSWITCH 0x3 10365 /* enum: siena_compat variant RX PD firmware using PM rather than MAC 10366 * (Huntington development only) 10367 */ 10368 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 10369 /* enum: Low latency RX PD production firmware */ 10370 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5 10371 /* enum: Packed stream RX PD production firmware */ 10372 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6 10373 /* enum: RX PD firmware handling layer 2 only for high packet rate performance 10374 * tests (Medford development only) 10375 */ 10376 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7 10377 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 10378 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 10379 /* enum: RX PD firmware parsing but not filtering network overlay tunnel 10380 * encapsulations (Medford development only) 10381 */ 10382 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf 10383 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_OFST 10 10384 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_LEN 2 10385 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_REV_LBN 0 10386 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_REV_WIDTH 12 10387 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_TYPE_LBN 12 10388 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4 10389 /* enum: reserved value - do not use (may indicate alternative interpretation 10390 * of REV field in future) 10391 */ 10392 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_RESERVED 0x0 10393 /* enum: Trivial TX PD firmware for early Huntington development (Huntington 10394 * development only) 10395 */ 10396 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1 10397 /* enum: TX PD firmware with approximately Siena-compatible behaviour 10398 * (Huntington development only) 10399 */ 10400 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2 10401 /* enum: Virtual switching (full feature) TX PD production firmware */ 10402 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_VSWITCH 0x3 10403 /* enum: siena_compat variant TX PD firmware using PM rather than MAC 10404 * (Huntington development only) 10405 */ 10406 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 10407 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */ 10408 /* enum: TX PD firmware handling layer 2 only for high packet rate performance 10409 * tests (Medford development only) 10410 */ 10411 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7 10412 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 10413 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 10414 /* Hardware capabilities of NIC */ 10415 #define MC_CMD_GET_CAPABILITIES_V2_OUT_HW_CAPABILITIES_OFST 12 10416 /* Licensed capabilities */ 10417 #define MC_CMD_GET_CAPABILITIES_V2_OUT_LICENSE_CAPABILITIES_OFST 16 10418 /* Second word of flags. Not present on older firmware (check the length). */ 10419 #define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS2_OFST 20 10420 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN 0 10421 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_WIDTH 1 10422 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_ENCAP_LBN 1 10423 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_ENCAP_WIDTH 1 10424 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVQ_TIMER_CTRL_LBN 2 10425 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVQ_TIMER_CTRL_WIDTH 1 10426 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVENT_CUT_THROUGH_LBN 3 10427 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVENT_CUT_THROUGH_WIDTH 1 10428 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_CUT_THROUGH_LBN 4 10429 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_CUT_THROUGH_WIDTH 1 10430 /* Number of FATSOv2 contexts per datapath supported by this NIC. Not present 10431 * on older firmware (check the length). 10432 */ 10433 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24 10434 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2 10435 /* One byte per PF containing the number of the external port assigned to this 10436 * PF, indexed by PF number. Special values indicate that a PF is either not 10437 * present or not assigned. 10438 */ 10439 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26 10440 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1 10441 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16 10442 /* enum: The caller is not permitted to access information on this PF. */ 10443 #define MC_CMD_GET_CAPABILITIES_V2_OUT_ACCESS_NOT_PERMITTED 0xff 10444 /* enum: PF does not exist. */ 10445 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_PRESENT 0xfe 10446 /* enum: PF does exist but is not assigned to any external port. */ 10447 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_ASSIGNED 0xfd 10448 /* enum: This value indicates that PF is assigned, but it cannot be expressed 10449 * in this field. It is intended for a possible future situation where a more 10450 * complex scheme of PFs to ports mapping is being used. The future driver 10451 * should look for a new field supporting the new scheme. The current/old 10452 * driver should treat this value as PF_NOT_ASSIGNED. 10453 */ 10454 #define MC_CMD_GET_CAPABILITIES_V2_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc 10455 /* One byte per PF containing the number of its VFs, indexed by PF number. A 10456 * special value indicates that a PF is not present. 10457 */ 10458 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VFS_PER_PF_OFST 42 10459 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VFS_PER_PF_LEN 1 10460 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VFS_PER_PF_NUM 16 10461 /* enum: The caller is not permitted to access information on this PF. */ 10462 /* MC_CMD_GET_CAPABILITIES_V2_OUT_ACCESS_NOT_PERMITTED 0xff */ 10463 /* enum: PF does not exist. */ 10464 /* MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_PRESENT 0xfe */ 10465 /* Number of VIs available for each external port */ 10466 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_OFST 58 10467 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_LEN 2 10468 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_NUM 4 10469 /* Size of RX descriptor cache expressed as binary logarithm The actual size 10470 * equals (2 ^ RX_DESC_CACHE_SIZE) 10471 */ 10472 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DESC_CACHE_SIZE_OFST 66 10473 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DESC_CACHE_SIZE_LEN 1 10474 /* Size of TX descriptor cache expressed as binary logarithm The actual size 10475 * equals (2 ^ TX_DESC_CACHE_SIZE) 10476 */ 10477 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DESC_CACHE_SIZE_OFST 67 10478 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DESC_CACHE_SIZE_LEN 1 10479 /* Total number of available PIO buffers */ 10480 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_PIO_BUFFS_OFST 68 10481 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_PIO_BUFFS_LEN 2 10482 /* Size of a single PIO buffer */ 10483 #define MC_CMD_GET_CAPABILITIES_V2_OUT_SIZE_PIO_BUFF_OFST 70 10484 #define MC_CMD_GET_CAPABILITIES_V2_OUT_SIZE_PIO_BUFF_LEN 2 10485 10486 10487 /***********************************/ 10488 /* MC_CMD_V2_EXTN 10489 * Encapsulation for a v2 extended command 10490 */ 10491 #define MC_CMD_V2_EXTN 0x7f 10492 10493 /* MC_CMD_V2_EXTN_IN msgrequest */ 10494 #define MC_CMD_V2_EXTN_IN_LEN 4 10495 /* the extended command number */ 10496 #define MC_CMD_V2_EXTN_IN_EXTENDED_CMD_LBN 0 10497 #define MC_CMD_V2_EXTN_IN_EXTENDED_CMD_WIDTH 15 10498 #define MC_CMD_V2_EXTN_IN_UNUSED_LBN 15 10499 #define MC_CMD_V2_EXTN_IN_UNUSED_WIDTH 1 10500 /* the actual length of the encapsulated command (which is not in the v1 10501 * header) 10502 */ 10503 #define MC_CMD_V2_EXTN_IN_ACTUAL_LEN_LBN 16 10504 #define MC_CMD_V2_EXTN_IN_ACTUAL_LEN_WIDTH 10 10505 #define MC_CMD_V2_EXTN_IN_UNUSED2_LBN 26 10506 #define MC_CMD_V2_EXTN_IN_UNUSED2_WIDTH 6 10507 10508 10509 /***********************************/ 10510 /* MC_CMD_TCM_BUCKET_ALLOC 10511 * Allocate a pacer bucket (for qau rp or a snapper test) 10512 */ 10513 #define MC_CMD_TCM_BUCKET_ALLOC 0xb2 10514 #undef MC_CMD_0xb2_PRIVILEGE_CTG 10515 10516 #define MC_CMD_0xb2_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10517 10518 /* MC_CMD_TCM_BUCKET_ALLOC_IN msgrequest */ 10519 #define MC_CMD_TCM_BUCKET_ALLOC_IN_LEN 0 10520 10521 /* MC_CMD_TCM_BUCKET_ALLOC_OUT msgresponse */ 10522 #define MC_CMD_TCM_BUCKET_ALLOC_OUT_LEN 4 10523 /* the bucket id */ 10524 #define MC_CMD_TCM_BUCKET_ALLOC_OUT_BUCKET_OFST 0 10525 10526 10527 /***********************************/ 10528 /* MC_CMD_TCM_BUCKET_FREE 10529 * Free a pacer bucket 10530 */ 10531 #define MC_CMD_TCM_BUCKET_FREE 0xb3 10532 #undef MC_CMD_0xb3_PRIVILEGE_CTG 10533 10534 #define MC_CMD_0xb3_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10535 10536 /* MC_CMD_TCM_BUCKET_FREE_IN msgrequest */ 10537 #define MC_CMD_TCM_BUCKET_FREE_IN_LEN 4 10538 /* the bucket id */ 10539 #define MC_CMD_TCM_BUCKET_FREE_IN_BUCKET_OFST 0 10540 10541 /* MC_CMD_TCM_BUCKET_FREE_OUT msgresponse */ 10542 #define MC_CMD_TCM_BUCKET_FREE_OUT_LEN 0 10543 10544 10545 /***********************************/ 10546 /* MC_CMD_TCM_BUCKET_INIT 10547 * Initialise pacer bucket with a given rate 10548 */ 10549 #define MC_CMD_TCM_BUCKET_INIT 0xb4 10550 #undef MC_CMD_0xb4_PRIVILEGE_CTG 10551 10552 #define MC_CMD_0xb4_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10553 10554 /* MC_CMD_TCM_BUCKET_INIT_IN msgrequest */ 10555 #define MC_CMD_TCM_BUCKET_INIT_IN_LEN 8 10556 /* the bucket id */ 10557 #define MC_CMD_TCM_BUCKET_INIT_IN_BUCKET_OFST 0 10558 /* the rate in mbps */ 10559 #define MC_CMD_TCM_BUCKET_INIT_IN_RATE_OFST 4 10560 10561 /* MC_CMD_TCM_BUCKET_INIT_EXT_IN msgrequest */ 10562 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_LEN 12 10563 /* the bucket id */ 10564 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_BUCKET_OFST 0 10565 /* the rate in mbps */ 10566 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_RATE_OFST 4 10567 /* the desired maximum fill level */ 10568 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_MAX_FILL_OFST 8 10569 10570 /* MC_CMD_TCM_BUCKET_INIT_OUT msgresponse */ 10571 #define MC_CMD_TCM_BUCKET_INIT_OUT_LEN 0 10572 10573 10574 /***********************************/ 10575 /* MC_CMD_TCM_TXQ_INIT 10576 * Initialise txq in pacer with given options or set options 10577 */ 10578 #define MC_CMD_TCM_TXQ_INIT 0xb5 10579 #undef MC_CMD_0xb5_PRIVILEGE_CTG 10580 10581 #define MC_CMD_0xb5_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10582 10583 /* MC_CMD_TCM_TXQ_INIT_IN msgrequest */ 10584 #define MC_CMD_TCM_TXQ_INIT_IN_LEN 28 10585 /* the txq id */ 10586 #define MC_CMD_TCM_TXQ_INIT_IN_QID_OFST 0 10587 /* the static priority associated with the txq */ 10588 #define MC_CMD_TCM_TXQ_INIT_IN_LABEL_OFST 4 10589 /* bitmask of the priority queues this txq is inserted into when inserted. */ 10590 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAGS_OFST 8 10591 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_GUARANTEED_LBN 0 10592 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_GUARANTEED_WIDTH 1 10593 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_NORMAL_LBN 1 10594 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_NORMAL_WIDTH 1 10595 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_LOW_LBN 2 10596 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_LOW_WIDTH 1 10597 /* the reaction point (RP) bucket */ 10598 #define MC_CMD_TCM_TXQ_INIT_IN_RP_BKT_OFST 12 10599 /* an already reserved bucket (typically set to bucket associated with outer 10600 * vswitch) 10601 */ 10602 #define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT1_OFST 16 10603 /* an already reserved bucket (typically set to bucket associated with inner 10604 * vswitch) 10605 */ 10606 #define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT2_OFST 20 10607 /* the min bucket (typically for ETS/minimum bandwidth) */ 10608 #define MC_CMD_TCM_TXQ_INIT_IN_MIN_BKT_OFST 24 10609 10610 /* MC_CMD_TCM_TXQ_INIT_EXT_IN msgrequest */ 10611 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_LEN 32 10612 /* the txq id */ 10613 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_QID_OFST 0 10614 /* the static priority associated with the txq */ 10615 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_NORMAL_OFST 4 10616 /* bitmask of the priority queues this txq is inserted into when inserted. */ 10617 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAGS_OFST 8 10618 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_GUARANTEED_LBN 0 10619 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_GUARANTEED_WIDTH 1 10620 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_NORMAL_LBN 1 10621 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_NORMAL_WIDTH 1 10622 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_LOW_LBN 2 10623 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_LOW_WIDTH 1 10624 /* the reaction point (RP) bucket */ 10625 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_RP_BKT_OFST 12 10626 /* an already reserved bucket (typically set to bucket associated with outer 10627 * vswitch) 10628 */ 10629 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT1_OFST 16 10630 /* an already reserved bucket (typically set to bucket associated with inner 10631 * vswitch) 10632 */ 10633 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT2_OFST 20 10634 /* the min bucket (typically for ETS/minimum bandwidth) */ 10635 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MIN_BKT_OFST 24 10636 /* the static priority associated with the txq */ 10637 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_GUARANTEED_OFST 28 10638 10639 /* MC_CMD_TCM_TXQ_INIT_OUT msgresponse */ 10640 #define MC_CMD_TCM_TXQ_INIT_OUT_LEN 0 10641 10642 10643 /***********************************/ 10644 /* MC_CMD_LINK_PIOBUF 10645 * Link a push I/O buffer to a TxQ 10646 */ 10647 #define MC_CMD_LINK_PIOBUF 0x92 10648 #undef MC_CMD_0x92_PRIVILEGE_CTG 10649 10650 #define MC_CMD_0x92_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 10651 10652 /* MC_CMD_LINK_PIOBUF_IN msgrequest */ 10653 #define MC_CMD_LINK_PIOBUF_IN_LEN 8 10654 /* Handle for allocated push I/O buffer. */ 10655 #define MC_CMD_LINK_PIOBUF_IN_PIOBUF_HANDLE_OFST 0 10656 /* Function Local Instance (VI) number. */ 10657 #define MC_CMD_LINK_PIOBUF_IN_TXQ_INSTANCE_OFST 4 10658 10659 /* MC_CMD_LINK_PIOBUF_OUT msgresponse */ 10660 #define MC_CMD_LINK_PIOBUF_OUT_LEN 0 10661 10662 10663 /***********************************/ 10664 /* MC_CMD_UNLINK_PIOBUF 10665 * Unlink a push I/O buffer from a TxQ 10666 */ 10667 #define MC_CMD_UNLINK_PIOBUF 0x93 10668 #undef MC_CMD_0x93_PRIVILEGE_CTG 10669 10670 #define MC_CMD_0x93_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 10671 10672 /* MC_CMD_UNLINK_PIOBUF_IN msgrequest */ 10673 #define MC_CMD_UNLINK_PIOBUF_IN_LEN 4 10674 /* Function Local Instance (VI) number. */ 10675 #define MC_CMD_UNLINK_PIOBUF_IN_TXQ_INSTANCE_OFST 0 10676 10677 /* MC_CMD_UNLINK_PIOBUF_OUT msgresponse */ 10678 #define MC_CMD_UNLINK_PIOBUF_OUT_LEN 0 10679 10680 10681 /***********************************/ 10682 /* MC_CMD_VSWITCH_ALLOC 10683 * allocate and initialise a v-switch. 10684 */ 10685 #define MC_CMD_VSWITCH_ALLOC 0x94 10686 #undef MC_CMD_0x94_PRIVILEGE_CTG 10687 10688 #define MC_CMD_0x94_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10689 10690 /* MC_CMD_VSWITCH_ALLOC_IN msgrequest */ 10691 #define MC_CMD_VSWITCH_ALLOC_IN_LEN 16 10692 /* The port to connect to the v-switch's upstream port. */ 10693 #define MC_CMD_VSWITCH_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 10694 /* The type of v-switch to create. */ 10695 #define MC_CMD_VSWITCH_ALLOC_IN_TYPE_OFST 4 10696 /* enum: VLAN */ 10697 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VLAN 0x1 10698 /* enum: VEB */ 10699 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEB 0x2 10700 /* enum: VEPA (obsolete) */ 10701 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEPA 0x3 10702 /* enum: MUX */ 10703 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_MUX 0x4 10704 /* enum: Snapper specific; semantics TBD */ 10705 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_TEST 0x5 10706 /* Flags controlling v-port creation */ 10707 #define MC_CMD_VSWITCH_ALLOC_IN_FLAGS_OFST 8 10708 #define MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_LBN 0 10709 #define MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_WIDTH 1 10710 /* The number of VLAN tags to allow for attached v-ports. For VLAN aggregators, 10711 * this must be one or greated, and the attached v-ports must have exactly this 10712 * number of tags. For other v-switch types, this must be zero of greater, and 10713 * is an upper limit on the number of VLAN tags for attached v-ports. An error 10714 * will be returned if existing configuration means we can't support attached 10715 * v-ports with this number of tags. 10716 */ 10717 #define MC_CMD_VSWITCH_ALLOC_IN_NUM_VLAN_TAGS_OFST 12 10718 10719 /* MC_CMD_VSWITCH_ALLOC_OUT msgresponse */ 10720 #define MC_CMD_VSWITCH_ALLOC_OUT_LEN 0 10721 10722 10723 /***********************************/ 10724 /* MC_CMD_VSWITCH_FREE 10725 * de-allocate a v-switch. 10726 */ 10727 #define MC_CMD_VSWITCH_FREE 0x95 10728 #undef MC_CMD_0x95_PRIVILEGE_CTG 10729 10730 #define MC_CMD_0x95_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10731 10732 /* MC_CMD_VSWITCH_FREE_IN msgrequest */ 10733 #define MC_CMD_VSWITCH_FREE_IN_LEN 4 10734 /* The port to which the v-switch is connected. */ 10735 #define MC_CMD_VSWITCH_FREE_IN_UPSTREAM_PORT_ID_OFST 0 10736 10737 /* MC_CMD_VSWITCH_FREE_OUT msgresponse */ 10738 #define MC_CMD_VSWITCH_FREE_OUT_LEN 0 10739 10740 10741 /***********************************/ 10742 /* MC_CMD_VSWITCH_QUERY 10743 * read some config of v-switch. For now this command is an empty placeholder. 10744 * It may be used to check if a v-switch is connected to a given EVB port (if 10745 * not, then the command returns ENOENT). 10746 */ 10747 #define MC_CMD_VSWITCH_QUERY 0x63 10748 #undef MC_CMD_0x63_PRIVILEGE_CTG 10749 10750 #define MC_CMD_0x63_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10751 10752 /* MC_CMD_VSWITCH_QUERY_IN msgrequest */ 10753 #define MC_CMD_VSWITCH_QUERY_IN_LEN 4 10754 /* The port to which the v-switch is connected. */ 10755 #define MC_CMD_VSWITCH_QUERY_IN_UPSTREAM_PORT_ID_OFST 0 10756 10757 /* MC_CMD_VSWITCH_QUERY_OUT msgresponse */ 10758 #define MC_CMD_VSWITCH_QUERY_OUT_LEN 0 10759 10760 10761 /***********************************/ 10762 /* MC_CMD_VPORT_ALLOC 10763 * allocate a v-port. 10764 */ 10765 #define MC_CMD_VPORT_ALLOC 0x96 10766 #undef MC_CMD_0x96_PRIVILEGE_CTG 10767 10768 #define MC_CMD_0x96_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10769 10770 /* MC_CMD_VPORT_ALLOC_IN msgrequest */ 10771 #define MC_CMD_VPORT_ALLOC_IN_LEN 20 10772 /* The port to which the v-switch is connected. */ 10773 #define MC_CMD_VPORT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 10774 /* The type of the new v-port. */ 10775 #define MC_CMD_VPORT_ALLOC_IN_TYPE_OFST 4 10776 /* enum: VLAN (obsolete) */ 10777 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VLAN 0x1 10778 /* enum: VEB (obsolete) */ 10779 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEB 0x2 10780 /* enum: VEPA (obsolete) */ 10781 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEPA 0x3 10782 /* enum: A normal v-port receives packets which match a specified MAC and/or 10783 * VLAN. 10784 */ 10785 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_NORMAL 0x4 10786 /* enum: An expansion v-port packets traffic which don't match any other 10787 * v-port. 10788 */ 10789 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_EXPANSION 0x5 10790 /* enum: An test v-port receives packets which match any filters installed by 10791 * its downstream components. 10792 */ 10793 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_TEST 0x6 10794 /* Flags controlling v-port creation */ 10795 #define MC_CMD_VPORT_ALLOC_IN_FLAGS_OFST 8 10796 #define MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_LBN 0 10797 #define MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_WIDTH 1 10798 #define MC_CMD_VPORT_ALLOC_IN_FLAG_VLAN_RESTRICT_LBN 1 10799 #define MC_CMD_VPORT_ALLOC_IN_FLAG_VLAN_RESTRICT_WIDTH 1 10800 /* The number of VLAN tags to insert/remove. An error will be returned if 10801 * incompatible with the number of VLAN tags specified for the upstream 10802 * v-switch. 10803 */ 10804 #define MC_CMD_VPORT_ALLOC_IN_NUM_VLAN_TAGS_OFST 12 10805 /* The actual VLAN tags to insert/remove */ 10806 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAGS_OFST 16 10807 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_LBN 0 10808 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_WIDTH 16 10809 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_LBN 16 10810 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_WIDTH 16 10811 10812 /* MC_CMD_VPORT_ALLOC_OUT msgresponse */ 10813 #define MC_CMD_VPORT_ALLOC_OUT_LEN 4 10814 /* The handle of the new v-port */ 10815 #define MC_CMD_VPORT_ALLOC_OUT_VPORT_ID_OFST 0 10816 10817 10818 /***********************************/ 10819 /* MC_CMD_VPORT_FREE 10820 * de-allocate a v-port. 10821 */ 10822 #define MC_CMD_VPORT_FREE 0x97 10823 #undef MC_CMD_0x97_PRIVILEGE_CTG 10824 10825 #define MC_CMD_0x97_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10826 10827 /* MC_CMD_VPORT_FREE_IN msgrequest */ 10828 #define MC_CMD_VPORT_FREE_IN_LEN 4 10829 /* The handle of the v-port */ 10830 #define MC_CMD_VPORT_FREE_IN_VPORT_ID_OFST 0 10831 10832 /* MC_CMD_VPORT_FREE_OUT msgresponse */ 10833 #define MC_CMD_VPORT_FREE_OUT_LEN 0 10834 10835 10836 /***********************************/ 10837 /* MC_CMD_VADAPTOR_ALLOC 10838 * allocate a v-adaptor. 10839 */ 10840 #define MC_CMD_VADAPTOR_ALLOC 0x98 10841 #undef MC_CMD_0x98_PRIVILEGE_CTG 10842 10843 #define MC_CMD_0x98_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10844 10845 /* MC_CMD_VADAPTOR_ALLOC_IN msgrequest */ 10846 #define MC_CMD_VADAPTOR_ALLOC_IN_LEN 30 10847 /* The port to connect to the v-adaptor's port. */ 10848 #define MC_CMD_VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 10849 /* Flags controlling v-adaptor creation */ 10850 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAGS_OFST 8 10851 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_LBN 0 10852 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_WIDTH 1 10853 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 1 10854 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1 10855 /* The number of VLAN tags to strip on receive */ 10856 #define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLANS_OFST 12 10857 /* The number of VLAN tags to transparently insert/remove. */ 10858 #define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLAN_TAGS_OFST 16 10859 /* The actual VLAN tags to insert/remove */ 10860 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAGS_OFST 20 10861 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_0_LBN 0 10862 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_0_WIDTH 16 10863 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_1_LBN 16 10864 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_1_WIDTH 16 10865 /* The MAC address to assign to this v-adaptor */ 10866 #define MC_CMD_VADAPTOR_ALLOC_IN_MACADDR_OFST 24 10867 #define MC_CMD_VADAPTOR_ALLOC_IN_MACADDR_LEN 6 10868 /* enum: Derive the MAC address from the upstream port */ 10869 #define MC_CMD_VADAPTOR_ALLOC_IN_AUTO_MAC 0x0 10870 10871 /* MC_CMD_VADAPTOR_ALLOC_OUT msgresponse */ 10872 #define MC_CMD_VADAPTOR_ALLOC_OUT_LEN 0 10873 10874 10875 /***********************************/ 10876 /* MC_CMD_VADAPTOR_FREE 10877 * de-allocate a v-adaptor. 10878 */ 10879 #define MC_CMD_VADAPTOR_FREE 0x99 10880 #undef MC_CMD_0x99_PRIVILEGE_CTG 10881 10882 #define MC_CMD_0x99_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10883 10884 /* MC_CMD_VADAPTOR_FREE_IN msgrequest */ 10885 #define MC_CMD_VADAPTOR_FREE_IN_LEN 4 10886 /* The port to which the v-adaptor is connected. */ 10887 #define MC_CMD_VADAPTOR_FREE_IN_UPSTREAM_PORT_ID_OFST 0 10888 10889 /* MC_CMD_VADAPTOR_FREE_OUT msgresponse */ 10890 #define MC_CMD_VADAPTOR_FREE_OUT_LEN 0 10891 10892 10893 /***********************************/ 10894 /* MC_CMD_VADAPTOR_SET_MAC 10895 * assign a new MAC address to a v-adaptor. 10896 */ 10897 #define MC_CMD_VADAPTOR_SET_MAC 0x5d 10898 #undef MC_CMD_0x5d_PRIVILEGE_CTG 10899 10900 #define MC_CMD_0x5d_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10901 10902 /* MC_CMD_VADAPTOR_SET_MAC_IN msgrequest */ 10903 #define MC_CMD_VADAPTOR_SET_MAC_IN_LEN 10 10904 /* The port to which the v-adaptor is connected. */ 10905 #define MC_CMD_VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID_OFST 0 10906 /* The new MAC address to assign to this v-adaptor */ 10907 #define MC_CMD_VADAPTOR_SET_MAC_IN_MACADDR_OFST 4 10908 #define MC_CMD_VADAPTOR_SET_MAC_IN_MACADDR_LEN 6 10909 10910 /* MC_CMD_VADAPTOR_SET_MAC_OUT msgresponse */ 10911 #define MC_CMD_VADAPTOR_SET_MAC_OUT_LEN 0 10912 10913 10914 /***********************************/ 10915 /* MC_CMD_VADAPTOR_GET_MAC 10916 * read the MAC address assigned to a v-adaptor. 10917 */ 10918 #define MC_CMD_VADAPTOR_GET_MAC 0x5e 10919 #undef MC_CMD_0x5e_PRIVILEGE_CTG 10920 10921 #define MC_CMD_0x5e_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10922 10923 /* MC_CMD_VADAPTOR_GET_MAC_IN msgrequest */ 10924 #define MC_CMD_VADAPTOR_GET_MAC_IN_LEN 4 10925 /* The port to which the v-adaptor is connected. */ 10926 #define MC_CMD_VADAPTOR_GET_MAC_IN_UPSTREAM_PORT_ID_OFST 0 10927 10928 /* MC_CMD_VADAPTOR_GET_MAC_OUT msgresponse */ 10929 #define MC_CMD_VADAPTOR_GET_MAC_OUT_LEN 6 10930 /* The MAC address assigned to this v-adaptor */ 10931 #define MC_CMD_VADAPTOR_GET_MAC_OUT_MACADDR_OFST 0 10932 #define MC_CMD_VADAPTOR_GET_MAC_OUT_MACADDR_LEN 6 10933 10934 10935 /***********************************/ 10936 /* MC_CMD_VADAPTOR_QUERY 10937 * read some config of v-adaptor. 10938 */ 10939 #define MC_CMD_VADAPTOR_QUERY 0x61 10940 #undef MC_CMD_0x61_PRIVILEGE_CTG 10941 10942 #define MC_CMD_0x61_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10943 10944 /* MC_CMD_VADAPTOR_QUERY_IN msgrequest */ 10945 #define MC_CMD_VADAPTOR_QUERY_IN_LEN 4 10946 /* The port to which the v-adaptor is connected. */ 10947 #define MC_CMD_VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID_OFST 0 10948 10949 /* MC_CMD_VADAPTOR_QUERY_OUT msgresponse */ 10950 #define MC_CMD_VADAPTOR_QUERY_OUT_LEN 12 10951 /* The EVB port flags as defined at MC_CMD_VPORT_ALLOC. */ 10952 #define MC_CMD_VADAPTOR_QUERY_OUT_PORT_FLAGS_OFST 0 10953 /* The v-adaptor flags as defined at MC_CMD_VADAPTOR_ALLOC. */ 10954 #define MC_CMD_VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS_OFST 4 10955 /* The number of VLAN tags that may still be added */ 10956 #define MC_CMD_VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_OFST 8 10957 10958 10959 /***********************************/ 10960 /* MC_CMD_EVB_PORT_ASSIGN 10961 * assign a port to a PCI function. 10962 */ 10963 #define MC_CMD_EVB_PORT_ASSIGN 0x9a 10964 #undef MC_CMD_0x9a_PRIVILEGE_CTG 10965 10966 #define MC_CMD_0x9a_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10967 10968 /* MC_CMD_EVB_PORT_ASSIGN_IN msgrequest */ 10969 #define MC_CMD_EVB_PORT_ASSIGN_IN_LEN 8 10970 /* The port to assign. */ 10971 #define MC_CMD_EVB_PORT_ASSIGN_IN_PORT_ID_OFST 0 10972 /* The target function to modify. */ 10973 #define MC_CMD_EVB_PORT_ASSIGN_IN_FUNCTION_OFST 4 10974 #define MC_CMD_EVB_PORT_ASSIGN_IN_PF_LBN 0 10975 #define MC_CMD_EVB_PORT_ASSIGN_IN_PF_WIDTH 16 10976 #define MC_CMD_EVB_PORT_ASSIGN_IN_VF_LBN 16 10977 #define MC_CMD_EVB_PORT_ASSIGN_IN_VF_WIDTH 16 10978 10979 /* MC_CMD_EVB_PORT_ASSIGN_OUT msgresponse */ 10980 #define MC_CMD_EVB_PORT_ASSIGN_OUT_LEN 0 10981 10982 10983 /***********************************/ 10984 /* MC_CMD_RDWR_A64_REGIONS 10985 * Assign the 64 bit region addresses. 10986 */ 10987 #define MC_CMD_RDWR_A64_REGIONS 0x9b 10988 #undef MC_CMD_0x9b_PRIVILEGE_CTG 10989 10990 #define MC_CMD_0x9b_PRIVILEGE_CTG SRIOV_CTG_ADMIN 10991 10992 /* MC_CMD_RDWR_A64_REGIONS_IN msgrequest */ 10993 #define MC_CMD_RDWR_A64_REGIONS_IN_LEN 17 10994 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION0_OFST 0 10995 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION1_OFST 4 10996 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION2_OFST 8 10997 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION3_OFST 12 10998 /* Write enable bits 0-3, set to write, clear to read. */ 10999 #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_LBN 128 11000 #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_WIDTH 4 11001 #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_BYTE_OFST 16 11002 #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_BYTE_LEN 1 11003 11004 /* MC_CMD_RDWR_A64_REGIONS_OUT msgresponse: This data always included 11005 * regardless of state of write bits in the request. 11006 */ 11007 #define MC_CMD_RDWR_A64_REGIONS_OUT_LEN 16 11008 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION0_OFST 0 11009 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION1_OFST 4 11010 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION2_OFST 8 11011 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION3_OFST 12 11012 11013 11014 /***********************************/ 11015 /* MC_CMD_ONLOAD_STACK_ALLOC 11016 * Allocate an Onload stack ID. 11017 */ 11018 #define MC_CMD_ONLOAD_STACK_ALLOC 0x9c 11019 #undef MC_CMD_0x9c_PRIVILEGE_CTG 11020 11021 #define MC_CMD_0x9c_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 11022 11023 /* MC_CMD_ONLOAD_STACK_ALLOC_IN msgrequest */ 11024 #define MC_CMD_ONLOAD_STACK_ALLOC_IN_LEN 4 11025 /* The handle of the owning upstream port */ 11026 #define MC_CMD_ONLOAD_STACK_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 11027 11028 /* MC_CMD_ONLOAD_STACK_ALLOC_OUT msgresponse */ 11029 #define MC_CMD_ONLOAD_STACK_ALLOC_OUT_LEN 4 11030 /* The handle of the new Onload stack */ 11031 #define MC_CMD_ONLOAD_STACK_ALLOC_OUT_ONLOAD_STACK_ID_OFST 0 11032 11033 11034 /***********************************/ 11035 /* MC_CMD_ONLOAD_STACK_FREE 11036 * Free an Onload stack ID. 11037 */ 11038 #define MC_CMD_ONLOAD_STACK_FREE 0x9d 11039 #undef MC_CMD_0x9d_PRIVILEGE_CTG 11040 11041 #define MC_CMD_0x9d_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 11042 11043 /* MC_CMD_ONLOAD_STACK_FREE_IN msgrequest */ 11044 #define MC_CMD_ONLOAD_STACK_FREE_IN_LEN 4 11045 /* The handle of the Onload stack */ 11046 #define MC_CMD_ONLOAD_STACK_FREE_IN_ONLOAD_STACK_ID_OFST 0 11047 11048 /* MC_CMD_ONLOAD_STACK_FREE_OUT msgresponse */ 11049 #define MC_CMD_ONLOAD_STACK_FREE_OUT_LEN 0 11050 11051 11052 /***********************************/ 11053 /* MC_CMD_RSS_CONTEXT_ALLOC 11054 * Allocate an RSS context. 11055 */ 11056 #define MC_CMD_RSS_CONTEXT_ALLOC 0x9e 11057 #undef MC_CMD_0x9e_PRIVILEGE_CTG 11058 11059 #define MC_CMD_0x9e_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11060 11061 /* MC_CMD_RSS_CONTEXT_ALLOC_IN msgrequest */ 11062 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN 12 11063 /* The handle of the owning upstream port */ 11064 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 11065 /* The type of context to allocate */ 11066 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_OFST 4 11067 /* enum: Allocate a context for exclusive use. The key and indirection table 11068 * must be explicitly configured. 11069 */ 11070 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE 0x0 11071 /* enum: Allocate a context for shared use; this will spread across a range of 11072 * queues, but the key and indirection table are pre-configured and may not be 11073 * changed. For this mode, NUM_QUEUES must 2, 4, 8, 16, 32 or 64. 11074 */ 11075 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED 0x1 11076 /* Number of queues spanned by this context, in the range 1-64; valid offsets 11077 * in the indirection table will be in the range 0 to NUM_QUEUES-1. 11078 */ 11079 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_NUM_QUEUES_OFST 8 11080 11081 /* MC_CMD_RSS_CONTEXT_ALLOC_OUT msgresponse */ 11082 #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN 4 11083 /* The handle of the new RSS context. This should be considered opaque to the 11084 * host, although a value of 0xFFFFFFFF is guaranteed never to be a valid 11085 * handle. 11086 */ 11087 #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_OFST 0 11088 /* enum: guaranteed invalid RSS context handle value */ 11089 #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_INVALID 0xffffffff 11090 11091 11092 /***********************************/ 11093 /* MC_CMD_RSS_CONTEXT_FREE 11094 * Free an RSS context. 11095 */ 11096 #define MC_CMD_RSS_CONTEXT_FREE 0x9f 11097 #undef MC_CMD_0x9f_PRIVILEGE_CTG 11098 11099 #define MC_CMD_0x9f_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11100 11101 /* MC_CMD_RSS_CONTEXT_FREE_IN msgrequest */ 11102 #define MC_CMD_RSS_CONTEXT_FREE_IN_LEN 4 11103 /* The handle of the RSS context */ 11104 #define MC_CMD_RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID_OFST 0 11105 11106 /* MC_CMD_RSS_CONTEXT_FREE_OUT msgresponse */ 11107 #define MC_CMD_RSS_CONTEXT_FREE_OUT_LEN 0 11108 11109 11110 /***********************************/ 11111 /* MC_CMD_RSS_CONTEXT_SET_KEY 11112 * Set the Toeplitz hash key for an RSS context. 11113 */ 11114 #define MC_CMD_RSS_CONTEXT_SET_KEY 0xa0 11115 #undef MC_CMD_0xa0_PRIVILEGE_CTG 11116 11117 #define MC_CMD_0xa0_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11118 11119 /* MC_CMD_RSS_CONTEXT_SET_KEY_IN msgrequest */ 11120 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN 44 11121 /* The handle of the RSS context */ 11122 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID_OFST 0 11123 /* The 40-byte Toeplitz hash key (TBD endianness issues?) */ 11124 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_OFST 4 11125 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN 40 11126 11127 /* MC_CMD_RSS_CONTEXT_SET_KEY_OUT msgresponse */ 11128 #define MC_CMD_RSS_CONTEXT_SET_KEY_OUT_LEN 0 11129 11130 11131 /***********************************/ 11132 /* MC_CMD_RSS_CONTEXT_GET_KEY 11133 * Get the Toeplitz hash key for an RSS context. 11134 */ 11135 #define MC_CMD_RSS_CONTEXT_GET_KEY 0xa1 11136 #undef MC_CMD_0xa1_PRIVILEGE_CTG 11137 11138 #define MC_CMD_0xa1_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11139 11140 /* MC_CMD_RSS_CONTEXT_GET_KEY_IN msgrequest */ 11141 #define MC_CMD_RSS_CONTEXT_GET_KEY_IN_LEN 4 11142 /* The handle of the RSS context */ 11143 #define MC_CMD_RSS_CONTEXT_GET_KEY_IN_RSS_CONTEXT_ID_OFST 0 11144 11145 /* MC_CMD_RSS_CONTEXT_GET_KEY_OUT msgresponse */ 11146 #define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_LEN 44 11147 /* The 40-byte Toeplitz hash key (TBD endianness issues?) */ 11148 #define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY_OFST 4 11149 #define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY_LEN 40 11150 11151 11152 /***********************************/ 11153 /* MC_CMD_RSS_CONTEXT_SET_TABLE 11154 * Set the indirection table for an RSS context. 11155 */ 11156 #define MC_CMD_RSS_CONTEXT_SET_TABLE 0xa2 11157 #undef MC_CMD_0xa2_PRIVILEGE_CTG 11158 11159 #define MC_CMD_0xa2_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11160 11161 /* MC_CMD_RSS_CONTEXT_SET_TABLE_IN msgrequest */ 11162 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN 132 11163 /* The handle of the RSS context */ 11164 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID_OFST 0 11165 /* The 128-byte indirection table (1 byte per entry) */ 11166 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_OFST 4 11167 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN 128 11168 11169 /* MC_CMD_RSS_CONTEXT_SET_TABLE_OUT msgresponse */ 11170 #define MC_CMD_RSS_CONTEXT_SET_TABLE_OUT_LEN 0 11171 11172 11173 /***********************************/ 11174 /* MC_CMD_RSS_CONTEXT_GET_TABLE 11175 * Get the indirection table for an RSS context. 11176 */ 11177 #define MC_CMD_RSS_CONTEXT_GET_TABLE 0xa3 11178 #undef MC_CMD_0xa3_PRIVILEGE_CTG 11179 11180 #define MC_CMD_0xa3_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11181 11182 /* MC_CMD_RSS_CONTEXT_GET_TABLE_IN msgrequest */ 11183 #define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_LEN 4 11184 /* The handle of the RSS context */ 11185 #define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_RSS_CONTEXT_ID_OFST 0 11186 11187 /* MC_CMD_RSS_CONTEXT_GET_TABLE_OUT msgresponse */ 11188 #define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_LEN 132 11189 /* The 128-byte indirection table (1 byte per entry) */ 11190 #define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_OFST 4 11191 #define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_LEN 128 11192 11193 11194 /***********************************/ 11195 /* MC_CMD_RSS_CONTEXT_SET_FLAGS 11196 * Set various control flags for an RSS context. 11197 */ 11198 #define MC_CMD_RSS_CONTEXT_SET_FLAGS 0xe1 11199 #undef MC_CMD_0xe1_PRIVILEGE_CTG 11200 11201 #define MC_CMD_0xe1_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11202 11203 /* MC_CMD_RSS_CONTEXT_SET_FLAGS_IN msgrequest */ 11204 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_LEN 8 11205 /* The handle of the RSS context */ 11206 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID_OFST 0 11207 /* Hash control flags. The _EN bits are always supported, but new modes are 11208 * available when ADDITIONAL_RSS_MODES is reported by MC_CMD_GET_CAPABILITIES: 11209 * in this case, the MODE fields may be set to non-zero values, and will take 11210 * effect regardless of the settings of the _EN flags. See the RSS_MODE 11211 * structure for the meaning of the mode bits. Drivers must check the 11212 * capability before trying to set any _MODE fields, as older firmware will 11213 * reject any attempt to set the FLAGS field to a value > 0xff with EINVAL. In 11214 * the case where all the _MODE flags are zero, the _EN flags take effect, 11215 * providing backward compatibility for existing drivers. (Setting all _MODE 11216 * *and* all _EN flags to zero is valid, to disable RSS spreading for that 11217 * particular packet type.) 11218 */ 11219 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_FLAGS_OFST 4 11220 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_LBN 0 11221 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_WIDTH 1 11222 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_LBN 1 11223 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_WIDTH 1 11224 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_LBN 2 11225 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_WIDTH 1 11226 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_LBN 3 11227 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_WIDTH 1 11228 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_LBN 4 11229 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_WIDTH 4 11230 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_LBN 8 11231 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_WIDTH 4 11232 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE_LBN 12 11233 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE_WIDTH 4 11234 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_LBN 16 11235 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_WIDTH 4 11236 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_LBN 20 11237 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_WIDTH 4 11238 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE_LBN 24 11239 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE_WIDTH 4 11240 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_LBN 28 11241 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_WIDTH 4 11242 11243 /* MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT msgresponse */ 11244 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT_LEN 0 11245 11246 11247 /***********************************/ 11248 /* MC_CMD_RSS_CONTEXT_GET_FLAGS 11249 * Get various control flags for an RSS context. 11250 */ 11251 #define MC_CMD_RSS_CONTEXT_GET_FLAGS 0xe2 11252 #undef MC_CMD_0xe2_PRIVILEGE_CTG 11253 11254 #define MC_CMD_0xe2_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11255 11256 /* MC_CMD_RSS_CONTEXT_GET_FLAGS_IN msgrequest */ 11257 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_LEN 4 11258 /* The handle of the RSS context */ 11259 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_RSS_CONTEXT_ID_OFST 0 11260 11261 /* MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT msgresponse */ 11262 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN 8 11263 /* Hash control flags. If all _MODE bits are zero (which will always be true 11264 * for older firmware which does not report the ADDITIONAL_RSS_MODES 11265 * capability), the _EN bits report the state. If any _MODE bits are non-zero 11266 * (which will only be true when the firmware reports ADDITIONAL_RSS_MODES) 11267 * then the _EN bits should be disregarded, although the _MODE flags are 11268 * guaranteed to be consistent with the _EN flags for a freshly-allocated RSS 11269 * context and in the case where the _EN flags were used in the SET. This 11270 * provides backward compatibility: old drivers will not be attempting to 11271 * derive any meaning from the _MODE bits (and can never set them to any value 11272 * not representable by the _EN bits); new drivers can always determine the 11273 * mode by looking only at the _MODE bits; the value returned by a GET can 11274 * always be used for a SET regardless of old/new driver vs. old/new firmware. 11275 */ 11276 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_OFST 4 11277 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_LBN 0 11278 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_WIDTH 1 11279 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_LBN 1 11280 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_WIDTH 1 11281 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_LBN 2 11282 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_WIDTH 1 11283 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_LBN 3 11284 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_WIDTH 1 11285 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_LBN 4 11286 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_WIDTH 4 11287 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_LBN 8 11288 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_WIDTH 4 11289 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_LBN 12 11290 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_WIDTH 4 11291 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_LBN 16 11292 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_WIDTH 4 11293 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_LBN 20 11294 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_WIDTH 4 11295 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_LBN 24 11296 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_WIDTH 4 11297 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_LBN 28 11298 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_WIDTH 4 11299 11300 11301 /***********************************/ 11302 /* MC_CMD_DOT1P_MAPPING_ALLOC 11303 * Allocate a .1p mapping. 11304 */ 11305 #define MC_CMD_DOT1P_MAPPING_ALLOC 0xa4 11306 #undef MC_CMD_0xa4_PRIVILEGE_CTG 11307 11308 #define MC_CMD_0xa4_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11309 11310 /* MC_CMD_DOT1P_MAPPING_ALLOC_IN msgrequest */ 11311 #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_LEN 8 11312 /* The handle of the owning upstream port */ 11313 #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 11314 /* Number of queues spanned by this mapping, in the range 1-64; valid fixed 11315 * offsets in the mapping table will be in the range 0 to NUM_QUEUES-1, and 11316 * referenced RSS contexts must span no more than this number. 11317 */ 11318 #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_NUM_QUEUES_OFST 4 11319 11320 /* MC_CMD_DOT1P_MAPPING_ALLOC_OUT msgresponse */ 11321 #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_LEN 4 11322 /* The handle of the new .1p mapping. This should be considered opaque to the 11323 * host, although a value of 0xFFFFFFFF is guaranteed never to be a valid 11324 * handle. 11325 */ 11326 #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_OFST 0 11327 /* enum: guaranteed invalid .1p mapping handle value */ 11328 #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_INVALID 0xffffffff 11329 11330 11331 /***********************************/ 11332 /* MC_CMD_DOT1P_MAPPING_FREE 11333 * Free a .1p mapping. 11334 */ 11335 #define MC_CMD_DOT1P_MAPPING_FREE 0xa5 11336 #undef MC_CMD_0xa5_PRIVILEGE_CTG 11337 11338 #define MC_CMD_0xa5_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11339 11340 /* MC_CMD_DOT1P_MAPPING_FREE_IN msgrequest */ 11341 #define MC_CMD_DOT1P_MAPPING_FREE_IN_LEN 4 11342 /* The handle of the .1p mapping */ 11343 #define MC_CMD_DOT1P_MAPPING_FREE_IN_DOT1P_MAPPING_ID_OFST 0 11344 11345 /* MC_CMD_DOT1P_MAPPING_FREE_OUT msgresponse */ 11346 #define MC_CMD_DOT1P_MAPPING_FREE_OUT_LEN 0 11347 11348 11349 /***********************************/ 11350 /* MC_CMD_DOT1P_MAPPING_SET_TABLE 11351 * Set the mapping table for a .1p mapping. 11352 */ 11353 #define MC_CMD_DOT1P_MAPPING_SET_TABLE 0xa6 11354 #undef MC_CMD_0xa6_PRIVILEGE_CTG 11355 11356 #define MC_CMD_0xa6_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11357 11358 /* MC_CMD_DOT1P_MAPPING_SET_TABLE_IN msgrequest */ 11359 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_LEN 36 11360 /* The handle of the .1p mapping */ 11361 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_DOT1P_MAPPING_ID_OFST 0 11362 /* Per-priority mappings (1 32-bit word per entry - an offset or RSS context 11363 * handle) 11364 */ 11365 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_MAPPING_TABLE_OFST 4 11366 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_MAPPING_TABLE_LEN 32 11367 11368 /* MC_CMD_DOT1P_MAPPING_SET_TABLE_OUT msgresponse */ 11369 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_OUT_LEN 0 11370 11371 11372 /***********************************/ 11373 /* MC_CMD_DOT1P_MAPPING_GET_TABLE 11374 * Get the mapping table for a .1p mapping. 11375 */ 11376 #define MC_CMD_DOT1P_MAPPING_GET_TABLE 0xa7 11377 #undef MC_CMD_0xa7_PRIVILEGE_CTG 11378 11379 #define MC_CMD_0xa7_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11380 11381 /* MC_CMD_DOT1P_MAPPING_GET_TABLE_IN msgrequest */ 11382 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_IN_LEN 4 11383 /* The handle of the .1p mapping */ 11384 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_IN_DOT1P_MAPPING_ID_OFST 0 11385 11386 /* MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT msgresponse */ 11387 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_LEN 36 11388 /* Per-priority mappings (1 32-bit word per entry - an offset or RSS context 11389 * handle) 11390 */ 11391 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_MAPPING_TABLE_OFST 4 11392 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_MAPPING_TABLE_LEN 32 11393 11394 11395 /***********************************/ 11396 /* MC_CMD_GET_VECTOR_CFG 11397 * Get Interrupt Vector config for this PF. 11398 */ 11399 #define MC_CMD_GET_VECTOR_CFG 0xbf 11400 #undef MC_CMD_0xbf_PRIVILEGE_CTG 11401 11402 #define MC_CMD_0xbf_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11403 11404 /* MC_CMD_GET_VECTOR_CFG_IN msgrequest */ 11405 #define MC_CMD_GET_VECTOR_CFG_IN_LEN 0 11406 11407 /* MC_CMD_GET_VECTOR_CFG_OUT msgresponse */ 11408 #define MC_CMD_GET_VECTOR_CFG_OUT_LEN 12 11409 /* Base absolute interrupt vector number. */ 11410 #define MC_CMD_GET_VECTOR_CFG_OUT_VEC_BASE_OFST 0 11411 /* Number of interrupt vectors allocate to this PF. */ 11412 #define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_PF_OFST 4 11413 /* Number of interrupt vectors to allocate per VF. */ 11414 #define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_VF_OFST 8 11415 11416 11417 /***********************************/ 11418 /* MC_CMD_SET_VECTOR_CFG 11419 * Set Interrupt Vector config for this PF. 11420 */ 11421 #define MC_CMD_SET_VECTOR_CFG 0xc0 11422 #undef MC_CMD_0xc0_PRIVILEGE_CTG 11423 11424 #define MC_CMD_0xc0_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11425 11426 /* MC_CMD_SET_VECTOR_CFG_IN msgrequest */ 11427 #define MC_CMD_SET_VECTOR_CFG_IN_LEN 12 11428 /* Base absolute interrupt vector number, or MC_CMD_RESOURCE_INSTANCE_ANY to 11429 * let the system find a suitable base. 11430 */ 11431 #define MC_CMD_SET_VECTOR_CFG_IN_VEC_BASE_OFST 0 11432 /* Number of interrupt vectors allocate to this PF. */ 11433 #define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_PF_OFST 4 11434 /* Number of interrupt vectors to allocate per VF. */ 11435 #define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_VF_OFST 8 11436 11437 /* MC_CMD_SET_VECTOR_CFG_OUT msgresponse */ 11438 #define MC_CMD_SET_VECTOR_CFG_OUT_LEN 0 11439 11440 11441 /***********************************/ 11442 /* MC_CMD_VPORT_ADD_MAC_ADDRESS 11443 * Add a MAC address to a v-port 11444 */ 11445 #define MC_CMD_VPORT_ADD_MAC_ADDRESS 0xa8 11446 #undef MC_CMD_0xa8_PRIVILEGE_CTG 11447 11448 #define MC_CMD_0xa8_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11449 11450 /* MC_CMD_VPORT_ADD_MAC_ADDRESS_IN msgrequest */ 11451 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN 10 11452 /* The handle of the v-port */ 11453 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID_OFST 0 11454 /* MAC address to add */ 11455 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_MACADDR_OFST 4 11456 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_MACADDR_LEN 6 11457 11458 /* MC_CMD_VPORT_ADD_MAC_ADDRESS_OUT msgresponse */ 11459 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_OUT_LEN 0 11460 11461 11462 /***********************************/ 11463 /* MC_CMD_VPORT_DEL_MAC_ADDRESS 11464 * Delete a MAC address from a v-port 11465 */ 11466 #define MC_CMD_VPORT_DEL_MAC_ADDRESS 0xa9 11467 #undef MC_CMD_0xa9_PRIVILEGE_CTG 11468 11469 #define MC_CMD_0xa9_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11470 11471 /* MC_CMD_VPORT_DEL_MAC_ADDRESS_IN msgrequest */ 11472 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN 10 11473 /* The handle of the v-port */ 11474 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID_OFST 0 11475 /* MAC address to add */ 11476 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_MACADDR_OFST 4 11477 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_MACADDR_LEN 6 11478 11479 /* MC_CMD_VPORT_DEL_MAC_ADDRESS_OUT msgresponse */ 11480 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_OUT_LEN 0 11481 11482 11483 /***********************************/ 11484 /* MC_CMD_VPORT_GET_MAC_ADDRESSES 11485 * Delete a MAC address from a v-port 11486 */ 11487 #define MC_CMD_VPORT_GET_MAC_ADDRESSES 0xaa 11488 #undef MC_CMD_0xaa_PRIVILEGE_CTG 11489 11490 #define MC_CMD_0xaa_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11491 11492 /* MC_CMD_VPORT_GET_MAC_ADDRESSES_IN msgrequest */ 11493 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN 4 11494 /* The handle of the v-port */ 11495 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID_OFST 0 11496 11497 /* MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT msgresponse */ 11498 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN 4 11499 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX 250 11500 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LEN(num) (4+6*(num)) 11501 /* The number of MAC addresses returned */ 11502 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT_OFST 0 11503 /* Array of MAC addresses */ 11504 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_OFST 4 11505 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_LEN 6 11506 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MINNUM 0 11507 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MAXNUM 41 11508 11509 11510 /***********************************/ 11511 /* MC_CMD_VPORT_RECONFIGURE 11512 * Replace VLAN tags and/or MAC addresses of an existing v-port. If the v-port 11513 * has already been passed to another function (v-port's user), then that 11514 * function will be reset before applying the changes. 11515 */ 11516 #define MC_CMD_VPORT_RECONFIGURE 0xeb 11517 #undef MC_CMD_0xeb_PRIVILEGE_CTG 11518 11519 #define MC_CMD_0xeb_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11520 11521 /* MC_CMD_VPORT_RECONFIGURE_IN msgrequest */ 11522 #define MC_CMD_VPORT_RECONFIGURE_IN_LEN 44 11523 /* The handle of the v-port */ 11524 #define MC_CMD_VPORT_RECONFIGURE_IN_VPORT_ID_OFST 0 11525 /* Flags requesting what should be changed. */ 11526 #define MC_CMD_VPORT_RECONFIGURE_IN_FLAGS_OFST 4 11527 #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_VLAN_TAGS_LBN 0 11528 #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_VLAN_TAGS_WIDTH 1 11529 #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_MACADDRS_LBN 1 11530 #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_MACADDRS_WIDTH 1 11531 /* The number of VLAN tags to insert/remove. An error will be returned if 11532 * incompatible with the number of VLAN tags specified for the upstream 11533 * v-switch. 11534 */ 11535 #define MC_CMD_VPORT_RECONFIGURE_IN_NUM_VLAN_TAGS_OFST 8 11536 /* The actual VLAN tags to insert/remove */ 11537 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAGS_OFST 12 11538 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_0_LBN 0 11539 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_0_WIDTH 16 11540 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_1_LBN 16 11541 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_1_WIDTH 16 11542 /* The number of MAC addresses to add */ 11543 #define MC_CMD_VPORT_RECONFIGURE_IN_NUM_MACADDRS_OFST 16 11544 /* MAC addresses to add */ 11545 #define MC_CMD_VPORT_RECONFIGURE_IN_MACADDRS_OFST 20 11546 #define MC_CMD_VPORT_RECONFIGURE_IN_MACADDRS_LEN 6 11547 #define MC_CMD_VPORT_RECONFIGURE_IN_MACADDRS_NUM 4 11548 11549 /* MC_CMD_VPORT_RECONFIGURE_OUT msgresponse */ 11550 #define MC_CMD_VPORT_RECONFIGURE_OUT_LEN 4 11551 #define MC_CMD_VPORT_RECONFIGURE_OUT_FLAGS_OFST 0 11552 #define MC_CMD_VPORT_RECONFIGURE_OUT_RESET_DONE_LBN 0 11553 #define MC_CMD_VPORT_RECONFIGURE_OUT_RESET_DONE_WIDTH 1 11554 11555 11556 /***********************************/ 11557 /* MC_CMD_EVB_PORT_QUERY 11558 * read some config of v-port. 11559 */ 11560 #define MC_CMD_EVB_PORT_QUERY 0x62 11561 #undef MC_CMD_0x62_PRIVILEGE_CTG 11562 11563 #define MC_CMD_0x62_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11564 11565 /* MC_CMD_EVB_PORT_QUERY_IN msgrequest */ 11566 #define MC_CMD_EVB_PORT_QUERY_IN_LEN 4 11567 /* The handle of the v-port */ 11568 #define MC_CMD_EVB_PORT_QUERY_IN_PORT_ID_OFST 0 11569 11570 /* MC_CMD_EVB_PORT_QUERY_OUT msgresponse */ 11571 #define MC_CMD_EVB_PORT_QUERY_OUT_LEN 8 11572 /* The EVB port flags as defined at MC_CMD_VPORT_ALLOC. */ 11573 #define MC_CMD_EVB_PORT_QUERY_OUT_PORT_FLAGS_OFST 0 11574 /* The number of VLAN tags that may be used on a v-adaptor connected to this 11575 * EVB port. 11576 */ 11577 #define MC_CMD_EVB_PORT_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_OFST 4 11578 11579 11580 /***********************************/ 11581 /* MC_CMD_DUMP_BUFTBL_ENTRIES 11582 * Dump buffer table entries, mainly for command client debug use. Dumps 11583 * absolute entries, and does not use chunk handles. All entries must be in 11584 * range, and used for q page mapping, Although the latter restriction may be 11585 * lifted in future. 11586 */ 11587 #define MC_CMD_DUMP_BUFTBL_ENTRIES 0xab 11588 #undef MC_CMD_0xab_PRIVILEGE_CTG 11589 11590 #define MC_CMD_0xab_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11591 11592 /* MC_CMD_DUMP_BUFTBL_ENTRIES_IN msgrequest */ 11593 #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_LEN 8 11594 /* Index of the first buffer table entry. */ 11595 #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_FIRSTID_OFST 0 11596 /* Number of buffer table entries to dump. */ 11597 #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_NUMENTRIES_OFST 4 11598 11599 /* MC_CMD_DUMP_BUFTBL_ENTRIES_OUT msgresponse */ 11600 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LENMIN 12 11601 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LENMAX 252 11602 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LEN(num) (0+12*(num)) 11603 /* Raw buffer table entries, laid out as BUFTBL_ENTRY. */ 11604 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_OFST 0 11605 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_LEN 12 11606 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_MINNUM 1 11607 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_MAXNUM 21 11608 11609 11610 /***********************************/ 11611 /* MC_CMD_SET_RXDP_CONFIG 11612 * Set global RXDP configuration settings 11613 */ 11614 #define MC_CMD_SET_RXDP_CONFIG 0xc1 11615 #undef MC_CMD_0xc1_PRIVILEGE_CTG 11616 11617 #define MC_CMD_0xc1_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11618 11619 /* MC_CMD_SET_RXDP_CONFIG_IN msgrequest */ 11620 #define MC_CMD_SET_RXDP_CONFIG_IN_LEN 4 11621 #define MC_CMD_SET_RXDP_CONFIG_IN_DATA_OFST 0 11622 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_LBN 0 11623 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_WIDTH 1 11624 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_LEN_LBN 1 11625 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_LEN_WIDTH 2 11626 /* enum: pad to 64 bytes */ 11627 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_64 0x0 11628 /* enum: pad to 128 bytes (Medford only) */ 11629 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_128 0x1 11630 /* enum: pad to 256 bytes (Medford only) */ 11631 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_256 0x2 11632 11633 /* MC_CMD_SET_RXDP_CONFIG_OUT msgresponse */ 11634 #define MC_CMD_SET_RXDP_CONFIG_OUT_LEN 0 11635 11636 11637 /***********************************/ 11638 /* MC_CMD_GET_RXDP_CONFIG 11639 * Get global RXDP configuration settings 11640 */ 11641 #define MC_CMD_GET_RXDP_CONFIG 0xc2 11642 #undef MC_CMD_0xc2_PRIVILEGE_CTG 11643 11644 #define MC_CMD_0xc2_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11645 11646 /* MC_CMD_GET_RXDP_CONFIG_IN msgrequest */ 11647 #define MC_CMD_GET_RXDP_CONFIG_IN_LEN 0 11648 11649 /* MC_CMD_GET_RXDP_CONFIG_OUT msgresponse */ 11650 #define MC_CMD_GET_RXDP_CONFIG_OUT_LEN 4 11651 #define MC_CMD_GET_RXDP_CONFIG_OUT_DATA_OFST 0 11652 #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_LBN 0 11653 #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_WIDTH 1 11654 #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_LEN_LBN 1 11655 #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_LEN_WIDTH 2 11656 /* Enum values, see field(s): */ 11657 /* MC_CMD_SET_RXDP_CONFIG/MC_CMD_SET_RXDP_CONFIG_IN/PAD_HOST_LEN */ 11658 11659 11660 /***********************************/ 11661 /* MC_CMD_GET_CLOCK 11662 * Return the system and PDCPU clock frequencies. 11663 */ 11664 #define MC_CMD_GET_CLOCK 0xac 11665 #undef MC_CMD_0xac_PRIVILEGE_CTG 11666 11667 #define MC_CMD_0xac_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11668 11669 /* MC_CMD_GET_CLOCK_IN msgrequest */ 11670 #define MC_CMD_GET_CLOCK_IN_LEN 0 11671 11672 /* MC_CMD_GET_CLOCK_OUT msgresponse */ 11673 #define MC_CMD_GET_CLOCK_OUT_LEN 8 11674 /* System frequency, MHz */ 11675 #define MC_CMD_GET_CLOCK_OUT_SYS_FREQ_OFST 0 11676 /* DPCPU frequency, MHz */ 11677 #define MC_CMD_GET_CLOCK_OUT_DPCPU_FREQ_OFST 4 11678 11679 11680 /***********************************/ 11681 /* MC_CMD_SET_CLOCK 11682 * Control the system and DPCPU clock frequencies. Changes are lost reboot. 11683 */ 11684 #define MC_CMD_SET_CLOCK 0xad 11685 #undef MC_CMD_0xad_PRIVILEGE_CTG 11686 11687 #define MC_CMD_0xad_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11688 11689 /* MC_CMD_SET_CLOCK_IN msgrequest */ 11690 #define MC_CMD_SET_CLOCK_IN_LEN 28 11691 /* Requested frequency in MHz for system clock domain */ 11692 #define MC_CMD_SET_CLOCK_IN_SYS_FREQ_OFST 0 11693 /* enum: Leave the system clock domain frequency unchanged */ 11694 #define MC_CMD_SET_CLOCK_IN_SYS_DOMAIN_DONT_CHANGE 0x0 11695 /* Requested frequency in MHz for inter-core clock domain */ 11696 #define MC_CMD_SET_CLOCK_IN_ICORE_FREQ_OFST 4 11697 /* enum: Leave the inter-core clock domain frequency unchanged */ 11698 #define MC_CMD_SET_CLOCK_IN_ICORE_DOMAIN_DONT_CHANGE 0x0 11699 /* Requested frequency in MHz for DPCPU clock domain */ 11700 #define MC_CMD_SET_CLOCK_IN_DPCPU_FREQ_OFST 8 11701 /* enum: Leave the DPCPU clock domain frequency unchanged */ 11702 #define MC_CMD_SET_CLOCK_IN_DPCPU_DOMAIN_DONT_CHANGE 0x0 11703 /* Requested frequency in MHz for PCS clock domain */ 11704 #define MC_CMD_SET_CLOCK_IN_PCS_FREQ_OFST 12 11705 /* enum: Leave the PCS clock domain frequency unchanged */ 11706 #define MC_CMD_SET_CLOCK_IN_PCS_DOMAIN_DONT_CHANGE 0x0 11707 /* Requested frequency in MHz for MC clock domain */ 11708 #define MC_CMD_SET_CLOCK_IN_MC_FREQ_OFST 16 11709 /* enum: Leave the MC clock domain frequency unchanged */ 11710 #define MC_CMD_SET_CLOCK_IN_MC_DOMAIN_DONT_CHANGE 0x0 11711 /* Requested frequency in MHz for rmon clock domain */ 11712 #define MC_CMD_SET_CLOCK_IN_RMON_FREQ_OFST 20 11713 /* enum: Leave the rmon clock domain frequency unchanged */ 11714 #define MC_CMD_SET_CLOCK_IN_RMON_DOMAIN_DONT_CHANGE 0x0 11715 /* Requested frequency in MHz for vswitch clock domain */ 11716 #define MC_CMD_SET_CLOCK_IN_VSWITCH_FREQ_OFST 24 11717 /* enum: Leave the vswitch clock domain frequency unchanged */ 11718 #define MC_CMD_SET_CLOCK_IN_VSWITCH_DOMAIN_DONT_CHANGE 0x0 11719 11720 /* MC_CMD_SET_CLOCK_OUT msgresponse */ 11721 #define MC_CMD_SET_CLOCK_OUT_LEN 28 11722 /* Resulting system frequency in MHz */ 11723 #define MC_CMD_SET_CLOCK_OUT_SYS_FREQ_OFST 0 11724 /* enum: The system clock domain doesn't exist */ 11725 #define MC_CMD_SET_CLOCK_OUT_SYS_DOMAIN_UNSUPPORTED 0x0 11726 /* Resulting inter-core frequency in MHz */ 11727 #define MC_CMD_SET_CLOCK_OUT_ICORE_FREQ_OFST 4 11728 /* enum: The inter-core clock domain doesn't exist / isn't used */ 11729 #define MC_CMD_SET_CLOCK_OUT_ICORE_DOMAIN_UNSUPPORTED 0x0 11730 /* Resulting DPCPU frequency in MHz */ 11731 #define MC_CMD_SET_CLOCK_OUT_DPCPU_FREQ_OFST 8 11732 /* enum: The dpcpu clock domain doesn't exist */ 11733 #define MC_CMD_SET_CLOCK_OUT_DPCPU_DOMAIN_UNSUPPORTED 0x0 11734 /* Resulting PCS frequency in MHz */ 11735 #define MC_CMD_SET_CLOCK_OUT_PCS_FREQ_OFST 12 11736 /* enum: The PCS clock domain doesn't exist / isn't controlled */ 11737 #define MC_CMD_SET_CLOCK_OUT_PCS_DOMAIN_UNSUPPORTED 0x0 11738 /* Resulting MC frequency in MHz */ 11739 #define MC_CMD_SET_CLOCK_OUT_MC_FREQ_OFST 16 11740 /* enum: The MC clock domain doesn't exist / isn't controlled */ 11741 #define MC_CMD_SET_CLOCK_OUT_MC_DOMAIN_UNSUPPORTED 0x0 11742 /* Resulting rmon frequency in MHz */ 11743 #define MC_CMD_SET_CLOCK_OUT_RMON_FREQ_OFST 20 11744 /* enum: The rmon clock domain doesn't exist / isn't controlled */ 11745 #define MC_CMD_SET_CLOCK_OUT_RMON_DOMAIN_UNSUPPORTED 0x0 11746 /* Resulting vswitch frequency in MHz */ 11747 #define MC_CMD_SET_CLOCK_OUT_VSWITCH_FREQ_OFST 24 11748 /* enum: The vswitch clock domain doesn't exist / isn't controlled */ 11749 #define MC_CMD_SET_CLOCK_OUT_VSWITCH_DOMAIN_UNSUPPORTED 0x0 11750 11751 11752 /***********************************/ 11753 /* MC_CMD_DPCPU_RPC 11754 * Send an arbitrary DPCPU message. 11755 */ 11756 #define MC_CMD_DPCPU_RPC 0xae 11757 #undef MC_CMD_0xae_PRIVILEGE_CTG 11758 11759 #define MC_CMD_0xae_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11760 11761 /* MC_CMD_DPCPU_RPC_IN msgrequest */ 11762 #define MC_CMD_DPCPU_RPC_IN_LEN 36 11763 #define MC_CMD_DPCPU_RPC_IN_CPU_OFST 0 11764 /* enum: RxDPCPU0 */ 11765 #define MC_CMD_DPCPU_RPC_IN_DPCPU_RX0 0x0 11766 /* enum: TxDPCPU0 */ 11767 #define MC_CMD_DPCPU_RPC_IN_DPCPU_TX0 0x1 11768 /* enum: TxDPCPU1 */ 11769 #define MC_CMD_DPCPU_RPC_IN_DPCPU_TX1 0x2 11770 /* enum: RxDPCPU1 (Medford only) */ 11771 #define MC_CMD_DPCPU_RPC_IN_DPCPU_RX1 0x3 11772 /* enum: RxDPCPU (will be for the calling function; for now, just an alias of 11773 * DPCPU_RX0) 11774 */ 11775 #define MC_CMD_DPCPU_RPC_IN_DPCPU_RX 0x80 11776 /* enum: TxDPCPU (will be for the calling function; for now, just an alias of 11777 * DPCPU_TX0) 11778 */ 11779 #define MC_CMD_DPCPU_RPC_IN_DPCPU_TX 0x81 11780 /* First 8 bits [39:32] of DATA are consumed by MC-DPCPU protocol and must be 11781 * initialised to zero 11782 */ 11783 #define MC_CMD_DPCPU_RPC_IN_DATA_OFST 4 11784 #define MC_CMD_DPCPU_RPC_IN_DATA_LEN 32 11785 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_CMDNUM_LBN 8 11786 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_CMDNUM_WIDTH 8 11787 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_READ 0x6 /* enum */ 11788 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_WRITE 0x7 /* enum */ 11789 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_SELF_TEST 0xc /* enum */ 11790 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_CSR_ACCESS 0xe /* enum */ 11791 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_READ 0x46 /* enum */ 11792 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_WRITE 0x47 /* enum */ 11793 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_SELF_TEST 0x4a /* enum */ 11794 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_CSR_ACCESS 0x4c /* enum */ 11795 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_SET_MC_REPLAY_CNTXT 0x4d /* enum */ 11796 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_OBJID_LBN 16 11797 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_OBJID_WIDTH 16 11798 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_ADDR_LBN 16 11799 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_ADDR_WIDTH 16 11800 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_COUNT_LBN 48 11801 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_COUNT_WIDTH 16 11802 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_INFO_LBN 16 11803 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_INFO_WIDTH 240 11804 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_LBN 16 11805 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_WIDTH 16 11806 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_STOP_RETURN_RESULT 0x0 /* enum */ 11807 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_READ 0x1 /* enum */ 11808 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_WRITE 0x2 /* enum */ 11809 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_WRITE_READ 0x3 /* enum */ 11810 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_PIPELINED_READ 0x4 /* enum */ 11811 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_START_DELAY_LBN 48 11812 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_START_DELAY_WIDTH 16 11813 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_RPT_COUNT_LBN 64 11814 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_RPT_COUNT_WIDTH 16 11815 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_GAP_DELAY_LBN 80 11816 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_GAP_DELAY_WIDTH 16 11817 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_LBN 16 11818 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_WIDTH 16 11819 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_CUT_THROUGH 0x1 /* enum */ 11820 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_STORE_FORWARD 0x2 /* enum */ 11821 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_STORE_FORWARD_FIRST 0x3 /* enum */ 11822 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_CNTXT_LBN 64 11823 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_CNTXT_WIDTH 16 11824 #define MC_CMD_DPCPU_RPC_IN_WDATA_OFST 12 11825 #define MC_CMD_DPCPU_RPC_IN_WDATA_LEN 24 11826 /* Register data to write. Only valid in write/write-read. */ 11827 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_DATA_OFST 16 11828 /* Register address. */ 11829 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_ADDRESS_OFST 20 11830 11831 /* MC_CMD_DPCPU_RPC_OUT msgresponse */ 11832 #define MC_CMD_DPCPU_RPC_OUT_LEN 36 11833 #define MC_CMD_DPCPU_RPC_OUT_RC_OFST 0 11834 /* DATA */ 11835 #define MC_CMD_DPCPU_RPC_OUT_DATA_OFST 4 11836 #define MC_CMD_DPCPU_RPC_OUT_DATA_LEN 32 11837 #define MC_CMD_DPCPU_RPC_OUT_HDR_CMD_RESP_ERRCODE_LBN 32 11838 #define MC_CMD_DPCPU_RPC_OUT_HDR_CMD_RESP_ERRCODE_WIDTH 16 11839 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_COUNT_LBN 48 11840 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_COUNT_WIDTH 16 11841 #define MC_CMD_DPCPU_RPC_OUT_RDATA_OFST 12 11842 #define MC_CMD_DPCPU_RPC_OUT_RDATA_LEN 24 11843 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_1_OFST 12 11844 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_2_OFST 16 11845 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_3_OFST 20 11846 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_4_OFST 24 11847 11848 11849 /***********************************/ 11850 /* MC_CMD_TRIGGER_INTERRUPT 11851 * Trigger an interrupt by prodding the BIU. 11852 */ 11853 #define MC_CMD_TRIGGER_INTERRUPT 0xe3 11854 #undef MC_CMD_0xe3_PRIVILEGE_CTG 11855 11856 #define MC_CMD_0xe3_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11857 11858 /* MC_CMD_TRIGGER_INTERRUPT_IN msgrequest */ 11859 #define MC_CMD_TRIGGER_INTERRUPT_IN_LEN 4 11860 /* Interrupt level relative to base for function. */ 11861 #define MC_CMD_TRIGGER_INTERRUPT_IN_INTR_LEVEL_OFST 0 11862 11863 /* MC_CMD_TRIGGER_INTERRUPT_OUT msgresponse */ 11864 #define MC_CMD_TRIGGER_INTERRUPT_OUT_LEN 0 11865 11866 11867 /***********************************/ 11868 /* MC_CMD_SHMBOOT_OP 11869 * Special operations to support (for now) shmboot. 11870 */ 11871 #define MC_CMD_SHMBOOT_OP 0xe6 11872 #undef MC_CMD_0xe6_PRIVILEGE_CTG 11873 11874 #define MC_CMD_0xe6_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11875 11876 /* MC_CMD_SHMBOOT_OP_IN msgrequest */ 11877 #define MC_CMD_SHMBOOT_OP_IN_LEN 4 11878 /* Identifies the operation to perform */ 11879 #define MC_CMD_SHMBOOT_OP_IN_SHMBOOT_OP_OFST 0 11880 /* enum: Copy slave_data section to the slave core. (Greenport only) */ 11881 #define MC_CMD_SHMBOOT_OP_IN_PUSH_SLAVE_DATA 0x0 11882 11883 /* MC_CMD_SHMBOOT_OP_OUT msgresponse */ 11884 #define MC_CMD_SHMBOOT_OP_OUT_LEN 0 11885 11886 11887 /***********************************/ 11888 /* MC_CMD_CAP_BLK_READ 11889 * Read multiple 64bit words from capture block memory 11890 */ 11891 #define MC_CMD_CAP_BLK_READ 0xe7 11892 #undef MC_CMD_0xe7_PRIVILEGE_CTG 11893 11894 #define MC_CMD_0xe7_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11895 11896 /* MC_CMD_CAP_BLK_READ_IN msgrequest */ 11897 #define MC_CMD_CAP_BLK_READ_IN_LEN 12 11898 #define MC_CMD_CAP_BLK_READ_IN_CAP_REG_OFST 0 11899 #define MC_CMD_CAP_BLK_READ_IN_ADDR_OFST 4 11900 #define MC_CMD_CAP_BLK_READ_IN_COUNT_OFST 8 11901 11902 /* MC_CMD_CAP_BLK_READ_OUT msgresponse */ 11903 #define MC_CMD_CAP_BLK_READ_OUT_LENMIN 8 11904 #define MC_CMD_CAP_BLK_READ_OUT_LENMAX 248 11905 #define MC_CMD_CAP_BLK_READ_OUT_LEN(num) (0+8*(num)) 11906 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_OFST 0 11907 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LEN 8 11908 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LO_OFST 0 11909 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_HI_OFST 4 11910 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_MINNUM 1 11911 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_MAXNUM 31 11912 11913 11914 /***********************************/ 11915 /* MC_CMD_DUMP_DO 11916 * Take a dump of the DUT state 11917 */ 11918 #define MC_CMD_DUMP_DO 0xe8 11919 #undef MC_CMD_0xe8_PRIVILEGE_CTG 11920 11921 #define MC_CMD_0xe8_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11922 11923 /* MC_CMD_DUMP_DO_IN msgrequest */ 11924 #define MC_CMD_DUMP_DO_IN_LEN 52 11925 #define MC_CMD_DUMP_DO_IN_PADDING_OFST 0 11926 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_OFST 4 11927 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM 0x0 /* enum */ 11928 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_DEFAULT 0x1 /* enum */ 11929 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_TYPE_OFST 8 11930 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_NVRAM 0x1 /* enum */ 11931 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_HOST_MEMORY 0x2 /* enum */ 11932 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_HOST_MEMORY_MLI 0x3 /* enum */ 11933 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_UART 0x4 /* enum */ 11934 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 12 11935 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_OFST 16 11936 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 12 11937 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 16 11938 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 12 11939 #define MC_CMD_DUMP_DO_IN_HOST_MEMORY_MLI_PAGE_SIZE 0x1000 /* enum */ 11940 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 16 11941 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 20 11942 #define MC_CMD_DUMP_DO_IN_HOST_MEMORY_MLI_MAX_DEPTH 0x2 /* enum */ 11943 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_OFST 12 11944 /* enum: The uart port this command was received over (if using a uart 11945 * transport) 11946 */ 11947 #define MC_CMD_DUMP_DO_IN_UART_PORT_SRC 0xff 11948 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_SIZE_OFST 24 11949 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_OFST 28 11950 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM 0x0 /* enum */ 11951 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_NVRAM_DUMP_PARTITION 0x1 /* enum */ 11952 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_TYPE_OFST 32 11953 /* Enum values, see field(s): */ 11954 /* MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */ 11955 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 36 11956 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_OFST 40 11957 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 36 11958 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 40 11959 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 36 11960 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 40 11961 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 44 11962 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_UART_PORT_OFST 36 11963 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_SIZE_OFST 48 11964 11965 /* MC_CMD_DUMP_DO_OUT msgresponse */ 11966 #define MC_CMD_DUMP_DO_OUT_LEN 4 11967 #define MC_CMD_DUMP_DO_OUT_DUMPFILE_SIZE_OFST 0 11968 11969 11970 /***********************************/ 11971 /* MC_CMD_DUMP_CONFIGURE_UNSOLICITED 11972 * Configure unsolicited dumps 11973 */ 11974 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED 0xe9 11975 #undef MC_CMD_0xe9_PRIVILEGE_CTG 11976 11977 #define MC_CMD_0xe9_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11978 11979 /* MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN msgrequest */ 11980 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_LEN 52 11981 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_ENABLE_OFST 0 11982 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_OFST 4 11983 /* Enum values, see field(s): */ 11984 /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC */ 11985 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_TYPE_OFST 8 11986 /* Enum values, see field(s): */ 11987 /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */ 11988 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 12 11989 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_OFST 16 11990 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 12 11991 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 16 11992 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 12 11993 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 16 11994 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 20 11995 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_OFST 12 11996 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_SIZE_OFST 24 11997 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_OFST 28 11998 /* Enum values, see field(s): */ 11999 /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPFILE_DST */ 12000 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_TYPE_OFST 32 12001 /* Enum values, see field(s): */ 12002 /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */ 12003 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 36 12004 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_OFST 40 12005 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 36 12006 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 40 12007 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 36 12008 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 40 12009 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 44 12010 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_UART_PORT_OFST 36 12011 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_SIZE_OFST 48 12012 12013 12014 /***********************************/ 12015 /* MC_CMD_SET_PSU 12016 * Adjusts power supply parameters. This is a warranty-voiding operation. 12017 * Returns: ENOENT if the parameter or rail specified does not exist, EINVAL if 12018 * the parameter is out of range. 12019 */ 12020 #define MC_CMD_SET_PSU 0xea 12021 #undef MC_CMD_0xea_PRIVILEGE_CTG 12022 12023 #define MC_CMD_0xea_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12024 12025 /* MC_CMD_SET_PSU_IN msgrequest */ 12026 #define MC_CMD_SET_PSU_IN_LEN 12 12027 #define MC_CMD_SET_PSU_IN_PARAM_OFST 0 12028 #define MC_CMD_SET_PSU_IN_PARAM_SUPPLY_VOLTAGE 0x0 /* enum */ 12029 #define MC_CMD_SET_PSU_IN_RAIL_OFST 4 12030 #define MC_CMD_SET_PSU_IN_RAIL_0V9 0x0 /* enum */ 12031 #define MC_CMD_SET_PSU_IN_RAIL_1V2 0x1 /* enum */ 12032 /* desired value, eg voltage in mV */ 12033 #define MC_CMD_SET_PSU_IN_VALUE_OFST 8 12034 12035 /* MC_CMD_SET_PSU_OUT msgresponse */ 12036 #define MC_CMD_SET_PSU_OUT_LEN 0 12037 12038 12039 /***********************************/ 12040 /* MC_CMD_GET_FUNCTION_INFO 12041 * Get function information. PF and VF number. 12042 */ 12043 #define MC_CMD_GET_FUNCTION_INFO 0xec 12044 #undef MC_CMD_0xec_PRIVILEGE_CTG 12045 12046 #define MC_CMD_0xec_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12047 12048 /* MC_CMD_GET_FUNCTION_INFO_IN msgrequest */ 12049 #define MC_CMD_GET_FUNCTION_INFO_IN_LEN 0 12050 12051 /* MC_CMD_GET_FUNCTION_INFO_OUT msgresponse */ 12052 #define MC_CMD_GET_FUNCTION_INFO_OUT_LEN 8 12053 #define MC_CMD_GET_FUNCTION_INFO_OUT_PF_OFST 0 12054 #define MC_CMD_GET_FUNCTION_INFO_OUT_VF_OFST 4 12055 12056 12057 /***********************************/ 12058 /* MC_CMD_ENABLE_OFFLINE_BIST 12059 * Enters offline BIST mode. All queues are torn down, chip enters quiescent 12060 * mode, calling function gets exclusive MCDI ownership. The only way out is 12061 * reboot. 12062 */ 12063 #define MC_CMD_ENABLE_OFFLINE_BIST 0xed 12064 #undef MC_CMD_0xed_PRIVILEGE_CTG 12065 12066 #define MC_CMD_0xed_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12067 12068 /* MC_CMD_ENABLE_OFFLINE_BIST_IN msgrequest */ 12069 #define MC_CMD_ENABLE_OFFLINE_BIST_IN_LEN 0 12070 12071 /* MC_CMD_ENABLE_OFFLINE_BIST_OUT msgresponse */ 12072 #define MC_CMD_ENABLE_OFFLINE_BIST_OUT_LEN 0 12073 12074 12075 /***********************************/ 12076 /* MC_CMD_UART_SEND_DATA 12077 * Send checksummed[sic] block of data over the uart. Response is a placeholder 12078 * should we wish to make this reliable; currently requests are fire-and- 12079 * forget. 12080 */ 12081 #define MC_CMD_UART_SEND_DATA 0xee 12082 #undef MC_CMD_0xee_PRIVILEGE_CTG 12083 12084 #define MC_CMD_0xee_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12085 12086 /* MC_CMD_UART_SEND_DATA_OUT msgrequest */ 12087 #define MC_CMD_UART_SEND_DATA_OUT_LENMIN 16 12088 #define MC_CMD_UART_SEND_DATA_OUT_LENMAX 252 12089 #define MC_CMD_UART_SEND_DATA_OUT_LEN(num) (16+1*(num)) 12090 /* CRC32 over OFFSET, LENGTH, RESERVED, DATA */ 12091 #define MC_CMD_UART_SEND_DATA_OUT_CHECKSUM_OFST 0 12092 /* Offset at which to write the data */ 12093 #define MC_CMD_UART_SEND_DATA_OUT_OFFSET_OFST 4 12094 /* Length of data */ 12095 #define MC_CMD_UART_SEND_DATA_OUT_LENGTH_OFST 8 12096 /* Reserved for future use */ 12097 #define MC_CMD_UART_SEND_DATA_OUT_RESERVED_OFST 12 12098 #define MC_CMD_UART_SEND_DATA_OUT_DATA_OFST 16 12099 #define MC_CMD_UART_SEND_DATA_OUT_DATA_LEN 1 12100 #define MC_CMD_UART_SEND_DATA_OUT_DATA_MINNUM 0 12101 #define MC_CMD_UART_SEND_DATA_OUT_DATA_MAXNUM 236 12102 12103 /* MC_CMD_UART_SEND_DATA_IN msgresponse */ 12104 #define MC_CMD_UART_SEND_DATA_IN_LEN 0 12105 12106 12107 /***********************************/ 12108 /* MC_CMD_UART_RECV_DATA 12109 * Request checksummed[sic] block of data over the uart. Only a placeholder, 12110 * subject to change and not currently implemented. 12111 */ 12112 #define MC_CMD_UART_RECV_DATA 0xef 12113 #undef MC_CMD_0xef_PRIVILEGE_CTG 12114 12115 #define MC_CMD_0xef_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12116 12117 /* MC_CMD_UART_RECV_DATA_OUT msgrequest */ 12118 #define MC_CMD_UART_RECV_DATA_OUT_LEN 16 12119 /* CRC32 over OFFSET, LENGTH, RESERVED */ 12120 #define MC_CMD_UART_RECV_DATA_OUT_CHECKSUM_OFST 0 12121 /* Offset from which to read the data */ 12122 #define MC_CMD_UART_RECV_DATA_OUT_OFFSET_OFST 4 12123 /* Length of data */ 12124 #define MC_CMD_UART_RECV_DATA_OUT_LENGTH_OFST 8 12125 /* Reserved for future use */ 12126 #define MC_CMD_UART_RECV_DATA_OUT_RESERVED_OFST 12 12127 12128 /* MC_CMD_UART_RECV_DATA_IN msgresponse */ 12129 #define MC_CMD_UART_RECV_DATA_IN_LENMIN 16 12130 #define MC_CMD_UART_RECV_DATA_IN_LENMAX 252 12131 #define MC_CMD_UART_RECV_DATA_IN_LEN(num) (16+1*(num)) 12132 /* CRC32 over RESERVED1, RESERVED2, RESERVED3, DATA */ 12133 #define MC_CMD_UART_RECV_DATA_IN_CHECKSUM_OFST 0 12134 /* Offset at which to write the data */ 12135 #define MC_CMD_UART_RECV_DATA_IN_RESERVED1_OFST 4 12136 /* Length of data */ 12137 #define MC_CMD_UART_RECV_DATA_IN_RESERVED2_OFST 8 12138 /* Reserved for future use */ 12139 #define MC_CMD_UART_RECV_DATA_IN_RESERVED3_OFST 12 12140 #define MC_CMD_UART_RECV_DATA_IN_DATA_OFST 16 12141 #define MC_CMD_UART_RECV_DATA_IN_DATA_LEN 1 12142 #define MC_CMD_UART_RECV_DATA_IN_DATA_MINNUM 0 12143 #define MC_CMD_UART_RECV_DATA_IN_DATA_MAXNUM 236 12144 12145 12146 /***********************************/ 12147 /* MC_CMD_READ_FUSES 12148 * Read data programmed into the device One-Time-Programmable (OTP) Fuses 12149 */ 12150 #define MC_CMD_READ_FUSES 0xf0 12151 #undef MC_CMD_0xf0_PRIVILEGE_CTG 12152 12153 #define MC_CMD_0xf0_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12154 12155 /* MC_CMD_READ_FUSES_IN msgrequest */ 12156 #define MC_CMD_READ_FUSES_IN_LEN 8 12157 /* Offset in OTP to read */ 12158 #define MC_CMD_READ_FUSES_IN_OFFSET_OFST 0 12159 /* Length of data to read in bytes */ 12160 #define MC_CMD_READ_FUSES_IN_LENGTH_OFST 4 12161 12162 /* MC_CMD_READ_FUSES_OUT msgresponse */ 12163 #define MC_CMD_READ_FUSES_OUT_LENMIN 4 12164 #define MC_CMD_READ_FUSES_OUT_LENMAX 252 12165 #define MC_CMD_READ_FUSES_OUT_LEN(num) (4+1*(num)) 12166 /* Length of returned OTP data in bytes */ 12167 #define MC_CMD_READ_FUSES_OUT_LENGTH_OFST 0 12168 /* Returned data */ 12169 #define MC_CMD_READ_FUSES_OUT_DATA_OFST 4 12170 #define MC_CMD_READ_FUSES_OUT_DATA_LEN 1 12171 #define MC_CMD_READ_FUSES_OUT_DATA_MINNUM 0 12172 #define MC_CMD_READ_FUSES_OUT_DATA_MAXNUM 248 12173 12174 12175 /***********************************/ 12176 /* MC_CMD_KR_TUNE 12177 * Get or set KR Serdes RXEQ and TX Driver settings 12178 */ 12179 #define MC_CMD_KR_TUNE 0xf1 12180 #undef MC_CMD_0xf1_PRIVILEGE_CTG 12181 12182 #define MC_CMD_0xf1_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12183 12184 /* MC_CMD_KR_TUNE_IN msgrequest */ 12185 #define MC_CMD_KR_TUNE_IN_LENMIN 4 12186 #define MC_CMD_KR_TUNE_IN_LENMAX 252 12187 #define MC_CMD_KR_TUNE_IN_LEN(num) (4+4*(num)) 12188 /* Requested operation */ 12189 #define MC_CMD_KR_TUNE_IN_KR_TUNE_OP_OFST 0 12190 #define MC_CMD_KR_TUNE_IN_KR_TUNE_OP_LEN 1 12191 /* enum: Get current RXEQ settings */ 12192 #define MC_CMD_KR_TUNE_IN_RXEQ_GET 0x0 12193 /* enum: Override RXEQ settings */ 12194 #define MC_CMD_KR_TUNE_IN_RXEQ_SET 0x1 12195 /* enum: Get current TX Driver settings */ 12196 #define MC_CMD_KR_TUNE_IN_TXEQ_GET 0x2 12197 /* enum: Override TX Driver settings */ 12198 #define MC_CMD_KR_TUNE_IN_TXEQ_SET 0x3 12199 /* enum: Force KR Serdes reset / recalibration */ 12200 #define MC_CMD_KR_TUNE_IN_RECAL 0x4 12201 /* enum: Start KR Serdes Eye diagram plot on a given lane. Lane must have valid 12202 * signal. 12203 */ 12204 #define MC_CMD_KR_TUNE_IN_START_EYE_PLOT 0x5 12205 /* enum: Poll KR Serdes Eye diagram plot. Returns one row of BER data. The 12206 * caller should call this command repeatedly after starting eye plot, until no 12207 * more data is returned. 12208 */ 12209 #define MC_CMD_KR_TUNE_IN_POLL_EYE_PLOT 0x6 12210 /* enum: Read Figure Of Merit (eye quality, higher is better). */ 12211 #define MC_CMD_KR_TUNE_IN_READ_FOM 0x7 12212 /* Align the arguments to 32 bits */ 12213 #define MC_CMD_KR_TUNE_IN_KR_TUNE_RSVD_OFST 1 12214 #define MC_CMD_KR_TUNE_IN_KR_TUNE_RSVD_LEN 3 12215 /* Arguments specific to the operation */ 12216 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_OFST 4 12217 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_LEN 4 12218 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_MINNUM 0 12219 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_MAXNUM 62 12220 12221 /* MC_CMD_KR_TUNE_OUT msgresponse */ 12222 #define MC_CMD_KR_TUNE_OUT_LEN 0 12223 12224 /* MC_CMD_KR_TUNE_RXEQ_GET_IN msgrequest */ 12225 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_LEN 4 12226 /* Requested operation */ 12227 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_OP_OFST 0 12228 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_OP_LEN 1 12229 /* Align the arguments to 32 bits */ 12230 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_RSVD_OFST 1 12231 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_RSVD_LEN 3 12232 12233 /* MC_CMD_KR_TUNE_RXEQ_GET_OUT msgresponse */ 12234 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LENMIN 4 12235 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LENMAX 252 12236 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LEN(num) (0+4*(num)) 12237 /* RXEQ Parameter */ 12238 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_OFST 0 12239 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LEN 4 12240 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_MINNUM 1 12241 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_MAXNUM 63 12242 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_LBN 0 12243 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_WIDTH 8 12244 /* enum: Attenuation (0-15, Huntington) */ 12245 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_ATT 0x0 12246 /* enum: CTLE Boost (0-15, Huntington) */ 12247 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_BOOST 0x1 12248 /* enum: Edge DFE Tap1 (Huntington - 0 - max negative, 64 - zero, 127 - max 12249 * positive, Medford - 0-31) 12250 */ 12251 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP1 0x2 12252 /* enum: Edge DFE Tap2 (Huntington - 0 - max negative, 32 - zero, 63 - max 12253 * positive, Medford - 0-31) 12254 */ 12255 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP2 0x3 12256 /* enum: Edge DFE Tap3 (Huntington - 0 - max negative, 32 - zero, 63 - max 12257 * positive, Medford - 0-16) 12258 */ 12259 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP3 0x4 12260 /* enum: Edge DFE Tap4 (Huntington - 0 - max negative, 32 - zero, 63 - max 12261 * positive, Medford - 0-16) 12262 */ 12263 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP4 0x5 12264 /* enum: Edge DFE Tap5 (Huntington - 0 - max negative, 32 - zero, 63 - max 12265 * positive, Medford - 0-16) 12266 */ 12267 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP5 0x6 12268 /* enum: Edge DFE DLEV (0-128 for Medford) */ 12269 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_DLEV 0x7 12270 /* enum: Variable Gain Amplifier (0-15, Medford) */ 12271 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_VGA 0x8 12272 /* enum: CTLE EQ Capacitor (0-15, Medford) */ 12273 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_EQC 0x9 12274 /* enum: CTLE EQ Resistor (0-7, Medford) */ 12275 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_EQRES 0xa 12276 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_LBN 8 12277 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_WIDTH 3 12278 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */ 12279 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_1 0x1 /* enum */ 12280 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_2 0x2 /* enum */ 12281 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_3 0x3 /* enum */ 12282 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_ALL 0x4 /* enum */ 12283 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_LBN 11 12284 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_WIDTH 1 12285 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_RESERVED_LBN 12 12286 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_RESERVED_WIDTH 4 12287 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_INITIAL_LBN 16 12288 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_INITIAL_WIDTH 8 12289 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_LBN 24 12290 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8 12291 12292 /* MC_CMD_KR_TUNE_RXEQ_SET_IN msgrequest */ 12293 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_LENMIN 8 12294 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_LENMAX 252 12295 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_LEN(num) (4+4*(num)) 12296 /* Requested operation */ 12297 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_OP_OFST 0 12298 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_OP_LEN 1 12299 /* Align the arguments to 32 bits */ 12300 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_RSVD_OFST 1 12301 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_RSVD_LEN 3 12302 /* RXEQ Parameter */ 12303 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_OFST 4 12304 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LEN 4 12305 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_MINNUM 1 12306 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_MAXNUM 62 12307 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_ID_LBN 0 12308 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_ID_WIDTH 8 12309 /* Enum values, see field(s): */ 12310 /* MC_CMD_KR_TUNE_RXEQ_GET_OUT/PARAM_ID */ 12311 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LANE_LBN 8 12312 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LANE_WIDTH 3 12313 /* Enum values, see field(s): */ 12314 /* MC_CMD_KR_TUNE_RXEQ_GET_OUT/PARAM_LANE */ 12315 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_LBN 11 12316 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_WIDTH 1 12317 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED_LBN 12 12318 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED_WIDTH 4 12319 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_INITIAL_LBN 16 12320 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_INITIAL_WIDTH 8 12321 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED2_LBN 24 12322 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED2_WIDTH 8 12323 12324 /* MC_CMD_KR_TUNE_RXEQ_SET_OUT msgresponse */ 12325 #define MC_CMD_KR_TUNE_RXEQ_SET_OUT_LEN 0 12326 12327 /* MC_CMD_KR_TUNE_TXEQ_GET_IN msgrequest */ 12328 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_LEN 4 12329 /* Requested operation */ 12330 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_OP_OFST 0 12331 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_OP_LEN 1 12332 /* Align the arguments to 32 bits */ 12333 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_RSVD_OFST 1 12334 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_RSVD_LEN 3 12335 12336 /* MC_CMD_KR_TUNE_TXEQ_GET_OUT msgresponse */ 12337 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LENMIN 4 12338 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LENMAX 252 12339 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LEN(num) (0+4*(num)) 12340 /* TXEQ Parameter */ 12341 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_OFST 0 12342 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LEN 4 12343 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_MINNUM 1 12344 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_MAXNUM 63 12345 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_LBN 0 12346 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_WIDTH 8 12347 /* enum: TX Amplitude (Huntington, Medford) */ 12348 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV 0x0 12349 /* enum: De-Emphasis Tap1 Magnitude (0-7) (Huntington) */ 12350 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_MODE 0x1 12351 /* enum: De-Emphasis Tap1 Fine */ 12352 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_DTLEV 0x2 12353 /* enum: De-Emphasis Tap2 Magnitude (0-6) (Huntington) */ 12354 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_D2 0x3 12355 /* enum: De-Emphasis Tap2 Fine (Huntington) */ 12356 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_D2TLEV 0x4 12357 /* enum: Pre-Emphasis Magnitude (Huntington) */ 12358 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_E 0x5 12359 /* enum: Pre-Emphasis Fine (Huntington) */ 12360 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_ETLEV 0x6 12361 /* enum: TX Slew Rate Coarse control (Huntington) */ 12362 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_PREDRV_DLY 0x7 12363 /* enum: TX Slew Rate Fine control (Huntington) */ 12364 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_SR_SET 0x8 12365 /* enum: TX Termination Impedance control (Huntington) */ 12366 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_RT_SET 0x9 12367 /* enum: TX Amplitude Fine control (Medford) */ 12368 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV_FINE 0xa 12369 /* enum: Pre-shoot Tap (Medford) */ 12370 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_ADV 0xb 12371 /* enum: De-emphasis Tap (Medford) */ 12372 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_DLY 0xc 12373 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LANE_LBN 8 12374 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LANE_WIDTH 3 12375 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_0 0x0 /* enum */ 12376 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_1 0x1 /* enum */ 12377 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_2 0x2 /* enum */ 12378 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_3 0x3 /* enum */ 12379 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_ALL 0x4 /* enum */ 12380 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED_LBN 11 12381 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED_WIDTH 5 12382 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_INITIAL_LBN 16 12383 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_INITIAL_WIDTH 8 12384 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED2_LBN 24 12385 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED2_WIDTH 8 12386 12387 /* MC_CMD_KR_TUNE_TXEQ_SET_IN msgrequest */ 12388 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_LENMIN 8 12389 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_LENMAX 252 12390 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_LEN(num) (4+4*(num)) 12391 /* Requested operation */ 12392 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_OP_OFST 0 12393 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_OP_LEN 1 12394 /* Align the arguments to 32 bits */ 12395 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_RSVD_OFST 1 12396 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_RSVD_LEN 3 12397 /* TXEQ Parameter */ 12398 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_OFST 4 12399 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LEN 4 12400 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_MINNUM 1 12401 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_MAXNUM 62 12402 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_ID_LBN 0 12403 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_ID_WIDTH 8 12404 /* Enum values, see field(s): */ 12405 /* MC_CMD_KR_TUNE_TXEQ_GET_OUT/PARAM_ID */ 12406 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LANE_LBN 8 12407 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LANE_WIDTH 3 12408 /* Enum values, see field(s): */ 12409 /* MC_CMD_KR_TUNE_TXEQ_GET_OUT/PARAM_LANE */ 12410 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED_LBN 11 12411 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED_WIDTH 5 12412 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_INITIAL_LBN 16 12413 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_INITIAL_WIDTH 8 12414 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED2_LBN 24 12415 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED2_WIDTH 8 12416 12417 /* MC_CMD_KR_TUNE_TXEQ_SET_OUT msgresponse */ 12418 #define MC_CMD_KR_TUNE_TXEQ_SET_OUT_LEN 0 12419 12420 /* MC_CMD_KR_TUNE_RECAL_IN msgrequest */ 12421 #define MC_CMD_KR_TUNE_RECAL_IN_LEN 4 12422 /* Requested operation */ 12423 #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_OP_OFST 0 12424 #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_OP_LEN 1 12425 /* Align the arguments to 32 bits */ 12426 #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_RSVD_OFST 1 12427 #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_RSVD_LEN 3 12428 12429 /* MC_CMD_KR_TUNE_RECAL_OUT msgresponse */ 12430 #define MC_CMD_KR_TUNE_RECAL_OUT_LEN 0 12431 12432 /* MC_CMD_KR_TUNE_START_EYE_PLOT_IN msgrequest */ 12433 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_LEN 8 12434 /* Requested operation */ 12435 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_OP_OFST 0 12436 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_OP_LEN 1 12437 /* Align the arguments to 32 bits */ 12438 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_RSVD_OFST 1 12439 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_RSVD_LEN 3 12440 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_LANE_OFST 4 12441 12442 /* MC_CMD_KR_TUNE_START_EYE_PLOT_OUT msgresponse */ 12443 #define MC_CMD_KR_TUNE_START_EYE_PLOT_OUT_LEN 0 12444 12445 /* MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN msgrequest */ 12446 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_LEN 4 12447 /* Requested operation */ 12448 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_OP_OFST 0 12449 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_OP_LEN 1 12450 /* Align the arguments to 32 bits */ 12451 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_RSVD_OFST 1 12452 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_RSVD_LEN 3 12453 12454 /* MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT msgresponse */ 12455 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LENMIN 0 12456 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LENMAX 252 12457 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LEN(num) (0+2*(num)) 12458 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_OFST 0 12459 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_LEN 2 12460 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MINNUM 0 12461 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MAXNUM 126 12462 12463 /* MC_CMD_KR_TUNE_READ_FOM_IN msgrequest */ 12464 #define MC_CMD_KR_TUNE_READ_FOM_IN_LEN 8 12465 /* Requested operation */ 12466 #define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_OP_OFST 0 12467 #define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_OP_LEN 1 12468 /* Align the arguments to 32 bits */ 12469 #define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_RSVD_OFST 1 12470 #define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_RSVD_LEN 3 12471 #define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_OFST 4 12472 12473 /* MC_CMD_KR_TUNE_READ_FOM_OUT msgresponse */ 12474 #define MC_CMD_KR_TUNE_READ_FOM_OUT_LEN 4 12475 #define MC_CMD_KR_TUNE_READ_FOM_OUT_FOM_OFST 0 12476 12477 12478 /***********************************/ 12479 /* MC_CMD_PCIE_TUNE 12480 * Get or set PCIE Serdes RXEQ and TX Driver settings 12481 */ 12482 #define MC_CMD_PCIE_TUNE 0xf2 12483 #undef MC_CMD_0xf2_PRIVILEGE_CTG 12484 12485 #define MC_CMD_0xf2_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12486 12487 /* MC_CMD_PCIE_TUNE_IN msgrequest */ 12488 #define MC_CMD_PCIE_TUNE_IN_LENMIN 4 12489 #define MC_CMD_PCIE_TUNE_IN_LENMAX 252 12490 #define MC_CMD_PCIE_TUNE_IN_LEN(num) (4+4*(num)) 12491 /* Requested operation */ 12492 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_OP_OFST 0 12493 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_OP_LEN 1 12494 /* enum: Get current RXEQ settings */ 12495 #define MC_CMD_PCIE_TUNE_IN_RXEQ_GET 0x0 12496 /* enum: Override RXEQ settings */ 12497 #define MC_CMD_PCIE_TUNE_IN_RXEQ_SET 0x1 12498 /* enum: Get current TX Driver settings */ 12499 #define MC_CMD_PCIE_TUNE_IN_TXEQ_GET 0x2 12500 /* enum: Override TX Driver settings */ 12501 #define MC_CMD_PCIE_TUNE_IN_TXEQ_SET 0x3 12502 /* enum: Start PCIe Serdes Eye diagram plot on a given lane. */ 12503 #define MC_CMD_PCIE_TUNE_IN_START_EYE_PLOT 0x5 12504 /* enum: Poll PCIe Serdes Eye diagram plot. Returns one row of BER data. The 12505 * caller should call this command repeatedly after starting eye plot, until no 12506 * more data is returned. 12507 */ 12508 #define MC_CMD_PCIE_TUNE_IN_POLL_EYE_PLOT 0x6 12509 /* Align the arguments to 32 bits */ 12510 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_RSVD_OFST 1 12511 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_RSVD_LEN 3 12512 /* Arguments specific to the operation */ 12513 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_OFST 4 12514 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_LEN 4 12515 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_MINNUM 0 12516 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_MAXNUM 62 12517 12518 /* MC_CMD_PCIE_TUNE_OUT msgresponse */ 12519 #define MC_CMD_PCIE_TUNE_OUT_LEN 0 12520 12521 /* MC_CMD_PCIE_TUNE_RXEQ_GET_IN msgrequest */ 12522 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_LEN 4 12523 /* Requested operation */ 12524 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_OP_OFST 0 12525 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_OP_LEN 1 12526 /* Align the arguments to 32 bits */ 12527 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_RSVD_OFST 1 12528 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_RSVD_LEN 3 12529 12530 /* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT msgresponse */ 12531 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LENMIN 4 12532 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LENMAX 252 12533 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LEN(num) (0+4*(num)) 12534 /* RXEQ Parameter */ 12535 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_OFST 0 12536 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LEN 4 12537 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_MINNUM 1 12538 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_MAXNUM 63 12539 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_ID_LBN 0 12540 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_ID_WIDTH 8 12541 /* enum: Attenuation (0-15) */ 12542 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_ATT 0x0 12543 /* enum: CTLE Boost (0-15) */ 12544 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_BOOST 0x1 12545 /* enum: DFE Tap1 (0 - max negative, 64 - zero, 127 - max positive) */ 12546 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP1 0x2 12547 /* enum: DFE Tap2 (0 - max negative, 32 - zero, 63 - max positive) */ 12548 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP2 0x3 12549 /* enum: DFE Tap3 (0 - max negative, 32 - zero, 63 - max positive) */ 12550 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP3 0x4 12551 /* enum: DFE Tap4 (0 - max negative, 32 - zero, 63 - max positive) */ 12552 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP4 0x5 12553 /* enum: DFE Tap5 (0 - max negative, 32 - zero, 63 - max positive) */ 12554 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP5 0x6 12555 /* enum: DFE DLev */ 12556 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_DLEV 0x7 12557 /* enum: Figure of Merit */ 12558 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_FOM 0x8 12559 /* enum: CTLE EQ Capacitor (HF Gain) */ 12560 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_CTLE_EQC 0x9 12561 /* enum: CTLE EQ Resistor (DC Gain) */ 12562 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_CTLE_EQRES 0xa 12563 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_LBN 8 12564 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_WIDTH 5 12565 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */ 12566 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_1 0x1 /* enum */ 12567 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_2 0x2 /* enum */ 12568 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_3 0x3 /* enum */ 12569 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_4 0x4 /* enum */ 12570 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_5 0x5 /* enum */ 12571 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_6 0x6 /* enum */ 12572 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_7 0x7 /* enum */ 12573 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_8 0x8 /* enum */ 12574 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_9 0x9 /* enum */ 12575 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_10 0xa /* enum */ 12576 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_11 0xb /* enum */ 12577 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_12 0xc /* enum */ 12578 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_13 0xd /* enum */ 12579 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_14 0xe /* enum */ 12580 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_15 0xf /* enum */ 12581 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_ALL 0x10 /* enum */ 12582 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_LBN 13 12583 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_WIDTH 1 12584 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_LBN 14 12585 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_WIDTH 10 12586 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_LBN 24 12587 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8 12588 12589 /* MC_CMD_PCIE_TUNE_RXEQ_SET_IN msgrequest */ 12590 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LENMIN 8 12591 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LENMAX 252 12592 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LEN(num) (4+4*(num)) 12593 /* Requested operation */ 12594 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_OP_OFST 0 12595 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_OP_LEN 1 12596 /* Align the arguments to 32 bits */ 12597 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_RSVD_OFST 1 12598 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_RSVD_LEN 3 12599 /* RXEQ Parameter */ 12600 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_OFST 4 12601 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LEN 4 12602 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_MINNUM 1 12603 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_MAXNUM 62 12604 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_ID_LBN 0 12605 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_ID_WIDTH 8 12606 /* Enum values, see field(s): */ 12607 /* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_ID */ 12608 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LANE_LBN 8 12609 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LANE_WIDTH 5 12610 /* Enum values, see field(s): */ 12611 /* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_LANE */ 12612 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_LBN 13 12613 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_WIDTH 1 12614 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED_LBN 14 12615 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED_WIDTH 2 12616 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_INITIAL_LBN 16 12617 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_INITIAL_WIDTH 8 12618 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED2_LBN 24 12619 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED2_WIDTH 8 12620 12621 /* MC_CMD_PCIE_TUNE_RXEQ_SET_OUT msgresponse */ 12622 #define MC_CMD_PCIE_TUNE_RXEQ_SET_OUT_LEN 0 12623 12624 /* MC_CMD_PCIE_TUNE_TXEQ_GET_IN msgrequest */ 12625 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_LEN 4 12626 /* Requested operation */ 12627 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_OP_OFST 0 12628 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_OP_LEN 1 12629 /* Align the arguments to 32 bits */ 12630 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_RSVD_OFST 1 12631 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_RSVD_LEN 3 12632 12633 /* MC_CMD_PCIE_TUNE_TXEQ_GET_OUT msgresponse */ 12634 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LENMIN 4 12635 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LENMAX 252 12636 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LEN(num) (0+4*(num)) 12637 /* RXEQ Parameter */ 12638 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_OFST 0 12639 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LEN 4 12640 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_MINNUM 1 12641 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_MAXNUM 63 12642 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_ID_LBN 0 12643 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_ID_WIDTH 8 12644 /* enum: TxMargin (PIPE) */ 12645 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_TXMARGIN 0x0 12646 /* enum: TxSwing (PIPE) */ 12647 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_TXSWING 0x1 12648 /* enum: De-emphasis coefficient C(-1) (PIPE) */ 12649 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_CM1 0x2 12650 /* enum: De-emphasis coefficient C(0) (PIPE) */ 12651 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_C0 0x3 12652 /* enum: De-emphasis coefficient C(+1) (PIPE) */ 12653 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_CP1 0x4 12654 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LANE_LBN 8 12655 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LANE_WIDTH 4 12656 /* Enum values, see field(s): */ 12657 /* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_LANE */ 12658 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_RESERVED_LBN 12 12659 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_RESERVED_WIDTH 12 12660 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_CURRENT_LBN 24 12661 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8 12662 12663 /* MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN msgrequest */ 12664 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_LEN 8 12665 /* Requested operation */ 12666 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_OP_OFST 0 12667 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_OP_LEN 1 12668 /* Align the arguments to 32 bits */ 12669 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_RSVD_OFST 1 12670 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_RSVD_LEN 3 12671 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_LANE_OFST 4 12672 12673 /* MC_CMD_PCIE_TUNE_START_EYE_PLOT_OUT msgresponse */ 12674 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_OUT_LEN 0 12675 12676 /* MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN msgrequest */ 12677 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_LEN 4 12678 /* Requested operation */ 12679 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_OP_OFST 0 12680 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_OP_LEN 1 12681 /* Align the arguments to 32 bits */ 12682 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_RSVD_OFST 1 12683 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_RSVD_LEN 3 12684 12685 /* MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT msgresponse */ 12686 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LENMIN 0 12687 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LENMAX 252 12688 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LEN(num) (0+2*(num)) 12689 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_OFST 0 12690 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_LEN 2 12691 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MINNUM 0 12692 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MAXNUM 126 12693 12694 12695 /***********************************/ 12696 /* MC_CMD_LICENSING 12697 * Operations on the NVRAM_PARTITION_TYPE_LICENSE application license partition 12698 * - not used for V3 licensing 12699 */ 12700 #define MC_CMD_LICENSING 0xf3 12701 #undef MC_CMD_0xf3_PRIVILEGE_CTG 12702 12703 #define MC_CMD_0xf3_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12704 12705 /* MC_CMD_LICENSING_IN msgrequest */ 12706 #define MC_CMD_LICENSING_IN_LEN 4 12707 /* identifies the type of operation requested */ 12708 #define MC_CMD_LICENSING_IN_OP_OFST 0 12709 /* enum: re-read and apply licenses after a license key partition update; note 12710 * that this operation returns a zero-length response 12711 */ 12712 #define MC_CMD_LICENSING_IN_OP_UPDATE_LICENSE 0x0 12713 /* enum: report counts of installed licenses */ 12714 #define MC_CMD_LICENSING_IN_OP_GET_KEY_STATS 0x1 12715 12716 /* MC_CMD_LICENSING_OUT msgresponse */ 12717 #define MC_CMD_LICENSING_OUT_LEN 28 12718 /* count of application keys which are valid */ 12719 #define MC_CMD_LICENSING_OUT_VALID_APP_KEYS_OFST 0 12720 /* sum of UNVERIFIABLE_APP_KEYS + WRONG_NODE_APP_KEYS (for compatibility with 12721 * MC_CMD_FC_OP_LICENSE) 12722 */ 12723 #define MC_CMD_LICENSING_OUT_INVALID_APP_KEYS_OFST 4 12724 /* count of application keys which are invalid due to being blacklisted */ 12725 #define MC_CMD_LICENSING_OUT_BLACKLISTED_APP_KEYS_OFST 8 12726 /* count of application keys which are invalid due to being unverifiable */ 12727 #define MC_CMD_LICENSING_OUT_UNVERIFIABLE_APP_KEYS_OFST 12 12728 /* count of application keys which are invalid due to being for the wrong node 12729 */ 12730 #define MC_CMD_LICENSING_OUT_WRONG_NODE_APP_KEYS_OFST 16 12731 /* licensing state (for diagnostics; the exact meaning of the bits in this 12732 * field are private to the firmware) 12733 */ 12734 #define MC_CMD_LICENSING_OUT_LICENSING_STATE_OFST 20 12735 /* licensing subsystem self-test report (for manftest) */ 12736 #define MC_CMD_LICENSING_OUT_LICENSING_SELF_TEST_OFST 24 12737 /* enum: licensing subsystem self-test failed */ 12738 #define MC_CMD_LICENSING_OUT_SELF_TEST_FAIL 0x0 12739 /* enum: licensing subsystem self-test passed */ 12740 #define MC_CMD_LICENSING_OUT_SELF_TEST_PASS 0x1 12741 12742 12743 /***********************************/ 12744 /* MC_CMD_LICENSING_V3 12745 * Operations on the NVRAM_PARTITION_TYPE_LICENSE application license partition 12746 * - V3 licensing (Medford) 12747 */ 12748 #define MC_CMD_LICENSING_V3 0xd0 12749 #undef MC_CMD_0xd0_PRIVILEGE_CTG 12750 12751 #define MC_CMD_0xd0_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12752 12753 /* MC_CMD_LICENSING_V3_IN msgrequest */ 12754 #define MC_CMD_LICENSING_V3_IN_LEN 4 12755 /* identifies the type of operation requested */ 12756 #define MC_CMD_LICENSING_V3_IN_OP_OFST 0 12757 /* enum: re-read and apply licenses after a license key partition update; note 12758 * that this operation returns a zero-length response 12759 */ 12760 #define MC_CMD_LICENSING_V3_IN_OP_UPDATE_LICENSE 0x0 12761 /* enum: report counts of installed licenses */ 12762 #define MC_CMD_LICENSING_V3_IN_OP_REPORT_LICENSE 0x1 12763 12764 /* MC_CMD_LICENSING_V3_OUT msgresponse */ 12765 #define MC_CMD_LICENSING_V3_OUT_LEN 88 12766 /* count of keys which are valid */ 12767 #define MC_CMD_LICENSING_V3_OUT_VALID_KEYS_OFST 0 12768 /* sum of UNVERIFIABLE_KEYS + WRONG_NODE_KEYS (for compatibility with 12769 * MC_CMD_FC_OP_LICENSE) 12770 */ 12771 #define MC_CMD_LICENSING_V3_OUT_INVALID_KEYS_OFST 4 12772 /* count of keys which are invalid due to being unverifiable */ 12773 #define MC_CMD_LICENSING_V3_OUT_UNVERIFIABLE_KEYS_OFST 8 12774 /* count of keys which are invalid due to being for the wrong node */ 12775 #define MC_CMD_LICENSING_V3_OUT_WRONG_NODE_KEYS_OFST 12 12776 /* licensing state (for diagnostics; the exact meaning of the bits in this 12777 * field are private to the firmware) 12778 */ 12779 #define MC_CMD_LICENSING_V3_OUT_LICENSING_STATE_OFST 16 12780 /* licensing subsystem self-test report (for manftest) */ 12781 #define MC_CMD_LICENSING_V3_OUT_LICENSING_SELF_TEST_OFST 20 12782 /* enum: licensing subsystem self-test failed */ 12783 #define MC_CMD_LICENSING_V3_OUT_SELF_TEST_FAIL 0x0 12784 /* enum: licensing subsystem self-test passed */ 12785 #define MC_CMD_LICENSING_V3_OUT_SELF_TEST_PASS 0x1 12786 /* bitmask of licensed applications */ 12787 #define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_OFST 24 12788 #define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LEN 8 12789 #define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LO_OFST 24 12790 #define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_HI_OFST 28 12791 /* reserved for future use */ 12792 #define MC_CMD_LICENSING_V3_OUT_RESERVED_0_OFST 32 12793 #define MC_CMD_LICENSING_V3_OUT_RESERVED_0_LEN 24 12794 /* bitmask of licensed features */ 12795 #define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_OFST 56 12796 #define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LEN 8 12797 #define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LO_OFST 56 12798 #define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_HI_OFST 60 12799 /* reserved for future use */ 12800 #define MC_CMD_LICENSING_V3_OUT_RESERVED_1_OFST 64 12801 #define MC_CMD_LICENSING_V3_OUT_RESERVED_1_LEN 24 12802 12803 12804 /***********************************/ 12805 /* MC_CMD_LICENSING_GET_ID_V3 12806 * Get ID and type from the NVRAM_PARTITION_TYPE_LICENSE application license 12807 * partition - V3 licensing (Medford) 12808 */ 12809 #define MC_CMD_LICENSING_GET_ID_V3 0xd1 12810 #undef MC_CMD_0xd1_PRIVILEGE_CTG 12811 12812 #define MC_CMD_0xd1_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12813 12814 /* MC_CMD_LICENSING_GET_ID_V3_IN msgrequest */ 12815 #define MC_CMD_LICENSING_GET_ID_V3_IN_LEN 0 12816 12817 /* MC_CMD_LICENSING_GET_ID_V3_OUT msgresponse */ 12818 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LENMIN 8 12819 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LENMAX 252 12820 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LEN(num) (8+1*(num)) 12821 /* type of license (eg 3) */ 12822 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_TYPE_OFST 0 12823 /* length of the license ID (in bytes) */ 12824 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_LENGTH_OFST 4 12825 /* the unique license ID of the adapter */ 12826 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_OFST 8 12827 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_LEN 1 12828 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_MINNUM 0 12829 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_MAXNUM 244 12830 12831 12832 /***********************************/ 12833 /* MC_CMD_MC2MC_PROXY 12834 * Execute an arbitrary MCDI command on the slave MC of a dual-core device. 12835 * This will fail on a single-core system. 12836 */ 12837 #define MC_CMD_MC2MC_PROXY 0xf4 12838 #undef MC_CMD_0xf4_PRIVILEGE_CTG 12839 12840 #define MC_CMD_0xf4_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12841 12842 /* MC_CMD_MC2MC_PROXY_IN msgrequest */ 12843 #define MC_CMD_MC2MC_PROXY_IN_LEN 0 12844 12845 /* MC_CMD_MC2MC_PROXY_OUT msgresponse */ 12846 #define MC_CMD_MC2MC_PROXY_OUT_LEN 0 12847 12848 12849 /***********************************/ 12850 /* MC_CMD_GET_LICENSED_APP_STATE 12851 * Query the state of an individual licensed application. (Note that the actual 12852 * state may be invalidated by the MC_CMD_LICENSING OP_UPDATE_LICENSE operation 12853 * or a reboot of the MC.) Not used for V3 licensing 12854 */ 12855 #define MC_CMD_GET_LICENSED_APP_STATE 0xf5 12856 #undef MC_CMD_0xf5_PRIVILEGE_CTG 12857 12858 #define MC_CMD_0xf5_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12859 12860 /* MC_CMD_GET_LICENSED_APP_STATE_IN msgrequest */ 12861 #define MC_CMD_GET_LICENSED_APP_STATE_IN_LEN 4 12862 /* application ID to query (LICENSED_APP_ID_xxx) */ 12863 #define MC_CMD_GET_LICENSED_APP_STATE_IN_APP_ID_OFST 0 12864 12865 /* MC_CMD_GET_LICENSED_APP_STATE_OUT msgresponse */ 12866 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_LEN 4 12867 /* state of this application */ 12868 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_STATE_OFST 0 12869 /* enum: no (or invalid) license is present for the application */ 12870 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_NOT_LICENSED 0x0 12871 /* enum: a valid license is present for the application */ 12872 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_LICENSED 0x1 12873 12874 12875 /***********************************/ 12876 /* MC_CMD_GET_LICENSED_V3_APP_STATE 12877 * Query the state of an individual licensed application. (Note that the actual 12878 * state may be invalidated by the MC_CMD_LICENSING_V3 OP_UPDATE_LICENSE 12879 * operation or a reboot of the MC.) Used for V3 licensing (Medford) 12880 */ 12881 #define MC_CMD_GET_LICENSED_V3_APP_STATE 0xd2 12882 #undef MC_CMD_0xd2_PRIVILEGE_CTG 12883 12884 #define MC_CMD_0xd2_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12885 12886 /* MC_CMD_GET_LICENSED_V3_APP_STATE_IN msgrequest */ 12887 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_LEN 8 12888 /* application ID to query (LICENSED_V3_APPS_xxx) expressed as a single bit 12889 * mask 12890 */ 12891 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_OFST 0 12892 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LEN 8 12893 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LO_OFST 0 12894 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_HI_OFST 4 12895 12896 /* MC_CMD_GET_LICENSED_V3_APP_STATE_OUT msgresponse */ 12897 #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_LEN 4 12898 /* state of this application */ 12899 #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_STATE_OFST 0 12900 /* enum: no (or invalid) license is present for the application */ 12901 #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_NOT_LICENSED 0x0 12902 /* enum: a valid license is present for the application */ 12903 #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_LICENSED 0x1 12904 12905 12906 /***********************************/ 12907 /* MC_CMD_GET_LICENSED_V3_FEATURE_STATES 12908 * Query the state of an one or more licensed features. (Note that the actual 12909 * state may be invalidated by the MC_CMD_LICENSING_V3 OP_UPDATE_LICENSE 12910 * operation or a reboot of the MC.) Used for V3 licensing (Medford) 12911 */ 12912 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES 0xd3 12913 #undef MC_CMD_0xd3_PRIVILEGE_CTG 12914 12915 #define MC_CMD_0xd3_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12916 12917 /* MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN msgrequest */ 12918 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_LEN 8 12919 /* features to query (LICENSED_V3_FEATURES_xxx) expressed as a mask with one or 12920 * more bits set 12921 */ 12922 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_OFST 0 12923 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LEN 8 12924 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LO_OFST 0 12925 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_HI_OFST 4 12926 12927 /* MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT msgresponse */ 12928 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_LEN 8 12929 /* states of these features - bit set for licensed, clear for not licensed */ 12930 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_OFST 0 12931 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LEN 8 12932 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LO_OFST 0 12933 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_HI_OFST 4 12934 12935 12936 /***********************************/ 12937 /* MC_CMD_LICENSED_APP_OP 12938 * Perform an action for an individual licensed application - not used for V3 12939 * licensing. 12940 */ 12941 #define MC_CMD_LICENSED_APP_OP 0xf6 12942 #undef MC_CMD_0xf6_PRIVILEGE_CTG 12943 12944 #define MC_CMD_0xf6_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12945 12946 /* MC_CMD_LICENSED_APP_OP_IN msgrequest */ 12947 #define MC_CMD_LICENSED_APP_OP_IN_LENMIN 8 12948 #define MC_CMD_LICENSED_APP_OP_IN_LENMAX 252 12949 #define MC_CMD_LICENSED_APP_OP_IN_LEN(num) (8+4*(num)) 12950 /* application ID */ 12951 #define MC_CMD_LICENSED_APP_OP_IN_APP_ID_OFST 0 12952 /* the type of operation requested */ 12953 #define MC_CMD_LICENSED_APP_OP_IN_OP_OFST 4 12954 /* enum: validate application */ 12955 #define MC_CMD_LICENSED_APP_OP_IN_OP_VALIDATE 0x0 12956 /* enum: mask application */ 12957 #define MC_CMD_LICENSED_APP_OP_IN_OP_MASK 0x1 12958 /* arguments specific to this particular operation */ 12959 #define MC_CMD_LICENSED_APP_OP_IN_ARGS_OFST 8 12960 #define MC_CMD_LICENSED_APP_OP_IN_ARGS_LEN 4 12961 #define MC_CMD_LICENSED_APP_OP_IN_ARGS_MINNUM 0 12962 #define MC_CMD_LICENSED_APP_OP_IN_ARGS_MAXNUM 61 12963 12964 /* MC_CMD_LICENSED_APP_OP_OUT msgresponse */ 12965 #define MC_CMD_LICENSED_APP_OP_OUT_LENMIN 0 12966 #define MC_CMD_LICENSED_APP_OP_OUT_LENMAX 252 12967 #define MC_CMD_LICENSED_APP_OP_OUT_LEN(num) (0+4*(num)) 12968 /* result specific to this particular operation */ 12969 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_OFST 0 12970 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_LEN 4 12971 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_MINNUM 0 12972 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_MAXNUM 63 12973 12974 /* MC_CMD_LICENSED_APP_OP_VALIDATE_IN msgrequest */ 12975 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_LEN 72 12976 /* application ID */ 12977 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_APP_ID_OFST 0 12978 /* the type of operation requested */ 12979 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_OP_OFST 4 12980 /* validation challenge */ 12981 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_CHALLENGE_OFST 8 12982 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_CHALLENGE_LEN 64 12983 12984 /* MC_CMD_LICENSED_APP_OP_VALIDATE_OUT msgresponse */ 12985 #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_LEN 68 12986 /* feature expiry (time_t) */ 12987 #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_EXPIRY_OFST 0 12988 /* validation response */ 12989 #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_RESPONSE_OFST 4 12990 #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_RESPONSE_LEN 64 12991 12992 /* MC_CMD_LICENSED_APP_OP_MASK_IN msgrequest */ 12993 #define MC_CMD_LICENSED_APP_OP_MASK_IN_LEN 12 12994 /* application ID */ 12995 #define MC_CMD_LICENSED_APP_OP_MASK_IN_APP_ID_OFST 0 12996 /* the type of operation requested */ 12997 #define MC_CMD_LICENSED_APP_OP_MASK_IN_OP_OFST 4 12998 /* flag */ 12999 #define MC_CMD_LICENSED_APP_OP_MASK_IN_FLAG_OFST 8 13000 13001 /* MC_CMD_LICENSED_APP_OP_MASK_OUT msgresponse */ 13002 #define MC_CMD_LICENSED_APP_OP_MASK_OUT_LEN 0 13003 13004 13005 /***********************************/ 13006 /* MC_CMD_LICENSED_V3_VALIDATE_APP 13007 * Perform validation for an individual licensed application - V3 licensing 13008 * (Medford) 13009 */ 13010 #define MC_CMD_LICENSED_V3_VALIDATE_APP 0xd4 13011 #undef MC_CMD_0xd4_PRIVILEGE_CTG 13012 13013 #define MC_CMD_0xd4_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13014 13015 /* MC_CMD_LICENSED_V3_VALIDATE_APP_IN msgrequest */ 13016 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_LEN 72 13017 /* application ID expressed as a single bit mask */ 13018 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_OFST 0 13019 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LEN 8 13020 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LO_OFST 0 13021 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_HI_OFST 4 13022 /* challenge for validation */ 13023 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_CHALLENGE_OFST 8 13024 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_CHALLENGE_LEN 64 13025 13026 /* MC_CMD_LICENSED_V3_VALIDATE_APP_OUT msgresponse */ 13027 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_LEN 72 13028 /* application expiry time */ 13029 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_TIME_OFST 0 13030 /* application expiry units */ 13031 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNITS_OFST 4 13032 /* enum: expiry units are accounting units */ 13033 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNIT_ACC 0x0 13034 /* enum: expiry units are calendar days */ 13035 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNIT_DAYS 0x1 13036 /* validation response to challenge */ 13037 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_RESPONSE_OFST 8 13038 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_RESPONSE_LEN 64 13039 13040 13041 /***********************************/ 13042 /* MC_CMD_LICENSED_V3_MASK_FEATURES 13043 * Mask features - V3 licensing (Medford) 13044 */ 13045 #define MC_CMD_LICENSED_V3_MASK_FEATURES 0xd5 13046 #undef MC_CMD_0xd5_PRIVILEGE_CTG 13047 13048 #define MC_CMD_0xd5_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13049 13050 /* MC_CMD_LICENSED_V3_MASK_FEATURES_IN msgrequest */ 13051 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_LEN 12 13052 /* mask to be applied to features to be changed */ 13053 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_OFST 0 13054 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LEN 8 13055 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LO_OFST 0 13056 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_HI_OFST 4 13057 /* whether to turn on or turn off the masked features */ 13058 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_FLAG_OFST 8 13059 /* enum: turn the features off */ 13060 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_OFF 0x0 13061 /* enum: turn the features back on */ 13062 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_ON 0x1 13063 13064 /* MC_CMD_LICENSED_V3_MASK_FEATURES_OUT msgresponse */ 13065 #define MC_CMD_LICENSED_V3_MASK_FEATURES_OUT_LEN 0 13066 13067 13068 /***********************************/ 13069 /* MC_CMD_SET_PORT_SNIFF_CONFIG 13070 * Configure RX port sniffing for the physical port associated with the calling 13071 * function. Only a privileged function may change the port sniffing 13072 * configuration. A copy of all traffic delivered to the host (non-promiscuous 13073 * mode) or all traffic arriving at the port (promiscuous mode) may be 13074 * delivered to a specific queue, or a set of queues with RSS. 13075 */ 13076 #define MC_CMD_SET_PORT_SNIFF_CONFIG 0xf7 13077 #undef MC_CMD_0xf7_PRIVILEGE_CTG 13078 13079 #define MC_CMD_0xf7_PRIVILEGE_CTG SRIOV_CTG_ADMIN 13080 13081 /* MC_CMD_SET_PORT_SNIFF_CONFIG_IN msgrequest */ 13082 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_LEN 16 13083 /* configuration flags */ 13084 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_FLAGS_OFST 0 13085 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_ENABLE_LBN 0 13086 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_ENABLE_WIDTH 1 13087 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_PROMISCUOUS_LBN 1 13088 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_PROMISCUOUS_WIDTH 1 13089 /* receive queue handle (for RSS mode, this is the base queue) */ 13090 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_QUEUE_OFST 4 13091 /* receive mode */ 13092 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_OFST 8 13093 /* enum: receive to just the specified queue */ 13094 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_SIMPLE 0x0 13095 /* enum: receive to multiple queues using RSS context */ 13096 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_RSS 0x1 13097 /* RSS context (for RX_MODE_RSS) as returned by MC_CMD_RSS_CONTEXT_ALLOC. Note 13098 * that these handles should be considered opaque to the host, although a value 13099 * of 0xFFFFFFFF is guaranteed never to be a valid handle. 13100 */ 13101 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_OFST 12 13102 13103 /* MC_CMD_SET_PORT_SNIFF_CONFIG_OUT msgresponse */ 13104 #define MC_CMD_SET_PORT_SNIFF_CONFIG_OUT_LEN 0 13105 13106 13107 /***********************************/ 13108 /* MC_CMD_GET_PORT_SNIFF_CONFIG 13109 * Obtain the current RX port sniffing configuration for the physical port 13110 * associated with the calling function. Only a privileged function may read 13111 * the configuration. 13112 */ 13113 #define MC_CMD_GET_PORT_SNIFF_CONFIG 0xf8 13114 #undef MC_CMD_0xf8_PRIVILEGE_CTG 13115 13116 #define MC_CMD_0xf8_PRIVILEGE_CTG SRIOV_CTG_ADMIN 13117 13118 /* MC_CMD_GET_PORT_SNIFF_CONFIG_IN msgrequest */ 13119 #define MC_CMD_GET_PORT_SNIFF_CONFIG_IN_LEN 0 13120 13121 /* MC_CMD_GET_PORT_SNIFF_CONFIG_OUT msgresponse */ 13122 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_LEN 16 13123 /* configuration flags */ 13124 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_FLAGS_OFST 0 13125 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_ENABLE_LBN 0 13126 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_ENABLE_WIDTH 1 13127 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_PROMISCUOUS_LBN 1 13128 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_PROMISCUOUS_WIDTH 1 13129 /* receiving queue handle (for RSS mode, this is the base queue) */ 13130 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_OFST 4 13131 /* receive mode */ 13132 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_OFST 8 13133 /* enum: receiving to just the specified queue */ 13134 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_SIMPLE 0x0 13135 /* enum: receiving to multiple queues using RSS context */ 13136 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_RSS 0x1 13137 /* RSS context (for RX_MODE_RSS) */ 13138 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_OFST 12 13139 13140 13141 /***********************************/ 13142 /* MC_CMD_SET_PARSER_DISP_CONFIG 13143 * Change configuration related to the parser-dispatcher subsystem. 13144 */ 13145 #define MC_CMD_SET_PARSER_DISP_CONFIG 0xf9 13146 #undef MC_CMD_0xf9_PRIVILEGE_CTG 13147 13148 #define MC_CMD_0xf9_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13149 13150 /* MC_CMD_SET_PARSER_DISP_CONFIG_IN msgrequest */ 13151 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LENMIN 12 13152 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LENMAX 252 13153 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LEN(num) (8+4*(num)) 13154 /* the type of configuration setting to change */ 13155 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_TYPE_OFST 0 13156 /* enum: Per-TXQ enable for multicast UDP destination lookup for possible 13157 * internal loopback. (ENTITY is a queue handle, VALUE is a single boolean.) 13158 */ 13159 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_TXQ_MCAST_UDP_DST_LOOKUP_EN 0x0 13160 /* enum: Per-v-adaptor enable for suppression of self-transmissions on the 13161 * internal loopback path. (ENTITY is an EVB_PORT_ID, VALUE is a single 13162 * boolean.) 13163 */ 13164 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VADAPTOR_SUPPRESS_SELF_TX 0x1 13165 /* handle for the entity to update: queue handle, EVB port ID, etc. depending 13166 * on the type of configuration setting being changed 13167 */ 13168 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_ENTITY_OFST 4 13169 /* new value: the details depend on the type of configuration setting being 13170 * changed 13171 */ 13172 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_OFST 8 13173 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_LEN 4 13174 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_MINNUM 1 13175 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_MAXNUM 61 13176 13177 /* MC_CMD_SET_PARSER_DISP_CONFIG_OUT msgresponse */ 13178 #define MC_CMD_SET_PARSER_DISP_CONFIG_OUT_LEN 0 13179 13180 13181 /***********************************/ 13182 /* MC_CMD_GET_PARSER_DISP_CONFIG 13183 * Read configuration related to the parser-dispatcher subsystem. 13184 */ 13185 #define MC_CMD_GET_PARSER_DISP_CONFIG 0xfa 13186 #undef MC_CMD_0xfa_PRIVILEGE_CTG 13187 13188 #define MC_CMD_0xfa_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13189 13190 /* MC_CMD_GET_PARSER_DISP_CONFIG_IN msgrequest */ 13191 #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_LEN 8 13192 /* the type of configuration setting to read */ 13193 #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_TYPE_OFST 0 13194 /* Enum values, see field(s): */ 13195 /* MC_CMD_SET_PARSER_DISP_CONFIG/MC_CMD_SET_PARSER_DISP_CONFIG_IN/TYPE */ 13196 /* handle for the entity to query: queue handle, EVB port ID, etc. depending on 13197 * the type of configuration setting being read 13198 */ 13199 #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_ENTITY_OFST 4 13200 13201 /* MC_CMD_GET_PARSER_DISP_CONFIG_OUT msgresponse */ 13202 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LENMIN 4 13203 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LENMAX 252 13204 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LEN(num) (0+4*(num)) 13205 /* current value: the details depend on the type of configuration setting being 13206 * read 13207 */ 13208 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_OFST 0 13209 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_LEN 4 13210 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_MINNUM 1 13211 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_MAXNUM 63 13212 13213 13214 /***********************************/ 13215 /* MC_CMD_SET_TX_PORT_SNIFF_CONFIG 13216 * Configure TX port sniffing for the physical port associated with the calling 13217 * function. Only a privileged function may change the port sniffing 13218 * configuration. A copy of all traffic transmitted through the port may be 13219 * delivered to a specific queue, or a set of queues with RSS. Note that these 13220 * packets are delivered with transmit timestamps in the packet prefix, not 13221 * receive timestamps, so it is likely that the queue(s) will need to be 13222 * dedicated as TX sniff receivers. 13223 */ 13224 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG 0xfb 13225 #undef MC_CMD_0xfb_PRIVILEGE_CTG 13226 13227 #define MC_CMD_0xfb_PRIVILEGE_CTG SRIOV_CTG_ADMIN 13228 13229 /* MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN msgrequest */ 13230 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_LEN 16 13231 /* configuration flags */ 13232 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_FLAGS_OFST 0 13233 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_ENABLE_LBN 0 13234 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_ENABLE_WIDTH 1 13235 /* receive queue handle (for RSS mode, this is the base queue) */ 13236 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_QUEUE_OFST 4 13237 /* receive mode */ 13238 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_OFST 8 13239 /* enum: receive to just the specified queue */ 13240 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_SIMPLE 0x0 13241 /* enum: receive to multiple queues using RSS context */ 13242 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_RSS 0x1 13243 /* RSS context (for RX_MODE_RSS) as returned by MC_CMD_RSS_CONTEXT_ALLOC. Note 13244 * that these handles should be considered opaque to the host, although a value 13245 * of 0xFFFFFFFF is guaranteed never to be a valid handle. 13246 */ 13247 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_OFST 12 13248 13249 /* MC_CMD_SET_TX_PORT_SNIFF_CONFIG_OUT msgresponse */ 13250 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_OUT_LEN 0 13251 13252 13253 /***********************************/ 13254 /* MC_CMD_GET_TX_PORT_SNIFF_CONFIG 13255 * Obtain the current TX port sniffing configuration for the physical port 13256 * associated with the calling function. Only a privileged function may read 13257 * the configuration. 13258 */ 13259 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG 0xfc 13260 #undef MC_CMD_0xfc_PRIVILEGE_CTG 13261 13262 #define MC_CMD_0xfc_PRIVILEGE_CTG SRIOV_CTG_ADMIN 13263 13264 /* MC_CMD_GET_TX_PORT_SNIFF_CONFIG_IN msgrequest */ 13265 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_IN_LEN 0 13266 13267 /* MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT msgresponse */ 13268 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_LEN 16 13269 /* configuration flags */ 13270 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_FLAGS_OFST 0 13271 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_ENABLE_LBN 0 13272 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_ENABLE_WIDTH 1 13273 /* receiving queue handle (for RSS mode, this is the base queue) */ 13274 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_OFST 4 13275 /* receive mode */ 13276 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_OFST 8 13277 /* enum: receiving to just the specified queue */ 13278 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_SIMPLE 0x0 13279 /* enum: receiving to multiple queues using RSS context */ 13280 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_RSS 0x1 13281 /* RSS context (for RX_MODE_RSS) */ 13282 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_OFST 12 13283 13284 13285 /***********************************/ 13286 /* MC_CMD_RMON_STATS_RX_ERRORS 13287 * Per queue rx error stats. 13288 */ 13289 #define MC_CMD_RMON_STATS_RX_ERRORS 0xfe 13290 #undef MC_CMD_0xfe_PRIVILEGE_CTG 13291 13292 #define MC_CMD_0xfe_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13293 13294 /* MC_CMD_RMON_STATS_RX_ERRORS_IN msgrequest */ 13295 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_LEN 8 13296 /* The rx queue to get stats for. */ 13297 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_RX_QUEUE_OFST 0 13298 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_FLAGS_OFST 4 13299 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_RST_LBN 0 13300 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_RST_WIDTH 1 13301 13302 /* MC_CMD_RMON_STATS_RX_ERRORS_OUT msgresponse */ 13303 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_LEN 16 13304 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_CRC_ERRORS_OFST 0 13305 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_TRUNC_ERRORS_OFST 4 13306 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_NO_DESC_DROPS_OFST 8 13307 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_ABORT_OFST 12 13308 13309 13310 /***********************************/ 13311 /* MC_CMD_GET_PCIE_RESOURCE_INFO 13312 * Find out about available PCIE resources 13313 */ 13314 #define MC_CMD_GET_PCIE_RESOURCE_INFO 0xfd 13315 13316 /* MC_CMD_GET_PCIE_RESOURCE_INFO_IN msgrequest */ 13317 #define MC_CMD_GET_PCIE_RESOURCE_INFO_IN_LEN 0 13318 13319 /* MC_CMD_GET_PCIE_RESOURCE_INFO_OUT msgresponse */ 13320 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_LEN 28 13321 /* The maximum number of PFs the device can expose */ 13322 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PFS_OFST 0 13323 /* The maximum number of VFs the device can expose in total */ 13324 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VFS_OFST 4 13325 /* The maximum number of MSI-X vectors the device can provide in total */ 13326 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VECTORS_OFST 8 13327 /* the number of MSI-X vectors the device will allocate by default to each PF 13328 */ 13329 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_PF_VECTORS_OFST 12 13330 /* the number of MSI-X vectors the device will allocate by default to each VF 13331 */ 13332 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_VF_VECTORS_OFST 16 13333 /* the maximum number of MSI-X vectors the device can allocate to any one PF */ 13334 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PF_VECTORS_OFST 20 13335 /* the maximum number of MSI-X vectors the device can allocate to any one VF */ 13336 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VF_VECTORS_OFST 24 13337 13338 13339 /***********************************/ 13340 /* MC_CMD_GET_PORT_MODES 13341 * Find out about available port modes 13342 */ 13343 #define MC_CMD_GET_PORT_MODES 0xff 13344 #undef MC_CMD_0xff_PRIVILEGE_CTG 13345 13346 #define MC_CMD_0xff_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13347 13348 /* MC_CMD_GET_PORT_MODES_IN msgrequest */ 13349 #define MC_CMD_GET_PORT_MODES_IN_LEN 0 13350 13351 /* MC_CMD_GET_PORT_MODES_OUT msgresponse */ 13352 #define MC_CMD_GET_PORT_MODES_OUT_LEN 12 13353 /* Bitmask of port modes available on the board (indexed by TLV_PORT_MODE_*) */ 13354 #define MC_CMD_GET_PORT_MODES_OUT_MODES_OFST 0 13355 /* Default (canonical) board mode */ 13356 #define MC_CMD_GET_PORT_MODES_OUT_DEFAULT_MODE_OFST 4 13357 /* Current board mode */ 13358 #define MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST 8 13359 13360 13361 /***********************************/ 13362 /* MC_CMD_READ_ATB 13363 * Sample voltages on the ATB 13364 */ 13365 #define MC_CMD_READ_ATB 0x100 13366 #undef MC_CMD_0x100_PRIVILEGE_CTG 13367 13368 #define MC_CMD_0x100_PRIVILEGE_CTG SRIOV_CTG_ADMIN 13369 13370 /* MC_CMD_READ_ATB_IN msgrequest */ 13371 #define MC_CMD_READ_ATB_IN_LEN 16 13372 #define MC_CMD_READ_ATB_IN_SIGNAL_BUS_OFST 0 13373 #define MC_CMD_READ_ATB_IN_BUS_CCOM 0x0 /* enum */ 13374 #define MC_CMD_READ_ATB_IN_BUS_CKR 0x1 /* enum */ 13375 #define MC_CMD_READ_ATB_IN_BUS_CPCIE 0x8 /* enum */ 13376 #define MC_CMD_READ_ATB_IN_SIGNAL_EN_BITNO_OFST 4 13377 #define MC_CMD_READ_ATB_IN_SIGNAL_SEL_OFST 8 13378 #define MC_CMD_READ_ATB_IN_SETTLING_TIME_US_OFST 12 13379 13380 /* MC_CMD_READ_ATB_OUT msgresponse */ 13381 #define MC_CMD_READ_ATB_OUT_LEN 4 13382 #define MC_CMD_READ_ATB_OUT_SAMPLE_MV_OFST 0 13383 13384 13385 /***********************************/ 13386 /* MC_CMD_GET_WORKAROUNDS 13387 * Read the list of all implemented and all currently enabled workarounds. The 13388 * enums here must correspond with those in MC_CMD_WORKAROUND. 13389 */ 13390 #define MC_CMD_GET_WORKAROUNDS 0x59 13391 #undef MC_CMD_0x59_PRIVILEGE_CTG 13392 13393 #define MC_CMD_0x59_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13394 13395 /* MC_CMD_GET_WORKAROUNDS_OUT msgresponse */ 13396 #define MC_CMD_GET_WORKAROUNDS_OUT_LEN 8 13397 /* Each workaround is represented by a single bit according to the enums below. 13398 */ 13399 #define MC_CMD_GET_WORKAROUNDS_OUT_IMPLEMENTED_OFST 0 13400 #define MC_CMD_GET_WORKAROUNDS_OUT_ENABLED_OFST 4 13401 /* enum: Bug 17230 work around. */ 13402 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG17230 0x2 13403 /* enum: Bug 35388 work around (unsafe EVQ writes). */ 13404 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG35388 0x4 13405 /* enum: Bug35017 workaround (A64 tables must be identity map) */ 13406 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG35017 0x8 13407 /* enum: Bug 41750 present (MC_CMD_TRIGGER_INTERRUPT won't work) */ 13408 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG41750 0x10 13409 /* enum: Bug 42008 present (Interrupts can overtake associated events). Caution 13410 * - before adding code that queries this workaround, remember that there's 13411 * released Monza firmware that doesn't understand MC_CMD_WORKAROUND_BUG42008, 13412 * and will hence (incorrectly) report that the bug doesn't exist. 13413 */ 13414 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG42008 0x20 13415 /* enum: Bug 26807 features present in firmware (multicast filter chaining) */ 13416 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG26807 0x40 13417 13418 13419 /***********************************/ 13420 /* MC_CMD_PRIVILEGE_MASK 13421 * Read/set privileges of an arbitrary PCIe function 13422 */ 13423 #define MC_CMD_PRIVILEGE_MASK 0x5a 13424 #undef MC_CMD_0x5a_PRIVILEGE_CTG 13425 13426 #define MC_CMD_0x5a_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13427 13428 /* MC_CMD_PRIVILEGE_MASK_IN msgrequest */ 13429 #define MC_CMD_PRIVILEGE_MASK_IN_LEN 8 13430 /* The target function to have its mask read or set e.g. PF 0 = 0xFFFF0000, VF 13431 * 1,3 = 0x00030001 13432 */ 13433 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_OFST 0 13434 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_PF_LBN 0 13435 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_PF_WIDTH 16 13436 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_VF_LBN 16 13437 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_VF_WIDTH 16 13438 #define MC_CMD_PRIVILEGE_MASK_IN_VF_NULL 0xffff /* enum */ 13439 /* New privilege mask to be set. The mask will only be changed if the MSB is 13440 * set to 1. 13441 */ 13442 #define MC_CMD_PRIVILEGE_MASK_IN_NEW_MASK_OFST 4 13443 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN 0x1 /* enum */ 13444 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_LINK 0x2 /* enum */ 13445 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ONLOAD 0x4 /* enum */ 13446 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_PTP 0x8 /* enum */ 13447 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE_FILTERS 0x10 /* enum */ 13448 /* enum: Deprecated. Equivalent to MAC_SPOOFING_TX combined with CHANGE_MAC. */ 13449 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING 0x20 13450 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_UNICAST 0x40 /* enum */ 13451 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_MULTICAST 0x80 /* enum */ 13452 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_BROADCAST 0x100 /* enum */ 13453 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ALL_MULTICAST 0x200 /* enum */ 13454 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_PROMISCUOUS 0x400 /* enum */ 13455 /* enum: Allows to set the TX packets' source MAC address to any arbitrary MAC 13456 * address. 13457 */ 13458 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING_TX 0x800 13459 /* enum: Privilege that allows a Function to change the MAC address configured 13460 * in its associated vAdapter/vPort. 13461 */ 13462 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_CHANGE_MAC 0x1000 13463 /* enum: Privilege that allows a Function to install filters that specify VLANs 13464 * that are not in the permit list for the associated vPort. This privilege is 13465 * primarily to support ESX where vPorts are created that restrict traffic to 13466 * only a set of permitted VLANs. See the vPort flag FLAG_VLAN_RESTRICT. 13467 */ 13468 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_UNRESTRICTED_VLAN 0x2000 13469 /* enum: Set this bit to indicate that a new privilege mask is to be set, 13470 * otherwise the command will only read the existing mask. 13471 */ 13472 #define MC_CMD_PRIVILEGE_MASK_IN_DO_CHANGE 0x80000000 13473 13474 /* MC_CMD_PRIVILEGE_MASK_OUT msgresponse */ 13475 #define MC_CMD_PRIVILEGE_MASK_OUT_LEN 4 13476 /* For an admin function, always all the privileges are reported. */ 13477 #define MC_CMD_PRIVILEGE_MASK_OUT_OLD_MASK_OFST 0 13478 13479 13480 /***********************************/ 13481 /* MC_CMD_LINK_STATE_MODE 13482 * Read/set link state mode of a VF 13483 */ 13484 #define MC_CMD_LINK_STATE_MODE 0x5c 13485 #undef MC_CMD_0x5c_PRIVILEGE_CTG 13486 13487 #define MC_CMD_0x5c_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13488 13489 /* MC_CMD_LINK_STATE_MODE_IN msgrequest */ 13490 #define MC_CMD_LINK_STATE_MODE_IN_LEN 8 13491 /* The target function to have its link state mode read or set, must be a VF 13492 * e.g. VF 1,3 = 0x00030001 13493 */ 13494 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_OFST 0 13495 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_LBN 0 13496 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_WIDTH 16 13497 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_VF_LBN 16 13498 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_VF_WIDTH 16 13499 /* New link state mode to be set */ 13500 #define MC_CMD_LINK_STATE_MODE_IN_NEW_MODE_OFST 4 13501 #define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_AUTO 0x0 /* enum */ 13502 #define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_UP 0x1 /* enum */ 13503 #define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_DOWN 0x2 /* enum */ 13504 /* enum: Use this value to just read the existing setting without modifying it. 13505 */ 13506 #define MC_CMD_LINK_STATE_MODE_IN_DO_NOT_CHANGE 0xffffffff 13507 13508 /* MC_CMD_LINK_STATE_MODE_OUT msgresponse */ 13509 #define MC_CMD_LINK_STATE_MODE_OUT_LEN 4 13510 #define MC_CMD_LINK_STATE_MODE_OUT_OLD_MODE_OFST 0 13511 13512 13513 /***********************************/ 13514 /* MC_CMD_GET_SNAPSHOT_LENGTH 13515 * Obtain the curent range of allowable values for the SNAPSHOT_LENGTH 13516 * parameter to MC_CMD_INIT_RXQ. 13517 */ 13518 #define MC_CMD_GET_SNAPSHOT_LENGTH 0x101 13519 #undef MC_CMD_0x101_PRIVILEGE_CTG 13520 13521 #define MC_CMD_0x101_PRIVILEGE_CTG SRIOV_CTG_GENERAL 13522 13523 /* MC_CMD_GET_SNAPSHOT_LENGTH_IN msgrequest */ 13524 #define MC_CMD_GET_SNAPSHOT_LENGTH_IN_LEN 0 13525 13526 /* MC_CMD_GET_SNAPSHOT_LENGTH_OUT msgresponse */ 13527 #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_LEN 8 13528 /* Minimum acceptable snapshot length. */ 13529 #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MIN_OFST 0 13530 /* Maximum acceptable snapshot length. */ 13531 #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MAX_OFST 4 13532 13533 13534 /***********************************/ 13535 /* MC_CMD_FUSE_DIAGS 13536 * Additional fuse diagnostics 13537 */ 13538 #define MC_CMD_FUSE_DIAGS 0x102 13539 #undef MC_CMD_0x102_PRIVILEGE_CTG 13540 13541 #define MC_CMD_0x102_PRIVILEGE_CTG SRIOV_CTG_ADMIN 13542 13543 /* MC_CMD_FUSE_DIAGS_IN msgrequest */ 13544 #define MC_CMD_FUSE_DIAGS_IN_LEN 0 13545 13546 /* MC_CMD_FUSE_DIAGS_OUT msgresponse */ 13547 #define MC_CMD_FUSE_DIAGS_OUT_LEN 48 13548 /* Total number of mismatched bits between pairs in area 0 */ 13549 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_MISMATCH_BITS_OFST 0 13550 /* Total number of unexpectedly clear (set in B but not A) bits in area 0 */ 13551 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_A_BAD_BITS_OFST 4 13552 /* Total number of unexpectedly clear (set in A but not B) bits in area 0 */ 13553 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_B_BAD_BITS_OFST 8 13554 /* Checksum of data after logical OR of pairs in area 0 */ 13555 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_CHECKSUM_OFST 12 13556 /* Total number of mismatched bits between pairs in area 1 */ 13557 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_MISMATCH_BITS_OFST 16 13558 /* Total number of unexpectedly clear (set in B but not A) bits in area 1 */ 13559 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_A_BAD_BITS_OFST 20 13560 /* Total number of unexpectedly clear (set in A but not B) bits in area 1 */ 13561 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_B_BAD_BITS_OFST 24 13562 /* Checksum of data after logical OR of pairs in area 1 */ 13563 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_CHECKSUM_OFST 28 13564 /* Total number of mismatched bits between pairs in area 2 */ 13565 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_MISMATCH_BITS_OFST 32 13566 /* Total number of unexpectedly clear (set in B but not A) bits in area 2 */ 13567 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_A_BAD_BITS_OFST 36 13568 /* Total number of unexpectedly clear (set in A but not B) bits in area 2 */ 13569 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_B_BAD_BITS_OFST 40 13570 /* Checksum of data after logical OR of pairs in area 2 */ 13571 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_CHECKSUM_OFST 44 13572 13573 13574 /***********************************/ 13575 /* MC_CMD_PRIVILEGE_MODIFY 13576 * Modify the privileges of a set of PCIe functions. Note that this operation 13577 * only effects non-admin functions unless the admin privilege itself is 13578 * included in one of the masks provided. 13579 */ 13580 #define MC_CMD_PRIVILEGE_MODIFY 0x60 13581 #undef MC_CMD_0x60_PRIVILEGE_CTG 13582 13583 #define MC_CMD_0x60_PRIVILEGE_CTG SRIOV_CTG_ADMIN 13584 13585 /* MC_CMD_PRIVILEGE_MODIFY_IN msgrequest */ 13586 #define MC_CMD_PRIVILEGE_MODIFY_IN_LEN 16 13587 /* The groups of functions to have their privilege masks modified. */ 13588 #define MC_CMD_PRIVILEGE_MODIFY_IN_FN_GROUP_OFST 0 13589 #define MC_CMD_PRIVILEGE_MODIFY_IN_NONE 0x0 /* enum */ 13590 #define MC_CMD_PRIVILEGE_MODIFY_IN_ALL 0x1 /* enum */ 13591 #define MC_CMD_PRIVILEGE_MODIFY_IN_PFS_ONLY 0x2 /* enum */ 13592 #define MC_CMD_PRIVILEGE_MODIFY_IN_VFS_ONLY 0x3 /* enum */ 13593 #define MC_CMD_PRIVILEGE_MODIFY_IN_VFS_OF_PF 0x4 /* enum */ 13594 #define MC_CMD_PRIVILEGE_MODIFY_IN_ONE 0x5 /* enum */ 13595 /* For VFS_OF_PF specify the PF, for ONE specify the target function */ 13596 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_OFST 4 13597 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_PF_LBN 0 13598 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_PF_WIDTH 16 13599 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_VF_LBN 16 13600 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_VF_WIDTH 16 13601 /* Privileges to be added to the target functions. For privilege definitions 13602 * refer to the command MC_CMD_PRIVILEGE_MASK 13603 */ 13604 #define MC_CMD_PRIVILEGE_MODIFY_IN_ADD_MASK_OFST 8 13605 /* Privileges to be removed from the target functions. For privilege 13606 * definitions refer to the command MC_CMD_PRIVILEGE_MASK 13607 */ 13608 #define MC_CMD_PRIVILEGE_MODIFY_IN_REMOVE_MASK_OFST 12 13609 13610 /* MC_CMD_PRIVILEGE_MODIFY_OUT msgresponse */ 13611 #define MC_CMD_PRIVILEGE_MODIFY_OUT_LEN 0 13612 13613 13614 /***********************************/ 13615 /* MC_CMD_XPM_READ_BYTES 13616 * Read XPM memory 13617 */ 13618 #define MC_CMD_XPM_READ_BYTES 0x103 13619 #undef MC_CMD_0x103_PRIVILEGE_CTG 13620 13621 #define MC_CMD_0x103_PRIVILEGE_CTG SRIOV_CTG_ADMIN 13622 13623 /* MC_CMD_XPM_READ_BYTES_IN msgrequest */ 13624 #define MC_CMD_XPM_READ_BYTES_IN_LEN 8 13625 /* Start address (byte) */ 13626 #define MC_CMD_XPM_READ_BYTES_IN_ADDR_OFST 0 13627 /* Count (bytes) */ 13628 #define MC_CMD_XPM_READ_BYTES_IN_COUNT_OFST 4 13629 13630 /* MC_CMD_XPM_READ_BYTES_OUT msgresponse */ 13631 #define MC_CMD_XPM_READ_BYTES_OUT_LENMIN 0 13632 #define MC_CMD_XPM_READ_BYTES_OUT_LENMAX 252 13633 #define MC_CMD_XPM_READ_BYTES_OUT_LEN(num) (0+1*(num)) 13634 /* Data */ 13635 #define MC_CMD_XPM_READ_BYTES_OUT_DATA_OFST 0 13636 #define MC_CMD_XPM_READ_BYTES_OUT_DATA_LEN 1 13637 #define MC_CMD_XPM_READ_BYTES_OUT_DATA_MINNUM 0 13638 #define MC_CMD_XPM_READ_BYTES_OUT_DATA_MAXNUM 252 13639 13640 13641 /***********************************/ 13642 /* MC_CMD_XPM_WRITE_BYTES 13643 * Write XPM memory 13644 */ 13645 #define MC_CMD_XPM_WRITE_BYTES 0x104 13646 #undef MC_CMD_0x104_PRIVILEGE_CTG 13647 13648 #define MC_CMD_0x104_PRIVILEGE_CTG SRIOV_CTG_ADMIN 13649 13650 /* MC_CMD_XPM_WRITE_BYTES_IN msgrequest */ 13651 #define MC_CMD_XPM_WRITE_BYTES_IN_LENMIN 8 13652 #define MC_CMD_XPM_WRITE_BYTES_IN_LENMAX 252 13653 #define MC_CMD_XPM_WRITE_BYTES_IN_LEN(num) (8+1*(num)) 13654 /* Start address (byte) */ 13655 #define MC_CMD_XPM_WRITE_BYTES_IN_ADDR_OFST 0 13656 /* Count (bytes) */ 13657 #define MC_CMD_XPM_WRITE_BYTES_IN_COUNT_OFST 4 13658 /* Data */ 13659 #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_OFST 8 13660 #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_LEN 1 13661 #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_MINNUM 0 13662 #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_MAXNUM 244 13663 13664 /* MC_CMD_XPM_WRITE_BYTES_OUT msgresponse */ 13665 #define MC_CMD_XPM_WRITE_BYTES_OUT_LEN 0 13666 13667 13668 /***********************************/ 13669 /* MC_CMD_XPM_READ_SECTOR 13670 * Read XPM sector 13671 */ 13672 #define MC_CMD_XPM_READ_SECTOR 0x105 13673 #undef MC_CMD_0x105_PRIVILEGE_CTG 13674 13675 #define MC_CMD_0x105_PRIVILEGE_CTG SRIOV_CTG_ADMIN 13676 13677 /* MC_CMD_XPM_READ_SECTOR_IN msgrequest */ 13678 #define MC_CMD_XPM_READ_SECTOR_IN_LEN 8 13679 /* Sector index */ 13680 #define MC_CMD_XPM_READ_SECTOR_IN_INDEX_OFST 0 13681 /* Sector size */ 13682 #define MC_CMD_XPM_READ_SECTOR_IN_SIZE_OFST 4 13683 13684 /* MC_CMD_XPM_READ_SECTOR_OUT msgresponse */ 13685 #define MC_CMD_XPM_READ_SECTOR_OUT_LENMIN 4 13686 #define MC_CMD_XPM_READ_SECTOR_OUT_LENMAX 36 13687 #define MC_CMD_XPM_READ_SECTOR_OUT_LEN(num) (4+1*(num)) 13688 /* Sector type */ 13689 #define MC_CMD_XPM_READ_SECTOR_OUT_TYPE_OFST 0 13690 #define MC_CMD_XPM_READ_SECTOR_OUT_BLANK 0x0 /* enum */ 13691 #define MC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_KEY_128 0x1 /* enum */ 13692 #define MC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_KEY_256 0x2 /* enum */ 13693 #define MC_CMD_XPM_READ_SECTOR_OUT_INVALID 0xff /* enum */ 13694 /* Sector data */ 13695 #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_OFST 4 13696 #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_LEN 1 13697 #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_MINNUM 0 13698 #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_MAXNUM 32 13699 13700 13701 /***********************************/ 13702 /* MC_CMD_XPM_WRITE_SECTOR 13703 * Write XPM sector 13704 */ 13705 #define MC_CMD_XPM_WRITE_SECTOR 0x106 13706 #undef MC_CMD_0x106_PRIVILEGE_CTG 13707 13708 #define MC_CMD_0x106_PRIVILEGE_CTG SRIOV_CTG_ADMIN 13709 13710 /* MC_CMD_XPM_WRITE_SECTOR_IN msgrequest */ 13711 #define MC_CMD_XPM_WRITE_SECTOR_IN_LENMIN 12 13712 #define MC_CMD_XPM_WRITE_SECTOR_IN_LENMAX 44 13713 #define MC_CMD_XPM_WRITE_SECTOR_IN_LEN(num) (12+1*(num)) 13714 /* If writing fails due to an uncorrectable error, try up to RETRIES following 13715 * sectors (or until no more space available). If 0, only one write attempt is 13716 * made. Note that uncorrectable errors are unlikely, thanks to XPM self-repair 13717 * mechanism. 13718 */ 13719 #define MC_CMD_XPM_WRITE_SECTOR_IN_RETRIES_OFST 0 13720 #define MC_CMD_XPM_WRITE_SECTOR_IN_RETRIES_LEN 1 13721 #define MC_CMD_XPM_WRITE_SECTOR_IN_RESERVED_OFST 1 13722 #define MC_CMD_XPM_WRITE_SECTOR_IN_RESERVED_LEN 3 13723 /* Sector type */ 13724 #define MC_CMD_XPM_WRITE_SECTOR_IN_TYPE_OFST 4 13725 /* Enum values, see field(s): */ 13726 /* MC_CMD_XPM_READ_SECTOR/MC_CMD_XPM_READ_SECTOR_OUT/TYPE */ 13727 /* Sector size */ 13728 #define MC_CMD_XPM_WRITE_SECTOR_IN_SIZE_OFST 8 13729 /* Sector data */ 13730 #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_OFST 12 13731 #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_LEN 1 13732 #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_MINNUM 0 13733 #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_MAXNUM 32 13734 13735 /* MC_CMD_XPM_WRITE_SECTOR_OUT msgresponse */ 13736 #define MC_CMD_XPM_WRITE_SECTOR_OUT_LEN 4 13737 /* New sector index */ 13738 #define MC_CMD_XPM_WRITE_SECTOR_OUT_INDEX_OFST 0 13739 13740 13741 /***********************************/ 13742 /* MC_CMD_XPM_INVALIDATE_SECTOR 13743 * Invalidate XPM sector 13744 */ 13745 #define MC_CMD_XPM_INVALIDATE_SECTOR 0x107 13746 #undef MC_CMD_0x107_PRIVILEGE_CTG 13747 13748 #define MC_CMD_0x107_PRIVILEGE_CTG SRIOV_CTG_ADMIN 13749 13750 /* MC_CMD_XPM_INVALIDATE_SECTOR_IN msgrequest */ 13751 #define MC_CMD_XPM_INVALIDATE_SECTOR_IN_LEN 4 13752 /* Sector index */ 13753 #define MC_CMD_XPM_INVALIDATE_SECTOR_IN_INDEX_OFST 0 13754 13755 /* MC_CMD_XPM_INVALIDATE_SECTOR_OUT msgresponse */ 13756 #define MC_CMD_XPM_INVALIDATE_SECTOR_OUT_LEN 0 13757 13758 13759 /***********************************/ 13760 /* MC_CMD_XPM_BLANK_CHECK 13761 * Blank-check XPM memory and report bad locations 13762 */ 13763 #define MC_CMD_XPM_BLANK_CHECK 0x108 13764 #undef MC_CMD_0x108_PRIVILEGE_CTG 13765 13766 #define MC_CMD_0x108_PRIVILEGE_CTG SRIOV_CTG_ADMIN 13767 13768 /* MC_CMD_XPM_BLANK_CHECK_IN msgrequest */ 13769 #define MC_CMD_XPM_BLANK_CHECK_IN_LEN 8 13770 /* Start address (byte) */ 13771 #define MC_CMD_XPM_BLANK_CHECK_IN_ADDR_OFST 0 13772 /* Count (bytes) */ 13773 #define MC_CMD_XPM_BLANK_CHECK_IN_COUNT_OFST 4 13774 13775 /* MC_CMD_XPM_BLANK_CHECK_OUT msgresponse */ 13776 #define MC_CMD_XPM_BLANK_CHECK_OUT_LENMIN 4 13777 #define MC_CMD_XPM_BLANK_CHECK_OUT_LENMAX 252 13778 #define MC_CMD_XPM_BLANK_CHECK_OUT_LEN(num) (4+2*(num)) 13779 /* Total number of bad (non-blank) locations */ 13780 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_COUNT_OFST 0 13781 /* Addresses of bad locations (may be less than BAD_COUNT, if all cannot fit 13782 * into MCDI response) 13783 */ 13784 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_OFST 4 13785 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_LEN 2 13786 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_MINNUM 0 13787 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_MAXNUM 124 13788 13789 13790 /***********************************/ 13791 /* MC_CMD_XPM_REPAIR 13792 * Blank-check and repair XPM memory 13793 */ 13794 #define MC_CMD_XPM_REPAIR 0x109 13795 #undef MC_CMD_0x109_PRIVILEGE_CTG 13796 13797 #define MC_CMD_0x109_PRIVILEGE_CTG SRIOV_CTG_ADMIN 13798 13799 /* MC_CMD_XPM_REPAIR_IN msgrequest */ 13800 #define MC_CMD_XPM_REPAIR_IN_LEN 8 13801 /* Start address (byte) */ 13802 #define MC_CMD_XPM_REPAIR_IN_ADDR_OFST 0 13803 /* Count (bytes) */ 13804 #define MC_CMD_XPM_REPAIR_IN_COUNT_OFST 4 13805 13806 /* MC_CMD_XPM_REPAIR_OUT msgresponse */ 13807 #define MC_CMD_XPM_REPAIR_OUT_LEN 0 13808 13809 13810 /***********************************/ 13811 /* MC_CMD_XPM_DECODER_TEST 13812 * Test XPM memory address decoders for gross manufacturing defects. Can only 13813 * be performed on an unprogrammed part. 13814 */ 13815 #define MC_CMD_XPM_DECODER_TEST 0x10a 13816 #undef MC_CMD_0x10a_PRIVILEGE_CTG 13817 13818 #define MC_CMD_0x10a_PRIVILEGE_CTG SRIOV_CTG_ADMIN 13819 13820 /* MC_CMD_XPM_DECODER_TEST_IN msgrequest */ 13821 #define MC_CMD_XPM_DECODER_TEST_IN_LEN 0 13822 13823 /* MC_CMD_XPM_DECODER_TEST_OUT msgresponse */ 13824 #define MC_CMD_XPM_DECODER_TEST_OUT_LEN 0 13825 13826 13827 /***********************************/ 13828 /* MC_CMD_XPM_WRITE_TEST 13829 * XPM memory write test. Test XPM write logic for gross manufacturing defects 13830 * by writing to a dedicated test row. There are 16 locations in the test row 13831 * and the test can only be performed on locations that have not been 13832 * previously used (i.e. can be run at most 16 times). The test will pick the 13833 * first available location to use, or fail with ENOSPC if none left. 13834 */ 13835 #define MC_CMD_XPM_WRITE_TEST 0x10b 13836 #undef MC_CMD_0x10b_PRIVILEGE_CTG 13837 13838 #define MC_CMD_0x10b_PRIVILEGE_CTG SRIOV_CTG_ADMIN 13839 13840 /* MC_CMD_XPM_WRITE_TEST_IN msgrequest */ 13841 #define MC_CMD_XPM_WRITE_TEST_IN_LEN 0 13842 13843 /* MC_CMD_XPM_WRITE_TEST_OUT msgresponse */ 13844 #define MC_CMD_XPM_WRITE_TEST_OUT_LEN 0 13845 13846 13847 /***********************************/ 13848 /* MC_CMD_EXEC_SIGNED 13849 * Check the CMAC of the contents of IMEM and DMEM against the value supplied 13850 * and if correct begin execution from the start of IMEM. The caller supplies a 13851 * key ID, the length of IMEM and DMEM to validate and the expected CMAC. CMAC 13852 * computation runs from the start of IMEM, and from the start of DMEM + 16k, 13853 * to match flash booting. The command will respond with EINVAL if the CMAC 13854 * does match, otherwise it will respond with success before it jumps to IMEM. 13855 */ 13856 #define MC_CMD_EXEC_SIGNED 0x10c 13857 #undef MC_CMD_0x10c_PRIVILEGE_CTG 13858 13859 #define MC_CMD_0x10c_PRIVILEGE_CTG SRIOV_CTG_ADMIN 13860 13861 /* MC_CMD_EXEC_SIGNED_IN msgrequest */ 13862 #define MC_CMD_EXEC_SIGNED_IN_LEN 28 13863 /* the length of code to include in the CMAC */ 13864 #define MC_CMD_EXEC_SIGNED_IN_CODELEN_OFST 0 13865 /* the length of date to include in the CMAC */ 13866 #define MC_CMD_EXEC_SIGNED_IN_DATALEN_OFST 4 13867 /* the XPM sector containing the key to use */ 13868 #define MC_CMD_EXEC_SIGNED_IN_KEYSECTOR_OFST 8 13869 /* the expected CMAC value */ 13870 #define MC_CMD_EXEC_SIGNED_IN_CMAC_OFST 12 13871 #define MC_CMD_EXEC_SIGNED_IN_CMAC_LEN 16 13872 13873 /* MC_CMD_EXEC_SIGNED_OUT msgresponse */ 13874 #define MC_CMD_EXEC_SIGNED_OUT_LEN 0 13875 13876 13877 /***********************************/ 13878 /* MC_CMD_PREPARE_SIGNED 13879 * Prepare to upload a signed image. This will scrub the specified length of 13880 * the data region, which must be at least as large as the DATALEN supplied to 13881 * MC_CMD_EXEC_SIGNED. 13882 */ 13883 #define MC_CMD_PREPARE_SIGNED 0x10d 13884 #undef MC_CMD_0x10d_PRIVILEGE_CTG 13885 13886 #define MC_CMD_0x10d_PRIVILEGE_CTG SRIOV_CTG_ADMIN 13887 13888 /* MC_CMD_PREPARE_SIGNED_IN msgrequest */ 13889 #define MC_CMD_PREPARE_SIGNED_IN_LEN 4 13890 /* the length of data area to clear */ 13891 #define MC_CMD_PREPARE_SIGNED_IN_DATALEN_OFST 0 13892 13893 /* MC_CMD_PREPARE_SIGNED_OUT msgresponse */ 13894 #define MC_CMD_PREPARE_SIGNED_OUT_LEN 0 13895 13896 13897 /***********************************/ 13898 /* MC_CMD_SET_SECURITY_RULE 13899 * Set blacklist and/or whitelist action for a particular match criteria. 13900 * (Medford-only; for use by SolarSecure apps, not directly by drivers. See 13901 * SF-114946-SW.) NOTE - this message definition is provisional. It has not yet 13902 * been used in any released code and may change during development. This note 13903 * will be removed once it is regarded as stable. 13904 */ 13905 #define MC_CMD_SET_SECURITY_RULE 0x10f 13906 #undef MC_CMD_0x10f_PRIVILEGE_CTG 13907 13908 #define MC_CMD_0x10f_PRIVILEGE_CTG SRIOV_CTG_ADMIN 13909 13910 /* MC_CMD_SET_SECURITY_RULE_IN msgrequest */ 13911 #define MC_CMD_SET_SECURITY_RULE_IN_LEN 92 13912 /* fields to include in match criteria */ 13913 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_FIELDS_OFST 0 13914 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_IP_LBN 0 13915 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_IP_WIDTH 1 13916 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_IP_LBN 1 13917 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_IP_WIDTH 1 13918 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_MAC_LBN 2 13919 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_MAC_WIDTH 1 13920 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_PORT_LBN 3 13921 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_PORT_WIDTH 1 13922 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_MAC_LBN 4 13923 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_MAC_WIDTH 1 13924 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_PORT_LBN 5 13925 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_PORT_WIDTH 1 13926 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_ETHER_TYPE_LBN 6 13927 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_ETHER_TYPE_WIDTH 1 13928 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_INNER_VLAN_LBN 7 13929 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_INNER_VLAN_WIDTH 1 13930 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_OUTER_VLAN_LBN 8 13931 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_OUTER_VLAN_WIDTH 1 13932 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_IP_PROTO_LBN 9 13933 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_IP_PROTO_WIDTH 1 13934 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_PHYSICAL_PORT_LBN 10 13935 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_PHYSICAL_PORT_WIDTH 1 13936 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_RESERVED_LBN 11 13937 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_RESERVED_WIDTH 1 13938 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_SUBNET_ID_LBN 12 13939 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_SUBNET_ID_WIDTH 1 13940 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_PORTRANGE_ID_LBN 13 13941 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_PORTRANGE_ID_WIDTH 1 13942 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_PORTRANGE_ID_LBN 14 13943 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_LOCAL_PORTRANGE_ID_WIDTH 1 13944 /* remote MAC address to match (as bytes in network order) */ 13945 #define MC_CMD_SET_SECURITY_RULE_IN_REMOTE_MAC_OFST 4 13946 #define MC_CMD_SET_SECURITY_RULE_IN_REMOTE_MAC_LEN 6 13947 /* remote port to match (as bytes in network order) */ 13948 #define MC_CMD_SET_SECURITY_RULE_IN_REMOTE_PORT_OFST 10 13949 #define MC_CMD_SET_SECURITY_RULE_IN_REMOTE_PORT_LEN 2 13950 /* local MAC address to match (as bytes in network order) */ 13951 #define MC_CMD_SET_SECURITY_RULE_IN_LOCAL_MAC_OFST 12 13952 #define MC_CMD_SET_SECURITY_RULE_IN_LOCAL_MAC_LEN 6 13953 /* local port to match (as bytes in network order) */ 13954 #define MC_CMD_SET_SECURITY_RULE_IN_LOCAL_PORT_OFST 18 13955 #define MC_CMD_SET_SECURITY_RULE_IN_LOCAL_PORT_LEN 2 13956 /* Ethernet type to match (as bytes in network order) */ 13957 #define MC_CMD_SET_SECURITY_RULE_IN_ETHER_TYPE_OFST 20 13958 #define MC_CMD_SET_SECURITY_RULE_IN_ETHER_TYPE_LEN 2 13959 /* Inner VLAN tag to match (as bytes in network order) */ 13960 #define MC_CMD_SET_SECURITY_RULE_IN_INNER_VLAN_OFST 22 13961 #define MC_CMD_SET_SECURITY_RULE_IN_INNER_VLAN_LEN 2 13962 /* Outer VLAN tag to match (as bytes in network order) */ 13963 #define MC_CMD_SET_SECURITY_RULE_IN_OUTER_VLAN_OFST 24 13964 #define MC_CMD_SET_SECURITY_RULE_IN_OUTER_VLAN_LEN 2 13965 /* IP protocol to match (in low byte; set high byte to 0) */ 13966 #define MC_CMD_SET_SECURITY_RULE_IN_IP_PROTO_OFST 26 13967 #define MC_CMD_SET_SECURITY_RULE_IN_IP_PROTO_LEN 2 13968 /* Physical port to match (as little-endian 32-bit value) */ 13969 #define MC_CMD_SET_SECURITY_RULE_IN_PHYSICAL_PORT_OFST 28 13970 /* Reserved; set to 0 */ 13971 #define MC_CMD_SET_SECURITY_RULE_IN_RESERVED_OFST 32 13972 /* remote IP address to match (as bytes in network order; set last 12 bytes to 13973 * 0 for IPv4 address) 13974 */ 13975 #define MC_CMD_SET_SECURITY_RULE_IN_REMOTE_IP_OFST 36 13976 #define MC_CMD_SET_SECURITY_RULE_IN_REMOTE_IP_LEN 16 13977 /* local IP address to match (as bytes in network order; set last 12 bytes to 0 13978 * for IPv4 address) 13979 */ 13980 #define MC_CMD_SET_SECURITY_RULE_IN_LOCAL_IP_OFST 52 13981 #define MC_CMD_SET_SECURITY_RULE_IN_LOCAL_IP_LEN 16 13982 /* remote subnet ID to match (as little-endian 32-bit value); note that remote 13983 * subnets are matched by mapping the remote IP address to a "subnet ID" via a 13984 * data structure which must already have been configured using 13985 * MC_CMD_SUBNET_MAP_SET_NODE appropriately 13986 */ 13987 #define MC_CMD_SET_SECURITY_RULE_IN_REMOTE_SUBNET_ID_OFST 68 13988 /* remote portrange ID to match (as little-endian 32-bit value); note that 13989 * remote port ranges are matched by mapping the remote port to a "portrange 13990 * ID" via a data structure which must already have been configured using 13991 * MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE 13992 */ 13993 #define MC_CMD_SET_SECURITY_RULE_IN_REMOTE_PORTRANGE_ID_OFST 72 13994 /* local portrange ID to match (as little-endian 32-bit value); note that local 13995 * port ranges are matched by mapping the local port to a "portrange ID" via a 13996 * data structure which must already have been configured using 13997 * MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE 13998 */ 13999 #define MC_CMD_SET_SECURITY_RULE_IN_LOCAL_PORTRANGE_ID_OFST 76 14000 /* set the action for transmitted packets matching this rule */ 14001 #define MC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_OFST 80 14002 /* enum: make no decision */ 14003 #define MC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_NONE 0x0 14004 /* enum: decide to accept the packet */ 14005 #define MC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_WHITELIST 0x1 14006 /* enum: decide to drop the packet */ 14007 #define MC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_BLACKLIST 0x2 14008 /* enum: do not change the current TX action */ 14009 #define MC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_UNCHANGED 0xffffffff 14010 /* set the action for received packets matching this rule */ 14011 #define MC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_OFST 84 14012 /* enum: make no decision */ 14013 #define MC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_NONE 0x0 14014 /* enum: decide to accept the packet */ 14015 #define MC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_WHITELIST 0x1 14016 /* enum: decide to drop the packet */ 14017 #define MC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_BLACKLIST 0x2 14018 /* enum: do not change the current RX action */ 14019 #define MC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_UNCHANGED 0xffffffff 14020 /* counter ID to associate with this rule; IDs are allocated using 14021 * MC_CMD_SECURITY_RULE_COUNTER_ALLOC 14022 */ 14023 #define MC_CMD_SET_SECURITY_RULE_IN_COUNTER_ID_OFST 88 14024 /* enum: special value for the null counter ID */ 14025 #define MC_CMD_SET_SECURITY_RULE_IN_COUNTER_ID_NONE 0x0 14026 14027 /* MC_CMD_SET_SECURITY_RULE_OUT msgresponse */ 14028 #define MC_CMD_SET_SECURITY_RULE_OUT_LEN 28 14029 /* new reference count for uses of counter ID */ 14030 #define MC_CMD_SET_SECURITY_RULE_OUT_COUNTER_REFCNT_OFST 0 14031 /* constructed match bits for this rule (as a tracing aid only) */ 14032 #define MC_CMD_SET_SECURITY_RULE_OUT_LUE_MATCH_BITS_OFST 4 14033 #define MC_CMD_SET_SECURITY_RULE_OUT_LUE_MATCH_BITS_LEN 12 14034 /* constructed discriminator bits for this rule (as a tracing aid only) */ 14035 #define MC_CMD_SET_SECURITY_RULE_OUT_LUE_DISCRIMINATOR_OFST 16 14036 /* base location for probes for this rule (as a tracing aid only) */ 14037 #define MC_CMD_SET_SECURITY_RULE_OUT_LUE_PROBE_BASE_OFST 20 14038 /* step for probes for this rule (as a tracing aid only) */ 14039 #define MC_CMD_SET_SECURITY_RULE_OUT_LUE_PROBE_STEP_OFST 24 14040 14041 14042 /***********************************/ 14043 /* MC_CMD_RESET_SECURITY_RULES 14044 * Reset all blacklist and whitelist actions for a particular physical port, or 14045 * all ports. (Medford-only; for use by SolarSecure apps, not directly by 14046 * drivers. See SF-114946-SW.) NOTE - this message definition is provisional. 14047 * It has not yet been used in any released code and may change during 14048 * development. This note will be removed once it is regarded as stable. 14049 */ 14050 #define MC_CMD_RESET_SECURITY_RULES 0x110 14051 #undef MC_CMD_0x110_PRIVILEGE_CTG 14052 14053 #define MC_CMD_0x110_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14054 14055 /* MC_CMD_RESET_SECURITY_RULES_IN msgrequest */ 14056 #define MC_CMD_RESET_SECURITY_RULES_IN_LEN 4 14057 /* index of physical port to reset (or ALL_PHYSICAL_PORTS to reset all) */ 14058 #define MC_CMD_RESET_SECURITY_RULES_IN_PHYSICAL_PORT_OFST 0 14059 /* enum: special value to reset all physical ports */ 14060 #define MC_CMD_RESET_SECURITY_RULES_IN_ALL_PHYSICAL_PORTS 0xffffffff 14061 14062 /* MC_CMD_RESET_SECURITY_RULES_OUT msgresponse */ 14063 #define MC_CMD_RESET_SECURITY_RULES_OUT_LEN 0 14064 14065 14066 /***********************************/ 14067 /* MC_CMD_GET_SECURITY_RULESET_VERSION 14068 * Return a large hash value representing a "version" of the complete set of 14069 * currently active blacklist / whitelist rules and associated data structures. 14070 * (Medford-only; for use by SolarSecure apps, not directly by drivers. See 14071 * SF-114946-SW.) NOTE - this message definition is provisional. It has not yet 14072 * been used in any released code and may change during development. This note 14073 * will be removed once it is regarded as stable. 14074 */ 14075 #define MC_CMD_GET_SECURITY_RULESET_VERSION 0x111 14076 #undef MC_CMD_0x111_PRIVILEGE_CTG 14077 14078 #define MC_CMD_0x111_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14079 14080 /* MC_CMD_GET_SECURITY_RULESET_VERSION_IN msgrequest */ 14081 #define MC_CMD_GET_SECURITY_RULESET_VERSION_IN_LEN 0 14082 14083 /* MC_CMD_GET_SECURITY_RULESET_VERSION_OUT msgresponse */ 14084 #define MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_LENMIN 1 14085 #define MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_LENMAX 252 14086 #define MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_LEN(num) (0+1*(num)) 14087 /* Opaque hash value; length may vary depending on the hash scheme used */ 14088 #define MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_VERSION_OFST 0 14089 #define MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_VERSION_LEN 1 14090 #define MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_VERSION_MINNUM 1 14091 #define MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_VERSION_MAXNUM 252 14092 14093 14094 /***********************************/ 14095 /* MC_CMD_SECURITY_RULE_COUNTER_ALLOC 14096 * Allocate counters for use with blacklist / whitelist rules. (Medford-only; 14097 * for use by SolarSecure apps, not directly by drivers. See SF-114946-SW.) 14098 * NOTE - this message definition is provisional. It has not yet been used in 14099 * any released code and may change during development. This note will be 14100 * removed once it is regarded as stable. 14101 */ 14102 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC 0x112 14103 #undef MC_CMD_0x112_PRIVILEGE_CTG 14104 14105 #define MC_CMD_0x112_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14106 14107 /* MC_CMD_SECURITY_RULE_COUNTER_ALLOC_IN msgrequest */ 14108 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_IN_LEN 4 14109 /* the number of new counter IDs to request */ 14110 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_IN_NUM_COUNTERS_OFST 0 14111 14112 /* MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT msgresponse */ 14113 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_LENMIN 4 14114 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_LENMAX 252 14115 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_LEN(num) (4+4*(num)) 14116 /* the number of new counter IDs allocated (may be less than the number 14117 * requested if resources are unavailable) 14118 */ 14119 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_NUM_COUNTERS_OFST 0 14120 /* new counter ID(s) */ 14121 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_COUNTER_ID_OFST 4 14122 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_COUNTER_ID_LEN 4 14123 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_COUNTER_ID_MINNUM 0 14124 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_COUNTER_ID_MAXNUM 62 14125 14126 14127 /***********************************/ 14128 /* MC_CMD_SECURITY_RULE_COUNTER_FREE 14129 * Allocate counters for use with blacklist / whitelist rules. (Medford-only; 14130 * for use by SolarSecure apps, not directly by drivers. See SF-114946-SW.) 14131 * NOTE - this message definition is provisional. It has not yet been used in 14132 * any released code and may change during development. This note will be 14133 * removed once it is regarded as stable. 14134 */ 14135 #define MC_CMD_SECURITY_RULE_COUNTER_FREE 0x113 14136 #undef MC_CMD_0x113_PRIVILEGE_CTG 14137 14138 #define MC_CMD_0x113_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14139 14140 /* MC_CMD_SECURITY_RULE_COUNTER_FREE_IN msgrequest */ 14141 #define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_LENMIN 4 14142 #define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_LENMAX 252 14143 #define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_LEN(num) (4+4*(num)) 14144 /* the number of counter IDs to free */ 14145 #define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_NUM_COUNTERS_OFST 0 14146 /* the counter ID(s) to free */ 14147 #define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_COUNTER_ID_OFST 4 14148 #define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_COUNTER_ID_LEN 4 14149 #define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_COUNTER_ID_MINNUM 0 14150 #define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_COUNTER_ID_MAXNUM 62 14151 14152 /* MC_CMD_SECURITY_RULE_COUNTER_FREE_OUT msgresponse */ 14153 #define MC_CMD_SECURITY_RULE_COUNTER_FREE_OUT_LEN 0 14154 14155 14156 /***********************************/ 14157 /* MC_CMD_SUBNET_MAP_SET_NODE 14158 * Atomically update a trie node in the map of subnets to subnet IDs. The 14159 * constants in the descriptions of the fields of this message may be retrieved 14160 * by the GET_SECURITY_RULE_INFO op of MC_CMD_GET_PARSER_DISP_INFO. (Medford- 14161 * only; for use by SolarSecure apps, not directly by drivers. See 14162 * SF-114946-SW.) NOTE - this message definition is provisional. It has not yet 14163 * been used in any released code and may change during development. This note 14164 * will be removed once it is regarded as stable. 14165 */ 14166 #define MC_CMD_SUBNET_MAP_SET_NODE 0x114 14167 #undef MC_CMD_0x114_PRIVILEGE_CTG 14168 14169 #define MC_CMD_0x114_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14170 14171 /* MC_CMD_SUBNET_MAP_SET_NODE_IN msgrequest */ 14172 #define MC_CMD_SUBNET_MAP_SET_NODE_IN_LENMIN 6 14173 #define MC_CMD_SUBNET_MAP_SET_NODE_IN_LENMAX 252 14174 #define MC_CMD_SUBNET_MAP_SET_NODE_IN_LEN(num) (4+2*(num)) 14175 /* node to update in the range 0 .. SUBNET_MAP_NUM_NODES-1 */ 14176 #define MC_CMD_SUBNET_MAP_SET_NODE_IN_NODE_ID_OFST 0 14177 /* SUBNET_MAP_NUM_ENTRIES_PER_NODE new entries; each entry is either a pointer 14178 * to the next node, expressed as an offset in the trie memory (i.e. node ID 14179 * multiplied by SUBNET_MAP_NUM_ENTRIES_PER_NODE), or a leaf value in the range 14180 * SUBNET_ID_MIN .. SUBNET_ID_MAX 14181 */ 14182 #define MC_CMD_SUBNET_MAP_SET_NODE_IN_ENTRY_OFST 4 14183 #define MC_CMD_SUBNET_MAP_SET_NODE_IN_ENTRY_LEN 2 14184 #define MC_CMD_SUBNET_MAP_SET_NODE_IN_ENTRY_MINNUM 1 14185 #define MC_CMD_SUBNET_MAP_SET_NODE_IN_ENTRY_MAXNUM 124 14186 14187 /* MC_CMD_SUBNET_MAP_SET_NODE_OUT msgresponse */ 14188 #define MC_CMD_SUBNET_MAP_SET_NODE_OUT_LEN 0 14189 14190 /* PORTRANGE_TREE_ENTRY structuredef */ 14191 #define PORTRANGE_TREE_ENTRY_LEN 4 14192 /* key for branch nodes (<= key takes left branch, > key takes right branch), 14193 * or magic value for leaf nodes 14194 */ 14195 #define PORTRANGE_TREE_ENTRY_BRANCH_KEY_OFST 0 14196 #define PORTRANGE_TREE_ENTRY_BRANCH_KEY_LEN 2 14197 #define PORTRANGE_TREE_ENTRY_LEAF_NODE_KEY 0xffff /* enum */ 14198 #define PORTRANGE_TREE_ENTRY_BRANCH_KEY_LBN 0 14199 #define PORTRANGE_TREE_ENTRY_BRANCH_KEY_WIDTH 16 14200 /* final portrange ID for leaf nodes (don't care for branch nodes) */ 14201 #define PORTRANGE_TREE_ENTRY_LEAF_PORTRANGE_ID_OFST 2 14202 #define PORTRANGE_TREE_ENTRY_LEAF_PORTRANGE_ID_LEN 2 14203 #define PORTRANGE_TREE_ENTRY_LEAF_PORTRANGE_ID_LBN 16 14204 #define PORTRANGE_TREE_ENTRY_LEAF_PORTRANGE_ID_WIDTH 16 14205 14206 14207 /***********************************/ 14208 /* MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE 14209 * Atomically update the entire tree mapping remote port ranges to portrange 14210 * IDs. The constants in the descriptions of the fields of this message may be 14211 * retrieved by the GET_SECURITY_RULE_INFO op of MC_CMD_GET_PARSER_DISP_INFO. 14212 * (Medford-only; for use by SolarSecure apps, not directly by drivers. See 14213 * SF-114946-SW.) NOTE - this message definition is provisional. It has not yet 14214 * been used in any released code and may change during development. This note 14215 * will be removed once it is regarded as stable. 14216 */ 14217 #define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE 0x115 14218 #undef MC_CMD_0x115_PRIVILEGE_CTG 14219 14220 #define MC_CMD_0x115_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14221 14222 /* MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN msgrequest */ 14223 #define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN_LENMIN 4 14224 #define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN_LENMAX 252 14225 #define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN_LEN(num) (0+4*(num)) 14226 /* PORTRANGE_TREE_NUM_ENTRIES new entries, each laid out as a 14227 * PORTRANGE_TREE_ENTRY 14228 */ 14229 #define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_OFST 0 14230 #define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_LEN 4 14231 #define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_MINNUM 1 14232 #define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_MAXNUM 63 14233 14234 /* MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_OUT msgresponse */ 14235 #define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_OUT_LEN 0 14236 14237 14238 /***********************************/ 14239 /* MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE 14240 * Atomically update the entire tree mapping remote port ranges to portrange 14241 * IDs. The constants in the descriptions of the fields of this message may be 14242 * retrieved by the GET_SECURITY_RULE_INFO op of MC_CMD_GET_PARSER_DISP_INFO. 14243 * (Medford-only; for use by SolarSecure apps, not directly by drivers. See 14244 * SF-114946-SW.) NOTE - this message definition is provisional. It has not yet 14245 * been used in any released code and may change during development. This note 14246 * will be removed once it is regarded as stable. 14247 */ 14248 #define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE 0x116 14249 #undef MC_CMD_0x116_PRIVILEGE_CTG 14250 14251 #define MC_CMD_0x116_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14252 14253 /* MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN msgrequest */ 14254 #define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN_LENMIN 4 14255 #define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN_LENMAX 252 14256 #define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN_LEN(num) (0+4*(num)) 14257 /* PORTRANGE_TREE_NUM_ENTRIES new entries, each laid out as a 14258 * PORTRANGE_TREE_ENTRY 14259 */ 14260 #define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_OFST 0 14261 #define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_LEN 4 14262 #define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_MINNUM 1 14263 #define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_MAXNUM 63 14264 14265 /* MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_OUT msgresponse */ 14266 #define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_OUT_LEN 0 14267 14268 /* TUNNEL_ENCAP_UDP_PORT_ENTRY structuredef */ 14269 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_LEN 4 14270 /* UDP port (the standard ports are named below but any port may be used) */ 14271 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_OFST 0 14272 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_LEN 2 14273 /* enum: the IANA allocated UDP port for VXLAN */ 14274 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_IANA_VXLAN_UDP_PORT 0x12b5 14275 /* enum: the IANA allocated UDP port for Geneve */ 14276 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_IANA_GENEVE_UDP_PORT 0x17c1 14277 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_LBN 0 14278 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_WIDTH 16 14279 /* tunnel encapsulation protocol (only those named below are supported) */ 14280 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_OFST 2 14281 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_LEN 2 14282 /* enum: This port will be used for VXLAN on both IPv4 and IPv6 */ 14283 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_VXLAN 0x0 14284 /* enum: This port will be used for Geneve on both IPv4 and IPv6 */ 14285 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_GENEVE 0x1 14286 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_LBN 16 14287 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_WIDTH 16 14288 14289 14290 /***********************************/ 14291 /* MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS 14292 * Configure UDP ports for tunnel encapsulation hardware acceleration. The 14293 * parser-dispatcher will attempt to parse traffic on these ports as tunnel 14294 * encapsulation PDUs and filter them using the tunnel encapsulation filter 14295 * chain rather than the standard filter chain. Note that this command can 14296 * cause all functions to see a reset. (Available on Medford only.) 14297 */ 14298 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS 0x117 14299 #undef MC_CMD_0x117_PRIVILEGE_CTG 14300 14301 #define MC_CMD_0x117_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14302 14303 /* MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN msgrequest */ 14304 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMIN 4 14305 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMAX 68 14306 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LEN(num) (4+4*(num)) 14307 /* Flags */ 14308 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_OFST 0 14309 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_LEN 2 14310 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING_LBN 0 14311 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING_WIDTH 1 14312 /* The number of entries in the ENTRIES array */ 14313 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_OFST 2 14314 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_LEN 2 14315 /* Entries defining the UDP port to protocol mapping, each laid out as a 14316 * TUNNEL_ENCAP_UDP_PORT_ENTRY 14317 */ 14318 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_OFST 4 14319 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_LEN 4 14320 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MINNUM 0 14321 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MAXNUM 16 14322 14323 /* MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT msgresponse */ 14324 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_LEN 2 14325 /* Flags */ 14326 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_FLAGS_OFST 0 14327 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_FLAGS_LEN 2 14328 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_LBN 0 14329 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_WIDTH 1 14330 14331 14332 /***********************************/ 14333 /* MC_CMD_RX_BALANCING 14334 * Configure a port upconverter to distribute the packets on both RX engines. 14335 * Packets are distributed based on a table with the destination vFIFO. The 14336 * index of the table is a hash of source and destination of IPV4 and VLAN 14337 * priority. 14338 */ 14339 #define MC_CMD_RX_BALANCING 0x118 14340 #undef MC_CMD_0x118_PRIVILEGE_CTG 14341 14342 #define MC_CMD_0x118_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14343 14344 /* MC_CMD_RX_BALANCING_IN msgrequest */ 14345 #define MC_CMD_RX_BALANCING_IN_LEN 4 14346 /* The RX port whose upconverter table will be modified */ 14347 #define MC_CMD_RX_BALANCING_IN_PORT_OFST 0 14348 #define MC_CMD_RX_BALANCING_IN_PORT_LEN 1 14349 /* The VLAN priority associated to the table index and vFIFO */ 14350 #define MC_CMD_RX_BALANCING_IN_PRIORITY_OFST 1 14351 #define MC_CMD_RX_BALANCING_IN_PRIORITY_LEN 1 14352 /* The resulting bit of SRC^DST for indexing the table */ 14353 #define MC_CMD_RX_BALANCING_IN_SRC_DST_OFST 2 14354 #define MC_CMD_RX_BALANCING_IN_SRC_DST_LEN 1 14355 /* The RX engine to which the vFIFO in the table entry will point to */ 14356 #define MC_CMD_RX_BALANCING_IN_ENG_OFST 3 14357 #define MC_CMD_RX_BALANCING_IN_ENG_LEN 1 14358 14359 /* MC_CMD_RX_BALANCING_OUT msgresponse */ 14360 #define MC_CMD_RX_BALANCING_OUT_LEN 0 14361 14362 14363 /***********************************/ 14364 /* MC_CMD_TSA_BIND 14365 * TSAN - TSAC binding communication protocol. Refer to SF-115479-TC for more 14366 * info in respect to the binding protocol. Note- This MCDI command is only 14367 * available over a TLS secure connection between the TSAN and TSAC, and is not 14368 * available to host software. 14369 */ 14370 #define MC_CMD_TSA_BIND 0x119 14371 14372 /* MC_CMD_TSA_BIND_IN msgrequest: Protocol operation code */ 14373 #define MC_CMD_TSA_BIND_IN_LEN 4 14374 #define MC_CMD_TSA_BIND_IN_OP_OFST 0 14375 /* enum: Retrieve the TSAN ID from a TSAN. TSAN ID is a unique identifier for 14376 * the network adapter. More specifically, TSAN ID equals the MAC address of 14377 * the network adapter. TSAN ID is used as part of the TSAN authentication 14378 * protocol. Refer to SF-114946-SW for more information. 14379 */ 14380 #define MC_CMD_TSA_BIND_OP_GET_ID 0x1 14381 /* enum: Get a binding ticket from the TSAN. The binding ticket is used as part 14382 * of the binding procedure to authorize the binding of an adapter to a TSAID. 14383 * Refer to SF-114946-SW for more information. 14384 */ 14385 #define MC_CMD_TSA_BIND_OP_GET_TICKET 0x2 14386 /* enum: Opcode associated with the propagation of a private key that TSAN uses 14387 * as part of post-binding authentication procedure. More specifically, TSAN 14388 * uses this key for a signing operation. TSAC uses the counterpart public key 14389 * to verify the signature. Note - The post-binding authentication occurs when 14390 * the TSAN-TSAC connection terminates and TSAN tries to reconnect. Refer to 14391 * SF-114946-SW for more information. 14392 */ 14393 #define MC_CMD_TSA_BIND_OP_SET_KEY 0x3 14394 /* enum: Request an unbinding operation. Note- TSAN clears the binding ticket 14395 * from the Nvram section. 14396 */ 14397 #define MC_CMD_TSA_BIND_OP_UNBIND 0x4 14398 14399 /* MC_CMD_TSA_BIND_IN_GET_ID msgrequest */ 14400 #define MC_CMD_TSA_BIND_IN_GET_ID_LEN 20 14401 /* The operation requested. */ 14402 #define MC_CMD_TSA_BIND_IN_GET_ID_OP_OFST 0 14403 /* Cryptographic nonce that TSAC generates and sends to TSAN. TSAC generates 14404 * the nonce every time as part of the TSAN post-binding authentication 14405 * procedure when the TSAN-TSAC connection terminates and TSAN does need to re- 14406 * connect to the TSAC. Refer to SF-114946-SW for more information. 14407 */ 14408 #define MC_CMD_TSA_BIND_IN_GET_ID_NONCE_OFST 4 14409 #define MC_CMD_TSA_BIND_IN_GET_ID_NONCE_LEN 16 14410 14411 /* MC_CMD_TSA_BIND_IN_GET_TICKET msgrequest */ 14412 #define MC_CMD_TSA_BIND_IN_GET_TICKET_LEN 4 14413 /* The operation requested. */ 14414 #define MC_CMD_TSA_BIND_IN_GET_TICKET_OP_OFST 0 14415 14416 /* MC_CMD_TSA_BIND_IN_SET_KEY msgrequest */ 14417 #define MC_CMD_TSA_BIND_IN_SET_KEY_LENMIN 5 14418 #define MC_CMD_TSA_BIND_IN_SET_KEY_LENMAX 252 14419 #define MC_CMD_TSA_BIND_IN_SET_KEY_LEN(num) (4+1*(num)) 14420 /* The operation requested. */ 14421 #define MC_CMD_TSA_BIND_IN_SET_KEY_OP_OFST 0 14422 /* This data blob contains the private key generated by the TSAC. TSAN uses 14423 * this key for a signing operation. Note- This private key is used in 14424 * conjunction with the post-binding TSAN authentication procedure that occurs 14425 * when the TSAN-TSAC connection terminates and TSAN tries to reconnect. Refer 14426 * to SF-114946-SW for more information. 14427 */ 14428 #define MC_CMD_TSA_BIND_IN_SET_KEY_DATKEY_OFST 4 14429 #define MC_CMD_TSA_BIND_IN_SET_KEY_DATKEY_LEN 1 14430 #define MC_CMD_TSA_BIND_IN_SET_KEY_DATKEY_MINNUM 1 14431 #define MC_CMD_TSA_BIND_IN_SET_KEY_DATKEY_MAXNUM 248 14432 14433 /* MC_CMD_TSA_BIND_IN_UNBIND msgrequest: Asks for the un-binding procedure */ 14434 #define MC_CMD_TSA_BIND_IN_UNBIND_LEN 6 14435 /* TSAN unique identifier for the network adapter */ 14436 #define MC_CMD_TSA_BIND_IN_UNBIND_TSANID_OFST 0 14437 #define MC_CMD_TSA_BIND_IN_UNBIND_TSANID_LEN 6 14438 14439 /* MC_CMD_TSA_BIND_OUT_GET_ID msgresponse */ 14440 #define MC_CMD_TSA_BIND_OUT_GET_ID_LENMIN 11 14441 #define MC_CMD_TSA_BIND_OUT_GET_ID_LENMAX 252 14442 #define MC_CMD_TSA_BIND_OUT_GET_ID_LEN(num) (10+1*(num)) 14443 /* The operation completion code. */ 14444 #define MC_CMD_TSA_BIND_OUT_GET_ID_OP_OFST 0 14445 /* TSAN unique identifier for the network adapter */ 14446 #define MC_CMD_TSA_BIND_OUT_GET_ID_TSANID_OFST 4 14447 #define MC_CMD_TSA_BIND_OUT_GET_ID_TSANID_LEN 6 14448 /* The signature data blob. The signature is computed against the message 14449 * formed by TSAN ID concatenated with the NONCE value. Refer to SF-115479-TC 14450 * for more information also in respect to the private keys that are used to 14451 * sign the message based on TSAN pre/post-binding authentication procedure. 14452 */ 14453 #define MC_CMD_TSA_BIND_OUT_GET_ID_SIG_OFST 10 14454 #define MC_CMD_TSA_BIND_OUT_GET_ID_SIG_LEN 1 14455 #define MC_CMD_TSA_BIND_OUT_GET_ID_SIG_MINNUM 1 14456 #define MC_CMD_TSA_BIND_OUT_GET_ID_SIG_MAXNUM 242 14457 14458 /* MC_CMD_TSA_BIND_OUT_GET_TICKET msgresponse */ 14459 #define MC_CMD_TSA_BIND_OUT_GET_TICKET_LENMIN 5 14460 #define MC_CMD_TSA_BIND_OUT_GET_TICKET_LENMAX 252 14461 #define MC_CMD_TSA_BIND_OUT_GET_TICKET_LEN(num) (4+1*(num)) 14462 /* The operation completion code. */ 14463 #define MC_CMD_TSA_BIND_OUT_GET_TICKET_OP_OFST 0 14464 /* The ticket represents the data blob construct that TSAN sends to TSAC as 14465 * part of the binding protocol. From the TSAN perspective the ticket is an 14466 * opaque construct. For more info refer to SF-115479-TC. 14467 */ 14468 #define MC_CMD_TSA_BIND_OUT_GET_TICKET_TICKET_OFST 4 14469 #define MC_CMD_TSA_BIND_OUT_GET_TICKET_TICKET_LEN 1 14470 #define MC_CMD_TSA_BIND_OUT_GET_TICKET_TICKET_MINNUM 1 14471 #define MC_CMD_TSA_BIND_OUT_GET_TICKET_TICKET_MAXNUM 248 14472 14473 /* MC_CMD_TSA_BIND_OUT_SET_KEY msgresponse */ 14474 #define MC_CMD_TSA_BIND_OUT_SET_KEY_LEN 4 14475 /* The operation completion code. */ 14476 #define MC_CMD_TSA_BIND_OUT_SET_KEY_OP_OFST 0 14477 14478 /* MC_CMD_TSA_BIND_OUT_UNBIND msgresponse */ 14479 #define MC_CMD_TSA_BIND_OUT_UNBIND_LEN 8 14480 /* Same as MC_CMD_ERR field, but included as 0 in success cases */ 14481 #define MC_CMD_TSA_BIND_OUT_UNBIND_RESULT_OFST 0 14482 /* Extra status information */ 14483 #define MC_CMD_TSA_BIND_OUT_UNBIND_INFO_OFST 4 14484 /* enum: Unbind successful. */ 14485 #define MC_CMD_TSA_BIND_OUT_UNBIND_OK_UNBOUND 0x0 14486 /* enum: TSANID mismatch */ 14487 #define MC_CMD_TSA_BIND_OUT_UNBIND_ERR_BAD_TSANID 0x1 14488 /* enum: Unable to remove the binding ticket from persistent storage. */ 14489 #define MC_CMD_TSA_BIND_OUT_UNBIND_ERR_REMOVE_TICKET 0x2 14490 /* enum: TSAN is not bound to a binding ticket. */ 14491 #define MC_CMD_TSA_BIND_OUT_UNBIND_ERR_NOT_BOUND 0x3 14492 14493 14494 /***********************************/ 14495 /* MC_CMD_MANAGE_SECURITY_RULESET_CACHE 14496 * Manage the persistent NVRAM cache of security rules created with 14497 * MC_CMD_SET_SECURITY_RULE. Note that the cache is not automatically updated 14498 * as rules are added or removed; the active ruleset must be explicitly 14499 * committed to the cache. The cache may also be explicitly invalidated, 14500 * without affecting the currently active ruleset. When the cache is valid, it 14501 * will be loaded at power on or MC reboot, instead of the default ruleset. 14502 * Rollback of the currently active ruleset to the cached version (when it is 14503 * valid) is also supported. (Medford-only; for use by SolarSecure apps, not 14504 * directly by drivers. See SF-114946-SW.) NOTE - this message definition is 14505 * provisional. It has not yet been used in any released code and may change 14506 * during development. This note will be removed once it is regarded as stable. 14507 */ 14508 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE 0x11a 14509 #undef MC_CMD_0x11a_PRIVILEGE_CTG 14510 14511 #define MC_CMD_0x11a_PRIVILEGE_CTG SRIOV_CTG_ADMIN 14512 14513 /* MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN msgrequest */ 14514 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_LEN 4 14515 /* the operation to perform */ 14516 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_OP_OFST 0 14517 /* enum: reports the ruleset version that is cached in persistent storage but 14518 * performs no other action 14519 */ 14520 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_OP_GET_CACHED_VERSION 0x0 14521 /* enum: rolls back the active state to the cached version. (May fail with 14522 * ENOENT if there is no valid cached version.) 14523 */ 14524 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_OP_ROLLBACK 0x1 14525 /* enum: commits the active state to the persistent cache */ 14526 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_OP_COMMIT 0x2 14527 /* enum: invalidates the persistent cache without affecting the active state */ 14528 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_OP_INVALIDATE 0x3 14529 14530 /* MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT msgresponse */ 14531 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_LENMIN 5 14532 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_LENMAX 252 14533 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_LEN(num) (4+1*(num)) 14534 /* indicates whether the persistent cache is valid (after completion of the 14535 * requested operation in the case of rollback, commit, or invalidate) 14536 */ 14537 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_STATE_OFST 0 14538 /* enum: persistent cache is invalid (the VERSION field will be empty in this 14539 * case) 14540 */ 14541 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_STATE_INVALID 0x0 14542 /* enum: persistent cache is valid */ 14543 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_STATE_VALID 0x1 14544 /* cached ruleset version (after completion of the requested operation, in the 14545 * case of rollback, commit, or invalidate) as an opaque hash value in the same 14546 * form as MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_VERSION 14547 */ 14548 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_VERSION_OFST 4 14549 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_VERSION_LEN 1 14550 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_VERSION_MINNUM 1 14551 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_VERSION_MAXNUM 248 14552 14553 #endif /* _SIENA_MC_DRIVER_PCOL_H */ 14554