1 /*- 2 * Copyright 2008-2013 Solarflare Communications Inc. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #ifndef _SIENA_MC_DRIVER_PCOL_H 29 #define _SIENA_MC_DRIVER_PCOL_H 30 31 32 /* Values to be written into FMCR_CZ_RESET_STATE_REG to control boot. */ 33 /* Power-on reset state */ 34 #define MC_FW_STATE_POR (1) 35 /* If this is set in MC_RESET_STATE_REG then it should be 36 * possible to jump into IMEM without loading code from flash. */ 37 #define MC_FW_WARM_BOOT_OK (2) 38 /* The MC main image has started to boot. */ 39 #define MC_FW_STATE_BOOTING (4) 40 /* The Scheduler has started. */ 41 #define MC_FW_STATE_SCHED (8) 42 /* If this is set in MC_RESET_STATE_REG then it should be 43 * possible to jump into IMEM without loading code from flash. 44 * Unlike a warm boot, assume DMEM has been reloaded, so that 45 * the MC persistent data must be reinitialised. */ 46 #define MC_FW_TEPID_BOOT_OK (16) 47 /* We have entered the main firmware via recovery mode. This 48 * means that MC persistent data must be reinitialised, but that 49 * we shouldn't touch PCIe config. */ 50 #define MC_FW_RECOVERY_MODE_PCIE_INIT_OK (32) 51 /* BIST state has been initialized */ 52 #define MC_FW_BIST_INIT_OK (128) 53 54 /* Siena MC shared memmory offsets */ 55 /* The 'doorbell' addresses are hard-wired to alert the MC when written */ 56 #define MC_SMEM_P0_DOORBELL_OFST 0x000 57 #define MC_SMEM_P1_DOORBELL_OFST 0x004 58 /* The rest of these are firmware-defined */ 59 #define MC_SMEM_P0_PDU_OFST 0x008 60 #define MC_SMEM_P1_PDU_OFST 0x108 61 #define MC_SMEM_PDU_LEN 0x100 62 #define MC_SMEM_P0_PTP_TIME_OFST 0x7f0 63 #define MC_SMEM_P0_STATUS_OFST 0x7f8 64 #define MC_SMEM_P1_STATUS_OFST 0x7fc 65 66 /* Values to be written to the per-port status dword in shared 67 * memory on reboot and assert */ 68 #define MC_STATUS_DWORD_REBOOT (0xb007b007) 69 #define MC_STATUS_DWORD_ASSERT (0xdeaddead) 70 71 /* Check whether an mcfw version (in host order) belongs to a bootloader */ 72 #define MC_FW_VERSION_IS_BOOTLOADER(_v) (((_v) >> 16) == 0xb007) 73 74 /* The current version of the MCDI protocol. 75 * 76 * Note that the ROM burnt into the card only talks V0, so at the very 77 * least every driver must support version 0 and MCDI_PCOL_VERSION 78 */ 79 #ifdef WITH_MCDI_V2 80 #define MCDI_PCOL_VERSION 2 81 #else 82 #define MCDI_PCOL_VERSION 1 83 #endif 84 85 /* Unused commands: 0x23, 0x27, 0x30, 0x31 */ 86 87 /* MCDI version 1 88 * 89 * Each MCDI request starts with an MCDI_HEADER, which is a 32bit 90 * structure, filled in by the client. 91 * 92 * 0 7 8 16 20 22 23 24 31 93 * | CODE | R | LEN | SEQ | Rsvd | E | R | XFLAGS | 94 * | | | 95 * | | \--- Response 96 * | \------- Error 97 * \------------------------------ Resync (always set) 98 * 99 * The client writes it's request into MC shared memory, and rings the 100 * doorbell. Each request is completed by either by the MC writting 101 * back into shared memory, or by writting out an event. 102 * 103 * All MCDI commands support completion by shared memory response. Each 104 * request may also contain additional data (accounted for by HEADER.LEN), 105 * and some response's may also contain additional data (again, accounted 106 * for by HEADER.LEN). 107 * 108 * Some MCDI commands support completion by event, in which any associated 109 * response data is included in the event. 110 * 111 * The protocol requires one response to be delivered for every request, a 112 * request should not be sent unless the response for the previous request 113 * has been received (either by polling shared memory, or by receiving 114 * an event). 115 */ 116 117 /** Request/Response structure */ 118 #define MCDI_HEADER_OFST 0 119 #define MCDI_HEADER_CODE_LBN 0 120 #define MCDI_HEADER_CODE_WIDTH 7 121 #define MCDI_HEADER_RESYNC_LBN 7 122 #define MCDI_HEADER_RESYNC_WIDTH 1 123 #define MCDI_HEADER_DATALEN_LBN 8 124 #define MCDI_HEADER_DATALEN_WIDTH 8 125 #define MCDI_HEADER_SEQ_LBN 16 126 #define MCDI_HEADER_SEQ_WIDTH 4 127 #define MCDI_HEADER_RSVD_LBN 20 128 #define MCDI_HEADER_RSVD_WIDTH 1 129 #define MCDI_HEADER_NOT_EPOCH_LBN 21 130 #define MCDI_HEADER_NOT_EPOCH_WIDTH 1 131 #define MCDI_HEADER_ERROR_LBN 22 132 #define MCDI_HEADER_ERROR_WIDTH 1 133 #define MCDI_HEADER_RESPONSE_LBN 23 134 #define MCDI_HEADER_RESPONSE_WIDTH 1 135 #define MCDI_HEADER_XFLAGS_LBN 24 136 #define MCDI_HEADER_XFLAGS_WIDTH 8 137 /* Request response using event */ 138 #define MCDI_HEADER_XFLAGS_EVREQ 0x01 139 140 /* Maximum number of payload bytes */ 141 #define MCDI_CTL_SDU_LEN_MAX_V1 0xfc 142 #define MCDI_CTL_SDU_LEN_MAX_V2 0x400 143 144 #ifdef WITH_MCDI_V2 145 #define MCDI_CTL_SDU_LEN_MAX MCDI_CTL_SDU_LEN_MAX_V2 146 #else 147 #define MCDI_CTL_SDU_LEN_MAX MCDI_CTL_SDU_LEN_MAX_V1 148 #endif 149 150 151 /* The MC can generate events for two reasons: 152 * - To complete a shared memory request if XFLAGS_EVREQ was set 153 * - As a notification (link state, i2c event), controlled 154 * via MC_CMD_LOG_CTRL 155 * 156 * Both events share a common structure: 157 * 158 * 0 32 33 36 44 52 60 159 * | Data | Cont | Level | Src | Code | Rsvd | 160 * | 161 * \ There is another event pending in this notification 162 * 163 * If Code==CMDDONE, then the fields are further interpreted as: 164 * 165 * - LEVEL==INFO Command succeeded 166 * - LEVEL==ERR Command failed 167 * 168 * 0 8 16 24 32 169 * | Seq | Datalen | Errno | Rsvd | 170 * 171 * These fields are taken directly out of the standard MCDI header, i.e., 172 * LEVEL==ERR, Datalen == 0 => Reboot 173 * 174 * Events can be squirted out of the UART (using LOG_CTRL) without a 175 * MCDI header. An event can be distinguished from a MCDI response by 176 * examining the first byte which is 0xc0. This corresponds to the 177 * non-existent MCDI command MC_CMD_DEBUG_LOG. 178 * 179 * 0 7 8 180 * | command | Resync | = 0xc0 181 * 182 * Since the event is written in big-endian byte order, this works 183 * providing bits 56-63 of the event are 0xc0. 184 * 185 * 56 60 63 186 * | Rsvd | Code | = 0xc0 187 * 188 * Which means for convenience the event code is 0xc for all MC 189 * generated events. 190 */ 191 #define FSE_AZ_EV_CODE_MCDI_EVRESPONSE 0xc 192 193 194 /* Operation not permitted. */ 195 #define MC_CMD_ERR_EPERM 1 196 /* Non-existent command target */ 197 #define MC_CMD_ERR_ENOENT 2 198 /* assert() has killed the MC */ 199 #define MC_CMD_ERR_EINTR 4 200 /* I/O failure */ 201 #define MC_CMD_ERR_EIO 5 202 /* Already exists */ 203 #define MC_CMD_ERR_EEXIST 6 204 /* Try again */ 205 #define MC_CMD_ERR_EAGAIN 11 206 /* Out of memory */ 207 #define MC_CMD_ERR_ENOMEM 12 208 /* Caller does not hold required locks */ 209 #define MC_CMD_ERR_EACCES 13 210 /* Resource is currently unavailable (e.g. lock contention) */ 211 #define MC_CMD_ERR_EBUSY 16 212 /* No such device */ 213 #define MC_CMD_ERR_ENODEV 19 214 /* Invalid argument to target */ 215 #define MC_CMD_ERR_EINVAL 22 216 /* Broken pipe */ 217 #define MC_CMD_ERR_EPIPE 32 218 /* Read-only */ 219 #define MC_CMD_ERR_EROFS 30 220 /* Out of range */ 221 #define MC_CMD_ERR_ERANGE 34 222 /* Non-recursive resource is already acquired */ 223 #define MC_CMD_ERR_EDEADLK 35 224 /* Operation not implemented */ 225 #define MC_CMD_ERR_ENOSYS 38 226 /* Operation timed out */ 227 #define MC_CMD_ERR_ETIME 62 228 /* Link has been severed */ 229 #define MC_CMD_ERR_ENOLINK 67 230 /* Protocol error */ 231 #define MC_CMD_ERR_EPROTO 71 232 /* Operation not supported */ 233 #define MC_CMD_ERR_ENOTSUP 95 234 /* Address not available */ 235 #define MC_CMD_ERR_EADDRNOTAVAIL 99 236 /* Not connected */ 237 #define MC_CMD_ERR_ENOTCONN 107 238 /* Operation already in progress */ 239 #define MC_CMD_ERR_EALREADY 114 240 241 /* Resource allocation failed. */ 242 #define MC_CMD_ERR_ALLOC_FAIL 0x1000 243 /* V-adaptor not found. */ 244 #define MC_CMD_ERR_NO_VADAPTOR 0x1001 245 /* EVB port not found. */ 246 #define MC_CMD_ERR_NO_EVB_PORT 0x1002 247 /* V-switch not found. */ 248 #define MC_CMD_ERR_NO_VSWITCH 0x1003 249 /* Too many VLAN tags. */ 250 #define MC_CMD_ERR_VLAN_LIMIT 0x1004 251 /* Bad PCI function number. */ 252 #define MC_CMD_ERR_BAD_PCI_FUNC 0x1005 253 /* Invalid VLAN mode. */ 254 #define MC_CMD_ERR_BAD_VLAN_MODE 0x1006 255 /* Invalid v-switch type. */ 256 #define MC_CMD_ERR_BAD_VSWITCH_TYPE 0x1007 257 /* Invalid v-port type. */ 258 #define MC_CMD_ERR_BAD_VPORT_TYPE 0x1008 259 /* MAC address exists. */ 260 #define MC_CMD_ERR_MAC_EXIST 0x1009 261 /* Slave core not present */ 262 #define MC_CMD_ERR_SLAVE_NOT_PRESENT 0x100a 263 /* The datapath is disabled. */ 264 #define MC_CMD_ERR_DATAPATH_DISABLED 0x100b 265 /* The requesting client is not a function */ 266 #define MC_CMD_ERR_CLIENT_NOT_FN 0x100c 267 /* The requested operation might require the 268 command to be passed between MCs, and the 269 transport doesn't support that. Should 270 only ever been seen over the UART. */ 271 #define MC_CMD_ERR_TRANSPORT_NOPROXY 0x100d 272 /* VLAN tag(s) exists */ 273 #define MC_CMD_ERR_VLAN_EXIST 0x100e 274 /* No MAC address assigned to an EVB port */ 275 #define MC_CMD_ERR_NO_MAC_ADDR 0x100f 276 /* Notifies the driver that the request has been relayed 277 * to an admin function for authorization. The driver should 278 * wait for a PROXY_RESPONSE event and then resend its request. 279 * This error code is followed by a 32-bit handle that 280 * helps matching it with the respective PROXY_RESPONSE event. */ 281 #define MC_CMD_ERR_PROXY_PENDING 0x1010 282 #define MC_CMD_ERR_PROXY_PENDING_HANDLE_OFST 4 283 /* The request cannot be passed for authorization because 284 * another request from the same function is currently being 285 * authorized. The drvier should try again later. */ 286 #define MC_CMD_ERR_PROXY_INPROGRESS 0x1011 287 /* Returned by MC_CMD_PROXY_COMPLETE if the caller is not the function 288 * that has enabled proxying or BLOCK_INDEX points to a function that 289 * doesn't await an authorization. */ 290 #define MC_CMD_ERR_PROXY_UNEXPECTED 0x1012 291 /* This code is currently only used internally in FW. Its meaning is that 292 * an operation failed due to lack of SR-IOV privilege. 293 * Normally it is translated to EPERM by send_cmd_err(), 294 * but it may also be used to trigger some special mechanism 295 * for handling such case, e.g. to relay the failed request 296 * to a designated admin function for authorization. */ 297 #define MC_CMD_ERR_NO_PRIVILEGE 0x1013 298 /* Workaround 26807 could not be turned on/off because some functions 299 * have already installed filters. See the comment at 300 * MC_CMD_WORKAROUND_BUG26807. */ 301 #define MC_CMD_ERR_FILTERS_PRESENT 0x1014 302 303 #define MC_CMD_ERR_CODE_OFST 0 304 305 /* We define 8 "escape" commands to allow 306 for command number space extension */ 307 308 #define MC_CMD_CMD_SPACE_ESCAPE_0 0x78 309 #define MC_CMD_CMD_SPACE_ESCAPE_1 0x79 310 #define MC_CMD_CMD_SPACE_ESCAPE_2 0x7A 311 #define MC_CMD_CMD_SPACE_ESCAPE_3 0x7B 312 #define MC_CMD_CMD_SPACE_ESCAPE_4 0x7C 313 #define MC_CMD_CMD_SPACE_ESCAPE_5 0x7D 314 #define MC_CMD_CMD_SPACE_ESCAPE_6 0x7E 315 #define MC_CMD_CMD_SPACE_ESCAPE_7 0x7F 316 317 /* Vectors in the boot ROM */ 318 /* Point to the copycode entry point. */ 319 #define SIENA_MC_BOOTROM_COPYCODE_VEC (0x800 - 3 * 0x4) 320 #define HUNT_MC_BOOTROM_COPYCODE_VEC (0x8000 - 3 * 0x4) 321 /* Points to the recovery mode entry point. */ 322 #define SIENA_MC_BOOTROM_NOFLASH_VEC (0x800 - 2 * 0x4) 323 #define HUNT_MC_BOOTROM_NOFLASH_VEC (0x8000 - 2 * 0x4) 324 325 /* The command set exported by the boot ROM (MCDI v0) */ 326 #define MC_CMD_GET_VERSION_V0_SUPPORTED_FUNCS { \ 327 (1 << MC_CMD_READ32) | \ 328 (1 << MC_CMD_WRITE32) | \ 329 (1 << MC_CMD_COPYCODE) | \ 330 (1 << MC_CMD_GET_VERSION), \ 331 0, 0, 0 } 332 333 #define MC_CMD_SENSOR_INFO_OUT_OFFSET_OFST(_x) \ 334 (MC_CMD_SENSOR_ENTRY_OFST + (_x)) 335 336 #define MC_CMD_DBI_WRITE_IN_ADDRESS_OFST(n) \ 337 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \ 338 MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST + \ 339 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN) 340 341 #define MC_CMD_DBI_WRITE_IN_BYTE_MASK_OFST(n) \ 342 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \ 343 MC_CMD_DBIWROP_TYPEDEF_BYTE_MASK_OFST + \ 344 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN) 345 346 #define MC_CMD_DBI_WRITE_IN_VALUE_OFST(n) \ 347 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \ 348 MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST + \ 349 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN) 350 351 /* This may be ORed with an EVB_PORT_ID_xxx constant to pass a non-default 352 * stack ID (which must be in the range 1-255) along with an EVB port ID. 353 */ 354 #define EVB_STACK_ID(n) (((n) & 0xff) << 16) 355 356 357 #ifdef WITH_MCDI_V2 358 359 /* Version 2 adds an optional argument to error returns: the errno value 360 * may be followed by the (0-based) number of the first argument that 361 * could not be processed. 362 */ 363 #define MC_CMD_ERR_ARG_OFST 4 364 365 /* No space */ 366 #define MC_CMD_ERR_ENOSPC 28 367 368 #endif 369 370 /* MCDI_EVENT structuredef */ 371 #define MCDI_EVENT_LEN 8 372 #define MCDI_EVENT_CONT_LBN 32 373 #define MCDI_EVENT_CONT_WIDTH 1 374 #define MCDI_EVENT_LEVEL_LBN 33 375 #define MCDI_EVENT_LEVEL_WIDTH 3 376 /* enum: Info. */ 377 #define MCDI_EVENT_LEVEL_INFO 0x0 378 /* enum: Warning. */ 379 #define MCDI_EVENT_LEVEL_WARN 0x1 380 /* enum: Error. */ 381 #define MCDI_EVENT_LEVEL_ERR 0x2 382 /* enum: Fatal. */ 383 #define MCDI_EVENT_LEVEL_FATAL 0x3 384 #define MCDI_EVENT_DATA_OFST 0 385 #define MCDI_EVENT_CMDDONE_SEQ_LBN 0 386 #define MCDI_EVENT_CMDDONE_SEQ_WIDTH 8 387 #define MCDI_EVENT_CMDDONE_DATALEN_LBN 8 388 #define MCDI_EVENT_CMDDONE_DATALEN_WIDTH 8 389 #define MCDI_EVENT_CMDDONE_ERRNO_LBN 16 390 #define MCDI_EVENT_CMDDONE_ERRNO_WIDTH 8 391 #define MCDI_EVENT_LINKCHANGE_LP_CAP_LBN 0 392 #define MCDI_EVENT_LINKCHANGE_LP_CAP_WIDTH 16 393 #define MCDI_EVENT_LINKCHANGE_SPEED_LBN 16 394 #define MCDI_EVENT_LINKCHANGE_SPEED_WIDTH 4 395 /* enum: 100Mbs */ 396 #define MCDI_EVENT_LINKCHANGE_SPEED_100M 0x1 397 /* enum: 1Gbs */ 398 #define MCDI_EVENT_LINKCHANGE_SPEED_1G 0x2 399 /* enum: 10Gbs */ 400 #define MCDI_EVENT_LINKCHANGE_SPEED_10G 0x3 401 /* enum: 40Gbs */ 402 #define MCDI_EVENT_LINKCHANGE_SPEED_40G 0x4 403 #define MCDI_EVENT_LINKCHANGE_FCNTL_LBN 20 404 #define MCDI_EVENT_LINKCHANGE_FCNTL_WIDTH 4 405 #define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_LBN 24 406 #define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_WIDTH 8 407 #define MCDI_EVENT_SENSOREVT_MONITOR_LBN 0 408 #define MCDI_EVENT_SENSOREVT_MONITOR_WIDTH 8 409 #define MCDI_EVENT_SENSOREVT_STATE_LBN 8 410 #define MCDI_EVENT_SENSOREVT_STATE_WIDTH 8 411 #define MCDI_EVENT_SENSOREVT_VALUE_LBN 16 412 #define MCDI_EVENT_SENSOREVT_VALUE_WIDTH 16 413 #define MCDI_EVENT_FWALERT_DATA_LBN 8 414 #define MCDI_EVENT_FWALERT_DATA_WIDTH 24 415 #define MCDI_EVENT_FWALERT_REASON_LBN 0 416 #define MCDI_EVENT_FWALERT_REASON_WIDTH 8 417 /* enum: SRAM Access. */ 418 #define MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS 0x1 419 #define MCDI_EVENT_FLR_VF_LBN 0 420 #define MCDI_EVENT_FLR_VF_WIDTH 8 421 #define MCDI_EVENT_TX_ERR_TXQ_LBN 0 422 #define MCDI_EVENT_TX_ERR_TXQ_WIDTH 12 423 #define MCDI_EVENT_TX_ERR_TYPE_LBN 12 424 #define MCDI_EVENT_TX_ERR_TYPE_WIDTH 4 425 /* enum: Descriptor loader reported failure */ 426 #define MCDI_EVENT_TX_ERR_DL_FAIL 0x1 427 /* enum: Descriptor ring empty and no EOP seen for packet */ 428 #define MCDI_EVENT_TX_ERR_NO_EOP 0x2 429 /* enum: Overlength packet */ 430 #define MCDI_EVENT_TX_ERR_2BIG 0x3 431 /* enum: Malformed option descriptor */ 432 #define MCDI_EVENT_TX_BAD_OPTDESC 0x5 433 /* enum: Option descriptor part way through a packet */ 434 #define MCDI_EVENT_TX_OPT_IN_PKT 0x8 435 /* enum: DMA or PIO data access error */ 436 #define MCDI_EVENT_TX_ERR_BAD_DMA_OR_PIO 0x9 437 #define MCDI_EVENT_TX_ERR_INFO_LBN 16 438 #define MCDI_EVENT_TX_ERR_INFO_WIDTH 16 439 #define MCDI_EVENT_TX_FLUSH_TO_DRIVER_LBN 12 440 #define MCDI_EVENT_TX_FLUSH_TO_DRIVER_WIDTH 1 441 #define MCDI_EVENT_TX_FLUSH_TXQ_LBN 0 442 #define MCDI_EVENT_TX_FLUSH_TXQ_WIDTH 12 443 #define MCDI_EVENT_PTP_ERR_TYPE_LBN 0 444 #define MCDI_EVENT_PTP_ERR_TYPE_WIDTH 8 445 /* enum: PLL lost lock */ 446 #define MCDI_EVENT_PTP_ERR_PLL_LOST 0x1 447 /* enum: Filter overflow (PDMA) */ 448 #define MCDI_EVENT_PTP_ERR_FILTER 0x2 449 /* enum: FIFO overflow (FPGA) */ 450 #define MCDI_EVENT_PTP_ERR_FIFO 0x3 451 /* enum: Merge queue overflow */ 452 #define MCDI_EVENT_PTP_ERR_QUEUE 0x4 453 #define MCDI_EVENT_AOE_ERR_TYPE_LBN 0 454 #define MCDI_EVENT_AOE_ERR_TYPE_WIDTH 8 455 /* enum: AOE failed to load - no valid image? */ 456 #define MCDI_EVENT_AOE_NO_LOAD 0x1 457 /* enum: AOE FC reported an exception */ 458 #define MCDI_EVENT_AOE_FC_ASSERT 0x2 459 /* enum: AOE FC watchdogged */ 460 #define MCDI_EVENT_AOE_FC_WATCHDOG 0x3 461 /* enum: AOE FC failed to start */ 462 #define MCDI_EVENT_AOE_FC_NO_START 0x4 463 /* enum: Generic AOE fault - likely to have been reported via other means too 464 * but intended for use by aoex driver. 465 */ 466 #define MCDI_EVENT_AOE_FAULT 0x5 467 /* enum: Results of reprogramming the CPLD (status in AOE_ERR_DATA) */ 468 #define MCDI_EVENT_AOE_CPLD_REPROGRAMMED 0x6 469 /* enum: AOE loaded successfully */ 470 #define MCDI_EVENT_AOE_LOAD 0x7 471 /* enum: AOE DMA operation completed (LSB of HOST_HANDLE in AOE_ERR_DATA) */ 472 #define MCDI_EVENT_AOE_DMA 0x8 473 /* enum: AOE byteblaster connected/disconnected (Connection status in 474 * AOE_ERR_DATA) 475 */ 476 #define MCDI_EVENT_AOE_BYTEBLASTER 0x9 477 /* enum: DDR ECC status update */ 478 #define MCDI_EVENT_AOE_DDR_ECC_STATUS 0xa 479 /* enum: PTP status update */ 480 #define MCDI_EVENT_AOE_PTP_STATUS 0xb 481 #define MCDI_EVENT_AOE_ERR_DATA_LBN 8 482 #define MCDI_EVENT_AOE_ERR_DATA_WIDTH 8 483 #define MCDI_EVENT_RX_ERR_RXQ_LBN 0 484 #define MCDI_EVENT_RX_ERR_RXQ_WIDTH 12 485 #define MCDI_EVENT_RX_ERR_TYPE_LBN 12 486 #define MCDI_EVENT_RX_ERR_TYPE_WIDTH 4 487 #define MCDI_EVENT_RX_ERR_INFO_LBN 16 488 #define MCDI_EVENT_RX_ERR_INFO_WIDTH 16 489 #define MCDI_EVENT_RX_FLUSH_TO_DRIVER_LBN 12 490 #define MCDI_EVENT_RX_FLUSH_TO_DRIVER_WIDTH 1 491 #define MCDI_EVENT_RX_FLUSH_RXQ_LBN 0 492 #define MCDI_EVENT_RX_FLUSH_RXQ_WIDTH 12 493 #define MCDI_EVENT_MC_REBOOT_COUNT_LBN 0 494 #define MCDI_EVENT_MC_REBOOT_COUNT_WIDTH 16 495 #define MCDI_EVENT_MUM_ERR_TYPE_LBN 0 496 #define MCDI_EVENT_MUM_ERR_TYPE_WIDTH 8 497 /* enum: MUM failed to load - no valid image? */ 498 #define MCDI_EVENT_MUM_NO_LOAD 0x1 499 /* enum: MUM f/w reported an exception */ 500 #define MCDI_EVENT_MUM_ASSERT 0x2 501 /* enum: MUM not kicking watchdog */ 502 #define MCDI_EVENT_MUM_WATCHDOG 0x3 503 #define MCDI_EVENT_MUM_ERR_DATA_LBN 8 504 #define MCDI_EVENT_MUM_ERR_DATA_WIDTH 8 505 #define MCDI_EVENT_DATA_LBN 0 506 #define MCDI_EVENT_DATA_WIDTH 32 507 #define MCDI_EVENT_SRC_LBN 36 508 #define MCDI_EVENT_SRC_WIDTH 8 509 #define MCDI_EVENT_EV_CODE_LBN 60 510 #define MCDI_EVENT_EV_CODE_WIDTH 4 511 #define MCDI_EVENT_CODE_LBN 44 512 #define MCDI_EVENT_CODE_WIDTH 8 513 /* enum: Event generated by host software */ 514 #define MCDI_EVENT_SW_EVENT 0x0 515 /* enum: Bad assert. */ 516 #define MCDI_EVENT_CODE_BADSSERT 0x1 517 /* enum: PM Notice. */ 518 #define MCDI_EVENT_CODE_PMNOTICE 0x2 519 /* enum: Command done. */ 520 #define MCDI_EVENT_CODE_CMDDONE 0x3 521 /* enum: Link change. */ 522 #define MCDI_EVENT_CODE_LINKCHANGE 0x4 523 /* enum: Sensor Event. */ 524 #define MCDI_EVENT_CODE_SENSOREVT 0x5 525 /* enum: Schedule error. */ 526 #define MCDI_EVENT_CODE_SCHEDERR 0x6 527 /* enum: Reboot. */ 528 #define MCDI_EVENT_CODE_REBOOT 0x7 529 /* enum: Mac stats DMA. */ 530 #define MCDI_EVENT_CODE_MAC_STATS_DMA 0x8 531 /* enum: Firmware alert. */ 532 #define MCDI_EVENT_CODE_FWALERT 0x9 533 /* enum: Function level reset. */ 534 #define MCDI_EVENT_CODE_FLR 0xa 535 /* enum: Transmit error */ 536 #define MCDI_EVENT_CODE_TX_ERR 0xb 537 /* enum: Tx flush has completed */ 538 #define MCDI_EVENT_CODE_TX_FLUSH 0xc 539 /* enum: PTP packet received timestamp */ 540 #define MCDI_EVENT_CODE_PTP_RX 0xd 541 /* enum: PTP NIC failure */ 542 #define MCDI_EVENT_CODE_PTP_FAULT 0xe 543 /* enum: PTP PPS event */ 544 #define MCDI_EVENT_CODE_PTP_PPS 0xf 545 /* enum: Rx flush has completed */ 546 #define MCDI_EVENT_CODE_RX_FLUSH 0x10 547 /* enum: Receive error */ 548 #define MCDI_EVENT_CODE_RX_ERR 0x11 549 /* enum: AOE fault */ 550 #define MCDI_EVENT_CODE_AOE 0x12 551 /* enum: Network port calibration failed (VCAL). */ 552 #define MCDI_EVENT_CODE_VCAL_FAIL 0x13 553 /* enum: HW PPS event */ 554 #define MCDI_EVENT_CODE_HW_PPS 0x14 555 /* enum: The MC has rebooted (huntington and later, siena uses CODE_REBOOT and 556 * a different format) 557 */ 558 #define MCDI_EVENT_CODE_MC_REBOOT 0x15 559 /* enum: the MC has detected a parity error */ 560 #define MCDI_EVENT_CODE_PAR_ERR 0x16 561 /* enum: the MC has detected a correctable error */ 562 #define MCDI_EVENT_CODE_ECC_CORR_ERR 0x17 563 /* enum: the MC has detected an uncorrectable error */ 564 #define MCDI_EVENT_CODE_ECC_FATAL_ERR 0x18 565 /* enum: The MC has entered offline BIST mode */ 566 #define MCDI_EVENT_CODE_MC_BIST 0x19 567 /* enum: PTP tick event providing current NIC time */ 568 #define MCDI_EVENT_CODE_PTP_TIME 0x1a 569 /* enum: MUM fault */ 570 #define MCDI_EVENT_CODE_MUM 0x1b 571 /* enum: notify the designated PF of a new authorization request */ 572 #define MCDI_EVENT_CODE_PROXY_REQUEST 0x1c 573 /* enum: notify a function that awaits an authorization that its request has 574 * been processed and it may now resend the command 575 */ 576 #define MCDI_EVENT_CODE_PROXY_RESPONSE 0x1d 577 /* enum: Artificial event generated by host and posted via MC for test 578 * purposes. 579 */ 580 #define MCDI_EVENT_CODE_TESTGEN 0xfa 581 #define MCDI_EVENT_CMDDONE_DATA_OFST 0 582 #define MCDI_EVENT_CMDDONE_DATA_LBN 0 583 #define MCDI_EVENT_CMDDONE_DATA_WIDTH 32 584 #define MCDI_EVENT_LINKCHANGE_DATA_OFST 0 585 #define MCDI_EVENT_LINKCHANGE_DATA_LBN 0 586 #define MCDI_EVENT_LINKCHANGE_DATA_WIDTH 32 587 #define MCDI_EVENT_SENSOREVT_DATA_OFST 0 588 #define MCDI_EVENT_SENSOREVT_DATA_LBN 0 589 #define MCDI_EVENT_SENSOREVT_DATA_WIDTH 32 590 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_OFST 0 591 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_LBN 0 592 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_WIDTH 32 593 #define MCDI_EVENT_TX_ERR_DATA_OFST 0 594 #define MCDI_EVENT_TX_ERR_DATA_LBN 0 595 #define MCDI_EVENT_TX_ERR_DATA_WIDTH 32 596 /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the seconds field of 597 * timestamp 598 */ 599 #define MCDI_EVENT_PTP_SECONDS_OFST 0 600 #define MCDI_EVENT_PTP_SECONDS_LBN 0 601 #define MCDI_EVENT_PTP_SECONDS_WIDTH 32 602 /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the major field of 603 * timestamp 604 */ 605 #define MCDI_EVENT_PTP_MAJOR_OFST 0 606 #define MCDI_EVENT_PTP_MAJOR_LBN 0 607 #define MCDI_EVENT_PTP_MAJOR_WIDTH 32 608 /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the nanoseconds field 609 * of timestamp 610 */ 611 #define MCDI_EVENT_PTP_NANOSECONDS_OFST 0 612 #define MCDI_EVENT_PTP_NANOSECONDS_LBN 0 613 #define MCDI_EVENT_PTP_NANOSECONDS_WIDTH 32 614 /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the minor field of 615 * timestamp 616 */ 617 #define MCDI_EVENT_PTP_MINOR_OFST 0 618 #define MCDI_EVENT_PTP_MINOR_LBN 0 619 #define MCDI_EVENT_PTP_MINOR_WIDTH 32 620 /* For CODE_PTP_RX events, the lowest four bytes of sourceUUID from PTP packet 621 */ 622 #define MCDI_EVENT_PTP_UUID_OFST 0 623 #define MCDI_EVENT_PTP_UUID_LBN 0 624 #define MCDI_EVENT_PTP_UUID_WIDTH 32 625 #define MCDI_EVENT_RX_ERR_DATA_OFST 0 626 #define MCDI_EVENT_RX_ERR_DATA_LBN 0 627 #define MCDI_EVENT_RX_ERR_DATA_WIDTH 32 628 #define MCDI_EVENT_PAR_ERR_DATA_OFST 0 629 #define MCDI_EVENT_PAR_ERR_DATA_LBN 0 630 #define MCDI_EVENT_PAR_ERR_DATA_WIDTH 32 631 #define MCDI_EVENT_ECC_CORR_ERR_DATA_OFST 0 632 #define MCDI_EVENT_ECC_CORR_ERR_DATA_LBN 0 633 #define MCDI_EVENT_ECC_CORR_ERR_DATA_WIDTH 32 634 #define MCDI_EVENT_ECC_FATAL_ERR_DATA_OFST 0 635 #define MCDI_EVENT_ECC_FATAL_ERR_DATA_LBN 0 636 #define MCDI_EVENT_ECC_FATAL_ERR_DATA_WIDTH 32 637 /* For CODE_PTP_TIME events, the major value of the PTP clock */ 638 #define MCDI_EVENT_PTP_TIME_MAJOR_OFST 0 639 #define MCDI_EVENT_PTP_TIME_MAJOR_LBN 0 640 #define MCDI_EVENT_PTP_TIME_MAJOR_WIDTH 32 641 /* For CODE_PTP_TIME events, bits 19-26 of the minor value of the PTP clock */ 642 #define MCDI_EVENT_PTP_TIME_MINOR_26_19_LBN 36 643 #define MCDI_EVENT_PTP_TIME_MINOR_26_19_WIDTH 8 644 /* For CODE_PTP_TIME events where report sync status is enabled, indicates 645 * whether the NIC clock has ever been set 646 */ 647 #define MCDI_EVENT_PTP_TIME_NIC_CLOCK_VALID_LBN 36 648 #define MCDI_EVENT_PTP_TIME_NIC_CLOCK_VALID_WIDTH 1 649 /* For CODE_PTP_TIME events where report sync status is enabled, indicates 650 * whether the NIC and System clocks are in sync 651 */ 652 #define MCDI_EVENT_PTP_TIME_HOST_NIC_IN_SYNC_LBN 37 653 #define MCDI_EVENT_PTP_TIME_HOST_NIC_IN_SYNC_WIDTH 1 654 /* For CODE_PTP_TIME events where report sync status is enabled, bits 21-26 of 655 * the minor value of the PTP clock 656 */ 657 #define MCDI_EVENT_PTP_TIME_MINOR_26_21_LBN 38 658 #define MCDI_EVENT_PTP_TIME_MINOR_26_21_WIDTH 6 659 #define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_OFST 0 660 #define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_LBN 0 661 #define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_WIDTH 32 662 #define MCDI_EVENT_PROXY_RESPONSE_HANDLE_OFST 0 663 #define MCDI_EVENT_PROXY_RESPONSE_HANDLE_LBN 0 664 #define MCDI_EVENT_PROXY_RESPONSE_HANDLE_WIDTH 32 665 /* Zero means that the request has been completed or authorized, and the driver 666 * should resend it. A non-zero value means that the authorization has been 667 * denied, and gives the reason. Typically it will be EPERM. 668 */ 669 #define MCDI_EVENT_PROXY_RESPONSE_RC_LBN 36 670 #define MCDI_EVENT_PROXY_RESPONSE_RC_WIDTH 8 671 672 /* FCDI_EVENT structuredef */ 673 #define FCDI_EVENT_LEN 8 674 #define FCDI_EVENT_CONT_LBN 32 675 #define FCDI_EVENT_CONT_WIDTH 1 676 #define FCDI_EVENT_LEVEL_LBN 33 677 #define FCDI_EVENT_LEVEL_WIDTH 3 678 /* enum: Info. */ 679 #define FCDI_EVENT_LEVEL_INFO 0x0 680 /* enum: Warning. */ 681 #define FCDI_EVENT_LEVEL_WARN 0x1 682 /* enum: Error. */ 683 #define FCDI_EVENT_LEVEL_ERR 0x2 684 /* enum: Fatal. */ 685 #define FCDI_EVENT_LEVEL_FATAL 0x3 686 #define FCDI_EVENT_DATA_OFST 0 687 #define FCDI_EVENT_LINK_STATE_STATUS_LBN 0 688 #define FCDI_EVENT_LINK_STATE_STATUS_WIDTH 1 689 #define FCDI_EVENT_LINK_DOWN 0x0 /* enum */ 690 #define FCDI_EVENT_LINK_UP 0x1 /* enum */ 691 #define FCDI_EVENT_DATA_LBN 0 692 #define FCDI_EVENT_DATA_WIDTH 32 693 #define FCDI_EVENT_SRC_LBN 36 694 #define FCDI_EVENT_SRC_WIDTH 8 695 #define FCDI_EVENT_EV_CODE_LBN 60 696 #define FCDI_EVENT_EV_CODE_WIDTH 4 697 #define FCDI_EVENT_CODE_LBN 44 698 #define FCDI_EVENT_CODE_WIDTH 8 699 /* enum: The FC was rebooted. */ 700 #define FCDI_EVENT_CODE_REBOOT 0x1 701 /* enum: Bad assert. */ 702 #define FCDI_EVENT_CODE_ASSERT 0x2 703 /* enum: DDR3 test result. */ 704 #define FCDI_EVENT_CODE_DDR_TEST_RESULT 0x3 705 /* enum: Link status. */ 706 #define FCDI_EVENT_CODE_LINK_STATE 0x4 707 /* enum: A timed read is ready to be serviced. */ 708 #define FCDI_EVENT_CODE_TIMED_READ 0x5 709 /* enum: One or more PPS IN events */ 710 #define FCDI_EVENT_CODE_PPS_IN 0x6 711 /* enum: Tick event from PTP clock */ 712 #define FCDI_EVENT_CODE_PTP_TICK 0x7 713 /* enum: ECC error counters */ 714 #define FCDI_EVENT_CODE_DDR_ECC_STATUS 0x8 715 /* enum: Current status of PTP */ 716 #define FCDI_EVENT_CODE_PTP_STATUS 0x9 717 /* enum: Port id config to map MC-FC port idx */ 718 #define FCDI_EVENT_CODE_PORT_CONFIG 0xa 719 #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_OFST 0 720 #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_LBN 0 721 #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_WIDTH 32 722 #define FCDI_EVENT_ASSERT_TYPE_LBN 36 723 #define FCDI_EVENT_ASSERT_TYPE_WIDTH 8 724 #define FCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_LBN 36 725 #define FCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_WIDTH 8 726 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_OFST 0 727 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_LBN 0 728 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_WIDTH 32 729 #define FCDI_EVENT_LINK_STATE_DATA_OFST 0 730 #define FCDI_EVENT_LINK_STATE_DATA_LBN 0 731 #define FCDI_EVENT_LINK_STATE_DATA_WIDTH 32 732 #define FCDI_EVENT_PTP_STATE_OFST 0 733 #define FCDI_EVENT_PTP_UNDEFINED 0x0 /* enum */ 734 #define FCDI_EVENT_PTP_SETUP_FAILED 0x1 /* enum */ 735 #define FCDI_EVENT_PTP_OPERATIONAL 0x2 /* enum */ 736 #define FCDI_EVENT_PTP_STATE_LBN 0 737 #define FCDI_EVENT_PTP_STATE_WIDTH 32 738 #define FCDI_EVENT_DDR_ECC_STATUS_BANK_ID_LBN 36 739 #define FCDI_EVENT_DDR_ECC_STATUS_BANK_ID_WIDTH 8 740 #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_OFST 0 741 #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_LBN 0 742 #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_WIDTH 32 743 /* Index of MC port being referred to */ 744 #define FCDI_EVENT_PORT_CONFIG_SRC_LBN 36 745 #define FCDI_EVENT_PORT_CONFIG_SRC_WIDTH 8 746 /* FC Port index that matches the MC port index in SRC */ 747 #define FCDI_EVENT_PORT_CONFIG_DATA_OFST 0 748 #define FCDI_EVENT_PORT_CONFIG_DATA_LBN 0 749 #define FCDI_EVENT_PORT_CONFIG_DATA_WIDTH 32 750 751 /* FCDI_EXTENDED_EVENT_PPS structuredef: Extended FCDI event to send PPS events 752 * to the MC. Note that this structure | is overlayed over a normal FCDI event 753 * such that bits 32-63 containing | event code, level, source etc remain the 754 * same. In this case the data | field of the header is defined to be the 755 * number of timestamps 756 */ 757 #define FCDI_EXTENDED_EVENT_PPS_LENMIN 16 758 #define FCDI_EXTENDED_EVENT_PPS_LENMAX 248 759 #define FCDI_EXTENDED_EVENT_PPS_LEN(num) (8+8*(num)) 760 /* Number of timestamps following */ 761 #define FCDI_EXTENDED_EVENT_PPS_COUNT_OFST 0 762 #define FCDI_EXTENDED_EVENT_PPS_COUNT_LBN 0 763 #define FCDI_EXTENDED_EVENT_PPS_COUNT_WIDTH 32 764 /* Seconds field of a timestamp record */ 765 #define FCDI_EXTENDED_EVENT_PPS_SECONDS_OFST 8 766 #define FCDI_EXTENDED_EVENT_PPS_SECONDS_LBN 64 767 #define FCDI_EXTENDED_EVENT_PPS_SECONDS_WIDTH 32 768 /* Nanoseconds field of a timestamp record */ 769 #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_OFST 12 770 #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_LBN 96 771 #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_WIDTH 32 772 /* Timestamp records comprising the event */ 773 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_OFST 8 774 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LEN 8 775 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LO_OFST 8 776 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_HI_OFST 12 777 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MINNUM 1 778 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MAXNUM 30 779 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LBN 64 780 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_WIDTH 64 781 782 /* MUM_EVENT structuredef */ 783 #define MUM_EVENT_LEN 8 784 #define MUM_EVENT_CONT_LBN 32 785 #define MUM_EVENT_CONT_WIDTH 1 786 #define MUM_EVENT_LEVEL_LBN 33 787 #define MUM_EVENT_LEVEL_WIDTH 3 788 /* enum: Info. */ 789 #define MUM_EVENT_LEVEL_INFO 0x0 790 /* enum: Warning. */ 791 #define MUM_EVENT_LEVEL_WARN 0x1 792 /* enum: Error. */ 793 #define MUM_EVENT_LEVEL_ERR 0x2 794 /* enum: Fatal. */ 795 #define MUM_EVENT_LEVEL_FATAL 0x3 796 #define MUM_EVENT_DATA_OFST 0 797 #define MUM_EVENT_SENSOR_ID_LBN 0 798 #define MUM_EVENT_SENSOR_ID_WIDTH 8 799 /* Enum values, see field(s): */ 800 /* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */ 801 #define MUM_EVENT_SENSOR_STATE_LBN 8 802 #define MUM_EVENT_SENSOR_STATE_WIDTH 8 803 #define MUM_EVENT_PORT_PHY_READY_LBN 0 804 #define MUM_EVENT_PORT_PHY_READY_WIDTH 1 805 #define MUM_EVENT_PORT_PHY_LINK_UP_LBN 1 806 #define MUM_EVENT_PORT_PHY_LINK_UP_WIDTH 1 807 #define MUM_EVENT_PORT_PHY_TX_LOL_LBN 2 808 #define MUM_EVENT_PORT_PHY_TX_LOL_WIDTH 1 809 #define MUM_EVENT_PORT_PHY_RX_LOL_LBN 3 810 #define MUM_EVENT_PORT_PHY_RX_LOL_WIDTH 1 811 #define MUM_EVENT_PORT_PHY_TX_LOS_LBN 4 812 #define MUM_EVENT_PORT_PHY_TX_LOS_WIDTH 1 813 #define MUM_EVENT_PORT_PHY_RX_LOS_LBN 5 814 #define MUM_EVENT_PORT_PHY_RX_LOS_WIDTH 1 815 #define MUM_EVENT_PORT_PHY_TX_FAULT_LBN 6 816 #define MUM_EVENT_PORT_PHY_TX_FAULT_WIDTH 1 817 #define MUM_EVENT_DATA_LBN 0 818 #define MUM_EVENT_DATA_WIDTH 32 819 #define MUM_EVENT_SRC_LBN 36 820 #define MUM_EVENT_SRC_WIDTH 8 821 #define MUM_EVENT_EV_CODE_LBN 60 822 #define MUM_EVENT_EV_CODE_WIDTH 4 823 #define MUM_EVENT_CODE_LBN 44 824 #define MUM_EVENT_CODE_WIDTH 8 825 /* enum: The MUM was rebooted. */ 826 #define MUM_EVENT_CODE_REBOOT 0x1 827 /* enum: Bad assert. */ 828 #define MUM_EVENT_CODE_ASSERT 0x2 829 /* enum: Sensor failure. */ 830 #define MUM_EVENT_CODE_SENSOR 0x3 831 /* enum: Link fault has been asserted, or has cleared. */ 832 #define MUM_EVENT_CODE_QSFP_LASI_INTERRUPT 0x4 833 #define MUM_EVENT_SENSOR_DATA_OFST 0 834 #define MUM_EVENT_SENSOR_DATA_LBN 0 835 #define MUM_EVENT_SENSOR_DATA_WIDTH 32 836 #define MUM_EVENT_PORT_PHY_FLAGS_OFST 0 837 #define MUM_EVENT_PORT_PHY_FLAGS_LBN 0 838 #define MUM_EVENT_PORT_PHY_FLAGS_WIDTH 32 839 #define MUM_EVENT_PORT_PHY_COPPER_LEN_OFST 0 840 #define MUM_EVENT_PORT_PHY_COPPER_LEN_LBN 0 841 #define MUM_EVENT_PORT_PHY_COPPER_LEN_WIDTH 32 842 #define MUM_EVENT_PORT_PHY_CAPS_OFST 0 843 #define MUM_EVENT_PORT_PHY_CAPS_LBN 0 844 #define MUM_EVENT_PORT_PHY_CAPS_WIDTH 32 845 #define MUM_EVENT_PORT_PHY_TECH_OFST 0 846 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_UNKNOWN 0x0 /* enum */ 847 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_OPTICAL 0x1 /* enum */ 848 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_PASSIVE 0x2 /* enum */ 849 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_PASSIVE_EQUALIZED 0x3 /* enum */ 850 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_ACTIVE_LIMITING 0x4 /* enum */ 851 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_ACTIVE_LINEAR 0x5 /* enum */ 852 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_BASE_T 0x6 /* enum */ 853 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_LOOPBACK_PASSIVE 0x7 /* enum */ 854 #define MUM_EVENT_PORT_PHY_TECH_LBN 0 855 #define MUM_EVENT_PORT_PHY_TECH_WIDTH 32 856 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_LBN 36 857 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_WIDTH 4 858 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_FLAGS 0x0 /* enum */ 859 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_COPPER_LEN 0x1 /* enum */ 860 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_CAPS 0x2 /* enum */ 861 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_TECH 0x3 /* enum */ 862 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_MAX 0x4 /* enum */ 863 #define MUM_EVENT_PORT_PHY_SRC_PORT_NO_LBN 40 864 #define MUM_EVENT_PORT_PHY_SRC_PORT_NO_WIDTH 4 865 866 867 /***********************************/ 868 /* MC_CMD_READ32 869 * Read multiple 32byte words from MC memory. 870 */ 871 #define MC_CMD_READ32 0x1 872 #undef MC_CMD_0x1_PRIVILEGE_CTG 873 874 #define MC_CMD_0x1_PRIVILEGE_CTG SRIOV_CTG_ADMIN 875 876 /* MC_CMD_READ32_IN msgrequest */ 877 #define MC_CMD_READ32_IN_LEN 8 878 #define MC_CMD_READ32_IN_ADDR_OFST 0 879 #define MC_CMD_READ32_IN_NUMWORDS_OFST 4 880 881 /* MC_CMD_READ32_OUT msgresponse */ 882 #define MC_CMD_READ32_OUT_LENMIN 4 883 #define MC_CMD_READ32_OUT_LENMAX 252 884 #define MC_CMD_READ32_OUT_LEN(num) (0+4*(num)) 885 #define MC_CMD_READ32_OUT_BUFFER_OFST 0 886 #define MC_CMD_READ32_OUT_BUFFER_LEN 4 887 #define MC_CMD_READ32_OUT_BUFFER_MINNUM 1 888 #define MC_CMD_READ32_OUT_BUFFER_MAXNUM 63 889 890 891 /***********************************/ 892 /* MC_CMD_WRITE32 893 * Write multiple 32byte words to MC memory. 894 */ 895 #define MC_CMD_WRITE32 0x2 896 #undef MC_CMD_0x2_PRIVILEGE_CTG 897 898 #define MC_CMD_0x2_PRIVILEGE_CTG SRIOV_CTG_ADMIN 899 900 /* MC_CMD_WRITE32_IN msgrequest */ 901 #define MC_CMD_WRITE32_IN_LENMIN 8 902 #define MC_CMD_WRITE32_IN_LENMAX 252 903 #define MC_CMD_WRITE32_IN_LEN(num) (4+4*(num)) 904 #define MC_CMD_WRITE32_IN_ADDR_OFST 0 905 #define MC_CMD_WRITE32_IN_BUFFER_OFST 4 906 #define MC_CMD_WRITE32_IN_BUFFER_LEN 4 907 #define MC_CMD_WRITE32_IN_BUFFER_MINNUM 1 908 #define MC_CMD_WRITE32_IN_BUFFER_MAXNUM 62 909 910 /* MC_CMD_WRITE32_OUT msgresponse */ 911 #define MC_CMD_WRITE32_OUT_LEN 0 912 913 914 /***********************************/ 915 /* MC_CMD_COPYCODE 916 * Copy MC code between two locations and jump. 917 */ 918 #define MC_CMD_COPYCODE 0x3 919 #undef MC_CMD_0x3_PRIVILEGE_CTG 920 921 #define MC_CMD_0x3_PRIVILEGE_CTG SRIOV_CTG_ADMIN 922 923 /* MC_CMD_COPYCODE_IN msgrequest */ 924 #define MC_CMD_COPYCODE_IN_LEN 16 925 /* Source address 926 * 927 * The main image should be entered via a copy of a single word from and to a 928 * magic address, which controls various aspects of the boot. The magic address 929 * is a bitfield, with each bit as documented below. 930 */ 931 #define MC_CMD_COPYCODE_IN_SRC_ADDR_OFST 0 932 /* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT (see below) */ 933 #define MC_CMD_COPYCODE_HUNT_NO_MAGIC_ADDR 0x10000 934 /* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT and 935 * BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED (see below) 936 */ 937 #define MC_CMD_COPYCODE_HUNT_NO_DATAPATH_MAGIC_ADDR 0x1d0d0 938 /* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT, 939 * BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED and BOOT_MAGIC_IGNORE_CONFIG (see 940 * below) 941 */ 942 #define MC_CMD_COPYCODE_HUNT_IGNORE_CONFIG_MAGIC_ADDR 0x1badc 943 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_LBN 17 944 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_WIDTH 1 945 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_LBN 2 946 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_WIDTH 1 947 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_LBN 3 948 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_WIDTH 1 949 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_LBN 4 950 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_WIDTH 1 951 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_LBN 5 952 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_WIDTH 1 953 /* Destination address */ 954 #define MC_CMD_COPYCODE_IN_DEST_ADDR_OFST 4 955 #define MC_CMD_COPYCODE_IN_NUMWORDS_OFST 8 956 /* Address of where to jump after copy. */ 957 #define MC_CMD_COPYCODE_IN_JUMP_OFST 12 958 /* enum: Control should return to the caller rather than jumping */ 959 #define MC_CMD_COPYCODE_JUMP_NONE 0x1 960 961 /* MC_CMD_COPYCODE_OUT msgresponse */ 962 #define MC_CMD_COPYCODE_OUT_LEN 0 963 964 965 /***********************************/ 966 /* MC_CMD_SET_FUNC 967 * Select function for function-specific commands. 968 */ 969 #define MC_CMD_SET_FUNC 0x4 970 #undef MC_CMD_0x4_PRIVILEGE_CTG 971 972 #define MC_CMD_0x4_PRIVILEGE_CTG SRIOV_CTG_ADMIN 973 974 /* MC_CMD_SET_FUNC_IN msgrequest */ 975 #define MC_CMD_SET_FUNC_IN_LEN 4 976 /* Set function */ 977 #define MC_CMD_SET_FUNC_IN_FUNC_OFST 0 978 979 /* MC_CMD_SET_FUNC_OUT msgresponse */ 980 #define MC_CMD_SET_FUNC_OUT_LEN 0 981 982 983 /***********************************/ 984 /* MC_CMD_GET_BOOT_STATUS 985 * Get the instruction address from which the MC booted. 986 */ 987 #define MC_CMD_GET_BOOT_STATUS 0x5 988 #undef MC_CMD_0x5_PRIVILEGE_CTG 989 990 #define MC_CMD_0x5_PRIVILEGE_CTG SRIOV_CTG_ADMIN 991 992 /* MC_CMD_GET_BOOT_STATUS_IN msgrequest */ 993 #define MC_CMD_GET_BOOT_STATUS_IN_LEN 0 994 995 /* MC_CMD_GET_BOOT_STATUS_OUT msgresponse */ 996 #define MC_CMD_GET_BOOT_STATUS_OUT_LEN 8 997 /* ?? */ 998 #define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_OFST 0 999 /* enum: indicates that the MC wasn't flash booted */ 1000 #define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_NULL 0xdeadbeef 1001 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_OFST 4 1002 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_LBN 0 1003 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_WIDTH 1 1004 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_LBN 1 1005 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_WIDTH 1 1006 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_LBN 2 1007 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_WIDTH 1 1008 1009 1010 /***********************************/ 1011 /* MC_CMD_GET_ASSERTS 1012 * Get (and optionally clear) the current assertion status. Only 1013 * OUT.GLOBAL_FLAGS is guaranteed to exist in the completion payload. The other 1014 * fields will only be present if OUT.GLOBAL_FLAGS != NO_FAILS 1015 */ 1016 #define MC_CMD_GET_ASSERTS 0x6 1017 #undef MC_CMD_0x6_PRIVILEGE_CTG 1018 1019 #define MC_CMD_0x6_PRIVILEGE_CTG SRIOV_CTG_ADMIN 1020 1021 /* MC_CMD_GET_ASSERTS_IN msgrequest */ 1022 #define MC_CMD_GET_ASSERTS_IN_LEN 4 1023 /* Set to clear assertion */ 1024 #define MC_CMD_GET_ASSERTS_IN_CLEAR_OFST 0 1025 1026 /* MC_CMD_GET_ASSERTS_OUT msgresponse */ 1027 #define MC_CMD_GET_ASSERTS_OUT_LEN 140 1028 /* Assertion status flag. */ 1029 #define MC_CMD_GET_ASSERTS_OUT_GLOBAL_FLAGS_OFST 0 1030 /* enum: No assertions have failed. */ 1031 #define MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1 1032 /* enum: A system-level assertion has failed. */ 1033 #define MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2 1034 /* enum: A thread-level assertion has failed. */ 1035 #define MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3 1036 /* enum: The system was reset by the watchdog. */ 1037 #define MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4 1038 /* enum: An illegal address trap stopped the system (huntington and later) */ 1039 #define MC_CMD_GET_ASSERTS_FLAGS_ADDR_TRAP 0x5 1040 /* Failing PC value */ 1041 #define MC_CMD_GET_ASSERTS_OUT_SAVED_PC_OFFS_OFST 4 1042 /* Saved GP regs */ 1043 #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_OFST 8 1044 #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_LEN 4 1045 #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_NUM 31 1046 /* enum: A magic value hinting that the value in this register at the time of 1047 * the failure has likely been lost. 1048 */ 1049 #define MC_CMD_GET_ASSERTS_REG_NO_DATA 0xda7a1057 1050 /* Failing thread address */ 1051 #define MC_CMD_GET_ASSERTS_OUT_THREAD_OFFS_OFST 132 1052 #define MC_CMD_GET_ASSERTS_OUT_RESERVED_OFST 136 1053 1054 1055 /***********************************/ 1056 /* MC_CMD_LOG_CTRL 1057 * Configure the output stream for log events such as link state changes, 1058 * sensor notifications and MCDI completions 1059 */ 1060 #define MC_CMD_LOG_CTRL 0x7 1061 #undef MC_CMD_0x7_PRIVILEGE_CTG 1062 1063 #define MC_CMD_0x7_PRIVILEGE_CTG SRIOV_CTG_GENERAL 1064 1065 /* MC_CMD_LOG_CTRL_IN msgrequest */ 1066 #define MC_CMD_LOG_CTRL_IN_LEN 8 1067 /* Log destination */ 1068 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_OFST 0 1069 /* enum: UART. */ 1070 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_UART 0x1 1071 /* enum: Event queue. */ 1072 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ 0x2 1073 /* Legacy argument. Must be zero. */ 1074 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ_OFST 4 1075 1076 /* MC_CMD_LOG_CTRL_OUT msgresponse */ 1077 #define MC_CMD_LOG_CTRL_OUT_LEN 0 1078 1079 1080 /***********************************/ 1081 /* MC_CMD_GET_VERSION 1082 * Get version information about the MC firmware. 1083 */ 1084 #define MC_CMD_GET_VERSION 0x8 1085 #undef MC_CMD_0x8_PRIVILEGE_CTG 1086 1087 #define MC_CMD_0x8_PRIVILEGE_CTG SRIOV_CTG_GENERAL 1088 1089 /* MC_CMD_GET_VERSION_IN msgrequest */ 1090 #define MC_CMD_GET_VERSION_IN_LEN 0 1091 1092 /* MC_CMD_GET_VERSION_EXT_IN msgrequest: Asks for the extended version */ 1093 #define MC_CMD_GET_VERSION_EXT_IN_LEN 4 1094 /* placeholder, set to 0 */ 1095 #define MC_CMD_GET_VERSION_EXT_IN_EXT_FLAGS_OFST 0 1096 1097 /* MC_CMD_GET_VERSION_V0_OUT msgresponse: deprecated version format */ 1098 #define MC_CMD_GET_VERSION_V0_OUT_LEN 4 1099 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 1100 /* enum: Reserved version number to indicate "any" version. */ 1101 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_ANY 0xffffffff 1102 /* enum: Bootrom version value for Siena. */ 1103 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_SIENA_BOOTROM 0xb0070000 1104 /* enum: Bootrom version value for Huntington. */ 1105 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_HUNT_BOOTROM 0xb0070001 1106 1107 /* MC_CMD_GET_VERSION_OUT msgresponse */ 1108 #define MC_CMD_GET_VERSION_OUT_LEN 32 1109 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */ 1110 /* Enum values, see field(s): */ 1111 /* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */ 1112 #define MC_CMD_GET_VERSION_OUT_PCOL_OFST 4 1113 /* 128bit mask of functions supported by the current firmware */ 1114 #define MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_OFST 8 1115 #define MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_LEN 16 1116 #define MC_CMD_GET_VERSION_OUT_VERSION_OFST 24 1117 #define MC_CMD_GET_VERSION_OUT_VERSION_LEN 8 1118 #define MC_CMD_GET_VERSION_OUT_VERSION_LO_OFST 24 1119 #define MC_CMD_GET_VERSION_OUT_VERSION_HI_OFST 28 1120 1121 /* MC_CMD_GET_VERSION_EXT_OUT msgresponse */ 1122 #define MC_CMD_GET_VERSION_EXT_OUT_LEN 48 1123 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */ 1124 /* Enum values, see field(s): */ 1125 /* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */ 1126 #define MC_CMD_GET_VERSION_EXT_OUT_PCOL_OFST 4 1127 /* 128bit mask of functions supported by the current firmware */ 1128 #define MC_CMD_GET_VERSION_EXT_OUT_SUPPORTED_FUNCS_OFST 8 1129 #define MC_CMD_GET_VERSION_EXT_OUT_SUPPORTED_FUNCS_LEN 16 1130 #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_OFST 24 1131 #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LEN 8 1132 #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LO_OFST 24 1133 #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_HI_OFST 28 1134 /* extra info */ 1135 #define MC_CMD_GET_VERSION_EXT_OUT_EXTRA_OFST 32 1136 #define MC_CMD_GET_VERSION_EXT_OUT_EXTRA_LEN 16 1137 1138 1139 /***********************************/ 1140 /* MC_CMD_FC 1141 * Perform an FC operation 1142 */ 1143 #define MC_CMD_FC 0x9 1144 1145 /* MC_CMD_FC_IN msgrequest */ 1146 #define MC_CMD_FC_IN_LEN 4 1147 #define MC_CMD_FC_IN_OP_HDR_OFST 0 1148 #define MC_CMD_FC_IN_OP_LBN 0 1149 #define MC_CMD_FC_IN_OP_WIDTH 8 1150 /* enum: NULL MCDI command to FC. */ 1151 #define MC_CMD_FC_OP_NULL 0x1 1152 /* enum: Unused opcode */ 1153 #define MC_CMD_FC_OP_UNUSED 0x2 1154 /* enum: MAC driver commands */ 1155 #define MC_CMD_FC_OP_MAC 0x3 1156 /* enum: Read FC memory */ 1157 #define MC_CMD_FC_OP_READ32 0x4 1158 /* enum: Write to FC memory */ 1159 #define MC_CMD_FC_OP_WRITE32 0x5 1160 /* enum: Read FC memory */ 1161 #define MC_CMD_FC_OP_TRC_READ 0x6 1162 /* enum: Write to FC memory */ 1163 #define MC_CMD_FC_OP_TRC_WRITE 0x7 1164 /* enum: FC firmware Version */ 1165 #define MC_CMD_FC_OP_GET_VERSION 0x8 1166 /* enum: Read FC memory */ 1167 #define MC_CMD_FC_OP_TRC_RX_READ 0x9 1168 /* enum: Write to FC memory */ 1169 #define MC_CMD_FC_OP_TRC_RX_WRITE 0xa 1170 /* enum: SFP parameters */ 1171 #define MC_CMD_FC_OP_SFP 0xb 1172 /* enum: DDR3 test */ 1173 #define MC_CMD_FC_OP_DDR_TEST 0xc 1174 /* enum: Get Crash context from FC */ 1175 #define MC_CMD_FC_OP_GET_ASSERT 0xd 1176 /* enum: Get FPGA Build registers */ 1177 #define MC_CMD_FC_OP_FPGA_BUILD 0xe 1178 /* enum: Read map support commands */ 1179 #define MC_CMD_FC_OP_READ_MAP 0xf 1180 /* enum: FC Capabilities */ 1181 #define MC_CMD_FC_OP_CAPABILITIES 0x10 1182 /* enum: FC Global flags */ 1183 #define MC_CMD_FC_OP_GLOBAL_FLAGS 0x11 1184 /* enum: FC IO using relative addressing modes */ 1185 #define MC_CMD_FC_OP_IO_REL 0x12 1186 /* enum: FPGA link information */ 1187 #define MC_CMD_FC_OP_UHLINK 0x13 1188 /* enum: Configure loopbacks and link on FPGA ports */ 1189 #define MC_CMD_FC_OP_SET_LINK 0x14 1190 /* enum: Licensing operations relating to AOE */ 1191 #define MC_CMD_FC_OP_LICENSE 0x15 1192 /* enum: Startup information to the FC */ 1193 #define MC_CMD_FC_OP_STARTUP 0x16 1194 /* enum: Configure a DMA read */ 1195 #define MC_CMD_FC_OP_DMA 0x17 1196 /* enum: Configure a timed read */ 1197 #define MC_CMD_FC_OP_TIMED_READ 0x18 1198 /* enum: Control UART logging */ 1199 #define MC_CMD_FC_OP_LOG 0x19 1200 /* enum: Get the value of a given clock_id */ 1201 #define MC_CMD_FC_OP_CLOCK 0x1a 1202 /* enum: DDR3/QDR3 parameters */ 1203 #define MC_CMD_FC_OP_DDR 0x1b 1204 /* enum: PTP and timestamp control */ 1205 #define MC_CMD_FC_OP_TIMESTAMP 0x1c 1206 /* enum: Commands for SPI Flash interface */ 1207 #define MC_CMD_FC_OP_SPI 0x1d 1208 /* enum: Commands for diagnostic components */ 1209 #define MC_CMD_FC_OP_DIAG 0x1e 1210 /* enum: External AOE port. */ 1211 #define MC_CMD_FC_IN_PORT_EXT_OFST 0x0 1212 /* enum: Internal AOE port. */ 1213 #define MC_CMD_FC_IN_PORT_INT_OFST 0x40 1214 1215 /* MC_CMD_FC_IN_NULL msgrequest */ 1216 #define MC_CMD_FC_IN_NULL_LEN 4 1217 #define MC_CMD_FC_IN_CMD_OFST 0 1218 1219 /* MC_CMD_FC_IN_PHY msgrequest */ 1220 #define MC_CMD_FC_IN_PHY_LEN 5 1221 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1222 /* FC PHY driver operation code */ 1223 #define MC_CMD_FC_IN_PHY_OP_OFST 4 1224 #define MC_CMD_FC_IN_PHY_OP_LEN 1 1225 /* enum: PHY init handler */ 1226 #define MC_CMD_FC_OP_PHY_OP_INIT 0x1 1227 /* enum: PHY reconfigure handler */ 1228 #define MC_CMD_FC_OP_PHY_OP_RECONFIGURE 0x2 1229 /* enum: PHY reboot handler */ 1230 #define MC_CMD_FC_OP_PHY_OP_REBOOT 0x3 1231 /* enum: PHY get_supported_cap handler */ 1232 #define MC_CMD_FC_OP_PHY_OP_GET_SUPPORTED_CAP 0x4 1233 /* enum: PHY get_config handler */ 1234 #define MC_CMD_FC_OP_PHY_OP_GET_CONFIG 0x5 1235 /* enum: PHY get_media_info handler */ 1236 #define MC_CMD_FC_OP_PHY_OP_GET_MEDIA_INFO 0x6 1237 /* enum: PHY set_led handler */ 1238 #define MC_CMD_FC_OP_PHY_OP_SET_LED 0x7 1239 /* enum: PHY lasi_interrupt handler */ 1240 #define MC_CMD_FC_OP_PHY_OP_LASI_INTERRUPT 0x8 1241 /* enum: PHY check_link handler */ 1242 #define MC_CMD_FC_OP_PHY_OP_CHECK_LINK 0x9 1243 /* enum: PHY fill_stats handler */ 1244 #define MC_CMD_FC_OP_PHY_OP_FILL_STATS 0xa 1245 /* enum: PHY bpx_link_state_changed handler */ 1246 #define MC_CMD_FC_OP_PHY_OP_BPX_LINK_STATE_CHANGED 0xb 1247 /* enum: PHY get_state handler */ 1248 #define MC_CMD_FC_OP_PHY_OP_GET_STATE 0xc 1249 /* enum: PHY start_bist handler */ 1250 #define MC_CMD_FC_OP_PHY_OP_START_BIST 0xd 1251 /* enum: PHY poll_bist handler */ 1252 #define MC_CMD_FC_OP_PHY_OP_POLL_BIST 0xe 1253 /* enum: PHY nvram_test handler */ 1254 #define MC_CMD_FC_OP_PHY_OP_NVRAM_TEST 0xf 1255 /* enum: PHY relinquish handler */ 1256 #define MC_CMD_FC_OP_PHY_OP_RELINQUISH_SPI 0x10 1257 /* enum: PHY read connection from FC - may be not required */ 1258 #define MC_CMD_FC_OP_PHY_OP_GET_CONNECTION 0x11 1259 /* enum: PHY read flags from FC - may be not required */ 1260 #define MC_CMD_FC_OP_PHY_OP_GET_FLAGS 0x12 1261 1262 /* MC_CMD_FC_IN_PHY_INIT msgrequest */ 1263 #define MC_CMD_FC_IN_PHY_INIT_LEN 4 1264 #define MC_CMD_FC_IN_PHY_CMD_OFST 0 1265 1266 /* MC_CMD_FC_IN_MAC msgrequest */ 1267 #define MC_CMD_FC_IN_MAC_LEN 8 1268 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1269 #define MC_CMD_FC_IN_MAC_HEADER_OFST 4 1270 #define MC_CMD_FC_IN_MAC_OP_LBN 0 1271 #define MC_CMD_FC_IN_MAC_OP_WIDTH 8 1272 /* enum: MAC reconfigure handler */ 1273 #define MC_CMD_FC_OP_MAC_OP_RECONFIGURE 0x1 1274 /* enum: MAC Set command - same as MC_CMD_SET_MAC */ 1275 #define MC_CMD_FC_OP_MAC_OP_SET_LINK 0x2 1276 /* enum: MAC statistics */ 1277 #define MC_CMD_FC_OP_MAC_OP_GET_STATS 0x3 1278 /* enum: MAC RX statistics */ 1279 #define MC_CMD_FC_OP_MAC_OP_GET_RX_STATS 0x6 1280 /* enum: MAC TX statistics */ 1281 #define MC_CMD_FC_OP_MAC_OP_GET_TX_STATS 0x7 1282 /* enum: MAC Read status */ 1283 #define MC_CMD_FC_OP_MAC_OP_READ_STATUS 0x8 1284 #define MC_CMD_FC_IN_MAC_PORT_TYPE_LBN 8 1285 #define MC_CMD_FC_IN_MAC_PORT_TYPE_WIDTH 8 1286 /* enum: External FPGA port. */ 1287 #define MC_CMD_FC_PORT_EXT 0x0 1288 /* enum: Internal Siena-facing FPGA ports. */ 1289 #define MC_CMD_FC_PORT_INT 0x1 1290 #define MC_CMD_FC_IN_MAC_PORT_IDX_LBN 16 1291 #define MC_CMD_FC_IN_MAC_PORT_IDX_WIDTH 8 1292 #define MC_CMD_FC_IN_MAC_CMD_FORMAT_LBN 24 1293 #define MC_CMD_FC_IN_MAC_CMD_FORMAT_WIDTH 8 1294 /* enum: Default FC command format; the fields PORT_TYPE and PORT_IDX are 1295 * irrelevant. Port number is derived from pci_fn; passed in FC header. 1296 */ 1297 #define MC_CMD_FC_OP_MAC_CMD_FORMAT_DEFAULT 0x0 1298 /* enum: Override default port number. Port number determined by fields 1299 * PORT_TYPE and PORT_IDX. 1300 */ 1301 #define MC_CMD_FC_OP_MAC_CMD_FORMAT_PORT_OVERRIDE 0x1 1302 1303 /* MC_CMD_FC_IN_MAC_RECONFIGURE msgrequest */ 1304 #define MC_CMD_FC_IN_MAC_RECONFIGURE_LEN 8 1305 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1306 /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ 1307 1308 /* MC_CMD_FC_IN_MAC_SET_LINK msgrequest */ 1309 #define MC_CMD_FC_IN_MAC_SET_LINK_LEN 32 1310 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1311 /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ 1312 /* MTU size */ 1313 #define MC_CMD_FC_IN_MAC_SET_LINK_MTU_OFST 8 1314 /* Drain Tx FIFO */ 1315 #define MC_CMD_FC_IN_MAC_SET_LINK_DRAIN_OFST 12 1316 #define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_OFST 16 1317 #define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_LEN 8 1318 #define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_LO_OFST 16 1319 #define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_HI_OFST 20 1320 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_OFST 24 1321 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_UNICAST_LBN 0 1322 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_UNICAST_WIDTH 1 1323 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_BRDCAST_LBN 1 1324 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_BRDCAST_WIDTH 1 1325 #define MC_CMD_FC_IN_MAC_SET_LINK_FCNTL_OFST 28 1326 1327 /* MC_CMD_FC_IN_MAC_READ_STATUS msgrequest */ 1328 #define MC_CMD_FC_IN_MAC_READ_STATUS_LEN 8 1329 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1330 /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ 1331 1332 /* MC_CMD_FC_IN_MAC_GET_RX_STATS msgrequest */ 1333 #define MC_CMD_FC_IN_MAC_GET_RX_STATS_LEN 8 1334 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1335 /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ 1336 1337 /* MC_CMD_FC_IN_MAC_GET_TX_STATS msgrequest */ 1338 #define MC_CMD_FC_IN_MAC_GET_TX_STATS_LEN 8 1339 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1340 /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ 1341 1342 /* MC_CMD_FC_IN_MAC_GET_STATS msgrequest */ 1343 #define MC_CMD_FC_IN_MAC_GET_STATS_LEN 20 1344 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1345 /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ 1346 /* MC Statistics index */ 1347 #define MC_CMD_FC_IN_MAC_GET_STATS_STATS_INDEX_OFST 8 1348 #define MC_CMD_FC_IN_MAC_GET_STATS_FLAGS_OFST 12 1349 #define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_ALL_LBN 0 1350 #define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_ALL_WIDTH 1 1351 #define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_LBN 1 1352 #define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_WIDTH 1 1353 #define MC_CMD_FC_IN_MAC_GET_STATS_UPDATE_LBN 2 1354 #define MC_CMD_FC_IN_MAC_GET_STATS_UPDATE_WIDTH 1 1355 /* Number of statistics to read */ 1356 #define MC_CMD_FC_IN_MAC_GET_STATS_NUM_OFST 16 1357 #define MC_CMD_FC_MAC_NSTATS_PER_BLOCK 0x1e /* enum */ 1358 #define MC_CMD_FC_MAC_NBYTES_PER_STAT 0x8 /* enum */ 1359 1360 /* MC_CMD_FC_IN_READ32 msgrequest */ 1361 #define MC_CMD_FC_IN_READ32_LEN 16 1362 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1363 #define MC_CMD_FC_IN_READ32_ADDR_HI_OFST 4 1364 #define MC_CMD_FC_IN_READ32_ADDR_LO_OFST 8 1365 #define MC_CMD_FC_IN_READ32_NUMWORDS_OFST 12 1366 1367 /* MC_CMD_FC_IN_WRITE32 msgrequest */ 1368 #define MC_CMD_FC_IN_WRITE32_LENMIN 16 1369 #define MC_CMD_FC_IN_WRITE32_LENMAX 252 1370 #define MC_CMD_FC_IN_WRITE32_LEN(num) (12+4*(num)) 1371 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1372 #define MC_CMD_FC_IN_WRITE32_ADDR_HI_OFST 4 1373 #define MC_CMD_FC_IN_WRITE32_ADDR_LO_OFST 8 1374 #define MC_CMD_FC_IN_WRITE32_BUFFER_OFST 12 1375 #define MC_CMD_FC_IN_WRITE32_BUFFER_LEN 4 1376 #define MC_CMD_FC_IN_WRITE32_BUFFER_MINNUM 1 1377 #define MC_CMD_FC_IN_WRITE32_BUFFER_MAXNUM 60 1378 1379 /* MC_CMD_FC_IN_TRC_READ msgrequest */ 1380 #define MC_CMD_FC_IN_TRC_READ_LEN 12 1381 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1382 #define MC_CMD_FC_IN_TRC_READ_TRC_OFST 4 1383 #define MC_CMD_FC_IN_TRC_READ_CHANNEL_OFST 8 1384 1385 /* MC_CMD_FC_IN_TRC_WRITE msgrequest */ 1386 #define MC_CMD_FC_IN_TRC_WRITE_LEN 28 1387 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1388 #define MC_CMD_FC_IN_TRC_WRITE_TRC_OFST 4 1389 #define MC_CMD_FC_IN_TRC_WRITE_CHANNEL_OFST 8 1390 #define MC_CMD_FC_IN_TRC_WRITE_DATA_OFST 12 1391 #define MC_CMD_FC_IN_TRC_WRITE_DATA_LEN 4 1392 #define MC_CMD_FC_IN_TRC_WRITE_DATA_NUM 4 1393 1394 /* MC_CMD_FC_IN_GET_VERSION msgrequest */ 1395 #define MC_CMD_FC_IN_GET_VERSION_LEN 4 1396 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1397 1398 /* MC_CMD_FC_IN_TRC_RX_READ msgrequest */ 1399 #define MC_CMD_FC_IN_TRC_RX_READ_LEN 12 1400 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1401 #define MC_CMD_FC_IN_TRC_RX_READ_TRC_OFST 4 1402 #define MC_CMD_FC_IN_TRC_RX_READ_CHANNEL_OFST 8 1403 1404 /* MC_CMD_FC_IN_TRC_RX_WRITE msgrequest */ 1405 #define MC_CMD_FC_IN_TRC_RX_WRITE_LEN 20 1406 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1407 #define MC_CMD_FC_IN_TRC_RX_WRITE_TRC_OFST 4 1408 #define MC_CMD_FC_IN_TRC_RX_WRITE_CHANNEL_OFST 8 1409 #define MC_CMD_FC_IN_TRC_RX_WRITE_DATA_OFST 12 1410 #define MC_CMD_FC_IN_TRC_RX_WRITE_DATA_LEN 4 1411 #define MC_CMD_FC_IN_TRC_RX_WRITE_DATA_NUM 2 1412 1413 /* MC_CMD_FC_IN_SFP msgrequest */ 1414 #define MC_CMD_FC_IN_SFP_LEN 28 1415 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1416 /* Link speed is 100, 1000, 10000, 40000 */ 1417 #define MC_CMD_FC_IN_SFP_SPEED_OFST 4 1418 /* Length of copper cable - zero when not relevant (e.g. if cable is fibre) */ 1419 #define MC_CMD_FC_IN_SFP_COPPER_LEN_OFST 8 1420 /* Not relevant for cards with QSFP modules. For older cards, true if module is 1421 * a dual speed SFP+ module. 1422 */ 1423 #define MC_CMD_FC_IN_SFP_DUAL_SPEED_OFST 12 1424 /* True if an SFP Module is present (other fields valid when true) */ 1425 #define MC_CMD_FC_IN_SFP_PRESENT_OFST 16 1426 /* The type of the SFP+ Module. For later cards with QSFP modules, this field 1427 * is unused and the type is communicated by other means. 1428 */ 1429 #define MC_CMD_FC_IN_SFP_TYPE_OFST 20 1430 /* Capabilities corresponding to 1 bits. */ 1431 #define MC_CMD_FC_IN_SFP_CAPS_OFST 24 1432 1433 /* MC_CMD_FC_IN_DDR_TEST msgrequest */ 1434 #define MC_CMD_FC_IN_DDR_TEST_LEN 8 1435 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1436 #define MC_CMD_FC_IN_DDR_TEST_HEADER_OFST 4 1437 #define MC_CMD_FC_IN_DDR_TEST_OP_LBN 0 1438 #define MC_CMD_FC_IN_DDR_TEST_OP_WIDTH 8 1439 /* enum: DRAM Test Start */ 1440 #define MC_CMD_FC_OP_DDR_TEST_START 0x1 1441 /* enum: DRAM Test Poll */ 1442 #define MC_CMD_FC_OP_DDR_TEST_POLL 0x2 1443 1444 /* MC_CMD_FC_IN_DDR_TEST_START msgrequest */ 1445 #define MC_CMD_FC_IN_DDR_TEST_START_LEN 12 1446 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1447 /* MC_CMD_FC_IN_DDR_TEST_HEADER_OFST 4 */ 1448 #define MC_CMD_FC_IN_DDR_TEST_START_MASK_OFST 8 1449 #define MC_CMD_FC_IN_DDR_TEST_START_T0_LBN 0 1450 #define MC_CMD_FC_IN_DDR_TEST_START_T0_WIDTH 1 1451 #define MC_CMD_FC_IN_DDR_TEST_START_T1_LBN 1 1452 #define MC_CMD_FC_IN_DDR_TEST_START_T1_WIDTH 1 1453 #define MC_CMD_FC_IN_DDR_TEST_START_B0_LBN 2 1454 #define MC_CMD_FC_IN_DDR_TEST_START_B0_WIDTH 1 1455 #define MC_CMD_FC_IN_DDR_TEST_START_B1_LBN 3 1456 #define MC_CMD_FC_IN_DDR_TEST_START_B1_WIDTH 1 1457 1458 /* MC_CMD_FC_IN_DDR_TEST_POLL msgrequest */ 1459 #define MC_CMD_FC_IN_DDR_TEST_POLL_LEN 8 1460 #define MC_CMD_FC_IN_DDR_TEST_CMD_OFST 0 1461 /* MC_CMD_FC_IN_DDR_TEST_HEADER_OFST 4 */ 1462 1463 /* MC_CMD_FC_IN_GET_ASSERT msgrequest */ 1464 #define MC_CMD_FC_IN_GET_ASSERT_LEN 4 1465 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1466 1467 /* MC_CMD_FC_IN_FPGA_BUILD msgrequest */ 1468 #define MC_CMD_FC_IN_FPGA_BUILD_LEN 8 1469 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1470 /* FPGA build info operation code */ 1471 #define MC_CMD_FC_IN_FPGA_BUILD_OP_OFST 4 1472 /* enum: Get the build registers */ 1473 #define MC_CMD_FC_IN_FPGA_BUILD_BUILD 0x1 1474 /* enum: Get the services registers */ 1475 #define MC_CMD_FC_IN_FPGA_BUILD_SERVICES 0x2 1476 /* enum: Get the BSP version */ 1477 #define MC_CMD_FC_IN_FPGA_BUILD_BSP_VERSION 0x3 1478 1479 /* MC_CMD_FC_IN_READ_MAP msgrequest */ 1480 #define MC_CMD_FC_IN_READ_MAP_LEN 8 1481 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1482 #define MC_CMD_FC_IN_READ_MAP_HEADER_OFST 4 1483 #define MC_CMD_FC_IN_READ_MAP_OP_LBN 0 1484 #define MC_CMD_FC_IN_READ_MAP_OP_WIDTH 8 1485 /* enum: Get the number of map regions */ 1486 #define MC_CMD_FC_OP_READ_MAP_COUNT 0x1 1487 /* enum: Get the specified map */ 1488 #define MC_CMD_FC_OP_READ_MAP_INDEX 0x2 1489 1490 /* MC_CMD_FC_IN_READ_MAP_COUNT msgrequest */ 1491 #define MC_CMD_FC_IN_READ_MAP_COUNT_LEN 8 1492 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1493 /* MC_CMD_FC_IN_READ_MAP_HEADER_OFST 4 */ 1494 1495 /* MC_CMD_FC_IN_READ_MAP_INDEX msgrequest */ 1496 #define MC_CMD_FC_IN_READ_MAP_INDEX_LEN 12 1497 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1498 /* MC_CMD_FC_IN_READ_MAP_HEADER_OFST 4 */ 1499 #define MC_CMD_FC_IN_MAP_INDEX_OFST 8 1500 1501 /* MC_CMD_FC_IN_CAPABILITIES msgrequest */ 1502 #define MC_CMD_FC_IN_CAPABILITIES_LEN 4 1503 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1504 1505 /* MC_CMD_FC_IN_GLOBAL_FLAGS msgrequest */ 1506 #define MC_CMD_FC_IN_GLOBAL_FLAGS_LEN 8 1507 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1508 #define MC_CMD_FC_IN_GLOBAL_FLAGS_FLAGS_OFST 4 1509 #define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_CABLE_PLUGGED_IN_LBN 0 1510 #define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_CABLE_PLUGGED_IN_WIDTH 1 1511 #define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_LINK_MONITORING_LBN 1 1512 #define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_LINK_MONITORING_WIDTH 1 1513 #define MC_CMD_FC_IN_GLOBAL_FLAGS_DFE_ENABLE_LBN 2 1514 #define MC_CMD_FC_IN_GLOBAL_FLAGS_DFE_ENABLE_WIDTH 1 1515 #define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_EYE_ENABLE_LBN 3 1516 #define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_EYE_ENABLE_WIDTH 1 1517 #define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_TUNING_ENABLE_LBN 4 1518 #define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_TUNING_ENABLE_WIDTH 1 1519 #define MC_CMD_FC_IN_GLOBAL_FLAGS_OFFCAL_ENABLE_LBN 5 1520 #define MC_CMD_FC_IN_GLOBAL_FLAGS_OFFCAL_ENABLE_WIDTH 1 1521 1522 /* MC_CMD_FC_IN_IO_REL msgrequest */ 1523 #define MC_CMD_FC_IN_IO_REL_LEN 8 1524 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1525 #define MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 1526 #define MC_CMD_FC_IN_IO_REL_OP_LBN 0 1527 #define MC_CMD_FC_IN_IO_REL_OP_WIDTH 8 1528 /* enum: Get the base address that the FC applies to relative commands */ 1529 #define MC_CMD_FC_IN_IO_REL_GET_ADDR 0x1 1530 /* enum: Read data */ 1531 #define MC_CMD_FC_IN_IO_REL_READ32 0x2 1532 /* enum: Write data */ 1533 #define MC_CMD_FC_IN_IO_REL_WRITE32 0x3 1534 #define MC_CMD_FC_IN_IO_REL_COMP_TYPE_LBN 8 1535 #define MC_CMD_FC_IN_IO_REL_COMP_TYPE_WIDTH 8 1536 /* enum: Application address space */ 1537 #define MC_CMD_FC_COMP_TYPE_APP_ADDR_SPACE 0x1 1538 /* enum: Flash address space */ 1539 #define MC_CMD_FC_COMP_TYPE_FLASH 0x2 1540 1541 /* MC_CMD_FC_IN_IO_REL_GET_ADDR msgrequest */ 1542 #define MC_CMD_FC_IN_IO_REL_GET_ADDR_LEN 8 1543 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1544 /* MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 */ 1545 1546 /* MC_CMD_FC_IN_IO_REL_READ32 msgrequest */ 1547 #define MC_CMD_FC_IN_IO_REL_READ32_LEN 20 1548 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1549 /* MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 */ 1550 #define MC_CMD_FC_IN_IO_REL_READ32_ADDR_HI_OFST 8 1551 #define MC_CMD_FC_IN_IO_REL_READ32_ADDR_LO_OFST 12 1552 #define MC_CMD_FC_IN_IO_REL_READ32_NUMWORDS_OFST 16 1553 1554 /* MC_CMD_FC_IN_IO_REL_WRITE32 msgrequest */ 1555 #define MC_CMD_FC_IN_IO_REL_WRITE32_LENMIN 20 1556 #define MC_CMD_FC_IN_IO_REL_WRITE32_LENMAX 252 1557 #define MC_CMD_FC_IN_IO_REL_WRITE32_LEN(num) (16+4*(num)) 1558 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1559 /* MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 */ 1560 #define MC_CMD_FC_IN_IO_REL_WRITE32_ADDR_HI_OFST 8 1561 #define MC_CMD_FC_IN_IO_REL_WRITE32_ADDR_LO_OFST 12 1562 #define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_OFST 16 1563 #define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_LEN 4 1564 #define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_MINNUM 1 1565 #define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_MAXNUM 59 1566 1567 /* MC_CMD_FC_IN_UHLINK msgrequest */ 1568 #define MC_CMD_FC_IN_UHLINK_LEN 8 1569 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1570 #define MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 1571 #define MC_CMD_FC_IN_UHLINK_OP_LBN 0 1572 #define MC_CMD_FC_IN_UHLINK_OP_WIDTH 8 1573 /* enum: Get PHY configuration info */ 1574 #define MC_CMD_FC_OP_UHLINK_PHY 0x1 1575 /* enum: Get MAC configuration info */ 1576 #define MC_CMD_FC_OP_UHLINK_MAC 0x2 1577 /* enum: Get Rx eye table */ 1578 #define MC_CMD_FC_OP_UHLINK_RX_EYE 0x3 1579 /* enum: Get Rx eye plot */ 1580 #define MC_CMD_FC_OP_UHLINK_DUMP_RX_EYE_PLOT 0x4 1581 /* enum: Get Rx eye plot */ 1582 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT 0x5 1583 /* enum: Retune Rx settings */ 1584 #define MC_CMD_FC_OP_UHLINK_RX_TUNE 0x6 1585 /* enum: Set loopback mode on fpga port */ 1586 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET 0x7 1587 /* enum: Get loopback mode config state on fpga port */ 1588 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_GET 0x8 1589 #define MC_CMD_FC_IN_UHLINK_PORT_TYPE_LBN 8 1590 #define MC_CMD_FC_IN_UHLINK_PORT_TYPE_WIDTH 8 1591 #define MC_CMD_FC_IN_UHLINK_PORT_IDX_LBN 16 1592 #define MC_CMD_FC_IN_UHLINK_PORT_IDX_WIDTH 8 1593 #define MC_CMD_FC_IN_UHLINK_CMD_FORMAT_LBN 24 1594 #define MC_CMD_FC_IN_UHLINK_CMD_FORMAT_WIDTH 8 1595 /* enum: Default FC command format; the fields PORT_TYPE and PORT_IDX are 1596 * irrelevant. Port number is derived from pci_fn; passed in FC header. 1597 */ 1598 #define MC_CMD_FC_OP_UHLINK_CMD_FORMAT_DEFAULT 0x0 1599 /* enum: Override default port number. Port number determined by fields 1600 * PORT_TYPE and PORT_IDX. 1601 */ 1602 #define MC_CMD_FC_OP_UHLINK_CMD_FORMAT_PORT_OVERRIDE 0x1 1603 1604 /* MC_CMD_FC_OP_UHLINK_PHY msgrequest */ 1605 #define MC_CMD_FC_OP_UHLINK_PHY_LEN 8 1606 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1607 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 1608 1609 /* MC_CMD_FC_OP_UHLINK_MAC msgrequest */ 1610 #define MC_CMD_FC_OP_UHLINK_MAC_LEN 8 1611 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1612 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 1613 1614 /* MC_CMD_FC_OP_UHLINK_RX_EYE msgrequest */ 1615 #define MC_CMD_FC_OP_UHLINK_RX_EYE_LEN 12 1616 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1617 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 1618 #define MC_CMD_FC_OP_UHLINK_RX_EYE_INDEX_OFST 8 1619 #define MC_CMD_FC_UHLINK_RX_EYE_PER_BLOCK 0x30 /* enum */ 1620 1621 /* MC_CMD_FC_OP_UHLINK_DUMP_RX_EYE_PLOT msgrequest */ 1622 #define MC_CMD_FC_OP_UHLINK_DUMP_RX_EYE_PLOT_LEN 8 1623 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1624 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 1625 1626 /* MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT msgrequest */ 1627 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_LEN 20 1628 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1629 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 1630 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_DC_GAIN_OFST 8 1631 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_EQ_CONTROL_OFST 12 1632 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_INDEX_OFST 16 1633 #define MC_CMD_FC_UHLINK_RX_EYE_PLOT_ROWS_PER_BLOCK 0x1e /* enum */ 1634 1635 /* MC_CMD_FC_OP_UHLINK_RX_TUNE msgrequest */ 1636 #define MC_CMD_FC_OP_UHLINK_RX_TUNE_LEN 8 1637 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1638 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 1639 1640 /* MC_CMD_FC_OP_UHLINK_LOOPBACK_SET msgrequest */ 1641 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET_LEN 16 1642 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1643 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 1644 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET_TYPE_OFST 8 1645 #define MC_CMD_FC_UHLINK_LOOPBACK_TYPE_PCS_SERIAL 0x0 /* enum */ 1646 #define MC_CMD_FC_UHLINK_LOOPBACK_TYPE_PMA_PRE_CDR 0x1 /* enum */ 1647 #define MC_CMD_FC_UHLINK_LOOPBACK_TYPE_PMA_POST_CDR 0x2 /* enum */ 1648 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET_STATE_OFST 12 1649 #define MC_CMD_FC_UHLINK_LOOPBACK_STATE_OFF 0x0 /* enum */ 1650 #define MC_CMD_FC_UHLINK_LOOPBACK_STATE_ON 0x1 /* enum */ 1651 1652 /* MC_CMD_FC_OP_UHLINK_LOOPBACK_GET msgrequest */ 1653 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_GET_LEN 12 1654 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1655 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 1656 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_GET_TYPE_OFST 8 1657 1658 /* MC_CMD_FC_IN_SET_LINK msgrequest */ 1659 #define MC_CMD_FC_IN_SET_LINK_LEN 16 1660 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1661 /* See MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */ 1662 #define MC_CMD_FC_IN_SET_LINK_MODE_OFST 4 1663 #define MC_CMD_FC_IN_SET_LINK_SPEED_OFST 8 1664 #define MC_CMD_FC_IN_SET_LINK_FLAGS_OFST 12 1665 #define MC_CMD_FC_IN_SET_LINK_LOWPOWER_LBN 0 1666 #define MC_CMD_FC_IN_SET_LINK_LOWPOWER_WIDTH 1 1667 #define MC_CMD_FC_IN_SET_LINK_POWEROFF_LBN 1 1668 #define MC_CMD_FC_IN_SET_LINK_POWEROFF_WIDTH 1 1669 #define MC_CMD_FC_IN_SET_LINK_TXDIS_LBN 2 1670 #define MC_CMD_FC_IN_SET_LINK_TXDIS_WIDTH 1 1671 1672 /* MC_CMD_FC_IN_LICENSE msgrequest */ 1673 #define MC_CMD_FC_IN_LICENSE_LEN 8 1674 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1675 #define MC_CMD_FC_IN_LICENSE_OP_OFST 4 1676 #define MC_CMD_FC_IN_LICENSE_UPDATE_LICENSE 0x0 /* enum */ 1677 #define MC_CMD_FC_IN_LICENSE_GET_KEY_STATS 0x1 /* enum */ 1678 1679 /* MC_CMD_FC_IN_STARTUP msgrequest */ 1680 #define MC_CMD_FC_IN_STARTUP_LEN 40 1681 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1682 #define MC_CMD_FC_IN_STARTUP_BASE_OFST 4 1683 #define MC_CMD_FC_IN_STARTUP_LENGTH_OFST 8 1684 /* Length of identifier */ 1685 #define MC_CMD_FC_IN_STARTUP_IDLENGTH_OFST 12 1686 /* Identifier for AOE FPGA */ 1687 #define MC_CMD_FC_IN_STARTUP_ID_OFST 16 1688 #define MC_CMD_FC_IN_STARTUP_ID_LEN 1 1689 #define MC_CMD_FC_IN_STARTUP_ID_NUM 24 1690 1691 /* MC_CMD_FC_IN_DMA msgrequest */ 1692 #define MC_CMD_FC_IN_DMA_LEN 8 1693 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1694 #define MC_CMD_FC_IN_DMA_OP_OFST 4 1695 #define MC_CMD_FC_IN_DMA_STOP 0x0 /* enum */ 1696 #define MC_CMD_FC_IN_DMA_READ 0x1 /* enum */ 1697 1698 /* MC_CMD_FC_IN_DMA_STOP msgrequest */ 1699 #define MC_CMD_FC_IN_DMA_STOP_LEN 12 1700 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1701 /* MC_CMD_FC_IN_DMA_OP_OFST 4 */ 1702 /* FC supplied handle */ 1703 #define MC_CMD_FC_IN_DMA_STOP_FC_HANDLE_OFST 8 1704 1705 /* MC_CMD_FC_IN_DMA_READ msgrequest */ 1706 #define MC_CMD_FC_IN_DMA_READ_LEN 16 1707 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1708 /* MC_CMD_FC_IN_DMA_OP_OFST 4 */ 1709 #define MC_CMD_FC_IN_DMA_READ_OFFSET_OFST 8 1710 #define MC_CMD_FC_IN_DMA_READ_LENGTH_OFST 12 1711 1712 /* MC_CMD_FC_IN_TIMED_READ msgrequest */ 1713 #define MC_CMD_FC_IN_TIMED_READ_LEN 8 1714 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1715 #define MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 1716 #define MC_CMD_FC_IN_TIMED_READ_SET 0x0 /* enum */ 1717 #define MC_CMD_FC_IN_TIMED_READ_GET 0x1 /* enum */ 1718 #define MC_CMD_FC_IN_TIMED_READ_CLEAR 0x2 /* enum */ 1719 1720 /* MC_CMD_FC_IN_TIMED_READ_SET msgrequest */ 1721 #define MC_CMD_FC_IN_TIMED_READ_SET_LEN 52 1722 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1723 /* MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 */ 1724 /* Host supplied handle (unique) */ 1725 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_HANDLE_OFST 8 1726 /* Address into which to transfer data in host */ 1727 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_OFST 12 1728 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_LEN 8 1729 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_LO_OFST 12 1730 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_HI_OFST 16 1731 /* AOE address from which to transfer data */ 1732 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_OFST 20 1733 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_LEN 8 1734 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_LO_OFST 20 1735 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_HI_OFST 24 1736 /* Length of AOE transfer (total) */ 1737 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_LENGTH_OFST 28 1738 /* Length of host transfer (total) */ 1739 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_LENGTH_OFST 32 1740 /* Offset back from aoe_address to apply operation to */ 1741 #define MC_CMD_FC_IN_TIMED_READ_SET_OFFSET_OFST 36 1742 /* Data to apply at offset */ 1743 #define MC_CMD_FC_IN_TIMED_READ_SET_DATA_OFST 40 1744 #define MC_CMD_FC_IN_TIMED_READ_SET_FLAGS_OFST 44 1745 #define MC_CMD_FC_IN_TIMED_READ_SET_INDIRECT_LBN 0 1746 #define MC_CMD_FC_IN_TIMED_READ_SET_INDIRECT_WIDTH 1 1747 #define MC_CMD_FC_IN_TIMED_READ_SET_DOUBLE_LBN 1 1748 #define MC_CMD_FC_IN_TIMED_READ_SET_DOUBLE_WIDTH 1 1749 #define MC_CMD_FC_IN_TIMED_READ_SET_EVENT_LBN 2 1750 #define MC_CMD_FC_IN_TIMED_READ_SET_EVENT_WIDTH 1 1751 #define MC_CMD_FC_IN_TIMED_READ_SET_PREREAD_LBN 3 1752 #define MC_CMD_FC_IN_TIMED_READ_SET_PREREAD_WIDTH 2 1753 #define MC_CMD_FC_IN_TIMED_READ_SET_NONE 0x0 /* enum */ 1754 #define MC_CMD_FC_IN_TIMED_READ_SET_READ 0x1 /* enum */ 1755 #define MC_CMD_FC_IN_TIMED_READ_SET_WRITE 0x2 /* enum */ 1756 #define MC_CMD_FC_IN_TIMED_READ_SET_READWRITE 0x3 /* enum */ 1757 /* Period at which reads are performed (100ms units) */ 1758 #define MC_CMD_FC_IN_TIMED_READ_SET_PERIOD_OFST 48 1759 1760 /* MC_CMD_FC_IN_TIMED_READ_GET msgrequest */ 1761 #define MC_CMD_FC_IN_TIMED_READ_GET_LEN 12 1762 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1763 /* MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 */ 1764 /* FC supplied handle */ 1765 #define MC_CMD_FC_IN_TIMED_READ_GET_FC_HANDLE_OFST 8 1766 1767 /* MC_CMD_FC_IN_TIMED_READ_CLEAR msgrequest */ 1768 #define MC_CMD_FC_IN_TIMED_READ_CLEAR_LEN 12 1769 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1770 /* MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 */ 1771 /* FC supplied handle */ 1772 #define MC_CMD_FC_IN_TIMED_READ_CLEAR_FC_HANDLE_OFST 8 1773 1774 /* MC_CMD_FC_IN_LOG msgrequest */ 1775 #define MC_CMD_FC_IN_LOG_LEN 8 1776 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1777 #define MC_CMD_FC_IN_LOG_OP_OFST 4 1778 #define MC_CMD_FC_IN_LOG_ADDR_RANGE 0x0 /* enum */ 1779 #define MC_CMD_FC_IN_LOG_JTAG_UART 0x1 /* enum */ 1780 1781 /* MC_CMD_FC_IN_LOG_ADDR_RANGE msgrequest */ 1782 #define MC_CMD_FC_IN_LOG_ADDR_RANGE_LEN 20 1783 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1784 /* MC_CMD_FC_IN_LOG_OP_OFST 4 */ 1785 /* Partition offset into flash */ 1786 #define MC_CMD_FC_IN_LOG_ADDR_RANGE_OFFSET_OFST 8 1787 /* Partition length */ 1788 #define MC_CMD_FC_IN_LOG_ADDR_RANGE_LENGTH_OFST 12 1789 /* Partition erase size */ 1790 #define MC_CMD_FC_IN_LOG_ADDR_RANGE_ERASE_SIZE_OFST 16 1791 1792 /* MC_CMD_FC_IN_LOG_JTAG_UART msgrequest */ 1793 #define MC_CMD_FC_IN_LOG_JTAG_UART_LEN 12 1794 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1795 /* MC_CMD_FC_IN_LOG_OP_OFST 4 */ 1796 /* Enable/disable printing to JTAG UART */ 1797 #define MC_CMD_FC_IN_LOG_JTAG_UART_ENABLE_OFST 8 1798 1799 /* MC_CMD_FC_IN_CLOCK msgrequest */ 1800 #define MC_CMD_FC_IN_CLOCK_LEN 12 1801 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1802 #define MC_CMD_FC_IN_CLOCK_OP_OFST 4 1803 #define MC_CMD_FC_IN_CLOCK_GET_TIME 0x0 /* enum */ 1804 #define MC_CMD_FC_IN_CLOCK_SET_TIME 0x1 /* enum */ 1805 /* Perform a clock operation */ 1806 #define MC_CMD_FC_IN_CLOCK_ID_OFST 8 1807 #define MC_CMD_FC_IN_CLOCK_STATS 0x0 /* enum */ 1808 #define MC_CMD_FC_IN_CLOCK_MAC 0x1 /* enum */ 1809 1810 /* MC_CMD_FC_IN_CLOCK_GET_TIME msgrequest */ 1811 #define MC_CMD_FC_IN_CLOCK_GET_TIME_LEN 12 1812 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1813 /* MC_CMD_FC_IN_CLOCK_OP_OFST 4 */ 1814 /* Retrieve the clock value of the specified clock */ 1815 /* MC_CMD_FC_IN_CLOCK_ID_OFST 8 */ 1816 1817 /* MC_CMD_FC_IN_CLOCK_SET_TIME msgrequest */ 1818 #define MC_CMD_FC_IN_CLOCK_SET_TIME_LEN 24 1819 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1820 /* MC_CMD_FC_IN_CLOCK_OP_OFST 4 */ 1821 /* MC_CMD_FC_IN_CLOCK_ID_OFST 8 */ 1822 #define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_OFST 12 1823 #define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LEN 8 1824 #define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LO_OFST 12 1825 #define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_HI_OFST 16 1826 /* Set the clock value of the specified clock */ 1827 #define MC_CMD_FC_IN_CLOCK_SET_TIME_NANOSECONDS_OFST 20 1828 1829 /* MC_CMD_FC_IN_DDR msgrequest */ 1830 #define MC_CMD_FC_IN_DDR_LEN 12 1831 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1832 #define MC_CMD_FC_IN_DDR_OP_OFST 4 1833 #define MC_CMD_FC_IN_DDR_SET_SPD 0x0 /* enum */ 1834 #define MC_CMD_FC_IN_DDR_GET_STATUS 0x1 /* enum */ 1835 #define MC_CMD_FC_IN_DDR_BANK_OFST 8 1836 #define MC_CMD_FC_IN_DDR_BANK_B0 0x0 /* enum */ 1837 #define MC_CMD_FC_IN_DDR_BANK_B1 0x1 /* enum */ 1838 #define MC_CMD_FC_IN_DDR_BANK_T0 0x2 /* enum */ 1839 #define MC_CMD_FC_IN_DDR_BANK_T1 0x3 /* enum */ 1840 #define MC_CMD_FC_IN_DDR_NUM_BANKS 0x4 /* enum */ 1841 1842 /* MC_CMD_FC_IN_DDR_SET_SPD msgrequest */ 1843 #define MC_CMD_FC_IN_DDR_SET_SPD_LEN 148 1844 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1845 /* MC_CMD_FC_IN_DDR_OP_OFST 4 */ 1846 /* Affected bank */ 1847 /* MC_CMD_FC_IN_DDR_BANK_OFST 8 */ 1848 /* Flags */ 1849 #define MC_CMD_FC_IN_DDR_FLAGS_OFST 12 1850 #define MC_CMD_FC_IN_DDR_SET_SPD_ACTIVE 0x1 /* enum */ 1851 /* 128-byte page of serial presence detect data read from module's EEPROM */ 1852 #define MC_CMD_FC_IN_DDR_SPD_OFST 16 1853 #define MC_CMD_FC_IN_DDR_SPD_LEN 1 1854 #define MC_CMD_FC_IN_DDR_SPD_NUM 128 1855 /* Page index of the spd data copied into MC_CMD_FC_IN_DDR_SPD */ 1856 #define MC_CMD_FC_IN_DDR_SPD_PAGE_ID_OFST 144 1857 1858 /* MC_CMD_FC_IN_DDR_GET_STATUS msgrequest */ 1859 #define MC_CMD_FC_IN_DDR_GET_STATUS_LEN 12 1860 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1861 /* MC_CMD_FC_IN_DDR_OP_OFST 4 */ 1862 /* Affected bank */ 1863 /* MC_CMD_FC_IN_DDR_BANK_OFST 8 */ 1864 1865 /* MC_CMD_FC_IN_TIMESTAMP msgrequest */ 1866 #define MC_CMD_FC_IN_TIMESTAMP_LEN 8 1867 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1868 /* FC timestamp operation code */ 1869 #define MC_CMD_FC_IN_TIMESTAMP_OP_OFST 4 1870 /* enum: Read transmit timestamp(s) */ 1871 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT 0x0 1872 /* enum: Read snapshot timestamps */ 1873 #define MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT 0x1 1874 /* enum: Clear all transmit timestamps */ 1875 #define MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT 0x2 1876 1877 /* MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT msgrequest */ 1878 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_LEN 28 1879 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1880 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_OP_OFST 4 1881 /* Control filtering of the returned timestamp and sequence number specified 1882 * here 1883 */ 1884 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_FILTER_OFST 8 1885 /* enum: Return most recent timestamp. No filtering */ 1886 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_LATEST 0x0 1887 /* enum: Match timestamp against the PTP clock ID, port number and sequence 1888 * number specified 1889 */ 1890 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_MATCH 0x1 1891 /* Clock identity of PTP packet for which timestamp required */ 1892 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_OFST 12 1893 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_LEN 8 1894 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_LO_OFST 12 1895 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_HI_OFST 16 1896 /* Port number of PTP packet for which timestamp required */ 1897 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_PORT_NUM_OFST 20 1898 /* Sequence number of PTP packet for which timestamp required */ 1899 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_SEQ_NUM_OFST 24 1900 1901 /* MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT msgrequest */ 1902 #define MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT_LEN 8 1903 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1904 #define MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT_OP_OFST 4 1905 1906 /* MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT msgrequest */ 1907 #define MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT_LEN 8 1908 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1909 #define MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT_OP_OFST 4 1910 1911 /* MC_CMD_FC_IN_SPI msgrequest */ 1912 #define MC_CMD_FC_IN_SPI_LEN 8 1913 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1914 /* Basic commands for SPI Flash. */ 1915 #define MC_CMD_FC_IN_SPI_OP_OFST 4 1916 /* enum: SPI Flash read */ 1917 #define MC_CMD_FC_IN_SPI_READ 0x0 1918 /* enum: SPI Flash write */ 1919 #define MC_CMD_FC_IN_SPI_WRITE 0x1 1920 /* enum: SPI Flash erase */ 1921 #define MC_CMD_FC_IN_SPI_ERASE 0x2 1922 1923 /* MC_CMD_FC_IN_SPI_READ msgrequest */ 1924 #define MC_CMD_FC_IN_SPI_READ_LEN 16 1925 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1926 #define MC_CMD_FC_IN_SPI_READ_OP_OFST 4 1927 #define MC_CMD_FC_IN_SPI_READ_ADDR_OFST 8 1928 #define MC_CMD_FC_IN_SPI_READ_NUMBYTES_OFST 12 1929 1930 /* MC_CMD_FC_IN_SPI_WRITE msgrequest */ 1931 #define MC_CMD_FC_IN_SPI_WRITE_LENMIN 16 1932 #define MC_CMD_FC_IN_SPI_WRITE_LENMAX 252 1933 #define MC_CMD_FC_IN_SPI_WRITE_LEN(num) (12+4*(num)) 1934 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1935 #define MC_CMD_FC_IN_SPI_WRITE_OP_OFST 4 1936 #define MC_CMD_FC_IN_SPI_WRITE_ADDR_OFST 8 1937 #define MC_CMD_FC_IN_SPI_WRITE_BUFFER_OFST 12 1938 #define MC_CMD_FC_IN_SPI_WRITE_BUFFER_LEN 4 1939 #define MC_CMD_FC_IN_SPI_WRITE_BUFFER_MINNUM 1 1940 #define MC_CMD_FC_IN_SPI_WRITE_BUFFER_MAXNUM 60 1941 1942 /* MC_CMD_FC_IN_SPI_ERASE msgrequest */ 1943 #define MC_CMD_FC_IN_SPI_ERASE_LEN 16 1944 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1945 #define MC_CMD_FC_IN_SPI_ERASE_OP_OFST 4 1946 #define MC_CMD_FC_IN_SPI_ERASE_ADDR_OFST 8 1947 #define MC_CMD_FC_IN_SPI_ERASE_NUMBYTES_OFST 12 1948 1949 /* MC_CMD_FC_IN_DIAG msgrequest */ 1950 #define MC_CMD_FC_IN_DIAG_LEN 8 1951 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1952 /* Operation code indicating component type */ 1953 #define MC_CMD_FC_IN_DIAG_OP_OFST 4 1954 /* enum: Power noise generator. */ 1955 #define MC_CMD_FC_IN_DIAG_POWER_NOISE 0x0 1956 /* enum: DDR soak test component. */ 1957 #define MC_CMD_FC_IN_DIAG_DDR_SOAK 0x1 1958 /* enum: Diagnostics datapath control component. */ 1959 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL 0x2 1960 1961 /* MC_CMD_FC_IN_DIAG_POWER_NOISE msgrequest */ 1962 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_LEN 12 1963 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1964 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_OP_OFST 4 1965 /* Sub-opcode describing the operation to be carried out */ 1966 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_SUB_OP_OFST 8 1967 /* enum: Read the configuration (the 32-bit values in each of the clock enable 1968 * count and toggle count registers) 1969 */ 1970 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG 0x0 1971 /* enum: Write a new configuration to the clock enable count and toggle count 1972 * registers 1973 */ 1974 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG 0x1 1975 1976 /* MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG msgrequest */ 1977 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_LEN 12 1978 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1979 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_OP_OFST 4 1980 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_SUB_OP_OFST 8 1981 1982 /* MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG msgrequest */ 1983 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_LEN 20 1984 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1985 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_OP_OFST 4 1986 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_SUB_OP_OFST 8 1987 /* The 32-bit value to be written to the toggle count register */ 1988 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_TOGGLE_COUNT_OFST 12 1989 /* The 32-bit value to be written to the clock enable count register */ 1990 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_CLKEN_COUNT_OFST 16 1991 1992 /* MC_CMD_FC_IN_DIAG_DDR_SOAK msgrequest */ 1993 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_LEN 12 1994 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1995 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_OP_OFST 4 1996 /* Sub-opcode describing the operation to be carried out */ 1997 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_SUB_OP_OFST 8 1998 /* enum: Starts DDR soak test on selected banks */ 1999 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START 0x0 2000 /* enum: Read status of DDR soak test */ 2001 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT 0x1 2002 /* enum: Stop test */ 2003 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP 0x2 2004 /* enum: Set or clear bit that triggers fake errors. These cause subsequent 2005 * tests to fail until the bit is cleared. 2006 */ 2007 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR 0x3 2008 2009 /* MC_CMD_FC_IN_DIAG_DDR_SOAK_START msgrequest */ 2010 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_LEN 24 2011 /* MC_CMD_FC_IN_CMD_OFST 0 */ 2012 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_OP_OFST 4 2013 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_SUB_OP_OFST 8 2014 /* Mask of DDR banks to be tested */ 2015 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_BANK_MASK_OFST 12 2016 /* Pattern to use in the soak test */ 2017 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_TEST_PATTERN_OFST 16 2018 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_ZEROS 0x0 /* enum */ 2019 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_ONES 0x1 /* enum */ 2020 /* Either multiple automatic tests until a STOP command is issued, or one 2021 * single test 2022 */ 2023 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_TEST_TYPE_OFST 20 2024 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_ONGOING_TEST 0x0 /* enum */ 2025 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_SINGLE_TEST 0x1 /* enum */ 2026 2027 /* MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT msgrequest */ 2028 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_LEN 16 2029 /* MC_CMD_FC_IN_CMD_OFST 0 */ 2030 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_OP_OFST 4 2031 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_SUB_OP_OFST 8 2032 /* DDR bank to read status from */ 2033 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_BANK_ID_OFST 12 2034 #define MC_CMD_FC_DDR_BANK0 0x0 /* enum */ 2035 #define MC_CMD_FC_DDR_BANK1 0x1 /* enum */ 2036 #define MC_CMD_FC_DDR_BANK2 0x2 /* enum */ 2037 #define MC_CMD_FC_DDR_BANK3 0x3 /* enum */ 2038 #define MC_CMD_FC_DDR_AOEMEM_MAX_BANKS 0x4 /* enum */ 2039 2040 /* MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP msgrequest */ 2041 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_LEN 16 2042 /* MC_CMD_FC_IN_CMD_OFST 0 */ 2043 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_OP_OFST 4 2044 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_SUB_OP_OFST 8 2045 /* Mask of DDR banks to be tested */ 2046 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_BANK_MASK_OFST 12 2047 2048 /* MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR msgrequest */ 2049 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_LEN 20 2050 /* MC_CMD_FC_IN_CMD_OFST 0 */ 2051 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_OP_OFST 4 2052 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_SUB_OP_OFST 8 2053 /* Mask of DDR banks to set/clear error flag on */ 2054 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_BANK_MASK_OFST 12 2055 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_FLAG_ACTION_OFST 16 2056 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_CLEAR 0x0 /* enum */ 2057 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_SET 0x1 /* enum */ 2058 2059 /* MC_CMD_FC_IN_DIAG_DATAPATH_CTRL msgrequest */ 2060 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_LEN 12 2061 /* MC_CMD_FC_IN_CMD_OFST 0 */ 2062 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_OP_OFST 4 2063 /* Sub-opcode describing the operation to be carried out */ 2064 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SUB_OP_OFST 8 2065 /* enum: Set a known datapath configuration */ 2066 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE 0x0 2067 /* enum: Apply raw config to datapath control registers */ 2068 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG 0x1 2069 2070 /* MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE msgrequest */ 2071 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_LEN 16 2072 /* MC_CMD_FC_IN_CMD_OFST 0 */ 2073 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_OP_OFST 4 2074 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_SUB_OP_OFST 8 2075 /* Datapath configuration identifier */ 2076 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_MODE_OFST 12 2077 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_PASSTHROUGH 0x0 /* enum */ 2078 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_SNAKE 0x1 /* enum */ 2079 2080 /* MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG msgrequest */ 2081 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_LEN 24 2082 /* MC_CMD_FC_IN_CMD_OFST 0 */ 2083 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_OP_OFST 4 2084 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_SUB_OP_OFST 8 2085 /* Value to write into control register 1 */ 2086 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL1_OFST 12 2087 /* Value to write into control register 2 */ 2088 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL2_OFST 16 2089 /* Value to write into control register 3 */ 2090 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL3_OFST 20 2091 2092 /* MC_CMD_FC_OUT msgresponse */ 2093 #define MC_CMD_FC_OUT_LEN 0 2094 2095 /* MC_CMD_FC_OUT_NULL msgresponse */ 2096 #define MC_CMD_FC_OUT_NULL_LEN 0 2097 2098 /* MC_CMD_FC_OUT_READ32 msgresponse */ 2099 #define MC_CMD_FC_OUT_READ32_LENMIN 4 2100 #define MC_CMD_FC_OUT_READ32_LENMAX 252 2101 #define MC_CMD_FC_OUT_READ32_LEN(num) (0+4*(num)) 2102 #define MC_CMD_FC_OUT_READ32_BUFFER_OFST 0 2103 #define MC_CMD_FC_OUT_READ32_BUFFER_LEN 4 2104 #define MC_CMD_FC_OUT_READ32_BUFFER_MINNUM 1 2105 #define MC_CMD_FC_OUT_READ32_BUFFER_MAXNUM 63 2106 2107 /* MC_CMD_FC_OUT_WRITE32 msgresponse */ 2108 #define MC_CMD_FC_OUT_WRITE32_LEN 0 2109 2110 /* MC_CMD_FC_OUT_TRC_READ msgresponse */ 2111 #define MC_CMD_FC_OUT_TRC_READ_LEN 16 2112 #define MC_CMD_FC_OUT_TRC_READ_DATA_OFST 0 2113 #define MC_CMD_FC_OUT_TRC_READ_DATA_LEN 4 2114 #define MC_CMD_FC_OUT_TRC_READ_DATA_NUM 4 2115 2116 /* MC_CMD_FC_OUT_TRC_WRITE msgresponse */ 2117 #define MC_CMD_FC_OUT_TRC_WRITE_LEN 0 2118 2119 /* MC_CMD_FC_OUT_GET_VERSION msgresponse */ 2120 #define MC_CMD_FC_OUT_GET_VERSION_LEN 12 2121 #define MC_CMD_FC_OUT_GET_VERSION_FIRMWARE_OFST 0 2122 #define MC_CMD_FC_OUT_GET_VERSION_VERSION_OFST 4 2123 #define MC_CMD_FC_OUT_GET_VERSION_VERSION_LEN 8 2124 #define MC_CMD_FC_OUT_GET_VERSION_VERSION_LO_OFST 4 2125 #define MC_CMD_FC_OUT_GET_VERSION_VERSION_HI_OFST 8 2126 2127 /* MC_CMD_FC_OUT_TRC_RX_READ msgresponse */ 2128 #define MC_CMD_FC_OUT_TRC_RX_READ_LEN 8 2129 #define MC_CMD_FC_OUT_TRC_RX_READ_DATA_OFST 0 2130 #define MC_CMD_FC_OUT_TRC_RX_READ_DATA_LEN 4 2131 #define MC_CMD_FC_OUT_TRC_RX_READ_DATA_NUM 2 2132 2133 /* MC_CMD_FC_OUT_TRC_RX_WRITE msgresponse */ 2134 #define MC_CMD_FC_OUT_TRC_RX_WRITE_LEN 0 2135 2136 /* MC_CMD_FC_OUT_MAC_RECONFIGURE msgresponse */ 2137 #define MC_CMD_FC_OUT_MAC_RECONFIGURE_LEN 0 2138 2139 /* MC_CMD_FC_OUT_MAC_SET_LINK msgresponse */ 2140 #define MC_CMD_FC_OUT_MAC_SET_LINK_LEN 0 2141 2142 /* MC_CMD_FC_OUT_MAC_READ_STATUS msgresponse */ 2143 #define MC_CMD_FC_OUT_MAC_READ_STATUS_LEN 4 2144 #define MC_CMD_FC_OUT_MAC_READ_STATUS_STATUS_OFST 0 2145 2146 /* MC_CMD_FC_OUT_MAC_GET_RX_STATS msgresponse */ 2147 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_LEN ((((0-1+(64*MC_CMD_FC_MAC_RX_NSTATS))+1))>>3) 2148 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_OFST 0 2149 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_LEN 8 2150 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_LO_OFST 0 2151 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_HI_OFST 4 2152 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_NUM MC_CMD_FC_MAC_RX_NSTATS 2153 #define MC_CMD_FC_MAC_RX_STATS_OCTETS 0x0 /* enum */ 2154 #define MC_CMD_FC_MAC_RX_OCTETS_OK 0x1 /* enum */ 2155 #define MC_CMD_FC_MAC_RX_ALIGNMENT_ERRORS 0x2 /* enum */ 2156 #define MC_CMD_FC_MAC_RX_PAUSE_MAC_CTRL_FRAMES 0x3 /* enum */ 2157 #define MC_CMD_FC_MAC_RX_FRAMES_OK 0x4 /* enum */ 2158 #define MC_CMD_FC_MAC_RX_CRC_ERRORS 0x5 /* enum */ 2159 #define MC_CMD_FC_MAC_RX_VLAN_OK 0x6 /* enum */ 2160 #define MC_CMD_FC_MAC_RX_ERRORS 0x7 /* enum */ 2161 #define MC_CMD_FC_MAC_RX_UCAST_PKTS 0x8 /* enum */ 2162 #define MC_CMD_FC_MAC_RX_MULTICAST_PKTS 0x9 /* enum */ 2163 #define MC_CMD_FC_MAC_RX_BROADCAST_PKTS 0xa /* enum */ 2164 #define MC_CMD_FC_MAC_RX_STATS_DROP_EVENTS 0xb /* enum */ 2165 #define MC_CMD_FC_MAC_RX_STATS_PKTS 0xc /* enum */ 2166 #define MC_CMD_FC_MAC_RX_STATS_UNDERSIZE_PKTS 0xd /* enum */ 2167 #define MC_CMD_FC_MAC_RX_STATS_PKTS_64 0xe /* enum */ 2168 #define MC_CMD_FC_MAC_RX_STATS_PKTS_65_127 0xf /* enum */ 2169 #define MC_CMD_FC_MAC_RX_STATS_PKTS_128_255 0x10 /* enum */ 2170 #define MC_CMD_FC_MAC_RX_STATS_PKTS_256_511 0x11 /* enum */ 2171 #define MC_CMD_FC_MAC_RX_STATS_PKTS_512_1023 0x12 /* enum */ 2172 #define MC_CMD_FC_MAC_RX_STATS_PKTS_1024_1518 0x13 /* enum */ 2173 #define MC_CMD_FC_MAC_RX_STATS_PKTS_1519_MAX 0x14 /* enum */ 2174 #define MC_CMD_FC_MAC_RX_STATS_OVERSIZE_PKTS 0x15 /* enum */ 2175 #define MC_CMD_FC_MAC_RX_STATS_JABBERS 0x16 /* enum */ 2176 #define MC_CMD_FC_MAC_RX_STATS_FRAGMENTS 0x17 /* enum */ 2177 #define MC_CMD_FC_MAC_RX_MAC_CONTROL_FRAMES 0x18 /* enum */ 2178 /* enum: (Last entry) */ 2179 #define MC_CMD_FC_MAC_RX_NSTATS 0x19 2180 2181 /* MC_CMD_FC_OUT_MAC_GET_TX_STATS msgresponse */ 2182 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_LEN ((((0-1+(64*MC_CMD_FC_MAC_TX_NSTATS))+1))>>3) 2183 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_OFST 0 2184 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_LEN 8 2185 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_LO_OFST 0 2186 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_HI_OFST 4 2187 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_NUM MC_CMD_FC_MAC_TX_NSTATS 2188 #define MC_CMD_FC_MAC_TX_STATS_OCTETS 0x0 /* enum */ 2189 #define MC_CMD_FC_MAC_TX_OCTETS_OK 0x1 /* enum */ 2190 #define MC_CMD_FC_MAC_TX_ALIGNMENT_ERRORS 0x2 /* enum */ 2191 #define MC_CMD_FC_MAC_TX_PAUSE_MAC_CTRL_FRAMES 0x3 /* enum */ 2192 #define MC_CMD_FC_MAC_TX_FRAMES_OK 0x4 /* enum */ 2193 #define MC_CMD_FC_MAC_TX_CRC_ERRORS 0x5 /* enum */ 2194 #define MC_CMD_FC_MAC_TX_VLAN_OK 0x6 /* enum */ 2195 #define MC_CMD_FC_MAC_TX_ERRORS 0x7 /* enum */ 2196 #define MC_CMD_FC_MAC_TX_UCAST_PKTS 0x8 /* enum */ 2197 #define MC_CMD_FC_MAC_TX_MULTICAST_PKTS 0x9 /* enum */ 2198 #define MC_CMD_FC_MAC_TX_BROADCAST_PKTS 0xa /* enum */ 2199 #define MC_CMD_FC_MAC_TX_STATS_DROP_EVENTS 0xb /* enum */ 2200 #define MC_CMD_FC_MAC_TX_STATS_PKTS 0xc /* enum */ 2201 #define MC_CMD_FC_MAC_TX_STATS_UNDERSIZE_PKTS 0xd /* enum */ 2202 #define MC_CMD_FC_MAC_TX_STATS_PKTS_64 0xe /* enum */ 2203 #define MC_CMD_FC_MAC_TX_STATS_PKTS_65_127 0xf /* enum */ 2204 #define MC_CMD_FC_MAC_TX_STATS_PKTS_128_255 0x10 /* enum */ 2205 #define MC_CMD_FC_MAC_TX_STATS_PKTS_256_511 0x11 /* enum */ 2206 #define MC_CMD_FC_MAC_TX_STATS_PKTS_512_1023 0x12 /* enum */ 2207 #define MC_CMD_FC_MAC_TX_STATS_PKTS_1024_1518 0x13 /* enum */ 2208 #define MC_CMD_FC_MAC_TX_STATS_PKTS_1519_TX_MTU 0x14 /* enum */ 2209 #define MC_CMD_FC_MAC_TX_MAC_CONTROL_FRAMES 0x15 /* enum */ 2210 /* enum: (Last entry) */ 2211 #define MC_CMD_FC_MAC_TX_NSTATS 0x16 2212 2213 /* MC_CMD_FC_OUT_MAC_GET_STATS msgresponse */ 2214 #define MC_CMD_FC_OUT_MAC_GET_STATS_LEN ((((0-1+(64*MC_CMD_FC_MAC_NSTATS_PER_BLOCK))+1))>>3) 2215 /* MAC Statistics */ 2216 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_OFST 0 2217 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_LEN 8 2218 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_LO_OFST 0 2219 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_HI_OFST 4 2220 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_NUM MC_CMD_FC_MAC_NSTATS_PER_BLOCK 2221 2222 /* MC_CMD_FC_OUT_MAC msgresponse */ 2223 #define MC_CMD_FC_OUT_MAC_LEN 0 2224 2225 /* MC_CMD_FC_OUT_SFP msgresponse */ 2226 #define MC_CMD_FC_OUT_SFP_LEN 0 2227 2228 /* MC_CMD_FC_OUT_DDR_TEST_START msgresponse */ 2229 #define MC_CMD_FC_OUT_DDR_TEST_START_LEN 0 2230 2231 /* MC_CMD_FC_OUT_DDR_TEST_POLL msgresponse */ 2232 #define MC_CMD_FC_OUT_DDR_TEST_POLL_LEN 8 2233 #define MC_CMD_FC_OUT_DDR_TEST_POLL_STATUS_OFST 0 2234 #define MC_CMD_FC_OUT_DDR_TEST_POLL_CODE_LBN 0 2235 #define MC_CMD_FC_OUT_DDR_TEST_POLL_CODE_WIDTH 8 2236 /* enum: Test not yet initiated */ 2237 #define MC_CMD_FC_OP_DDR_TEST_NONE 0x0 2238 /* enum: Test is in progress */ 2239 #define MC_CMD_FC_OP_DDR_TEST_INPROGRESS 0x1 2240 /* enum: Timed completed */ 2241 #define MC_CMD_FC_OP_DDR_TEST_SUCCESS 0x2 2242 /* enum: Test did not complete in specified time */ 2243 #define MC_CMD_FC_OP_DDR_TEST_TIMER_EXPIRED 0x3 2244 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T0_LBN 11 2245 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T0_WIDTH 1 2246 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T1_LBN 10 2247 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T1_WIDTH 1 2248 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B0_LBN 9 2249 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B0_WIDTH 1 2250 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B1_LBN 8 2251 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B1_WIDTH 1 2252 /* Test result from FPGA */ 2253 #define MC_CMD_FC_OUT_DDR_TEST_POLL_RESULT_OFST 4 2254 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T0_LBN 31 2255 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T0_WIDTH 1 2256 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T1_LBN 30 2257 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T1_WIDTH 1 2258 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B0_LBN 29 2259 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B0_WIDTH 1 2260 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B1_LBN 28 2261 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B1_WIDTH 1 2262 #define MC_CMD_FC_OUT_DDR_TEST_POLL_T0_LBN 15 2263 #define MC_CMD_FC_OUT_DDR_TEST_POLL_T0_WIDTH 5 2264 #define MC_CMD_FC_OUT_DDR_TEST_POLL_T1_LBN 10 2265 #define MC_CMD_FC_OUT_DDR_TEST_POLL_T1_WIDTH 5 2266 #define MC_CMD_FC_OUT_DDR_TEST_POLL_B0_LBN 5 2267 #define MC_CMD_FC_OUT_DDR_TEST_POLL_B0_WIDTH 5 2268 #define MC_CMD_FC_OUT_DDR_TEST_POLL_B1_LBN 0 2269 #define MC_CMD_FC_OUT_DDR_TEST_POLL_B1_WIDTH 5 2270 #define MC_CMD_FC_OUT_DDR_TEST_POLL_TEST_COMPLETE 0x0 /* enum */ 2271 #define MC_CMD_FC_OUT_DDR_TEST_POLL_TEST_FAIL 0x1 /* enum */ 2272 #define MC_CMD_FC_OUT_DDR_TEST_POLL_TEST_PASS 0x2 /* enum */ 2273 #define MC_CMD_FC_OUT_DDR_TEST_POLL_CAL_FAIL 0x3 /* enum */ 2274 #define MC_CMD_FC_OUT_DDR_TEST_POLL_CAL_SUCCESS 0x4 /* enum */ 2275 2276 /* MC_CMD_FC_OUT_DDR_TEST msgresponse */ 2277 #define MC_CMD_FC_OUT_DDR_TEST_LEN 0 2278 2279 /* MC_CMD_FC_OUT_GET_ASSERT msgresponse */ 2280 #define MC_CMD_FC_OUT_GET_ASSERT_LEN 144 2281 /* Assertion status flag. */ 2282 #define MC_CMD_FC_OUT_GET_ASSERT_GLOBAL_FLAGS_OFST 0 2283 #define MC_CMD_FC_OUT_GET_ASSERT_STATE_LBN 8 2284 #define MC_CMD_FC_OUT_GET_ASSERT_STATE_WIDTH 8 2285 /* enum: No crash data available */ 2286 #define MC_CMD_FC_GET_ASSERT_FLAGS_STATE_CLEAR 0x0 2287 /* enum: New crash data available */ 2288 #define MC_CMD_FC_GET_ASSERT_FLAGS_STATE_NEW 0x1 2289 /* enum: Crash data has been sent */ 2290 #define MC_CMD_FC_GET_ASSERT_FLAGS_STATE_NOTIFIED 0x2 2291 #define MC_CMD_FC_OUT_GET_ASSERT_TYPE_LBN 0 2292 #define MC_CMD_FC_OUT_GET_ASSERT_TYPE_WIDTH 8 2293 /* enum: No crash has been recorded. */ 2294 #define MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_NONE 0x0 2295 /* enum: Crash due to exception. */ 2296 #define MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_EXCEPTION 0x1 2297 /* enum: Crash due to assertion. */ 2298 #define MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_ASSERTION 0x2 2299 /* Failing PC value */ 2300 #define MC_CMD_FC_OUT_GET_ASSERT_SAVED_PC_OFFS_OFST 4 2301 /* Saved GP regs */ 2302 #define MC_CMD_FC_OUT_GET_ASSERT_GP_REGS_OFFS_OFST 8 2303 #define MC_CMD_FC_OUT_GET_ASSERT_GP_REGS_OFFS_LEN 4 2304 #define MC_CMD_FC_OUT_GET_ASSERT_GP_REGS_OFFS_NUM 31 2305 /* Exception Type */ 2306 #define MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_TYPE_OFFS_OFST 132 2307 /* Instruction at which exception occurred */ 2308 #define MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_PC_ADDR_OFFS_OFST 136 2309 /* BAD Address that triggered address-based exception */ 2310 #define MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_BAD_ADDR_OFFS_OFST 140 2311 2312 /* MC_CMD_FC_OUT_FPGA_BUILD msgresponse */ 2313 #define MC_CMD_FC_OUT_FPGA_BUILD_LEN 32 2314 #define MC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_INFO_OFST 0 2315 #define MC_CMD_FC_OUT_FPGA_BUILD_IS_APPLICATION_LBN 31 2316 #define MC_CMD_FC_OUT_FPGA_BUILD_IS_APPLICATION_WIDTH 1 2317 #define MC_CMD_FC_OUT_FPGA_BUILD_IS_LICENSED_LBN 30 2318 #define MC_CMD_FC_OUT_FPGA_BUILD_IS_LICENSED_WIDTH 1 2319 #define MC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_ID_LBN 16 2320 #define MC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_ID_WIDTH 14 2321 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MAJOR_LBN 12 2322 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MAJOR_WIDTH 4 2323 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MINOR_LBN 4 2324 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MINOR_WIDTH 8 2325 #define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_NUM_LBN 0 2326 #define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_NUM_WIDTH 4 2327 /* Build timestamp (seconds since epoch) */ 2328 #define MC_CMD_FC_OUT_FPGA_BUILD_TIMESTAMP_OFST 4 2329 #define MC_CMD_FC_OUT_FPGA_BUILD_PARAMETERS_OFST 8 2330 #define MC_CMD_FC_OUT_FPGA_BUILD_FPGA_TYPE_LBN 0 2331 #define MC_CMD_FC_OUT_FPGA_BUILD_FPGA_TYPE_WIDTH 8 2332 #define MC_CMD_FC_FPGA_TYPE_A7 0xa7 /* enum */ 2333 #define MC_CMD_FC_FPGA_TYPE_A5 0xa5 /* enum */ 2334 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED1_LBN 8 2335 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED1_WIDTH 10 2336 #define MC_CMD_FC_OUT_FPGA_BUILD_PTP_ENABLED_LBN 18 2337 #define MC_CMD_FC_OUT_FPGA_BUILD_PTP_ENABLED_WIDTH 1 2338 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM1_RLDRAM_DEF_LBN 19 2339 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM1_RLDRAM_DEF_WIDTH 1 2340 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM2_RLDRAM_DEF_LBN 20 2341 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM2_RLDRAM_DEF_WIDTH 1 2342 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM3_RLDRAM_DEF_LBN 21 2343 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM3_RLDRAM_DEF_WIDTH 1 2344 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM4_RLDRAM_DEF_LBN 22 2345 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM4_RLDRAM_DEF_WIDTH 1 2346 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T0_DDR3_DEF_LBN 23 2347 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T0_DDR3_DEF_WIDTH 1 2348 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_DDR3_DEF_LBN 24 2349 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_DDR3_DEF_WIDTH 1 2350 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B0_DDR3_DEF_LBN 25 2351 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B0_DDR3_DEF_WIDTH 1 2352 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B1_DDR3_DEF_LBN 26 2353 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B1_DDR3_DEF_WIDTH 1 2354 #define MC_CMD_FC_OUT_FPGA_BUILD_DDR3_ECC_ENABLED_LBN 27 2355 #define MC_CMD_FC_OUT_FPGA_BUILD_DDR3_ECC_ENABLED_WIDTH 1 2356 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_QDR_DEF_LBN 28 2357 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_QDR_DEF_WIDTH 1 2358 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED2_LBN 29 2359 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED2_WIDTH 2 2360 #define MC_CMD_FC_OUT_FPGA_BUILD_CRC_APPEND_LBN 31 2361 #define MC_CMD_FC_OUT_FPGA_BUILD_CRC_APPEND_WIDTH 1 2362 #define MC_CMD_FC_OUT_FPGA_BUILD_IDENTIFIER_OFST 12 2363 #define MC_CMD_FC_OUT_FPGA_BUILD_CHANGESET_LBN 0 2364 #define MC_CMD_FC_OUT_FPGA_BUILD_CHANGESET_WIDTH 16 2365 #define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_FLAG_LBN 16 2366 #define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_FLAG_WIDTH 1 2367 #define MC_CMD_FC_FPGA_BUILD_FLAG_INTERNAL 0x0 /* enum */ 2368 #define MC_CMD_FC_FPGA_BUILD_FLAG_RELEASE 0x1 /* enum */ 2369 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED3_LBN 17 2370 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED3_WIDTH 15 2371 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_HI_OFST 16 2372 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MINOR_LBN 0 2373 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MINOR_WIDTH 16 2374 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MAJOR_LBN 16 2375 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MAJOR_WIDTH 16 2376 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_LO_OFST 20 2377 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_BUILD_LBN 0 2378 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_BUILD_WIDTH 16 2379 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MICRO_LBN 16 2380 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MICRO_WIDTH 16 2381 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_OFST 16 2382 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_LEN 8 2383 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_LO_OFST 16 2384 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_HI_OFST 20 2385 #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_LO_OFST 24 2386 #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HI_OFST 28 2387 #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HIGH_LBN 0 2388 #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HIGH_WIDTH 16 2389 2390 /* MC_CMD_FC_OUT_FPGA_SERVICES msgresponse */ 2391 #define MC_CMD_FC_OUT_FPGA_SERVICES_LEN 32 2392 #define MC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_INFO_OFST 0 2393 #define MC_CMD_FC_OUT_FPGA_SERVICES_IS_APPLICATION_LBN 31 2394 #define MC_CMD_FC_OUT_FPGA_SERVICES_IS_APPLICATION_WIDTH 1 2395 #define MC_CMD_FC_OUT_FPGA_SERVICES_IS_LICENSED_LBN 30 2396 #define MC_CMD_FC_OUT_FPGA_SERVICES_IS_LICENSED_WIDTH 1 2397 #define MC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_ID_LBN 16 2398 #define MC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_ID_WIDTH 14 2399 #define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MAJOR_LBN 12 2400 #define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MAJOR_WIDTH 4 2401 #define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MINOR_LBN 4 2402 #define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MINOR_WIDTH 8 2403 #define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_NUM_LBN 0 2404 #define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_NUM_WIDTH 4 2405 /* Build timestamp (seconds since epoch) */ 2406 #define MC_CMD_FC_OUT_FPGA_SERVICES_TIMESTAMP_OFST 4 2407 #define MC_CMD_FC_OUT_FPGA_SERVICES_PARAMETERS_OFST 8 2408 #define MC_CMD_FC_OUT_FPGA_SERVICES_FC_FLASH_BOOTED_LBN 8 2409 #define MC_CMD_FC_OUT_FPGA_SERVICES_FC_FLASH_BOOTED_WIDTH 1 2410 #define MC_CMD_FC_OUT_FPGA_SERVICES_NIC0_DEF_LBN 27 2411 #define MC_CMD_FC_OUT_FPGA_SERVICES_NIC0_DEF_WIDTH 1 2412 #define MC_CMD_FC_OUT_FPGA_SERVICES_NIC1_DEF_LBN 28 2413 #define MC_CMD_FC_OUT_FPGA_SERVICES_NIC1_DEF_WIDTH 1 2414 #define MC_CMD_FC_OUT_FPGA_SERVICES_SFP0_DEF_LBN 29 2415 #define MC_CMD_FC_OUT_FPGA_SERVICES_SFP0_DEF_WIDTH 1 2416 #define MC_CMD_FC_OUT_FPGA_SERVICES_SFP1_DEF_LBN 30 2417 #define MC_CMD_FC_OUT_FPGA_SERVICES_SFP1_DEF_WIDTH 1 2418 #define MC_CMD_FC_OUT_FPGA_SERVICES_RESERVED_LBN 31 2419 #define MC_CMD_FC_OUT_FPGA_SERVICES_RESERVED_WIDTH 1 2420 #define MC_CMD_FC_OUT_FPGA_SERVICES_IDENTIFIER_OFST 12 2421 #define MC_CMD_FC_OUT_FPGA_SERVICES_CHANGESET_LBN 0 2422 #define MC_CMD_FC_OUT_FPGA_SERVICES_CHANGESET_WIDTH 16 2423 #define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_FLAG_LBN 16 2424 #define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_FLAG_WIDTH 1 2425 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_OFST 16 2426 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_WIDTH_LBN 0 2427 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_WIDTH_WIDTH 16 2428 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_COUNT_LBN 16 2429 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_COUNT_WIDTH 16 2430 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_OFST 20 2431 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_WIDTH_LBN 0 2432 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_WIDTH_WIDTH 16 2433 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_COUNT_LBN 16 2434 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_COUNT_WIDTH 16 2435 #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_LO_OFST 24 2436 #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HI_OFST 28 2437 #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HIGH_LBN 0 2438 #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HIGH_WIDTH 16 2439 2440 /* MC_CMD_FC_OUT_BSP_VERSION msgresponse */ 2441 #define MC_CMD_FC_OUT_BSP_VERSION_LEN 4 2442 /* Qsys system ID */ 2443 #define MC_CMD_FC_OUT_BSP_VERSION_SYSID_OFST 0 2444 #define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MAJOR_LBN 12 2445 #define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MAJOR_WIDTH 4 2446 #define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MINOR_LBN 4 2447 #define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MINOR_WIDTH 8 2448 #define MC_CMD_FC_OUT_BSP_VERSION_BUILD_NUM_LBN 0 2449 #define MC_CMD_FC_OUT_BSP_VERSION_BUILD_NUM_WIDTH 4 2450 2451 /* MC_CMD_FC_OUT_READ_MAP_COUNT msgresponse */ 2452 #define MC_CMD_FC_OUT_READ_MAP_COUNT_LEN 4 2453 /* Number of maps */ 2454 #define MC_CMD_FC_OUT_READ_MAP_COUNT_NUM_MAPS_OFST 0 2455 2456 /* MC_CMD_FC_OUT_READ_MAP_INDEX msgresponse */ 2457 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN 164 2458 /* Index of the map */ 2459 #define MC_CMD_FC_OUT_READ_MAP_INDEX_INDEX_OFST 0 2460 /* Options for the map */ 2461 #define MC_CMD_FC_OUT_READ_MAP_INDEX_OPTIONS_OFST 4 2462 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_8 0x0 /* enum */ 2463 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_16 0x1 /* enum */ 2464 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_32 0x2 /* enum */ 2465 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_64 0x3 /* enum */ 2466 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_MASK 0x3 /* enum */ 2467 #define MC_CMD_FC_OUT_READ_MAP_INDEX_PATH_FC 0x4 /* enum */ 2468 #define MC_CMD_FC_OUT_READ_MAP_INDEX_PATH_MEM 0x8 /* enum */ 2469 #define MC_CMD_FC_OUT_READ_MAP_INDEX_PERM_READ 0x10 /* enum */ 2470 #define MC_CMD_FC_OUT_READ_MAP_INDEX_PERM_WRITE 0x20 /* enum */ 2471 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_FREE 0x0 /* enum */ 2472 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_LICENSED 0x40 /* enum */ 2473 /* Address of start of map */ 2474 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_OFST 8 2475 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_LEN 8 2476 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_LO_OFST 8 2477 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_HI_OFST 12 2478 /* Length of address map */ 2479 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_OFST 16 2480 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_LEN 8 2481 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_LO_OFST 16 2482 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_HI_OFST 20 2483 /* Component information field */ 2484 #define MC_CMD_FC_OUT_READ_MAP_INDEX_COMP_INFO_OFST 24 2485 /* License expiry data for map */ 2486 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_OFST 28 2487 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_LEN 8 2488 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_LO_OFST 28 2489 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_HI_OFST 32 2490 /* Name of the component */ 2491 #define MC_CMD_FC_OUT_READ_MAP_INDEX_NAME_OFST 36 2492 #define MC_CMD_FC_OUT_READ_MAP_INDEX_NAME_LEN 1 2493 #define MC_CMD_FC_OUT_READ_MAP_INDEX_NAME_NUM 128 2494 2495 /* MC_CMD_FC_OUT_READ_MAP msgresponse */ 2496 #define MC_CMD_FC_OUT_READ_MAP_LEN 0 2497 2498 /* MC_CMD_FC_OUT_CAPABILITIES msgresponse */ 2499 #define MC_CMD_FC_OUT_CAPABILITIES_LEN 8 2500 /* Number of internal ports */ 2501 #define MC_CMD_FC_OUT_CAPABILITIES_INTERNAL_OFST 0 2502 /* Number of external ports */ 2503 #define MC_CMD_FC_OUT_CAPABILITIES_EXTERNAL_OFST 4 2504 2505 /* MC_CMD_FC_OUT_GLOBAL_FLAGS msgresponse */ 2506 #define MC_CMD_FC_OUT_GLOBAL_FLAGS_LEN 4 2507 #define MC_CMD_FC_OUT_GLOBAL_FLAGS_FLAGS_OFST 0 2508 2509 /* MC_CMD_FC_OUT_IO_REL msgresponse */ 2510 #define MC_CMD_FC_OUT_IO_REL_LEN 0 2511 2512 /* MC_CMD_FC_OUT_IO_REL_GET_ADDR msgresponse */ 2513 #define MC_CMD_FC_OUT_IO_REL_GET_ADDR_LEN 8 2514 #define MC_CMD_FC_OUT_IO_REL_GET_ADDR_ADDR_HI_OFST 0 2515 #define MC_CMD_FC_OUT_IO_REL_GET_ADDR_ADDR_LO_OFST 4 2516 2517 /* MC_CMD_FC_OUT_IO_REL_READ32 msgresponse */ 2518 #define MC_CMD_FC_OUT_IO_REL_READ32_LENMIN 4 2519 #define MC_CMD_FC_OUT_IO_REL_READ32_LENMAX 252 2520 #define MC_CMD_FC_OUT_IO_REL_READ32_LEN(num) (0+4*(num)) 2521 #define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_OFST 0 2522 #define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_LEN 4 2523 #define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_MINNUM 1 2524 #define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_MAXNUM 63 2525 2526 /* MC_CMD_FC_OUT_IO_REL_WRITE32 msgresponse */ 2527 #define MC_CMD_FC_OUT_IO_REL_WRITE32_LEN 0 2528 2529 /* MC_CMD_FC_OUT_UHLINK_PHY msgresponse */ 2530 #define MC_CMD_FC_OUT_UHLINK_PHY_LEN 48 2531 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_SETTINGS_0_OFST 0 2532 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_VOD_LBN 0 2533 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_VOD_WIDTH 16 2534 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_1STPOSTTAP_LBN 16 2535 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_1STPOSTTAP_WIDTH 16 2536 /* Transceiver Transmit settings */ 2537 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_SETTINGS_1_OFST 4 2538 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_PRETAP_LBN 0 2539 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_PRETAP_WIDTH 16 2540 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_2NDPOSTTAP_LBN 16 2541 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_2NDPOSTTAP_WIDTH 16 2542 /* Transceiver Receive settings */ 2543 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_SETTINGS_OFST 8 2544 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_DC_GAIN_LBN 0 2545 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_DC_GAIN_WIDTH 16 2546 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_EQ_CONTROL_LBN 16 2547 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_EQ_CONTROL_WIDTH 16 2548 /* Rx eye opening */ 2549 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_OFST 12 2550 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_WIDTH_LBN 0 2551 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_WIDTH_WIDTH 16 2552 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_HEIGHT_LBN 16 2553 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_HEIGHT_WIDTH 16 2554 /* PCS status word */ 2555 #define MC_CMD_FC_OUT_UHLINK_PHY_PCS_STATUS_OFST 16 2556 /* Link status word */ 2557 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_WORD_OFST 20 2558 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_LBN 0 2559 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_WIDTH 1 2560 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_CONFIGURED_LBN 1 2561 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_CONFIGURED_WIDTH 1 2562 /* Current SFp parameters applied */ 2563 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_PARAMS_OFST 24 2564 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_PARAMS_LEN 20 2565 /* Link speed is 100, 1000, 10000 */ 2566 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_SPEED_OFST 24 2567 /* Length of copper cable - zero when not relevant */ 2568 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_COPPER_LEN_OFST 28 2569 /* True if a dual speed SFP+ module */ 2570 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_DUAL_SPEED_OFST 32 2571 /* True if an SFP Module is present (other fields valid when true) */ 2572 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_PRESENT_OFST 36 2573 /* The type of the SFP+ Module */ 2574 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_TYPE_OFST 40 2575 /* PHY config flags */ 2576 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_OFST 44 2577 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_DFE_LBN 0 2578 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_DFE_WIDTH 1 2579 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_AEQ_LBN 1 2580 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_AEQ_WIDTH 1 2581 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_RX_TUNING_LBN 2 2582 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_RX_TUNING_WIDTH 1 2583 2584 /* MC_CMD_FC_OUT_UHLINK_MAC msgresponse */ 2585 #define MC_CMD_FC_OUT_UHLINK_MAC_LEN 20 2586 /* MAC configuration applied */ 2587 #define MC_CMD_FC_OUT_UHLINK_MAC_CONFIG_OFST 0 2588 /* MTU size */ 2589 #define MC_CMD_FC_OUT_UHLINK_MAC_MTU_OFST 4 2590 /* IF Mode status */ 2591 #define MC_CMD_FC_OUT_UHLINK_MAC_IF_STATUS_OFST 8 2592 /* MAC address configured */ 2593 #define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_OFST 12 2594 #define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_LEN 8 2595 #define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_LO_OFST 12 2596 #define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_HI_OFST 16 2597 2598 /* MC_CMD_FC_OUT_UHLINK_RX_EYE msgresponse */ 2599 #define MC_CMD_FC_OUT_UHLINK_RX_EYE_LEN ((((0-1+(32*MC_CMD_FC_UHLINK_RX_EYE_PER_BLOCK))+1))>>3) 2600 /* Rx Eye measurements */ 2601 #define MC_CMD_FC_OUT_UHLINK_RX_EYE_RX_EYE_OFST 0 2602 #define MC_CMD_FC_OUT_UHLINK_RX_EYE_RX_EYE_LEN 4 2603 #define MC_CMD_FC_OUT_UHLINK_RX_EYE_RX_EYE_NUM MC_CMD_FC_UHLINK_RX_EYE_PER_BLOCK 2604 2605 /* MC_CMD_FC_OUT_UHLINK_DUMP_RX_EYE_PLOT msgresponse */ 2606 #define MC_CMD_FC_OUT_UHLINK_DUMP_RX_EYE_PLOT_LEN 0 2607 2608 /* MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT msgresponse */ 2609 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_LEN ((((32-1+(64*MC_CMD_FC_UHLINK_RX_EYE_PLOT_ROWS_PER_BLOCK))+1))>>3) 2610 /* Has the eye plot dump completed and data returned is valid? */ 2611 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_VALID_OFST 0 2612 /* Rx Eye binary plot */ 2613 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_OFST 4 2614 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_LEN 8 2615 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_LO_OFST 4 2616 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_HI_OFST 8 2617 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_NUM MC_CMD_FC_UHLINK_RX_EYE_PLOT_ROWS_PER_BLOCK 2618 2619 /* MC_CMD_FC_OUT_UHLINK_RX_TUNE msgresponse */ 2620 #define MC_CMD_FC_OUT_UHLINK_RX_TUNE_LEN 0 2621 2622 /* MC_CMD_FC_OUT_UHLINK_LOOPBACK_SET msgresponse */ 2623 #define MC_CMD_FC_OUT_UHLINK_LOOPBACK_SET_LEN 0 2624 2625 /* MC_CMD_FC_OUT_UHLINK_LOOPBACK_GET msgresponse */ 2626 #define MC_CMD_FC_OUT_UHLINK_LOOPBACK_GET_LEN 4 2627 #define MC_CMD_FC_OUT_UHLINK_LOOPBACK_GET_STATE_OFST 0 2628 2629 /* MC_CMD_FC_OUT_UHLINK msgresponse */ 2630 #define MC_CMD_FC_OUT_UHLINK_LEN 0 2631 2632 /* MC_CMD_FC_OUT_SET_LINK msgresponse */ 2633 #define MC_CMD_FC_OUT_SET_LINK_LEN 0 2634 2635 /* MC_CMD_FC_OUT_LICENSE msgresponse */ 2636 #define MC_CMD_FC_OUT_LICENSE_LEN 12 2637 /* Count of valid keys */ 2638 #define MC_CMD_FC_OUT_LICENSE_VALID_KEYS_OFST 0 2639 /* Count of invalid keys */ 2640 #define MC_CMD_FC_OUT_LICENSE_INVALID_KEYS_OFST 4 2641 /* Count of blacklisted keys */ 2642 #define MC_CMD_FC_OUT_LICENSE_BLACKLISTED_KEYS_OFST 8 2643 2644 /* MC_CMD_FC_OUT_STARTUP msgresponse */ 2645 #define MC_CMD_FC_OUT_STARTUP_LEN 4 2646 /* Capabilities of the FPGA/FC */ 2647 #define MC_CMD_FC_OUT_STARTUP_CAPABILITIES_OFST 0 2648 #define MC_CMD_FC_OUT_STARTUP_CAN_ACCESS_FLASH_LBN 0 2649 #define MC_CMD_FC_OUT_STARTUP_CAN_ACCESS_FLASH_WIDTH 1 2650 2651 /* MC_CMD_FC_OUT_DMA_READ msgresponse */ 2652 #define MC_CMD_FC_OUT_DMA_READ_LENMIN 1 2653 #define MC_CMD_FC_OUT_DMA_READ_LENMAX 252 2654 #define MC_CMD_FC_OUT_DMA_READ_LEN(num) (0+1*(num)) 2655 /* The data read */ 2656 #define MC_CMD_FC_OUT_DMA_READ_DATA_OFST 0 2657 #define MC_CMD_FC_OUT_DMA_READ_DATA_LEN 1 2658 #define MC_CMD_FC_OUT_DMA_READ_DATA_MINNUM 1 2659 #define MC_CMD_FC_OUT_DMA_READ_DATA_MAXNUM 252 2660 2661 /* MC_CMD_FC_OUT_TIMED_READ_SET msgresponse */ 2662 #define MC_CMD_FC_OUT_TIMED_READ_SET_LEN 4 2663 /* Timer handle */ 2664 #define MC_CMD_FC_OUT_TIMED_READ_SET_FC_HANDLE_OFST 0 2665 2666 /* MC_CMD_FC_OUT_TIMED_READ_GET msgresponse */ 2667 #define MC_CMD_FC_OUT_TIMED_READ_GET_LEN 52 2668 /* Host supplied handle (unique) */ 2669 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_HANDLE_OFST 0 2670 /* Address into which to transfer data in host */ 2671 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_OFST 4 2672 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_LEN 8 2673 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_LO_OFST 4 2674 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_HI_OFST 8 2675 /* AOE address from which to transfer data */ 2676 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_OFST 12 2677 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_LEN 8 2678 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_LO_OFST 12 2679 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_HI_OFST 16 2680 /* Length of AOE transfer (total) */ 2681 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_LENGTH_OFST 20 2682 /* Length of host transfer (total) */ 2683 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_LENGTH_OFST 24 2684 /* See FLAGS entry for MC_CMD_FC_IN_TIMED_READ_SET */ 2685 #define MC_CMD_FC_OUT_TIMED_READ_GET_FLAGS_OFST 28 2686 #define MC_CMD_FC_OUT_TIMED_READ_GET_PERIOD_OFST 32 2687 /* When active, start read time */ 2688 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_OFST 36 2689 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_LEN 8 2690 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_LO_OFST 36 2691 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_HI_OFST 40 2692 /* When active, end read time */ 2693 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_OFST 44 2694 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_LEN 8 2695 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_LO_OFST 44 2696 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_HI_OFST 48 2697 2698 /* MC_CMD_FC_OUT_LOG_ADDR_RANGE msgresponse */ 2699 #define MC_CMD_FC_OUT_LOG_ADDR_RANGE_LEN 0 2700 2701 /* MC_CMD_FC_OUT_LOG msgresponse */ 2702 #define MC_CMD_FC_OUT_LOG_LEN 0 2703 2704 /* MC_CMD_FC_OUT_CLOCK_GET_TIME msgresponse */ 2705 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_LEN 24 2706 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_CLOCK_ID_OFST 0 2707 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_OFST 4 2708 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_LEN 8 2709 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_LO_OFST 4 2710 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_HI_OFST 8 2711 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_NANOSECONDS_OFST 12 2712 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_RANGE_OFST 16 2713 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_PRECISION_OFST 20 2714 2715 /* MC_CMD_FC_OUT_CLOCK_SET_TIME msgresponse */ 2716 #define MC_CMD_FC_OUT_CLOCK_SET_TIME_LEN 0 2717 2718 /* MC_CMD_FC_OUT_DDR_SET_SPD msgresponse */ 2719 #define MC_CMD_FC_OUT_DDR_SET_SPD_LEN 0 2720 2721 /* MC_CMD_FC_OUT_DDR_GET_STATUS msgresponse */ 2722 #define MC_CMD_FC_OUT_DDR_GET_STATUS_LEN 4 2723 #define MC_CMD_FC_OUT_DDR_GET_STATUS_FLAGS_OFST 0 2724 #define MC_CMD_FC_OUT_DDR_GET_STATUS_READY_LBN 0 2725 #define MC_CMD_FC_OUT_DDR_GET_STATUS_READY_WIDTH 1 2726 #define MC_CMD_FC_OUT_DDR_GET_STATUS_CALIBRATED_LBN 1 2727 #define MC_CMD_FC_OUT_DDR_GET_STATUS_CALIBRATED_WIDTH 1 2728 2729 /* MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT msgresponse */ 2730 #define MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_LEN 8 2731 #define MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_SECONDS_OFST 0 2732 #define MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_NANOSECONDS_OFST 4 2733 2734 /* MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT msgresponse */ 2735 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LENMIN 8 2736 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LENMAX 248 2737 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LEN(num) (0+8*(num)) 2738 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_SECONDS_OFST 0 2739 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_NANOSECONDS_OFST 4 2740 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_OFST 0 2741 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_LEN 8 2742 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_LO_OFST 0 2743 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_HI_OFST 4 2744 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_MINNUM 0 2745 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_MAXNUM 31 2746 2747 /* MC_CMD_FC_OUT_SPI_READ msgresponse */ 2748 #define MC_CMD_FC_OUT_SPI_READ_LENMIN 4 2749 #define MC_CMD_FC_OUT_SPI_READ_LENMAX 252 2750 #define MC_CMD_FC_OUT_SPI_READ_LEN(num) (0+4*(num)) 2751 #define MC_CMD_FC_OUT_SPI_READ_BUFFER_OFST 0 2752 #define MC_CMD_FC_OUT_SPI_READ_BUFFER_LEN 4 2753 #define MC_CMD_FC_OUT_SPI_READ_BUFFER_MINNUM 1 2754 #define MC_CMD_FC_OUT_SPI_READ_BUFFER_MAXNUM 63 2755 2756 /* MC_CMD_FC_OUT_SPI_WRITE msgresponse */ 2757 #define MC_CMD_FC_OUT_SPI_WRITE_LEN 0 2758 2759 /* MC_CMD_FC_OUT_SPI_ERASE msgresponse */ 2760 #define MC_CMD_FC_OUT_SPI_ERASE_LEN 0 2761 2762 /* MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG msgresponse */ 2763 #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_LEN 8 2764 /* The 32-bit value read from the toggle count register */ 2765 #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_TOGGLE_COUNT_OFST 0 2766 /* The 32-bit value read from the clock enable count register */ 2767 #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_CLKEN_COUNT_OFST 4 2768 2769 /* MC_CMD_FC_OUT_DIAG_POWER_NOISE_WRITE_CONFIG msgresponse */ 2770 #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_WRITE_CONFIG_LEN 0 2771 2772 /* MC_CMD_FC_OUT_DIAG_DDR_SOAK_START msgresponse */ 2773 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_START_LEN 0 2774 2775 /* MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT msgresponse */ 2776 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_LEN 8 2777 /* DDR soak test status word; bits [4:0] are relevant. */ 2778 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_STATUS_OFST 0 2779 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PASSED_LBN 0 2780 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PASSED_WIDTH 1 2781 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_FAILED_LBN 1 2782 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_FAILED_WIDTH 1 2783 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_COMPLETED_LBN 2 2784 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_COMPLETED_WIDTH 1 2785 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_TIMEOUT_LBN 3 2786 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_TIMEOUT_WIDTH 1 2787 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PNF_LBN 4 2788 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PNF_WIDTH 1 2789 /* DDR soak test error count */ 2790 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_ERR_COUNT_OFST 4 2791 2792 /* MC_CMD_FC_OUT_DIAG_DDR_SOAK_STOP msgresponse */ 2793 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_STOP_LEN 0 2794 2795 /* MC_CMD_FC_OUT_DIAG_DDR_SOAK_ERROR msgresponse */ 2796 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_ERROR_LEN 0 2797 2798 /* MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_SET_MODE msgresponse */ 2799 #define MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_SET_MODE_LEN 0 2800 2801 /* MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_RAW_CONFIG msgresponse */ 2802 #define MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_RAW_CONFIG_LEN 0 2803 2804 2805 /***********************************/ 2806 /* MC_CMD_AOE 2807 * AOE operations on MC 2808 */ 2809 #define MC_CMD_AOE 0xa 2810 2811 /* MC_CMD_AOE_IN msgrequest */ 2812 #define MC_CMD_AOE_IN_LEN 4 2813 #define MC_CMD_AOE_IN_OP_HDR_OFST 0 2814 #define MC_CMD_AOE_IN_OP_LBN 0 2815 #define MC_CMD_AOE_IN_OP_WIDTH 8 2816 /* enum: FPGA and CPLD information */ 2817 #define MC_CMD_AOE_OP_INFO 0x1 2818 /* enum: Currents and voltages read from MCP3424s; DEBUG */ 2819 #define MC_CMD_AOE_OP_CURRENTS 0x2 2820 /* enum: Temperatures at locations around the PCB; DEBUG */ 2821 #define MC_CMD_AOE_OP_TEMPERATURES 0x3 2822 /* enum: Set CPLD to idle */ 2823 #define MC_CMD_AOE_OP_CPLD_IDLE 0x4 2824 /* enum: Read from CPLD register */ 2825 #define MC_CMD_AOE_OP_CPLD_READ 0x5 2826 /* enum: Write to CPLD register */ 2827 #define MC_CMD_AOE_OP_CPLD_WRITE 0x6 2828 /* enum: Execute CPLD instruction */ 2829 #define MC_CMD_AOE_OP_CPLD_INSTRUCTION 0x7 2830 /* enum: Reprogram the CPLD on the AOE device */ 2831 #define MC_CMD_AOE_OP_CPLD_REPROGRAM 0x8 2832 /* enum: AOE power control */ 2833 #define MC_CMD_AOE_OP_POWER 0x9 2834 /* enum: AOE image loading */ 2835 #define MC_CMD_AOE_OP_LOAD 0xa 2836 /* enum: Fan monitoring */ 2837 #define MC_CMD_AOE_OP_FAN_CONTROL 0xb 2838 /* enum: Fan failures since last reset */ 2839 #define MC_CMD_AOE_OP_FAN_FAILURES 0xc 2840 /* enum: Get generic AOE MAC statistics */ 2841 #define MC_CMD_AOE_OP_MAC_STATS 0xd 2842 /* enum: Retrieve PHY specific information */ 2843 #define MC_CMD_AOE_OP_GET_PHY_MEDIA_INFO 0xe 2844 /* enum: Write a number of JTAG primitive commands, return will give data */ 2845 #define MC_CMD_AOE_OP_JTAG_WRITE 0xf 2846 /* enum: Control access to the FPGA via the Siena JTAG Chain */ 2847 #define MC_CMD_AOE_OP_FPGA_ACCESS 0x10 2848 /* enum: Set the MTU offset between Siena and AOE MACs */ 2849 #define MC_CMD_AOE_OP_SET_MTU_OFFSET 0x11 2850 /* enum: How link state is handled */ 2851 #define MC_CMD_AOE_OP_LINK_STATE 0x12 2852 /* enum: How Siena MAC statistics are reported (deprecated - use 2853 * MC_CMD_AOE_OP_ASIC_STATS) 2854 */ 2855 #define MC_CMD_AOE_OP_SIENA_STATS 0x13 2856 /* enum: How native ASIC MAC statistics are reported - replaces the deprecated 2857 * command MC_CMD_AOE_OP_SIENA_STATS 2858 */ 2859 #define MC_CMD_AOE_OP_ASIC_STATS 0x13 2860 /* enum: DDR memory information */ 2861 #define MC_CMD_AOE_OP_DDR 0x14 2862 /* enum: FC control */ 2863 #define MC_CMD_AOE_OP_FC 0x15 2864 /* enum: DDR ECC status reads */ 2865 #define MC_CMD_AOE_OP_DDR_ECC_STATUS 0x16 2866 /* enum: Commands for MC-SPI Master emulation */ 2867 #define MC_CMD_AOE_OP_MC_SPI_MASTER 0x17 2868 /* enum: Commands for FC boot control */ 2869 #define MC_CMD_AOE_OP_FC_BOOT 0x18 2870 2871 /* MC_CMD_AOE_OUT msgresponse */ 2872 #define MC_CMD_AOE_OUT_LEN 0 2873 2874 /* MC_CMD_AOE_IN_INFO msgrequest */ 2875 #define MC_CMD_AOE_IN_INFO_LEN 4 2876 #define MC_CMD_AOE_IN_CMD_OFST 0 2877 2878 /* MC_CMD_AOE_IN_CURRENTS msgrequest */ 2879 #define MC_CMD_AOE_IN_CURRENTS_LEN 4 2880 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2881 2882 /* MC_CMD_AOE_IN_TEMPERATURES msgrequest */ 2883 #define MC_CMD_AOE_IN_TEMPERATURES_LEN 4 2884 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2885 2886 /* MC_CMD_AOE_IN_CPLD_IDLE msgrequest */ 2887 #define MC_CMD_AOE_IN_CPLD_IDLE_LEN 4 2888 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2889 2890 /* MC_CMD_AOE_IN_CPLD_READ msgrequest */ 2891 #define MC_CMD_AOE_IN_CPLD_READ_LEN 12 2892 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2893 #define MC_CMD_AOE_IN_CPLD_READ_REGISTER_OFST 4 2894 #define MC_CMD_AOE_IN_CPLD_READ_WIDTH_OFST 8 2895 2896 /* MC_CMD_AOE_IN_CPLD_WRITE msgrequest */ 2897 #define MC_CMD_AOE_IN_CPLD_WRITE_LEN 16 2898 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2899 #define MC_CMD_AOE_IN_CPLD_WRITE_REGISTER_OFST 4 2900 #define MC_CMD_AOE_IN_CPLD_WRITE_WIDTH_OFST 8 2901 #define MC_CMD_AOE_IN_CPLD_WRITE_VALUE_OFST 12 2902 2903 /* MC_CMD_AOE_IN_CPLD_INSTRUCTION msgrequest */ 2904 #define MC_CMD_AOE_IN_CPLD_INSTRUCTION_LEN 8 2905 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2906 #define MC_CMD_AOE_IN_CPLD_INSTRUCTION_INSTRUCTION_OFST 4 2907 2908 /* MC_CMD_AOE_IN_CPLD_REPROGRAM msgrequest */ 2909 #define MC_CMD_AOE_IN_CPLD_REPROGRAM_LEN 8 2910 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2911 #define MC_CMD_AOE_IN_CPLD_REPROGRAM_OP_OFST 4 2912 /* enum: Reprogram CPLD, poll for completion */ 2913 #define MC_CMD_AOE_IN_CPLD_REPROGRAM_REPROGRAM 0x1 2914 /* enum: Reprogram CPLD, send event on completion */ 2915 #define MC_CMD_AOE_IN_CPLD_REPROGRAM_REPROGRAM_EVENT 0x3 2916 /* enum: Get status of reprogramming operation */ 2917 #define MC_CMD_AOE_IN_CPLD_REPROGRAM_STATUS 0x4 2918 2919 /* MC_CMD_AOE_IN_POWER msgrequest */ 2920 #define MC_CMD_AOE_IN_POWER_LEN 8 2921 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2922 /* Turn on or off AOE power */ 2923 #define MC_CMD_AOE_IN_POWER_OP_OFST 4 2924 /* enum: Turn off FPGA power */ 2925 #define MC_CMD_AOE_IN_POWER_OFF 0x0 2926 /* enum: Turn on FPGA power */ 2927 #define MC_CMD_AOE_IN_POWER_ON 0x1 2928 /* enum: Clear peak power measurement */ 2929 #define MC_CMD_AOE_IN_POWER_CLEAR 0x2 2930 /* enum: Show current power in sensors output */ 2931 #define MC_CMD_AOE_IN_POWER_SHOW_CURRENT 0x3 2932 /* enum: Show peak power in sensors output */ 2933 #define MC_CMD_AOE_IN_POWER_SHOW_PEAK 0x4 2934 /* enum: Show current DDR current */ 2935 #define MC_CMD_AOE_IN_POWER_DDR_LAST 0x5 2936 /* enum: Show peak DDR current */ 2937 #define MC_CMD_AOE_IN_POWER_DDR_PEAK 0x6 2938 /* enum: Clear peak DDR current */ 2939 #define MC_CMD_AOE_IN_POWER_DDR_CLEAR 0x7 2940 2941 /* MC_CMD_AOE_IN_LOAD msgrequest */ 2942 #define MC_CMD_AOE_IN_LOAD_LEN 8 2943 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2944 /* Image to be loaded (0 - main or 1 - diagnostic) to load in normal sequence 2945 */ 2946 #define MC_CMD_AOE_IN_LOAD_IMAGE_OFST 4 2947 2948 /* MC_CMD_AOE_IN_FAN_CONTROL msgrequest */ 2949 #define MC_CMD_AOE_IN_FAN_CONTROL_LEN 8 2950 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2951 /* If non zero report measured fan RPM rather than nominal */ 2952 #define MC_CMD_AOE_IN_FAN_CONTROL_REAL_RPM_OFST 4 2953 2954 /* MC_CMD_AOE_IN_FAN_FAILURES msgrequest */ 2955 #define MC_CMD_AOE_IN_FAN_FAILURES_LEN 4 2956 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2957 2958 /* MC_CMD_AOE_IN_MAC_STATS msgrequest */ 2959 #define MC_CMD_AOE_IN_MAC_STATS_LEN 24 2960 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2961 /* AOE port */ 2962 #define MC_CMD_AOE_IN_MAC_STATS_PORT_OFST 4 2963 /* Host memory address for statistics */ 2964 #define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_OFST 8 2965 #define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_LEN 8 2966 #define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_LO_OFST 8 2967 #define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_HI_OFST 12 2968 #define MC_CMD_AOE_IN_MAC_STATS_CMD_OFST 16 2969 #define MC_CMD_AOE_IN_MAC_STATS_DMA_LBN 0 2970 #define MC_CMD_AOE_IN_MAC_STATS_DMA_WIDTH 1 2971 #define MC_CMD_AOE_IN_MAC_STATS_CLEAR_LBN 1 2972 #define MC_CMD_AOE_IN_MAC_STATS_CLEAR_WIDTH 1 2973 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CHANGE_LBN 2 2974 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CHANGE_WIDTH 1 2975 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_ENABLE_LBN 3 2976 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_ENABLE_WIDTH 1 2977 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CLEAR_LBN 4 2978 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CLEAR_WIDTH 1 2979 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_NOEVENT_LBN 5 2980 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_NOEVENT_WIDTH 1 2981 #define MC_CMD_AOE_IN_MAC_STATS_PERIOD_MS_LBN 16 2982 #define MC_CMD_AOE_IN_MAC_STATS_PERIOD_MS_WIDTH 16 2983 /* Length of DMA data (optional) */ 2984 #define MC_CMD_AOE_IN_MAC_STATS_DMA_LEN_OFST 20 2985 2986 /* MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO msgrequest */ 2987 #define MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_LEN 12 2988 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2989 /* AOE port */ 2990 #define MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_PORT_OFST 4 2991 #define MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_PAGE_OFST 8 2992 2993 /* MC_CMD_AOE_IN_JTAG_WRITE msgrequest */ 2994 #define MC_CMD_AOE_IN_JTAG_WRITE_LENMIN 12 2995 #define MC_CMD_AOE_IN_JTAG_WRITE_LENMAX 252 2996 #define MC_CMD_AOE_IN_JTAG_WRITE_LEN(num) (8+4*(num)) 2997 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2998 #define MC_CMD_AOE_IN_JTAG_WRITE_DATALEN_OFST 4 2999 #define MC_CMD_AOE_IN_JTAG_WRITE_DATA_OFST 8 3000 #define MC_CMD_AOE_IN_JTAG_WRITE_DATA_LEN 4 3001 #define MC_CMD_AOE_IN_JTAG_WRITE_DATA_MINNUM 1 3002 #define MC_CMD_AOE_IN_JTAG_WRITE_DATA_MAXNUM 61 3003 3004 /* MC_CMD_AOE_IN_FPGA_ACCESS msgrequest */ 3005 #define MC_CMD_AOE_IN_FPGA_ACCESS_LEN 8 3006 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3007 /* Enable or disable access */ 3008 #define MC_CMD_AOE_IN_FPGA_ACCESS_OP_OFST 4 3009 /* enum: Enable access */ 3010 #define MC_CMD_AOE_IN_FPGA_ACCESS_ENABLE 0x1 3011 /* enum: Disable access */ 3012 #define MC_CMD_AOE_IN_FPGA_ACCESS_DISABLE 0x2 3013 3014 /* MC_CMD_AOE_IN_SET_MTU_OFFSET msgrequest */ 3015 #define MC_CMD_AOE_IN_SET_MTU_OFFSET_LEN 12 3016 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3017 /* AOE port - when not ALL_EXTERNAL or ALL_INTERNAL specifies port number */ 3018 #define MC_CMD_AOE_IN_SET_MTU_OFFSET_PORT_OFST 4 3019 /* enum: Apply to all external ports */ 3020 #define MC_CMD_AOE_IN_SET_MTU_OFFSET_ALL_EXTERNAL 0x8000 3021 /* enum: Apply to all internal ports */ 3022 #define MC_CMD_AOE_IN_SET_MTU_OFFSET_ALL_INTERNAL 0x4000 3023 /* The MTU offset to be applied to the external ports */ 3024 #define MC_CMD_AOE_IN_SET_MTU_OFFSET_OFFSET_OFST 8 3025 3026 /* MC_CMD_AOE_IN_LINK_STATE msgrequest */ 3027 #define MC_CMD_AOE_IN_LINK_STATE_LEN 8 3028 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3029 #define MC_CMD_AOE_IN_LINK_STATE_MODE_OFST 4 3030 #define MC_CMD_AOE_IN_LINK_STATE_CONFIG_MODE_LBN 0 3031 #define MC_CMD_AOE_IN_LINK_STATE_CONFIG_MODE_WIDTH 8 3032 /* enum: AOE and associated external port */ 3033 #define MC_CMD_AOE_IN_LINK_STATE_SIMPLE_SEPARATE 0x0 3034 /* enum: AOE and OR of all external ports */ 3035 #define MC_CMD_AOE_IN_LINK_STATE_SIMPLE_COMBINED 0x1 3036 /* enum: Individual ports */ 3037 #define MC_CMD_AOE_IN_LINK_STATE_DIAGNOSTIC 0x2 3038 /* enum: Configure link state mode on given AOE port */ 3039 #define MC_CMD_AOE_IN_LINK_STATE_CUSTOM 0x3 3040 #define MC_CMD_AOE_IN_LINK_STATE_OPERATION_LBN 8 3041 #define MC_CMD_AOE_IN_LINK_STATE_OPERATION_WIDTH 8 3042 /* enum: No-op */ 3043 #define MC_CMD_AOE_IN_LINK_STATE_OP_NONE 0x0 3044 /* enum: logical OR of all SFP ports link status */ 3045 #define MC_CMD_AOE_IN_LINK_STATE_OP_OR 0x1 3046 /* enum: logical AND of all SFP ports link status */ 3047 #define MC_CMD_AOE_IN_LINK_STATE_OP_AND 0x2 3048 #define MC_CMD_AOE_IN_LINK_STATE_SFP_MASK_LBN 16 3049 #define MC_CMD_AOE_IN_LINK_STATE_SFP_MASK_WIDTH 16 3050 3051 /* MC_CMD_AOE_IN_SIENA_STATS msgrequest */ 3052 #define MC_CMD_AOE_IN_SIENA_STATS_LEN 8 3053 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3054 /* How MAC statistics are reported */ 3055 #define MC_CMD_AOE_IN_SIENA_STATS_MODE_OFST 4 3056 /* enum: Statistics from Siena (default) */ 3057 #define MC_CMD_AOE_IN_SIENA_STATS_STATS_SIENA 0x0 3058 /* enum: Statistics from AOE external ports */ 3059 #define MC_CMD_AOE_IN_SIENA_STATS_STATS_AOE 0x1 3060 3061 /* MC_CMD_AOE_IN_ASIC_STATS msgrequest */ 3062 #define MC_CMD_AOE_IN_ASIC_STATS_LEN 8 3063 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3064 /* How MAC statistics are reported */ 3065 #define MC_CMD_AOE_IN_ASIC_STATS_MODE_OFST 4 3066 /* enum: Statistics from the ASIC (default) */ 3067 #define MC_CMD_AOE_IN_ASIC_STATS_STATS_ASIC 0x0 3068 /* enum: Statistics from AOE external ports */ 3069 #define MC_CMD_AOE_IN_ASIC_STATS_STATS_AOE 0x1 3070 3071 /* MC_CMD_AOE_IN_DDR msgrequest */ 3072 #define MC_CMD_AOE_IN_DDR_LEN 12 3073 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3074 #define MC_CMD_AOE_IN_DDR_BANK_OFST 4 3075 /* Enum values, see field(s): */ 3076 /* MC_CMD_FC/MC_CMD_FC_IN_DDR/MC_CMD_FC_IN_DDR_BANK */ 3077 /* Page index of SPD data */ 3078 #define MC_CMD_AOE_IN_DDR_SPD_PAGE_ID_OFST 8 3079 3080 /* MC_CMD_AOE_IN_FC msgrequest */ 3081 #define MC_CMD_AOE_IN_FC_LEN 4 3082 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3083 3084 /* MC_CMD_AOE_IN_DDR_ECC_STATUS msgrequest */ 3085 #define MC_CMD_AOE_IN_DDR_ECC_STATUS_LEN 8 3086 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3087 #define MC_CMD_AOE_IN_DDR_ECC_STATUS_BANK_OFST 4 3088 /* Enum values, see field(s): */ 3089 /* MC_CMD_FC/MC_CMD_FC_IN_DDR/MC_CMD_FC_IN_DDR_BANK */ 3090 3091 /* MC_CMD_AOE_IN_MC_SPI_MASTER msgrequest */ 3092 #define MC_CMD_AOE_IN_MC_SPI_MASTER_LEN 8 3093 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3094 /* Basic commands for MC SPI Master emulation. */ 3095 #define MC_CMD_AOE_IN_MC_SPI_MASTER_OP_OFST 4 3096 /* enum: MC SPI read */ 3097 #define MC_CMD_AOE_IN_MC_SPI_MASTER_READ 0x0 3098 /* enum: MC SPI write */ 3099 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE 0x1 3100 3101 /* MC_CMD_AOE_IN_MC_SPI_MASTER_READ msgrequest */ 3102 #define MC_CMD_AOE_IN_MC_SPI_MASTER_READ_LEN 12 3103 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3104 #define MC_CMD_AOE_IN_MC_SPI_MASTER_READ_OP_OFST 4 3105 #define MC_CMD_AOE_IN_MC_SPI_MASTER_READ_OFFSET_OFST 8 3106 3107 /* MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE msgrequest */ 3108 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_LEN 16 3109 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3110 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_OP_OFST 4 3111 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_OFFSET_OFST 8 3112 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_DATA_OFST 12 3113 3114 /* MC_CMD_AOE_IN_FC_BOOT msgrequest */ 3115 #define MC_CMD_AOE_IN_FC_BOOT_LEN 8 3116 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 3117 /* FC boot control flags */ 3118 #define MC_CMD_AOE_IN_FC_BOOT_CONTROL_OFST 4 3119 #define MC_CMD_AOE_IN_FC_BOOT_CONTROL_BOOT_ENABLE_LBN 0 3120 #define MC_CMD_AOE_IN_FC_BOOT_CONTROL_BOOT_ENABLE_WIDTH 1 3121 3122 /* MC_CMD_AOE_OUT_INFO msgresponse */ 3123 #define MC_CMD_AOE_OUT_INFO_LEN 44 3124 /* JTAG IDCODE of CPLD */ 3125 #define MC_CMD_AOE_OUT_INFO_CPLD_IDCODE_OFST 0 3126 /* Version of CPLD */ 3127 #define MC_CMD_AOE_OUT_INFO_CPLD_VERSION_OFST 4 3128 /* JTAG IDCODE of FPGA */ 3129 #define MC_CMD_AOE_OUT_INFO_FPGA_IDCODE_OFST 8 3130 /* JTAG USERCODE of FPGA */ 3131 #define MC_CMD_AOE_OUT_INFO_FPGA_VERSION_OFST 12 3132 /* FPGA type - read from CPLD straps */ 3133 #define MC_CMD_AOE_OUT_INFO_FPGA_TYPE_OFST 16 3134 /* FPGA state (debug) */ 3135 #define MC_CMD_AOE_OUT_INFO_FPGA_STATE_OFST 20 3136 /* FPGA image - partition from which loaded */ 3137 #define MC_CMD_AOE_OUT_INFO_FPGA_IMAGE_OFST 24 3138 /* FC state */ 3139 #define MC_CMD_AOE_OUT_INFO_FC_STATE_OFST 28 3140 /* enum: Set if watchdog working */ 3141 #define MC_CMD_AOE_OUT_INFO_WATCHDOG 0x1 3142 /* enum: Set if MC-FC communications working */ 3143 #define MC_CMD_AOE_OUT_INFO_COMMS 0x2 3144 /* Random pieces of information */ 3145 #define MC_CMD_AOE_OUT_INFO_FLAGS_OFST 32 3146 /* enum: Power to FPGA supplied by PEG connector, not PCIe bus */ 3147 #define MC_CMD_AOE_OUT_INFO_PEG_POWER 0x1 3148 /* enum: CPLD apparently good */ 3149 #define MC_CMD_AOE_OUT_INFO_CPLD_GOOD 0x2 3150 /* enum: FPGA working normally */ 3151 #define MC_CMD_AOE_OUT_INFO_FPGA_GOOD 0x4 3152 /* enum: FPGA is powered */ 3153 #define MC_CMD_AOE_OUT_INFO_FPGA_POWER 0x8 3154 /* enum: Board has incompatible SODIMMs fitted */ 3155 #define MC_CMD_AOE_OUT_INFO_BAD_SODIMM 0x10 3156 /* enum: Board has ByteBlaster connected */ 3157 #define MC_CMD_AOE_OUT_INFO_HAS_BYTEBLASTER 0x20 3158 /* Revision of Modena board */ 3159 #define MC_CMD_AOE_OUT_INFO_BOARD_REVISION_OFST 36 3160 #define MC_CMD_AOE_OUT_INFO_UNKNOWN 0x0 /* enum */ 3161 #define MC_CMD_AOE_OUT_INFO_R1_0 0x10 /* enum */ 3162 #define MC_CMD_AOE_OUT_INFO_R1_1 0x11 /* enum */ 3163 #define MC_CMD_AOE_OUT_INFO_R1_2 0x12 /* enum */ 3164 /* Result of FC booting - not valid while a ByteBlaster is connected. */ 3165 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_RESULT_OFST 40 3166 /* enum: No error */ 3167 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_NO_ERROR 0x0 3168 /* enum: Bad address set in CPLD */ 3169 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_ADDRESS 0x1 3170 /* enum: Bad header */ 3171 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_MAGIC 0x2 3172 /* enum: Bad text section details */ 3173 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_TEXT 0x3 3174 /* enum: Bad checksum */ 3175 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_CHECKSUM 0x4 3176 /* enum: Bad BSP */ 3177 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_BSP 0x5 3178 /* enum: FC application loaded and execution attempted */ 3179 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_APP_EXECUTE 0x80 3180 /* enum: FC application Started */ 3181 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_APP_STARTED 0x81 3182 /* enum: No bootrom in FPGA */ 3183 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_NO_BOOTROM 0xff 3184 3185 /* MC_CMD_AOE_OUT_CURRENTS msgresponse */ 3186 #define MC_CMD_AOE_OUT_CURRENTS_LEN 68 3187 /* Set of currents and voltages (mA or mV as appropriate) */ 3188 #define MC_CMD_AOE_OUT_CURRENTS_VALUES_OFST 0 3189 #define MC_CMD_AOE_OUT_CURRENTS_VALUES_LEN 4 3190 #define MC_CMD_AOE_OUT_CURRENTS_VALUES_NUM 17 3191 #define MC_CMD_AOE_OUT_CURRENTS_I_2V5 0x0 /* enum */ 3192 #define MC_CMD_AOE_OUT_CURRENTS_I_1V8 0x1 /* enum */ 3193 #define MC_CMD_AOE_OUT_CURRENTS_I_GXB 0x2 /* enum */ 3194 #define MC_CMD_AOE_OUT_CURRENTS_I_PGM 0x3 /* enum */ 3195 #define MC_CMD_AOE_OUT_CURRENTS_I_XCVR 0x4 /* enum */ 3196 #define MC_CMD_AOE_OUT_CURRENTS_I_1V5 0x5 /* enum */ 3197 #define MC_CMD_AOE_OUT_CURRENTS_V_3V3 0x6 /* enum */ 3198 #define MC_CMD_AOE_OUT_CURRENTS_V_1V5 0x7 /* enum */ 3199 #define MC_CMD_AOE_OUT_CURRENTS_I_IN 0x8 /* enum */ 3200 #define MC_CMD_AOE_OUT_CURRENTS_I_OUT 0x9 /* enum */ 3201 #define MC_CMD_AOE_OUT_CURRENTS_V_IN 0xa /* enum */ 3202 #define MC_CMD_AOE_OUT_CURRENTS_I_OUT_DDR1 0xb /* enum */ 3203 #define MC_CMD_AOE_OUT_CURRENTS_V_OUT_DDR1 0xc /* enum */ 3204 #define MC_CMD_AOE_OUT_CURRENTS_I_OUT_DDR2 0xd /* enum */ 3205 #define MC_CMD_AOE_OUT_CURRENTS_V_OUT_DDR2 0xe /* enum */ 3206 #define MC_CMD_AOE_OUT_CURRENTS_I_OUT_DDR3 0xf /* enum */ 3207 #define MC_CMD_AOE_OUT_CURRENTS_V_OUT_DDR3 0x10 /* enum */ 3208 3209 /* MC_CMD_AOE_OUT_TEMPERATURES msgresponse */ 3210 #define MC_CMD_AOE_OUT_TEMPERATURES_LEN 40 3211 /* Set of temperatures */ 3212 #define MC_CMD_AOE_OUT_TEMPERATURES_VALUES_OFST 0 3213 #define MC_CMD_AOE_OUT_TEMPERATURES_VALUES_LEN 4 3214 #define MC_CMD_AOE_OUT_TEMPERATURES_VALUES_NUM 10 3215 /* enum: The first set of enum values are for Modena code. */ 3216 #define MC_CMD_AOE_OUT_TEMPERATURES_MAIN_0 0x0 3217 #define MC_CMD_AOE_OUT_TEMPERATURES_MAIN_1 0x1 /* enum */ 3218 #define MC_CMD_AOE_OUT_TEMPERATURES_IND_0 0x2 /* enum */ 3219 #define MC_CMD_AOE_OUT_TEMPERATURES_IND_1 0x3 /* enum */ 3220 #define MC_CMD_AOE_OUT_TEMPERATURES_VCCIO1 0x4 /* enum */ 3221 #define MC_CMD_AOE_OUT_TEMPERATURES_VCCIO2 0x5 /* enum */ 3222 #define MC_CMD_AOE_OUT_TEMPERATURES_VCCIO3 0x6 /* enum */ 3223 #define MC_CMD_AOE_OUT_TEMPERATURES_PSU 0x7 /* enum */ 3224 #define MC_CMD_AOE_OUT_TEMPERATURES_FPGA 0x8 /* enum */ 3225 #define MC_CMD_AOE_OUT_TEMPERATURES_SIENA 0x9 /* enum */ 3226 /* enum: The second set of enum values are for Sorrento code. */ 3227 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_MAIN_0 0x0 3228 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_MAIN_1 0x1 /* enum */ 3229 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_IND_0 0x2 /* enum */ 3230 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_IND_1 0x3 /* enum */ 3231 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_SODIMM_0 0x4 /* enum */ 3232 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_SODIMM_1 0x5 /* enum */ 3233 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_FPGA 0x6 /* enum */ 3234 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_PHY0 0x7 /* enum */ 3235 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_PHY1 0x8 /* enum */ 3236 3237 /* MC_CMD_AOE_OUT_CPLD_READ msgresponse */ 3238 #define MC_CMD_AOE_OUT_CPLD_READ_LEN 4 3239 /* The value read from the CPLD */ 3240 #define MC_CMD_AOE_OUT_CPLD_READ_VALUE_OFST 0 3241 3242 /* MC_CMD_AOE_OUT_FAN_FAILURES msgresponse */ 3243 #define MC_CMD_AOE_OUT_FAN_FAILURES_LENMIN 4 3244 #define MC_CMD_AOE_OUT_FAN_FAILURES_LENMAX 252 3245 #define MC_CMD_AOE_OUT_FAN_FAILURES_LEN(num) (0+4*(num)) 3246 /* Failure counts for each fan */ 3247 #define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_OFST 0 3248 #define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_LEN 4 3249 #define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_MINNUM 1 3250 #define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_MAXNUM 63 3251 3252 /* MC_CMD_AOE_OUT_CPLD_REPROGRAM msgresponse */ 3253 #define MC_CMD_AOE_OUT_CPLD_REPROGRAM_LEN 4 3254 /* Results of status command (only) */ 3255 #define MC_CMD_AOE_OUT_CPLD_REPROGRAM_STATUS_OFST 0 3256 3257 /* MC_CMD_AOE_OUT_POWER_OFF msgresponse */ 3258 #define MC_CMD_AOE_OUT_POWER_OFF_LEN 0 3259 3260 /* MC_CMD_AOE_OUT_POWER_ON msgresponse */ 3261 #define MC_CMD_AOE_OUT_POWER_ON_LEN 0 3262 3263 /* MC_CMD_AOE_OUT_LOAD msgresponse */ 3264 #define MC_CMD_AOE_OUT_LOAD_LEN 0 3265 3266 /* MC_CMD_AOE_OUT_MAC_STATS_DMA msgresponse */ 3267 #define MC_CMD_AOE_OUT_MAC_STATS_DMA_LEN 0 3268 3269 /* MC_CMD_AOE_OUT_MAC_STATS_NO_DMA msgresponse: See MC_CMD_MAC_STATS_OUT_NO_DMA 3270 * for details 3271 */ 3272 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_LEN (((MC_CMD_MAC_NSTATS*64))>>3) 3273 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_OFST 0 3274 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_LEN 8 3275 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_LO_OFST 0 3276 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_HI_OFST 4 3277 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS 3278 3279 /* MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO msgresponse */ 3280 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LENMIN 5 3281 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LENMAX 252 3282 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LEN(num) (4+1*(num)) 3283 /* in bytes */ 3284 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATALEN_OFST 0 3285 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_OFST 4 3286 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_LEN 1 3287 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_MINNUM 1 3288 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_MAXNUM 248 3289 3290 /* MC_CMD_AOE_OUT_JTAG_WRITE msgresponse */ 3291 #define MC_CMD_AOE_OUT_JTAG_WRITE_LENMIN 12 3292 #define MC_CMD_AOE_OUT_JTAG_WRITE_LENMAX 252 3293 #define MC_CMD_AOE_OUT_JTAG_WRITE_LEN(num) (8+4*(num)) 3294 /* Used to align the in and out data blocks so the MC can re-use the cmd */ 3295 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATALEN_OFST 0 3296 /* out bytes */ 3297 #define MC_CMD_AOE_OUT_JTAG_WRITE_PAD_OFST 4 3298 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_OFST 8 3299 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_LEN 4 3300 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_MINNUM 1 3301 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_MAXNUM 61 3302 3303 /* MC_CMD_AOE_OUT_FPGA_ACCESS msgresponse */ 3304 #define MC_CMD_AOE_OUT_FPGA_ACCESS_LEN 0 3305 3306 /* MC_CMD_AOE_OUT_DDR msgresponse */ 3307 #define MC_CMD_AOE_OUT_DDR_LENMIN 17 3308 #define MC_CMD_AOE_OUT_DDR_LENMAX 252 3309 #define MC_CMD_AOE_OUT_DDR_LEN(num) (16+1*(num)) 3310 /* Information on the module. */ 3311 #define MC_CMD_AOE_OUT_DDR_FLAGS_OFST 0 3312 #define MC_CMD_AOE_OUT_DDR_PRESENT_LBN 0 3313 #define MC_CMD_AOE_OUT_DDR_PRESENT_WIDTH 1 3314 #define MC_CMD_AOE_OUT_DDR_POWERED_LBN 1 3315 #define MC_CMD_AOE_OUT_DDR_POWERED_WIDTH 1 3316 #define MC_CMD_AOE_OUT_DDR_OPERATIONAL_LBN 2 3317 #define MC_CMD_AOE_OUT_DDR_OPERATIONAL_WIDTH 1 3318 #define MC_CMD_AOE_OUT_DDR_NOT_REACHABLE_LBN 3 3319 #define MC_CMD_AOE_OUT_DDR_NOT_REACHABLE_WIDTH 1 3320 /* Memory size, in MB. */ 3321 #define MC_CMD_AOE_OUT_DDR_CAPACITY_OFST 4 3322 /* The memory type, as reported from SPD information */ 3323 #define MC_CMD_AOE_OUT_DDR_TYPE_OFST 8 3324 /* Nominal voltage of the module (as applied) */ 3325 #define MC_CMD_AOE_OUT_DDR_VOLTAGE_OFST 12 3326 /* SPD data read from the module */ 3327 #define MC_CMD_AOE_OUT_DDR_SPD_OFST 16 3328 #define MC_CMD_AOE_OUT_DDR_SPD_LEN 1 3329 #define MC_CMD_AOE_OUT_DDR_SPD_MINNUM 1 3330 #define MC_CMD_AOE_OUT_DDR_SPD_MAXNUM 236 3331 3332 /* MC_CMD_AOE_OUT_SET_MTU_OFFSET msgresponse */ 3333 #define MC_CMD_AOE_OUT_SET_MTU_OFFSET_LEN 0 3334 3335 /* MC_CMD_AOE_OUT_LINK_STATE msgresponse */ 3336 #define MC_CMD_AOE_OUT_LINK_STATE_LEN 0 3337 3338 /* MC_CMD_AOE_OUT_SIENA_STATS msgresponse */ 3339 #define MC_CMD_AOE_OUT_SIENA_STATS_LEN 0 3340 3341 /* MC_CMD_AOE_OUT_ASIC_STATS msgresponse */ 3342 #define MC_CMD_AOE_OUT_ASIC_STATS_LEN 0 3343 3344 /* MC_CMD_AOE_OUT_FC msgresponse */ 3345 #define MC_CMD_AOE_OUT_FC_LEN 0 3346 3347 /* MC_CMD_AOE_OUT_DDR_ECC_STATUS msgresponse */ 3348 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_LEN 8 3349 /* Flags describing status info on the module. */ 3350 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_FLAGS_OFST 0 3351 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_VALID_LBN 0 3352 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_VALID_WIDTH 1 3353 /* DDR ECC status on the module. */ 3354 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_STATUS_OFST 4 3355 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_LBN 0 3356 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_WIDTH 1 3357 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_LBN 1 3358 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_WIDTH 1 3359 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_LBN 2 3360 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_WIDTH 1 3361 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_COUNT_LBN 8 3362 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_COUNT_WIDTH 8 3363 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_COUNT_LBN 16 3364 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_COUNT_WIDTH 8 3365 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_COUNT_LBN 24 3366 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_COUNT_WIDTH 8 3367 3368 /* MC_CMD_AOE_OUT_MC_SPI_MASTER_READ msgresponse */ 3369 #define MC_CMD_AOE_OUT_MC_SPI_MASTER_READ_LEN 4 3370 #define MC_CMD_AOE_OUT_MC_SPI_MASTER_READ_DATA_OFST 0 3371 3372 /* MC_CMD_AOE_OUT_MC_SPI_MASTER_WRITE msgresponse */ 3373 #define MC_CMD_AOE_OUT_MC_SPI_MASTER_WRITE_LEN 0 3374 3375 /* MC_CMD_AOE_OUT_MC_SPI_MASTER msgresponse */ 3376 #define MC_CMD_AOE_OUT_MC_SPI_MASTER_LEN 0 3377 3378 /* MC_CMD_AOE_OUT_FC_BOOT msgresponse */ 3379 #define MC_CMD_AOE_OUT_FC_BOOT_LEN 0 3380 3381 3382 /***********************************/ 3383 /* MC_CMD_PTP 3384 * Perform PTP operation 3385 */ 3386 #define MC_CMD_PTP 0xb 3387 #undef MC_CMD_0xb_PRIVILEGE_CTG 3388 3389 #define MC_CMD_0xb_PRIVILEGE_CTG SRIOV_CTG_GENERAL 3390 3391 /* MC_CMD_PTP_IN msgrequest */ 3392 #define MC_CMD_PTP_IN_LEN 1 3393 /* PTP operation code */ 3394 #define MC_CMD_PTP_IN_OP_OFST 0 3395 #define MC_CMD_PTP_IN_OP_LEN 1 3396 /* enum: Enable PTP packet timestamping operation. */ 3397 #define MC_CMD_PTP_OP_ENABLE 0x1 3398 /* enum: Disable PTP packet timestamping operation. */ 3399 #define MC_CMD_PTP_OP_DISABLE 0x2 3400 /* enum: Send a PTP packet. */ 3401 #define MC_CMD_PTP_OP_TRANSMIT 0x3 3402 /* enum: Read the current NIC time. */ 3403 #define MC_CMD_PTP_OP_READ_NIC_TIME 0x4 3404 /* enum: Get the current PTP status. */ 3405 #define MC_CMD_PTP_OP_STATUS 0x5 3406 /* enum: Adjust the PTP NIC's time. */ 3407 #define MC_CMD_PTP_OP_ADJUST 0x6 3408 /* enum: Synchronize host and NIC time. */ 3409 #define MC_CMD_PTP_OP_SYNCHRONIZE 0x7 3410 /* enum: Basic manufacturing tests. */ 3411 #define MC_CMD_PTP_OP_MANFTEST_BASIC 0x8 3412 /* enum: Packet based manufacturing tests. */ 3413 #define MC_CMD_PTP_OP_MANFTEST_PACKET 0x9 3414 /* enum: Reset some of the PTP related statistics */ 3415 #define MC_CMD_PTP_OP_RESET_STATS 0xa 3416 /* enum: Debug operations to MC. */ 3417 #define MC_CMD_PTP_OP_DEBUG 0xb 3418 /* enum: Read an FPGA register */ 3419 #define MC_CMD_PTP_OP_FPGAREAD 0xc 3420 /* enum: Write an FPGA register */ 3421 #define MC_CMD_PTP_OP_FPGAWRITE 0xd 3422 /* enum: Apply an offset to the NIC clock */ 3423 #define MC_CMD_PTP_OP_CLOCK_OFFSET_ADJUST 0xe 3424 /* enum: Change Apply an offset to the NIC clock */ 3425 #define MC_CMD_PTP_OP_CLOCK_FREQ_ADJUST 0xf 3426 /* enum: Set the MC packet filter VLAN tags for received PTP packets */ 3427 #define MC_CMD_PTP_OP_RX_SET_VLAN_FILTER 0x10 3428 /* enum: Set the MC packet filter UUID for received PTP packets */ 3429 #define MC_CMD_PTP_OP_RX_SET_UUID_FILTER 0x11 3430 /* enum: Set the MC packet filter Domain for received PTP packets */ 3431 #define MC_CMD_PTP_OP_RX_SET_DOMAIN_FILTER 0x12 3432 /* enum: Set the clock source */ 3433 #define MC_CMD_PTP_OP_SET_CLK_SRC 0x13 3434 /* enum: Reset value of Timer Reg. */ 3435 #define MC_CMD_PTP_OP_RST_CLK 0x14 3436 /* enum: Enable the forwarding of PPS events to the host */ 3437 #define MC_CMD_PTP_OP_PPS_ENABLE 0x15 3438 /* enum: Get the time format used by this NIC for PTP operations */ 3439 #define MC_CMD_PTP_OP_GET_TIME_FORMAT 0x16 3440 /* enum: Get the clock attributes. NOTE- extended version of 3441 * MC_CMD_PTP_OP_GET_TIME_FORMAT 3442 */ 3443 #define MC_CMD_PTP_OP_GET_ATTRIBUTES 0x16 3444 /* enum: Get corrections that should be applied to the various different 3445 * timestamps 3446 */ 3447 #define MC_CMD_PTP_OP_GET_TIMESTAMP_CORRECTIONS 0x17 3448 /* enum: Subscribe to receive periodic time events indicating the current NIC 3449 * time 3450 */ 3451 #define MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE 0x18 3452 /* enum: Unsubscribe to stop receiving time events */ 3453 #define MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE 0x19 3454 /* enum: PPS based manfacturing tests. Requires PPS output to be looped to PPS 3455 * input on the same NIC. 3456 */ 3457 #define MC_CMD_PTP_OP_MANFTEST_PPS 0x1a 3458 /* enum: Set the PTP sync status. Status is used by firmware to report to event 3459 * subscribers. 3460 */ 3461 #define MC_CMD_PTP_OP_SET_SYNC_STATUS 0x1b 3462 /* enum: Above this for future use. */ 3463 #define MC_CMD_PTP_OP_MAX 0x1c 3464 3465 /* MC_CMD_PTP_IN_ENABLE msgrequest */ 3466 #define MC_CMD_PTP_IN_ENABLE_LEN 16 3467 #define MC_CMD_PTP_IN_CMD_OFST 0 3468 #define MC_CMD_PTP_IN_PERIPH_ID_OFST 4 3469 /* Event queue for PTP events */ 3470 #define MC_CMD_PTP_IN_ENABLE_QUEUE_OFST 8 3471 /* PTP timestamping mode */ 3472 #define MC_CMD_PTP_IN_ENABLE_MODE_OFST 12 3473 /* enum: PTP, version 1 */ 3474 #define MC_CMD_PTP_MODE_V1 0x0 3475 /* enum: PTP, version 1, with VLAN headers - deprecated */ 3476 #define MC_CMD_PTP_MODE_V1_VLAN 0x1 3477 /* enum: PTP, version 2 */ 3478 #define MC_CMD_PTP_MODE_V2 0x2 3479 /* enum: PTP, version 2, with VLAN headers - deprecated */ 3480 #define MC_CMD_PTP_MODE_V2_VLAN 0x3 3481 /* enum: PTP, version 2, with improved UUID filtering */ 3482 #define MC_CMD_PTP_MODE_V2_ENHANCED 0x4 3483 /* enum: FCoE (seconds and microseconds) */ 3484 #define MC_CMD_PTP_MODE_FCOE 0x5 3485 3486 /* MC_CMD_PTP_IN_DISABLE msgrequest */ 3487 #define MC_CMD_PTP_IN_DISABLE_LEN 8 3488 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3489 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3490 3491 /* MC_CMD_PTP_IN_TRANSMIT msgrequest */ 3492 #define MC_CMD_PTP_IN_TRANSMIT_LENMIN 13 3493 #define MC_CMD_PTP_IN_TRANSMIT_LENMAX 252 3494 #define MC_CMD_PTP_IN_TRANSMIT_LEN(num) (12+1*(num)) 3495 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3496 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3497 /* Transmit packet length */ 3498 #define MC_CMD_PTP_IN_TRANSMIT_LENGTH_OFST 8 3499 /* Transmit packet data */ 3500 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_OFST 12 3501 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_LEN 1 3502 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_MINNUM 1 3503 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_MAXNUM 240 3504 3505 /* MC_CMD_PTP_IN_READ_NIC_TIME msgrequest */ 3506 #define MC_CMD_PTP_IN_READ_NIC_TIME_LEN 8 3507 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3508 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3509 3510 /* MC_CMD_PTP_IN_STATUS msgrequest */ 3511 #define MC_CMD_PTP_IN_STATUS_LEN 8 3512 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3513 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3514 3515 /* MC_CMD_PTP_IN_ADJUST msgrequest */ 3516 #define MC_CMD_PTP_IN_ADJUST_LEN 24 3517 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3518 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3519 /* Frequency adjustment 40 bit fixed point ns */ 3520 #define MC_CMD_PTP_IN_ADJUST_FREQ_OFST 8 3521 #define MC_CMD_PTP_IN_ADJUST_FREQ_LEN 8 3522 #define MC_CMD_PTP_IN_ADJUST_FREQ_LO_OFST 8 3523 #define MC_CMD_PTP_IN_ADJUST_FREQ_HI_OFST 12 3524 /* enum: Number of fractional bits in frequency adjustment */ 3525 #define MC_CMD_PTP_IN_ADJUST_BITS 0x28 3526 /* Time adjustment in seconds */ 3527 #define MC_CMD_PTP_IN_ADJUST_SECONDS_OFST 16 3528 /* Time adjustment major value */ 3529 #define MC_CMD_PTP_IN_ADJUST_MAJOR_OFST 16 3530 /* Time adjustment in nanoseconds */ 3531 #define MC_CMD_PTP_IN_ADJUST_NANOSECONDS_OFST 20 3532 /* Time adjustment minor value */ 3533 #define MC_CMD_PTP_IN_ADJUST_MINOR_OFST 20 3534 3535 /* MC_CMD_PTP_IN_SYNCHRONIZE msgrequest */ 3536 #define MC_CMD_PTP_IN_SYNCHRONIZE_LEN 20 3537 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3538 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3539 /* Number of time readings to capture */ 3540 #define MC_CMD_PTP_IN_SYNCHRONIZE_NUMTIMESETS_OFST 8 3541 /* Host address in which to write "synchronization started" indication (64 3542 * bits) 3543 */ 3544 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_OFST 12 3545 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LEN 8 3546 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LO_OFST 12 3547 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_HI_OFST 16 3548 3549 /* MC_CMD_PTP_IN_MANFTEST_BASIC msgrequest */ 3550 #define MC_CMD_PTP_IN_MANFTEST_BASIC_LEN 8 3551 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3552 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3553 3554 /* MC_CMD_PTP_IN_MANFTEST_PACKET msgrequest */ 3555 #define MC_CMD_PTP_IN_MANFTEST_PACKET_LEN 12 3556 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3557 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3558 /* Enable or disable packet testing */ 3559 #define MC_CMD_PTP_IN_MANFTEST_PACKET_TEST_ENABLE_OFST 8 3560 3561 /* MC_CMD_PTP_IN_RESET_STATS msgrequest */ 3562 #define MC_CMD_PTP_IN_RESET_STATS_LEN 8 3563 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3564 /* Reset PTP statistics */ 3565 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3566 3567 /* MC_CMD_PTP_IN_DEBUG msgrequest */ 3568 #define MC_CMD_PTP_IN_DEBUG_LEN 12 3569 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3570 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3571 /* Debug operations */ 3572 #define MC_CMD_PTP_IN_DEBUG_DEBUG_PARAM_OFST 8 3573 3574 /* MC_CMD_PTP_IN_FPGAREAD msgrequest */ 3575 #define MC_CMD_PTP_IN_FPGAREAD_LEN 16 3576 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3577 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3578 #define MC_CMD_PTP_IN_FPGAREAD_ADDR_OFST 8 3579 #define MC_CMD_PTP_IN_FPGAREAD_NUMBYTES_OFST 12 3580 3581 /* MC_CMD_PTP_IN_FPGAWRITE msgrequest */ 3582 #define MC_CMD_PTP_IN_FPGAWRITE_LENMIN 13 3583 #define MC_CMD_PTP_IN_FPGAWRITE_LENMAX 252 3584 #define MC_CMD_PTP_IN_FPGAWRITE_LEN(num) (12+1*(num)) 3585 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3586 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3587 #define MC_CMD_PTP_IN_FPGAWRITE_ADDR_OFST 8 3588 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_OFST 12 3589 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_LEN 1 3590 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MINNUM 1 3591 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MAXNUM 240 3592 3593 /* MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST msgrequest */ 3594 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_LEN 16 3595 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3596 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3597 /* Time adjustment in seconds */ 3598 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_SECONDS_OFST 8 3599 /* Time adjustment major value */ 3600 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MAJOR_OFST 8 3601 /* Time adjustment in nanoseconds */ 3602 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_NANOSECONDS_OFST 12 3603 /* Time adjustment minor value */ 3604 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MINOR_OFST 12 3605 3606 /* MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST msgrequest */ 3607 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_LEN 16 3608 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3609 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3610 /* Frequency adjustment 40 bit fixed point ns */ 3611 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_OFST 8 3612 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LEN 8 3613 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LO_OFST 8 3614 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_HI_OFST 12 3615 /* enum: Number of fractional bits in frequency adjustment */ 3616 /* MC_CMD_PTP_IN_ADJUST_BITS 0x28 */ 3617 3618 /* MC_CMD_PTP_IN_RX_SET_VLAN_FILTER msgrequest */ 3619 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_LEN 24 3620 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3621 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3622 /* Number of VLAN tags, 0 if not VLAN */ 3623 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_NUM_VLAN_TAGS_OFST 8 3624 /* Set of VLAN tags to filter against */ 3625 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_OFST 12 3626 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_LEN 4 3627 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_NUM 3 3628 3629 /* MC_CMD_PTP_IN_RX_SET_UUID_FILTER msgrequest */ 3630 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_LEN 20 3631 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3632 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3633 /* 1 to enable UUID filtering, 0 to disable */ 3634 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_ENABLE_OFST 8 3635 /* UUID to filter against */ 3636 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_OFST 12 3637 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LEN 8 3638 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LO_OFST 12 3639 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_HI_OFST 16 3640 3641 /* MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER msgrequest */ 3642 #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_LEN 16 3643 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3644 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3645 /* 1 to enable Domain filtering, 0 to disable */ 3646 #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_ENABLE_OFST 8 3647 /* Domain number to filter against */ 3648 #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_DOMAIN_OFST 12 3649 3650 /* MC_CMD_PTP_IN_SET_CLK_SRC msgrequest */ 3651 #define MC_CMD_PTP_IN_SET_CLK_SRC_LEN 12 3652 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3653 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3654 /* Set the clock source. */ 3655 #define MC_CMD_PTP_IN_SET_CLK_SRC_CLK_OFST 8 3656 /* enum: Internal. */ 3657 #define MC_CMD_PTP_CLK_SRC_INTERNAL 0x0 3658 /* enum: External. */ 3659 #define MC_CMD_PTP_CLK_SRC_EXTERNAL 0x1 3660 3661 /* MC_CMD_PTP_IN_RST_CLK msgrequest */ 3662 #define MC_CMD_PTP_IN_RST_CLK_LEN 8 3663 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3664 /* Reset value of Timer Reg. */ 3665 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3666 3667 /* MC_CMD_PTP_IN_PPS_ENABLE msgrequest */ 3668 #define MC_CMD_PTP_IN_PPS_ENABLE_LEN 12 3669 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3670 /* Enable or disable */ 3671 #define MC_CMD_PTP_IN_PPS_ENABLE_OP_OFST 4 3672 /* enum: Enable */ 3673 #define MC_CMD_PTP_ENABLE_PPS 0x0 3674 /* enum: Disable */ 3675 #define MC_CMD_PTP_DISABLE_PPS 0x1 3676 /* Queue id to send events back */ 3677 #define MC_CMD_PTP_IN_PPS_ENABLE_QUEUE_ID_OFST 8 3678 3679 /* MC_CMD_PTP_IN_GET_TIME_FORMAT msgrequest */ 3680 #define MC_CMD_PTP_IN_GET_TIME_FORMAT_LEN 8 3681 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3682 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3683 3684 /* MC_CMD_PTP_IN_GET_ATTRIBUTES msgrequest */ 3685 #define MC_CMD_PTP_IN_GET_ATTRIBUTES_LEN 8 3686 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3687 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3688 3689 /* MC_CMD_PTP_IN_GET_TIMESTAMP_CORRECTIONS msgrequest */ 3690 #define MC_CMD_PTP_IN_GET_TIMESTAMP_CORRECTIONS_LEN 8 3691 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3692 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3693 3694 /* MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE msgrequest */ 3695 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN 12 3696 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3697 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3698 /* Original field containing queue ID. Now extended to include flags. */ 3699 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_OFST 8 3700 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_LBN 0 3701 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_WIDTH 16 3702 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_REPORT_SYNC_STATUS_LBN 31 3703 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_REPORT_SYNC_STATUS_WIDTH 1 3704 3705 /* MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE msgrequest */ 3706 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN 16 3707 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3708 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3709 /* Unsubscribe options */ 3710 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL_OFST 8 3711 /* enum: Unsubscribe a single queue */ 3712 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE 0x0 3713 /* enum: Unsubscribe all queues */ 3714 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_ALL 0x1 3715 /* Event queue ID */ 3716 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE_OFST 12 3717 3718 /* MC_CMD_PTP_IN_MANFTEST_PPS msgrequest */ 3719 #define MC_CMD_PTP_IN_MANFTEST_PPS_LEN 12 3720 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3721 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3722 /* 1 to enable PPS test mode, 0 to disable and return result. */ 3723 #define MC_CMD_PTP_IN_MANFTEST_PPS_TEST_ENABLE_OFST 8 3724 3725 /* MC_CMD_PTP_IN_SET_SYNC_STATUS msgrequest */ 3726 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_LEN 24 3727 /* MC_CMD_PTP_IN_CMD_OFST 0 */ 3728 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ 3729 /* NIC - Host System Clock Synchronization status */ 3730 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_STATUS_OFST 8 3731 /* enum: Host System clock and NIC clock are not in sync */ 3732 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_NOT_IN_SYNC 0x0 3733 /* enum: Host System clock and NIC clock are synchronized */ 3734 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_IN_SYNC 0x1 3735 /* If synchronized, number of seconds until clocks should be considered to be 3736 * no longer in sync. 3737 */ 3738 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_TIMEOUT_OFST 12 3739 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED0_OFST 16 3740 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED1_OFST 20 3741 3742 /* MC_CMD_PTP_OUT msgresponse */ 3743 #define MC_CMD_PTP_OUT_LEN 0 3744 3745 /* MC_CMD_PTP_OUT_TRANSMIT msgresponse */ 3746 #define MC_CMD_PTP_OUT_TRANSMIT_LEN 8 3747 /* Value of seconds timestamp */ 3748 #define MC_CMD_PTP_OUT_TRANSMIT_SECONDS_OFST 0 3749 /* Timestamp major value */ 3750 #define MC_CMD_PTP_OUT_TRANSMIT_MAJOR_OFST 0 3751 /* Value of nanoseconds timestamp */ 3752 #define MC_CMD_PTP_OUT_TRANSMIT_NANOSECONDS_OFST 4 3753 /* Timestamp minor value */ 3754 #define MC_CMD_PTP_OUT_TRANSMIT_MINOR_OFST 4 3755 3756 /* MC_CMD_PTP_OUT_TIME_EVENT_SUBSCRIBE msgresponse */ 3757 #define MC_CMD_PTP_OUT_TIME_EVENT_SUBSCRIBE_LEN 0 3758 3759 /* MC_CMD_PTP_OUT_TIME_EVENT_UNSUBSCRIBE msgresponse */ 3760 #define MC_CMD_PTP_OUT_TIME_EVENT_UNSUBSCRIBE_LEN 0 3761 3762 /* MC_CMD_PTP_OUT_READ_NIC_TIME msgresponse */ 3763 #define MC_CMD_PTP_OUT_READ_NIC_TIME_LEN 8 3764 /* Value of seconds timestamp */ 3765 #define MC_CMD_PTP_OUT_READ_NIC_TIME_SECONDS_OFST 0 3766 /* Timestamp major value */ 3767 #define MC_CMD_PTP_OUT_READ_NIC_TIME_MAJOR_OFST 0 3768 /* Value of nanoseconds timestamp */ 3769 #define MC_CMD_PTP_OUT_READ_NIC_TIME_NANOSECONDS_OFST 4 3770 /* Timestamp minor value */ 3771 #define MC_CMD_PTP_OUT_READ_NIC_TIME_MINOR_OFST 4 3772 3773 /* MC_CMD_PTP_OUT_STATUS msgresponse */ 3774 #define MC_CMD_PTP_OUT_STATUS_LEN 64 3775 /* Frequency of NIC's hardware clock */ 3776 #define MC_CMD_PTP_OUT_STATUS_CLOCK_FREQ_OFST 0 3777 /* Number of packets transmitted and timestamped */ 3778 #define MC_CMD_PTP_OUT_STATUS_STATS_TX_OFST 4 3779 /* Number of packets received and timestamped */ 3780 #define MC_CMD_PTP_OUT_STATUS_STATS_RX_OFST 8 3781 /* Number of packets timestamped by the FPGA */ 3782 #define MC_CMD_PTP_OUT_STATUS_STATS_TS_OFST 12 3783 /* Number of packets filter matched */ 3784 #define MC_CMD_PTP_OUT_STATUS_STATS_FM_OFST 16 3785 /* Number of packets not filter matched */ 3786 #define MC_CMD_PTP_OUT_STATUS_STATS_NFM_OFST 20 3787 /* Number of PPS overflows (noise on input?) */ 3788 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFLOW_OFST 24 3789 /* Number of PPS bad periods */ 3790 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_BAD_OFST 28 3791 /* Minimum period of PPS pulse in nanoseconds */ 3792 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MIN_OFST 32 3793 /* Maximum period of PPS pulse in nanoseconds */ 3794 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MAX_OFST 36 3795 /* Last period of PPS pulse in nanoseconds */ 3796 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_LAST_OFST 40 3797 /* Mean period of PPS pulse in nanoseconds */ 3798 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MEAN_OFST 44 3799 /* Minimum offset of PPS pulse in nanoseconds (signed) */ 3800 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MIN_OFST 48 3801 /* Maximum offset of PPS pulse in nanoseconds (signed) */ 3802 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MAX_OFST 52 3803 /* Last offset of PPS pulse in nanoseconds (signed) */ 3804 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_LAST_OFST 56 3805 /* Mean offset of PPS pulse in nanoseconds (signed) */ 3806 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MEAN_OFST 60 3807 3808 /* MC_CMD_PTP_OUT_SYNCHRONIZE msgresponse */ 3809 #define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMIN 20 3810 #define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMAX 240 3811 #define MC_CMD_PTP_OUT_SYNCHRONIZE_LEN(num) (0+20*(num)) 3812 /* A set of host and NIC times */ 3813 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_OFST 0 3814 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_LEN 20 3815 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MINNUM 1 3816 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MAXNUM 12 3817 /* Host time immediately before NIC's hardware clock read */ 3818 #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTSTART_OFST 0 3819 /* Value of seconds timestamp */ 3820 #define MC_CMD_PTP_OUT_SYNCHRONIZE_SECONDS_OFST 4 3821 /* Timestamp major value */ 3822 #define MC_CMD_PTP_OUT_SYNCHRONIZE_MAJOR_OFST 4 3823 /* Value of nanoseconds timestamp */ 3824 #define MC_CMD_PTP_OUT_SYNCHRONIZE_NANOSECONDS_OFST 8 3825 /* Timestamp minor value */ 3826 #define MC_CMD_PTP_OUT_SYNCHRONIZE_MINOR_OFST 8 3827 /* Host time immediately after NIC's hardware clock read */ 3828 #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTEND_OFST 12 3829 /* Number of nanoseconds waited after reading NIC's hardware clock */ 3830 #define MC_CMD_PTP_OUT_SYNCHRONIZE_WAITNS_OFST 16 3831 3832 /* MC_CMD_PTP_OUT_MANFTEST_BASIC msgresponse */ 3833 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_LEN 8 3834 /* Results of testing */ 3835 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_RESULT_OFST 0 3836 /* enum: Successful test */ 3837 #define MC_CMD_PTP_MANF_SUCCESS 0x0 3838 /* enum: FPGA load failed */ 3839 #define MC_CMD_PTP_MANF_FPGA_LOAD 0x1 3840 /* enum: FPGA version invalid */ 3841 #define MC_CMD_PTP_MANF_FPGA_VERSION 0x2 3842 /* enum: FPGA registers incorrect */ 3843 #define MC_CMD_PTP_MANF_FPGA_REGISTERS 0x3 3844 /* enum: Oscillator possibly not working? */ 3845 #define MC_CMD_PTP_MANF_OSCILLATOR 0x4 3846 /* enum: Timestamps not increasing */ 3847 #define MC_CMD_PTP_MANF_TIMESTAMPS 0x5 3848 /* enum: Mismatched packet count */ 3849 #define MC_CMD_PTP_MANF_PACKET_COUNT 0x6 3850 /* enum: Mismatched packet count (Siena filter and FPGA) */ 3851 #define MC_CMD_PTP_MANF_FILTER_COUNT 0x7 3852 /* enum: Not enough packets to perform timestamp check */ 3853 #define MC_CMD_PTP_MANF_PACKET_ENOUGH 0x8 3854 /* enum: Timestamp trigger GPIO not working */ 3855 #define MC_CMD_PTP_MANF_GPIO_TRIGGER 0x9 3856 /* enum: Insufficient PPS events to perform checks */ 3857 #define MC_CMD_PTP_MANF_PPS_ENOUGH 0xa 3858 /* enum: PPS time event period not sufficiently close to 1s. */ 3859 #define MC_CMD_PTP_MANF_PPS_PERIOD 0xb 3860 /* enum: PPS time event nS reading not sufficiently close to zero. */ 3861 #define MC_CMD_PTP_MANF_PPS_NS 0xc 3862 /* enum: PTP peripheral registers incorrect */ 3863 #define MC_CMD_PTP_MANF_REGISTERS 0xd 3864 /* enum: Failed to read time from PTP peripheral */ 3865 #define MC_CMD_PTP_MANF_CLOCK_READ 0xe 3866 /* Presence of external oscillator */ 3867 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_EXTOSC_OFST 4 3868 3869 /* MC_CMD_PTP_OUT_MANFTEST_PACKET msgresponse */ 3870 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_LEN 12 3871 /* Results of testing */ 3872 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_RESULT_OFST 0 3873 /* Number of packets received by FPGA */ 3874 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FPGACOUNT_OFST 4 3875 /* Number of packets received by Siena filters */ 3876 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FILTERCOUNT_OFST 8 3877 3878 /* MC_CMD_PTP_OUT_FPGAREAD msgresponse */ 3879 #define MC_CMD_PTP_OUT_FPGAREAD_LENMIN 1 3880 #define MC_CMD_PTP_OUT_FPGAREAD_LENMAX 252 3881 #define MC_CMD_PTP_OUT_FPGAREAD_LEN(num) (0+1*(num)) 3882 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_OFST 0 3883 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_LEN 1 3884 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MINNUM 1 3885 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MAXNUM 252 3886 3887 /* MC_CMD_PTP_OUT_GET_TIME_FORMAT msgresponse */ 3888 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_LEN 4 3889 /* Time format required/used by for this NIC. Applies to all PTP MCDI 3890 * operations that pass times between the host and firmware. If this operation 3891 * is not supported (older firmware) a format of seconds and nanoseconds should 3892 * be assumed. 3893 */ 3894 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_FORMAT_OFST 0 3895 /* enum: Times are in seconds and nanoseconds */ 3896 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_NANOSECONDS 0x0 3897 /* enum: Major register has units of 16 second per tick, minor 8 ns per tick */ 3898 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_16SECONDS_8NANOSECONDS 0x1 3899 /* enum: Major register has units of seconds, minor 2^-27s per tick */ 3900 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_27FRACTION 0x2 3901 3902 /* MC_CMD_PTP_OUT_GET_ATTRIBUTES msgresponse */ 3903 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_LEN 24 3904 /* Time format required/used by for this NIC. Applies to all PTP MCDI 3905 * operations that pass times between the host and firmware. If this operation 3906 * is not supported (older firmware) a format of seconds and nanoseconds should 3907 * be assumed. 3908 */ 3909 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_TIME_FORMAT_OFST 0 3910 /* enum: Times are in seconds and nanoseconds */ 3911 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_NANOSECONDS 0x0 3912 /* enum: Major register has units of 16 second per tick, minor 8 ns per tick */ 3913 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_16SECONDS_8NANOSECONDS 0x1 3914 /* enum: Major register has units of seconds, minor 2^-27s per tick */ 3915 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_27FRACTION 0x2 3916 /* Minimum acceptable value for a corrected synchronization timeset. When 3917 * comparing host and NIC clock times, the MC returns a set of samples that 3918 * contain the host start and end time, the MC time when the host start was 3919 * detected and the time the MC waited between reading the time and detecting 3920 * the host end. The corrected sync window is the difference between the host 3921 * end and start times minus the time that the MC waited for host end. 3922 */ 3923 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SYNC_WINDOW_MIN_OFST 4 3924 /* Various PTP capabilities */ 3925 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_CAPABILITIES_OFST 8 3926 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_LBN 0 3927 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_WIDTH 1 3928 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED0_OFST 12 3929 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED1_OFST 16 3930 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED2_OFST 20 3931 3932 /* MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS msgresponse */ 3933 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_LEN 16 3934 /* Uncorrected error on transmit timestamps in NIC clock format */ 3935 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_TRANSMIT_OFST 0 3936 /* Uncorrected error on receive timestamps in NIC clock format */ 3937 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_RECEIVE_OFST 4 3938 /* Uncorrected error on PPS output in NIC clock format */ 3939 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_OUT_OFST 8 3940 /* Uncorrected error on PPS input in NIC clock format */ 3941 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_IN_OFST 12 3942 3943 /* MC_CMD_PTP_OUT_MANFTEST_PPS msgresponse */ 3944 #define MC_CMD_PTP_OUT_MANFTEST_PPS_LEN 4 3945 /* Results of testing */ 3946 #define MC_CMD_PTP_OUT_MANFTEST_PPS_TEST_RESULT_OFST 0 3947 /* Enum values, see field(s): */ 3948 /* MC_CMD_PTP_OUT_MANFTEST_BASIC/TEST_RESULT */ 3949 3950 /* MC_CMD_PTP_OUT_SET_SYNC_STATUS msgresponse */ 3951 #define MC_CMD_PTP_OUT_SET_SYNC_STATUS_LEN 0 3952 3953 3954 /***********************************/ 3955 /* MC_CMD_CSR_READ32 3956 * Read 32bit words from the indirect memory map. 3957 */ 3958 #define MC_CMD_CSR_READ32 0xc 3959 #undef MC_CMD_0xc_PRIVILEGE_CTG 3960 3961 #define MC_CMD_0xc_PRIVILEGE_CTG SRIOV_CTG_ADMIN 3962 3963 /* MC_CMD_CSR_READ32_IN msgrequest */ 3964 #define MC_CMD_CSR_READ32_IN_LEN 12 3965 /* Address */ 3966 #define MC_CMD_CSR_READ32_IN_ADDR_OFST 0 3967 #define MC_CMD_CSR_READ32_IN_STEP_OFST 4 3968 #define MC_CMD_CSR_READ32_IN_NUMWORDS_OFST 8 3969 3970 /* MC_CMD_CSR_READ32_OUT msgresponse */ 3971 #define MC_CMD_CSR_READ32_OUT_LENMIN 4 3972 #define MC_CMD_CSR_READ32_OUT_LENMAX 252 3973 #define MC_CMD_CSR_READ32_OUT_LEN(num) (0+4*(num)) 3974 /* The last dword is the status, not a value read */ 3975 #define MC_CMD_CSR_READ32_OUT_BUFFER_OFST 0 3976 #define MC_CMD_CSR_READ32_OUT_BUFFER_LEN 4 3977 #define MC_CMD_CSR_READ32_OUT_BUFFER_MINNUM 1 3978 #define MC_CMD_CSR_READ32_OUT_BUFFER_MAXNUM 63 3979 3980 3981 /***********************************/ 3982 /* MC_CMD_CSR_WRITE32 3983 * Write 32bit dwords to the indirect memory map. 3984 */ 3985 #define MC_CMD_CSR_WRITE32 0xd 3986 #undef MC_CMD_0xd_PRIVILEGE_CTG 3987 3988 #define MC_CMD_0xd_PRIVILEGE_CTG SRIOV_CTG_ADMIN 3989 3990 /* MC_CMD_CSR_WRITE32_IN msgrequest */ 3991 #define MC_CMD_CSR_WRITE32_IN_LENMIN 12 3992 #define MC_CMD_CSR_WRITE32_IN_LENMAX 252 3993 #define MC_CMD_CSR_WRITE32_IN_LEN(num) (8+4*(num)) 3994 /* Address */ 3995 #define MC_CMD_CSR_WRITE32_IN_ADDR_OFST 0 3996 #define MC_CMD_CSR_WRITE32_IN_STEP_OFST 4 3997 #define MC_CMD_CSR_WRITE32_IN_BUFFER_OFST 8 3998 #define MC_CMD_CSR_WRITE32_IN_BUFFER_LEN 4 3999 #define MC_CMD_CSR_WRITE32_IN_BUFFER_MINNUM 1 4000 #define MC_CMD_CSR_WRITE32_IN_BUFFER_MAXNUM 61 4001 4002 /* MC_CMD_CSR_WRITE32_OUT msgresponse */ 4003 #define MC_CMD_CSR_WRITE32_OUT_LEN 4 4004 #define MC_CMD_CSR_WRITE32_OUT_STATUS_OFST 0 4005 4006 4007 /***********************************/ 4008 /* MC_CMD_HP 4009 * These commands are used for HP related features. They are grouped under one 4010 * MCDI command to avoid creating too many MCDI commands. 4011 */ 4012 #define MC_CMD_HP 0x54 4013 #undef MC_CMD_0x54_PRIVILEGE_CTG 4014 4015 #define MC_CMD_0x54_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4016 4017 /* MC_CMD_HP_IN msgrequest */ 4018 #define MC_CMD_HP_IN_LEN 16 4019 /* HP OCSD sub-command. When address is not NULL, request activation of OCSD at 4020 * the specified address with the specified interval.When address is NULL, 4021 * INTERVAL is interpreted as a command: 0: stop OCSD / 1: Report OCSD current 4022 * state / 2: (debug) Show temperature reported by one of the supported 4023 * sensors. 4024 */ 4025 #define MC_CMD_HP_IN_SUBCMD_OFST 0 4026 /* enum: OCSD (Option Card Sensor Data) sub-command. */ 4027 #define MC_CMD_HP_IN_OCSD_SUBCMD 0x0 4028 /* enum: Last known valid HP sub-command. */ 4029 #define MC_CMD_HP_IN_LAST_SUBCMD 0x0 4030 /* The address to the array of sensor fields. (Or NULL to use a sub-command.) 4031 */ 4032 #define MC_CMD_HP_IN_OCSD_ADDR_OFST 4 4033 #define MC_CMD_HP_IN_OCSD_ADDR_LEN 8 4034 #define MC_CMD_HP_IN_OCSD_ADDR_LO_OFST 4 4035 #define MC_CMD_HP_IN_OCSD_ADDR_HI_OFST 8 4036 /* The requested update interval, in seconds. (Or the sub-command if ADDR is 4037 * NULL.) 4038 */ 4039 #define MC_CMD_HP_IN_OCSD_INTERVAL_OFST 12 4040 4041 /* MC_CMD_HP_OUT msgresponse */ 4042 #define MC_CMD_HP_OUT_LEN 4 4043 #define MC_CMD_HP_OUT_OCSD_STATUS_OFST 0 4044 /* enum: OCSD stopped for this card. */ 4045 #define MC_CMD_HP_OUT_OCSD_STOPPED 0x1 4046 /* enum: OCSD was successfully started with the address provided. */ 4047 #define MC_CMD_HP_OUT_OCSD_STARTED 0x2 4048 /* enum: OCSD was already started for this card. */ 4049 #define MC_CMD_HP_OUT_OCSD_ALREADY_STARTED 0x3 4050 4051 4052 /***********************************/ 4053 /* MC_CMD_STACKINFO 4054 * Get stack information. 4055 */ 4056 #define MC_CMD_STACKINFO 0xf 4057 #undef MC_CMD_0xf_PRIVILEGE_CTG 4058 4059 #define MC_CMD_0xf_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4060 4061 /* MC_CMD_STACKINFO_IN msgrequest */ 4062 #define MC_CMD_STACKINFO_IN_LEN 0 4063 4064 /* MC_CMD_STACKINFO_OUT msgresponse */ 4065 #define MC_CMD_STACKINFO_OUT_LENMIN 12 4066 #define MC_CMD_STACKINFO_OUT_LENMAX 252 4067 #define MC_CMD_STACKINFO_OUT_LEN(num) (0+12*(num)) 4068 /* (thread ptr, stack size, free space) for each thread in system */ 4069 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_OFST 0 4070 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_LEN 12 4071 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_MINNUM 1 4072 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_MAXNUM 21 4073 4074 4075 /***********************************/ 4076 /* MC_CMD_MDIO_READ 4077 * MDIO register read. 4078 */ 4079 #define MC_CMD_MDIO_READ 0x10 4080 #undef MC_CMD_0x10_PRIVILEGE_CTG 4081 4082 #define MC_CMD_0x10_PRIVILEGE_CTG SRIOV_CTG_GENERAL 4083 4084 /* MC_CMD_MDIO_READ_IN msgrequest */ 4085 #define MC_CMD_MDIO_READ_IN_LEN 16 4086 /* Bus number; there are two MDIO buses: one for the internal PHY, and one for 4087 * external devices. 4088 */ 4089 #define MC_CMD_MDIO_READ_IN_BUS_OFST 0 4090 /* enum: Internal. */ 4091 #define MC_CMD_MDIO_BUS_INTERNAL 0x0 4092 /* enum: External. */ 4093 #define MC_CMD_MDIO_BUS_EXTERNAL 0x1 4094 /* Port address */ 4095 #define MC_CMD_MDIO_READ_IN_PRTAD_OFST 4 4096 /* Device Address or clause 22. */ 4097 #define MC_CMD_MDIO_READ_IN_DEVAD_OFST 8 4098 /* enum: By default all the MCDI MDIO operations perform clause45 mode. If you 4099 * want to use clause22 then set DEVAD = MC_CMD_MDIO_CLAUSE22. 4100 */ 4101 #define MC_CMD_MDIO_CLAUSE22 0x20 4102 /* Address */ 4103 #define MC_CMD_MDIO_READ_IN_ADDR_OFST 12 4104 4105 /* MC_CMD_MDIO_READ_OUT msgresponse */ 4106 #define MC_CMD_MDIO_READ_OUT_LEN 8 4107 /* Value */ 4108 #define MC_CMD_MDIO_READ_OUT_VALUE_OFST 0 4109 /* Status the MDIO commands return the raw status bits from the MDIO block. A 4110 * "good" transaction should have the DONE bit set and all other bits clear. 4111 */ 4112 #define MC_CMD_MDIO_READ_OUT_STATUS_OFST 4 4113 /* enum: Good. */ 4114 #define MC_CMD_MDIO_STATUS_GOOD 0x8 4115 4116 4117 /***********************************/ 4118 /* MC_CMD_MDIO_WRITE 4119 * MDIO register write. 4120 */ 4121 #define MC_CMD_MDIO_WRITE 0x11 4122 #undef MC_CMD_0x11_PRIVILEGE_CTG 4123 4124 #define MC_CMD_0x11_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4125 4126 /* MC_CMD_MDIO_WRITE_IN msgrequest */ 4127 #define MC_CMD_MDIO_WRITE_IN_LEN 20 4128 /* Bus number; there are two MDIO buses: one for the internal PHY, and one for 4129 * external devices. 4130 */ 4131 #define MC_CMD_MDIO_WRITE_IN_BUS_OFST 0 4132 /* enum: Internal. */ 4133 /* MC_CMD_MDIO_BUS_INTERNAL 0x0 */ 4134 /* enum: External. */ 4135 /* MC_CMD_MDIO_BUS_EXTERNAL 0x1 */ 4136 /* Port address */ 4137 #define MC_CMD_MDIO_WRITE_IN_PRTAD_OFST 4 4138 /* Device Address or clause 22. */ 4139 #define MC_CMD_MDIO_WRITE_IN_DEVAD_OFST 8 4140 /* enum: By default all the MCDI MDIO operations perform clause45 mode. If you 4141 * want to use clause22 then set DEVAD = MC_CMD_MDIO_CLAUSE22. 4142 */ 4143 /* MC_CMD_MDIO_CLAUSE22 0x20 */ 4144 /* Address */ 4145 #define MC_CMD_MDIO_WRITE_IN_ADDR_OFST 12 4146 /* Value */ 4147 #define MC_CMD_MDIO_WRITE_IN_VALUE_OFST 16 4148 4149 /* MC_CMD_MDIO_WRITE_OUT msgresponse */ 4150 #define MC_CMD_MDIO_WRITE_OUT_LEN 4 4151 /* Status; the MDIO commands return the raw status bits from the MDIO block. A 4152 * "good" transaction should have the DONE bit set and all other bits clear. 4153 */ 4154 #define MC_CMD_MDIO_WRITE_OUT_STATUS_OFST 0 4155 /* enum: Good. */ 4156 /* MC_CMD_MDIO_STATUS_GOOD 0x8 */ 4157 4158 4159 /***********************************/ 4160 /* MC_CMD_DBI_WRITE 4161 * Write DBI register(s). 4162 */ 4163 #define MC_CMD_DBI_WRITE 0x12 4164 #undef MC_CMD_0x12_PRIVILEGE_CTG 4165 4166 #define MC_CMD_0x12_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4167 4168 /* MC_CMD_DBI_WRITE_IN msgrequest */ 4169 #define MC_CMD_DBI_WRITE_IN_LENMIN 12 4170 #define MC_CMD_DBI_WRITE_IN_LENMAX 252 4171 #define MC_CMD_DBI_WRITE_IN_LEN(num) (0+12*(num)) 4172 /* Each write op consists of an address (offset 0), byte enable/VF/CS2 (offset 4173 * 32) and value (offset 64). See MC_CMD_DBIWROP_TYPEDEF. 4174 */ 4175 #define MC_CMD_DBI_WRITE_IN_DBIWROP_OFST 0 4176 #define MC_CMD_DBI_WRITE_IN_DBIWROP_LEN 12 4177 #define MC_CMD_DBI_WRITE_IN_DBIWROP_MINNUM 1 4178 #define MC_CMD_DBI_WRITE_IN_DBIWROP_MAXNUM 21 4179 4180 /* MC_CMD_DBI_WRITE_OUT msgresponse */ 4181 #define MC_CMD_DBI_WRITE_OUT_LEN 0 4182 4183 /* MC_CMD_DBIWROP_TYPEDEF structuredef */ 4184 #define MC_CMD_DBIWROP_TYPEDEF_LEN 12 4185 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST 0 4186 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_LBN 0 4187 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_WIDTH 32 4188 #define MC_CMD_DBIWROP_TYPEDEF_PARMS_OFST 4 4189 #define MC_CMD_DBIWROP_TYPEDEF_VF_NUM_LBN 16 4190 #define MC_CMD_DBIWROP_TYPEDEF_VF_NUM_WIDTH 16 4191 #define MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_LBN 15 4192 #define MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_WIDTH 1 4193 #define MC_CMD_DBIWROP_TYPEDEF_CS2_LBN 14 4194 #define MC_CMD_DBIWROP_TYPEDEF_CS2_WIDTH 1 4195 #define MC_CMD_DBIWROP_TYPEDEF_PARMS_LBN 32 4196 #define MC_CMD_DBIWROP_TYPEDEF_PARMS_WIDTH 32 4197 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST 8 4198 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_LBN 64 4199 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_WIDTH 32 4200 4201 4202 /***********************************/ 4203 /* MC_CMD_PORT_READ32 4204 * Read a 32-bit register from the indirect port register map. The port to 4205 * access is implied by the Shared memory channel used. 4206 */ 4207 #define MC_CMD_PORT_READ32 0x14 4208 4209 /* MC_CMD_PORT_READ32_IN msgrequest */ 4210 #define MC_CMD_PORT_READ32_IN_LEN 4 4211 /* Address */ 4212 #define MC_CMD_PORT_READ32_IN_ADDR_OFST 0 4213 4214 /* MC_CMD_PORT_READ32_OUT msgresponse */ 4215 #define MC_CMD_PORT_READ32_OUT_LEN 8 4216 /* Value */ 4217 #define MC_CMD_PORT_READ32_OUT_VALUE_OFST 0 4218 /* Status */ 4219 #define MC_CMD_PORT_READ32_OUT_STATUS_OFST 4 4220 4221 4222 /***********************************/ 4223 /* MC_CMD_PORT_WRITE32 4224 * Write a 32-bit register to the indirect port register map. The port to 4225 * access is implied by the Shared memory channel used. 4226 */ 4227 #define MC_CMD_PORT_WRITE32 0x15 4228 4229 /* MC_CMD_PORT_WRITE32_IN msgrequest */ 4230 #define MC_CMD_PORT_WRITE32_IN_LEN 8 4231 /* Address */ 4232 #define MC_CMD_PORT_WRITE32_IN_ADDR_OFST 0 4233 /* Value */ 4234 #define MC_CMD_PORT_WRITE32_IN_VALUE_OFST 4 4235 4236 /* MC_CMD_PORT_WRITE32_OUT msgresponse */ 4237 #define MC_CMD_PORT_WRITE32_OUT_LEN 4 4238 /* Status */ 4239 #define MC_CMD_PORT_WRITE32_OUT_STATUS_OFST 0 4240 4241 4242 /***********************************/ 4243 /* MC_CMD_PORT_READ128 4244 * Read a 128-bit register from the indirect port register map. The port to 4245 * access is implied by the Shared memory channel used. 4246 */ 4247 #define MC_CMD_PORT_READ128 0x16 4248 4249 /* MC_CMD_PORT_READ128_IN msgrequest */ 4250 #define MC_CMD_PORT_READ128_IN_LEN 4 4251 /* Address */ 4252 #define MC_CMD_PORT_READ128_IN_ADDR_OFST 0 4253 4254 /* MC_CMD_PORT_READ128_OUT msgresponse */ 4255 #define MC_CMD_PORT_READ128_OUT_LEN 20 4256 /* Value */ 4257 #define MC_CMD_PORT_READ128_OUT_VALUE_OFST 0 4258 #define MC_CMD_PORT_READ128_OUT_VALUE_LEN 16 4259 /* Status */ 4260 #define MC_CMD_PORT_READ128_OUT_STATUS_OFST 16 4261 4262 4263 /***********************************/ 4264 /* MC_CMD_PORT_WRITE128 4265 * Write a 128-bit register to the indirect port register map. The port to 4266 * access is implied by the Shared memory channel used. 4267 */ 4268 #define MC_CMD_PORT_WRITE128 0x17 4269 4270 /* MC_CMD_PORT_WRITE128_IN msgrequest */ 4271 #define MC_CMD_PORT_WRITE128_IN_LEN 20 4272 /* Address */ 4273 #define MC_CMD_PORT_WRITE128_IN_ADDR_OFST 0 4274 /* Value */ 4275 #define MC_CMD_PORT_WRITE128_IN_VALUE_OFST 4 4276 #define MC_CMD_PORT_WRITE128_IN_VALUE_LEN 16 4277 4278 /* MC_CMD_PORT_WRITE128_OUT msgresponse */ 4279 #define MC_CMD_PORT_WRITE128_OUT_LEN 4 4280 /* Status */ 4281 #define MC_CMD_PORT_WRITE128_OUT_STATUS_OFST 0 4282 4283 /* MC_CMD_CAPABILITIES structuredef */ 4284 #define MC_CMD_CAPABILITIES_LEN 4 4285 /* Small buf table. */ 4286 #define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_LBN 0 4287 #define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_WIDTH 1 4288 /* Turbo mode (for Maranello). */ 4289 #define MC_CMD_CAPABILITIES_TURBO_LBN 1 4290 #define MC_CMD_CAPABILITIES_TURBO_WIDTH 1 4291 /* Turbo mode active (for Maranello). */ 4292 #define MC_CMD_CAPABILITIES_TURBO_ACTIVE_LBN 2 4293 #define MC_CMD_CAPABILITIES_TURBO_ACTIVE_WIDTH 1 4294 /* PTP offload. */ 4295 #define MC_CMD_CAPABILITIES_PTP_LBN 3 4296 #define MC_CMD_CAPABILITIES_PTP_WIDTH 1 4297 /* AOE mode. */ 4298 #define MC_CMD_CAPABILITIES_AOE_LBN 4 4299 #define MC_CMD_CAPABILITIES_AOE_WIDTH 1 4300 /* AOE mode active. */ 4301 #define MC_CMD_CAPABILITIES_AOE_ACTIVE_LBN 5 4302 #define MC_CMD_CAPABILITIES_AOE_ACTIVE_WIDTH 1 4303 /* AOE mode active. */ 4304 #define MC_CMD_CAPABILITIES_FC_ACTIVE_LBN 6 4305 #define MC_CMD_CAPABILITIES_FC_ACTIVE_WIDTH 1 4306 #define MC_CMD_CAPABILITIES_RESERVED_LBN 7 4307 #define MC_CMD_CAPABILITIES_RESERVED_WIDTH 25 4308 4309 4310 /***********************************/ 4311 /* MC_CMD_GET_BOARD_CFG 4312 * Returns the MC firmware configuration structure. 4313 */ 4314 #define MC_CMD_GET_BOARD_CFG 0x18 4315 #undef MC_CMD_0x18_PRIVILEGE_CTG 4316 4317 #define MC_CMD_0x18_PRIVILEGE_CTG SRIOV_CTG_GENERAL 4318 4319 /* MC_CMD_GET_BOARD_CFG_IN msgrequest */ 4320 #define MC_CMD_GET_BOARD_CFG_IN_LEN 0 4321 4322 /* MC_CMD_GET_BOARD_CFG_OUT msgresponse */ 4323 #define MC_CMD_GET_BOARD_CFG_OUT_LENMIN 96 4324 #define MC_CMD_GET_BOARD_CFG_OUT_LENMAX 136 4325 #define MC_CMD_GET_BOARD_CFG_OUT_LEN(num) (72+2*(num)) 4326 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_OFST 0 4327 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_OFST 4 4328 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_LEN 32 4329 /* See MC_CMD_CAPABILITIES */ 4330 #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT0_OFST 36 4331 /* See MC_CMD_CAPABILITIES */ 4332 #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT1_OFST 40 4333 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_OFST 44 4334 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_LEN 6 4335 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_OFST 50 4336 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_LEN 6 4337 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT0_OFST 56 4338 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT1_OFST 60 4339 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT0_OFST 64 4340 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT1_OFST 68 4341 /* This field contains a 16-bit value for each of the types of NVRAM area. The 4342 * values are defined in the firmware/mc/platform/.c file for a specific board 4343 * type, but otherwise have no meaning to the MC; they are used by the driver 4344 * to manage selection of appropriate firmware updates. 4345 */ 4346 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_OFST 72 4347 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_LEN 2 4348 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MINNUM 12 4349 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM 32 4350 4351 4352 /***********************************/ 4353 /* MC_CMD_DBI_READX 4354 * Read DBI register(s) -- extended functionality 4355 */ 4356 #define MC_CMD_DBI_READX 0x19 4357 #undef MC_CMD_0x19_PRIVILEGE_CTG 4358 4359 #define MC_CMD_0x19_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4360 4361 /* MC_CMD_DBI_READX_IN msgrequest */ 4362 #define MC_CMD_DBI_READX_IN_LENMIN 8 4363 #define MC_CMD_DBI_READX_IN_LENMAX 248 4364 #define MC_CMD_DBI_READX_IN_LEN(num) (0+8*(num)) 4365 /* Each Read op consists of an address (offset 0), VF/CS2) */ 4366 #define MC_CMD_DBI_READX_IN_DBIRDOP_OFST 0 4367 #define MC_CMD_DBI_READX_IN_DBIRDOP_LEN 8 4368 #define MC_CMD_DBI_READX_IN_DBIRDOP_LO_OFST 0 4369 #define MC_CMD_DBI_READX_IN_DBIRDOP_HI_OFST 4 4370 #define MC_CMD_DBI_READX_IN_DBIRDOP_MINNUM 1 4371 #define MC_CMD_DBI_READX_IN_DBIRDOP_MAXNUM 31 4372 4373 /* MC_CMD_DBI_READX_OUT msgresponse */ 4374 #define MC_CMD_DBI_READX_OUT_LENMIN 4 4375 #define MC_CMD_DBI_READX_OUT_LENMAX 252 4376 #define MC_CMD_DBI_READX_OUT_LEN(num) (0+4*(num)) 4377 /* Value */ 4378 #define MC_CMD_DBI_READX_OUT_VALUE_OFST 0 4379 #define MC_CMD_DBI_READX_OUT_VALUE_LEN 4 4380 #define MC_CMD_DBI_READX_OUT_VALUE_MINNUM 1 4381 #define MC_CMD_DBI_READX_OUT_VALUE_MAXNUM 63 4382 4383 /* MC_CMD_DBIRDOP_TYPEDEF structuredef */ 4384 #define MC_CMD_DBIRDOP_TYPEDEF_LEN 8 4385 #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_OFST 0 4386 #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_LBN 0 4387 #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_WIDTH 32 4388 #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_OFST 4 4389 #define MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_LBN 16 4390 #define MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_WIDTH 16 4391 #define MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_LBN 15 4392 #define MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_WIDTH 1 4393 #define MC_CMD_DBIRDOP_TYPEDEF_CS2_LBN 14 4394 #define MC_CMD_DBIRDOP_TYPEDEF_CS2_WIDTH 1 4395 #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_LBN 32 4396 #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_WIDTH 32 4397 4398 4399 /***********************************/ 4400 /* MC_CMD_SET_RAND_SEED 4401 * Set the 16byte seed for the MC pseudo-random generator. 4402 */ 4403 #define MC_CMD_SET_RAND_SEED 0x1a 4404 #undef MC_CMD_0x1a_PRIVILEGE_CTG 4405 4406 #define MC_CMD_0x1a_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4407 4408 /* MC_CMD_SET_RAND_SEED_IN msgrequest */ 4409 #define MC_CMD_SET_RAND_SEED_IN_LEN 16 4410 /* Seed value. */ 4411 #define MC_CMD_SET_RAND_SEED_IN_SEED_OFST 0 4412 #define MC_CMD_SET_RAND_SEED_IN_SEED_LEN 16 4413 4414 /* MC_CMD_SET_RAND_SEED_OUT msgresponse */ 4415 #define MC_CMD_SET_RAND_SEED_OUT_LEN 0 4416 4417 4418 /***********************************/ 4419 /* MC_CMD_LTSSM_HIST 4420 * Retrieve the history of the LTSSM, if the build supports it. 4421 */ 4422 #define MC_CMD_LTSSM_HIST 0x1b 4423 4424 /* MC_CMD_LTSSM_HIST_IN msgrequest */ 4425 #define MC_CMD_LTSSM_HIST_IN_LEN 0 4426 4427 /* MC_CMD_LTSSM_HIST_OUT msgresponse */ 4428 #define MC_CMD_LTSSM_HIST_OUT_LENMIN 0 4429 #define MC_CMD_LTSSM_HIST_OUT_LENMAX 252 4430 #define MC_CMD_LTSSM_HIST_OUT_LEN(num) (0+4*(num)) 4431 /* variable number of LTSSM values, as bytes. The history is read-to-clear. */ 4432 #define MC_CMD_LTSSM_HIST_OUT_DATA_OFST 0 4433 #define MC_CMD_LTSSM_HIST_OUT_DATA_LEN 4 4434 #define MC_CMD_LTSSM_HIST_OUT_DATA_MINNUM 0 4435 #define MC_CMD_LTSSM_HIST_OUT_DATA_MAXNUM 63 4436 4437 4438 /***********************************/ 4439 /* MC_CMD_DRV_ATTACH 4440 * Inform MCPU that this port is managed on the host (i.e. driver active). For 4441 * Huntington, also request the preferred datapath firmware to use if possible 4442 * (it may not be possible for this request to be fulfilled; the driver must 4443 * issue a subsequent MC_CMD_GET_CAPABILITIES command to determine which 4444 * features are actually available). The FIRMWARE_ID field is ignored by older 4445 * platforms. 4446 */ 4447 #define MC_CMD_DRV_ATTACH 0x1c 4448 #undef MC_CMD_0x1c_PRIVILEGE_CTG 4449 4450 #define MC_CMD_0x1c_PRIVILEGE_CTG SRIOV_CTG_GENERAL 4451 4452 /* MC_CMD_DRV_ATTACH_IN msgrequest */ 4453 #define MC_CMD_DRV_ATTACH_IN_LEN 12 4454 /* new state (0=detached, 1=attached) to set if UPDATE=1 */ 4455 #define MC_CMD_DRV_ATTACH_IN_NEW_STATE_OFST 0 4456 /* 1 to set new state, or 0 to just report the existing state */ 4457 #define MC_CMD_DRV_ATTACH_IN_UPDATE_OFST 4 4458 /* preferred datapath firmware (for Huntington; ignored for Siena) */ 4459 #define MC_CMD_DRV_ATTACH_IN_FIRMWARE_ID_OFST 8 4460 /* enum: Prefer to use full featured firmware */ 4461 #define MC_CMD_FW_FULL_FEATURED 0x0 4462 /* enum: Prefer to use firmware with fewer features but lower latency */ 4463 #define MC_CMD_FW_LOW_LATENCY 0x1 4464 /* enum: Prefer to use firmware for SolarCapture packed stream mode */ 4465 #define MC_CMD_FW_PACKED_STREAM 0x2 4466 /* enum: Prefer to use firmware with fewer features and simpler TX event 4467 * batching but higher TX packet rate 4468 */ 4469 #define MC_CMD_FW_HIGH_TX_RATE 0x3 4470 /* enum: Reserved value */ 4471 #define MC_CMD_FW_PACKED_STREAM_HASH_MODE_1 0x4 4472 /* enum: Only this option is allowed for non-admin functions */ 4473 #define MC_CMD_FW_DONT_CARE 0xffffffff 4474 4475 /* MC_CMD_DRV_ATTACH_OUT msgresponse */ 4476 #define MC_CMD_DRV_ATTACH_OUT_LEN 4 4477 /* previous or existing state (0=detached, 1=attached) */ 4478 #define MC_CMD_DRV_ATTACH_OUT_OLD_STATE_OFST 0 4479 4480 /* MC_CMD_DRV_ATTACH_EXT_OUT msgresponse */ 4481 #define MC_CMD_DRV_ATTACH_EXT_OUT_LEN 8 4482 /* previous or existing state (0=detached, 1=attached) */ 4483 #define MC_CMD_DRV_ATTACH_EXT_OUT_OLD_STATE_OFST 0 4484 /* Flags associated with this function */ 4485 #define MC_CMD_DRV_ATTACH_EXT_OUT_FUNC_FLAGS_OFST 4 4486 /* enum: Labels the lowest-numbered function visible to the OS */ 4487 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY 0x0 4488 /* enum: The function can control the link state of the physical port it is 4489 * bound to. 4490 */ 4491 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL 0x1 4492 /* enum: The function can perform privileged operations */ 4493 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TRUSTED 0x2 4494 4495 4496 /***********************************/ 4497 /* MC_CMD_SHMUART 4498 * Route UART output to circular buffer in shared memory instead. 4499 */ 4500 #define MC_CMD_SHMUART 0x1f 4501 4502 /* MC_CMD_SHMUART_IN msgrequest */ 4503 #define MC_CMD_SHMUART_IN_LEN 4 4504 /* ??? */ 4505 #define MC_CMD_SHMUART_IN_FLAG_OFST 0 4506 4507 /* MC_CMD_SHMUART_OUT msgresponse */ 4508 #define MC_CMD_SHMUART_OUT_LEN 0 4509 4510 4511 /***********************************/ 4512 /* MC_CMD_PORT_RESET 4513 * Generic per-port reset. There is no equivalent for per-board reset. Locks 4514 * required: None; Return code: 0, ETIME. NOTE: This command is deprecated - 4515 * use MC_CMD_ENTITY_RESET instead. 4516 */ 4517 #define MC_CMD_PORT_RESET 0x20 4518 #undef MC_CMD_0x20_PRIVILEGE_CTG 4519 4520 #define MC_CMD_0x20_PRIVILEGE_CTG SRIOV_CTG_GENERAL 4521 4522 /* MC_CMD_PORT_RESET_IN msgrequest */ 4523 #define MC_CMD_PORT_RESET_IN_LEN 0 4524 4525 /* MC_CMD_PORT_RESET_OUT msgresponse */ 4526 #define MC_CMD_PORT_RESET_OUT_LEN 0 4527 4528 4529 /***********************************/ 4530 /* MC_CMD_ENTITY_RESET 4531 * Generic per-resource reset. There is no equivalent for per-board reset. 4532 * Locks required: None; Return code: 0, ETIME. NOTE: This command is an 4533 * extended version of the deprecated MC_CMD_PORT_RESET with added fields. 4534 */ 4535 #define MC_CMD_ENTITY_RESET 0x20 4536 /* MC_CMD_0x20_PRIVILEGE_CTG SRIOV_CTG_GENERAL */ 4537 4538 /* MC_CMD_ENTITY_RESET_IN msgrequest */ 4539 #define MC_CMD_ENTITY_RESET_IN_LEN 4 4540 /* Optional flags field. Omitting this will perform a "legacy" reset action 4541 * (TBD). 4542 */ 4543 #define MC_CMD_ENTITY_RESET_IN_FLAG_OFST 0 4544 #define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_LBN 0 4545 #define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_WIDTH 1 4546 4547 /* MC_CMD_ENTITY_RESET_OUT msgresponse */ 4548 #define MC_CMD_ENTITY_RESET_OUT_LEN 0 4549 4550 4551 /***********************************/ 4552 /* MC_CMD_PCIE_CREDITS 4553 * Read instantaneous and minimum flow control thresholds. 4554 */ 4555 #define MC_CMD_PCIE_CREDITS 0x21 4556 4557 /* MC_CMD_PCIE_CREDITS_IN msgrequest */ 4558 #define MC_CMD_PCIE_CREDITS_IN_LEN 8 4559 /* poll period. 0 is disabled */ 4560 #define MC_CMD_PCIE_CREDITS_IN_POLL_PERIOD_OFST 0 4561 /* wipe statistics */ 4562 #define MC_CMD_PCIE_CREDITS_IN_WIPE_OFST 4 4563 4564 /* MC_CMD_PCIE_CREDITS_OUT msgresponse */ 4565 #define MC_CMD_PCIE_CREDITS_OUT_LEN 16 4566 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_OFST 0 4567 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_LEN 2 4568 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_OFST 2 4569 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_LEN 2 4570 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_OFST 4 4571 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_LEN 2 4572 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_OFST 6 4573 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_LEN 2 4574 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_OFST 8 4575 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_LEN 2 4576 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_OFST 10 4577 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_LEN 2 4578 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_OFST 12 4579 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_LEN 2 4580 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_OFST 14 4581 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_LEN 2 4582 4583 4584 /***********************************/ 4585 /* MC_CMD_RXD_MONITOR 4586 * Get histogram of RX queue fill level. 4587 */ 4588 #define MC_CMD_RXD_MONITOR 0x22 4589 4590 /* MC_CMD_RXD_MONITOR_IN msgrequest */ 4591 #define MC_CMD_RXD_MONITOR_IN_LEN 12 4592 #define MC_CMD_RXD_MONITOR_IN_QID_OFST 0 4593 #define MC_CMD_RXD_MONITOR_IN_POLL_PERIOD_OFST 4 4594 #define MC_CMD_RXD_MONITOR_IN_WIPE_OFST 8 4595 4596 /* MC_CMD_RXD_MONITOR_OUT msgresponse */ 4597 #define MC_CMD_RXD_MONITOR_OUT_LEN 80 4598 #define MC_CMD_RXD_MONITOR_OUT_QID_OFST 0 4599 #define MC_CMD_RXD_MONITOR_OUT_RING_FILL_OFST 4 4600 #define MC_CMD_RXD_MONITOR_OUT_CACHE_FILL_OFST 8 4601 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_1_OFST 12 4602 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_2_OFST 16 4603 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_4_OFST 20 4604 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_8_OFST 24 4605 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_16_OFST 28 4606 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_32_OFST 32 4607 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_64_OFST 36 4608 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_128_OFST 40 4609 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_256_OFST 44 4610 #define MC_CMD_RXD_MONITOR_OUT_RING_GE_256_OFST 48 4611 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_1_OFST 52 4612 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_2_OFST 56 4613 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_4_OFST 60 4614 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_8_OFST 64 4615 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_16_OFST 68 4616 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_32_OFST 72 4617 #define MC_CMD_RXD_MONITOR_OUT_CACHE_GE_32_OFST 76 4618 4619 4620 /***********************************/ 4621 /* MC_CMD_PUTS 4622 * Copy the given ASCII string out onto UART and/or out of the network port. 4623 */ 4624 #define MC_CMD_PUTS 0x23 4625 #undef MC_CMD_0x23_PRIVILEGE_CTG 4626 4627 #define MC_CMD_0x23_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4628 4629 /* MC_CMD_PUTS_IN msgrequest */ 4630 #define MC_CMD_PUTS_IN_LENMIN 13 4631 #define MC_CMD_PUTS_IN_LENMAX 252 4632 #define MC_CMD_PUTS_IN_LEN(num) (12+1*(num)) 4633 #define MC_CMD_PUTS_IN_DEST_OFST 0 4634 #define MC_CMD_PUTS_IN_UART_LBN 0 4635 #define MC_CMD_PUTS_IN_UART_WIDTH 1 4636 #define MC_CMD_PUTS_IN_PORT_LBN 1 4637 #define MC_CMD_PUTS_IN_PORT_WIDTH 1 4638 #define MC_CMD_PUTS_IN_DHOST_OFST 4 4639 #define MC_CMD_PUTS_IN_DHOST_LEN 6 4640 #define MC_CMD_PUTS_IN_STRING_OFST 12 4641 #define MC_CMD_PUTS_IN_STRING_LEN 1 4642 #define MC_CMD_PUTS_IN_STRING_MINNUM 1 4643 #define MC_CMD_PUTS_IN_STRING_MAXNUM 240 4644 4645 /* MC_CMD_PUTS_OUT msgresponse */ 4646 #define MC_CMD_PUTS_OUT_LEN 0 4647 4648 4649 /***********************************/ 4650 /* MC_CMD_GET_PHY_CFG 4651 * Report PHY configuration. This guarantees to succeed even if the PHY is in a 4652 * 'zombie' state. Locks required: None 4653 */ 4654 #define MC_CMD_GET_PHY_CFG 0x24 4655 #undef MC_CMD_0x24_PRIVILEGE_CTG 4656 4657 #define MC_CMD_0x24_PRIVILEGE_CTG SRIOV_CTG_GENERAL 4658 4659 /* MC_CMD_GET_PHY_CFG_IN msgrequest */ 4660 #define MC_CMD_GET_PHY_CFG_IN_LEN 0 4661 4662 /* MC_CMD_GET_PHY_CFG_OUT msgresponse */ 4663 #define MC_CMD_GET_PHY_CFG_OUT_LEN 72 4664 /* flags */ 4665 #define MC_CMD_GET_PHY_CFG_OUT_FLAGS_OFST 0 4666 #define MC_CMD_GET_PHY_CFG_OUT_PRESENT_LBN 0 4667 #define MC_CMD_GET_PHY_CFG_OUT_PRESENT_WIDTH 1 4668 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_LBN 1 4669 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_WIDTH 1 4670 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_LBN 2 4671 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_WIDTH 1 4672 #define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_LBN 3 4673 #define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_WIDTH 1 4674 #define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_LBN 4 4675 #define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_WIDTH 1 4676 #define MC_CMD_GET_PHY_CFG_OUT_TXDIS_LBN 5 4677 #define MC_CMD_GET_PHY_CFG_OUT_TXDIS_WIDTH 1 4678 #define MC_CMD_GET_PHY_CFG_OUT_BIST_LBN 6 4679 #define MC_CMD_GET_PHY_CFG_OUT_BIST_WIDTH 1 4680 /* ?? */ 4681 #define MC_CMD_GET_PHY_CFG_OUT_TYPE_OFST 4 4682 /* Bitmask of supported capabilities */ 4683 #define MC_CMD_GET_PHY_CFG_OUT_SUPPORTED_CAP_OFST 8 4684 #define MC_CMD_PHY_CAP_10HDX_LBN 1 4685 #define MC_CMD_PHY_CAP_10HDX_WIDTH 1 4686 #define MC_CMD_PHY_CAP_10FDX_LBN 2 4687 #define MC_CMD_PHY_CAP_10FDX_WIDTH 1 4688 #define MC_CMD_PHY_CAP_100HDX_LBN 3 4689 #define MC_CMD_PHY_CAP_100HDX_WIDTH 1 4690 #define MC_CMD_PHY_CAP_100FDX_LBN 4 4691 #define MC_CMD_PHY_CAP_100FDX_WIDTH 1 4692 #define MC_CMD_PHY_CAP_1000HDX_LBN 5 4693 #define MC_CMD_PHY_CAP_1000HDX_WIDTH 1 4694 #define MC_CMD_PHY_CAP_1000FDX_LBN 6 4695 #define MC_CMD_PHY_CAP_1000FDX_WIDTH 1 4696 #define MC_CMD_PHY_CAP_10000FDX_LBN 7 4697 #define MC_CMD_PHY_CAP_10000FDX_WIDTH 1 4698 #define MC_CMD_PHY_CAP_PAUSE_LBN 8 4699 #define MC_CMD_PHY_CAP_PAUSE_WIDTH 1 4700 #define MC_CMD_PHY_CAP_ASYM_LBN 9 4701 #define MC_CMD_PHY_CAP_ASYM_WIDTH 1 4702 #define MC_CMD_PHY_CAP_AN_LBN 10 4703 #define MC_CMD_PHY_CAP_AN_WIDTH 1 4704 #define MC_CMD_PHY_CAP_40000FDX_LBN 11 4705 #define MC_CMD_PHY_CAP_40000FDX_WIDTH 1 4706 #define MC_CMD_PHY_CAP_DDM_LBN 12 4707 #define MC_CMD_PHY_CAP_DDM_WIDTH 1 4708 /* ?? */ 4709 #define MC_CMD_GET_PHY_CFG_OUT_CHANNEL_OFST 12 4710 /* ?? */ 4711 #define MC_CMD_GET_PHY_CFG_OUT_PRT_OFST 16 4712 /* ?? */ 4713 #define MC_CMD_GET_PHY_CFG_OUT_STATS_MASK_OFST 20 4714 /* ?? */ 4715 #define MC_CMD_GET_PHY_CFG_OUT_NAME_OFST 24 4716 #define MC_CMD_GET_PHY_CFG_OUT_NAME_LEN 20 4717 /* ?? */ 4718 #define MC_CMD_GET_PHY_CFG_OUT_MEDIA_TYPE_OFST 44 4719 /* enum: Xaui. */ 4720 #define MC_CMD_MEDIA_XAUI 0x1 4721 /* enum: CX4. */ 4722 #define MC_CMD_MEDIA_CX4 0x2 4723 /* enum: KX4. */ 4724 #define MC_CMD_MEDIA_KX4 0x3 4725 /* enum: XFP Far. */ 4726 #define MC_CMD_MEDIA_XFP 0x4 4727 /* enum: SFP+. */ 4728 #define MC_CMD_MEDIA_SFP_PLUS 0x5 4729 /* enum: 10GBaseT. */ 4730 #define MC_CMD_MEDIA_BASE_T 0x6 4731 /* enum: QSFP+. */ 4732 #define MC_CMD_MEDIA_QSFP_PLUS 0x7 4733 #define MC_CMD_GET_PHY_CFG_OUT_MMD_MASK_OFST 48 4734 /* enum: Native clause 22 */ 4735 #define MC_CMD_MMD_CLAUSE22 0x0 4736 #define MC_CMD_MMD_CLAUSE45_PMAPMD 0x1 /* enum */ 4737 #define MC_CMD_MMD_CLAUSE45_WIS 0x2 /* enum */ 4738 #define MC_CMD_MMD_CLAUSE45_PCS 0x3 /* enum */ 4739 #define MC_CMD_MMD_CLAUSE45_PHYXS 0x4 /* enum */ 4740 #define MC_CMD_MMD_CLAUSE45_DTEXS 0x5 /* enum */ 4741 #define MC_CMD_MMD_CLAUSE45_TC 0x6 /* enum */ 4742 #define MC_CMD_MMD_CLAUSE45_AN 0x7 /* enum */ 4743 /* enum: Clause22 proxied over clause45 by PHY. */ 4744 #define MC_CMD_MMD_CLAUSE45_C22EXT 0x1d 4745 #define MC_CMD_MMD_CLAUSE45_VEND1 0x1e /* enum */ 4746 #define MC_CMD_MMD_CLAUSE45_VEND2 0x1f /* enum */ 4747 #define MC_CMD_GET_PHY_CFG_OUT_REVISION_OFST 52 4748 #define MC_CMD_GET_PHY_CFG_OUT_REVISION_LEN 20 4749 4750 4751 /***********************************/ 4752 /* MC_CMD_START_BIST 4753 * Start a BIST test on the PHY. Locks required: PHY_LOCK if doing a PHY BIST 4754 * Return code: 0, EINVAL, EACCES (if PHY_LOCK is not held) 4755 */ 4756 #define MC_CMD_START_BIST 0x25 4757 #undef MC_CMD_0x25_PRIVILEGE_CTG 4758 4759 #define MC_CMD_0x25_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4760 4761 /* MC_CMD_START_BIST_IN msgrequest */ 4762 #define MC_CMD_START_BIST_IN_LEN 4 4763 /* Type of test. */ 4764 #define MC_CMD_START_BIST_IN_TYPE_OFST 0 4765 /* enum: Run the PHY's short cable BIST. */ 4766 #define MC_CMD_PHY_BIST_CABLE_SHORT 0x1 4767 /* enum: Run the PHY's long cable BIST. */ 4768 #define MC_CMD_PHY_BIST_CABLE_LONG 0x2 4769 /* enum: Run BIST on the currently selected BPX Serdes (XAUI or XFI) . */ 4770 #define MC_CMD_BPX_SERDES_BIST 0x3 4771 /* enum: Run the MC loopback tests. */ 4772 #define MC_CMD_MC_LOOPBACK_BIST 0x4 4773 /* enum: Run the PHY's standard BIST. */ 4774 #define MC_CMD_PHY_BIST 0x5 4775 /* enum: Run MC RAM test. */ 4776 #define MC_CMD_MC_MEM_BIST 0x6 4777 /* enum: Run Port RAM test. */ 4778 #define MC_CMD_PORT_MEM_BIST 0x7 4779 /* enum: Run register test. */ 4780 #define MC_CMD_REG_BIST 0x8 4781 4782 /* MC_CMD_START_BIST_OUT msgresponse */ 4783 #define MC_CMD_START_BIST_OUT_LEN 0 4784 4785 4786 /***********************************/ 4787 /* MC_CMD_POLL_BIST 4788 * Poll for BIST completion. Returns a single status code, and optionally some 4789 * PHY specific bist output. The driver should only consume the BIST output 4790 * after validating OUTLEN and MC_CMD_GET_PHY_CFG.TYPE. If a driver can't 4791 * successfully parse the BIST output, it should still respect the pass/Fail in 4792 * OUT.RESULT. Locks required: PHY_LOCK if doing a PHY BIST. Return code: 0, 4793 * EACCES (if PHY_LOCK is not held). 4794 */ 4795 #define MC_CMD_POLL_BIST 0x26 4796 #undef MC_CMD_0x26_PRIVILEGE_CTG 4797 4798 #define MC_CMD_0x26_PRIVILEGE_CTG SRIOV_CTG_ADMIN 4799 4800 /* MC_CMD_POLL_BIST_IN msgrequest */ 4801 #define MC_CMD_POLL_BIST_IN_LEN 0 4802 4803 /* MC_CMD_POLL_BIST_OUT msgresponse */ 4804 #define MC_CMD_POLL_BIST_OUT_LEN 8 4805 /* result */ 4806 #define MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 4807 /* enum: Running. */ 4808 #define MC_CMD_POLL_BIST_RUNNING 0x1 4809 /* enum: Passed. */ 4810 #define MC_CMD_POLL_BIST_PASSED 0x2 4811 /* enum: Failed. */ 4812 #define MC_CMD_POLL_BIST_FAILED 0x3 4813 /* enum: Timed-out. */ 4814 #define MC_CMD_POLL_BIST_TIMEOUT 0x4 4815 #define MC_CMD_POLL_BIST_OUT_PRIVATE_OFST 4 4816 4817 /* MC_CMD_POLL_BIST_OUT_SFT9001 msgresponse */ 4818 #define MC_CMD_POLL_BIST_OUT_SFT9001_LEN 36 4819 /* result */ 4820 /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */ 4821 /* Enum values, see field(s): */ 4822 /* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */ 4823 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A_OFST 4 4824 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B_OFST 8 4825 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C_OFST 12 4826 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D_OFST 16 4827 /* Status of each channel A */ 4828 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_A_OFST 20 4829 /* enum: Ok. */ 4830 #define MC_CMD_POLL_BIST_SFT9001_PAIR_OK 0x1 4831 /* enum: Open. */ 4832 #define MC_CMD_POLL_BIST_SFT9001_PAIR_OPEN 0x2 4833 /* enum: Intra-pair short. */ 4834 #define MC_CMD_POLL_BIST_SFT9001_INTRA_PAIR_SHORT 0x3 4835 /* enum: Inter-pair short. */ 4836 #define MC_CMD_POLL_BIST_SFT9001_INTER_PAIR_SHORT 0x4 4837 /* enum: Busy. */ 4838 #define MC_CMD_POLL_BIST_SFT9001_PAIR_BUSY 0x9 4839 /* Status of each channel B */ 4840 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_B_OFST 24 4841 /* Enum values, see field(s): */ 4842 /* CABLE_STATUS_A */ 4843 /* Status of each channel C */ 4844 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_C_OFST 28 4845 /* Enum values, see field(s): */ 4846 /* CABLE_STATUS_A */ 4847 /* Status of each channel D */ 4848 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_D_OFST 32 4849 /* Enum values, see field(s): */ 4850 /* CABLE_STATUS_A */ 4851 4852 /* MC_CMD_POLL_BIST_OUT_MRSFP msgresponse */ 4853 #define MC_CMD_POLL_BIST_OUT_MRSFP_LEN 8 4854 /* result */ 4855 /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */ 4856 /* Enum values, see field(s): */ 4857 /* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */ 4858 #define MC_CMD_POLL_BIST_OUT_MRSFP_TEST_OFST 4 4859 /* enum: Complete. */ 4860 #define MC_CMD_POLL_BIST_MRSFP_TEST_COMPLETE 0x0 4861 /* enum: Bus switch off I2C write. */ 4862 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_WRITE 0x1 4863 /* enum: Bus switch off I2C no access IO exp. */ 4864 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_IO_EXP 0x2 4865 /* enum: Bus switch off I2C no access module. */ 4866 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_MODULE 0x3 4867 /* enum: IO exp I2C configure. */ 4868 #define MC_CMD_POLL_BIST_MRSFP_TEST_IO_EXP_I2C_CONFIGURE 0x4 4869 /* enum: Bus switch I2C no cross talk. */ 4870 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_I2C_NO_CROSSTALK 0x5 4871 /* enum: Module presence. */ 4872 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_PRESENCE 0x6 4873 /* enum: Module ID I2C access. */ 4874 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_I2C_ACCESS 0x7 4875 /* enum: Module ID sane value. */ 4876 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_SANE_VALUE 0x8 4877 4878 /* MC_CMD_POLL_BIST_OUT_MEM msgresponse */ 4879 #define MC_CMD_POLL_BIST_OUT_MEM_LEN 36 4880 /* result */ 4881 /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */ 4882 /* Enum values, see field(s): */ 4883 /* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */ 4884 #define MC_CMD_POLL_BIST_OUT_MEM_TEST_OFST 4 4885 /* enum: Test has completed. */ 4886 #define MC_CMD_POLL_BIST_MEM_COMPLETE 0x0 4887 /* enum: RAM test - walk ones. */ 4888 #define MC_CMD_POLL_BIST_MEM_MEM_WALK_ONES 0x1 4889 /* enum: RAM test - walk zeros. */ 4890 #define MC_CMD_POLL_BIST_MEM_MEM_WALK_ZEROS 0x2 4891 /* enum: RAM test - walking inversions zeros/ones. */ 4892 #define MC_CMD_POLL_BIST_MEM_MEM_INV_ZERO_ONE 0x3 4893 /* enum: RAM test - walking inversions checkerboard. */ 4894 #define MC_CMD_POLL_BIST_MEM_MEM_INV_CHKBOARD 0x4 4895 /* enum: Register test - set / clear individual bits. */ 4896 #define MC_CMD_POLL_BIST_MEM_REG 0x5 4897 /* enum: ECC error detected. */ 4898 #define MC_CMD_POLL_BIST_MEM_ECC 0x6 4899 /* Failure address, only valid if result is POLL_BIST_FAILED */ 4900 #define MC_CMD_POLL_BIST_OUT_MEM_ADDR_OFST 8 4901 /* Bus or address space to which the failure address corresponds */ 4902 #define MC_CMD_POLL_BIST_OUT_MEM_BUS_OFST 12 4903 /* enum: MC MIPS bus. */ 4904 #define MC_CMD_POLL_BIST_MEM_BUS_MC 0x0 4905 /* enum: CSR IREG bus. */ 4906 #define MC_CMD_POLL_BIST_MEM_BUS_CSR 0x1 4907 /* enum: RX DPCPU bus. */ 4908 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_RX 0x2 4909 /* enum: TX0 DPCPU bus. */ 4910 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX0 0x3 4911 /* enum: TX1 DPCPU bus. */ 4912 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX1 0x4 4913 /* enum: RX DICPU bus. */ 4914 #define MC_CMD_POLL_BIST_MEM_BUS_DICPU_RX 0x5 4915 /* enum: TX DICPU bus. */ 4916 #define MC_CMD_POLL_BIST_MEM_BUS_DICPU_TX 0x6 4917 /* Pattern written to RAM / register */ 4918 #define MC_CMD_POLL_BIST_OUT_MEM_EXPECT_OFST 16 4919 /* Actual value read from RAM / register */ 4920 #define MC_CMD_POLL_BIST_OUT_MEM_ACTUAL_OFST 20 4921 /* ECC error mask */ 4922 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_OFST 24 4923 /* ECC parity error mask */ 4924 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_PARITY_OFST 28 4925 /* ECC fatal error mask */ 4926 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_FATAL_OFST 32 4927 4928 4929 /***********************************/ 4930 /* MC_CMD_FLUSH_RX_QUEUES 4931 * Flush receive queue(s). If SRIOV is enabled (via MC_CMD_SRIOV), then RXQ 4932 * flushes should be initiated via this MCDI operation, rather than via 4933 * directly writing FLUSH_CMD. 4934 * 4935 * The flush is completed (either done/fail) asynchronously (after this command 4936 * returns). The driver must still wait for flush done/failure events as usual. 4937 */ 4938 #define MC_CMD_FLUSH_RX_QUEUES 0x27 4939 4940 /* MC_CMD_FLUSH_RX_QUEUES_IN msgrequest */ 4941 #define MC_CMD_FLUSH_RX_QUEUES_IN_LENMIN 4 4942 #define MC_CMD_FLUSH_RX_QUEUES_IN_LENMAX 252 4943 #define MC_CMD_FLUSH_RX_QUEUES_IN_LEN(num) (0+4*(num)) 4944 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_OFST 0 4945 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_LEN 4 4946 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MINNUM 1 4947 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MAXNUM 63 4948 4949 /* MC_CMD_FLUSH_RX_QUEUES_OUT msgresponse */ 4950 #define MC_CMD_FLUSH_RX_QUEUES_OUT_LEN 0 4951 4952 4953 /***********************************/ 4954 /* MC_CMD_GET_LOOPBACK_MODES 4955 * Returns a bitmask of loopback modes available at each speed. 4956 */ 4957 #define MC_CMD_GET_LOOPBACK_MODES 0x28 4958 #undef MC_CMD_0x28_PRIVILEGE_CTG 4959 4960 #define MC_CMD_0x28_PRIVILEGE_CTG SRIOV_CTG_GENERAL 4961 4962 /* MC_CMD_GET_LOOPBACK_MODES_IN msgrequest */ 4963 #define MC_CMD_GET_LOOPBACK_MODES_IN_LEN 0 4964 4965 /* MC_CMD_GET_LOOPBACK_MODES_OUT msgresponse */ 4966 #define MC_CMD_GET_LOOPBACK_MODES_OUT_LEN 40 4967 /* Supported loopbacks. */ 4968 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_OFST 0 4969 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LEN 8 4970 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_OFST 0 4971 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_OFST 4 4972 /* enum: None. */ 4973 #define MC_CMD_LOOPBACK_NONE 0x0 4974 /* enum: Data. */ 4975 #define MC_CMD_LOOPBACK_DATA 0x1 4976 /* enum: GMAC. */ 4977 #define MC_CMD_LOOPBACK_GMAC 0x2 4978 /* enum: XGMII. */ 4979 #define MC_CMD_LOOPBACK_XGMII 0x3 4980 /* enum: XGXS. */ 4981 #define MC_CMD_LOOPBACK_XGXS 0x4 4982 /* enum: XAUI. */ 4983 #define MC_CMD_LOOPBACK_XAUI 0x5 4984 /* enum: GMII. */ 4985 #define MC_CMD_LOOPBACK_GMII 0x6 4986 /* enum: SGMII. */ 4987 #define MC_CMD_LOOPBACK_SGMII 0x7 4988 /* enum: XGBR. */ 4989 #define MC_CMD_LOOPBACK_XGBR 0x8 4990 /* enum: XFI. */ 4991 #define MC_CMD_LOOPBACK_XFI 0x9 4992 /* enum: XAUI Far. */ 4993 #define MC_CMD_LOOPBACK_XAUI_FAR 0xa 4994 /* enum: GMII Far. */ 4995 #define MC_CMD_LOOPBACK_GMII_FAR 0xb 4996 /* enum: SGMII Far. */ 4997 #define MC_CMD_LOOPBACK_SGMII_FAR 0xc 4998 /* enum: XFI Far. */ 4999 #define MC_CMD_LOOPBACK_XFI_FAR 0xd 5000 /* enum: GPhy. */ 5001 #define MC_CMD_LOOPBACK_GPHY 0xe 5002 /* enum: PhyXS. */ 5003 #define MC_CMD_LOOPBACK_PHYXS 0xf 5004 /* enum: PCS. */ 5005 #define MC_CMD_LOOPBACK_PCS 0x10 5006 /* enum: PMA-PMD. */ 5007 #define MC_CMD_LOOPBACK_PMAPMD 0x11 5008 /* enum: Cross-Port. */ 5009 #define MC_CMD_LOOPBACK_XPORT 0x12 5010 /* enum: XGMII-Wireside. */ 5011 #define MC_CMD_LOOPBACK_XGMII_WS 0x13 5012 /* enum: XAUI Wireside. */ 5013 #define MC_CMD_LOOPBACK_XAUI_WS 0x14 5014 /* enum: XAUI Wireside Far. */ 5015 #define MC_CMD_LOOPBACK_XAUI_WS_FAR 0x15 5016 /* enum: XAUI Wireside near. */ 5017 #define MC_CMD_LOOPBACK_XAUI_WS_NEAR 0x16 5018 /* enum: GMII Wireside. */ 5019 #define MC_CMD_LOOPBACK_GMII_WS 0x17 5020 /* enum: XFI Wireside. */ 5021 #define MC_CMD_LOOPBACK_XFI_WS 0x18 5022 /* enum: XFI Wireside Far. */ 5023 #define MC_CMD_LOOPBACK_XFI_WS_FAR 0x19 5024 /* enum: PhyXS Wireside. */ 5025 #define MC_CMD_LOOPBACK_PHYXS_WS 0x1a 5026 /* enum: PMA lanes MAC-Serdes. */ 5027 #define MC_CMD_LOOPBACK_PMA_INT 0x1b 5028 /* enum: KR Serdes Parallel (Encoder). */ 5029 #define MC_CMD_LOOPBACK_SD_NEAR 0x1c 5030 /* enum: KR Serdes Serial. */ 5031 #define MC_CMD_LOOPBACK_SD_FAR 0x1d 5032 /* enum: PMA lanes MAC-Serdes Wireside. */ 5033 #define MC_CMD_LOOPBACK_PMA_INT_WS 0x1e 5034 /* enum: KR Serdes Parallel Wireside (Full PCS). */ 5035 #define MC_CMD_LOOPBACK_SD_FEP2_WS 0x1f 5036 /* enum: KR Serdes Parallel Wireside (Sym Aligner to TX). */ 5037 #define MC_CMD_LOOPBACK_SD_FEP1_5_WS 0x20 5038 /* enum: KR Serdes Parallel Wireside (Deserializer to Serializer). */ 5039 #define MC_CMD_LOOPBACK_SD_FEP_WS 0x21 5040 /* enum: KR Serdes Serial Wireside. */ 5041 #define MC_CMD_LOOPBACK_SD_FES_WS 0x22 5042 /* enum: Near side of AOE Siena side port */ 5043 #define MC_CMD_LOOPBACK_AOE_INT_NEAR 0x23 5044 /* enum: Medford Wireside datapath loopback */ 5045 #define MC_CMD_LOOPBACK_DATA_WS 0x24 5046 /* enum: Force link up without setting up any physical loopback (snapper use 5047 * only) 5048 */ 5049 #define MC_CMD_LOOPBACK_FORCE_EXT_LINK 0x25 5050 /* Supported loopbacks. */ 5051 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_OFST 8 5052 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LEN 8 5053 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LO_OFST 8 5054 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_HI_OFST 12 5055 /* Enum values, see field(s): */ 5056 /* 100M */ 5057 /* Supported loopbacks. */ 5058 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_OFST 16 5059 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LEN 8 5060 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LO_OFST 16 5061 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_HI_OFST 20 5062 /* Enum values, see field(s): */ 5063 /* 100M */ 5064 /* Supported loopbacks. */ 5065 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_OFST 24 5066 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LEN 8 5067 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LO_OFST 24 5068 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_HI_OFST 28 5069 /* Enum values, see field(s): */ 5070 /* 100M */ 5071 /* Supported loopbacks. */ 5072 #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_OFST 32 5073 #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LEN 8 5074 #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LO_OFST 32 5075 #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_HI_OFST 36 5076 /* Enum values, see field(s): */ 5077 /* 100M */ 5078 5079 5080 /***********************************/ 5081 /* MC_CMD_GET_LINK 5082 * Read the unified MAC/PHY link state. Locks required: None Return code: 0, 5083 * ETIME. 5084 */ 5085 #define MC_CMD_GET_LINK 0x29 5086 #undef MC_CMD_0x29_PRIVILEGE_CTG 5087 5088 #define MC_CMD_0x29_PRIVILEGE_CTG SRIOV_CTG_GENERAL 5089 5090 /* MC_CMD_GET_LINK_IN msgrequest */ 5091 #define MC_CMD_GET_LINK_IN_LEN 0 5092 5093 /* MC_CMD_GET_LINK_OUT msgresponse */ 5094 #define MC_CMD_GET_LINK_OUT_LEN 28 5095 /* near-side advertised capabilities */ 5096 #define MC_CMD_GET_LINK_OUT_CAP_OFST 0 5097 /* link-partner advertised capabilities */ 5098 #define MC_CMD_GET_LINK_OUT_LP_CAP_OFST 4 5099 /* Autonegotiated speed in mbit/s. The link may still be down even if this 5100 * reads non-zero. 5101 */ 5102 #define MC_CMD_GET_LINK_OUT_LINK_SPEED_OFST 8 5103 /* Current loopback setting. */ 5104 #define MC_CMD_GET_LINK_OUT_LOOPBACK_MODE_OFST 12 5105 /* Enum values, see field(s): */ 5106 /* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */ 5107 #define MC_CMD_GET_LINK_OUT_FLAGS_OFST 16 5108 #define MC_CMD_GET_LINK_OUT_LINK_UP_LBN 0 5109 #define MC_CMD_GET_LINK_OUT_LINK_UP_WIDTH 1 5110 #define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_LBN 1 5111 #define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_WIDTH 1 5112 #define MC_CMD_GET_LINK_OUT_BPX_LINK_LBN 2 5113 #define MC_CMD_GET_LINK_OUT_BPX_LINK_WIDTH 1 5114 #define MC_CMD_GET_LINK_OUT_PHY_LINK_LBN 3 5115 #define MC_CMD_GET_LINK_OUT_PHY_LINK_WIDTH 1 5116 #define MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_LBN 6 5117 #define MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_WIDTH 1 5118 #define MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_LBN 7 5119 #define MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_WIDTH 1 5120 /* This returns the negotiated flow control value. */ 5121 #define MC_CMD_GET_LINK_OUT_FCNTL_OFST 20 5122 /* Enum values, see field(s): */ 5123 /* MC_CMD_SET_MAC/MC_CMD_SET_MAC_IN/FCNTL */ 5124 #define MC_CMD_GET_LINK_OUT_MAC_FAULT_OFST 24 5125 #define MC_CMD_MAC_FAULT_XGMII_LOCAL_LBN 0 5126 #define MC_CMD_MAC_FAULT_XGMII_LOCAL_WIDTH 1 5127 #define MC_CMD_MAC_FAULT_XGMII_REMOTE_LBN 1 5128 #define MC_CMD_MAC_FAULT_XGMII_REMOTE_WIDTH 1 5129 #define MC_CMD_MAC_FAULT_SGMII_REMOTE_LBN 2 5130 #define MC_CMD_MAC_FAULT_SGMII_REMOTE_WIDTH 1 5131 #define MC_CMD_MAC_FAULT_PENDING_RECONFIG_LBN 3 5132 #define MC_CMD_MAC_FAULT_PENDING_RECONFIG_WIDTH 1 5133 5134 5135 /***********************************/ 5136 /* MC_CMD_SET_LINK 5137 * Write the unified MAC/PHY link configuration. Locks required: None. Return 5138 * code: 0, EINVAL, ETIME 5139 */ 5140 #define MC_CMD_SET_LINK 0x2a 5141 #undef MC_CMD_0x2a_PRIVILEGE_CTG 5142 5143 #define MC_CMD_0x2a_PRIVILEGE_CTG SRIOV_CTG_LINK 5144 5145 /* MC_CMD_SET_LINK_IN msgrequest */ 5146 #define MC_CMD_SET_LINK_IN_LEN 16 5147 /* ??? */ 5148 #define MC_CMD_SET_LINK_IN_CAP_OFST 0 5149 /* Flags */ 5150 #define MC_CMD_SET_LINK_IN_FLAGS_OFST 4 5151 #define MC_CMD_SET_LINK_IN_LOWPOWER_LBN 0 5152 #define MC_CMD_SET_LINK_IN_LOWPOWER_WIDTH 1 5153 #define MC_CMD_SET_LINK_IN_POWEROFF_LBN 1 5154 #define MC_CMD_SET_LINK_IN_POWEROFF_WIDTH 1 5155 #define MC_CMD_SET_LINK_IN_TXDIS_LBN 2 5156 #define MC_CMD_SET_LINK_IN_TXDIS_WIDTH 1 5157 /* Loopback mode. */ 5158 #define MC_CMD_SET_LINK_IN_LOOPBACK_MODE_OFST 8 5159 /* Enum values, see field(s): */ 5160 /* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */ 5161 /* A loopback speed of "0" is supported, and means (choose any available 5162 * speed). 5163 */ 5164 #define MC_CMD_SET_LINK_IN_LOOPBACK_SPEED_OFST 12 5165 5166 /* MC_CMD_SET_LINK_OUT msgresponse */ 5167 #define MC_CMD_SET_LINK_OUT_LEN 0 5168 5169 5170 /***********************************/ 5171 /* MC_CMD_SET_ID_LED 5172 * Set identification LED state. Locks required: None. Return code: 0, EINVAL 5173 */ 5174 #define MC_CMD_SET_ID_LED 0x2b 5175 #undef MC_CMD_0x2b_PRIVILEGE_CTG 5176 5177 #define MC_CMD_0x2b_PRIVILEGE_CTG SRIOV_CTG_LINK 5178 5179 /* MC_CMD_SET_ID_LED_IN msgrequest */ 5180 #define MC_CMD_SET_ID_LED_IN_LEN 4 5181 /* Set LED state. */ 5182 #define MC_CMD_SET_ID_LED_IN_STATE_OFST 0 5183 #define MC_CMD_LED_OFF 0x0 /* enum */ 5184 #define MC_CMD_LED_ON 0x1 /* enum */ 5185 #define MC_CMD_LED_DEFAULT 0x2 /* enum */ 5186 5187 /* MC_CMD_SET_ID_LED_OUT msgresponse */ 5188 #define MC_CMD_SET_ID_LED_OUT_LEN 0 5189 5190 5191 /***********************************/ 5192 /* MC_CMD_SET_MAC 5193 * Set MAC configuration. Locks required: None. Return code: 0, EINVAL 5194 */ 5195 #define MC_CMD_SET_MAC 0x2c 5196 #undef MC_CMD_0x2c_PRIVILEGE_CTG 5197 5198 #define MC_CMD_0x2c_PRIVILEGE_CTG SRIOV_CTG_LINK 5199 5200 /* MC_CMD_SET_MAC_IN msgrequest */ 5201 #define MC_CMD_SET_MAC_IN_LEN 28 5202 /* The MTU is the MTU programmed directly into the XMAC/GMAC (inclusive of 5203 * EtherII, VLAN, bug16011 padding). 5204 */ 5205 #define MC_CMD_SET_MAC_IN_MTU_OFST 0 5206 #define MC_CMD_SET_MAC_IN_DRAIN_OFST 4 5207 #define MC_CMD_SET_MAC_IN_ADDR_OFST 8 5208 #define MC_CMD_SET_MAC_IN_ADDR_LEN 8 5209 #define MC_CMD_SET_MAC_IN_ADDR_LO_OFST 8 5210 #define MC_CMD_SET_MAC_IN_ADDR_HI_OFST 12 5211 #define MC_CMD_SET_MAC_IN_REJECT_OFST 16 5212 #define MC_CMD_SET_MAC_IN_REJECT_UNCST_LBN 0 5213 #define MC_CMD_SET_MAC_IN_REJECT_UNCST_WIDTH 1 5214 #define MC_CMD_SET_MAC_IN_REJECT_BRDCST_LBN 1 5215 #define MC_CMD_SET_MAC_IN_REJECT_BRDCST_WIDTH 1 5216 #define MC_CMD_SET_MAC_IN_FCNTL_OFST 20 5217 /* enum: Flow control is off. */ 5218 #define MC_CMD_FCNTL_OFF 0x0 5219 /* enum: Respond to flow control. */ 5220 #define MC_CMD_FCNTL_RESPOND 0x1 5221 /* enum: Respond to and Issue flow control. */ 5222 #define MC_CMD_FCNTL_BIDIR 0x2 5223 /* enum: Auto neg flow control. */ 5224 #define MC_CMD_FCNTL_AUTO 0x3 5225 /* enum: Priority flow control (eftest builds only). */ 5226 #define MC_CMD_FCNTL_QBB 0x4 5227 /* enum: Issue flow control. */ 5228 #define MC_CMD_FCNTL_GENERATE 0x5 5229 #define MC_CMD_SET_MAC_IN_FLAGS_OFST 24 5230 #define MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_LBN 0 5231 #define MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_WIDTH 1 5232 5233 /* MC_CMD_SET_MAC_OUT msgresponse */ 5234 #define MC_CMD_SET_MAC_OUT_LEN 0 5235 5236 5237 /***********************************/ 5238 /* MC_CMD_PHY_STATS 5239 * Get generic PHY statistics. This call returns the statistics for a generic 5240 * PHY in a sparse array (indexed by the enumerate). Each value is represented 5241 * by a 32bit number. If the DMA_ADDR is 0, then no DMA is performed, and the 5242 * statistics may be read from the message response. If DMA_ADDR != 0, then the 5243 * statistics are dmad to that (page-aligned location). Locks required: None. 5244 * Returns: 0, ETIME 5245 */ 5246 #define MC_CMD_PHY_STATS 0x2d 5247 #undef MC_CMD_0x2d_PRIVILEGE_CTG 5248 5249 #define MC_CMD_0x2d_PRIVILEGE_CTG SRIOV_CTG_LINK 5250 5251 /* MC_CMD_PHY_STATS_IN msgrequest */ 5252 #define MC_CMD_PHY_STATS_IN_LEN 8 5253 /* ??? */ 5254 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_OFST 0 5255 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_LEN 8 5256 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_OFST 0 5257 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_HI_OFST 4 5258 5259 /* MC_CMD_PHY_STATS_OUT_DMA msgresponse */ 5260 #define MC_CMD_PHY_STATS_OUT_DMA_LEN 0 5261 5262 /* MC_CMD_PHY_STATS_OUT_NO_DMA msgresponse */ 5263 #define MC_CMD_PHY_STATS_OUT_NO_DMA_LEN (((MC_CMD_PHY_NSTATS*32))>>3) 5264 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_OFST 0 5265 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_LEN 4 5266 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_PHY_NSTATS 5267 /* enum: OUI. */ 5268 #define MC_CMD_OUI 0x0 5269 /* enum: PMA-PMD Link Up. */ 5270 #define MC_CMD_PMA_PMD_LINK_UP 0x1 5271 /* enum: PMA-PMD RX Fault. */ 5272 #define MC_CMD_PMA_PMD_RX_FAULT 0x2 5273 /* enum: PMA-PMD TX Fault. */ 5274 #define MC_CMD_PMA_PMD_TX_FAULT 0x3 5275 /* enum: PMA-PMD Signal */ 5276 #define MC_CMD_PMA_PMD_SIGNAL 0x4 5277 /* enum: PMA-PMD SNR A. */ 5278 #define MC_CMD_PMA_PMD_SNR_A 0x5 5279 /* enum: PMA-PMD SNR B. */ 5280 #define MC_CMD_PMA_PMD_SNR_B 0x6 5281 /* enum: PMA-PMD SNR C. */ 5282 #define MC_CMD_PMA_PMD_SNR_C 0x7 5283 /* enum: PMA-PMD SNR D. */ 5284 #define MC_CMD_PMA_PMD_SNR_D 0x8 5285 /* enum: PCS Link Up. */ 5286 #define MC_CMD_PCS_LINK_UP 0x9 5287 /* enum: PCS RX Fault. */ 5288 #define MC_CMD_PCS_RX_FAULT 0xa 5289 /* enum: PCS TX Fault. */ 5290 #define MC_CMD_PCS_TX_FAULT 0xb 5291 /* enum: PCS BER. */ 5292 #define MC_CMD_PCS_BER 0xc 5293 /* enum: PCS Block Errors. */ 5294 #define MC_CMD_PCS_BLOCK_ERRORS 0xd 5295 /* enum: PhyXS Link Up. */ 5296 #define MC_CMD_PHYXS_LINK_UP 0xe 5297 /* enum: PhyXS RX Fault. */ 5298 #define MC_CMD_PHYXS_RX_FAULT 0xf 5299 /* enum: PhyXS TX Fault. */ 5300 #define MC_CMD_PHYXS_TX_FAULT 0x10 5301 /* enum: PhyXS Align. */ 5302 #define MC_CMD_PHYXS_ALIGN 0x11 5303 /* enum: PhyXS Sync. */ 5304 #define MC_CMD_PHYXS_SYNC 0x12 5305 /* enum: AN link-up. */ 5306 #define MC_CMD_AN_LINK_UP 0x13 5307 /* enum: AN Complete. */ 5308 #define MC_CMD_AN_COMPLETE 0x14 5309 /* enum: AN 10GBaseT Status. */ 5310 #define MC_CMD_AN_10GBT_STATUS 0x15 5311 /* enum: Clause 22 Link-Up. */ 5312 #define MC_CMD_CL22_LINK_UP 0x16 5313 /* enum: (Last entry) */ 5314 #define MC_CMD_PHY_NSTATS 0x17 5315 5316 5317 /***********************************/ 5318 /* MC_CMD_MAC_STATS 5319 * Get generic MAC statistics. This call returns unified statistics maintained 5320 * by the MC as it switches between the GMAC and XMAC. The MC will write out 5321 * all supported stats. The driver should zero initialise the buffer to 5322 * guarantee consistent results. If the DMA_ADDR is 0, then no DMA is 5323 * performed, and the statistics may be read from the message response. If 5324 * DMA_ADDR != 0, then the statistics are dmad to that (page-aligned location). 5325 * Locks required: None. The PERIODIC_CLEAR option is not used and now has no 5326 * effect. Returns: 0, ETIME 5327 */ 5328 #define MC_CMD_MAC_STATS 0x2e 5329 #undef MC_CMD_0x2e_PRIVILEGE_CTG 5330 5331 #define MC_CMD_0x2e_PRIVILEGE_CTG SRIOV_CTG_GENERAL 5332 5333 /* MC_CMD_MAC_STATS_IN msgrequest */ 5334 #define MC_CMD_MAC_STATS_IN_LEN 20 5335 /* ??? */ 5336 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_OFST 0 5337 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_LEN 8 5338 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_OFST 0 5339 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_OFST 4 5340 #define MC_CMD_MAC_STATS_IN_CMD_OFST 8 5341 #define MC_CMD_MAC_STATS_IN_DMA_LBN 0 5342 #define MC_CMD_MAC_STATS_IN_DMA_WIDTH 1 5343 #define MC_CMD_MAC_STATS_IN_CLEAR_LBN 1 5344 #define MC_CMD_MAC_STATS_IN_CLEAR_WIDTH 1 5345 #define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_LBN 2 5346 #define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_WIDTH 1 5347 #define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_LBN 3 5348 #define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_WIDTH 1 5349 #define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_LBN 4 5350 #define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_WIDTH 1 5351 #define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_LBN 5 5352 #define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_WIDTH 1 5353 #define MC_CMD_MAC_STATS_IN_PERIOD_MS_LBN 16 5354 #define MC_CMD_MAC_STATS_IN_PERIOD_MS_WIDTH 16 5355 #define MC_CMD_MAC_STATS_IN_DMA_LEN_OFST 12 5356 /* port id so vadapter stats can be provided */ 5357 #define MC_CMD_MAC_STATS_IN_PORT_ID_OFST 16 5358 5359 /* MC_CMD_MAC_STATS_OUT_DMA msgresponse */ 5360 #define MC_CMD_MAC_STATS_OUT_DMA_LEN 0 5361 5362 /* MC_CMD_MAC_STATS_OUT_NO_DMA msgresponse */ 5363 #define MC_CMD_MAC_STATS_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS*64))>>3) 5364 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_OFST 0 5365 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LEN 8 5366 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_OFST 0 5367 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_OFST 4 5368 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS 5369 #define MC_CMD_MAC_GENERATION_START 0x0 /* enum */ 5370 #define MC_CMD_MAC_DMABUF_START 0x1 /* enum */ 5371 #define MC_CMD_MAC_TX_PKTS 0x1 /* enum */ 5372 #define MC_CMD_MAC_TX_PAUSE_PKTS 0x2 /* enum */ 5373 #define MC_CMD_MAC_TX_CONTROL_PKTS 0x3 /* enum */ 5374 #define MC_CMD_MAC_TX_UNICAST_PKTS 0x4 /* enum */ 5375 #define MC_CMD_MAC_TX_MULTICAST_PKTS 0x5 /* enum */ 5376 #define MC_CMD_MAC_TX_BROADCAST_PKTS 0x6 /* enum */ 5377 #define MC_CMD_MAC_TX_BYTES 0x7 /* enum */ 5378 #define MC_CMD_MAC_TX_BAD_BYTES 0x8 /* enum */ 5379 #define MC_CMD_MAC_TX_LT64_PKTS 0x9 /* enum */ 5380 #define MC_CMD_MAC_TX_64_PKTS 0xa /* enum */ 5381 #define MC_CMD_MAC_TX_65_TO_127_PKTS 0xb /* enum */ 5382 #define MC_CMD_MAC_TX_128_TO_255_PKTS 0xc /* enum */ 5383 #define MC_CMD_MAC_TX_256_TO_511_PKTS 0xd /* enum */ 5384 #define MC_CMD_MAC_TX_512_TO_1023_PKTS 0xe /* enum */ 5385 #define MC_CMD_MAC_TX_1024_TO_15XX_PKTS 0xf /* enum */ 5386 #define MC_CMD_MAC_TX_15XX_TO_JUMBO_PKTS 0x10 /* enum */ 5387 #define MC_CMD_MAC_TX_GTJUMBO_PKTS 0x11 /* enum */ 5388 #define MC_CMD_MAC_TX_BAD_FCS_PKTS 0x12 /* enum */ 5389 #define MC_CMD_MAC_TX_SINGLE_COLLISION_PKTS 0x13 /* enum */ 5390 #define MC_CMD_MAC_TX_MULTIPLE_COLLISION_PKTS 0x14 /* enum */ 5391 #define MC_CMD_MAC_TX_EXCESSIVE_COLLISION_PKTS 0x15 /* enum */ 5392 #define MC_CMD_MAC_TX_LATE_COLLISION_PKTS 0x16 /* enum */ 5393 #define MC_CMD_MAC_TX_DEFERRED_PKTS 0x17 /* enum */ 5394 #define MC_CMD_MAC_TX_EXCESSIVE_DEFERRED_PKTS 0x18 /* enum */ 5395 #define MC_CMD_MAC_TX_NON_TCPUDP_PKTS 0x19 /* enum */ 5396 #define MC_CMD_MAC_TX_MAC_SRC_ERR_PKTS 0x1a /* enum */ 5397 #define MC_CMD_MAC_TX_IP_SRC_ERR_PKTS 0x1b /* enum */ 5398 #define MC_CMD_MAC_RX_PKTS 0x1c /* enum */ 5399 #define MC_CMD_MAC_RX_PAUSE_PKTS 0x1d /* enum */ 5400 #define MC_CMD_MAC_RX_GOOD_PKTS 0x1e /* enum */ 5401 #define MC_CMD_MAC_RX_CONTROL_PKTS 0x1f /* enum */ 5402 #define MC_CMD_MAC_RX_UNICAST_PKTS 0x20 /* enum */ 5403 #define MC_CMD_MAC_RX_MULTICAST_PKTS 0x21 /* enum */ 5404 #define MC_CMD_MAC_RX_BROADCAST_PKTS 0x22 /* enum */ 5405 #define MC_CMD_MAC_RX_BYTES 0x23 /* enum */ 5406 #define MC_CMD_MAC_RX_BAD_BYTES 0x24 /* enum */ 5407 #define MC_CMD_MAC_RX_64_PKTS 0x25 /* enum */ 5408 #define MC_CMD_MAC_RX_65_TO_127_PKTS 0x26 /* enum */ 5409 #define MC_CMD_MAC_RX_128_TO_255_PKTS 0x27 /* enum */ 5410 #define MC_CMD_MAC_RX_256_TO_511_PKTS 0x28 /* enum */ 5411 #define MC_CMD_MAC_RX_512_TO_1023_PKTS 0x29 /* enum */ 5412 #define MC_CMD_MAC_RX_1024_TO_15XX_PKTS 0x2a /* enum */ 5413 #define MC_CMD_MAC_RX_15XX_TO_JUMBO_PKTS 0x2b /* enum */ 5414 #define MC_CMD_MAC_RX_GTJUMBO_PKTS 0x2c /* enum */ 5415 #define MC_CMD_MAC_RX_UNDERSIZE_PKTS 0x2d /* enum */ 5416 #define MC_CMD_MAC_RX_BAD_FCS_PKTS 0x2e /* enum */ 5417 #define MC_CMD_MAC_RX_OVERFLOW_PKTS 0x2f /* enum */ 5418 #define MC_CMD_MAC_RX_FALSE_CARRIER_PKTS 0x30 /* enum */ 5419 #define MC_CMD_MAC_RX_SYMBOL_ERROR_PKTS 0x31 /* enum */ 5420 #define MC_CMD_MAC_RX_ALIGN_ERROR_PKTS 0x32 /* enum */ 5421 #define MC_CMD_MAC_RX_LENGTH_ERROR_PKTS 0x33 /* enum */ 5422 #define MC_CMD_MAC_RX_INTERNAL_ERROR_PKTS 0x34 /* enum */ 5423 #define MC_CMD_MAC_RX_JABBER_PKTS 0x35 /* enum */ 5424 #define MC_CMD_MAC_RX_NODESC_DROPS 0x36 /* enum */ 5425 #define MC_CMD_MAC_RX_LANES01_CHAR_ERR 0x37 /* enum */ 5426 #define MC_CMD_MAC_RX_LANES23_CHAR_ERR 0x38 /* enum */ 5427 #define MC_CMD_MAC_RX_LANES01_DISP_ERR 0x39 /* enum */ 5428 #define MC_CMD_MAC_RX_LANES23_DISP_ERR 0x3a /* enum */ 5429 #define MC_CMD_MAC_RX_MATCH_FAULT 0x3b /* enum */ 5430 /* enum: PM trunc_bb_overflow counter. Valid for EF10 with PM_AND_RXDP_COUNTERS 5431 * capability only. 5432 */ 5433 #define MC_CMD_MAC_PM_TRUNC_BB_OVERFLOW 0x3c 5434 /* enum: PM discard_bb_overflow counter. Valid for EF10 with 5435 * PM_AND_RXDP_COUNTERS capability only. 5436 */ 5437 #define MC_CMD_MAC_PM_DISCARD_BB_OVERFLOW 0x3d 5438 /* enum: PM trunc_vfifo_full counter. Valid for EF10 with PM_AND_RXDP_COUNTERS 5439 * capability only. 5440 */ 5441 #define MC_CMD_MAC_PM_TRUNC_VFIFO_FULL 0x3e 5442 /* enum: PM discard_vfifo_full counter. Valid for EF10 with 5443 * PM_AND_RXDP_COUNTERS capability only. 5444 */ 5445 #define MC_CMD_MAC_PM_DISCARD_VFIFO_FULL 0x3f 5446 /* enum: PM trunc_qbb counter. Valid for EF10 with PM_AND_RXDP_COUNTERS 5447 * capability only. 5448 */ 5449 #define MC_CMD_MAC_PM_TRUNC_QBB 0x40 5450 /* enum: PM discard_qbb counter. Valid for EF10 with PM_AND_RXDP_COUNTERS 5451 * capability only. 5452 */ 5453 #define MC_CMD_MAC_PM_DISCARD_QBB 0x41 5454 /* enum: PM discard_mapping counter. Valid for EF10 with PM_AND_RXDP_COUNTERS 5455 * capability only. 5456 */ 5457 #define MC_CMD_MAC_PM_DISCARD_MAPPING 0x42 5458 /* enum: RXDP counter: Number of packets dropped due to the queue being 5459 * disabled. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only. 5460 */ 5461 #define MC_CMD_MAC_RXDP_Q_DISABLED_PKTS 0x43 5462 /* enum: RXDP counter: Number of packets dropped by the DICPU. Valid for EF10 5463 * with PM_AND_RXDP_COUNTERS capability only. 5464 */ 5465 #define MC_CMD_MAC_RXDP_DI_DROPPED_PKTS 0x45 5466 /* enum: RXDP counter: Number of non-host packets. Valid for EF10 with 5467 * PM_AND_RXDP_COUNTERS capability only. 5468 */ 5469 #define MC_CMD_MAC_RXDP_STREAMING_PKTS 0x46 5470 /* enum: RXDP counter: Number of times an hlb descriptor fetch was performed. 5471 * Valid for EF10 with PM_AND_RXDP_COUNTERS capability only. 5472 */ 5473 #define MC_CMD_MAC_RXDP_HLB_FETCH_CONDITIONS 0x47 5474 /* enum: RXDP counter: Number of times the DPCPU waited for an existing 5475 * descriptor fetch. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only. 5476 */ 5477 #define MC_CMD_MAC_RXDP_HLB_WAIT_CONDITIONS 0x48 5478 #define MC_CMD_MAC_VADAPTER_RX_DMABUF_START 0x4c /* enum */ 5479 #define MC_CMD_MAC_VADAPTER_RX_UNICAST_PACKETS 0x4c /* enum */ 5480 #define MC_CMD_MAC_VADAPTER_RX_UNICAST_BYTES 0x4d /* enum */ 5481 #define MC_CMD_MAC_VADAPTER_RX_MULTICAST_PACKETS 0x4e /* enum */ 5482 #define MC_CMD_MAC_VADAPTER_RX_MULTICAST_BYTES 0x4f /* enum */ 5483 #define MC_CMD_MAC_VADAPTER_RX_BROADCAST_PACKETS 0x50 /* enum */ 5484 #define MC_CMD_MAC_VADAPTER_RX_BROADCAST_BYTES 0x51 /* enum */ 5485 #define MC_CMD_MAC_VADAPTER_RX_BAD_PACKETS 0x52 /* enum */ 5486 #define MC_CMD_MAC_VADAPTER_RX_BAD_BYTES 0x53 /* enum */ 5487 #define MC_CMD_MAC_VADAPTER_RX_OVERFLOW 0x54 /* enum */ 5488 #define MC_CMD_MAC_VADAPTER_TX_DMABUF_START 0x57 /* enum */ 5489 #define MC_CMD_MAC_VADAPTER_TX_UNICAST_PACKETS 0x57 /* enum */ 5490 #define MC_CMD_MAC_VADAPTER_TX_UNICAST_BYTES 0x58 /* enum */ 5491 #define MC_CMD_MAC_VADAPTER_TX_MULTICAST_PACKETS 0x59 /* enum */ 5492 #define MC_CMD_MAC_VADAPTER_TX_MULTICAST_BYTES 0x5a /* enum */ 5493 #define MC_CMD_MAC_VADAPTER_TX_BROADCAST_PACKETS 0x5b /* enum */ 5494 #define MC_CMD_MAC_VADAPTER_TX_BROADCAST_BYTES 0x5c /* enum */ 5495 #define MC_CMD_MAC_VADAPTER_TX_BAD_PACKETS 0x5d /* enum */ 5496 #define MC_CMD_MAC_VADAPTER_TX_BAD_BYTES 0x5e /* enum */ 5497 #define MC_CMD_MAC_VADAPTER_TX_OVERFLOW 0x5f /* enum */ 5498 /* enum: Start of GMAC stats buffer space, for Siena only. */ 5499 #define MC_CMD_GMAC_DMABUF_START 0x40 5500 /* enum: End of GMAC stats buffer space, for Siena only. */ 5501 #define MC_CMD_GMAC_DMABUF_END 0x5f 5502 #define MC_CMD_MAC_GENERATION_END 0x60 /* enum */ 5503 #define MC_CMD_MAC_NSTATS 0x61 /* enum */ 5504 5505 5506 /***********************************/ 5507 /* MC_CMD_SRIOV 5508 * to be documented 5509 */ 5510 #define MC_CMD_SRIOV 0x30 5511 5512 /* MC_CMD_SRIOV_IN msgrequest */ 5513 #define MC_CMD_SRIOV_IN_LEN 12 5514 #define MC_CMD_SRIOV_IN_ENABLE_OFST 0 5515 #define MC_CMD_SRIOV_IN_VI_BASE_OFST 4 5516 #define MC_CMD_SRIOV_IN_VF_COUNT_OFST 8 5517 5518 /* MC_CMD_SRIOV_OUT msgresponse */ 5519 #define MC_CMD_SRIOV_OUT_LEN 8 5520 #define MC_CMD_SRIOV_OUT_VI_SCALE_OFST 0 5521 #define MC_CMD_SRIOV_OUT_VF_TOTAL_OFST 4 5522 5523 /* MC_CMD_MEMCPY_RECORD_TYPEDEF structuredef */ 5524 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LEN 32 5525 /* this is only used for the first record */ 5526 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_OFST 0 5527 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_LBN 0 5528 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_WIDTH 32 5529 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_OFST 4 5530 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_LBN 32 5531 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_WIDTH 32 5532 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_OFST 8 5533 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LEN 8 5534 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LO_OFST 8 5535 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_HI_OFST 12 5536 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LBN 64 5537 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_WIDTH 64 5538 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_OFST 16 5539 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_RID_INLINE 0x100 /* enum */ 5540 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_LBN 128 5541 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_WIDTH 32 5542 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_OFST 20 5543 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LEN 8 5544 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LO_OFST 20 5545 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_HI_OFST 24 5546 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LBN 160 5547 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_WIDTH 64 5548 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_OFST 28 5549 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_LBN 224 5550 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_WIDTH 32 5551 5552 5553 /***********************************/ 5554 /* MC_CMD_MEMCPY 5555 * DMA write data into (Rid,Addr), either by dma reading (Rid,Addr), or by data 5556 * embedded directly in the command. 5557 * 5558 * A common pattern is for a client to use generation counts to signal a dma 5559 * update of a datastructure. To facilitate this, this MCDI operation can 5560 * contain multiple requests which are executed in strict order. Requests take 5561 * the form of duplicating the entire MCDI request continuously (including the 5562 * requests record, which is ignored in all but the first structure) 5563 * 5564 * The source data can either come from a DMA from the host, or it can be 5565 * embedded within the request directly, thereby eliminating a DMA read. To 5566 * indicate this, the client sets FROM_RID=%RID_INLINE, ADDR_HI=0, and 5567 * ADDR_LO=offset, and inserts the data at %offset from the start of the 5568 * payload. It's the callers responsibility to ensure that the embedded data 5569 * doesn't overlap the records. 5570 * 5571 * Returns: 0, EINVAL (invalid RID) 5572 */ 5573 #define MC_CMD_MEMCPY 0x31 5574 5575 /* MC_CMD_MEMCPY_IN msgrequest */ 5576 #define MC_CMD_MEMCPY_IN_LENMIN 32 5577 #define MC_CMD_MEMCPY_IN_LENMAX 224 5578 #define MC_CMD_MEMCPY_IN_LEN(num) (0+32*(num)) 5579 /* see MC_CMD_MEMCPY_RECORD_TYPEDEF */ 5580 #define MC_CMD_MEMCPY_IN_RECORD_OFST 0 5581 #define MC_CMD_MEMCPY_IN_RECORD_LEN 32 5582 #define MC_CMD_MEMCPY_IN_RECORD_MINNUM 1 5583 #define MC_CMD_MEMCPY_IN_RECORD_MAXNUM 7 5584 5585 /* MC_CMD_MEMCPY_OUT msgresponse */ 5586 #define MC_CMD_MEMCPY_OUT_LEN 0 5587 5588 5589 /***********************************/ 5590 /* MC_CMD_WOL_FILTER_SET 5591 * Set a WoL filter. 5592 */ 5593 #define MC_CMD_WOL_FILTER_SET 0x32 5594 #undef MC_CMD_0x32_PRIVILEGE_CTG 5595 5596 #define MC_CMD_0x32_PRIVILEGE_CTG SRIOV_CTG_LINK 5597 5598 /* MC_CMD_WOL_FILTER_SET_IN msgrequest */ 5599 #define MC_CMD_WOL_FILTER_SET_IN_LEN 192 5600 #define MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 5601 #define MC_CMD_FILTER_MODE_SIMPLE 0x0 /* enum */ 5602 #define MC_CMD_FILTER_MODE_STRUCTURED 0xffffffff /* enum */ 5603 /* A type value of 1 is unused. */ 5604 #define MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 5605 /* enum: Magic */ 5606 #define MC_CMD_WOL_TYPE_MAGIC 0x0 5607 /* enum: MS Windows Magic */ 5608 #define MC_CMD_WOL_TYPE_WIN_MAGIC 0x2 5609 /* enum: IPv4 Syn */ 5610 #define MC_CMD_WOL_TYPE_IPV4_SYN 0x3 5611 /* enum: IPv6 Syn */ 5612 #define MC_CMD_WOL_TYPE_IPV6_SYN 0x4 5613 /* enum: Bitmap */ 5614 #define MC_CMD_WOL_TYPE_BITMAP 0x5 5615 /* enum: Link */ 5616 #define MC_CMD_WOL_TYPE_LINK 0x6 5617 /* enum: (Above this for future use) */ 5618 #define MC_CMD_WOL_TYPE_MAX 0x7 5619 #define MC_CMD_WOL_FILTER_SET_IN_DATA_OFST 8 5620 #define MC_CMD_WOL_FILTER_SET_IN_DATA_LEN 4 5621 #define MC_CMD_WOL_FILTER_SET_IN_DATA_NUM 46 5622 5623 /* MC_CMD_WOL_FILTER_SET_IN_MAGIC msgrequest */ 5624 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_LEN 16 5625 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 5626 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 5627 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_OFST 8 5628 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LEN 8 5629 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LO_OFST 8 5630 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_HI_OFST 12 5631 5632 /* MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN msgrequest */ 5633 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_LEN 20 5634 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 5635 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 5636 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_IP_OFST 8 5637 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_IP_OFST 12 5638 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_OFST 16 5639 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_LEN 2 5640 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_OFST 18 5641 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_LEN 2 5642 5643 /* MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN msgrequest */ 5644 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_LEN 44 5645 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 5646 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 5647 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_OFST 8 5648 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_LEN 16 5649 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_OFST 24 5650 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_LEN 16 5651 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_OFST 40 5652 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_LEN 2 5653 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_OFST 42 5654 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_LEN 2 5655 5656 /* MC_CMD_WOL_FILTER_SET_IN_BITMAP msgrequest */ 5657 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN 187 5658 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 5659 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 5660 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_OFST 8 5661 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_LEN 48 5662 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_OFST 56 5663 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_LEN 128 5664 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_OFST 184 5665 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_LEN 1 5666 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_OFST 185 5667 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_LEN 1 5668 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_OFST 186 5669 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_LEN 1 5670 5671 /* MC_CMD_WOL_FILTER_SET_IN_LINK msgrequest */ 5672 #define MC_CMD_WOL_FILTER_SET_IN_LINK_LEN 12 5673 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ 5674 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ 5675 #define MC_CMD_WOL_FILTER_SET_IN_LINK_MASK_OFST 8 5676 #define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_LBN 0 5677 #define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_WIDTH 1 5678 #define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_LBN 1 5679 #define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_WIDTH 1 5680 5681 /* MC_CMD_WOL_FILTER_SET_OUT msgresponse */ 5682 #define MC_CMD_WOL_FILTER_SET_OUT_LEN 4 5683 #define MC_CMD_WOL_FILTER_SET_OUT_FILTER_ID_OFST 0 5684 5685 5686 /***********************************/ 5687 /* MC_CMD_WOL_FILTER_REMOVE 5688 * Remove a WoL filter. Locks required: None. Returns: 0, EINVAL, ENOSYS 5689 */ 5690 #define MC_CMD_WOL_FILTER_REMOVE 0x33 5691 #undef MC_CMD_0x33_PRIVILEGE_CTG 5692 5693 #define MC_CMD_0x33_PRIVILEGE_CTG SRIOV_CTG_LINK 5694 5695 /* MC_CMD_WOL_FILTER_REMOVE_IN msgrequest */ 5696 #define MC_CMD_WOL_FILTER_REMOVE_IN_LEN 4 5697 #define MC_CMD_WOL_FILTER_REMOVE_IN_FILTER_ID_OFST 0 5698 5699 /* MC_CMD_WOL_FILTER_REMOVE_OUT msgresponse */ 5700 #define MC_CMD_WOL_FILTER_REMOVE_OUT_LEN 0 5701 5702 5703 /***********************************/ 5704 /* MC_CMD_WOL_FILTER_RESET 5705 * Reset (i.e. remove all) WoL filters. Locks required: None. Returns: 0, 5706 * ENOSYS 5707 */ 5708 #define MC_CMD_WOL_FILTER_RESET 0x34 5709 #undef MC_CMD_0x34_PRIVILEGE_CTG 5710 5711 #define MC_CMD_0x34_PRIVILEGE_CTG SRIOV_CTG_LINK 5712 5713 /* MC_CMD_WOL_FILTER_RESET_IN msgrequest */ 5714 #define MC_CMD_WOL_FILTER_RESET_IN_LEN 4 5715 #define MC_CMD_WOL_FILTER_RESET_IN_MASK_OFST 0 5716 #define MC_CMD_WOL_FILTER_RESET_IN_WAKE_FILTERS 0x1 /* enum */ 5717 #define MC_CMD_WOL_FILTER_RESET_IN_LIGHTSOUT_OFFLOADS 0x2 /* enum */ 5718 5719 /* MC_CMD_WOL_FILTER_RESET_OUT msgresponse */ 5720 #define MC_CMD_WOL_FILTER_RESET_OUT_LEN 0 5721 5722 5723 /***********************************/ 5724 /* MC_CMD_SET_MCAST_HASH 5725 * Set the MCAST hash value without otherwise reconfiguring the MAC 5726 */ 5727 #define MC_CMD_SET_MCAST_HASH 0x35 5728 5729 /* MC_CMD_SET_MCAST_HASH_IN msgrequest */ 5730 #define MC_CMD_SET_MCAST_HASH_IN_LEN 32 5731 #define MC_CMD_SET_MCAST_HASH_IN_HASH0_OFST 0 5732 #define MC_CMD_SET_MCAST_HASH_IN_HASH0_LEN 16 5733 #define MC_CMD_SET_MCAST_HASH_IN_HASH1_OFST 16 5734 #define MC_CMD_SET_MCAST_HASH_IN_HASH1_LEN 16 5735 5736 /* MC_CMD_SET_MCAST_HASH_OUT msgresponse */ 5737 #define MC_CMD_SET_MCAST_HASH_OUT_LEN 0 5738 5739 5740 /***********************************/ 5741 /* MC_CMD_NVRAM_TYPES 5742 * Return bitfield indicating available types of virtual NVRAM partitions. 5743 * Locks required: none. Returns: 0 5744 */ 5745 #define MC_CMD_NVRAM_TYPES 0x36 5746 #undef MC_CMD_0x36_PRIVILEGE_CTG 5747 5748 #define MC_CMD_0x36_PRIVILEGE_CTG SRIOV_CTG_ADMIN 5749 5750 /* MC_CMD_NVRAM_TYPES_IN msgrequest */ 5751 #define MC_CMD_NVRAM_TYPES_IN_LEN 0 5752 5753 /* MC_CMD_NVRAM_TYPES_OUT msgresponse */ 5754 #define MC_CMD_NVRAM_TYPES_OUT_LEN 4 5755 /* Bit mask of supported types. */ 5756 #define MC_CMD_NVRAM_TYPES_OUT_TYPES_OFST 0 5757 /* enum: Disabled callisto. */ 5758 #define MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO 0x0 5759 /* enum: MC firmware. */ 5760 #define MC_CMD_NVRAM_TYPE_MC_FW 0x1 5761 /* enum: MC backup firmware. */ 5762 #define MC_CMD_NVRAM_TYPE_MC_FW_BACKUP 0x2 5763 /* enum: Static configuration Port0. */ 5764 #define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0 0x3 5765 /* enum: Static configuration Port1. */ 5766 #define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1 0x4 5767 /* enum: Dynamic configuration Port0. */ 5768 #define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0 0x5 5769 /* enum: Dynamic configuration Port1. */ 5770 #define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1 0x6 5771 /* enum: Expansion Rom. */ 5772 #define MC_CMD_NVRAM_TYPE_EXP_ROM 0x7 5773 /* enum: Expansion Rom Configuration Port0. */ 5774 #define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0 0x8 5775 /* enum: Expansion Rom Configuration Port1. */ 5776 #define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1 0x9 5777 /* enum: Phy Configuration Port0. */ 5778 #define MC_CMD_NVRAM_TYPE_PHY_PORT0 0xa 5779 /* enum: Phy Configuration Port1. */ 5780 #define MC_CMD_NVRAM_TYPE_PHY_PORT1 0xb 5781 /* enum: Log. */ 5782 #define MC_CMD_NVRAM_TYPE_LOG 0xc 5783 /* enum: FPGA image. */ 5784 #define MC_CMD_NVRAM_TYPE_FPGA 0xd 5785 /* enum: FPGA backup image */ 5786 #define MC_CMD_NVRAM_TYPE_FPGA_BACKUP 0xe 5787 /* enum: FC firmware. */ 5788 #define MC_CMD_NVRAM_TYPE_FC_FW 0xf 5789 /* enum: FC backup firmware. */ 5790 #define MC_CMD_NVRAM_TYPE_FC_FW_BACKUP 0x10 5791 /* enum: CPLD image. */ 5792 #define MC_CMD_NVRAM_TYPE_CPLD 0x11 5793 /* enum: Licensing information. */ 5794 #define MC_CMD_NVRAM_TYPE_LICENSE 0x12 5795 /* enum: FC Log. */ 5796 #define MC_CMD_NVRAM_TYPE_FC_LOG 0x13 5797 /* enum: Additional flash on FPGA. */ 5798 #define MC_CMD_NVRAM_TYPE_FC_EXTRA 0x14 5799 5800 5801 /***********************************/ 5802 /* MC_CMD_NVRAM_INFO 5803 * Read info about a virtual NVRAM partition. Locks required: none. Returns: 0, 5804 * EINVAL (bad type). 5805 */ 5806 #define MC_CMD_NVRAM_INFO 0x37 5807 #undef MC_CMD_0x37_PRIVILEGE_CTG 5808 5809 #define MC_CMD_0x37_PRIVILEGE_CTG SRIOV_CTG_ADMIN 5810 5811 /* MC_CMD_NVRAM_INFO_IN msgrequest */ 5812 #define MC_CMD_NVRAM_INFO_IN_LEN 4 5813 #define MC_CMD_NVRAM_INFO_IN_TYPE_OFST 0 5814 /* Enum values, see field(s): */ 5815 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 5816 5817 /* MC_CMD_NVRAM_INFO_OUT msgresponse */ 5818 #define MC_CMD_NVRAM_INFO_OUT_LEN 24 5819 #define MC_CMD_NVRAM_INFO_OUT_TYPE_OFST 0 5820 /* Enum values, see field(s): */ 5821 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 5822 #define MC_CMD_NVRAM_INFO_OUT_SIZE_OFST 4 5823 #define MC_CMD_NVRAM_INFO_OUT_ERASESIZE_OFST 8 5824 #define MC_CMD_NVRAM_INFO_OUT_FLAGS_OFST 12 5825 #define MC_CMD_NVRAM_INFO_OUT_PROTECTED_LBN 0 5826 #define MC_CMD_NVRAM_INFO_OUT_PROTECTED_WIDTH 1 5827 #define MC_CMD_NVRAM_INFO_OUT_TLV_LBN 1 5828 #define MC_CMD_NVRAM_INFO_OUT_TLV_WIDTH 1 5829 #define MC_CMD_NVRAM_INFO_OUT_A_B_LBN 7 5830 #define MC_CMD_NVRAM_INFO_OUT_A_B_WIDTH 1 5831 #define MC_CMD_NVRAM_INFO_OUT_PHYSDEV_OFST 16 5832 #define MC_CMD_NVRAM_INFO_OUT_PHYSADDR_OFST 20 5833 5834 5835 /***********************************/ 5836 /* MC_CMD_NVRAM_UPDATE_START 5837 * Start a group of update operations on a virtual NVRAM partition. Locks 5838 * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad type), EACCES (if 5839 * PHY_LOCK required and not held). 5840 */ 5841 #define MC_CMD_NVRAM_UPDATE_START 0x38 5842 #undef MC_CMD_0x38_PRIVILEGE_CTG 5843 5844 #define MC_CMD_0x38_PRIVILEGE_CTG SRIOV_CTG_ADMIN 5845 5846 /* MC_CMD_NVRAM_UPDATE_START_IN msgrequest */ 5847 #define MC_CMD_NVRAM_UPDATE_START_IN_LEN 4 5848 #define MC_CMD_NVRAM_UPDATE_START_IN_TYPE_OFST 0 5849 /* Enum values, see field(s): */ 5850 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 5851 5852 /* MC_CMD_NVRAM_UPDATE_START_OUT msgresponse */ 5853 #define MC_CMD_NVRAM_UPDATE_START_OUT_LEN 0 5854 5855 5856 /***********************************/ 5857 /* MC_CMD_NVRAM_READ 5858 * Read data from a virtual NVRAM partition. Locks required: PHY_LOCK if 5859 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if 5860 * PHY_LOCK required and not held) 5861 */ 5862 #define MC_CMD_NVRAM_READ 0x39 5863 #undef MC_CMD_0x39_PRIVILEGE_CTG 5864 5865 #define MC_CMD_0x39_PRIVILEGE_CTG SRIOV_CTG_ADMIN 5866 5867 /* MC_CMD_NVRAM_READ_IN msgrequest */ 5868 #define MC_CMD_NVRAM_READ_IN_LEN 12 5869 #define MC_CMD_NVRAM_READ_IN_TYPE_OFST 0 5870 /* Enum values, see field(s): */ 5871 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 5872 #define MC_CMD_NVRAM_READ_IN_OFFSET_OFST 4 5873 /* amount to read in bytes */ 5874 #define MC_CMD_NVRAM_READ_IN_LENGTH_OFST 8 5875 5876 /* MC_CMD_NVRAM_READ_OUT msgresponse */ 5877 #define MC_CMD_NVRAM_READ_OUT_LENMIN 1 5878 #define MC_CMD_NVRAM_READ_OUT_LENMAX 252 5879 #define MC_CMD_NVRAM_READ_OUT_LEN(num) (0+1*(num)) 5880 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_OFST 0 5881 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_LEN 1 5882 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MINNUM 1 5883 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MAXNUM 252 5884 5885 5886 /***********************************/ 5887 /* MC_CMD_NVRAM_WRITE 5888 * Write data to a virtual NVRAM partition. Locks required: PHY_LOCK if 5889 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if 5890 * PHY_LOCK required and not held) 5891 */ 5892 #define MC_CMD_NVRAM_WRITE 0x3a 5893 #undef MC_CMD_0x3a_PRIVILEGE_CTG 5894 5895 #define MC_CMD_0x3a_PRIVILEGE_CTG SRIOV_CTG_ADMIN 5896 5897 /* MC_CMD_NVRAM_WRITE_IN msgrequest */ 5898 #define MC_CMD_NVRAM_WRITE_IN_LENMIN 13 5899 #define MC_CMD_NVRAM_WRITE_IN_LENMAX 252 5900 #define MC_CMD_NVRAM_WRITE_IN_LEN(num) (12+1*(num)) 5901 #define MC_CMD_NVRAM_WRITE_IN_TYPE_OFST 0 5902 /* Enum values, see field(s): */ 5903 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 5904 #define MC_CMD_NVRAM_WRITE_IN_OFFSET_OFST 4 5905 #define MC_CMD_NVRAM_WRITE_IN_LENGTH_OFST 8 5906 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_OFST 12 5907 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_LEN 1 5908 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MINNUM 1 5909 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MAXNUM 240 5910 5911 /* MC_CMD_NVRAM_WRITE_OUT msgresponse */ 5912 #define MC_CMD_NVRAM_WRITE_OUT_LEN 0 5913 5914 5915 /***********************************/ 5916 /* MC_CMD_NVRAM_ERASE 5917 * Erase sector(s) from a virtual NVRAM partition. Locks required: PHY_LOCK if 5918 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if 5919 * PHY_LOCK required and not held) 5920 */ 5921 #define MC_CMD_NVRAM_ERASE 0x3b 5922 #undef MC_CMD_0x3b_PRIVILEGE_CTG 5923 5924 #define MC_CMD_0x3b_PRIVILEGE_CTG SRIOV_CTG_ADMIN 5925 5926 /* MC_CMD_NVRAM_ERASE_IN msgrequest */ 5927 #define MC_CMD_NVRAM_ERASE_IN_LEN 12 5928 #define MC_CMD_NVRAM_ERASE_IN_TYPE_OFST 0 5929 /* Enum values, see field(s): */ 5930 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 5931 #define MC_CMD_NVRAM_ERASE_IN_OFFSET_OFST 4 5932 #define MC_CMD_NVRAM_ERASE_IN_LENGTH_OFST 8 5933 5934 /* MC_CMD_NVRAM_ERASE_OUT msgresponse */ 5935 #define MC_CMD_NVRAM_ERASE_OUT_LEN 0 5936 5937 5938 /***********************************/ 5939 /* MC_CMD_NVRAM_UPDATE_FINISH 5940 * Finish a group of update operations on a virtual NVRAM partition. Locks 5941 * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad 5942 * type/offset/length), EACCES (if PHY_LOCK required and not held) 5943 */ 5944 #define MC_CMD_NVRAM_UPDATE_FINISH 0x3c 5945 #undef MC_CMD_0x3c_PRIVILEGE_CTG 5946 5947 #define MC_CMD_0x3c_PRIVILEGE_CTG SRIOV_CTG_ADMIN 5948 5949 /* MC_CMD_NVRAM_UPDATE_FINISH_IN msgrequest */ 5950 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_LEN 8 5951 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_TYPE_OFST 0 5952 /* Enum values, see field(s): */ 5953 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 5954 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_REBOOT_OFST 4 5955 5956 /* MC_CMD_NVRAM_UPDATE_FINISH_OUT msgresponse */ 5957 #define MC_CMD_NVRAM_UPDATE_FINISH_OUT_LEN 0 5958 5959 5960 /***********************************/ 5961 /* MC_CMD_REBOOT 5962 * Reboot the MC. 5963 * 5964 * The AFTER_ASSERTION flag is intended to be used when the driver notices an 5965 * assertion failure (at which point it is expected to perform a complete tear 5966 * down and reinitialise), to allow both ports to reset the MC once in an 5967 * atomic fashion. 5968 * 5969 * Production mc firmwares are generally compiled with REBOOT_ON_ASSERT=1, 5970 * which means that they will automatically reboot out of the assertion 5971 * handler, so this is in practise an optional operation. It is still 5972 * recommended that drivers execute this to support custom firmwares with 5973 * REBOOT_ON_ASSERT=0. 5974 * 5975 * Locks required: NONE Returns: Nothing. You get back a response with ERR=1, 5976 * DATALEN=0 5977 */ 5978 #define MC_CMD_REBOOT 0x3d 5979 #undef MC_CMD_0x3d_PRIVILEGE_CTG 5980 5981 #define MC_CMD_0x3d_PRIVILEGE_CTG SRIOV_CTG_ADMIN 5982 5983 /* MC_CMD_REBOOT_IN msgrequest */ 5984 #define MC_CMD_REBOOT_IN_LEN 4 5985 #define MC_CMD_REBOOT_IN_FLAGS_OFST 0 5986 #define MC_CMD_REBOOT_FLAGS_AFTER_ASSERTION 0x1 /* enum */ 5987 5988 /* MC_CMD_REBOOT_OUT msgresponse */ 5989 #define MC_CMD_REBOOT_OUT_LEN 0 5990 5991 5992 /***********************************/ 5993 /* MC_CMD_SCHEDINFO 5994 * Request scheduler info. Locks required: NONE. Returns: An array of 5995 * (timeslice,maximum overrun), one for each thread, in ascending order of 5996 * thread address. 5997 */ 5998 #define MC_CMD_SCHEDINFO 0x3e 5999 #undef MC_CMD_0x3e_PRIVILEGE_CTG 6000 6001 #define MC_CMD_0x3e_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6002 6003 /* MC_CMD_SCHEDINFO_IN msgrequest */ 6004 #define MC_CMD_SCHEDINFO_IN_LEN 0 6005 6006 /* MC_CMD_SCHEDINFO_OUT msgresponse */ 6007 #define MC_CMD_SCHEDINFO_OUT_LENMIN 4 6008 #define MC_CMD_SCHEDINFO_OUT_LENMAX 252 6009 #define MC_CMD_SCHEDINFO_OUT_LEN(num) (0+4*(num)) 6010 #define MC_CMD_SCHEDINFO_OUT_DATA_OFST 0 6011 #define MC_CMD_SCHEDINFO_OUT_DATA_LEN 4 6012 #define MC_CMD_SCHEDINFO_OUT_DATA_MINNUM 1 6013 #define MC_CMD_SCHEDINFO_OUT_DATA_MAXNUM 63 6014 6015 6016 /***********************************/ 6017 /* MC_CMD_REBOOT_MODE 6018 * Set the mode for the next MC reboot. Locks required: NONE. Sets the reboot 6019 * mode to the specified value. Returns the old mode. 6020 */ 6021 #define MC_CMD_REBOOT_MODE 0x3f 6022 #undef MC_CMD_0x3f_PRIVILEGE_CTG 6023 6024 #define MC_CMD_0x3f_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6025 6026 /* MC_CMD_REBOOT_MODE_IN msgrequest */ 6027 #define MC_CMD_REBOOT_MODE_IN_LEN 4 6028 #define MC_CMD_REBOOT_MODE_IN_VALUE_OFST 0 6029 /* enum: Normal. */ 6030 #define MC_CMD_REBOOT_MODE_NORMAL 0x0 6031 /* enum: Power-on Reset. */ 6032 #define MC_CMD_REBOOT_MODE_POR 0x2 6033 /* enum: Snapper. */ 6034 #define MC_CMD_REBOOT_MODE_SNAPPER 0x3 6035 /* enum: snapper fake POR */ 6036 #define MC_CMD_REBOOT_MODE_SNAPPER_POR 0x4 6037 #define MC_CMD_REBOOT_MODE_IN_FAKE_LBN 7 6038 #define MC_CMD_REBOOT_MODE_IN_FAKE_WIDTH 1 6039 6040 /* MC_CMD_REBOOT_MODE_OUT msgresponse */ 6041 #define MC_CMD_REBOOT_MODE_OUT_LEN 4 6042 #define MC_CMD_REBOOT_MODE_OUT_VALUE_OFST 0 6043 6044 6045 /***********************************/ 6046 /* MC_CMD_SENSOR_INFO 6047 * Returns information about every available sensor. 6048 * 6049 * Each sensor has a single (16bit) value, and a corresponding state. The 6050 * mapping between value and state is nominally determined by the MC, but may 6051 * be implemented using up to 2 ranges per sensor. 6052 * 6053 * This call returns a mask (32bit) of the sensors that are supported by this 6054 * platform, then an array of sensor information structures, in order of sensor 6055 * type (but without gaps for unimplemented sensors). Each structure defines 6056 * the ranges for the corresponding sensor. An unused range is indicated by 6057 * equal limit values. If one range is used, a value outside that range results 6058 * in STATE_FATAL. If two ranges are used, a value outside the second range 6059 * results in STATE_FATAL while a value outside the first and inside the second 6060 * range results in STATE_WARNING. 6061 * 6062 * Sensor masks and sensor information arrays are organised into pages. For 6063 * backward compatibility, older host software can only use sensors in page 0. 6064 * Bit 32 in the sensor mask was previously unused, and is no reserved for use 6065 * as the next page flag. 6066 * 6067 * If the request does not contain a PAGE value then firmware will only return 6068 * page 0 of sensor information, with bit 31 in the sensor mask cleared. 6069 * 6070 * If the request contains a PAGE value then firmware responds with the sensor 6071 * mask and sensor information array for that page of sensors. In this case bit 6072 * 31 in the mask is set if another page exists. 6073 * 6074 * Locks required: None Returns: 0 6075 */ 6076 #define MC_CMD_SENSOR_INFO 0x41 6077 #undef MC_CMD_0x41_PRIVILEGE_CTG 6078 6079 #define MC_CMD_0x41_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6080 6081 /* MC_CMD_SENSOR_INFO_IN msgrequest */ 6082 #define MC_CMD_SENSOR_INFO_IN_LEN 0 6083 6084 /* MC_CMD_SENSOR_INFO_EXT_IN msgrequest */ 6085 #define MC_CMD_SENSOR_INFO_EXT_IN_LEN 4 6086 /* Which page of sensors to report. 6087 * 6088 * Page 0 contains sensors 0 to 30 (sensor 31 is the next page bit). 6089 * 6090 * Page 1 contains sensors 32 to 62 (sensor 63 is the next page bit). etc. 6091 */ 6092 #define MC_CMD_SENSOR_INFO_EXT_IN_PAGE_OFST 0 6093 6094 /* MC_CMD_SENSOR_INFO_OUT msgresponse */ 6095 #define MC_CMD_SENSOR_INFO_OUT_LENMIN 4 6096 #define MC_CMD_SENSOR_INFO_OUT_LENMAX 252 6097 #define MC_CMD_SENSOR_INFO_OUT_LEN(num) (4+8*(num)) 6098 #define MC_CMD_SENSOR_INFO_OUT_MASK_OFST 0 6099 /* enum: Controller temperature: degC */ 6100 #define MC_CMD_SENSOR_CONTROLLER_TEMP 0x0 6101 /* enum: Phy common temperature: degC */ 6102 #define MC_CMD_SENSOR_PHY_COMMON_TEMP 0x1 6103 /* enum: Controller cooling: bool */ 6104 #define MC_CMD_SENSOR_CONTROLLER_COOLING 0x2 6105 /* enum: Phy 0 temperature: degC */ 6106 #define MC_CMD_SENSOR_PHY0_TEMP 0x3 6107 /* enum: Phy 0 cooling: bool */ 6108 #define MC_CMD_SENSOR_PHY0_COOLING 0x4 6109 /* enum: Phy 1 temperature: degC */ 6110 #define MC_CMD_SENSOR_PHY1_TEMP 0x5 6111 /* enum: Phy 1 cooling: bool */ 6112 #define MC_CMD_SENSOR_PHY1_COOLING 0x6 6113 /* enum: 1.0v power: mV */ 6114 #define MC_CMD_SENSOR_IN_1V0 0x7 6115 /* enum: 1.2v power: mV */ 6116 #define MC_CMD_SENSOR_IN_1V2 0x8 6117 /* enum: 1.8v power: mV */ 6118 #define MC_CMD_SENSOR_IN_1V8 0x9 6119 /* enum: 2.5v power: mV */ 6120 #define MC_CMD_SENSOR_IN_2V5 0xa 6121 /* enum: 3.3v power: mV */ 6122 #define MC_CMD_SENSOR_IN_3V3 0xb 6123 /* enum: 12v power: mV */ 6124 #define MC_CMD_SENSOR_IN_12V0 0xc 6125 /* enum: 1.2v analogue power: mV */ 6126 #define MC_CMD_SENSOR_IN_1V2A 0xd 6127 /* enum: reference voltage: mV */ 6128 #define MC_CMD_SENSOR_IN_VREF 0xe 6129 /* enum: AOE FPGA power: mV */ 6130 #define MC_CMD_SENSOR_OUT_VAOE 0xf 6131 /* enum: AOE FPGA temperature: degC */ 6132 #define MC_CMD_SENSOR_AOE_TEMP 0x10 6133 /* enum: AOE FPGA PSU temperature: degC */ 6134 #define MC_CMD_SENSOR_PSU_AOE_TEMP 0x11 6135 /* enum: AOE PSU temperature: degC */ 6136 #define MC_CMD_SENSOR_PSU_TEMP 0x12 6137 /* enum: Fan 0 speed: RPM */ 6138 #define MC_CMD_SENSOR_FAN_0 0x13 6139 /* enum: Fan 1 speed: RPM */ 6140 #define MC_CMD_SENSOR_FAN_1 0x14 6141 /* enum: Fan 2 speed: RPM */ 6142 #define MC_CMD_SENSOR_FAN_2 0x15 6143 /* enum: Fan 3 speed: RPM */ 6144 #define MC_CMD_SENSOR_FAN_3 0x16 6145 /* enum: Fan 4 speed: RPM */ 6146 #define MC_CMD_SENSOR_FAN_4 0x17 6147 /* enum: AOE FPGA input power: mV */ 6148 #define MC_CMD_SENSOR_IN_VAOE 0x18 6149 /* enum: AOE FPGA current: mA */ 6150 #define MC_CMD_SENSOR_OUT_IAOE 0x19 6151 /* enum: AOE FPGA input current: mA */ 6152 #define MC_CMD_SENSOR_IN_IAOE 0x1a 6153 /* enum: NIC power consumption: W */ 6154 #define MC_CMD_SENSOR_NIC_POWER 0x1b 6155 /* enum: 0.9v power voltage: mV */ 6156 #define MC_CMD_SENSOR_IN_0V9 0x1c 6157 /* enum: 0.9v power current: mA */ 6158 #define MC_CMD_SENSOR_IN_I0V9 0x1d 6159 /* enum: 1.2v power current: mA */ 6160 #define MC_CMD_SENSOR_IN_I1V2 0x1e 6161 /* enum: Not a sensor: reserved for the next page flag */ 6162 #define MC_CMD_SENSOR_PAGE0_NEXT 0x1f 6163 /* enum: 0.9v power voltage (at ADC): mV */ 6164 #define MC_CMD_SENSOR_IN_0V9_ADC 0x20 6165 /* enum: Controller temperature 2: degC */ 6166 #define MC_CMD_SENSOR_CONTROLLER_2_TEMP 0x21 6167 /* enum: Voltage regulator internal temperature: degC */ 6168 #define MC_CMD_SENSOR_VREG_INTERNAL_TEMP 0x22 6169 /* enum: 0.9V voltage regulator temperature: degC */ 6170 #define MC_CMD_SENSOR_VREG_0V9_TEMP 0x23 6171 /* enum: 1.2V voltage regulator temperature: degC */ 6172 #define MC_CMD_SENSOR_VREG_1V2_TEMP 0x24 6173 /* enum: controller internal temperature sensor voltage (internal ADC): mV */ 6174 #define MC_CMD_SENSOR_CONTROLLER_VPTAT 0x25 6175 /* enum: controller internal temperature (internal ADC): degC */ 6176 #define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP 0x26 6177 /* enum: controller internal temperature sensor voltage (external ADC): mV */ 6178 #define MC_CMD_SENSOR_CONTROLLER_VPTAT_EXTADC 0x27 6179 /* enum: controller internal temperature (external ADC): degC */ 6180 #define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP_EXTADC 0x28 6181 /* enum: ambient temperature: degC */ 6182 #define MC_CMD_SENSOR_AMBIENT_TEMP 0x29 6183 /* enum: air flow: bool */ 6184 #define MC_CMD_SENSOR_AIRFLOW 0x2a 6185 /* enum: voltage between VSS08D and VSS08D at CSR: mV */ 6186 #define MC_CMD_SENSOR_VDD08D_VSS08D_CSR 0x2b 6187 /* enum: voltage between VSS08D and VSS08D at CSR (external ADC): mV */ 6188 #define MC_CMD_SENSOR_VDD08D_VSS08D_CSR_EXTADC 0x2c 6189 /* enum: Hotpoint temperature: degC */ 6190 #define MC_CMD_SENSOR_HOTPOINT_TEMP 0x2d 6191 /* enum: Port 0 PHY power switch over-current: bool */ 6192 #define MC_CMD_SENSOR_PHY_POWER_PORT0 0x2e 6193 /* enum: Port 1 PHY power switch over-current: bool */ 6194 #define MC_CMD_SENSOR_PHY_POWER_PORT1 0x2f 6195 /* enum: Mop-up microcontroller reference voltage (millivolts) */ 6196 #define MC_CMD_SENSOR_MUM_VCC 0x30 6197 /* enum: 0.9v power phase A voltage: mV */ 6198 #define MC_CMD_SENSOR_IN_0V9_A 0x31 6199 /* enum: 0.9v power phase A current: mA */ 6200 #define MC_CMD_SENSOR_IN_I0V9_A 0x32 6201 /* enum: 0.9V voltage regulator phase A temperature: degC */ 6202 #define MC_CMD_SENSOR_VREG_0V9_A_TEMP 0x33 6203 /* enum: 0.9v power phase B voltage: mV */ 6204 #define MC_CMD_SENSOR_IN_0V9_B 0x34 6205 /* enum: 0.9v power phase B current: mA */ 6206 #define MC_CMD_SENSOR_IN_I0V9_B 0x35 6207 /* enum: 0.9V voltage regulator phase B temperature: degC */ 6208 #define MC_CMD_SENSOR_VREG_0V9_B_TEMP 0x36 6209 /* enum: CCOM AVREG 1v2 supply (interval ADC): mV */ 6210 #define MC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY 0x37 6211 /* enum: CCOM AVREG 1v2 supply (external ADC): mV */ 6212 #define MC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY_EXTADC 0x38 6213 /* enum: CCOM AVREG 1v8 supply (interval ADC): mV */ 6214 #define MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY 0x39 6215 /* enum: CCOM AVREG 1v8 supply (external ADC): mV */ 6216 #define MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY_EXTADC 0x3a 6217 /* enum: Not a sensor: reserved for the next page flag */ 6218 #define MC_CMD_SENSOR_PAGE1_NEXT 0x3f 6219 /* enum: controller internal temperature sensor voltage on master core 6220 * (internal ADC): mV 6221 */ 6222 #define MC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT 0x40 6223 /* enum: controller internal temperature on master core (internal ADC): degC */ 6224 #define MC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP 0x41 6225 /* enum: controller internal temperature sensor voltage on master core 6226 * (external ADC): mV 6227 */ 6228 #define MC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT_EXTADC 0x42 6229 /* enum: controller internal temperature on master core (external ADC): degC */ 6230 #define MC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC 0x43 6231 /* enum: controller internal temperature on slave core sensor voltage (internal 6232 * ADC): mV 6233 */ 6234 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT 0x44 6235 /* enum: controller internal temperature on slave core (internal ADC): degC */ 6236 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP 0x45 6237 /* enum: controller internal temperature on slave core sensor voltage (external 6238 * ADC): mV 6239 */ 6240 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT_EXTADC 0x46 6241 /* enum: controller internal temperature on slave core (external ADC): degC */ 6242 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC 0x47 6243 /* enum: Voltage supplied to the SODIMMs from their power supply: mV */ 6244 #define MC_CMD_SENSOR_SODIMM_VOUT 0x49 6245 /* enum: Temperature of SODIMM 0 (if installed): degC */ 6246 #define MC_CMD_SENSOR_SODIMM_0_TEMP 0x4a 6247 /* enum: Temperature of SODIMM 1 (if installed): degC */ 6248 #define MC_CMD_SENSOR_SODIMM_1_TEMP 0x4b 6249 /* enum: Voltage supplied to the QSFP #0 from their power supply: mV */ 6250 #define MC_CMD_SENSOR_PHY0_VCC 0x4c 6251 /* enum: Voltage supplied to the QSFP #1 from their power supply: mV */ 6252 #define MC_CMD_SENSOR_PHY1_VCC 0x4d 6253 /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */ 6254 #define MC_CMD_SENSOR_ENTRY_OFST 4 6255 #define MC_CMD_SENSOR_ENTRY_LEN 8 6256 #define MC_CMD_SENSOR_ENTRY_LO_OFST 4 6257 #define MC_CMD_SENSOR_ENTRY_HI_OFST 8 6258 #define MC_CMD_SENSOR_ENTRY_MINNUM 0 6259 #define MC_CMD_SENSOR_ENTRY_MAXNUM 31 6260 6261 /* MC_CMD_SENSOR_INFO_EXT_OUT msgresponse */ 6262 #define MC_CMD_SENSOR_INFO_EXT_OUT_LENMIN 4 6263 #define MC_CMD_SENSOR_INFO_EXT_OUT_LENMAX 252 6264 #define MC_CMD_SENSOR_INFO_EXT_OUT_LEN(num) (4+8*(num)) 6265 #define MC_CMD_SENSOR_INFO_EXT_OUT_MASK_OFST 0 6266 /* Enum values, see field(s): */ 6267 /* MC_CMD_SENSOR_INFO_OUT */ 6268 #define MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_LBN 31 6269 #define MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_WIDTH 1 6270 /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */ 6271 /* MC_CMD_SENSOR_ENTRY_OFST 4 */ 6272 /* MC_CMD_SENSOR_ENTRY_LEN 8 */ 6273 /* MC_CMD_SENSOR_ENTRY_LO_OFST 4 */ 6274 /* MC_CMD_SENSOR_ENTRY_HI_OFST 8 */ 6275 /* MC_CMD_SENSOR_ENTRY_MINNUM 0 */ 6276 /* MC_CMD_SENSOR_ENTRY_MAXNUM 31 */ 6277 6278 /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF structuredef */ 6279 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_LEN 8 6280 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_OFST 0 6281 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LEN 2 6282 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LBN 0 6283 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_WIDTH 16 6284 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_OFST 2 6285 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LEN 2 6286 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LBN 16 6287 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_WIDTH 16 6288 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_OFST 4 6289 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LEN 2 6290 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LBN 32 6291 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_WIDTH 16 6292 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_OFST 6 6293 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LEN 2 6294 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LBN 48 6295 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_WIDTH 16 6296 6297 6298 /***********************************/ 6299 /* MC_CMD_READ_SENSORS 6300 * Returns the current reading from each sensor. DMAs an array of sensor 6301 * readings, in order of sensor type (but without gaps for unimplemented 6302 * sensors), into host memory. Each array element is a 6303 * MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF dword. 6304 * 6305 * If the request does not contain the LENGTH field then only sensors 0 to 30 6306 * are reported, to avoid DMA buffer overflow in older host software. If the 6307 * sensor reading require more space than the LENGTH allows, then return 6308 * EINVAL. 6309 * 6310 * The MC will send a SENSOREVT event every time any sensor changes state. The 6311 * driver is responsible for ensuring that it doesn't miss any events. The 6312 * board will function normally if all sensors are in STATE_OK or 6313 * STATE_WARNING. Otherwise the board should not be expected to function. 6314 */ 6315 #define MC_CMD_READ_SENSORS 0x42 6316 #undef MC_CMD_0x42_PRIVILEGE_CTG 6317 6318 #define MC_CMD_0x42_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6319 6320 /* MC_CMD_READ_SENSORS_IN msgrequest */ 6321 #define MC_CMD_READ_SENSORS_IN_LEN 8 6322 /* DMA address of host buffer for sensor readings (must be 4Kbyte aligned). */ 6323 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_OFST 0 6324 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LEN 8 6325 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_OFST 0 6326 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_OFST 4 6327 6328 /* MC_CMD_READ_SENSORS_EXT_IN msgrequest */ 6329 #define MC_CMD_READ_SENSORS_EXT_IN_LEN 12 6330 /* DMA address of host buffer for sensor readings */ 6331 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_OFST 0 6332 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LEN 8 6333 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_OFST 0 6334 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_HI_OFST 4 6335 /* Size in bytes of host buffer. */ 6336 #define MC_CMD_READ_SENSORS_EXT_IN_LENGTH_OFST 8 6337 6338 /* MC_CMD_READ_SENSORS_OUT msgresponse */ 6339 #define MC_CMD_READ_SENSORS_OUT_LEN 0 6340 6341 /* MC_CMD_READ_SENSORS_EXT_OUT msgresponse */ 6342 #define MC_CMD_READ_SENSORS_EXT_OUT_LEN 0 6343 6344 /* MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF structuredef */ 6345 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_LEN 4 6346 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_OFST 0 6347 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LEN 2 6348 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LBN 0 6349 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_WIDTH 16 6350 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_OFST 2 6351 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LEN 1 6352 /* enum: Ok. */ 6353 #define MC_CMD_SENSOR_STATE_OK 0x0 6354 /* enum: Breached warning threshold. */ 6355 #define MC_CMD_SENSOR_STATE_WARNING 0x1 6356 /* enum: Breached fatal threshold. */ 6357 #define MC_CMD_SENSOR_STATE_FATAL 0x2 6358 /* enum: Fault with sensor. */ 6359 #define MC_CMD_SENSOR_STATE_BROKEN 0x3 6360 /* enum: Sensor is working but does not currently have a reading. */ 6361 #define MC_CMD_SENSOR_STATE_NO_READING 0x4 6362 /* enum: Sensor initialisation failed. */ 6363 #define MC_CMD_SENSOR_STATE_INIT_FAILED 0x5 6364 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LBN 16 6365 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_WIDTH 8 6366 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_OFST 3 6367 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_LEN 1 6368 /* Enum values, see field(s): */ 6369 /* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */ 6370 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_LBN 24 6371 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_WIDTH 8 6372 6373 6374 /***********************************/ 6375 /* MC_CMD_GET_PHY_STATE 6376 * Report current state of PHY. A 'zombie' PHY is a PHY that has failed to boot 6377 * (e.g. due to missing or corrupted firmware). Locks required: None. Return 6378 * code: 0 6379 */ 6380 #define MC_CMD_GET_PHY_STATE 0x43 6381 #undef MC_CMD_0x43_PRIVILEGE_CTG 6382 6383 #define MC_CMD_0x43_PRIVILEGE_CTG SRIOV_CTG_GENERAL 6384 6385 /* MC_CMD_GET_PHY_STATE_IN msgrequest */ 6386 #define MC_CMD_GET_PHY_STATE_IN_LEN 0 6387 6388 /* MC_CMD_GET_PHY_STATE_OUT msgresponse */ 6389 #define MC_CMD_GET_PHY_STATE_OUT_LEN 4 6390 #define MC_CMD_GET_PHY_STATE_OUT_STATE_OFST 0 6391 /* enum: Ok. */ 6392 #define MC_CMD_PHY_STATE_OK 0x1 6393 /* enum: Faulty. */ 6394 #define MC_CMD_PHY_STATE_ZOMBIE 0x2 6395 6396 6397 /***********************************/ 6398 /* MC_CMD_SETUP_8021QBB 6399 * 802.1Qbb control. 8 Tx queues that map to priorities 0 - 7. Use all 1s to 6400 * disable 802.Qbb for a given priority. 6401 */ 6402 #define MC_CMD_SETUP_8021QBB 0x44 6403 6404 /* MC_CMD_SETUP_8021QBB_IN msgrequest */ 6405 #define MC_CMD_SETUP_8021QBB_IN_LEN 32 6406 #define MC_CMD_SETUP_8021QBB_IN_TXQS_OFST 0 6407 #define MC_CMD_SETUP_8021QBB_IN_TXQS_LEN 32 6408 6409 /* MC_CMD_SETUP_8021QBB_OUT msgresponse */ 6410 #define MC_CMD_SETUP_8021QBB_OUT_LEN 0 6411 6412 6413 /***********************************/ 6414 /* MC_CMD_WOL_FILTER_GET 6415 * Retrieve ID of any WoL filters. Locks required: None. Returns: 0, ENOSYS 6416 */ 6417 #define MC_CMD_WOL_FILTER_GET 0x45 6418 #undef MC_CMD_0x45_PRIVILEGE_CTG 6419 6420 #define MC_CMD_0x45_PRIVILEGE_CTG SRIOV_CTG_LINK 6421 6422 /* MC_CMD_WOL_FILTER_GET_IN msgrequest */ 6423 #define MC_CMD_WOL_FILTER_GET_IN_LEN 0 6424 6425 /* MC_CMD_WOL_FILTER_GET_OUT msgresponse */ 6426 #define MC_CMD_WOL_FILTER_GET_OUT_LEN 4 6427 #define MC_CMD_WOL_FILTER_GET_OUT_FILTER_ID_OFST 0 6428 6429 6430 /***********************************/ 6431 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD 6432 * Add a protocol offload to NIC for lights-out state. Locks required: None. 6433 * Returns: 0, ENOSYS 6434 */ 6435 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD 0x46 6436 #undef MC_CMD_0x46_PRIVILEGE_CTG 6437 6438 #define MC_CMD_0x46_PRIVILEGE_CTG SRIOV_CTG_LINK 6439 6440 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN msgrequest */ 6441 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMIN 8 6442 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMAX 252 6443 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LEN(num) (4+4*(num)) 6444 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 6445 #define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_ARP 0x1 /* enum */ 6446 #define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_NS 0x2 /* enum */ 6447 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_OFST 4 6448 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_LEN 4 6449 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MINNUM 1 6450 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MAXNUM 62 6451 6452 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP msgrequest */ 6453 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_LEN 14 6454 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */ 6455 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_OFST 4 6456 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_LEN 6 6457 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_IP_OFST 10 6458 6459 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS msgrequest */ 6460 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_LEN 42 6461 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */ 6462 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_OFST 4 6463 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_LEN 6 6464 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_OFST 10 6465 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_LEN 16 6466 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_OFST 26 6467 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_LEN 16 6468 6469 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT msgresponse */ 6470 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_LEN 4 6471 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_FILTER_ID_OFST 0 6472 6473 6474 /***********************************/ 6475 /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD 6476 * Remove a protocol offload from NIC for lights-out state. Locks required: 6477 * None. Returns: 0, ENOSYS 6478 */ 6479 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD 0x47 6480 #undef MC_CMD_0x47_PRIVILEGE_CTG 6481 6482 #define MC_CMD_0x47_PRIVILEGE_CTG SRIOV_CTG_LINK 6483 6484 /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN msgrequest */ 6485 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_LEN 8 6486 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 6487 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_FILTER_ID_OFST 4 6488 6489 /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT msgresponse */ 6490 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT_LEN 0 6491 6492 6493 /***********************************/ 6494 /* MC_CMD_MAC_RESET_RESTORE 6495 * Restore MAC after block reset. Locks required: None. Returns: 0. 6496 */ 6497 #define MC_CMD_MAC_RESET_RESTORE 0x48 6498 6499 /* MC_CMD_MAC_RESET_RESTORE_IN msgrequest */ 6500 #define MC_CMD_MAC_RESET_RESTORE_IN_LEN 0 6501 6502 /* MC_CMD_MAC_RESET_RESTORE_OUT msgresponse */ 6503 #define MC_CMD_MAC_RESET_RESTORE_OUT_LEN 0 6504 6505 6506 /***********************************/ 6507 /* MC_CMD_TESTASSERT 6508 * Deliberately trigger an assert-detonation in the firmware for testing 6509 * purposes (i.e. to allow tests that the driver copes gracefully). Locks 6510 * required: None Returns: 0 6511 */ 6512 #define MC_CMD_TESTASSERT 0x49 6513 #undef MC_CMD_0x49_PRIVILEGE_CTG 6514 6515 #define MC_CMD_0x49_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6516 6517 /* MC_CMD_TESTASSERT_IN msgrequest */ 6518 #define MC_CMD_TESTASSERT_IN_LEN 0 6519 6520 /* MC_CMD_TESTASSERT_OUT msgresponse */ 6521 #define MC_CMD_TESTASSERT_OUT_LEN 0 6522 6523 6524 /***********************************/ 6525 /* MC_CMD_WORKAROUND 6526 * Enable/Disable a given workaround. The mcfw will return EINVAL if it doesn't 6527 * understand the given workaround number - which should not be treated as a 6528 * hard error by client code. This op does not imply any semantics about each 6529 * workaround, that's between the driver and the mcfw on a per-workaround 6530 * basis. Locks required: None. Returns: 0, EINVAL . 6531 */ 6532 #define MC_CMD_WORKAROUND 0x4a 6533 #undef MC_CMD_0x4a_PRIVILEGE_CTG 6534 6535 #define MC_CMD_0x4a_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6536 6537 /* MC_CMD_WORKAROUND_IN msgrequest */ 6538 #define MC_CMD_WORKAROUND_IN_LEN 8 6539 /* The enums here must correspond with those in MC_CMD_GET_WORKAROUND. */ 6540 #define MC_CMD_WORKAROUND_IN_TYPE_OFST 0 6541 /* enum: Bug 17230 work around. */ 6542 #define MC_CMD_WORKAROUND_BUG17230 0x1 6543 /* enum: Bug 35388 work around (unsafe EVQ writes). */ 6544 #define MC_CMD_WORKAROUND_BUG35388 0x2 6545 /* enum: Bug35017 workaround (A64 tables must be identity map) */ 6546 #define MC_CMD_WORKAROUND_BUG35017 0x3 6547 /* enum: Bug 41750 present (MC_CMD_TRIGGER_INTERRUPT won't work) */ 6548 #define MC_CMD_WORKAROUND_BUG41750 0x4 6549 /* enum: Bug 42008 present (Interrupts can overtake associated events). Caution 6550 * - before adding code that queries this workaround, remember that there's 6551 * released Monza firmware that doesn't understand MC_CMD_WORKAROUND_BUG42008, 6552 * and will hence (incorrectly) report that the bug doesn't exist. 6553 */ 6554 #define MC_CMD_WORKAROUND_BUG42008 0x5 6555 /* enum: Bug 26807 features present in firmware (multicast filter chaining) 6556 * This feature cannot be turned on/off while there are any filters already 6557 * present. The behaviour in such case depends on the acting client's privilege 6558 * level. If the client has the admin privilege, then all functions that have 6559 * filters installed will be FLRed and the FLR_DONE flag will be set. Otherwise 6560 * the command will fail with MC_CMD_ERR_FILTERS_PRESENT. 6561 */ 6562 #define MC_CMD_WORKAROUND_BUG26807 0x6 6563 /* 0 = disable the workaround indicated by TYPE; any non-zero value = enable 6564 * the workaround 6565 */ 6566 #define MC_CMD_WORKAROUND_IN_ENABLED_OFST 4 6567 6568 /* MC_CMD_WORKAROUND_OUT msgresponse */ 6569 #define MC_CMD_WORKAROUND_OUT_LEN 0 6570 6571 /* MC_CMD_WORKAROUND_EXT_OUT msgresponse: This response format will be used 6572 * when (TYPE == MC_CMD_WORKAROUND_BUG26807) 6573 */ 6574 #define MC_CMD_WORKAROUND_EXT_OUT_LEN 4 6575 #define MC_CMD_WORKAROUND_EXT_OUT_FLAGS_OFST 0 6576 #define MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN 0 6577 #define MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_WIDTH 1 6578 6579 6580 /***********************************/ 6581 /* MC_CMD_GET_PHY_MEDIA_INFO 6582 * Read media-specific data from PHY (e.g. SFP/SFP+ module ID information for 6583 * SFP+ PHYs). The 'media type' can be found via GET_PHY_CFG 6584 * (GET_PHY_CFG_OUT_MEDIA_TYPE); the valid 'page number' input values, and the 6585 * output data, are interpreted on a per-type basis. For SFP+: PAGE=0 or 1 6586 * returns a 128-byte block read from module I2C address 0xA0 offset 0 or 0x80. 6587 * Anything else: currently undefined. Locks required: None. Return code: 0. 6588 */ 6589 #define MC_CMD_GET_PHY_MEDIA_INFO 0x4b 6590 #undef MC_CMD_0x4b_PRIVILEGE_CTG 6591 6592 #define MC_CMD_0x4b_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6593 6594 /* MC_CMD_GET_PHY_MEDIA_INFO_IN msgrequest */ 6595 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_LEN 4 6596 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_PAGE_OFST 0 6597 6598 /* MC_CMD_GET_PHY_MEDIA_INFO_OUT msgresponse */ 6599 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMIN 5 6600 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMAX 252 6601 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LEN(num) (4+1*(num)) 6602 /* in bytes */ 6603 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATALEN_OFST 0 6604 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_OFST 4 6605 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_LEN 1 6606 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MINNUM 1 6607 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MAXNUM 248 6608 6609 6610 /***********************************/ 6611 /* MC_CMD_NVRAM_TEST 6612 * Test a particular NVRAM partition for valid contents (where "valid" depends 6613 * on the type of partition). 6614 */ 6615 #define MC_CMD_NVRAM_TEST 0x4c 6616 #undef MC_CMD_0x4c_PRIVILEGE_CTG 6617 6618 #define MC_CMD_0x4c_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6619 6620 /* MC_CMD_NVRAM_TEST_IN msgrequest */ 6621 #define MC_CMD_NVRAM_TEST_IN_LEN 4 6622 #define MC_CMD_NVRAM_TEST_IN_TYPE_OFST 0 6623 /* Enum values, see field(s): */ 6624 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ 6625 6626 /* MC_CMD_NVRAM_TEST_OUT msgresponse */ 6627 #define MC_CMD_NVRAM_TEST_OUT_LEN 4 6628 #define MC_CMD_NVRAM_TEST_OUT_RESULT_OFST 0 6629 /* enum: Passed. */ 6630 #define MC_CMD_NVRAM_TEST_PASS 0x0 6631 /* enum: Failed. */ 6632 #define MC_CMD_NVRAM_TEST_FAIL 0x1 6633 /* enum: Not supported. */ 6634 #define MC_CMD_NVRAM_TEST_NOTSUPP 0x2 6635 6636 6637 /***********************************/ 6638 /* MC_CMD_MRSFP_TWEAK 6639 * Read status and/or set parameters for the 'mrsfp' driver in mr_rusty builds. 6640 * I2C I/O expander bits are always read; if equaliser parameters are supplied, 6641 * they are configured first. Locks required: None. Return code: 0, EINVAL. 6642 */ 6643 #define MC_CMD_MRSFP_TWEAK 0x4d 6644 6645 /* MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG msgrequest */ 6646 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_LEN 16 6647 /* 0-6 low->high de-emph. */ 6648 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_LEVEL_OFST 0 6649 /* 0-8 low->high ref.V */ 6650 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_DT_CFG_OFST 4 6651 /* 0-8 0-8 low->high boost */ 6652 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_BOOST_OFST 8 6653 /* 0-8 low->high ref.V */ 6654 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_DT_CFG_OFST 12 6655 6656 /* MC_CMD_MRSFP_TWEAK_IN_READ_ONLY msgrequest */ 6657 #define MC_CMD_MRSFP_TWEAK_IN_READ_ONLY_LEN 0 6658 6659 /* MC_CMD_MRSFP_TWEAK_OUT msgresponse */ 6660 #define MC_CMD_MRSFP_TWEAK_OUT_LEN 12 6661 /* input bits */ 6662 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_INPUTS_OFST 0 6663 /* output bits */ 6664 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_OUTPUTS_OFST 4 6665 /* direction */ 6666 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OFST 8 6667 /* enum: Out. */ 6668 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OUT 0x0 6669 /* enum: In. */ 6670 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_IN 0x1 6671 6672 6673 /***********************************/ 6674 /* MC_CMD_SENSOR_SET_LIMS 6675 * Adjusts the sensor limits. This is a warranty-voiding operation. Returns: 6676 * ENOENT if the sensor specified does not exist, EINVAL if the limits are out 6677 * of range. 6678 */ 6679 #define MC_CMD_SENSOR_SET_LIMS 0x4e 6680 #undef MC_CMD_0x4e_PRIVILEGE_CTG 6681 6682 #define MC_CMD_0x4e_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6683 6684 /* MC_CMD_SENSOR_SET_LIMS_IN msgrequest */ 6685 #define MC_CMD_SENSOR_SET_LIMS_IN_LEN 20 6686 #define MC_CMD_SENSOR_SET_LIMS_IN_SENSOR_OFST 0 6687 /* Enum values, see field(s): */ 6688 /* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */ 6689 /* interpretation is is sensor-specific. */ 6690 #define MC_CMD_SENSOR_SET_LIMS_IN_LOW0_OFST 4 6691 /* interpretation is is sensor-specific. */ 6692 #define MC_CMD_SENSOR_SET_LIMS_IN_HI0_OFST 8 6693 /* interpretation is is sensor-specific. */ 6694 #define MC_CMD_SENSOR_SET_LIMS_IN_LOW1_OFST 12 6695 /* interpretation is is sensor-specific. */ 6696 #define MC_CMD_SENSOR_SET_LIMS_IN_HI1_OFST 16 6697 6698 /* MC_CMD_SENSOR_SET_LIMS_OUT msgresponse */ 6699 #define MC_CMD_SENSOR_SET_LIMS_OUT_LEN 0 6700 6701 6702 /***********************************/ 6703 /* MC_CMD_GET_RESOURCE_LIMITS 6704 */ 6705 #define MC_CMD_GET_RESOURCE_LIMITS 0x4f 6706 6707 /* MC_CMD_GET_RESOURCE_LIMITS_IN msgrequest */ 6708 #define MC_CMD_GET_RESOURCE_LIMITS_IN_LEN 0 6709 6710 /* MC_CMD_GET_RESOURCE_LIMITS_OUT msgresponse */ 6711 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_LEN 16 6712 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_BUFTBL_OFST 0 6713 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_EVQ_OFST 4 6714 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_RXQ_OFST 8 6715 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_TXQ_OFST 12 6716 6717 6718 /***********************************/ 6719 /* MC_CMD_NVRAM_PARTITIONS 6720 * Reads the list of available virtual NVRAM partition types. Locks required: 6721 * none. Returns: 0, EINVAL (bad type). 6722 */ 6723 #define MC_CMD_NVRAM_PARTITIONS 0x51 6724 #undef MC_CMD_0x51_PRIVILEGE_CTG 6725 6726 #define MC_CMD_0x51_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6727 6728 /* MC_CMD_NVRAM_PARTITIONS_IN msgrequest */ 6729 #define MC_CMD_NVRAM_PARTITIONS_IN_LEN 0 6730 6731 /* MC_CMD_NVRAM_PARTITIONS_OUT msgresponse */ 6732 #define MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN 4 6733 #define MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX 252 6734 #define MC_CMD_NVRAM_PARTITIONS_OUT_LEN(num) (4+4*(num)) 6735 /* total number of partitions */ 6736 #define MC_CMD_NVRAM_PARTITIONS_OUT_NUM_PARTITIONS_OFST 0 6737 /* type ID code for each of NUM_PARTITIONS partitions */ 6738 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_OFST 4 6739 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_LEN 4 6740 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MINNUM 0 6741 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MAXNUM 62 6742 6743 6744 /***********************************/ 6745 /* MC_CMD_NVRAM_METADATA 6746 * Reads soft metadata for a virtual NVRAM partition type. Locks required: 6747 * none. Returns: 0, EINVAL (bad type). 6748 */ 6749 #define MC_CMD_NVRAM_METADATA 0x52 6750 #undef MC_CMD_0x52_PRIVILEGE_CTG 6751 6752 #define MC_CMD_0x52_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6753 6754 /* MC_CMD_NVRAM_METADATA_IN msgrequest */ 6755 #define MC_CMD_NVRAM_METADATA_IN_LEN 4 6756 /* Partition type ID code */ 6757 #define MC_CMD_NVRAM_METADATA_IN_TYPE_OFST 0 6758 6759 /* MC_CMD_NVRAM_METADATA_OUT msgresponse */ 6760 #define MC_CMD_NVRAM_METADATA_OUT_LENMIN 20 6761 #define MC_CMD_NVRAM_METADATA_OUT_LENMAX 252 6762 #define MC_CMD_NVRAM_METADATA_OUT_LEN(num) (20+1*(num)) 6763 /* Partition type ID code */ 6764 #define MC_CMD_NVRAM_METADATA_OUT_TYPE_OFST 0 6765 #define MC_CMD_NVRAM_METADATA_OUT_FLAGS_OFST 4 6766 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN 0 6767 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_WIDTH 1 6768 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_LBN 1 6769 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_WIDTH 1 6770 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_LBN 2 6771 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_WIDTH 1 6772 /* Subtype ID code for content of this partition */ 6773 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_OFST 8 6774 /* 1st component of W.X.Y.Z version number for content of this partition */ 6775 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_W_OFST 12 6776 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_W_LEN 2 6777 /* 2nd component of W.X.Y.Z version number for content of this partition */ 6778 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_X_OFST 14 6779 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_X_LEN 2 6780 /* 3rd component of W.X.Y.Z version number for content of this partition */ 6781 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Y_OFST 16 6782 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Y_LEN 2 6783 /* 4th component of W.X.Y.Z version number for content of this partition */ 6784 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Z_OFST 18 6785 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Z_LEN 2 6786 /* Zero-terminated string describing the content of this partition */ 6787 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_OFST 20 6788 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_LEN 1 6789 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MINNUM 0 6790 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MAXNUM 232 6791 6792 6793 /***********************************/ 6794 /* MC_CMD_GET_MAC_ADDRESSES 6795 * Returns the base MAC, count and stride for the requesting function 6796 */ 6797 #define MC_CMD_GET_MAC_ADDRESSES 0x55 6798 #undef MC_CMD_0x55_PRIVILEGE_CTG 6799 6800 #define MC_CMD_0x55_PRIVILEGE_CTG SRIOV_CTG_GENERAL 6801 6802 /* MC_CMD_GET_MAC_ADDRESSES_IN msgrequest */ 6803 #define MC_CMD_GET_MAC_ADDRESSES_IN_LEN 0 6804 6805 /* MC_CMD_GET_MAC_ADDRESSES_OUT msgresponse */ 6806 #define MC_CMD_GET_MAC_ADDRESSES_OUT_LEN 16 6807 /* Base MAC address */ 6808 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE_OFST 0 6809 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE_LEN 6 6810 /* Padding */ 6811 #define MC_CMD_GET_MAC_ADDRESSES_OUT_RESERVED_OFST 6 6812 #define MC_CMD_GET_MAC_ADDRESSES_OUT_RESERVED_LEN 2 6813 /* Number of allocated MAC addresses */ 6814 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_COUNT_OFST 8 6815 /* Spacing of allocated MAC addresses */ 6816 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_STRIDE_OFST 12 6817 6818 6819 /***********************************/ 6820 /* MC_CMD_CLP 6821 * Perform a CLP related operation 6822 */ 6823 #define MC_CMD_CLP 0x56 6824 #undef MC_CMD_0x56_PRIVILEGE_CTG 6825 6826 #define MC_CMD_0x56_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6827 6828 /* MC_CMD_CLP_IN msgrequest */ 6829 #define MC_CMD_CLP_IN_LEN 4 6830 /* Sub operation */ 6831 #define MC_CMD_CLP_IN_OP_OFST 0 6832 /* enum: Return to factory default settings */ 6833 #define MC_CMD_CLP_OP_DEFAULT 0x1 6834 /* enum: Set MAC address */ 6835 #define MC_CMD_CLP_OP_SET_MAC 0x2 6836 /* enum: Get MAC address */ 6837 #define MC_CMD_CLP_OP_GET_MAC 0x3 6838 /* enum: Set UEFI/GPXE boot mode */ 6839 #define MC_CMD_CLP_OP_SET_BOOT 0x4 6840 /* enum: Get UEFI/GPXE boot mode */ 6841 #define MC_CMD_CLP_OP_GET_BOOT 0x5 6842 6843 /* MC_CMD_CLP_OUT msgresponse */ 6844 #define MC_CMD_CLP_OUT_LEN 0 6845 6846 /* MC_CMD_CLP_IN_DEFAULT msgrequest */ 6847 #define MC_CMD_CLP_IN_DEFAULT_LEN 4 6848 /* MC_CMD_CLP_IN_OP_OFST 0 */ 6849 6850 /* MC_CMD_CLP_OUT_DEFAULT msgresponse */ 6851 #define MC_CMD_CLP_OUT_DEFAULT_LEN 0 6852 6853 /* MC_CMD_CLP_IN_SET_MAC msgrequest */ 6854 #define MC_CMD_CLP_IN_SET_MAC_LEN 12 6855 /* MC_CMD_CLP_IN_OP_OFST 0 */ 6856 /* MAC address assigned to port */ 6857 #define MC_CMD_CLP_IN_SET_MAC_ADDR_OFST 4 6858 #define MC_CMD_CLP_IN_SET_MAC_ADDR_LEN 6 6859 /* Padding */ 6860 #define MC_CMD_CLP_IN_SET_MAC_RESERVED_OFST 10 6861 #define MC_CMD_CLP_IN_SET_MAC_RESERVED_LEN 2 6862 6863 /* MC_CMD_CLP_OUT_SET_MAC msgresponse */ 6864 #define MC_CMD_CLP_OUT_SET_MAC_LEN 0 6865 6866 /* MC_CMD_CLP_IN_GET_MAC msgrequest */ 6867 #define MC_CMD_CLP_IN_GET_MAC_LEN 4 6868 /* MC_CMD_CLP_IN_OP_OFST 0 */ 6869 6870 /* MC_CMD_CLP_OUT_GET_MAC msgresponse */ 6871 #define MC_CMD_CLP_OUT_GET_MAC_LEN 8 6872 /* MAC address assigned to port */ 6873 #define MC_CMD_CLP_OUT_GET_MAC_ADDR_OFST 0 6874 #define MC_CMD_CLP_OUT_GET_MAC_ADDR_LEN 6 6875 /* Padding */ 6876 #define MC_CMD_CLP_OUT_GET_MAC_RESERVED_OFST 6 6877 #define MC_CMD_CLP_OUT_GET_MAC_RESERVED_LEN 2 6878 6879 /* MC_CMD_CLP_IN_SET_BOOT msgrequest */ 6880 #define MC_CMD_CLP_IN_SET_BOOT_LEN 5 6881 /* MC_CMD_CLP_IN_OP_OFST 0 */ 6882 /* Boot flag */ 6883 #define MC_CMD_CLP_IN_SET_BOOT_FLAG_OFST 4 6884 #define MC_CMD_CLP_IN_SET_BOOT_FLAG_LEN 1 6885 6886 /* MC_CMD_CLP_OUT_SET_BOOT msgresponse */ 6887 #define MC_CMD_CLP_OUT_SET_BOOT_LEN 0 6888 6889 /* MC_CMD_CLP_IN_GET_BOOT msgrequest */ 6890 #define MC_CMD_CLP_IN_GET_BOOT_LEN 4 6891 /* MC_CMD_CLP_IN_OP_OFST 0 */ 6892 6893 /* MC_CMD_CLP_OUT_GET_BOOT msgresponse */ 6894 #define MC_CMD_CLP_OUT_GET_BOOT_LEN 4 6895 /* Boot flag */ 6896 #define MC_CMD_CLP_OUT_GET_BOOT_FLAG_OFST 0 6897 #define MC_CMD_CLP_OUT_GET_BOOT_FLAG_LEN 1 6898 /* Padding */ 6899 #define MC_CMD_CLP_OUT_GET_BOOT_RESERVED_OFST 1 6900 #define MC_CMD_CLP_OUT_GET_BOOT_RESERVED_LEN 3 6901 6902 6903 /***********************************/ 6904 /* MC_CMD_MUM 6905 * Perform a MUM operation 6906 */ 6907 #define MC_CMD_MUM 0x57 6908 #undef MC_CMD_0x57_PRIVILEGE_CTG 6909 6910 #define MC_CMD_0x57_PRIVILEGE_CTG SRIOV_CTG_ADMIN 6911 6912 /* MC_CMD_MUM_IN msgrequest */ 6913 #define MC_CMD_MUM_IN_LEN 4 6914 #define MC_CMD_MUM_IN_OP_HDR_OFST 0 6915 #define MC_CMD_MUM_IN_OP_LBN 0 6916 #define MC_CMD_MUM_IN_OP_WIDTH 8 6917 /* enum: NULL MCDI command to MUM */ 6918 #define MC_CMD_MUM_OP_NULL 0x1 6919 /* enum: Get MUM version */ 6920 #define MC_CMD_MUM_OP_GET_VERSION 0x2 6921 /* enum: Issue raw I2C command to MUM */ 6922 #define MC_CMD_MUM_OP_RAW_CMD 0x3 6923 /* enum: Read from registers on devices connected to MUM. */ 6924 #define MC_CMD_MUM_OP_READ 0x4 6925 /* enum: Write to registers on devices connected to MUM. */ 6926 #define MC_CMD_MUM_OP_WRITE 0x5 6927 /* enum: Control UART logging. */ 6928 #define MC_CMD_MUM_OP_LOG 0x6 6929 /* enum: Operations on MUM GPIO lines */ 6930 #define MC_CMD_MUM_OP_GPIO 0x7 6931 /* enum: Get sensor readings from MUM */ 6932 #define MC_CMD_MUM_OP_READ_SENSORS 0x8 6933 /* enum: Initiate clock programming on the MUM */ 6934 #define MC_CMD_MUM_OP_PROGRAM_CLOCKS 0x9 6935 /* enum: Initiate FPGA load from flash on the MUM */ 6936 #define MC_CMD_MUM_OP_FPGA_LOAD 0xa 6937 /* enum: Request sensor reading from MUM ADC resulting from earlier request via 6938 * MUM ATB 6939 */ 6940 #define MC_CMD_MUM_OP_READ_ATB_SENSOR 0xb 6941 /* enum: Send commands relating to the QSFP ports via the MUM for PHY 6942 * operations 6943 */ 6944 #define MC_CMD_MUM_OP_QSFP 0xc 6945 6946 /* MC_CMD_MUM_IN_NULL msgrequest */ 6947 #define MC_CMD_MUM_IN_NULL_LEN 4 6948 /* MUM cmd header */ 6949 #define MC_CMD_MUM_IN_CMD_OFST 0 6950 6951 /* MC_CMD_MUM_IN_GET_VERSION msgrequest */ 6952 #define MC_CMD_MUM_IN_GET_VERSION_LEN 4 6953 /* MUM cmd header */ 6954 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6955 6956 /* MC_CMD_MUM_IN_READ msgrequest */ 6957 #define MC_CMD_MUM_IN_READ_LEN 16 6958 /* MUM cmd header */ 6959 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6960 /* ID of (device connected to MUM) to read from registers of */ 6961 #define MC_CMD_MUM_IN_READ_DEVICE_OFST 4 6962 /* enum: Hittite HMC1035 clock generator on Sorrento board */ 6963 #define MC_CMD_MUM_DEV_HITTITE 0x1 6964 /* enum: Hittite HMC1035 clock generator for NIC-side on Sorrento board */ 6965 #define MC_CMD_MUM_DEV_HITTITE_NIC 0x2 6966 /* 32-bit address to read from */ 6967 #define MC_CMD_MUM_IN_READ_ADDR_OFST 8 6968 /* Number of words to read. */ 6969 #define MC_CMD_MUM_IN_READ_NUMWORDS_OFST 12 6970 6971 /* MC_CMD_MUM_IN_WRITE msgrequest */ 6972 #define MC_CMD_MUM_IN_WRITE_LENMIN 16 6973 #define MC_CMD_MUM_IN_WRITE_LENMAX 252 6974 #define MC_CMD_MUM_IN_WRITE_LEN(num) (12+4*(num)) 6975 /* MUM cmd header */ 6976 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6977 /* ID of (device connected to MUM) to write to registers of */ 6978 #define MC_CMD_MUM_IN_WRITE_DEVICE_OFST 4 6979 /* enum: Hittite HMC1035 clock generator on Sorrento board */ 6980 /* MC_CMD_MUM_DEV_HITTITE 0x1 */ 6981 /* 32-bit address to write to */ 6982 #define MC_CMD_MUM_IN_WRITE_ADDR_OFST 8 6983 /* Words to write */ 6984 #define MC_CMD_MUM_IN_WRITE_BUFFER_OFST 12 6985 #define MC_CMD_MUM_IN_WRITE_BUFFER_LEN 4 6986 #define MC_CMD_MUM_IN_WRITE_BUFFER_MINNUM 1 6987 #define MC_CMD_MUM_IN_WRITE_BUFFER_MAXNUM 60 6988 6989 /* MC_CMD_MUM_IN_RAW_CMD msgrequest */ 6990 #define MC_CMD_MUM_IN_RAW_CMD_LENMIN 17 6991 #define MC_CMD_MUM_IN_RAW_CMD_LENMAX 252 6992 #define MC_CMD_MUM_IN_RAW_CMD_LEN(num) (16+1*(num)) 6993 /* MUM cmd header */ 6994 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 6995 /* MUM I2C cmd code */ 6996 #define MC_CMD_MUM_IN_RAW_CMD_CMD_CODE_OFST 4 6997 /* Number of bytes to write */ 6998 #define MC_CMD_MUM_IN_RAW_CMD_NUM_WRITE_OFST 8 6999 /* Number of bytes to read */ 7000 #define MC_CMD_MUM_IN_RAW_CMD_NUM_READ_OFST 12 7001 /* Bytes to write */ 7002 #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_OFST 16 7003 #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_LEN 1 7004 #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_MINNUM 1 7005 #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_MAXNUM 236 7006 7007 /* MC_CMD_MUM_IN_LOG msgrequest */ 7008 #define MC_CMD_MUM_IN_LOG_LEN 8 7009 /* MUM cmd header */ 7010 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7011 #define MC_CMD_MUM_IN_LOG_OP_OFST 4 7012 #define MC_CMD_MUM_IN_LOG_OP_UART 0x1 /* enum */ 7013 7014 /* MC_CMD_MUM_IN_LOG_OP_UART msgrequest */ 7015 #define MC_CMD_MUM_IN_LOG_OP_UART_LEN 12 7016 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7017 /* MC_CMD_MUM_IN_LOG_OP_OFST 4 */ 7018 /* Enable/disable debug output to UART */ 7019 #define MC_CMD_MUM_IN_LOG_OP_UART_ENABLE_OFST 8 7020 7021 /* MC_CMD_MUM_IN_GPIO msgrequest */ 7022 #define MC_CMD_MUM_IN_GPIO_LEN 8 7023 /* MUM cmd header */ 7024 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7025 #define MC_CMD_MUM_IN_GPIO_HDR_OFST 4 7026 #define MC_CMD_MUM_IN_GPIO_OPCODE_LBN 0 7027 #define MC_CMD_MUM_IN_GPIO_OPCODE_WIDTH 8 7028 #define MC_CMD_MUM_IN_GPIO_IN_READ 0x0 /* enum */ 7029 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE 0x1 /* enum */ 7030 #define MC_CMD_MUM_IN_GPIO_OUT_READ 0x2 /* enum */ 7031 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE 0x3 /* enum */ 7032 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ 0x4 /* enum */ 7033 #define MC_CMD_MUM_IN_GPIO_OP 0x5 /* enum */ 7034 7035 /* MC_CMD_MUM_IN_GPIO_IN_READ msgrequest */ 7036 #define MC_CMD_MUM_IN_GPIO_IN_READ_LEN 8 7037 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7038 #define MC_CMD_MUM_IN_GPIO_IN_READ_HDR_OFST 4 7039 7040 /* MC_CMD_MUM_IN_GPIO_OUT_WRITE msgrequest */ 7041 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_LEN 16 7042 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7043 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_HDR_OFST 4 7044 /* The first 32-bit word to be written to the GPIO OUT register. */ 7045 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK1_OFST 8 7046 /* The second 32-bit word to be written to the GPIO OUT register. */ 7047 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK2_OFST 12 7048 7049 /* MC_CMD_MUM_IN_GPIO_OUT_READ msgrequest */ 7050 #define MC_CMD_MUM_IN_GPIO_OUT_READ_LEN 8 7051 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7052 #define MC_CMD_MUM_IN_GPIO_OUT_READ_HDR_OFST 4 7053 7054 /* MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE msgrequest */ 7055 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_LEN 16 7056 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7057 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_HDR_OFST 4 7058 /* The first 32-bit word to be written to the GPIO OUT ENABLE register. */ 7059 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK1_OFST 8 7060 /* The second 32-bit word to be written to the GPIO OUT ENABLE register. */ 7061 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK2_OFST 12 7062 7063 /* MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ msgrequest */ 7064 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_LEN 8 7065 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7066 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_HDR_OFST 4 7067 7068 /* MC_CMD_MUM_IN_GPIO_OP msgrequest */ 7069 #define MC_CMD_MUM_IN_GPIO_OP_LEN 8 7070 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7071 #define MC_CMD_MUM_IN_GPIO_OP_HDR_OFST 4 7072 #define MC_CMD_MUM_IN_GPIO_OP_BITWISE_OP_LBN 8 7073 #define MC_CMD_MUM_IN_GPIO_OP_BITWISE_OP_WIDTH 8 7074 #define MC_CMD_MUM_IN_GPIO_OP_OUT_READ 0x0 /* enum */ 7075 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE 0x1 /* enum */ 7076 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG 0x2 /* enum */ 7077 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE 0x3 /* enum */ 7078 #define MC_CMD_MUM_IN_GPIO_OP_GPIO_NUMBER_LBN 16 7079 #define MC_CMD_MUM_IN_GPIO_OP_GPIO_NUMBER_WIDTH 8 7080 7081 /* MC_CMD_MUM_IN_GPIO_OP_OUT_READ msgrequest */ 7082 #define MC_CMD_MUM_IN_GPIO_OP_OUT_READ_LEN 8 7083 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7084 #define MC_CMD_MUM_IN_GPIO_OP_OUT_READ_HDR_OFST 4 7085 7086 /* MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE msgrequest */ 7087 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_LEN 8 7088 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7089 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_HDR_OFST 4 7090 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_WRITEBIT_LBN 24 7091 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_WRITEBIT_WIDTH 8 7092 7093 /* MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG msgrequest */ 7094 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_LEN 8 7095 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7096 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_HDR_OFST 4 7097 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_CFG_LBN 24 7098 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_CFG_WIDTH 8 7099 7100 /* MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE msgrequest */ 7101 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_LEN 8 7102 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7103 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_HDR_OFST 4 7104 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_ENABLEBIT_LBN 24 7105 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_ENABLEBIT_WIDTH 8 7106 7107 /* MC_CMD_MUM_IN_READ_SENSORS msgrequest */ 7108 #define MC_CMD_MUM_IN_READ_SENSORS_LEN 8 7109 /* MUM cmd header */ 7110 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7111 #define MC_CMD_MUM_IN_READ_SENSORS_PARAMS_OFST 4 7112 #define MC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_LBN 0 7113 #define MC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_WIDTH 8 7114 #define MC_CMD_MUM_IN_READ_SENSORS_NUM_SENSORS_LBN 8 7115 #define MC_CMD_MUM_IN_READ_SENSORS_NUM_SENSORS_WIDTH 8 7116 7117 /* MC_CMD_MUM_IN_PROGRAM_CLOCKS msgrequest */ 7118 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_LEN 12 7119 /* MUM cmd header */ 7120 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7121 /* Bit-mask of clocks to be programmed */ 7122 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_MASK_OFST 4 7123 #define MC_CMD_MUM_CLOCK_ID_FPGA 0x0 /* enum */ 7124 #define MC_CMD_MUM_CLOCK_ID_DDR 0x1 /* enum */ 7125 #define MC_CMD_MUM_CLOCK_ID_NIC 0x2 /* enum */ 7126 /* Control flags for clock programming */ 7127 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_FLAGS_OFST 8 7128 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_LBN 0 7129 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_WIDTH 1 7130 7131 /* MC_CMD_MUM_IN_FPGA_LOAD msgrequest */ 7132 #define MC_CMD_MUM_IN_FPGA_LOAD_LEN 8 7133 /* MUM cmd header */ 7134 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7135 /* Enable/Disable FPGA config from flash */ 7136 #define MC_CMD_MUM_IN_FPGA_LOAD_ENABLE_OFST 4 7137 7138 /* MC_CMD_MUM_IN_READ_ATB_SENSOR msgrequest */ 7139 #define MC_CMD_MUM_IN_READ_ATB_SENSOR_LEN 4 7140 /* MUM cmd header */ 7141 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7142 7143 /* MC_CMD_MUM_IN_QSFP msgrequest */ 7144 #define MC_CMD_MUM_IN_QSFP_LEN 12 7145 /* MUM cmd header */ 7146 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7147 #define MC_CMD_MUM_IN_QSFP_HDR_OFST 4 7148 #define MC_CMD_MUM_IN_QSFP_OPCODE_LBN 0 7149 #define MC_CMD_MUM_IN_QSFP_OPCODE_WIDTH 4 7150 #define MC_CMD_MUM_IN_QSFP_INIT 0x0 /* enum */ 7151 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE 0x1 /* enum */ 7152 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP 0x2 /* enum */ 7153 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO 0x3 /* enum */ 7154 #define MC_CMD_MUM_IN_QSFP_FILL_STATS 0x4 /* enum */ 7155 #define MC_CMD_MUM_IN_QSFP_POLL_BIST 0x5 /* enum */ 7156 #define MC_CMD_MUM_IN_QSFP_IDX_OFST 8 7157 7158 /* MC_CMD_MUM_IN_QSFP_INIT msgrequest */ 7159 #define MC_CMD_MUM_IN_QSFP_INIT_LEN 16 7160 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7161 #define MC_CMD_MUM_IN_QSFP_INIT_HDR_OFST 4 7162 #define MC_CMD_MUM_IN_QSFP_INIT_IDX_OFST 8 7163 #define MC_CMD_MUM_IN_QSFP_INIT_CAGE_OFST 12 7164 7165 /* MC_CMD_MUM_IN_QSFP_RECONFIGURE msgrequest */ 7166 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_LEN 24 7167 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7168 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_HDR_OFST 4 7169 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_IDX_OFST 8 7170 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_TX_DISABLE_OFST 12 7171 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LANES_OFST 16 7172 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LINK_SPEED_OFST 20 7173 7174 /* MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP msgrequest */ 7175 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_LEN 12 7176 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7177 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_HDR_OFST 4 7178 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_IDX_OFST 8 7179 7180 /* MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO msgrequest */ 7181 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_LEN 16 7182 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7183 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_HDR_OFST 4 7184 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_IDX_OFST 8 7185 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_PAGE_OFST 12 7186 7187 /* MC_CMD_MUM_IN_QSFP_FILL_STATS msgrequest */ 7188 #define MC_CMD_MUM_IN_QSFP_FILL_STATS_LEN 12 7189 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7190 #define MC_CMD_MUM_IN_QSFP_FILL_STATS_HDR_OFST 4 7191 #define MC_CMD_MUM_IN_QSFP_FILL_STATS_IDX_OFST 8 7192 7193 /* MC_CMD_MUM_IN_QSFP_POLL_BIST msgrequest */ 7194 #define MC_CMD_MUM_IN_QSFP_POLL_BIST_LEN 12 7195 /* MC_CMD_MUM_IN_CMD_OFST 0 */ 7196 #define MC_CMD_MUM_IN_QSFP_POLL_BIST_HDR_OFST 4 7197 #define MC_CMD_MUM_IN_QSFP_POLL_BIST_IDX_OFST 8 7198 7199 /* MC_CMD_MUM_OUT msgresponse */ 7200 #define MC_CMD_MUM_OUT_LEN 0 7201 7202 /* MC_CMD_MUM_OUT_NULL msgresponse */ 7203 #define MC_CMD_MUM_OUT_NULL_LEN 0 7204 7205 /* MC_CMD_MUM_OUT_GET_VERSION msgresponse */ 7206 #define MC_CMD_MUM_OUT_GET_VERSION_LEN 12 7207 #define MC_CMD_MUM_OUT_GET_VERSION_FIRMWARE_OFST 0 7208 #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_OFST 4 7209 #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LEN 8 7210 #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LO_OFST 4 7211 #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_HI_OFST 8 7212 7213 /* MC_CMD_MUM_OUT_RAW_CMD msgresponse */ 7214 #define MC_CMD_MUM_OUT_RAW_CMD_LENMIN 1 7215 #define MC_CMD_MUM_OUT_RAW_CMD_LENMAX 252 7216 #define MC_CMD_MUM_OUT_RAW_CMD_LEN(num) (0+1*(num)) 7217 /* returned data */ 7218 #define MC_CMD_MUM_OUT_RAW_CMD_DATA_OFST 0 7219 #define MC_CMD_MUM_OUT_RAW_CMD_DATA_LEN 1 7220 #define MC_CMD_MUM_OUT_RAW_CMD_DATA_MINNUM 1 7221 #define MC_CMD_MUM_OUT_RAW_CMD_DATA_MAXNUM 252 7222 7223 /* MC_CMD_MUM_OUT_READ msgresponse */ 7224 #define MC_CMD_MUM_OUT_READ_LENMIN 4 7225 #define MC_CMD_MUM_OUT_READ_LENMAX 252 7226 #define MC_CMD_MUM_OUT_READ_LEN(num) (0+4*(num)) 7227 #define MC_CMD_MUM_OUT_READ_BUFFER_OFST 0 7228 #define MC_CMD_MUM_OUT_READ_BUFFER_LEN 4 7229 #define MC_CMD_MUM_OUT_READ_BUFFER_MINNUM 1 7230 #define MC_CMD_MUM_OUT_READ_BUFFER_MAXNUM 63 7231 7232 /* MC_CMD_MUM_OUT_WRITE msgresponse */ 7233 #define MC_CMD_MUM_OUT_WRITE_LEN 0 7234 7235 /* MC_CMD_MUM_OUT_LOG msgresponse */ 7236 #define MC_CMD_MUM_OUT_LOG_LEN 0 7237 7238 /* MC_CMD_MUM_OUT_LOG_OP_UART msgresponse */ 7239 #define MC_CMD_MUM_OUT_LOG_OP_UART_LEN 0 7240 7241 /* MC_CMD_MUM_OUT_GPIO_IN_READ msgresponse */ 7242 #define MC_CMD_MUM_OUT_GPIO_IN_READ_LEN 8 7243 /* The first 32-bit word read from the GPIO IN register. */ 7244 #define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK1_OFST 0 7245 /* The second 32-bit word read from the GPIO IN register. */ 7246 #define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK2_OFST 4 7247 7248 /* MC_CMD_MUM_OUT_GPIO_OUT_WRITE msgresponse */ 7249 #define MC_CMD_MUM_OUT_GPIO_OUT_WRITE_LEN 0 7250 7251 /* MC_CMD_MUM_OUT_GPIO_OUT_READ msgresponse */ 7252 #define MC_CMD_MUM_OUT_GPIO_OUT_READ_LEN 8 7253 /* The first 32-bit word read from the GPIO OUT register. */ 7254 #define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK1_OFST 0 7255 /* The second 32-bit word read from the GPIO OUT register. */ 7256 #define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK2_OFST 4 7257 7258 /* MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_WRITE msgresponse */ 7259 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_WRITE_LEN 0 7260 7261 /* MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ msgresponse */ 7262 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_LEN 8 7263 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK1_OFST 0 7264 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK2_OFST 4 7265 7266 /* MC_CMD_MUM_OUT_GPIO_OP_OUT_READ msgresponse */ 7267 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_LEN 4 7268 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_BIT_READ_OFST 0 7269 7270 /* MC_CMD_MUM_OUT_GPIO_OP_OUT_WRITE msgresponse */ 7271 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_WRITE_LEN 0 7272 7273 /* MC_CMD_MUM_OUT_GPIO_OP_OUT_CONFIG msgresponse */ 7274 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_CONFIG_LEN 0 7275 7276 /* MC_CMD_MUM_OUT_GPIO_OP_OUT_ENABLE msgresponse */ 7277 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_ENABLE_LEN 0 7278 7279 /* MC_CMD_MUM_OUT_READ_SENSORS msgresponse */ 7280 #define MC_CMD_MUM_OUT_READ_SENSORS_LENMIN 4 7281 #define MC_CMD_MUM_OUT_READ_SENSORS_LENMAX 252 7282 #define MC_CMD_MUM_OUT_READ_SENSORS_LEN(num) (0+4*(num)) 7283 #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_OFST 0 7284 #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_LEN 4 7285 #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_MINNUM 1 7286 #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_MAXNUM 63 7287 #define MC_CMD_MUM_OUT_READ_SENSORS_READING_LBN 0 7288 #define MC_CMD_MUM_OUT_READ_SENSORS_READING_WIDTH 16 7289 #define MC_CMD_MUM_OUT_READ_SENSORS_STATE_LBN 16 7290 #define MC_CMD_MUM_OUT_READ_SENSORS_STATE_WIDTH 8 7291 #define MC_CMD_MUM_OUT_READ_SENSORS_TYPE_LBN 24 7292 #define MC_CMD_MUM_OUT_READ_SENSORS_TYPE_WIDTH 8 7293 7294 /* MC_CMD_MUM_OUT_PROGRAM_CLOCKS msgresponse */ 7295 #define MC_CMD_MUM_OUT_PROGRAM_CLOCKS_LEN 4 7296 #define MC_CMD_MUM_OUT_PROGRAM_CLOCKS_OK_MASK_OFST 0 7297 7298 /* MC_CMD_MUM_OUT_FPGA_LOAD msgresponse */ 7299 #define MC_CMD_MUM_OUT_FPGA_LOAD_LEN 0 7300 7301 /* MC_CMD_MUM_OUT_READ_ATB_SENSOR msgresponse */ 7302 #define MC_CMD_MUM_OUT_READ_ATB_SENSOR_LEN 4 7303 #define MC_CMD_MUM_OUT_READ_ATB_SENSOR_RESULT_OFST 0 7304 7305 /* MC_CMD_MUM_OUT_QSFP_INIT msgresponse */ 7306 #define MC_CMD_MUM_OUT_QSFP_INIT_LEN 0 7307 7308 /* MC_CMD_MUM_OUT_QSFP_RECONFIGURE msgresponse */ 7309 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_LEN 8 7310 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LP_CAP_OFST 0 7311 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_FLAGS_OFST 4 7312 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_LBN 0 7313 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_WIDTH 1 7314 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_LBN 1 7315 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_WIDTH 1 7316 7317 /* MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP msgresponse */ 7318 #define MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_LEN 4 7319 #define MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_PORT_PHY_LP_CAP_OFST 0 7320 7321 /* MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO msgresponse */ 7322 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LENMIN 5 7323 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LENMAX 252 7324 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LEN(num) (4+1*(num)) 7325 /* in bytes */ 7326 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATALEN_OFST 0 7327 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_OFST 4 7328 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_LEN 1 7329 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_MINNUM 1 7330 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_MAXNUM 248 7331 7332 /* MC_CMD_MUM_OUT_QSFP_FILL_STATS msgresponse */ 7333 #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_LEN 8 7334 #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PMA_PMD_LINK_UP_OFST 0 7335 #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PCS_LINK_UP_OFST 4 7336 7337 /* MC_CMD_MUM_OUT_QSFP_POLL_BIST msgresponse */ 7338 #define MC_CMD_MUM_OUT_QSFP_POLL_BIST_LEN 4 7339 #define MC_CMD_MUM_OUT_QSFP_POLL_BIST_TEST_OFST 0 7340 7341 /* MC_CMD_RESOURCE_SPECIFIER enum */ 7342 /* enum: Any */ 7343 #define MC_CMD_RESOURCE_INSTANCE_ANY 0xffffffff 7344 /* enum: None */ 7345 #define MC_CMD_RESOURCE_INSTANCE_NONE 0xfffffffe 7346 7347 /* EVB_PORT_ID structuredef */ 7348 #define EVB_PORT_ID_LEN 4 7349 #define EVB_PORT_ID_PORT_ID_OFST 0 7350 /* enum: An invalid port handle. */ 7351 #define EVB_PORT_ID_NULL 0x0 7352 /* enum: The port assigned to this function.. */ 7353 #define EVB_PORT_ID_ASSIGNED 0x1000000 7354 /* enum: External network port 0 */ 7355 #define EVB_PORT_ID_MAC0 0x2000000 7356 /* enum: External network port 1 */ 7357 #define EVB_PORT_ID_MAC1 0x2000001 7358 /* enum: External network port 2 */ 7359 #define EVB_PORT_ID_MAC2 0x2000002 7360 /* enum: External network port 3 */ 7361 #define EVB_PORT_ID_MAC3 0x2000003 7362 #define EVB_PORT_ID_PORT_ID_LBN 0 7363 #define EVB_PORT_ID_PORT_ID_WIDTH 32 7364 7365 /* EVB_VLAN_TAG structuredef */ 7366 #define EVB_VLAN_TAG_LEN 2 7367 /* The VLAN tag value */ 7368 #define EVB_VLAN_TAG_VLAN_ID_LBN 0 7369 #define EVB_VLAN_TAG_VLAN_ID_WIDTH 12 7370 #define EVB_VLAN_TAG_MODE_LBN 12 7371 #define EVB_VLAN_TAG_MODE_WIDTH 4 7372 /* enum: Insert the VLAN. */ 7373 #define EVB_VLAN_TAG_INSERT 0x0 7374 /* enum: Replace the VLAN if already present. */ 7375 #define EVB_VLAN_TAG_REPLACE 0x1 7376 7377 /* BUFTBL_ENTRY structuredef */ 7378 #define BUFTBL_ENTRY_LEN 12 7379 /* the owner ID */ 7380 #define BUFTBL_ENTRY_OID_OFST 0 7381 #define BUFTBL_ENTRY_OID_LEN 2 7382 #define BUFTBL_ENTRY_OID_LBN 0 7383 #define BUFTBL_ENTRY_OID_WIDTH 16 7384 /* the page parameter as one of ESE_DZ_SMC_PAGE_SIZE_ */ 7385 #define BUFTBL_ENTRY_PGSZ_OFST 2 7386 #define BUFTBL_ENTRY_PGSZ_LEN 2 7387 #define BUFTBL_ENTRY_PGSZ_LBN 16 7388 #define BUFTBL_ENTRY_PGSZ_WIDTH 16 7389 /* the raw 64-bit address field from the SMC, not adjusted for page size */ 7390 #define BUFTBL_ENTRY_RAWADDR_OFST 4 7391 #define BUFTBL_ENTRY_RAWADDR_LEN 8 7392 #define BUFTBL_ENTRY_RAWADDR_LO_OFST 4 7393 #define BUFTBL_ENTRY_RAWADDR_HI_OFST 8 7394 #define BUFTBL_ENTRY_RAWADDR_LBN 32 7395 #define BUFTBL_ENTRY_RAWADDR_WIDTH 64 7396 7397 /* NVRAM_PARTITION_TYPE structuredef */ 7398 #define NVRAM_PARTITION_TYPE_LEN 2 7399 #define NVRAM_PARTITION_TYPE_ID_OFST 0 7400 #define NVRAM_PARTITION_TYPE_ID_LEN 2 7401 /* enum: Primary MC firmware partition */ 7402 #define NVRAM_PARTITION_TYPE_MC_FIRMWARE 0x100 7403 /* enum: Secondary MC firmware partition */ 7404 #define NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP 0x200 7405 /* enum: Expansion ROM partition */ 7406 #define NVRAM_PARTITION_TYPE_EXPANSION_ROM 0x300 7407 /* enum: Static configuration TLV partition */ 7408 #define NVRAM_PARTITION_TYPE_STATIC_CONFIG 0x400 7409 /* enum: Dynamic configuration TLV partition */ 7410 #define NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG 0x500 7411 /* enum: Expansion ROM configuration data for port 0 */ 7412 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0 0x600 7413 /* enum: Expansion ROM configuration data for port 1 */ 7414 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1 0x601 7415 /* enum: Expansion ROM configuration data for port 2 */ 7416 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2 0x602 7417 /* enum: Expansion ROM configuration data for port 3 */ 7418 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3 0x603 7419 /* enum: Non-volatile log output partition */ 7420 #define NVRAM_PARTITION_TYPE_LOG 0x700 7421 /* enum: Device state dump output partition */ 7422 #define NVRAM_PARTITION_TYPE_DUMP 0x800 7423 /* enum: Application license key storage partition */ 7424 #define NVRAM_PARTITION_TYPE_LICENSE 0x900 7425 /* enum: Start of range used for PHY partitions (low 8 bits are the PHY ID) */ 7426 #define NVRAM_PARTITION_TYPE_PHY_MIN 0xa00 7427 /* enum: End of range used for PHY partitions (low 8 bits are the PHY ID) */ 7428 #define NVRAM_PARTITION_TYPE_PHY_MAX 0xaff 7429 /* enum: Primary FPGA partition */ 7430 #define NVRAM_PARTITION_TYPE_FPGA 0xb00 7431 /* enum: Secondary FPGA partition */ 7432 #define NVRAM_PARTITION_TYPE_FPGA_BACKUP 0xb01 7433 /* enum: FC firmware partition */ 7434 #define NVRAM_PARTITION_TYPE_FC_FIRMWARE 0xb02 7435 /* enum: FC License partition */ 7436 #define NVRAM_PARTITION_TYPE_FC_LICENSE 0xb03 7437 /* enum: Non-volatile log output partition for FC */ 7438 #define NVRAM_PARTITION_TYPE_FC_LOG 0xb04 7439 /* enum: MUM firmware partition */ 7440 #define NVRAM_PARTITION_TYPE_MUM_FIRMWARE 0xc00 7441 /* enum: MUM Non-volatile log output partition. */ 7442 #define NVRAM_PARTITION_TYPE_MUM_LOG 0xc01 7443 /* enum: MUM Application table partition. */ 7444 #define NVRAM_PARTITION_TYPE_MUM_APPTABLE 0xc02 7445 /* enum: MUM boot rom partition. */ 7446 #define NVRAM_PARTITION_TYPE_MUM_BOOT_ROM 0xc03 7447 /* enum: MUM production signatures & calibration rom partition. */ 7448 #define NVRAM_PARTITION_TYPE_MUM_PROD_ROM 0xc04 7449 /* enum: MUM user signatures & calibration rom partition. */ 7450 #define NVRAM_PARTITION_TYPE_MUM_USER_ROM 0xc05 7451 /* enum: MUM fuses and lockbits partition. */ 7452 #define NVRAM_PARTITION_TYPE_MUM_FUSELOCK 0xc06 7453 /* enum: Start of reserved value range (firmware may use for any purpose) */ 7454 #define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MIN 0xff00 7455 /* enum: End of reserved value range (firmware may use for any purpose) */ 7456 #define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MAX 0xfffd 7457 /* enum: Recovery partition map (provided if real map is missing or corrupt) */ 7458 #define NVRAM_PARTITION_TYPE_RECOVERY_MAP 0xfffe 7459 /* enum: Partition map (real map as stored in flash) */ 7460 #define NVRAM_PARTITION_TYPE_PARTITION_MAP 0xffff 7461 #define NVRAM_PARTITION_TYPE_ID_LBN 0 7462 #define NVRAM_PARTITION_TYPE_ID_WIDTH 16 7463 7464 /* LICENSED_APP_ID structuredef */ 7465 #define LICENSED_APP_ID_LEN 4 7466 #define LICENSED_APP_ID_ID_OFST 0 7467 /* enum: OpenOnload */ 7468 #define LICENSED_APP_ID_ONLOAD 0x1 7469 /* enum: PTP timestamping */ 7470 #define LICENSED_APP_ID_PTP 0x2 7471 /* enum: SolarCapture Pro */ 7472 #define LICENSED_APP_ID_SOLARCAPTURE_PRO 0x4 7473 /* enum: SolarSecure filter engine */ 7474 #define LICENSED_APP_ID_SOLARSECURE 0x8 7475 /* enum: Performance monitor */ 7476 #define LICENSED_APP_ID_PERF_MONITOR 0x10 7477 /* enum: SolarCapture Live */ 7478 #define LICENSED_APP_ID_SOLARCAPTURE_LIVE 0x20 7479 /* enum: Capture SolarSystem */ 7480 #define LICENSED_APP_ID_CAPTURE_SOLARSYSTEM 0x40 7481 /* enum: Network Access Control */ 7482 #define LICENSED_APP_ID_NETWORK_ACCESS_CONTROL 0x80 7483 #define LICENSED_APP_ID_ID_LBN 0 7484 #define LICENSED_APP_ID_ID_WIDTH 32 7485 7486 /* TX_TIMESTAMP_EVENT structuredef */ 7487 #define TX_TIMESTAMP_EVENT_LEN 6 7488 /* lower 16 bits of timestamp data */ 7489 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_OFST 0 7490 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_LEN 2 7491 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_LBN 0 7492 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_WIDTH 16 7493 /* Type of TX event, ordinary TX completion, low or high part of TX timestamp 7494 */ 7495 #define TX_TIMESTAMP_EVENT_TX_EV_TYPE_OFST 3 7496 #define TX_TIMESTAMP_EVENT_TX_EV_TYPE_LEN 1 7497 /* enum: This is a TX completion event, not a timestamp */ 7498 #define TX_TIMESTAMP_EVENT_TX_EV_COMPLETION 0x0 7499 /* enum: This is the low part of a TX timestamp event */ 7500 #define TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_LO 0x51 7501 /* enum: This is the high part of a TX timestamp event */ 7502 #define TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_HI 0x52 7503 #define TX_TIMESTAMP_EVENT_TX_EV_TYPE_LBN 24 7504 #define TX_TIMESTAMP_EVENT_TX_EV_TYPE_WIDTH 8 7505 /* upper 16 bits of timestamp data */ 7506 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_OFST 4 7507 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_LEN 2 7508 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_LBN 32 7509 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_WIDTH 16 7510 7511 /* RSS_MODE structuredef */ 7512 #define RSS_MODE_LEN 1 7513 /* The RSS mode for a particular packet type is a value from 0 - 15 which can 7514 * be considered as 4 bits selecting which fields are included in the hash. (A 7515 * value 0 effectively disables RSS spreading for the packet type.) The YAML 7516 * generation tools require this structure to be a whole number of bytes wide, 7517 * but only 4 bits are relevant. 7518 */ 7519 #define RSS_MODE_HASH_SELECTOR_OFST 0 7520 #define RSS_MODE_HASH_SELECTOR_LEN 1 7521 #define RSS_MODE_HASH_SRC_ADDR_LBN 0 7522 #define RSS_MODE_HASH_SRC_ADDR_WIDTH 1 7523 #define RSS_MODE_HASH_DST_ADDR_LBN 1 7524 #define RSS_MODE_HASH_DST_ADDR_WIDTH 1 7525 #define RSS_MODE_HASH_SRC_PORT_LBN 2 7526 #define RSS_MODE_HASH_SRC_PORT_WIDTH 1 7527 #define RSS_MODE_HASH_DST_PORT_LBN 3 7528 #define RSS_MODE_HASH_DST_PORT_WIDTH 1 7529 #define RSS_MODE_HASH_SELECTOR_LBN 0 7530 #define RSS_MODE_HASH_SELECTOR_WIDTH 8 7531 7532 7533 /***********************************/ 7534 /* MC_CMD_READ_REGS 7535 * Get a dump of the MCPU registers 7536 */ 7537 #define MC_CMD_READ_REGS 0x50 7538 #undef MC_CMD_0x50_PRIVILEGE_CTG 7539 7540 #define MC_CMD_0x50_PRIVILEGE_CTG SRIOV_CTG_ADMIN 7541 7542 /* MC_CMD_READ_REGS_IN msgrequest */ 7543 #define MC_CMD_READ_REGS_IN_LEN 0 7544 7545 /* MC_CMD_READ_REGS_OUT msgresponse */ 7546 #define MC_CMD_READ_REGS_OUT_LEN 308 7547 /* Whether the corresponding register entry contains a valid value */ 7548 #define MC_CMD_READ_REGS_OUT_MASK_OFST 0 7549 #define MC_CMD_READ_REGS_OUT_MASK_LEN 16 7550 /* Same order as MIPS GDB (r0-r31, sr, lo, hi, bad, cause, 32 x float, fsr, 7551 * fir, fp) 7552 */ 7553 #define MC_CMD_READ_REGS_OUT_REGS_OFST 16 7554 #define MC_CMD_READ_REGS_OUT_REGS_LEN 4 7555 #define MC_CMD_READ_REGS_OUT_REGS_NUM 73 7556 7557 7558 /***********************************/ 7559 /* MC_CMD_INIT_EVQ 7560 * Set up an event queue according to the supplied parameters. The IN arguments 7561 * end with an address for each 4k of host memory required to back the EVQ. 7562 */ 7563 #define MC_CMD_INIT_EVQ 0x80 7564 #undef MC_CMD_0x80_PRIVILEGE_CTG 7565 7566 #define MC_CMD_0x80_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7567 7568 /* MC_CMD_INIT_EVQ_IN msgrequest */ 7569 #define MC_CMD_INIT_EVQ_IN_LENMIN 44 7570 #define MC_CMD_INIT_EVQ_IN_LENMAX 548 7571 #define MC_CMD_INIT_EVQ_IN_LEN(num) (36+8*(num)) 7572 /* Size, in entries */ 7573 #define MC_CMD_INIT_EVQ_IN_SIZE_OFST 0 7574 /* Desired instance. Must be set to a specific instance, which is a function 7575 * local queue index. 7576 */ 7577 #define MC_CMD_INIT_EVQ_IN_INSTANCE_OFST 4 7578 /* The initial timer value. The load value is ignored if the timer mode is DIS. 7579 */ 7580 #define MC_CMD_INIT_EVQ_IN_TMR_LOAD_OFST 8 7581 /* The reload value is ignored in one-shot modes */ 7582 #define MC_CMD_INIT_EVQ_IN_TMR_RELOAD_OFST 12 7583 /* tbd */ 7584 #define MC_CMD_INIT_EVQ_IN_FLAGS_OFST 16 7585 #define MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_LBN 0 7586 #define MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_WIDTH 1 7587 #define MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_LBN 1 7588 #define MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_WIDTH 1 7589 #define MC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_LBN 2 7590 #define MC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_WIDTH 1 7591 #define MC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_LBN 3 7592 #define MC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_WIDTH 1 7593 #define MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_LBN 4 7594 #define MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_WIDTH 1 7595 #define MC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_LBN 5 7596 #define MC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_WIDTH 1 7597 #define MC_CMD_INIT_EVQ_IN_TMR_MODE_OFST 20 7598 /* enum: Disabled */ 7599 #define MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS 0x0 7600 /* enum: Immediate */ 7601 #define MC_CMD_INIT_EVQ_IN_TMR_IMMED_START 0x1 7602 /* enum: Triggered */ 7603 #define MC_CMD_INIT_EVQ_IN_TMR_TRIG_START 0x2 7604 /* enum: Hold-off */ 7605 #define MC_CMD_INIT_EVQ_IN_TMR_INT_HLDOFF 0x3 7606 /* Target EVQ for wakeups if in wakeup mode. */ 7607 #define MC_CMD_INIT_EVQ_IN_TARGET_EVQ_OFST 24 7608 /* Target interrupt if in interrupting mode (note union with target EVQ). Use 7609 * MC_CMD_RESOURCE_INSTANCE_ANY unless a specific one required for test 7610 * purposes. 7611 */ 7612 #define MC_CMD_INIT_EVQ_IN_IRQ_NUM_OFST 24 7613 /* Event Counter Mode. */ 7614 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_OFST 28 7615 /* enum: Disabled */ 7616 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS 0x0 7617 /* enum: Disabled */ 7618 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_RX 0x1 7619 /* enum: Disabled */ 7620 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_TX 0x2 7621 /* enum: Disabled */ 7622 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_RXTX 0x3 7623 /* Event queue packet count threshold. */ 7624 #define MC_CMD_INIT_EVQ_IN_COUNT_THRSHLD_OFST 32 7625 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 7626 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_OFST 36 7627 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LEN 8 7628 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LO_OFST 36 7629 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_HI_OFST 40 7630 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MINNUM 1 7631 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MAXNUM 64 7632 7633 /* MC_CMD_INIT_EVQ_OUT msgresponse */ 7634 #define MC_CMD_INIT_EVQ_OUT_LEN 4 7635 /* Only valid if INTRFLAG was true */ 7636 #define MC_CMD_INIT_EVQ_OUT_IRQ_OFST 0 7637 7638 /* QUEUE_CRC_MODE structuredef */ 7639 #define QUEUE_CRC_MODE_LEN 1 7640 #define QUEUE_CRC_MODE_MODE_LBN 0 7641 #define QUEUE_CRC_MODE_MODE_WIDTH 4 7642 /* enum: No CRC. */ 7643 #define QUEUE_CRC_MODE_NONE 0x0 7644 /* enum: CRC Fiber channel over ethernet. */ 7645 #define QUEUE_CRC_MODE_FCOE 0x1 7646 /* enum: CRC (digest) iSCSI header only. */ 7647 #define QUEUE_CRC_MODE_ISCSI_HDR 0x2 7648 /* enum: CRC (digest) iSCSI header and payload. */ 7649 #define QUEUE_CRC_MODE_ISCSI 0x3 7650 /* enum: CRC Fiber channel over IP over ethernet. */ 7651 #define QUEUE_CRC_MODE_FCOIPOE 0x4 7652 /* enum: CRC MPA. */ 7653 #define QUEUE_CRC_MODE_MPA 0x5 7654 #define QUEUE_CRC_MODE_SPARE_LBN 4 7655 #define QUEUE_CRC_MODE_SPARE_WIDTH 4 7656 7657 7658 /***********************************/ 7659 /* MC_CMD_INIT_RXQ 7660 * set up a receive queue according to the supplied parameters. The IN 7661 * arguments end with an address for each 4k of host memory required to back 7662 * the RXQ. 7663 */ 7664 #define MC_CMD_INIT_RXQ 0x81 7665 #undef MC_CMD_0x81_PRIVILEGE_CTG 7666 7667 #define MC_CMD_0x81_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7668 7669 /* MC_CMD_INIT_RXQ_IN msgrequest: Legacy RXQ_INIT request. Use extended version 7670 * in new code. 7671 */ 7672 #define MC_CMD_INIT_RXQ_IN_LENMIN 36 7673 #define MC_CMD_INIT_RXQ_IN_LENMAX 252 7674 #define MC_CMD_INIT_RXQ_IN_LEN(num) (28+8*(num)) 7675 /* Size, in entries */ 7676 #define MC_CMD_INIT_RXQ_IN_SIZE_OFST 0 7677 /* The EVQ to send events to. This is an index originally specified to INIT_EVQ 7678 */ 7679 #define MC_CMD_INIT_RXQ_IN_TARGET_EVQ_OFST 4 7680 /* The value to put in the event data. Check hardware spec. for valid range. */ 7681 #define MC_CMD_INIT_RXQ_IN_LABEL_OFST 8 7682 /* Desired instance. Must be set to a specific instance, which is a function 7683 * local queue index. 7684 */ 7685 #define MC_CMD_INIT_RXQ_IN_INSTANCE_OFST 12 7686 /* There will be more flags here. */ 7687 #define MC_CMD_INIT_RXQ_IN_FLAGS_OFST 16 7688 #define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_LBN 0 7689 #define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_WIDTH 1 7690 #define MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_LBN 1 7691 #define MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_WIDTH 1 7692 #define MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_LBN 2 7693 #define MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_WIDTH 1 7694 #define MC_CMD_INIT_RXQ_IN_CRC_MODE_LBN 3 7695 #define MC_CMD_INIT_RXQ_IN_CRC_MODE_WIDTH 4 7696 #define MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_LBN 7 7697 #define MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_WIDTH 1 7698 #define MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_LBN 8 7699 #define MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_WIDTH 1 7700 #define MC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_LBN 9 7701 #define MC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_WIDTH 1 7702 /* Owner ID to use if in buffer mode (zero if physical) */ 7703 #define MC_CMD_INIT_RXQ_IN_OWNER_ID_OFST 20 7704 /* The port ID associated with the v-adaptor which should contain this DMAQ. */ 7705 #define MC_CMD_INIT_RXQ_IN_PORT_ID_OFST 24 7706 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 7707 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_OFST 28 7708 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LEN 8 7709 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LO_OFST 28 7710 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_HI_OFST 32 7711 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MINNUM 1 7712 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MAXNUM 28 7713 7714 /* MC_CMD_INIT_RXQ_EXT_IN msgrequest: Extended RXQ_INIT with additional mode 7715 * flags 7716 */ 7717 #define MC_CMD_INIT_RXQ_EXT_IN_LEN 544 7718 /* Size, in entries */ 7719 #define MC_CMD_INIT_RXQ_EXT_IN_SIZE_OFST 0 7720 /* The EVQ to send events to. This is an index originally specified to INIT_EVQ 7721 */ 7722 #define MC_CMD_INIT_RXQ_EXT_IN_TARGET_EVQ_OFST 4 7723 /* The value to put in the event data. Check hardware spec. for valid range. */ 7724 #define MC_CMD_INIT_RXQ_EXT_IN_LABEL_OFST 8 7725 /* Desired instance. Must be set to a specific instance, which is a function 7726 * local queue index. 7727 */ 7728 #define MC_CMD_INIT_RXQ_EXT_IN_INSTANCE_OFST 12 7729 /* There will be more flags here. */ 7730 #define MC_CMD_INIT_RXQ_EXT_IN_FLAGS_OFST 16 7731 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_LBN 0 7732 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_WIDTH 1 7733 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT_LBN 1 7734 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT_WIDTH 1 7735 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_TIMESTAMP_LBN 2 7736 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_TIMESTAMP_WIDTH 1 7737 #define MC_CMD_INIT_RXQ_EXT_IN_CRC_MODE_LBN 3 7738 #define MC_CMD_INIT_RXQ_EXT_IN_CRC_MODE_WIDTH 4 7739 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_CHAIN_LBN 7 7740 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_CHAIN_WIDTH 1 7741 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_PREFIX_LBN 8 7742 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_PREFIX_WIDTH 1 7743 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER_LBN 9 7744 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER_WIDTH 1 7745 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_LBN 10 7746 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_WIDTH 4 7747 /* enum: One packet per descriptor (for normal networking) */ 7748 #define MC_CMD_INIT_RXQ_EXT_IN_SINGLE_PACKET 0x0 7749 /* enum: Pack multiple packets into large descriptors (for SolarCapture) */ 7750 #define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM 0x1 7751 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_LBN 14 7752 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_WIDTH 1 7753 #define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE_LBN 15 7754 #define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE_WIDTH 3 7755 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_1M 0x0 /* enum */ 7756 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_512K 0x1 /* enum */ 7757 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_256K 0x2 /* enum */ 7758 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_128K 0x3 /* enum */ 7759 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_64K 0x4 /* enum */ 7760 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES_LBN 18 7761 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 1 7762 /* Owner ID to use if in buffer mode (zero if physical) */ 7763 #define MC_CMD_INIT_RXQ_EXT_IN_OWNER_ID_OFST 20 7764 /* The port ID associated with the v-adaptor which should contain this DMAQ. */ 7765 #define MC_CMD_INIT_RXQ_EXT_IN_PORT_ID_OFST 24 7766 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 7767 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_OFST 28 7768 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LEN 8 7769 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LO_OFST 28 7770 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_HI_OFST 32 7771 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_NUM 64 7772 /* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */ 7773 #define MC_CMD_INIT_RXQ_EXT_IN_SNAPSHOT_LENGTH_OFST 540 7774 7775 /* MC_CMD_INIT_RXQ_OUT msgresponse */ 7776 #define MC_CMD_INIT_RXQ_OUT_LEN 0 7777 7778 /* MC_CMD_INIT_RXQ_EXT_OUT msgresponse */ 7779 #define MC_CMD_INIT_RXQ_EXT_OUT_LEN 0 7780 7781 7782 /***********************************/ 7783 /* MC_CMD_INIT_TXQ 7784 */ 7785 #define MC_CMD_INIT_TXQ 0x82 7786 #undef MC_CMD_0x82_PRIVILEGE_CTG 7787 7788 #define MC_CMD_0x82_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7789 7790 /* MC_CMD_INIT_TXQ_IN msgrequest: Legacy INIT_TXQ request. Use extended version 7791 * in new code. 7792 */ 7793 #define MC_CMD_INIT_TXQ_IN_LENMIN 36 7794 #define MC_CMD_INIT_TXQ_IN_LENMAX 252 7795 #define MC_CMD_INIT_TXQ_IN_LEN(num) (28+8*(num)) 7796 /* Size, in entries */ 7797 #define MC_CMD_INIT_TXQ_IN_SIZE_OFST 0 7798 /* The EVQ to send events to. This is an index originally specified to 7799 * INIT_EVQ. 7800 */ 7801 #define MC_CMD_INIT_TXQ_IN_TARGET_EVQ_OFST 4 7802 /* The value to put in the event data. Check hardware spec. for valid range. */ 7803 #define MC_CMD_INIT_TXQ_IN_LABEL_OFST 8 7804 /* Desired instance. Must be set to a specific instance, which is a function 7805 * local queue index. 7806 */ 7807 #define MC_CMD_INIT_TXQ_IN_INSTANCE_OFST 12 7808 /* There will be more flags here. */ 7809 #define MC_CMD_INIT_TXQ_IN_FLAGS_OFST 16 7810 #define MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_LBN 0 7811 #define MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_WIDTH 1 7812 #define MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_LBN 1 7813 #define MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_WIDTH 1 7814 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_LBN 2 7815 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_WIDTH 1 7816 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_LBN 3 7817 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_WIDTH 1 7818 #define MC_CMD_INIT_TXQ_IN_CRC_MODE_LBN 4 7819 #define MC_CMD_INIT_TXQ_IN_CRC_MODE_WIDTH 4 7820 #define MC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_LBN 8 7821 #define MC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_WIDTH 1 7822 #define MC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_LBN 9 7823 #define MC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_WIDTH 1 7824 #define MC_CMD_INIT_TXQ_IN_FLAG_INNER_IP_CSUM_EN_LBN 10 7825 #define MC_CMD_INIT_TXQ_IN_FLAG_INNER_IP_CSUM_EN_WIDTH 1 7826 #define MC_CMD_INIT_TXQ_IN_FLAG_INNER_TCP_CSUM_EN_LBN 11 7827 #define MC_CMD_INIT_TXQ_IN_FLAG_INNER_TCP_CSUM_EN_WIDTH 1 7828 /* Owner ID to use if in buffer mode (zero if physical) */ 7829 #define MC_CMD_INIT_TXQ_IN_OWNER_ID_OFST 20 7830 /* The port ID associated with the v-adaptor which should contain this DMAQ. */ 7831 #define MC_CMD_INIT_TXQ_IN_PORT_ID_OFST 24 7832 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 7833 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_OFST 28 7834 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LEN 8 7835 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LO_OFST 28 7836 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_HI_OFST 32 7837 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MINNUM 1 7838 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MAXNUM 28 7839 7840 /* MC_CMD_INIT_TXQ_EXT_IN msgrequest: Extended INIT_TXQ with additional mode 7841 * flags 7842 */ 7843 #define MC_CMD_INIT_TXQ_EXT_IN_LEN 544 7844 /* Size, in entries */ 7845 #define MC_CMD_INIT_TXQ_EXT_IN_SIZE_OFST 0 7846 /* The EVQ to send events to. This is an index originally specified to 7847 * INIT_EVQ. 7848 */ 7849 #define MC_CMD_INIT_TXQ_EXT_IN_TARGET_EVQ_OFST 4 7850 /* The value to put in the event data. Check hardware spec. for valid range. */ 7851 #define MC_CMD_INIT_TXQ_EXT_IN_LABEL_OFST 8 7852 /* Desired instance. Must be set to a specific instance, which is a function 7853 * local queue index. 7854 */ 7855 #define MC_CMD_INIT_TXQ_EXT_IN_INSTANCE_OFST 12 7856 /* There will be more flags here. */ 7857 #define MC_CMD_INIT_TXQ_EXT_IN_FLAGS_OFST 16 7858 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_BUFF_MODE_LBN 0 7859 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_BUFF_MODE_WIDTH 1 7860 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_IP_CSUM_DIS_LBN 1 7861 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_IP_CSUM_DIS_WIDTH 1 7862 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_CSUM_DIS_LBN 2 7863 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_CSUM_DIS_WIDTH 1 7864 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_UDP_ONLY_LBN 3 7865 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_UDP_ONLY_WIDTH 1 7866 #define MC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_LBN 4 7867 #define MC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_WIDTH 4 7868 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TIMESTAMP_LBN 8 7869 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TIMESTAMP_WIDTH 1 7870 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_PACER_BYPASS_LBN 9 7871 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_PACER_BYPASS_WIDTH 1 7872 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN_LBN 10 7873 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN_WIDTH 1 7874 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN_LBN 11 7875 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN_WIDTH 1 7876 /* Owner ID to use if in buffer mode (zero if physical) */ 7877 #define MC_CMD_INIT_TXQ_EXT_IN_OWNER_ID_OFST 20 7878 /* The port ID associated with the v-adaptor which should contain this DMAQ. */ 7879 #define MC_CMD_INIT_TXQ_EXT_IN_PORT_ID_OFST 24 7880 /* 64-bit address of 4k of 4k-aligned host memory buffer */ 7881 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_OFST 28 7882 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LEN 8 7883 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LO_OFST 28 7884 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_HI_OFST 32 7885 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MINNUM 1 7886 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MAXNUM 64 7887 /* Flags related to Qbb flow control mode. */ 7888 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_FLAGS_OFST 540 7889 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_ENABLE_LBN 0 7890 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_ENABLE_WIDTH 1 7891 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_PRIORITY_LBN 1 7892 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_PRIORITY_WIDTH 3 7893 7894 /* MC_CMD_INIT_TXQ_OUT msgresponse */ 7895 #define MC_CMD_INIT_TXQ_OUT_LEN 0 7896 7897 7898 /***********************************/ 7899 /* MC_CMD_FINI_EVQ 7900 * Teardown an EVQ. 7901 * 7902 * All DMAQs or EVQs that point to the EVQ to tear down must be torn down first 7903 * or the operation will fail with EBUSY 7904 */ 7905 #define MC_CMD_FINI_EVQ 0x83 7906 #undef MC_CMD_0x83_PRIVILEGE_CTG 7907 7908 #define MC_CMD_0x83_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7909 7910 /* MC_CMD_FINI_EVQ_IN msgrequest */ 7911 #define MC_CMD_FINI_EVQ_IN_LEN 4 7912 /* Instance of EVQ to destroy. Should be the same instance as that previously 7913 * passed to INIT_EVQ 7914 */ 7915 #define MC_CMD_FINI_EVQ_IN_INSTANCE_OFST 0 7916 7917 /* MC_CMD_FINI_EVQ_OUT msgresponse */ 7918 #define MC_CMD_FINI_EVQ_OUT_LEN 0 7919 7920 7921 /***********************************/ 7922 /* MC_CMD_FINI_RXQ 7923 * Teardown a RXQ. 7924 */ 7925 #define MC_CMD_FINI_RXQ 0x84 7926 #undef MC_CMD_0x84_PRIVILEGE_CTG 7927 7928 #define MC_CMD_0x84_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7929 7930 /* MC_CMD_FINI_RXQ_IN msgrequest */ 7931 #define MC_CMD_FINI_RXQ_IN_LEN 4 7932 /* Instance of RXQ to destroy */ 7933 #define MC_CMD_FINI_RXQ_IN_INSTANCE_OFST 0 7934 7935 /* MC_CMD_FINI_RXQ_OUT msgresponse */ 7936 #define MC_CMD_FINI_RXQ_OUT_LEN 0 7937 7938 7939 /***********************************/ 7940 /* MC_CMD_FINI_TXQ 7941 * Teardown a TXQ. 7942 */ 7943 #define MC_CMD_FINI_TXQ 0x85 7944 #undef MC_CMD_0x85_PRIVILEGE_CTG 7945 7946 #define MC_CMD_0x85_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7947 7948 /* MC_CMD_FINI_TXQ_IN msgrequest */ 7949 #define MC_CMD_FINI_TXQ_IN_LEN 4 7950 /* Instance of TXQ to destroy */ 7951 #define MC_CMD_FINI_TXQ_IN_INSTANCE_OFST 0 7952 7953 /* MC_CMD_FINI_TXQ_OUT msgresponse */ 7954 #define MC_CMD_FINI_TXQ_OUT_LEN 0 7955 7956 7957 /***********************************/ 7958 /* MC_CMD_DRIVER_EVENT 7959 * Generate an event on an EVQ belonging to the function issuing the command. 7960 */ 7961 #define MC_CMD_DRIVER_EVENT 0x86 7962 #undef MC_CMD_0x86_PRIVILEGE_CTG 7963 7964 #define MC_CMD_0x86_PRIVILEGE_CTG SRIOV_CTG_GENERAL 7965 7966 /* MC_CMD_DRIVER_EVENT_IN msgrequest */ 7967 #define MC_CMD_DRIVER_EVENT_IN_LEN 12 7968 /* Handle of target EVQ */ 7969 #define MC_CMD_DRIVER_EVENT_IN_EVQ_OFST 0 7970 /* Bits 0 - 63 of event */ 7971 #define MC_CMD_DRIVER_EVENT_IN_DATA_OFST 4 7972 #define MC_CMD_DRIVER_EVENT_IN_DATA_LEN 8 7973 #define MC_CMD_DRIVER_EVENT_IN_DATA_LO_OFST 4 7974 #define MC_CMD_DRIVER_EVENT_IN_DATA_HI_OFST 8 7975 7976 /* MC_CMD_DRIVER_EVENT_OUT msgresponse */ 7977 #define MC_CMD_DRIVER_EVENT_OUT_LEN 0 7978 7979 7980 /***********************************/ 7981 /* MC_CMD_PROXY_CMD 7982 * Execute an arbitrary MCDI command on behalf of a different function, subject 7983 * to security restrictions. The command to be proxied follows immediately 7984 * afterward in the host buffer (or on the UART). This command supercedes 7985 * MC_CMD_SET_FUNC, which remains available for Siena but now deprecated. 7986 */ 7987 #define MC_CMD_PROXY_CMD 0x5b 7988 #undef MC_CMD_0x5b_PRIVILEGE_CTG 7989 7990 #define MC_CMD_0x5b_PRIVILEGE_CTG SRIOV_CTG_ADMIN 7991 7992 /* MC_CMD_PROXY_CMD_IN msgrequest */ 7993 #define MC_CMD_PROXY_CMD_IN_LEN 4 7994 /* The handle of the target function. */ 7995 #define MC_CMD_PROXY_CMD_IN_TARGET_OFST 0 7996 #define MC_CMD_PROXY_CMD_IN_TARGET_PF_LBN 0 7997 #define MC_CMD_PROXY_CMD_IN_TARGET_PF_WIDTH 16 7998 #define MC_CMD_PROXY_CMD_IN_TARGET_VF_LBN 16 7999 #define MC_CMD_PROXY_CMD_IN_TARGET_VF_WIDTH 16 8000 #define MC_CMD_PROXY_CMD_IN_VF_NULL 0xffff /* enum */ 8001 8002 /* MC_CMD_PROXY_CMD_OUT msgresponse */ 8003 #define MC_CMD_PROXY_CMD_OUT_LEN 0 8004 8005 /* MC_PROXY_STATUS_BUFFER structuredef: Host memory status buffer used to 8006 * manage proxied requests 8007 */ 8008 #define MC_PROXY_STATUS_BUFFER_LEN 16 8009 /* Handle allocated by the firmware for this proxy transaction */ 8010 #define MC_PROXY_STATUS_BUFFER_HANDLE_OFST 0 8011 /* enum: An invalid handle. */ 8012 #define MC_PROXY_STATUS_BUFFER_HANDLE_INVALID 0x0 8013 #define MC_PROXY_STATUS_BUFFER_HANDLE_LBN 0 8014 #define MC_PROXY_STATUS_BUFFER_HANDLE_WIDTH 32 8015 /* The requesting physical function number */ 8016 #define MC_PROXY_STATUS_BUFFER_PF_OFST 4 8017 #define MC_PROXY_STATUS_BUFFER_PF_LEN 2 8018 #define MC_PROXY_STATUS_BUFFER_PF_LBN 32 8019 #define MC_PROXY_STATUS_BUFFER_PF_WIDTH 16 8020 /* The requesting virtual function number. Set to VF_NULL if the target is a 8021 * PF. 8022 */ 8023 #define MC_PROXY_STATUS_BUFFER_VF_OFST 6 8024 #define MC_PROXY_STATUS_BUFFER_VF_LEN 2 8025 #define MC_PROXY_STATUS_BUFFER_VF_LBN 48 8026 #define MC_PROXY_STATUS_BUFFER_VF_WIDTH 16 8027 /* The target function RID. */ 8028 #define MC_PROXY_STATUS_BUFFER_RID_OFST 8 8029 #define MC_PROXY_STATUS_BUFFER_RID_LEN 2 8030 #define MC_PROXY_STATUS_BUFFER_RID_LBN 64 8031 #define MC_PROXY_STATUS_BUFFER_RID_WIDTH 16 8032 /* The status of the proxy as described in MC_CMD_PROXY_COMPLETE. */ 8033 #define MC_PROXY_STATUS_BUFFER_STATUS_OFST 10 8034 #define MC_PROXY_STATUS_BUFFER_STATUS_LEN 2 8035 #define MC_PROXY_STATUS_BUFFER_STATUS_LBN 80 8036 #define MC_PROXY_STATUS_BUFFER_STATUS_WIDTH 16 8037 /* If a request is authorized rather than carried out by the host, this is the 8038 * elevated privilege mask granted to the requesting function. 8039 */ 8040 #define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_OFST 12 8041 #define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_LBN 96 8042 #define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_WIDTH 32 8043 8044 8045 /***********************************/ 8046 /* MC_CMD_PROXY_CONFIGURE 8047 * Enable/disable authorization of MCDI requests from unprivileged functions by 8048 * a designated admin function 8049 */ 8050 #define MC_CMD_PROXY_CONFIGURE 0x58 8051 #undef MC_CMD_0x58_PRIVILEGE_CTG 8052 8053 #define MC_CMD_0x58_PRIVILEGE_CTG SRIOV_CTG_ADMIN 8054 8055 /* MC_CMD_PROXY_CONFIGURE_IN msgrequest */ 8056 #define MC_CMD_PROXY_CONFIGURE_IN_LEN 108 8057 #define MC_CMD_PROXY_CONFIGURE_IN_FLAGS_OFST 0 8058 #define MC_CMD_PROXY_CONFIGURE_IN_ENABLE_LBN 0 8059 #define MC_CMD_PROXY_CONFIGURE_IN_ENABLE_WIDTH 1 8060 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 8061 * of blocks, each of the size REQUEST_BLOCK_SIZE. 8062 */ 8063 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_OFST 4 8064 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LEN 8 8065 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LO_OFST 4 8066 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_HI_OFST 8 8067 /* Must be a power of 2 */ 8068 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BLOCK_SIZE_OFST 12 8069 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 8070 * of blocks, each of the size REPLY_BLOCK_SIZE. 8071 */ 8072 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_OFST 16 8073 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LEN 8 8074 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LO_OFST 16 8075 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_HI_OFST 20 8076 /* Must be a power of 2 */ 8077 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BLOCK_SIZE_OFST 24 8078 /* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS 8079 * of blocks, each of the size STATUS_BLOCK_SIZE. This buffer is only needed if 8080 * host intends to complete proxied operations by using MC_CMD_PROXY_CMD. 8081 */ 8082 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_OFST 28 8083 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LEN 8 8084 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LO_OFST 28 8085 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_HI_OFST 32 8086 /* Must be a power of 2, or zero if this buffer is not provided */ 8087 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BLOCK_SIZE_OFST 36 8088 /* Applies to all three buffers */ 8089 #define MC_CMD_PROXY_CONFIGURE_IN_NUM_BLOCKS_OFST 40 8090 /* A bit mask defining which MCDI operations may be proxied */ 8091 #define MC_CMD_PROXY_CONFIGURE_IN_ALLOWED_MCDI_MASK_OFST 44 8092 #define MC_CMD_PROXY_CONFIGURE_IN_ALLOWED_MCDI_MASK_LEN 64 8093 8094 /* MC_CMD_PROXY_CONFIGURE_OUT msgresponse */ 8095 #define MC_CMD_PROXY_CONFIGURE_OUT_LEN 0 8096 8097 8098 /***********************************/ 8099 /* MC_CMD_PROXY_COMPLETE 8100 * Tells FW that a requested proxy operation has either been completed (by 8101 * using MC_CMD_PROXY_CMD) or authorized/declined. May only be sent by the 8102 * function that enabled proxying/authorization (by using 8103 * MC_CMD_PROXY_CONFIGURE). 8104 */ 8105 #define MC_CMD_PROXY_COMPLETE 0x5f 8106 #undef MC_CMD_0x5f_PRIVILEGE_CTG 8107 8108 #define MC_CMD_0x5f_PRIVILEGE_CTG SRIOV_CTG_ADMIN 8109 8110 /* MC_CMD_PROXY_COMPLETE_IN msgrequest */ 8111 #define MC_CMD_PROXY_COMPLETE_IN_LEN 12 8112 #define MC_CMD_PROXY_COMPLETE_IN_BLOCK_INDEX_OFST 0 8113 #define MC_CMD_PROXY_COMPLETE_IN_STATUS_OFST 4 8114 /* enum: The operation has been completed by using MC_CMD_PROXY_CMD, the reply 8115 * is stored in the REPLY_BUFF. 8116 */ 8117 #define MC_CMD_PROXY_COMPLETE_IN_COMPLETE 0x0 8118 /* enum: The operation has been authorized. The originating function may now 8119 * try again. 8120 */ 8121 #define MC_CMD_PROXY_COMPLETE_IN_AUTHORIZED 0x1 8122 /* enum: The operation has been declined. */ 8123 #define MC_CMD_PROXY_COMPLETE_IN_DECLINED 0x2 8124 /* enum: The authorization failed because the relevant application did not 8125 * respond in time. 8126 */ 8127 #define MC_CMD_PROXY_COMPLETE_IN_TIMEDOUT 0x3 8128 #define MC_CMD_PROXY_COMPLETE_IN_HANDLE_OFST 8 8129 8130 /* MC_CMD_PROXY_COMPLETE_OUT msgresponse */ 8131 #define MC_CMD_PROXY_COMPLETE_OUT_LEN 0 8132 8133 8134 /***********************************/ 8135 /* MC_CMD_ALLOC_BUFTBL_CHUNK 8136 * Allocate a set of buffer table entries using the specified owner ID. This 8137 * operation allocates the required buffer table entries (and fails if it 8138 * cannot do so). The buffer table entries will initially be zeroed. 8139 */ 8140 #define MC_CMD_ALLOC_BUFTBL_CHUNK 0x87 8141 #undef MC_CMD_0x87_PRIVILEGE_CTG 8142 8143 #define MC_CMD_0x87_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 8144 8145 /* MC_CMD_ALLOC_BUFTBL_CHUNK_IN msgrequest */ 8146 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_LEN 8 8147 /* Owner ID to use */ 8148 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_OWNER_OFST 0 8149 /* Size of buffer table pages to use, in bytes (note that only a few values are 8150 * legal on any specific hardware). 8151 */ 8152 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_PAGE_SIZE_OFST 4 8153 8154 /* MC_CMD_ALLOC_BUFTBL_CHUNK_OUT msgresponse */ 8155 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_LEN 12 8156 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_HANDLE_OFST 0 8157 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_NUMENTRIES_OFST 4 8158 /* Buffer table IDs for use in DMA descriptors. */ 8159 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_ID_OFST 8 8160 8161 8162 /***********************************/ 8163 /* MC_CMD_PROGRAM_BUFTBL_ENTRIES 8164 * Reprogram a set of buffer table entries in the specified chunk. 8165 */ 8166 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES 0x88 8167 #undef MC_CMD_0x88_PRIVILEGE_CTG 8168 8169 #define MC_CMD_0x88_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 8170 8171 /* MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN msgrequest */ 8172 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMIN 20 8173 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMAX 268 8174 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LEN(num) (12+8*(num)) 8175 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_HANDLE_OFST 0 8176 /* ID */ 8177 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_FIRSTID_OFST 4 8178 /* Num entries */ 8179 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_NUMENTRIES_OFST 8 8180 /* Buffer table entry address */ 8181 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_OFST 12 8182 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LEN 8 8183 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LO_OFST 12 8184 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_HI_OFST 16 8185 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MINNUM 1 8186 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MAXNUM 32 8187 8188 /* MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT msgresponse */ 8189 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT_LEN 0 8190 8191 8192 /***********************************/ 8193 /* MC_CMD_FREE_BUFTBL_CHUNK 8194 */ 8195 #define MC_CMD_FREE_BUFTBL_CHUNK 0x89 8196 #undef MC_CMD_0x89_PRIVILEGE_CTG 8197 8198 #define MC_CMD_0x89_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 8199 8200 /* MC_CMD_FREE_BUFTBL_CHUNK_IN msgrequest */ 8201 #define MC_CMD_FREE_BUFTBL_CHUNK_IN_LEN 4 8202 #define MC_CMD_FREE_BUFTBL_CHUNK_IN_HANDLE_OFST 0 8203 8204 /* MC_CMD_FREE_BUFTBL_CHUNK_OUT msgresponse */ 8205 #define MC_CMD_FREE_BUFTBL_CHUNK_OUT_LEN 0 8206 8207 /* PORT_CONFIG_ENTRY structuredef */ 8208 #define PORT_CONFIG_ENTRY_LEN 16 8209 /* External port number (label) */ 8210 #define PORT_CONFIG_ENTRY_EXT_NUMBER_OFST 0 8211 #define PORT_CONFIG_ENTRY_EXT_NUMBER_LEN 1 8212 #define PORT_CONFIG_ENTRY_EXT_NUMBER_LBN 0 8213 #define PORT_CONFIG_ENTRY_EXT_NUMBER_WIDTH 8 8214 /* Port core location */ 8215 #define PORT_CONFIG_ENTRY_CORE_OFST 1 8216 #define PORT_CONFIG_ENTRY_CORE_LEN 1 8217 #define PORT_CONFIG_ENTRY_STANDALONE 0x0 /* enum */ 8218 #define PORT_CONFIG_ENTRY_MASTER 0x1 /* enum */ 8219 #define PORT_CONFIG_ENTRY_SLAVE 0x2 /* enum */ 8220 #define PORT_CONFIG_ENTRY_CORE_LBN 8 8221 #define PORT_CONFIG_ENTRY_CORE_WIDTH 8 8222 /* Internal number (HW resource) relative to the core */ 8223 #define PORT_CONFIG_ENTRY_INT_NUMBER_OFST 2 8224 #define PORT_CONFIG_ENTRY_INT_NUMBER_LEN 1 8225 #define PORT_CONFIG_ENTRY_INT_NUMBER_LBN 16 8226 #define PORT_CONFIG_ENTRY_INT_NUMBER_WIDTH 8 8227 /* Reserved */ 8228 #define PORT_CONFIG_ENTRY_RSVD_OFST 3 8229 #define PORT_CONFIG_ENTRY_RSVD_LEN 1 8230 #define PORT_CONFIG_ENTRY_RSVD_LBN 24 8231 #define PORT_CONFIG_ENTRY_RSVD_WIDTH 8 8232 /* Bitmask of KR lanes used by the port */ 8233 #define PORT_CONFIG_ENTRY_LANES_OFST 4 8234 #define PORT_CONFIG_ENTRY_LANES_LBN 32 8235 #define PORT_CONFIG_ENTRY_LANES_WIDTH 32 8236 /* Port capabilities (MC_CMD_PHY_CAP_*) */ 8237 #define PORT_CONFIG_ENTRY_SUPPORTED_CAPS_OFST 8 8238 #define PORT_CONFIG_ENTRY_SUPPORTED_CAPS_LBN 64 8239 #define PORT_CONFIG_ENTRY_SUPPORTED_CAPS_WIDTH 32 8240 /* Reserved (align to 16 bytes) */ 8241 #define PORT_CONFIG_ENTRY_RSVD2_OFST 12 8242 #define PORT_CONFIG_ENTRY_RSVD2_LBN 96 8243 #define PORT_CONFIG_ENTRY_RSVD2_WIDTH 32 8244 8245 8246 /***********************************/ 8247 /* MC_CMD_FILTER_OP 8248 * Multiplexed MCDI call for filter operations 8249 */ 8250 #define MC_CMD_FILTER_OP 0x8a 8251 #undef MC_CMD_0x8a_PRIVILEGE_CTG 8252 8253 #define MC_CMD_0x8a_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8254 8255 /* MC_CMD_FILTER_OP_IN msgrequest */ 8256 #define MC_CMD_FILTER_OP_IN_LEN 108 8257 /* identifies the type of operation requested */ 8258 #define MC_CMD_FILTER_OP_IN_OP_OFST 0 8259 /* enum: single-recipient filter insert */ 8260 #define MC_CMD_FILTER_OP_IN_OP_INSERT 0x0 8261 /* enum: single-recipient filter remove */ 8262 #define MC_CMD_FILTER_OP_IN_OP_REMOVE 0x1 8263 /* enum: multi-recipient filter subscribe */ 8264 #define MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE 0x2 8265 /* enum: multi-recipient filter unsubscribe */ 8266 #define MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE 0x3 8267 /* enum: replace one recipient with another (warning - the filter handle may 8268 * change) 8269 */ 8270 #define MC_CMD_FILTER_OP_IN_OP_REPLACE 0x4 8271 /* filter handle (for remove / unsubscribe operations) */ 8272 #define MC_CMD_FILTER_OP_IN_HANDLE_OFST 4 8273 #define MC_CMD_FILTER_OP_IN_HANDLE_LEN 8 8274 #define MC_CMD_FILTER_OP_IN_HANDLE_LO_OFST 4 8275 #define MC_CMD_FILTER_OP_IN_HANDLE_HI_OFST 8 8276 /* The port ID associated with the v-adaptor which should contain this filter. 8277 */ 8278 #define MC_CMD_FILTER_OP_IN_PORT_ID_OFST 12 8279 /* fields to include in match criteria */ 8280 #define MC_CMD_FILTER_OP_IN_MATCH_FIELDS_OFST 16 8281 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_LBN 0 8282 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_WIDTH 1 8283 #define MC_CMD_FILTER_OP_IN_MATCH_DST_IP_LBN 1 8284 #define MC_CMD_FILTER_OP_IN_MATCH_DST_IP_WIDTH 1 8285 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_LBN 2 8286 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_WIDTH 1 8287 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_LBN 3 8288 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_WIDTH 1 8289 #define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_LBN 4 8290 #define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_WIDTH 1 8291 #define MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_LBN 5 8292 #define MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_WIDTH 1 8293 #define MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_LBN 6 8294 #define MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_WIDTH 1 8295 #define MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_LBN 7 8296 #define MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_WIDTH 1 8297 #define MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_LBN 8 8298 #define MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_WIDTH 1 8299 #define MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_LBN 9 8300 #define MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_WIDTH 1 8301 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_LBN 10 8302 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_WIDTH 1 8303 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_LBN 11 8304 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_WIDTH 1 8305 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN 30 8306 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1 8307 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN 31 8308 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1 8309 /* receive destination */ 8310 #define MC_CMD_FILTER_OP_IN_RX_DEST_OFST 20 8311 /* enum: drop packets */ 8312 #define MC_CMD_FILTER_OP_IN_RX_DEST_DROP 0x0 8313 /* enum: receive to host */ 8314 #define MC_CMD_FILTER_OP_IN_RX_DEST_HOST 0x1 8315 /* enum: receive to MC */ 8316 #define MC_CMD_FILTER_OP_IN_RX_DEST_MC 0x2 8317 /* enum: loop back to TXDP 0 */ 8318 #define MC_CMD_FILTER_OP_IN_RX_DEST_TX0 0x3 8319 /* enum: loop back to TXDP 1 */ 8320 #define MC_CMD_FILTER_OP_IN_RX_DEST_TX1 0x4 8321 /* receive queue handle (for multiple queue modes, this is the base queue) */ 8322 #define MC_CMD_FILTER_OP_IN_RX_QUEUE_OFST 24 8323 /* receive mode */ 8324 #define MC_CMD_FILTER_OP_IN_RX_MODE_OFST 28 8325 /* enum: receive to just the specified queue */ 8326 #define MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE 0x0 8327 /* enum: receive to multiple queues using RSS context */ 8328 #define MC_CMD_FILTER_OP_IN_RX_MODE_RSS 0x1 8329 /* enum: receive to multiple queues using .1p mapping */ 8330 #define MC_CMD_FILTER_OP_IN_RX_MODE_DOT1P_MAPPING 0x2 8331 /* enum: install a filter entry that will never match; for test purposes only 8332 */ 8333 #define MC_CMD_FILTER_OP_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000 8334 /* RSS context (for RX_MODE_RSS) or .1p mapping handle (for 8335 * RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or 8336 * MC_CMD_DOT1P_MAPPING_ALLOC. 8337 */ 8338 #define MC_CMD_FILTER_OP_IN_RX_CONTEXT_OFST 32 8339 /* transmit domain (reserved; set to 0) */ 8340 #define MC_CMD_FILTER_OP_IN_TX_DOMAIN_OFST 36 8341 /* transmit destination (either set the MAC and/or PM bits for explicit 8342 * control, or set this field to TX_DEST_DEFAULT for sensible default 8343 * behaviour) 8344 */ 8345 #define MC_CMD_FILTER_OP_IN_TX_DEST_OFST 40 8346 /* enum: request default behaviour (based on filter type) */ 8347 #define MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT 0xffffffff 8348 #define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_LBN 0 8349 #define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_WIDTH 1 8350 #define MC_CMD_FILTER_OP_IN_TX_DEST_PM_LBN 1 8351 #define MC_CMD_FILTER_OP_IN_TX_DEST_PM_WIDTH 1 8352 /* source MAC address to match (as bytes in network order) */ 8353 #define MC_CMD_FILTER_OP_IN_SRC_MAC_OFST 44 8354 #define MC_CMD_FILTER_OP_IN_SRC_MAC_LEN 6 8355 /* source port to match (as bytes in network order) */ 8356 #define MC_CMD_FILTER_OP_IN_SRC_PORT_OFST 50 8357 #define MC_CMD_FILTER_OP_IN_SRC_PORT_LEN 2 8358 /* destination MAC address to match (as bytes in network order) */ 8359 #define MC_CMD_FILTER_OP_IN_DST_MAC_OFST 52 8360 #define MC_CMD_FILTER_OP_IN_DST_MAC_LEN 6 8361 /* destination port to match (as bytes in network order) */ 8362 #define MC_CMD_FILTER_OP_IN_DST_PORT_OFST 58 8363 #define MC_CMD_FILTER_OP_IN_DST_PORT_LEN 2 8364 /* Ethernet type to match (as bytes in network order) */ 8365 #define MC_CMD_FILTER_OP_IN_ETHER_TYPE_OFST 60 8366 #define MC_CMD_FILTER_OP_IN_ETHER_TYPE_LEN 2 8367 /* Inner VLAN tag to match (as bytes in network order) */ 8368 #define MC_CMD_FILTER_OP_IN_INNER_VLAN_OFST 62 8369 #define MC_CMD_FILTER_OP_IN_INNER_VLAN_LEN 2 8370 /* Outer VLAN tag to match (as bytes in network order) */ 8371 #define MC_CMD_FILTER_OP_IN_OUTER_VLAN_OFST 64 8372 #define MC_CMD_FILTER_OP_IN_OUTER_VLAN_LEN 2 8373 /* IP protocol to match (in low byte; set high byte to 0) */ 8374 #define MC_CMD_FILTER_OP_IN_IP_PROTO_OFST 66 8375 #define MC_CMD_FILTER_OP_IN_IP_PROTO_LEN 2 8376 /* Firmware defined register 0 to match (reserved; set to 0) */ 8377 #define MC_CMD_FILTER_OP_IN_FWDEF0_OFST 68 8378 /* Firmware defined register 1 to match (reserved; set to 0) */ 8379 #define MC_CMD_FILTER_OP_IN_FWDEF1_OFST 72 8380 /* source IP address to match (as bytes in network order; set last 12 bytes to 8381 * 0 for IPv4 address) 8382 */ 8383 #define MC_CMD_FILTER_OP_IN_SRC_IP_OFST 76 8384 #define MC_CMD_FILTER_OP_IN_SRC_IP_LEN 16 8385 /* destination IP address to match (as bytes in network order; set last 12 8386 * bytes to 0 for IPv4 address) 8387 */ 8388 #define MC_CMD_FILTER_OP_IN_DST_IP_OFST 92 8389 #define MC_CMD_FILTER_OP_IN_DST_IP_LEN 16 8390 8391 /* MC_CMD_FILTER_OP_EXT_IN msgrequest: Extension to MC_CMD_FILTER_OP_IN to 8392 * include handling of VXLAN/NVGRE encapsulated frame filtering (which is 8393 * supported on Medford only). 8394 */ 8395 #define MC_CMD_FILTER_OP_EXT_IN_LEN 172 8396 /* identifies the type of operation requested */ 8397 #define MC_CMD_FILTER_OP_EXT_IN_OP_OFST 0 8398 /* Enum values, see field(s): */ 8399 /* MC_CMD_FILTER_OP_IN/OP */ 8400 /* filter handle (for remove / unsubscribe operations) */ 8401 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_OFST 4 8402 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LEN 8 8403 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LO_OFST 4 8404 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_HI_OFST 8 8405 /* The port ID associated with the v-adaptor which should contain this filter. 8406 */ 8407 #define MC_CMD_FILTER_OP_EXT_IN_PORT_ID_OFST 12 8408 /* fields to include in match criteria */ 8409 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_FIELDS_OFST 16 8410 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_LBN 0 8411 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_WIDTH 1 8412 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_IP_LBN 1 8413 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_IP_WIDTH 1 8414 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_MAC_LBN 2 8415 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_MAC_WIDTH 1 8416 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_PORT_LBN 3 8417 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_PORT_WIDTH 1 8418 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_LBN 4 8419 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_WIDTH 1 8420 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_PORT_LBN 5 8421 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_PORT_WIDTH 1 8422 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_LBN 6 8423 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_WIDTH 1 8424 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_INNER_VLAN_LBN 7 8425 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_INNER_VLAN_WIDTH 1 8426 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_OUTER_VLAN_LBN 8 8427 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_OUTER_VLAN_WIDTH 1 8428 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_LBN 9 8429 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_WIDTH 1 8430 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_FWDEF0_LBN 10 8431 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_FWDEF0_WIDTH 1 8432 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_VNI_OR_VSID_LBN 11 8433 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_VNI_OR_VSID_WIDTH 1 8434 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_IP_LBN 12 8435 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_IP_WIDTH 1 8436 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_IP_LBN 13 8437 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_IP_WIDTH 1 8438 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_MAC_LBN 14 8439 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_MAC_WIDTH 1 8440 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_PORT_LBN 15 8441 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_PORT_WIDTH 1 8442 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_MAC_LBN 16 8443 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_MAC_WIDTH 1 8444 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_PORT_LBN 17 8445 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_PORT_WIDTH 1 8446 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ETHER_TYPE_LBN 18 8447 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ETHER_TYPE_WIDTH 1 8448 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_INNER_VLAN_LBN 19 8449 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_INNER_VLAN_WIDTH 1 8450 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_OUTER_VLAN_LBN 20 8451 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_OUTER_VLAN_WIDTH 1 8452 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_IP_PROTO_LBN 21 8453 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_IP_PROTO_WIDTH 1 8454 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF0_LBN 22 8455 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF0_WIDTH 1 8456 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF1_LBN 23 8457 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF1_WIDTH 1 8458 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_LBN 24 8459 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_WIDTH 1 8460 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_LBN 25 8461 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_WIDTH 1 8462 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_LBN 30 8463 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1 8464 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_LBN 31 8465 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1 8466 /* receive destination */ 8467 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_OFST 20 8468 /* enum: drop packets */ 8469 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_DROP 0x0 8470 /* enum: receive to host */ 8471 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_HOST 0x1 8472 /* enum: receive to MC */ 8473 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_MC 0x2 8474 /* enum: loop back to TXDP 0 */ 8475 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_TX0 0x3 8476 /* enum: loop back to TXDP 1 */ 8477 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_TX1 0x4 8478 /* receive queue handle (for multiple queue modes, this is the base queue) */ 8479 #define MC_CMD_FILTER_OP_EXT_IN_RX_QUEUE_OFST 24 8480 /* receive mode */ 8481 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_OFST 28 8482 /* enum: receive to just the specified queue */ 8483 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_SIMPLE 0x0 8484 /* enum: receive to multiple queues using RSS context */ 8485 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_RSS 0x1 8486 /* enum: receive to multiple queues using .1p mapping */ 8487 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_DOT1P_MAPPING 0x2 8488 /* enum: install a filter entry that will never match; for test purposes only 8489 */ 8490 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000 8491 /* RSS context (for RX_MODE_RSS) or .1p mapping handle (for 8492 * RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or 8493 * MC_CMD_DOT1P_MAPPING_ALLOC. 8494 */ 8495 #define MC_CMD_FILTER_OP_EXT_IN_RX_CONTEXT_OFST 32 8496 /* transmit domain (reserved; set to 0) */ 8497 #define MC_CMD_FILTER_OP_EXT_IN_TX_DOMAIN_OFST 36 8498 /* transmit destination (either set the MAC and/or PM bits for explicit 8499 * control, or set this field to TX_DEST_DEFAULT for sensible default 8500 * behaviour) 8501 */ 8502 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_OFST 40 8503 /* enum: request default behaviour (based on filter type) */ 8504 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_DEFAULT 0xffffffff 8505 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_LBN 0 8506 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_WIDTH 1 8507 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_PM_LBN 1 8508 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_PM_WIDTH 1 8509 /* source MAC address to match (as bytes in network order) */ 8510 #define MC_CMD_FILTER_OP_EXT_IN_SRC_MAC_OFST 44 8511 #define MC_CMD_FILTER_OP_EXT_IN_SRC_MAC_LEN 6 8512 /* source port to match (as bytes in network order) */ 8513 #define MC_CMD_FILTER_OP_EXT_IN_SRC_PORT_OFST 50 8514 #define MC_CMD_FILTER_OP_EXT_IN_SRC_PORT_LEN 2 8515 /* destination MAC address to match (as bytes in network order) */ 8516 #define MC_CMD_FILTER_OP_EXT_IN_DST_MAC_OFST 52 8517 #define MC_CMD_FILTER_OP_EXT_IN_DST_MAC_LEN 6 8518 /* destination port to match (as bytes in network order) */ 8519 #define MC_CMD_FILTER_OP_EXT_IN_DST_PORT_OFST 58 8520 #define MC_CMD_FILTER_OP_EXT_IN_DST_PORT_LEN 2 8521 /* Ethernet type to match (as bytes in network order) */ 8522 #define MC_CMD_FILTER_OP_EXT_IN_ETHER_TYPE_OFST 60 8523 #define MC_CMD_FILTER_OP_EXT_IN_ETHER_TYPE_LEN 2 8524 /* Inner VLAN tag to match (as bytes in network order) */ 8525 #define MC_CMD_FILTER_OP_EXT_IN_INNER_VLAN_OFST 62 8526 #define MC_CMD_FILTER_OP_EXT_IN_INNER_VLAN_LEN 2 8527 /* Outer VLAN tag to match (as bytes in network order) */ 8528 #define MC_CMD_FILTER_OP_EXT_IN_OUTER_VLAN_OFST 64 8529 #define MC_CMD_FILTER_OP_EXT_IN_OUTER_VLAN_LEN 2 8530 /* IP protocol to match (in low byte; set high byte to 0) */ 8531 #define MC_CMD_FILTER_OP_EXT_IN_IP_PROTO_OFST 66 8532 #define MC_CMD_FILTER_OP_EXT_IN_IP_PROTO_LEN 2 8533 /* Firmware defined register 0 to match (reserved; set to 0) */ 8534 #define MC_CMD_FILTER_OP_EXT_IN_FWDEF0_OFST 68 8535 /* VNI (for VXLAN/Geneve, when IP protocol is UDP) or VSID (for NVGRE, when IP 8536 * protocol is GRE) to match (as bytes in network order; set last byte to 0 for 8537 * VXLAN/NVGRE, or 1 for Geneve) 8538 */ 8539 #define MC_CMD_FILTER_OP_EXT_IN_VNI_OR_VSID_OFST 72 8540 #define MC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_LBN 0 8541 #define MC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_WIDTH 24 8542 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_LBN 24 8543 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_WIDTH 8 8544 /* enum: Match VXLAN traffic with this VNI */ 8545 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_VXLAN 0x0 8546 /* enum: Match Geneve traffic with this VNI */ 8547 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_GENEVE 0x1 8548 /* enum: Reserved for experimental development use */ 8549 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_EXPERIMENTAL 0xfe 8550 #define MC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_LBN 0 8551 #define MC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_WIDTH 24 8552 #define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_LBN 24 8553 #define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_WIDTH 8 8554 /* enum: Match NVGRE traffic with this VSID */ 8555 #define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_NVGRE 0x0 8556 /* source IP address to match (as bytes in network order; set last 12 bytes to 8557 * 0 for IPv4 address) 8558 */ 8559 #define MC_CMD_FILTER_OP_EXT_IN_SRC_IP_OFST 76 8560 #define MC_CMD_FILTER_OP_EXT_IN_SRC_IP_LEN 16 8561 /* destination IP address to match (as bytes in network order; set last 12 8562 * bytes to 0 for IPv4 address) 8563 */ 8564 #define MC_CMD_FILTER_OP_EXT_IN_DST_IP_OFST 92 8565 #define MC_CMD_FILTER_OP_EXT_IN_DST_IP_LEN 16 8566 /* VXLAN/NVGRE inner frame source MAC address to match (as bytes in network 8567 * order) 8568 */ 8569 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_MAC_OFST 108 8570 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_MAC_LEN 6 8571 /* VXLAN/NVGRE inner frame source port to match (as bytes in network order) */ 8572 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_PORT_OFST 114 8573 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_PORT_LEN 2 8574 /* VXLAN/NVGRE inner frame destination MAC address to match (as bytes in 8575 * network order) 8576 */ 8577 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_MAC_OFST 116 8578 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_MAC_LEN 6 8579 /* VXLAN/NVGRE inner frame destination port to match (as bytes in network 8580 * order) 8581 */ 8582 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_PORT_OFST 122 8583 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_PORT_LEN 2 8584 /* VXLAN/NVGRE inner frame Ethernet type to match (as bytes in network order) 8585 */ 8586 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_ETHER_TYPE_OFST 124 8587 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_ETHER_TYPE_LEN 2 8588 /* VXLAN/NVGRE inner frame Inner VLAN tag to match (as bytes in network order) 8589 */ 8590 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_INNER_VLAN_OFST 126 8591 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_INNER_VLAN_LEN 2 8592 /* VXLAN/NVGRE inner frame Outer VLAN tag to match (as bytes in network order) 8593 */ 8594 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_OUTER_VLAN_OFST 128 8595 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_OUTER_VLAN_LEN 2 8596 /* VXLAN/NVGRE inner frame IP protocol to match (in low byte; set high byte to 8597 * 0) 8598 */ 8599 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_IP_PROTO_OFST 130 8600 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_IP_PROTO_LEN 2 8601 /* VXLAN/NVGRE inner frame Firmware defined register 0 to match (reserved; set 8602 * to 0) 8603 */ 8604 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF0_OFST 132 8605 /* VXLAN/NVGRE inner frame Firmware defined register 1 to match (reserved; set 8606 * to 0) 8607 */ 8608 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF1_OFST 136 8609 /* VXLAN/NVGRE inner frame source IP address to match (as bytes in network 8610 * order; set last 12 bytes to 0 for IPv4 address) 8611 */ 8612 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_IP_OFST 140 8613 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_IP_LEN 16 8614 /* VXLAN/NVGRE inner frame destination IP address to match (as bytes in network 8615 * order; set last 12 bytes to 0 for IPv4 address) 8616 */ 8617 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_IP_OFST 156 8618 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_IP_LEN 16 8619 8620 /* MC_CMD_FILTER_OP_OUT msgresponse */ 8621 #define MC_CMD_FILTER_OP_OUT_LEN 12 8622 /* identifies the type of operation requested */ 8623 #define MC_CMD_FILTER_OP_OUT_OP_OFST 0 8624 /* Enum values, see field(s): */ 8625 /* MC_CMD_FILTER_OP_IN/OP */ 8626 /* Returned filter handle (for insert / subscribe operations). Note that these 8627 * handles should be considered opaque to the host, although a value of 8628 * 0xFFFFFFFF_FFFFFFFF is guaranteed never to be a valid handle. 8629 */ 8630 #define MC_CMD_FILTER_OP_OUT_HANDLE_OFST 4 8631 #define MC_CMD_FILTER_OP_OUT_HANDLE_LEN 8 8632 #define MC_CMD_FILTER_OP_OUT_HANDLE_LO_OFST 4 8633 #define MC_CMD_FILTER_OP_OUT_HANDLE_HI_OFST 8 8634 /* enum: guaranteed invalid filter handle (low 32 bits) */ 8635 #define MC_CMD_FILTER_OP_OUT_HANDLE_LO_INVALID 0xffffffff 8636 /* enum: guaranteed invalid filter handle (high 32 bits) */ 8637 #define MC_CMD_FILTER_OP_OUT_HANDLE_HI_INVALID 0xffffffff 8638 8639 /* MC_CMD_FILTER_OP_EXT_OUT msgresponse */ 8640 #define MC_CMD_FILTER_OP_EXT_OUT_LEN 12 8641 /* identifies the type of operation requested */ 8642 #define MC_CMD_FILTER_OP_EXT_OUT_OP_OFST 0 8643 /* Enum values, see field(s): */ 8644 /* MC_CMD_FILTER_OP_EXT_IN/OP */ 8645 /* Returned filter handle (for insert / subscribe operations). Note that these 8646 * handles should be considered opaque to the host, although a value of 8647 * 0xFFFFFFFF_FFFFFFFF is guaranteed never to be a valid handle. 8648 */ 8649 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_OFST 4 8650 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LEN 8 8651 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LO_OFST 4 8652 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_HI_OFST 8 8653 /* Enum values, see field(s): */ 8654 /* MC_CMD_FILTER_OP_OUT/HANDLE */ 8655 8656 8657 /***********************************/ 8658 /* MC_CMD_GET_PARSER_DISP_INFO 8659 * Get information related to the parser-dispatcher subsystem 8660 */ 8661 #define MC_CMD_GET_PARSER_DISP_INFO 0xe4 8662 #undef MC_CMD_0xe4_PRIVILEGE_CTG 8663 8664 #define MC_CMD_0xe4_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8665 8666 /* MC_CMD_GET_PARSER_DISP_INFO_IN msgrequest */ 8667 #define MC_CMD_GET_PARSER_DISP_INFO_IN_LEN 4 8668 /* identifies the type of operation requested */ 8669 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_OFST 0 8670 /* enum: read the list of supported RX filter matches */ 8671 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES 0x1 8672 /* enum: read flags indicating restrictions on filter insertion for the calling 8673 * client 8674 */ 8675 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_RESTRICTIONS 0x2 8676 8677 /* MC_CMD_GET_PARSER_DISP_INFO_OUT msgresponse */ 8678 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMIN 8 8679 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX 252 8680 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_LEN(num) (8+4*(num)) 8681 /* identifies the type of operation requested */ 8682 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_OP_OFST 0 8683 /* Enum values, see field(s): */ 8684 /* MC_CMD_GET_PARSER_DISP_INFO_IN/OP */ 8685 /* number of supported match types */ 8686 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_NUM_SUPPORTED_MATCHES_OFST 4 8687 /* array of supported match types (valid MATCH_FIELDS values for 8688 * MC_CMD_FILTER_OP) sorted in decreasing priority order 8689 */ 8690 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_OFST 8 8691 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_LEN 4 8692 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MINNUM 0 8693 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM 61 8694 8695 /* MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT msgresponse */ 8696 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_LEN 8 8697 /* identifies the type of operation requested */ 8698 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_OP_OFST 0 8699 /* Enum values, see field(s): */ 8700 /* MC_CMD_GET_PARSER_DISP_INFO_IN/OP */ 8701 /* bitfield of filter insertion restrictions */ 8702 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_RESTRICTION_FLAGS_OFST 4 8703 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_LBN 0 8704 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_WIDTH 1 8705 8706 8707 /***********************************/ 8708 /* MC_CMD_PARSER_DISP_RW 8709 * Direct read/write of parser-dispatcher state (DICPUs and LUE) for debugging 8710 */ 8711 #define MC_CMD_PARSER_DISP_RW 0xe5 8712 #undef MC_CMD_0xe5_PRIVILEGE_CTG 8713 8714 #define MC_CMD_0xe5_PRIVILEGE_CTG SRIOV_CTG_ADMIN 8715 8716 /* MC_CMD_PARSER_DISP_RW_IN msgrequest */ 8717 #define MC_CMD_PARSER_DISP_RW_IN_LEN 32 8718 /* identifies the target of the operation */ 8719 #define MC_CMD_PARSER_DISP_RW_IN_TARGET_OFST 0 8720 /* enum: RX dispatcher CPU */ 8721 #define MC_CMD_PARSER_DISP_RW_IN_RX_DICPU 0x0 8722 /* enum: TX dispatcher CPU */ 8723 #define MC_CMD_PARSER_DISP_RW_IN_TX_DICPU 0x1 8724 /* enum: Lookup engine (with original metadata format) */ 8725 #define MC_CMD_PARSER_DISP_RW_IN_LUE 0x2 8726 /* enum: Lookup engine (with requested metadata format) */ 8727 #define MC_CMD_PARSER_DISP_RW_IN_LUE_VERSIONED_METADATA 0x3 8728 /* identifies the type of operation requested */ 8729 #define MC_CMD_PARSER_DISP_RW_IN_OP_OFST 4 8730 /* enum: read a word of DICPU DMEM or a LUE entry */ 8731 #define MC_CMD_PARSER_DISP_RW_IN_READ 0x0 8732 /* enum: write a word of DICPU DMEM or a LUE entry */ 8733 #define MC_CMD_PARSER_DISP_RW_IN_WRITE 0x1 8734 /* enum: read-modify-write a word of DICPU DMEM (not valid for LUE) */ 8735 #define MC_CMD_PARSER_DISP_RW_IN_RMW 0x2 8736 /* data memory address or LUE index */ 8737 #define MC_CMD_PARSER_DISP_RW_IN_ADDRESS_OFST 8 8738 /* value to write (for DMEM writes) */ 8739 #define MC_CMD_PARSER_DISP_RW_IN_DMEM_WRITE_VALUE_OFST 12 8740 /* XOR value (for DMEM read-modify-writes: new = (old & mask) ^ value) */ 8741 #define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_XOR_VALUE_OFST 12 8742 /* AND mask (for DMEM read-modify-writes: new = (old & mask) ^ value) */ 8743 #define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_AND_MASK_OFST 16 8744 /* metadata format (for LUE reads using LUE_VERSIONED_METADATA) */ 8745 #define MC_CMD_PARSER_DISP_RW_IN_LUE_READ_METADATA_VERSION_OFST 12 8746 /* value to write (for LUE writes) */ 8747 #define MC_CMD_PARSER_DISP_RW_IN_LUE_WRITE_VALUE_OFST 12 8748 #define MC_CMD_PARSER_DISP_RW_IN_LUE_WRITE_VALUE_LEN 20 8749 8750 /* MC_CMD_PARSER_DISP_RW_OUT msgresponse */ 8751 #define MC_CMD_PARSER_DISP_RW_OUT_LEN 52 8752 /* value read (for DMEM reads) */ 8753 #define MC_CMD_PARSER_DISP_RW_OUT_DMEM_READ_VALUE_OFST 0 8754 /* value read (for LUE reads) */ 8755 #define MC_CMD_PARSER_DISP_RW_OUT_LUE_READ_VALUE_OFST 0 8756 #define MC_CMD_PARSER_DISP_RW_OUT_LUE_READ_VALUE_LEN 20 8757 /* up to 8 32-bit words of additional soft state from the LUE manager (the 8758 * exact content is firmware-dependent and intended only for debug use) 8759 */ 8760 #define MC_CMD_PARSER_DISP_RW_OUT_LUE_MGR_STATE_OFST 20 8761 #define MC_CMD_PARSER_DISP_RW_OUT_LUE_MGR_STATE_LEN 32 8762 8763 8764 /***********************************/ 8765 /* MC_CMD_GET_PF_COUNT 8766 * Get number of PFs on the device. 8767 */ 8768 #define MC_CMD_GET_PF_COUNT 0xb6 8769 #undef MC_CMD_0xb6_PRIVILEGE_CTG 8770 8771 #define MC_CMD_0xb6_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8772 8773 /* MC_CMD_GET_PF_COUNT_IN msgrequest */ 8774 #define MC_CMD_GET_PF_COUNT_IN_LEN 0 8775 8776 /* MC_CMD_GET_PF_COUNT_OUT msgresponse */ 8777 #define MC_CMD_GET_PF_COUNT_OUT_LEN 1 8778 /* Identifies the number of PFs on the device. */ 8779 #define MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_OFST 0 8780 #define MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_LEN 1 8781 8782 8783 /***********************************/ 8784 /* MC_CMD_SET_PF_COUNT 8785 * Set number of PFs on the device. 8786 */ 8787 #define MC_CMD_SET_PF_COUNT 0xb7 8788 8789 /* MC_CMD_SET_PF_COUNT_IN msgrequest */ 8790 #define MC_CMD_SET_PF_COUNT_IN_LEN 4 8791 /* New number of PFs on the device. */ 8792 #define MC_CMD_SET_PF_COUNT_IN_PF_COUNT_OFST 0 8793 8794 /* MC_CMD_SET_PF_COUNT_OUT msgresponse */ 8795 #define MC_CMD_SET_PF_COUNT_OUT_LEN 0 8796 8797 8798 /***********************************/ 8799 /* MC_CMD_GET_PORT_ASSIGNMENT 8800 * Get port assignment for current PCI function. 8801 */ 8802 #define MC_CMD_GET_PORT_ASSIGNMENT 0xb8 8803 #undef MC_CMD_0xb8_PRIVILEGE_CTG 8804 8805 #define MC_CMD_0xb8_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8806 8807 /* MC_CMD_GET_PORT_ASSIGNMENT_IN msgrequest */ 8808 #define MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN 0 8809 8810 /* MC_CMD_GET_PORT_ASSIGNMENT_OUT msgresponse */ 8811 #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN 4 8812 /* Identifies the port assignment for this function. */ 8813 #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_PORT_OFST 0 8814 8815 8816 /***********************************/ 8817 /* MC_CMD_SET_PORT_ASSIGNMENT 8818 * Set port assignment for current PCI function. 8819 */ 8820 #define MC_CMD_SET_PORT_ASSIGNMENT 0xb9 8821 #undef MC_CMD_0xb9_PRIVILEGE_CTG 8822 8823 #define MC_CMD_0xb9_PRIVILEGE_CTG SRIOV_CTG_ADMIN 8824 8825 /* MC_CMD_SET_PORT_ASSIGNMENT_IN msgrequest */ 8826 #define MC_CMD_SET_PORT_ASSIGNMENT_IN_LEN 4 8827 /* Identifies the port assignment for this function. */ 8828 #define MC_CMD_SET_PORT_ASSIGNMENT_IN_PORT_OFST 0 8829 8830 /* MC_CMD_SET_PORT_ASSIGNMENT_OUT msgresponse */ 8831 #define MC_CMD_SET_PORT_ASSIGNMENT_OUT_LEN 0 8832 8833 8834 /***********************************/ 8835 /* MC_CMD_ALLOC_VIS 8836 * Allocate VIs for current PCI function. 8837 */ 8838 #define MC_CMD_ALLOC_VIS 0x8b 8839 #undef MC_CMD_0x8b_PRIVILEGE_CTG 8840 8841 #define MC_CMD_0x8b_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8842 8843 /* MC_CMD_ALLOC_VIS_IN msgrequest */ 8844 #define MC_CMD_ALLOC_VIS_IN_LEN 8 8845 /* The minimum number of VIs that is acceptable */ 8846 #define MC_CMD_ALLOC_VIS_IN_MIN_VI_COUNT_OFST 0 8847 /* The maximum number of VIs that would be useful */ 8848 #define MC_CMD_ALLOC_VIS_IN_MAX_VI_COUNT_OFST 4 8849 8850 /* MC_CMD_ALLOC_VIS_OUT msgresponse: Huntington-compatible VI_ALLOC request. 8851 * Use extended version in new code. 8852 */ 8853 #define MC_CMD_ALLOC_VIS_OUT_LEN 8 8854 /* The number of VIs allocated on this function */ 8855 #define MC_CMD_ALLOC_VIS_OUT_VI_COUNT_OFST 0 8856 /* The base absolute VI number allocated to this function. Required to 8857 * correctly interpret wakeup events. 8858 */ 8859 #define MC_CMD_ALLOC_VIS_OUT_VI_BASE_OFST 4 8860 8861 /* MC_CMD_ALLOC_VIS_EXT_OUT msgresponse */ 8862 #define MC_CMD_ALLOC_VIS_EXT_OUT_LEN 12 8863 /* The number of VIs allocated on this function */ 8864 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_COUNT_OFST 0 8865 /* The base absolute VI number allocated to this function. Required to 8866 * correctly interpret wakeup events. 8867 */ 8868 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_BASE_OFST 4 8869 /* Function's port vi_shift value (always 0 on Huntington) */ 8870 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_SHIFT_OFST 8 8871 8872 8873 /***********************************/ 8874 /* MC_CMD_FREE_VIS 8875 * Free VIs for current PCI function. Any linked PIO buffers will be unlinked, 8876 * but not freed. 8877 */ 8878 #define MC_CMD_FREE_VIS 0x8c 8879 #undef MC_CMD_0x8c_PRIVILEGE_CTG 8880 8881 #define MC_CMD_0x8c_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8882 8883 /* MC_CMD_FREE_VIS_IN msgrequest */ 8884 #define MC_CMD_FREE_VIS_IN_LEN 0 8885 8886 /* MC_CMD_FREE_VIS_OUT msgresponse */ 8887 #define MC_CMD_FREE_VIS_OUT_LEN 0 8888 8889 8890 /***********************************/ 8891 /* MC_CMD_GET_SRIOV_CFG 8892 * Get SRIOV config for this PF. 8893 */ 8894 #define MC_CMD_GET_SRIOV_CFG 0xba 8895 #undef MC_CMD_0xba_PRIVILEGE_CTG 8896 8897 #define MC_CMD_0xba_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8898 8899 /* MC_CMD_GET_SRIOV_CFG_IN msgrequest */ 8900 #define MC_CMD_GET_SRIOV_CFG_IN_LEN 0 8901 8902 /* MC_CMD_GET_SRIOV_CFG_OUT msgresponse */ 8903 #define MC_CMD_GET_SRIOV_CFG_OUT_LEN 20 8904 /* Number of VFs currently enabled. */ 8905 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_CURRENT_OFST 0 8906 /* Max number of VFs before sriov stride and offset may need to be changed. */ 8907 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_MAX_OFST 4 8908 #define MC_CMD_GET_SRIOV_CFG_OUT_FLAGS_OFST 8 8909 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_LBN 0 8910 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_WIDTH 1 8911 /* RID offset of first VF from PF. */ 8912 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_OFFSET_OFST 12 8913 /* RID offset of each subsequent VF from the previous. */ 8914 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_STRIDE_OFST 16 8915 8916 8917 /***********************************/ 8918 /* MC_CMD_SET_SRIOV_CFG 8919 * Set SRIOV config for this PF. 8920 */ 8921 #define MC_CMD_SET_SRIOV_CFG 0xbb 8922 #undef MC_CMD_0xbb_PRIVILEGE_CTG 8923 8924 #define MC_CMD_0xbb_PRIVILEGE_CTG SRIOV_CTG_ADMIN 8925 8926 /* MC_CMD_SET_SRIOV_CFG_IN msgrequest */ 8927 #define MC_CMD_SET_SRIOV_CFG_IN_LEN 20 8928 /* Number of VFs currently enabled. */ 8929 #define MC_CMD_SET_SRIOV_CFG_IN_VF_CURRENT_OFST 0 8930 /* Max number of VFs before sriov stride and offset may need to be changed. */ 8931 #define MC_CMD_SET_SRIOV_CFG_IN_VF_MAX_OFST 4 8932 #define MC_CMD_SET_SRIOV_CFG_IN_FLAGS_OFST 8 8933 #define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_LBN 0 8934 #define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_WIDTH 1 8935 /* RID offset of first VF from PF, or 0 for no change, or 8936 * MC_CMD_RESOURCE_INSTANCE_ANY to allow the system to allocate an offset. 8937 */ 8938 #define MC_CMD_SET_SRIOV_CFG_IN_VF_OFFSET_OFST 12 8939 /* RID offset of each subsequent VF from the previous, 0 for no change, or 8940 * MC_CMD_RESOURCE_INSTANCE_ANY to allow the system to allocate a stride. 8941 */ 8942 #define MC_CMD_SET_SRIOV_CFG_IN_VF_STRIDE_OFST 16 8943 8944 /* MC_CMD_SET_SRIOV_CFG_OUT msgresponse */ 8945 #define MC_CMD_SET_SRIOV_CFG_OUT_LEN 0 8946 8947 8948 /***********************************/ 8949 /* MC_CMD_GET_VI_ALLOC_INFO 8950 * Get information about number of VI's and base VI number allocated to this 8951 * function. 8952 */ 8953 #define MC_CMD_GET_VI_ALLOC_INFO 0x8d 8954 #undef MC_CMD_0x8d_PRIVILEGE_CTG 8955 8956 #define MC_CMD_0x8d_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8957 8958 /* MC_CMD_GET_VI_ALLOC_INFO_IN msgrequest */ 8959 #define MC_CMD_GET_VI_ALLOC_INFO_IN_LEN 0 8960 8961 /* MC_CMD_GET_VI_ALLOC_INFO_OUT msgresponse */ 8962 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_LEN 12 8963 /* The number of VIs allocated on this function */ 8964 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_COUNT_OFST 0 8965 /* The base absolute VI number allocated to this function. Required to 8966 * correctly interpret wakeup events. 8967 */ 8968 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_BASE_OFST 4 8969 /* Function's port vi_shift value (always 0 on Huntington) */ 8970 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_SHIFT_OFST 8 8971 8972 8973 /***********************************/ 8974 /* MC_CMD_DUMP_VI_STATE 8975 * For CmdClient use. Dump pertinent information on a specific absolute VI. 8976 */ 8977 #define MC_CMD_DUMP_VI_STATE 0x8e 8978 #undef MC_CMD_0x8e_PRIVILEGE_CTG 8979 8980 #define MC_CMD_0x8e_PRIVILEGE_CTG SRIOV_CTG_GENERAL 8981 8982 /* MC_CMD_DUMP_VI_STATE_IN msgrequest */ 8983 #define MC_CMD_DUMP_VI_STATE_IN_LEN 4 8984 /* The VI number to query. */ 8985 #define MC_CMD_DUMP_VI_STATE_IN_VI_NUMBER_OFST 0 8986 8987 /* MC_CMD_DUMP_VI_STATE_OUT msgresponse */ 8988 #define MC_CMD_DUMP_VI_STATE_OUT_LEN 96 8989 /* The PF part of the function owning this VI. */ 8990 #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_OFST 0 8991 #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_LEN 2 8992 /* The VF part of the function owning this VI. */ 8993 #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_VF_OFST 2 8994 #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_VF_LEN 2 8995 /* Base of VIs allocated to this function. */ 8996 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_BASE_OFST 4 8997 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_BASE_LEN 2 8998 /* Count of VIs allocated to the owner function. */ 8999 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_COUNT_OFST 6 9000 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_COUNT_LEN 2 9001 /* Base interrupt vector allocated to this function. */ 9002 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_BASE_OFST 8 9003 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_BASE_LEN 2 9004 /* Number of interrupt vectors allocated to this function. */ 9005 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_COUNT_OFST 10 9006 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_COUNT_LEN 2 9007 /* Raw evq ptr table data. */ 9008 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_OFST 12 9009 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LEN 8 9010 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LO_OFST 12 9011 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_HI_OFST 16 9012 /* Raw evq timer table data. */ 9013 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_OFST 20 9014 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LEN 8 9015 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LO_OFST 20 9016 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_HI_OFST 24 9017 /* Combined metadata field. */ 9018 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_OFST 28 9019 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_LBN 0 9020 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_WIDTH 16 9021 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_LBN 16 9022 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_WIDTH 8 9023 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_LBN 24 9024 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_WIDTH 8 9025 /* TXDPCPU raw table data for queue. */ 9026 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_OFST 32 9027 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LEN 8 9028 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LO_OFST 32 9029 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_HI_OFST 36 9030 /* TXDPCPU raw table data for queue. */ 9031 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_OFST 40 9032 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LEN 8 9033 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LO_OFST 40 9034 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_HI_OFST 44 9035 /* TXDPCPU raw table data for queue. */ 9036 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_OFST 48 9037 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LEN 8 9038 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LO_OFST 48 9039 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_HI_OFST 52 9040 /* Combined metadata field. */ 9041 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_OFST 56 9042 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LEN 8 9043 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LO_OFST 56 9044 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_HI_OFST 60 9045 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_LBN 0 9046 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_WIDTH 16 9047 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_LBN 16 9048 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_WIDTH 8 9049 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_LBN 24 9050 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_WIDTH 8 9051 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_LBN 32 9052 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_WIDTH 8 9053 #define MC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_LBN 40 9054 #define MC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_WIDTH 24 9055 /* RXDPCPU raw table data for queue. */ 9056 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_OFST 64 9057 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LEN 8 9058 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LO_OFST 64 9059 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_HI_OFST 68 9060 /* RXDPCPU raw table data for queue. */ 9061 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_OFST 72 9062 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LEN 8 9063 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LO_OFST 72 9064 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_HI_OFST 76 9065 /* Reserved, currently 0. */ 9066 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_OFST 80 9067 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LEN 8 9068 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LO_OFST 80 9069 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_HI_OFST 84 9070 /* Combined metadata field. */ 9071 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_OFST 88 9072 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LEN 8 9073 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LO_OFST 88 9074 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_HI_OFST 92 9075 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_LBN 0 9076 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_WIDTH 16 9077 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_LBN 16 9078 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_WIDTH 8 9079 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_LBN 24 9080 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_WIDTH 8 9081 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_LBN 32 9082 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_WIDTH 8 9083 9084 9085 /***********************************/ 9086 /* MC_CMD_ALLOC_PIOBUF 9087 * Allocate a push I/O buffer for later use with a tx queue. 9088 */ 9089 #define MC_CMD_ALLOC_PIOBUF 0x8f 9090 #undef MC_CMD_0x8f_PRIVILEGE_CTG 9091 9092 #define MC_CMD_0x8f_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 9093 9094 /* MC_CMD_ALLOC_PIOBUF_IN msgrequest */ 9095 #define MC_CMD_ALLOC_PIOBUF_IN_LEN 0 9096 9097 /* MC_CMD_ALLOC_PIOBUF_OUT msgresponse */ 9098 #define MC_CMD_ALLOC_PIOBUF_OUT_LEN 4 9099 /* Handle for allocated push I/O buffer. */ 9100 #define MC_CMD_ALLOC_PIOBUF_OUT_PIOBUF_HANDLE_OFST 0 9101 9102 9103 /***********************************/ 9104 /* MC_CMD_FREE_PIOBUF 9105 * Free a push I/O buffer. 9106 */ 9107 #define MC_CMD_FREE_PIOBUF 0x90 9108 #undef MC_CMD_0x90_PRIVILEGE_CTG 9109 9110 #define MC_CMD_0x90_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 9111 9112 /* MC_CMD_FREE_PIOBUF_IN msgrequest */ 9113 #define MC_CMD_FREE_PIOBUF_IN_LEN 4 9114 /* Handle for allocated push I/O buffer. */ 9115 #define MC_CMD_FREE_PIOBUF_IN_PIOBUF_HANDLE_OFST 0 9116 9117 /* MC_CMD_FREE_PIOBUF_OUT msgresponse */ 9118 #define MC_CMD_FREE_PIOBUF_OUT_LEN 0 9119 9120 9121 /***********************************/ 9122 /* MC_CMD_GET_VI_TLP_PROCESSING 9123 * Get TLP steering and ordering information for a VI. 9124 */ 9125 #define MC_CMD_GET_VI_TLP_PROCESSING 0xb0 9126 #undef MC_CMD_0xb0_PRIVILEGE_CTG 9127 9128 #define MC_CMD_0xb0_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9129 9130 /* MC_CMD_GET_VI_TLP_PROCESSING_IN msgrequest */ 9131 #define MC_CMD_GET_VI_TLP_PROCESSING_IN_LEN 4 9132 /* VI number to get information for. */ 9133 #define MC_CMD_GET_VI_TLP_PROCESSING_IN_INSTANCE_OFST 0 9134 9135 /* MC_CMD_GET_VI_TLP_PROCESSING_OUT msgresponse */ 9136 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_LEN 4 9137 /* Transaction processing steering hint 1 for use with the Rx Queue. */ 9138 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG1_RX_OFST 0 9139 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG1_RX_LEN 1 9140 /* Transaction processing steering hint 2 for use with the Ev Queue. */ 9141 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG2_EV_OFST 1 9142 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG2_EV_LEN 1 9143 /* Use Relaxed ordering model for TLPs on this VI. */ 9144 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_RELAXED_ORDERING_LBN 16 9145 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_RELAXED_ORDERING_WIDTH 1 9146 /* Use ID based ordering for TLPs on this VI. */ 9147 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_ID_BASED_ORDERING_LBN 17 9148 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_ID_BASED_ORDERING_WIDTH 1 9149 /* Set no snoop bit for TLPs on this VI. */ 9150 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_NO_SNOOP_LBN 18 9151 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_NO_SNOOP_WIDTH 1 9152 /* Enable TPH for TLPs on this VI. */ 9153 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_ON_LBN 19 9154 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_ON_WIDTH 1 9155 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_DATA_OFST 0 9156 9157 9158 /***********************************/ 9159 /* MC_CMD_SET_VI_TLP_PROCESSING 9160 * Set TLP steering and ordering information for a VI. 9161 */ 9162 #define MC_CMD_SET_VI_TLP_PROCESSING 0xb1 9163 #undef MC_CMD_0xb1_PRIVILEGE_CTG 9164 9165 #define MC_CMD_0xb1_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9166 9167 /* MC_CMD_SET_VI_TLP_PROCESSING_IN msgrequest */ 9168 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_LEN 8 9169 /* VI number to set information for. */ 9170 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_INSTANCE_OFST 0 9171 /* Transaction processing steering hint 1 for use with the Rx Queue. */ 9172 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG1_RX_OFST 4 9173 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG1_RX_LEN 1 9174 /* Transaction processing steering hint 2 for use with the Ev Queue. */ 9175 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG2_EV_OFST 5 9176 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG2_EV_LEN 1 9177 /* Use Relaxed ordering model for TLPs on this VI. */ 9178 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_RELAXED_ORDERING_LBN 48 9179 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_RELAXED_ORDERING_WIDTH 1 9180 /* Use ID based ordering for TLPs on this VI. */ 9181 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_ID_BASED_ORDERING_LBN 49 9182 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_ID_BASED_ORDERING_WIDTH 1 9183 /* Set the no snoop bit for TLPs on this VI. */ 9184 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_NO_SNOOP_LBN 50 9185 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_NO_SNOOP_WIDTH 1 9186 /* Enable TPH for TLPs on this VI. */ 9187 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_ON_LBN 51 9188 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_ON_WIDTH 1 9189 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_DATA_OFST 4 9190 9191 /* MC_CMD_SET_VI_TLP_PROCESSING_OUT msgresponse */ 9192 #define MC_CMD_SET_VI_TLP_PROCESSING_OUT_LEN 0 9193 9194 9195 /***********************************/ 9196 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS 9197 * Get global PCIe steering and transaction processing configuration. 9198 */ 9199 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS 0xbc 9200 #undef MC_CMD_0xbc_PRIVILEGE_CTG 9201 9202 #define MC_CMD_0xbc_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9203 9204 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN msgrequest */ 9205 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_LEN 4 9206 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_OFST 0 9207 /* enum: MISC. */ 9208 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_MISC 0x0 9209 /* enum: IDO. */ 9210 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_IDO 0x1 9211 /* enum: RO. */ 9212 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_RO 0x2 9213 /* enum: TPH Type. */ 9214 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_TPH_TYPE 0x3 9215 9216 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT msgresponse */ 9217 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_LEN 8 9218 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_GLOBAL_CATEGORY_OFST 0 9219 /* Enum values, see field(s): */ 9220 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN/TLP_GLOBAL_CATEGORY */ 9221 /* Amalgamated TLP info word. */ 9222 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_WORD_OFST 4 9223 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_LBN 0 9224 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_WIDTH 1 9225 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_LBN 1 9226 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_WIDTH 31 9227 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_LBN 0 9228 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_WIDTH 1 9229 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_LBN 1 9230 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_WIDTH 1 9231 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_EV_EN_LBN 2 9232 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_EV_EN_WIDTH 1 9233 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_LBN 3 9234 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_WIDTH 1 9235 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_LBN 4 9236 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_WIDTH 28 9237 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_LBN 0 9238 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_WIDTH 1 9239 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_LBN 1 9240 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_WIDTH 1 9241 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_LBN 2 9242 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_WIDTH 1 9243 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_LBN 3 9244 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_WIDTH 29 9245 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_LBN 0 9246 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_WIDTH 2 9247 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_DL_LBN 2 9248 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_DL_WIDTH 2 9249 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_LBN 4 9250 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_WIDTH 2 9251 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_EV_LBN 6 9252 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_EV_WIDTH 2 9253 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_LBN 8 9254 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_WIDTH 2 9255 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_LBN 9 9256 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_WIDTH 23 9257 9258 9259 /***********************************/ 9260 /* MC_CMD_SET_TLP_PROCESSING_GLOBALS 9261 * Set global PCIe steering and transaction processing configuration. 9262 */ 9263 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS 0xbd 9264 #undef MC_CMD_0xbd_PRIVILEGE_CTG 9265 9266 #define MC_CMD_0xbd_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9267 9268 /* MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN msgrequest */ 9269 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_LEN 8 9270 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_OFST 0 9271 /* Enum values, see field(s): */ 9272 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS/MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN/TLP_GLOBAL_CATEGORY */ 9273 /* Amalgamated TLP info word. */ 9274 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_WORD_OFST 4 9275 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_LBN 0 9276 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_WIDTH 1 9277 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_LBN 0 9278 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_WIDTH 1 9279 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_LBN 1 9280 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_WIDTH 1 9281 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_EV_EN_LBN 2 9282 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_EV_EN_WIDTH 1 9283 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_RX_EN_LBN 3 9284 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_RX_EN_WIDTH 1 9285 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_LBN 0 9286 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_WIDTH 1 9287 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_LBN 1 9288 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_WIDTH 1 9289 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_DL_EN_LBN 2 9290 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_DL_EN_WIDTH 1 9291 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_LBN 0 9292 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_WIDTH 2 9293 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_DL_LBN 2 9294 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_DL_WIDTH 2 9295 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_LBN 4 9296 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_WIDTH 2 9297 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_EV_LBN 6 9298 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_EV_WIDTH 2 9299 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_LBN 8 9300 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_WIDTH 2 9301 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_LBN 10 9302 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_WIDTH 22 9303 9304 /* MC_CMD_SET_TLP_PROCESSING_GLOBALS_OUT msgresponse */ 9305 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_OUT_LEN 0 9306 9307 9308 /***********************************/ 9309 /* MC_CMD_SATELLITE_DOWNLOAD 9310 * Download a new set of images to the satellite CPUs from the host. 9311 */ 9312 #define MC_CMD_SATELLITE_DOWNLOAD 0x91 9313 #undef MC_CMD_0x91_PRIVILEGE_CTG 9314 9315 #define MC_CMD_0x91_PRIVILEGE_CTG SRIOV_CTG_ADMIN 9316 9317 /* MC_CMD_SATELLITE_DOWNLOAD_IN msgrequest: The reset requirements for the CPUs 9318 * are subtle, and so downloads must proceed in a number of phases. 9319 * 9320 * 1) PHASE_RESET with a target of TARGET_ALL and chunk ID/length of 0. 9321 * 9322 * 2) PHASE_IMEMS for each of the IMEM targets (target IDs 0-11). Each download 9323 * may consist of multiple chunks. The final chunk (with CHUNK_ID_LAST) should 9324 * be a checksum (a simple 32-bit sum) of the transferred data. An individual 9325 * download may be aborted using CHUNK_ID_ABORT. 9326 * 9327 * 3) PHASE_VECTORS for each of the vector table targets (target IDs 12-15), 9328 * similar to PHASE_IMEMS. 9329 * 9330 * 4) PHASE_READY with a target of TARGET_ALL and chunk ID/length of 0. 9331 * 9332 * After any error (a requested abort is not considered to be an error) the 9333 * sequence must be restarted from PHASE_RESET. 9334 */ 9335 #define MC_CMD_SATELLITE_DOWNLOAD_IN_LENMIN 20 9336 #define MC_CMD_SATELLITE_DOWNLOAD_IN_LENMAX 252 9337 #define MC_CMD_SATELLITE_DOWNLOAD_IN_LEN(num) (16+4*(num)) 9338 /* Download phase. (Note: the IDLE phase is used internally and is never valid 9339 * in a command from the host.) 9340 */ 9341 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_OFST 0 9342 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_IDLE 0x0 /* enum */ 9343 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_RESET 0x1 /* enum */ 9344 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_IMEMS 0x2 /* enum */ 9345 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_VECTORS 0x3 /* enum */ 9346 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_READY 0x4 /* enum */ 9347 /* Target for download. (These match the blob numbers defined in 9348 * mc_flash_layout.h.) 9349 */ 9350 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_OFST 4 9351 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 9352 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_TEXT 0x0 9353 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 9354 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_TEXT 0x1 9355 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 9356 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDP_TEXT 0x2 9357 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 9358 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDP_TEXT 0x3 9359 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 9360 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_LUT 0x4 9361 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 9362 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_LUT_CFG 0x5 9363 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 9364 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_LUT 0x6 9365 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 9366 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_LUT_CFG 0x7 9367 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 9368 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_PGM 0x8 9369 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 9370 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_SL_PGM 0x9 9371 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 9372 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_PGM 0xa 9373 /* enum: Valid in phase 2 (PHASE_IMEMS) only */ 9374 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_SL_PGM 0xb 9375 /* enum: Valid in phase 3 (PHASE_VECTORS) only */ 9376 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_VTBL0 0xc 9377 /* enum: Valid in phase 3 (PHASE_VECTORS) only */ 9378 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_VTBL0 0xd 9379 /* enum: Valid in phase 3 (PHASE_VECTORS) only */ 9380 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_VTBL1 0xe 9381 /* enum: Valid in phase 3 (PHASE_VECTORS) only */ 9382 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_VTBL1 0xf 9383 /* enum: Valid in phases 1 (PHASE_RESET) and 4 (PHASE_READY) only */ 9384 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_ALL 0xffffffff 9385 /* Chunk ID, or CHUNK_ID_LAST or CHUNK_ID_ABORT */ 9386 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_OFST 8 9387 /* enum: Last chunk, containing checksum rather than data */ 9388 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_LAST 0xffffffff 9389 /* enum: Abort download of this item */ 9390 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_ABORT 0xfffffffe 9391 /* Length of this chunk in bytes */ 9392 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_LEN_OFST 12 9393 /* Data for this chunk */ 9394 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_OFST 16 9395 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_LEN 4 9396 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_MINNUM 1 9397 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_MAXNUM 59 9398 9399 /* MC_CMD_SATELLITE_DOWNLOAD_OUT msgresponse */ 9400 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_LEN 8 9401 /* Same as MC_CMD_ERR field, but included as 0 in success cases */ 9402 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_RESULT_OFST 0 9403 /* Extra status information */ 9404 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_INFO_OFST 4 9405 /* enum: Code download OK, completed. */ 9406 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_COMPLETE 0x0 9407 /* enum: Code download aborted as requested. */ 9408 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_ABORTED 0x1 9409 /* enum: Code download OK so far, send next chunk. */ 9410 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_NEXT_CHUNK 0x2 9411 /* enum: Download phases out of sequence */ 9412 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_PHASE 0x100 9413 /* enum: Bad target for this phase */ 9414 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_TARGET 0x101 9415 /* enum: Chunk ID out of sequence */ 9416 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHUNK_ID 0x200 9417 /* enum: Chunk length zero or too large */ 9418 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHUNK_LEN 0x201 9419 /* enum: Checksum was incorrect */ 9420 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHECKSUM 0x300 9421 9422 9423 /***********************************/ 9424 /* MC_CMD_GET_CAPABILITIES 9425 * Get device capabilities. 9426 * 9427 * This is supplementary to the MC_CMD_GET_BOARD_CFG command, and intended to 9428 * reference inherent device capabilities as opposed to current NVRAM config. 9429 */ 9430 #define MC_CMD_GET_CAPABILITIES 0xbe 9431 #undef MC_CMD_0xbe_PRIVILEGE_CTG 9432 9433 #define MC_CMD_0xbe_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9434 9435 /* MC_CMD_GET_CAPABILITIES_IN msgrequest */ 9436 #define MC_CMD_GET_CAPABILITIES_IN_LEN 0 9437 9438 /* MC_CMD_GET_CAPABILITIES_OUT msgresponse */ 9439 #define MC_CMD_GET_CAPABILITIES_OUT_LEN 20 9440 /* First word of flags. */ 9441 #define MC_CMD_GET_CAPABILITIES_OUT_FLAGS1_OFST 0 9442 #define MC_CMD_GET_CAPABILITIES_OUT_TX_MAC_SECURITY_FILTERING_LBN 12 9443 #define MC_CMD_GET_CAPABILITIES_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1 9444 #define MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_LBN 13 9445 #define MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_WIDTH 1 9446 #define MC_CMD_GET_CAPABILITIES_OUT_QBB_LBN 14 9447 #define MC_CMD_GET_CAPABILITIES_OUT_QBB_WIDTH 1 9448 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15 9449 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1 9450 #define MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_LBN 16 9451 #define MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_WIDTH 1 9452 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_LBN 17 9453 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_WIDTH 1 9454 #define MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_LBN 18 9455 #define MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_WIDTH 1 9456 #define MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_LBN 19 9457 #define MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_WIDTH 1 9458 #define MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_LBN 20 9459 #define MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_WIDTH 1 9460 #define MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN 21 9461 #define MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_WIDTH 1 9462 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_LBN 22 9463 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_WIDTH 1 9464 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN 23 9465 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_WIDTH 1 9466 #define MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_LBN 24 9467 #define MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_WIDTH 1 9468 #define MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN 25 9469 #define MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_WIDTH 1 9470 #define MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_LBN 26 9471 #define MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_WIDTH 1 9472 #define MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN 27 9473 #define MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1 9474 #define MC_CMD_GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER_LBN 28 9475 #define MC_CMD_GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER_WIDTH 1 9476 #define MC_CMD_GET_CAPABILITIES_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29 9477 #define MC_CMD_GET_CAPABILITIES_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1 9478 #define MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN 30 9479 #define MC_CMD_GET_CAPABILITIES_OUT_EVB_WIDTH 1 9480 #define MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN 31 9481 #define MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_WIDTH 1 9482 /* RxDPCPU firmware id. */ 9483 #define MC_CMD_GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID_OFST 4 9484 #define MC_CMD_GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID_LEN 2 9485 /* enum: Standard RXDP firmware */ 9486 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP 0x0 9487 /* enum: Low latency RXDP firmware */ 9488 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_LOW_LATENCY 0x1 9489 /* enum: Packed stream RXDP firmware */ 9490 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_PACKED_STREAM 0x2 9491 /* enum: BIST RXDP firmware */ 9492 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_BIST 0x10a 9493 /* enum: RXDP Test firmware image 1 */ 9494 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101 9495 /* enum: RXDP Test firmware image 2 */ 9496 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102 9497 /* enum: RXDP Test firmware image 3 */ 9498 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103 9499 /* enum: RXDP Test firmware image 4 */ 9500 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104 9501 /* enum: RXDP Test firmware image 5 */ 9502 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_BACKPRESSURE 0x105 9503 /* enum: RXDP Test firmware image 6 */ 9504 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106 9505 /* enum: RXDP Test firmware image 7 */ 9506 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107 9507 /* enum: RXDP Test firmware image 8 */ 9508 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_DISABLE_DL 0x108 9509 /* TxDPCPU firmware id. */ 9510 #define MC_CMD_GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID_OFST 6 9511 #define MC_CMD_GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID_LEN 2 9512 /* enum: Standard TXDP firmware */ 9513 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP 0x0 9514 /* enum: Low latency TXDP firmware */ 9515 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_LOW_LATENCY 0x1 9516 /* enum: High packet rate TXDP firmware */ 9517 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_HIGH_PACKET_RATE 0x3 9518 /* enum: BIST TXDP firmware */ 9519 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_BIST 0x12d 9520 /* enum: TXDP Test firmware image 1 */ 9521 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_TSO_EDIT 0x101 9522 /* enum: TXDP Test firmware image 2 */ 9523 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102 9524 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_OFST 8 9525 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_LEN 2 9526 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_LBN 0 9527 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_WIDTH 12 9528 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_LBN 12 9529 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4 9530 /* enum: reserved value - do not use (may indicate alternative interpretation 9531 * of REV field in future) 9532 */ 9533 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_RESERVED 0x0 9534 /* enum: Trivial RX PD firmware for early Huntington development (Huntington 9535 * development only) 9536 */ 9537 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1 9538 /* enum: RX PD firmware with approximately Siena-compatible behaviour 9539 * (Huntington development only) 9540 */ 9541 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2 9542 /* enum: Virtual switching (full feature) RX PD production firmware */ 9543 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_VSWITCH 0x3 9544 /* enum: siena_compat variant RX PD firmware using PM rather than MAC 9545 * (Huntington development only) 9546 */ 9547 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 9548 /* enum: Low latency RX PD production firmware */ 9549 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5 9550 /* enum: Packed stream RX PD production firmware */ 9551 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6 9552 /* enum: RX PD firmware handling layer 2 only for high packet rate performance 9553 * tests (Medford development only) 9554 */ 9555 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7 9556 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 9557 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 9558 /* enum: RX PD firmware parsing but not filtering network overlay tunnel 9559 * encapsulations (Medford development only) 9560 */ 9561 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf 9562 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_OFST 10 9563 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_LEN 2 9564 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_LBN 0 9565 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_WIDTH 12 9566 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_LBN 12 9567 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4 9568 /* enum: reserved value - do not use (may indicate alternative interpretation 9569 * of REV field in future) 9570 */ 9571 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_RESERVED 0x0 9572 /* enum: Trivial TX PD firmware for early Huntington development (Huntington 9573 * development only) 9574 */ 9575 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1 9576 /* enum: TX PD firmware with approximately Siena-compatible behaviour 9577 * (Huntington development only) 9578 */ 9579 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2 9580 /* enum: Virtual switching (full feature) TX PD production firmware */ 9581 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_VSWITCH 0x3 9582 /* enum: siena_compat variant TX PD firmware using PM rather than MAC 9583 * (Huntington development only) 9584 */ 9585 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 9586 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */ 9587 /* enum: TX PD firmware handling layer 2 only for high packet rate performance 9588 * tests (Medford development only) 9589 */ 9590 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7 9591 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ 9592 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe 9593 /* Hardware capabilities of NIC */ 9594 #define MC_CMD_GET_CAPABILITIES_OUT_HW_CAPABILITIES_OFST 12 9595 /* Licensed capabilities */ 9596 #define MC_CMD_GET_CAPABILITIES_OUT_LICENSE_CAPABILITIES_OFST 16 9597 9598 9599 /***********************************/ 9600 /* MC_CMD_V2_EXTN 9601 * Encapsulation for a v2 extended command 9602 */ 9603 #define MC_CMD_V2_EXTN 0x7f 9604 9605 /* MC_CMD_V2_EXTN_IN msgrequest */ 9606 #define MC_CMD_V2_EXTN_IN_LEN 4 9607 /* the extended command number */ 9608 #define MC_CMD_V2_EXTN_IN_EXTENDED_CMD_LBN 0 9609 #define MC_CMD_V2_EXTN_IN_EXTENDED_CMD_WIDTH 15 9610 #define MC_CMD_V2_EXTN_IN_UNUSED_LBN 15 9611 #define MC_CMD_V2_EXTN_IN_UNUSED_WIDTH 1 9612 /* the actual length of the encapsulated command (which is not in the v1 9613 * header) 9614 */ 9615 #define MC_CMD_V2_EXTN_IN_ACTUAL_LEN_LBN 16 9616 #define MC_CMD_V2_EXTN_IN_ACTUAL_LEN_WIDTH 10 9617 #define MC_CMD_V2_EXTN_IN_UNUSED2_LBN 26 9618 #define MC_CMD_V2_EXTN_IN_UNUSED2_WIDTH 6 9619 9620 9621 /***********************************/ 9622 /* MC_CMD_TCM_BUCKET_ALLOC 9623 * Allocate a pacer bucket (for qau rp or a snapper test) 9624 */ 9625 #define MC_CMD_TCM_BUCKET_ALLOC 0xb2 9626 #undef MC_CMD_0xb2_PRIVILEGE_CTG 9627 9628 #define MC_CMD_0xb2_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9629 9630 /* MC_CMD_TCM_BUCKET_ALLOC_IN msgrequest */ 9631 #define MC_CMD_TCM_BUCKET_ALLOC_IN_LEN 0 9632 9633 /* MC_CMD_TCM_BUCKET_ALLOC_OUT msgresponse */ 9634 #define MC_CMD_TCM_BUCKET_ALLOC_OUT_LEN 4 9635 /* the bucket id */ 9636 #define MC_CMD_TCM_BUCKET_ALLOC_OUT_BUCKET_OFST 0 9637 9638 9639 /***********************************/ 9640 /* MC_CMD_TCM_BUCKET_FREE 9641 * Free a pacer bucket 9642 */ 9643 #define MC_CMD_TCM_BUCKET_FREE 0xb3 9644 #undef MC_CMD_0xb3_PRIVILEGE_CTG 9645 9646 #define MC_CMD_0xb3_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9647 9648 /* MC_CMD_TCM_BUCKET_FREE_IN msgrequest */ 9649 #define MC_CMD_TCM_BUCKET_FREE_IN_LEN 4 9650 /* the bucket id */ 9651 #define MC_CMD_TCM_BUCKET_FREE_IN_BUCKET_OFST 0 9652 9653 /* MC_CMD_TCM_BUCKET_FREE_OUT msgresponse */ 9654 #define MC_CMD_TCM_BUCKET_FREE_OUT_LEN 0 9655 9656 9657 /***********************************/ 9658 /* MC_CMD_TCM_BUCKET_INIT 9659 * Initialise pacer bucket with a given rate 9660 */ 9661 #define MC_CMD_TCM_BUCKET_INIT 0xb4 9662 #undef MC_CMD_0xb4_PRIVILEGE_CTG 9663 9664 #define MC_CMD_0xb4_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9665 9666 /* MC_CMD_TCM_BUCKET_INIT_IN msgrequest */ 9667 #define MC_CMD_TCM_BUCKET_INIT_IN_LEN 8 9668 /* the bucket id */ 9669 #define MC_CMD_TCM_BUCKET_INIT_IN_BUCKET_OFST 0 9670 /* the rate in mbps */ 9671 #define MC_CMD_TCM_BUCKET_INIT_IN_RATE_OFST 4 9672 9673 /* MC_CMD_TCM_BUCKET_INIT_EXT_IN msgrequest */ 9674 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_LEN 12 9675 /* the bucket id */ 9676 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_BUCKET_OFST 0 9677 /* the rate in mbps */ 9678 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_RATE_OFST 4 9679 /* the desired maximum fill level */ 9680 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_MAX_FILL_OFST 8 9681 9682 /* MC_CMD_TCM_BUCKET_INIT_OUT msgresponse */ 9683 #define MC_CMD_TCM_BUCKET_INIT_OUT_LEN 0 9684 9685 9686 /***********************************/ 9687 /* MC_CMD_TCM_TXQ_INIT 9688 * Initialise txq in pacer with given options or set options 9689 */ 9690 #define MC_CMD_TCM_TXQ_INIT 0xb5 9691 #undef MC_CMD_0xb5_PRIVILEGE_CTG 9692 9693 #define MC_CMD_0xb5_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9694 9695 /* MC_CMD_TCM_TXQ_INIT_IN msgrequest */ 9696 #define MC_CMD_TCM_TXQ_INIT_IN_LEN 28 9697 /* the txq id */ 9698 #define MC_CMD_TCM_TXQ_INIT_IN_QID_OFST 0 9699 /* the static priority associated with the txq */ 9700 #define MC_CMD_TCM_TXQ_INIT_IN_LABEL_OFST 4 9701 /* bitmask of the priority queues this txq is inserted into when inserted. */ 9702 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAGS_OFST 8 9703 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_GUARANTEED_LBN 0 9704 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_GUARANTEED_WIDTH 1 9705 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_NORMAL_LBN 1 9706 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_NORMAL_WIDTH 1 9707 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_LOW_LBN 2 9708 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_LOW_WIDTH 1 9709 /* the reaction point (RP) bucket */ 9710 #define MC_CMD_TCM_TXQ_INIT_IN_RP_BKT_OFST 12 9711 /* an already reserved bucket (typically set to bucket associated with outer 9712 * vswitch) 9713 */ 9714 #define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT1_OFST 16 9715 /* an already reserved bucket (typically set to bucket associated with inner 9716 * vswitch) 9717 */ 9718 #define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT2_OFST 20 9719 /* the min bucket (typically for ETS/minimum bandwidth) */ 9720 #define MC_CMD_TCM_TXQ_INIT_IN_MIN_BKT_OFST 24 9721 9722 /* MC_CMD_TCM_TXQ_INIT_EXT_IN msgrequest */ 9723 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_LEN 32 9724 /* the txq id */ 9725 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_QID_OFST 0 9726 /* the static priority associated with the txq */ 9727 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_NORMAL_OFST 4 9728 /* bitmask of the priority queues this txq is inserted into when inserted. */ 9729 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAGS_OFST 8 9730 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_GUARANTEED_LBN 0 9731 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_GUARANTEED_WIDTH 1 9732 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_NORMAL_LBN 1 9733 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_NORMAL_WIDTH 1 9734 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_LOW_LBN 2 9735 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_LOW_WIDTH 1 9736 /* the reaction point (RP) bucket */ 9737 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_RP_BKT_OFST 12 9738 /* an already reserved bucket (typically set to bucket associated with outer 9739 * vswitch) 9740 */ 9741 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT1_OFST 16 9742 /* an already reserved bucket (typically set to bucket associated with inner 9743 * vswitch) 9744 */ 9745 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT2_OFST 20 9746 /* the min bucket (typically for ETS/minimum bandwidth) */ 9747 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MIN_BKT_OFST 24 9748 /* the static priority associated with the txq */ 9749 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_GUARANTEED_OFST 28 9750 9751 /* MC_CMD_TCM_TXQ_INIT_OUT msgresponse */ 9752 #define MC_CMD_TCM_TXQ_INIT_OUT_LEN 0 9753 9754 9755 /***********************************/ 9756 /* MC_CMD_LINK_PIOBUF 9757 * Link a push I/O buffer to a TxQ 9758 */ 9759 #define MC_CMD_LINK_PIOBUF 0x92 9760 #undef MC_CMD_0x92_PRIVILEGE_CTG 9761 9762 #define MC_CMD_0x92_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 9763 9764 /* MC_CMD_LINK_PIOBUF_IN msgrequest */ 9765 #define MC_CMD_LINK_PIOBUF_IN_LEN 8 9766 /* Handle for allocated push I/O buffer. */ 9767 #define MC_CMD_LINK_PIOBUF_IN_PIOBUF_HANDLE_OFST 0 9768 /* Function Local Instance (VI) number. */ 9769 #define MC_CMD_LINK_PIOBUF_IN_TXQ_INSTANCE_OFST 4 9770 9771 /* MC_CMD_LINK_PIOBUF_OUT msgresponse */ 9772 #define MC_CMD_LINK_PIOBUF_OUT_LEN 0 9773 9774 9775 /***********************************/ 9776 /* MC_CMD_UNLINK_PIOBUF 9777 * Unlink a push I/O buffer from a TxQ 9778 */ 9779 #define MC_CMD_UNLINK_PIOBUF 0x93 9780 #undef MC_CMD_0x93_PRIVILEGE_CTG 9781 9782 #define MC_CMD_0x93_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 9783 9784 /* MC_CMD_UNLINK_PIOBUF_IN msgrequest */ 9785 #define MC_CMD_UNLINK_PIOBUF_IN_LEN 4 9786 /* Function Local Instance (VI) number. */ 9787 #define MC_CMD_UNLINK_PIOBUF_IN_TXQ_INSTANCE_OFST 0 9788 9789 /* MC_CMD_UNLINK_PIOBUF_OUT msgresponse */ 9790 #define MC_CMD_UNLINK_PIOBUF_OUT_LEN 0 9791 9792 9793 /***********************************/ 9794 /* MC_CMD_VSWITCH_ALLOC 9795 * allocate and initialise a v-switch. 9796 */ 9797 #define MC_CMD_VSWITCH_ALLOC 0x94 9798 #undef MC_CMD_0x94_PRIVILEGE_CTG 9799 9800 #define MC_CMD_0x94_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9801 9802 /* MC_CMD_VSWITCH_ALLOC_IN msgrequest */ 9803 #define MC_CMD_VSWITCH_ALLOC_IN_LEN 16 9804 /* The port to connect to the v-switch's upstream port. */ 9805 #define MC_CMD_VSWITCH_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 9806 /* The type of v-switch to create. */ 9807 #define MC_CMD_VSWITCH_ALLOC_IN_TYPE_OFST 4 9808 /* enum: VLAN */ 9809 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VLAN 0x1 9810 /* enum: VEB */ 9811 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEB 0x2 9812 /* enum: VEPA (obsolete) */ 9813 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEPA 0x3 9814 /* enum: MUX */ 9815 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_MUX 0x4 9816 /* enum: Snapper specific; semantics TBD */ 9817 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_TEST 0x5 9818 /* Flags controlling v-port creation */ 9819 #define MC_CMD_VSWITCH_ALLOC_IN_FLAGS_OFST 8 9820 #define MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_LBN 0 9821 #define MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_WIDTH 1 9822 /* The number of VLAN tags to allow for attached v-ports. For VLAN aggregators, 9823 * this must be one or greated, and the attached v-ports must have exactly this 9824 * number of tags. For other v-switch types, this must be zero of greater, and 9825 * is an upper limit on the number of VLAN tags for attached v-ports. An error 9826 * will be returned if existing configuration means we can't support attached 9827 * v-ports with this number of tags. 9828 */ 9829 #define MC_CMD_VSWITCH_ALLOC_IN_NUM_VLAN_TAGS_OFST 12 9830 9831 /* MC_CMD_VSWITCH_ALLOC_OUT msgresponse */ 9832 #define MC_CMD_VSWITCH_ALLOC_OUT_LEN 0 9833 9834 9835 /***********************************/ 9836 /* MC_CMD_VSWITCH_FREE 9837 * de-allocate a v-switch. 9838 */ 9839 #define MC_CMD_VSWITCH_FREE 0x95 9840 #undef MC_CMD_0x95_PRIVILEGE_CTG 9841 9842 #define MC_CMD_0x95_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9843 9844 /* MC_CMD_VSWITCH_FREE_IN msgrequest */ 9845 #define MC_CMD_VSWITCH_FREE_IN_LEN 4 9846 /* The port to which the v-switch is connected. */ 9847 #define MC_CMD_VSWITCH_FREE_IN_UPSTREAM_PORT_ID_OFST 0 9848 9849 /* MC_CMD_VSWITCH_FREE_OUT msgresponse */ 9850 #define MC_CMD_VSWITCH_FREE_OUT_LEN 0 9851 9852 9853 /***********************************/ 9854 /* MC_CMD_VPORT_ALLOC 9855 * allocate a v-port. 9856 */ 9857 #define MC_CMD_VPORT_ALLOC 0x96 9858 #undef MC_CMD_0x96_PRIVILEGE_CTG 9859 9860 #define MC_CMD_0x96_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9861 9862 /* MC_CMD_VPORT_ALLOC_IN msgrequest */ 9863 #define MC_CMD_VPORT_ALLOC_IN_LEN 20 9864 /* The port to which the v-switch is connected. */ 9865 #define MC_CMD_VPORT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 9866 /* The type of the new v-port. */ 9867 #define MC_CMD_VPORT_ALLOC_IN_TYPE_OFST 4 9868 /* enum: VLAN (obsolete) */ 9869 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VLAN 0x1 9870 /* enum: VEB (obsolete) */ 9871 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEB 0x2 9872 /* enum: VEPA (obsolete) */ 9873 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEPA 0x3 9874 /* enum: A normal v-port receives packets which match a specified MAC and/or 9875 * VLAN. 9876 */ 9877 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_NORMAL 0x4 9878 /* enum: An expansion v-port packets traffic which don't match any other 9879 * v-port. 9880 */ 9881 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_EXPANSION 0x5 9882 /* enum: An test v-port receives packets which match any filters installed by 9883 * its downstream components. 9884 */ 9885 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_TEST 0x6 9886 /* Flags controlling v-port creation */ 9887 #define MC_CMD_VPORT_ALLOC_IN_FLAGS_OFST 8 9888 #define MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_LBN 0 9889 #define MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_WIDTH 1 9890 /* The number of VLAN tags to insert/remove. An error will be returned if 9891 * incompatible with the number of VLAN tags specified for the upstream 9892 * v-switch. 9893 */ 9894 #define MC_CMD_VPORT_ALLOC_IN_NUM_VLAN_TAGS_OFST 12 9895 /* The actual VLAN tags to insert/remove */ 9896 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAGS_OFST 16 9897 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_LBN 0 9898 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_WIDTH 16 9899 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_LBN 16 9900 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_WIDTH 16 9901 9902 /* MC_CMD_VPORT_ALLOC_OUT msgresponse */ 9903 #define MC_CMD_VPORT_ALLOC_OUT_LEN 4 9904 /* The handle of the new v-port */ 9905 #define MC_CMD_VPORT_ALLOC_OUT_VPORT_ID_OFST 0 9906 9907 9908 /***********************************/ 9909 /* MC_CMD_VPORT_FREE 9910 * de-allocate a v-port. 9911 */ 9912 #define MC_CMD_VPORT_FREE 0x97 9913 #undef MC_CMD_0x97_PRIVILEGE_CTG 9914 9915 #define MC_CMD_0x97_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9916 9917 /* MC_CMD_VPORT_FREE_IN msgrequest */ 9918 #define MC_CMD_VPORT_FREE_IN_LEN 4 9919 /* The handle of the v-port */ 9920 #define MC_CMD_VPORT_FREE_IN_VPORT_ID_OFST 0 9921 9922 /* MC_CMD_VPORT_FREE_OUT msgresponse */ 9923 #define MC_CMD_VPORT_FREE_OUT_LEN 0 9924 9925 9926 /***********************************/ 9927 /* MC_CMD_VADAPTOR_ALLOC 9928 * allocate a v-adaptor. 9929 */ 9930 #define MC_CMD_VADAPTOR_ALLOC 0x98 9931 #undef MC_CMD_0x98_PRIVILEGE_CTG 9932 9933 #define MC_CMD_0x98_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9934 9935 /* MC_CMD_VADAPTOR_ALLOC_IN msgrequest */ 9936 #define MC_CMD_VADAPTOR_ALLOC_IN_LEN 30 9937 /* The port to connect to the v-adaptor's port. */ 9938 #define MC_CMD_VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 9939 /* Flags controlling v-adaptor creation */ 9940 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAGS_OFST 8 9941 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_LBN 0 9942 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_WIDTH 1 9943 /* The number of VLAN tags to strip on receive */ 9944 #define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLANS_OFST 12 9945 /* The number of VLAN tags to transparently insert/remove. */ 9946 #define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLAN_TAGS_OFST 16 9947 /* The actual VLAN tags to insert/remove */ 9948 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAGS_OFST 20 9949 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_0_LBN 0 9950 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_0_WIDTH 16 9951 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_1_LBN 16 9952 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_1_WIDTH 16 9953 /* The MAC address to assign to this v-adaptor */ 9954 #define MC_CMD_VADAPTOR_ALLOC_IN_MACADDR_OFST 24 9955 #define MC_CMD_VADAPTOR_ALLOC_IN_MACADDR_LEN 6 9956 /* enum: Derive the MAC address from the upstream port */ 9957 #define MC_CMD_VADAPTOR_ALLOC_IN_AUTO_MAC 0x0 9958 9959 /* MC_CMD_VADAPTOR_ALLOC_OUT msgresponse */ 9960 #define MC_CMD_VADAPTOR_ALLOC_OUT_LEN 0 9961 9962 9963 /***********************************/ 9964 /* MC_CMD_VADAPTOR_FREE 9965 * de-allocate a v-adaptor. 9966 */ 9967 #define MC_CMD_VADAPTOR_FREE 0x99 9968 #undef MC_CMD_0x99_PRIVILEGE_CTG 9969 9970 #define MC_CMD_0x99_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9971 9972 /* MC_CMD_VADAPTOR_FREE_IN msgrequest */ 9973 #define MC_CMD_VADAPTOR_FREE_IN_LEN 4 9974 /* The port to which the v-adaptor is connected. */ 9975 #define MC_CMD_VADAPTOR_FREE_IN_UPSTREAM_PORT_ID_OFST 0 9976 9977 /* MC_CMD_VADAPTOR_FREE_OUT msgresponse */ 9978 #define MC_CMD_VADAPTOR_FREE_OUT_LEN 0 9979 9980 9981 /***********************************/ 9982 /* MC_CMD_VADAPTOR_SET_MAC 9983 * assign a new MAC address to a v-adaptor. 9984 */ 9985 #define MC_CMD_VADAPTOR_SET_MAC 0x5d 9986 #undef MC_CMD_0x5d_PRIVILEGE_CTG 9987 9988 #define MC_CMD_0x5d_PRIVILEGE_CTG SRIOV_CTG_GENERAL 9989 9990 /* MC_CMD_VADAPTOR_SET_MAC_IN msgrequest */ 9991 #define MC_CMD_VADAPTOR_SET_MAC_IN_LEN 10 9992 /* The port to which the v-adaptor is connected. */ 9993 #define MC_CMD_VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID_OFST 0 9994 /* The new MAC address to assign to this v-adaptor */ 9995 #define MC_CMD_VADAPTOR_SET_MAC_IN_MACADDR_OFST 4 9996 #define MC_CMD_VADAPTOR_SET_MAC_IN_MACADDR_LEN 6 9997 9998 /* MC_CMD_VADAPTOR_SET_MAC_OUT msgresponse */ 9999 #define MC_CMD_VADAPTOR_SET_MAC_OUT_LEN 0 10000 10001 10002 /***********************************/ 10003 /* MC_CMD_VADAPTOR_GET_MAC 10004 * read the MAC address assigned to a v-adaptor. 10005 */ 10006 #define MC_CMD_VADAPTOR_GET_MAC 0x5e 10007 #undef MC_CMD_0x5e_PRIVILEGE_CTG 10008 10009 #define MC_CMD_0x5e_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10010 10011 /* MC_CMD_VADAPTOR_GET_MAC_IN msgrequest */ 10012 #define MC_CMD_VADAPTOR_GET_MAC_IN_LEN 4 10013 /* The port to which the v-adaptor is connected. */ 10014 #define MC_CMD_VADAPTOR_GET_MAC_IN_UPSTREAM_PORT_ID_OFST 0 10015 10016 /* MC_CMD_VADAPTOR_GET_MAC_OUT msgresponse */ 10017 #define MC_CMD_VADAPTOR_GET_MAC_OUT_LEN 6 10018 /* The MAC address assigned to this v-adaptor */ 10019 #define MC_CMD_VADAPTOR_GET_MAC_OUT_MACADDR_OFST 0 10020 #define MC_CMD_VADAPTOR_GET_MAC_OUT_MACADDR_LEN 6 10021 10022 10023 /***********************************/ 10024 /* MC_CMD_EVB_PORT_ASSIGN 10025 * assign a port to a PCI function. 10026 */ 10027 #define MC_CMD_EVB_PORT_ASSIGN 0x9a 10028 #undef MC_CMD_0x9a_PRIVILEGE_CTG 10029 10030 #define MC_CMD_0x9a_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10031 10032 /* MC_CMD_EVB_PORT_ASSIGN_IN msgrequest */ 10033 #define MC_CMD_EVB_PORT_ASSIGN_IN_LEN 8 10034 /* The port to assign. */ 10035 #define MC_CMD_EVB_PORT_ASSIGN_IN_PORT_ID_OFST 0 10036 /* The target function to modify. */ 10037 #define MC_CMD_EVB_PORT_ASSIGN_IN_FUNCTION_OFST 4 10038 #define MC_CMD_EVB_PORT_ASSIGN_IN_PF_LBN 0 10039 #define MC_CMD_EVB_PORT_ASSIGN_IN_PF_WIDTH 16 10040 #define MC_CMD_EVB_PORT_ASSIGN_IN_VF_LBN 16 10041 #define MC_CMD_EVB_PORT_ASSIGN_IN_VF_WIDTH 16 10042 10043 /* MC_CMD_EVB_PORT_ASSIGN_OUT msgresponse */ 10044 #define MC_CMD_EVB_PORT_ASSIGN_OUT_LEN 0 10045 10046 10047 /***********************************/ 10048 /* MC_CMD_RDWR_A64_REGIONS 10049 * Assign the 64 bit region addresses. 10050 */ 10051 #define MC_CMD_RDWR_A64_REGIONS 0x9b 10052 #undef MC_CMD_0x9b_PRIVILEGE_CTG 10053 10054 #define MC_CMD_0x9b_PRIVILEGE_CTG SRIOV_CTG_ADMIN 10055 10056 /* MC_CMD_RDWR_A64_REGIONS_IN msgrequest */ 10057 #define MC_CMD_RDWR_A64_REGIONS_IN_LEN 17 10058 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION0_OFST 0 10059 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION1_OFST 4 10060 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION2_OFST 8 10061 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION3_OFST 12 10062 /* Write enable bits 0-3, set to write, clear to read. */ 10063 #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_LBN 128 10064 #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_WIDTH 4 10065 #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_BYTE_OFST 16 10066 #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_BYTE_LEN 1 10067 10068 /* MC_CMD_RDWR_A64_REGIONS_OUT msgresponse: This data always included 10069 * regardless of state of write bits in the request. 10070 */ 10071 #define MC_CMD_RDWR_A64_REGIONS_OUT_LEN 16 10072 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION0_OFST 0 10073 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION1_OFST 4 10074 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION2_OFST 8 10075 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION3_OFST 12 10076 10077 10078 /***********************************/ 10079 /* MC_CMD_ONLOAD_STACK_ALLOC 10080 * Allocate an Onload stack ID. 10081 */ 10082 #define MC_CMD_ONLOAD_STACK_ALLOC 0x9c 10083 #undef MC_CMD_0x9c_PRIVILEGE_CTG 10084 10085 #define MC_CMD_0x9c_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 10086 10087 /* MC_CMD_ONLOAD_STACK_ALLOC_IN msgrequest */ 10088 #define MC_CMD_ONLOAD_STACK_ALLOC_IN_LEN 4 10089 /* The handle of the owning upstream port */ 10090 #define MC_CMD_ONLOAD_STACK_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 10091 10092 /* MC_CMD_ONLOAD_STACK_ALLOC_OUT msgresponse */ 10093 #define MC_CMD_ONLOAD_STACK_ALLOC_OUT_LEN 4 10094 /* The handle of the new Onload stack */ 10095 #define MC_CMD_ONLOAD_STACK_ALLOC_OUT_ONLOAD_STACK_ID_OFST 0 10096 10097 10098 /***********************************/ 10099 /* MC_CMD_ONLOAD_STACK_FREE 10100 * Free an Onload stack ID. 10101 */ 10102 #define MC_CMD_ONLOAD_STACK_FREE 0x9d 10103 #undef MC_CMD_0x9d_PRIVILEGE_CTG 10104 10105 #define MC_CMD_0x9d_PRIVILEGE_CTG SRIOV_CTG_ONLOAD 10106 10107 /* MC_CMD_ONLOAD_STACK_FREE_IN msgrequest */ 10108 #define MC_CMD_ONLOAD_STACK_FREE_IN_LEN 4 10109 /* The handle of the Onload stack */ 10110 #define MC_CMD_ONLOAD_STACK_FREE_IN_ONLOAD_STACK_ID_OFST 0 10111 10112 /* MC_CMD_ONLOAD_STACK_FREE_OUT msgresponse */ 10113 #define MC_CMD_ONLOAD_STACK_FREE_OUT_LEN 0 10114 10115 10116 /***********************************/ 10117 /* MC_CMD_RSS_CONTEXT_ALLOC 10118 * Allocate an RSS context. 10119 */ 10120 #define MC_CMD_RSS_CONTEXT_ALLOC 0x9e 10121 #undef MC_CMD_0x9e_PRIVILEGE_CTG 10122 10123 #define MC_CMD_0x9e_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10124 10125 /* MC_CMD_RSS_CONTEXT_ALLOC_IN msgrequest */ 10126 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN 12 10127 /* The handle of the owning upstream port */ 10128 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 10129 /* The type of context to allocate */ 10130 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_OFST 4 10131 /* enum: Allocate a context for exclusive use. The key and indirection table 10132 * must be explicitly configured. 10133 */ 10134 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE 0x0 10135 /* enum: Allocate a context for shared use; this will spread across a range of 10136 * queues, but the key and indirection table are pre-configured and may not be 10137 * changed. For this mode, NUM_QUEUES must 2, 4, 8, 16, 32 or 64. 10138 */ 10139 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED 0x1 10140 /* Number of queues spanned by this context, in the range 1-64; valid offsets 10141 * in the indirection table will be in the range 0 to NUM_QUEUES-1. 10142 */ 10143 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_NUM_QUEUES_OFST 8 10144 10145 /* MC_CMD_RSS_CONTEXT_ALLOC_OUT msgresponse */ 10146 #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN 4 10147 /* The handle of the new RSS context. This should be considered opaque to the 10148 * host, although a value of 0xFFFFFFFF is guaranteed never to be a valid 10149 * handle. 10150 */ 10151 #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_OFST 0 10152 /* enum: guaranteed invalid RSS context handle value */ 10153 #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_INVALID 0xffffffff 10154 10155 10156 /***********************************/ 10157 /* MC_CMD_RSS_CONTEXT_FREE 10158 * Free an RSS context. 10159 */ 10160 #define MC_CMD_RSS_CONTEXT_FREE 0x9f 10161 #undef MC_CMD_0x9f_PRIVILEGE_CTG 10162 10163 #define MC_CMD_0x9f_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10164 10165 /* MC_CMD_RSS_CONTEXT_FREE_IN msgrequest */ 10166 #define MC_CMD_RSS_CONTEXT_FREE_IN_LEN 4 10167 /* The handle of the RSS context */ 10168 #define MC_CMD_RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID_OFST 0 10169 10170 /* MC_CMD_RSS_CONTEXT_FREE_OUT msgresponse */ 10171 #define MC_CMD_RSS_CONTEXT_FREE_OUT_LEN 0 10172 10173 10174 /***********************************/ 10175 /* MC_CMD_RSS_CONTEXT_SET_KEY 10176 * Set the Toeplitz hash key for an RSS context. 10177 */ 10178 #define MC_CMD_RSS_CONTEXT_SET_KEY 0xa0 10179 #undef MC_CMD_0xa0_PRIVILEGE_CTG 10180 10181 #define MC_CMD_0xa0_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10182 10183 /* MC_CMD_RSS_CONTEXT_SET_KEY_IN msgrequest */ 10184 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN 44 10185 /* The handle of the RSS context */ 10186 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID_OFST 0 10187 /* The 40-byte Toeplitz hash key (TBD endianness issues?) */ 10188 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_OFST 4 10189 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN 40 10190 10191 /* MC_CMD_RSS_CONTEXT_SET_KEY_OUT msgresponse */ 10192 #define MC_CMD_RSS_CONTEXT_SET_KEY_OUT_LEN 0 10193 10194 10195 /***********************************/ 10196 /* MC_CMD_RSS_CONTEXT_GET_KEY 10197 * Get the Toeplitz hash key for an RSS context. 10198 */ 10199 #define MC_CMD_RSS_CONTEXT_GET_KEY 0xa1 10200 #undef MC_CMD_0xa1_PRIVILEGE_CTG 10201 10202 #define MC_CMD_0xa1_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10203 10204 /* MC_CMD_RSS_CONTEXT_GET_KEY_IN msgrequest */ 10205 #define MC_CMD_RSS_CONTEXT_GET_KEY_IN_LEN 4 10206 /* The handle of the RSS context */ 10207 #define MC_CMD_RSS_CONTEXT_GET_KEY_IN_RSS_CONTEXT_ID_OFST 0 10208 10209 /* MC_CMD_RSS_CONTEXT_GET_KEY_OUT msgresponse */ 10210 #define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_LEN 44 10211 /* The 40-byte Toeplitz hash key (TBD endianness issues?) */ 10212 #define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY_OFST 4 10213 #define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY_LEN 40 10214 10215 10216 /***********************************/ 10217 /* MC_CMD_RSS_CONTEXT_SET_TABLE 10218 * Set the indirection table for an RSS context. 10219 */ 10220 #define MC_CMD_RSS_CONTEXT_SET_TABLE 0xa2 10221 #undef MC_CMD_0xa2_PRIVILEGE_CTG 10222 10223 #define MC_CMD_0xa2_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10224 10225 /* MC_CMD_RSS_CONTEXT_SET_TABLE_IN msgrequest */ 10226 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN 132 10227 /* The handle of the RSS context */ 10228 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID_OFST 0 10229 /* The 128-byte indirection table (1 byte per entry) */ 10230 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_OFST 4 10231 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN 128 10232 10233 /* MC_CMD_RSS_CONTEXT_SET_TABLE_OUT msgresponse */ 10234 #define MC_CMD_RSS_CONTEXT_SET_TABLE_OUT_LEN 0 10235 10236 10237 /***********************************/ 10238 /* MC_CMD_RSS_CONTEXT_GET_TABLE 10239 * Get the indirection table for an RSS context. 10240 */ 10241 #define MC_CMD_RSS_CONTEXT_GET_TABLE 0xa3 10242 #undef MC_CMD_0xa3_PRIVILEGE_CTG 10243 10244 #define MC_CMD_0xa3_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10245 10246 /* MC_CMD_RSS_CONTEXT_GET_TABLE_IN msgrequest */ 10247 #define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_LEN 4 10248 /* The handle of the RSS context */ 10249 #define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_RSS_CONTEXT_ID_OFST 0 10250 10251 /* MC_CMD_RSS_CONTEXT_GET_TABLE_OUT msgresponse */ 10252 #define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_LEN 132 10253 /* The 128-byte indirection table (1 byte per entry) */ 10254 #define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_OFST 4 10255 #define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_LEN 128 10256 10257 10258 /***********************************/ 10259 /* MC_CMD_RSS_CONTEXT_SET_FLAGS 10260 * Set various control flags for an RSS context. 10261 */ 10262 #define MC_CMD_RSS_CONTEXT_SET_FLAGS 0xe1 10263 #undef MC_CMD_0xe1_PRIVILEGE_CTG 10264 10265 #define MC_CMD_0xe1_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10266 10267 /* MC_CMD_RSS_CONTEXT_SET_FLAGS_IN msgrequest */ 10268 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_LEN 8 10269 /* The handle of the RSS context */ 10270 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID_OFST 0 10271 /* Hash control flags. The _EN bits are always supported. The _MODE bits only 10272 * work when the firmware reports ADDITIONAL_RSS_MODES in 10273 * MC_CMD_GET_CAPABILITIES and override the _EN bits if any of them are not 0. 10274 * See the RSS_MODE structure for the meaning of the mode bits. 10275 */ 10276 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_FLAGS_OFST 4 10277 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_LBN 0 10278 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_WIDTH 1 10279 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_LBN 1 10280 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_WIDTH 1 10281 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_LBN 2 10282 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_WIDTH 1 10283 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_LBN 3 10284 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_WIDTH 1 10285 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_LBN 4 10286 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_WIDTH 4 10287 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_LBN 8 10288 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_WIDTH 4 10289 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE_LBN 12 10290 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE_WIDTH 4 10291 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_LBN 16 10292 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_WIDTH 4 10293 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_LBN 20 10294 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_WIDTH 4 10295 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE_LBN 24 10296 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE_WIDTH 4 10297 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_LBN 28 10298 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_WIDTH 4 10299 10300 /* MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT msgresponse */ 10301 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT_LEN 0 10302 10303 10304 /***********************************/ 10305 /* MC_CMD_RSS_CONTEXT_GET_FLAGS 10306 * Get various control flags for an RSS context. 10307 */ 10308 #define MC_CMD_RSS_CONTEXT_GET_FLAGS 0xe2 10309 #undef MC_CMD_0xe2_PRIVILEGE_CTG 10310 10311 #define MC_CMD_0xe2_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10312 10313 /* MC_CMD_RSS_CONTEXT_GET_FLAGS_IN msgrequest */ 10314 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_LEN 4 10315 /* The handle of the RSS context */ 10316 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_RSS_CONTEXT_ID_OFST 0 10317 10318 /* MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT msgresponse */ 10319 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN 8 10320 /* Hash control flags. If any _MODE bits are non-zero (which will only be true 10321 * when the firmware reports ADDITIONAL_RSS_MODES) then the _EN bits should be 10322 * disregarded (but are guaranteed to be consistent with the _MODE bits if 10323 * RSS_CONTEXT_SET_FLAGS has never been called for this context since it was 10324 * allocated). 10325 */ 10326 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_OFST 4 10327 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_LBN 0 10328 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_WIDTH 1 10329 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_LBN 1 10330 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_WIDTH 1 10331 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_LBN 2 10332 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_WIDTH 1 10333 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_LBN 3 10334 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_WIDTH 1 10335 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_LBN 4 10336 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_WIDTH 4 10337 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_LBN 8 10338 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_WIDTH 4 10339 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_LBN 12 10340 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_WIDTH 4 10341 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_LBN 16 10342 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_WIDTH 4 10343 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_LBN 20 10344 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_WIDTH 4 10345 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_LBN 24 10346 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_WIDTH 4 10347 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_LBN 28 10348 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_WIDTH 4 10349 10350 10351 /***********************************/ 10352 /* MC_CMD_DOT1P_MAPPING_ALLOC 10353 * Allocate a .1p mapping. 10354 */ 10355 #define MC_CMD_DOT1P_MAPPING_ALLOC 0xa4 10356 #undef MC_CMD_0xa4_PRIVILEGE_CTG 10357 10358 #define MC_CMD_0xa4_PRIVILEGE_CTG SRIOV_CTG_ADMIN 10359 10360 /* MC_CMD_DOT1P_MAPPING_ALLOC_IN msgrequest */ 10361 #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_LEN 8 10362 /* The handle of the owning upstream port */ 10363 #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0 10364 /* Number of queues spanned by this mapping, in the range 1-64; valid fixed 10365 * offsets in the mapping table will be in the range 0 to NUM_QUEUES-1, and 10366 * referenced RSS contexts must span no more than this number. 10367 */ 10368 #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_NUM_QUEUES_OFST 4 10369 10370 /* MC_CMD_DOT1P_MAPPING_ALLOC_OUT msgresponse */ 10371 #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_LEN 4 10372 /* The handle of the new .1p mapping. This should be considered opaque to the 10373 * host, although a value of 0xFFFFFFFF is guaranteed never to be a valid 10374 * handle. 10375 */ 10376 #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_OFST 0 10377 /* enum: guaranteed invalid .1p mapping handle value */ 10378 #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_INVALID 0xffffffff 10379 10380 10381 /***********************************/ 10382 /* MC_CMD_DOT1P_MAPPING_FREE 10383 * Free a .1p mapping. 10384 */ 10385 #define MC_CMD_DOT1P_MAPPING_FREE 0xa5 10386 #undef MC_CMD_0xa5_PRIVILEGE_CTG 10387 10388 #define MC_CMD_0xa5_PRIVILEGE_CTG SRIOV_CTG_ADMIN 10389 10390 /* MC_CMD_DOT1P_MAPPING_FREE_IN msgrequest */ 10391 #define MC_CMD_DOT1P_MAPPING_FREE_IN_LEN 4 10392 /* The handle of the .1p mapping */ 10393 #define MC_CMD_DOT1P_MAPPING_FREE_IN_DOT1P_MAPPING_ID_OFST 0 10394 10395 /* MC_CMD_DOT1P_MAPPING_FREE_OUT msgresponse */ 10396 #define MC_CMD_DOT1P_MAPPING_FREE_OUT_LEN 0 10397 10398 10399 /***********************************/ 10400 /* MC_CMD_DOT1P_MAPPING_SET_TABLE 10401 * Set the mapping table for a .1p mapping. 10402 */ 10403 #define MC_CMD_DOT1P_MAPPING_SET_TABLE 0xa6 10404 #undef MC_CMD_0xa6_PRIVILEGE_CTG 10405 10406 #define MC_CMD_0xa6_PRIVILEGE_CTG SRIOV_CTG_ADMIN 10407 10408 /* MC_CMD_DOT1P_MAPPING_SET_TABLE_IN msgrequest */ 10409 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_LEN 36 10410 /* The handle of the .1p mapping */ 10411 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_DOT1P_MAPPING_ID_OFST 0 10412 /* Per-priority mappings (1 32-bit word per entry - an offset or RSS context 10413 * handle) 10414 */ 10415 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_MAPPING_TABLE_OFST 4 10416 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_MAPPING_TABLE_LEN 32 10417 10418 /* MC_CMD_DOT1P_MAPPING_SET_TABLE_OUT msgresponse */ 10419 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_OUT_LEN 0 10420 10421 10422 /***********************************/ 10423 /* MC_CMD_DOT1P_MAPPING_GET_TABLE 10424 * Get the mapping table for a .1p mapping. 10425 */ 10426 #define MC_CMD_DOT1P_MAPPING_GET_TABLE 0xa7 10427 #undef MC_CMD_0xa7_PRIVILEGE_CTG 10428 10429 #define MC_CMD_0xa7_PRIVILEGE_CTG SRIOV_CTG_ADMIN 10430 10431 /* MC_CMD_DOT1P_MAPPING_GET_TABLE_IN msgrequest */ 10432 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_IN_LEN 4 10433 /* The handle of the .1p mapping */ 10434 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_IN_DOT1P_MAPPING_ID_OFST 0 10435 10436 /* MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT msgresponse */ 10437 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_LEN 36 10438 /* Per-priority mappings (1 32-bit word per entry - an offset or RSS context 10439 * handle) 10440 */ 10441 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_MAPPING_TABLE_OFST 4 10442 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_MAPPING_TABLE_LEN 32 10443 10444 10445 /***********************************/ 10446 /* MC_CMD_GET_VECTOR_CFG 10447 * Get Interrupt Vector config for this PF. 10448 */ 10449 #define MC_CMD_GET_VECTOR_CFG 0xbf 10450 #undef MC_CMD_0xbf_PRIVILEGE_CTG 10451 10452 #define MC_CMD_0xbf_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10453 10454 /* MC_CMD_GET_VECTOR_CFG_IN msgrequest */ 10455 #define MC_CMD_GET_VECTOR_CFG_IN_LEN 0 10456 10457 /* MC_CMD_GET_VECTOR_CFG_OUT msgresponse */ 10458 #define MC_CMD_GET_VECTOR_CFG_OUT_LEN 12 10459 /* Base absolute interrupt vector number. */ 10460 #define MC_CMD_GET_VECTOR_CFG_OUT_VEC_BASE_OFST 0 10461 /* Number of interrupt vectors allocate to this PF. */ 10462 #define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_PF_OFST 4 10463 /* Number of interrupt vectors to allocate per VF. */ 10464 #define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_VF_OFST 8 10465 10466 10467 /***********************************/ 10468 /* MC_CMD_SET_VECTOR_CFG 10469 * Set Interrupt Vector config for this PF. 10470 */ 10471 #define MC_CMD_SET_VECTOR_CFG 0xc0 10472 #undef MC_CMD_0xc0_PRIVILEGE_CTG 10473 10474 #define MC_CMD_0xc0_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10475 10476 /* MC_CMD_SET_VECTOR_CFG_IN msgrequest */ 10477 #define MC_CMD_SET_VECTOR_CFG_IN_LEN 12 10478 /* Base absolute interrupt vector number, or MC_CMD_RESOURCE_INSTANCE_ANY to 10479 * let the system find a suitable base. 10480 */ 10481 #define MC_CMD_SET_VECTOR_CFG_IN_VEC_BASE_OFST 0 10482 /* Number of interrupt vectors allocate to this PF. */ 10483 #define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_PF_OFST 4 10484 /* Number of interrupt vectors to allocate per VF. */ 10485 #define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_VF_OFST 8 10486 10487 /* MC_CMD_SET_VECTOR_CFG_OUT msgresponse */ 10488 #define MC_CMD_SET_VECTOR_CFG_OUT_LEN 0 10489 10490 10491 /***********************************/ 10492 /* MC_CMD_VPORT_ADD_MAC_ADDRESS 10493 * Add a MAC address to a v-port 10494 */ 10495 #define MC_CMD_VPORT_ADD_MAC_ADDRESS 0xa8 10496 #undef MC_CMD_0xa8_PRIVILEGE_CTG 10497 10498 #define MC_CMD_0xa8_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10499 10500 /* MC_CMD_VPORT_ADD_MAC_ADDRESS_IN msgrequest */ 10501 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN 10 10502 /* The handle of the v-port */ 10503 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID_OFST 0 10504 /* MAC address to add */ 10505 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_MACADDR_OFST 4 10506 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_MACADDR_LEN 6 10507 10508 /* MC_CMD_VPORT_ADD_MAC_ADDRESS_OUT msgresponse */ 10509 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_OUT_LEN 0 10510 10511 10512 /***********************************/ 10513 /* MC_CMD_VPORT_DEL_MAC_ADDRESS 10514 * Delete a MAC address from a v-port 10515 */ 10516 #define MC_CMD_VPORT_DEL_MAC_ADDRESS 0xa9 10517 #undef MC_CMD_0xa9_PRIVILEGE_CTG 10518 10519 #define MC_CMD_0xa9_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10520 10521 /* MC_CMD_VPORT_DEL_MAC_ADDRESS_IN msgrequest */ 10522 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN 10 10523 /* The handle of the v-port */ 10524 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID_OFST 0 10525 /* MAC address to add */ 10526 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_MACADDR_OFST 4 10527 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_MACADDR_LEN 6 10528 10529 /* MC_CMD_VPORT_DEL_MAC_ADDRESS_OUT msgresponse */ 10530 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_OUT_LEN 0 10531 10532 10533 /***********************************/ 10534 /* MC_CMD_VPORT_GET_MAC_ADDRESSES 10535 * Delete a MAC address from a v-port 10536 */ 10537 #define MC_CMD_VPORT_GET_MAC_ADDRESSES 0xaa 10538 #undef MC_CMD_0xaa_PRIVILEGE_CTG 10539 10540 #define MC_CMD_0xaa_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10541 10542 /* MC_CMD_VPORT_GET_MAC_ADDRESSES_IN msgrequest */ 10543 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN 4 10544 /* The handle of the v-port */ 10545 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID_OFST 0 10546 10547 /* MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT msgresponse */ 10548 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN 4 10549 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX 250 10550 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LEN(num) (4+6*(num)) 10551 /* The number of MAC addresses returned */ 10552 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT_OFST 0 10553 /* Array of MAC addresses */ 10554 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_OFST 4 10555 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_LEN 6 10556 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MINNUM 0 10557 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MAXNUM 41 10558 10559 10560 /***********************************/ 10561 /* MC_CMD_DUMP_BUFTBL_ENTRIES 10562 * Dump buffer table entries, mainly for command client debug use. Dumps 10563 * absolute entries, and does not use chunk handles. All entries must be in 10564 * range, and used for q page mapping, Although the latter restriction may be 10565 * lifted in future. 10566 */ 10567 #define MC_CMD_DUMP_BUFTBL_ENTRIES 0xab 10568 #undef MC_CMD_0xab_PRIVILEGE_CTG 10569 10570 #define MC_CMD_0xab_PRIVILEGE_CTG SRIOV_CTG_ADMIN 10571 10572 /* MC_CMD_DUMP_BUFTBL_ENTRIES_IN msgrequest */ 10573 #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_LEN 8 10574 /* Index of the first buffer table entry. */ 10575 #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_FIRSTID_OFST 0 10576 /* Number of buffer table entries to dump. */ 10577 #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_NUMENTRIES_OFST 4 10578 10579 /* MC_CMD_DUMP_BUFTBL_ENTRIES_OUT msgresponse */ 10580 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LENMIN 12 10581 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LENMAX 252 10582 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LEN(num) (0+12*(num)) 10583 /* Raw buffer table entries, layed out as BUFTBL_ENTRY. */ 10584 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_OFST 0 10585 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_LEN 12 10586 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_MINNUM 1 10587 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_MAXNUM 21 10588 10589 10590 /***********************************/ 10591 /* MC_CMD_SET_RXDP_CONFIG 10592 * Set global RXDP configuration settings 10593 */ 10594 #define MC_CMD_SET_RXDP_CONFIG 0xc1 10595 #undef MC_CMD_0xc1_PRIVILEGE_CTG 10596 10597 #define MC_CMD_0xc1_PRIVILEGE_CTG SRIOV_CTG_ADMIN 10598 10599 /* MC_CMD_SET_RXDP_CONFIG_IN msgrequest */ 10600 #define MC_CMD_SET_RXDP_CONFIG_IN_LEN 4 10601 #define MC_CMD_SET_RXDP_CONFIG_IN_DATA_OFST 0 10602 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_LBN 0 10603 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_WIDTH 1 10604 10605 /* MC_CMD_SET_RXDP_CONFIG_OUT msgresponse */ 10606 #define MC_CMD_SET_RXDP_CONFIG_OUT_LEN 0 10607 10608 10609 /***********************************/ 10610 /* MC_CMD_GET_RXDP_CONFIG 10611 * Get global RXDP configuration settings 10612 */ 10613 #define MC_CMD_GET_RXDP_CONFIG 0xc2 10614 #undef MC_CMD_0xc2_PRIVILEGE_CTG 10615 10616 #define MC_CMD_0xc2_PRIVILEGE_CTG SRIOV_CTG_ADMIN 10617 10618 /* MC_CMD_GET_RXDP_CONFIG_IN msgrequest */ 10619 #define MC_CMD_GET_RXDP_CONFIG_IN_LEN 0 10620 10621 /* MC_CMD_GET_RXDP_CONFIG_OUT msgresponse */ 10622 #define MC_CMD_GET_RXDP_CONFIG_OUT_LEN 4 10623 #define MC_CMD_GET_RXDP_CONFIG_OUT_DATA_OFST 0 10624 #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_LBN 0 10625 #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_WIDTH 1 10626 10627 10628 /***********************************/ 10629 /* MC_CMD_GET_CLOCK 10630 * Return the system and PDCPU clock frequencies. 10631 */ 10632 #define MC_CMD_GET_CLOCK 0xac 10633 #undef MC_CMD_0xac_PRIVILEGE_CTG 10634 10635 #define MC_CMD_0xac_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10636 10637 /* MC_CMD_GET_CLOCK_IN msgrequest */ 10638 #define MC_CMD_GET_CLOCK_IN_LEN 0 10639 10640 /* MC_CMD_GET_CLOCK_OUT msgresponse */ 10641 #define MC_CMD_GET_CLOCK_OUT_LEN 8 10642 /* System frequency, MHz */ 10643 #define MC_CMD_GET_CLOCK_OUT_SYS_FREQ_OFST 0 10644 /* DPCPU frequency, MHz */ 10645 #define MC_CMD_GET_CLOCK_OUT_DPCPU_FREQ_OFST 4 10646 10647 10648 /***********************************/ 10649 /* MC_CMD_SET_CLOCK 10650 * Control the system and DPCPU clock frequencies. Changes are lost reboot. 10651 */ 10652 #define MC_CMD_SET_CLOCK 0xad 10653 #undef MC_CMD_0xad_PRIVILEGE_CTG 10654 10655 #define MC_CMD_0xad_PRIVILEGE_CTG SRIOV_CTG_ADMIN 10656 10657 /* MC_CMD_SET_CLOCK_IN msgrequest */ 10658 #define MC_CMD_SET_CLOCK_IN_LEN 28 10659 /* Requested frequency in MHz for system clock domain */ 10660 #define MC_CMD_SET_CLOCK_IN_SYS_FREQ_OFST 0 10661 /* enum: Leave the system clock domain frequency unchanged */ 10662 #define MC_CMD_SET_CLOCK_IN_SYS_DOMAIN_DONT_CHANGE 0x0 10663 /* Requested frequency in MHz for inter-core clock domain */ 10664 #define MC_CMD_SET_CLOCK_IN_ICORE_FREQ_OFST 4 10665 /* enum: Leave the inter-core clock domain frequency unchanged */ 10666 #define MC_CMD_SET_CLOCK_IN_ICORE_DOMAIN_DONT_CHANGE 0x0 10667 /* Requested frequency in MHz for DPCPU clock domain */ 10668 #define MC_CMD_SET_CLOCK_IN_DPCPU_FREQ_OFST 8 10669 /* enum: Leave the DPCPU clock domain frequency unchanged */ 10670 #define MC_CMD_SET_CLOCK_IN_DPCPU_DOMAIN_DONT_CHANGE 0x0 10671 /* Requested frequency in MHz for PCS clock domain */ 10672 #define MC_CMD_SET_CLOCK_IN_PCS_FREQ_OFST 12 10673 /* enum: Leave the PCS clock domain frequency unchanged */ 10674 #define MC_CMD_SET_CLOCK_IN_PCS_DOMAIN_DONT_CHANGE 0x0 10675 /* Requested frequency in MHz for MC clock domain */ 10676 #define MC_CMD_SET_CLOCK_IN_MC_FREQ_OFST 16 10677 /* enum: Leave the MC clock domain frequency unchanged */ 10678 #define MC_CMD_SET_CLOCK_IN_MC_DOMAIN_DONT_CHANGE 0x0 10679 /* Requested frequency in MHz for rmon clock domain */ 10680 #define MC_CMD_SET_CLOCK_IN_RMON_FREQ_OFST 20 10681 /* enum: Leave the rmon clock domain frequency unchanged */ 10682 #define MC_CMD_SET_CLOCK_IN_RMON_DOMAIN_DONT_CHANGE 0x0 10683 /* Requested frequency in MHz for vswitch clock domain */ 10684 #define MC_CMD_SET_CLOCK_IN_VSWITCH_FREQ_OFST 24 10685 /* enum: Leave the vswitch clock domain frequency unchanged */ 10686 #define MC_CMD_SET_CLOCK_IN_VSWITCH_DOMAIN_DONT_CHANGE 0x0 10687 10688 /* MC_CMD_SET_CLOCK_OUT msgresponse */ 10689 #define MC_CMD_SET_CLOCK_OUT_LEN 28 10690 /* Resulting system frequency in MHz */ 10691 #define MC_CMD_SET_CLOCK_OUT_SYS_FREQ_OFST 0 10692 /* enum: The system clock domain doesn't exist */ 10693 #define MC_CMD_SET_CLOCK_OUT_SYS_DOMAIN_UNSUPPORTED 0x0 10694 /* Resulting inter-core frequency in MHz */ 10695 #define MC_CMD_SET_CLOCK_OUT_ICORE_FREQ_OFST 4 10696 /* enum: The inter-core clock domain doesn't exist / isn't used */ 10697 #define MC_CMD_SET_CLOCK_OUT_ICORE_DOMAIN_UNSUPPORTED 0x0 10698 /* Resulting DPCPU frequency in MHz */ 10699 #define MC_CMD_SET_CLOCK_OUT_DPCPU_FREQ_OFST 8 10700 /* enum: The dpcpu clock domain doesn't exist */ 10701 #define MC_CMD_SET_CLOCK_OUT_DPCPU_DOMAIN_UNSUPPORTED 0x0 10702 /* Resulting PCS frequency in MHz */ 10703 #define MC_CMD_SET_CLOCK_OUT_PCS_FREQ_OFST 12 10704 /* enum: The PCS clock domain doesn't exist / isn't controlled */ 10705 #define MC_CMD_SET_CLOCK_OUT_PCS_DOMAIN_UNSUPPORTED 0x0 10706 /* Resulting MC frequency in MHz */ 10707 #define MC_CMD_SET_CLOCK_OUT_MC_FREQ_OFST 16 10708 /* enum: The MC clock domain doesn't exist / isn't controlled */ 10709 #define MC_CMD_SET_CLOCK_OUT_MC_DOMAIN_UNSUPPORTED 0x0 10710 /* Resulting rmon frequency in MHz */ 10711 #define MC_CMD_SET_CLOCK_OUT_RMON_FREQ_OFST 20 10712 /* enum: The rmon clock domain doesn't exist / isn't controlled */ 10713 #define MC_CMD_SET_CLOCK_OUT_RMON_DOMAIN_UNSUPPORTED 0x0 10714 /* Resulting vswitch frequency in MHz */ 10715 #define MC_CMD_SET_CLOCK_OUT_VSWITCH_FREQ_OFST 24 10716 /* enum: The vswitch clock domain doesn't exist / isn't controlled */ 10717 #define MC_CMD_SET_CLOCK_OUT_VSWITCH_DOMAIN_UNSUPPORTED 0x0 10718 10719 10720 /***********************************/ 10721 /* MC_CMD_DPCPU_RPC 10722 * Send an arbitrary DPCPU message. 10723 */ 10724 #define MC_CMD_DPCPU_RPC 0xae 10725 #undef MC_CMD_0xae_PRIVILEGE_CTG 10726 10727 #define MC_CMD_0xae_PRIVILEGE_CTG SRIOV_CTG_ADMIN 10728 10729 /* MC_CMD_DPCPU_RPC_IN msgrequest */ 10730 #define MC_CMD_DPCPU_RPC_IN_LEN 36 10731 #define MC_CMD_DPCPU_RPC_IN_CPU_OFST 0 10732 /* enum: RxDPCPU0 */ 10733 #define MC_CMD_DPCPU_RPC_IN_DPCPU_RX0 0x0 10734 /* enum: TxDPCPU0 */ 10735 #define MC_CMD_DPCPU_RPC_IN_DPCPU_TX0 0x1 10736 /* enum: TxDPCPU1 */ 10737 #define MC_CMD_DPCPU_RPC_IN_DPCPU_TX1 0x2 10738 /* enum: RxDPCPU1 (Medford only) */ 10739 #define MC_CMD_DPCPU_RPC_IN_DPCPU_RX1 0x3 10740 /* enum: RxDPCPU (will be for the calling function; for now, just an alias of 10741 * DPCPU_RX0) 10742 */ 10743 #define MC_CMD_DPCPU_RPC_IN_DPCPU_RX 0x80 10744 /* enum: TxDPCPU (will be for the calling function; for now, just an alias of 10745 * DPCPU_TX0) 10746 */ 10747 #define MC_CMD_DPCPU_RPC_IN_DPCPU_TX 0x81 10748 /* First 8 bits [39:32] of DATA are consumed by MC-DPCPU protocol and must be 10749 * initialised to zero 10750 */ 10751 #define MC_CMD_DPCPU_RPC_IN_DATA_OFST 4 10752 #define MC_CMD_DPCPU_RPC_IN_DATA_LEN 32 10753 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_CMDNUM_LBN 8 10754 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_CMDNUM_WIDTH 8 10755 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_READ 0x6 /* enum */ 10756 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_WRITE 0x7 /* enum */ 10757 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_SELF_TEST 0xc /* enum */ 10758 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_CSR_ACCESS 0xe /* enum */ 10759 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_READ 0x46 /* enum */ 10760 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_WRITE 0x47 /* enum */ 10761 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_SELF_TEST 0x4a /* enum */ 10762 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_CSR_ACCESS 0x4c /* enum */ 10763 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_SET_MC_REPLAY_CNTXT 0x4d /* enum */ 10764 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_OBJID_LBN 16 10765 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_OBJID_WIDTH 16 10766 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_ADDR_LBN 16 10767 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_ADDR_WIDTH 16 10768 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_COUNT_LBN 48 10769 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_COUNT_WIDTH 16 10770 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_INFO_LBN 16 10771 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_INFO_WIDTH 240 10772 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_LBN 16 10773 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_WIDTH 16 10774 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_STOP_RETURN_RESULT 0x0 /* enum */ 10775 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_READ 0x1 /* enum */ 10776 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_WRITE 0x2 /* enum */ 10777 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_WRITE_READ 0x3 /* enum */ 10778 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_PIPELINED_READ 0x4 /* enum */ 10779 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_START_DELAY_LBN 48 10780 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_START_DELAY_WIDTH 16 10781 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_RPT_COUNT_LBN 64 10782 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_RPT_COUNT_WIDTH 16 10783 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_GAP_DELAY_LBN 80 10784 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_GAP_DELAY_WIDTH 16 10785 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_LBN 16 10786 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_WIDTH 16 10787 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_CUT_THROUGH 0x1 /* enum */ 10788 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_STORE_FORWARD 0x2 /* enum */ 10789 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_STORE_FORWARD_FIRST 0x3 /* enum */ 10790 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_CNTXT_LBN 64 10791 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_CNTXT_WIDTH 16 10792 #define MC_CMD_DPCPU_RPC_IN_WDATA_OFST 12 10793 #define MC_CMD_DPCPU_RPC_IN_WDATA_LEN 24 10794 /* Register data to write. Only valid in write/write-read. */ 10795 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_DATA_OFST 16 10796 /* Register address. */ 10797 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_ADDRESS_OFST 20 10798 10799 /* MC_CMD_DPCPU_RPC_OUT msgresponse */ 10800 #define MC_CMD_DPCPU_RPC_OUT_LEN 36 10801 #define MC_CMD_DPCPU_RPC_OUT_RC_OFST 0 10802 /* DATA */ 10803 #define MC_CMD_DPCPU_RPC_OUT_DATA_OFST 4 10804 #define MC_CMD_DPCPU_RPC_OUT_DATA_LEN 32 10805 #define MC_CMD_DPCPU_RPC_OUT_HDR_CMD_RESP_ERRCODE_LBN 32 10806 #define MC_CMD_DPCPU_RPC_OUT_HDR_CMD_RESP_ERRCODE_WIDTH 16 10807 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_COUNT_LBN 48 10808 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_COUNT_WIDTH 16 10809 #define MC_CMD_DPCPU_RPC_OUT_RDATA_OFST 12 10810 #define MC_CMD_DPCPU_RPC_OUT_RDATA_LEN 24 10811 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_1_OFST 12 10812 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_2_OFST 16 10813 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_3_OFST 20 10814 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_4_OFST 24 10815 10816 10817 /***********************************/ 10818 /* MC_CMD_TRIGGER_INTERRUPT 10819 * Trigger an interrupt by prodding the BIU. 10820 */ 10821 #define MC_CMD_TRIGGER_INTERRUPT 0xe3 10822 #undef MC_CMD_0xe3_PRIVILEGE_CTG 10823 10824 #define MC_CMD_0xe3_PRIVILEGE_CTG SRIOV_CTG_GENERAL 10825 10826 /* MC_CMD_TRIGGER_INTERRUPT_IN msgrequest */ 10827 #define MC_CMD_TRIGGER_INTERRUPT_IN_LEN 4 10828 /* Interrupt level relative to base for function. */ 10829 #define MC_CMD_TRIGGER_INTERRUPT_IN_INTR_LEVEL_OFST 0 10830 10831 /* MC_CMD_TRIGGER_INTERRUPT_OUT msgresponse */ 10832 #define MC_CMD_TRIGGER_INTERRUPT_OUT_LEN 0 10833 10834 10835 /***********************************/ 10836 /* MC_CMD_SHMBOOT_OP 10837 * Special operations to support (for now) shmboot. 10838 */ 10839 #define MC_CMD_SHMBOOT_OP 0xe6 10840 #undef MC_CMD_0xe6_PRIVILEGE_CTG 10841 10842 #define MC_CMD_0xe6_PRIVILEGE_CTG SRIOV_CTG_ADMIN 10843 10844 /* MC_CMD_SHMBOOT_OP_IN msgrequest */ 10845 #define MC_CMD_SHMBOOT_OP_IN_LEN 4 10846 /* Identifies the operation to perform */ 10847 #define MC_CMD_SHMBOOT_OP_IN_SHMBOOT_OP_OFST 0 10848 /* enum: Copy slave_data section to the slave core. (Greenport only) */ 10849 #define MC_CMD_SHMBOOT_OP_IN_PUSH_SLAVE_DATA 0x0 10850 10851 /* MC_CMD_SHMBOOT_OP_OUT msgresponse */ 10852 #define MC_CMD_SHMBOOT_OP_OUT_LEN 0 10853 10854 10855 /***********************************/ 10856 /* MC_CMD_CAP_BLK_READ 10857 * Read multiple 64bit words from capture block memory 10858 */ 10859 #define MC_CMD_CAP_BLK_READ 0xe7 10860 #undef MC_CMD_0xe7_PRIVILEGE_CTG 10861 10862 #define MC_CMD_0xe7_PRIVILEGE_CTG SRIOV_CTG_ADMIN 10863 10864 /* MC_CMD_CAP_BLK_READ_IN msgrequest */ 10865 #define MC_CMD_CAP_BLK_READ_IN_LEN 12 10866 #define MC_CMD_CAP_BLK_READ_IN_CAP_REG_OFST 0 10867 #define MC_CMD_CAP_BLK_READ_IN_ADDR_OFST 4 10868 #define MC_CMD_CAP_BLK_READ_IN_COUNT_OFST 8 10869 10870 /* MC_CMD_CAP_BLK_READ_OUT msgresponse */ 10871 #define MC_CMD_CAP_BLK_READ_OUT_LENMIN 8 10872 #define MC_CMD_CAP_BLK_READ_OUT_LENMAX 248 10873 #define MC_CMD_CAP_BLK_READ_OUT_LEN(num) (0+8*(num)) 10874 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_OFST 0 10875 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LEN 8 10876 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LO_OFST 0 10877 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_HI_OFST 4 10878 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_MINNUM 1 10879 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_MAXNUM 31 10880 10881 10882 /***********************************/ 10883 /* MC_CMD_DUMP_DO 10884 * Take a dump of the DUT state 10885 */ 10886 #define MC_CMD_DUMP_DO 0xe8 10887 #undef MC_CMD_0xe8_PRIVILEGE_CTG 10888 10889 #define MC_CMD_0xe8_PRIVILEGE_CTG SRIOV_CTG_ADMIN 10890 10891 /* MC_CMD_DUMP_DO_IN msgrequest */ 10892 #define MC_CMD_DUMP_DO_IN_LEN 52 10893 #define MC_CMD_DUMP_DO_IN_PADDING_OFST 0 10894 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_OFST 4 10895 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM 0x0 /* enum */ 10896 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_DEFAULT 0x1 /* enum */ 10897 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_TYPE_OFST 8 10898 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_NVRAM 0x1 /* enum */ 10899 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_HOST_MEMORY 0x2 /* enum */ 10900 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_HOST_MEMORY_MLI 0x3 /* enum */ 10901 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_UART 0x4 /* enum */ 10902 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 12 10903 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_OFST 16 10904 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 12 10905 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 16 10906 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 12 10907 #define MC_CMD_DUMP_DO_IN_HOST_MEMORY_MLI_PAGE_SIZE 0x1000 /* enum */ 10908 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 16 10909 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 20 10910 #define MC_CMD_DUMP_DO_IN_HOST_MEMORY_MLI_MAX_DEPTH 0x2 /* enum */ 10911 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_OFST 12 10912 /* enum: The uart port this command was received over (if using a uart 10913 * transport) 10914 */ 10915 #define MC_CMD_DUMP_DO_IN_UART_PORT_SRC 0xff 10916 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_SIZE_OFST 24 10917 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_OFST 28 10918 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM 0x0 /* enum */ 10919 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_NVRAM_DUMP_PARTITION 0x1 /* enum */ 10920 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_TYPE_OFST 32 10921 /* Enum values, see field(s): */ 10922 /* MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */ 10923 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 36 10924 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_OFST 40 10925 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 36 10926 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 40 10927 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 36 10928 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 40 10929 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 44 10930 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_UART_PORT_OFST 36 10931 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_SIZE_OFST 48 10932 10933 /* MC_CMD_DUMP_DO_OUT msgresponse */ 10934 #define MC_CMD_DUMP_DO_OUT_LEN 4 10935 #define MC_CMD_DUMP_DO_OUT_DUMPFILE_SIZE_OFST 0 10936 10937 10938 /***********************************/ 10939 /* MC_CMD_DUMP_CONFIGURE_UNSOLICITED 10940 * Configure unsolicited dumps 10941 */ 10942 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED 0xe9 10943 #undef MC_CMD_0xe9_PRIVILEGE_CTG 10944 10945 #define MC_CMD_0xe9_PRIVILEGE_CTG SRIOV_CTG_ADMIN 10946 10947 /* MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN msgrequest */ 10948 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_LEN 52 10949 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_ENABLE_OFST 0 10950 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_OFST 4 10951 /* Enum values, see field(s): */ 10952 /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC */ 10953 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_TYPE_OFST 8 10954 /* Enum values, see field(s): */ 10955 /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */ 10956 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 12 10957 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_OFST 16 10958 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 12 10959 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 16 10960 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 12 10961 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 16 10962 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 20 10963 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_OFST 12 10964 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_SIZE_OFST 24 10965 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_OFST 28 10966 /* Enum values, see field(s): */ 10967 /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPFILE_DST */ 10968 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_TYPE_OFST 32 10969 /* Enum values, see field(s): */ 10970 /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */ 10971 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 36 10972 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_OFST 40 10973 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 36 10974 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 40 10975 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 36 10976 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 40 10977 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 44 10978 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_UART_PORT_OFST 36 10979 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_SIZE_OFST 48 10980 10981 10982 /***********************************/ 10983 /* MC_CMD_SET_PSU 10984 * Adjusts power supply parameters. This is a warranty-voiding operation. 10985 * Returns: ENOENT if the parameter or rail specified does not exist, EINVAL if 10986 * the parameter is out of range. 10987 */ 10988 #define MC_CMD_SET_PSU 0xea 10989 #undef MC_CMD_0xea_PRIVILEGE_CTG 10990 10991 #define MC_CMD_0xea_PRIVILEGE_CTG SRIOV_CTG_ADMIN 10992 10993 /* MC_CMD_SET_PSU_IN msgrequest */ 10994 #define MC_CMD_SET_PSU_IN_LEN 12 10995 #define MC_CMD_SET_PSU_IN_PARAM_OFST 0 10996 #define MC_CMD_SET_PSU_IN_PARAM_SUPPLY_VOLTAGE 0x0 /* enum */ 10997 #define MC_CMD_SET_PSU_IN_RAIL_OFST 4 10998 #define MC_CMD_SET_PSU_IN_RAIL_0V9 0x0 /* enum */ 10999 #define MC_CMD_SET_PSU_IN_RAIL_1V2 0x1 /* enum */ 11000 /* desired value, eg voltage in mV */ 11001 #define MC_CMD_SET_PSU_IN_VALUE_OFST 8 11002 11003 /* MC_CMD_SET_PSU_OUT msgresponse */ 11004 #define MC_CMD_SET_PSU_OUT_LEN 0 11005 11006 11007 /***********************************/ 11008 /* MC_CMD_GET_FUNCTION_INFO 11009 * Get function information. PF and VF number. 11010 */ 11011 #define MC_CMD_GET_FUNCTION_INFO 0xec 11012 #undef MC_CMD_0xec_PRIVILEGE_CTG 11013 11014 #define MC_CMD_0xec_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11015 11016 /* MC_CMD_GET_FUNCTION_INFO_IN msgrequest */ 11017 #define MC_CMD_GET_FUNCTION_INFO_IN_LEN 0 11018 11019 /* MC_CMD_GET_FUNCTION_INFO_OUT msgresponse */ 11020 #define MC_CMD_GET_FUNCTION_INFO_OUT_LEN 8 11021 #define MC_CMD_GET_FUNCTION_INFO_OUT_PF_OFST 0 11022 #define MC_CMD_GET_FUNCTION_INFO_OUT_VF_OFST 4 11023 11024 11025 /***********************************/ 11026 /* MC_CMD_ENABLE_OFFLINE_BIST 11027 * Enters offline BIST mode. All queues are torn down, chip enters quiescent 11028 * mode, calling function gets exclusive MCDI ownership. The only way out is 11029 * reboot. 11030 */ 11031 #define MC_CMD_ENABLE_OFFLINE_BIST 0xed 11032 #undef MC_CMD_0xed_PRIVILEGE_CTG 11033 11034 #define MC_CMD_0xed_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11035 11036 /* MC_CMD_ENABLE_OFFLINE_BIST_IN msgrequest */ 11037 #define MC_CMD_ENABLE_OFFLINE_BIST_IN_LEN 0 11038 11039 /* MC_CMD_ENABLE_OFFLINE_BIST_OUT msgresponse */ 11040 #define MC_CMD_ENABLE_OFFLINE_BIST_OUT_LEN 0 11041 11042 11043 /***********************************/ 11044 /* MC_CMD_UART_SEND_DATA 11045 * Send checksummed[sic] block of data over the uart. Response is a placeholder 11046 * should we wish to make this reliable; currently requests are fire-and- 11047 * forget. 11048 */ 11049 #define MC_CMD_UART_SEND_DATA 0xee 11050 #undef MC_CMD_0xee_PRIVILEGE_CTG 11051 11052 #define MC_CMD_0xee_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11053 11054 /* MC_CMD_UART_SEND_DATA_OUT msgrequest */ 11055 #define MC_CMD_UART_SEND_DATA_OUT_LENMIN 16 11056 #define MC_CMD_UART_SEND_DATA_OUT_LENMAX 252 11057 #define MC_CMD_UART_SEND_DATA_OUT_LEN(num) (16+1*(num)) 11058 /* CRC32 over OFFSET, LENGTH, RESERVED, DATA */ 11059 #define MC_CMD_UART_SEND_DATA_OUT_CHECKSUM_OFST 0 11060 /* Offset at which to write the data */ 11061 #define MC_CMD_UART_SEND_DATA_OUT_OFFSET_OFST 4 11062 /* Length of data */ 11063 #define MC_CMD_UART_SEND_DATA_OUT_LENGTH_OFST 8 11064 /* Reserved for future use */ 11065 #define MC_CMD_UART_SEND_DATA_OUT_RESERVED_OFST 12 11066 #define MC_CMD_UART_SEND_DATA_OUT_DATA_OFST 16 11067 #define MC_CMD_UART_SEND_DATA_OUT_DATA_LEN 1 11068 #define MC_CMD_UART_SEND_DATA_OUT_DATA_MINNUM 0 11069 #define MC_CMD_UART_SEND_DATA_OUT_DATA_MAXNUM 236 11070 11071 /* MC_CMD_UART_SEND_DATA_IN msgresponse */ 11072 #define MC_CMD_UART_SEND_DATA_IN_LEN 0 11073 11074 11075 /***********************************/ 11076 /* MC_CMD_UART_RECV_DATA 11077 * Request checksummed[sic] block of data over the uart. Only a placeholder, 11078 * subject to change and not currently implemented. 11079 */ 11080 #define MC_CMD_UART_RECV_DATA 0xef 11081 #undef MC_CMD_0xef_PRIVILEGE_CTG 11082 11083 #define MC_CMD_0xef_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11084 11085 /* MC_CMD_UART_RECV_DATA_OUT msgrequest */ 11086 #define MC_CMD_UART_RECV_DATA_OUT_LEN 16 11087 /* CRC32 over OFFSET, LENGTH, RESERVED */ 11088 #define MC_CMD_UART_RECV_DATA_OUT_CHECKSUM_OFST 0 11089 /* Offset from which to read the data */ 11090 #define MC_CMD_UART_RECV_DATA_OUT_OFFSET_OFST 4 11091 /* Length of data */ 11092 #define MC_CMD_UART_RECV_DATA_OUT_LENGTH_OFST 8 11093 /* Reserved for future use */ 11094 #define MC_CMD_UART_RECV_DATA_OUT_RESERVED_OFST 12 11095 11096 /* MC_CMD_UART_RECV_DATA_IN msgresponse */ 11097 #define MC_CMD_UART_RECV_DATA_IN_LENMIN 16 11098 #define MC_CMD_UART_RECV_DATA_IN_LENMAX 252 11099 #define MC_CMD_UART_RECV_DATA_IN_LEN(num) (16+1*(num)) 11100 /* CRC32 over RESERVED1, RESERVED2, RESERVED3, DATA */ 11101 #define MC_CMD_UART_RECV_DATA_IN_CHECKSUM_OFST 0 11102 /* Offset at which to write the data */ 11103 #define MC_CMD_UART_RECV_DATA_IN_RESERVED1_OFST 4 11104 /* Length of data */ 11105 #define MC_CMD_UART_RECV_DATA_IN_RESERVED2_OFST 8 11106 /* Reserved for future use */ 11107 #define MC_CMD_UART_RECV_DATA_IN_RESERVED3_OFST 12 11108 #define MC_CMD_UART_RECV_DATA_IN_DATA_OFST 16 11109 #define MC_CMD_UART_RECV_DATA_IN_DATA_LEN 1 11110 #define MC_CMD_UART_RECV_DATA_IN_DATA_MINNUM 0 11111 #define MC_CMD_UART_RECV_DATA_IN_DATA_MAXNUM 236 11112 11113 11114 /***********************************/ 11115 /* MC_CMD_READ_FUSES 11116 * Read data programmed into the device One-Time-Programmable (OTP) Fuses 11117 */ 11118 #define MC_CMD_READ_FUSES 0xf0 11119 #undef MC_CMD_0xf0_PRIVILEGE_CTG 11120 11121 #define MC_CMD_0xf0_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11122 11123 /* MC_CMD_READ_FUSES_IN msgrequest */ 11124 #define MC_CMD_READ_FUSES_IN_LEN 8 11125 /* Offset in OTP to read */ 11126 #define MC_CMD_READ_FUSES_IN_OFFSET_OFST 0 11127 /* Length of data to read in bytes */ 11128 #define MC_CMD_READ_FUSES_IN_LENGTH_OFST 4 11129 11130 /* MC_CMD_READ_FUSES_OUT msgresponse */ 11131 #define MC_CMD_READ_FUSES_OUT_LENMIN 4 11132 #define MC_CMD_READ_FUSES_OUT_LENMAX 252 11133 #define MC_CMD_READ_FUSES_OUT_LEN(num) (4+1*(num)) 11134 /* Length of returned OTP data in bytes */ 11135 #define MC_CMD_READ_FUSES_OUT_LENGTH_OFST 0 11136 /* Returned data */ 11137 #define MC_CMD_READ_FUSES_OUT_DATA_OFST 4 11138 #define MC_CMD_READ_FUSES_OUT_DATA_LEN 1 11139 #define MC_CMD_READ_FUSES_OUT_DATA_MINNUM 0 11140 #define MC_CMD_READ_FUSES_OUT_DATA_MAXNUM 248 11141 11142 11143 /***********************************/ 11144 /* MC_CMD_KR_TUNE 11145 * Get or set KR Serdes RXEQ and TX Driver settings 11146 */ 11147 #define MC_CMD_KR_TUNE 0xf1 11148 #undef MC_CMD_0xf1_PRIVILEGE_CTG 11149 11150 #define MC_CMD_0xf1_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11151 11152 /* MC_CMD_KR_TUNE_IN msgrequest */ 11153 #define MC_CMD_KR_TUNE_IN_LENMIN 4 11154 #define MC_CMD_KR_TUNE_IN_LENMAX 252 11155 #define MC_CMD_KR_TUNE_IN_LEN(num) (4+4*(num)) 11156 /* Requested operation */ 11157 #define MC_CMD_KR_TUNE_IN_KR_TUNE_OP_OFST 0 11158 #define MC_CMD_KR_TUNE_IN_KR_TUNE_OP_LEN 1 11159 /* enum: Get current RXEQ settings */ 11160 #define MC_CMD_KR_TUNE_IN_RXEQ_GET 0x0 11161 /* enum: Override RXEQ settings */ 11162 #define MC_CMD_KR_TUNE_IN_RXEQ_SET 0x1 11163 /* enum: Get current TX Driver settings */ 11164 #define MC_CMD_KR_TUNE_IN_TXEQ_GET 0x2 11165 /* enum: Override TX Driver settings */ 11166 #define MC_CMD_KR_TUNE_IN_TXEQ_SET 0x3 11167 /* enum: Force KR Serdes reset / recalibration */ 11168 #define MC_CMD_KR_TUNE_IN_RECAL 0x4 11169 /* enum: Start KR Serdes Eye diagram plot on a given lane. Lane must have valid 11170 * signal. 11171 */ 11172 #define MC_CMD_KR_TUNE_IN_START_EYE_PLOT 0x5 11173 /* enum: Poll KR Serdes Eye diagram plot. Returns one row of BER data. The 11174 * caller should call this command repeatedly after starting eye plot, until no 11175 * more data is returned. 11176 */ 11177 #define MC_CMD_KR_TUNE_IN_POLL_EYE_PLOT 0x6 11178 /* enum: Read Figure Of Merit (eye quality, higher is better). */ 11179 #define MC_CMD_KR_TUNE_IN_READ_FOM 0x7 11180 /* Align the arguments to 32 bits */ 11181 #define MC_CMD_KR_TUNE_IN_KR_TUNE_RSVD_OFST 1 11182 #define MC_CMD_KR_TUNE_IN_KR_TUNE_RSVD_LEN 3 11183 /* Arguments specific to the operation */ 11184 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_OFST 4 11185 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_LEN 4 11186 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_MINNUM 0 11187 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_MAXNUM 62 11188 11189 /* MC_CMD_KR_TUNE_OUT msgresponse */ 11190 #define MC_CMD_KR_TUNE_OUT_LEN 0 11191 11192 /* MC_CMD_KR_TUNE_RXEQ_GET_IN msgrequest */ 11193 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_LEN 4 11194 /* Requested operation */ 11195 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_OP_OFST 0 11196 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_OP_LEN 1 11197 /* Align the arguments to 32 bits */ 11198 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_RSVD_OFST 1 11199 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_RSVD_LEN 3 11200 11201 /* MC_CMD_KR_TUNE_RXEQ_GET_OUT msgresponse */ 11202 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LENMIN 4 11203 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LENMAX 252 11204 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LEN(num) (0+4*(num)) 11205 /* RXEQ Parameter */ 11206 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_OFST 0 11207 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LEN 4 11208 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_MINNUM 1 11209 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_MAXNUM 63 11210 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_LBN 0 11211 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_WIDTH 8 11212 /* enum: Attenuation (0-15, TBD for Medford) */ 11213 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_ATT 0x0 11214 /* enum: CTLE Boost (0-15, TBD for Medford) */ 11215 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_BOOST 0x1 11216 /* enum: Edge DFE Tap1 (0 - max negative, 64 - zero, 127 - max positive, TBD 11217 * for Medford) 11218 */ 11219 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP1 0x2 11220 /* enum: Edge DFE Tap2 (0 - max negative, 32 - zero, 63 - max positive, TBD for 11221 * Medford) 11222 */ 11223 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP2 0x3 11224 /* enum: Edge DFE Tap3 (0 - max negative, 32 - zero, 63 - max positive, TBD for 11225 * Medford) 11226 */ 11227 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP3 0x4 11228 /* enum: Edge DFE Tap4 (0 - max negative, 32 - zero, 63 - max positive, TBD for 11229 * Medford) 11230 */ 11231 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP4 0x5 11232 /* enum: Edge DFE Tap5 (0 - max negative, 32 - zero, 63 - max positive, TBD for 11233 * Medford) 11234 */ 11235 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP5 0x6 11236 /* enum: Edge DFE DLEV (TBD for Medford) */ 11237 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_DLEV 0x7 11238 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_LBN 8 11239 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_WIDTH 3 11240 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */ 11241 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_1 0x1 /* enum */ 11242 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_2 0x2 /* enum */ 11243 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_3 0x3 /* enum */ 11244 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_ALL 0x4 /* enum */ 11245 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_LBN 11 11246 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_WIDTH 1 11247 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_RESERVED_LBN 12 11248 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_RESERVED_WIDTH 4 11249 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_INITIAL_LBN 16 11250 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_INITIAL_WIDTH 8 11251 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_LBN 24 11252 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8 11253 11254 /* MC_CMD_KR_TUNE_RXEQ_SET_IN msgrequest */ 11255 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_LENMIN 8 11256 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_LENMAX 252 11257 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_LEN(num) (4+4*(num)) 11258 /* Requested operation */ 11259 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_OP_OFST 0 11260 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_OP_LEN 1 11261 /* Align the arguments to 32 bits */ 11262 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_RSVD_OFST 1 11263 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_RSVD_LEN 3 11264 /* RXEQ Parameter */ 11265 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_OFST 4 11266 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LEN 4 11267 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_MINNUM 1 11268 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_MAXNUM 62 11269 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_ID_LBN 0 11270 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_ID_WIDTH 8 11271 /* Enum values, see field(s): */ 11272 /* MC_CMD_KR_TUNE_RXEQ_GET_OUT/PARAM_ID */ 11273 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LANE_LBN 8 11274 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LANE_WIDTH 3 11275 /* Enum values, see field(s): */ 11276 /* MC_CMD_KR_TUNE_RXEQ_GET_OUT/PARAM_LANE */ 11277 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_LBN 11 11278 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_WIDTH 1 11279 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED_LBN 12 11280 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED_WIDTH 4 11281 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_INITIAL_LBN 16 11282 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_INITIAL_WIDTH 8 11283 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED2_LBN 24 11284 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED2_WIDTH 8 11285 11286 /* MC_CMD_KR_TUNE_RXEQ_SET_OUT msgresponse */ 11287 #define MC_CMD_KR_TUNE_RXEQ_SET_OUT_LEN 0 11288 11289 /* MC_CMD_KR_TUNE_TXEQ_GET_IN msgrequest */ 11290 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_LEN 4 11291 /* Requested operation */ 11292 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_OP_OFST 0 11293 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_OP_LEN 1 11294 /* Align the arguments to 32 bits */ 11295 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_RSVD_OFST 1 11296 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_RSVD_LEN 3 11297 11298 /* MC_CMD_KR_TUNE_TXEQ_GET_OUT msgresponse */ 11299 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LENMIN 4 11300 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LENMAX 252 11301 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LEN(num) (0+4*(num)) 11302 /* TXEQ Parameter */ 11303 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_OFST 0 11304 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LEN 4 11305 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_MINNUM 1 11306 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_MAXNUM 63 11307 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_LBN 0 11308 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_WIDTH 8 11309 /* enum: TX Amplitude */ 11310 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV 0x0 11311 /* enum: De-Emphasis Tap1 Magnitude (0-7) */ 11312 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_MODE 0x1 11313 /* enum: De-Emphasis Tap1 Fine */ 11314 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_DTLEV 0x2 11315 /* enum: De-Emphasis Tap2 Magnitude (0-6) */ 11316 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_D2 0x3 11317 /* enum: De-Emphasis Tap2 Fine */ 11318 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_D2TLEV 0x4 11319 /* enum: Pre-Emphasis Magnitude */ 11320 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_E 0x5 11321 /* enum: Pre-Emphasis Fine */ 11322 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_ETLEV 0x6 11323 /* enum: TX Slew Rate Coarse control */ 11324 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_PREDRV_DLY 0x7 11325 /* enum: TX Slew Rate Fine control */ 11326 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_SR_SET 0x8 11327 /* enum: TX Termination Impedance control */ 11328 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_RT_SET 0x9 11329 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LANE_LBN 8 11330 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LANE_WIDTH 3 11331 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_0 0x0 /* enum */ 11332 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_1 0x1 /* enum */ 11333 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_2 0x2 /* enum */ 11334 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_3 0x3 /* enum */ 11335 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_ALL 0x4 /* enum */ 11336 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED_LBN 11 11337 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED_WIDTH 5 11338 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_INITIAL_LBN 16 11339 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_INITIAL_WIDTH 8 11340 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED2_LBN 24 11341 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED2_WIDTH 8 11342 11343 /* MC_CMD_KR_TUNE_TXEQ_SET_IN msgrequest */ 11344 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_LENMIN 8 11345 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_LENMAX 252 11346 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_LEN(num) (4+4*(num)) 11347 /* Requested operation */ 11348 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_OP_OFST 0 11349 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_OP_LEN 1 11350 /* Align the arguments to 32 bits */ 11351 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_RSVD_OFST 1 11352 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_RSVD_LEN 3 11353 /* TXEQ Parameter */ 11354 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_OFST 4 11355 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LEN 4 11356 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_MINNUM 1 11357 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_MAXNUM 62 11358 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_ID_LBN 0 11359 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_ID_WIDTH 8 11360 /* Enum values, see field(s): */ 11361 /* MC_CMD_KR_TUNE_TXEQ_GET_OUT/PARAM_ID */ 11362 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LANE_LBN 8 11363 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LANE_WIDTH 3 11364 /* Enum values, see field(s): */ 11365 /* MC_CMD_KR_TUNE_TXEQ_GET_OUT/PARAM_LANE */ 11366 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED_LBN 11 11367 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED_WIDTH 5 11368 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_INITIAL_LBN 16 11369 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_INITIAL_WIDTH 8 11370 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED2_LBN 24 11371 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED2_WIDTH 8 11372 11373 /* MC_CMD_KR_TUNE_TXEQ_SET_OUT msgresponse */ 11374 #define MC_CMD_KR_TUNE_TXEQ_SET_OUT_LEN 0 11375 11376 /* MC_CMD_KR_TUNE_RECAL_IN msgrequest */ 11377 #define MC_CMD_KR_TUNE_RECAL_IN_LEN 4 11378 /* Requested operation */ 11379 #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_OP_OFST 0 11380 #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_OP_LEN 1 11381 /* Align the arguments to 32 bits */ 11382 #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_RSVD_OFST 1 11383 #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_RSVD_LEN 3 11384 11385 /* MC_CMD_KR_TUNE_RECAL_OUT msgresponse */ 11386 #define MC_CMD_KR_TUNE_RECAL_OUT_LEN 0 11387 11388 /* MC_CMD_KR_TUNE_START_EYE_PLOT_IN msgrequest */ 11389 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_LEN 8 11390 /* Requested operation */ 11391 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_OP_OFST 0 11392 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_OP_LEN 1 11393 /* Align the arguments to 32 bits */ 11394 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_RSVD_OFST 1 11395 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_RSVD_LEN 3 11396 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_LANE_OFST 4 11397 11398 /* MC_CMD_KR_TUNE_START_EYE_PLOT_OUT msgresponse */ 11399 #define MC_CMD_KR_TUNE_START_EYE_PLOT_OUT_LEN 0 11400 11401 /* MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN msgrequest */ 11402 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_LEN 4 11403 /* Requested operation */ 11404 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_OP_OFST 0 11405 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_OP_LEN 1 11406 /* Align the arguments to 32 bits */ 11407 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_RSVD_OFST 1 11408 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_RSVD_LEN 3 11409 11410 /* MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT msgresponse */ 11411 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LENMIN 0 11412 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LENMAX 252 11413 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LEN(num) (0+2*(num)) 11414 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_OFST 0 11415 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_LEN 2 11416 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MINNUM 0 11417 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MAXNUM 126 11418 11419 /* MC_CMD_KR_TUNE_READ_FOM_IN msgrequest */ 11420 #define MC_CMD_KR_TUNE_READ_FOM_IN_LEN 8 11421 /* Requested operation */ 11422 #define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_OP_OFST 0 11423 #define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_OP_LEN 1 11424 /* Align the arguments to 32 bits */ 11425 #define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_RSVD_OFST 1 11426 #define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_RSVD_LEN 3 11427 #define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_OFST 4 11428 11429 /* MC_CMD_KR_TUNE_READ_FOM_OUT msgresponse */ 11430 #define MC_CMD_KR_TUNE_READ_FOM_OUT_LEN 4 11431 #define MC_CMD_KR_TUNE_READ_FOM_OUT_FOM_OFST 0 11432 11433 11434 /***********************************/ 11435 /* MC_CMD_PCIE_TUNE 11436 * Get or set PCIE Serdes RXEQ and TX Driver settings 11437 */ 11438 #define MC_CMD_PCIE_TUNE 0xf2 11439 #undef MC_CMD_0xf2_PRIVILEGE_CTG 11440 11441 #define MC_CMD_0xf2_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11442 11443 /* MC_CMD_PCIE_TUNE_IN msgrequest */ 11444 #define MC_CMD_PCIE_TUNE_IN_LENMIN 4 11445 #define MC_CMD_PCIE_TUNE_IN_LENMAX 252 11446 #define MC_CMD_PCIE_TUNE_IN_LEN(num) (4+4*(num)) 11447 /* Requested operation */ 11448 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_OP_OFST 0 11449 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_OP_LEN 1 11450 /* enum: Get current RXEQ settings */ 11451 #define MC_CMD_PCIE_TUNE_IN_RXEQ_GET 0x0 11452 /* enum: Override RXEQ settings */ 11453 #define MC_CMD_PCIE_TUNE_IN_RXEQ_SET 0x1 11454 /* enum: Get current TX Driver settings */ 11455 #define MC_CMD_PCIE_TUNE_IN_TXEQ_GET 0x2 11456 /* enum: Override TX Driver settings */ 11457 #define MC_CMD_PCIE_TUNE_IN_TXEQ_SET 0x3 11458 /* enum: Start PCIe Serdes Eye diagram plot on a given lane. */ 11459 #define MC_CMD_PCIE_TUNE_IN_START_EYE_PLOT 0x5 11460 /* enum: Poll PCIe Serdes Eye diagram plot. Returns one row of BER data. The 11461 * caller should call this command repeatedly after starting eye plot, until no 11462 * more data is returned. 11463 */ 11464 #define MC_CMD_PCIE_TUNE_IN_POLL_EYE_PLOT 0x6 11465 /* Align the arguments to 32 bits */ 11466 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_RSVD_OFST 1 11467 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_RSVD_LEN 3 11468 /* Arguments specific to the operation */ 11469 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_OFST 4 11470 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_LEN 4 11471 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_MINNUM 0 11472 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_MAXNUM 62 11473 11474 /* MC_CMD_PCIE_TUNE_OUT msgresponse */ 11475 #define MC_CMD_PCIE_TUNE_OUT_LEN 0 11476 11477 /* MC_CMD_PCIE_TUNE_RXEQ_GET_IN msgrequest */ 11478 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_LEN 4 11479 /* Requested operation */ 11480 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_OP_OFST 0 11481 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_OP_LEN 1 11482 /* Align the arguments to 32 bits */ 11483 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_RSVD_OFST 1 11484 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_RSVD_LEN 3 11485 11486 /* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT msgresponse */ 11487 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LENMIN 4 11488 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LENMAX 252 11489 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LEN(num) (0+4*(num)) 11490 /* RXEQ Parameter */ 11491 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_OFST 0 11492 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LEN 4 11493 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_MINNUM 1 11494 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_MAXNUM 63 11495 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_ID_LBN 0 11496 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_ID_WIDTH 8 11497 /* enum: Attenuation (0-15) */ 11498 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_ATT 0x0 11499 /* enum: CTLE Boost (0-15) */ 11500 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_BOOST 0x1 11501 /* enum: DFE Tap1 (0 - max negative, 64 - zero, 127 - max positive) */ 11502 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP1 0x2 11503 /* enum: DFE Tap2 (0 - max negative, 32 - zero, 63 - max positive) */ 11504 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP2 0x3 11505 /* enum: DFE Tap3 (0 - max negative, 32 - zero, 63 - max positive) */ 11506 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP3 0x4 11507 /* enum: DFE Tap4 (0 - max negative, 32 - zero, 63 - max positive) */ 11508 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP4 0x5 11509 /* enum: DFE Tap5 (0 - max negative, 32 - zero, 63 - max positive) */ 11510 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP5 0x6 11511 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_LBN 8 11512 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_WIDTH 4 11513 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */ 11514 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_1 0x1 /* enum */ 11515 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_2 0x2 /* enum */ 11516 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_3 0x3 /* enum */ 11517 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_4 0x4 /* enum */ 11518 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_5 0x5 /* enum */ 11519 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_6 0x6 /* enum */ 11520 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_7 0x7 /* enum */ 11521 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_ALL 0x8 /* enum */ 11522 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_LBN 12 11523 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_WIDTH 12 11524 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_LBN 24 11525 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8 11526 11527 /* MC_CMD_PCIE_TUNE_TXEQ_GET_IN msgrequest */ 11528 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_LEN 4 11529 /* Requested operation */ 11530 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_OP_OFST 0 11531 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_OP_LEN 1 11532 /* Align the arguments to 32 bits */ 11533 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_RSVD_OFST 1 11534 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_RSVD_LEN 3 11535 11536 /* MC_CMD_PCIE_TUNE_TXEQ_GET_OUT msgresponse */ 11537 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LENMIN 4 11538 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LENMAX 252 11539 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LEN(num) (0+4*(num)) 11540 /* RXEQ Parameter */ 11541 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_OFST 0 11542 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LEN 4 11543 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_MINNUM 1 11544 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_MAXNUM 63 11545 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_ID_LBN 0 11546 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_ID_WIDTH 8 11547 /* enum: TxMargin (PIPE) */ 11548 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_TXMARGIN 0x0 11549 /* enum: TxSwing (PIPE) */ 11550 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_TXSWING 0x1 11551 /* enum: De-emphasis coefficient C(-1) (PIPE) */ 11552 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_CM1 0x2 11553 /* enum: De-emphasis coefficient C(0) (PIPE) */ 11554 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_C0 0x3 11555 /* enum: De-emphasis coefficient C(+1) (PIPE) */ 11556 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_CP1 0x4 11557 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LANE_LBN 8 11558 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LANE_WIDTH 4 11559 /* Enum values, see field(s): */ 11560 /* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_LANE */ 11561 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_RESERVED_LBN 12 11562 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_RESERVED_WIDTH 12 11563 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_CURRENT_LBN 24 11564 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8 11565 11566 /* MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN msgrequest */ 11567 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_LEN 8 11568 /* Requested operation */ 11569 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_OP_OFST 0 11570 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_OP_LEN 1 11571 /* Align the arguments to 32 bits */ 11572 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_RSVD_OFST 1 11573 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_RSVD_LEN 3 11574 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_LANE_OFST 4 11575 11576 /* MC_CMD_PCIE_TUNE_START_EYE_PLOT_OUT msgresponse */ 11577 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_OUT_LEN 0 11578 11579 /* MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN msgrequest */ 11580 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_LEN 4 11581 /* Requested operation */ 11582 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_OP_OFST 0 11583 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_OP_LEN 1 11584 /* Align the arguments to 32 bits */ 11585 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_RSVD_OFST 1 11586 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_RSVD_LEN 3 11587 11588 /* MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT msgresponse */ 11589 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LENMIN 0 11590 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LENMAX 252 11591 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LEN(num) (0+2*(num)) 11592 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_OFST 0 11593 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_LEN 2 11594 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MINNUM 0 11595 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MAXNUM 126 11596 11597 11598 /***********************************/ 11599 /* MC_CMD_LICENSING 11600 * Operations on the NVRAM_PARTITION_TYPE_LICENSE application license partition 11601 */ 11602 #define MC_CMD_LICENSING 0xf3 11603 #undef MC_CMD_0xf3_PRIVILEGE_CTG 11604 11605 #define MC_CMD_0xf3_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11606 11607 /* MC_CMD_LICENSING_IN msgrequest */ 11608 #define MC_CMD_LICENSING_IN_LEN 4 11609 /* identifies the type of operation requested */ 11610 #define MC_CMD_LICENSING_IN_OP_OFST 0 11611 /* enum: re-read and apply licenses after a license key partition update; note 11612 * that this operation returns a zero-length response 11613 */ 11614 #define MC_CMD_LICENSING_IN_OP_UPDATE_LICENSE 0x0 11615 /* enum: report counts of installed licenses */ 11616 #define MC_CMD_LICENSING_IN_OP_GET_KEY_STATS 0x1 11617 11618 /* MC_CMD_LICENSING_OUT msgresponse */ 11619 #define MC_CMD_LICENSING_OUT_LEN 28 11620 /* count of application keys which are valid */ 11621 #define MC_CMD_LICENSING_OUT_VALID_APP_KEYS_OFST 0 11622 /* sum of UNVERIFIABLE_APP_KEYS + WRONG_NODE_APP_KEYS (for compatibility with 11623 * MC_CMD_FC_OP_LICENSE) 11624 */ 11625 #define MC_CMD_LICENSING_OUT_INVALID_APP_KEYS_OFST 4 11626 /* count of application keys which are invalid due to being blacklisted */ 11627 #define MC_CMD_LICENSING_OUT_BLACKLISTED_APP_KEYS_OFST 8 11628 /* count of application keys which are invalid due to being unverifiable */ 11629 #define MC_CMD_LICENSING_OUT_UNVERIFIABLE_APP_KEYS_OFST 12 11630 /* count of application keys which are invalid due to being for the wrong node 11631 */ 11632 #define MC_CMD_LICENSING_OUT_WRONG_NODE_APP_KEYS_OFST 16 11633 /* licensing state (for diagnostics; the exact meaning of the bits in this 11634 * field are private to the firmware) 11635 */ 11636 #define MC_CMD_LICENSING_OUT_LICENSING_STATE_OFST 20 11637 /* licensing subsystem self-test report (for manftest) */ 11638 #define MC_CMD_LICENSING_OUT_LICENSING_SELF_TEST_OFST 24 11639 /* enum: licensing subsystem self-test failed */ 11640 #define MC_CMD_LICENSING_OUT_SELF_TEST_FAIL 0x0 11641 /* enum: licensing subsystem self-test passed */ 11642 #define MC_CMD_LICENSING_OUT_SELF_TEST_PASS 0x1 11643 11644 11645 /***********************************/ 11646 /* MC_CMD_MC2MC_PROXY 11647 * Execute an arbitrary MCDI command on the slave MC of a dual-core device. 11648 * This will fail on a single-core system. 11649 */ 11650 #define MC_CMD_MC2MC_PROXY 0xf4 11651 #undef MC_CMD_0xf4_PRIVILEGE_CTG 11652 11653 #define MC_CMD_0xf4_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11654 11655 /* MC_CMD_MC2MC_PROXY_IN msgrequest */ 11656 #define MC_CMD_MC2MC_PROXY_IN_LEN 0 11657 11658 /* MC_CMD_MC2MC_PROXY_OUT msgresponse */ 11659 #define MC_CMD_MC2MC_PROXY_OUT_LEN 0 11660 11661 11662 /***********************************/ 11663 /* MC_CMD_GET_LICENSED_APP_STATE 11664 * Query the state of an individual licensed application. (Note that the actual 11665 * state may be invalidated by the MC_CMD_LICENSING OP_UPDATE_LICENSE operation 11666 * or a reboot of the MC.) 11667 */ 11668 #define MC_CMD_GET_LICENSED_APP_STATE 0xf5 11669 #undef MC_CMD_0xf5_PRIVILEGE_CTG 11670 11671 #define MC_CMD_0xf5_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11672 11673 /* MC_CMD_GET_LICENSED_APP_STATE_IN msgrequest */ 11674 #define MC_CMD_GET_LICENSED_APP_STATE_IN_LEN 4 11675 /* application ID to query (LICENSED_APP_ID_xxx) */ 11676 #define MC_CMD_GET_LICENSED_APP_STATE_IN_APP_ID_OFST 0 11677 11678 /* MC_CMD_GET_LICENSED_APP_STATE_OUT msgresponse */ 11679 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_LEN 4 11680 /* state of this application */ 11681 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_STATE_OFST 0 11682 /* enum: no (or invalid) license is present for the application */ 11683 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_NOT_LICENSED 0x0 11684 /* enum: a valid license is present for the application */ 11685 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_LICENSED 0x1 11686 11687 11688 /***********************************/ 11689 /* MC_CMD_LICENSED_APP_OP 11690 * Perform an action for an individual licensed application. 11691 */ 11692 #define MC_CMD_LICENSED_APP_OP 0xf6 11693 #undef MC_CMD_0xf6_PRIVILEGE_CTG 11694 11695 #define MC_CMD_0xf6_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11696 11697 /* MC_CMD_LICENSED_APP_OP_IN msgrequest */ 11698 #define MC_CMD_LICENSED_APP_OP_IN_LENMIN 8 11699 #define MC_CMD_LICENSED_APP_OP_IN_LENMAX 252 11700 #define MC_CMD_LICENSED_APP_OP_IN_LEN(num) (8+4*(num)) 11701 /* application ID */ 11702 #define MC_CMD_LICENSED_APP_OP_IN_APP_ID_OFST 0 11703 /* the type of operation requested */ 11704 #define MC_CMD_LICENSED_APP_OP_IN_OP_OFST 4 11705 /* enum: validate application */ 11706 #define MC_CMD_LICENSED_APP_OP_IN_OP_VALIDATE 0x0 11707 /* enum: mask application */ 11708 #define MC_CMD_LICENSED_APP_OP_IN_OP_MASK 0x1 11709 /* arguments specific to this particular operation */ 11710 #define MC_CMD_LICENSED_APP_OP_IN_ARGS_OFST 8 11711 #define MC_CMD_LICENSED_APP_OP_IN_ARGS_LEN 4 11712 #define MC_CMD_LICENSED_APP_OP_IN_ARGS_MINNUM 0 11713 #define MC_CMD_LICENSED_APP_OP_IN_ARGS_MAXNUM 61 11714 11715 /* MC_CMD_LICENSED_APP_OP_OUT msgresponse */ 11716 #define MC_CMD_LICENSED_APP_OP_OUT_LENMIN 0 11717 #define MC_CMD_LICENSED_APP_OP_OUT_LENMAX 252 11718 #define MC_CMD_LICENSED_APP_OP_OUT_LEN(num) (0+4*(num)) 11719 /* result specific to this particular operation */ 11720 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_OFST 0 11721 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_LEN 4 11722 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_MINNUM 0 11723 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_MAXNUM 63 11724 11725 /* MC_CMD_LICENSED_APP_OP_VALIDATE_IN msgrequest */ 11726 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_LEN 72 11727 /* application ID */ 11728 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_APP_ID_OFST 0 11729 /* the type of operation requested */ 11730 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_OP_OFST 4 11731 /* validation challenge */ 11732 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_CHALLENGE_OFST 8 11733 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_CHALLENGE_LEN 64 11734 11735 /* MC_CMD_LICENSED_APP_OP_VALIDATE_OUT msgresponse */ 11736 #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_LEN 68 11737 /* feature expiry (time_t) */ 11738 #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_EXPIRY_OFST 0 11739 /* validation response */ 11740 #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_RESPONSE_OFST 4 11741 #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_RESPONSE_LEN 64 11742 11743 /* MC_CMD_LICENSED_APP_OP_MASK_IN msgrequest */ 11744 #define MC_CMD_LICENSED_APP_OP_MASK_IN_LEN 12 11745 /* application ID */ 11746 #define MC_CMD_LICENSED_APP_OP_MASK_IN_APP_ID_OFST 0 11747 /* the type of operation requested */ 11748 #define MC_CMD_LICENSED_APP_OP_MASK_IN_OP_OFST 4 11749 /* flag */ 11750 #define MC_CMD_LICENSED_APP_OP_MASK_IN_FLAG_OFST 8 11751 11752 /* MC_CMD_LICENSED_APP_OP_MASK_OUT msgresponse */ 11753 #define MC_CMD_LICENSED_APP_OP_MASK_OUT_LEN 0 11754 11755 11756 /***********************************/ 11757 /* MC_CMD_SET_PORT_SNIFF_CONFIG 11758 * Configure RX port sniffing for the physical port associated with the calling 11759 * function. Only a privileged function may change the port sniffing 11760 * configuration. A copy of all traffic delivered to the host (non-promiscuous 11761 * mode) or all traffic arriving at the port (promiscuous mode) may be 11762 * delivered to a specific queue, or a set of queues with RSS. 11763 */ 11764 #define MC_CMD_SET_PORT_SNIFF_CONFIG 0xf7 11765 #undef MC_CMD_0xf7_PRIVILEGE_CTG 11766 11767 #define MC_CMD_0xf7_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11768 11769 /* MC_CMD_SET_PORT_SNIFF_CONFIG_IN msgrequest */ 11770 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_LEN 16 11771 /* configuration flags */ 11772 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_FLAGS_OFST 0 11773 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_ENABLE_LBN 0 11774 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_ENABLE_WIDTH 1 11775 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_PROMISCUOUS_LBN 1 11776 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_PROMISCUOUS_WIDTH 1 11777 /* receive queue handle (for RSS mode, this is the base queue) */ 11778 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_QUEUE_OFST 4 11779 /* receive mode */ 11780 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_OFST 8 11781 /* enum: receive to just the specified queue */ 11782 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_SIMPLE 0x0 11783 /* enum: receive to multiple queues using RSS context */ 11784 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_RSS 0x1 11785 /* RSS context (for RX_MODE_RSS) as returned by MC_CMD_RSS_CONTEXT_ALLOC. Note 11786 * that these handles should be considered opaque to the host, although a value 11787 * of 0xFFFFFFFF is guaranteed never to be a valid handle. 11788 */ 11789 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_OFST 12 11790 11791 /* MC_CMD_SET_PORT_SNIFF_CONFIG_OUT msgresponse */ 11792 #define MC_CMD_SET_PORT_SNIFF_CONFIG_OUT_LEN 0 11793 11794 11795 /***********************************/ 11796 /* MC_CMD_GET_PORT_SNIFF_CONFIG 11797 * Obtain the current RX port sniffing configuration for the physical port 11798 * associated with the calling function. Only a privileged function may read 11799 * the configuration. 11800 */ 11801 #define MC_CMD_GET_PORT_SNIFF_CONFIG 0xf8 11802 #undef MC_CMD_0xf8_PRIVILEGE_CTG 11803 11804 #define MC_CMD_0xf8_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11805 11806 /* MC_CMD_GET_PORT_SNIFF_CONFIG_IN msgrequest */ 11807 #define MC_CMD_GET_PORT_SNIFF_CONFIG_IN_LEN 0 11808 11809 /* MC_CMD_GET_PORT_SNIFF_CONFIG_OUT msgresponse */ 11810 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_LEN 16 11811 /* configuration flags */ 11812 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_FLAGS_OFST 0 11813 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_ENABLE_LBN 0 11814 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_ENABLE_WIDTH 1 11815 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_PROMISCUOUS_LBN 1 11816 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_PROMISCUOUS_WIDTH 1 11817 /* receiving queue handle (for RSS mode, this is the base queue) */ 11818 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_OFST 4 11819 /* receive mode */ 11820 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_OFST 8 11821 /* enum: receiving to just the specified queue */ 11822 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_SIMPLE 0x0 11823 /* enum: receiving to multiple queues using RSS context */ 11824 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_RSS 0x1 11825 /* RSS context (for RX_MODE_RSS) */ 11826 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_OFST 12 11827 11828 11829 /***********************************/ 11830 /* MC_CMD_SET_PARSER_DISP_CONFIG 11831 * Change configuration related to the parser-dispatcher subsystem. 11832 */ 11833 #define MC_CMD_SET_PARSER_DISP_CONFIG 0xf9 11834 #undef MC_CMD_0xf9_PRIVILEGE_CTG 11835 11836 #define MC_CMD_0xf9_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11837 11838 /* MC_CMD_SET_PARSER_DISP_CONFIG_IN msgrequest */ 11839 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LENMIN 12 11840 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LENMAX 252 11841 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LEN(num) (8+4*(num)) 11842 /* the type of configuration setting to change */ 11843 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_TYPE_OFST 0 11844 /* enum: Per-TXQ enable for multicast UDP destination lookup for possible 11845 * internal loopback. (ENTITY is a queue handle, VALUE is a single boolean.) 11846 */ 11847 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_TXQ_MCAST_UDP_DST_LOOKUP_EN 0x0 11848 /* enum: Per-v-adaptor enable for suppression of self-transmissions on the 11849 * internal loopback path. (ENTITY is an EVB_PORT_ID, VALUE is a single 11850 * boolean.) 11851 */ 11852 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VADAPTOR_SUPPRESS_SELF_TX 0x1 11853 /* handle for the entity to update: queue handle, EVB port ID, etc. depending 11854 * on the type of configuration setting being changed 11855 */ 11856 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_ENTITY_OFST 4 11857 /* new value: the details depend on the type of configuration setting being 11858 * changed 11859 */ 11860 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_OFST 8 11861 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_LEN 4 11862 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_MINNUM 1 11863 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_MAXNUM 61 11864 11865 /* MC_CMD_SET_PARSER_DISP_CONFIG_OUT msgresponse */ 11866 #define MC_CMD_SET_PARSER_DISP_CONFIG_OUT_LEN 0 11867 11868 11869 /***********************************/ 11870 /* MC_CMD_GET_PARSER_DISP_CONFIG 11871 * Read configuration related to the parser-dispatcher subsystem. 11872 */ 11873 #define MC_CMD_GET_PARSER_DISP_CONFIG 0xfa 11874 #undef MC_CMD_0xfa_PRIVILEGE_CTG 11875 11876 #define MC_CMD_0xfa_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11877 11878 /* MC_CMD_GET_PARSER_DISP_CONFIG_IN msgrequest */ 11879 #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_LEN 8 11880 /* the type of configuration setting to read */ 11881 #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_TYPE_OFST 0 11882 /* Enum values, see field(s): */ 11883 /* MC_CMD_SET_PARSER_DISP_CONFIG/MC_CMD_SET_PARSER_DISP_CONFIG_IN/TYPE */ 11884 /* handle for the entity to query: queue handle, EVB port ID, etc. depending on 11885 * the type of configuration setting being read 11886 */ 11887 #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_ENTITY_OFST 4 11888 11889 /* MC_CMD_GET_PARSER_DISP_CONFIG_OUT msgresponse */ 11890 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LENMIN 4 11891 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LENMAX 252 11892 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LEN(num) (0+4*(num)) 11893 /* current value: the details depend on the type of configuration setting being 11894 * read 11895 */ 11896 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_OFST 0 11897 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_LEN 4 11898 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_MINNUM 1 11899 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_MAXNUM 63 11900 11901 11902 /***********************************/ 11903 /* MC_CMD_SET_TX_PORT_SNIFF_CONFIG 11904 * Configure TX port sniffing for the physical port associated with the calling 11905 * function. Only a privileged function may change the port sniffing 11906 * configuration. A copy of all traffic transmitted through the port may be 11907 * delivered to a specific queue, or a set of queues with RSS. Note that these 11908 * packets are delivered with transmit timestamps in the packet prefix, not 11909 * receive timestamps, so it is likely that the queue(s) will need to be 11910 * dedicated as TX sniff receivers. 11911 */ 11912 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG 0xfb 11913 #undef MC_CMD_0xfb_PRIVILEGE_CTG 11914 11915 #define MC_CMD_0xfb_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11916 11917 /* MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN msgrequest */ 11918 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_LEN 16 11919 /* configuration flags */ 11920 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_FLAGS_OFST 0 11921 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_ENABLE_LBN 0 11922 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_ENABLE_WIDTH 1 11923 /* receive queue handle (for RSS mode, this is the base queue) */ 11924 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_QUEUE_OFST 4 11925 /* receive mode */ 11926 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_OFST 8 11927 /* enum: receive to just the specified queue */ 11928 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_SIMPLE 0x0 11929 /* enum: receive to multiple queues using RSS context */ 11930 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_RSS 0x1 11931 /* RSS context (for RX_MODE_RSS) as returned by MC_CMD_RSS_CONTEXT_ALLOC. Note 11932 * that these handles should be considered opaque to the host, although a value 11933 * of 0xFFFFFFFF is guaranteed never to be a valid handle. 11934 */ 11935 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_OFST 12 11936 11937 /* MC_CMD_SET_TX_PORT_SNIFF_CONFIG_OUT msgresponse */ 11938 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_OUT_LEN 0 11939 11940 11941 /***********************************/ 11942 /* MC_CMD_GET_TX_PORT_SNIFF_CONFIG 11943 * Obtain the current TX port sniffing configuration for the physical port 11944 * associated with the calling function. Only a privileged function may read 11945 * the configuration. 11946 */ 11947 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG 0xfc 11948 #undef MC_CMD_0xfc_PRIVILEGE_CTG 11949 11950 #define MC_CMD_0xfc_PRIVILEGE_CTG SRIOV_CTG_ADMIN 11951 11952 /* MC_CMD_GET_TX_PORT_SNIFF_CONFIG_IN msgrequest */ 11953 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_IN_LEN 0 11954 11955 /* MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT msgresponse */ 11956 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_LEN 16 11957 /* configuration flags */ 11958 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_FLAGS_OFST 0 11959 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_ENABLE_LBN 0 11960 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_ENABLE_WIDTH 1 11961 /* receiving queue handle (for RSS mode, this is the base queue) */ 11962 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_OFST 4 11963 /* receive mode */ 11964 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_OFST 8 11965 /* enum: receiving to just the specified queue */ 11966 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_SIMPLE 0x0 11967 /* enum: receiving to multiple queues using RSS context */ 11968 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_RSS 0x1 11969 /* RSS context (for RX_MODE_RSS) */ 11970 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_OFST 12 11971 11972 11973 /***********************************/ 11974 /* MC_CMD_RMON_STATS_RX_ERRORS 11975 * Per queue rx error stats. 11976 */ 11977 #define MC_CMD_RMON_STATS_RX_ERRORS 0xfe 11978 #undef MC_CMD_0xfe_PRIVILEGE_CTG 11979 11980 #define MC_CMD_0xfe_PRIVILEGE_CTG SRIOV_CTG_GENERAL 11981 11982 /* MC_CMD_RMON_STATS_RX_ERRORS_IN msgrequest */ 11983 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_LEN 8 11984 /* The rx queue to get stats for. */ 11985 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_RX_QUEUE_OFST 0 11986 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_FLAGS_OFST 4 11987 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_RST_LBN 0 11988 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_RST_WIDTH 1 11989 11990 /* MC_CMD_RMON_STATS_RX_ERRORS_OUT msgresponse */ 11991 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_LEN 16 11992 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_CRC_ERRORS_OFST 0 11993 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_TRUNC_ERRORS_OFST 4 11994 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_NO_DESC_DROPS_OFST 8 11995 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_ABORT_OFST 12 11996 11997 11998 /***********************************/ 11999 /* MC_CMD_GET_PCIE_RESOURCE_INFO 12000 * Find out about available PCIE resources 12001 */ 12002 #define MC_CMD_GET_PCIE_RESOURCE_INFO 0xfd 12003 12004 /* MC_CMD_GET_PCIE_RESOURCE_INFO_IN msgrequest */ 12005 #define MC_CMD_GET_PCIE_RESOURCE_INFO_IN_LEN 0 12006 12007 /* MC_CMD_GET_PCIE_RESOURCE_INFO_OUT msgresponse */ 12008 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_LEN 28 12009 /* The maximum number of PFs the device can expose */ 12010 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PFS_OFST 0 12011 /* The maximum number of VFs the device can expose in total */ 12012 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VFS_OFST 4 12013 /* The maximum number of MSI-X vectors the device can provide in total */ 12014 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VECTORS_OFST 8 12015 /* the number of MSI-X vectors the device will allocate by default to each PF 12016 */ 12017 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_PF_VECTORS_OFST 12 12018 /* the number of MSI-X vectors the device will allocate by default to each VF 12019 */ 12020 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_VF_VECTORS_OFST 16 12021 /* the maximum number of MSI-X vectors the device can allocate to any one PF */ 12022 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PF_VECTORS_OFST 20 12023 /* the maximum number of MSI-X vectors the device can allocate to any one VF */ 12024 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VF_VECTORS_OFST 24 12025 12026 12027 /***********************************/ 12028 /* MC_CMD_GET_PORT_MODES 12029 * Find out about available port modes 12030 */ 12031 #define MC_CMD_GET_PORT_MODES 0xff 12032 #undef MC_CMD_0xff_PRIVILEGE_CTG 12033 12034 #define MC_CMD_0xff_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12035 12036 /* MC_CMD_GET_PORT_MODES_IN msgrequest */ 12037 #define MC_CMD_GET_PORT_MODES_IN_LEN 0 12038 12039 /* MC_CMD_GET_PORT_MODES_OUT msgresponse */ 12040 #define MC_CMD_GET_PORT_MODES_OUT_LEN 12 12041 /* Bitmask of port modes available on the board (indexed by TLV_PORT_MODE_*) */ 12042 #define MC_CMD_GET_PORT_MODES_OUT_MODES_OFST 0 12043 /* Default (canonical) board mode */ 12044 #define MC_CMD_GET_PORT_MODES_OUT_DEFAULT_MODE_OFST 4 12045 /* Current board mode */ 12046 #define MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST 8 12047 12048 12049 /***********************************/ 12050 /* MC_CMD_READ_ATB 12051 * Sample voltages on the ATB 12052 */ 12053 #define MC_CMD_READ_ATB 0x100 12054 #undef MC_CMD_0x100_PRIVILEGE_CTG 12055 12056 #define MC_CMD_0x100_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12057 12058 /* MC_CMD_READ_ATB_IN msgrequest */ 12059 #define MC_CMD_READ_ATB_IN_LEN 16 12060 #define MC_CMD_READ_ATB_IN_SIGNAL_BUS_OFST 0 12061 #define MC_CMD_READ_ATB_IN_BUS_CCOM 0x0 /* enum */ 12062 #define MC_CMD_READ_ATB_IN_BUS_CKR 0x1 /* enum */ 12063 #define MC_CMD_READ_ATB_IN_BUS_CPCIE 0x8 /* enum */ 12064 #define MC_CMD_READ_ATB_IN_SIGNAL_EN_BITNO_OFST 4 12065 #define MC_CMD_READ_ATB_IN_SIGNAL_SEL_OFST 8 12066 #define MC_CMD_READ_ATB_IN_SETTLING_TIME_US_OFST 12 12067 12068 /* MC_CMD_READ_ATB_OUT msgresponse */ 12069 #define MC_CMD_READ_ATB_OUT_LEN 4 12070 #define MC_CMD_READ_ATB_OUT_SAMPLE_MV_OFST 0 12071 12072 12073 /***********************************/ 12074 /* MC_CMD_GET_WORKAROUNDS 12075 * Read the list of all implemented and all currently enabled workarounds. The 12076 * enums here must correspond with those in MC_CMD_WORKAROUND. 12077 */ 12078 #define MC_CMD_GET_WORKAROUNDS 0x59 12079 #undef MC_CMD_0x59_PRIVILEGE_CTG 12080 12081 #define MC_CMD_0x59_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12082 12083 /* MC_CMD_GET_WORKAROUNDS_OUT msgresponse */ 12084 #define MC_CMD_GET_WORKAROUNDS_OUT_LEN 8 12085 /* Each workaround is represented by a single bit according to the enums below. 12086 */ 12087 #define MC_CMD_GET_WORKAROUNDS_OUT_IMPLEMENTED_OFST 0 12088 #define MC_CMD_GET_WORKAROUNDS_OUT_ENABLED_OFST 4 12089 /* enum: Bug 17230 work around. */ 12090 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG17230 0x2 12091 /* enum: Bug 35388 work around (unsafe EVQ writes). */ 12092 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG35388 0x4 12093 /* enum: Bug35017 workaround (A64 tables must be identity map) */ 12094 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG35017 0x8 12095 /* enum: Bug 41750 present (MC_CMD_TRIGGER_INTERRUPT won't work) */ 12096 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG41750 0x10 12097 /* enum: Bug 42008 present (Interrupts can overtake associated events). Caution 12098 * - before adding code that queries this workaround, remember that there's 12099 * released Monza firmware that doesn't understand MC_CMD_WORKAROUND_BUG42008, 12100 * and will hence (incorrectly) report that the bug doesn't exist. 12101 */ 12102 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG42008 0x20 12103 /* enum: Bug 26807 features present in firmware (multicast filter chaining) */ 12104 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG26807 0x40 12105 12106 12107 /***********************************/ 12108 /* MC_CMD_PRIVILEGE_MASK 12109 * Read/set privileges of an arbitrary PCIe function 12110 */ 12111 #define MC_CMD_PRIVILEGE_MASK 0x5a 12112 #undef MC_CMD_0x5a_PRIVILEGE_CTG 12113 12114 #define MC_CMD_0x5a_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12115 12116 /* MC_CMD_PRIVILEGE_MASK_IN msgrequest */ 12117 #define MC_CMD_PRIVILEGE_MASK_IN_LEN 8 12118 /* The target function to have its mask read or set e.g. PF 0 = 0xFFFF0000, VF 12119 * 1,3 = 0x00030001 12120 */ 12121 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_OFST 0 12122 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_PF_LBN 0 12123 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_PF_WIDTH 16 12124 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_VF_LBN 16 12125 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_VF_WIDTH 16 12126 #define MC_CMD_PRIVILEGE_MASK_IN_VF_NULL 0xffff /* enum */ 12127 /* New privilege mask to be set. The mask will only be changed if the MSB is 12128 * set to 1. 12129 */ 12130 #define MC_CMD_PRIVILEGE_MASK_IN_NEW_MASK_OFST 4 12131 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN 0x1 /* enum */ 12132 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_LINK 0x2 /* enum */ 12133 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ONLOAD 0x4 /* enum */ 12134 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_PTP 0x8 /* enum */ 12135 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE_FILTERS 0x10 /* enum */ 12136 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING 0x20 /* enum */ 12137 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_UNICAST 0x40 /* enum */ 12138 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_MULTICAST 0x80 /* enum */ 12139 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_BROADCAST 0x100 /* enum */ 12140 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ALL_MULTICAST 0x200 /* enum */ 12141 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_PROMISCUOUS 0x400 /* enum */ 12142 /* enum: Set this bit to indicate that a new privilege mask is to be set, 12143 * otherwise the command will only read the existing mask. 12144 */ 12145 #define MC_CMD_PRIVILEGE_MASK_IN_DO_CHANGE 0x80000000 12146 12147 /* MC_CMD_PRIVILEGE_MASK_OUT msgresponse */ 12148 #define MC_CMD_PRIVILEGE_MASK_OUT_LEN 4 12149 /* For an admin function, always all the privileges are reported. */ 12150 #define MC_CMD_PRIVILEGE_MASK_OUT_OLD_MASK_OFST 0 12151 12152 12153 /***********************************/ 12154 /* MC_CMD_LINK_STATE_MODE 12155 * Read/set link state mode of a VF 12156 */ 12157 #define MC_CMD_LINK_STATE_MODE 0x5c 12158 #undef MC_CMD_0x5c_PRIVILEGE_CTG 12159 12160 #define MC_CMD_0x5c_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12161 12162 /* MC_CMD_LINK_STATE_MODE_IN msgrequest */ 12163 #define MC_CMD_LINK_STATE_MODE_IN_LEN 8 12164 /* The target function to have its link state mode read or set, must be a VF 12165 * e.g. VF 1,3 = 0x00030001 12166 */ 12167 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_OFST 0 12168 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_LBN 0 12169 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_WIDTH 16 12170 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_VF_LBN 16 12171 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_VF_WIDTH 16 12172 /* New link state mode to be set */ 12173 #define MC_CMD_LINK_STATE_MODE_IN_NEW_MODE_OFST 4 12174 #define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_AUTO 0x0 /* enum */ 12175 #define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_UP 0x1 /* enum */ 12176 #define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_DOWN 0x2 /* enum */ 12177 /* enum: Use this value to just read the existing setting without modifying it. 12178 */ 12179 #define MC_CMD_LINK_STATE_MODE_IN_DO_NOT_CHANGE 0xffffffff 12180 12181 /* MC_CMD_LINK_STATE_MODE_OUT msgresponse */ 12182 #define MC_CMD_LINK_STATE_MODE_OUT_LEN 4 12183 #define MC_CMD_LINK_STATE_MODE_OUT_OLD_MODE_OFST 0 12184 12185 12186 /***********************************/ 12187 /* MC_CMD_GET_SNAPSHOT_LENGTH 12188 * Obtain the curent range of allowable values for the SNAPSHOT_LENGTH 12189 * parameter to MC_CMD_INIT_RXQ. 12190 */ 12191 #define MC_CMD_GET_SNAPSHOT_LENGTH 0x101 12192 #undef MC_CMD_0x101_PRIVILEGE_CTG 12193 12194 #define MC_CMD_0x101_PRIVILEGE_CTG SRIOV_CTG_GENERAL 12195 12196 /* MC_CMD_GET_SNAPSHOT_LENGTH_IN msgrequest */ 12197 #define MC_CMD_GET_SNAPSHOT_LENGTH_IN_LEN 0 12198 12199 /* MC_CMD_GET_SNAPSHOT_LENGTH_OUT msgresponse */ 12200 #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_LEN 8 12201 /* Minimum acceptable snapshot length. */ 12202 #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MIN_OFST 0 12203 /* Maximum acceptable snapshot length. */ 12204 #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MAX_OFST 4 12205 12206 12207 /***********************************/ 12208 /* MC_CMD_FUSE_DIAGS 12209 * Additional fuse diagnostics 12210 */ 12211 #define MC_CMD_FUSE_DIAGS 0x102 12212 #undef MC_CMD_0x102_PRIVILEGE_CTG 12213 12214 #define MC_CMD_0x102_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12215 12216 /* MC_CMD_FUSE_DIAGS_IN msgrequest */ 12217 #define MC_CMD_FUSE_DIAGS_IN_LEN 0 12218 12219 /* MC_CMD_FUSE_DIAGS_OUT msgresponse */ 12220 #define MC_CMD_FUSE_DIAGS_OUT_LEN 48 12221 /* Total number of mismatched bits between pairs in area 0 */ 12222 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_MISMATCH_BITS_OFST 0 12223 /* Total number of unexpectedly clear (set in B but not A) bits in area 0 */ 12224 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_A_BAD_BITS_OFST 4 12225 /* Total number of unexpectedly clear (set in A but not B) bits in area 0 */ 12226 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_B_BAD_BITS_OFST 8 12227 /* Checksum of data after logical OR of pairs in area 0 */ 12228 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_CHECKSUM_OFST 12 12229 /* Total number of mismatched bits between pairs in area 1 */ 12230 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_MISMATCH_BITS_OFST 16 12231 /* Total number of unexpectedly clear (set in B but not A) bits in area 1 */ 12232 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_A_BAD_BITS_OFST 20 12233 /* Total number of unexpectedly clear (set in A but not B) bits in area 1 */ 12234 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_B_BAD_BITS_OFST 24 12235 /* Checksum of data after logical OR of pairs in area 1 */ 12236 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_CHECKSUM_OFST 28 12237 /* Total number of mismatched bits between pairs in area 2 */ 12238 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_MISMATCH_BITS_OFST 32 12239 /* Total number of unexpectedly clear (set in B but not A) bits in area 2 */ 12240 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_A_BAD_BITS_OFST 36 12241 /* Total number of unexpectedly clear (set in A but not B) bits in area 2 */ 12242 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_B_BAD_BITS_OFST 40 12243 /* Checksum of data after logical OR of pairs in area 2 */ 12244 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_CHECKSUM_OFST 44 12245 12246 12247 /***********************************/ 12248 /* MC_CMD_PRIVILEGE_MODIFY 12249 * Modify the privileges of a set of PCIe functions. Note that this operation 12250 * only effects non-admin functions unless the admin privilege itself is 12251 * included in one of the masks provided. 12252 */ 12253 #define MC_CMD_PRIVILEGE_MODIFY 0x60 12254 #undef MC_CMD_0x60_PRIVILEGE_CTG 12255 12256 #define MC_CMD_0x60_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12257 12258 /* MC_CMD_PRIVILEGE_MODIFY_IN msgrequest */ 12259 #define MC_CMD_PRIVILEGE_MODIFY_IN_LEN 16 12260 /* The groups of functions to have their privilege masks modified. */ 12261 #define MC_CMD_PRIVILEGE_MODIFY_IN_FN_GROUP_OFST 0 12262 #define MC_CMD_PRIVILEGE_MODIFY_IN_NONE 0x0 /* enum */ 12263 #define MC_CMD_PRIVILEGE_MODIFY_IN_ALL 0x1 /* enum */ 12264 #define MC_CMD_PRIVILEGE_MODIFY_IN_PFS_ONLY 0x2 /* enum */ 12265 #define MC_CMD_PRIVILEGE_MODIFY_IN_VFS_ONLY 0x3 /* enum */ 12266 #define MC_CMD_PRIVILEGE_MODIFY_IN_VFS_OF_PF 0x4 /* enum */ 12267 #define MC_CMD_PRIVILEGE_MODIFY_IN_ONE 0x5 /* enum */ 12268 /* For VFS_OF_PF specify the PF, for ONE specify the target function */ 12269 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_OFST 4 12270 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_PF_LBN 0 12271 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_PF_WIDTH 16 12272 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_VF_LBN 16 12273 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_VF_WIDTH 16 12274 /* Privileges to be added to the target functions. For privilege definitions 12275 * refer to the command MC_CMD_PRIVILEGE_MASK 12276 */ 12277 #define MC_CMD_PRIVILEGE_MODIFY_IN_ADD_MASK_OFST 8 12278 /* Privileges to be removed from the target functions. For privilege 12279 * definitions refer to the command MC_CMD_PRIVILEGE_MASK 12280 */ 12281 #define MC_CMD_PRIVILEGE_MODIFY_IN_REMOVE_MASK_OFST 12 12282 12283 /* MC_CMD_PRIVILEGE_MODIFY_OUT msgresponse */ 12284 #define MC_CMD_PRIVILEGE_MODIFY_OUT_LEN 0 12285 12286 12287 /***********************************/ 12288 /* MC_CMD_XPM_READ_BYTES 12289 * Read XPM memory 12290 */ 12291 #define MC_CMD_XPM_READ_BYTES 0x103 12292 #undef MC_CMD_0x103_PRIVILEGE_CTG 12293 12294 #define MC_CMD_0x103_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12295 12296 /* MC_CMD_XPM_READ_BYTES_IN msgrequest */ 12297 #define MC_CMD_XPM_READ_BYTES_IN_LEN 8 12298 /* Start address (byte) */ 12299 #define MC_CMD_XPM_READ_BYTES_IN_ADDR_OFST 0 12300 /* Count (bytes) */ 12301 #define MC_CMD_XPM_READ_BYTES_IN_COUNT_OFST 4 12302 12303 /* MC_CMD_XPM_READ_BYTES_OUT msgresponse */ 12304 #define MC_CMD_XPM_READ_BYTES_OUT_LENMIN 0 12305 #define MC_CMD_XPM_READ_BYTES_OUT_LENMAX 252 12306 #define MC_CMD_XPM_READ_BYTES_OUT_LEN(num) (0+1*(num)) 12307 /* Data */ 12308 #define MC_CMD_XPM_READ_BYTES_OUT_DATA_OFST 0 12309 #define MC_CMD_XPM_READ_BYTES_OUT_DATA_LEN 1 12310 #define MC_CMD_XPM_READ_BYTES_OUT_DATA_MINNUM 0 12311 #define MC_CMD_XPM_READ_BYTES_OUT_DATA_MAXNUM 252 12312 12313 12314 /***********************************/ 12315 /* MC_CMD_XPM_WRITE_BYTES 12316 * Write XPM memory 12317 */ 12318 #define MC_CMD_XPM_WRITE_BYTES 0x104 12319 #undef MC_CMD_0x104_PRIVILEGE_CTG 12320 12321 #define MC_CMD_0x104_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12322 12323 /* MC_CMD_XPM_WRITE_BYTES_IN msgrequest */ 12324 #define MC_CMD_XPM_WRITE_BYTES_IN_LENMIN 8 12325 #define MC_CMD_XPM_WRITE_BYTES_IN_LENMAX 252 12326 #define MC_CMD_XPM_WRITE_BYTES_IN_LEN(num) (8+1*(num)) 12327 /* Start address (byte) */ 12328 #define MC_CMD_XPM_WRITE_BYTES_IN_ADDR_OFST 0 12329 /* Count (bytes) */ 12330 #define MC_CMD_XPM_WRITE_BYTES_IN_COUNT_OFST 4 12331 /* Data */ 12332 #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_OFST 8 12333 #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_LEN 1 12334 #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_MINNUM 0 12335 #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_MAXNUM 244 12336 12337 /* MC_CMD_XPM_WRITE_BYTES_OUT msgresponse */ 12338 #define MC_CMD_XPM_WRITE_BYTES_OUT_LEN 0 12339 12340 12341 /***********************************/ 12342 /* MC_CMD_XPM_READ_SECTOR 12343 * Read XPM sector 12344 */ 12345 #define MC_CMD_XPM_READ_SECTOR 0x105 12346 #undef MC_CMD_0x105_PRIVILEGE_CTG 12347 12348 #define MC_CMD_0x105_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12349 12350 /* MC_CMD_XPM_READ_SECTOR_IN msgrequest */ 12351 #define MC_CMD_XPM_READ_SECTOR_IN_LEN 8 12352 /* Sector index */ 12353 #define MC_CMD_XPM_READ_SECTOR_IN_INDEX_OFST 0 12354 /* Sector size */ 12355 #define MC_CMD_XPM_READ_SECTOR_IN_SIZE_OFST 4 12356 12357 /* MC_CMD_XPM_READ_SECTOR_OUT msgresponse */ 12358 #define MC_CMD_XPM_READ_SECTOR_OUT_LENMIN 4 12359 #define MC_CMD_XPM_READ_SECTOR_OUT_LENMAX 36 12360 #define MC_CMD_XPM_READ_SECTOR_OUT_LEN(num) (4+1*(num)) 12361 /* Sector type */ 12362 #define MC_CMD_XPM_READ_SECTOR_OUT_TYPE_OFST 0 12363 #define MC_CMD_XPM_READ_SECTOR_OUT_BLANK 0x0 /* enum */ 12364 #define MC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_KEY_128 0x1 /* enum */ 12365 #define MC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_KEY_256 0x2 /* enum */ 12366 #define MC_CMD_XPM_READ_SECTOR_OUT_INVALID 0xff /* enum */ 12367 /* Sector data */ 12368 #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_OFST 4 12369 #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_LEN 1 12370 #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_MINNUM 0 12371 #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_MAXNUM 32 12372 12373 12374 /***********************************/ 12375 /* MC_CMD_XPM_WRITE_SECTOR 12376 * Write XPM sector 12377 */ 12378 #define MC_CMD_XPM_WRITE_SECTOR 0x106 12379 #undef MC_CMD_0x106_PRIVILEGE_CTG 12380 12381 #define MC_CMD_0x106_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12382 12383 /* MC_CMD_XPM_WRITE_SECTOR_IN msgrequest */ 12384 #define MC_CMD_XPM_WRITE_SECTOR_IN_LENMIN 12 12385 #define MC_CMD_XPM_WRITE_SECTOR_IN_LENMAX 44 12386 #define MC_CMD_XPM_WRITE_SECTOR_IN_LEN(num) (12+1*(num)) 12387 /* If writing fails due to an uncorrectable error, try up to RETRIES following 12388 * sectors (or until no more space available). If 0, only one write attempt is 12389 * made. Note that uncorrectable errors are unlikely, thanks to XPM self-repair 12390 * mechanism. 12391 */ 12392 #define MC_CMD_XPM_WRITE_SECTOR_IN_RETRIES_OFST 0 12393 #define MC_CMD_XPM_WRITE_SECTOR_IN_RETRIES_LEN 1 12394 #define MC_CMD_XPM_WRITE_SECTOR_IN_RESERVED_OFST 1 12395 #define MC_CMD_XPM_WRITE_SECTOR_IN_RESERVED_LEN 3 12396 /* Sector type */ 12397 #define MC_CMD_XPM_WRITE_SECTOR_IN_TYPE_OFST 4 12398 /* Enum values, see field(s): */ 12399 /* MC_CMD_XPM_READ_SECTOR_OUT/TYPE */ 12400 /* Sector size */ 12401 #define MC_CMD_XPM_WRITE_SECTOR_IN_SIZE_OFST 8 12402 /* Sector data */ 12403 #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_OFST 12 12404 #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_LEN 1 12405 #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_MINNUM 0 12406 #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_MAXNUM 32 12407 12408 /* MC_CMD_XPM_WRITE_SECTOR_OUT msgresponse */ 12409 #define MC_CMD_XPM_WRITE_SECTOR_OUT_LEN 4 12410 /* New sector index */ 12411 #define MC_CMD_XPM_WRITE_SECTOR_OUT_INDEX_OFST 0 12412 12413 12414 /***********************************/ 12415 /* MC_CMD_XPM_INVALIDATE_SECTOR 12416 * Invalidate XPM sector 12417 */ 12418 #define MC_CMD_XPM_INVALIDATE_SECTOR 0x107 12419 #undef MC_CMD_0x107_PRIVILEGE_CTG 12420 12421 #define MC_CMD_0x107_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12422 12423 /* MC_CMD_XPM_INVALIDATE_SECTOR_IN msgrequest */ 12424 #define MC_CMD_XPM_INVALIDATE_SECTOR_IN_LEN 4 12425 /* Sector index */ 12426 #define MC_CMD_XPM_INVALIDATE_SECTOR_IN_INDEX_OFST 0 12427 12428 /* MC_CMD_XPM_INVALIDATE_SECTOR_OUT msgresponse */ 12429 #define MC_CMD_XPM_INVALIDATE_SECTOR_OUT_LEN 0 12430 12431 12432 /***********************************/ 12433 /* MC_CMD_XPM_BLANK_CHECK 12434 * Blank-check XPM memory and report bad locations 12435 */ 12436 #define MC_CMD_XPM_BLANK_CHECK 0x108 12437 #undef MC_CMD_0x108_PRIVILEGE_CTG 12438 12439 #define MC_CMD_0x108_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12440 12441 /* MC_CMD_XPM_BLANK_CHECK_IN msgrequest */ 12442 #define MC_CMD_XPM_BLANK_CHECK_IN_LEN 8 12443 /* Start address (byte) */ 12444 #define MC_CMD_XPM_BLANK_CHECK_IN_ADDR_OFST 0 12445 /* Count (bytes) */ 12446 #define MC_CMD_XPM_BLANK_CHECK_IN_COUNT_OFST 4 12447 12448 /* MC_CMD_XPM_BLANK_CHECK_OUT msgresponse */ 12449 #define MC_CMD_XPM_BLANK_CHECK_OUT_LENMIN 4 12450 #define MC_CMD_XPM_BLANK_CHECK_OUT_LENMAX 252 12451 #define MC_CMD_XPM_BLANK_CHECK_OUT_LEN(num) (4+2*(num)) 12452 /* Total number of bad (non-blank) locations */ 12453 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_COUNT_OFST 0 12454 /* Addresses of bad locations (may be less than BAD_COUNT, if all cannot fit 12455 * into MCDI response) 12456 */ 12457 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_OFST 4 12458 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_LEN 2 12459 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_MINNUM 0 12460 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_MAXNUM 124 12461 12462 12463 /***********************************/ 12464 /* MC_CMD_XPM_REPAIR 12465 * Blank-check and repair XPM memory 12466 */ 12467 #define MC_CMD_XPM_REPAIR 0x109 12468 #undef MC_CMD_0x109_PRIVILEGE_CTG 12469 12470 #define MC_CMD_0x109_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12471 12472 /* MC_CMD_XPM_REPAIR_IN msgrequest */ 12473 #define MC_CMD_XPM_REPAIR_IN_LEN 8 12474 /* Start address (byte) */ 12475 #define MC_CMD_XPM_REPAIR_IN_ADDR_OFST 0 12476 /* Count (bytes) */ 12477 #define MC_CMD_XPM_REPAIR_IN_COUNT_OFST 4 12478 12479 /* MC_CMD_XPM_REPAIR_OUT msgresponse */ 12480 #define MC_CMD_XPM_REPAIR_OUT_LEN 0 12481 12482 12483 /***********************************/ 12484 /* MC_CMD_XPM_DECODER_TEST 12485 * Test XPM memory address decoders for gross manufacturing defects. Can only 12486 * be performed on an unprogrammed part. 12487 */ 12488 #define MC_CMD_XPM_DECODER_TEST 0x10a 12489 #undef MC_CMD_0x10a_PRIVILEGE_CTG 12490 12491 #define MC_CMD_0x10a_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12492 12493 /* MC_CMD_XPM_DECODER_TEST_IN msgrequest */ 12494 #define MC_CMD_XPM_DECODER_TEST_IN_LEN 0 12495 12496 /* MC_CMD_XPM_DECODER_TEST_OUT msgresponse */ 12497 #define MC_CMD_XPM_DECODER_TEST_OUT_LEN 0 12498 12499 12500 /***********************************/ 12501 /* MC_CMD_XPM_WRITE_TEST 12502 * XPM memory write test. Test XPM write logic for gross manufacturing defects 12503 * by writing to a dedicated test row. There are 16 locations in the test row 12504 * and the test can only be performed on locations that have not been 12505 * previously used (i.e. can be run at most 16 times). The test will pick the 12506 * first available location to use, or fail with ENOSPC if none left. 12507 */ 12508 #define MC_CMD_XPM_WRITE_TEST 0x10b 12509 #undef MC_CMD_0x10b_PRIVILEGE_CTG 12510 12511 #define MC_CMD_0x10b_PRIVILEGE_CTG SRIOV_CTG_ADMIN 12512 12513 /* MC_CMD_XPM_WRITE_TEST_IN msgrequest */ 12514 #define MC_CMD_XPM_WRITE_TEST_IN_LEN 0 12515 12516 /* MC_CMD_XPM_WRITE_TEST_OUT msgresponse */ 12517 #define MC_CMD_XPM_WRITE_TEST_OUT_LEN 0 12518 12519 #endif /* _SIENA_MC_DRIVER_PCOL_H */ 12520