1 /*- 2 * Copyright (c) 2007-2015 Solarflare Communications Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * The views and conclusions contained in the software and documentation are 27 * those of the authors and should not be interpreted as representing official 28 * policies, either expressed or implied, of the FreeBSD Project. 29 * 30 * $FreeBSD$ 31 */ 32 33 #ifndef _SYS_EFX_EF10_REGS_H 34 #define _SYS_EFX_EF10_REGS_H 35 36 #ifdef __cplusplus 37 extern "C" { 38 #endif 39 40 /************************************************************************** 41 * NOTE: the line below marks the start of the autogenerated section 42 * EF10 registers and descriptors 43 * 44 ************************************************************************** 45 */ 46 47 /* 48 * BIU_HW_REV_ID_REG(32bit): 49 * 50 */ 51 52 #define ER_DZ_BIU_HW_REV_ID_REG_OFST 0x00000000 53 /* hunta0=pcie_pf_bar2 */ 54 #define ER_DZ_BIU_HW_REV_ID_REG_RESET 0xeb14face 55 56 57 #define ERF_DZ_HW_REV_ID_LBN 0 58 #define ERF_DZ_HW_REV_ID_WIDTH 32 59 60 61 /* 62 * BIU_MC_SFT_STATUS_REG(32bit): 63 * 64 */ 65 66 #define ER_DZ_BIU_MC_SFT_STATUS_REG_OFST 0x00000010 67 /* hunta0=pcie_pf_bar2 */ 68 #define ER_DZ_BIU_MC_SFT_STATUS_REG_STEP 4 69 #define ER_DZ_BIU_MC_SFT_STATUS_REG_ROWS 8 70 #define ER_DZ_BIU_MC_SFT_STATUS_REG_RESET 0x1111face 71 72 73 #define ERF_DZ_MC_SFT_STATUS_LBN 0 74 #define ERF_DZ_MC_SFT_STATUS_WIDTH 32 75 76 77 /* 78 * BIU_INT_ISR_REG(32bit): 79 * 80 */ 81 82 #define ER_DZ_BIU_INT_ISR_REG_OFST 0x00000090 83 /* hunta0=pcie_pf_bar2 */ 84 #define ER_DZ_BIU_INT_ISR_REG_RESET 0x0 85 86 87 #define ERF_DZ_ISR_REG_LBN 0 88 #define ERF_DZ_ISR_REG_WIDTH 32 89 90 91 /* 92 * MC_DB_LWRD_REG(32bit): 93 * 94 */ 95 96 #define ER_DZ_MC_DB_LWRD_REG_OFST 0x00000200 97 /* hunta0=pcie_pf_bar2 */ 98 #define ER_DZ_MC_DB_LWRD_REG_RESET 0x0 99 100 101 #define ERF_DZ_MC_DOORBELL_L_LBN 0 102 #define ERF_DZ_MC_DOORBELL_L_WIDTH 32 103 104 105 /* 106 * MC_DB_HWRD_REG(32bit): 107 * 108 */ 109 110 #define ER_DZ_MC_DB_HWRD_REG_OFST 0x00000204 111 /* hunta0=pcie_pf_bar2 */ 112 #define ER_DZ_MC_DB_HWRD_REG_RESET 0x0 113 114 115 #define ERF_DZ_MC_DOORBELL_H_LBN 0 116 #define ERF_DZ_MC_DOORBELL_H_WIDTH 32 117 118 119 /* 120 * EVQ_RPTR_REG(32bit): 121 * 122 */ 123 124 #define ER_DZ_EVQ_RPTR_REG_OFST 0x00000400 125 /* hunta0=pcie_pf_bar2 */ 126 #define ER_DZ_EVQ_RPTR_REG_STEP 8192 127 #define ER_DZ_EVQ_RPTR_REG_ROWS 2048 128 #define ER_DZ_EVQ_RPTR_REG_RESET 0x0 129 130 131 #define ERF_DZ_EVQ_RPTR_VLD_LBN 15 132 #define ERF_DZ_EVQ_RPTR_VLD_WIDTH 1 133 #define ERF_DZ_EVQ_RPTR_LBN 0 134 #define ERF_DZ_EVQ_RPTR_WIDTH 15 135 136 137 /* 138 * EVQ_TMR_REG(32bit): 139 * 140 */ 141 142 #define ER_DZ_EVQ_TMR_REG_OFST 0x00000420 143 /* hunta0=pcie_pf_bar2 */ 144 #define ER_DZ_EVQ_TMR_REG_STEP 8192 145 #define ER_DZ_EVQ_TMR_REG_ROWS 2048 146 #define ER_DZ_EVQ_TMR_REG_RESET 0x0 147 148 149 #define ERF_DZ_TC_TIMER_MODE_LBN 14 150 #define ERF_DZ_TC_TIMER_MODE_WIDTH 2 151 #define ERF_DZ_TC_TIMER_VAL_LBN 0 152 #define ERF_DZ_TC_TIMER_VAL_WIDTH 14 153 154 155 /* 156 * RX_DESC_UPD_REG(32bit): 157 * 158 */ 159 160 #define ER_DZ_RX_DESC_UPD_REG_OFST 0x00000830 161 /* hunta0=pcie_pf_bar2 */ 162 #define ER_DZ_RX_DESC_UPD_REG_STEP 8192 163 #define ER_DZ_RX_DESC_UPD_REG_ROWS 2048 164 #define ER_DZ_RX_DESC_UPD_REG_RESET 0x0 165 166 167 #define ERF_DZ_RX_DESC_WPTR_LBN 0 168 #define ERF_DZ_RX_DESC_WPTR_WIDTH 12 169 170 171 /* 172 * TX_DESC_UPD_REG(96bit): 173 * 174 */ 175 176 #define ER_DZ_TX_DESC_UPD_REG_OFST 0x00000a10 177 /* hunta0=pcie_pf_bar2 */ 178 #define ER_DZ_TX_DESC_UPD_REG_STEP 8192 179 #define ER_DZ_TX_DESC_UPD_REG_ROWS 2048 180 #define ER_DZ_TX_DESC_UPD_REG_RESET 0x0 181 182 183 #define ERF_DZ_RSVD_LBN 76 184 #define ERF_DZ_RSVD_WIDTH 20 185 #define ERF_DZ_TX_DESC_WPTR_LBN 64 186 #define ERF_DZ_TX_DESC_WPTR_WIDTH 12 187 #define ERF_DZ_TX_DESC_HWORD_LBN 32 188 #define ERF_DZ_TX_DESC_HWORD_WIDTH 32 189 #define ERF_DZ_TX_DESC_LWORD_LBN 0 190 #define ERF_DZ_TX_DESC_LWORD_WIDTH 32 191 192 193 /* ES_DRIVER_EV */ 194 #define ESF_DZ_DRV_CODE_LBN 60 195 #define ESF_DZ_DRV_CODE_WIDTH 4 196 #define ESF_DZ_DRV_SUB_CODE_LBN 56 197 #define ESF_DZ_DRV_SUB_CODE_WIDTH 4 198 #define ESE_DZ_DRV_TIMER_EV 3 199 #define ESE_DZ_DRV_START_UP_EV 2 200 #define ESE_DZ_DRV_WAKE_UP_EV 1 201 #define ESF_DZ_DRV_SUB_DATA_DW0_LBN 0 202 #define ESF_DZ_DRV_SUB_DATA_DW0_WIDTH 32 203 #define ESF_DZ_DRV_SUB_DATA_DW1_LBN 32 204 #define ESF_DZ_DRV_SUB_DATA_DW1_WIDTH 24 205 #define ESF_DZ_DRV_SUB_DATA_LBN 0 206 #define ESF_DZ_DRV_SUB_DATA_WIDTH 56 207 #define ESF_DZ_DRV_EVQ_ID_LBN 0 208 #define ESF_DZ_DRV_EVQ_ID_WIDTH 14 209 #define ESF_DZ_DRV_TMR_ID_LBN 0 210 #define ESF_DZ_DRV_TMR_ID_WIDTH 14 211 212 213 /* ES_EVENT_ENTRY */ 214 #define ESF_DZ_EV_CODE_LBN 60 215 #define ESF_DZ_EV_CODE_WIDTH 4 216 #define ESE_DZ_EV_CODE_MCDI_EV 12 217 #define ESE_DZ_EV_CODE_DRIVER_EV 5 218 #define ESE_DZ_EV_CODE_TX_EV 2 219 #define ESE_DZ_EV_CODE_RX_EV 0 220 #define ESE_DZ_OTHER other 221 #define ESF_DZ_EV_DATA_DW0_LBN 0 222 #define ESF_DZ_EV_DATA_DW0_WIDTH 32 223 #define ESF_DZ_EV_DATA_DW1_LBN 32 224 #define ESF_DZ_EV_DATA_DW1_WIDTH 28 225 #define ESF_DZ_EV_DATA_LBN 0 226 #define ESF_DZ_EV_DATA_WIDTH 60 227 228 229 /* ES_MC_EVENT */ 230 #define ESF_DZ_MC_CODE_LBN 60 231 #define ESF_DZ_MC_CODE_WIDTH 4 232 #define ESF_DZ_MC_OVERRIDE_HOLDOFF_LBN 59 233 #define ESF_DZ_MC_OVERRIDE_HOLDOFF_WIDTH 1 234 #define ESF_DZ_MC_DROP_EVENT_LBN 58 235 #define ESF_DZ_MC_DROP_EVENT_WIDTH 1 236 #define ESF_DZ_MC_SOFT_DW0_LBN 0 237 #define ESF_DZ_MC_SOFT_DW0_WIDTH 32 238 #define ESF_DZ_MC_SOFT_DW1_LBN 32 239 #define ESF_DZ_MC_SOFT_DW1_WIDTH 26 240 #define ESF_DZ_MC_SOFT_LBN 0 241 #define ESF_DZ_MC_SOFT_WIDTH 58 242 243 244 /* ES_RX_EVENT */ 245 #define ESF_DZ_RX_CODE_LBN 60 246 #define ESF_DZ_RX_CODE_WIDTH 4 247 #define ESF_DZ_RX_OVERRIDE_HOLDOFF_LBN 59 248 #define ESF_DZ_RX_OVERRIDE_HOLDOFF_WIDTH 1 249 #define ESF_DZ_RX_DROP_EVENT_LBN 58 250 #define ESF_DZ_RX_DROP_EVENT_WIDTH 1 251 #define ESF_DZ_RX_EV_RSVD2_LBN 54 252 #define ESF_DZ_RX_EV_RSVD2_WIDTH 4 253 #define ESF_DZ_RX_EV_SOFT2_LBN 52 254 #define ESF_DZ_RX_EV_SOFT2_WIDTH 2 255 #define ESF_DZ_RX_DSC_PTR_LBITS_LBN 48 256 #define ESF_DZ_RX_DSC_PTR_LBITS_WIDTH 4 257 #define ESF_DZ_RX_L4_CLASS_LBN 45 258 #define ESF_DZ_RX_L4_CLASS_WIDTH 3 259 #define ESE_DZ_L4_CLASS_RSVD7 7 260 #define ESE_DZ_L4_CLASS_RSVD6 6 261 #define ESE_DZ_L4_CLASS_RSVD5 5 262 #define ESE_DZ_L4_CLASS_RSVD4 4 263 #define ESE_DZ_L4_CLASS_RSVD3 3 264 #define ESE_DZ_L4_CLASS_UDP 2 265 #define ESE_DZ_L4_CLASS_TCP 1 266 #define ESE_DZ_L4_CLASS_UNKNOWN 0 267 #define ESF_DZ_RX_L3_CLASS_LBN 42 268 #define ESF_DZ_RX_L3_CLASS_WIDTH 3 269 #define ESE_DZ_L3_CLASS_RSVD7 7 270 #define ESE_DZ_L3_CLASS_IP6_FRAG 6 271 #define ESE_DZ_L3_CLASS_ARP 5 272 #define ESE_DZ_L3_CLASS_IP4_FRAG 4 273 #define ESE_DZ_L3_CLASS_FCOE 3 274 #define ESE_DZ_L3_CLASS_IP6 2 275 #define ESE_DZ_L3_CLASS_IP4 1 276 #define ESE_DZ_L3_CLASS_UNKNOWN 0 277 #define ESF_DZ_RX_ETH_TAG_CLASS_LBN 39 278 #define ESF_DZ_RX_ETH_TAG_CLASS_WIDTH 3 279 #define ESE_DZ_ETH_TAG_CLASS_RSVD7 7 280 #define ESE_DZ_ETH_TAG_CLASS_RSVD6 6 281 #define ESE_DZ_ETH_TAG_CLASS_RSVD5 5 282 #define ESE_DZ_ETH_TAG_CLASS_RSVD4 4 283 #define ESE_DZ_ETH_TAG_CLASS_RSVD3 3 284 #define ESE_DZ_ETH_TAG_CLASS_VLAN2 2 285 #define ESE_DZ_ETH_TAG_CLASS_VLAN1 1 286 #define ESE_DZ_ETH_TAG_CLASS_NONE 0 287 #define ESF_DZ_RX_ETH_BASE_CLASS_LBN 36 288 #define ESF_DZ_RX_ETH_BASE_CLASS_WIDTH 3 289 #define ESE_DZ_ETH_BASE_CLASS_LLC_SNAP 2 290 #define ESE_DZ_ETH_BASE_CLASS_LLC 1 291 #define ESE_DZ_ETH_BASE_CLASS_ETH2 0 292 #define ESF_DZ_RX_MAC_CLASS_LBN 35 293 #define ESF_DZ_RX_MAC_CLASS_WIDTH 1 294 #define ESE_DZ_MAC_CLASS_MCAST 1 295 #define ESE_DZ_MAC_CLASS_UCAST 0 296 #define ESF_DZ_RX_EV_SOFT1_LBN 32 297 #define ESF_DZ_RX_EV_SOFT1_WIDTH 3 298 #define ESF_DZ_RX_EV_RSVD1_LBN 30 299 #define ESF_DZ_RX_EV_RSVD1_WIDTH 2 300 #define ESF_DZ_RX_ECC_ERR_LBN 29 301 #define ESF_DZ_RX_ECC_ERR_WIDTH 1 302 #define ESF_DZ_RX_CRC1_ERR_LBN 28 303 #define ESF_DZ_RX_CRC1_ERR_WIDTH 1 304 #define ESF_DZ_RX_CRC0_ERR_LBN 27 305 #define ESF_DZ_RX_CRC0_ERR_WIDTH 1 306 #define ESF_DZ_RX_TCPUDP_CKSUM_ERR_LBN 26 307 #define ESF_DZ_RX_TCPUDP_CKSUM_ERR_WIDTH 1 308 #define ESF_DZ_RX_IPCKSUM_ERR_LBN 25 309 #define ESF_DZ_RX_IPCKSUM_ERR_WIDTH 1 310 #define ESF_DZ_RX_ECRC_ERR_LBN 24 311 #define ESF_DZ_RX_ECRC_ERR_WIDTH 1 312 #define ESF_DZ_RX_QLABEL_LBN 16 313 #define ESF_DZ_RX_QLABEL_WIDTH 5 314 #define ESF_DZ_RX_PARSE_INCOMPLETE_LBN 15 315 #define ESF_DZ_RX_PARSE_INCOMPLETE_WIDTH 1 316 #define ESF_DZ_RX_CONT_LBN 14 317 #define ESF_DZ_RX_CONT_WIDTH 1 318 #define ESF_DZ_RX_BYTES_LBN 0 319 #define ESF_DZ_RX_BYTES_WIDTH 14 320 321 322 /* ES_RX_KER_DESC */ 323 #define ESF_DZ_RX_KER_RESERVED_LBN 62 324 #define ESF_DZ_RX_KER_RESERVED_WIDTH 2 325 #define ESF_DZ_RX_KER_BYTE_CNT_LBN 48 326 #define ESF_DZ_RX_KER_BYTE_CNT_WIDTH 14 327 #define ESF_DZ_RX_KER_BUF_ADDR_DW0_LBN 0 328 #define ESF_DZ_RX_KER_BUF_ADDR_DW0_WIDTH 32 329 #define ESF_DZ_RX_KER_BUF_ADDR_DW1_LBN 32 330 #define ESF_DZ_RX_KER_BUF_ADDR_DW1_WIDTH 16 331 #define ESF_DZ_RX_KER_BUF_ADDR_LBN 0 332 #define ESF_DZ_RX_KER_BUF_ADDR_WIDTH 48 333 334 335 /* ES_TX_CSUM_TSTAMP_DESC */ 336 #define ESF_DZ_TX_DESC_IS_OPT_LBN 63 337 #define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1 338 #define ESF_DZ_TX_OPTION_TYPE_LBN 60 339 #define ESF_DZ_TX_OPTION_TYPE_WIDTH 3 340 #define ESE_DZ_TX_OPTION_DESC_TSO 7 341 #define ESE_DZ_TX_OPTION_DESC_VLAN 6 342 #define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0 343 #define ESF_DZ_TX_OPTION_TS_AT_TXDP_LBN 8 344 #define ESF_DZ_TX_OPTION_TS_AT_TXDP_WIDTH 1 345 #define ESF_DZ_TX_OPTION_INNER_UDP_TCP_CSUM_LBN 7 346 #define ESF_DZ_TX_OPTION_INNER_UDP_TCP_CSUM_WIDTH 1 347 #define ESF_DZ_TX_OPTION_INNER_IP_CSUM_LBN 6 348 #define ESF_DZ_TX_OPTION_INNER_IP_CSUM_WIDTH 1 349 #define ESF_DZ_TX_TIMESTAMP_LBN 5 350 #define ESF_DZ_TX_TIMESTAMP_WIDTH 1 351 #define ESF_DZ_TX_OPTION_CRC_MODE_LBN 2 352 #define ESF_DZ_TX_OPTION_CRC_MODE_WIDTH 3 353 #define ESE_DZ_TX_OPTION_CRC_FCOIP_MPA 5 354 #define ESE_DZ_TX_OPTION_CRC_FCOIP_FCOE 4 355 #define ESE_DZ_TX_OPTION_CRC_ISCSI_HDR_AND_PYLD 3 356 #define ESE_DZ_TX_OPTION_CRC_ISCSI_HDR 2 357 #define ESE_DZ_TX_OPTION_CRC_FCOE 1 358 #define ESE_DZ_TX_OPTION_CRC_OFF 0 359 #define ESF_DZ_TX_OPTION_UDP_TCP_CSUM_LBN 1 360 #define ESF_DZ_TX_OPTION_UDP_TCP_CSUM_WIDTH 1 361 #define ESF_DZ_TX_OPTION_IP_CSUM_LBN 0 362 #define ESF_DZ_TX_OPTION_IP_CSUM_WIDTH 1 363 364 365 /* ES_TX_EVENT */ 366 #define ESF_DZ_TX_CODE_LBN 60 367 #define ESF_DZ_TX_CODE_WIDTH 4 368 #define ESF_DZ_TX_OVERRIDE_HOLDOFF_LBN 59 369 #define ESF_DZ_TX_OVERRIDE_HOLDOFF_WIDTH 1 370 #define ESF_DZ_TX_DROP_EVENT_LBN 58 371 #define ESF_DZ_TX_DROP_EVENT_WIDTH 1 372 #define ESF_DZ_TX_EV_RSVD_LBN 48 373 #define ESF_DZ_TX_EV_RSVD_WIDTH 10 374 #define ESF_DZ_TX_SOFT2_LBN 32 375 #define ESF_DZ_TX_SOFT2_WIDTH 16 376 #define ESF_DZ_TX_SOFT1_LBN 24 377 #define ESF_DZ_TX_SOFT1_WIDTH 8 378 #define ESF_DZ_TX_QLABEL_LBN 16 379 #define ESF_DZ_TX_QLABEL_WIDTH 5 380 #define ESF_DZ_TX_DESCR_INDX_LBN 0 381 #define ESF_DZ_TX_DESCR_INDX_WIDTH 16 382 383 384 /* ES_TX_KER_DESC */ 385 #define ESF_DZ_TX_KER_TYPE_LBN 63 386 #define ESF_DZ_TX_KER_TYPE_WIDTH 1 387 #define ESF_DZ_TX_KER_CONT_LBN 62 388 #define ESF_DZ_TX_KER_CONT_WIDTH 1 389 #define ESF_DZ_TX_KER_BYTE_CNT_LBN 48 390 #define ESF_DZ_TX_KER_BYTE_CNT_WIDTH 14 391 #define ESF_DZ_TX_KER_BUF_ADDR_DW0_LBN 0 392 #define ESF_DZ_TX_KER_BUF_ADDR_DW0_WIDTH 32 393 #define ESF_DZ_TX_KER_BUF_ADDR_DW1_LBN 32 394 #define ESF_DZ_TX_KER_BUF_ADDR_DW1_WIDTH 16 395 #define ESF_DZ_TX_KER_BUF_ADDR_LBN 0 396 #define ESF_DZ_TX_KER_BUF_ADDR_WIDTH 48 397 398 399 /* ES_TX_PIO_DESC */ 400 #define ESF_DZ_TX_PIO_TYPE_LBN 63 401 #define ESF_DZ_TX_PIO_TYPE_WIDTH 1 402 #define ESF_DZ_TX_PIO_OPT_LBN 60 403 #define ESF_DZ_TX_PIO_OPT_WIDTH 3 404 #define ESF_DZ_TX_PIO_CONT_LBN 59 405 #define ESF_DZ_TX_PIO_CONT_WIDTH 1 406 #define ESF_DZ_TX_PIO_BYTE_CNT_LBN 32 407 #define ESF_DZ_TX_PIO_BYTE_CNT_WIDTH 12 408 #define ESF_DZ_TX_PIO_BUF_ADDR_LBN 0 409 #define ESF_DZ_TX_PIO_BUF_ADDR_WIDTH 12 410 411 412 /* ES_TX_TSO_DESC */ 413 #define ESF_DZ_TX_DESC_IS_OPT_LBN 63 414 #define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1 415 #define ESF_DZ_TX_OPTION_TYPE_LBN 60 416 #define ESF_DZ_TX_OPTION_TYPE_WIDTH 3 417 #define ESE_DZ_TX_OPTION_DESC_TSO 7 418 #define ESE_DZ_TX_OPTION_DESC_VLAN 6 419 #define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0 420 #define ESF_DZ_TX_TSO_OPTION_TYPE_LBN 56 421 #define ESF_DZ_TX_TSO_OPTION_TYPE_WIDTH 4 422 #define ESE_DZ_TX_TSO_OPTION_DESC_ENCAP 1 423 #define ESE_DZ_TX_TSO_OPTION_DESC_NORMAL 0 424 #define ESF_DZ_TX_TSO_TCP_FLAGS_LBN 48 425 #define ESF_DZ_TX_TSO_TCP_FLAGS_WIDTH 8 426 #define ESF_DZ_TX_TSO_IP_ID_LBN 32 427 #define ESF_DZ_TX_TSO_IP_ID_WIDTH 16 428 #define ESF_DZ_TX_TSO_TCP_SEQNO_LBN 0 429 #define ESF_DZ_TX_TSO_TCP_SEQNO_WIDTH 32 430 431 432 /* TX_TSO_FATSO2A_DESC */ 433 #define ESF_DZ_TX_DESC_IS_OPT_LBN 63 434 #define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1 435 #define ESF_DZ_TX_OPTION_TYPE_LBN 60 436 #define ESF_DZ_TX_OPTION_TYPE_WIDTH 3 437 #define ESE_DZ_TX_OPTION_DESC_TSO 7 438 #define ESE_DZ_TX_OPTION_DESC_VLAN 6 439 #define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0 440 #define ESF_DZ_TX_TSO_OPTION_TYPE_LBN 56 441 #define ESF_DZ_TX_TSO_OPTION_TYPE_WIDTH 4 442 #define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B 3 443 #define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A 2 444 #define ESE_DZ_TX_TSO_OPTION_DESC_ENCAP 1 445 #define ESE_DZ_TX_TSO_OPTION_DESC_NORMAL 0 446 #define ESF_DZ_TX_TSO_IP_ID_LBN 32 447 #define ESF_DZ_TX_TSO_IP_ID_WIDTH 16 448 #define ESF_DZ_TX_TSO_TCP_SEQNO_LBN 0 449 #define ESF_DZ_TX_TSO_TCP_SEQNO_WIDTH 32 450 451 452 /* TX_TSO_FATSO2B_DESC */ 453 #define ESF_DZ_TX_DESC_IS_OPT_LBN 63 454 #define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1 455 #define ESF_DZ_TX_OPTION_TYPE_LBN 60 456 #define ESF_DZ_TX_OPTION_TYPE_WIDTH 3 457 #define ESE_DZ_TX_OPTION_DESC_TSO 7 458 #define ESE_DZ_TX_OPTION_DESC_VLAN 6 459 #define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0 460 #define ESF_DZ_TX_TSO_OPTION_TYPE_LBN 56 461 #define ESF_DZ_TX_TSO_OPTION_TYPE_WIDTH 4 462 #define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B 3 463 #define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A 2 464 #define ESE_DZ_TX_TSO_OPTION_DESC_ENCAP 1 465 #define ESE_DZ_TX_TSO_OPTION_DESC_NORMAL 0 466 #define ESF_DZ_TX_TSO_OUTER_IP_ID_LBN 16 467 #define ESF_DZ_TX_TSO_OUTER_IP_ID_WIDTH 16 468 #define ESF_DZ_TX_TSO_TCP_MSS_LBN 32 469 #define ESF_DZ_TX_TSO_TCP_MSS_WIDTH 16 470 #define ESF_DZ_TX_TSO_INNER_PE_CSUM_LBN 0 471 #define ESF_DZ_TX_TSO_INNER_PE_CSUM_WIDTH 16 472 473 474 /* ES_TX_VLAN_DESC */ 475 #define ESF_DZ_TX_DESC_IS_OPT_LBN 63 476 #define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1 477 #define ESF_DZ_TX_OPTION_TYPE_LBN 60 478 #define ESF_DZ_TX_OPTION_TYPE_WIDTH 3 479 #define ESE_DZ_TX_OPTION_DESC_TSO 7 480 #define ESE_DZ_TX_OPTION_DESC_VLAN 6 481 #define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0 482 #define ESF_DZ_TX_VLAN_OP_LBN 32 483 #define ESF_DZ_TX_VLAN_OP_WIDTH 2 484 #define ESF_DZ_TX_VLAN_TAG2_LBN 16 485 #define ESF_DZ_TX_VLAN_TAG2_WIDTH 16 486 #define ESF_DZ_TX_VLAN_TAG1_LBN 0 487 #define ESF_DZ_TX_VLAN_TAG1_WIDTH 16 488 489 490 /************************************************************************* 491 * NOTE: the comment line above marks the end of the autogenerated section 492 */ 493 494 /* 495 * The workaround for bug 35388 requires multiplexing writes through 496 * the ERF_DZ_TX_DESC_WPTR address. 497 * TX_DESC_UPD: 0ppppppppppp (bit 11 lost) 498 * EVQ_RPTR: 1000hhhhhhhh, 1001llllllll (split into high and low bits) 499 * EVQ_TMR: 11mmvvvvvvvv (bits 8:13 of value lost) 500 */ 501 #define ER_DD_EVQ_INDIRECT_OFST (ER_DZ_TX_DESC_UPD_REG_OFST + 2 * 4) 502 #define ER_DD_EVQ_INDIRECT_STEP ER_DZ_TX_DESC_UPD_REG_STEP 503 #define ERF_DD_EVQ_IND_RPTR_FLAGS_LBN 8 504 #define ERF_DD_EVQ_IND_RPTR_FLAGS_WIDTH 4 505 #define EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH 8 506 #define EFE_DD_EVQ_IND_RPTR_FLAGS_LOW 9 507 #define ERF_DD_EVQ_IND_RPTR_LBN 0 508 #define ERF_DD_EVQ_IND_RPTR_WIDTH 8 509 #define ERF_DD_EVQ_IND_TIMER_FLAGS_LBN 10 510 #define ERF_DD_EVQ_IND_TIMER_FLAGS_WIDTH 2 511 #define EFE_DD_EVQ_IND_TIMER_FLAGS 3 512 #define ERF_DD_EVQ_IND_TIMER_MODE_LBN 8 513 #define ERF_DD_EVQ_IND_TIMER_MODE_WIDTH 2 514 #define ERF_DD_EVQ_IND_TIMER_VAL_LBN 0 515 #define ERF_DD_EVQ_IND_TIMER_VAL_WIDTH 8 516 517 518 #ifdef __cplusplus 519 } 520 #endif 521 522 #endif /* _SYS_EFX_EF10_REGS_H */ 523