1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2007-2016 Solarflare Communications Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 18 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 26 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * The views and conclusions contained in the software and documentation are 29 * those of the authors and should not be interpreted as representing official 30 * policies, either expressed or implied, of the FreeBSD Project. 31 * 32 * $FreeBSD$ 33 */ 34 35 #ifndef _SYS_EFX_EF10_REGS_H 36 #define _SYS_EFX_EF10_REGS_H 37 38 #ifdef __cplusplus 39 extern "C" { 40 #endif 41 42 /************************************************************************** 43 * NOTE: the line below marks the start of the autogenerated section 44 * EF10 registers and descriptors 45 * 46 ************************************************************************** 47 */ 48 49 /* 50 * BIU_HW_REV_ID_REG(32bit): 51 * 52 */ 53 54 #define ER_DZ_BIU_HW_REV_ID_REG_OFST 0x00000000 55 /* hunta0,medforda0,medford2a0=pf_dbell_bar */ 56 #define ER_DZ_BIU_HW_REV_ID_REG_RESET 0xeb14face 57 58 59 #define ERF_DZ_HW_REV_ID_LBN 0 60 #define ERF_DZ_HW_REV_ID_WIDTH 32 61 62 63 /* 64 * BIU_MC_SFT_STATUS_REG(32bit): 65 * 66 */ 67 68 #define ER_DZ_BIU_MC_SFT_STATUS_REG_OFST 0x00000010 69 /* hunta0,medforda0,medford2a0=pf_dbell_bar */ 70 #define ER_DZ_BIU_MC_SFT_STATUS_REG_STEP 4 71 #define ER_DZ_BIU_MC_SFT_STATUS_REG_ROWS 8 72 #define ER_DZ_BIU_MC_SFT_STATUS_REG_RESET 0x1111face 73 74 75 #define ERF_DZ_MC_SFT_STATUS_LBN 0 76 #define ERF_DZ_MC_SFT_STATUS_WIDTH 32 77 78 79 /* 80 * BIU_INT_ISR_REG(32bit): 81 * 82 */ 83 84 #define ER_DZ_BIU_INT_ISR_REG_OFST 0x00000090 85 /* hunta0,medforda0,medford2a0=pf_dbell_bar */ 86 #define ER_DZ_BIU_INT_ISR_REG_RESET 0x0 87 88 89 #define ERF_DZ_ISR_REG_LBN 0 90 #define ERF_DZ_ISR_REG_WIDTH 32 91 92 93 /* 94 * MC_DB_LWRD_REG(32bit): 95 * 96 */ 97 98 #define ER_DZ_MC_DB_LWRD_REG_OFST 0x00000200 99 /* hunta0,medforda0,medford2a0=pf_dbell_bar */ 100 #define ER_DZ_MC_DB_LWRD_REG_RESET 0x0 101 102 103 #define ERF_DZ_MC_DOORBELL_L_LBN 0 104 #define ERF_DZ_MC_DOORBELL_L_WIDTH 32 105 106 107 /* 108 * MC_DB_HWRD_REG(32bit): 109 * 110 */ 111 112 #define ER_DZ_MC_DB_HWRD_REG_OFST 0x00000204 113 /* hunta0,medforda0,medford2a0=pf_dbell_bar */ 114 #define ER_DZ_MC_DB_HWRD_REG_RESET 0x0 115 116 117 #define ERF_DZ_MC_DOORBELL_H_LBN 0 118 #define ERF_DZ_MC_DOORBELL_H_WIDTH 32 119 120 121 /* 122 * EVQ_RPTR_REG(32bit): 123 * 124 */ 125 126 #define ER_DZ_EVQ_RPTR_REG_OFST 0x00000400 127 /* hunta0,medforda0,medford2a0=pf_dbell_bar */ 128 #define ER_DZ_EVQ_RPTR_REG_STEP 8192 129 #define ER_DZ_EVQ_RPTR_REG_ROWS 2048 130 #define ER_DZ_EVQ_RPTR_REG_RESET 0x0 131 132 133 #define ERF_DZ_EVQ_RPTR_VLD_LBN 15 134 #define ERF_DZ_EVQ_RPTR_VLD_WIDTH 1 135 #define ERF_DZ_EVQ_RPTR_LBN 0 136 #define ERF_DZ_EVQ_RPTR_WIDTH 15 137 138 139 /* 140 * EVQ_RPTR_REG_64K(32bit): 141 * 142 */ 143 144 #define ER_FZ_EVQ_RPTR_REG_64K_OFST 0x00000400 145 /* medford2a0=pf_dbell_bar */ 146 #define ER_FZ_EVQ_RPTR_REG_64K_STEP 65536 147 #define ER_FZ_EVQ_RPTR_REG_64K_ROWS 2048 148 #define ER_FZ_EVQ_RPTR_REG_64K_RESET 0x0 149 150 151 #define ERF_FZ_EVQ_RPTR_VLD_LBN 15 152 #define ERF_FZ_EVQ_RPTR_VLD_WIDTH 1 153 #define ERF_FZ_EVQ_RPTR_LBN 0 154 #define ERF_FZ_EVQ_RPTR_WIDTH 15 155 156 157 /* 158 * EVQ_RPTR_REG_16K(32bit): 159 * 160 */ 161 162 #define ER_FZ_EVQ_RPTR_REG_16K_OFST 0x00000400 163 /* medford2a0=pf_dbell_bar */ 164 #define ER_FZ_EVQ_RPTR_REG_16K_STEP 16384 165 #define ER_FZ_EVQ_RPTR_REG_16K_ROWS 2048 166 #define ER_FZ_EVQ_RPTR_REG_16K_RESET 0x0 167 168 169 /* defined as ERF_FZ_EVQ_RPTR_VLD_LBN 15; */ 170 /* defined as ERF_FZ_EVQ_RPTR_VLD_WIDTH 1 */ 171 /* defined as ERF_FZ_EVQ_RPTR_LBN 0; */ 172 /* defined as ERF_FZ_EVQ_RPTR_WIDTH 15 */ 173 174 175 /* 176 * EVQ_TMR_REG_64K(32bit): 177 * 178 */ 179 180 #define ER_FZ_EVQ_TMR_REG_64K_OFST 0x00000420 181 /* medford2a0=pf_dbell_bar */ 182 #define ER_FZ_EVQ_TMR_REG_64K_STEP 65536 183 #define ER_FZ_EVQ_TMR_REG_64K_ROWS 2048 184 #define ER_FZ_EVQ_TMR_REG_64K_RESET 0x0 185 186 187 #define ERF_FZ_TC_TIMER_MODE_LBN 14 188 #define ERF_FZ_TC_TIMER_MODE_WIDTH 2 189 #define ERF_FZ_TC_TIMER_VAL_LBN 0 190 #define ERF_FZ_TC_TIMER_VAL_WIDTH 14 191 192 193 /* 194 * EVQ_TMR_REG_16K(32bit): 195 * 196 */ 197 198 #define ER_FZ_EVQ_TMR_REG_16K_OFST 0x00000420 199 /* medford2a0=pf_dbell_bar */ 200 #define ER_FZ_EVQ_TMR_REG_16K_STEP 16384 201 #define ER_FZ_EVQ_TMR_REG_16K_ROWS 2048 202 #define ER_FZ_EVQ_TMR_REG_16K_RESET 0x0 203 204 205 /* defined as ERF_FZ_TC_TIMER_MODE_LBN 14; */ 206 /* defined as ERF_FZ_TC_TIMER_MODE_WIDTH 2 */ 207 /* defined as ERF_FZ_TC_TIMER_VAL_LBN 0; */ 208 /* defined as ERF_FZ_TC_TIMER_VAL_WIDTH 14 */ 209 210 211 /* 212 * EVQ_TMR_REG(32bit): 213 * 214 */ 215 216 #define ER_DZ_EVQ_TMR_REG_OFST 0x00000420 217 /* hunta0,medforda0,medford2a0=pf_dbell_bar */ 218 #define ER_DZ_EVQ_TMR_REG_STEP 8192 219 #define ER_DZ_EVQ_TMR_REG_ROWS 2048 220 #define ER_DZ_EVQ_TMR_REG_RESET 0x0 221 222 223 #define ERF_DZ_TC_TIMER_MODE_LBN 14 224 #define ERF_DZ_TC_TIMER_MODE_WIDTH 2 225 #define ERF_DZ_TC_TIMER_VAL_LBN 0 226 #define ERF_DZ_TC_TIMER_VAL_WIDTH 14 227 228 229 /* 230 * RX_DESC_UPD_REG_16K(32bit): 231 * 232 */ 233 234 #define ER_FZ_RX_DESC_UPD_REG_16K_OFST 0x00000830 235 /* medford2a0=pf_dbell_bar */ 236 #define ER_FZ_RX_DESC_UPD_REG_16K_STEP 16384 237 #define ER_FZ_RX_DESC_UPD_REG_16K_ROWS 2048 238 #define ER_FZ_RX_DESC_UPD_REG_16K_RESET 0x0 239 240 241 #define ERF_FZ_RX_DESC_WPTR_LBN 0 242 #define ERF_FZ_RX_DESC_WPTR_WIDTH 12 243 244 245 /* 246 * RX_DESC_UPD_REG(32bit): 247 * 248 */ 249 250 #define ER_DZ_RX_DESC_UPD_REG_OFST 0x00000830 251 /* hunta0,medforda0,medford2a0=pf_dbell_bar */ 252 #define ER_DZ_RX_DESC_UPD_REG_STEP 8192 253 #define ER_DZ_RX_DESC_UPD_REG_ROWS 2048 254 #define ER_DZ_RX_DESC_UPD_REG_RESET 0x0 255 256 257 #define ERF_DZ_RX_DESC_WPTR_LBN 0 258 #define ERF_DZ_RX_DESC_WPTR_WIDTH 12 259 260 261 /* 262 * RX_DESC_UPD_REG_64K(32bit): 263 * 264 */ 265 266 #define ER_FZ_RX_DESC_UPD_REG_64K_OFST 0x00000830 267 /* medford2a0=pf_dbell_bar */ 268 #define ER_FZ_RX_DESC_UPD_REG_64K_STEP 65536 269 #define ER_FZ_RX_DESC_UPD_REG_64K_ROWS 2048 270 #define ER_FZ_RX_DESC_UPD_REG_64K_RESET 0x0 271 272 273 /* defined as ERF_FZ_RX_DESC_WPTR_LBN 0; */ 274 /* defined as ERF_FZ_RX_DESC_WPTR_WIDTH 12 */ 275 276 277 /* 278 * TX_DESC_UPD_REG_64K(96bit): 279 * 280 */ 281 282 #define ER_FZ_TX_DESC_UPD_REG_64K_OFST 0x00000a10 283 /* medford2a0=pf_dbell_bar */ 284 #define ER_FZ_TX_DESC_UPD_REG_64K_STEP 65536 285 #define ER_FZ_TX_DESC_UPD_REG_64K_ROWS 2048 286 #define ER_FZ_TX_DESC_UPD_REG_64K_RESET 0x0 287 288 289 #define ERF_FZ_RSVD_LBN 76 290 #define ERF_FZ_RSVD_WIDTH 20 291 #define ERF_FZ_TX_DESC_WPTR_LBN 64 292 #define ERF_FZ_TX_DESC_WPTR_WIDTH 12 293 #define ERF_FZ_TX_DESC_HWORD_LBN 32 294 #define ERF_FZ_TX_DESC_HWORD_WIDTH 32 295 #define ERF_FZ_TX_DESC_LWORD_LBN 0 296 #define ERF_FZ_TX_DESC_LWORD_WIDTH 32 297 298 299 /* 300 * TX_DESC_UPD_REG_16K(96bit): 301 * 302 */ 303 304 #define ER_FZ_TX_DESC_UPD_REG_16K_OFST 0x00000a10 305 /* medford2a0=pf_dbell_bar */ 306 #define ER_FZ_TX_DESC_UPD_REG_16K_STEP 16384 307 #define ER_FZ_TX_DESC_UPD_REG_16K_ROWS 2048 308 #define ER_FZ_TX_DESC_UPD_REG_16K_RESET 0x0 309 310 311 /* defined as ERF_FZ_RSVD_LBN 76; */ 312 /* defined as ERF_FZ_RSVD_WIDTH 20 */ 313 /* defined as ERF_FZ_TX_DESC_WPTR_LBN 64; */ 314 /* defined as ERF_FZ_TX_DESC_WPTR_WIDTH 12 */ 315 /* defined as ERF_FZ_TX_DESC_HWORD_LBN 32; */ 316 /* defined as ERF_FZ_TX_DESC_HWORD_WIDTH 32 */ 317 /* defined as ERF_FZ_TX_DESC_LWORD_LBN 0; */ 318 /* defined as ERF_FZ_TX_DESC_LWORD_WIDTH 32 */ 319 320 321 /* 322 * TX_DESC_UPD_REG(96bit): 323 * 324 */ 325 326 #define ER_DZ_TX_DESC_UPD_REG_OFST 0x00000a10 327 /* hunta0,medforda0,medford2a0=pf_dbell_bar */ 328 #define ER_DZ_TX_DESC_UPD_REG_STEP 8192 329 #define ER_DZ_TX_DESC_UPD_REG_ROWS 2048 330 #define ER_DZ_TX_DESC_UPD_REG_RESET 0x0 331 332 333 #define ERF_DZ_RSVD_LBN 76 334 #define ERF_DZ_RSVD_WIDTH 20 335 #define ERF_DZ_TX_DESC_WPTR_LBN 64 336 #define ERF_DZ_TX_DESC_WPTR_WIDTH 12 337 #define ERF_DZ_TX_DESC_HWORD_LBN 32 338 #define ERF_DZ_TX_DESC_HWORD_WIDTH 32 339 #define ERF_DZ_TX_DESC_LWORD_LBN 0 340 #define ERF_DZ_TX_DESC_LWORD_WIDTH 32 341 342 343 /* ES_DRIVER_EV */ 344 #define ESF_DZ_DRV_CODE_LBN 60 345 #define ESF_DZ_DRV_CODE_WIDTH 4 346 #define ESF_DZ_DRV_SUB_CODE_LBN 56 347 #define ESF_DZ_DRV_SUB_CODE_WIDTH 4 348 #define ESE_DZ_DRV_TIMER_EV 3 349 #define ESE_DZ_DRV_START_UP_EV 2 350 #define ESE_DZ_DRV_WAKE_UP_EV 1 351 #define ESF_DZ_DRV_SUB_DATA_DW0_LBN 0 352 #define ESF_DZ_DRV_SUB_DATA_DW0_WIDTH 32 353 #define ESF_DZ_DRV_SUB_DATA_DW1_LBN 32 354 #define ESF_DZ_DRV_SUB_DATA_DW1_WIDTH 24 355 #define ESF_DZ_DRV_SUB_DATA_LBN 0 356 #define ESF_DZ_DRV_SUB_DATA_WIDTH 56 357 #define ESF_DZ_DRV_EVQ_ID_LBN 0 358 #define ESF_DZ_DRV_EVQ_ID_WIDTH 14 359 #define ESF_DZ_DRV_TMR_ID_LBN 0 360 #define ESF_DZ_DRV_TMR_ID_WIDTH 14 361 362 363 /* ES_EVENT_ENTRY */ 364 #define ESF_DZ_EV_CODE_LBN 60 365 #define ESF_DZ_EV_CODE_WIDTH 4 366 #define ESE_DZ_EV_CODE_MCDI_EV 12 367 #define ESE_DZ_EV_CODE_DRIVER_EV 5 368 #define ESE_DZ_EV_CODE_TX_EV 2 369 #define ESE_DZ_EV_CODE_RX_EV 0 370 #define ESE_DZ_OTHER other 371 #define ESF_DZ_EV_DATA_DW0_LBN 0 372 #define ESF_DZ_EV_DATA_DW0_WIDTH 32 373 #define ESF_DZ_EV_DATA_DW1_LBN 32 374 #define ESF_DZ_EV_DATA_DW1_WIDTH 28 375 #define ESF_DZ_EV_DATA_LBN 0 376 #define ESF_DZ_EV_DATA_WIDTH 60 377 378 379 /* ES_MC_EVENT */ 380 #define ESF_DZ_MC_CODE_LBN 60 381 #define ESF_DZ_MC_CODE_WIDTH 4 382 #define ESF_DZ_MC_OVERRIDE_HOLDOFF_LBN 59 383 #define ESF_DZ_MC_OVERRIDE_HOLDOFF_WIDTH 1 384 #define ESF_DZ_MC_DROP_EVENT_LBN 58 385 #define ESF_DZ_MC_DROP_EVENT_WIDTH 1 386 #define ESF_DZ_MC_SOFT_DW0_LBN 0 387 #define ESF_DZ_MC_SOFT_DW0_WIDTH 32 388 #define ESF_DZ_MC_SOFT_DW1_LBN 32 389 #define ESF_DZ_MC_SOFT_DW1_WIDTH 26 390 #define ESF_DZ_MC_SOFT_LBN 0 391 #define ESF_DZ_MC_SOFT_WIDTH 58 392 393 394 /* ES_RX_EVENT */ 395 #define ESF_DZ_RX_CODE_LBN 60 396 #define ESF_DZ_RX_CODE_WIDTH 4 397 #define ESF_DZ_RX_OVERRIDE_HOLDOFF_LBN 59 398 #define ESF_DZ_RX_OVERRIDE_HOLDOFF_WIDTH 1 399 #define ESF_DZ_RX_DROP_EVENT_LBN 58 400 #define ESF_DZ_RX_DROP_EVENT_WIDTH 1 401 #define ESF_DD_RX_EV_RSVD2_LBN 54 402 #define ESF_DD_RX_EV_RSVD2_WIDTH 4 403 #define ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR_LBN 57 404 #define ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR_WIDTH 1 405 #define ESF_EZ_RX_IP_INNER_CHKSUM_ERR_LBN 56 406 #define ESF_EZ_RX_IP_INNER_CHKSUM_ERR_WIDTH 1 407 #define ESF_EZ_RX_EV_RSVD2_LBN 54 408 #define ESF_EZ_RX_EV_RSVD2_WIDTH 2 409 #define ESF_DZ_RX_EV_SOFT2_LBN 52 410 #define ESF_DZ_RX_EV_SOFT2_WIDTH 2 411 #define ESF_DZ_RX_DSC_PTR_LBITS_LBN 48 412 #define ESF_DZ_RX_DSC_PTR_LBITS_WIDTH 4 413 #define ESF_DE_RX_L4_CLASS_LBN 45 414 #define ESF_DE_RX_L4_CLASS_WIDTH 3 415 #define ESE_DE_L4_CLASS_RSVD7 7 416 #define ESE_DE_L4_CLASS_RSVD6 6 417 #define ESE_DE_L4_CLASS_RSVD5 5 418 #define ESE_DE_L4_CLASS_RSVD4 4 419 #define ESE_DE_L4_CLASS_RSVD3 3 420 #define ESE_DE_L4_CLASS_UDP 2 421 #define ESE_DE_L4_CLASS_TCP 1 422 #define ESE_DE_L4_CLASS_UNKNOWN 0 423 #define ESF_FZ_RX_FASTPD_INDCTR_LBN 47 424 #define ESF_FZ_RX_FASTPD_INDCTR_WIDTH 1 425 #define ESF_FZ_RX_L4_CLASS_LBN 45 426 #define ESF_FZ_RX_L4_CLASS_WIDTH 2 427 #define ESE_FZ_L4_CLASS_RSVD3 3 428 #define ESE_FZ_L4_CLASS_UDP 2 429 #define ESE_FZ_L4_CLASS_TCP 1 430 #define ESE_FZ_L4_CLASS_UNKNOWN 0 431 #define ESF_DZ_RX_L3_CLASS_LBN 42 432 #define ESF_DZ_RX_L3_CLASS_WIDTH 3 433 #define ESE_DZ_L3_CLASS_RSVD7 7 434 #define ESE_DZ_L3_CLASS_IP6_FRAG 6 435 #define ESE_DZ_L3_CLASS_ARP 5 436 #define ESE_DZ_L3_CLASS_IP4_FRAG 4 437 #define ESE_DZ_L3_CLASS_FCOE 3 438 #define ESE_DZ_L3_CLASS_IP6 2 439 #define ESE_DZ_L3_CLASS_IP4 1 440 #define ESE_DZ_L3_CLASS_UNKNOWN 0 441 #define ESF_DZ_RX_ETH_TAG_CLASS_LBN 39 442 #define ESF_DZ_RX_ETH_TAG_CLASS_WIDTH 3 443 #define ESE_DZ_ETH_TAG_CLASS_RSVD7 7 444 #define ESE_DZ_ETH_TAG_CLASS_RSVD6 6 445 #define ESE_DZ_ETH_TAG_CLASS_RSVD5 5 446 #define ESE_DZ_ETH_TAG_CLASS_RSVD4 4 447 #define ESE_DZ_ETH_TAG_CLASS_RSVD3 3 448 #define ESE_DZ_ETH_TAG_CLASS_VLAN2 2 449 #define ESE_DZ_ETH_TAG_CLASS_VLAN1 1 450 #define ESE_DZ_ETH_TAG_CLASS_NONE 0 451 #define ESF_DZ_RX_ETH_BASE_CLASS_LBN 36 452 #define ESF_DZ_RX_ETH_BASE_CLASS_WIDTH 3 453 #define ESE_DZ_ETH_BASE_CLASS_LLC_SNAP 2 454 #define ESE_DZ_ETH_BASE_CLASS_LLC 1 455 #define ESE_DZ_ETH_BASE_CLASS_ETH2 0 456 #define ESF_DZ_RX_MAC_CLASS_LBN 35 457 #define ESF_DZ_RX_MAC_CLASS_WIDTH 1 458 #define ESE_DZ_MAC_CLASS_MCAST 1 459 #define ESE_DZ_MAC_CLASS_UCAST 0 460 #define ESF_DD_RX_EV_SOFT1_LBN 32 461 #define ESF_DD_RX_EV_SOFT1_WIDTH 3 462 #define ESF_EZ_RX_EV_SOFT1_LBN 34 463 #define ESF_EZ_RX_EV_SOFT1_WIDTH 1 464 #define ESF_EZ_RX_ENCAP_HDR_LBN 32 465 #define ESF_EZ_RX_ENCAP_HDR_WIDTH 2 466 #define ESE_EZ_ENCAP_HDR_GRE 2 467 #define ESE_EZ_ENCAP_HDR_VXLAN 1 468 #define ESE_EZ_ENCAP_HDR_NONE 0 469 #define ESF_DD_RX_EV_RSVD1_LBN 30 470 #define ESF_DD_RX_EV_RSVD1_WIDTH 2 471 #define ESF_EZ_RX_EV_RSVD1_LBN 31 472 #define ESF_EZ_RX_EV_RSVD1_WIDTH 1 473 #define ESF_EZ_RX_ABORT_LBN 30 474 #define ESF_EZ_RX_ABORT_WIDTH 1 475 #define ESF_DZ_RX_ECC_ERR_LBN 29 476 #define ESF_DZ_RX_ECC_ERR_WIDTH 1 477 #define ESF_DZ_RX_CRC1_ERR_LBN 28 478 #define ESF_DZ_RX_CRC1_ERR_WIDTH 1 479 #define ESF_DZ_RX_CRC0_ERR_LBN 27 480 #define ESF_DZ_RX_CRC0_ERR_WIDTH 1 481 #define ESF_DZ_RX_TCPUDP_CKSUM_ERR_LBN 26 482 #define ESF_DZ_RX_TCPUDP_CKSUM_ERR_WIDTH 1 483 #define ESF_DZ_RX_IPCKSUM_ERR_LBN 25 484 #define ESF_DZ_RX_IPCKSUM_ERR_WIDTH 1 485 #define ESF_DZ_RX_ECRC_ERR_LBN 24 486 #define ESF_DZ_RX_ECRC_ERR_WIDTH 1 487 #define ESF_DZ_RX_QLABEL_LBN 16 488 #define ESF_DZ_RX_QLABEL_WIDTH 5 489 #define ESF_DZ_RX_PARSE_INCOMPLETE_LBN 15 490 #define ESF_DZ_RX_PARSE_INCOMPLETE_WIDTH 1 491 #define ESF_DZ_RX_CONT_LBN 14 492 #define ESF_DZ_RX_CONT_WIDTH 1 493 #define ESF_DZ_RX_BYTES_LBN 0 494 #define ESF_DZ_RX_BYTES_WIDTH 14 495 496 497 /* ES_RX_KER_DESC */ 498 #define ESF_DZ_RX_KER_RESERVED_LBN 62 499 #define ESF_DZ_RX_KER_RESERVED_WIDTH 2 500 #define ESF_DZ_RX_KER_BYTE_CNT_LBN 48 501 #define ESF_DZ_RX_KER_BYTE_CNT_WIDTH 14 502 #define ESF_DZ_RX_KER_BUF_ADDR_DW0_LBN 0 503 #define ESF_DZ_RX_KER_BUF_ADDR_DW0_WIDTH 32 504 #define ESF_DZ_RX_KER_BUF_ADDR_DW1_LBN 32 505 #define ESF_DZ_RX_KER_BUF_ADDR_DW1_WIDTH 16 506 #define ESF_DZ_RX_KER_BUF_ADDR_LBN 0 507 #define ESF_DZ_RX_KER_BUF_ADDR_WIDTH 48 508 509 510 /* ES_TX_CSUM_TSTAMP_DESC */ 511 #define ESF_DZ_TX_DESC_IS_OPT_LBN 63 512 #define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1 513 #define ESF_DZ_TX_OPTION_TYPE_LBN 60 514 #define ESF_DZ_TX_OPTION_TYPE_WIDTH 3 515 #define ESE_DZ_TX_OPTION_DESC_TSO 7 516 #define ESE_DZ_TX_OPTION_DESC_VLAN 6 517 #define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0 518 #define ESF_DZ_TX_OPTION_TS_AT_TXDP_LBN 8 519 #define ESF_DZ_TX_OPTION_TS_AT_TXDP_WIDTH 1 520 #define ESF_DZ_TX_OPTION_INNER_UDP_TCP_CSUM_LBN 7 521 #define ESF_DZ_TX_OPTION_INNER_UDP_TCP_CSUM_WIDTH 1 522 #define ESF_DZ_TX_OPTION_INNER_IP_CSUM_LBN 6 523 #define ESF_DZ_TX_OPTION_INNER_IP_CSUM_WIDTH 1 524 #define ESF_DZ_TX_TIMESTAMP_LBN 5 525 #define ESF_DZ_TX_TIMESTAMP_WIDTH 1 526 #define ESF_DZ_TX_OPTION_CRC_MODE_LBN 2 527 #define ESF_DZ_TX_OPTION_CRC_MODE_WIDTH 3 528 #define ESE_DZ_TX_OPTION_CRC_FCOIP_MPA 5 529 #define ESE_DZ_TX_OPTION_CRC_FCOIP_FCOE 4 530 #define ESE_DZ_TX_OPTION_CRC_ISCSI_HDR_AND_PYLD 3 531 #define ESE_DZ_TX_OPTION_CRC_ISCSI_HDR 2 532 #define ESE_DZ_TX_OPTION_CRC_FCOE 1 533 #define ESE_DZ_TX_OPTION_CRC_OFF 0 534 #define ESF_DZ_TX_OPTION_UDP_TCP_CSUM_LBN 1 535 #define ESF_DZ_TX_OPTION_UDP_TCP_CSUM_WIDTH 1 536 #define ESF_DZ_TX_OPTION_IP_CSUM_LBN 0 537 #define ESF_DZ_TX_OPTION_IP_CSUM_WIDTH 1 538 539 540 /* ES_TX_EVENT */ 541 #define ESF_DZ_TX_CODE_LBN 60 542 #define ESF_DZ_TX_CODE_WIDTH 4 543 #define ESF_DZ_TX_OVERRIDE_HOLDOFF_LBN 59 544 #define ESF_DZ_TX_OVERRIDE_HOLDOFF_WIDTH 1 545 #define ESF_DZ_TX_DROP_EVENT_LBN 58 546 #define ESF_DZ_TX_DROP_EVENT_WIDTH 1 547 #define ESF_DD_TX_EV_RSVD_LBN 48 548 #define ESF_DD_TX_EV_RSVD_WIDTH 10 549 #define ESF_EZ_TCP_UDP_INNER_CHKSUM_ERR_LBN 57 550 #define ESF_EZ_TCP_UDP_INNER_CHKSUM_ERR_WIDTH 1 551 #define ESF_EZ_IP_INNER_CHKSUM_ERR_LBN 56 552 #define ESF_EZ_IP_INNER_CHKSUM_ERR_WIDTH 1 553 #define ESF_EZ_TX_EV_RSVD_LBN 48 554 #define ESF_EZ_TX_EV_RSVD_WIDTH 8 555 #define ESF_DZ_TX_SOFT2_LBN 32 556 #define ESF_DZ_TX_SOFT2_WIDTH 16 557 #define ESF_DD_TX_SOFT1_LBN 24 558 #define ESF_DD_TX_SOFT1_WIDTH 8 559 #define ESF_EZ_TX_CAN_MERGE_LBN 31 560 #define ESF_EZ_TX_CAN_MERGE_WIDTH 1 561 #define ESF_EZ_TX_SOFT1_LBN 24 562 #define ESF_EZ_TX_SOFT1_WIDTH 7 563 #define ESF_DZ_TX_QLABEL_LBN 16 564 #define ESF_DZ_TX_QLABEL_WIDTH 5 565 #define ESF_DZ_TX_DESCR_INDX_LBN 0 566 #define ESF_DZ_TX_DESCR_INDX_WIDTH 16 567 568 569 /* ES_TX_KER_DESC */ 570 #define ESF_DZ_TX_KER_TYPE_LBN 63 571 #define ESF_DZ_TX_KER_TYPE_WIDTH 1 572 #define ESF_DZ_TX_KER_CONT_LBN 62 573 #define ESF_DZ_TX_KER_CONT_WIDTH 1 574 #define ESF_DZ_TX_KER_BYTE_CNT_LBN 48 575 #define ESF_DZ_TX_KER_BYTE_CNT_WIDTH 14 576 #define ESF_DZ_TX_KER_BUF_ADDR_DW0_LBN 0 577 #define ESF_DZ_TX_KER_BUF_ADDR_DW0_WIDTH 32 578 #define ESF_DZ_TX_KER_BUF_ADDR_DW1_LBN 32 579 #define ESF_DZ_TX_KER_BUF_ADDR_DW1_WIDTH 16 580 #define ESF_DZ_TX_KER_BUF_ADDR_LBN 0 581 #define ESF_DZ_TX_KER_BUF_ADDR_WIDTH 48 582 583 584 /* ES_TX_PIO_DESC */ 585 #define ESF_DZ_TX_PIO_TYPE_LBN 63 586 #define ESF_DZ_TX_PIO_TYPE_WIDTH 1 587 #define ESF_DZ_TX_PIO_OPT_LBN 60 588 #define ESF_DZ_TX_PIO_OPT_WIDTH 3 589 #define ESF_DZ_TX_PIO_CONT_LBN 59 590 #define ESF_DZ_TX_PIO_CONT_WIDTH 1 591 #define ESF_DZ_TX_PIO_BYTE_CNT_LBN 32 592 #define ESF_DZ_TX_PIO_BYTE_CNT_WIDTH 12 593 #define ESF_DZ_TX_PIO_BUF_ADDR_LBN 0 594 #define ESF_DZ_TX_PIO_BUF_ADDR_WIDTH 12 595 596 597 /* ES_TX_TSO_DESC */ 598 #define ESF_DZ_TX_DESC_IS_OPT_LBN 63 599 #define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1 600 #define ESF_DZ_TX_OPTION_TYPE_LBN 60 601 #define ESF_DZ_TX_OPTION_TYPE_WIDTH 3 602 #define ESE_DZ_TX_OPTION_DESC_TSO 7 603 #define ESE_DZ_TX_OPTION_DESC_VLAN 6 604 #define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0 605 #define ESF_DZ_TX_TSO_OPTION_TYPE_LBN 56 606 #define ESF_DZ_TX_TSO_OPTION_TYPE_WIDTH 4 607 #define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B 3 608 #define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A 2 609 #define ESE_DZ_TX_TSO_OPTION_DESC_ENCAP 1 610 #define ESE_DZ_TX_TSO_OPTION_DESC_NORMAL 0 611 #define ESF_DZ_TX_TSO_TCP_FLAGS_LBN 48 612 #define ESF_DZ_TX_TSO_TCP_FLAGS_WIDTH 8 613 #define ESF_DZ_TX_TSO_IP_ID_LBN 32 614 #define ESF_DZ_TX_TSO_IP_ID_WIDTH 16 615 #define ESF_DZ_TX_TSO_TCP_SEQNO_LBN 0 616 #define ESF_DZ_TX_TSO_TCP_SEQNO_WIDTH 32 617 618 619 /* ES_TX_TSO_V2_DESC_A */ 620 #define ESF_DZ_TX_DESC_IS_OPT_LBN 63 621 #define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1 622 #define ESF_DZ_TX_OPTION_TYPE_LBN 60 623 #define ESF_DZ_TX_OPTION_TYPE_WIDTH 3 624 #define ESE_DZ_TX_OPTION_DESC_TSO 7 625 #define ESE_DZ_TX_OPTION_DESC_VLAN 6 626 #define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0 627 #define ESF_DZ_TX_TSO_OPTION_TYPE_LBN 56 628 #define ESF_DZ_TX_TSO_OPTION_TYPE_WIDTH 4 629 #define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B 3 630 #define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A 2 631 #define ESE_DZ_TX_TSO_OPTION_DESC_ENCAP 1 632 #define ESE_DZ_TX_TSO_OPTION_DESC_NORMAL 0 633 #define ESF_DZ_TX_TSO_IP_ID_LBN 32 634 #define ESF_DZ_TX_TSO_IP_ID_WIDTH 16 635 #define ESF_DZ_TX_TSO_TCP_SEQNO_LBN 0 636 #define ESF_DZ_TX_TSO_TCP_SEQNO_WIDTH 32 637 638 639 /* ES_TX_TSO_V2_DESC_B */ 640 #define ESF_DZ_TX_DESC_IS_OPT_LBN 63 641 #define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1 642 #define ESF_DZ_TX_OPTION_TYPE_LBN 60 643 #define ESF_DZ_TX_OPTION_TYPE_WIDTH 3 644 #define ESE_DZ_TX_OPTION_DESC_TSO 7 645 #define ESE_DZ_TX_OPTION_DESC_VLAN 6 646 #define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0 647 #define ESF_DZ_TX_TSO_OPTION_TYPE_LBN 56 648 #define ESF_DZ_TX_TSO_OPTION_TYPE_WIDTH 4 649 #define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B 3 650 #define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A 2 651 #define ESE_DZ_TX_TSO_OPTION_DESC_ENCAP 1 652 #define ESE_DZ_TX_TSO_OPTION_DESC_NORMAL 0 653 #define ESF_DZ_TX_TSO_TCP_MSS_LBN 32 654 #define ESF_DZ_TX_TSO_TCP_MSS_WIDTH 16 655 #define ESF_DZ_TX_TSO_OUTER_IPID_LBN 0 656 #define ESF_DZ_TX_TSO_OUTER_IPID_WIDTH 16 657 658 659 /* ES_TX_VLAN_DESC */ 660 #define ESF_DZ_TX_DESC_IS_OPT_LBN 63 661 #define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1 662 #define ESF_DZ_TX_OPTION_TYPE_LBN 60 663 #define ESF_DZ_TX_OPTION_TYPE_WIDTH 3 664 #define ESE_DZ_TX_OPTION_DESC_TSO 7 665 #define ESE_DZ_TX_OPTION_DESC_VLAN 6 666 #define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0 667 #define ESF_DZ_TX_VLAN_OP_LBN 32 668 #define ESF_DZ_TX_VLAN_OP_WIDTH 2 669 #define ESF_DZ_TX_VLAN_TAG2_LBN 16 670 #define ESF_DZ_TX_VLAN_TAG2_WIDTH 16 671 #define ESF_DZ_TX_VLAN_TAG1_LBN 0 672 #define ESF_DZ_TX_VLAN_TAG1_WIDTH 16 673 674 675 /************************************************************************* 676 * NOTE: the comment line above marks the end of the autogenerated section 677 */ 678 679 /* 680 * The workaround for bug 35388 requires multiplexing writes through 681 * the ERF_DZ_TX_DESC_WPTR address. 682 * TX_DESC_UPD: 0ppppppppppp (bit 11 lost) 683 * EVQ_RPTR: 1000hhhhhhhh, 1001llllllll (split into high and low bits) 684 * EVQ_TMR: 11mmvvvvvvvv (bits 8:13 of value lost) 685 */ 686 #define ER_DD_EVQ_INDIRECT_OFST (ER_DZ_TX_DESC_UPD_REG_OFST + 2 * 4) 687 #define ER_DD_EVQ_INDIRECT_STEP ER_DZ_TX_DESC_UPD_REG_STEP 688 #define ERF_DD_EVQ_IND_RPTR_FLAGS_LBN 8 689 #define ERF_DD_EVQ_IND_RPTR_FLAGS_WIDTH 4 690 #define EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH 8 691 #define EFE_DD_EVQ_IND_RPTR_FLAGS_LOW 9 692 #define ERF_DD_EVQ_IND_RPTR_LBN 0 693 #define ERF_DD_EVQ_IND_RPTR_WIDTH 8 694 #define ERF_DD_EVQ_IND_TIMER_FLAGS_LBN 10 695 #define ERF_DD_EVQ_IND_TIMER_FLAGS_WIDTH 2 696 #define EFE_DD_EVQ_IND_TIMER_FLAGS 3 697 #define ERF_DD_EVQ_IND_TIMER_MODE_LBN 8 698 #define ERF_DD_EVQ_IND_TIMER_MODE_WIDTH 2 699 #define ERF_DD_EVQ_IND_TIMER_VAL_LBN 0 700 #define ERF_DD_EVQ_IND_TIMER_VAL_WIDTH 8 701 702 /* Packed stream magic doorbell command */ 703 #define ERF_DZ_RX_DESC_MAGIC_DOORBELL_LBN 11 704 #define ERF_DZ_RX_DESC_MAGIC_DOORBELL_WIDTH 1 705 706 #define ERF_DZ_RX_DESC_MAGIC_CMD_LBN 8 707 #define ERF_DZ_RX_DESC_MAGIC_CMD_WIDTH 3 708 #define ERE_DZ_RX_DESC_MAGIC_CMD_PS_CREDITS 0 709 710 #define ERF_DZ_RX_DESC_MAGIC_DATA_LBN 0 711 #define ERF_DZ_RX_DESC_MAGIC_DATA_WIDTH 8 712 713 /* Packed stream RX packet prefix */ 714 #define ES_DZ_PS_RX_PREFIX_TSTAMP_LBN 0 715 #define ES_DZ_PS_RX_PREFIX_TSTAMP_WIDTH 32 716 #define ES_DZ_PS_RX_PREFIX_CAP_LEN_LBN 32 717 #define ES_DZ_PS_RX_PREFIX_CAP_LEN_WIDTH 16 718 #define ES_DZ_PS_RX_PREFIX_ORIG_LEN_LBN 48 719 #define ES_DZ_PS_RX_PREFIX_ORIG_LEN_WIDTH 16 720 721 /* 722 * An extra flag for the packed stream mode, 723 * signalling the start of a new buffer 724 */ 725 #define ESF_DZ_RX_EV_ROTATE_LBN 53 726 #define ESF_DZ_RX_EV_ROTATE_WIDTH 1 727 728 #ifdef __cplusplus 729 } 730 #endif 731 732 #endif /* _SYS_EFX_EF10_REGS_H */ 733