1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2007-2016 Solarflare Communications Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 18 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 26 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * The views and conclusions contained in the software and documentation are 29 * those of the authors and should not be interpreted as representing official 30 * policies, either expressed or implied, of the FreeBSD Project. 31 * 32 * $FreeBSD$ 33 */ 34 35 #ifndef _SYS_EFX_EF10_REGS_H 36 #define _SYS_EFX_EF10_REGS_H 37 38 #ifdef __cplusplus 39 extern "C" { 40 #endif 41 42 /************************************************************************** 43 * NOTE: the line below marks the start of the autogenerated section 44 * EF10 registers and descriptors 45 * 46 ************************************************************************** 47 */ 48 49 /* 50 * BIU_HW_REV_ID_REG(32bit): 51 * 52 */ 53 54 #define ER_DZ_BIU_HW_REV_ID_REG_OFST 0x00000000 55 /* hunta0,medforda0,medford2a0=pf_dbell_bar */ 56 #define ER_DZ_BIU_HW_REV_ID_REG_RESET 0xeb14face 57 58 59 #define ERF_DZ_HW_REV_ID_LBN 0 60 #define ERF_DZ_HW_REV_ID_WIDTH 32 61 62 63 /* 64 * BIU_MC_SFT_STATUS_REG(32bit): 65 * 66 */ 67 68 #define ER_DZ_BIU_MC_SFT_STATUS_REG_OFST 0x00000010 69 /* hunta0,medforda0,medford2a0=pf_dbell_bar */ 70 #define ER_DZ_BIU_MC_SFT_STATUS_REG_STEP 4 71 #define ER_DZ_BIU_MC_SFT_STATUS_REG_ROWS 8 72 #define ER_DZ_BIU_MC_SFT_STATUS_REG_RESET 0x1111face 73 74 75 #define ERF_DZ_MC_SFT_STATUS_LBN 0 76 #define ERF_DZ_MC_SFT_STATUS_WIDTH 32 77 78 79 /* 80 * BIU_INT_ISR_REG(32bit): 81 * 82 */ 83 84 #define ER_DZ_BIU_INT_ISR_REG_OFST 0x00000090 85 /* hunta0,medforda0,medford2a0=pf_dbell_bar */ 86 #define ER_DZ_BIU_INT_ISR_REG_RESET 0x0 87 88 89 #define ERF_DZ_ISR_REG_LBN 0 90 #define ERF_DZ_ISR_REG_WIDTH 32 91 92 93 /* 94 * MC_DB_LWRD_REG(32bit): 95 * 96 */ 97 98 #define ER_DZ_MC_DB_LWRD_REG_OFST 0x00000200 99 /* hunta0,medforda0,medford2a0=pf_dbell_bar */ 100 #define ER_DZ_MC_DB_LWRD_REG_RESET 0x0 101 102 103 #define ERF_DZ_MC_DOORBELL_L_LBN 0 104 #define ERF_DZ_MC_DOORBELL_L_WIDTH 32 105 106 107 /* 108 * MC_DB_HWRD_REG(32bit): 109 * 110 */ 111 112 #define ER_DZ_MC_DB_HWRD_REG_OFST 0x00000204 113 /* hunta0,medforda0,medford2a0=pf_dbell_bar */ 114 #define ER_DZ_MC_DB_HWRD_REG_RESET 0x0 115 116 117 #define ERF_DZ_MC_DOORBELL_H_LBN 0 118 #define ERF_DZ_MC_DOORBELL_H_WIDTH 32 119 120 121 /* 122 * EVQ_RPTR_REG(32bit): 123 * 124 */ 125 126 #define ER_DZ_EVQ_RPTR_REG_OFST 0x00000400 127 /* hunta0,medforda0,medford2a0=pf_dbell_bar */ 128 #define ER_DZ_EVQ_RPTR_REG_STEP 8192 129 #define ER_DZ_EVQ_RPTR_REG_ROWS 2048 130 #define ER_DZ_EVQ_RPTR_REG_RESET 0x0 131 132 133 #define ERF_DZ_EVQ_RPTR_VLD_LBN 15 134 #define ERF_DZ_EVQ_RPTR_VLD_WIDTH 1 135 #define ERF_DZ_EVQ_RPTR_LBN 0 136 #define ERF_DZ_EVQ_RPTR_WIDTH 15 137 138 139 /* 140 * EVQ_RPTR_REG_64K(32bit): 141 * 142 */ 143 144 #define ER_FZ_EVQ_RPTR_REG_64K_OFST 0x00000400 145 /* medford2a0=pf_dbell_bar */ 146 #define ER_FZ_EVQ_RPTR_REG_64K_STEP 65536 147 #define ER_FZ_EVQ_RPTR_REG_64K_ROWS 2048 148 #define ER_FZ_EVQ_RPTR_REG_64K_RESET 0x0 149 150 151 #define ERF_FZ_EVQ_RPTR_VLD_LBN 15 152 #define ERF_FZ_EVQ_RPTR_VLD_WIDTH 1 153 #define ERF_FZ_EVQ_RPTR_LBN 0 154 #define ERF_FZ_EVQ_RPTR_WIDTH 15 155 156 157 /* 158 * EVQ_RPTR_REG_16K(32bit): 159 * 160 */ 161 162 #define ER_FZ_EVQ_RPTR_REG_16K_OFST 0x00000400 163 /* medford2a0=pf_dbell_bar */ 164 #define ER_FZ_EVQ_RPTR_REG_16K_STEP 16384 165 #define ER_FZ_EVQ_RPTR_REG_16K_ROWS 2048 166 #define ER_FZ_EVQ_RPTR_REG_16K_RESET 0x0 167 168 169 /* defined as ERF_FZ_EVQ_RPTR_VLD_LBN 15; */ 170 /* defined as ERF_FZ_EVQ_RPTR_VLD_WIDTH 1 */ 171 /* defined as ERF_FZ_EVQ_RPTR_LBN 0; */ 172 /* defined as ERF_FZ_EVQ_RPTR_WIDTH 15 */ 173 174 175 /* 176 * EVQ_TMR_REG_64K(32bit): 177 * 178 */ 179 180 #define ER_FZ_EVQ_TMR_REG_64K_OFST 0x00000420 181 /* medford2a0=pf_dbell_bar */ 182 #define ER_FZ_EVQ_TMR_REG_64K_STEP 65536 183 #define ER_FZ_EVQ_TMR_REG_64K_ROWS 2048 184 #define ER_FZ_EVQ_TMR_REG_64K_RESET 0x0 185 186 187 #define ERF_FZ_TC_TMR_REL_VAL_LBN 16 188 #define ERF_FZ_TC_TMR_REL_VAL_WIDTH 14 189 #define ERF_FZ_TC_TIMER_MODE_LBN 14 190 #define ERF_FZ_TC_TIMER_MODE_WIDTH 2 191 #define ERF_FZ_TC_TIMER_VAL_LBN 0 192 #define ERF_FZ_TC_TIMER_VAL_WIDTH 14 193 194 195 /* 196 * EVQ_TMR_REG_16K(32bit): 197 * 198 */ 199 200 #define ER_FZ_EVQ_TMR_REG_16K_OFST 0x00000420 201 /* medford2a0=pf_dbell_bar */ 202 #define ER_FZ_EVQ_TMR_REG_16K_STEP 16384 203 #define ER_FZ_EVQ_TMR_REG_16K_ROWS 2048 204 #define ER_FZ_EVQ_TMR_REG_16K_RESET 0x0 205 206 207 /* defined as ERF_FZ_TC_TMR_REL_VAL_LBN 16; */ 208 /* defined as ERF_FZ_TC_TMR_REL_VAL_WIDTH 14 */ 209 /* defined as ERF_FZ_TC_TIMER_MODE_LBN 14; */ 210 /* defined as ERF_FZ_TC_TIMER_MODE_WIDTH 2 */ 211 /* defined as ERF_FZ_TC_TIMER_VAL_LBN 0; */ 212 /* defined as ERF_FZ_TC_TIMER_VAL_WIDTH 14 */ 213 214 215 /* 216 * EVQ_TMR_REG(32bit): 217 * 218 */ 219 220 #define ER_DZ_EVQ_TMR_REG_OFST 0x00000420 221 /* hunta0,medforda0,medford2a0=pf_dbell_bar */ 222 #define ER_DZ_EVQ_TMR_REG_STEP 8192 223 #define ER_DZ_EVQ_TMR_REG_ROWS 2048 224 #define ER_DZ_EVQ_TMR_REG_RESET 0x0 225 226 227 /* defined as ERF_FZ_TC_TMR_REL_VAL_LBN 16; */ 228 /* defined as ERF_FZ_TC_TMR_REL_VAL_WIDTH 14 */ 229 #define ERF_DZ_TC_TIMER_MODE_LBN 14 230 #define ERF_DZ_TC_TIMER_MODE_WIDTH 2 231 #define ERF_DZ_TC_TIMER_VAL_LBN 0 232 #define ERF_DZ_TC_TIMER_VAL_WIDTH 14 233 234 235 /* 236 * RX_DESC_UPD_REG_16K(32bit): 237 * 238 */ 239 240 #define ER_FZ_RX_DESC_UPD_REG_16K_OFST 0x00000830 241 /* medford2a0=pf_dbell_bar */ 242 #define ER_FZ_RX_DESC_UPD_REG_16K_STEP 16384 243 #define ER_FZ_RX_DESC_UPD_REG_16K_ROWS 2048 244 #define ER_FZ_RX_DESC_UPD_REG_16K_RESET 0x0 245 246 247 #define ERF_FZ_RX_DESC_WPTR_LBN 0 248 #define ERF_FZ_RX_DESC_WPTR_WIDTH 12 249 250 251 /* 252 * RX_DESC_UPD_REG(32bit): 253 * 254 */ 255 256 #define ER_DZ_RX_DESC_UPD_REG_OFST 0x00000830 257 /* hunta0,medforda0,medford2a0=pf_dbell_bar */ 258 #define ER_DZ_RX_DESC_UPD_REG_STEP 8192 259 #define ER_DZ_RX_DESC_UPD_REG_ROWS 2048 260 #define ER_DZ_RX_DESC_UPD_REG_RESET 0x0 261 262 263 #define ERF_DZ_RX_DESC_WPTR_LBN 0 264 #define ERF_DZ_RX_DESC_WPTR_WIDTH 12 265 266 267 /* 268 * RX_DESC_UPD_REG_64K(32bit): 269 * 270 */ 271 272 #define ER_FZ_RX_DESC_UPD_REG_64K_OFST 0x00000830 273 /* medford2a0=pf_dbell_bar */ 274 #define ER_FZ_RX_DESC_UPD_REG_64K_STEP 65536 275 #define ER_FZ_RX_DESC_UPD_REG_64K_ROWS 2048 276 #define ER_FZ_RX_DESC_UPD_REG_64K_RESET 0x0 277 278 279 /* defined as ERF_FZ_RX_DESC_WPTR_LBN 0; */ 280 /* defined as ERF_FZ_RX_DESC_WPTR_WIDTH 12 */ 281 282 283 /* 284 * TX_DESC_UPD_REG_64K(96bit): 285 * 286 */ 287 288 #define ER_FZ_TX_DESC_UPD_REG_64K_OFST 0x00000a10 289 /* medford2a0=pf_dbell_bar */ 290 #define ER_FZ_TX_DESC_UPD_REG_64K_STEP 65536 291 #define ER_FZ_TX_DESC_UPD_REG_64K_ROWS 2048 292 #define ER_FZ_TX_DESC_UPD_REG_64K_RESET 0x0 293 294 295 #define ERF_FZ_RSVD_LBN 76 296 #define ERF_FZ_RSVD_WIDTH 20 297 #define ERF_FZ_TX_DESC_WPTR_LBN 64 298 #define ERF_FZ_TX_DESC_WPTR_WIDTH 12 299 #define ERF_FZ_TX_DESC_HWORD_LBN 32 300 #define ERF_FZ_TX_DESC_HWORD_WIDTH 32 301 #define ERF_FZ_TX_DESC_LWORD_LBN 0 302 #define ERF_FZ_TX_DESC_LWORD_WIDTH 32 303 304 305 /* 306 * TX_DESC_UPD_REG_16K(96bit): 307 * 308 */ 309 310 #define ER_FZ_TX_DESC_UPD_REG_16K_OFST 0x00000a10 311 /* medford2a0=pf_dbell_bar */ 312 #define ER_FZ_TX_DESC_UPD_REG_16K_STEP 16384 313 #define ER_FZ_TX_DESC_UPD_REG_16K_ROWS 2048 314 #define ER_FZ_TX_DESC_UPD_REG_16K_RESET 0x0 315 316 317 /* defined as ERF_FZ_RSVD_LBN 76; */ 318 /* defined as ERF_FZ_RSVD_WIDTH 20 */ 319 /* defined as ERF_FZ_TX_DESC_WPTR_LBN 64; */ 320 /* defined as ERF_FZ_TX_DESC_WPTR_WIDTH 12 */ 321 /* defined as ERF_FZ_TX_DESC_HWORD_LBN 32; */ 322 /* defined as ERF_FZ_TX_DESC_HWORD_WIDTH 32 */ 323 /* defined as ERF_FZ_TX_DESC_LWORD_LBN 0; */ 324 /* defined as ERF_FZ_TX_DESC_LWORD_WIDTH 32 */ 325 326 327 /* 328 * TX_DESC_UPD_REG(96bit): 329 * 330 */ 331 332 #define ER_DZ_TX_DESC_UPD_REG_OFST 0x00000a10 333 /* hunta0,medforda0,medford2a0=pf_dbell_bar */ 334 #define ER_DZ_TX_DESC_UPD_REG_STEP 8192 335 #define ER_DZ_TX_DESC_UPD_REG_ROWS 2048 336 #define ER_DZ_TX_DESC_UPD_REG_RESET 0x0 337 338 339 #define ERF_DZ_RSVD_LBN 76 340 #define ERF_DZ_RSVD_WIDTH 20 341 #define ERF_DZ_TX_DESC_WPTR_LBN 64 342 #define ERF_DZ_TX_DESC_WPTR_WIDTH 12 343 #define ERF_DZ_TX_DESC_HWORD_LBN 32 344 #define ERF_DZ_TX_DESC_HWORD_WIDTH 32 345 #define ERF_DZ_TX_DESC_LWORD_LBN 0 346 #define ERF_DZ_TX_DESC_LWORD_WIDTH 32 347 348 349 /* ES_DRIVER_EV */ 350 #define ESF_DZ_DRV_CODE_LBN 60 351 #define ESF_DZ_DRV_CODE_WIDTH 4 352 #define ESF_DZ_DRV_SUB_CODE_LBN 56 353 #define ESF_DZ_DRV_SUB_CODE_WIDTH 4 354 #define ESE_DZ_DRV_TIMER_EV 3 355 #define ESE_DZ_DRV_START_UP_EV 2 356 #define ESE_DZ_DRV_WAKE_UP_EV 1 357 #define ESF_DZ_DRV_SUB_DATA_DW0_LBN 0 358 #define ESF_DZ_DRV_SUB_DATA_DW0_WIDTH 32 359 #define ESF_DZ_DRV_SUB_DATA_DW1_LBN 32 360 #define ESF_DZ_DRV_SUB_DATA_DW1_WIDTH 24 361 #define ESF_DZ_DRV_SUB_DATA_LBN 0 362 #define ESF_DZ_DRV_SUB_DATA_WIDTH 56 363 #define ESF_DZ_DRV_EVQ_ID_LBN 0 364 #define ESF_DZ_DRV_EVQ_ID_WIDTH 14 365 #define ESF_DZ_DRV_TMR_ID_LBN 0 366 #define ESF_DZ_DRV_TMR_ID_WIDTH 14 367 368 369 /* ES_EVENT_ENTRY */ 370 #define ESF_DZ_EV_CODE_LBN 60 371 #define ESF_DZ_EV_CODE_WIDTH 4 372 #define ESE_DZ_EV_CODE_MCDI_EV 12 373 #define ESE_DZ_EV_CODE_DRIVER_EV 5 374 #define ESE_DZ_EV_CODE_TX_EV 2 375 #define ESE_DZ_EV_CODE_RX_EV 0 376 #define ESE_DZ_OTHER other 377 #define ESF_DZ_EV_DATA_DW0_LBN 0 378 #define ESF_DZ_EV_DATA_DW0_WIDTH 32 379 #define ESF_DZ_EV_DATA_DW1_LBN 32 380 #define ESF_DZ_EV_DATA_DW1_WIDTH 28 381 #define ESF_DZ_EV_DATA_LBN 0 382 #define ESF_DZ_EV_DATA_WIDTH 60 383 384 385 /* ES_MC_EVENT */ 386 #define ESF_DZ_MC_CODE_LBN 60 387 #define ESF_DZ_MC_CODE_WIDTH 4 388 #define ESF_DZ_MC_OVERRIDE_HOLDOFF_LBN 59 389 #define ESF_DZ_MC_OVERRIDE_HOLDOFF_WIDTH 1 390 #define ESF_DZ_MC_DROP_EVENT_LBN 58 391 #define ESF_DZ_MC_DROP_EVENT_WIDTH 1 392 #define ESF_DZ_MC_SOFT_DW0_LBN 0 393 #define ESF_DZ_MC_SOFT_DW0_WIDTH 32 394 #define ESF_DZ_MC_SOFT_DW1_LBN 32 395 #define ESF_DZ_MC_SOFT_DW1_WIDTH 26 396 #define ESF_DZ_MC_SOFT_LBN 0 397 #define ESF_DZ_MC_SOFT_WIDTH 58 398 399 400 /* ES_RX_EVENT */ 401 #define ESF_DZ_RX_CODE_LBN 60 402 #define ESF_DZ_RX_CODE_WIDTH 4 403 #define ESF_DZ_RX_OVERRIDE_HOLDOFF_LBN 59 404 #define ESF_DZ_RX_OVERRIDE_HOLDOFF_WIDTH 1 405 #define ESF_DZ_RX_DROP_EVENT_LBN 58 406 #define ESF_DZ_RX_DROP_EVENT_WIDTH 1 407 #define ESF_DD_RX_EV_RSVD2_LBN 54 408 #define ESF_DD_RX_EV_RSVD2_WIDTH 4 409 #define ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR_LBN 57 410 #define ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR_WIDTH 1 411 #define ESF_EZ_RX_IP_INNER_CHKSUM_ERR_LBN 56 412 #define ESF_EZ_RX_IP_INNER_CHKSUM_ERR_WIDTH 1 413 #define ESF_EZ_RX_EV_RSVD2_LBN 54 414 #define ESF_EZ_RX_EV_RSVD2_WIDTH 2 415 #define ESF_DZ_RX_EV_SOFT2_LBN 52 416 #define ESF_DZ_RX_EV_SOFT2_WIDTH 2 417 #define ESF_DZ_RX_DSC_PTR_LBITS_LBN 48 418 #define ESF_DZ_RX_DSC_PTR_LBITS_WIDTH 4 419 #define ESF_DE_RX_L4_CLASS_LBN 45 420 #define ESF_DE_RX_L4_CLASS_WIDTH 3 421 #define ESE_DE_L4_CLASS_RSVD7 7 422 #define ESE_DE_L4_CLASS_RSVD6 6 423 #define ESE_DE_L4_CLASS_RSVD5 5 424 #define ESE_DE_L4_CLASS_RSVD4 4 425 #define ESE_DE_L4_CLASS_RSVD3 3 426 #define ESE_DE_L4_CLASS_UDP 2 427 #define ESE_DE_L4_CLASS_TCP 1 428 #define ESE_DE_L4_CLASS_UNKNOWN 0 429 #define ESF_FZ_RX_FASTPD_INDCTR_LBN 47 430 #define ESF_FZ_RX_FASTPD_INDCTR_WIDTH 1 431 #define ESF_FZ_RX_L4_CLASS_LBN 45 432 #define ESF_FZ_RX_L4_CLASS_WIDTH 2 433 #define ESE_FZ_L4_CLASS_RSVD3 3 434 #define ESE_FZ_L4_CLASS_UDP 2 435 #define ESE_FZ_L4_CLASS_TCP 1 436 #define ESE_FZ_L4_CLASS_UNKNOWN 0 437 #define ESF_DZ_RX_L3_CLASS_LBN 42 438 #define ESF_DZ_RX_L3_CLASS_WIDTH 3 439 #define ESE_DZ_L3_CLASS_RSVD7 7 440 #define ESE_DZ_L3_CLASS_IP6_FRAG 6 441 #define ESE_DZ_L3_CLASS_ARP 5 442 #define ESE_DZ_L3_CLASS_IP4_FRAG 4 443 #define ESE_DZ_L3_CLASS_FCOE 3 444 #define ESE_DZ_L3_CLASS_IP6 2 445 #define ESE_DZ_L3_CLASS_IP4 1 446 #define ESE_DZ_L3_CLASS_UNKNOWN 0 447 #define ESF_DZ_RX_ETH_TAG_CLASS_LBN 39 448 #define ESF_DZ_RX_ETH_TAG_CLASS_WIDTH 3 449 #define ESE_DZ_ETH_TAG_CLASS_RSVD7 7 450 #define ESE_DZ_ETH_TAG_CLASS_RSVD6 6 451 #define ESE_DZ_ETH_TAG_CLASS_RSVD5 5 452 #define ESE_DZ_ETH_TAG_CLASS_RSVD4 4 453 #define ESE_DZ_ETH_TAG_CLASS_RSVD3 3 454 #define ESE_DZ_ETH_TAG_CLASS_VLAN2 2 455 #define ESE_DZ_ETH_TAG_CLASS_VLAN1 1 456 #define ESE_DZ_ETH_TAG_CLASS_NONE 0 457 #define ESF_DZ_RX_ETH_BASE_CLASS_LBN 36 458 #define ESF_DZ_RX_ETH_BASE_CLASS_WIDTH 3 459 #define ESE_DZ_ETH_BASE_CLASS_LLC_SNAP 2 460 #define ESE_DZ_ETH_BASE_CLASS_LLC 1 461 #define ESE_DZ_ETH_BASE_CLASS_ETH2 0 462 #define ESF_DZ_RX_MAC_CLASS_LBN 35 463 #define ESF_DZ_RX_MAC_CLASS_WIDTH 1 464 #define ESE_DZ_MAC_CLASS_MCAST 1 465 #define ESE_DZ_MAC_CLASS_UCAST 0 466 #define ESF_DD_RX_EV_SOFT1_LBN 32 467 #define ESF_DD_RX_EV_SOFT1_WIDTH 3 468 #define ESF_EZ_RX_EV_SOFT1_LBN 34 469 #define ESF_EZ_RX_EV_SOFT1_WIDTH 1 470 #define ESF_EZ_RX_ENCAP_HDR_LBN 32 471 #define ESF_EZ_RX_ENCAP_HDR_WIDTH 2 472 #define ESE_EZ_ENCAP_HDR_GRE 2 473 #define ESE_EZ_ENCAP_HDR_VXLAN 1 474 #define ESE_EZ_ENCAP_HDR_NONE 0 475 #define ESF_DD_RX_EV_RSVD1_LBN 30 476 #define ESF_DD_RX_EV_RSVD1_WIDTH 2 477 #define ESF_EZ_RX_EV_RSVD1_LBN 31 478 #define ESF_EZ_RX_EV_RSVD1_WIDTH 1 479 #define ESF_EZ_RX_ABORT_LBN 30 480 #define ESF_EZ_RX_ABORT_WIDTH 1 481 #define ESF_DZ_RX_ECC_ERR_LBN 29 482 #define ESF_DZ_RX_ECC_ERR_WIDTH 1 483 #define ESF_DZ_RX_TRUNC_ERR_LBN 29 484 #define ESF_DZ_RX_TRUNC_ERR_WIDTH 1 485 #define ESF_DZ_RX_CRC1_ERR_LBN 28 486 #define ESF_DZ_RX_CRC1_ERR_WIDTH 1 487 #define ESF_DZ_RX_CRC0_ERR_LBN 27 488 #define ESF_DZ_RX_CRC0_ERR_WIDTH 1 489 #define ESF_DZ_RX_TCPUDP_CKSUM_ERR_LBN 26 490 #define ESF_DZ_RX_TCPUDP_CKSUM_ERR_WIDTH 1 491 #define ESF_DZ_RX_IPCKSUM_ERR_LBN 25 492 #define ESF_DZ_RX_IPCKSUM_ERR_WIDTH 1 493 #define ESF_DZ_RX_ECRC_ERR_LBN 24 494 #define ESF_DZ_RX_ECRC_ERR_WIDTH 1 495 #define ESF_DZ_RX_QLABEL_LBN 16 496 #define ESF_DZ_RX_QLABEL_WIDTH 5 497 #define ESF_DZ_RX_PARSE_INCOMPLETE_LBN 15 498 #define ESF_DZ_RX_PARSE_INCOMPLETE_WIDTH 1 499 #define ESF_DZ_RX_CONT_LBN 14 500 #define ESF_DZ_RX_CONT_WIDTH 1 501 #define ESF_DZ_RX_BYTES_LBN 0 502 #define ESF_DZ_RX_BYTES_WIDTH 14 503 504 505 /* ES_RX_KER_DESC */ 506 #define ESF_DZ_RX_KER_RESERVED_LBN 62 507 #define ESF_DZ_RX_KER_RESERVED_WIDTH 2 508 #define ESF_DZ_RX_KER_BYTE_CNT_LBN 48 509 #define ESF_DZ_RX_KER_BYTE_CNT_WIDTH 14 510 #define ESF_DZ_RX_KER_BUF_ADDR_DW0_LBN 0 511 #define ESF_DZ_RX_KER_BUF_ADDR_DW0_WIDTH 32 512 #define ESF_DZ_RX_KER_BUF_ADDR_DW1_LBN 32 513 #define ESF_DZ_RX_KER_BUF_ADDR_DW1_WIDTH 16 514 #define ESF_DZ_RX_KER_BUF_ADDR_LBN 0 515 #define ESF_DZ_RX_KER_BUF_ADDR_WIDTH 48 516 517 518 /* ES_TX_CSUM_TSTAMP_DESC */ 519 #define ESF_DZ_TX_DESC_IS_OPT_LBN 63 520 #define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1 521 #define ESF_DZ_TX_OPTION_TYPE_LBN 60 522 #define ESF_DZ_TX_OPTION_TYPE_WIDTH 3 523 #define ESE_DZ_TX_OPTION_DESC_TSO 7 524 #define ESE_DZ_TX_OPTION_DESC_VLAN 6 525 #define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0 526 #define ESF_DZ_TX_OPTION_TS_AT_TXDP_LBN 8 527 #define ESF_DZ_TX_OPTION_TS_AT_TXDP_WIDTH 1 528 #define ESF_DZ_TX_OPTION_INNER_UDP_TCP_CSUM_LBN 7 529 #define ESF_DZ_TX_OPTION_INNER_UDP_TCP_CSUM_WIDTH 1 530 #define ESF_DZ_TX_OPTION_INNER_IP_CSUM_LBN 6 531 #define ESF_DZ_TX_OPTION_INNER_IP_CSUM_WIDTH 1 532 #define ESF_DZ_TX_TIMESTAMP_LBN 5 533 #define ESF_DZ_TX_TIMESTAMP_WIDTH 1 534 #define ESF_DZ_TX_OPTION_CRC_MODE_LBN 2 535 #define ESF_DZ_TX_OPTION_CRC_MODE_WIDTH 3 536 #define ESE_DZ_TX_OPTION_CRC_FCOIP_MPA 5 537 #define ESE_DZ_TX_OPTION_CRC_FCOIP_FCOE 4 538 #define ESE_DZ_TX_OPTION_CRC_ISCSI_HDR_AND_PYLD 3 539 #define ESE_DZ_TX_OPTION_CRC_ISCSI_HDR 2 540 #define ESE_DZ_TX_OPTION_CRC_FCOE 1 541 #define ESE_DZ_TX_OPTION_CRC_OFF 0 542 #define ESF_DZ_TX_OPTION_UDP_TCP_CSUM_LBN 1 543 #define ESF_DZ_TX_OPTION_UDP_TCP_CSUM_WIDTH 1 544 #define ESF_DZ_TX_OPTION_IP_CSUM_LBN 0 545 #define ESF_DZ_TX_OPTION_IP_CSUM_WIDTH 1 546 547 548 /* ES_TX_EVENT */ 549 #define ESF_DZ_TX_CODE_LBN 60 550 #define ESF_DZ_TX_CODE_WIDTH 4 551 #define ESF_DZ_TX_OVERRIDE_HOLDOFF_LBN 59 552 #define ESF_DZ_TX_OVERRIDE_HOLDOFF_WIDTH 1 553 #define ESF_DZ_TX_DROP_EVENT_LBN 58 554 #define ESF_DZ_TX_DROP_EVENT_WIDTH 1 555 #define ESF_DD_TX_EV_RSVD_LBN 48 556 #define ESF_DD_TX_EV_RSVD_WIDTH 10 557 #define ESF_EZ_TCP_UDP_INNER_CHKSUM_ERR_LBN 57 558 #define ESF_EZ_TCP_UDP_INNER_CHKSUM_ERR_WIDTH 1 559 #define ESF_EZ_IP_INNER_CHKSUM_ERR_LBN 56 560 #define ESF_EZ_IP_INNER_CHKSUM_ERR_WIDTH 1 561 #define ESF_EZ_TX_EV_RSVD_LBN 48 562 #define ESF_EZ_TX_EV_RSVD_WIDTH 8 563 #define ESF_DZ_TX_SOFT2_LBN 32 564 #define ESF_DZ_TX_SOFT2_WIDTH 16 565 #define ESF_DD_TX_SOFT1_LBN 24 566 #define ESF_DD_TX_SOFT1_WIDTH 8 567 #define ESF_EZ_TX_CAN_MERGE_LBN 31 568 #define ESF_EZ_TX_CAN_MERGE_WIDTH 1 569 #define ESF_EZ_TX_SOFT1_LBN 24 570 #define ESF_EZ_TX_SOFT1_WIDTH 7 571 #define ESF_DZ_TX_QLABEL_LBN 16 572 #define ESF_DZ_TX_QLABEL_WIDTH 5 573 #define ESF_DZ_TX_DESCR_INDX_LBN 0 574 #define ESF_DZ_TX_DESCR_INDX_WIDTH 16 575 576 577 /* ES_TX_KER_DESC */ 578 #define ESF_DZ_TX_KER_TYPE_LBN 63 579 #define ESF_DZ_TX_KER_TYPE_WIDTH 1 580 #define ESF_DZ_TX_KER_CONT_LBN 62 581 #define ESF_DZ_TX_KER_CONT_WIDTH 1 582 #define ESF_DZ_TX_KER_BYTE_CNT_LBN 48 583 #define ESF_DZ_TX_KER_BYTE_CNT_WIDTH 14 584 #define ESF_DZ_TX_KER_BUF_ADDR_DW0_LBN 0 585 #define ESF_DZ_TX_KER_BUF_ADDR_DW0_WIDTH 32 586 #define ESF_DZ_TX_KER_BUF_ADDR_DW1_LBN 32 587 #define ESF_DZ_TX_KER_BUF_ADDR_DW1_WIDTH 16 588 #define ESF_DZ_TX_KER_BUF_ADDR_LBN 0 589 #define ESF_DZ_TX_KER_BUF_ADDR_WIDTH 48 590 591 592 /* ES_TX_PIO_DESC */ 593 #define ESF_DZ_TX_PIO_TYPE_LBN 63 594 #define ESF_DZ_TX_PIO_TYPE_WIDTH 1 595 #define ESF_DZ_TX_PIO_OPT_LBN 60 596 #define ESF_DZ_TX_PIO_OPT_WIDTH 3 597 #define ESF_DZ_TX_PIO_CONT_LBN 59 598 #define ESF_DZ_TX_PIO_CONT_WIDTH 1 599 #define ESF_DZ_TX_PIO_BYTE_CNT_LBN 32 600 #define ESF_DZ_TX_PIO_BYTE_CNT_WIDTH 12 601 #define ESF_DZ_TX_PIO_BUF_ADDR_LBN 0 602 #define ESF_DZ_TX_PIO_BUF_ADDR_WIDTH 12 603 604 605 /* ES_TX_TSO_DESC */ 606 #define ESF_DZ_TX_DESC_IS_OPT_LBN 63 607 #define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1 608 #define ESF_DZ_TX_OPTION_TYPE_LBN 60 609 #define ESF_DZ_TX_OPTION_TYPE_WIDTH 3 610 #define ESE_DZ_TX_OPTION_DESC_TSO 7 611 #define ESE_DZ_TX_OPTION_DESC_VLAN 6 612 #define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0 613 #define ESF_DZ_TX_TSO_OPTION_TYPE_LBN 56 614 #define ESF_DZ_TX_TSO_OPTION_TYPE_WIDTH 4 615 #define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B 3 616 #define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A 2 617 #define ESE_DZ_TX_TSO_OPTION_DESC_ENCAP 1 618 #define ESE_DZ_TX_TSO_OPTION_DESC_NORMAL 0 619 #define ESF_DZ_TX_TSO_TCP_FLAGS_LBN 48 620 #define ESF_DZ_TX_TSO_TCP_FLAGS_WIDTH 8 621 #define ESF_DZ_TX_TSO_IP_ID_LBN 32 622 #define ESF_DZ_TX_TSO_IP_ID_WIDTH 16 623 #define ESF_DZ_TX_TSO_TCP_SEQNO_LBN 0 624 #define ESF_DZ_TX_TSO_TCP_SEQNO_WIDTH 32 625 626 627 /* ES_TX_TSO_V2_DESC_A */ 628 #define ESF_DZ_TX_DESC_IS_OPT_LBN 63 629 #define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1 630 #define ESF_DZ_TX_OPTION_TYPE_LBN 60 631 #define ESF_DZ_TX_OPTION_TYPE_WIDTH 3 632 #define ESE_DZ_TX_OPTION_DESC_TSO 7 633 #define ESE_DZ_TX_OPTION_DESC_VLAN 6 634 #define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0 635 #define ESF_DZ_TX_TSO_OPTION_TYPE_LBN 56 636 #define ESF_DZ_TX_TSO_OPTION_TYPE_WIDTH 4 637 #define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B 3 638 #define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A 2 639 #define ESE_DZ_TX_TSO_OPTION_DESC_ENCAP 1 640 #define ESE_DZ_TX_TSO_OPTION_DESC_NORMAL 0 641 #define ESF_DZ_TX_TSO_IP_ID_LBN 32 642 #define ESF_DZ_TX_TSO_IP_ID_WIDTH 16 643 #define ESF_DZ_TX_TSO_TCP_SEQNO_LBN 0 644 #define ESF_DZ_TX_TSO_TCP_SEQNO_WIDTH 32 645 646 647 /* ES_TX_TSO_V2_DESC_B */ 648 #define ESF_DZ_TX_DESC_IS_OPT_LBN 63 649 #define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1 650 #define ESF_DZ_TX_OPTION_TYPE_LBN 60 651 #define ESF_DZ_TX_OPTION_TYPE_WIDTH 3 652 #define ESE_DZ_TX_OPTION_DESC_TSO 7 653 #define ESE_DZ_TX_OPTION_DESC_VLAN 6 654 #define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0 655 #define ESF_DZ_TX_TSO_OPTION_TYPE_LBN 56 656 #define ESF_DZ_TX_TSO_OPTION_TYPE_WIDTH 4 657 #define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B 3 658 #define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A 2 659 #define ESE_DZ_TX_TSO_OPTION_DESC_ENCAP 1 660 #define ESE_DZ_TX_TSO_OPTION_DESC_NORMAL 0 661 #define ESF_DZ_TX_TSO_TCP_MSS_LBN 32 662 #define ESF_DZ_TX_TSO_TCP_MSS_WIDTH 16 663 #define ESF_DZ_TX_TSO_OUTER_IPID_LBN 0 664 #define ESF_DZ_TX_TSO_OUTER_IPID_WIDTH 16 665 666 667 /* ES_TX_VLAN_DESC */ 668 #define ESF_DZ_TX_DESC_IS_OPT_LBN 63 669 #define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1 670 #define ESF_DZ_TX_OPTION_TYPE_LBN 60 671 #define ESF_DZ_TX_OPTION_TYPE_WIDTH 3 672 #define ESE_DZ_TX_OPTION_DESC_TSO 7 673 #define ESE_DZ_TX_OPTION_DESC_VLAN 6 674 #define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0 675 #define ESF_DZ_TX_VLAN_OP_LBN 32 676 #define ESF_DZ_TX_VLAN_OP_WIDTH 2 677 #define ESF_DZ_TX_VLAN_TAG2_LBN 16 678 #define ESF_DZ_TX_VLAN_TAG2_WIDTH 16 679 #define ESF_DZ_TX_VLAN_TAG1_LBN 0 680 #define ESF_DZ_TX_VLAN_TAG1_WIDTH 16 681 682 683 /************************************************************************* 684 * NOTE: the comment line above marks the end of the autogenerated section 685 */ 686 687 /* 688 * The workaround for bug 35388 requires multiplexing writes through 689 * the ERF_DZ_TX_DESC_WPTR address. 690 * TX_DESC_UPD: 0ppppppppppp (bit 11 lost) 691 * EVQ_RPTR: 1000hhhhhhhh, 1001llllllll (split into high and low bits) 692 * EVQ_TMR: 11mmvvvvvvvv (bits 8:13 of value lost) 693 */ 694 #define ER_DD_EVQ_INDIRECT_OFST (ER_DZ_TX_DESC_UPD_REG_OFST + 2 * 4) 695 #define ER_DD_EVQ_INDIRECT_STEP ER_DZ_TX_DESC_UPD_REG_STEP 696 #define ERF_DD_EVQ_IND_RPTR_FLAGS_LBN 8 697 #define ERF_DD_EVQ_IND_RPTR_FLAGS_WIDTH 4 698 #define EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH 8 699 #define EFE_DD_EVQ_IND_RPTR_FLAGS_LOW 9 700 #define ERF_DD_EVQ_IND_RPTR_LBN 0 701 #define ERF_DD_EVQ_IND_RPTR_WIDTH 8 702 #define ERF_DD_EVQ_IND_TIMER_FLAGS_LBN 10 703 #define ERF_DD_EVQ_IND_TIMER_FLAGS_WIDTH 2 704 #define EFE_DD_EVQ_IND_TIMER_FLAGS 3 705 #define ERF_DD_EVQ_IND_TIMER_MODE_LBN 8 706 #define ERF_DD_EVQ_IND_TIMER_MODE_WIDTH 2 707 #define ERF_DD_EVQ_IND_TIMER_VAL_LBN 0 708 #define ERF_DD_EVQ_IND_TIMER_VAL_WIDTH 8 709 710 /* Packed stream magic doorbell command */ 711 #define ERF_DZ_RX_DESC_MAGIC_DOORBELL_LBN 11 712 #define ERF_DZ_RX_DESC_MAGIC_DOORBELL_WIDTH 1 713 714 #define ERF_DZ_RX_DESC_MAGIC_CMD_LBN 8 715 #define ERF_DZ_RX_DESC_MAGIC_CMD_WIDTH 3 716 #define ERE_DZ_RX_DESC_MAGIC_CMD_PS_CREDITS 0 717 718 #define ERF_DZ_RX_DESC_MAGIC_DATA_LBN 0 719 #define ERF_DZ_RX_DESC_MAGIC_DATA_WIDTH 8 720 721 /* Packed stream RX packet prefix */ 722 #define ES_DZ_PS_RX_PREFIX_TSTAMP_LBN 0 723 #define ES_DZ_PS_RX_PREFIX_TSTAMP_WIDTH 32 724 #define ES_DZ_PS_RX_PREFIX_CAP_LEN_LBN 32 725 #define ES_DZ_PS_RX_PREFIX_CAP_LEN_WIDTH 16 726 #define ES_DZ_PS_RX_PREFIX_ORIG_LEN_LBN 48 727 #define ES_DZ_PS_RX_PREFIX_ORIG_LEN_WIDTH 16 728 729 /* Equal stride super-buffer RX packet prefix (see SF-119419-TC) */ 730 #define ES_EZ_ESSB_RX_PREFIX_LEN 8 731 #define ES_EZ_ESSB_RX_PREFIX_DATA_LEN_LBN 0 732 #define ES_EZ_ESSB_RX_PREFIX_DATA_LEN_WIDTH 16 733 #define ES_EZ_ESSB_RX_PREFIX_MARK_LBN 16 734 #define ES_EZ_ESSB_RX_PREFIX_MARK_WIDTH 8 735 #define ES_EZ_ESSB_RX_PREFIX_HASH_VALID_LBN 28 736 #define ES_EZ_ESSB_RX_PREFIX_HASH_VALID_WIDTH 1 737 #define ES_EZ_ESSB_RX_PREFIX_MARK_VALID_LBN 29 738 #define ES_EZ_ESSB_RX_PREFIX_MARK_VALID_WIDTH 1 739 #define ES_EZ_ESSB_RX_PREFIX_MATCH_FLAG_LBN 30 740 #define ES_EZ_ESSB_RX_PREFIX_MATCH_FLAG_WIDTH 1 741 #define ES_EZ_ESSB_RX_PREFIX_HASH_LBN 32 742 #define ES_EZ_ESSB_RX_PREFIX_HASH_WIDTH 32 743 744 /* 745 * An extra flag for the packed stream mode, 746 * signalling the start of a new buffer 747 */ 748 #define ESF_DZ_RX_EV_ROTATE_LBN 53 749 #define ESF_DZ_RX_EV_ROTATE_WIDTH 1 750 751 #ifdef __cplusplus 752 } 753 #endif 754 755 #endif /* _SYS_EFX_EF10_REGS_H */ 756