1 /*- 2 * Copyright (c) 2007-2015 Solarflare Communications Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * The views and conclusions contained in the software and documentation are 27 * those of the authors and should not be interpreted as representing official 28 * policies, either expressed or implied, of the FreeBSD Project. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include "efx.h" 35 #include "efx_impl.h" 36 37 __checkReturn efx_rc_t 38 efx_family( 39 __in uint16_t venid, 40 __in uint16_t devid, 41 __out efx_family_t *efp) 42 { 43 if (venid == EFX_PCI_VENID_SFC) { 44 switch (devid) { 45 #if EFSYS_OPT_FALCON 46 case EFX_PCI_DEVID_FALCON: 47 *efp = EFX_FAMILY_FALCON; 48 return (0); 49 #endif /* EFSYS_OPT_FALCON */ 50 51 #if EFSYS_OPT_SIENA 52 case EFX_PCI_DEVID_SIENA_F1_UNINIT: 53 /* 54 * Hardware default for PF0 of uninitialised Siena. 55 * manftest must be able to cope with this device id. 56 */ 57 *efp = EFX_FAMILY_SIENA; 58 return (0); 59 60 case EFX_PCI_DEVID_BETHPAGE: 61 case EFX_PCI_DEVID_SIENA: 62 *efp = EFX_FAMILY_SIENA; 63 return (0); 64 #endif /* EFSYS_OPT_SIENA */ 65 66 #if EFSYS_OPT_HUNTINGTON 67 case EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT: 68 /* 69 * Hardware default for PF0 of uninitialised Huntington. 70 * manftest must be able to cope with this device id. 71 */ 72 *efp = EFX_FAMILY_HUNTINGTON; 73 return (0); 74 75 case EFX_PCI_DEVID_FARMINGDALE: 76 case EFX_PCI_DEVID_GREENPORT: 77 *efp = EFX_FAMILY_HUNTINGTON; 78 return (0); 79 80 case EFX_PCI_DEVID_FARMINGDALE_VF: 81 case EFX_PCI_DEVID_GREENPORT_VF: 82 *efp = EFX_FAMILY_HUNTINGTON; 83 return (0); 84 #endif /* EFSYS_OPT_HUNTINGTON */ 85 86 #if EFSYS_OPT_MEDFORD 87 case EFX_PCI_DEVID_MEDFORD_PF_UNINIT: 88 /* 89 * Hardware default for PF0 of uninitialised Medford. 90 * manftest must be able to cope with this device id. 91 */ 92 *efp = EFX_FAMILY_MEDFORD; 93 return (0); 94 95 case EFX_PCI_DEVID_MEDFORD: 96 *efp = EFX_FAMILY_MEDFORD; 97 return (0); 98 99 case EFX_PCI_DEVID_MEDFORD_VF: 100 *efp = EFX_FAMILY_MEDFORD; 101 return (0); 102 #endif /* EFSYS_OPT_MEDFORD */ 103 104 default: 105 break; 106 } 107 } 108 109 *efp = EFX_FAMILY_INVALID; 110 return (ENOTSUP); 111 } 112 113 /* 114 * To support clients which aren't provided with any PCI context infer 115 * the hardware family by inspecting the hardware. Obviously the caller 116 * must be damn sure they're really talking to a supported device. 117 */ 118 __checkReturn efx_rc_t 119 efx_infer_family( 120 __in efsys_bar_t *esbp, 121 __out efx_family_t *efp) 122 { 123 efx_family_t family; 124 efx_oword_t oword; 125 unsigned int portnum; 126 efx_rc_t rc; 127 128 EFSYS_BAR_READO(esbp, FR_AZ_CS_DEBUG_REG_OFST, &oword, B_TRUE); 129 portnum = EFX_OWORD_FIELD(oword, FRF_CZ_CS_PORT_NUM); 130 if ((portnum == 1) || (portnum == 2)) { 131 #if EFSYS_OPT_SIENA 132 family = EFX_FAMILY_SIENA; 133 goto out; 134 #endif 135 } else if (portnum == 0) { 136 efx_dword_t dword; 137 uint32_t hw_rev; 138 139 EFSYS_BAR_READD(esbp, ER_DZ_BIU_HW_REV_ID_REG_OFST, &dword, 140 B_TRUE); 141 hw_rev = EFX_DWORD_FIELD(dword, ERF_DZ_HW_REV_ID); 142 if (hw_rev == ER_DZ_BIU_HW_REV_ID_REG_RESET) { 143 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD 144 /* 145 * BIU_HW_REV_ID is the same for Huntington and Medford. 146 * Assume Huntington, as Medford is very similar. 147 */ 148 family = EFX_FAMILY_HUNTINGTON; 149 goto out; 150 #endif 151 } else { 152 #if EFSYS_OPT_FALCON 153 family = EFX_FAMILY_FALCON; 154 goto out; 155 #endif 156 } 157 } 158 rc = ENOTSUP; 159 goto fail1; 160 161 out: 162 if (efp != NULL) 163 *efp = family; 164 return (0); 165 166 fail1: 167 EFSYS_PROBE1(fail1, efx_rc_t, rc); 168 169 return (rc); 170 } 171 172 #define EFX_BIU_MAGIC0 0x01234567 173 #define EFX_BIU_MAGIC1 0xfedcba98 174 175 __checkReturn efx_rc_t 176 efx_nic_biu_test( 177 __in efx_nic_t *enp) 178 { 179 efx_oword_t oword; 180 efx_rc_t rc; 181 182 /* 183 * Write magic values to scratch registers 0 and 1, then 184 * verify that the values were written correctly. Interleave 185 * the accesses to ensure that the BIU is not just reading 186 * back the cached value that was last written. 187 */ 188 EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, EFX_BIU_MAGIC0); 189 EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE); 190 191 EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, EFX_BIU_MAGIC1); 192 EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 1, &oword, B_TRUE); 193 194 EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE); 195 if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != EFX_BIU_MAGIC0) { 196 rc = EIO; 197 goto fail1; 198 } 199 200 EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 1, &oword, B_TRUE); 201 if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != EFX_BIU_MAGIC1) { 202 rc = EIO; 203 goto fail2; 204 } 205 206 /* 207 * Perform the same test, with the values swapped. This 208 * ensures that subsequent tests don't start with the correct 209 * values already written into the scratch registers. 210 */ 211 EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, EFX_BIU_MAGIC1); 212 EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE); 213 214 EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, EFX_BIU_MAGIC0); 215 EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 1, &oword, B_TRUE); 216 217 EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE); 218 if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != EFX_BIU_MAGIC1) { 219 rc = EIO; 220 goto fail3; 221 } 222 223 EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 1, &oword, B_TRUE); 224 if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != EFX_BIU_MAGIC0) { 225 rc = EIO; 226 goto fail4; 227 } 228 229 return (0); 230 231 fail4: 232 EFSYS_PROBE(fail4); 233 fail3: 234 EFSYS_PROBE(fail3); 235 fail2: 236 EFSYS_PROBE(fail2); 237 fail1: 238 EFSYS_PROBE1(fail1, efx_rc_t, rc); 239 240 return (rc); 241 } 242 243 #if EFSYS_OPT_FALCON 244 245 static efx_nic_ops_t __efx_nic_falcon_ops = { 246 falcon_nic_probe, /* eno_probe */ 247 NULL, /* eno_set_drv_limits */ 248 falcon_nic_reset, /* eno_reset */ 249 falcon_nic_init, /* eno_init */ 250 NULL, /* eno_get_vi_pool */ 251 NULL, /* eno_get_bar_region */ 252 #if EFSYS_OPT_DIAG 253 falcon_sram_test, /* eno_sram_test */ 254 falcon_nic_register_test, /* eno_register_test */ 255 #endif /* EFSYS_OPT_DIAG */ 256 falcon_nic_fini, /* eno_fini */ 257 falcon_nic_unprobe, /* eno_unprobe */ 258 }; 259 260 #endif /* EFSYS_OPT_FALCON */ 261 262 #if EFSYS_OPT_SIENA 263 264 static efx_nic_ops_t __efx_nic_siena_ops = { 265 siena_nic_probe, /* eno_probe */ 266 NULL, /* eno_set_drv_limits */ 267 siena_nic_reset, /* eno_reset */ 268 siena_nic_init, /* eno_init */ 269 NULL, /* eno_get_vi_pool */ 270 NULL, /* eno_get_bar_region */ 271 #if EFSYS_OPT_DIAG 272 siena_sram_test, /* eno_sram_test */ 273 siena_nic_register_test, /* eno_register_test */ 274 #endif /* EFSYS_OPT_DIAG */ 275 siena_nic_fini, /* eno_fini */ 276 siena_nic_unprobe, /* eno_unprobe */ 277 }; 278 279 #endif /* EFSYS_OPT_SIENA */ 280 281 #if EFSYS_OPT_HUNTINGTON 282 283 static efx_nic_ops_t __efx_nic_hunt_ops = { 284 ef10_nic_probe, /* eno_probe */ 285 ef10_nic_set_drv_limits, /* eno_set_drv_limits */ 286 ef10_nic_reset, /* eno_reset */ 287 ef10_nic_init, /* eno_init */ 288 ef10_nic_get_vi_pool, /* eno_get_vi_pool */ 289 ef10_nic_get_bar_region, /* eno_get_bar_region */ 290 #if EFSYS_OPT_DIAG 291 ef10_sram_test, /* eno_sram_test */ 292 ef10_nic_register_test, /* eno_register_test */ 293 #endif /* EFSYS_OPT_DIAG */ 294 ef10_nic_fini, /* eno_fini */ 295 ef10_nic_unprobe, /* eno_unprobe */ 296 }; 297 298 #endif /* EFSYS_OPT_HUNTINGTON */ 299 300 __checkReturn efx_rc_t 301 efx_nic_create( 302 __in efx_family_t family, 303 __in efsys_identifier_t *esip, 304 __in efsys_bar_t *esbp, 305 __in efsys_lock_t *eslp, 306 __deref_out efx_nic_t **enpp) 307 { 308 efx_nic_t *enp; 309 efx_rc_t rc; 310 311 EFSYS_ASSERT3U(family, >, EFX_FAMILY_INVALID); 312 EFSYS_ASSERT3U(family, <, EFX_FAMILY_NTYPES); 313 314 /* Allocate a NIC object */ 315 EFSYS_KMEM_ALLOC(esip, sizeof (efx_nic_t), enp); 316 317 if (enp == NULL) { 318 rc = ENOMEM; 319 goto fail1; 320 } 321 322 enp->en_magic = EFX_NIC_MAGIC; 323 324 switch (family) { 325 #if EFSYS_OPT_FALCON 326 case EFX_FAMILY_FALCON: 327 enp->en_enop = (efx_nic_ops_t *)&__efx_nic_falcon_ops; 328 enp->en_features = 0; 329 break; 330 #endif /* EFSYS_OPT_FALCON */ 331 332 #if EFSYS_OPT_SIENA 333 case EFX_FAMILY_SIENA: 334 enp->en_enop = (efx_nic_ops_t *)&__efx_nic_siena_ops; 335 enp->en_features = 336 EFX_FEATURE_IPV6 | 337 EFX_FEATURE_LFSR_HASH_INSERT | 338 EFX_FEATURE_LINK_EVENTS | 339 EFX_FEATURE_PERIODIC_MAC_STATS | 340 EFX_FEATURE_WOL | 341 EFX_FEATURE_MCDI | 342 EFX_FEATURE_LOOKAHEAD_SPLIT | 343 EFX_FEATURE_MAC_HEADER_FILTERS | 344 EFX_FEATURE_TX_SRC_FILTERS; 345 break; 346 #endif /* EFSYS_OPT_SIENA */ 347 348 #if EFSYS_OPT_HUNTINGTON 349 case EFX_FAMILY_HUNTINGTON: 350 enp->en_enop = (efx_nic_ops_t *)&__efx_nic_hunt_ops; 351 /* FIXME: Add WOL support */ 352 enp->en_features = 353 EFX_FEATURE_IPV6 | 354 EFX_FEATURE_LINK_EVENTS | 355 EFX_FEATURE_PERIODIC_MAC_STATS | 356 EFX_FEATURE_MCDI | 357 EFX_FEATURE_MAC_HEADER_FILTERS | 358 EFX_FEATURE_MCDI_DMA | 359 EFX_FEATURE_PIO_BUFFERS | 360 EFX_FEATURE_FW_ASSISTED_TSO; 361 break; 362 #endif /* EFSYS_OPT_HUNTINGTON */ 363 364 default: 365 rc = ENOTSUP; 366 goto fail2; 367 } 368 369 enp->en_family = family; 370 enp->en_esip = esip; 371 enp->en_esbp = esbp; 372 enp->en_eslp = eslp; 373 374 *enpp = enp; 375 376 return (0); 377 378 fail2: 379 EFSYS_PROBE(fail2); 380 381 enp->en_magic = 0; 382 383 /* Free the NIC object */ 384 EFSYS_KMEM_FREE(esip, sizeof (efx_nic_t), enp); 385 386 fail1: 387 EFSYS_PROBE1(fail1, efx_rc_t, rc); 388 389 return (rc); 390 } 391 392 __checkReturn efx_rc_t 393 efx_nic_probe( 394 __in efx_nic_t *enp) 395 { 396 efx_nic_ops_t *enop; 397 efx_rc_t rc; 398 399 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 400 #if EFSYS_OPT_MCDI 401 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI); 402 #endif /* EFSYS_OPT_MCDI */ 403 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_PROBE)); 404 405 enop = enp->en_enop; 406 if ((rc = enop->eno_probe(enp)) != 0) 407 goto fail1; 408 409 if ((rc = efx_phy_probe(enp)) != 0) 410 goto fail2; 411 412 enp->en_mod_flags |= EFX_MOD_PROBE; 413 414 return (0); 415 416 fail2: 417 EFSYS_PROBE(fail2); 418 419 enop->eno_unprobe(enp); 420 421 fail1: 422 EFSYS_PROBE1(fail1, efx_rc_t, rc); 423 424 return (rc); 425 } 426 427 #if EFSYS_OPT_PCIE_TUNE 428 429 __checkReturn efx_rc_t 430 efx_nic_pcie_tune( 431 __in efx_nic_t *enp, 432 unsigned int nlanes) 433 { 434 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 435 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE); 436 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_NIC)); 437 438 #if EFSYS_OPT_FALCON 439 if (enp->en_family == EFX_FAMILY_FALCON) 440 return (falcon_nic_pcie_tune(enp, nlanes)); 441 #endif 442 return (ENOTSUP); 443 } 444 445 __checkReturn efx_rc_t 446 efx_nic_pcie_extended_sync( 447 __in efx_nic_t *enp) 448 { 449 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 450 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE); 451 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_NIC)); 452 453 #if EFSYS_OPT_SIENA 454 if (enp->en_family == EFX_FAMILY_SIENA) 455 return (siena_nic_pcie_extended_sync(enp)); 456 #endif 457 458 return (ENOTSUP); 459 } 460 461 #endif /* EFSYS_OPT_PCIE_TUNE */ 462 463 __checkReturn efx_rc_t 464 efx_nic_set_drv_limits( 465 __inout efx_nic_t *enp, 466 __in efx_drv_limits_t *edlp) 467 { 468 efx_nic_ops_t *enop = enp->en_enop; 469 efx_rc_t rc; 470 471 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 472 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE); 473 474 if (enop->eno_set_drv_limits != NULL) { 475 if ((rc = enop->eno_set_drv_limits(enp, edlp)) != 0) 476 goto fail1; 477 } 478 479 return (0); 480 481 fail1: 482 EFSYS_PROBE1(fail1, efx_rc_t, rc); 483 484 return (rc); 485 } 486 487 __checkReturn efx_rc_t 488 efx_nic_get_bar_region( 489 __in efx_nic_t *enp, 490 __in efx_nic_region_t region, 491 __out uint32_t *offsetp, 492 __out size_t *sizep) 493 { 494 efx_nic_ops_t *enop = enp->en_enop; 495 efx_rc_t rc; 496 497 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 498 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE); 499 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC); 500 501 if (enop->eno_get_bar_region == NULL) { 502 rc = ENOTSUP; 503 goto fail1; 504 } 505 if ((rc = (enop->eno_get_bar_region)(enp, 506 region, offsetp, sizep)) != 0) { 507 goto fail2; 508 } 509 510 return (0); 511 512 fail2: 513 EFSYS_PROBE(fail2); 514 515 fail1: 516 EFSYS_PROBE1(fail1, efx_rc_t, rc); 517 518 return (rc); 519 } 520 521 522 __checkReturn efx_rc_t 523 efx_nic_get_vi_pool( 524 __in efx_nic_t *enp, 525 __out uint32_t *evq_countp, 526 __out uint32_t *rxq_countp, 527 __out uint32_t *txq_countp) 528 { 529 efx_nic_ops_t *enop = enp->en_enop; 530 efx_nic_cfg_t *encp = &enp->en_nic_cfg; 531 efx_rc_t rc; 532 533 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 534 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE); 535 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC); 536 537 if (enop->eno_get_vi_pool != NULL) { 538 uint32_t vi_count = 0; 539 540 if ((rc = (enop->eno_get_vi_pool)(enp, &vi_count)) != 0) 541 goto fail1; 542 543 *evq_countp = vi_count; 544 *rxq_countp = vi_count; 545 *txq_countp = vi_count; 546 } else { 547 /* Use NIC limits as default value */ 548 *evq_countp = encp->enc_evq_limit; 549 *rxq_countp = encp->enc_rxq_limit; 550 *txq_countp = encp->enc_txq_limit; 551 } 552 553 return (0); 554 555 fail1: 556 EFSYS_PROBE1(fail1, efx_rc_t, rc); 557 558 return (rc); 559 } 560 561 562 __checkReturn efx_rc_t 563 efx_nic_init( 564 __in efx_nic_t *enp) 565 { 566 efx_nic_ops_t *enop = enp->en_enop; 567 efx_rc_t rc; 568 569 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 570 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE); 571 572 if (enp->en_mod_flags & EFX_MOD_NIC) { 573 rc = EINVAL; 574 goto fail1; 575 } 576 577 if ((rc = enop->eno_init(enp)) != 0) 578 goto fail2; 579 580 enp->en_mod_flags |= EFX_MOD_NIC; 581 582 return (0); 583 584 fail2: 585 EFSYS_PROBE(fail2); 586 fail1: 587 EFSYS_PROBE1(fail1, efx_rc_t, rc); 588 589 return (rc); 590 } 591 592 void 593 efx_nic_fini( 594 __in efx_nic_t *enp) 595 { 596 efx_nic_ops_t *enop = enp->en_enop; 597 598 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 599 EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROBE); 600 EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_NIC); 601 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_INTR)); 602 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV)); 603 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX)); 604 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX)); 605 606 enop->eno_fini(enp); 607 608 enp->en_mod_flags &= ~EFX_MOD_NIC; 609 } 610 611 void 612 efx_nic_unprobe( 613 __in efx_nic_t *enp) 614 { 615 efx_nic_ops_t *enop = enp->en_enop; 616 617 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 618 #if EFSYS_OPT_MCDI 619 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI); 620 #endif /* EFSYS_OPT_MCDI */ 621 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE); 622 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_NIC)); 623 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_INTR)); 624 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV)); 625 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX)); 626 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX)); 627 628 efx_phy_unprobe(enp); 629 630 enop->eno_unprobe(enp); 631 632 enp->en_mod_flags &= ~EFX_MOD_PROBE; 633 } 634 635 void 636 efx_nic_destroy( 637 __in efx_nic_t *enp) 638 { 639 efsys_identifier_t *esip = enp->en_esip; 640 641 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 642 EFSYS_ASSERT3U(enp->en_mod_flags, ==, 0); 643 644 enp->en_family = 0; 645 enp->en_esip = NULL; 646 enp->en_esbp = NULL; 647 enp->en_eslp = NULL; 648 649 enp->en_enop = NULL; 650 651 enp->en_magic = 0; 652 653 /* Free the NIC object */ 654 EFSYS_KMEM_FREE(esip, sizeof (efx_nic_t), enp); 655 } 656 657 __checkReturn efx_rc_t 658 efx_nic_reset( 659 __in efx_nic_t *enp) 660 { 661 efx_nic_ops_t *enop = enp->en_enop; 662 unsigned int mod_flags; 663 efx_rc_t rc; 664 665 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 666 EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROBE); 667 /* 668 * All modules except the MCDI, PROBE, NVRAM, VPD, MON (which we 669 * do not reset here) must have been shut down or never initialized. 670 * 671 * A rule of thumb here is: If the controller or MC reboots, is *any* 672 * state lost. If it's lost and needs reapplying, then the module 673 * *must* not be initialised during the reset. 674 */ 675 mod_flags = enp->en_mod_flags; 676 mod_flags &= ~(EFX_MOD_MCDI | EFX_MOD_PROBE | EFX_MOD_NVRAM | 677 EFX_MOD_VPD | EFX_MOD_MON); 678 EFSYS_ASSERT3U(mod_flags, ==, 0); 679 if (mod_flags != 0) { 680 rc = EINVAL; 681 goto fail1; 682 } 683 684 if ((rc = enop->eno_reset(enp)) != 0) 685 goto fail2; 686 687 enp->en_reset_flags |= EFX_RESET_MAC; 688 689 return (0); 690 691 fail2: 692 EFSYS_PROBE(fail2); 693 fail1: 694 EFSYS_PROBE1(fail1, efx_rc_t, rc); 695 696 return (rc); 697 } 698 699 const efx_nic_cfg_t * 700 efx_nic_cfg_get( 701 __in efx_nic_t *enp) 702 { 703 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 704 705 return (&(enp->en_nic_cfg)); 706 } 707 708 #if EFSYS_OPT_DIAG 709 710 __checkReturn efx_rc_t 711 efx_nic_register_test( 712 __in efx_nic_t *enp) 713 { 714 efx_nic_ops_t *enop = enp->en_enop; 715 efx_rc_t rc; 716 717 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 718 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE); 719 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_NIC)); 720 721 if ((rc = enop->eno_register_test(enp)) != 0) 722 goto fail1; 723 724 return (0); 725 726 fail1: 727 EFSYS_PROBE1(fail1, efx_rc_t, rc); 728 729 return (rc); 730 } 731 732 __checkReturn efx_rc_t 733 efx_nic_test_registers( 734 __in efx_nic_t *enp, 735 __in efx_register_set_t *rsp, 736 __in size_t count) 737 { 738 unsigned int bit; 739 efx_oword_t original; 740 efx_oword_t reg; 741 efx_oword_t buf; 742 efx_rc_t rc; 743 744 while (count > 0) { 745 /* This function is only suitable for registers */ 746 EFSYS_ASSERT(rsp->rows == 1); 747 748 /* bit sweep on and off */ 749 EFSYS_BAR_READO(enp->en_esbp, rsp->address, &original, 750 B_TRUE); 751 for (bit = 0; bit < 128; bit++) { 752 /* Is this bit in the mask? */ 753 if (~(rsp->mask.eo_u32[bit >> 5]) & (1 << bit)) 754 continue; 755 756 /* Test this bit can be set in isolation */ 757 reg = original; 758 EFX_AND_OWORD(reg, rsp->mask); 759 EFX_SET_OWORD_BIT(reg, bit); 760 761 EFSYS_BAR_WRITEO(enp->en_esbp, rsp->address, ®, 762 B_TRUE); 763 EFSYS_BAR_READO(enp->en_esbp, rsp->address, &buf, 764 B_TRUE); 765 766 EFX_AND_OWORD(buf, rsp->mask); 767 if (memcmp(®, &buf, sizeof (reg))) { 768 rc = EIO; 769 goto fail1; 770 } 771 772 /* Test this bit can be cleared in isolation */ 773 EFX_OR_OWORD(reg, rsp->mask); 774 EFX_CLEAR_OWORD_BIT(reg, bit); 775 776 EFSYS_BAR_WRITEO(enp->en_esbp, rsp->address, ®, 777 B_TRUE); 778 EFSYS_BAR_READO(enp->en_esbp, rsp->address, &buf, 779 B_TRUE); 780 781 EFX_AND_OWORD(buf, rsp->mask); 782 if (memcmp(®, &buf, sizeof (reg))) { 783 rc = EIO; 784 goto fail2; 785 } 786 } 787 788 /* Restore the old value */ 789 EFSYS_BAR_WRITEO(enp->en_esbp, rsp->address, &original, 790 B_TRUE); 791 792 --count; 793 ++rsp; 794 } 795 796 return (0); 797 798 fail2: 799 EFSYS_PROBE(fail2); 800 fail1: 801 EFSYS_PROBE1(fail1, efx_rc_t, rc); 802 803 /* Restore the old value */ 804 EFSYS_BAR_WRITEO(enp->en_esbp, rsp->address, &original, B_TRUE); 805 806 return (rc); 807 } 808 809 __checkReturn efx_rc_t 810 efx_nic_test_tables( 811 __in efx_nic_t *enp, 812 __in efx_register_set_t *rsp, 813 __in efx_pattern_type_t pattern, 814 __in size_t count) 815 { 816 efx_sram_pattern_fn_t func; 817 unsigned int index; 818 unsigned int address; 819 efx_oword_t reg; 820 efx_oword_t buf; 821 efx_rc_t rc; 822 823 EFSYS_ASSERT(pattern < EFX_PATTERN_NTYPES); 824 func = __efx_sram_pattern_fns[pattern]; 825 826 while (count > 0) { 827 /* Write */ 828 address = rsp->address; 829 for (index = 0; index < rsp->rows; ++index) { 830 func(2 * index + 0, B_FALSE, ®.eo_qword[0]); 831 func(2 * index + 1, B_FALSE, ®.eo_qword[1]); 832 EFX_AND_OWORD(reg, rsp->mask); 833 EFSYS_BAR_WRITEO(enp->en_esbp, address, ®, B_TRUE); 834 835 address += rsp->step; 836 } 837 838 /* Read */ 839 address = rsp->address; 840 for (index = 0; index < rsp->rows; ++index) { 841 func(2 * index + 0, B_FALSE, ®.eo_qword[0]); 842 func(2 * index + 1, B_FALSE, ®.eo_qword[1]); 843 EFX_AND_OWORD(reg, rsp->mask); 844 EFSYS_BAR_READO(enp->en_esbp, address, &buf, B_TRUE); 845 if (memcmp(®, &buf, sizeof (reg))) { 846 rc = EIO; 847 goto fail1; 848 } 849 850 address += rsp->step; 851 } 852 853 ++rsp; 854 --count; 855 } 856 857 return (0); 858 859 fail1: 860 EFSYS_PROBE1(fail1, efx_rc_t, rc); 861 862 return (rc); 863 } 864 865 #endif /* EFSYS_OPT_DIAG */ 866 867 #if EFSYS_OPT_LOOPBACK 868 869 extern void 870 efx_loopback_mask( 871 __in efx_loopback_kind_t loopback_kind, 872 __out efx_qword_t *maskp) 873 { 874 efx_qword_t mask; 875 876 EFSYS_ASSERT3U(loopback_kind, <, EFX_LOOPBACK_NKINDS); 877 EFSYS_ASSERT(maskp != NULL); 878 879 /* Assert the MC_CMD_LOOPBACK and EFX_LOOPBACK namespace agree */ 880 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_NONE == EFX_LOOPBACK_OFF); 881 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_DATA == EFX_LOOPBACK_DATA); 882 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GMAC == EFX_LOOPBACK_GMAC); 883 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XGMII == EFX_LOOPBACK_XGMII); 884 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XGXS == EFX_LOOPBACK_XGXS); 885 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XAUI == EFX_LOOPBACK_XAUI); 886 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GMII == EFX_LOOPBACK_GMII); 887 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SGMII == EFX_LOOPBACK_SGMII); 888 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XGBR == EFX_LOOPBACK_XGBR); 889 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XFI == EFX_LOOPBACK_XFI); 890 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XAUI_FAR == EFX_LOOPBACK_XAUI_FAR); 891 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GMII_FAR == EFX_LOOPBACK_GMII_FAR); 892 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SGMII_FAR == EFX_LOOPBACK_SGMII_FAR); 893 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XFI_FAR == EFX_LOOPBACK_XFI_FAR); 894 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GPHY == EFX_LOOPBACK_GPHY); 895 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PHYXS == EFX_LOOPBACK_PHY_XS); 896 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PCS == EFX_LOOPBACK_PCS); 897 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PMAPMD == EFX_LOOPBACK_PMA_PMD); 898 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XPORT == EFX_LOOPBACK_XPORT); 899 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XGMII_WS == EFX_LOOPBACK_XGMII_WS); 900 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XAUI_WS == EFX_LOOPBACK_XAUI_WS); 901 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XAUI_WS_FAR == 902 EFX_LOOPBACK_XAUI_WS_FAR); 903 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XAUI_WS_NEAR == 904 EFX_LOOPBACK_XAUI_WS_NEAR); 905 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GMII_WS == EFX_LOOPBACK_GMII_WS); 906 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XFI_WS == EFX_LOOPBACK_XFI_WS); 907 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XFI_WS_FAR == 908 EFX_LOOPBACK_XFI_WS_FAR); 909 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PHYXS_WS == EFX_LOOPBACK_PHYXS_WS); 910 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PMA_INT == EFX_LOOPBACK_PMA_INT); 911 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SD_NEAR == EFX_LOOPBACK_SD_NEAR); 912 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SD_FAR == EFX_LOOPBACK_SD_FAR); 913 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PMA_INT_WS == 914 EFX_LOOPBACK_PMA_INT_WS); 915 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SD_FEP2_WS == 916 EFX_LOOPBACK_SD_FEP2_WS); 917 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SD_FEP1_5_WS == 918 EFX_LOOPBACK_SD_FEP1_5_WS); 919 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SD_FEP_WS == EFX_LOOPBACK_SD_FEP_WS); 920 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SD_FES_WS == EFX_LOOPBACK_SD_FES_WS); 921 922 /* Build bitmask of possible loopback types */ 923 EFX_ZERO_QWORD(mask); 924 925 if ((loopback_kind == EFX_LOOPBACK_KIND_OFF) || 926 (loopback_kind == EFX_LOOPBACK_KIND_ALL)) { 927 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_OFF); 928 } 929 930 if ((loopback_kind == EFX_LOOPBACK_KIND_MAC) || 931 (loopback_kind == EFX_LOOPBACK_KIND_ALL)) { 932 /* 933 * The "MAC" grouping has historically been used by drivers to 934 * mean loopbacks supported by on-chip hardware. Keep that 935 * meaning here, and include on-chip PHY layer loopbacks. 936 */ 937 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_DATA); 938 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GMAC); 939 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XGMII); 940 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XGXS); 941 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XAUI); 942 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GMII); 943 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SGMII); 944 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XGBR); 945 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XFI); 946 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XAUI_FAR); 947 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GMII_FAR); 948 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SGMII_FAR); 949 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XFI_FAR); 950 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PMA_INT); 951 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SD_NEAR); 952 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SD_FAR); 953 } 954 955 if ((loopback_kind == EFX_LOOPBACK_KIND_PHY) || 956 (loopback_kind == EFX_LOOPBACK_KIND_ALL)) { 957 /* 958 * The "PHY" grouping has historically been used by drivers to 959 * mean loopbacks supported by off-chip hardware. Keep that 960 * meaning here. 961 */ 962 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GPHY); 963 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PHY_XS); 964 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PCS); 965 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PMA_PMD); 966 } 967 968 *maskp = mask; 969 } 970 971 __checkReturn efx_rc_t 972 efx_mcdi_get_loopback_modes( 973 __in efx_nic_t *enp) 974 { 975 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); 976 efx_mcdi_req_t req; 977 uint8_t payload[MAX(MC_CMD_GET_LOOPBACK_MODES_IN_LEN, 978 MC_CMD_GET_LOOPBACK_MODES_OUT_LEN)]; 979 efx_qword_t mask; 980 efx_qword_t modes; 981 efx_rc_t rc; 982 983 (void) memset(payload, 0, sizeof (payload)); 984 req.emr_cmd = MC_CMD_GET_LOOPBACK_MODES; 985 req.emr_in_buf = payload; 986 req.emr_in_length = MC_CMD_GET_LOOPBACK_MODES_IN_LEN; 987 req.emr_out_buf = payload; 988 req.emr_out_length = MC_CMD_GET_LOOPBACK_MODES_OUT_LEN; 989 990 efx_mcdi_execute(enp, &req); 991 992 if (req.emr_rc != 0) { 993 rc = req.emr_rc; 994 goto fail1; 995 } 996 997 if (req.emr_out_length_used < 998 MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_OFST + 999 MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LEN) { 1000 rc = EMSGSIZE; 1001 goto fail2; 1002 } 1003 1004 /* 1005 * We assert the MC_CMD_LOOPBACK and EFX_LOOPBACK namespaces agree 1006 * in efx_loopback_mask() and in siena_phy.c:siena_phy_get_link(). 1007 */ 1008 efx_loopback_mask(EFX_LOOPBACK_KIND_ALL, &mask); 1009 1010 EFX_AND_QWORD(mask, 1011 *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_SUGGESTED)); 1012 1013 modes = *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_100M); 1014 EFX_AND_QWORD(modes, mask); 1015 encp->enc_loopback_types[EFX_LINK_100FDX] = modes; 1016 1017 modes = *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_1G); 1018 EFX_AND_QWORD(modes, mask); 1019 encp->enc_loopback_types[EFX_LINK_1000FDX] = modes; 1020 1021 modes = *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_10G); 1022 EFX_AND_QWORD(modes, mask); 1023 encp->enc_loopback_types[EFX_LINK_10000FDX] = modes; 1024 1025 if (req.emr_out_length_used >= 1026 MC_CMD_GET_LOOPBACK_MODES_OUT_40G_OFST + 1027 MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LEN) { 1028 /* Response includes 40G loopback modes */ 1029 modes = 1030 *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_40G); 1031 EFX_AND_QWORD(modes, mask); 1032 encp->enc_loopback_types[EFX_LINK_40000FDX] = modes; 1033 } 1034 1035 EFX_ZERO_QWORD(modes); 1036 EFX_SET_QWORD_BIT(modes, EFX_LOOPBACK_OFF); 1037 EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_100FDX]); 1038 EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_1000FDX]); 1039 EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_10000FDX]); 1040 EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_40000FDX]); 1041 encp->enc_loopback_types[EFX_LINK_UNKNOWN] = modes; 1042 1043 return (0); 1044 1045 fail2: 1046 EFSYS_PROBE(fail2); 1047 fail1: 1048 EFSYS_PROBE1(fail1, efx_rc_t, rc); 1049 1050 return (rc); 1051 } 1052 1053 #endif /* EFSYS_OPT_LOOPBACK */ 1054