1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2007-2016 Solarflare Communications Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 18 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 26 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * The views and conclusions contained in the software and documentation are 29 * those of the authors and should not be interpreted as representing official 30 * policies, either expressed or implied, of the FreeBSD Project. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 #include "efx.h" 37 #include "efx_impl.h" 38 39 40 #if EFSYS_OPT_SIENA 41 42 static __checkReturn efx_rc_t 43 siena_intr_init( 44 __in efx_nic_t *enp, 45 __in efx_intr_type_t type, 46 __in efsys_mem_t *esmp); 47 48 static void 49 siena_intr_enable( 50 __in efx_nic_t *enp); 51 52 static void 53 siena_intr_disable( 54 __in efx_nic_t *enp); 55 56 static void 57 siena_intr_disable_unlocked( 58 __in efx_nic_t *enp); 59 60 static __checkReturn efx_rc_t 61 siena_intr_trigger( 62 __in efx_nic_t *enp, 63 __in unsigned int level); 64 65 static void 66 siena_intr_fini( 67 __in efx_nic_t *enp); 68 69 static void 70 siena_intr_status_line( 71 __in efx_nic_t *enp, 72 __out boolean_t *fatalp, 73 __out uint32_t *qmaskp); 74 75 static void 76 siena_intr_status_message( 77 __in efx_nic_t *enp, 78 __in unsigned int message, 79 __out boolean_t *fatalp); 80 81 static void 82 siena_intr_fatal( 83 __in efx_nic_t *enp); 84 85 static __checkReturn boolean_t 86 siena_intr_check_fatal( 87 __in efx_nic_t *enp); 88 89 90 #endif /* EFSYS_OPT_SIENA */ 91 92 93 #if EFSYS_OPT_SIENA 94 static const efx_intr_ops_t __efx_intr_siena_ops = { 95 siena_intr_init, /* eio_init */ 96 siena_intr_enable, /* eio_enable */ 97 siena_intr_disable, /* eio_disable */ 98 siena_intr_disable_unlocked, /* eio_disable_unlocked */ 99 siena_intr_trigger, /* eio_trigger */ 100 siena_intr_status_line, /* eio_status_line */ 101 siena_intr_status_message, /* eio_status_message */ 102 siena_intr_fatal, /* eio_fatal */ 103 siena_intr_fini, /* eio_fini */ 104 }; 105 #endif /* EFSYS_OPT_SIENA */ 106 107 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 108 static const efx_intr_ops_t __efx_intr_ef10_ops = { 109 ef10_intr_init, /* eio_init */ 110 ef10_intr_enable, /* eio_enable */ 111 ef10_intr_disable, /* eio_disable */ 112 ef10_intr_disable_unlocked, /* eio_disable_unlocked */ 113 ef10_intr_trigger, /* eio_trigger */ 114 ef10_intr_status_line, /* eio_status_line */ 115 ef10_intr_status_message, /* eio_status_message */ 116 ef10_intr_fatal, /* eio_fatal */ 117 ef10_intr_fini, /* eio_fini */ 118 }; 119 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */ 120 121 __checkReturn efx_rc_t 122 efx_intr_init( 123 __in efx_nic_t *enp, 124 __in efx_intr_type_t type, 125 __in_opt efsys_mem_t *esmp) 126 { 127 efx_intr_t *eip = &(enp->en_intr); 128 const efx_intr_ops_t *eiop; 129 efx_rc_t rc; 130 131 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 132 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC); 133 134 if (enp->en_mod_flags & EFX_MOD_INTR) { 135 rc = EINVAL; 136 goto fail1; 137 } 138 139 eip->ei_esmp = esmp; 140 eip->ei_type = type; 141 eip->ei_level = 0; 142 143 enp->en_mod_flags |= EFX_MOD_INTR; 144 145 switch (enp->en_family) { 146 #if EFSYS_OPT_SIENA 147 case EFX_FAMILY_SIENA: 148 eiop = &__efx_intr_siena_ops; 149 break; 150 #endif /* EFSYS_OPT_SIENA */ 151 152 #if EFSYS_OPT_HUNTINGTON 153 case EFX_FAMILY_HUNTINGTON: 154 eiop = &__efx_intr_ef10_ops; 155 break; 156 #endif /* EFSYS_OPT_HUNTINGTON */ 157 158 #if EFSYS_OPT_MEDFORD 159 case EFX_FAMILY_MEDFORD: 160 eiop = &__efx_intr_ef10_ops; 161 break; 162 #endif /* EFSYS_OPT_MEDFORD */ 163 164 #if EFSYS_OPT_MEDFORD2 165 case EFX_FAMILY_MEDFORD2: 166 eiop = &__efx_intr_ef10_ops; 167 break; 168 #endif /* EFSYS_OPT_MEDFORD2 */ 169 170 default: 171 EFSYS_ASSERT(B_FALSE); 172 rc = ENOTSUP; 173 goto fail2; 174 } 175 176 if ((rc = eiop->eio_init(enp, type, esmp)) != 0) 177 goto fail3; 178 179 eip->ei_eiop = eiop; 180 181 return (0); 182 183 fail3: 184 EFSYS_PROBE(fail3); 185 fail2: 186 EFSYS_PROBE(fail2); 187 fail1: 188 EFSYS_PROBE1(fail1, efx_rc_t, rc); 189 190 return (rc); 191 } 192 193 void 194 efx_intr_fini( 195 __in efx_nic_t *enp) 196 { 197 efx_intr_t *eip = &(enp->en_intr); 198 const efx_intr_ops_t *eiop = eip->ei_eiop; 199 200 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 201 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC); 202 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR); 203 204 eiop->eio_fini(enp); 205 206 enp->en_mod_flags &= ~EFX_MOD_INTR; 207 } 208 209 void 210 efx_intr_enable( 211 __in efx_nic_t *enp) 212 { 213 efx_intr_t *eip = &(enp->en_intr); 214 const efx_intr_ops_t *eiop = eip->ei_eiop; 215 216 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 217 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR); 218 219 eiop->eio_enable(enp); 220 } 221 222 void 223 efx_intr_disable( 224 __in efx_nic_t *enp) 225 { 226 efx_intr_t *eip = &(enp->en_intr); 227 const efx_intr_ops_t *eiop = eip->ei_eiop; 228 229 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 230 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR); 231 232 eiop->eio_disable(enp); 233 } 234 235 void 236 efx_intr_disable_unlocked( 237 __in efx_nic_t *enp) 238 { 239 efx_intr_t *eip = &(enp->en_intr); 240 const efx_intr_ops_t *eiop = eip->ei_eiop; 241 242 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 243 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR); 244 245 eiop->eio_disable_unlocked(enp); 246 } 247 248 249 __checkReturn efx_rc_t 250 efx_intr_trigger( 251 __in efx_nic_t *enp, 252 __in unsigned int level) 253 { 254 efx_intr_t *eip = &(enp->en_intr); 255 const efx_intr_ops_t *eiop = eip->ei_eiop; 256 257 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 258 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR); 259 260 return (eiop->eio_trigger(enp, level)); 261 } 262 263 void 264 efx_intr_status_line( 265 __in efx_nic_t *enp, 266 __out boolean_t *fatalp, 267 __out uint32_t *qmaskp) 268 { 269 efx_intr_t *eip = &(enp->en_intr); 270 const efx_intr_ops_t *eiop = eip->ei_eiop; 271 272 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 273 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR); 274 275 eiop->eio_status_line(enp, fatalp, qmaskp); 276 } 277 278 void 279 efx_intr_status_message( 280 __in efx_nic_t *enp, 281 __in unsigned int message, 282 __out boolean_t *fatalp) 283 { 284 efx_intr_t *eip = &(enp->en_intr); 285 const efx_intr_ops_t *eiop = eip->ei_eiop; 286 287 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 288 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR); 289 290 eiop->eio_status_message(enp, message, fatalp); 291 } 292 293 void 294 efx_intr_fatal( 295 __in efx_nic_t *enp) 296 { 297 efx_intr_t *eip = &(enp->en_intr); 298 const efx_intr_ops_t *eiop = eip->ei_eiop; 299 300 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 301 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR); 302 303 eiop->eio_fatal(enp); 304 } 305 306 307 /* ************************************************************************* */ 308 /* ************************************************************************* */ 309 /* ************************************************************************* */ 310 311 #if EFSYS_OPT_SIENA 312 313 static __checkReturn efx_rc_t 314 siena_intr_init( 315 __in efx_nic_t *enp, 316 __in efx_intr_type_t type, 317 __in efsys_mem_t *esmp) 318 { 319 efx_intr_t *eip = &(enp->en_intr); 320 efx_oword_t oword; 321 efx_rc_t rc; 322 323 if ((esmp == NULL) || (EFSYS_MEM_SIZE(esmp) < EFX_INTR_SIZE)) { 324 rc = EINVAL; 325 goto fail1; 326 } 327 328 /* 329 * bug17213 workaround. 330 * 331 * Under legacy interrupts, don't share a level between fatal 332 * interrupts and event queue interrupts. Under MSI-X, they 333 * must share, or we won't get an interrupt. 334 */ 335 if (enp->en_family == EFX_FAMILY_SIENA && 336 eip->ei_type == EFX_INTR_LINE) 337 eip->ei_level = 0x1f; 338 else 339 eip->ei_level = 0; 340 341 /* Enable all the genuinely fatal interrupts */ 342 EFX_SET_OWORD(oword); 343 EFX_SET_OWORD_FIELD(oword, FRF_AZ_ILL_ADR_INT_KER_EN, 0); 344 EFX_SET_OWORD_FIELD(oword, FRF_AZ_RBUF_OWN_INT_KER_EN, 0); 345 EFX_SET_OWORD_FIELD(oword, FRF_AZ_TBUF_OWN_INT_KER_EN, 0); 346 if (enp->en_family >= EFX_FAMILY_SIENA) 347 EFX_SET_OWORD_FIELD(oword, FRF_CZ_SRAM_PERR_INT_P_KER_EN, 0); 348 EFX_BAR_WRITEO(enp, FR_AZ_FATAL_INTR_REG_KER, &oword); 349 350 /* Set up the interrupt address register */ 351 EFX_POPULATE_OWORD_3(oword, 352 FRF_AZ_NORM_INT_VEC_DIS_KER, (type == EFX_INTR_MESSAGE) ? 1 : 0, 353 FRF_AZ_INT_ADR_KER_DW0, EFSYS_MEM_ADDR(esmp) & 0xffffffff, 354 FRF_AZ_INT_ADR_KER_DW1, EFSYS_MEM_ADDR(esmp) >> 32); 355 EFX_BAR_WRITEO(enp, FR_AZ_INT_ADR_REG_KER, &oword); 356 357 return (0); 358 359 fail1: 360 EFSYS_PROBE1(fail1, efx_rc_t, rc); 361 362 return (rc); 363 } 364 365 static void 366 siena_intr_enable( 367 __in efx_nic_t *enp) 368 { 369 efx_intr_t *eip = &(enp->en_intr); 370 efx_oword_t oword; 371 372 EFX_BAR_READO(enp, FR_AZ_INT_EN_REG_KER, &oword); 373 374 EFX_SET_OWORD_FIELD(oword, FRF_AZ_KER_INT_LEVE_SEL, eip->ei_level); 375 EFX_SET_OWORD_FIELD(oword, FRF_AZ_DRV_INT_EN_KER, 1); 376 EFX_BAR_WRITEO(enp, FR_AZ_INT_EN_REG_KER, &oword); 377 } 378 379 static void 380 siena_intr_disable( 381 __in efx_nic_t *enp) 382 { 383 efx_oword_t oword; 384 385 EFX_BAR_READO(enp, FR_AZ_INT_EN_REG_KER, &oword); 386 EFX_SET_OWORD_FIELD(oword, FRF_AZ_DRV_INT_EN_KER, 0); 387 EFX_BAR_WRITEO(enp, FR_AZ_INT_EN_REG_KER, &oword); 388 389 EFSYS_SPIN(10); 390 } 391 392 static void 393 siena_intr_disable_unlocked( 394 __in efx_nic_t *enp) 395 { 396 efx_oword_t oword; 397 398 EFSYS_BAR_READO(enp->en_esbp, FR_AZ_INT_EN_REG_KER_OFST, 399 &oword, B_FALSE); 400 EFX_SET_OWORD_FIELD(oword, FRF_AZ_DRV_INT_EN_KER, 0); 401 EFSYS_BAR_WRITEO(enp->en_esbp, FR_AZ_INT_EN_REG_KER_OFST, 402 &oword, B_FALSE); 403 } 404 405 static __checkReturn efx_rc_t 406 siena_intr_trigger( 407 __in efx_nic_t *enp, 408 __in unsigned int level) 409 { 410 efx_intr_t *eip = &(enp->en_intr); 411 efx_oword_t oword; 412 unsigned int count; 413 uint32_t sel; 414 efx_rc_t rc; 415 416 /* bug16757: No event queues can be initialized */ 417 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV)); 418 419 if (level >= EFX_NINTR_SIENA) { 420 rc = EINVAL; 421 goto fail1; 422 } 423 424 if (level > EFX_MASK32(FRF_AZ_KER_INT_LEVE_SEL)) 425 return (ENOTSUP); /* avoid EFSYS_PROBE() */ 426 427 sel = level; 428 429 /* Trigger a test interrupt */ 430 EFX_BAR_READO(enp, FR_AZ_INT_EN_REG_KER, &oword); 431 EFX_SET_OWORD_FIELD(oword, FRF_AZ_KER_INT_LEVE_SEL, sel); 432 EFX_SET_OWORD_FIELD(oword, FRF_AZ_KER_INT_KER, 1); 433 EFX_BAR_WRITEO(enp, FR_AZ_INT_EN_REG_KER, &oword); 434 435 /* 436 * Wait up to 100ms for the interrupt to be raised before restoring 437 * KER_INT_LEVE_SEL. Ignore a failure to raise (the caller will 438 * observe this soon enough anyway), but always reset KER_INT_LEVE_SEL 439 */ 440 count = 0; 441 do { 442 EFSYS_SPIN(100); /* 100us */ 443 444 EFX_BAR_READO(enp, FR_AZ_INT_EN_REG_KER, &oword); 445 } while (EFX_OWORD_FIELD(oword, FRF_AZ_KER_INT_KER) && ++count < 1000); 446 447 EFX_SET_OWORD_FIELD(oword, FRF_AZ_KER_INT_LEVE_SEL, eip->ei_level); 448 EFX_BAR_WRITEO(enp, FR_AZ_INT_EN_REG_KER, &oword); 449 450 return (0); 451 452 fail1: 453 EFSYS_PROBE1(fail1, efx_rc_t, rc); 454 455 return (rc); 456 } 457 458 static __checkReturn boolean_t 459 siena_intr_check_fatal( 460 __in efx_nic_t *enp) 461 { 462 efx_intr_t *eip = &(enp->en_intr); 463 efsys_mem_t *esmp = eip->ei_esmp; 464 efx_oword_t oword; 465 466 /* Read the syndrome */ 467 EFSYS_MEM_READO(esmp, 0, &oword); 468 469 if (EFX_OWORD_FIELD(oword, FSF_AZ_NET_IVEC_FATAL_INT) != 0) { 470 EFSYS_PROBE(fatal); 471 472 /* Clear the fatal interrupt condition */ 473 EFX_SET_OWORD_FIELD(oword, FSF_AZ_NET_IVEC_FATAL_INT, 0); 474 EFSYS_MEM_WRITEO(esmp, 0, &oword); 475 476 return (B_TRUE); 477 } 478 479 return (B_FALSE); 480 } 481 482 static void 483 siena_intr_status_line( 484 __in efx_nic_t *enp, 485 __out boolean_t *fatalp, 486 __out uint32_t *qmaskp) 487 { 488 efx_intr_t *eip = &(enp->en_intr); 489 efx_dword_t dword; 490 491 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 492 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR); 493 494 /* 495 * Read the queue mask and implicitly acknowledge the 496 * interrupt. 497 */ 498 EFX_BAR_READD(enp, FR_BZ_INT_ISR0_REG, &dword, B_FALSE); 499 *qmaskp = EFX_DWORD_FIELD(dword, EFX_DWORD_0); 500 501 EFSYS_PROBE1(qmask, uint32_t, *qmaskp); 502 503 if (*qmaskp & (1U << eip->ei_level)) 504 *fatalp = siena_intr_check_fatal(enp); 505 else 506 *fatalp = B_FALSE; 507 } 508 509 static void 510 siena_intr_status_message( 511 __in efx_nic_t *enp, 512 __in unsigned int message, 513 __out boolean_t *fatalp) 514 { 515 efx_intr_t *eip = &(enp->en_intr); 516 517 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 518 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR); 519 520 if (message == eip->ei_level) 521 *fatalp = siena_intr_check_fatal(enp); 522 else 523 *fatalp = B_FALSE; 524 } 525 526 527 static void 528 siena_intr_fatal( 529 __in efx_nic_t *enp) 530 { 531 #if EFSYS_OPT_DECODE_INTR_FATAL 532 efx_oword_t fatal; 533 efx_oword_t mem_per; 534 535 EFX_BAR_READO(enp, FR_AZ_FATAL_INTR_REG_KER, &fatal); 536 EFX_ZERO_OWORD(mem_per); 537 538 if (EFX_OWORD_FIELD(fatal, FRF_AZ_SRM_PERR_INT_KER) != 0 || 539 EFX_OWORD_FIELD(fatal, FRF_AZ_MEM_PERR_INT_KER) != 0) 540 EFX_BAR_READO(enp, FR_AZ_MEM_STAT_REG, &mem_per); 541 542 if (EFX_OWORD_FIELD(fatal, FRF_AZ_SRAM_OOB_INT_KER) != 0) 543 EFSYS_ERR(enp->en_esip, EFX_ERR_SRAM_OOB, 0, 0); 544 545 if (EFX_OWORD_FIELD(fatal, FRF_AZ_BUFID_DC_OOB_INT_KER) != 0) 546 EFSYS_ERR(enp->en_esip, EFX_ERR_BUFID_DC_OOB, 0, 0); 547 548 if (EFX_OWORD_FIELD(fatal, FRF_AZ_MEM_PERR_INT_KER) != 0) 549 EFSYS_ERR(enp->en_esip, EFX_ERR_MEM_PERR, 550 EFX_OWORD_FIELD(mem_per, EFX_DWORD_0), 551 EFX_OWORD_FIELD(mem_per, EFX_DWORD_1)); 552 553 if (EFX_OWORD_FIELD(fatal, FRF_AZ_RBUF_OWN_INT_KER) != 0) 554 EFSYS_ERR(enp->en_esip, EFX_ERR_RBUF_OWN, 0, 0); 555 556 if (EFX_OWORD_FIELD(fatal, FRF_AZ_TBUF_OWN_INT_KER) != 0) 557 EFSYS_ERR(enp->en_esip, EFX_ERR_TBUF_OWN, 0, 0); 558 559 if (EFX_OWORD_FIELD(fatal, FRF_AZ_RDESCQ_OWN_INT_KER) != 0) 560 EFSYS_ERR(enp->en_esip, EFX_ERR_RDESQ_OWN, 0, 0); 561 562 if (EFX_OWORD_FIELD(fatal, FRF_AZ_TDESCQ_OWN_INT_KER) != 0) 563 EFSYS_ERR(enp->en_esip, EFX_ERR_TDESQ_OWN, 0, 0); 564 565 if (EFX_OWORD_FIELD(fatal, FRF_AZ_EVQ_OWN_INT_KER) != 0) 566 EFSYS_ERR(enp->en_esip, EFX_ERR_EVQ_OWN, 0, 0); 567 568 if (EFX_OWORD_FIELD(fatal, FRF_AZ_EVF_OFLO_INT_KER) != 0) 569 EFSYS_ERR(enp->en_esip, EFX_ERR_EVFF_OFLO, 0, 0); 570 571 if (EFX_OWORD_FIELD(fatal, FRF_AZ_ILL_ADR_INT_KER) != 0) 572 EFSYS_ERR(enp->en_esip, EFX_ERR_ILL_ADDR, 0, 0); 573 574 if (EFX_OWORD_FIELD(fatal, FRF_AZ_SRM_PERR_INT_KER) != 0) 575 EFSYS_ERR(enp->en_esip, EFX_ERR_SRAM_PERR, 576 EFX_OWORD_FIELD(mem_per, EFX_DWORD_0), 577 EFX_OWORD_FIELD(mem_per, EFX_DWORD_1)); 578 #else 579 EFSYS_ASSERT(0); 580 #endif 581 } 582 583 static void 584 siena_intr_fini( 585 __in efx_nic_t *enp) 586 { 587 efx_oword_t oword; 588 589 /* Clear the interrupt address register */ 590 EFX_ZERO_OWORD(oword); 591 EFX_BAR_WRITEO(enp, FR_AZ_INT_ADR_REG_KER, &oword); 592 } 593 594 #endif /* EFSYS_OPT_SIENA */ 595