1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2007-2016 Solarflare Communications Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 18 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 26 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * The views and conclusions contained in the software and documentation are 29 * those of the authors and should not be interpreted as representing official 30 * policies, either expressed or implied, of the FreeBSD Project. 31 */ 32 33 #include <sys/cdefs.h> 34 #include "efx.h" 35 #include "efx_impl.h" 36 37 #if EFSYS_OPT_SIENA 38 39 static __checkReturn efx_rc_t 40 siena_intr_init( 41 __in efx_nic_t *enp, 42 __in efx_intr_type_t type, 43 __in efsys_mem_t *esmp); 44 45 static void 46 siena_intr_enable( 47 __in efx_nic_t *enp); 48 49 static void 50 siena_intr_disable( 51 __in efx_nic_t *enp); 52 53 static void 54 siena_intr_disable_unlocked( 55 __in efx_nic_t *enp); 56 57 static __checkReturn efx_rc_t 58 siena_intr_trigger( 59 __in efx_nic_t *enp, 60 __in unsigned int level); 61 62 static void 63 siena_intr_fini( 64 __in efx_nic_t *enp); 65 66 static void 67 siena_intr_status_line( 68 __in efx_nic_t *enp, 69 __out boolean_t *fatalp, 70 __out uint32_t *qmaskp); 71 72 static void 73 siena_intr_status_message( 74 __in efx_nic_t *enp, 75 __in unsigned int message, 76 __out boolean_t *fatalp); 77 78 static void 79 siena_intr_fatal( 80 __in efx_nic_t *enp); 81 82 static __checkReturn boolean_t 83 siena_intr_check_fatal( 84 __in efx_nic_t *enp); 85 86 #endif /* EFSYS_OPT_SIENA */ 87 88 #if EFSYS_OPT_SIENA 89 static const efx_intr_ops_t __efx_intr_siena_ops = { 90 siena_intr_init, /* eio_init */ 91 siena_intr_enable, /* eio_enable */ 92 siena_intr_disable, /* eio_disable */ 93 siena_intr_disable_unlocked, /* eio_disable_unlocked */ 94 siena_intr_trigger, /* eio_trigger */ 95 siena_intr_status_line, /* eio_status_line */ 96 siena_intr_status_message, /* eio_status_message */ 97 siena_intr_fatal, /* eio_fatal */ 98 siena_intr_fini, /* eio_fini */ 99 }; 100 #endif /* EFSYS_OPT_SIENA */ 101 102 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 103 static const efx_intr_ops_t __efx_intr_ef10_ops = { 104 ef10_intr_init, /* eio_init */ 105 ef10_intr_enable, /* eio_enable */ 106 ef10_intr_disable, /* eio_disable */ 107 ef10_intr_disable_unlocked, /* eio_disable_unlocked */ 108 ef10_intr_trigger, /* eio_trigger */ 109 ef10_intr_status_line, /* eio_status_line */ 110 ef10_intr_status_message, /* eio_status_message */ 111 ef10_intr_fatal, /* eio_fatal */ 112 ef10_intr_fini, /* eio_fini */ 113 }; 114 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */ 115 116 __checkReturn efx_rc_t 117 efx_intr_init( 118 __in efx_nic_t *enp, 119 __in efx_intr_type_t type, 120 __in_opt efsys_mem_t *esmp) 121 { 122 efx_intr_t *eip = &(enp->en_intr); 123 const efx_intr_ops_t *eiop; 124 efx_rc_t rc; 125 126 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 127 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC); 128 129 if (enp->en_mod_flags & EFX_MOD_INTR) { 130 rc = EINVAL; 131 goto fail1; 132 } 133 134 eip->ei_esmp = esmp; 135 eip->ei_type = type; 136 eip->ei_level = 0; 137 138 enp->en_mod_flags |= EFX_MOD_INTR; 139 140 switch (enp->en_family) { 141 #if EFSYS_OPT_SIENA 142 case EFX_FAMILY_SIENA: 143 eiop = &__efx_intr_siena_ops; 144 break; 145 #endif /* EFSYS_OPT_SIENA */ 146 147 #if EFSYS_OPT_HUNTINGTON 148 case EFX_FAMILY_HUNTINGTON: 149 eiop = &__efx_intr_ef10_ops; 150 break; 151 #endif /* EFSYS_OPT_HUNTINGTON */ 152 153 #if EFSYS_OPT_MEDFORD 154 case EFX_FAMILY_MEDFORD: 155 eiop = &__efx_intr_ef10_ops; 156 break; 157 #endif /* EFSYS_OPT_MEDFORD */ 158 159 #if EFSYS_OPT_MEDFORD2 160 case EFX_FAMILY_MEDFORD2: 161 eiop = &__efx_intr_ef10_ops; 162 break; 163 #endif /* EFSYS_OPT_MEDFORD2 */ 164 165 default: 166 EFSYS_ASSERT(B_FALSE); 167 rc = ENOTSUP; 168 goto fail2; 169 } 170 171 if ((rc = eiop->eio_init(enp, type, esmp)) != 0) 172 goto fail3; 173 174 eip->ei_eiop = eiop; 175 176 return (0); 177 178 fail3: 179 EFSYS_PROBE(fail3); 180 fail2: 181 EFSYS_PROBE(fail2); 182 fail1: 183 EFSYS_PROBE1(fail1, efx_rc_t, rc); 184 185 return (rc); 186 } 187 188 void 189 efx_intr_fini( 190 __in efx_nic_t *enp) 191 { 192 efx_intr_t *eip = &(enp->en_intr); 193 const efx_intr_ops_t *eiop = eip->ei_eiop; 194 195 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 196 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC); 197 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR); 198 199 eiop->eio_fini(enp); 200 201 enp->en_mod_flags &= ~EFX_MOD_INTR; 202 } 203 204 void 205 efx_intr_enable( 206 __in efx_nic_t *enp) 207 { 208 efx_intr_t *eip = &(enp->en_intr); 209 const efx_intr_ops_t *eiop = eip->ei_eiop; 210 211 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 212 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR); 213 214 eiop->eio_enable(enp); 215 } 216 217 void 218 efx_intr_disable( 219 __in efx_nic_t *enp) 220 { 221 efx_intr_t *eip = &(enp->en_intr); 222 const efx_intr_ops_t *eiop = eip->ei_eiop; 223 224 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 225 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR); 226 227 eiop->eio_disable(enp); 228 } 229 230 void 231 efx_intr_disable_unlocked( 232 __in efx_nic_t *enp) 233 { 234 efx_intr_t *eip = &(enp->en_intr); 235 const efx_intr_ops_t *eiop = eip->ei_eiop; 236 237 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 238 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR); 239 240 eiop->eio_disable_unlocked(enp); 241 } 242 243 __checkReturn efx_rc_t 244 efx_intr_trigger( 245 __in efx_nic_t *enp, 246 __in unsigned int level) 247 { 248 efx_intr_t *eip = &(enp->en_intr); 249 const efx_intr_ops_t *eiop = eip->ei_eiop; 250 251 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 252 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR); 253 254 return (eiop->eio_trigger(enp, level)); 255 } 256 257 void 258 efx_intr_status_line( 259 __in efx_nic_t *enp, 260 __out boolean_t *fatalp, 261 __out uint32_t *qmaskp) 262 { 263 efx_intr_t *eip = &(enp->en_intr); 264 const efx_intr_ops_t *eiop = eip->ei_eiop; 265 266 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 267 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR); 268 269 eiop->eio_status_line(enp, fatalp, qmaskp); 270 } 271 272 void 273 efx_intr_status_message( 274 __in efx_nic_t *enp, 275 __in unsigned int message, 276 __out boolean_t *fatalp) 277 { 278 efx_intr_t *eip = &(enp->en_intr); 279 const efx_intr_ops_t *eiop = eip->ei_eiop; 280 281 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 282 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR); 283 284 eiop->eio_status_message(enp, message, fatalp); 285 } 286 287 void 288 efx_intr_fatal( 289 __in efx_nic_t *enp) 290 { 291 efx_intr_t *eip = &(enp->en_intr); 292 const efx_intr_ops_t *eiop = eip->ei_eiop; 293 294 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 295 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR); 296 297 eiop->eio_fatal(enp); 298 } 299 300 /* ************************************************************************* */ 301 /* ************************************************************************* */ 302 /* ************************************************************************* */ 303 304 #if EFSYS_OPT_SIENA 305 306 static __checkReturn efx_rc_t 307 siena_intr_init( 308 __in efx_nic_t *enp, 309 __in efx_intr_type_t type, 310 __in efsys_mem_t *esmp) 311 { 312 efx_intr_t *eip = &(enp->en_intr); 313 efx_oword_t oword; 314 efx_rc_t rc; 315 316 if ((esmp == NULL) || (EFSYS_MEM_SIZE(esmp) < EFX_INTR_SIZE)) { 317 rc = EINVAL; 318 goto fail1; 319 } 320 321 /* 322 * bug17213 workaround. 323 * 324 * Under legacy interrupts, don't share a level between fatal 325 * interrupts and event queue interrupts. Under MSI-X, they 326 * must share, or we won't get an interrupt. 327 */ 328 if (enp->en_family == EFX_FAMILY_SIENA && 329 eip->ei_type == EFX_INTR_LINE) 330 eip->ei_level = 0x1f; 331 else 332 eip->ei_level = 0; 333 334 /* Enable all the genuinely fatal interrupts */ 335 EFX_SET_OWORD(oword); 336 EFX_SET_OWORD_FIELD(oword, FRF_AZ_ILL_ADR_INT_KER_EN, 0); 337 EFX_SET_OWORD_FIELD(oword, FRF_AZ_RBUF_OWN_INT_KER_EN, 0); 338 EFX_SET_OWORD_FIELD(oword, FRF_AZ_TBUF_OWN_INT_KER_EN, 0); 339 if (enp->en_family >= EFX_FAMILY_SIENA) 340 EFX_SET_OWORD_FIELD(oword, FRF_CZ_SRAM_PERR_INT_P_KER_EN, 0); 341 EFX_BAR_WRITEO(enp, FR_AZ_FATAL_INTR_REG_KER, &oword); 342 343 /* Set up the interrupt address register */ 344 EFX_POPULATE_OWORD_3(oword, 345 FRF_AZ_NORM_INT_VEC_DIS_KER, (type == EFX_INTR_MESSAGE) ? 1 : 0, 346 FRF_AZ_INT_ADR_KER_DW0, EFSYS_MEM_ADDR(esmp) & 0xffffffff, 347 FRF_AZ_INT_ADR_KER_DW1, EFSYS_MEM_ADDR(esmp) >> 32); 348 EFX_BAR_WRITEO(enp, FR_AZ_INT_ADR_REG_KER, &oword); 349 350 return (0); 351 352 fail1: 353 EFSYS_PROBE1(fail1, efx_rc_t, rc); 354 355 return (rc); 356 } 357 358 static void 359 siena_intr_enable( 360 __in efx_nic_t *enp) 361 { 362 efx_intr_t *eip = &(enp->en_intr); 363 efx_oword_t oword; 364 365 EFX_BAR_READO(enp, FR_AZ_INT_EN_REG_KER, &oword); 366 367 EFX_SET_OWORD_FIELD(oword, FRF_AZ_KER_INT_LEVE_SEL, eip->ei_level); 368 EFX_SET_OWORD_FIELD(oword, FRF_AZ_DRV_INT_EN_KER, 1); 369 EFX_BAR_WRITEO(enp, FR_AZ_INT_EN_REG_KER, &oword); 370 } 371 372 static void 373 siena_intr_disable( 374 __in efx_nic_t *enp) 375 { 376 efx_oword_t oword; 377 378 EFX_BAR_READO(enp, FR_AZ_INT_EN_REG_KER, &oword); 379 EFX_SET_OWORD_FIELD(oword, FRF_AZ_DRV_INT_EN_KER, 0); 380 EFX_BAR_WRITEO(enp, FR_AZ_INT_EN_REG_KER, &oword); 381 382 EFSYS_SPIN(10); 383 } 384 385 static void 386 siena_intr_disable_unlocked( 387 __in efx_nic_t *enp) 388 { 389 efx_oword_t oword; 390 391 EFSYS_BAR_READO(enp->en_esbp, FR_AZ_INT_EN_REG_KER_OFST, 392 &oword, B_FALSE); 393 EFX_SET_OWORD_FIELD(oword, FRF_AZ_DRV_INT_EN_KER, 0); 394 EFSYS_BAR_WRITEO(enp->en_esbp, FR_AZ_INT_EN_REG_KER_OFST, 395 &oword, B_FALSE); 396 } 397 398 static __checkReturn efx_rc_t 399 siena_intr_trigger( 400 __in efx_nic_t *enp, 401 __in unsigned int level) 402 { 403 efx_intr_t *eip = &(enp->en_intr); 404 efx_oword_t oword; 405 unsigned int count; 406 uint32_t sel; 407 efx_rc_t rc; 408 409 /* bug16757: No event queues can be initialized */ 410 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV)); 411 412 if (level >= EFX_NINTR_SIENA) { 413 rc = EINVAL; 414 goto fail1; 415 } 416 417 if (level > EFX_MASK32(FRF_AZ_KER_INT_LEVE_SEL)) 418 return (ENOTSUP); /* avoid EFSYS_PROBE() */ 419 420 sel = level; 421 422 /* Trigger a test interrupt */ 423 EFX_BAR_READO(enp, FR_AZ_INT_EN_REG_KER, &oword); 424 EFX_SET_OWORD_FIELD(oword, FRF_AZ_KER_INT_LEVE_SEL, sel); 425 EFX_SET_OWORD_FIELD(oword, FRF_AZ_KER_INT_KER, 1); 426 EFX_BAR_WRITEO(enp, FR_AZ_INT_EN_REG_KER, &oword); 427 428 /* 429 * Wait up to 100ms for the interrupt to be raised before restoring 430 * KER_INT_LEVE_SEL. Ignore a failure to raise (the caller will 431 * observe this soon enough anyway), but always reset KER_INT_LEVE_SEL 432 */ 433 count = 0; 434 do { 435 EFSYS_SPIN(100); /* 100us */ 436 437 EFX_BAR_READO(enp, FR_AZ_INT_EN_REG_KER, &oword); 438 } while (EFX_OWORD_FIELD(oword, FRF_AZ_KER_INT_KER) && ++count < 1000); 439 440 EFX_SET_OWORD_FIELD(oword, FRF_AZ_KER_INT_LEVE_SEL, eip->ei_level); 441 EFX_BAR_WRITEO(enp, FR_AZ_INT_EN_REG_KER, &oword); 442 443 return (0); 444 445 fail1: 446 EFSYS_PROBE1(fail1, efx_rc_t, rc); 447 448 return (rc); 449 } 450 451 static __checkReturn boolean_t 452 siena_intr_check_fatal( 453 __in efx_nic_t *enp) 454 { 455 efx_intr_t *eip = &(enp->en_intr); 456 efsys_mem_t *esmp = eip->ei_esmp; 457 efx_oword_t oword; 458 459 /* Read the syndrome */ 460 EFSYS_MEM_READO(esmp, 0, &oword); 461 462 if (EFX_OWORD_FIELD(oword, FSF_AZ_NET_IVEC_FATAL_INT) != 0) { 463 EFSYS_PROBE(fatal); 464 465 /* Clear the fatal interrupt condition */ 466 EFX_SET_OWORD_FIELD(oword, FSF_AZ_NET_IVEC_FATAL_INT, 0); 467 EFSYS_MEM_WRITEO(esmp, 0, &oword); 468 469 return (B_TRUE); 470 } 471 472 return (B_FALSE); 473 } 474 475 static void 476 siena_intr_status_line( 477 __in efx_nic_t *enp, 478 __out boolean_t *fatalp, 479 __out uint32_t *qmaskp) 480 { 481 efx_intr_t *eip = &(enp->en_intr); 482 efx_dword_t dword; 483 484 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 485 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR); 486 487 /* 488 * Read the queue mask and implicitly acknowledge the 489 * interrupt. 490 */ 491 EFX_BAR_READD(enp, FR_BZ_INT_ISR0_REG, &dword, B_FALSE); 492 *qmaskp = EFX_DWORD_FIELD(dword, EFX_DWORD_0); 493 494 EFSYS_PROBE1(qmask, uint32_t, *qmaskp); 495 496 if (*qmaskp & (1U << eip->ei_level)) 497 *fatalp = siena_intr_check_fatal(enp); 498 else 499 *fatalp = B_FALSE; 500 } 501 502 static void 503 siena_intr_status_message( 504 __in efx_nic_t *enp, 505 __in unsigned int message, 506 __out boolean_t *fatalp) 507 { 508 efx_intr_t *eip = &(enp->en_intr); 509 510 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 511 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR); 512 513 if (message == eip->ei_level) 514 *fatalp = siena_intr_check_fatal(enp); 515 else 516 *fatalp = B_FALSE; 517 } 518 519 static void 520 siena_intr_fatal( 521 __in efx_nic_t *enp) 522 { 523 #if EFSYS_OPT_DECODE_INTR_FATAL 524 efx_oword_t fatal; 525 efx_oword_t mem_per; 526 527 EFX_BAR_READO(enp, FR_AZ_FATAL_INTR_REG_KER, &fatal); 528 EFX_ZERO_OWORD(mem_per); 529 530 if (EFX_OWORD_FIELD(fatal, FRF_AZ_SRM_PERR_INT_KER) != 0 || 531 EFX_OWORD_FIELD(fatal, FRF_AZ_MEM_PERR_INT_KER) != 0) 532 EFX_BAR_READO(enp, FR_AZ_MEM_STAT_REG, &mem_per); 533 534 if (EFX_OWORD_FIELD(fatal, FRF_AZ_SRAM_OOB_INT_KER) != 0) 535 EFSYS_ERR(enp->en_esip, EFX_ERR_SRAM_OOB, 0, 0); 536 537 if (EFX_OWORD_FIELD(fatal, FRF_AZ_BUFID_DC_OOB_INT_KER) != 0) 538 EFSYS_ERR(enp->en_esip, EFX_ERR_BUFID_DC_OOB, 0, 0); 539 540 if (EFX_OWORD_FIELD(fatal, FRF_AZ_MEM_PERR_INT_KER) != 0) 541 EFSYS_ERR(enp->en_esip, EFX_ERR_MEM_PERR, 542 EFX_OWORD_FIELD(mem_per, EFX_DWORD_0), 543 EFX_OWORD_FIELD(mem_per, EFX_DWORD_1)); 544 545 if (EFX_OWORD_FIELD(fatal, FRF_AZ_RBUF_OWN_INT_KER) != 0) 546 EFSYS_ERR(enp->en_esip, EFX_ERR_RBUF_OWN, 0, 0); 547 548 if (EFX_OWORD_FIELD(fatal, FRF_AZ_TBUF_OWN_INT_KER) != 0) 549 EFSYS_ERR(enp->en_esip, EFX_ERR_TBUF_OWN, 0, 0); 550 551 if (EFX_OWORD_FIELD(fatal, FRF_AZ_RDESCQ_OWN_INT_KER) != 0) 552 EFSYS_ERR(enp->en_esip, EFX_ERR_RDESQ_OWN, 0, 0); 553 554 if (EFX_OWORD_FIELD(fatal, FRF_AZ_TDESCQ_OWN_INT_KER) != 0) 555 EFSYS_ERR(enp->en_esip, EFX_ERR_TDESQ_OWN, 0, 0); 556 557 if (EFX_OWORD_FIELD(fatal, FRF_AZ_EVQ_OWN_INT_KER) != 0) 558 EFSYS_ERR(enp->en_esip, EFX_ERR_EVQ_OWN, 0, 0); 559 560 if (EFX_OWORD_FIELD(fatal, FRF_AZ_EVF_OFLO_INT_KER) != 0) 561 EFSYS_ERR(enp->en_esip, EFX_ERR_EVFF_OFLO, 0, 0); 562 563 if (EFX_OWORD_FIELD(fatal, FRF_AZ_ILL_ADR_INT_KER) != 0) 564 EFSYS_ERR(enp->en_esip, EFX_ERR_ILL_ADDR, 0, 0); 565 566 if (EFX_OWORD_FIELD(fatal, FRF_AZ_SRM_PERR_INT_KER) != 0) 567 EFSYS_ERR(enp->en_esip, EFX_ERR_SRAM_PERR, 568 EFX_OWORD_FIELD(mem_per, EFX_DWORD_0), 569 EFX_OWORD_FIELD(mem_per, EFX_DWORD_1)); 570 #else 571 EFSYS_ASSERT(0); 572 #endif 573 } 574 575 static void 576 siena_intr_fini( 577 __in efx_nic_t *enp) 578 { 579 efx_oword_t oword; 580 581 /* Clear the interrupt address register */ 582 EFX_ZERO_OWORD(oword); 583 EFX_BAR_WRITEO(enp, FR_AZ_INT_ADR_REG_KER, &oword); 584 } 585 586 #endif /* EFSYS_OPT_SIENA */ 587