1 /*- 2 * Copyright (c) 2007-2015 Solarflare Communications Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * The views and conclusions contained in the software and documentation are 27 * those of the authors and should not be interpreted as representing official 28 * policies, either expressed or implied, of the FreeBSD Project. 29 * 30 * $FreeBSD$ 31 */ 32 33 #ifndef _SYS_EFX_IMPL_H 34 #define _SYS_EFX_IMPL_H 35 36 #include "efsys.h" 37 #include "efx.h" 38 #include "efx_regs.h" 39 #include "efx_regs_ef10.h" 40 41 /* FIXME: Add definition for driver generated software events */ 42 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV 43 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV 44 #endif 45 46 #include "efx_check.h" 47 48 49 #if EFSYS_OPT_FALCON 50 #include "falcon_impl.h" 51 #endif /* EFSYS_OPT_FALCON */ 52 53 #if EFSYS_OPT_SIENA 54 #include "siena_impl.h" 55 #endif /* EFSYS_OPT_SIENA */ 56 57 #if EFSYS_OPT_HUNTINGTON 58 #include "hunt_impl.h" 59 #endif /* EFSYS_OPT_HUNTINGTON */ 60 61 #if EFSYS_OPT_MEDFORD 62 #include "medford_impl.h" 63 #endif /* EFSYS_OPT_MEDFORD */ 64 65 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) 66 #include "ef10_impl.h" 67 #endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */ 68 69 #ifdef __cplusplus 70 extern "C" { 71 #endif 72 73 #define EFX_MOD_MCDI 0x00000001 74 #define EFX_MOD_PROBE 0x00000002 75 #define EFX_MOD_NVRAM 0x00000004 76 #define EFX_MOD_VPD 0x00000008 77 #define EFX_MOD_NIC 0x00000010 78 #define EFX_MOD_INTR 0x00000020 79 #define EFX_MOD_EV 0x00000040 80 #define EFX_MOD_RX 0x00000080 81 #define EFX_MOD_TX 0x00000100 82 #define EFX_MOD_PORT 0x00000200 83 #define EFX_MOD_MON 0x00000400 84 #define EFX_MOD_WOL 0x00000800 85 #define EFX_MOD_FILTER 0x00001000 86 #define EFX_MOD_PKTFILTER 0x00002000 87 #define EFX_MOD_LIC 0x00004000 88 89 #define EFX_RESET_MAC 0x00000001 90 #define EFX_RESET_PHY 0x00000002 91 #define EFX_RESET_RXQ_ERR 0x00000004 92 #define EFX_RESET_TXQ_ERR 0x00000008 93 94 typedef enum efx_mac_type_e { 95 EFX_MAC_INVALID = 0, 96 EFX_MAC_FALCON_GMAC, 97 EFX_MAC_FALCON_XMAC, 98 EFX_MAC_SIENA, 99 EFX_MAC_HUNTINGTON, 100 EFX_MAC_MEDFORD, 101 EFX_MAC_NTYPES 102 } efx_mac_type_t; 103 104 typedef struct efx_ev_ops_s { 105 efx_rc_t (*eevo_init)(efx_nic_t *); 106 void (*eevo_fini)(efx_nic_t *); 107 efx_rc_t (*eevo_qcreate)(efx_nic_t *, unsigned int, 108 efsys_mem_t *, size_t, uint32_t, 109 efx_evq_t *); 110 void (*eevo_qdestroy)(efx_evq_t *); 111 efx_rc_t (*eevo_qprime)(efx_evq_t *, unsigned int); 112 void (*eevo_qpost)(efx_evq_t *, uint16_t); 113 efx_rc_t (*eevo_qmoderate)(efx_evq_t *, unsigned int); 114 #if EFSYS_OPT_QSTATS 115 void (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *); 116 #endif 117 } efx_ev_ops_t; 118 119 typedef struct efx_tx_ops_s { 120 efx_rc_t (*etxo_init)(efx_nic_t *); 121 void (*etxo_fini)(efx_nic_t *); 122 efx_rc_t (*etxo_qcreate)(efx_nic_t *, 123 unsigned int, unsigned int, 124 efsys_mem_t *, size_t, 125 uint32_t, uint16_t, 126 efx_evq_t *, efx_txq_t *, 127 unsigned int *); 128 void (*etxo_qdestroy)(efx_txq_t *); 129 efx_rc_t (*etxo_qpost)(efx_txq_t *, efx_buffer_t *, 130 unsigned int, unsigned int, 131 unsigned int *); 132 void (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int); 133 efx_rc_t (*etxo_qpace)(efx_txq_t *, unsigned int); 134 efx_rc_t (*etxo_qflush)(efx_txq_t *); 135 void (*etxo_qenable)(efx_txq_t *); 136 efx_rc_t (*etxo_qpio_enable)(efx_txq_t *); 137 void (*etxo_qpio_disable)(efx_txq_t *); 138 efx_rc_t (*etxo_qpio_write)(efx_txq_t *,uint8_t *, size_t, 139 size_t); 140 efx_rc_t (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int, 141 unsigned int *); 142 efx_rc_t (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *, 143 unsigned int, unsigned int, 144 unsigned int *); 145 void (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t, 146 size_t, boolean_t, 147 efx_desc_t *); 148 void (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t, 149 uint32_t, uint8_t, 150 efx_desc_t *); 151 void (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t, 152 uint32_t, uint16_t, 153 efx_desc_t *, int); 154 void (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t, 155 efx_desc_t *); 156 #if EFSYS_OPT_QSTATS 157 void (*etxo_qstats_update)(efx_txq_t *, 158 efsys_stat_t *); 159 #endif 160 } efx_tx_ops_t; 161 162 typedef struct efx_rx_ops_s { 163 efx_rc_t (*erxo_init)(efx_nic_t *); 164 void (*erxo_fini)(efx_nic_t *); 165 #if EFSYS_OPT_RX_SCATTER 166 efx_rc_t (*erxo_scatter_enable)(efx_nic_t *, unsigned int); 167 #endif 168 #if EFSYS_OPT_RX_SCALE 169 efx_rc_t (*erxo_scale_mode_set)(efx_nic_t *, efx_rx_hash_alg_t, 170 efx_rx_hash_type_t, boolean_t); 171 efx_rc_t (*erxo_scale_key_set)(efx_nic_t *, uint8_t *, size_t); 172 efx_rc_t (*erxo_scale_tbl_set)(efx_nic_t *, unsigned int *, 173 size_t); 174 uint32_t (*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t, 175 uint8_t *); 176 #endif /* EFSYS_OPT_RX_SCALE */ 177 efx_rc_t (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *, 178 uint16_t *); 179 void (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t, 180 unsigned int, unsigned int, 181 unsigned int); 182 void (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *); 183 efx_rc_t (*erxo_qflush)(efx_rxq_t *); 184 void (*erxo_qenable)(efx_rxq_t *); 185 efx_rc_t (*erxo_qcreate)(efx_nic_t *enp, unsigned int, 186 unsigned int, efx_rxq_type_t, 187 efsys_mem_t *, size_t, uint32_t, 188 efx_evq_t *, efx_rxq_t *); 189 void (*erxo_qdestroy)(efx_rxq_t *); 190 } efx_rx_ops_t; 191 192 typedef struct efx_mac_ops_s { 193 efx_rc_t (*emo_reset)(efx_nic_t *); /* optional */ 194 efx_rc_t (*emo_poll)(efx_nic_t *, efx_link_mode_t *); 195 efx_rc_t (*emo_up)(efx_nic_t *, boolean_t *); 196 efx_rc_t (*emo_addr_set)(efx_nic_t *); 197 efx_rc_t (*emo_pdu_set)(efx_nic_t *); 198 efx_rc_t (*emo_reconfigure)(efx_nic_t *); 199 efx_rc_t (*emo_multicast_list_set)(efx_nic_t *); 200 efx_rc_t (*emo_filter_default_rxq_set)(efx_nic_t *, 201 efx_rxq_t *, boolean_t); 202 void (*emo_filter_default_rxq_clear)(efx_nic_t *); 203 #if EFSYS_OPT_LOOPBACK 204 efx_rc_t (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t, 205 efx_loopback_type_t); 206 #endif /* EFSYS_OPT_LOOPBACK */ 207 #if EFSYS_OPT_MAC_STATS 208 efx_rc_t (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *); 209 efx_rc_t (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *, 210 uint16_t, boolean_t); 211 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *, 212 efsys_stat_t *, uint32_t *); 213 #endif /* EFSYS_OPT_MAC_STATS */ 214 } efx_mac_ops_t; 215 216 typedef struct efx_phy_ops_s { 217 efx_rc_t (*epo_power)(efx_nic_t *, boolean_t); /* optional */ 218 efx_rc_t (*epo_reset)(efx_nic_t *); 219 efx_rc_t (*epo_reconfigure)(efx_nic_t *); 220 efx_rc_t (*epo_verify)(efx_nic_t *); 221 efx_rc_t (*epo_uplink_check)(efx_nic_t *, 222 boolean_t *); /* optional */ 223 efx_rc_t (*epo_downlink_check)(efx_nic_t *, efx_link_mode_t *, 224 unsigned int *, uint32_t *); 225 efx_rc_t (*epo_oui_get)(efx_nic_t *, uint32_t *); 226 #if EFSYS_OPT_PHY_STATS 227 efx_rc_t (*epo_stats_update)(efx_nic_t *, efsys_mem_t *, 228 uint32_t *); 229 #endif /* EFSYS_OPT_PHY_STATS */ 230 #if EFSYS_OPT_PHY_PROPS 231 #if EFSYS_OPT_NAMES 232 const char *(*epo_prop_name)(efx_nic_t *, unsigned int); 233 #endif /* EFSYS_OPT_PHY_PROPS */ 234 efx_rc_t (*epo_prop_get)(efx_nic_t *, unsigned int, uint32_t, 235 uint32_t *); 236 efx_rc_t (*epo_prop_set)(efx_nic_t *, unsigned int, uint32_t); 237 #endif /* EFSYS_OPT_PHY_PROPS */ 238 #if EFSYS_OPT_BIST 239 efx_rc_t (*epo_bist_enable_offline)(efx_nic_t *); 240 efx_rc_t (*epo_bist_start)(efx_nic_t *, efx_bist_type_t); 241 efx_rc_t (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t, 242 efx_bist_result_t *, uint32_t *, 243 unsigned long *, size_t); 244 void (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t); 245 #endif /* EFSYS_OPT_BIST */ 246 } efx_phy_ops_t; 247 248 #if EFSYS_OPT_FILTER 249 typedef struct efx_filter_ops_s { 250 efx_rc_t (*efo_init)(efx_nic_t *); 251 void (*efo_fini)(efx_nic_t *); 252 efx_rc_t (*efo_restore)(efx_nic_t *); 253 efx_rc_t (*efo_add)(efx_nic_t *, efx_filter_spec_t *, 254 boolean_t may_replace); 255 efx_rc_t (*efo_delete)(efx_nic_t *, efx_filter_spec_t *); 256 efx_rc_t (*efo_supported_filters)(efx_nic_t *, uint32_t *, size_t *); 257 efx_rc_t (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t, 258 boolean_t, boolean_t, boolean_t, 259 uint8_t const *, int); 260 } efx_filter_ops_t; 261 262 extern __checkReturn efx_rc_t 263 efx_filter_reconfigure( 264 __in efx_nic_t *enp, 265 __in_ecount(6) uint8_t const *mac_addr, 266 __in boolean_t all_unicst, 267 __in boolean_t mulcst, 268 __in boolean_t all_mulcst, 269 __in boolean_t brdcst, 270 __in_ecount(6*count) uint8_t const *addrs, 271 __in int count); 272 273 #endif /* EFSYS_OPT_FILTER */ 274 275 276 typedef struct efx_port_s { 277 efx_mac_type_t ep_mac_type; 278 uint32_t ep_phy_type; 279 uint8_t ep_port; 280 uint32_t ep_mac_pdu; 281 uint8_t ep_mac_addr[6]; 282 efx_link_mode_t ep_link_mode; 283 boolean_t ep_all_unicst; 284 boolean_t ep_mulcst; 285 boolean_t ep_all_mulcst; 286 boolean_t ep_brdcst; 287 unsigned int ep_fcntl; 288 boolean_t ep_fcntl_autoneg; 289 efx_oword_t ep_multicst_hash[2]; 290 uint8_t ep_mulcst_addr_list[EFX_MAC_ADDR_LEN * 291 EFX_MAC_MULTICAST_LIST_MAX]; 292 uint32_t ep_mulcst_addr_count; 293 #if EFSYS_OPT_LOOPBACK 294 efx_loopback_type_t ep_loopback_type; 295 efx_link_mode_t ep_loopback_link_mode; 296 #endif /* EFSYS_OPT_LOOPBACK */ 297 #if EFSYS_OPT_PHY_FLAGS 298 uint32_t ep_phy_flags; 299 #endif /* EFSYS_OPT_PHY_FLAGS */ 300 #if EFSYS_OPT_PHY_LED_CONTROL 301 efx_phy_led_mode_t ep_phy_led_mode; 302 #endif /* EFSYS_OPT_PHY_LED_CONTROL */ 303 efx_phy_media_type_t ep_fixed_port_type; 304 efx_phy_media_type_t ep_module_type; 305 uint32_t ep_adv_cap_mask; 306 uint32_t ep_lp_cap_mask; 307 uint32_t ep_default_adv_cap_mask; 308 uint32_t ep_phy_cap_mask; 309 #if EFSYS_OPT_PHY_TXC43128 || EFSYS_OPT_PHY_QT2025C 310 union { 311 struct { 312 unsigned int bug10934_count; 313 } ep_txc43128; 314 struct { 315 unsigned int bug17190_count; 316 } ep_qt2025c; 317 }; 318 #endif 319 boolean_t ep_mac_poll_needed; /* falcon only */ 320 boolean_t ep_mac_up; /* falcon only */ 321 uint32_t ep_fwver; /* falcon only */ 322 boolean_t ep_mac_drain; 323 boolean_t ep_mac_stats_pending; 324 #if EFSYS_OPT_BIST 325 efx_bist_type_t ep_current_bist; 326 #endif 327 efx_mac_ops_t *ep_emop; 328 efx_phy_ops_t *ep_epop; 329 } efx_port_t; 330 331 typedef struct efx_mon_ops_s { 332 efx_rc_t (*emo_reset)(efx_nic_t *); 333 efx_rc_t (*emo_reconfigure)(efx_nic_t *); 334 #if EFSYS_OPT_MON_STATS 335 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *, 336 efx_mon_stat_value_t *); 337 #endif /* EFSYS_OPT_MON_STATS */ 338 } efx_mon_ops_t; 339 340 typedef struct efx_mon_s { 341 efx_mon_type_t em_type; 342 efx_mon_ops_t *em_emop; 343 } efx_mon_t; 344 345 typedef struct efx_intr_ops_s { 346 efx_rc_t (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *); 347 void (*eio_enable)(efx_nic_t *); 348 void (*eio_disable)(efx_nic_t *); 349 void (*eio_disable_unlocked)(efx_nic_t *); 350 efx_rc_t (*eio_trigger)(efx_nic_t *, unsigned int); 351 void (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *); 352 void (*eio_status_message)(efx_nic_t *, unsigned int, 353 boolean_t *); 354 void (*eio_fatal)(efx_nic_t *); 355 void (*eio_fini)(efx_nic_t *); 356 } efx_intr_ops_t; 357 358 typedef struct efx_intr_s { 359 efx_intr_ops_t *ei_eiop; 360 efsys_mem_t *ei_esmp; 361 efx_intr_type_t ei_type; 362 unsigned int ei_level; 363 } efx_intr_t; 364 365 typedef struct efx_nic_ops_s { 366 efx_rc_t (*eno_probe)(efx_nic_t *); 367 efx_rc_t (*eno_board_cfg)(efx_nic_t *); 368 efx_rc_t (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*); 369 efx_rc_t (*eno_reset)(efx_nic_t *); 370 efx_rc_t (*eno_init)(efx_nic_t *); 371 efx_rc_t (*eno_get_vi_pool)(efx_nic_t *, uint32_t *); 372 efx_rc_t (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t, 373 uint32_t *, size_t *); 374 #if EFSYS_OPT_DIAG 375 efx_rc_t (*eno_sram_test)(efx_nic_t *, efx_sram_pattern_fn_t); 376 efx_rc_t (*eno_register_test)(efx_nic_t *); 377 #endif /* EFSYS_OPT_DIAG */ 378 void (*eno_fini)(efx_nic_t *); 379 void (*eno_unprobe)(efx_nic_t *); 380 } efx_nic_ops_t; 381 382 #ifndef EFX_TXQ_LIMIT_TARGET 383 #define EFX_TXQ_LIMIT_TARGET 259 384 #endif 385 #ifndef EFX_RXQ_LIMIT_TARGET 386 #define EFX_RXQ_LIMIT_TARGET 512 387 #endif 388 #ifndef EFX_TXQ_DC_SIZE 389 #define EFX_TXQ_DC_SIZE 1 /* 16 descriptors */ 390 #endif 391 #ifndef EFX_RXQ_DC_SIZE 392 #define EFX_RXQ_DC_SIZE 3 /* 64 descriptors */ 393 #endif 394 395 #if EFSYS_OPT_FILTER 396 397 typedef struct falconsiena_filter_spec_s { 398 uint8_t fsfs_type; 399 uint32_t fsfs_flags; 400 uint32_t fsfs_dmaq_id; 401 uint32_t fsfs_dword[3]; 402 } falconsiena_filter_spec_t; 403 404 typedef enum falconsiena_filter_type_e { 405 EFX_FS_FILTER_RX_TCP_FULL, /* TCP/IPv4 4-tuple {dIP,dTCP,sIP,sTCP} */ 406 EFX_FS_FILTER_RX_TCP_WILD, /* TCP/IPv4 dest {dIP,dTCP, -, -} */ 407 EFX_FS_FILTER_RX_UDP_FULL, /* UDP/IPv4 4-tuple {dIP,dUDP,sIP,sUDP} */ 408 EFX_FS_FILTER_RX_UDP_WILD, /* UDP/IPv4 dest {dIP,dUDP, -, -} */ 409 410 #if EFSYS_OPT_SIENA 411 EFX_FS_FILTER_RX_MAC_FULL, /* Ethernet {dMAC,VLAN} */ 412 EFX_FS_FILTER_RX_MAC_WILD, /* Ethernet {dMAC, -} */ 413 414 EFX_FS_FILTER_TX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */ 415 EFX_FS_FILTER_TX_TCP_WILD, /* TCP/IPv4 { -, -,sIP,sTCP} */ 416 EFX_FS_FILTER_TX_UDP_FULL, /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */ 417 EFX_FS_FILTER_TX_UDP_WILD, /* UDP/IPv4 source (host, port) */ 418 419 EFX_FS_FILTER_TX_MAC_FULL, /* Ethernet source (MAC address, VLAN ID) */ 420 EFX_FS_FILTER_TX_MAC_WILD, /* Ethernet source (MAC address) */ 421 #endif /* EFSYS_OPT_SIENA */ 422 423 EFX_FS_FILTER_NTYPES 424 } falconsiena_filter_type_t; 425 426 typedef enum falconsiena_filter_tbl_id_e { 427 EFX_FS_FILTER_TBL_RX_IP = 0, 428 EFX_FS_FILTER_TBL_RX_MAC, 429 EFX_FS_FILTER_TBL_TX_IP, 430 EFX_FS_FILTER_TBL_TX_MAC, 431 EFX_FS_FILTER_NTBLS 432 } falconsiena_filter_tbl_id_t; 433 434 typedef struct falconsiena_filter_tbl_s { 435 int fsft_size; /* number of entries */ 436 int fsft_used; /* active count */ 437 uint32_t *fsft_bitmap; /* active bitmap */ 438 falconsiena_filter_spec_t *fsft_spec; /* array of saved specs */ 439 } falconsiena_filter_tbl_t; 440 441 typedef struct falconsiena_filter_s { 442 falconsiena_filter_tbl_t fsf_tbl[EFX_FS_FILTER_NTBLS]; 443 unsigned int fsf_depth[EFX_FS_FILTER_NTYPES]; 444 } falconsiena_filter_t; 445 446 typedef struct efx_filter_s { 447 #if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA 448 falconsiena_filter_t *ef_falconsiena_filter; 449 #endif /* EFSYS_OPT_FALCON || EFSYS_OPT_SIENA */ 450 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD 451 ef10_filter_table_t *ef_ef10_filter_table; 452 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */ 453 } efx_filter_t; 454 455 extern void 456 falconsiena_filter_tbl_clear( 457 __in efx_nic_t *enp, 458 __in falconsiena_filter_tbl_id_t tbl); 459 460 #endif /* EFSYS_OPT_FILTER */ 461 462 #if EFSYS_OPT_MCDI 463 464 typedef struct efx_mcdi_ops_s { 465 efx_rc_t (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *); 466 void (*emco_send_request)(efx_nic_t *, void *, size_t, 467 void *, size_t); 468 efx_rc_t (*emco_poll_reboot)(efx_nic_t *); 469 boolean_t (*emco_poll_response)(efx_nic_t *); 470 void (*emco_read_response)(efx_nic_t *, void *, size_t, size_t); 471 void (*emco_fini)(efx_nic_t *); 472 efx_rc_t (*emco_feature_supported)(efx_nic_t *, efx_mcdi_feature_id_t, boolean_t *); 473 } efx_mcdi_ops_t; 474 475 typedef struct efx_mcdi_s { 476 efx_mcdi_ops_t *em_emcop; 477 const efx_mcdi_transport_t *em_emtp; 478 efx_mcdi_iface_t em_emip; 479 } efx_mcdi_t; 480 481 #endif /* EFSYS_OPT_MCDI */ 482 483 #if EFSYS_OPT_NVRAM 484 typedef struct efx_nvram_ops_s { 485 #if EFSYS_OPT_DIAG 486 efx_rc_t (*envo_test)(efx_nic_t *); 487 #endif /* EFSYS_OPT_DIAG */ 488 efx_rc_t (*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t, 489 uint32_t *); 490 efx_rc_t (*envo_partn_size)(efx_nic_t *, uint32_t, size_t *); 491 efx_rc_t (*envo_partn_rw_start)(efx_nic_t *, uint32_t, size_t *); 492 efx_rc_t (*envo_partn_read)(efx_nic_t *, uint32_t, 493 unsigned int, caddr_t, size_t); 494 efx_rc_t (*envo_partn_erase)(efx_nic_t *, uint32_t, 495 unsigned int, size_t); 496 efx_rc_t (*envo_partn_write)(efx_nic_t *, uint32_t, 497 unsigned int, caddr_t, size_t); 498 void (*envo_partn_rw_finish)(efx_nic_t *, uint32_t); 499 efx_rc_t (*envo_partn_get_version)(efx_nic_t *, uint32_t, 500 uint32_t *, uint16_t *); 501 efx_rc_t (*envo_partn_set_version)(efx_nic_t *, uint32_t, 502 uint16_t *); 503 } efx_nvram_ops_t; 504 #endif /* EFSYS_OPT_NVRAM */ 505 506 #if EFSYS_OPT_VPD 507 typedef struct efx_vpd_ops_s { 508 efx_rc_t (*evpdo_init)(efx_nic_t *); 509 efx_rc_t (*evpdo_size)(efx_nic_t *, size_t *); 510 efx_rc_t (*evpdo_read)(efx_nic_t *, caddr_t, size_t); 511 efx_rc_t (*evpdo_verify)(efx_nic_t *, caddr_t, size_t); 512 efx_rc_t (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t); 513 efx_rc_t (*evpdo_get)(efx_nic_t *, caddr_t, size_t, 514 efx_vpd_value_t *); 515 efx_rc_t (*evpdo_set)(efx_nic_t *, caddr_t, size_t, 516 efx_vpd_value_t *); 517 efx_rc_t (*evpdo_next)(efx_nic_t *, caddr_t, size_t, 518 efx_vpd_value_t *, unsigned int *); 519 efx_rc_t (*evpdo_write)(efx_nic_t *, caddr_t, size_t); 520 void (*evpdo_fini)(efx_nic_t *); 521 } efx_vpd_ops_t; 522 #endif /* EFSYS_OPT_VPD */ 523 524 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM 525 526 __checkReturn efx_rc_t 527 efx_mcdi_nvram_partitions( 528 __in efx_nic_t *enp, 529 __out_bcount(size) caddr_t data, 530 __in size_t size, 531 __out unsigned int *npartnp); 532 533 __checkReturn efx_rc_t 534 efx_mcdi_nvram_metadata( 535 __in efx_nic_t *enp, 536 __in uint32_t partn, 537 __out uint32_t *subtypep, 538 __out_ecount(4) uint16_t version[4], 539 __out_bcount_opt(size) char *descp, 540 __in size_t size); 541 542 __checkReturn efx_rc_t 543 efx_mcdi_nvram_info( 544 __in efx_nic_t *enp, 545 __in uint32_t partn, 546 __out_opt size_t *sizep, 547 __out_opt uint32_t *addressp, 548 __out_opt uint32_t *erase_sizep, 549 __out_opt uint32_t *write_sizep); 550 551 __checkReturn efx_rc_t 552 efx_mcdi_nvram_update_start( 553 __in efx_nic_t *enp, 554 __in uint32_t partn); 555 556 __checkReturn efx_rc_t 557 efx_mcdi_nvram_read( 558 __in efx_nic_t *enp, 559 __in uint32_t partn, 560 __in uint32_t offset, 561 __out_bcount(size) caddr_t data, 562 __in size_t size); 563 564 __checkReturn efx_rc_t 565 efx_mcdi_nvram_erase( 566 __in efx_nic_t *enp, 567 __in uint32_t partn, 568 __in uint32_t offset, 569 __in size_t size); 570 571 __checkReturn efx_rc_t 572 efx_mcdi_nvram_write( 573 __in efx_nic_t *enp, 574 __in uint32_t partn, 575 __in uint32_t offset, 576 __out_bcount(size) caddr_t data, 577 __in size_t size); 578 579 __checkReturn efx_rc_t 580 efx_mcdi_nvram_update_finish( 581 __in efx_nic_t *enp, 582 __in uint32_t partn, 583 __in boolean_t reboot); 584 585 #if EFSYS_OPT_DIAG 586 587 __checkReturn efx_rc_t 588 efx_mcdi_nvram_test( 589 __in efx_nic_t *enp, 590 __in uint32_t partn); 591 592 #endif /* EFSYS_OPT_DIAG */ 593 594 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */ 595 596 #if EFSYS_OPT_LICENSING 597 598 typedef struct efx_lic_ops_s { 599 efx_rc_t (*elo_update_licenses)(efx_nic_t *); 600 efx_rc_t (*elo_get_key_stats)(efx_nic_t *, efx_key_stats_t *); 601 efx_rc_t (*elo_app_state)(efx_nic_t *, uint64_t, boolean_t *); 602 efx_rc_t (*elo_get_id)(efx_nic_t *, size_t, uint32_t *, 603 size_t *, uint8_t *); 604 } efx_lic_ops_t; 605 606 #endif 607 608 typedef struct efx_drv_cfg_s { 609 uint32_t edc_min_vi_count; 610 uint32_t edc_max_vi_count; 611 612 uint32_t edc_max_piobuf_count; 613 uint32_t edc_pio_alloc_size; 614 } efx_drv_cfg_t; 615 616 struct efx_nic_s { 617 uint32_t en_magic; 618 efx_family_t en_family; 619 uint32_t en_features; 620 efsys_identifier_t *en_esip; 621 efsys_lock_t *en_eslp; 622 efsys_bar_t *en_esbp; 623 unsigned int en_mod_flags; 624 unsigned int en_reset_flags; 625 efx_nic_cfg_t en_nic_cfg; 626 efx_drv_cfg_t en_drv_cfg; 627 efx_port_t en_port; 628 efx_mon_t en_mon; 629 efx_intr_t en_intr; 630 uint32_t en_ev_qcount; 631 uint32_t en_rx_qcount; 632 uint32_t en_tx_qcount; 633 efx_nic_ops_t *en_enop; 634 efx_ev_ops_t *en_eevop; 635 efx_tx_ops_t *en_etxop; 636 efx_rx_ops_t *en_erxop; 637 #if EFSYS_OPT_FILTER 638 efx_filter_t en_filter; 639 efx_filter_ops_t *en_efop; 640 #endif /* EFSYS_OPT_FILTER */ 641 #if EFSYS_OPT_MCDI 642 efx_mcdi_t en_mcdi; 643 #endif /* EFSYS_OPT_MCDI */ 644 #if EFSYS_OPT_NVRAM 645 efx_nvram_type_t en_nvram_locked; 646 efx_nvram_ops_t *en_envop; 647 #endif /* EFSYS_OPT_NVRAM */ 648 #if EFSYS_OPT_VPD 649 efx_vpd_ops_t *en_evpdop; 650 #endif /* EFSYS_OPT_VPD */ 651 #if EFSYS_OPT_RX_SCALE 652 efx_rx_hash_support_t en_hash_support; 653 efx_rx_scale_support_t en_rss_support; 654 uint32_t en_rss_context; 655 #endif /* EFSYS_OPT_RX_SCALE */ 656 uint32_t en_vport_id; 657 #if EFSYS_OPT_LICENSING 658 efx_lic_ops_t *en_elop; 659 #endif 660 union { 661 #if EFSYS_OPT_FALCON 662 struct { 663 falcon_spi_dev_t enu_fsd[FALCON_SPI_NTYPES]; 664 falcon_i2c_t enu_fip; 665 boolean_t enu_i2c_locked; 666 #if EFSYS_OPT_FALCON_NIC_CFG_OVERRIDE 667 const uint8_t *enu_forced_cfg; 668 #endif /* EFSYS_OPT_FALCON_NIC_CFG_OVERRIDE */ 669 uint8_t enu_mon_devid; 670 #if EFSYS_OPT_PCIE_TUNE 671 unsigned int enu_nlanes; 672 #endif /* EFSYS_OPT_PCIE_TUNE */ 673 uint16_t enu_board_rev; 674 boolean_t enu_internal_sram; 675 uint8_t enu_sram_num_bank; 676 uint8_t enu_sram_bank_size; 677 } falcon; 678 #endif /* EFSYS_OPT_FALCON */ 679 #if EFSYS_OPT_SIENA 680 struct { 681 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD 682 unsigned int enu_partn_mask; 683 #endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */ 684 #if EFSYS_OPT_VPD 685 caddr_t enu_svpd; 686 size_t enu_svpd_length; 687 #endif /* EFSYS_OPT_VPD */ 688 int enu_unused; 689 } siena; 690 #endif /* EFSYS_OPT_SIENA */ 691 int enu_unused; 692 } en_u; 693 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) 694 union en_arch { 695 struct { 696 int ena_vi_base; 697 int ena_vi_count; 698 int ena_vi_shift; 699 #if EFSYS_OPT_VPD 700 caddr_t ena_svpd; 701 size_t ena_svpd_length; 702 #endif /* EFSYS_OPT_VPD */ 703 efx_piobuf_handle_t ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS]; 704 uint32_t ena_piobuf_count; 705 uint32_t ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS]; 706 uint32_t ena_pio_write_vi_base; 707 /* Memory BAR mapping regions */ 708 uint32_t ena_uc_mem_map_offset; 709 size_t ena_uc_mem_map_size; 710 uint32_t ena_wc_mem_map_offset; 711 size_t ena_wc_mem_map_size; 712 } ef10; 713 } en_arch; 714 #endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */ 715 }; 716 717 718 #define EFX_NIC_MAGIC 0x02121996 719 720 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *, 721 const efx_ev_callbacks_t *, void *); 722 723 typedef struct efx_evq_rxq_state_s { 724 unsigned int eers_rx_read_ptr; 725 unsigned int eers_rx_mask; 726 } efx_evq_rxq_state_t; 727 728 struct efx_evq_s { 729 uint32_t ee_magic; 730 efx_nic_t *ee_enp; 731 unsigned int ee_index; 732 unsigned int ee_mask; 733 efsys_mem_t *ee_esmp; 734 #if EFSYS_OPT_QSTATS 735 uint32_t ee_stat[EV_NQSTATS]; 736 #endif /* EFSYS_OPT_QSTATS */ 737 738 efx_ev_handler_t ee_rx; 739 efx_ev_handler_t ee_tx; 740 efx_ev_handler_t ee_driver; 741 efx_ev_handler_t ee_global; 742 efx_ev_handler_t ee_drv_gen; 743 #if EFSYS_OPT_MCDI 744 efx_ev_handler_t ee_mcdi; 745 #endif /* EFSYS_OPT_MCDI */ 746 747 efx_evq_rxq_state_t ee_rxq_state[EFX_EV_RX_NLABELS]; 748 }; 749 750 #define EFX_EVQ_MAGIC 0x08081997 751 752 #define EFX_EVQ_FALCON_TIMER_QUANTUM_NS 4968 /* 621 cycles */ 753 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS 6144 /* 768 cycles */ 754 755 struct efx_rxq_s { 756 uint32_t er_magic; 757 efx_nic_t *er_enp; 758 efx_evq_t *er_eep; 759 unsigned int er_index; 760 unsigned int er_label; 761 unsigned int er_mask; 762 efsys_mem_t *er_esmp; 763 }; 764 765 #define EFX_RXQ_MAGIC 0x15022005 766 767 struct efx_txq_s { 768 uint32_t et_magic; 769 efx_nic_t *et_enp; 770 unsigned int et_index; 771 unsigned int et_mask; 772 efsys_mem_t *et_esmp; 773 #if EFSYS_OPT_HUNTINGTON 774 uint32_t et_pio_bufnum; 775 uint32_t et_pio_blknum; 776 uint32_t et_pio_write_offset; 777 uint32_t et_pio_offset; 778 size_t et_pio_size; 779 #endif 780 #if EFSYS_OPT_QSTATS 781 uint32_t et_stat[TX_NQSTATS]; 782 #endif /* EFSYS_OPT_QSTATS */ 783 }; 784 785 #define EFX_TXQ_MAGIC 0x05092005 786 787 #define EFX_MAC_ADDR_COPY(_dst, _src) \ 788 do { \ 789 (_dst)[0] = (_src)[0]; \ 790 (_dst)[1] = (_src)[1]; \ 791 (_dst)[2] = (_src)[2]; \ 792 (_dst)[3] = (_src)[3]; \ 793 (_dst)[4] = (_src)[4]; \ 794 (_dst)[5] = (_src)[5]; \ 795 _NOTE(CONSTANTCONDITION) \ 796 } while (B_FALSE) 797 798 #define EFX_MAC_BROADCAST_ADDR_SET(_dst) \ 799 do { \ 800 uint16_t *_d = (uint16_t *)(_dst); \ 801 _d[0] = 0xffff; \ 802 _d[1] = 0xffff; \ 803 _d[2] = 0xffff; \ 804 _NOTE(CONSTANTCONDITION) \ 805 } while (B_FALSE) 806 807 #if EFSYS_OPT_CHECK_REG 808 #define EFX_CHECK_REG(_enp, _reg) \ 809 do { \ 810 const char *name = #_reg; \ 811 char min = name[4]; \ 812 char max = name[5]; \ 813 char rev; \ 814 \ 815 switch ((_enp)->en_family) { \ 816 case EFX_FAMILY_FALCON: \ 817 rev = 'B'; \ 818 break; \ 819 \ 820 case EFX_FAMILY_SIENA: \ 821 rev = 'C'; \ 822 break; \ 823 \ 824 case EFX_FAMILY_HUNTINGTON: \ 825 rev = 'D'; \ 826 break; \ 827 \ 828 case EFX_FAMILY_MEDFORD: \ 829 rev = 'E'; \ 830 break; \ 831 \ 832 default: \ 833 rev = '?'; \ 834 break; \ 835 } \ 836 \ 837 EFSYS_ASSERT3S(rev, >=, min); \ 838 EFSYS_ASSERT3S(rev, <=, max); \ 839 \ 840 _NOTE(CONSTANTCONDITION) \ 841 } while (B_FALSE) 842 #else 843 #define EFX_CHECK_REG(_enp, _reg) do { \ 844 _NOTE(CONSTANTCONDITION) \ 845 } while(B_FALSE) 846 #endif 847 848 #define EFX_BAR_READD(_enp, _reg, _edp, _lock) \ 849 do { \ 850 EFX_CHECK_REG((_enp), (_reg)); \ 851 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST, \ 852 (_edp), (_lock)); \ 853 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg, \ 854 uint32_t, _reg ## _OFST, \ 855 uint32_t, (_edp)->ed_u32[0]); \ 856 _NOTE(CONSTANTCONDITION) \ 857 } while (B_FALSE) 858 859 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock) \ 860 do { \ 861 EFX_CHECK_REG((_enp), (_reg)); \ 862 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg, \ 863 uint32_t, _reg ## _OFST, \ 864 uint32_t, (_edp)->ed_u32[0]); \ 865 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST, \ 866 (_edp), (_lock)); \ 867 _NOTE(CONSTANTCONDITION) \ 868 } while (B_FALSE) 869 870 #define EFX_BAR_READQ(_enp, _reg, _eqp) \ 871 do { \ 872 EFX_CHECK_REG((_enp), (_reg)); \ 873 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST, \ 874 (_eqp)); \ 875 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg, \ 876 uint32_t, _reg ## _OFST, \ 877 uint32_t, (_eqp)->eq_u32[1], \ 878 uint32_t, (_eqp)->eq_u32[0]); \ 879 _NOTE(CONSTANTCONDITION) \ 880 } while (B_FALSE) 881 882 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp) \ 883 do { \ 884 EFX_CHECK_REG((_enp), (_reg)); \ 885 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg, \ 886 uint32_t, _reg ## _OFST, \ 887 uint32_t, (_eqp)->eq_u32[1], \ 888 uint32_t, (_eqp)->eq_u32[0]); \ 889 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST, \ 890 (_eqp)); \ 891 _NOTE(CONSTANTCONDITION) \ 892 } while (B_FALSE) 893 894 #define EFX_BAR_READO(_enp, _reg, _eop) \ 895 do { \ 896 EFX_CHECK_REG((_enp), (_reg)); \ 897 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST, \ 898 (_eop), B_TRUE); \ 899 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg, \ 900 uint32_t, _reg ## _OFST, \ 901 uint32_t, (_eop)->eo_u32[3], \ 902 uint32_t, (_eop)->eo_u32[2], \ 903 uint32_t, (_eop)->eo_u32[1], \ 904 uint32_t, (_eop)->eo_u32[0]); \ 905 _NOTE(CONSTANTCONDITION) \ 906 } while (B_FALSE) 907 908 #define EFX_BAR_WRITEO(_enp, _reg, _eop) \ 909 do { \ 910 EFX_CHECK_REG((_enp), (_reg)); \ 911 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg, \ 912 uint32_t, _reg ## _OFST, \ 913 uint32_t, (_eop)->eo_u32[3], \ 914 uint32_t, (_eop)->eo_u32[2], \ 915 uint32_t, (_eop)->eo_u32[1], \ 916 uint32_t, (_eop)->eo_u32[0]); \ 917 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST, \ 918 (_eop), B_TRUE); \ 919 _NOTE(CONSTANTCONDITION) \ 920 } while (B_FALSE) 921 922 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock) \ 923 do { \ 924 EFX_CHECK_REG((_enp), (_reg)); \ 925 EFSYS_BAR_READD((_enp)->en_esbp, \ 926 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 927 (_edp), (_lock)); \ 928 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg, \ 929 uint32_t, (_index), \ 930 uint32_t, _reg ## _OFST, \ 931 uint32_t, (_edp)->ed_u32[0]); \ 932 _NOTE(CONSTANTCONDITION) \ 933 } while (B_FALSE) 934 935 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock) \ 936 do { \ 937 EFX_CHECK_REG((_enp), (_reg)); \ 938 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \ 939 uint32_t, (_index), \ 940 uint32_t, _reg ## _OFST, \ 941 uint32_t, (_edp)->ed_u32[0]); \ 942 EFSYS_BAR_WRITED((_enp)->en_esbp, \ 943 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 944 (_edp), (_lock)); \ 945 _NOTE(CONSTANTCONDITION) \ 946 } while (B_FALSE) 947 948 #define EFX_BAR_TBL_WRITED2(_enp, _reg, _index, _edp, _lock) \ 949 do { \ 950 EFX_CHECK_REG((_enp), (_reg)); \ 951 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \ 952 uint32_t, (_index), \ 953 uint32_t, _reg ## _OFST, \ 954 uint32_t, (_edp)->ed_u32[0]); \ 955 EFSYS_BAR_WRITED((_enp)->en_esbp, \ 956 (_reg ## _OFST + \ 957 (2 * sizeof (efx_dword_t)) + \ 958 ((_index) * _reg ## _STEP)), \ 959 (_edp), (_lock)); \ 960 _NOTE(CONSTANTCONDITION) \ 961 } while (B_FALSE) 962 963 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock) \ 964 do { \ 965 EFX_CHECK_REG((_enp), (_reg)); \ 966 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \ 967 uint32_t, (_index), \ 968 uint32_t, _reg ## _OFST, \ 969 uint32_t, (_edp)->ed_u32[0]); \ 970 EFSYS_BAR_WRITED((_enp)->en_esbp, \ 971 (_reg ## _OFST + \ 972 (3 * sizeof (efx_dword_t)) + \ 973 ((_index) * _reg ## _STEP)), \ 974 (_edp), (_lock)); \ 975 _NOTE(CONSTANTCONDITION) \ 976 } while (B_FALSE) 977 978 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp) \ 979 do { \ 980 EFX_CHECK_REG((_enp), (_reg)); \ 981 EFSYS_BAR_READQ((_enp)->en_esbp, \ 982 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 983 (_eqp)); \ 984 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg, \ 985 uint32_t, (_index), \ 986 uint32_t, _reg ## _OFST, \ 987 uint32_t, (_eqp)->eq_u32[1], \ 988 uint32_t, (_eqp)->eq_u32[0]); \ 989 _NOTE(CONSTANTCONDITION) \ 990 } while (B_FALSE) 991 992 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp) \ 993 do { \ 994 EFX_CHECK_REG((_enp), (_reg)); \ 995 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg, \ 996 uint32_t, (_index), \ 997 uint32_t, _reg ## _OFST, \ 998 uint32_t, (_eqp)->eq_u32[1], \ 999 uint32_t, (_eqp)->eq_u32[0]); \ 1000 EFSYS_BAR_WRITEQ((_enp)->en_esbp, \ 1001 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1002 (_eqp)); \ 1003 _NOTE(CONSTANTCONDITION) \ 1004 } while (B_FALSE) 1005 1006 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock) \ 1007 do { \ 1008 EFX_CHECK_REG((_enp), (_reg)); \ 1009 EFSYS_BAR_READO((_enp)->en_esbp, \ 1010 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1011 (_eop), (_lock)); \ 1012 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg, \ 1013 uint32_t, (_index), \ 1014 uint32_t, _reg ## _OFST, \ 1015 uint32_t, (_eop)->eo_u32[3], \ 1016 uint32_t, (_eop)->eo_u32[2], \ 1017 uint32_t, (_eop)->eo_u32[1], \ 1018 uint32_t, (_eop)->eo_u32[0]); \ 1019 _NOTE(CONSTANTCONDITION) \ 1020 } while (B_FALSE) 1021 1022 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock) \ 1023 do { \ 1024 EFX_CHECK_REG((_enp), (_reg)); \ 1025 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg, \ 1026 uint32_t, (_index), \ 1027 uint32_t, _reg ## _OFST, \ 1028 uint32_t, (_eop)->eo_u32[3], \ 1029 uint32_t, (_eop)->eo_u32[2], \ 1030 uint32_t, (_eop)->eo_u32[1], \ 1031 uint32_t, (_eop)->eo_u32[0]); \ 1032 EFSYS_BAR_WRITEO((_enp)->en_esbp, \ 1033 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1034 (_eop), (_lock)); \ 1035 _NOTE(CONSTANTCONDITION) \ 1036 } while (B_FALSE) 1037 1038 /* 1039 * Allow drivers to perform optimised 128-bit doorbell writes. 1040 * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are 1041 * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid 1042 * the need for locking in the host, and are the only ones known to be safe to 1043 * use 128-bites write with. 1044 */ 1045 #define EFX_BAR_TBL_DOORBELL_WRITEO(_enp, _reg, _index, _eop) \ 1046 do { \ 1047 EFX_CHECK_REG((_enp), (_reg)); \ 1048 EFSYS_PROBE7(efx_bar_tbl_doorbell_writeo, \ 1049 const char *, \ 1050 #_reg, \ 1051 uint32_t, (_index), \ 1052 uint32_t, _reg ## _OFST, \ 1053 uint32_t, (_eop)->eo_u32[3], \ 1054 uint32_t, (_eop)->eo_u32[2], \ 1055 uint32_t, (_eop)->eo_u32[1], \ 1056 uint32_t, (_eop)->eo_u32[0]); \ 1057 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp, \ 1058 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1059 (_eop)); \ 1060 _NOTE(CONSTANTCONDITION) \ 1061 } while (B_FALSE) 1062 1063 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr) \ 1064 do { \ 1065 unsigned int _new = (_wptr); \ 1066 unsigned int _old = (_owptr); \ 1067 \ 1068 if ((_new) >= (_old)) \ 1069 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \ 1070 (_old) * sizeof (efx_desc_t), \ 1071 ((_new) - (_old)) * sizeof (efx_desc_t)); \ 1072 else \ 1073 /* \ 1074 * It is cheaper to sync entire map than sync \ 1075 * two parts especially when offset/size are \ 1076 * ignored and entire map is synced in any case.\ 1077 */ \ 1078 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \ 1079 0, \ 1080 (_entries) * sizeof (efx_desc_t)); \ 1081 _NOTE(CONSTANTCONDITION) \ 1082 } while (B_FALSE) 1083 1084 extern __checkReturn efx_rc_t 1085 efx_nic_biu_test( 1086 __in efx_nic_t *enp); 1087 1088 extern __checkReturn efx_rc_t 1089 efx_mac_select( 1090 __in efx_nic_t *enp); 1091 1092 extern void 1093 efx_mac_multicast_hash_compute( 1094 __in_ecount(6*count) uint8_t const *addrs, 1095 __in int count, 1096 __out efx_oword_t *hash_low, 1097 __out efx_oword_t *hash_high); 1098 1099 extern __checkReturn efx_rc_t 1100 efx_phy_probe( 1101 __in efx_nic_t *enp); 1102 1103 extern void 1104 efx_phy_unprobe( 1105 __in efx_nic_t *enp); 1106 1107 #if EFSYS_OPT_VPD 1108 1109 /* VPD utility functions */ 1110 1111 extern __checkReturn efx_rc_t 1112 efx_vpd_hunk_length( 1113 __in_bcount(size) caddr_t data, 1114 __in size_t size, 1115 __out size_t *lengthp); 1116 1117 extern __checkReturn efx_rc_t 1118 efx_vpd_hunk_verify( 1119 __in_bcount(size) caddr_t data, 1120 __in size_t size, 1121 __out_opt boolean_t *cksummedp); 1122 1123 extern __checkReturn efx_rc_t 1124 efx_vpd_hunk_reinit( 1125 __in_bcount(size) caddr_t data, 1126 __in size_t size, 1127 __in boolean_t wantpid); 1128 1129 extern __checkReturn efx_rc_t 1130 efx_vpd_hunk_get( 1131 __in_bcount(size) caddr_t data, 1132 __in size_t size, 1133 __in efx_vpd_tag_t tag, 1134 __in efx_vpd_keyword_t keyword, 1135 __out unsigned int *payloadp, 1136 __out uint8_t *paylenp); 1137 1138 extern __checkReturn efx_rc_t 1139 efx_vpd_hunk_next( 1140 __in_bcount(size) caddr_t data, 1141 __in size_t size, 1142 __out efx_vpd_tag_t *tagp, 1143 __out efx_vpd_keyword_t *keyword, 1144 __out_opt unsigned int *payloadp, 1145 __out_opt uint8_t *paylenp, 1146 __inout unsigned int *contp); 1147 1148 extern __checkReturn efx_rc_t 1149 efx_vpd_hunk_set( 1150 __in_bcount(size) caddr_t data, 1151 __in size_t size, 1152 __in efx_vpd_value_t *evvp); 1153 1154 #endif /* EFSYS_OPT_VPD */ 1155 1156 #if EFSYS_OPT_DIAG 1157 1158 extern efx_sram_pattern_fn_t __efx_sram_pattern_fns[]; 1159 1160 typedef struct efx_register_set_s { 1161 unsigned int address; 1162 unsigned int step; 1163 unsigned int rows; 1164 efx_oword_t mask; 1165 } efx_register_set_t; 1166 1167 extern __checkReturn efx_rc_t 1168 efx_nic_test_registers( 1169 __in efx_nic_t *enp, 1170 __in efx_register_set_t *rsp, 1171 __in size_t count); 1172 1173 extern __checkReturn efx_rc_t 1174 efx_nic_test_tables( 1175 __in efx_nic_t *enp, 1176 __in efx_register_set_t *rsp, 1177 __in efx_pattern_type_t pattern, 1178 __in size_t count); 1179 1180 #endif /* EFSYS_OPT_DIAG */ 1181 1182 #if EFSYS_OPT_MCDI 1183 1184 extern __checkReturn efx_rc_t 1185 efx_mcdi_set_workaround( 1186 __in efx_nic_t *enp, 1187 __in uint32_t type, 1188 __in boolean_t enabled, 1189 __out_opt uint32_t *flagsp); 1190 1191 extern __checkReturn efx_rc_t 1192 efx_mcdi_get_workarounds( 1193 __in efx_nic_t *enp, 1194 __out_opt uint32_t *implementedp, 1195 __out_opt uint32_t *enabledp); 1196 1197 #endif /* EFSYS_OPT_MCDI */ 1198 1199 #ifdef __cplusplus 1200 } 1201 #endif 1202 1203 #endif /* _SYS_EFX_IMPL_H */ 1204